-20170429 4.7.1
+20170501 4.7.1
- Fix scsi2sd-util size and sector-size inputs
- Fix crash when configured scsi disk starting sector is less than
SD card size
+ - Update to PSoC Creator 4.0
20170312 4.7
- Fix bug in SCSI Inquiry command for SCSI2 hosts
-/*******************************************************************************\r
-* File Name: Bootloadable_1.c\r
-* Version 1.30\r
+/****************************************************************************//**\r
+* \file Bootloadable_1.c\r
+* \version 1.50\r
*\r
-* Description:\r
-* Provides an API for the Bootloadable application. The API includes a\r
-* single function for starting the bootloader.\r
+* \brief\r
+* Provides an API for the Bootloadable application.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#include "Bootloadable_1.h"\r
\r
+/**\r
+ \defgroup functions_group Functions\r
+ @{\r
+*/\r
+\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
+static cystatus Bootloadable_1_WriteFlashByte(const uint32 address, const uint8 inputValue) CYLARGE \\r
+ ;\r
+#endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/\r
\r
/*******************************************************************************\r
* Function Name: Bootloadable_1_Load\r
-********************************************************************************\r
-* Summary:\r
-* Begins the bootloading algorithm downloading a new ACD image from the host.\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None\r
+* \brief\r
+* Schedules the Bootloader/Launcher to be launched and then performs\r
+* a software reset to launch it\r
*\r
-* Returns:\r
+* \return\r
* This method will never return. It will load a new application and reset\r
* the device.\r
*\r
void Bootloadable_1_Load(void) \r
{\r
/* Schedule Bootloader to start after reset */\r
- Bootloadable_1_SET_RUN_TYPE(Bootloadable_1_START_BTLDR);\r
+ Bootloadable_1_SET_RUN_TYPE(Bootloadable_1_SCHEDULE_BTLDR);\r
\r
CySoftwareReset();\r
}\r
\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
+/*******************************************************************************\r
+* Function Name: Bootloadable_1_GetActiveApplication\r
+****************************************************************************//**\r
+*\r
+* \brief\r
+* Gets the application which will be loaded after a next reset event.\r
+* NOTE Intended for the combination project type ONLY!\r
+*\r
+* \return \r
+* A number of the current active application set in the metadata section.\r
+* \n 0 - app#0 is set as active.\r
+* \n 1 - app#1 is set as active.\r
+*\r
+* \note If neither of the applications is set active, then the API returns 0x02.\r
+*\r
+*******************************************************************************/\r
+uint8 Bootloadable_1_GetActiveApplication(void) CYSMALL \\r
+ \r
+{ \r
+ uint8 result = Bootloadable_1_MD_BTLDB_ACTIVE_NONE;\r
+ \r
+ if (0u != Bootloadable_1_GET_CODE_DATA( \\r
+ Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(Bootloadable_1_MD_BTLDB_ACTIVE_0))) \r
+ {\r
+ result = Bootloadable_1_MD_BTLDB_ACTIVE_0;\r
+ }\r
+ else if (0u != Bootloadable_1_GET_CODE_DATA( \\r
+ Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(Bootloadable_1_MD_BTLDB_ACTIVE_1)))\r
+ {\r
+ result = Bootloadable_1_MD_BTLDB_ACTIVE_1; \r
+ }\r
+ else\r
+ {\r
+ /*Do nothing, result is none*/\r
+ }\r
+ \r
+ return (result);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name: Bootloadable_1_SetActiveApplication\r
+****************************************************************************//**\r
+*\r
+* \brief \r
+* Sets the application which will be loaded after a next reset event. \r
+* \r
+* \details\r
+* Theory: \r
+* This API sets in the Flash (metadata section) the given active application \r
+* number.\r
+* \r
+* NOTE The active application number is not set directly, but the boolean \r
+* mark instead means that the application is active or not for the relative \r
+* metadata. Both metadata sections are updated. For example, if the second \r
+* application is to be set active, then in the metadata section for the first \r
+* application there will be a "0" written, which means that it is not active, and \r
+* for the second metadata section there will be a "1" written, which means that it is \r
+* active. \r
+*\r
+* NOTE Intended for the combination project type ONLY!\r
+*\r
+* \param appId \r
+* The active application number to be written to flash (metadata section) \r
+* NOTE Possible values are:\r
+* 0 - for the first application\r
+* 1 - for the second application.\r
+* Any other number is considered invalid. \r
+*\r
+* \return \r
+* A status of writing to flash operation.\r
+* \n CYRET_SUCCESS - Returned if appId was successfully changed. \r
+* \n CYRET_BAD_PARAM - Returned if the parameter appID passed to the function has the \r
+* same value as the active application ID. \r
+* \note - The other non-zero value is considered as a failure during writing to flash. \r
+*\r
+* \note - This API does not update Bootloader_activeApp variable.\r
+*\r
+*******************************************************************************/\r
+cystatus Bootloadable_1_SetActiveApplication(uint8 appId) CYSMALL \\r
+ \r
+{\r
+ cystatus result = CYRET_SUCCESS;\r
+\r
+ uint8 CYDATA idx;\r
+ \r
+ /* If invalid application number */\r
+ if (appId > Bootloadable_1_MD_BTLDB_ACTIVE_1)\r
+ {\r
+ result = CYRET_BAD_PARAM;\r
+ }\r
+ else\r
+ {\r
+ /* If appID has same value as active application ID */\r
+ if (1u == Bootloadable_1_GET_CODE_DATA(Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(appId)))\r
+ {\r
+ result = CYRET_BAD_PARAM;\r
+ }\r
+ else\r
+ {\r
+ /* Updating metadata section */\r
+ for(idx = 0u; idx < Bootloadable_1_MAX_NUM_OF_BTLDB; idx++)\r
+ {\r
+ result |= Bootloadable_1_WriteFlashByte((uint32) Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(idx), \\r
+ (uint8)(idx == appId));\r
+ }\r
+ }\r
+ }\r
+ \r
+ return (result);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name: Bootloadable_1_WriteFlashByte\r
+****************************************************************************//**\r
+*\r
+* \brief \r
+* This API writes to flash the specified data.\r
+*\r
+* \param address \r
+* The address in flash.\r
+*\r
+* \param inputValue \r
+* One-byte data.\r
+*\r
+* \return \r
+* A status of the writing to flash procedure.\r
+*\r
+*******************************************************************************/\r
+static cystatus Bootloadable_1_WriteFlashByte(const uint32 address, const uint8 inputValue) CYLARGE \\r
+ \r
+{\r
+ cystatus result = CYRET_SUCCESS;\r
+ uint32 flsAddr = address - CYDEV_FLASH_BASE;\r
+ uint8 rowData[CYDEV_FLS_ROW_SIZE];\r
+\r
+ #if !(CY_PSOC4)\r
+ uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE);\r
+ #endif /* !(CY_PSOC4) */\r
+\r
+ #if (CY_PSOC4)\r
+ uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE);\r
+ #else\r
+ uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);\r
+ #endif /* (CY_PSOC4) */\r
+\r
+ uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE);\r
+ uint16 idx;\r
+\r
+ for(idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++)\r
+ {\r
+ rowData[idx] = (uint8)Bootloadable_1_GET_CODE_DATA(baseAddr + idx);\r
+ }\r
+\r
+ rowData[address % CYDEV_FLS_ROW_SIZE] = inputValue;\r
+\r
+ #if(CY_PSOC4)\r
+ result = CySysFlashWriteRow((uint32) rowNum, rowData);\r
+ #else\r
+ result = CyWriteRowData(arrayId, rowNum, rowData);\r
+ #endif /* (CY_PSOC4) */\r
+\r
+ #if(CY_PSOC5)\r
+ /***************************************************************************\r
+ * When writing to flash, data in the instruction cache can become stale.\r
+ * Therefore, the cache data does not correlate to the data just written to\r
+ * flash. A call to CyFlushCache() is required to invalidate the data in the\r
+ * cache and force fresh information to be loaded from flash.\r
+ ***************************************************************************/\r
+ CyFlushCache();\r
+ #endif /* (CY_PSOC5) */\r
+ return (result);\r
+}\r
+#endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/\r
+/** @} functions_group */\r
\r
/*******************************************************************************\r
* The following code is OBSOLETE and must not be used.\r
\r
#if(CY_PSOC5)\r
/***************************************************************************\r
- * When writing Flash, data in the instruction cache can become stale.\r
+ * When writing to flash, data in the instruction cache can become obsolete.\r
* Therefore, the cache data does not correlate to the data just written to\r
- * Flash. A call to CyFlushCache() is required to invalidate the data in the\r
- * cache and force fresh information to be loaded from Flash.\r
+ * flash. A call to CyFlushCache() is required to invalidate the data in the\r
+ * cache and force fresh information to be loaded from flash.\r
***************************************************************************/\r
CyFlushCache();\r
#endif /* (CY_PSOC5) */\r
}\r
\r
-\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: Bootloadable_1.h\r
-* Version 1.30\r
+/****************************************************************************//**\r
+* \file Bootloadable_1.c\r
+* \version 1.50\r
*\r
-* Description:\r
+* \brief\r
* Provides an API for the Bootloadable application. The API includes a\r
-* single function for starting bootloader.\r
+* single function for starting the Bootloader.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
/* Check to see if required defines such as CY_PSOC5LP are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5LP)\r
- #error Component Bootloadable_v1_30 requires cy_boot v3.0 or later\r
+ #error Component Bootloadable_v1_50 requires cy_boot v3.0 or later\r
#endif /* !defined (CY_PSOC5LP) */\r
\r
\r
\r
\r
/*******************************************************************************\r
-* This variable is used by Bootloader/Bootloadable components to schedule what\r
-* application will be started after software reset.\r
+* This variable is used by the Bootloader/Bootloadable components to schedule which\r
+* application will be started after a software reset.\r
*******************************************************************************/\r
#if (CY_PSOC4)\r
#if defined(__ARMCC_VERSION)\r
\r
\r
/*******************************************************************************\r
-* Get the reason of the device reset\r
+* Gets the reason for a device reset\r
*******************************************************************************/\r
#if(CY_PSOC4)\r
#define Bootloadable_1_RES_CAUSE_RESET_SOFT (0x10u)\r
\r
\r
/*******************************************************************************\r
-* Schedule Bootloader/Bootloadable to be run after software reset\r
+* Schedule the Bootloader/Bootloadable to be run after a software reset.\r
*******************************************************************************/\r
#if(CY_PSOC4)\r
#define Bootloadable_1_SET_RUN_TYPE(x) (cyBtldrRunType = (x))\r
\r
\r
/*******************************************************************************\r
-* The following code is OBSOLETE and must not be used starting from version 1.10\r
+* The following code is OBSOLETE and must not be used starting from version 1.10.\r
*******************************************************************************/\r
#define CYBTDLR_SET_RUN_TYPE(x) Bootloadable_1_SET_RUN_TYPE(x)\r
\r
+/*******************************************************************************\r
+* Bootloadable's declarations for in-app bootloading.\r
+*******************************************************************************/\r
+#define Bootloadable_1_MD_BTLDB_ACTIVE_0 (0x00u)\r
+\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
+ #define Bootloadable_1_MAX_NUM_OF_BTLDB (0x02u)\r
+ #define Bootloadable_1_MD_BTLDB_ACTIVE_1 (0x01u)\r
+ #define Bootloadable_1_MD_BTLDB_ACTIVE_NONE (0x02u)\r
+ #define Bootloadable_1_MD_SIZEOF (64u)\r
+ #define Bootloadable_1_MD_BASE_ADDR(appId) (CYDEV_FLASH_BASE + (CYDEV_FLASH_SIZE - ((uint32)(appId) * CYDEV_FLS_ROW_SIZE) - \\r
+ Bootloadable_1_MD_SIZEOF))\r
+ #define Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(appId) (Bootloadable_1_MD_BASE_ADDR(appId) + 16u)\r
+ \r
+#else\r
+ #define Bootloadable_1_MAX_NUM_OF_BTLDB (0x01u)\r
+#endif /* (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/\r
+\r
+/* Mask used to indicate starting application */\r
+#define Bootloadable_1_SCHEDULE_BTLDB (0x80u)\r
+#define Bootloadable_1_SCHEDULE_BTLDR (0x40u)\r
+#define Bootloadable_1_SCHEDULE_MASK (0xC0u)\r
+/*******************************************************************************\r
+* API prototypes\r
+*******************************************************************************/\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) \r
+ uint8 Bootloadable_1_GetActiveApplication(void) CYSMALL \\r
+ ;\r
+ cystatus Bootloadable_1_SetActiveApplication(uint8 appId) CYSMALL \\r
+ ;\r
+#endif /* (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/\r
\r
/*******************************************************************************\r
* The following code is OBSOLETE and must not be used starting from version 1.20\r
#define Bootloadable_1_APP_ADDRESS uint16\r
#define Bootloadable_1_GET_CODE_WORD(idx) (*((uint32 CYCODE *) (idx)))\r
\r
- /* Offset by 2 from 32 bit start because only need 16 bits */\r
+ /* Offset by 2 from 32 bit start because only 16 bits are needed */\r
#define Bootloadable_1_META_APP_ADDR_OFFSET (3u)\r
#define Bootloadable_1_META_APP_BL_LAST_ROW_OFFSET (7u)\r
#define Bootloadable_1_META_APP_BYTE_LEN_OFFSET (11u)\r
#define Bootloadable_1_SetFlashRunType(runType) \\r
Bootloadable_1_SetFlashByte(Bootloadable_1_MD_APP_RUN_ADDR(0), (runType))\r
\r
-\r
/*******************************************************************************\r
* The following code is OBSOLETE and must not be used.\r
*\r
-* If the obsoleted macro definitions intended for use in the application use the\r
+* If the obsoleted macro definitions are intended for the application, use the\r
* following scheme, redefine your own versions of these definitions:\r
* #ifdef <OBSOLETED_DEFINE>\r
* #undef <OBSOLETED_DEFINE>\r
* #define <OBSOLETED_DEFINE> (<New Value>)\r
* #endif\r
*\r
-* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* NOTE Redefine obsoleted macro definitions with caution. They might still be\r
* used in the application and their modification might lead to unexpected\r
* consequences.\r
*******************************************************************************/\r
/*******************************************************************************\r
* File Name: CFG_EEPROM.c\r
-* Version 2.10\r
+* Version 3.0\r
*\r
-* Description:\r
-* Provides the source code to the API for the EEPROM component.\r
+* Description:\r
+* Provides the source code to the API for the EEPROM component.\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#include "CFG_EEPROM.h"\r
\r
\r
-#if (CY_PSOC3 || CY_PSOC5LP)\r
-\r
- /*******************************************************************************\r
- * Function Name: CFG_EEPROM_Enable\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Enable the EEPROM.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- *******************************************************************************/\r
- void CFG_EEPROM_Enable(void) \r
- {\r
- CyEEPROM_Start();\r
- }\r
+/*******************************************************************************\r
+* Function Name: CFG_EEPROM_Enable\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enable the EEPROM block. Also reads the temperature and stores it for\r
+* future writes.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CFG_EEPROM_Enable(void) \r
+{\r
+ /* Read temperature value */\r
+ (void)CySetTemp();\r
\r
+ /* Start EEPROM block */\r
+ CyEEPROM_Start();\r
+}\r
\r
- /*******************************************************************************\r
- * Function Name: CFG_EEPROM_Start\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Starts EEPROM.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- *******************************************************************************/\r
- void CFG_EEPROM_Start(void) \r
- {\r
- /* Enable the EEPROM */\r
- CFG_EEPROM_Enable();\r
- }\r
\r
+/*******************************************************************************\r
+* Function Name: CFG_EEPROM_Start\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Starts EEPROM.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CFG_EEPROM_Start(void) \r
+{\r
+ CFG_EEPROM_Enable();\r
+}\r
\r
- /*******************************************************************************\r
- * Function Name: CFG_EEPROM_Stop\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Stops and powers down EEPROM.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- *******************************************************************************/\r
- void CFG_EEPROM_Stop (void) \r
- {\r
- /* Disable EEPROM */\r
- CyEEPROM_Stop();\r
- }\r
\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+/*******************************************************************************\r
+* Function Name: CFG_EEPROM_Stop\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Stops and powers down EEPROM.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CFG_EEPROM_Stop (void) \r
+{\r
+ /* Stop and power down EEPROM block */\r
+ CyEEPROM_Stop();\r
+}\r
\r
\r
/*******************************************************************************\r
-* Function Name: CFG_EEPROM_EraseSector\r
+* Function Name: CFG_EEPROM_WriteByte\r
********************************************************************************\r
*\r
* Summary:\r
-* Erases a sector of memory. This function blocks until the operation is\r
-* complete.\r
+* Writes a byte of data to the EEPROM. This function blocks until\r
+* the function is complete. For a reliable write procedure to occur you should\r
+* call CFG_EEPROM_UpdateTemperature() function if the temperature of the\r
+* silicon has been changed for more than 10C since the component was started.\r
*\r
* Parameters:\r
-* sectorNumber: Sector number to erase.\r
+* dataByte: The byte of data to write to the EEPROM\r
+* address: The address of data to be written. The maximum address is dependent\r
+* on the EEPROM size.\r
*\r
* Return:\r
* CYRET_SUCCESS, if the operation was successful.\r
-* CYRET_BAD_PARAM, if the parameter sectorNumber out of range.\r
-* CYRET_LOCKED, if the spc is being used.\r
+* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.\r
+* CYRET_LOCKED, if the SPC is being used.\r
* CYRET_UNKNOWN, if there was an SPC error.\r
*\r
*******************************************************************************/\r
-cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) \r
+cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address) \r
{\r
cystatus status;\r
-\r
- /* Start the SPC */\r
+ uint16 rowNumber;\r
+ uint16 byteNumber;\r
+ \r
CySpcStart();\r
\r
- if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS)\r
+ if (address < CY_EEPROM_SIZE)\r
{\r
- /* See if we can get the SPC. */\r
- if(CySpcLock() == CYRET_SUCCESS)\r
+ rowNumber = address/(uint16)CY_EEPROM_SIZEOF_ROW;\r
+ byteNumber = address - (rowNumber * ((uint16)CY_EEPROM_SIZEOF_ROW));\r
+ if(CYRET_SUCCESS == CySpcLock())\r
{\r
- #if(CY_PSOC5A)\r
-\r
+ status = CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, byteNumber, &dataByte, \\r
+ CFG_EEPROM_SPC_BYTE_WRITE_SIZE);\r
+ if (CYRET_STARTED == status)\r
+ {\r
/* Plan for failure */\r
status = CYRET_UNKNOWN;\r
\r
- /* Command to load a row of data */\r
- if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, 0, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)\r
+ while(CY_SPC_BUSY)\r
{\r
- while(CY_SPC_BUSY)\r
- {\r
- /* Wait until SPC becomes idle */\r
- }\r
-\r
- /* SPC is idle now */\r
- if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
- {\r
- status = CYRET_SUCCESS;\r
- }\r
+ /* Wait until SPC becomes idle */\r
}\r
\r
- /* Command to erase a sector */\r
- if(status == CYRET_SUCCESS)\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
{\r
-\r
- #endif /* (CY_PSOC5A) */\r
-\r
- if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ /* Command to erase and program the row. */\r
+ if(CYRET_SUCCESS == status)\r
+ {\r
+ if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],\r
+ dieTemperature[1u]) == CYRET_STARTED)\r
{\r
/* Plan for failure */\r
status = CYRET_UNKNOWN;\r
{\r
status = CYRET_UNKNOWN;\r
}\r
-\r
- #if(CY_PSOC5A)\r
-\r
}\r
else\r
{\r
status = CYRET_UNKNOWN;\r
}\r
+ }\r
+ else\r
+ {\r
+ if (CYRET_BAD_PARAM != status)\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
+ }\r
+ CySpcUnlock();\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+\r
+\r
+ return (status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CFG_EEPROM_ReadByte\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Reads and returns a byte of data from the on-chip EEPROM memory. Although\r
+* the data is present in the CPU memory space, this function provides an\r
+* intuitive user interface, addressing the EEPROM memory as a separate block with\r
+* the first EERPOM byte address equal to 0x0000.\r
+*\r
+* Parameters:\r
+* address: The address of data to be read. The maximum address is limited by the\r
+* size of the EEPROM array on a specific device.\r
+*\r
+* Return:\r
+* Data located at an address.\r
+*\r
+*******************************************************************************/\r
+uint8 CFG_EEPROM_ReadByte(uint16 address) \r
+{\r
+ uint8 retByte;\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ /* Request access to EEPROM for reading.\r
+ This is needed to reserve PHUB for read operation from EEPROM */\r
+ CyEEPROM_ReadReserve();\r
+ \r
+ retByte = *((reg8 *) (CYDEV_EE_BASE + address));\r
+\r
+ /* Release EEPROM array */\r
+ CyEEPROM_ReadRelease();\r
+ \r
+ CyExitCriticalSection(interruptState);\r
+\r
+ return (retByte);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CFG_EEPROM_UpdateTemperature\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Updates and stores the temperature value. This function should be called\r
+* before EEPROM writes if the temperature may have been changed by more than\r
+* 10 degrees Celsius.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* Status of operation, 0 if operation complete, non-zero value if error\r
+* was detected.\r
+*\r
+*******************************************************************************/\r
+uint8 CFG_EEPROM_UpdateTemperature(void) \r
+{\r
+ return ((uint8)CySetTemp());\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CFG_EEPROM_EraseSector\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Erase an EEPROM sector (64 rows). This function blocks until the erase\r
+* operation is complete. Using this API helps to erase the EEPROM sector at\r
+* a time. This is faster than using individual writes but affects a cycle\r
+* recourse of the whole EEPROM row.\r
+*\r
+* Parameters:\r
+* sectorNumber: The sector number to erase.\r
+*\r
+* Return:\r
+* CYRET_SUCCESS, if the operation was successful.\r
+* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.\r
+* CYRET_LOCKED, if the SPC is being used.\r
+* CYRET_UNKNOWN, if there was an SPC error.\r
+*\r
+*******************************************************************************/\r
+cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) \r
+{\r
+ cystatus status;\r
+ \r
+ CySpcStart();\r
+\r
+ if(sectorNumber < (uint8) CFG_EEPROM_SECTORS_NUMBER)\r
+ {\r
+ /* See if we can get SPC. */\r
+ if(CySpcLock() == CYRET_SUCCESS)\r
+ {\r
+ if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)\r
+ {\r
+ /* Plan for failure */\r
+ status = CYRET_UNKNOWN;\r
+\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Wait until SPC becomes idle */\r
+ }\r
\r
- #endif /* (CY_PSOC5A) */\r
+ /* SPC is idle now */\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
\r
- /* Unlock the SPC so someone else can use it. */\r
- CySpcUnlock();\r
+ /* Unlock SPC so that someone else can use it. */\r
+ CySpcUnlock();\r
}\r
else\r
{\r
********************************************************************************\r
*\r
* Summary:\r
-* Writes a row, CYDEV_EEPROM_ROW_SIZE of data to the EEPROM. This is\r
-* a blocking call. It will not return until the function succeeds or fails.\r
+* Writes a row (16 bytes) of data to the EEPROM. This function blocks until\r
+* the write operation is complete. Compared to functions that write one byte,\r
+* this function allows writing a whole row (16 bytes) at a time. For\r
+* a reliable write procedure to occur you should call the\r
+* CFG_EEPROM_UpdateTemperature() function if the temperature of the\r
+* silicon has changed for more than 10C since component was started.\r
*\r
* Parameters:\r
-* rowData: Address of the data to write to the EEPROM.\r
-* rowNumber: EEPROM row number to program.\r
+* rowData: The address of the data to write to the EEPROM.\r
+* rowNumber: The row number to write.\r
*\r
* Return:\r
* CYRET_SUCCESS, if the operation was successful.\r
-* CYRET_BAD_PARAM, if the parameter rowNumber out of range.\r
-* CYRET_LOCKED, if the spc is being used.\r
+* CYRET_BAD_PARAM, if the parameter rowNumber is out of range.\r
+* CYRET_LOCKED, if the SPC is being used.\r
* CYRET_UNKNOWN, if there was an SPC error.\r
*\r
*******************************************************************************/\r
cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) \r
{\r
cystatus status;\r
-\r
- /* Start the SPC */\r
+ \r
CySpcStart();\r
\r
if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)\r
{\r
- /* See if we can get the SPC. */\r
+ /* See if we can get SPC. */\r
if(CySpcLock() == CYRET_SUCCESS)\r
{\r
/* Plan for failure */\r
/* Command to erase and program the row. */\r
if(status == CYRET_SUCCESS)\r
{\r
- if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],\r
- dieTemperature[1]) == CYRET_STARTED)\r
+ if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],\r
+ dieTemperature[1u]) == CYRET_STARTED)\r
{\r
/* Plan for failure */\r
status = CYRET_UNKNOWN;\r
}\r
}\r
\r
- /* Unlock the SPC so someone else can use it. */\r
+ /* Unlock SPC so that someone else can use it. */\r
CySpcUnlock();\r
}\r
else\r
********************************************************************************\r
*\r
* Summary:\r
-* Starts the SPC write function. This function does not block, it returns\r
-* once the command has begun the SPC write function. This function must be used\r
-* in combination with CFG_EEPROM_QueryWrite(). Once this function has\r
-* been called the SPC will be locked until CFG_EEPROM_QueryWrite()\r
-* returns CYRET_SUCCESS.\r
+* Starts a write of a row (16 bytes) of data to the EEPROM.\r
+* This function does not block. The function returns once the SPC has begun\r
+* writing the data. This function must be used in combination with\r
+* CFG_EEPROM_Query(). CFG_EEPROM_Query() must be called\r
+* until it returns a status other than CYRET_STARTED. That indicates that the\r
+* write has completed. Until CFG_EEPROM_Query() detects that\r
+* the write is complete, the SPC is marked as locked to prevent another\r
+* SPC operation from being performed. For a reliable write procedure to occur\r
+* you should call CFG_EEPROM_UpdateTemperature() API if the temperature\r
+* of the silicon has changed for more than 10C since component was started.\r
*\r
* Parameters:\r
-* rowData: Address of buffer containing a row of data to write to the EEPROM.\r
-* rowNumber: EEPROM row number to program.\r
+* rowData: The address of the data to write to the EEPROM.\r
+* rowNumber: The row number to write.\r
*\r
* Return:\r
-* CYRET_STARTED, if the spc command to write was successfuly started.\r
-* CYRET_BAD_PARAM, if the parameter rowNumber out of range.\r
-* CYRET_LOCKED, if the spc is being used.\r
+* CYRET_STARTED, if the SPC command to write was successfully started.\r
+* CYRET_BAD_PARAM, if the parameter rowNumber is out of range.\r
+* CYRET_LOCKED, if the SPC is being used.\r
* CYRET_UNKNOWN, if there was an SPC error.\r
*\r
+* Side effects:\r
+* After calling this API, the device should not be powered down, reset or switched\r
+* to low power modes until EEPROM operation is complete. \r
+* Ignoring this recommendation may lead to data corruption or silicon\r
+* unexpected behavior.\r
+*\r
*******************************************************************************/\r
cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \\r
\r
{\r
cystatus status;\r
+ \r
+ CySpcStart();\r
\r
if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)\r
{\r
- /* See if we can get the SPC. */\r
+ /* See if we can get SPC. */\r
if(CySpcLock() == CYRET_SUCCESS)\r
{\r
/* Plan for failure */\r
/* Command to erase and program the row. */\r
if(status == CYRET_SUCCESS)\r
{\r
- if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],\r
- dieTemperature[1]) == CYRET_STARTED)\r
+ if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],\r
+ dieTemperature[1u]) == CYRET_STARTED)\r
{\r
status = CYRET_STARTED;\r
}\r
\r
\r
/*******************************************************************************\r
-* Function Name: CFG_EEPROM_QueryWrite\r
+* Function Name: CFG_EEPROM_StartErase\r
********************************************************************************\r
*\r
* Summary:\r
-* Checks the state of write to EEPROM. This function must be called until\r
-* the return value is not CYRET_STARTED.\r
+* Starts the EEPROM sector erase. This function does not block.\r
+* The function returns once the SPC has begun writing the data. This function\r
+* must be used in combination with CFG_EEPROM_Query().\r
+* CFG_EEPROM_Query() must be called until it returns a status\r
+* other than CYRET_STARTED. That indicates the erase has been completed.\r
+* Until CFG_EEPROM_Query() detects that the erase is\r
+* complete, the SPC is marked as locked to prevent another SPC operation\r
+* from being performed.\r
+*\r
+* Parameters:\r
+* sectorNumber: The sector number to erase.\r
+*\r
+* Return:\r
+* CYRET_STARTED, if the SPC command to erase was successfully started.\r
+* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range.\r
+* CYRET_LOCKED, if the SPC is being used.\r
+* CYRET_UNKNOWN, if there was an SPC error.\r
+*\r
+* Side effects:\r
+* After calling this API, the device should not be powered down, reset or switched\r
+* to low power modes until EEPROM operation is complete.\r
+* Ignoring this recommendation may lead to data corruption or silicon\r
+* unexpected behavior.\r
+*\r
+*******************************************************************************/\r
+cystatus CFG_EEPROM_StartErase(uint8 sectorNumber) \r
+{\r
+ cystatus status;\r
+ \r
+ CySpcStart();\r
+\r
+ if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS)\r
+ {\r
+ /* See if we can get SPC. */\r
+ if(CySpcLock() == CYRET_SUCCESS)\r
+ {\r
+ /* Plan for failure */\r
+ status = CYRET_UNKNOWN;\r
+\r
+ /* Command to load a row of data */\r
+ if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CFG_EEPROM_Query\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Checks the status of an earlier call to CFG_EEPROM_StartWrite() or\r
+* CFG_EEPROM_StartErase().\r
+* This function must be called until it returns a value other than\r
+* CYRET_STARTED. Once that occurs, the write or erase has been completed and\r
+* the SPC is unlocked.\r
*\r
* Parameters:\r
* None\r
*\r
* Return:\r
-* CYRET_STARTED, if the spc command is still processing.\r
-* CYRET_SUCCESS, if the operation was successful.\r
+* CYRET_STARTED, if the SPC command is still processing.\r
+* CYRET_SUCCESS, if the operation was completed successfully.\r
* CYRET_UNKNOWN, if there was an SPC error.\r
*\r
*******************************************************************************/\r
-cystatus CFG_EEPROM_QueryWrite(void) \r
+cystatus CFG_EEPROM_Query(void) \r
{\r
cystatus status;\r
+ \r
+ CySpcStart();\r
\r
/* Check if SPC is idle */\r
if(CY_SPC_IDLE)\r
status = CYRET_UNKNOWN;\r
}\r
\r
- /* Unlock the SPC so someone else can use it. */\r
+ /* Unlock SPC so that someone else can use it. */\r
CySpcUnlock();\r
}\r
else\r
\r
\r
/*******************************************************************************\r
-* Function Name: CFG_EEPROM_ByteWrite\r
+* Function Name: CFG_EEPROM_ByteWritePos\r
********************************************************************************\r
*\r
* Summary:\r
* Writes a byte of data to the EEPROM. This is a blocking call. It will not\r
-* return until the function succeeds or fails.\r
+* return until the write operation succeeds or fails.\r
*\r
* Parameters:\r
-* dataByte: Byte of data to write to the EEPROM.\r
-* rowNumber: EEPROM row number to program.\r
-* byteNumber: Byte number within the row to program.\r
+* dataByte: The byte of data to write to the EEPROM.\r
+* rowNumber: The EEPROM row number to program.\r
+* byteNumber: The byte number within the row to program.\r
*\r
* Return:\r
* CYRET_SUCCESS, if the operation was successful.\r
-* CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber out of range.\r
-* CYRET_LOCKED, if the spc is being used.\r
+* CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber is out of range.\r
+* CYRET_LOCKED, if the SPC is being used.\r
* CYRET_UNKNOWN, if there was an SPC error.\r
*\r
*******************************************************************************/\r
-cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \\r
+cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \\r
\r
{\r
cystatus status;\r
\r
- /* Start the SPC */\r
+ /* Start SPC */\r
CySpcStart();\r
\r
if((rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) && (byteNumber < (uint8) SIZEOF_EEPROM_ROW))\r
{\r
- /* See if we can get the SPC. */\r
+ /* See if we can get SPC. */\r
if(CySpcLock() == CYRET_SUCCESS)\r
{\r
/* Plan for failure */\r
status = CYRET_UNKNOWN;\r
\r
- /* Command to load a byte of data */\r
+ /* Command to load byte of data */\r
if(CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, (uint16)byteNumber, &dataByte,\\r
CFG_EEPROM_SPC_BYTE_WRITE_SIZE) == CYRET_STARTED)\r
{\r
/* Command to erase and program the row. */\r
if(status == CYRET_SUCCESS)\r
{\r
- if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],\r
- dieTemperature[1]) == CYRET_STARTED)\r
+ if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u],\r
+ dieTemperature[1u]) == CYRET_STARTED)\r
{\r
/* Plan for failure */\r
status = CYRET_UNKNOWN;\r
}\r
}\r
\r
- /* Unlock the SPC so someone else can use it. */\r
+ /* Unlock SPC so that someone else can use it. */\r
CySpcUnlock();\r
}\r
else\r
/*******************************************************************************\r
* File Name: CFG_EEPROM.h\r
-* Version 2.10\r
+* Version 3.0\r
*\r
-* Description:\r
-* Provides the function definitions for the EEPROM APIs.\r
+* Description:\r
+* Provides the function definitions for the EEPROM APIs.\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
#include "CyFlash.h"\r
\r
#if !defined(CY_PSOC5LP)\r
- #error Component EEPROM_v2_10 requires cy_boot v3.0 or later\r
+ #error Component EEPROM_v3_0 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5LP) */\r
\r
\r
* Function Prototypes\r
***************************************/\r
\r
-#if (CY_PSOC3 || CY_PSOC5LP) \r
- void CFG_EEPROM_Enable(void) ;\r
- void CFG_EEPROM_Start(void); \r
- void CFG_EEPROM_Stop(void) ;\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
-\r
+void CFG_EEPROM_Enable(void) ;\r
+void CFG_EEPROM_Start(void) ;\r
+void CFG_EEPROM_Stop (void) ;\r
+cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address) \\r
+ ;\r
+uint8 CFG_EEPROM_ReadByte(uint16 address) ;\r
+uint8 CFG_EEPROM_UpdateTemperature(void) ;\r
cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) ;\r
cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) ;\r
cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \\r
- ;\r
-cystatus CFG_EEPROM_QueryWrite(void) ;\r
-cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \\r
- ;\r
+ ;\r
+cystatus CFG_EEPROM_StartErase(uint8 sectorNumber) ;\r
+cystatus CFG_EEPROM_Query(void) ;\r
+cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \\r
+ ;\r
\r
\r
/****************************************\r
* API Constants\r
****************************************/\r
\r
-#define CFG_EEPROM_EEPROM_SIZE CYDEV_EE_SIZE\r
+#define CFG_EEPROM_EEPROM_SIZE CYDEV_EE_SIZE\r
#define CFG_EEPROM_SPC_BYTE_WRITE_SIZE (0x01u)\r
\r
+#define CFG_EEPROM_SECTORS_NUMBER (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)\r
\r
-/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from EEPROM 2.10\r
-*******************************************************************************/\r
-#define SPC_BYTE_WRITE_SIZE (CFG_EEPROM_SPC_BYTE_WRITE_SIZE)\r
+#define CFG_EEPROM_AHB_REQ_SHIFT (0x00u)\r
+#define CFG_EEPROM_AHB_REQ ((uint8)(0x01u << CFG_EEPROM_AHB_REQ_SHIFT))\r
+#define CFG_EEPROM_AHB_ACK_SHIFT (0x01u)\r
+#define CFG_EEPROM_AHB_ACK_MASK ((uint8)(0x01u << CFG_EEPROM_AHB_ACK_SHIFT))\r
+\r
+\r
+/***************************************\r
+* Registers\r
+***************************************/\r
+#define CFG_EEPROM_SPC_EE_SCR_REG (*(reg8 *) CYREG_SPC_EE_SCR)\r
+#define CFG_EEPROM_SPC_EE_SCR_PTR ( (reg8 *) CYREG_SPC_EE_SCR)\r
+\r
+\r
+\r
+/***************************************\r
+* The following code is DEPRECATED and\r
+* should not be used in new projects.\r
+***************************************/\r
+#define CFG_EEPROM_ByteWrite CFG_EEPROM_ByteWritePos\r
+#define CFG_EEPROM_QueryWrite CFG_EEPROM_Query\r
\r
#endif /* CY_EEPROM_CFG_EEPROM_H */\r
\r
define symbol CY_APPL_NUM = 1;\r
define symbol CY_APPL_MAX = 1;\r
define symbol CY_METADATA_SIZE = 64;\r
+define symbol CY_CHECKSUM_EXCLUDE_SIZE = 0;\r
define symbol CY_EE_IN_BTLDR = 0x00;\r
define symbol CY_EE_SIZE = 2048;\r
include "cybootloader.icf";\r
}\r
\r
define symbol CY_FLASH_SIZE = 131072;\r
-define symbol CY_APPL_ORIGIN = 0; \r
+define symbol CY_APPL_ORIGIN = 0;\r
define symbol CY_FLASH_ROW_SIZE = 256;\r
define symbol CY_ECC_ROW_SIZE = 32;\r
\r
}\r
define block APPL with fixed order {readonly section .romvectors, readonly};\r
\r
-/* The address of Flash row next after Bootloader image */\r
+/* The address of the Flash row next after the Bootloader image */\r
define symbol CY_BTLDR_END = CYDEV_BTLDR_SIZE +\r
((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ?\r
(CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0);\r
"readwrite" : place in RAM_region { readwrite };\r
"HSTACK" : place at end of RAM_region { block HSTACK};\r
\r
-keep { section .cybootloader, \r
- section .cyloadermeta, \r
+keep { section .cybootloader,\r
+ section .cyloadermeta,\r
section .cyloadablemeta,\r
- section .cyconfigecc, \r
- section .cycustnvl, \r
+ section .cyconfigecc,\r
+ section .cy_checksum_exclude,\r
+ section .cycustnvl,\r
section .cywolatch,\r
- section .cyeeprom, \r
+ section .cyeeprom,\r
section .cyflashprotect,\r
section .cymeta };\r
\r
-".cyloadermeta" : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };\r
+".cyloadermeta" : place at address mem : ((CY_APPL_LOADER && !CY_APPL_LOADABLE) ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };\r
if (CY_APPL_LOADABLE)\r
{\r
-".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };\r
+".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };\r
}\r
+\r
+\r
+/*******************************************************************************\r
+* Checksum Exclude Section. See cm0gcc.ld on placement details.\r
+*******************************************************************************/\r
+if (CY_APPL_LOADABLE)\r
+{\r
+ /* Align size to the flash row size */\r
+ define symbol CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED = CY_CHECKSUM_EXCLUDE_SIZE + ((CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE)) : 0);\r
+\r
+ if (CY_CHECKSUM_EXCLUDE_SIZE != 0)\r
+ {\r
+\r
+ /* General case */\r
+ if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2))\r
+ {\r
+ define symbol CY_CHECKSUM_EXCLUDE_START = CY_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED;\r
+ }\r
+ else\r
+ {\r
+ define symbol CY_CHECKSUM_EXCLUDE_START = (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED;\r
+ }\r
+\r
+ define symbol CY_CHECKSUM_EXCLUDE_START_ALIGNED = CY_CHECKSUM_EXCLUDE_START + ((CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE)) : 0);\r
+\r
+ ".cy_checksum_exclude" : place at address mem : (CY_CHECKSUM_EXCLUDE_START_ALIGNED) { readonly section .cy_checksum_exclude };\r
+\r
+ } /* (CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED != 0) */\r
+}\r
+else\r
+{\r
+ ".cy_checksum_exclude" : place in ROM_region { readonly section .cy_checksum_exclude };\r
+}\r
+\r
+\r
".cyconfigecc" : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };\r
".cycustnvl" : place at address mem : 0x90000000 { readonly section .cycustnvl };\r
".cywolatch" : place at address mem : 0x90100000 { readonly section .cywolatch };\r
#! armcc -E\r
-; The first line specifies a preprocessor command that the linker invokes \r
+; The first line specifies a preprocessor command that the linker invokes\r
; to pass a scatter file through a C preprocessor.\r
\r
;********************************************************************************\r
-;* File Name: Cm3RealView.scat\r
-;* Version 4.20\r
+;* \file Cm3RealView.scat\r
+;* \version 5.50\r
;*\r
-;* Description:\r
-;* This Linker Descriptor file describes the memory layout of the PSoC5\r
-;* device. The memory layout of the final binary and hex images as well as\r
-;* the placement in PSoC5 memory is described.\r
-;*\r
-;*\r
-;* Note:\r
+;* \brief\r
+;* This Linker Descriptor file describes the memory layout of the PSoC5\r
+;* device. The memory layout of the final binary and hex images as well as\r
+;* the placement in PSoC5 memory is described.\r
;*\r
;* romvectors: Cypress default Interrupt service routine vector table.\r
-;*\r
;* This is the ISR vector table at bootup. Used only for the reset vector.\r
;*\r
-;*\r
;* ramvectors: Cypress ram interrupt service routine vector table.\r
-;*\r
;* This is the ISR vector table used by the application.\r
;*\r
-;*\r
;********************************************************************************\r
-;* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+;* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
;* You may use this file only in accordance with the license, terms, conditions,\r
;* disclaimers, and limitations in the end user license agreement accompanying\r
;* the software package with which this file was provided.\r
#define CY_EE_SIZE 2048\r
#define CY_METADATA_SIZE 64\r
\r
+#define CY_CHECKSUM_EXCLUDE_SIZE AlignExpr(0, CY_FLASH_ROW_SIZE)\r
+#define CY_APPL_NUM 1\r
+#define CY_APPL_MAX 1\r
+\r
\r
; Define application base address\r
-#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)\r
- #define CY_APPL_NUM 1\r
- #define CY_APPL_MAX 1\r
- #define CY_EE_IN_BTLDR 0\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \\r
+ CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
+\r
+ #define CY_EE_IN_BTLDR 0\r
\r
#if CY_APPL_ORIGIN\r
#define APPL1_START CY_APPL_ORIGIN\r
\r
\r
; Place Bootloader at the beginning of Flash\r
-#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \\r
+ CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
\r
CYBOOTLOADER 0\r
{\r
}\r
\r
#if CY_APPL_ORIGIN\r
- ScatterAssert(APPL_START > LoadLimit(CYBOOTLOADER))\r
+ ScatterAssert(APPL_START >= LoadLimit(CYBOOTLOADER))\r
#endif\r
\r
#endif\r
}\r
\r
\r
-#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER)\r
+/*******************************************************************************\r
+* Bootloader Metadata Section. See cm0gcc.ld on placement details.\r
+*******************************************************************************/\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || \\r
+ CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER || \\r
+ CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LAUNCHER)\r
\r
CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE)\r
{\r
.cyloadermeta +0 { * (.cyloadermeta) }\r
}\r
\r
-#else\r
+#endif\r
+\r
+\r
+/*******************************************************************************\r
+* Bootloadable Metadata Section. See cm0gcc.ld on placement details.\r
+*******************************************************************************/\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \\r
+ CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
\r
- #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)\r
+ CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE)\r
+ {\r
+ .cyloadablemeta +0 { * (.cyloadablemeta) }\r
+ }\r
+\r
+#endif\r
+\r
+\r
+/*******************************************************************************\r
+* Checksum Exclude Section. See cm0gcc.ld on placement details.\r
+*******************************************************************************/\r
+#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) || (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))\r
\r
- CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE)\r
+ #if (0 != 0)\r
+\r
+ #if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2))\r
+ #define CY_CHECKSUM_APPL2_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ), CY_FLASH_ROW_SIZE))\r
+ #define CY_CHECKSUM_EXCLUDE_START AlignExpr(CY_CHECKSUM_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE)\r
+ #else\r
+ #define CY_CHECKSUM_EXCLUDE_START AlignExpr((CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE)\r
+ #endif\r
+\r
+ CY_CHECKSUM_EXCLUDE (CY_CHECKSUM_EXCLUDE_START)\r
{\r
- .cyloadablemeta +0 { * (.cyloadablemeta) }\r
+ .cy_checksum_exclude +0\r
+ {\r
+ * (.cy_checksum_exclude)\r
+ }\r
}\r
- \r
- #endif\r
+\r
+ #endif /* (0 != 0) */\r
\r
#endif\r
\r
+\r
#if (CYDEV_ECC_ENABLE == 0)\r
\r
CYCONFIGECC (0x80000000 + ECC_OFFSET)\r
.cymeta +0 { * (.cymeta) }\r
}\r
\r
-#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)\r
+\r
+/*******************************************************************************\r
+* Bootloader Metadata Section. Must be part of the image, but beyond rom memory.\r
+*******************************************************************************/\r
+#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) || (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))\r
\r
CYLOADERMETA +0\r
{\r
-/*******************************************************************************\r
-* File Name: Cm3Start.c\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file Cm3Start.c\r
+* \version 5.50\r
*\r
-* Description:\r
+* \brief\r
* Startup code for the ARM CM3.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#include "CyDmac.h"\r
#include "cyfitter.h"\r
\r
+\r
#define CY_NUM_INTERRUPTS (32u)\r
#define CY_NUM_VECTORS (CYINT_IRQ_BASE + CY_NUM_INTERRUPTS)\r
#define CY_NUM_ROM_VECTORS (4u)\r
#define CY_NVIC_APINT_VECTKEY (0x05FA0000u) /* This key is required in order to write the NVIC_APINT register */\r
#define CY_NVIC_CFG_STACKALIGN (0x00000200u) /* This specifies that the exception stack must be 8 byte aligned */\r
\r
-\r
-/* Extern functions */\r
-extern void CyBtldr_CheckLaunch(void);\r
-\r
-/* Function prototypes */\r
-void initialize_psoc(void);\r
-CY_ISR(IntDefaultHandler);\r
-void Reset(void);\r
-CY_ISR(IntDefaultHandler);\r
-\r
#if defined(__ARMCC_VERSION)\r
#define INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit)\r
#elif defined (__GNUC__)\r
extern int end;\r
#endif /* defined(__GNUC__) */\r
\r
+/* Extern functions */\r
+extern void CyBtldr_CheckLaunch(void);\r
+\r
+/* Function prototypes */\r
+void initialize_psoc(void);\r
+CY_ISR(IntDefaultHandler);\r
+void Reset(void);\r
+\r
/* Global variables */\r
#if !defined (__ICCARM__)\r
CY_NOINIT static uint32 cySysNoInitDataValid;\r
\r
/*******************************************************************************\r
* Function Name: IntDefaultHandler\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function is called for all interrupts, other than a reset that gets\r
* called before the system is setup.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
* Theory:\r
* Any value other than zero is acceptable.\r
*\r
*******************************************************************************/\r
CY_ISR(IntDefaultHandler)\r
{\r
+ /***************************************************************************\r
+ * We must not get here. If we do, a serious problem occurs, so go into\r
+ * an infinite loop.\r
+ ***************************************************************************/\r
\r
- while(1)\r
- {\r
- /***********************************************************************\r
- * We must not get here. If we do, a serious problem occurs, so go\r
- * into an infinite loop.\r
- ***********************************************************************/\r
- }\r
+ #if defined(__GNUC__)\r
+ if (errno == ENOMEM)\r
+ {\r
+ #ifdef CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK\r
+ CyBoot_IntDefaultHandler_Enomem_Exception_Callback();\r
+ #endif /* CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK */\r
+ \r
+ while(1)\r
+ {\r
+ /* Out Of Heap Space\r
+ * This can be increased in the System tab of the Design Wide Resources.\r
+ */\r
+ }\r
+ }\r
+ else\r
+ #endif\r
+ {\r
+ #ifdef CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK\r
+ CyBoot_IntDefaultHandler_Exception_EntryCallback();\r
+ #endif /* CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK */\r
+\r
+ while(1)\r
+ {\r
+\r
+ }\r
+ }\r
}\r
\r
\r
\r
/*******************************************************************************\r
* Function Name: Reset\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function handles the reset interrupt for the RVDS/MDK toolchains.\r
* This is the first bit of code that is executed at startup.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void Reset(void)\r
{\r
- #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)\r
+ #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
\r
/* For PSoC 5LP, debugging is enabled by default */\r
#if(CYDEV_DEBUGGING_ENABLE == 0)\r
*/\r
*(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);\r
\r
- #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */\r
+ #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */\r
\r
- #if(CYDEV_BOOTLOADER_ENABLE)\r
+ #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))\r
CyBtldr_CheckLaunch();\r
- #endif /* (CYDEV_BOOTLOADER_ENABLE) */\r
+ #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */\r
\r
__main();\r
}\r
\r
/*******************************************************************************\r
* Function Name: $Sub$$main\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function is called immediately before the users main\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void $Sub$$main(void)\r
{\r
\r
/*******************************************************************************\r
* Function Name: _exit\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Exit a program without cleaning up files. If your system doesn't provide\r
* this, it is best to avoid linking with subroutines that require it (exit,\r
* system).\r
*\r
-* Parameters:\r
-* status: Status caused program exit.\r
-*\r
-* Return:\r
-* None\r
+* \param status: Status caused program exit.\r
*\r
*******************************************************************************/\r
__attribute__((weak))\r
void _exit(int status)\r
{\r
- /* Cause divide by 0 exception */\r
- int x = status / (int) INT_MAX;\r
- x = 4 / x;\r
-\r
+ CyHalt((uint8) status);\r
while(1)\r
{\r
\r
\r
/*******************************************************************************\r
* Function Name: _sbrk\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Increase program data space. As malloc and related functions depend on this,\r
* it is useful to have a working implementation. The following suffices for a\r
* standalone system; it exploits the symbol end automatically defined by the\r
* GNU linker.\r
*\r
-* Parameters:\r
-* nbytes: The number of bytes requested (if the parameter value is positive)\r
+* \param nbytes: The number of bytes requested (if the parameter value is positive)\r
* from the heap or returned back to the heap (if the parameter value is\r
* negative).\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
__attribute__((weak))\r
void * _sbrk (int nbytes)\r
\r
/*******************************************************************************\r
* Function Name: Reset\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function handles the reset interrupt for the GCC toolchain. This is the\r
* first bit of code that is executed at startup.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void Reset(void)\r
{\r
- #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)\r
+ #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
\r
/* For PSoC 5LP, debugging is enabled by default */\r
#if(CYDEV_DEBUGGING_ENABLE == 0)\r
*/\r
*(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);\r
\r
- #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */\r
+ #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */\r
\r
- #if(CYDEV_BOOTLOADER_ENABLE)\r
+ #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))\r
CyBtldr_CheckLaunch();\r
- #endif /* (CYDEV_BOOTLOADER_ENABLE) */\r
+ #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */\r
\r
Start_c();\r
}\r
\r
/*******************************************************************************\r
* Function Name: Start_c\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function handles initializing the .data and .bss sections in\r
* preparation for running the standard C code. Once initialization is complete\r
* it will call main(). This function will never return.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void Start_c(void) __attribute__ ((noreturn));\r
void Start_c(void)\r
\r
/*******************************************************************************\r
* Function Name: __low_level_init\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function performs early initializations for the IAR Embedded\r
* Workbench IDE. It is executed in the context of a reset interrupt handler\r
* before the data sections are initialized.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* The value that determines whether or not data sections should be initialized\r
* by the system startup code:\r
* 0 - skip data sections initialization;\r
*******************************************************************************/\r
int __low_level_init(void)\r
{\r
- #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)\r
+ #if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
\r
/* For PSoC 5LP, debugging is enabled by default */\r
#if(CYDEV_DEBUGGING_ENABLE == 0)\r
*/\r
*(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);\r
\r
- #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */\r
+ #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */\r
\r
- #if (CYDEV_BOOTLOADER_ENABLE)\r
+ #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))\r
CyBtldr_CheckLaunch();\r
- #endif /* CYDEV_BOOTLOADER_ENABLE */\r
+ #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */\r
\r
/* Initialize data sections */\r
__iar_data_init3();\r
\r
/*******************************************************************************\r
* Function Name: initialize_psoc\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function used to initialize the PSoC chip before calling main.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
#if (defined(__GNUC__) && !defined(__ARMCC_VERSION))\r
__attribute__ ((constructor(101)))\r
-/*******************************************************************************\r
-* File Name: CyBootAsmGnu.s\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file CyBootAsmGnu.s\r
+* \version 5.50\r
*\r
-* Description:\r
+* \brief\r
* Assembly routines for GNU as.\r
*\r
********************************************************************************\r
-* Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2010-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: CyDelayCycles\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Delays for the specified number of cycles.\r
*\r
-* Parameters:\r
-* uint32 cycles: number of cycles to delay.\r
-*\r
-* Return:\r
-* None\r
+* \param uint32 cycles: number of cycles to delay.\r
*\r
*******************************************************************************/\r
/* void CyDelayCycles(uint32 cycles) */\r
\r
/*******************************************************************************\r
* Function Name: CyEnterCriticalSection\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* CyEnterCriticalSection disables interrupts and returns a value indicating\r
* whether interrupts were previously enabled (the actual value depends on\r
* whether the device is PSoC 3 or PSoC 5).\r
* corrupting processor state, it must be the policy that all interrupt routines\r
* restore the interrupt enable bits as they were found on entry.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* uint8\r
* Returns 0 if interrupts were previously enabled or 1 if interrupts\r
* were previously disabled.\r
\r
/*******************************************************************************\r
* Function Name: CyExitCriticalSection\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* CyExitCriticalSection re-enables interrupts if they were enabled before\r
* CyEnterCriticalSection was called. The argument should be the value returned\r
* from CyEnterCriticalSection.\r
*\r
-* Parameters:\r
-* uint8 savedIntrStatus:\r
+* \param uint8 savedIntrStatus:\r
* Saved interrupt status returned by the CyEnterCriticalSection function.\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
/* void CyExitCriticalSection(uint8 savedIntrStatus) */\r
.global CyExitCriticalSection\r
;-------------------------------------------------------------------------------\r
; FILENAME: CyBootAsmIar.s\r
-; Version 4.20\r
+; Version 5.50\r
;\r
; DESCRIPTION:\r
; Assembly routines for IAR Embedded Workbench IDE.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright 2013-2015, Cypress Semiconductor Corporation. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions,\r
; disclaimers, and limitations in the end user license agreement accompanying\r
; the software package with which this file was provided.\r
;-------------------------------------------------------------------------------\r
; FILENAME: CyBootAsmRv.s\r
-; Version 4.20\r
+; Version 5.50\r
;\r
; DESCRIPTION:\r
; Assembly routines for RealView.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright 2010-2015, Cypress Semiconductor Corporation. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions,\r
; disclaimers, and limitations in the end user license agreement accompanying\r
; the software package with which this file was provided.\r
-/*******************************************************************************\r
-* File Name: CyDmac.c\r
-* Version 4.20\r
-*\r
-* Description:\r
-* Provides an API for the DMAC component. The API includes functions for the\r
-* DMA controller, DMA channels and Transfer Descriptors.\r
+/***************************************************************************//**\r
+* \file CyDmac.c\r
+* \version 5.50\r
*\r
-* This API is the library version not the auto generated code that gets\r
-* generated when the user places a DMA component on the schematic.\r
+* \brief\r
+* Provides an API for the DMAC component. The API includes functions for the\r
+* DMA controller, DMA channels and Transfer Descriptors. This API is the library\r
+* version not the auto generated code that gets generated when the user places a\r
+* DMA component on the schematic.\r
*\r
-* The auto generated code would use the APi's in this module.\r
+* The auto generated code would use the APi's in this module.\r
*\r
-* Note:\r
-* This code is endian agnostic.\r
+* \note This code is endian agnostic.\r
*\r
-* The Transfer Descriptor memory can be used as regular memory if the TD's are\r
-* not being used.\r
+* \note The Transfer Descriptor memory can be used as regular memory if the\r
+* TD's are not being used.\r
*\r
-* This code uses the first byte of each TD to manage the free list of TD's.\r
-* The user can overwrite this once the TD is allocated.\r
+* \note This code uses the first byte of each TD to manage the free list of\r
+* TD's. The user can overwrite this once the TD is allocated.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: CyDmacConfigure\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Creates a linked list of all the TDs to be allocated. This function is called\r
-* by the startup code; you do not normally need to call it. You can call this\r
-* function if all of the DMA channels are inactive.\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
+* Creates a linked list of all the TDs to be allocated. This function is called\r
+* by the startup code; you do not normally need to call it. You can call this\r
+* function if all of the DMA channels are inactive.\r
*\r
*******************************************************************************/\r
void CyDmacConfigure(void) \r
\r
/*******************************************************************************\r
* Function Name: CyDmacError\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Returns errors of the last failed DMA transaction.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* Errors of the last failed DMA transaction.\r
+* \return Errors of the last failed DMA transaction.\r
*\r
* DMAC_PERIPH_ERR:\r
* Set to 1 when a peripheral responds to a bus transaction with an error\r
* are determined by the BUS_TIMEOUT field in the PHUBCFG register.\r
*\r
* Theory:\r
-* Once an error occurs the error bits are sticky and are only cleared by \r
+* Once an error occurs the error bits are sticky and are only cleared by\r
* writing 1 to the error register.\r
*\r
*******************************************************************************/\r
uint8 CyDmacError(void) \r
{\r
- return((uint8)(((uint32) 0x0Fu) & *CY_DMA_ERR_PTR));\r
+ return((uint8)(((uint32) 0x0Eu) & *CY_DMA_ERR_PTR));\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: CyDmacClearError\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Clears the error bits in the error register of the DMAC.\r
*\r
-* Parameters:\r
-* error:\r
+* \param error:\r
* Clears the error bits in the DMAC error register.\r
*\r
-* DMAC_PERIPH_ERR:\r
+* \param DMAC_PERIPH_ERR:\r
* Set to 1 when a peripheral responds to a bus transaction with an error\r
* response.\r
*\r
-* DMAC_UNPOP_ACC:\r
+* \param DMAC_UNPOP_ACC:\r
* Set to 1 when an access is attempted to an invalid address.\r
*\r
-* DMAC_BUS_TIMEOUT:\r
+* \param DMAC_BUS_TIMEOUT:\r
* Set to 1 when a bus timeout occurs. Cleared by writing 1. Timeout values\r
* are determined by the BUS_TIMEOUT field in the PHUBCFG register.\r
*\r
-* Return:\r
-* None\r
-*\r
* Theory:\r
-* Once an error occurs the error bits are sticky and are only cleared by \r
+* Once an error occurs the error bits are sticky and are only cleared by\r
* writing 1 to the error register.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyDmacErrorAddress\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* When DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC, and DMAC_PERIPH_ERR occur the\r
* address of the error is written to the error address register and can be read\r
* with this function.\r
*\r
* If there are multiple errors, only the address of the first is saved.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* The address that caused the error.\r
+* \return The address that caused the error.\r
*\r
*******************************************************************************/\r
uint32 CyDmacErrorAddress(void) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaChAlloc\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Allocates a channel from the DMAC to be used in all functions that require a\r
* channel handle.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* The allocated channel number. Zero is a valid channel number.\r
+* \return The allocated channel number. Zero is a valid channel number.\r
* DMA_INVALID_CHANNEL is returned if there are no channels available.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyDmaChFree\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Frees a channel allocated by DmaChAlloc().\r
+* Frees a channel allocated by \ref DmaChAlloc().\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* The handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+* \param chHandle The handle previously returned by \ref CyDmaChAlloc() or \ref\r
+* DMA_DmaInitalize().\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChFree(uint8 chHandle) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaChEnable\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the DMA channel. A software or hardware request still must happen\r
* before the channel is executed.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref\r
+* DMA_DmaInitalize().\r
*\r
-* uint8 preserveTds:\r
-* Preserves the original TD state when the TD has completed. This parameter\r
-* applies to all TDs in the channel.\r
+* \param preserveTds Preserves the original TD state when the TD has completed.\r
+* This parameter applies to all TDs in the channel.\r
*\r
* 0 - When TD is completed, the DMAC leaves the TD configuration values in\r
* their current state, and does not restore them to their original state.\r
* if you are using CH06 and preserveTds is set, you are not allowed to use TD\r
* slot 6. That is reclaimed by the DMA engine for its private use.\r
*\r
-* Note Do not chain back to a completed TD if the preserveTds for the channel\r
+* \note Do not chain back to a completed TD if the preserveTds for the channel\r
* is set to 0. When a TD has completed preserveTds for the channel set to 0,\r
* the transfer count will be at 0. If a TD with a transfer count of 0 is\r
* started, the TD will transfer an indefinite amount of data.\r
* Take extra precautions when using the hardware request (DRQ) option when the\r
* preserveTds is set to 0, as you might be requesting the wrong data.\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaChDisable\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Disables the DMA channel. Once this function is called, CyDmaChStatus() may\r
-* be called to determine when the channel is disabled and which TDs were being\r
-* executed.\r
+* Disables the DMA channel. Once this function is called, CyDmaChStatus() may\r
+* be called to determine when the channel is disabled and which TDs were being\r
+* executed.\r
*\r
-* If it is currently executing it will allow the current burst to finish\r
-* naturally.\r
+* If it is currently executing it will allow the current burst to finish\r
+* naturally.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref\r
+* DMA_DmaInitalize().\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChDisable(uint8 chHandle) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaClearPendingDrq\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Clears pending the DMA data request.\r
+* Clears pending the DMA data request.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* Handle to the dma channel.\r
+* \param chHandle Handle to the dma channel.\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaClearPendingDrq(uint8 chHandle) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaChPriority\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the priority of a DMA channel. You can use this function when you want\r
* to change the priority at run time. If the priority remains the same for a\r
* DMA channel, then you can configure the priority in the .cydwr file.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref\r
+* DMA_DmaInitalize().\r
*\r
-* uint8 priority:\r
-* Priority to set the channel to, 0 - 7.\r
+* \param priority Priority to set the channel to, 0 - 7.\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaChSetExtendedAddress\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the high 16 bits of the source and destination addresses for the DMA\r
* channel (valid for all TDs in the chain).\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref\r
+* DMA_DmaInitalize().\r
*\r
-* uint16 source:\r
-* Upper 16 bit address of the DMA transfer source.\r
+* \param source Upper 16 bit address of the DMA transfer source.\r
*\r
-* uint16 destination:\r
-* Upper 16 bit address of the DMA transfer destination.\r
+* \param destination Upper 16 bit address of the DMA transfer destination.\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination) \\r
\r
/*******************************************************************************\r
* Function Name: CyDmaChSetInitialTd\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Sets the initial TD to be executed for the channel when the CyDmaChEnable()\r
-* function is called.\r
+* Sets the initial TD to be executed for the channel when the \ref CyDmaChEnable()\r
+* function is called.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().\r
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or\r
+* \ref DMA_DmaInitialize().\r
*\r
-* uint8 startTd:\r
-* Set the TD index as the first TD associated with the channel. Zero is\r
-* a valid TD index.\r
+* \param startTd Set the TD index as the first TD associated with the\r
+* channel. Zero is a valid TD index.\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaChSetRequest\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Allows the caller to terminate a chain of TDs, terminate one TD, or create a\r
* direct request to start the DMA channel.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
-*\r
-* uint8 request:\r
-* One of the following constants. Each of the constants is a three-bit value.\r
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref\r
+* DMA_DmaInitalize().\r
*\r
+* \param request One of the following constants. Each of the constants is a\r
+* three-bit value.\r
* CPU_REQ - Create a direct request to start the DMA channel\r
* CPU_TERM_TD - Terminate one TD\r
* CPU_TERM_CHAIN - Terminate a chain of TDs\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaChGetRequest\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* This function allows the caller of CyDmaChSetRequest() to determine if the\r
-* request was completed.\r
+* This function allows the caller of \ref CyDmaChSetRequest() to determine if the\r
+* request was completed.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref\r
+* DMA_DmaInitalize().\r
*\r
-* Return:\r
-* Returns a three-bit field, corresponding to the three bits of the request,\r
-* which describes the state of the previously posted request. If the value is\r
-* zero, the request was completed. CY_DMA_INVALID_CHANNEL if the handle is\r
-* invalid.\r
+* \return Returns a three-bit field, corresponding to the three bits of the\r
+* request, which describes the state of the previously posted request. If the\r
+* value is zero, the request was completed. CY_DMA_INVALID_CHANNEL if the handle\r
+* is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChGetRequest(uint8 chHandle) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaChStatus\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Determines the status of the DMA channel.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref\r
+* DMA_DmaInitalize().\r
*\r
-* uint8 * currentTd:\r
-* The address to store the index of the current TD. Can be NULL if the value\r
-* is not needed.\r
+* \param currentTd The address to store the index of the current TD. Can be NULL\r
+* if the value is not needed.\r
*\r
-* uint8 * state:\r
-* The address to store the state of the channel. Can be NULL if the value is\r
-* not needed.\r
+* \param state The address to store the state of the channel. Can be NULL if the\r
+* value is not needed.\r
*\r
* STATUS_TD_ACTIVE\r
-* 0: Channel is not currently being serviced by DMAC\r
-* 1: Channel is currently being serviced by DMAC\r
+* \param 0: Channel is not currently being serviced by DMAC\r
+* \param 1: Channel is currently being serviced by DMAC\r
*\r
* STATUS_CHAIN_ACTIVE\r
-* 0: TD chain is inactive; either no DMA requests have triggered a new chain\r
+* \param 0: TD chain is inactive; either no DMA requests have triggered a new chain\r
* or the previous chain has completed.\r
-* 1: TD chain has been triggered by a DMA request\r
+* \param 1: TD chain has been triggered by a DMA request\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
* Theory:\r
* The caller can check on the activity of the Current TD and the Chain.\r
\r
/*******************************************************************************\r
* Function Name: CyDmaChSetConfiguration\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets configuration information of the channel.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
+* \param uint8 chHandle:\r
* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().\r
*\r
-* uint8 burstCount:\r
+* \param uint8 burstCount:\r
* Specifies the size of bursts (1 to 127) the data transfer should be divided\r
* into. If this value is zero then the whole transfer is done in one burst.\r
*\r
-* uint8 requestPerBurst:\r
+* \param uint8 requestPerBurst:\r
* The whole of the data can be split into multiple bursts, if this is\r
-* required to complete the transaction:\r
-* 0: All subsequent bursts after the first burst will be automatically\r
+* \param required to complete the transaction:\r
+* \param 0: All subsequent bursts after the first burst will be automatically\r
* requested and carried out\r
-* 1: All subsequent bursts after the first burst must also be individually\r
+* \param 1: All subsequent bursts after the first burst must also be individually\r
* requested.\r
*\r
-* uint8 tdDone0:\r
+* \param uint8 tdDone0:\r
* Selects one of the TERMOUT0 interrupt lines to signal completion. The line\r
* connected to the nrq terminal will determine the TERMOUT0_SEL definition and\r
* should be used as supplied by cyfitter.h\r
*\r
-* uint8 tdDone1:\r
+* \param uint8 tdDone1:\r
* Selects one of the TERMOUT1 interrupt lines to signal completion. The line\r
* connected to the nrq terminal will determine the TERMOUT1_SEL definition and\r
* should be used as supplied by cyfitter.h\r
*\r
-* uint8 tdStop:\r
+* \param uint8 tdStop:\r
* Selects one of the TERMIN interrupt lines to signal to the DMAC that the TD\r
* should terminate. The signal connected to the trq terminal will determine\r
* which TERMIN (termination request) is used.\r
*\r
-* Return:\r
+* \return\r
* CYRET_SUCCESS if successful.\r
* CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyDmaTdAllocate\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Allocates a TD for use with an allocated DMA channel.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* Zero-based index of the TD to be used by the caller. Since there are 128 TDs\r
* minus the reserved TDs (0 to 23), the value returned would range from 24 to\r
* 127 not 24 to 128. DMA_INVALID_TD is returned if there are no free TDs\r
\r
/*******************************************************************************\r
* Function Name: CyDmaTdFree\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Returns a TD to the free list.\r
*\r
-* Parameters:\r
-* uint8 tdHandle:\r
+* \param uint8 tdHandle:\r
* The TD handle returned by the CyDmaTdAllocate().\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyDmaTdFree(uint8 tdHandle) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyDmaTdFreeCount\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Returns the number of free TDs available to be allocated.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* The number of free TDs.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyDmaTdSetConfiguration\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Configures the TD.\r
*\r
-* Parameters:\r
-* uint8 tdHandle:\r
+* \param uint8 tdHandle:\r
* A handle previously returned by CyDmaTdAlloc().\r
*\r
-* uint16 transferCount:\r
+* \param uint16 transferCount:\r
* The size of the data transfer (in bytes) for this TD. A size of zero will\r
* cause the transfer to continue indefinitely. This parameter is limited to\r
* 4095 bytes; the TD is not initialized at all when a higher value is passed.\r
*\r
-* uint8 nextTd:\r
+* \param uint8 nextTd:\r
* Zero based index of the next Transfer Descriptor in the TD chain. Zero is a\r
* valid pointer to the next TD; DMA_END_CHAIN_TD is the end of the chain.\r
* DMA_DISABLE_TD indicates an end to the chain and the DMA is disabled. No\r
* further TDs are fetched. DMA_DISABLE_TD is only supported on PSoC3 and\r
* PSoC 5LP silicons.\r
*\r
-* uint8 configuration:\r
+* \param uint8 configuration:\r
* Stores the Bit field of configuration bits.\r
*\r
* CY_DMA_TD_SWAP_EN - Perform endian swap\r
* CY_DMA_TD_INC_SRC_ADR - Increment SRC_ADR according to the size of each\r
* data transaction in the burst.\r
*\r
-* Return:\r
+* \return\r
* CYRET_SUCCESS if successful.\r
* CYRET_BAD_PARAM if tdHandle or transferCount is invalid.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyDmaTdGetConfiguration\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Retrieves the configuration of the TD. If a NULL pointer is passed as a\r
* parameter, that parameter is skipped. You may request only the values you are\r
* interested in.\r
*\r
-* Parameters:\r
-* uint8 tdHandle:\r
+* \param uint8 tdHandle:\r
* A handle previously returned by CyDmaTdAlloc().\r
*\r
-* uint16 * transferCount:\r
+* \param uint16 * transferCount:\r
* The address to store the size of the data transfer (in bytes) for this TD.\r
* A size of zero could indicate that the TD has completed its transfer, or\r
* that the TD is doing an indefinite transfer.\r
*\r
-* uint8 * nextTd:\r
+* \param uint8 * nextTd:\r
* The address to store the index of the next TD in the TD chain.\r
*\r
-* uint8 * configuration:\r
+* \param uint8 * configuration:\r
* The address to store the Bit field of configuration bits.\r
* See CyDmaTdSetConfiguration() function description.\r
*\r
-* Return:\r
+* \return\r
* CYRET_SUCCESS if successful.\r
* CYRET_BAD_PARAM if tdHandle is invalid.\r
*\r
-* Side Effects:\r
+* \sideeffect\r
* If TD has a transfer count of N and is executed, the transfer count becomes\r
* 0. If it is reexecuted, the Transfer count of zero will be interpreted as a\r
* request for indefinite transfer. Be careful when requesting TD with a\r
\r
/*******************************************************************************\r
* Function Name: CyDmaTdSetAddress\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the lower 16 bits of the source and destination addresses for this TD\r
* only.\r
*\r
-* Parameters:\r
-* uint8 tdHandle:\r
+* \param uint8 tdHandle:\r
* A handle previously returned by CyDmaTdAlloc().\r
*\r
-* uint16 source:\r
+* \param uint16 source:\r
* The lower 16 address bits of the source of the data transfer.\r
*\r
-* uint16 destination:\r
+* \param uint16 destination:\r
* The lower 16 address bits of the destination of the data transfer.\r
*\r
-* Return:\r
+* \return\r
* CYRET_SUCCESS if successful.\r
* CYRET_BAD_PARAM if tdHandle is invalid.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyDmaTdGetAddress\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Retrieves the lower 16 bits of the source and/or destination addresses for\r
* this TD only. If NULL is passed for a pointer parameter, that value is\r
* skipped. You may request only the values of interest.\r
*\r
-* Parameters:\r
-* uint8 tdHandle:\r
+* \param uint8 tdHandle:\r
* A handle previously returned by CyDmaTdAlloc().\r
*\r
-* uint16 * source:\r
+* \param uint16 * source:\r
* The address to store the lower 16 address bits of the source of the data\r
* transfer.\r
*\r
-* uint16 * destination:\r
+* \param uint16 * destination:\r
* The address to store the lower 16 address bits of the destination of the\r
* data transfer.\r
*\r
-* Return:\r
+* \return\r
* CYRET_SUCCESS if successful.\r
* CYRET_BAD_PARAM if tdHandle is invalid.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyDmaChRoundRobin\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Either enables or disables the Round-Robin scheduling enforcement algorithm.\r
-* Within a priority level a Round-Robin fairness algorithm is enforced.\r
+* Either enables or disables the Round-Robin scheduling enforcement algorithm.\r
+* Within a priority level a Round-Robin fairness algorithm is enforced.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or Dma_DmaInitialize().\r
+* \param uint8 chHandle:\r
+* A handle previously returned by CyDmaChAlloc() or Dma_DmaInitialize().\r
*\r
-* uint8 enableRR:\r
-* 0: Disable Round-Robin fairness algorithm\r
-* 1: Enable Round-Robin fairness algorithm\r
+* \param uint8 enableRR:\r
+* \param 0: Disable Round-Robin fairness algorithm\r
+* \param 1: Enable Round-Robin fairness algorithm\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) \r
-/*******************************************************************************\r
-* File Name: CyDmac.h\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file CyDmac.h\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides the function definitions for the DMA Controller.\r
+* \brief Provides the function definitions for the DMA Controller.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the\r
-* System Reference Guide provided with PSoC Creator.\r
+* \note Documentation of the API's in this file is located in the System\r
+* Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
-/*******************************************************************************\r
-* File Name: CyFlash.c\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file CyFlash.c\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides an API for the FLASH/EEPROM.\r
+* \brief Provides an API for the FLASH/EEPROM.\r
*\r
-* Note:\r
-* This code is endian agnostic.\r
+* \note This code is endian agnostic.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the\r
-* System Reference Guide provided with PSoC Creator.\r
+* \note Documentation of the API's in this file is located in the System\r
+* Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: CyFlash_Start\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enable the Flash.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyFlash_Start(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyFlash_Stop\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disable the Flash.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* This setting is ignored as long as the CPU is currently running. This will\r
* only take effect when the CPU is later disabled.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CySetTempInt\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sends a command to the SPC to read the die temperature. Sets a global value\r
* used by the Write function. This function must be called once before\r
* executing a series of Flash writing functions.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* status:\r
* CYRET_SUCCESS - if successful\r
* CYRET_LOCKED - if Flash writing already in use\r
\r
/*******************************************************************************\r
* Function Name: CyFlashGetSpcAlgorithm\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sends a command to the SPC to download code into RAM.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* status:\r
* CYRET_SUCCESS - if successful\r
* CYRET_LOCKED - if Flash writing already in use\r
\r
/*******************************************************************************\r
* Function Name: CySetTemp\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This is a wraparound for CySetTempInt(). It is used to return the second\r
* successful read of the temperature value.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* status:\r
* CYRET_SUCCESS if successful.\r
* CYRET_LOCKED if Flash writing already in use\r
\r
/*******************************************************************************\r
* Function Name: CySetFlashEEBuffer\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the user supplied temporary buffer to store SPC data while performing\r
-* Flash and EEPROM commands. This buffer is only necessary when the Flash ECC is\r
-* disabled.\r
+* Flash and EEPROM commands. This buffer is only necessary when the Flash ECC\r
+* is disabled.\r
*\r
-* Parameters:\r
-* buffer:\r
-* The address of a block of memory to store temporary memory. The size of the block\r
-* of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.\r
+* \param buffer:\r
+* The address of a block of memory to store temporary memory. The size of the\r
+* block of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.\r
*\r
-* Return:\r
+* \return\r
* status:\r
* CYRET_SUCCESS if successful.\r
* CYRET_BAD_PARAM if the buffer is NULL\r
\r
/*******************************************************************************\r
* Function Name: CyWriteRowData\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sends a command to the SPC to load and program a row of data in\r
* Flash or EEPROM.\r
*\r
-* Parameters:\r
-* arrayID: ID of the array to write.\r
+* \param arrayID: ID of the array to write.\r
* The type of write, Flash or EEPROM, is determined from the array ID.\r
* The arrays in the part are sequential starting at the first ID for the\r
* specific memory type. The array ID for the Flash memory lasts from 0x00 to\r
* 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.\r
-* rowAddress: rowAddress of flash row to program.\r
-* rowData: Array of bytes to write.\r
+* \param rowAddress: rowAddress of flash row to program.\r
+* \param rowData: Array of bytes to write.\r
*\r
-* Return:\r
+* \return\r
* status:\r
* CYRET_SUCCESS if successful.\r
* CYRET_LOCKED if the SPC is already in use.\r
\r
/*******************************************************************************\r
* Function Name: CyWriteRowConfig\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
- * Sends a command to the SPC to load and program a row of config data in the Flash.\r
- * This function is only valid for Flash array IDs (not for EEPROM).\r
+ * Sends a command to the SPC to load and program a row of config data in the\r
+ * Flash. This function is only valid for Flash array IDs (not for EEPROM).\r
*\r
- * Parameters:\r
- * arrayId: ID of the array to write\r
+ * \param arrayId: ID of the array to write\r
* The arrays in the part are sequential starting at the first ID for the\r
* specific memory type. The array ID for the Flash memory lasts\r
* from 0x00 to 0x3F.\r
- * rowAddress: The address of the sector to erase.\r
- * rowECC: The array of bytes to write.\r
+ * \param rowAddress: The address of the sector to erase.\r
+ * \param rowECC: The array of bytes to write.\r
*\r
- * Return:\r
+ * \return\r
* status:\r
* CYRET_SUCCESS if successful.\r
* CYRET_LOCKED if the SPC is already in use.\r
\r
/*******************************************************************************\r
* Function Name: CyWriteRowFull\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Sends a command to the SPC to load and program a row of data in the Flash.\r
* rowData array is expected to contain Flash and ECC data if needed.\r
*\r
-* Parameters:\r
-* arrayId: FLASH or EEPROM array id.\r
-* rowData: Pointer to a row of data to write.\r
-* rowNumber: Zero based number of the row.\r
-* rowSize: Size of the row.\r
+* \param arrayId: FLASH or EEPROM array id.\r
+* \param rowData: Pointer to a row of data to write.\r
+* \param rowNumber: Zero based number of the row.\r
+* \param rowSize: Size of the row.\r
*\r
-* Return:\r
+* \return\r
* CYRET_SUCCESS if successful.\r
* CYRET_LOCKED if the SPC is already in use.\r
* CYRET_CANCELED if command not accepted\r
\r
/*******************************************************************************\r
* Function Name: CyFlash_SetWaitCycles\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the number of clock cycles the cache will wait before it samples data\r
-* coming back from the Flash. This function must be called before increasing the CPU\r
-* clock frequency. It can optionally be called after lowering the CPU clock\r
-* frequency in order to improve the CPU performance.\r
+* coming back from the Flash. This function must be called before increasing\r
+* the CPU clock frequency. It can optionally be called after lowering the CPU\r
+* clock frequency in order to improve the CPU performance.\r
*\r
-* Parameters:\r
-* uint8 freq:\r
+* \param uint8 freq:\r
* Frequency of operation in Megahertz.\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyFlash_SetWaitCycles(uint8 freq) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyEEPROM_Start\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enable the EEPROM.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyEEPROM_Start(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyEEPROM_Stop\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disable the EEPROM.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyEEPROM_Stop (void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyEEPROM_ReadReserve\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Request access to the EEPROM for reading and wait until access is available.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyEEPROM_ReadReserve(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyEEPROM_ReadRelease\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Release the read reservation of the EEPROM.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyEEPROM_ReadRelease(void) \r
{\r
-/*******************************************************************************\r
-* File Name: CyFlash.h\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file CyFlash.h\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides the function definitions for the FLASH/EEPROM.\r
+* \brief Provides the function definitions for the FLASH/EEPROM.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the\r
-* System Reference Guide provided with PSoC Creator.\r
+* \note Documentation of the API's in this file is located in the System\r
+* Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#endif /* (CYDEV_ECC_ENABLE == 0) */\r
#define CY_EEPROM_BASE (CYDEV_EE_BASE)\r
#define CY_EEPROM_SIZE (CYDEV_EE_SIZE)\r
-#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EEPROM_SECTOR_SIZE)\r
+#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EE_SIZE) /* EEPROM has one array */\r
#define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE)\r
#define CY_EEPROM_NUMBER_ROWS (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE)\r
#define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY)\r
#define FLASH_NUMBER_ROWS (CY_FLASH_NUMBER_ROWS)\r
#define FLASH_NUMBER_SECTORS (CY_FLASH_NUMBER_ARRAYS)\r
#define EEPROM_SIZE (CY_EEPROM_SIZE)\r
-#define EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY)\r
+#define EEPROM_SIZEOF_SECTOR (CYDEV_EEPROM_SECTOR_SIZE)\r
#define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS)\r
-#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS)\r
+#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_SECTORS)\r
\r
\r
/*******************************************************************************\r
-/*******************************************************************************\r
-* File Name: CyLib.c\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file CyLib.c\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides a system API for the clocking, interrupts and watchdog timer.\r
+* \brief Provides a system API for the clocking, interrupts and watchdog timer.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the\r
-* System Reference Guide provided with PSoC Creator.\r
+* \note Documentation of the API's in this file is located in the System\r
+* Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
static void CyBusClk_Internal_SetDivider(uint16 divider);\r
\r
#if(CY_PSOC5)\r
- static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];\r
+ static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];\r
static void CySysTickServiceCallbacks(void);\r
uint32 CySysTickInitVar = 0u;\r
#endif /* (CY_PSOC5) */\r
\r
\r
+#if(CY_PSOC3)\r
+ CY_ISR_PROTO(IntDefaultHandler);\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
/*******************************************************************************\r
* Function Name: CyPLL_OUT_Start\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the PLL. Optionally waits for it to become stable.\r
* Waits at least 250 us or until it is detected that the PLL is stable.\r
*\r
-* Parameters:\r
-* wait:\r
-* 0: Return immediately after configuration\r
-* 1: Wait for PLL lock or timeout.\r
+* \param wait:\r
+* \param 0: Return immediately after configuration\r
+* \param 1: Wait for PLL lock or timeout.\r
*\r
-* Return:\r
+* \return\r
* Status\r
* CYRET_SUCCESS - Completed successfully\r
* CYRET_TIMEOUT - Timeout occurred without detecting a stable clock.\r
* may not occur. However, after the timeout has expired the generated PLL\r
* clock can still be used.\r
*\r
-* Side Effects:\r
+* \sideeffect\r
* If wait is enabled: This function uses the Fast Time Wheel to time the wait.\r
* Any other use of the Fast Time Wheel will be stopped during the period of\r
* this function and then restored. This function also uses the 100 KHz ILO.\r
\r
/*******************************************************************************\r
* Function Name: CyPLL_OUT_Stop\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the PLL.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyPLL_OUT_Stop(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyPLL_OUT_SetPQ\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the P and Q dividers and the charge pump current.\r
* The Frequency Out will be P/Q * Frequency In.\r
* The PLL must be disabled before calling this function.\r
*\r
-* Parameters:\r
-* uint8 pDiv:\r
+* \param uint8 pDiv:\r
* Valid range [8 - 255].\r
*\r
-* uint8 qDiv:\r
+* \param uint8 qDiv:\r
* Valid range [1 - 16]. Input Frequency / Q must be in range of 1 to 3 MHz.\r
\r
-* uint8 current:\r
+* \param uint8 current:\r
* Valid range [1 - 7]. Charge pump current in uA. Refer to the device TRM and\r
* datasheet for more information.\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* If this function execution results in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with an appropriate parameter. It can be optionally called if the CPU clock\r
-* frequency is lowered in order to improve the CPU performance.\r
-* See CyFlash_SetWaitCycles() description for more information.\r
+* coming back from the Flash must be adjusted by calling\r
+* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally\r
+* called if the CPU clock frequency is lowered in order to improve the CPU\r
+* performance. See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) \r
\r
/*******************************************************************************\r
* Function Name: CyPLL_OUT_SetSource\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the input clock source to the PLL. The PLL must be disabled before\r
* calling this function.\r
*\r
-* Parameters:\r
-* source: One of the three available PLL clock sources\r
-* CY_PLL_SOURCE_IMO : IMO\r
-* CY_PLL_SOURCE_XTAL : MHz Crystal\r
-* CY_PLL_SOURCE_DSI : DSI\r
-*\r
-* Return:\r
-* None\r
+* \param source: One of the three available PLL clock sources\r
+* \param CY_PLL_SOURCE_IMO : IMO\r
+* \param CY_PLL_SOURCE_XTAL : MHz Crystal\r
+* \param CY_PLL_SOURCE_DSI : DSI\r
*\r
-* Side Effects:\r
+* \sideeffect\r
* If this function execution results in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from the3 Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with an appropriate parameter. It can be optionally called if the CPU clock\r
-* frequency is lowered in order to improve the CPU performance.\r
-* See CyFlash_SetWaitCycles() description for more information.\r
+* coming back from the3 Flash must be adjusted by calling\r
+* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally\r
+* called if the CPU clock frequency is lowered in order to improve the CPU\r
+* performance. See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
void CyPLL_OUT_SetSource(uint8 source) \r
\r
/*******************************************************************************\r
* Function Name: CyIMO_Start\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the IMO. Optionally waits at least 6 us for it to settle.\r
*\r
-* Parameters:\r
-* uint8 wait:\r
-* 0: Return immediately after configuration\r
-* 1: Wait for at least 6 us for the IMO to settle.\r
-*\r
-* Return:\r
-* None\r
+* \param uint8 wait:\r
+* \param 0: Return immediately after configuration\r
+* \param 1: Wait for at least 6 us for the IMO to settle.\r
*\r
-* Side Effects:\r
+* \sideeffect\r
* If wait is enabled: This function uses the Fast Time Wheel to time the wait.\r
* Any other use of the Fast Time Wheel will be stopped during the period of\r
* this function and then restored. This function also uses the 100 KHz ILO.\r
\r
/*******************************************************************************\r
* Function Name: CyIMO_Stop\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the IMO.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyIMO_Stop(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyUSB_PowerOnCheck\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Returns the USB power status value. A private function to cy_boot.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* uint8: one if the USB is enabled, 0 if not enabled.\r
*\r
*******************************************************************************/\r
{\r
uint8 poweredOn = 0u;\r
\r
- /* Check whether device is in Active or AltActiv and if USB is powered on */\r
+ /* Check whether device is in Active or AltActive and if USB is powered on */\r
if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) &&\r
(0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) ||\r
(((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) &&\r
\r
/*******************************************************************************\r
* Function Name: CyIMO_SetTrimValue\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the IMO factory trim values.\r
*\r
-* Parameters:\r
* uint8 freq - frequency for which trims must be set\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
static void CyIMO_SetTrimValue(uint8 freq) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyIMO_SetFreq\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the frequency of the IMO. Changes may be made while the IMO is running.\r
*\r
-* Parameters:\r
-* freq: Frequency of IMO operation\r
+* \param freq: Frequency of IMO operation\r
* CY_IMO_FREQ_3MHZ to set 3 MHz\r
* CY_IMO_FREQ_6MHZ to set 6 MHz\r
* CY_IMO_FREQ_12MHZ to set 12 MHz\r
* CY_IMO_FREQ_74MHZ to set 74.7 MHz (not applicable for PSoC 3)\r
* CY_IMO_FREQ_USB to set 24 MHz (Trimmed for USB operation)\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* If this function execution results in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with an appropriate parameter. It can be optionally called if the CPU clock\r
-* frequency is lowered in order to improve the CPU performance.\r
-* See CyFlash_SetWaitCycles() description for more information.\r
+* coming back from the Flash must be adjusted by calling\r
+* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally\r
+* called if the CPU clock frequency is lowered in order to improve the CPU\r
+* performance. See CyFlash_SetWaitCycles() description for more information.\r
*\r
* When the USB setting is chosen, the USB clock locking circuit is enabled.\r
* Otherwise this circuit is disabled. The USB block must be powered before\r
\r
/*******************************************************************************\r
* Function Name: CyIMO_SetSource\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the source of the clock output from the IMO block.\r
*\r
* The output from the IMO is by default the IMO itself. Optionally the MHz\r
* Crystal or DSI input can be the source of the IMO output instead.\r
*\r
-* Parameters:\r
-* source: CY_IMO_SOURCE_DSI to set the DSI as source.\r
+* \param source: CY_IMO_SOURCE_DSI to set the DSI as source.\r
* CY_IMO_SOURCE_XTAL to set the MHz as source.\r
* CY_IMO_SOURCE_IMO to set the IMO itself.\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with an appropriate parameter. It can be optionally called if the CPU clock\r
-* frequency is lowered in order to improve the CPU performance.\r
-* See CyFlash_SetWaitCycles() description for more information.\r
+* coming back from the Flash must be adjusted by calling\r
+* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally\r
+* called if the CPU clock frequency is lowered in order to improve the CPU\r
+* performance. See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
void CyIMO_SetSource(uint8 source) \r
\r
/*******************************************************************************\r
* Function Name: CyIMO_EnableDoubler\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the IMO doubler. The 2x frequency clock is used to convert a 24 MHz\r
* input to a 48 MHz output for use by the USB block.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyIMO_EnableDoubler(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyIMO_DisableDoubler\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the IMO doubler.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyIMO_DisableDoubler(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyMasterClk_SetSource\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the source of the master clock.\r
*\r
-* Parameters:\r
-* source: One of the four available Master clock sources.\r
+* \param source: One of the four available Master clock sources.\r
* CY_MASTER_SOURCE_IMO\r
* CY_MASTER_SOURCE_PLL\r
* CY_MASTER_SOURCE_XTAL\r
* CY_MASTER_SOURCE_DSI\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* The current source and the new source must both be running and stable before\r
* calling this function.\r
*\r
* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with an appropriate parameter. It can be optionally called if the CPU clock\r
-* frequency is lowered in order to improve the CPU performance.\r
-* See CyFlash_SetWaitCycles() description for more information.\r
+* coming back from the Flash must be adjusted by calling\r
+* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally\r
+* called if the CPU clock frequency is lowered in order to improve the CPU\r
+* performance. See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
void CyMasterClk_SetSource(uint8 source) \r
\r
/*******************************************************************************\r
* Function Name: CyMasterClk_SetDivider\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the divider value used to generate Master Clock.\r
*\r
-* Parameters:\r
-* uint8 divider:\r
+* \param uint8 divider:\r
* The valid range is [0-255]. The clock will be divided by this value + 1.\r
* For example to divide this parameter by two should be set to 1.\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with an appropriate parameter. It can be optionally called if the CPU clock\r
-* frequency is lowered in order to improve the CPU performance.\r
-* See CyFlash_SetWaitCycles() description for more information.\r
+* coming back from the Flash must be adjusted by calling\r
+* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally\r
+* called if the CPU clock frequency is lowered in order to improve the CPU\r
+* performance. See CyFlash_SetWaitCycles() description for more information.\r
*\r
* When changing the Master or Bus clock divider value from div-by-n to div-by-1\r
* the first clock cycle output after the div-by-1 can be up to 4 ns shorter\r
\r
/*******************************************************************************\r
* Function Name: CyBusClk_Internal_SetDivider\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* The function used by CyBusClk_SetDivider(). For internal use only.\r
*\r
-* Parameters:\r
-* divider: Valid range [0-65535].\r
+* \param divider: Valid range [0-65535].\r
* The clock will be divided by this value + 1.\r
* For example, to divide this parameter by two should be set to 1.\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
static void CyBusClk_Internal_SetDivider(uint16 divider)\r
{\r
\r
/*******************************************************************************\r
* Function Name: CyBusClk_SetDivider\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the divider value used to generate the Bus Clock.\r
*\r
-* Parameters:\r
-* divider: Valid range [0-65535]. The clock will be divided by this value + 1.\r
+* \param divider: Valid range [0-65535]. The clock will be divided by this value + 1.\r
* For example, to divide this parameter by two should be set to 1.\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with an appropriate parameter. It can be optionally called if the CPU clock\r
-* frequency is lowered in order to improve the CPU performance.\r
-* See CyFlash_SetWaitCycles() description for more information.\r
+* coming back from the Flash must be adjusted by calling\r
+* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally\r
+* called if the CPU clock frequency is lowered in order to improve the CPU\r
+* performance. See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
void CyBusClk_SetDivider(uint16 divider) \r
\r
/*******************************************************************************\r
* Function Name: CyCpuClk_SetDivider\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Sets the divider value used to generate the CPU Clock. Only applicable for\r
* PSoC 3 parts.\r
*\r
- * Parameters:\r
- * divider: Valid range [0-15]. The clock will be divided by this value + 1.\r
+ * \param divider: Valid range [0-15]. The clock will be divided by this value + 1.\r
* For example, to divide this parameter by two should be set to 1.\r
*\r
- * Return:\r
- * None\r
- *\r
- * Side Effects:\r
+ * \sideeffect\r
* If this function execution resulted in the CPU clock frequency increasing,\r
-* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with an appropriate parameter. It can be optionally called if the CPU clock\r
-* frequency is lowered in order to improve the CPU performance.\r
- * See CyFlash_SetWaitCycles() description for more information.\r
+ * then the number of clock cycles the cache will wait before it samples data\r
+ * coming back from the Flash must be adjusted by calling\r
+ * CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally\r
+ * called if the CPU clock frequency is lowered in order to improve the CPU\r
+ * performance. See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
void CyCpuClk_SetDivider(uint8 divider) \r
\r
/*******************************************************************************\r
* Function Name: CyUsbClk_SetSource\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the source of the USB clock.\r
*\r
-* Parameters:\r
-* source: One of the four available USB clock sources\r
+* \param source: One of the four available USB clock sources\r
* CY_LIB_USB_CLK_IMO2X - IMO 2x\r
* CY_LIB_USB_CLK_IMO - IMO\r
* CY_LIB_USB_CLK_PLL - PLL\r
* CY_LIB_USB_CLK_DSI - DSI\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyUsbClk_SetSource(uint8 source) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyILO_Start1K\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the ILO 1 KHz oscillator.\r
*\r
* Note The ILO 1 KHz oscillator is always enabled by default, regardless of the\r
* selection in the Clock Editor. Therefore, this API is only needed if the\r
* oscillator was turned off manually.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyILO_Start1K(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyILO_Stop1K\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the ILO 1 KHz oscillator.\r
*\r
-* Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low power\r
-* mode APIs are expected to be used. For more information, refer to the Power\r
-* Management section of this document.\r
-*\r
-* Parameters:\r
-* None\r
+* Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low\r
+* power mode APIs are expected to be used. For more information, refer to the\r
+* Power Management section of this document.\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* PSoC5: Stopping the ILO 1 kHz could break the active WDT functionality.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyILO_Start100K\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the ILO 100 KHz oscillator.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyILO_Start100K(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyILO_Stop100K\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the ILO 100 KHz oscillator.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyILO_Stop100K(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyILO_Enable33K\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the ILO 33 KHz divider.\r
*\r
* Note that the 33 KHz clock is generated from the 100 KHz oscillator,\r
* so it must also be running in order to generate the 33 KHz output.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyILO_Enable33K(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyILO_Disable33K\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the ILO 33 KHz divider.\r
*\r
* Note that the 33 KHz clock is generated from the 100 KHz oscillator, but this\r
* API does not disable the 100 KHz clock.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyILO_Disable33K(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyILO_SetSource\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the source of the clock output from the ILO block.\r
*\r
-* Parameters:\r
-* source: One of the three available ILO output sources\r
+* \param source: One of the three available ILO output sources\r
* Value Define Source\r
* 0 CY_ILO_SOURCE_100K ILO 100 KHz\r
* 1 CY_ILO_SOURCE_33K ILO 33 KHz\r
* 2 CY_ILO_SOURCE_1K ILO 1 KHz\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyILO_SetSource(uint8 source) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyILO_SetPowerMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Sets the power mode used by the ILO during power down. Allows for lower power\r
-* down power usage resulting in a slower startup time.\r
+* Sets the power mode used by the ILO during power down. Allows for lower power\r
+* down power usage resulting in a slower startup time.\r
*\r
-* Parameters:\r
-* uint8 mode\r
-* CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down\r
-* CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down\r
+* \param mode\r
+* CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down\r
+* CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down\r
*\r
-* Return:\r
-* Prevous power mode state.\r
+* \return Prevous power mode state.\r
*\r
*******************************************************************************/\r
uint8 CyILO_SetPowerMode(uint8 mode) \r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_32KHZ_Start\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the 32 KHz Crystal Oscillator.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_32KHZ_Start(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_32KHZ_Stop\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the 32KHz Crystal Oscillator.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_32KHZ_Stop(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_32KHZ_ReadStatus\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Returns status of the 32 KHz oscillator.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* Value Define Source\r
* 20 CY_XTAL32K_ANA_STAT Analog measurement\r
* 1: Stable\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_32KHZ_SetPowerMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the power mode for the 32 KHz oscillator used during the sleep mode.\r
* Allows for lower power during sleep when there are fewer sources of noise.\r
* During the active mode the oscillator is always run in the high power mode.\r
*\r
-* Parameters:\r
* uint8 mode\r
-* 0: High power mode\r
-* 1: Low power mode during sleep\r
+* \param 0: High power mode\r
+* \param 1: Low power mode during sleep\r
*\r
-* Return:\r
+* \return\r
* Previous power mode.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_Start\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the megahertz crystal.\r
*\r
* PSoC 3:\r
* Waits until the XERR bit is low (no error) for a millisecond or until the\r
* number of milliseconds specified by the wait parameter has expired.\r
*\r
-* Parameters:\r
-* wait: Valid range [0-255].\r
+* \param wait: Valid range [0-255].\r
* This is the timeout value in milliseconds.\r
* The appropriate value is crystal specific.\r
*\r
-* Return:\r
+* \return\r
* CYRET_SUCCESS - Completed successfully\r
* CYRET_TIMEOUT - Timeout occurred without detecting a low value on XERR.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_Stop\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the megahertz crystal oscillator.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_Stop(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_EnableErrStatus\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the generation of the XERR status bit for the megahertz crystal.\r
* This function is not available for PSoC5.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_EnableErrStatus(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_DisableErrStatus\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the generation of the XERR status bit for the megahertz crystal.\r
* This function is not available for PSoC5.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_DisableErrStatus(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_ReadStatus\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Reads the XERR status bit for the megahertz crystal. This status bit is a\r
* sticky, clear on read. This function is not available for PSoC5.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* Status\r
* 0: No error\r
* 1: Error\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_EnableFaultRecovery\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the fault recovery circuit which will switch to the IMO in the case\r
* of a fault in the megahertz crystal circuit. The crystal must be up and\r
* running with the XERR bit at 0, before calling this function to prevent\r
* an immediate fault switchover. This function is not available for PSoC5.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_EnableFaultRecovery(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_DisableFaultRecovery\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the fault recovery circuit which will switch to the IMO in the case\r
* of a fault in the megahertz crystal circuit. This function is not available\r
* for PSoC5.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_DisableFaultRecovery(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_SetStartup\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Sets the startup settings for the crystal. The logic model outputs a frequency\r
-* (setting + 4) MHz when enabled.\r
+* Sets the startup settings for the crystal. The logic model outputs a\r
+* frequency (setting + 4) MHz when enabled.\r
*\r
* This is artificial as the actual frequency is determined by an attached\r
* external crystal.\r
*\r
-* Parameters:\r
-* setting: Valid range [0-31].\r
-* The value is dependent on the frequency and quality of the crystal being used.\r
-* Refer to the device TRM and datasheet for more information.\r
-*\r
-* Return:\r
-* None\r
+* \param setting: Valid range [0-31].\r
+* The value is dependent on the frequency and quality of the crystal being\r
+* used. Refer to the device TRM and datasheet for more information.\r
*\r
*******************************************************************************/\r
void CyXTAL_SetStartup(uint8 setting) \r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_SetFbVoltage\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the feedback reference voltage to use for the crystal circuit.\r
* This function is only available for PSoC3 and PSoC 5LP.\r
*\r
-* Parameters:\r
-* setting: Valid range [0-15].\r
+* \param setting: Valid range [0-15].\r
* Refer to the device TRM and datasheet for more information.\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_SetFbVoltage(uint8 setting) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_SetWdVoltage\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the reference voltage used by the watchdog to detect a failure in the\r
* crystal circuit. This function is only available for PSoC3 and PSoC 5LP.\r
*\r
-* Parameters:\r
-* setting: Valid range [0-7].\r
+* \param setting: Valid range [0-7].\r
* Refer to the device TRM and datasheet for more information.\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_SetWdVoltage(uint8 setting) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyHalt\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Halts the CPU.\r
*\r
-* Parameters:\r
-* uint8 reason: Value to be used during debugging.\r
-*\r
-* Return:\r
-* None\r
+* \param uint8 reason: Value to be used during debugging.\r
*\r
*******************************************************************************/\r
void CyHalt(uint8 reason) CYREENTRANT\r
\r
/*******************************************************************************\r
* Function Name: CySoftwareReset\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Forces a device software reset.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CySoftwareReset(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyDelay\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Blocks for milliseconds.\r
*\r
* Note:\r
* For example, with instruction cache disabled CyDelay(100) would result in\r
* about 200 ms delay instead of 100 ms.\r
*\r
-* Parameters:\r
-* milliseconds: number of milliseconds to delay.\r
-*\r
-* Return:\r
-* None\r
+* \param milliseconds: number of milliseconds to delay.\r
*\r
*******************************************************************************/\r
void CyDelay(uint32 milliseconds) CYREENTRANT\r
\r
/*******************************************************************************\r
* Function Name: CyDelayUs\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Blocks for microseconds.\r
*\r
* Note:\r
* larger. Ex: With instruction cache disabled CyDelayUs(100) would result\r
* in about 200us delay instead of 100us.\r
*\r
- * Parameters:\r
- * uint16 microseconds: number of microseconds to delay.\r
- *\r
- * Return:\r
- * None\r
+ * \param uint16 microseconds: number of microseconds to delay.\r
*\r
- * Side Effects:\r
+ * \sideeffect\r
* CyDelayUS has been implemented with the instruction cache assumed enabled.\r
* When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times\r
* larger. For example, with the instruction cache disabled CyDelayUs(100) would\r
\r
/*******************************************************************************\r
* Function Name: CyDelayFreq\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the clock frequency for CyDelay.\r
*\r
-* Parameters:\r
-* freq: The frequency of the bus clock in Hertz.\r
-*\r
-* Return:\r
-* None\r
+* \param freq: The frequency of the bus clock in Hertz.\r
*\r
*******************************************************************************/\r
void CyDelayFreq(uint32 freq) CYREENTRANT\r
\r
/*******************************************************************************\r
* Function Name: CyWdtStart\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the watchdog timer.\r
*\r
* The timer is configured for the specified count interval, the central\r
-* timewheel is cleared, the setting for the low power mode is configured and the\r
-* watchdog timer is enabled.\r
+* timewheel is cleared, the setting for the low power mode is configured and\r
+* the watchdog timer is enabled.\r
*\r
* Once enabled the watchdog cannot be disabled. The watchdog counts each time\r
* the Central Time Wheel (CTW) reaches the period specified. The watchdog must\r
* set to be greater than the sleep wakeup period, then feed the dog on each\r
* wakeup from Sleep.\r
*\r
-* Parameters:\r
-* ticks: One of the four available timer periods. Once WDT enabled, the\r
+* \param ticks: One of the four available timer periods. Once WDT enabled, the\r
interval cannot be changed.\r
* CYWDT_2_TICKS - 4 - 6 ms\r
* CYWDT_16_TICKS - 32 - 48 ms\r
* CYWDT_128_TICKS - 256 - 384 ms\r
* CYWDT_1024_TICKS - 2.048 - 3.072 s\r
*\r
-* lpMode: Low power mode configuration. This parameter is ignored for PSoC 5.\r
+* \param lpMode: Low power mode configuration. This parameter is ignored for PSoC 5.\r
* The WDT always acts as if CYWDT_LPMODE_NOCHANGE is passed.\r
*\r
* CYWDT_LPMODE_NOCHANGE - No Change\r
* mode\r
* CYWDT_LPMODE_DISABLED - Disable WDT during low power mode\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* PSoC5: The ILO 1 KHz must be enabled for proper WDT operation. Stopping the\r
* ILO 1 kHz could break the active WDT functionality.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyWdtClear\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Clears (feeds) the watchdog timer.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyWdtClear(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyVdLvDigitEnable\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Enables the digital low voltage monitors to generate interrupt on Vddd\r
-* archives specified threshold and optionally resets the device.\r
+* Sets the voltage trip level, enables the output of the digital low-voltage\r
+* monitor, and optionally configures voltage monitor to reset device upon the\r
+* low-voltage event instead of generating an interrupt.\r
*\r
-* Parameters:\r
-* reset: The option to reset the device at a specified Vddd threshold:\r
-* 0 - Device is not reset.\r
-* 1 - Device is reset.\r
+* Note The associated interrupt enable/disable state is not changed by the\r
+* function. The Interrupt component API should be used to register the\r
+* interrupt service routine and to enable/disable associated interrupt.\r
*\r
-* threshold: Sets the trip level for the voltage monitor.\r
-* Values from 1.70 V to 5.45 V are accepted with an interval of approximately\r
-* 250 mV.\r
+* \param reset: Enables device reset on digital low-voltage event:\r
+* Zero - Interrupt on digital low-voltage event\r
+* Non-zero - Reset on digital low-voltage event\r
*\r
-* Return:\r
-* None\r
+* \param threshold: Sets the trip point of the digital low-voltage monitoring circuit\r
+* in steps of approximately 250 mV in range from 1.70 V (0x00) to 5.45 V\r
+* (0x0F). For example, the trip point is set to 1.80 V when the threshold\r
+* parameter value is 0x04. Refer to the device TRM for the exact trip voltage\r
+* values.\r
+*\r
+* Side Effects and Restrictions:\r
+* The voltage resets are momentary. When a voltage reset (analog/digital\r
+* low-voltage and analog high-voltage) occurs, the RESET_CR1 and RESET_CR3\r
+* registers are restored to their default values. This means that the voltage\r
+* monitor circuit is no longer enabled and the device exits reset. If the\r
+* supply is below the trip level and firmware enables the voltage reset\r
+* functionality, the device will reset again. This will continue as long as the\r
+* supply is below the trip level or as long as the user enables the reset\r
+* functionality of the voltage monitor functionality.\r
+*\r
+* When any voltage reset occurs, the RESET_SR0 and RESET_SR2 status registers\r
+* are cleared. This means that analog low-voltage, digital low-voltage and\r
+* analog high-voltage status bits are not persistent across any voltage reset.\r
*\r
*******************************************************************************/\r
void CyVdLvDigitEnable(uint8 reset, uint8 threshold) \r
{\r
- *CY_INT_CLEAR_PTR = 0x01u;\r
+ uint32 intRegTmp;\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ /* Store interrupt enable state */\r
+ intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK;\r
+\r
+ /* Disable VD interrupt (write 1) to protect against glitches */\r
+ CY_INT_CLEAR_REG = CY_VD_INT_MASK;\r
\r
CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));\r
\r
(CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK)));\r
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN;\r
\r
- /* Timeout to eliminate glitches on LVI/HVI when enabling */\r
+ /* Timeout to eliminate glitches on LVI/HVI when enabling (ID # 127412) */\r
CyDelayUs(1u);\r
\r
- (void)CY_VD_PERSISTENT_STATUS_REG;\r
+ (void) CyVdStickyStatus(CY_VD_LVID);\r
\r
if(0u != reset)\r
{\r
CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));\r
}\r
\r
- *CY_INT_CLR_PEND_PTR = 0x01u;\r
- *CY_INT_ENABLE_PTR = 0x01u;\r
+ /* Clear pending interrupt */\r
+ CY_INT_CLR_PEND_REG = CY_VD_INT_MASK;\r
+\r
+ /* Restore interrupt enable state */\r
+ CY_INT_ENABLE_REG = intRegTmp;\r
+\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: CyVdLvAnalogEnable\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Enables the analog low voltage monitors to generate interrupt on Vdda\r
-* archives specified threshold and optionally resets the device.\r
+* Sets the voltage trip level, enables the output of the analog low-voltage\r
+* monitor, and optionally configures voltage monitor to reset device upon the\r
+* low-voltage event instead of generating an interrupt.\r
*\r
-* Parameters:\r
-* reset: The option to reset the device at a specified Vdda threshold:\r
-* 0 - Device is not reset.\r
-* 1 - Device is reset.\r
+* Note The associated interrupt enable/disable state is not changed by the\r
+* function. The Interrupt component API should be used to register the\r
+* interrupt service routine and to enable/disable associated interrupt.\r
*\r
-* threshold: Sets the trip level for the voltage monitor.\r
-* Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV\r
-* interval.\r
+* \param reset: Enables device reset on analog low-voltage event:\r
+* Zero - Interrupt on analog low-voltage event\r
+* Non-zero - Reset on analog low-voltage event\r
*\r
-* Return:\r
-* None\r
+* \param threshold: Sets the trip point of the analog low-voltage monitoring circuit\r
+* in steps of approximately 250 mV in range from 1.70 V (0x00) to 5.45 V\r
+* (0x0F). For example, the trip point is set to 1.80 V when value of the\r
+* threshold parameter is 0x04. Please refer to the device TRM for the exact\r
+* trip voltage values.\r
+*\r
+* Side Effects and Restrictions:\r
+* The voltage resets are momentary. When a voltage reset (analog/digital\r
+* low-voltage and analog high-voltage) occurs, the RESET_CR1 and RESET_CR3\r
+* registers are restored to their default values. This means that the voltage\r
+* monitor circuit is no longer enabled and the device exits reset. If the\r
+* supply is below the trip level and firmware enables the voltage reset\r
+* functionality, the device will reset again. This will continue as long as\r
+* the supply is below the trip level or as long as the user enables the reset\r
+* functionality of the voltage monitor functionality.\r
+*\r
+* When any voltage reset occurs, the RESET_SR0 and RESET_SR2 status registers\r
+* are cleared. This means that analog low-voltage, digital low-voltage and\r
+* analog high-voltage status bits are not persistent across any voltage reset.\r
*\r
*******************************************************************************/\r
void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) \r
{\r
- *CY_INT_CLEAR_PTR = 0x01u;\r
+ uint32 intRegTmp;\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ /* Store interrupt enable state */\r
+ intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK;\r
+\r
+ /* Disable VD interrupt (write 1) to protect against glitches */\r
+ CY_INT_CLEAR_REG = CY_VD_INT_MASK;\r
\r
CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
\r
CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu);\r
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN;\r
\r
- /* Timeout to eliminate glitches on LVI/HVI when enabling */\r
+ /* Timeout to eliminate glitches on LVI/HVI when enabling (ID # 127412) */\r
CyDelayUs(1u);\r
\r
- (void)CY_VD_PERSISTENT_STATUS_REG;\r
+ (void) CyVdStickyStatus(CY_VD_LVIA);\r
\r
if(0u != reset)\r
{\r
CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
}\r
\r
- *CY_INT_CLR_PEND_PTR = 0x01u;\r
- *CY_INT_ENABLE_PTR = 0x01u;\r
+ /* Clear pending interrupt */\r
+ CY_INT_CLR_PEND_REG = CY_VD_INT_MASK;\r
+\r
+ /* Restore interrupt enable state */\r
+ CY_INT_ENABLE_REG = intRegTmp;\r
+\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: CyVdLvDigitDisable\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Disables the digital low voltage monitor (interrupt and device reset are\r
-* disabled).\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None\r
+* Disables the digital low-voltage monitor, turns off device reset upon the\r
+* digital low-voltage event, and clears the associated persistent status bit.\r
*\r
-* Return:\r
-* None\r
+* Note The associated interrupt enable/disable state is not changed by the\r
+* function. The pending interrupt status is not cleared. The Interrupt\r
+* component API should be used to manipulate with the associated interrupts.\r
*\r
*******************************************************************************/\r
void CyVdLvDigitDisable(void) \r
{\r
CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVID_EN));\r
-\r
CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));\r
+ (void) CyVdStickyStatus(CY_VD_LVID);\r
\r
- while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u))\r
+ while(0u != (CyVdStickyStatus(CY_VD_LVID) & CY_VD_LVID))\r
{\r
\r
}\r
\r
/*******************************************************************************\r
* Function Name: CyVdLvAnalogDisable\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Disables the analog low voltage monitor (interrupt and device reset are\r
-* disabled).\r
+* Disables the analog low-voltage monitor, turns off device reset upon the\r
+* analog low-voltage event, and clears the associated persistent status bit.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
+* Note The associated interrupt enable/disable state is not changed by the\r
+* function. The pending interrupt status is not cleared. The Interrupt\r
+* component API should be used to manipulate with the associated interrupts.\r
*\r
*******************************************************************************/\r
void CyVdLvAnalogDisable(void) \r
{\r
CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVIA_EN));\r
-\r
CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
-\r
- while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u))\r
+ while(0u != (CyVdStickyStatus(CY_VD_LVIA) & CY_VD_LVIA))\r
{\r
\r
}\r
\r
/*******************************************************************************\r
* Function Name: CyVdHvAnalogEnable\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Enables the analog high voltage monitors to generate interrupt on\r
-* Vdda archives 5.75 V threshold and optionally resets device.\r
+* Enables the output of the analog high-voltage monitor and sets 5.75 V\r
+* threshold detection for Vdda.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
+* Note The associated interrupt enable/disable state is not changed by the\r
+* function. The Interrupt component API should be used to register the\r
+* interrupt service routine and to enable/disable associated interrupt.\r
*\r
*******************************************************************************/\r
void CyVdHvAnalogEnable(void) \r
{\r
- *CY_INT_CLEAR_PTR = 0x01u;\r
+ uint32 intRegTmp;\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ /* Store interrupt enable state */\r
+ intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK;\r
+\r
+ /* Disable VD interrupt (write 1) to protect against glitches */\r
+ CY_INT_CLEAR_REG = CY_VD_INT_MASK;\r
\r
CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
\r
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_HVIA_EN;\r
\r
- /* Timeout to eliminate glitches on the LVI/HVI when enabling */\r
+ /* Timeout to eliminate glitches on the LVI/HVI when enabling (ID # 127412) */\r
CyDelayUs(1u);\r
\r
- (void) CY_VD_PERSISTENT_STATUS_REG;\r
+ (void) CyVdStickyStatus(CY_VD_HVIA);\r
+\r
+ /* Clear pending interrupt */\r
+ CY_INT_CLR_PEND_REG = CY_VD_INT_MASK;\r
+\r
+ /* Restore interrupt enable state */\r
+ CY_INT_ENABLE_REG = intRegTmp;\r
\r
- *CY_INT_CLR_PEND_PTR = 0x01u;\r
- *CY_INT_ENABLE_PTR = 0x01u;\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: CyVdHvAnalogDisable\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Disables the analog low voltage monitor\r
-* (interrupt and device reset are disabled).\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None\r
+* Disables the analog high-voltage monitor and clears the associated persistent\r
+* status bit.\r
*\r
-* Return:\r
-* None\r
+* Note The associated interrupt enable/disable state is not changed by the\r
+* function. The pending interrupt status is not cleared. The Interrupt\r
+* component API should be used to manipulate with the associated interrupts.\r
*\r
*******************************************************************************/\r
void CyVdHvAnalogDisable(void) \r
{\r
CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_HVIA_EN));\r
+ while(0u != (CyVdStickyStatus(CY_VD_HVIA) & CY_VD_HVIA))\r
+ {\r
+\r
+ }\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: CyVdStickyStatus\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Manages the Reset and Voltage Detection Status Register 0.\r
-* This register has the interrupt status for the HVIA, LVID and LVIA.\r
-* This hardware register clears on read.\r
+* Reads and clears the voltage detection status bits in the RESET_SR0 register.\r
+* The bits are set to 1 by the voltage monitor circuit when the supply is\r
+* outside the detector trip point. They stay set to 1 until they are read or\r
+* a POR / LVI / PRES reset occurs. This function uses a shadow register, so\r
+* only the bits passed in the parameter will be cleared in the shadow register.\r
*\r
-* Parameters:\r
-* mask: Bits in the shadow register to clear.\r
+* \param mask: Bits in the RESET_SR0 shadow register to clear and return.\r
* Define Definition\r
* CY_VD_LVID Persistent status of digital LVI.\r
* CY_VD_LVIA Persistent status of analog LVI.\r
* CY_VD_HVIA Persistent status of analog HVI.\r
*\r
-* Return:\r
-* Status. Same enumerated bit values as used for the mask parameter.\r
+* \return\r
+* Status. Same enumerated bit values as used for the mask parameter. A zero is\r
+* returned for bits not used in the mask parameter.\r
+*\r
+* Side Effects and Restrictions:\r
+* When an LVI reset occurs, the RESET_SR0 status registers are cleared. This\r
+* means that the voltage detection status bits are not persistent across an LVI\r
+* reset and cannot be used to determine a reset source.\r
*\r
*******************************************************************************/\r
uint8 CyVdStickyStatus(uint8 mask) \r
{\r
- uint8 status;\r
+ static uint8 interruptStatus;\r
+ uint8 interruptState;\r
+ uint8 tmpStatus;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
\r
- status = CY_VD_PERSISTENT_STATUS_REG;\r
- CY_VD_PERSISTENT_STATUS_REG &= ((uint8)(~mask));\r
+ interruptStatus |= CY_VD_PERSISTENT_STATUS_REG;\r
+ tmpStatus = interruptStatus & (uint8)(CY_VD_LVID | CY_VD_LVIA | CY_VD_HVIA);\r
+ interruptStatus &= ((uint8)(~mask));\r
\r
- return(status);\r
+ CyExitCriticalSection(interruptState);\r
+\r
+ return(tmpStatus);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: CyVdRealTimeStatus\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Returns the real time voltage detection status.\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None\r
+* Reads the real-time voltage detection status bits in the RESET_SR2 register.\r
+* The bits are set to 1 by the voltage monitor circuit when the supply is\r
+* outside the detector’s trip point, and set to 0 when the supply is inside the\r
+* trip point.\r
*\r
-* Return:\r
-* Status:\r
+* \return\r
+* Status of the LVID, LVIA, and HVIA bits in the RESET_SR2 register.\r
* Define Definition\r
-* CY_VD_LVID Persistent status of digital LVI.\r
-* CY_VD_LVIA Persistent status of analog LVI.\r
-* CY_VD_HVIA Persistent status of analog HVI.\r
+* CY_VD_LVID Real-time status of digital LVI.\r
+* CY_VD_LVIA Real-time status of analog LVI.\r
+* CY_VD_HVIA Real-time status of analog HVI.\r
+*\r
+* Side Effects and Restrictions:\r
+* When an LVI reset occurs, the RESET_SR2 status registers are cleared. This\r
+* means that the voltage detection status bits are not persistent across an LVI\r
+* reset and cannot be used to determine a reset source.\r
*\r
*******************************************************************************/\r
uint8 CyVdRealTimeStatus(void) \r
uint8 vdFlagsState;\r
\r
interruptState = CyEnterCriticalSection();\r
- vdFlagsState = CY_VD_RT_STATUS_REG;\r
+ vdFlagsState = CY_VD_RT_STATUS_REG & (CY_VD_LVID | CY_VD_LVIA | CY_VD_HVIA);\r
CyExitCriticalSection(interruptState);\r
\r
return(vdFlagsState);\r
\r
/*******************************************************************************\r
* Function Name: CyDisableInts\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the interrupt enable for each interrupt.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* 32 bit mask of previously enabled interrupts.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyEnableInts\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables interrupts to a given state.\r
*\r
-* Parameters:\r
-* uint32 mask: 32 bit mask of interrupts to enable.\r
-*\r
-* Return:\r
-* None\r
+* \param uint32 mask: 32 bit mask of interrupts to enable.\r
*\r
*******************************************************************************/\r
void CyEnableInts(uint32 mask) \r
\r
/*******************************************************************************\r
* Function Name: CyFlushCache\r
- ********************************************************************************\r
- * Summary:\r
- * Flushes the PSoC 5/5LP cache by invalidating all entries.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
+ ****************************************************************************//**\r
+ * Call this API after a flash row erase/write operation to invalidate or flush\r
+ * any of that particular flash region content already present in the cache.\r
+ * After a cache flush operation, any access to that flash region after the\r
+ * erase/write operation would reload the cache with the modified data from the\r
+ * flash region. If the flash region update involves multiple flash row write\r
+ * operations, then the flushing of the cache can be done once at the end of\r
+ * the operation as long as the flash data would not be accessed in the middle\r
+ * of the multiple row update process. Else, flush the cache after every flash\r
+ * row write.\r
*\r
*******************************************************************************/\r
void CyFlushCache(void)\r
\r
/*******************************************************************************\r
* Function Name: CyIntSetSysVector\r
- ********************************************************************************\r
- * Summary:\r
+ ****************************************************************************//**\r
* Sets the interrupt vector of the specified system interrupt number. System\r
* interrupts are present only for the ARM platform. These interrupts are for\r
* SysTick, PendSV and others.\r
*\r
- * Parameters:\r
- * number: System interrupt number:\r
+ * \param number: System interrupt number:\r
* CY_INT_NMI_IRQN - Non Maskable Interrupt\r
* CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt\r
* CY_INT_MEM_MANAGE_IRQN - Memory Management Interrupt\r
* CY_INT_PEND_SV_IRQN - Pend SV Interrupt\r
* CY_INT_SYSTICK_IRQN - System Tick Interrupt\r
*\r
- * address: Pointer to an interrupt service routine.\r
+ * \param address: Pointer to an interrupt service routine.\r
*\r
- * Return:\r
+ * \return\r
* The old ISR vector at this location.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyIntGetSysVector\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Gets the interrupt vector of the specified system interrupt number. System\r
* interrupts are present only for the ARM platform. These interrupts are for\r
* SysTick, PendSV and others.\r
*\r
- * Parameters:\r
- * number: System interrupt number:\r
+ * \param number: System interrupt number:\r
* CY_INT_NMI_IRQN - Non Maskable Interrupt\r
* CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt\r
* CY_INT_MEMORY_MANAGEMENT_IRQN - Memory Management Interrupt\r
* CY_INT_PEND_SV_IRQN - Pend SV Interrupt\r
* CY_INT_SYSTICK_IRQN - System Tick Interrupt\r
*\r
- * Return:\r
+ * \return\r
* Address of the ISR in the interrupt vector table.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyIntSetVector\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Sets the interrupt vector of the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number\r
- * address: Pointer to an interrupt service routine\r
+ * \param number: Valid range [0-31]. Interrupt number\r
+ * \param address: Pointer to an interrupt service routine\r
*\r
- * Return:\r
+ * \return\r
* Previous interrupt vector value.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyIntGetVector\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Gets the interrupt vector of the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number\r
+ * \param number: Valid range [0-31]. Interrupt number\r
*\r
- * Return:\r
+ * \return\r
* The address of the ISR in the interrupt vector table.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyIntSetPriority\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Sets the Priority of the Interrupt.\r
*\r
- * Parameters:\r
- * priority: Priority of the interrupt. 0 - 7, 0 being the highest.\r
- * number: The number of the interrupt, 0 - 31.\r
- *\r
- * Return:\r
- * None\r
+ * \param priority: Priority of the interrupt. 0 - 7, 0 being the highest.\r
+ * \param number: The number of the interrupt, 0 - 31.\r
*\r
*******************************************************************************/\r
void CyIntSetPriority(uint8 number, uint8 priority)\r
\r
/*******************************************************************************\r
* Function Name: CyIntGetPriority\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Gets the Priority of the Interrupt.\r
*\r
- * Parameters:\r
- * number: The number of the interrupt, 0 - 31.\r
+ * \param number: The number of the interrupt, 0 - 31.\r
*\r
- * Return:\r
+ * \return\r
* Priority of the interrupt. 0 - 7, 0 being the highest.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyIntGetState\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Gets the enable state of the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number.\r
+ * \param number: Valid range [0-31]. Interrupt number.\r
*\r
- * Return:\r
+ * \return\r
* Enable status: 1 if enabled, 0 if disabled\r
*\r
*******************************************************************************/\r
\r
#else /* PSoC3 */\r
\r
+ /*******************************************************************************\r
+ * Function Name: IntDefaultHandler\r
+ ****************************************************************************//**\r
+ *\r
+ * This function is called for all interrupts, other than a reset that gets\r
+ * called before the system is setup.\r
+ *\r
+ * Theory:\r
+ * Any value other than zero is acceptable.\r
+ *\r
+ *******************************************************************************/\r
+ CY_ISR(IntDefaultHandler)\r
+ {\r
+ #ifdef CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK\r
+ CyBoot_IntDefaultHandler_Exception_EntryCallback();\r
+ #endif /* CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK */\r
+\r
+ while(1)\r
+ {\r
+ /***********************************************************************\r
+ * We must not get here. If we do, a serious problem occurs, so go\r
+ * into an infinite loop.\r
+ ***********************************************************************/\r
+ }\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: IntDefaultHandler\r
+ ****************************************************************************//**\r
+ *\r
+ * This function is called during startup to initialize interrupt address vector\r
+ * registers with the address of the IntDefaultHandler().\r
+ *\r
+ *******************************************************************************/\r
+ void CyIntInitVectors(void) \r
+ {\r
+ uint8 i;\r
+\r
+ for (i = 0; i <= CY_INT_NUMBER_MAX; i++)\r
+ {\r
+ CY_SET_REG16(&CY_INT_VECT_TABLE[i], (uint16) &IntDefaultHandler);\r
+ }\r
+ }\r
+\r
\r
/*******************************************************************************\r
* Function Name: CyIntSetVector\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Sets the interrupt vector of the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number\r
- * address: Pointer to an interrupt service routine\r
+ * \param number: Valid range [0-31]. Interrupt number\r
+ * \param address: Pointer to an interrupt service routine\r
*\r
- * Return:\r
+ * \return\r
* Previous interrupt vector value.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyIntGetVector\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Gets the interrupt vector of the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number\r
+ * \param number: Valid range [0-31]. Interrupt number\r
*\r
- * Return:\r
+ * \return\r
* Address of the ISR in the interrupt vector table.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyIntSetPriority\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Sets the Priority of the Interrupt.\r
*\r
- * Parameters:\r
- * priority: Priority of the interrupt. 0 - 7, 0 being the highest.\r
- * number: The number of the interrupt, 0 - 31.\r
- *\r
- * Return:\r
- * None\r
+ * \param priority: Priority of the interrupt. 0 - 7, 0 being the highest.\r
+ * \param number: The number of the interrupt, 0 - 31.\r
*\r
*******************************************************************************/\r
void CyIntSetPriority(uint8 number, uint8 priority) \r
\r
/*******************************************************************************\r
* Function Name: CyIntGetPriority\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Gets the Priority of the Interrupt.\r
*\r
- * Parameters:\r
- * number: The number of the interrupt, 0 - 31.\r
+ * \param number: The number of the interrupt, 0 - 31.\r
*\r
- * Return:\r
+ * \return\r
* Priority of the interrupt. 0 - 7, 0 being the highest.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyIntGetState\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Gets the enable state of the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number.\r
+ * \param number: Valid range [0-31]. Interrupt number.\r
*\r
- * Return:\r
+ * \return\r
* Enable status: 1 if enabled, 0 if disabled\r
*\r
*******************************************************************************/\r
return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u)));\r
}\r
\r
-\r
#endif /* (CY_PSOC5) */\r
\r
\r
\r
/*******************************************************************************\r
* Function Name: CySetScPumps\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* If 1 is passed as a parameter:\r
* - if any of the SC blocks are used - enable pumps for the SC blocks and\r
* start boost clock.\r
* If non-1 value is passed as a parameter:\r
* - If all SC blocks are not used - disable pumps for the SC blocks and\r
* stop the boost clock.\r
- * - For each enabled SC block clear the boost clock index and disable the boost\r
- * clock.\r
+ * - For each enabled SC block clear the boost clock index and disable the\r
+ * boost clock.\r
*\r
* The global variable CyScPumpEnabled is updated to be equal to passed the\r
* parameter.\r
*\r
- * Parameters:\r
- * uint8 enable: Enable/disable SC pumps and the boost clock for the enabled SC block.\r
+ * \param uint8 enable: Enable/disable SC pumps and the boost clock for the enabled\r
+ * \param SC block:\r
* 1 - Enable\r
* 0 - Disable\r
*\r
- * Return:\r
- * None\r
- *\r
*******************************************************************************/\r
void CySetScPumps(uint8 enable) \r
{\r
#if(CY_PSOC5)\r
/*******************************************************************************\r
* Function Name: CySysTickStart\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Configures the SysTick timer to generate interrupt every 1 ms by call to the\r
* CySysTickInit() function and starts it by calling CySysTickEnable() function.\r
* Refer to the corresponding function description for the details.\r
\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Side Effects:\r
+ * \sideeffect\r
* Clears SysTick count flag if it was set\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CySysTickInit\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Initializes the callback addresses with pointers to NULL, associates the\r
* SysTick system vector with the function that is responsible for calling\r
* registered callback functions, configures SysTick timer to generate interrupt\r
* every 1 ms.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Side Effects:\r
+ * \sideeffect\r
* Clears SysTick count flag if it was set.\r
*\r
* The 1 ms interrupt interval is configured based on the frequency determined\r
CySysTickCallbacks[i] = (void *) 0;\r
}\r
\r
- (void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks);\r
+ (void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks);\r
CySysTickSetClockSource(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK);\r
CySysTickSetReload(cydelay_freq_hz/1000u);\r
CySysTickClear();\r
\r
/*******************************************************************************\r
* Function Name: CySysTickEnable\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Enables the SysTick timer and its interrupt.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Side Effects:\r
+ * \sideeffect\r
* Clears SysTick count flag if it was set\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CySysTickStop\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Stops the system timer (SysTick).\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Side Effects:\r
+ * \sideeffect\r
* Clears SysTick count flag if it was set\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CySysTickEnableInterrupt\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Enables the SysTick interrupt.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Side Effects:\r
+ * \sideeffect\r
* Clears SysTick count flag if it was set\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CySysTickDisableInterrupt\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Disables the SysTick interrupt.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Side Effects:\r
+ * \sideeffect\r
* Clears SysTick count flag if it was set\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CySysTickSetReload\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Sets value the counter is set to on startup and after it reaches zero. This\r
* function do not change or reset current sysTick counter value, so it should\r
* be cleared using CySysTickClear() API.\r
*\r
- * Parameters:\r
- * value: Valid range [0x0-0x00FFFFFF]. Counter reset value.\r
- *\r
- * Return:\r
- * None\r
+ * \param value: Valid range [0x0-0x00FFFFFF]. Counter reset value.\r
*\r
*******************************************************************************/\r
void CySysTickSetReload(uint32 value)\r
\r
/*******************************************************************************\r
* Function Name: CySysTickGetReload\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Sets value the counter is set to on startup and after it reaches zero.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
+ * \return\r
* Counter reset value\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CySysTickGetValue\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Gets current SysTick counter value.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
+ * \return\r
* Current SysTick counter value\r
*\r
*******************************************************************************/\r
uint32 CySysTickGetValue(void)\r
{\r
- return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_CVR_REG);\r
+ return(CY_SYS_SYST_CVR_REG & CY_SYS_SYST_CVR_CNT_MASK);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: CySysTickSetClockSource\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Sets the clock source for the SysTick counter.\r
*\r
- * Parameters:\r
- * clockSource: Clock source for SysTick counter\r
+ * \param clockSource: Clock source for SysTick counter\r
* Define Clock Source\r
* CY_SYS_SYST_CSR_CLK_SRC_SYSCLK SysTick is clocked by CPU clock.\r
* CY_SYS_SYST_CSR_CLK_SRC_LFCLK SysTick is clocked by the low frequency\r
- * clock (ILO 100 KHz for PSoC 5LP, LFCLK for PSoC 4).\r
- *\r
- * Return:\r
- * None\r
+ * clock (ILO 100 KHz for PSoC 5LP, and\r
+ * LFCLK for PSoC 4).\r
*\r
- * Side Effects:\r
+ * \sideeffect\r
* Clears SysTick count flag if it was set. If clock source is not ready this\r
- * function call will have no effect. After changing clock source to the low frequency\r
- * clock the counter and reload register values will remain unchanged so time to\r
- * the interrupt will be significantly bigger and vice versa.\r
+ * function call will have no effect. After changing clock source to the low\r
+ * frequency clock the counter and reload register values will remain unchanged\r
+ * so time to the interrupt will be significantly bigger and vice versa.\r
*\r
*******************************************************************************/\r
void CySysTickSetClockSource(uint32 clockSource)\r
}\r
else\r
{\r
- CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT));\r
+ CY_SYS_SYST_CSR_REG &= ((uint32) ~((uint32)(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT)));\r
}\r
}\r
\r
+ \r
+ /*******************************************************************************\r
+ * Function Name: CySysTickGetClockSource\r
+ ****************************************************************************//**\r
+ *\r
+ * Returns the current clock source of the SysTick counter.\r
+ *\r
+ * \return \r
+ * CY_SYS_SYST_CSR_CLK_SRC_SYSCLK SysTick is clocked by CPU clock.\r
+ * CY_SYS_SYST_CSR_CLK_SRC_LFCLK SysTick is clocked by the low frequency\r
+ * clock. (ILO 100 KHz for PSoC 5LP, and\r
+ * LFCLK for PSoC 4).\r
+ *******************************************************************************/\r
+ uint32 CySysTickGetClockSource(void)\r
+ {\r
+ return ((CY_SYS_SYST_CSR_REG >> CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT) & CY_SYS_SYST_CSR_CLK_SRC_SYSCLK );\r
+ }\r
\r
+ \r
/*******************************************************************************\r
* Function Name: CySysTickGetCountFlag\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* The count flag is set once SysTick counter reaches zero.\r
* The flag cleared on read.\r
*\r
- * Parameters:\r
- * None\r
+ * \return\r
+ * Returns non-zero value if flag is set, otherwise zero is returned.\r
*\r
- * Return:\r
- * Returns non-zero value if counter is set, otherwise zero is returned.\r
+ *\r
+ * \sideeffect\r
+ * Clears SysTick count flag if it was set.\r
*\r
*******************************************************************************/\r
uint32 CySysTickGetCountFlag(void)\r
{\r
- return ((CY_SYS_SYST_CSR_REG>>CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u);\r
+ return ((CY_SYS_SYST_CSR_REG >> CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: CySysTickClear\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Clears the SysTick counter for well-defined startup.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
*******************************************************************************/\r
void CySysTickClear(void)\r
{\r
\r
/*******************************************************************************\r
* Function Name: CySysTickSetCallback\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
+ *\r
+ * This function allows up to five user-defined interrupt service routine\r
+ * functions to be associated with the SysTick interrupt. These are specified\r
+ * through the use of pointers to the function.\r
+ *\r
+ * To set a custom callback function without the overhead of the system provided\r
+ * one, use CyIntSetSysVector(CY_INT_SYSTICK_IRQN, cyisraddress <address>),\r
+ * where <address> is address of the custom defined interrupt service routine.\r
+ * Note: a custom callback function overrides the system defined callback\r
+ * functions.\r
*\r
- * Summary:\r
- * The function set the pointers to the functions that will be called on\r
- * SysTick interrupt.\r
+ * \param number: The number of the callback function addresses to be set. The valid\r
+ * range is from 0 to 4.\r
*\r
- * Parameters:\r
- * number: The number of callback function address to be set.\r
- * The valid range is from 0 to 4.\r
- * CallbackFunction: Function address.\r
+ * void(*CallbackFunction(void): A pointer to the function that will be\r
+ * associated with the SysTick ISR for the\r
+ * specified number.\r
*\r
- * Return:\r
+ * \return\r
* Returns the address of the previous callback function.\r
* The NULL is returned if the specified address in not set.\r
*\r
+ * \sideeffect\r
+ * The registered callback functions will be executed in the interrupt.\r
+ *\r
*******************************************************************************/\r
cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function)\r
{\r
\r
/*******************************************************************************\r
* Function Name: CySysTickGetCallback\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* The function get the specified callback pointer.\r
*\r
- * Parameters:\r
- * None\r
+ * \param number: The number of callback function address to get. The valid\r
+ * range is from 0 to 4.\r
*\r
- * Return:\r
- * None\r
+ * \return\r
+ * Returns the address of the specified callback function.\r
+ * The NULL is returned if the specified address in not initialized.\r
*\r
*******************************************************************************/\r
cySysTickCallback CySysTickGetCallback(uint32 number)\r
\r
/*******************************************************************************\r
* Function Name: CySysTickServiceCallbacks\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* System Tick timer interrupt routine\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
*******************************************************************************/\r
static void CySysTickServiceCallbacks(void)\r
{\r
#endif /* (CY_PSOC5) */\r
\r
\r
+/*******************************************************************************\r
+* Function Name: CyGetUniqueId\r
+****************************************************************************//**\r
+*\r
+* Returns the 64-bit unique ID of the device. The uniqueness of the number is\r
+* guaranteed for 10 years due to the die lot number having a cycle life of 10\r
+* years and even after 10 years, the probability of getting two identical\r
+* numbers is very small.\r
+*\r
+* \param uniqueId: The pointer to a two element 32-bit unsigned integer array. Returns\r
+* the 64-bit unique ID of the device by loading them into the integer array\r
+* pointed to by uniqueId.\r
+*\r
+*******************************************************************************/\r
+void CyGetUniqueId(uint32* uniqueId)\r
+{\r
+#if(CY_PSOC4)\r
+ uniqueId[0u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT0 );\r
+ uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT1 ) << 8u);\r
+ uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT2 ) << 16u);\r
+ uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_WAFER ) << 24u);\r
+\r
+ uniqueId[1u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_X );\r
+ uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_Y ) << 8u);\r
+ uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_SORT ) << 16u);\r
+ uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_MINOR ) << 24u);\r
+#else\r
+ uniqueId[0u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_LSB ));\r
+ uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_MSB )) << 8u);\r
+ uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_MLOGIC_REV_ID )) << 16u);\r
+ uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WAFER_NUM )) << 24u);\r
+\r
+ uniqueId[1u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_X_LOC ));\r
+ uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_Y_LOC )) << 8u);\r
+ uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WRK_WK )) << 16u);\r
+ uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_FAB_YR )) << 24u);\r
+#endif /* (CY_PSOC4) */\r
+}\r
+\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: CyLib.h\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file CyLib.h\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides the function definitions for the system, clocking, interrupts and\r
-* watchdog timer API.\r
+* \brief Provides the function definitions for the system, clocking, interrupts\r
+* and watchdog timer API.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the System Reference\r
-* Guide provided with PSoC Creator.\r
+* \note Documentation of the API's in this file is located in the System\r
+* Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#endif /* (CY_PSOC5) */\r
\r
#if(CY_PSOC5)\r
- /* System tick timer APIs */\r
+ /** System tick timer APIs */\r
typedef void (*cySysTickCallback)(void);\r
\r
void CySysTickStart(void);\r
void CySysTickClear(void);\r
#endif /* (CY_PSOC5) */\r
\r
+void CyGetUniqueId(uint32* uniqueId);\r
+\r
+\r
/***************************************\r
* API Constants\r
***************************************/\r
#define CY_VD_HVIA (0x04u)\r
\r
#define CY_VD_LVI_TRIP_LVID_MASK (0x0Fu)\r
+#define CY_VD_INT_MASK ((uint32) (0x01u))\r
\r
\r
/*******************************************************************************\r
#if defined(__ARMCC_VERSION)\r
#define CY_SYS_ISB __isb(0x0f)\r
#else /* ASM for GCC & IAR */\r
- #define CY_SYS_ISB asm volatile ("isb \n")\r
+ #define CY_SYS_ISB __asm volatile ("isb \n")\r
#endif /* (__ARMCC_VERSION) */\r
\r
#endif /* (CY_PSOC5) */\r
\r
/*******************************************************************************\r
* Macro Name: CyAssert\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* The macro that evaluates the expression and if it is false (evaluates to 0)\r
* then the processor is halted.\r
*\r
* defined by default for a Release build setting and not defined for a Debug\r
* build setting.\r
*\r
-* Parameters:\r
-* expr: Logical expression. Asserts if false.\r
-*\r
-* Return:\r
-* None\r
+* \param expr: Logical expression. Asserts if false.\r
*\r
*******************************************************************************/\r
#if !defined(NDEBUG)\r
#define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ((uint32) (1u))\r
#define CY_SYS_SYST_CSR_CLK_SRC_LFCLK ((uint32) (0u))\r
#define CY_SYS_SYST_RVR_CNT_MASK ((uint32) (0x00FFFFFFu))\r
+ #define CY_SYS_SYST_CVR_CNT_MASK ((uint32) (0x00FFFFFFu))\r
#define CY_SYS_SYST_NUM_OF_CALLBACKS ((uint32) (5u))\r
#endif /* (CY_PSOC5) */\r
\r
\r
/*******************************************************************************\r
* Macro Name: CyIntEnable\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Enables the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number\r
- *\r
- * Return:\r
- * None\r
+ * \param number: Valid range [0-31]. Interrupt number\r
*\r
*******************************************************************************/\r
#define CyIntEnable(number) CY_SET_REG32(CY_INT_ENABLE_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))\r
\r
/*******************************************************************************\r
* Macro Name: CyIntDisable\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Disables the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number.\r
- *\r
- * Return:\r
- * None\r
+ * \param number: Valid range [0-31]. Interrupt number.\r
*\r
*******************************************************************************/\r
#define CyIntDisable(number) CY_SET_REG32(CY_INT_CLEAR_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))\r
\r
/*******************************************************************************\r
* Macro Name: CyIntSetPending\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Forces the specified interrupt number to be pending.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number.\r
- *\r
- * Return:\r
- * None\r
+ * \param number: Valid range [0-31]. Interrupt number.\r
*\r
*******************************************************************************/\r
#define CyIntSetPending(number) CY_SET_REG32(CY_INT_SET_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))\r
\r
/*******************************************************************************\r
* Macro Name: CyIntClearPending\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Clears any pending interrupt for the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number.\r
- *\r
- * Return:\r
- * None\r
+ * \param number: Valid range [0-31]. Interrupt number.\r
*\r
*******************************************************************************/\r
#define CyIntClearPending(number) CY_SET_REG32(CY_INT_CLR_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))\r
\r
/*******************************************************************************\r
* Macro Name: CyIntEnable\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Enables the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number\r
- *\r
- * Return:\r
- * None\r
+ * \param number: Valid range [0-31]. Interrupt number\r
*\r
*******************************************************************************/\r
#define CyIntEnable(number) CY_SET_REG8(CY_INT_SET_EN_INDX_PTR((number)), \\r
\r
/*******************************************************************************\r
* Macro Name: CyIntDisable\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Disables the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number.\r
- *\r
- * Return:\r
- * None\r
+ * \param number: Valid range [0-31]. Interrupt number.\r
*\r
*******************************************************************************/\r
#define CyIntDisable(number) CY_SET_REG8(CY_INT_CLR_EN_INDX_PTR((number)), \\r
\r
/*******************************************************************************\r
* Macro Name: CyIntSetPending\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Forces the specified interrupt number to be pending.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number.\r
- *\r
- * Return:\r
- * None\r
+ * \param number: Valid range [0-31]. Interrupt number.\r
*\r
*******************************************************************************/\r
#define CyIntSetPending(number) CY_SET_REG8(CY_INT_SET_PEND_INDX_PTR((number)), \\r
\r
/*******************************************************************************\r
* Macro Name: CyIntClearPending\r
- ********************************************************************************\r
- * Summary:\r
+ ****************************************************************************//**\r
* Clears any pending interrupt for the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number.\r
- *\r
- * Return:\r
- * None\r
+ * \param number: Valid range [0-31]. Interrupt number.\r
*\r
*******************************************************************************/\r
#define CyIntClearPending(number) CY_SET_REG8(CY_INT_CLR_PEND_INDX_PTR((number)), \\r
-/*******************************************************************************\r
-* File Name: CySpc.c\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file CySpc.c\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides an API for the System Performance Component.\r
-* The SPC functions are not meant to be called directly by the user\r
-* application.\r
+* \brief Provides an API for the System Performance Component.\r
+* The SPC functions are not meant to be called directly by the user\r
+* application.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: CySpcStart\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Starts the SPC.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CySpcStart(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CySpcStop\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Stops the SPC.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CySpcStop(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CySpcReadData\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Reads data from the SPC.\r
*\r
-* Parameters:\r
-* uint8 buffer:\r
+* \param uint8 buffer:\r
* Address to store data read.\r
*\r
-* uint8 size:\r
+* \param uint8 size:\r
* Number of bytes to read from the SPC.\r
*\r
-* Return:\r
+* \return\r
* uint8:\r
* The number of bytes read from the SPC.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CySpcLoadMultiByte\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Loads 1 to 32 bytes of data into the row latch of a Flash/EEPROM array.\r
*\r
-* Parameters:\r
-* uint8 array:\r
+* \param uint8 array:\r
* Id of the array.\r
*\r
-* uint16 address:\r
+* \param uint16 address:\r
* Flash/eeprom addrress\r
*\r
-* uint8* buffer:\r
+* \param uint8* buffer:\r
* Data to load to the row latch\r
*\r
-* uint16 number:\r
+* \param uint16 number:\r
* Number bytes to load.\r
*\r
-* Return:\r
+* \return\r
* CYRET_STARTED\r
* CYRET_CANCELED\r
* CYRET_LOCKED\r
\r
/*******************************************************************************\r
* Function Name: CySpcLoadRow\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Loads a row of data into the row latch of a Flash/EEPROM array.\r
*\r
* The buffer pointer should point to the data that should be written to the\r
* responsibility to prepare data: the preserved data are copied from flash into\r
* array with the modified data.\r
*\r
-* Parameters:\r
-* uint8 array:\r
+* \param uint8 array:\r
* Id of the array.\r
*\r
-* uint8* buffer:\r
+* \param uint8* buffer:\r
* Data to be loaded to the row latch\r
*\r
-* uint8 size:\r
+* \param uint8 size:\r
* The number of data bytes that the SPC expects to be written. Depends on the\r
* type of the array and, if the array is Flash, whether ECC is being enabled\r
* or not. There are following values: flash row latch size with ECC enabled,\r
* flash row latch size with ECC disabled and EEPROM row latch size.\r
*\r
-* Return:\r
+* \return\r
* CYRET_STARTED\r
* CYRET_CANCELED\r
* CYRET_LOCKED\r
\r
/*******************************************************************************\r
* Function Name: CySpcLoadRowFull\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Loads a row of data into the row latch of a Flash/EEPROM array.\r
*\r
* The only data that are going to be changed should be passed. The function\r
* will handle unmodified data preservation based on DWR settings and input\r
* parameters.\r
*\r
-* Parameters:\r
-* uint8 array:\r
+* \param uint8 array:\r
* Id of the array.\r
*\r
-* uint16 row:\r
+* \param uint16 row:\r
* Flash row number to be loaded.\r
*\r
-* uint8* buffer:\r
+* \param uint8* buffer:\r
* Data to be loaded to the row latch\r
*\r
-* uint8 size:\r
+* \param uint8 size:\r
* The number of data bytes that the SPC expects to be written. Depends on the\r
* type of the array and, if the array is Flash, whether ECC is being enabled\r
* or not. There are following values: flash row latch size with ECC enabled,\r
* flash row latch size with ECC disabled and EEPROM row latch size.\r
*\r
-* Return:\r
+* \return\r
* CYRET_STARTED\r
* CYRET_CANCELED\r
* CYRET_LOCKED\r
\r
/*******************************************************************************\r
* Function Name: CySpcWriteRow\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Erases then programs a row in Flash/EEPROM with data in row latch.\r
*\r
-* Parameters:\r
-* uint8 array:\r
+* \param uint8 array:\r
* Id of the array.\r
*\r
-* uint16 address:\r
+* \param uint16 address:\r
* flash/eeprom addrress\r
*\r
-* uint8 tempPolarity:\r
+* \param uint8 tempPolarity:\r
* temperature polarity.\r
-* 1: the Temp Magnitude is interpreted as a positive value\r
-* 0: the Temp Magnitude is interpreted as a negative value\r
+* \param 1: the Temp Magnitude is interpreted as a positive value\r
+* \param 0: the Temp Magnitude is interpreted as a negative value\r
*\r
-* uint8 tempMagnitude:\r
+* \param uint8 tempMagnitude:\r
* temperature magnitude.\r
*\r
-* Return:\r
+* \return\r
* CYRET_STARTED\r
* CYRET_CANCELED\r
* CYRET_LOCKED\r
\r
/*******************************************************************************\r
* Function Name: CySpcEraseSector\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Erases all data in the addressed sector (block of 64 rows).\r
*\r
-* Parameters:\r
-* uint8 array:\r
+* \param uint8 array:\r
* Id of the array.\r
*\r
-* uint8 sectorNumber:\r
+* \param uint8 sectorNumber:\r
* Zero based sector number within Flash/EEPROM array\r
*\r
-* Return:\r
+* \return\r
* CYRET_STARTED\r
* CYRET_CANCELED\r
* CYRET_LOCKED\r
\r
/*******************************************************************************\r
* Function Name: CySpcGetTemp\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Returns the internal die temperature\r
*\r
-* Parameters:\r
-* uint8 numSamples:\r
+* \param uint8 numSamples:\r
* Number of samples. Valid values are 1-5, resulting in 2 - 32 samples\r
* respectively.\r
*\r
-* uint16 timerPeriod:\r
+* \param uint16 timerPeriod:\r
* Number of ADC ACLK cycles. A valid 14 bit value is accepted, higher 2 bits\r
* of 16 bit values are ignored.\r
*\r
-* uint8 clkDivSelect:\r
+* \param uint8 clkDivSelect:\r
* ADC ACLK clock divide value. Valid values are 2 - 225.\r
*\r
-* Return:\r
+* \return\r
* CYRET_STARTED\r
* CYRET_CANCELED\r
* CYRET_LOCKED\r
\r
/*******************************************************************************\r
* Function Name: CySpcLock\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Locks the SPC so it can not be used by someone else:\r
* - Saves wait-pipeline enable state and enable pipeline (PSoC5)\r
*\r
-* Parameters:\r
-* Note\r
-*\r
-* Return:\r
+* \return\r
* CYRET_SUCCESS - if the resource was free.\r
* CYRET_LOCKED - if the SPC is in use.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CySpcUnlock\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Unlocks the SPC so it can be used by someone else:\r
* - Restores wait-pipeline enable state (PSoC5)\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CySpcUnlock(void)\r
{\r
\r
/*******************************************************************************\r
* Function Name: CySpcGetAlgorithm\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Downloads SPC algorithm from SPC SROM into SRAM.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* CYRET_STARTED\r
* CYRET_LOCKED\r
*\r
-/*******************************************************************************\r
-* File Name: CySpc.c\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file CySpc.c\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides definitions for the System Performance Component API.\r
+* \brief Provides definitions for the System Performance Component API.\r
* The SPC functions are not meant to be called directly by the user\r
* application.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: LED1.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: LED1_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet LED1_SUT.c usage_LED1_Write\r
*******************************************************************************/\r
-void LED1_Write(uint8 value) \r
+void LED1_Write(uint8 value)\r
{\r
uint8 staticBits = (LED1_DR & (uint8)(~LED1_MASK));\r
LED1_DR = staticBits | ((uint8)(value << LED1_SHIFT) & LED1_MASK);\r
\r
/*******************************************************************************\r
* Function Name: LED1_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* LED1_DM_STRONG Strong Drive \r
-* LED1_DM_OD_HI Open Drain, Drives High \r
-* LED1_DM_OD_LO Open Drain, Drives Low \r
-* LED1_DM_RES_UP Resistive Pull Up \r
-* LED1_DM_RES_DWN Resistive Pull Down \r
-* LED1_DM_RES_UPDWN Resistive Pull Up/Down \r
-* LED1_DM_DIG_HIZ High Impedance Digital \r
-* LED1_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet LED1_SUT.c usage_LED1_SetDriveMode\r
*******************************************************************************/\r
-void LED1_SetDriveMode(uint8 mode) \r
+void LED1_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(LED1_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: LED1_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro LED1_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet LED1_SUT.c usage_LED1_Read \r
*******************************************************************************/\r
-uint8 LED1_Read(void) \r
+uint8 LED1_Read(void)\r
{\r
return (LED1_PS & LED1_MASK) >> LED1_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: LED1_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred LED1_Read() API because the \r
+* LED1_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet LED1_SUT.c usage_LED1_ReadDataReg \r
*******************************************************************************/\r
-uint8 LED1_ReadDataReg(void) \r
+uint8 LED1_ReadDataReg(void)\r
{\r
return (LED1_DR & LED1_MASK) >> LED1_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(LED1_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: LED1_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use LED1_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - LED1_0_INTR (First pin in the list)\r
+ * - LED1_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - LED1_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet LED1_SUT.c usage_LED1_SetInterruptMode\r
+ *******************************************************************************/\r
+ void LED1_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & LED1_0_INTR) != 0u) \r
+ { \r
+ LED1_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: LED1_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet LED1_SUT.c usage_LED1_ClearInterrupt\r
*******************************************************************************/\r
- uint8 LED1_ClearInterrupt(void) \r
+ uint8 LED1_ClearInterrupt(void)\r
{\r
return (LED1_INTSTAT & LED1_MASK) >> LED1_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: LED1.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "LED1_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void LED1_Write(uint8 value) ;\r
-void LED1_SetDriveMode(uint8 mode) ;\r
-uint8 LED1_ReadDataReg(void) ;\r
-uint8 LED1_Read(void) ;\r
-uint8 LED1_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void LED1_Write(uint8 value);\r
+void LED1_SetDriveMode(uint8 mode);\r
+uint8 LED1_ReadDataReg(void);\r
+uint8 LED1_Read(void);\r
+void LED1_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 LED1_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define LED1_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define LED1_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define LED1_DM_RES_UP PIN_DM_RES_UP\r
-#define LED1_DM_RES_DWN PIN_DM_RES_DWN\r
-#define LED1_DM_OD_LO PIN_DM_OD_LO\r
-#define LED1_DM_OD_HI PIN_DM_OD_HI\r
-#define LED1_DM_STRONG PIN_DM_STRONG\r
-#define LED1_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the LED1_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define LED1_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define LED1_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define LED1_DM_RES_UP PIN_DM_RES_UP\r
+ #define LED1_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define LED1_DM_OD_LO PIN_DM_OD_LO\r
+ #define LED1_DM_OD_HI PIN_DM_OD_HI\r
+ #define LED1_DM_STRONG PIN_DM_STRONG\r
+ #define LED1_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define LED1_MASK LED1__MASK\r
#define LED1_SHIFT LED1__SHIFT\r
#define LED1_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(LED1__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in LED1_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define LED1_INTR_NONE (uint16)(0x0000u)\r
+ #define LED1_INTR_RISING (uint16)(0x0001u)\r
+ #define LED1_INTR_FALLING (uint16)(0x0002u)\r
+ #define LED1_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define LED1_INTR_MASK (0x01u) \r
+#endif /* (LED1__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define LED1_PRTDSI__SYNC_OUT (* (reg8 *) LED1__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(LED1__INTSTAT) /* Interrupt Registers */\r
-\r
- #define LED1_INTSTAT (* (reg8 *) LED1__INTSTAT)\r
- #define LED1_SNAP (* (reg8 *) LED1__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(LED1__SIO_CFG)\r
+ #define LED1_SIO_HYST_EN (* (reg8 *) LED1__SIO_HYST_EN)\r
+ #define LED1_SIO_REG_HIFREQ (* (reg8 *) LED1__SIO_REG_HIFREQ)\r
+ #define LED1_SIO_CFG (* (reg8 *) LED1__SIO_CFG)\r
+ #define LED1_SIO_DIFF (* (reg8 *) LED1__SIO_DIFF)\r
+#endif /* (LED1__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(LED1__INTSTAT)\r
+ #define LED1_INTSTAT (* (reg8 *) LED1__INTSTAT)\r
+ #define LED1_SNAP (* (reg8 *) LED1__SNAP)\r
+ \r
+ #define LED1_0_INTTYPE_REG (* (reg8 *) LED1__0__INTTYPE)\r
+#endif /* (LED1__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: LED1.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define LED1_0 (LED1__0__PC)\r
+#define LED1_0 (LED1__0__PC)\r
+#define LED1_0_INTR ((uint16)((uint16)0x0001u << LED1__0__SHIFT))\r
+\r
+#define LED1_INTR_ALL ((uint16)(LED1_0_INTR))\r
\r
#endif /* End Pins LED1_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************
* File Name: SCSI_CTL_PHASE.c
-* Version 1.70
+* Version 1.80
*
* Description:
* This file contains API to enable firmware control of a Control Register.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "SCSI_CTL_PHASE.h"
-#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+/* Check for removal by optimization */
+#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED)
+
/*******************************************************************************
* Function Name: SCSI_CTL_PHASE_Write
********************************************************************************
/*******************************************************************************
* File Name: SCSI_CTL_PHASE.h
-* Version 1.70
+* Version 1.80
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "cytypes.h"
+
+/***************************************
+* Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+ uint8 controlState;
+
+} SCSI_CTL_PHASE_BACKUP_STRUCT;
+
/***************************************
* Function Prototypes
void SCSI_CTL_PHASE_Write(uint8 control) ;
uint8 SCSI_CTL_PHASE_Read(void) ;
+void SCSI_CTL_PHASE_SaveConfig(void) ;
+void SCSI_CTL_PHASE_RestoreConfig(void) ;
+void SCSI_CTL_PHASE_Sleep(void) ;
+void SCSI_CTL_PHASE_Wakeup(void) ;
+
/***************************************
* Registers
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_CTL_PHASE_PM.c
+* Version 1.80
+*
+* Description:
+* This file contains the setup, control, and status commands to support
+* the component operation in the low power mode.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_CTL_PHASE.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED)
+
+static SCSI_CTL_PHASE_BACKUP_STRUCT SCSI_CTL_PHASE_backup = {0u};
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_SaveConfig
+********************************************************************************
+*
+* Summary:
+* Saves the control register value.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_SaveConfig(void)
+{
+ SCSI_CTL_PHASE_backup.controlState = SCSI_CTL_PHASE_Control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_RestoreConfig
+********************************************************************************
+*
+* Summary:
+* Restores the control register value.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_RestoreConfig(void)
+{
+ SCSI_CTL_PHASE_Control = SCSI_CTL_PHASE_backup.controlState;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_Sleep
+********************************************************************************
+*
+* Summary:
+* Prepares the component for entering the low power mode.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_Sleep(void)
+{
+ SCSI_CTL_PHASE_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CTL_PHASE_Wakeup
+********************************************************************************
+*
+* Summary:
+* Restores the component after waking up from the low power mode.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_CTL_PHASE_Wakeup(void)
+{
+ SCSI_CTL_PHASE_RestoreConfig();
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
/*******************************************************************************
* File Name: SCSI_Filtered.c
-* Version 1.80
+* Version 1.90
*
* Description:
* This file contains API to enable firmware to read the value of a Status
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
void SCSI_Filtered_WriteMask(uint8 mask)
{
#if(SCSI_Filtered_INPUTS < 8u)
- mask &= (uint8)((((uint8)1u) << SCSI_Filtered_INPUTS) - 1u);
+ mask &= ((uint8)(1u << SCSI_Filtered_INPUTS) - 1u);
#endif /* End SCSI_Filtered_INPUTS < 8u */
SCSI_Filtered_Status_Mask = mask;
}
/*******************************************************************************
* File Name: SCSI_Filtered.h
-* Version 1.80
+* Version 1.90
*
* Description:
* This file containts Status Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "cytypes.h"
#include "CyLib.h"
+
+/***************************************
+* Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+ uint8 statusState;
+
+} SCSI_Filtered_BACKUP_STRUCT;
+
/***************************************
* Function Prototypes
/*******************************************************************************
* File Name: SCSI_Glitch_Ctl.c
-* Version 1.70
+* Version 1.80
*
* Description:
* This file contains API to enable firmware control of a Control Register.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "SCSI_Glitch_Ctl.h"
-#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+/* Check for removal by optimization */
+#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED)
+
/*******************************************************************************
* Function Name: SCSI_Glitch_Ctl_Write
********************************************************************************
/*******************************************************************************
* File Name: SCSI_Glitch_Ctl.h
-* Version 1.70
+* Version 1.80
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "cytypes.h"
+
+/***************************************
+* Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+ uint8 controlState;
+
+} SCSI_Glitch_Ctl_BACKUP_STRUCT;
+
/***************************************
* Function Prototypes
void SCSI_Glitch_Ctl_Write(uint8 control) ;
uint8 SCSI_Glitch_Ctl_Read(void) ;
+void SCSI_Glitch_Ctl_SaveConfig(void) ;
+void SCSI_Glitch_Ctl_RestoreConfig(void) ;
+void SCSI_Glitch_Ctl_Sleep(void) ;
+void SCSI_Glitch_Ctl_Wakeup(void) ;
+
/***************************************
* Registers
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Glitch_Ctl_PM.c
+* Version 1.80
+*
+* Description:
+* This file contains the setup, control, and status commands to support
+* the component operation in the low power mode.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Glitch_Ctl.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED)
+
+static SCSI_Glitch_Ctl_BACKUP_STRUCT SCSI_Glitch_Ctl_backup = {0u};
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_SaveConfig
+********************************************************************************
+*
+* Summary:
+* Saves the control register value.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_SaveConfig(void)
+{
+ SCSI_Glitch_Ctl_backup.controlState = SCSI_Glitch_Ctl_Control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_RestoreConfig
+********************************************************************************
+*
+* Summary:
+* Restores the control register value.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_RestoreConfig(void)
+{
+ SCSI_Glitch_Ctl_Control = SCSI_Glitch_Ctl_backup.controlState;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Sleep
+********************************************************************************
+*
+* Summary:
+* Prepares the component for entering the low power mode.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_Sleep(void)
+{
+ SCSI_Glitch_Ctl_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Wakeup
+********************************************************************************
+*
+* Summary:
+* Restores the component after waking up from the low power mode.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_Wakeup(void)
+{
+ SCSI_Glitch_Ctl_RestoreConfig();
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
/*******************************************************************************\r
* File Name: SCSI_In_DBx.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SCSI_In_DBx_0 (SCSI_In_DBx__0__PC)\r
-#define SCSI_In_DBx_1 (SCSI_In_DBx__1__PC)\r
-#define SCSI_In_DBx_2 (SCSI_In_DBx__2__PC)\r
-#define SCSI_In_DBx_3 (SCSI_In_DBx__3__PC)\r
-#define SCSI_In_DBx_4 (SCSI_In_DBx__4__PC)\r
-#define SCSI_In_DBx_5 (SCSI_In_DBx__5__PC)\r
-#define SCSI_In_DBx_6 (SCSI_In_DBx__6__PC)\r
-#define SCSI_In_DBx_7 (SCSI_In_DBx__7__PC)\r
-\r
-#define SCSI_In_DBx_DB0 (SCSI_In_DBx__DB0__PC)\r
-#define SCSI_In_DBx_DB1 (SCSI_In_DBx__DB1__PC)\r
-#define SCSI_In_DBx_DB2 (SCSI_In_DBx__DB2__PC)\r
-#define SCSI_In_DBx_DB3 (SCSI_In_DBx__DB3__PC)\r
-#define SCSI_In_DBx_DB4 (SCSI_In_DBx__DB4__PC)\r
-#define SCSI_In_DBx_DB5 (SCSI_In_DBx__DB5__PC)\r
-#define SCSI_In_DBx_DB6 (SCSI_In_DBx__DB6__PC)\r
-#define SCSI_In_DBx_DB7 (SCSI_In_DBx__DB7__PC)\r
+#define SCSI_In_DBx_0 (SCSI_In_DBx__0__PC)\r
+#define SCSI_In_DBx_0_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__0__SHIFT))\r
+\r
+#define SCSI_In_DBx_1 (SCSI_In_DBx__1__PC)\r
+#define SCSI_In_DBx_1_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__1__SHIFT))\r
+\r
+#define SCSI_In_DBx_2 (SCSI_In_DBx__2__PC)\r
+#define SCSI_In_DBx_2_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__2__SHIFT))\r
+\r
+#define SCSI_In_DBx_3 (SCSI_In_DBx__3__PC)\r
+#define SCSI_In_DBx_3_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__3__SHIFT))\r
+\r
+#define SCSI_In_DBx_4 (SCSI_In_DBx__4__PC)\r
+#define SCSI_In_DBx_4_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__4__SHIFT))\r
+\r
+#define SCSI_In_DBx_5 (SCSI_In_DBx__5__PC)\r
+#define SCSI_In_DBx_5_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__5__SHIFT))\r
+\r
+#define SCSI_In_DBx_6 (SCSI_In_DBx__6__PC)\r
+#define SCSI_In_DBx_6_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__6__SHIFT))\r
+\r
+#define SCSI_In_DBx_7 (SCSI_In_DBx__7__PC)\r
+#define SCSI_In_DBx_7_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__7__SHIFT))\r
+\r
+#define SCSI_In_DBx_INTR_ALL ((uint16)(SCSI_In_DBx_0_INTR| SCSI_In_DBx_1_INTR| SCSI_In_DBx_2_INTR| SCSI_In_DBx_3_INTR| SCSI_In_DBx_4_INTR| SCSI_In_DBx_5_INTR| SCSI_In_DBx_6_INTR| SCSI_In_DBx_7_INTR))\r
+#define SCSI_In_DBx_DB0 (SCSI_In_DBx__DB0__PC)\r
+#define SCSI_In_DBx_DB0_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__0__SHIFT))\r
+\r
+#define SCSI_In_DBx_DB1 (SCSI_In_DBx__DB1__PC)\r
+#define SCSI_In_DBx_DB1_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__1__SHIFT))\r
+\r
+#define SCSI_In_DBx_DB2 (SCSI_In_DBx__DB2__PC)\r
+#define SCSI_In_DBx_DB2_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__2__SHIFT))\r
+\r
+#define SCSI_In_DBx_DB3 (SCSI_In_DBx__DB3__PC)\r
+#define SCSI_In_DBx_DB3_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__3__SHIFT))\r
+\r
+#define SCSI_In_DBx_DB4 (SCSI_In_DBx__DB4__PC)\r
+#define SCSI_In_DBx_DB4_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__4__SHIFT))\r
+\r
+#define SCSI_In_DBx_DB5 (SCSI_In_DBx__DB5__PC)\r
+#define SCSI_In_DBx_DB5_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__5__SHIFT))\r
+\r
+#define SCSI_In_DBx_DB6 (SCSI_In_DBx__DB6__PC)\r
+#define SCSI_In_DBx_DB6_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__6__SHIFT))\r
+\r
+#define SCSI_In_DBx_DB7 (SCSI_In_DBx__DB7__PC)\r
+#define SCSI_In_DBx_DB7_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__7__SHIFT))\r
\r
#endif /* End Pins SCSI_In_DBx_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SCSI_In.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SCSI_In_0 (SCSI_In__0__PC)\r
-#define SCSI_In_1 (SCSI_In__1__PC)\r
-#define SCSI_In_2 (SCSI_In__2__PC)\r
-#define SCSI_In_3 (SCSI_In__3__PC)\r
-#define SCSI_In_4 (SCSI_In__4__PC)\r
-\r
-#define SCSI_In_DBP (SCSI_In__DBP__PC)\r
-#define SCSI_In_MSG (SCSI_In__MSG__PC)\r
-#define SCSI_In_CD (SCSI_In__CD__PC)\r
-#define SCSI_In_REQ (SCSI_In__REQ__PC)\r
-#define SCSI_In_IO (SCSI_In__IO__PC)\r
+#define SCSI_In_0 (SCSI_In__0__PC)\r
+#define SCSI_In_0_INTR ((uint16)((uint16)0x0001u << SCSI_In__0__SHIFT))\r
+\r
+#define SCSI_In_1 (SCSI_In__1__PC)\r
+#define SCSI_In_1_INTR ((uint16)((uint16)0x0001u << SCSI_In__1__SHIFT))\r
+\r
+#define SCSI_In_2 (SCSI_In__2__PC)\r
+#define SCSI_In_2_INTR ((uint16)((uint16)0x0001u << SCSI_In__2__SHIFT))\r
+\r
+#define SCSI_In_3 (SCSI_In__3__PC)\r
+#define SCSI_In_3_INTR ((uint16)((uint16)0x0001u << SCSI_In__3__SHIFT))\r
+\r
+#define SCSI_In_4 (SCSI_In__4__PC)\r
+#define SCSI_In_4_INTR ((uint16)((uint16)0x0001u << SCSI_In__4__SHIFT))\r
+\r
+#define SCSI_In_INTR_ALL ((uint16)(SCSI_In_0_INTR| SCSI_In_1_INTR| SCSI_In_2_INTR| SCSI_In_3_INTR| SCSI_In_4_INTR))\r
+#define SCSI_In_DBP (SCSI_In__DBP__PC)\r
+#define SCSI_In_DBP_INTR ((uint16)((uint16)0x0001u << SCSI_In__0__SHIFT))\r
+\r
+#define SCSI_In_MSG (SCSI_In__MSG__PC)\r
+#define SCSI_In_MSG_INTR ((uint16)((uint16)0x0001u << SCSI_In__1__SHIFT))\r
+\r
+#define SCSI_In_CD (SCSI_In__CD__PC)\r
+#define SCSI_In_CD_INTR ((uint16)((uint16)0x0001u << SCSI_In__2__SHIFT))\r
+\r
+#define SCSI_In_REQ (SCSI_In__REQ__PC)\r
+#define SCSI_In_REQ_INTR ((uint16)((uint16)0x0001u << SCSI_In__3__SHIFT))\r
+\r
+#define SCSI_In_IO (SCSI_In__IO__PC)\r
+#define SCSI_In_IO_INTR ((uint16)((uint16)0x0001u << SCSI_In__4__SHIFT))\r
\r
#endif /* End Pins SCSI_In_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************
* File Name: SCSI_Noise.h
-* Version 2.10
+* Version 2.20
*
* Description:
-* This file containts Control Register function prototypes and register defines
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h.
+* Information on using these APIs can be found in the System Reference Guide.
*
* Note:
*
********************************************************************************
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "cyfitter.h"
-
/***************************************
* Constants
***************************************/
-#define SCSI_Noise_0 (SCSI_Noise__0__PC)
-#define SCSI_Noise_1 (SCSI_Noise__1__PC)
-#define SCSI_Noise_2 (SCSI_Noise__2__PC)
-#define SCSI_Noise_3 (SCSI_Noise__3__PC)
-#define SCSI_Noise_4 (SCSI_Noise__4__PC)
-
-#define SCSI_Noise_ATN (SCSI_Noise__ATN__PC)
-#define SCSI_Noise_BSY (SCSI_Noise__BSY__PC)
-#define SCSI_Noise_SEL (SCSI_Noise__SEL__PC)
-#define SCSI_Noise_RST (SCSI_Noise__RST__PC)
-#define SCSI_Noise_ACK (SCSI_Noise__ACK__PC)
+#define SCSI_Noise_0 (SCSI_Noise__0__PC)
+#define SCSI_Noise_0_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__0__SHIFT))
+
+#define SCSI_Noise_1 (SCSI_Noise__1__PC)
+#define SCSI_Noise_1_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__1__SHIFT))
+
+#define SCSI_Noise_2 (SCSI_Noise__2__PC)
+#define SCSI_Noise_2_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__2__SHIFT))
+
+#define SCSI_Noise_3 (SCSI_Noise__3__PC)
+#define SCSI_Noise_3_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__3__SHIFT))
+
+#define SCSI_Noise_4 (SCSI_Noise__4__PC)
+#define SCSI_Noise_4_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__4__SHIFT))
+
+#define SCSI_Noise_INTR_ALL ((uint16)(SCSI_Noise_0_INTR| SCSI_Noise_1_INTR| SCSI_Noise_2_INTR| SCSI_Noise_3_INTR| SCSI_Noise_4_INTR))
+#define SCSI_Noise_ATN (SCSI_Noise__ATN__PC)
+#define SCSI_Noise_ATN_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__0__SHIFT))
+
+#define SCSI_Noise_BSY (SCSI_Noise__BSY__PC)
+#define SCSI_Noise_BSY_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__1__SHIFT))
+
+#define SCSI_Noise_SEL (SCSI_Noise__SEL__PC)
+#define SCSI_Noise_SEL_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__2__SHIFT))
+
+#define SCSI_Noise_RST (SCSI_Noise__RST__PC)
+#define SCSI_Noise_RST_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__3__SHIFT))
+
+#define SCSI_Noise_ACK (SCSI_Noise__ACK__PC)
+#define SCSI_Noise_ACK_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__4__SHIFT))
#endif /* End Pins SCSI_Noise_ALIASES_H */
+
/* [] END OF FILE */
/*******************************************************************************
* File Name: SCSI_Out_Bits.c
-* Version 1.70
+* Version 1.80
*
* Description:
* This file contains API to enable firmware control of a Control Register.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "SCSI_Out_Bits.h"
-#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+/* Check for removal by optimization */
+#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED)
+
/*******************************************************************************
* Function Name: SCSI_Out_Bits_Write
********************************************************************************
/*******************************************************************************
* File Name: SCSI_Out_Bits.h
-* Version 1.70
+* Version 1.80
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "cytypes.h"
+
+/***************************************
+* Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+ uint8 controlState;
+
+} SCSI_Out_Bits_BACKUP_STRUCT;
+
/***************************************
* Function Prototypes
void SCSI_Out_Bits_Write(uint8 control) ;
uint8 SCSI_Out_Bits_Read(void) ;
+void SCSI_Out_Bits_SaveConfig(void) ;
+void SCSI_Out_Bits_RestoreConfig(void) ;
+void SCSI_Out_Bits_Sleep(void) ;
+void SCSI_Out_Bits_Wakeup(void) ;
+
/***************************************
* Registers
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Out_Bits_PM.c
+* Version 1.80
+*
+* Description:
+* This file contains the setup, control, and status commands to support
+* the component operation in the low power mode.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Out_Bits.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED)
+
+static SCSI_Out_Bits_BACKUP_STRUCT SCSI_Out_Bits_backup = {0u};
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_SaveConfig
+********************************************************************************
+*
+* Summary:
+* Saves the control register value.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Out_Bits_SaveConfig(void)
+{
+ SCSI_Out_Bits_backup.controlState = SCSI_Out_Bits_Control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_RestoreConfig
+********************************************************************************
+*
+* Summary:
+* Restores the control register value.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*
+*******************************************************************************/
+void SCSI_Out_Bits_RestoreConfig(void)
+{
+ SCSI_Out_Bits_Control = SCSI_Out_Bits_backup.controlState;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_Sleep
+********************************************************************************
+*
+* Summary:
+* Prepares the component for entering the low power mode.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Out_Bits_Sleep(void)
+{
+ SCSI_Out_Bits_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_Wakeup
+********************************************************************************
+*
+* Summary:
+* Restores the component after waking up from the low power mode.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Out_Bits_Wakeup(void)
+{
+ SCSI_Out_Bits_RestoreConfig();
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
/*******************************************************************************
* File Name: SCSI_Out_Ctl.c
-* Version 1.70
+* Version 1.80
*
* Description:
* This file contains API to enable firmware control of a Control Register.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "SCSI_Out_Ctl.h"
-#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+/* Check for removal by optimization */
+#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED)
+
/*******************************************************************************
* Function Name: SCSI_Out_Ctl_Write
********************************************************************************
/*******************************************************************************
* File Name: SCSI_Out_Ctl.h
-* Version 1.70
+* Version 1.80
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "cytypes.h"
+
+/***************************************
+* Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+ uint8 controlState;
+
+} SCSI_Out_Ctl_BACKUP_STRUCT;
+
/***************************************
* Function Prototypes
void SCSI_Out_Ctl_Write(uint8 control) ;
uint8 SCSI_Out_Ctl_Read(void) ;
+void SCSI_Out_Ctl_SaveConfig(void) ;
+void SCSI_Out_Ctl_RestoreConfig(void) ;
+void SCSI_Out_Ctl_Sleep(void) ;
+void SCSI_Out_Ctl_Wakeup(void) ;
+
/***************************************
* Registers
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Out_Ctl_PM.c
+* Version 1.80
+*
+* Description:
+* This file contains the setup, control, and status commands to support
+* the component operation in the low power mode.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Out_Ctl.h"
+
+/* Check for removal by optimization */
+#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED)
+
+static SCSI_Out_Ctl_BACKUP_STRUCT SCSI_Out_Ctl_backup = {0u};
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_SaveConfig
+********************************************************************************
+*
+* Summary:
+* Saves the control register value.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_SaveConfig(void)
+{
+ SCSI_Out_Ctl_backup.controlState = SCSI_Out_Ctl_Control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_RestoreConfig
+********************************************************************************
+*
+* Summary:
+* Restores the control register value.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_RestoreConfig(void)
+{
+ SCSI_Out_Ctl_Control = SCSI_Out_Ctl_backup.controlState;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_Sleep
+********************************************************************************
+*
+* Summary:
+* Prepares the component for entering the low power mode.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_Sleep(void)
+{
+ SCSI_Out_Ctl_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_Wakeup
+********************************************************************************
+*
+* Summary:
+* Restores the component after waking up from the low power mode.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_Wakeup(void)
+{
+ SCSI_Out_Ctl_RestoreConfig();
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
/*******************************************************************************\r
* File Name: SCSI_Out_DBx.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SCSI_Out_DBx_0 (SCSI_Out_DBx__0__PC)\r
-#define SCSI_Out_DBx_1 (SCSI_Out_DBx__1__PC)\r
-#define SCSI_Out_DBx_2 (SCSI_Out_DBx__2__PC)\r
-#define SCSI_Out_DBx_3 (SCSI_Out_DBx__3__PC)\r
-#define SCSI_Out_DBx_4 (SCSI_Out_DBx__4__PC)\r
-#define SCSI_Out_DBx_5 (SCSI_Out_DBx__5__PC)\r
-#define SCSI_Out_DBx_6 (SCSI_Out_DBx__6__PC)\r
-#define SCSI_Out_DBx_7 (SCSI_Out_DBx__7__PC)\r
-\r
-#define SCSI_Out_DBx_DB0 (SCSI_Out_DBx__DB0__PC)\r
-#define SCSI_Out_DBx_DB1 (SCSI_Out_DBx__DB1__PC)\r
-#define SCSI_Out_DBx_DB2 (SCSI_Out_DBx__DB2__PC)\r
-#define SCSI_Out_DBx_DB3 (SCSI_Out_DBx__DB3__PC)\r
-#define SCSI_Out_DBx_DB4 (SCSI_Out_DBx__DB4__PC)\r
-#define SCSI_Out_DBx_DB5 (SCSI_Out_DBx__DB5__PC)\r
-#define SCSI_Out_DBx_DB6 (SCSI_Out_DBx__DB6__PC)\r
-#define SCSI_Out_DBx_DB7 (SCSI_Out_DBx__DB7__PC)\r
+#define SCSI_Out_DBx_0 (SCSI_Out_DBx__0__PC)\r
+#define SCSI_Out_DBx_0_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__0__SHIFT))\r
+\r
+#define SCSI_Out_DBx_1 (SCSI_Out_DBx__1__PC)\r
+#define SCSI_Out_DBx_1_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__1__SHIFT))\r
+\r
+#define SCSI_Out_DBx_2 (SCSI_Out_DBx__2__PC)\r
+#define SCSI_Out_DBx_2_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__2__SHIFT))\r
+\r
+#define SCSI_Out_DBx_3 (SCSI_Out_DBx__3__PC)\r
+#define SCSI_Out_DBx_3_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__3__SHIFT))\r
+\r
+#define SCSI_Out_DBx_4 (SCSI_Out_DBx__4__PC)\r
+#define SCSI_Out_DBx_4_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__4__SHIFT))\r
+\r
+#define SCSI_Out_DBx_5 (SCSI_Out_DBx__5__PC)\r
+#define SCSI_Out_DBx_5_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__5__SHIFT))\r
+\r
+#define SCSI_Out_DBx_6 (SCSI_Out_DBx__6__PC)\r
+#define SCSI_Out_DBx_6_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__6__SHIFT))\r
+\r
+#define SCSI_Out_DBx_7 (SCSI_Out_DBx__7__PC)\r
+#define SCSI_Out_DBx_7_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__7__SHIFT))\r
+\r
+#define SCSI_Out_DBx_INTR_ALL ((uint16)(SCSI_Out_DBx_0_INTR| SCSI_Out_DBx_1_INTR| SCSI_Out_DBx_2_INTR| SCSI_Out_DBx_3_INTR| SCSI_Out_DBx_4_INTR| SCSI_Out_DBx_5_INTR| SCSI_Out_DBx_6_INTR| SCSI_Out_DBx_7_INTR))\r
+#define SCSI_Out_DBx_DB0 (SCSI_Out_DBx__DB0__PC)\r
+#define SCSI_Out_DBx_DB0_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__0__SHIFT))\r
+\r
+#define SCSI_Out_DBx_DB1 (SCSI_Out_DBx__DB1__PC)\r
+#define SCSI_Out_DBx_DB1_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__1__SHIFT))\r
+\r
+#define SCSI_Out_DBx_DB2 (SCSI_Out_DBx__DB2__PC)\r
+#define SCSI_Out_DBx_DB2_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__2__SHIFT))\r
+\r
+#define SCSI_Out_DBx_DB3 (SCSI_Out_DBx__DB3__PC)\r
+#define SCSI_Out_DBx_DB3_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__3__SHIFT))\r
+\r
+#define SCSI_Out_DBx_DB4 (SCSI_Out_DBx__DB4__PC)\r
+#define SCSI_Out_DBx_DB4_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__4__SHIFT))\r
+\r
+#define SCSI_Out_DBx_DB5 (SCSI_Out_DBx__DB5__PC)\r
+#define SCSI_Out_DBx_DB5_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__5__SHIFT))\r
+\r
+#define SCSI_Out_DBx_DB6 (SCSI_Out_DBx__DB6__PC)\r
+#define SCSI_Out_DBx_DB6_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__6__SHIFT))\r
+\r
+#define SCSI_Out_DBx_DB7 (SCSI_Out_DBx__DB7__PC)\r
+#define SCSI_Out_DBx_DB7_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__7__SHIFT))\r
\r
#endif /* End Pins SCSI_Out_DBx_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SCSI_Out.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SCSI_Out_0 (SCSI_Out__0__PC)\r
-#define SCSI_Out_1 (SCSI_Out__1__PC)\r
-#define SCSI_Out_2 (SCSI_Out__2__PC)\r
-#define SCSI_Out_3 (SCSI_Out__3__PC)\r
-#define SCSI_Out_4 (SCSI_Out__4__PC)\r
-#define SCSI_Out_5 (SCSI_Out__5__PC)\r
-#define SCSI_Out_6 (SCSI_Out__6__PC)\r
-#define SCSI_Out_7 (SCSI_Out__7__PC)\r
-#define SCSI_Out_8 (SCSI_Out__8__PC)\r
-#define SCSI_Out_9 (SCSI_Out__9__PC)\r
-\r
-#define SCSI_Out_DBP_raw (SCSI_Out__DBP_raw__PC)\r
-#define SCSI_Out_ATN (SCSI_Out__ATN__PC)\r
-#define SCSI_Out_BSY (SCSI_Out__BSY__PC)\r
-#define SCSI_Out_ACK (SCSI_Out__ACK__PC)\r
-#define SCSI_Out_RST (SCSI_Out__RST__PC)\r
-#define SCSI_Out_MSG_raw (SCSI_Out__MSG_raw__PC)\r
-#define SCSI_Out_SEL (SCSI_Out__SEL__PC)\r
-#define SCSI_Out_CD_raw (SCSI_Out__CD_raw__PC)\r
-#define SCSI_Out_REQ (SCSI_Out__REQ__PC)\r
-#define SCSI_Out_IO_raw (SCSI_Out__IO_raw__PC)\r
+#define SCSI_Out_0 (SCSI_Out__0__PC)\r
+#define SCSI_Out_0_INTR ((uint16)((uint16)0x0001u << SCSI_Out__0__SHIFT))\r
+\r
+#define SCSI_Out_1 (SCSI_Out__1__PC)\r
+#define SCSI_Out_1_INTR ((uint16)((uint16)0x0001u << SCSI_Out__1__SHIFT))\r
+\r
+#define SCSI_Out_2 (SCSI_Out__2__PC)\r
+#define SCSI_Out_2_INTR ((uint16)((uint16)0x0001u << SCSI_Out__2__SHIFT))\r
+\r
+#define SCSI_Out_3 (SCSI_Out__3__PC)\r
+#define SCSI_Out_3_INTR ((uint16)((uint16)0x0001u << SCSI_Out__3__SHIFT))\r
+\r
+#define SCSI_Out_4 (SCSI_Out__4__PC)\r
+#define SCSI_Out_4_INTR ((uint16)((uint16)0x0001u << SCSI_Out__4__SHIFT))\r
+\r
+#define SCSI_Out_5 (SCSI_Out__5__PC)\r
+#define SCSI_Out_5_INTR ((uint16)((uint16)0x0001u << SCSI_Out__5__SHIFT))\r
+\r
+#define SCSI_Out_6 (SCSI_Out__6__PC)\r
+#define SCSI_Out_6_INTR ((uint16)((uint16)0x0001u << SCSI_Out__6__SHIFT))\r
+\r
+#define SCSI_Out_7 (SCSI_Out__7__PC)\r
+#define SCSI_Out_7_INTR ((uint16)((uint16)0x0001u << SCSI_Out__7__SHIFT))\r
+\r
+#define SCSI_Out_8 (SCSI_Out__8__PC)\r
+#define SCSI_Out_8_INTR ((uint16)((uint16)0x0001u << SCSI_Out__8__SHIFT))\r
+\r
+#define SCSI_Out_9 (SCSI_Out__9__PC)\r
+#define SCSI_Out_9_INTR ((uint16)((uint16)0x0001u << SCSI_Out__9__SHIFT))\r
+\r
+#define SCSI_Out_INTR_ALL ((uint16)(SCSI_Out_0_INTR| SCSI_Out_1_INTR| SCSI_Out_2_INTR| SCSI_Out_3_INTR| SCSI_Out_4_INTR| SCSI_Out_5_INTR| SCSI_Out_6_INTR| SCSI_Out_7_INTR| SCSI_Out_8_INTR| SCSI_Out_9_INTR))\r
+#define SCSI_Out_DBP_raw (SCSI_Out__DBP_raw__PC)\r
+#define SCSI_Out_DBP_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__0__SHIFT))\r
+\r
+#define SCSI_Out_ATN (SCSI_Out__ATN__PC)\r
+#define SCSI_Out_ATN_INTR ((uint16)((uint16)0x0001u << SCSI_Out__1__SHIFT))\r
+\r
+#define SCSI_Out_BSY (SCSI_Out__BSY__PC)\r
+#define SCSI_Out_BSY_INTR ((uint16)((uint16)0x0001u << SCSI_Out__2__SHIFT))\r
+\r
+#define SCSI_Out_ACK (SCSI_Out__ACK__PC)\r
+#define SCSI_Out_ACK_INTR ((uint16)((uint16)0x0001u << SCSI_Out__3__SHIFT))\r
+\r
+#define SCSI_Out_RST (SCSI_Out__RST__PC)\r
+#define SCSI_Out_RST_INTR ((uint16)((uint16)0x0001u << SCSI_Out__4__SHIFT))\r
+\r
+#define SCSI_Out_MSG_raw (SCSI_Out__MSG_raw__PC)\r
+#define SCSI_Out_MSG_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__5__SHIFT))\r
+\r
+#define SCSI_Out_SEL (SCSI_Out__SEL__PC)\r
+#define SCSI_Out_SEL_INTR ((uint16)((uint16)0x0001u << SCSI_Out__6__SHIFT))\r
+\r
+#define SCSI_Out_CD_raw (SCSI_Out__CD_raw__PC)\r
+#define SCSI_Out_CD_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__7__SHIFT))\r
+\r
+#define SCSI_Out_REQ (SCSI_Out__REQ__PC)\r
+#define SCSI_Out_REQ_INTR ((uint16)((uint16)0x0001u << SCSI_Out__8__SHIFT))\r
+\r
+#define SCSI_Out_IO_raw (SCSI_Out__IO_raw__PC)\r
+#define SCSI_Out_IO_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__9__SHIFT))\r
\r
#endif /* End Pins SCSI_Out_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************
* File Name: SCSI_Parity_Error.c
-* Version 1.80
+* Version 1.90
*
* Description:
* This file contains API to enable firmware to read the value of a Status
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
void SCSI_Parity_Error_WriteMask(uint8 mask)
{
#if(SCSI_Parity_Error_INPUTS < 8u)
- mask &= (uint8)((((uint8)1u) << SCSI_Parity_Error_INPUTS) - 1u);
+ mask &= ((uint8)(1u << SCSI_Parity_Error_INPUTS) - 1u);
#endif /* End SCSI_Parity_Error_INPUTS < 8u */
SCSI_Parity_Error_Status_Mask = mask;
}
/*******************************************************************************
* File Name: SCSI_Parity_Error.h
-* Version 1.80
+* Version 1.90
*
* Description:
* This file containts Status Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "cytypes.h"
#include "CyLib.h"
+
+/***************************************
+* Data Struct Definitions
+***************************************/
+
+/* Sleep Mode API Support */
+typedef struct
+{
+ uint8 statusState;
+
+} SCSI_Parity_Error_BACKUP_STRUCT;
+
/***************************************
* Function Prototypes
/*******************************************************************************\r
* File Name: SDCard.c\r
-* Version 2.40\r
+* Version 2.50\r
*\r
* Description:\r
* This file provides all API functionality of the SPI Master component.\r
* None.\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#include "SDCard_PVT.h"\r
\r
#if(SDCard_TX_SOFTWARE_BUF_ENABLED)\r
- volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] = {0u};\r
+ volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE];\r
volatile uint8 SDCard_txBufferFull;\r
volatile uint8 SDCard_txBufferRead;\r
volatile uint8 SDCard_txBufferWrite;\r
#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */\r
\r
#if(SDCard_RX_SOFTWARE_BUF_ENABLED)\r
- volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] = {0u};\r
+ volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE];\r
volatile uint8 SDCard_rxBufferFull;\r
volatile uint8 SDCard_rxBufferRead;\r
volatile uint8 SDCard_rxBufferWrite;\r
if((SDCard_txBufferRead == SDCard_txBufferWrite) &&\r
(0u != (SDCard_swStatusTx & SDCard_STS_TX_FIFO_NOT_FULL)))\r
{\r
- /* Add directly to the TX FIFO */\r
+ /* Put data element into the TX FIFO */\r
CY_SET_REG8(SDCard_TXDATA_PTR, txData);\r
}\r
else\r
SDCard_EnableTxInt();\r
\r
#else\r
-\r
+ /* Wait until TX FIFO has a place */\r
while(0u == (SDCard_TX_STATUS_REG & SDCard_STS_TX_FIFO_NOT_FULL))\r
{\r
- ; /* Wait for room in FIFO */\r
}\r
\r
- /* Put byte in TX FIFO */\r
+ /* Put data element into the TX FIFO */\r
CY_SET_REG8(SDCard_TXDATA_PTR, txData);\r
\r
#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */\r
/*******************************************************************************\r
* File Name: SDCard.h\r
-* Version 2.40\r
+* Version 2.50\r
*\r
* Description:\r
* Contains the function prototypes, constants and register definition\r
* None\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
/* Check to see if required defines such as CY_PSOC5A are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5A)\r
- #error Component SPI_Master_v2_40 requires cy_boot v3.0 or later\r
+ #error Component SPI_Master_v2_50 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5A) */\r
\r
\r
{\r
uint8 enableState;\r
uint8 cntrPeriod;\r
- #if(CY_UDB_V0)\r
- uint8 saveSrTxIntMask;\r
- uint8 saveSrRxIntMask;\r
- #endif /* (CY_UDB_V0) */\r
-\r
} SDCard_BACKUP_STRUCT;\r
\r
\r
CY_ISR_PROTO(SDCard_RX_ISR);\r
\r
\r
-/**********************************\r
+/***************************************\r
* Variable with external linkage\r
-**********************************/\r
+***************************************/\r
\r
extern uint8 SDCard_initVar;\r
\r
/***************************************\r
* Registers\r
***************************************/\r
-\r
#if(CY_PSOC3 || CY_PSOC5)\r
#define SDCard_TXDATA_REG (* (reg8 *) \\r
SDCard_BSPIM_sR8_Dp_u0__F0_REG)\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG)\r
#define SDCard_RXDATA_REG (* (reg16 *) \\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG)\r
- #define SDCard_RXDATA_PTR ( (reg16 *) \\r
+ #define SDCard_RXDATA_PTR ( (reg16 *) \\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG)\r
#else\r
#define SDCard_TXDATA_REG (* (reg8 *) \\r
#define SDCard_RX_STATUS_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG)\r
\r
#define SDCard_CONTROL_REG (* (reg8 *) \\r
- SDCard_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)\r
+ SDCard_BSPIM_BidirMode_CtrlReg__CONTROL_REG)\r
#define SDCard_CONTROL_PTR ( (reg8 *) \\r
- SDCard_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)\r
+ SDCard_BSPIM_BidirMode_CtrlReg__CONTROL_REG)\r
\r
#define SDCard_TX_STATUS_MASK_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG)\r
#define SDCard_TX_STATUS_MASK_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG)\r
\r
\r
/***************************************\r
-* Obsolete definitions\r
+* The following code is DEPRECATED and \r
+* should not be used in new projects.\r
***************************************/\r
\r
-/* Following definitions are for version compatibility.\r
-* They are obsolete in SPIM v2_30.\r
-* Please do not use it in new projects\r
-*/\r
-\r
#define SDCard_WriteByte SDCard_WriteTxData\r
#define SDCard_ReadByte SDCard_ReadRxData\r
void SDCard_SetInterruptMode(uint8 intSrc) ;\r
void SDCard_EnableInt(void) ;\r
void SDCard_DisableInt(void) ;\r
\r
-/* Obsolete register names. Not to be used in new designs */\r
#define SDCard_TXDATA (SDCard_TXDATA_REG)\r
#define SDCard_RXDATA (SDCard_RXDATA_REG)\r
#define SDCard_AUX_CONTROLDP0 (SDCard_AUX_CONTROL_DP0_REG)\r
SDCard_INT_ON_RX_OVER | \\r
SDCard_INT_ON_BYTE_COMP)\r
\r
-/* Following definitions are for version Compatibility.\r
-* They are obsolete in SPIM v2_40.\r
-* Please do not use it in new projects\r
-*/\r
-\r
#define SDCard_DataWidth (SDCard_DATA_WIDTH)\r
#define SDCard_InternalClockUsed (SDCard_INTERNAL_CLOCK)\r
#define SDCard_InternalTxInterruptEnabled (SDCard_INTERNAL_TX_INT_ENABLED)\r
/*******************************************************************************\r
* File Name: SDCard_INT.c\r
-* Version 2.40\r
+* Version 2.50\r
*\r
* Description:\r
* This file provides all Interrupt Service Routine (ISR) for the SPI Master\r
* None.\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#include "SDCard_PVT.h"\r
\r
+\r
/* User code required at start of ISR */\r
/* `#START SDCard_ISR_START_DEF` */\r
\r
uint8 tmpStatus;\r
#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */\r
\r
+ #ifdef SDCard_TX_ISR_ENTRY_CALLBACK\r
+ SDCard_TX_ISR_EntryCallback();\r
+ #endif /* SDCard_TX_ISR_ENTRY_CALLBACK */\r
+\r
/* User code required at start of ISR */\r
/* `#START SDCard_TX_ISR_START` */\r
\r
/* `#END` */\r
-\r
+ \r
#if(SDCard_TX_SOFTWARE_BUF_ENABLED)\r
/* Check if TX data buffer is not empty and there is space in TX FIFO */\r
while(SDCard_txBufferRead != SDCard_txBufferWrite)\r
SDCard_txBufferFull = 0u;\r
}\r
\r
- /* Move data from the Buffer to the FIFO */\r
- CY_SET_REG8(SDCard_TXDATA_PTR,\r
- SDCard_txBuffer[SDCard_txBufferRead]);\r
+ /* Put data element into the TX FIFO */\r
+ CY_SET_REG8(SDCard_TXDATA_PTR, \r
+ SDCard_txBuffer[SDCard_txBufferRead]);\r
}\r
else\r
{\r
/* `#START SDCard_TX_ISR_END` */\r
\r
/* `#END` */\r
+ \r
+ #ifdef SDCard_TX_ISR_EXIT_CALLBACK\r
+ SDCard_TX_ISR_ExitCallback();\r
+ #endif /* SDCard_TX_ISR_EXIT_CALLBACK */\r
}\r
\r
\r
uint8 rxData;\r
#endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */\r
\r
+ #ifdef SDCard_RX_ISR_ENTRY_CALLBACK\r
+ SDCard_RX_ISR_EntryCallback();\r
+ #endif /* SDCard_RX_ISR_ENTRY_CALLBACK */\r
+\r
/* User code required at start of ISR */\r
/* `#START SDCard_RX_ISR_START` */\r
\r
/* `#END` */\r
-\r
+ \r
#if(SDCard_RX_SOFTWARE_BUF_ENABLED)\r
\r
tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx);\r
/* `#START SDCard_RX_ISR_END` */\r
\r
/* `#END` */\r
+ \r
+ #ifdef SDCard_RX_ISR_EXIT_CALLBACK\r
+ SDCard_RX_ISR_ExitCallback();\r
+ #endif /* SDCard_RX_ISR_EXIT_CALLBACK */\r
}\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SDCard_PM.c\r
-* Version 2.40\r
+* Version 2.50\r
*\r
* Description:\r
* This file contains the setup, control and status commands to support\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
{\r
SDCard_DISABLED,\r
SDCard_BITCTR_INIT,\r
- #if(CY_UDB_V0)\r
- SDCard_TX_INIT_INTERRUPTS_MASK,\r
- SDCard_RX_INIT_INTERRUPTS_MASK\r
- #endif /* CY_UDB_V0 */\r
};\r
\r
\r
********************************************************************************\r
*\r
* Summary:\r
-* Saves SPIM configuration.\r
+* Empty function. Included for consistency with other components.\r
*\r
* Parameters:\r
* None.\r
* Return:\r
* None.\r
*\r
-* Global Variables:\r
-* SDCard_backup - modified when non-retention registers are saved.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
*******************************************************************************/\r
void SDCard_SaveConfig(void) \r
{\r
- /* Store Status Mask registers */\r
- #if(CY_UDB_V0)\r
- SDCard_backup.cntrPeriod = SDCard_COUNTER_PERIOD_REG;\r
- SDCard_backup.saveSrTxIntMask = SDCard_TX_STATUS_MASK_REG;\r
- SDCard_backup.saveSrRxIntMask = SDCard_RX_STATUS_MASK_REG;\r
- #endif /* (CY_UDB_V0) */\r
+\r
}\r
\r
\r
********************************************************************************\r
*\r
* Summary:\r
-* Restores SPIM configuration.\r
+* Empty function. Included for consistency with other components.\r
*\r
* Parameters:\r
* None.\r
* Return:\r
* None.\r
*\r
-* Global Variables:\r
-* SDCard_backup - used when non-retention registers are restored.\r
-*\r
-* Side Effects:\r
-* If this API is called without first calling SaveConfig then in the following\r
-* registers will be default values from Customizer:\r
-* SDCard_STATUS_MASK_REG and SDCard_COUNTER_PERIOD_REG.\r
-*\r
*******************************************************************************/\r
void SDCard_RestoreConfig(void) \r
{\r
- /* Restore the data, saved by SaveConfig() function */\r
- #if(CY_UDB_V0)\r
- SDCard_COUNTER_PERIOD_REG = SDCard_backup.cntrPeriod;\r
- SDCard_TX_STATUS_MASK_REG = ((uint8) SDCard_backup.saveSrTxIntMask);\r
- SDCard_RX_STATUS_MASK_REG = ((uint8) SDCard_backup.saveSrRxIntMask);\r
- #endif /* (CY_UDB_V0) */\r
+\r
}\r
\r
\r
SDCard_backup.enableState = ((uint8) SDCard_IS_ENABLED);\r
\r
SDCard_Stop();\r
- SDCard_SaveConfig();\r
}\r
\r
\r
*******************************************************************************/\r
void SDCard_Wakeup(void) \r
{\r
- SDCard_RestoreConfig();\r
-\r
#if(SDCard_RX_SOFTWARE_BUF_ENABLED)\r
SDCard_rxBufferFull = 0u;\r
SDCard_rxBufferRead = 0u;\r
/*******************************************************************************\r
* File Name: .h\r
-* Version 2.40\r
+* Version 2.50\r
*\r
* Description:\r
* This private header file contains internal definitions for the SPIM\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2012-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: SD_CD.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: SD_CD_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_CD_SUT.c usage_SD_CD_Write\r
*******************************************************************************/\r
-void SD_CD_Write(uint8 value) \r
+void SD_CD_Write(uint8 value)\r
{\r
uint8 staticBits = (SD_CD_DR & (uint8)(~SD_CD_MASK));\r
SD_CD_DR = staticBits | ((uint8)(value << SD_CD_SHIFT) & SD_CD_MASK);\r
\r
/*******************************************************************************\r
* Function Name: SD_CD_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* SD_CD_DM_STRONG Strong Drive \r
-* SD_CD_DM_OD_HI Open Drain, Drives High \r
-* SD_CD_DM_OD_LO Open Drain, Drives Low \r
-* SD_CD_DM_RES_UP Resistive Pull Up \r
-* SD_CD_DM_RES_DWN Resistive Pull Down \r
-* SD_CD_DM_RES_UPDWN Resistive Pull Up/Down \r
-* SD_CD_DM_DIG_HIZ High Impedance Digital \r
-* SD_CD_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_CD_SUT.c usage_SD_CD_SetDriveMode\r
*******************************************************************************/\r
-void SD_CD_SetDriveMode(uint8 mode) \r
+void SD_CD_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(SD_CD_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_CD_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro SD_CD_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet SD_CD_SUT.c usage_SD_CD_Read \r
*******************************************************************************/\r
-uint8 SD_CD_Read(void) \r
+uint8 SD_CD_Read(void)\r
{\r
return (SD_CD_PS & SD_CD_MASK) >> SD_CD_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_CD_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred SD_CD_Read() API because the \r
+* SD_CD_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet SD_CD_SUT.c usage_SD_CD_ReadDataReg \r
*******************************************************************************/\r
-uint8 SD_CD_ReadDataReg(void) \r
+uint8 SD_CD_ReadDataReg(void)\r
{\r
return (SD_CD_DR & SD_CD_MASK) >> SD_CD_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(SD_CD_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: SD_CD_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use SD_CD_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - SD_CD_0_INTR (First pin in the list)\r
+ * - SD_CD_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - SD_CD_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_CD_SUT.c usage_SD_CD_SetInterruptMode\r
+ *******************************************************************************/\r
+ void SD_CD_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & SD_CD_0_INTR) != 0u) \r
+ { \r
+ SD_CD_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: SD_CD_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_CD_SUT.c usage_SD_CD_ClearInterrupt\r
*******************************************************************************/\r
- uint8 SD_CD_ClearInterrupt(void) \r
+ uint8 SD_CD_ClearInterrupt(void)\r
{\r
return (SD_CD_INTSTAT & SD_CD_MASK) >> SD_CD_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: SD_CD.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "SD_CD_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
SD_CD__PORT == 15 && ((SD_CD__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void SD_CD_Write(uint8 value) ;\r
-void SD_CD_SetDriveMode(uint8 mode) ;\r
-uint8 SD_CD_ReadDataReg(void) ;\r
-uint8 SD_CD_Read(void) ;\r
-uint8 SD_CD_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void SD_CD_Write(uint8 value);\r
+void SD_CD_SetDriveMode(uint8 mode);\r
+uint8 SD_CD_ReadDataReg(void);\r
+uint8 SD_CD_Read(void);\r
+void SD_CD_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 SD_CD_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define SD_CD_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define SD_CD_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define SD_CD_DM_RES_UP PIN_DM_RES_UP\r
-#define SD_CD_DM_RES_DWN PIN_DM_RES_DWN\r
-#define SD_CD_DM_OD_LO PIN_DM_OD_LO\r
-#define SD_CD_DM_OD_HI PIN_DM_OD_HI\r
-#define SD_CD_DM_STRONG PIN_DM_STRONG\r
-#define SD_CD_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the SD_CD_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define SD_CD_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define SD_CD_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define SD_CD_DM_RES_UP PIN_DM_RES_UP\r
+ #define SD_CD_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define SD_CD_DM_OD_LO PIN_DM_OD_LO\r
+ #define SD_CD_DM_OD_HI PIN_DM_OD_HI\r
+ #define SD_CD_DM_STRONG PIN_DM_STRONG\r
+ #define SD_CD_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define SD_CD_MASK SD_CD__MASK\r
#define SD_CD_SHIFT SD_CD__SHIFT\r
#define SD_CD_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(SD_CD__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in SD_CD_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define SD_CD_INTR_NONE (uint16)(0x0000u)\r
+ #define SD_CD_INTR_RISING (uint16)(0x0001u)\r
+ #define SD_CD_INTR_FALLING (uint16)(0x0002u)\r
+ #define SD_CD_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define SD_CD_INTR_MASK (0x01u) \r
+#endif /* (SD_CD__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define SD_CD_PRTDSI__SYNC_OUT (* (reg8 *) SD_CD__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(SD_CD__INTSTAT) /* Interrupt Registers */\r
-\r
- #define SD_CD_INTSTAT (* (reg8 *) SD_CD__INTSTAT)\r
- #define SD_CD_SNAP (* (reg8 *) SD_CD__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(SD_CD__SIO_CFG)\r
+ #define SD_CD_SIO_HYST_EN (* (reg8 *) SD_CD__SIO_HYST_EN)\r
+ #define SD_CD_SIO_REG_HIFREQ (* (reg8 *) SD_CD__SIO_REG_HIFREQ)\r
+ #define SD_CD_SIO_CFG (* (reg8 *) SD_CD__SIO_CFG)\r
+ #define SD_CD_SIO_DIFF (* (reg8 *) SD_CD__SIO_DIFF)\r
+#endif /* (SD_CD__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(SD_CD__INTSTAT)\r
+ #define SD_CD_INTSTAT (* (reg8 *) SD_CD__INTSTAT)\r
+ #define SD_CD_SNAP (* (reg8 *) SD_CD__SNAP)\r
+ \r
+ #define SD_CD_0_INTTYPE_REG (* (reg8 *) SD_CD__0__INTTYPE)\r
+#endif /* (SD_CD__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: SD_CD.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_CD_0 (SD_CD__0__PC)\r
+#define SD_CD_0 (SD_CD__0__PC)\r
+#define SD_CD_0_INTR ((uint16)((uint16)0x0001u << SD_CD__0__SHIFT))\r
+\r
+#define SD_CD_INTR_ALL ((uint16)(SD_CD_0_INTR))\r
\r
#endif /* End Pins SD_CD_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SD_CS.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: SD_CS_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_CS_SUT.c usage_SD_CS_Write\r
*******************************************************************************/\r
-void SD_CS_Write(uint8 value) \r
+void SD_CS_Write(uint8 value)\r
{\r
uint8 staticBits = (SD_CS_DR & (uint8)(~SD_CS_MASK));\r
SD_CS_DR = staticBits | ((uint8)(value << SD_CS_SHIFT) & SD_CS_MASK);\r
\r
/*******************************************************************************\r
* Function Name: SD_CS_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* SD_CS_DM_STRONG Strong Drive \r
-* SD_CS_DM_OD_HI Open Drain, Drives High \r
-* SD_CS_DM_OD_LO Open Drain, Drives Low \r
-* SD_CS_DM_RES_UP Resistive Pull Up \r
-* SD_CS_DM_RES_DWN Resistive Pull Down \r
-* SD_CS_DM_RES_UPDWN Resistive Pull Up/Down \r
-* SD_CS_DM_DIG_HIZ High Impedance Digital \r
-* SD_CS_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_CS_SUT.c usage_SD_CS_SetDriveMode\r
*******************************************************************************/\r
-void SD_CS_SetDriveMode(uint8 mode) \r
+void SD_CS_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(SD_CS_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_CS_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro SD_CS_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet SD_CS_SUT.c usage_SD_CS_Read \r
*******************************************************************************/\r
-uint8 SD_CS_Read(void) \r
+uint8 SD_CS_Read(void)\r
{\r
return (SD_CS_PS & SD_CS_MASK) >> SD_CS_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_CS_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred SD_CS_Read() API because the \r
+* SD_CS_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet SD_CS_SUT.c usage_SD_CS_ReadDataReg \r
*******************************************************************************/\r
-uint8 SD_CS_ReadDataReg(void) \r
+uint8 SD_CS_ReadDataReg(void)\r
{\r
return (SD_CS_DR & SD_CS_MASK) >> SD_CS_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(SD_CS_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: SD_CS_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use SD_CS_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - SD_CS_0_INTR (First pin in the list)\r
+ * - SD_CS_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - SD_CS_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_CS_SUT.c usage_SD_CS_SetInterruptMode\r
+ *******************************************************************************/\r
+ void SD_CS_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & SD_CS_0_INTR) != 0u) \r
+ { \r
+ SD_CS_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: SD_CS_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_CS_SUT.c usage_SD_CS_ClearInterrupt\r
*******************************************************************************/\r
- uint8 SD_CS_ClearInterrupt(void) \r
+ uint8 SD_CS_ClearInterrupt(void)\r
{\r
return (SD_CS_INTSTAT & SD_CS_MASK) >> SD_CS_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: SD_CS.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "SD_CS_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
SD_CS__PORT == 15 && ((SD_CS__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void SD_CS_Write(uint8 value) ;\r
-void SD_CS_SetDriveMode(uint8 mode) ;\r
-uint8 SD_CS_ReadDataReg(void) ;\r
-uint8 SD_CS_Read(void) ;\r
-uint8 SD_CS_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void SD_CS_Write(uint8 value);\r
+void SD_CS_SetDriveMode(uint8 mode);\r
+uint8 SD_CS_ReadDataReg(void);\r
+uint8 SD_CS_Read(void);\r
+void SD_CS_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 SD_CS_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define SD_CS_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define SD_CS_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define SD_CS_DM_RES_UP PIN_DM_RES_UP\r
-#define SD_CS_DM_RES_DWN PIN_DM_RES_DWN\r
-#define SD_CS_DM_OD_LO PIN_DM_OD_LO\r
-#define SD_CS_DM_OD_HI PIN_DM_OD_HI\r
-#define SD_CS_DM_STRONG PIN_DM_STRONG\r
-#define SD_CS_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the SD_CS_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define SD_CS_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define SD_CS_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define SD_CS_DM_RES_UP PIN_DM_RES_UP\r
+ #define SD_CS_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define SD_CS_DM_OD_LO PIN_DM_OD_LO\r
+ #define SD_CS_DM_OD_HI PIN_DM_OD_HI\r
+ #define SD_CS_DM_STRONG PIN_DM_STRONG\r
+ #define SD_CS_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define SD_CS_MASK SD_CS__MASK\r
#define SD_CS_SHIFT SD_CS__SHIFT\r
#define SD_CS_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(SD_CS__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in SD_CS_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define SD_CS_INTR_NONE (uint16)(0x0000u)\r
+ #define SD_CS_INTR_RISING (uint16)(0x0001u)\r
+ #define SD_CS_INTR_FALLING (uint16)(0x0002u)\r
+ #define SD_CS_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define SD_CS_INTR_MASK (0x01u) \r
+#endif /* (SD_CS__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define SD_CS_PRTDSI__SYNC_OUT (* (reg8 *) SD_CS__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(SD_CS__INTSTAT) /* Interrupt Registers */\r
-\r
- #define SD_CS_INTSTAT (* (reg8 *) SD_CS__INTSTAT)\r
- #define SD_CS_SNAP (* (reg8 *) SD_CS__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(SD_CS__SIO_CFG)\r
+ #define SD_CS_SIO_HYST_EN (* (reg8 *) SD_CS__SIO_HYST_EN)\r
+ #define SD_CS_SIO_REG_HIFREQ (* (reg8 *) SD_CS__SIO_REG_HIFREQ)\r
+ #define SD_CS_SIO_CFG (* (reg8 *) SD_CS__SIO_CFG)\r
+ #define SD_CS_SIO_DIFF (* (reg8 *) SD_CS__SIO_DIFF)\r
+#endif /* (SD_CS__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(SD_CS__INTSTAT)\r
+ #define SD_CS_INTSTAT (* (reg8 *) SD_CS__INTSTAT)\r
+ #define SD_CS_SNAP (* (reg8 *) SD_CS__SNAP)\r
+ \r
+ #define SD_CS_0_INTTYPE_REG (* (reg8 *) SD_CS__0__INTTYPE)\r
+#endif /* (SD_CS__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: SD_CS.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_CS_0 (SD_CS__0__PC)\r
+#define SD_CS_0 (SD_CS__0__PC)\r
+#define SD_CS_0_INTR ((uint16)((uint16)0x0001u << SD_CS__0__SHIFT))\r
+\r
+#define SD_CS_INTR_ALL ((uint16)(SD_CS_0_INTR))\r
\r
#endif /* End Pins SD_CS_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SD_DAT1.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: SD_DAT1_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_DAT1_SUT.c usage_SD_DAT1_Write\r
*******************************************************************************/\r
-void SD_DAT1_Write(uint8 value) \r
+void SD_DAT1_Write(uint8 value)\r
{\r
uint8 staticBits = (SD_DAT1_DR & (uint8)(~SD_DAT1_MASK));\r
SD_DAT1_DR = staticBits | ((uint8)(value << SD_DAT1_SHIFT) & SD_DAT1_MASK);\r
\r
/*******************************************************************************\r
* Function Name: SD_DAT1_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* SD_DAT1_DM_STRONG Strong Drive \r
-* SD_DAT1_DM_OD_HI Open Drain, Drives High \r
-* SD_DAT1_DM_OD_LO Open Drain, Drives Low \r
-* SD_DAT1_DM_RES_UP Resistive Pull Up \r
-* SD_DAT1_DM_RES_DWN Resistive Pull Down \r
-* SD_DAT1_DM_RES_UPDWN Resistive Pull Up/Down \r
-* SD_DAT1_DM_DIG_HIZ High Impedance Digital \r
-* SD_DAT1_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_DAT1_SUT.c usage_SD_DAT1_SetDriveMode\r
*******************************************************************************/\r
-void SD_DAT1_SetDriveMode(uint8 mode) \r
+void SD_DAT1_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(SD_DAT1_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_DAT1_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro SD_DAT1_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet SD_DAT1_SUT.c usage_SD_DAT1_Read \r
*******************************************************************************/\r
-uint8 SD_DAT1_Read(void) \r
+uint8 SD_DAT1_Read(void)\r
{\r
return (SD_DAT1_PS & SD_DAT1_MASK) >> SD_DAT1_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_DAT1_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred SD_DAT1_Read() API because the \r
+* SD_DAT1_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet SD_DAT1_SUT.c usage_SD_DAT1_ReadDataReg \r
*******************************************************************************/\r
-uint8 SD_DAT1_ReadDataReg(void) \r
+uint8 SD_DAT1_ReadDataReg(void)\r
{\r
return (SD_DAT1_DR & SD_DAT1_MASK) >> SD_DAT1_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(SD_DAT1_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: SD_DAT1_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use SD_DAT1_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - SD_DAT1_0_INTR (First pin in the list)\r
+ * - SD_DAT1_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - SD_DAT1_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_DAT1_SUT.c usage_SD_DAT1_SetInterruptMode\r
+ *******************************************************************************/\r
+ void SD_DAT1_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & SD_DAT1_0_INTR) != 0u) \r
+ { \r
+ SD_DAT1_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: SD_DAT1_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_DAT1_SUT.c usage_SD_DAT1_ClearInterrupt\r
*******************************************************************************/\r
- uint8 SD_DAT1_ClearInterrupt(void) \r
+ uint8 SD_DAT1_ClearInterrupt(void)\r
{\r
return (SD_DAT1_INTSTAT & SD_DAT1_MASK) >> SD_DAT1_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: SD_DAT1.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "SD_DAT1_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
SD_DAT1__PORT == 15 && ((SD_DAT1__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void SD_DAT1_Write(uint8 value) ;\r
-void SD_DAT1_SetDriveMode(uint8 mode) ;\r
-uint8 SD_DAT1_ReadDataReg(void) ;\r
-uint8 SD_DAT1_Read(void) ;\r
-uint8 SD_DAT1_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void SD_DAT1_Write(uint8 value);\r
+void SD_DAT1_SetDriveMode(uint8 mode);\r
+uint8 SD_DAT1_ReadDataReg(void);\r
+uint8 SD_DAT1_Read(void);\r
+void SD_DAT1_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 SD_DAT1_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define SD_DAT1_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define SD_DAT1_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define SD_DAT1_DM_RES_UP PIN_DM_RES_UP\r
-#define SD_DAT1_DM_RES_DWN PIN_DM_RES_DWN\r
-#define SD_DAT1_DM_OD_LO PIN_DM_OD_LO\r
-#define SD_DAT1_DM_OD_HI PIN_DM_OD_HI\r
-#define SD_DAT1_DM_STRONG PIN_DM_STRONG\r
-#define SD_DAT1_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the SD_DAT1_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define SD_DAT1_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define SD_DAT1_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define SD_DAT1_DM_RES_UP PIN_DM_RES_UP\r
+ #define SD_DAT1_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define SD_DAT1_DM_OD_LO PIN_DM_OD_LO\r
+ #define SD_DAT1_DM_OD_HI PIN_DM_OD_HI\r
+ #define SD_DAT1_DM_STRONG PIN_DM_STRONG\r
+ #define SD_DAT1_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define SD_DAT1_MASK SD_DAT1__MASK\r
#define SD_DAT1_SHIFT SD_DAT1__SHIFT\r
#define SD_DAT1_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(SD_DAT1__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in SD_DAT1_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define SD_DAT1_INTR_NONE (uint16)(0x0000u)\r
+ #define SD_DAT1_INTR_RISING (uint16)(0x0001u)\r
+ #define SD_DAT1_INTR_FALLING (uint16)(0x0002u)\r
+ #define SD_DAT1_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define SD_DAT1_INTR_MASK (0x01u) \r
+#endif /* (SD_DAT1__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define SD_DAT1_PRTDSI__SYNC_OUT (* (reg8 *) SD_DAT1__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(SD_DAT1__INTSTAT) /* Interrupt Registers */\r
-\r
- #define SD_DAT1_INTSTAT (* (reg8 *) SD_DAT1__INTSTAT)\r
- #define SD_DAT1_SNAP (* (reg8 *) SD_DAT1__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(SD_DAT1__SIO_CFG)\r
+ #define SD_DAT1_SIO_HYST_EN (* (reg8 *) SD_DAT1__SIO_HYST_EN)\r
+ #define SD_DAT1_SIO_REG_HIFREQ (* (reg8 *) SD_DAT1__SIO_REG_HIFREQ)\r
+ #define SD_DAT1_SIO_CFG (* (reg8 *) SD_DAT1__SIO_CFG)\r
+ #define SD_DAT1_SIO_DIFF (* (reg8 *) SD_DAT1__SIO_DIFF)\r
+#endif /* (SD_DAT1__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(SD_DAT1__INTSTAT)\r
+ #define SD_DAT1_INTSTAT (* (reg8 *) SD_DAT1__INTSTAT)\r
+ #define SD_DAT1_SNAP (* (reg8 *) SD_DAT1__SNAP)\r
+ \r
+ #define SD_DAT1_0_INTTYPE_REG (* (reg8 *) SD_DAT1__0__INTTYPE)\r
+#endif /* (SD_DAT1__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: SD_DAT1.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_DAT1_0 (SD_DAT1__0__PC)\r
+#define SD_DAT1_0 (SD_DAT1__0__PC)\r
+#define SD_DAT1_0_INTR ((uint16)((uint16)0x0001u << SD_DAT1__0__SHIFT))\r
+\r
+#define SD_DAT1_INTR_ALL ((uint16)(SD_DAT1_0_INTR))\r
\r
#endif /* End Pins SD_DAT1_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SD_DAT2.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: SD_DAT2_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_DAT2_SUT.c usage_SD_DAT2_Write\r
*******************************************************************************/\r
-void SD_DAT2_Write(uint8 value) \r
+void SD_DAT2_Write(uint8 value)\r
{\r
uint8 staticBits = (SD_DAT2_DR & (uint8)(~SD_DAT2_MASK));\r
SD_DAT2_DR = staticBits | ((uint8)(value << SD_DAT2_SHIFT) & SD_DAT2_MASK);\r
\r
/*******************************************************************************\r
* Function Name: SD_DAT2_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* SD_DAT2_DM_STRONG Strong Drive \r
-* SD_DAT2_DM_OD_HI Open Drain, Drives High \r
-* SD_DAT2_DM_OD_LO Open Drain, Drives Low \r
-* SD_DAT2_DM_RES_UP Resistive Pull Up \r
-* SD_DAT2_DM_RES_DWN Resistive Pull Down \r
-* SD_DAT2_DM_RES_UPDWN Resistive Pull Up/Down \r
-* SD_DAT2_DM_DIG_HIZ High Impedance Digital \r
-* SD_DAT2_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_DAT2_SUT.c usage_SD_DAT2_SetDriveMode\r
*******************************************************************************/\r
-void SD_DAT2_SetDriveMode(uint8 mode) \r
+void SD_DAT2_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(SD_DAT2_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_DAT2_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro SD_DAT2_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet SD_DAT2_SUT.c usage_SD_DAT2_Read \r
*******************************************************************************/\r
-uint8 SD_DAT2_Read(void) \r
+uint8 SD_DAT2_Read(void)\r
{\r
return (SD_DAT2_PS & SD_DAT2_MASK) >> SD_DAT2_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_DAT2_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred SD_DAT2_Read() API because the \r
+* SD_DAT2_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet SD_DAT2_SUT.c usage_SD_DAT2_ReadDataReg \r
*******************************************************************************/\r
-uint8 SD_DAT2_ReadDataReg(void) \r
+uint8 SD_DAT2_ReadDataReg(void)\r
{\r
return (SD_DAT2_DR & SD_DAT2_MASK) >> SD_DAT2_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(SD_DAT2_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: SD_DAT2_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use SD_DAT2_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - SD_DAT2_0_INTR (First pin in the list)\r
+ * - SD_DAT2_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - SD_DAT2_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_DAT2_SUT.c usage_SD_DAT2_SetInterruptMode\r
+ *******************************************************************************/\r
+ void SD_DAT2_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & SD_DAT2_0_INTR) != 0u) \r
+ { \r
+ SD_DAT2_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: SD_DAT2_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_DAT2_SUT.c usage_SD_DAT2_ClearInterrupt\r
*******************************************************************************/\r
- uint8 SD_DAT2_ClearInterrupt(void) \r
+ uint8 SD_DAT2_ClearInterrupt(void)\r
{\r
return (SD_DAT2_INTSTAT & SD_DAT2_MASK) >> SD_DAT2_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: SD_DAT2.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "SD_DAT2_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
SD_DAT2__PORT == 15 && ((SD_DAT2__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void SD_DAT2_Write(uint8 value) ;\r
-void SD_DAT2_SetDriveMode(uint8 mode) ;\r
-uint8 SD_DAT2_ReadDataReg(void) ;\r
-uint8 SD_DAT2_Read(void) ;\r
-uint8 SD_DAT2_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void SD_DAT2_Write(uint8 value);\r
+void SD_DAT2_SetDriveMode(uint8 mode);\r
+uint8 SD_DAT2_ReadDataReg(void);\r
+uint8 SD_DAT2_Read(void);\r
+void SD_DAT2_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 SD_DAT2_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define SD_DAT2_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define SD_DAT2_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define SD_DAT2_DM_RES_UP PIN_DM_RES_UP\r
-#define SD_DAT2_DM_RES_DWN PIN_DM_RES_DWN\r
-#define SD_DAT2_DM_OD_LO PIN_DM_OD_LO\r
-#define SD_DAT2_DM_OD_HI PIN_DM_OD_HI\r
-#define SD_DAT2_DM_STRONG PIN_DM_STRONG\r
-#define SD_DAT2_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the SD_DAT2_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define SD_DAT2_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define SD_DAT2_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define SD_DAT2_DM_RES_UP PIN_DM_RES_UP\r
+ #define SD_DAT2_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define SD_DAT2_DM_OD_LO PIN_DM_OD_LO\r
+ #define SD_DAT2_DM_OD_HI PIN_DM_OD_HI\r
+ #define SD_DAT2_DM_STRONG PIN_DM_STRONG\r
+ #define SD_DAT2_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define SD_DAT2_MASK SD_DAT2__MASK\r
#define SD_DAT2_SHIFT SD_DAT2__SHIFT\r
#define SD_DAT2_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(SD_DAT2__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in SD_DAT2_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define SD_DAT2_INTR_NONE (uint16)(0x0000u)\r
+ #define SD_DAT2_INTR_RISING (uint16)(0x0001u)\r
+ #define SD_DAT2_INTR_FALLING (uint16)(0x0002u)\r
+ #define SD_DAT2_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define SD_DAT2_INTR_MASK (0x01u) \r
+#endif /* (SD_DAT2__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define SD_DAT2_PRTDSI__SYNC_OUT (* (reg8 *) SD_DAT2__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(SD_DAT2__INTSTAT) /* Interrupt Registers */\r
-\r
- #define SD_DAT2_INTSTAT (* (reg8 *) SD_DAT2__INTSTAT)\r
- #define SD_DAT2_SNAP (* (reg8 *) SD_DAT2__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(SD_DAT2__SIO_CFG)\r
+ #define SD_DAT2_SIO_HYST_EN (* (reg8 *) SD_DAT2__SIO_HYST_EN)\r
+ #define SD_DAT2_SIO_REG_HIFREQ (* (reg8 *) SD_DAT2__SIO_REG_HIFREQ)\r
+ #define SD_DAT2_SIO_CFG (* (reg8 *) SD_DAT2__SIO_CFG)\r
+ #define SD_DAT2_SIO_DIFF (* (reg8 *) SD_DAT2__SIO_DIFF)\r
+#endif /* (SD_DAT2__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(SD_DAT2__INTSTAT)\r
+ #define SD_DAT2_INTSTAT (* (reg8 *) SD_DAT2__INTSTAT)\r
+ #define SD_DAT2_SNAP (* (reg8 *) SD_DAT2__SNAP)\r
+ \r
+ #define SD_DAT2_0_INTTYPE_REG (* (reg8 *) SD_DAT2__0__INTTYPE)\r
+#endif /* (SD_DAT2__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: SD_DAT2.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_DAT2_0 (SD_DAT2__0__PC)\r
+#define SD_DAT2_0 (SD_DAT2__0__PC)\r
+#define SD_DAT2_0_INTR ((uint16)((uint16)0x0001u << SD_DAT2__0__SHIFT))\r
+\r
+#define SD_DAT2_INTR_ALL ((uint16)(SD_DAT2_0_INTR))\r
\r
#endif /* End Pins SD_DAT2_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SD_MISO.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: SD_MISO_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_MISO_SUT.c usage_SD_MISO_Write\r
*******************************************************************************/\r
-void SD_MISO_Write(uint8 value) \r
+void SD_MISO_Write(uint8 value)\r
{\r
uint8 staticBits = (SD_MISO_DR & (uint8)(~SD_MISO_MASK));\r
SD_MISO_DR = staticBits | ((uint8)(value << SD_MISO_SHIFT) & SD_MISO_MASK);\r
\r
/*******************************************************************************\r
* Function Name: SD_MISO_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* SD_MISO_DM_STRONG Strong Drive \r
-* SD_MISO_DM_OD_HI Open Drain, Drives High \r
-* SD_MISO_DM_OD_LO Open Drain, Drives Low \r
-* SD_MISO_DM_RES_UP Resistive Pull Up \r
-* SD_MISO_DM_RES_DWN Resistive Pull Down \r
-* SD_MISO_DM_RES_UPDWN Resistive Pull Up/Down \r
-* SD_MISO_DM_DIG_HIZ High Impedance Digital \r
-* SD_MISO_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_MISO_SUT.c usage_SD_MISO_SetDriveMode\r
*******************************************************************************/\r
-void SD_MISO_SetDriveMode(uint8 mode) \r
+void SD_MISO_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(SD_MISO_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_MISO_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro SD_MISO_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet SD_MISO_SUT.c usage_SD_MISO_Read \r
*******************************************************************************/\r
-uint8 SD_MISO_Read(void) \r
+uint8 SD_MISO_Read(void)\r
{\r
return (SD_MISO_PS & SD_MISO_MASK) >> SD_MISO_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_MISO_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred SD_MISO_Read() API because the \r
+* SD_MISO_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet SD_MISO_SUT.c usage_SD_MISO_ReadDataReg \r
*******************************************************************************/\r
-uint8 SD_MISO_ReadDataReg(void) \r
+uint8 SD_MISO_ReadDataReg(void)\r
{\r
return (SD_MISO_DR & SD_MISO_MASK) >> SD_MISO_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(SD_MISO_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: SD_MISO_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use SD_MISO_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - SD_MISO_0_INTR (First pin in the list)\r
+ * - SD_MISO_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - SD_MISO_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_MISO_SUT.c usage_SD_MISO_SetInterruptMode\r
+ *******************************************************************************/\r
+ void SD_MISO_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & SD_MISO_0_INTR) != 0u) \r
+ { \r
+ SD_MISO_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: SD_MISO_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_MISO_SUT.c usage_SD_MISO_ClearInterrupt\r
*******************************************************************************/\r
- uint8 SD_MISO_ClearInterrupt(void) \r
+ uint8 SD_MISO_ClearInterrupt(void)\r
{\r
return (SD_MISO_INTSTAT & SD_MISO_MASK) >> SD_MISO_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: SD_MISO.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "SD_MISO_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
SD_MISO__PORT == 15 && ((SD_MISO__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void SD_MISO_Write(uint8 value) ;\r
-void SD_MISO_SetDriveMode(uint8 mode) ;\r
-uint8 SD_MISO_ReadDataReg(void) ;\r
-uint8 SD_MISO_Read(void) ;\r
-uint8 SD_MISO_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void SD_MISO_Write(uint8 value);\r
+void SD_MISO_SetDriveMode(uint8 mode);\r
+uint8 SD_MISO_ReadDataReg(void);\r
+uint8 SD_MISO_Read(void);\r
+void SD_MISO_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 SD_MISO_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define SD_MISO_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define SD_MISO_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define SD_MISO_DM_RES_UP PIN_DM_RES_UP\r
-#define SD_MISO_DM_RES_DWN PIN_DM_RES_DWN\r
-#define SD_MISO_DM_OD_LO PIN_DM_OD_LO\r
-#define SD_MISO_DM_OD_HI PIN_DM_OD_HI\r
-#define SD_MISO_DM_STRONG PIN_DM_STRONG\r
-#define SD_MISO_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the SD_MISO_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define SD_MISO_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define SD_MISO_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define SD_MISO_DM_RES_UP PIN_DM_RES_UP\r
+ #define SD_MISO_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define SD_MISO_DM_OD_LO PIN_DM_OD_LO\r
+ #define SD_MISO_DM_OD_HI PIN_DM_OD_HI\r
+ #define SD_MISO_DM_STRONG PIN_DM_STRONG\r
+ #define SD_MISO_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define SD_MISO_MASK SD_MISO__MASK\r
#define SD_MISO_SHIFT SD_MISO__SHIFT\r
#define SD_MISO_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(SD_MISO__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in SD_MISO_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define SD_MISO_INTR_NONE (uint16)(0x0000u)\r
+ #define SD_MISO_INTR_RISING (uint16)(0x0001u)\r
+ #define SD_MISO_INTR_FALLING (uint16)(0x0002u)\r
+ #define SD_MISO_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define SD_MISO_INTR_MASK (0x01u) \r
+#endif /* (SD_MISO__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define SD_MISO_PRTDSI__SYNC_OUT (* (reg8 *) SD_MISO__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(SD_MISO__INTSTAT) /* Interrupt Registers */\r
-\r
- #define SD_MISO_INTSTAT (* (reg8 *) SD_MISO__INTSTAT)\r
- #define SD_MISO_SNAP (* (reg8 *) SD_MISO__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(SD_MISO__SIO_CFG)\r
+ #define SD_MISO_SIO_HYST_EN (* (reg8 *) SD_MISO__SIO_HYST_EN)\r
+ #define SD_MISO_SIO_REG_HIFREQ (* (reg8 *) SD_MISO__SIO_REG_HIFREQ)\r
+ #define SD_MISO_SIO_CFG (* (reg8 *) SD_MISO__SIO_CFG)\r
+ #define SD_MISO_SIO_DIFF (* (reg8 *) SD_MISO__SIO_DIFF)\r
+#endif /* (SD_MISO__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(SD_MISO__INTSTAT)\r
+ #define SD_MISO_INTSTAT (* (reg8 *) SD_MISO__INTSTAT)\r
+ #define SD_MISO_SNAP (* (reg8 *) SD_MISO__SNAP)\r
+ \r
+ #define SD_MISO_0_INTTYPE_REG (* (reg8 *) SD_MISO__0__INTTYPE)\r
+#endif /* (SD_MISO__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: SD_MISO.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_MISO_0 (SD_MISO__0__PC)\r
+#define SD_MISO_0 (SD_MISO__0__PC)\r
+#define SD_MISO_0_INTR ((uint16)((uint16)0x0001u << SD_MISO__0__SHIFT))\r
+\r
+#define SD_MISO_INTR_ALL ((uint16)(SD_MISO_0_INTR))\r
\r
#endif /* End Pins SD_MISO_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SD_MOSI.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: SD_MOSI_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_MOSI_SUT.c usage_SD_MOSI_Write\r
*******************************************************************************/\r
-void SD_MOSI_Write(uint8 value) \r
+void SD_MOSI_Write(uint8 value)\r
{\r
uint8 staticBits = (SD_MOSI_DR & (uint8)(~SD_MOSI_MASK));\r
SD_MOSI_DR = staticBits | ((uint8)(value << SD_MOSI_SHIFT) & SD_MOSI_MASK);\r
\r
/*******************************************************************************\r
* Function Name: SD_MOSI_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* SD_MOSI_DM_STRONG Strong Drive \r
-* SD_MOSI_DM_OD_HI Open Drain, Drives High \r
-* SD_MOSI_DM_OD_LO Open Drain, Drives Low \r
-* SD_MOSI_DM_RES_UP Resistive Pull Up \r
-* SD_MOSI_DM_RES_DWN Resistive Pull Down \r
-* SD_MOSI_DM_RES_UPDWN Resistive Pull Up/Down \r
-* SD_MOSI_DM_DIG_HIZ High Impedance Digital \r
-* SD_MOSI_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_MOSI_SUT.c usage_SD_MOSI_SetDriveMode\r
*******************************************************************************/\r
-void SD_MOSI_SetDriveMode(uint8 mode) \r
+void SD_MOSI_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(SD_MOSI_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_MOSI_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro SD_MOSI_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet SD_MOSI_SUT.c usage_SD_MOSI_Read \r
*******************************************************************************/\r
-uint8 SD_MOSI_Read(void) \r
+uint8 SD_MOSI_Read(void)\r
{\r
return (SD_MOSI_PS & SD_MOSI_MASK) >> SD_MOSI_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_MOSI_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred SD_MOSI_Read() API because the \r
+* SD_MOSI_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet SD_MOSI_SUT.c usage_SD_MOSI_ReadDataReg \r
*******************************************************************************/\r
-uint8 SD_MOSI_ReadDataReg(void) \r
+uint8 SD_MOSI_ReadDataReg(void)\r
{\r
return (SD_MOSI_DR & SD_MOSI_MASK) >> SD_MOSI_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(SD_MOSI_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: SD_MOSI_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use SD_MOSI_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - SD_MOSI_0_INTR (First pin in the list)\r
+ * - SD_MOSI_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - SD_MOSI_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_MOSI_SUT.c usage_SD_MOSI_SetInterruptMode\r
+ *******************************************************************************/\r
+ void SD_MOSI_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & SD_MOSI_0_INTR) != 0u) \r
+ { \r
+ SD_MOSI_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: SD_MOSI_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_MOSI_SUT.c usage_SD_MOSI_ClearInterrupt\r
*******************************************************************************/\r
- uint8 SD_MOSI_ClearInterrupt(void) \r
+ uint8 SD_MOSI_ClearInterrupt(void)\r
{\r
return (SD_MOSI_INTSTAT & SD_MOSI_MASK) >> SD_MOSI_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: SD_MOSI.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "SD_MOSI_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
SD_MOSI__PORT == 15 && ((SD_MOSI__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void SD_MOSI_Write(uint8 value) ;\r
-void SD_MOSI_SetDriveMode(uint8 mode) ;\r
-uint8 SD_MOSI_ReadDataReg(void) ;\r
-uint8 SD_MOSI_Read(void) ;\r
-uint8 SD_MOSI_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void SD_MOSI_Write(uint8 value);\r
+void SD_MOSI_SetDriveMode(uint8 mode);\r
+uint8 SD_MOSI_ReadDataReg(void);\r
+uint8 SD_MOSI_Read(void);\r
+void SD_MOSI_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 SD_MOSI_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define SD_MOSI_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define SD_MOSI_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define SD_MOSI_DM_RES_UP PIN_DM_RES_UP\r
-#define SD_MOSI_DM_RES_DWN PIN_DM_RES_DWN\r
-#define SD_MOSI_DM_OD_LO PIN_DM_OD_LO\r
-#define SD_MOSI_DM_OD_HI PIN_DM_OD_HI\r
-#define SD_MOSI_DM_STRONG PIN_DM_STRONG\r
-#define SD_MOSI_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the SD_MOSI_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define SD_MOSI_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define SD_MOSI_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define SD_MOSI_DM_RES_UP PIN_DM_RES_UP\r
+ #define SD_MOSI_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define SD_MOSI_DM_OD_LO PIN_DM_OD_LO\r
+ #define SD_MOSI_DM_OD_HI PIN_DM_OD_HI\r
+ #define SD_MOSI_DM_STRONG PIN_DM_STRONG\r
+ #define SD_MOSI_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define SD_MOSI_MASK SD_MOSI__MASK\r
#define SD_MOSI_SHIFT SD_MOSI__SHIFT\r
#define SD_MOSI_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(SD_MOSI__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in SD_MOSI_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define SD_MOSI_INTR_NONE (uint16)(0x0000u)\r
+ #define SD_MOSI_INTR_RISING (uint16)(0x0001u)\r
+ #define SD_MOSI_INTR_FALLING (uint16)(0x0002u)\r
+ #define SD_MOSI_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define SD_MOSI_INTR_MASK (0x01u) \r
+#endif /* (SD_MOSI__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define SD_MOSI_PRTDSI__SYNC_OUT (* (reg8 *) SD_MOSI__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(SD_MOSI__INTSTAT) /* Interrupt Registers */\r
-\r
- #define SD_MOSI_INTSTAT (* (reg8 *) SD_MOSI__INTSTAT)\r
- #define SD_MOSI_SNAP (* (reg8 *) SD_MOSI__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(SD_MOSI__SIO_CFG)\r
+ #define SD_MOSI_SIO_HYST_EN (* (reg8 *) SD_MOSI__SIO_HYST_EN)\r
+ #define SD_MOSI_SIO_REG_HIFREQ (* (reg8 *) SD_MOSI__SIO_REG_HIFREQ)\r
+ #define SD_MOSI_SIO_CFG (* (reg8 *) SD_MOSI__SIO_CFG)\r
+ #define SD_MOSI_SIO_DIFF (* (reg8 *) SD_MOSI__SIO_DIFF)\r
+#endif /* (SD_MOSI__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(SD_MOSI__INTSTAT)\r
+ #define SD_MOSI_INTSTAT (* (reg8 *) SD_MOSI__INTSTAT)\r
+ #define SD_MOSI_SNAP (* (reg8 *) SD_MOSI__SNAP)\r
+ \r
+ #define SD_MOSI_0_INTTYPE_REG (* (reg8 *) SD_MOSI__0__INTTYPE)\r
+#endif /* (SD_MOSI__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: SD_MOSI.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_MOSI_0 (SD_MOSI__0__PC)\r
+#define SD_MOSI_0 (SD_MOSI__0__PC)\r
+#define SD_MOSI_0_INTR ((uint16)((uint16)0x0001u << SD_MOSI__0__SHIFT))\r
+\r
+#define SD_MOSI_INTR_ALL ((uint16)(SD_MOSI_0_INTR))\r
\r
#endif /* End Pins SD_MOSI_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SD_SCK.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: SD_SCK_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_SCK_SUT.c usage_SD_SCK_Write\r
*******************************************************************************/\r
-void SD_SCK_Write(uint8 value) \r
+void SD_SCK_Write(uint8 value)\r
{\r
uint8 staticBits = (SD_SCK_DR & (uint8)(~SD_SCK_MASK));\r
SD_SCK_DR = staticBits | ((uint8)(value << SD_SCK_SHIFT) & SD_SCK_MASK);\r
\r
/*******************************************************************************\r
* Function Name: SD_SCK_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* SD_SCK_DM_STRONG Strong Drive \r
-* SD_SCK_DM_OD_HI Open Drain, Drives High \r
-* SD_SCK_DM_OD_LO Open Drain, Drives Low \r
-* SD_SCK_DM_RES_UP Resistive Pull Up \r
-* SD_SCK_DM_RES_DWN Resistive Pull Down \r
-* SD_SCK_DM_RES_UPDWN Resistive Pull Up/Down \r
-* SD_SCK_DM_DIG_HIZ High Impedance Digital \r
-* SD_SCK_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_SCK_SUT.c usage_SD_SCK_SetDriveMode\r
*******************************************************************************/\r
-void SD_SCK_SetDriveMode(uint8 mode) \r
+void SD_SCK_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(SD_SCK_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_SCK_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro SD_SCK_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet SD_SCK_SUT.c usage_SD_SCK_Read \r
*******************************************************************************/\r
-uint8 SD_SCK_Read(void) \r
+uint8 SD_SCK_Read(void)\r
{\r
return (SD_SCK_PS & SD_SCK_MASK) >> SD_SCK_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_SCK_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred SD_SCK_Read() API because the \r
+* SD_SCK_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet SD_SCK_SUT.c usage_SD_SCK_ReadDataReg \r
*******************************************************************************/\r
-uint8 SD_SCK_ReadDataReg(void) \r
+uint8 SD_SCK_ReadDataReg(void)\r
{\r
return (SD_SCK_DR & SD_SCK_MASK) >> SD_SCK_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(SD_SCK_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: SD_SCK_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use SD_SCK_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - SD_SCK_0_INTR (First pin in the list)\r
+ * - SD_SCK_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - SD_SCK_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_SCK_SUT.c usage_SD_SCK_SetInterruptMode\r
+ *******************************************************************************/\r
+ void SD_SCK_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & SD_SCK_0_INTR) != 0u) \r
+ { \r
+ SD_SCK_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: SD_SCK_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_SCK_SUT.c usage_SD_SCK_ClearInterrupt\r
*******************************************************************************/\r
- uint8 SD_SCK_ClearInterrupt(void) \r
+ uint8 SD_SCK_ClearInterrupt(void)\r
{\r
return (SD_SCK_INTSTAT & SD_SCK_MASK) >> SD_SCK_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: SD_SCK.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "SD_SCK_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
SD_SCK__PORT == 15 && ((SD_SCK__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void SD_SCK_Write(uint8 value) ;\r
-void SD_SCK_SetDriveMode(uint8 mode) ;\r
-uint8 SD_SCK_ReadDataReg(void) ;\r
-uint8 SD_SCK_Read(void) ;\r
-uint8 SD_SCK_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void SD_SCK_Write(uint8 value);\r
+void SD_SCK_SetDriveMode(uint8 mode);\r
+uint8 SD_SCK_ReadDataReg(void);\r
+uint8 SD_SCK_Read(void);\r
+void SD_SCK_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 SD_SCK_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define SD_SCK_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define SD_SCK_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define SD_SCK_DM_RES_UP PIN_DM_RES_UP\r
-#define SD_SCK_DM_RES_DWN PIN_DM_RES_DWN\r
-#define SD_SCK_DM_OD_LO PIN_DM_OD_LO\r
-#define SD_SCK_DM_OD_HI PIN_DM_OD_HI\r
-#define SD_SCK_DM_STRONG PIN_DM_STRONG\r
-#define SD_SCK_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the SD_SCK_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define SD_SCK_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define SD_SCK_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define SD_SCK_DM_RES_UP PIN_DM_RES_UP\r
+ #define SD_SCK_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define SD_SCK_DM_OD_LO PIN_DM_OD_LO\r
+ #define SD_SCK_DM_OD_HI PIN_DM_OD_HI\r
+ #define SD_SCK_DM_STRONG PIN_DM_STRONG\r
+ #define SD_SCK_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define SD_SCK_MASK SD_SCK__MASK\r
#define SD_SCK_SHIFT SD_SCK__SHIFT\r
#define SD_SCK_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(SD_SCK__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in SD_SCK_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define SD_SCK_INTR_NONE (uint16)(0x0000u)\r
+ #define SD_SCK_INTR_RISING (uint16)(0x0001u)\r
+ #define SD_SCK_INTR_FALLING (uint16)(0x0002u)\r
+ #define SD_SCK_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define SD_SCK_INTR_MASK (0x01u) \r
+#endif /* (SD_SCK__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define SD_SCK_PRTDSI__SYNC_OUT (* (reg8 *) SD_SCK__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(SD_SCK__INTSTAT) /* Interrupt Registers */\r
-\r
- #define SD_SCK_INTSTAT (* (reg8 *) SD_SCK__INTSTAT)\r
- #define SD_SCK_SNAP (* (reg8 *) SD_SCK__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(SD_SCK__SIO_CFG)\r
+ #define SD_SCK_SIO_HYST_EN (* (reg8 *) SD_SCK__SIO_HYST_EN)\r
+ #define SD_SCK_SIO_REG_HIFREQ (* (reg8 *) SD_SCK__SIO_REG_HIFREQ)\r
+ #define SD_SCK_SIO_CFG (* (reg8 *) SD_SCK__SIO_CFG)\r
+ #define SD_SCK_SIO_DIFF (* (reg8 *) SD_SCK__SIO_DIFF)\r
+#endif /* (SD_SCK__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(SD_SCK__INTSTAT)\r
+ #define SD_SCK_INTSTAT (* (reg8 *) SD_SCK__INTSTAT)\r
+ #define SD_SCK_SNAP (* (reg8 *) SD_SCK__SNAP)\r
+ \r
+ #define SD_SCK_0_INTTYPE_REG (* (reg8 *) SD_SCK__0__INTTYPE)\r
+#endif /* (SD_SCK__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: SD_SCK.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_SCK_0 (SD_SCK__0__PC)\r
+#define SD_SCK_0 (SD_SCK__0__PC)\r
+#define SD_SCK_0_INTR ((uint16)((uint16)0x0001u << SD_SCK__0__SHIFT))\r
+\r
+#define SD_SCK_INTR_ALL ((uint16)(SD_SCK_0_INTR))\r
\r
#endif /* End Pins SD_SCK_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: USBFS.c\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS.c\r
+* \version 3.10\r
*\r
-* Description:\r
-* API for USBFS Component.\r
+* \brief\r
+* This file contains the global USBFS API functions.\r
*\r
* Note:\r
-* Many of the functions use endpoint number. RAM arrays are sized with 9\r
-* elements so they are indexed directly by epNumber. The SIE and ARB\r
+* Many of the functions use an endpoint number. SRAM arrays are sized with 9\r
+* elements, so they are indexed directly by epNumber. The SIE and ARB\r
* registers are indexed by variations of epNumber - 1.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include <CyDmac.h>\r
-#include "USBFS.h"\r
#include "USBFS_pvt.h"\r
+#include "USBFS_cydmac.h"\r
#include "USBFS_hid.h"\r
-#if(USBFS_DMA1_REMOVE == 0u)\r
- #include "USBFS_ep1_dma.h"\r
-#endif /* USBFS_DMA1_REMOVE */\r
-#if(USBFS_DMA2_REMOVE == 0u)\r
- #include "USBFS_ep2_dma.h"\r
-#endif /* USBFS_DMA2_REMOVE */\r
-#if(USBFS_DMA3_REMOVE == 0u)\r
- #include "USBFS_ep3_dma.h"\r
-#endif /* USBFS_DMA3_REMOVE */\r
-#if(USBFS_DMA4_REMOVE == 0u)\r
- #include "USBFS_ep4_dma.h"\r
-#endif /* USBFS_DMA4_REMOVE */\r
-#if(USBFS_DMA5_REMOVE == 0u)\r
- #include "USBFS_ep5_dma.h"\r
-#endif /* USBFS_DMA5_REMOVE */\r
-#if(USBFS_DMA6_REMOVE == 0u)\r
- #include "USBFS_ep6_dma.h"\r
-#endif /* USBFS_DMA6_REMOVE */\r
-#if(USBFS_DMA7_REMOVE == 0u)\r
- #include "USBFS_ep7_dma.h"\r
-#endif /* USBFS_DMA7_REMOVE */\r
-#if(USBFS_DMA8_REMOVE == 0u)\r
- #include "USBFS_ep8_dma.h"\r
-#endif /* USBFS_DMA8_REMOVE */\r
-#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- #include "USBFS_EP_DMA_Done_isr.h"\r
- #include "USBFS_EP8_DMA_Done_SR.h"\r
- #include "USBFS_EP17_DMA_Done_SR.h"\r
-#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+#include "USBFS_Dp.h"\r
\r
\r
/***************************************\r
* Global data allocation\r
***************************************/\r
\r
+/** Indicates whether the USBFS has been initialized. The variable is\r
+* initialized to 0 after device reset and set to 1 the first time USBFS_Start()\r
+* is called. This allows the Component to restart without reinitialization after\r
+* the first call to the USBFS_Start() routine.\r
+* If re-initialization of the Component is required, the variable should be set\r
+* to 0 before the USBFS_Start() routine is called. Alternatively, the USBFS can\r
+* be reinitialized by calling both USBFS_Init() and USBFS_InitComponent()\r
+* functions.\r
+*/\r
uint8 USBFS_initVar = 0u;\r
-#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- uint8 USBFS_DmaChan[USBFS_MAX_EP];\r
- uint8 USBFS_DmaTd[USBFS_MAX_EP];\r
-#endif /* USBFS_EP_MM */\r
-#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT;\r
- uint8 USBFS_DmaNextTd[USBFS_MAX_EP];\r
- const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] =\r
- { 0u,\r
- USBFS_ep1_TD_TERMOUT_EN,\r
- USBFS_ep2_TD_TERMOUT_EN,\r
- USBFS_ep3_TD_TERMOUT_EN,\r
- USBFS_ep4_TD_TERMOUT_EN,\r
- USBFS_ep5_TD_TERMOUT_EN,\r
- USBFS_ep6_TD_TERMOUT_EN,\r
- USBFS_ep7_TD_TERMOUT_EN,\r
- USBFS_ep8_TD_TERMOUT_EN\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+ #if (CY_PSOC4)\r
+ static void USBFS_InitEpDma(void);\r
+\r
+ /* DMA chanels assigend for endpoints. */\r
+ const uint8 USBFS_DmaChan[USBFS_MAX_EP] =\r
+ {\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ }; \r
+ #else\r
+ /* DMA chanels assigend for endpoints. */\r
+ uint8 USBFS_DmaChan[USBFS_MAX_EP];\r
+ \r
+ /* DMA TDs require for PSoC 3/5LP operation. */\r
+ uint8 USBFS_DmaTd[USBFS_MAX_EP];\r
+ #endif /* (CY_PSOC4) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+#if (CY_PSOC4)\r
+ /* Number of DMA bursts. */\r
+ uint8 USBFS_DmaEpBurstCnt [USBFS_MAX_EP];\r
+ \r
+ /* Number of bytes to transfer in last DMA burst. */\r
+ uint8 USBFS_DmaEpLastBurstEl[USBFS_MAX_EP];\r
+\r
+ /* Storage for arrays above. */\r
+ uint8 USBFS_DmaEpBurstCntBackup [USBFS_MAX_EP];\r
+ uint32 USBFS_DmaEpBufferAddrBackup[USBFS_MAX_EP];\r
+ \r
+ /* DMA trigger mux output for usb.dma_req[0-7]. */\r
+ const uint8 USBFS_DmaReqOut[USBFS_MAX_EP] =\r
+ {\r
+ 0u,\r
+ USBFS_ep1_dma__TR_OUTPUT,\r
+ USBFS_ep2_dma__TR_OUTPUT,\r
+ USBFS_ep3_dma__TR_OUTPUT,\r
+ USBFS_ep4_dma__TR_OUTPUT,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ };\r
+\r
+ /* DMA trigger mux output for usb.dma_burstend[0-7]. */\r
+ const uint8 USBFS_DmaBurstEndOut[USBFS_MAX_EP] =\r
+ {\r
+ 0u,\r
+ USBFS_BURSTEND_0_TR_OUTPUT,\r
+ USBFS_BURSTEND_1_TR_OUTPUT,\r
+ USBFS_BURSTEND_2_TR_OUTPUT,\r
+ USBFS_BURSTEND_3_TR_OUTPUT,\r
+ USBFS_BURSTEND_4_TR_OUTPUT,\r
+ USBFS_BURSTEND_5_TR_OUTPUT,\r
+ USBFS_BURSTEND_6_TR_OUTPUT,\r
+ USBFS_BURSTEND_7_TR_OUTPUT\r
};\r
- volatile uint16 USBFS_inLength[USBFS_MAX_EP];\r
- const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];\r
- volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];\r
-#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+ \r
+#else\r
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT;\r
+ uint8 USBFS_DmaNextTd[USBFS_MAX_EP];\r
+ const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] =\r
+ {\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ };\r
+\r
+ volatile uint16 USBFS_inLength[USBFS_MAX_EP];\r
+ const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];\r
+ volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];\r
+ #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+#endif /* (CY_PSOC4) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Start\r
-********************************************************************************\r
+****************************************************************************//**\r
+*\r
+* This function performs all required initialization for the USBFS component.\r
+* After this function call, the USB device initiates communication with the\r
+* host by pull-up D+ line. This is the preferred method to begin component\r
+* operation.\r
+*\r
+* Note that global interrupts have to be enabled because interrupts are\r
+* required for USBFS component operation.\r
*\r
-* Summary:\r
-* This function initialize the USB SIE, arbiter and the\r
-* endpoint APIs, including setting the D+ Pullup\r
+* PSoC 4200L devices: when USBFS component configured to DMA with Automatic\r
+* Buffer Management, the DMA interrupt priority is changed to the highest\r
+* (priority 0) inside this function.\r
*\r
-* Parameters:\r
-* device: Contains the device number of the desired device descriptor.\r
+* PSoC 3/PSoC 5LP devices: when USBFS component configured to DMA with\r
+* Automatic Buffer Management, the Arbiter interrupt priority is changed to\r
+* the highest (priority 0) inside this function.\r
+*\r
+* \param device\r
+* Contains the device number of the desired device descriptor.\r
* The device number can be found in the Device Descriptor Tab of\r
* "Configure" dialog, under the settings of desired Device Descriptor,\r
* in the "Device Number" field.\r
-* mode: The operating voltage. This determines whether the voltage regulator\r
-* is enabled for 5V operation or if pass through mode is used for 3.3V\r
-* operation. Symbolic names and their associated values are given in the\r
-* following table.\r
-* USBFS_3V_OPERATION - Disable voltage regulator and pass-thru\r
-* Vcc for pull-up\r
-* USBFS_5V_OPERATION - Enable voltage regulator and use\r
-* regulator for pull-up\r
-* USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage\r
-* regulator depend on Vddd Voltage configuration in DWR.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* The USBFS_intiVar variable is used to indicate initial\r
-* configuration of this component. The variable is initialized to zero (0u)\r
-* and set to one (1u) the first time USBFS_Start() is called.\r
-* This allows for component Re-Start without unnecessary re-initialization\r
-* in all subsequent calls to the USBFS_Start() routine.\r
-* If re-initialization of the component is required the variable should be set\r
-* to zero before call of UART_Start() routine, or the user may call\r
-* USBFS_Init() and USBFS_InitComponent() as done\r
-* in the USBFS_Start() routine.\r
-*\r
-* Side Effects:\r
+* \param mode:\r
+* The operating voltage. This determines whether the voltage regulator\r
+* is enabled for 5V operation or if pass through mode is used for 3.3V\r
+* operation. Symbolic names and their associated values are given in the\r
+* following list.\r
+*\r
+* *USBFS_3V_OPERATION* - Disable voltage regulator and pass-\r
+* through Vcc for pull-up\r
+*\r
+* *USBFS_5V_OPERATION* - Enable voltage regulator and use\r
+* regulator for pull-up\r
+*\r
+* *USBFS_DWR_POWER_OPERATION* - Enable or disable the voltage\r
+* regulator depending on the power supply\r
+* voltage configuration in the DWR tab.\r
+* For PSoC 3/5LP devices, the VDDD supply\r
+* voltage is considered and for PSoC 4A-L,\r
+* the VBUS supply voltage is considered.*\r
+* \globalvars\r
+* \ref USBFS_initVar\r
+*\r
+* \sideeffect\r
* This function will reset all communication states to default.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_Start(uint8 device, uint8 mode) \r
{\r
- /* If not Initialized then initialize all required hardware and software */\r
- if(USBFS_initVar == 0u)\r
+ if (0u == USBFS_initVar)\r
{\r
USBFS_Init();\r
USBFS_initVar = 1u;\r
}\r
+\r
USBFS_InitComponent(device, mode);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Init\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Initialize component's hardware. Usually called in USBFS_Start().\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None.\r
+* This function initializes or restores the component according to the\r
+* customizer Configure dialog settings. It is not necessary to call\r
+* USBFS_Init() because the USBFS_Start() routine calls\r
+* this function and is the preferred method to begin component operation.\r
*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_Init(void) \r
{\r
- uint8 enableInterrupts;\r
- #if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- uint16 i;\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
+#if (CY_PSOC4)\r
+ /* Enable clock to USB IP. */\r
+ USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_CSR_CLK_EN;\r
\r
- enableInterrupts = CyEnterCriticalSection();\r
+ /* The internal regulator (CR1.REG_ENABLE) is enabled in\r
+ * USBFS_InitComponent() if it is required.\r
+ */\r
+\r
+ /* Enable USBIO control on drive mode of D+ and D- pins. */\r
+ USBFS_USBIO_CR1_REG &= ~ (uint32) USBFS_USBIO_CR1_IOMODE;\r
+\r
+ /* Set number of LF CLK to detect UBS bus reset. */\r
+ USBFS_BUS_RST_CNT_REG = USBFS_DEFUALT_BUS_RST_CNT;\r
+\r
+ /* Select VBUS detection source and clear PHY isolate. The application level\r
+ * must ensure that VBUS is valid. There is no need to wait 2us before VBUS is valid.\r
+ */\r
+ USBFS_POWER_CTRL_REG = USBFS_DEFAULT_POWER_CTRL_VBUS;\r
\r
- /* Enable USB block */\r
+ /* Enable PHY detector and single-ended and differential receivers. */\r
+ USBFS_POWER_CTRL_REG |= USBFS_DEFAULT_POWER_CTRL_PHY;\r
+\r
+ /* Suspend clear sequence. */\r
+ USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND;\r
+ CyDelayUs(USBFS_WAIT_SUSPEND_DEL_DISABLE);\r
+ USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND_DEL;\r
+\r
+ /* Sets IMO lock options and clear all other bits. */\r
+ USBFS_CR1_REG = USBFS_DEFUALT_CR1;\r
+\r
+ /* Configure level (hi, lo, med) for each interrupt source. */\r
+ USBFS_INTR_LVL_SEL_REG = USBFS_DEFAULT_INTR_LVL_SEL;\r
+\r
+ /* Configure interrupt sources from: SOF, Bus Reset and EP0. */\r
+ USBFS_INTR_SIE_MASK_REG = USBFS_DEFAULT_INTR_SIE_MASK;\r
+\r
+#else\r
+ uint8 enableInterrupts = CyEnterCriticalSection();\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+ uint16 i;\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+ /* Enable USB block. */\r
USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB;\r
- /* Enable USB block for Standby Power Mode */\r
+ /* Enable USB block for Standby Power Mode. */\r
USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB;\r
\r
- /* Enable core clock */\r
+ /* Enable core clock. */\r
USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_ENABLE;\r
\r
USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;\r
\r
- /* ENABLING USBIO PADS IN USB MODE FROM I/O MODE */\r
- /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */\r
- USBFS_USBIO_CR0_REG &= ((uint8)(~USBFS_USBIO_CR0_TEN));\r
- CyDelayUs(0u); /*~50ns delay */\r
- /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted)\r
- * high. This will have been set low by the power manger out of reset.\r
- * Also confirm USBIO pull-up disabled\r
+ /* ENABLING USBIO PADS IN USB MODE FROM I/O MODE. */\r
+ /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled. */\r
+ USBFS_USBIO_CR0_REG &= (uint8) ~USBFS_USBIO_CR0_TEN;\r
+ CyDelayUs(USBFS_WAIT_REG_STABILITY_50NS); /* ~50ns delay. */\r
+ /* Disable USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted.\r
+ * high. These bits will be set low by the power manager out-of-reset.\r
+ * Also confirm USBIO pull-up is disabled.\r
*/\r
- USBFS_PM_USB_CR0_REG &= ((uint8)(~(USBFS_PM_USB_CR0_PD_N |\r
- USBFS_PM_USB_CR0_PD_PULLUP_N)));\r
+ USBFS_PM_USB_CR0_REG &= (uint8) ~(USBFS_PM_USB_CR0_PD_N |\r
+ USBFS_PM_USB_CR0_PD_PULLUP_N);\r
\r
- /* Select iomode to USB mode*/\r
- USBFS_USBIO_CR1_REG &= ((uint8)(~USBFS_USBIO_CR1_IOMODE));\r
+ /* Select IOMODE to USB mode. */\r
+ USBFS_USBIO_CR1_REG &= (uint8) ~USBFS_USBIO_CR1_IOMODE;\r
\r
- /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/\r
+ /* Enable USBIO reference by setting PM.USB_CR0.fsusbio_ref_en. */\r
USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN;\r
- /* The reference will be available 1 us after the regulator is enabled */\r
- CyDelayUs(1u);\r
- /* OR 40us after power restored */\r
- CyDelayUs(40u);\r
- /* Ensure the single ended disable bits are low (PRT15.INP_DIS[7:6])(input receiver enabled). */\r
- USBFS_DM_INP_DIS_REG &= ((uint8)(~USBFS_DM_MASK));\r
- USBFS_DP_INP_DIS_REG &= ((uint8)(~USBFS_DP_MASK));\r
-\r
- /* Enable USBIO */\r
+ /* Reference is available for 1us after regulator is enabled. */\r
+ CyDelayUs(USBFS_WAIT_REG_STABILITY_1US);\r
+ /* OR 40us after power is restored. */\r
+ CyDelayUs(USBFS_WAIT_VREF_RESTORE);\r
+ /* Ensure single-ended disable bits are low (PRT15.INP_DIS[7:6])(input receiver enabled). */\r
+ USBFS_DM_INP_DIS_REG &= (uint8) ~USBFS_DM_MASK;\r
+ USBFS_DP_INP_DIS_REG &= (uint8) ~USBFS_DP_MASK;\r
+\r
+ /* Enable USBIO. */\r
USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N;\r
- CyDelayUs(2u);\r
- /* Set the USBIO pull-up enable */\r
+ CyDelayUs(USBFS_WAIT_PD_PULLUP_N_ENABLE);\r
+ /* Set USBIO pull-up enable. */\r
USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N;\r
\r
- /* Write WAx */\r
+ /* Reset Arbiter Write Address register for endpoint 1. */\r
CY_SET_REG8(USBFS_ARB_RW1_WA_PTR, 0u);\r
CY_SET_REG8(USBFS_ARB_RW1_WA_MSB_PTR, 0u);\r
\r
- #if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- /* Init transfer descriptor. This will be used to detect the DMA state - initialized or not. */\r
- for (i = 0u; i < USBFS_MAX_EP; i++)\r
- {\r
- USBFS_DmaTd[i] = DMA_INVALID_TD;\r
- #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- USBFS_DmaNextTd[i] = DMA_INVALID_TD;\r
- #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
- }\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+ /* Initialize transfer descriptor. This will be used to detect DMA state - initialized or not. */\r
+ for (i = 0u; i < USBFS_MAX_EP; ++i)\r
+ {\r
+ USBFS_DmaTd[i] = DMA_INVALID_TD;\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ USBFS_DmaNextTd[i] = DMA_INVALID_TD;\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+ }\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
\r
CyExitCriticalSection(enableInterrupts);\r
+#endif /* (CY_PSOC4) */\r
\r
+ /* Configure interrupts from USB block. */\r
+#if (CY_PSOC4)\r
+ /* Configure hi_int: set handler and priority. */\r
+ CyIntSetPriority (USBFS_INTR_HI_VECT_NUM, USBFS_INTR_HI_PRIORITY);\r
+ (void) CyIntSetVector(USBFS_INTR_HI_VECT_NUM, &USBFS_INTR_HI_ISR);\r
\r
- /* Set the bus reset Interrupt. */\r
- (void) CyIntSetVector(USBFS_BUS_RESET_VECT_NUM, &USBFS_BUS_RESET_ISR);\r
- CyIntSetPriority(USBFS_BUS_RESET_VECT_NUM, USBFS_BUS_RESET_PRIOR);\r
+ /* Configure lo_int: set handler and priority. */\r
+ CyIntSetPriority (USBFS_INTR_LO_VECT_NUM, USBFS_INTR_LO_PRIORITY);\r
+ (void) CyIntSetVector(USBFS_INTR_LO_VECT_NUM, &USBFS_INTR_LO_ISR);\r
\r
- /* Set the SOF Interrupt. */\r
- #if(USBFS_SOF_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_SOF_VECT_NUM, &USBFS_SOF_ISR);\r
- CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR);\r
- #endif /* USBFS_SOF_ISR_REMOVE */\r
+ /* Configure med_int: set handler and priority (routed through DSI). */\r
+ CyIntSetPriority (USBFS_INTR_MED_VECT_NUM, USBFS_INTR_MED_PRIORITY);\r
+ (void) CyIntSetVector(USBFS_INTR_MED_VECT_NUM, &USBFS_INTR_MED_ISR);\r
\r
- /* Set the Control Endpoint Interrupt. */\r
- (void) CyIntSetVector(USBFS_EP_0_VECT_NUM, &USBFS_EP_0_ISR);\r
- CyIntSetPriority(USBFS_EP_0_VECT_NUM, USBFS_EP_0_PRIOR);\r
+#else\r
+ /* Set bus reset interrupt. */\r
+ CyIntSetPriority(USBFS_BUS_RESET_VECT_NUM, USBFS_BUS_RESET_PRIOR);\r
+ (void) CyIntSetVector(USBFS_BUS_RESET_VECT_NUM, &USBFS_BUS_RESET_ISR);\r
\r
- /* Set the Data Endpoint 1 Interrupt. */\r
- #if(USBFS_EP1_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_EP_1_VECT_NUM, &USBFS_EP_1_ISR);\r
- CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR);\r
- #endif /* USBFS_EP1_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 2 Interrupt. */\r
- #if(USBFS_EP2_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_EP_2_VECT_NUM, &USBFS_EP_2_ISR);\r
- CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR);\r
- #endif /* USBFS_EP2_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 3 Interrupt. */\r
- #if(USBFS_EP3_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_EP_3_VECT_NUM, &USBFS_EP_3_ISR);\r
- CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR);\r
- #endif /* USBFS_EP3_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 4 Interrupt. */\r
- #if(USBFS_EP4_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_EP_4_VECT_NUM, &USBFS_EP_4_ISR);\r
- CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR);\r
- #endif /* USBFS_EP4_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 5 Interrupt. */\r
- #if(USBFS_EP5_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_EP_5_VECT_NUM, &USBFS_EP_5_ISR);\r
- CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR);\r
- #endif /* USBFS_EP5_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 6 Interrupt. */\r
- #if(USBFS_EP6_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_EP_6_VECT_NUM, &USBFS_EP_6_ISR);\r
- CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR);\r
- #endif /* USBFS_EP6_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 7 Interrupt. */\r
- #if(USBFS_EP7_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_EP_7_VECT_NUM, &USBFS_EP_7_ISR);\r
- CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR);\r
- #endif /* USBFS_EP7_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 8 Interrupt. */\r
- #if(USBFS_EP8_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR);\r
- CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR);\r
- #endif /* USBFS_EP8_ISR_REMOVE */\r
-\r
- #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))\r
- /* Set the ARB Interrupt. */\r
- (void) CyIntSetVector(USBFS_ARB_VECT_NUM, &USBFS_ARB_ISR);\r
- CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR);\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ /* Set Control Endpoint Interrupt. */\r
+ CyIntSetPriority(USBFS_EP_0_VECT_NUM, USBFS_EP_0_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_0_VECT_NUM, &USBFS_EP_0_ISR);\r
\r
+ /* Set SOF interrupt. */\r
+ #if (USBFS_SOF_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR);\r
+ (void) CyIntSetVector(USBFS_SOF_VECT_NUM, &USBFS_SOF_ISR);\r
+ #endif /* (USBFS_SOF_ISR_ACTIVE) */\r
+\r
+ /* Set Data Endpoint 1 Interrupt. */\r
+ #if (USBFS_EP1_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_1_VECT_NUM, &USBFS_EP_1_ISR);\r
+ #endif /* (USBFS_EP1_ISR_ACTIVE) */\r
+\r
+ /* Set Data Endpoint 2 Interrupt. */\r
+ #if (USBFS_EP2_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_2_VECT_NUM, &USBFS_EP_2_ISR);\r
+ #endif /* (USBFS_EP2_ISR_ACTIVE) */\r
+\r
+ /* Set Data Endpoint 3 Interrupt. */\r
+ #if (USBFS_EP3_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_3_VECT_NUM, &USBFS_EP_3_ISR);\r
+ #endif /* (USBFS_EP3_ISR_ACTIVE) */\r
+\r
+ /* Set Data Endpoint 4 Interrupt. */\r
+ #if (USBFS_EP4_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_4_VECT_NUM, &USBFS_EP_4_ISR);\r
+ #endif /* (USBFS_EP4_ISR_ACTIVE) */\r
+\r
+ /* Set Data Endpoint 5 Interrupt. */\r
+ #if (USBFS_EP5_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_5_VECT_NUM, &USBFS_EP_5_ISR);\r
+ #endif /* (USBFS_EP5_ISR_ACTIVE) */\r
+\r
+ /* Set Data Endpoint 6 Interrupt. */\r
+ #if (USBFS_EP6_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_6_VECT_NUM, &USBFS_EP_6_ISR);\r
+ #endif /* (USBFS_EP6_ISR_ACTIVE) */\r
+\r
+ /* Set Data Endpoint 7 Interrupt. */\r
+ #if (USBFS_EP7_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_7_VECT_NUM, &USBFS_EP_7_ISR);\r
+ #endif /* (USBFS_EP7_ISR_ACTIVE) */\r
+\r
+ /* Set Data Endpoint 8 Interrupt. */\r
+ #if (USBFS_EP8_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR);\r
+ #endif /* (USBFS_EP8_ISR_ACTIVE) */\r
+\r
+ /* Set ARB Interrupt. */\r
+ #if (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR);\r
+ (void) CyIntSetVector(USBFS_ARB_VECT_NUM, &USBFS_ARB_ISR);\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) */\r
+#endif /* (CY_PSOC4) */\r
+\r
+ /* Common: Configure GPIO interrupt for wakeup. */\r
+#if (USBFS_DP_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIORITY);\r
+ (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR);\r
+#endif /* (USBFS_DP_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA && CY_PSOC4)\r
+ /* Initialize DMA channels. */\r
+ USBFS_InitEpDma();\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA && CY_PSOC4) */\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_InitComponent\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Initialize the component, except for the HW which is done one time in\r
-* the Start function. This function pulls up D+.\r
-*\r
-* Parameters:\r
-* device: Contains the device number of the desired device descriptor.\r
-* The device number can be found in the Device Descriptor Tab of\r
-* "Configure" dialog, under the settings of desired Device Descriptor,\r
-* in the "Device Number" field.\r
-* mode: The operating voltage. This determines whether the voltage regulator\r
-* is enabled for 5V operation or if pass through mode is used for 3.3V\r
-* operation. Symbolic names and their associated values are given in the\r
-* following table.\r
-* USBFS_3V_OPERATION - Disable voltage regulator and pass-thru\r
-* Vcc for pull-up\r
-* USBFS_5V_OPERATION - Enable voltage regulator and use\r
-* regulator for pull-up\r
-* USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage\r
-* regulator depend on Vddd Voltage configuration in DWR.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_device: Contains the device number of the desired device\r
-* descriptor. The device number can be found in the Device Descriptor Tab\r
-* of "Configure" dialog, under the settings of desired Device Descriptor,\r
-* in the "Device Number" field.\r
-* USBFS_transferState: This variable used by the communication\r
-* functions to handle current transfer state. Initialized to\r
-* TRANS_STATE_IDLE in this API.\r
-* USBFS_configuration: Contains current configuration number\r
-* which is set by the Host using SET_CONFIGURATION request.\r
-* Initialized to zero in this API.\r
-* USBFS_deviceAddress: Contains current device address. This\r
-* variable is initialized to zero in this API. Host starts to communicate\r
-* to device with address 0 and then set it to whatever value using\r
+****************************************************************************//**\r
+*\r
+* This function initializes the component’s global variables and initiates\r
+* communication with the host by pull-up D+ line.\r
+*\r
+* \param device:\r
+* Contains the device number of the desired device descriptor. The device\r
+* number can be found in the Device Descriptor Tab of "Configure" dialog,\r
+* under the settings of desired Device Descriptor, in the *Device Number*\r
+* field.\r
+* \param mode:\r
+* The operating voltage. This determines whether the voltage regulator\r
+* is enabled for 5V operation or if pass through mode is used for 3.3V\r
+* operation. Symbolic names and their associated values are given in the\r
+* following list.\r
+*\r
+* *USBFS_3V_OPERATION* - Disable voltage regulator and pass-\r
+* through Vcc for pull-up\r
+*\r
+* *USBFS_5V_OPERATION* - Enable voltage regulator and use\r
+* regulator for pull-up\r
+*\r
+* *USBFS_DWR_POWER_OPERATION* - Enable or disable the voltage\r
+* regulator depending on the power supply\r
+* voltage configuration in the DWR tab.\r
+* For PSoC 3/5LP devices, the VDDD supply\r
+* voltage is considered and for PSoC 4A-L,\r
+* the VBUS supply voltage is considered.\r
+*\r
+* \globalvars\r
+* \ref USBFS_device\r
+* \ref USBFS_transferState\r
+* \ref USBFS_configuration\r
+* \ref USBFS_deviceStatus\r
+*\r
+* \ref USBFS_deviceAddress - Contains the current device address. This\r
+* variable is initialized to zero in this API. The Host starts to communicate\r
+* to the device with address 0 and then sets it to a whatever value using a\r
* SET_ADDRESS request.\r
-* USBFS_deviceStatus: initialized to 0.\r
-* This is two bit variable which contain power status in first bit\r
-* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote\r
-* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit.\r
-* USBFS_lastPacketSize initialized to 0;\r
*\r
-* Reentrant:\r
+* \ref USBFS_lastPacketSize - Initialized to 0;\r
+*\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
* HID 7.2.6 Set_Protocol Request:\r
* "When initialized, all devices default to report protocol."\r
*/\r
- #if defined(USBFS_ENABLE_HID_CLASS)\r
- uint8 i;\r
+#if defined(USBFS_ENABLE_HID_CLASS)\r
+ uint8 i;\r
\r
- for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++)\r
- {\r
- USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT;\r
- }\r
- #endif /* USBFS_ENABLE_HID_CLASS */\r
+ for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++)\r
+ {\r
+ USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT;\r
+ }\r
+#endif /* USBFS_ENABLE_HID_CLASS */\r
+\r
+ /* Store device number to access descriptor. */\r
+ USBFS_device = device;\r
\r
- /* Enable Interrupts. */\r
+ /* Reset component internal variables. */\r
+ USBFS_transferState = USBFS_TRANS_STATE_IDLE;\r
+ USBFS_configurationChanged = 0u;\r
+ USBFS_configuration = 0u;\r
+ USBFS_interfaceNumber = 0u;\r
+ USBFS_deviceAddress = 0u;\r
+ USBFS_deviceStatus = 0u;\r
+ USBFS_lastPacketSize = 0u;\r
+\r
+ /* Enable component interrupts. */\r
+#if (CY_PSOC4)\r
+ CyIntEnable(USBFS_INTR_HI_VECT_NUM);\r
+ CyIntEnable(USBFS_INTR_MED_VECT_NUM);\r
+ CyIntEnable(USBFS_INTR_LO_VECT_NUM);\r
+#else\r
CyIntEnable(USBFS_BUS_RESET_VECT_NUM);\r
CyIntEnable(USBFS_EP_0_VECT_NUM);\r
- #if(USBFS_EP1_ISR_REMOVE == 0u)\r
+\r
+ #if (USBFS_SOF_ISR_ACTIVE)\r
+ CyIntEnable(USBFS_SOF_VECT_NUM);\r
+ #endif /* (USBFS_SOF_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP1_ISR_ACTIVE)\r
CyIntEnable(USBFS_EP_1_VECT_NUM);\r
- #endif /* USBFS_EP1_ISR_REMOVE */\r
- #if(USBFS_EP2_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP1_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP2_ISR_ACTIVE)\r
CyIntEnable(USBFS_EP_2_VECT_NUM);\r
- #endif /* USBFS_EP2_ISR_REMOVE */\r
- #if(USBFS_EP3_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP5_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP3_ISR_ACTIVE)\r
CyIntEnable(USBFS_EP_3_VECT_NUM);\r
- #endif /* USBFS_EP3_ISR_REMOVE */\r
- #if(USBFS_EP4_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP5_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP4_ISR_ACTIVE)\r
CyIntEnable(USBFS_EP_4_VECT_NUM);\r
- #endif /* USBFS_EP4_ISR_REMOVE */\r
- #if(USBFS_EP5_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP5_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP5_ISR_ACTIVE)\r
CyIntEnable(USBFS_EP_5_VECT_NUM);\r
- #endif /* USBFS_EP5_ISR_REMOVE */\r
- #if(USBFS_EP6_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP5_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP6_ISR_ACTIVE)\r
CyIntEnable(USBFS_EP_6_VECT_NUM);\r
- #endif /* USBFS_EP6_ISR_REMOVE */\r
- #if(USBFS_EP7_ISR_REMOVE == 0u)\r
+ #endif /* USBFS_EP6_ISR_REMOVE */\r
+\r
+ #if (USBFS_EP7_ISR_ACTIVE)\r
CyIntEnable(USBFS_EP_7_VECT_NUM);\r
- #endif /* USBFS_EP7_ISR_REMOVE */\r
- #if(USBFS_EP8_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP7_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP8_ISR_ACTIVE)\r
CyIntEnable(USBFS_EP_8_VECT_NUM);\r
- #endif /* USBFS_EP8_ISR_REMOVE */\r
- #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))\r
- /* usb arb interrupt enable */\r
- USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;\r
+ #endif /* (USBFS_EP8_ISR_ACTIVE) */\r
+#endif /* (CY_PSOC4) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE)\r
+ /* Enable ARB EP interrupt sources. */\r
+ USBFS_ARB_INT_EN_REG = USBFS_DEFAULT_ARB_INT_EN;\r
+\r
+ #if (CY_PSOC3 || CY_PSOC5)\r
CyIntEnable(USBFS_ARB_VECT_NUM);\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
-\r
- /* Arbiter configuration for DMA transfers */\r
- #if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
- USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- /*Set cfg cmplt this rises DMA request when the full configuration is done */\r
- USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;\r
- #if(USBFS_EP_DMA_AUTO_OPT == 0u)\r
- /* Init interrupt which handles verification of the successful DMA transaction */\r
+ #endif /* (CY_PSOC3 || CY_PSOC5) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) */\r
+\r
+/* Arbiter configuration for DMA transfers. */\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+ /* Configure Arbiter for Manual or Auto DMA operation and clear configuration completion. */\r
+ USBFS_ARB_CFG_REG = USBFS_DEFAULT_ARB_CFG;\r
+\r
+ #if (CY_PSOC4)\r
+ /* Enable DMA operation. */\r
+ CyDmaEnable();\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Change DMA priority to be highest. */\r
+ CyIntSetPriority(CYDMA_INTR_NUMBER, USBFS_DMA_AUTO_INTR_PRIO);\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ #endif /* (CY_PSOC4) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ #if (CY_PSOC4)\r
+ /* Enable DMA interrupt to handle DMA management. */\r
+ CyIntEnable(CYDMA_INTR_NUMBER);\r
+ #else\r
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ /* Initialize interrupts which handle verification of successful DMA transaction. */\r
USBFS_EP_DMA_Done_isr_StartEx(&USBFS_EP_DMA_DONE_ISR);\r
USBFS_EP17_DMA_Done_SR_InterruptEnable();\r
USBFS_EP8_DMA_Done_SR_InterruptEnable();\r
- #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
-\r
- USBFS_transferState = USBFS_TRANS_STATE_IDLE;\r
+ #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+ #endif /* (CY_PSOC4) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
\r
- /* USB Locking: Enabled, VRegulator: depend on mode or DWR Voltage configuration*/\r
+ /* Enable USB regulator depends on operation voltage. IMO Locking is enabled in Init(). */\r
switch(mode)\r
{\r
- case USBFS_3V_OPERATION:\r
- USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;\r
- break;\r
- case USBFS_5V_OPERATION:\r
- USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE;\r
- break;\r
- default: /*USBFS_DWR_VDDD_OPERATION */\r
- #if(USBFS_VDDD_MV < USBFS_3500MV)\r
- USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;\r
- #else\r
- USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE;\r
- #endif /* USBFS_VDDD_MV < USBFS_3500MV */\r
- break;\r
+ case USBFS_3V_OPERATION:\r
+ /* Disable regulator for 3V operation. */\r
+ USBFS_CR1_REG &= (uint8) ~USBFS_CR1_REG_ENABLE;\r
+ break;\r
+\r
+ case USBFS_5V_OPERATION:\r
+ /* Enable regulator for 5V operation. */\r
+ USBFS_CR1_REG |= (uint8) USBFS_CR1_REG_ENABLE;\r
+ break;\r
+\r
+ default: /* Check DWR settings of USB power supply. */\r
+ #if (USBFS_VDDD_MV < USBFS_3500MV)\r
+ /* Disable regulator for 3V operation. */\r
+ USBFS_CR1_REG &= (uint8) ~USBFS_CR1_REG_ENABLE;\r
+ #else\r
+ /* Enable regulator for 5V operation. */\r
+ USBFS_CR1_REG |= (uint8) USBFS_CR1_REG_ENABLE;\r
+ #endif /* (USBFS_VDDD_MV < USBFS_3500MV) */\r
+ break;\r
}\r
\r
- /* Record the descriptor selection */\r
- USBFS_device = device;\r
+#if (CY_PSOC4)\r
+ /* Clear bus activity. */\r
+ USBFS_CR1_REG &= (uint32) ~USBFS_CR1_BUS_ACTIVITY;\r
\r
- /* Clear all of the component data */\r
- USBFS_configuration = 0u;\r
- USBFS_interfaceNumber = 0u;\r
- USBFS_configurationChanged = 0u;\r
- USBFS_deviceAddress = 0u;\r
- USBFS_deviceStatus = 0u;\r
+ /* Clear EP0 count register. */\r
+ USBFS_EP0_CNT_REG = USBFS_CLEAR_REG;\r
+\r
+ /* Set EP0.CR: ACK Setup, NAK IN/OUT. */\r
+ USBFS_EP0_CR_REG = USBFS_MODE_NAK_IN_OUT;\r
\r
- USBFS_lastPacketSize = 0u;\r
+ #if (USBFS_LPM_ACTIVE)\r
+ if (NULL != USBFS_GetBOSPtr())\r
+ {\r
+ /* Enable LPM and acknowledge LPM packets for active device.\r
+ * Reset NYET_EN and SUB_RESP bits in the LPM_CTRL register.\r
+ */\r
+ USBFS_LPM_CTRL_REG = (USBFS_LPM_CTRL_LPM_EN | \\r
+ USBFS_LPM_CTRL_LPM_ACK_RESP);\r
+ }\r
+ else\r
+ {\r
+ /* Disable LPM for active device. */\r
+ USBFS_LPM_CTRL_REG &= (uint32) ~USBFS_LPM_CTRL_LPM_EN;\r
+ }\r
+ #endif /* (USBFS_LPM_ACTIVE) */\r
\r
- /* ACK Setup, Stall IN/OUT */\r
- CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);\r
+ /* Enable device to responds to USB traffic with address 0. */\r
+ USBFS_CR0_REG = USBFS_DEFUALT_CR0;\r
\r
- /* Enable the SIE with an address 0 */\r
- CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE);\r
+#else\r
+ /* Set EP0.CR: ACK Setup, STALL IN/OUT. */\r
+ USBFS_EP0_CR_REG = USBFS_MODE_STALL_IN_OUT;\r
\r
- /* Workaround for PSOC5LP */\r
- CyDelayCycles(1u);\r
+ /* Enable device to respond to USB traffic with address 0. */\r
+ USBFS_CR0_REG = USBFS_DEFUALT_CR0;\r
+ CyDelayCycles(USBFS_WAIT_CR0_REG_STABILITY);\r
+#endif /* (CY_PSOC4) */\r
\r
- /* Finally, Enable d+ pullup and select iomode to USB mode*/\r
- CY_SET_REG8(USBFS_USBIO_CR1_PTR, USBFS_USBIO_CR1_USBPUEN);\r
+ /* Enable D+ pull-up and keep USB control on IO. */\r
+ USBFS_USBIO_CR1_REG = USBFS_USBIO_CR1_USBPUEN;\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ReInitComponent\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function reinitialize the component configuration and is\r
* intend to be called from the Reset interrupt.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_device: Contains the device number of the desired device\r
-* descriptor. The device number can be found in the Device Descriptor Tab\r
-* of "Configure" dialog, under the settings of desired Device Descriptor,\r
-* in the "Device Number" field.\r
-* USBFS_transferState: This variable used by the communication\r
-* functions to handle current transfer state. Initialized to\r
+* \globalvars\r
+* USBFS_device - Contains the device number of the desired Device\r
+* Descriptor. The device number can be found in the Device Descriptor tab\r
+* of the Configure dialog, under the settings of the desired Device Descriptor,\r
+* in the Device Number field.\r
+* USBFS_transferState - This variable is used by the communication\r
+* functions to handle the current transfer state. Initialized to\r
* TRANS_STATE_IDLE in this API.\r
-* USBFS_configuration: Contains current configuration number\r
-* which is set by the Host using SET_CONFIGURATION request.\r
+* USBFS_configuration - Contains the current configuration number\r
+* set by the Host using a SET_CONFIGURATION request.\r
* Initialized to zero in this API.\r
-* USBFS_deviceAddress: Contains current device address. This\r
-* variable is initialized to zero in this API. Host starts to communicate\r
-* to device with address 0 and then set it to whatever value using\r
-* SET_ADDRESS request.\r
-* USBFS_deviceStatus: initialized to 0.\r
-* This is two bit variable which contain power status in first bit\r
-* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote\r
-* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit.\r
-* USBFS_lastPacketSize initialized to 0;\r
-*\r
-* Reentrant:\r
+* USBFS_deviceAddress - Contains the current device address. This\r
+* variable is initialized to zero in this API. The Host starts to communicate\r
+* to the device with address 0 and then sets it to a whatever value using\r
+* a SET_ADDRESS request.\r
+* USBFS_deviceStatus - Initialized to 0.\r
+* This is a two-bit variable which contains the power status in the first bit\r
+* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and the remote\r
+* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in the second bit.\r
+* USBFS_lastPacketSize - Initialized to 0;\r
+*\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
/* Initialize _hidProtocol variable to comply with HID 7.2.6 Set_Protocol\r
* Request: "When initialized, all devices default to report protocol."\r
*/\r
- #if defined(USBFS_ENABLE_HID_CLASS)\r
- uint8 i;\r
-\r
- for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++)\r
- {\r
- USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT;\r
- }\r
- #endif /* USBFS_ENABLE_HID_CLASS */\r
+#if defined(USBFS_ENABLE_HID_CLASS)\r
+ uint8 i;\r
\r
- USBFS_transferState = USBFS_TRANS_STATE_IDLE;\r
+ for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++)\r
+ {\r
+ USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT;\r
+ }\r
+#endif /* USBFS_ENABLE_HID_CLASS */\r
\r
- /* Clear all of the component data */\r
- USBFS_configuration = 0u;\r
- USBFS_interfaceNumber = 0u;\r
+ /* Reset component internal variables. */\r
+ USBFS_transferState = USBFS_TRANS_STATE_IDLE;\r
USBFS_configurationChanged = 0u;\r
- USBFS_deviceAddress = 0u;\r
- USBFS_deviceStatus = 0u;\r
-\r
- USBFS_lastPacketSize = 0u;\r
-\r
-\r
- /* ACK Setup, Stall IN/OUT */\r
- CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);\r
-\r
- /* Enable the SIE with an address 0 */\r
- CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE);\r
-\r
+ USBFS_configuration = 0u;\r
+ USBFS_interfaceNumber = 0u;\r
+ USBFS_deviceAddress = 0u;\r
+ USBFS_deviceStatus = 0u;\r
+ USBFS_lastPacketSize = 0u;\r
+\r
+#if (CY_PSOC4)\r
+ /* Set EP0.CR: ACK Setup, NAK IN/OUT. */\r
+ USBFS_EP0_CR_REG = USBFS_MODE_NAK_IN_OUT;\r
+#else\r
+ /* Set EP0.CR: ACK Setup, STALL IN/OUT. */\r
+ USBFS_EP0_CR_REG = USBFS_MODE_STALL_IN_OUT;\r
+#endif /* (CY_PSOC4) */\r
+\r
+ /* Enable device to respond to USB traffic with address 0. */\r
+ USBFS_CR0_REG = USBFS_DEFUALT_CR0;\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Stop\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function shuts down the USB function including to release\r
-* the D+ Pullup and disabling the SIE.\r
+* the D+ pull-up and disabling the SIE.\r
*\r
-* Parameters:\r
-* None.\r
+* \globalvars\r
+* \ref USBFS_configuration\r
*\r
-* Return:\r
-* None.\r
+* USBFS_deviceAddress - Contains the current device address. This\r
+* variable is initialized to zero in this API. The Host starts to communicate\r
+* to the device with address 0 and then sets it to a whatever value using\r
+* a SET_ADDRESS request.\r
*\r
-* Global variables:\r
-* USBFS_configuration: Contains current configuration number\r
-* which is set by the Host using SET_CONFIGURATION request.\r
-* Initialized to zero in this API.\r
-* USBFS_deviceAddress: Contains current device address. This\r
-* variable is initialized to zero in this API. Host starts to communicate\r
-* to device with address 0 and then set it to whatever value using\r
-* SET_ADDRESS request.\r
-* USBFS_deviceStatus: initialized to 0.\r
-* This is two bit variable which contain power status in first bit\r
-* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote\r
-* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit.\r
-* USBFS_configurationChanged: This variable is set to one after\r
-* SET_CONFIGURATION request and cleared in this function.\r
-* USBFS_intiVar variable is set to zero\r
+* \ref USBFS_deviceStatus\r
+*\r
+* \ref USBFS_configurationChanged\r
+*\r
+* USBFS_intiVar - This variable is set to zero\r
*\r
*******************************************************************************/\r
void USBFS_Stop(void) \r
{\r
+ uint8 enableInterrupts;\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+ /* Stop all DMA channels. */\r
+ USBFS_Stop_DMA(USBFS_MAX_EP);\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+ enableInterrupts = CyEnterCriticalSection();\r
+\r
+ /* Disable USB IP to respond to USB traffic. */\r
+ USBFS_CR0_REG &= (uint8) ~USBFS_CR0_ENABLE;\r
+\r
+ /* Disable D+ pull-up. */\r
+ USBFS_USBIO_CR1_REG &= (uint8) ~ USBFS_USBIO_CR1_USBPUEN;\r
+\r
+#if (CY_PSOC4)\r
+ /* Disable USBFS block. */\r
+ USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_ENABLE;\r
+#else\r
+ /* Clear power active and standby mode templates. */\r
+ USBFS_PM_ACT_CFG_REG &= (uint8) ~USBFS_PM_ACT_EN_FSUSB;\r
+ USBFS_PM_STBY_CFG_REG &= (uint8) ~USBFS_PM_STBY_EN_FSUSB;\r
+\r
+ /* Ensure single-ended disable bits are high (PRT15.INP_DIS[7:6])\r
+ * (input receiver disabled). */\r
+ USBFS_DM_INP_DIS_REG |= (uint8) USBFS_DM_MASK;\r
+ USBFS_DP_INP_DIS_REG |= (uint8) USBFS_DP_MASK;\r
\r
- #if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
+#endif /* (CY_PSOC4) */\r
\r
- /* Disable the SIE */\r
- USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE);\r
- /* Disable the d+ pullup */\r
- USBFS_USBIO_CR1_REG &= (uint8)(~USBFS_USBIO_CR1_USBPUEN);\r
- /* Disable USB in ACT PM */\r
- USBFS_PM_ACT_CFG_REG &= (uint8)(~USBFS_PM_ACT_EN_FSUSB);\r
- /* Disable USB block for Standby Power Mode */\r
- USBFS_PM_STBY_CFG_REG &= (uint8)(~USBFS_PM_STBY_EN_FSUSB);\r
+ CyExitCriticalSection(enableInterrupts);\r
+\r
+ /* Disable component interrupts. */\r
+#if (CY_PSOC4)\r
+ CyIntDisable(USBFS_INTR_HI_VECT_NUM);\r
+ CyIntDisable(USBFS_INTR_LO_VECT_NUM);\r
+ CyIntDisable(USBFS_INTR_MED_VECT_NUM);\r
+#else\r
\r
- /* Disable the reset and EP interrupts */\r
CyIntDisable(USBFS_BUS_RESET_VECT_NUM);\r
CyIntDisable(USBFS_EP_0_VECT_NUM);\r
- #if(USBFS_EP1_ISR_REMOVE == 0u)\r
+\r
+ #if (USBFS_SOF_ISR_ACTIVE)\r
+ CyIntDisable(USBFS_SOF_VECT_NUM);\r
+ #endif /* (USBFS_SOF_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP1_ISR_ACTIVE)\r
CyIntDisable(USBFS_EP_1_VECT_NUM);\r
- #endif /* USBFS_EP1_ISR_REMOVE */\r
- #if(USBFS_EP2_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP1_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP2_ISR_ACTIVE)\r
CyIntDisable(USBFS_EP_2_VECT_NUM);\r
- #endif /* USBFS_EP2_ISR_REMOVE */\r
- #if(USBFS_EP3_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP2_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP3_ISR_ACTIVE)\r
CyIntDisable(USBFS_EP_3_VECT_NUM);\r
- #endif /* USBFS_EP3_ISR_REMOVE */\r
- #if(USBFS_EP4_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP3_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP4_ISR_ACTIVE)\r
CyIntDisable(USBFS_EP_4_VECT_NUM);\r
- #endif /* USBFS_EP4_ISR_REMOVE */\r
- #if(USBFS_EP5_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP4_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP5_ISR_ACTIVE)\r
CyIntDisable(USBFS_EP_5_VECT_NUM);\r
- #endif /* USBFS_EP5_ISR_REMOVE */\r
- #if(USBFS_EP6_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP5_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP6_ISR_ACTIVE)\r
CyIntDisable(USBFS_EP_6_VECT_NUM);\r
- #endif /* USBFS_EP6_ISR_REMOVE */\r
- #if(USBFS_EP7_ISR_REMOVE == 0u)\r
+ #endif /* USBFS_EP6_ISR_REMOVE */\r
+\r
+ #if (USBFS_EP7_ISR_ACTIVE)\r
CyIntDisable(USBFS_EP_7_VECT_NUM);\r
- #endif /* USBFS_EP7_ISR_REMOVE */\r
- #if(USBFS_EP8_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP7_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP8_ISR_ACTIVE)\r
CyIntDisable(USBFS_EP_8_VECT_NUM);\r
- #endif /* USBFS_EP8_ISR_REMOVE */\r
+ #endif /* (USBFS_EP8_ISR_ACTIVE) */\r
\r
- /* Clear all of the component data */\r
- USBFS_configuration = 0u;\r
- USBFS_interfaceNumber = 0u;\r
+ #if (USBFS_DP_ISR_ACTIVE)\r
+ /* Clear active mode Dp interrupt source history. */\r
+ (void) USBFS_Dp_ClearInterrupt();\r
+ CyIntClearPending(USBFS_DP_INTC_VECT_NUM);\r
+ #endif /* (USBFS_DP_ISR_ACTIVE). */\r
+\r
+#endif /* (CY_PSOC4) */\r
+\r
+ /* Reset component internal variables. */\r
USBFS_configurationChanged = 0u;\r
- USBFS_deviceAddress = 0u;\r
- USBFS_deviceStatus = 0u;\r
- USBFS_initVar = 0u;\r
+ USBFS_configuration = 0u;\r
+ USBFS_interfaceNumber = 0u;\r
+ USBFS_deviceAddress = 0u;\r
+ USBFS_deviceStatus = 0u;\r
\r
+ /* It is mandatory for correct device startup. */\r
+ USBFS_initVar = 0u;\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_CheckActivity\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Returns the activity status of the bus. Clears the status hardware to\r
-* provide fresh activity status on the next call of this routine.\r
+* This function returns the activity status of the bus. It clears the hardware\r
+* status to provide updated status on the next call of this function. It\r
+* provides a way to determine whether any USB bus activity occurred. The\r
+* application should use this function to determine if the USB suspend\r
+* conditions are met.\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
-* 1 - If bus activity was detected since the last call to this function\r
-* 0 - If bus activity not was detected since the last call to this function\r
+* \return\r
+* cystatus: Status of the bus since the last call of the function.\r
+* Return Value | Description\r
+* -------------|---------------------------------------------------------------\r
+* 1 |Bus activity was detected since the last call to this function\r
+* 0 |Bus activity was not detected since the last call to this function\r
+*\r
*\r
*******************************************************************************/\r
uint8 USBFS_CheckActivity(void) \r
{\r
- uint8 r;\r
+ uint8 cr1Reg = USBFS_CR1_REG;\r
\r
- r = CY_GET_REG8(USBFS_CR1_PTR);\r
- CY_SET_REG8(USBFS_CR1_PTR, (r & ((uint8)(~USBFS_CR1_BUS_ACTIVITY))));\r
+ /* Clear bus activity. */\r
+ USBFS_CR1_REG = (cr1Reg & (uint8) ~USBFS_CR1_BUS_ACTIVITY);\r
\r
- return((r & USBFS_CR1_BUS_ACTIVITY) >> USBFS_CR1_BUS_ACTIVITY_SHIFT);\r
+ /* Get bus activity. */\r
+ return ((0u != (cr1Reg & USBFS_CR1_BUS_ACTIVITY)) ? (1u) : (0u));\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_GetConfiguration\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Returns the current configuration setting\r
+* This function gets the current configuration of the USB device.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* configuration.\r
+* \return\r
+* Returns the currently assigned configuration. Returns 0 if the device\r
+* is not configured\r
*\r
*******************************************************************************/\r
uint8 USBFS_GetConfiguration(void) \r
{\r
- return(USBFS_configuration);\r
+ return (USBFS_configuration);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_IsConfigurationChanged\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Returns the clear on read configuration state. It is usefull when PC send\r
-* double SET_CONFIGURATION request with same configuration number.\r
+* This function returns the clear-on-read configuration state. It is useful\r
+* when the host sends double SET_CONFIGURATION request with the same \r
+* configuration number or changes alternate settings of the interface. \r
+* After configuration has been changed the OUT endpoints must be enabled and IN \r
+* endpoint must be loaded with data to start communication with the host.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* Not zero value when new configuration has been changed, otherwise zero is\r
+* \return\r
+* None-zero value when new configuration has been changed, otherwise zero is\r
* returned.\r
*\r
-* Global variables:\r
-* USBFS_configurationChanged: This variable is set to one after\r
-* SET_CONFIGURATION request and cleared in this function.\r
+* \globalvars\r
+*\r
+* \ref USBFS_configurationChanged - This variable is set to 1 after\r
+* a SET_CONFIGURATION request and cleared in this function.\r
*\r
*******************************************************************************/\r
uint8 USBFS_IsConfigurationChanged(void) \r
{\r
uint8 res = 0u;\r
\r
- if(USBFS_configurationChanged != 0u)\r
+ if (USBFS_configurationChanged != 0u)\r
{\r
res = USBFS_configurationChanged;\r
USBFS_configurationChanged = 0u;\r
}\r
\r
- return(res);\r
+ return (res);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_GetInterfaceSetting\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Returns the alternate setting from current interface\r
+* This function gets the current alternate setting for the specified interface.\r
+* It is useful to identify which alternate settings are active in the specified \r
+* interface.\r
*\r
-* Parameters:\r
-* uint8 interfaceNumber, interface number\r
+* \param\r
+* interfaceNumber interface number\r
*\r
-* Return:\r
-* Alternate setting.\r
+* \return\r
+* Returns the current alternate setting for the specified interface.\r
*\r
*******************************************************************************/\r
uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber)\r
\r
{\r
- return(USBFS_interfaceSetting[interfaceNumber]);\r
+ return (USBFS_interfaceSetting[interfaceNumber]);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_GetEPState\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Returned the state of the requested endpoint.\r
+* This function returns the state of the requested endpoint.\r
*\r
-* Parameters:\r
-* epNumber: Endpoint Number\r
+* \param epNumber Data endpoint number\r
*\r
-* Return:\r
-* State of the requested endpoint.\r
+* \return\r
+* Returns the current state of the specified USBFS endpoint. Symbolic names and\r
+* their associated values are given in the following table. Use these constants\r
+* whenever you write code to change the state of the endpoints, such as ISR\r
+* code, to handle data sent or received.\r
+*\r
+* Return Value | Description\r
+* -----------------------|-----------------------------------------------------\r
+* USBFS_NO_EVENT_PENDING |The endpoint is awaiting SIE action\r
+* USBFS_EVENT_PENDING |The endpoint is awaiting CPU action\r
+* USBFS_NO_EVENT_ALLOWED |The endpoint is locked from access\r
+* USBFS_IN_BUFFER_FULL |The IN endpoint is loaded and the mode is set to ACK IN\r
+* USBFS_IN_BUFFER_EMPTY |An IN transaction occurred and more data can be loaded\r
+* USBFS_OUT_BUFFER_EMPTY |The OUT endpoint is set to ACK OUT and is waiting for data\r
+* USBFS_OUT_BUFFER_FULL |An OUT transaction has occurred and data can be read\r
*\r
*******************************************************************************/\r
uint8 USBFS_GetEPState(uint8 epNumber) \r
{\r
- return(USBFS_EP[epNumber].apiEpState);\r
+ return (USBFS_EP[epNumber].apiEpState);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_GetEPCount\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function supports Data Endpoints only(EP1-EP8).\r
* Returns the transfer count for the requested endpoint. The value from\r
* the count registers includes 2 counts for the two byte checksum of the\r
* packet. This function subtracts the two counts.\r
*\r
-* Parameters:\r
-* epNumber: Data Endpoint Number.\r
-* Valid values are between 1 and 8.\r
+* \param epNumber Data Endpoint Number.\r
+* Valid values are between 1 and 8.\r
*\r
-* Return:\r
+* \return\r
* Returns the current byte count from the specified endpoint or 0 for an\r
* invalid endpoint.\r
*\r
*******************************************************************************/\r
uint16 USBFS_GetEPCount(uint8 epNumber) \r
{\r
- uint8 ri;\r
- uint16 result = 0u;\r
+ uint16 cntr = 0u;\r
\r
- if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
+ if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
- ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
-\r
- result = (uint8)(CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) &\r
- USBFS_EPX_CNT0_MASK);\r
- result = (result << 8u) | CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri));\r
- result -= USBFS_EPX_CNTX_CRC_COUNT;\r
+ /* Get 11-bits EP counter where epCnt0 - 3 bits MSB and epCnt1 - 8 bits LSB. */\r
+ cntr = ((uint16) USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt0) & USBFS_EPX_CNT0_MASK;\r
+ cntr = ((uint16) (cntr << 8u)) | ((uint16) USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt1);\r
+ cntr -= USBFS_EPX_CNTX_CRC_COUNT;\r
}\r
- return(result);\r
+\r
+ return (cntr);\r
}\r
\r
\r
-#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+#if (CY_PSOC4)\r
+ /*******************************************************************************\r
+ * Function Name: USBFS_InitEpDma\r
+ ****************************************************************************//**\r
+ *\r
+ * This function configures priority for all DMA channels utilized by the\r
+ * component. Also sets callbacks for DMA auto mode.\r
+ *\r
+ *******************************************************************************/\r
+ static void USBFS_InitEpDma(void)\r
+ {\r
+ #if (USBFS_DMA1_ACTIVE)\r
+ CYDMA_CH_CTL_BASE.ctl[USBFS_ep1_dma_CHANNEL] = USBFS_ep1_dma_CHANNEL_CFG;\r
+ #endif /* (USBFS_DMA1_ACTIVE) */\r
+\r
+ #if (USBFS_DMA2_ACTIVE)\r
+ CYDMA_CH_CTL_BASE.ctl[USBFS_ep2_dma_CHANNEL] = USBFS_ep2_dma_CHANNEL_CFG;\r
+ #endif /* (USBFS_DMA2_ACTIVE) */\r
+\r
+ #if (USBFS_DMA3_ACTIVE)\r
+ CYDMA_CH_CTL_BASE.ctl[USBFS_ep3_dma_CHANNEL] = USBFS_ep3_dma_CHANNEL_CFG;\r
+ #endif /* (USBFS_DMA3_ACTIVE) */\r
+\r
+ #if (USBFS_DMA4_ACTIVE)\r
+ CYDMA_CH_CTL_BASE.ctl[USBFS_ep4_dma_CHANNEL] = USBFS_ep4_dma_CHANNEL_CFG;\r
+ #endif /* (USBFS_DMA4_ACTIVE) */\r
+\r
+ #if (USBFS_DMA5_ACTIVE)\r
+ CYDMA_CH_CTL_BASE.ctl[USBFS_ep5_dma_CHANNEL] = USBFS_ep5_dma_CHANNEL_CFG;\r
+ #endif /* (USBFS_DMA5_ACTIVE) */\r
+\r
+ #if (USBFS_DMA6_ACTIVE)\r
+ CYDMA_CH_CTL_BASE.ctl[USBFS_ep6_dma_CHANNEL] = USBFS_ep6_dma_CHANNEL_CFG;\r
+ #endif /* (USBFS_DMA6_ACTIVE) */\r
+\r
+ #if (USBFS_DMA7_ACTIVE)\r
+ CYDMA_CH_CTL_BASE.ctl[USBFS_ep7_dma_CHANNEL] = USBFS_ep7_dma_CHANNEL_CFG;\r
+ #endif /* (USBFS_DMA7_ACTIVE) */\r
+\r
+ #if (USBFS_DMA8_ACTIVE)\r
+ CYDMA_CH_CTL_BASE.ctl[USBFS_ep8_dma_CHANNEL] = USBFS_ep8_dma_CHANNEL_CFG;\r
+ #endif /* (USBFS_DMA8_ACTIVE) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Initialize DMA channel callbacks. */\r
+ #if (USBFS_DMA1_ACTIVE)\r
+ (void) USBFS_ep1_dma_SetInterruptCallback(&USBFS_EP1_DMA_DONE_ISR);\r
+ #endif /* (USBFS_DMA1_ACTIVE) */\r
+\r
+ #if (USBFS_DMA2_ACTIVE)\r
+ (void) USBFS_ep2_dma_SetInterruptCallback(&USBFS_EP2_DMA_DONE_ISR);\r
+ #endif /* (USBFS_DMA2_ACTIVE) */\r
+\r
+ #if (USBFS_DMA3_ACTIVE)\r
+ (void) USBFS_ep3_dma_SetInterruptCallback(&USBFS_EP3_DMA_DONE_ISR);\r
+ #endif /* (USBFS_DMA3_ACTIVE) */\r
+\r
+ #if (USBFS_DMA4_ACTIVE)\r
+ (void) USBFS_ep4_dma_SetInterruptCallback(&USBFS_EP4_DMA_DONE_ISR);\r
+ #endif /* (USBFS_DMA4_ACTIVE) */\r
+\r
+ #if (USBFS_DMA5_ACTIVE)\r
+ (void) USBFS_ep5_dma_SetInterruptCallback(&USBFS_EP5_DMA_DONE_ISR);\r
+ #endif /* (USBFS_DMA5_ACTIVE) */\r
+\r
+ #if (USBFS_DMA6_ACTIVE)\r
+ (void) USBFS_ep6_dma_SetInterruptCallback(&USBFS_EP6_DMA_DONE_ISR);\r
+ #endif /* (USBFS_DMA6_ACTIVE) */\r
+\r
+ #if (USBFS_DMA7_ACTIVE)\r
+ (void) USBFS_ep7_dma_SetInterruptCallback(&USBFS_EP7_DMA_DONE_ISR);\r
+ #endif /* (USBFS_DMA7_ACTIVE) */\r
+\r
+ #if (USBFS_DMA8_ACTIVE)\r
+ (void) USBFS_ep8_dma_SetInterruptCallback(&USBFS_EP8_DMA_DONE_ISR);\r
+ #endif /* (USBFS_DMA8_ACTIVE) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ }\r
+#else\r
\r
\r
- /*******************************************************************************\r
+ /***************************************************************************\r
* Function Name: USBFS_InitEP_DMA\r
- ********************************************************************************\r
+ ************************************************************************//**\r
*\r
- * Summary:\r
* This function allocates and initializes a DMA channel to be used by the\r
* USBFS_LoadInEP() or USBFS_ReadOutEP() APIs for data\r
- * transfer.\r
+ * transfer. It is available when the Endpoint Memory Management parameter\r
+ * is set to DMA.\r
*\r
- * Parameters:\r
- * epNumber: Contains the data endpoint number.\r
- * Valid values are between 1 and 8.\r
- * *pData: Pointer to a data array that is related to the EP transfers.\r
+ * This function is automatically called from the USBFS_LoadInEP() and USBFS_ReadOutEP() APIs.\r
*\r
- * Return:\r
- * None.\r
+ * \param epNumber Contains the data endpoint number.\r
+ * Valid values are between 1 and 8.\r
+ * \param *pData Pointer to a data array that is related to the EP transfers.\r
*\r
- * Reentrant:\r
- * No.\r
+ * \reentrant No.\r
*\r
- *******************************************************************************/\r
- void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)\r
+ ***************************************************************************/\r
+ void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)\r
\r
{\r
uint16 src;\r
uint16 dst;\r
- #if (CY_PSOC3) /* PSoC 3 */\r
- src = HI16(CYDEV_SRAM_BASE);\r
+\r
+ #if (CY_PSOC3)\r
+ src = HI16(CYDEV_SRAM_BASE);\r
+ dst = HI16(CYDEV_PERIPH_BASE);\r
+ pData = pData;\r
+ #else\r
+ if ((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u)\r
+ {\r
+ /* IN endpoint: source is memory buffer. */\r
+ src = HI16(pData);\r
dst = HI16(CYDEV_PERIPH_BASE);\r
- pData = pData;\r
- #else /* PSoC 5 */\r
- if((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u )\r
- { /* for the IN EP source is the SRAM memory buffer */\r
- src = HI16(pData);\r
- dst = HI16(CYDEV_PERIPH_BASE);\r
- }\r
- else\r
- { /* for the OUT EP source is the SIE register */\r
- src = HI16(CYDEV_PERIPH_BASE);\r
- dst = HI16(pData);\r
- }\r
- #endif /* C51 */\r
+ }\r
+ else\r
+ {\r
+ /* OUT endpoint: source is USB IP memory buffer. */\r
+ src = HI16(CYDEV_PERIPH_BASE);\r
+ dst = HI16(pData);\r
+ }\r
+ #endif /* (CY_PSOC3) */\r
+\r
switch(epNumber)\r
{\r
- case USBFS_EP1:\r
- #if(USBFS_DMA1_REMOVE == 0u)\r
- USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize(\r
- USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* USBFS_DMA1_REMOVE */\r
- break;\r
- case USBFS_EP2:\r
- #if(USBFS_DMA2_REMOVE == 0u)\r
- USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize(\r
- USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* USBFS_DMA2_REMOVE */\r
- break;\r
+ #if (USBFS_DMA1_ACTIVE)\r
+ case USBFS_EP1:\r
+ USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize(USBFS_DMA_BYTES_PER_BURST,\r
+ USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
+ break;\r
+ #endif /* (USBFS_DMA1_ACTIVE) */\r
+\r
+ #if (USBFS_DMA2_ACTIVE)\r
+ case USBFS_EP2:\r
+ USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize(USBFS_DMA_BYTES_PER_BURST,\r
+ USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
+ break;\r
+ #endif /* (USBFS_DMA2_ACTIVE) */\r
+\r
+ #if (USBFS_DMA3_ACTIVE)\r
case USBFS_EP3:\r
- #if(USBFS_DMA3_REMOVE == 0u)\r
- USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize(\r
- USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* USBFS_DMA3_REMOVE */\r
- break;\r
+ USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize(USBFS_DMA_BYTES_PER_BURST,\r
+ USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
+ break;\r
+ #endif /* (USBFS_DMA3_ACTIVE) */\r
+\r
+ #if (USBFS_DMA4_ACTIVE)\r
case USBFS_EP4:\r
- #if(USBFS_DMA4_REMOVE == 0u)\r
- USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize(\r
- USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* USBFS_DMA4_REMOVE */\r
- break;\r
+ USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize(USBFS_DMA_BYTES_PER_BURST,\r
+ USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
+ break;\r
+ #endif /* (USBFS_DMA4_ACTIVE) */\r
+\r
+ #if (USBFS_DMA5_ACTIVE)\r
case USBFS_EP5:\r
- #if(USBFS_DMA5_REMOVE == 0u)\r
- USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize(\r
- USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* USBFS_DMA5_REMOVE */\r
- break;\r
- case USBFS_EP6:\r
- #if(USBFS_DMA6_REMOVE == 0u)\r
- USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize(\r
- USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* USBFS_DMA6_REMOVE */\r
- break;\r
- case USBFS_EP7:\r
- #if(USBFS_DMA7_REMOVE == 0u)\r
- USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize(\r
- USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* USBFS_DMA7_REMOVE */\r
- break;\r
- case USBFS_EP8:\r
- #if(USBFS_DMA8_REMOVE == 0u)\r
- USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize(\r
- USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* USBFS_DMA8_REMOVE */\r
- break;\r
- default:\r
- /* Do not support EP0 DMA transfers */\r
- break;\r
+ USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize(USBFS_DMA_BYTES_PER_BURST,\r
+ USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
+ break;\r
+ #endif /* (USBFS_DMA5_ACTIVE) */\r
+\r
+ #if (USBFS_DMA6_ACTIVE)\r
+ case USBFS_EP6:\r
+ USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize(USBFS_DMA_BYTES_PER_BURST,\r
+ USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
+ break;\r
+ #endif /* (USBFS_DMA6_ACTIVE) */\r
+\r
+ #if (USBFS_DMA7_ACTIVE)\r
+ case USBFS_EP7:\r
+ USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize(USBFS_DMA_BYTES_PER_BURST,\r
+ USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
+ break;\r
+ #endif /* (USBFS_DMA7_ACTIVE) */\r
+\r
+ #if (USBFS_DMA8_ACTIVE)\r
+ case USBFS_EP8:\r
+ USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize(USBFS_DMA_BYTES_PER_BURST,\r
+ USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
+ break;\r
+ #endif /* (USBFS_DMA8_ACTIVE) */\r
+\r
+ default:\r
+ /* Do nothing for endpoints other than 1-8. */\r
+ break;\r
}\r
- if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
+\r
+ if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
USBFS_DmaTd[epNumber] = CyDmaTdAllocate();\r
- #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate();\r
- #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate();\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
}\r
}\r
+#endif /* (CY_PSOC4) */\r
\r
-\r
- /*******************************************************************************\r
+ /***************************************************************************\r
* Function Name: USBFS_Stop_DMA\r
- ********************************************************************************\r
- *\r
- * Summary: Stops and free DMA\r
+ ************************************************************************//**\r
+ * \r
+ * This function stops DMA channel associated with endpoint. It is available \r
+ * when the Endpoint Buffer Management parameter is set to DMA. Call this \r
+ * function when endpoint direction is changed from IN to OUT or vice versa \r
+ * to trigger DMA re-configuration when USBFS_LoadInEP() or \r
+ * USBFS_ReadOutEP() functions are called the first time. \r
+ * \r
+ * \param epNumber: The data endpoint number for which associated DMA \r
+ * channel is stopped. The range of valid values is between 1 and 8. To stop \r
+ * all DMAs associated with endpoints call this function with \r
+ * USBFS_MAX_EP argument.\r
*\r
- * Parameters:\r
- * epNumber: Contains the data endpoint number or\r
- * USBFS_MAX_EP to stop all DMAs\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Reentrant:\r
+ * \reentrant\r
* No.\r
*\r
- *******************************************************************************/\r
+ ***************************************************************************/\r
void USBFS_Stop_DMA(uint8 epNumber) \r
{\r
uint8 i;\r
+\r
i = (epNumber < USBFS_MAX_EP) ? epNumber : USBFS_EP1;\r
+\r
do\r
{\r
+ #if (CY_PSOC4)\r
+ if (0u != USBFS_DmaChan[i])\r
+ {\r
+ USBFS_CyDmaChDisable(USBFS_DmaChan[i]);\r
+ }\r
+ #else\r
if(USBFS_DmaTd[i] != DMA_INVALID_TD)\r
{\r
(void) CyDmaChDisable(USBFS_DmaChan[i]);\r
CyDmaTdFree(USBFS_DmaTd[i]);\r
USBFS_DmaTd[i] = DMA_INVALID_TD;\r
}\r
- #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
if(USBFS_DmaNextTd[i] != DMA_INVALID_TD)\r
{\r
CyDmaTdFree(USBFS_DmaNextTd[i]);\r
USBFS_DmaNextTd[i] = DMA_INVALID_TD;\r
}\r
- #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+\r
+ #endif /* (CY_PSOC4) */\r
i++;\r
- }while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP));\r
+ }\r
+ while ((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP));\r
}\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
\r
-#endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
-\r
-#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
-\r
-\r
- /*******************************************************************************\r
+#if (CY_PSOC3 || CY_PSOC5)\r
+#if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ /***************************************************************************\r
* Function Name: USBFS_LoadNextInEP\r
- ********************************************************************************\r
+ ************************************************************************//**\r
*\r
* Summary:\r
* This internal function is used for IN endpoint DMA reconfiguration in\r
* mode: 0 - Configure DMA to send the the rest of data.\r
* 1 - Configure DMA to repeat 2 last bytes of the first burst.\r
*\r
- * Return:\r
- * None.\r
- *\r
- *******************************************************************************/\r
+ ***************************************************************************/\r
void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) \r
{\r
reg16 *convert;\r
\r
- if(mode == 0u)\r
+ if (mode == 0u)\r
{\r
- /* Configure DMA to send the the rest of data */\r
- /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */\r
+ /* Configure DMA to send rest of data. */\r
+ /* CyDmaTdSetConfiguration API is optimized to change transfer length only and configure TD. */\r
convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];\r
- /* Set transfer length */\r
+ /* Set transfer length. */\r
CY_SET_REG16(convert, USBFS_inLength[epNumber] - USBFS_DMA_BYTES_PER_BURST);\r
- /* CyDmaTdSetAddress API is optimized to change only source address */\r
+ /* CyDmaTdSetAddress API is optimized to change source address only. */\r
convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];\r
CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +\r
USBFS_DMA_BYTES_PER_BURST));\r
else\r
{\r
/* Configure DMA to repeat 2 last bytes of the first burst. */\r
- /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */\r
+ /* CyDmaTdSetConfiguration API is optimized to change transfer length only and configure TD. */\r
convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];\r
- /* Set transfer length */\r
+ /* Set transfer length. */\r
CY_SET_REG16(convert, USBFS_DMA_BYTES_REPEAT);\r
- /* CyDmaTdSetAddress API is optimized to change only source address */\r
+ /* CyDmaTdSetAddress API is optimized to change source address only. */\r
convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];\r
CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +\r
- USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT));\r
+ (USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT)));\r
}\r
\r
- /* CyDmaChSetInitialTd API is optimised to init TD */\r
+ /* CyDmaChSetInitialTd API is optimized to initialize TD. */\r
CY_DMA_CH_STRUCT_PTR[USBFS_DmaChan[epNumber]].basic_status[1u] = USBFS_DmaTd[epNumber];\r
}\r
-#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+#endif /* (CY_PSOC3 || CY_PSOC5) */\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_LoadInEP\r
-********************************************************************************\r
+****************************************************************************//**\r
+*\r
+* This function performs different functionality depending on the Component’s\r
+* configured Endpoint Buffer Management. This parameter is defined in\r
+* the Descriptor Root in Component Configure window.\r
*\r
-* Summary:\r
-* Loads and enables the specified USB data endpoint for an IN transfer.\r
+* *Manual (Static/Dynamic Allocation):*\r
+* This function loads and enables the specified USB data endpoint for an IN\r
+* data transfer.\r
*\r
-* Parameters:\r
-* epNumber: Contains the data endpoint number.\r
+* *DMA with Manual Buffer Management:*\r
+* Configures DMA for a data transfer from system RAM to endpoint buffer.\r
+* Generates request for a transfer.\r
+*\r
+* *DMA with Automatic Buffer Management:*\r
+* Configures DMA. This is required only once, so it is done only when parameter\r
+* pData is not NULL. When the pData pointer is NULL, the function skips this\r
+* task. Sets Data ready status: This generates the first DMA transfer and\r
+* prepares data in endpoint buffer.\r
+*\r
+* \param epNumber Contains the data endpoint number.\r
* Valid values are between 1 and 8.\r
-* *pData: A pointer to a data array from which the data for the endpoint space\r
+* \param *pData A pointer to a data array from which the data for the endpoint space\r
* is loaded.\r
-* length: The number of bytes to transfer from the array and then send as a\r
-* result of an IN request. Valid values are between 0 and 512.\r
+* \param length The number of bytes to transfer from the array and then send as\r
+* a result of an IN request. Valid values are between 0 and 512\r
+* (1023 for DMA with Automatic Buffer Management mode). The value 512\r
+* is applicable if only one endpoint is used.\r
*\r
-* Return:\r
-* None.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)\r
\r
{\r
- uint8 ri;\r
- reg8 *p;\r
- #if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
- uint16 i;\r
- #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
-\r
- if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
+ if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
- ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
- p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri);\r
+ #if (!USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Limit length to available buffer USB IP buffer size.*/\r
+ if (length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset))\r
+ {\r
+ length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset;\r
+ }\r
+ #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+\r
+ /* Set count and data toggle. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt0 = (uint8) HI8(length) | USBFS_EP[epNumber].epToggle;\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt1 = (uint8) LO8(length);\r
\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- /* Limits length to available buffer space, auto MM could send packets up to 1024 bytes */\r
- if(length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset))\r
+ #if (USBFS_EP_MANAGEMENT_MANUAL)\r
+ if (NULL != pData)\r
+ {\r
+ /* Copy data using arbiter data register. */\r
+ uint16 i;\r
+ for (i = 0u; i < length; ++i)\r
{\r
- length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset;\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr = pData[i];\r
}\r
- #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ }\r
\r
- /* Set the count and data toggle */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri),\r
- (length >> 8u) | (USBFS_EP[epNumber].epToggle));\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri), length & 0xFFu);\r
+ /* IN endpoint buffer is full - read to be read. */\r
+ USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
\r
- #if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
- if(pData != NULL)\r
- {\r
- /* Copy the data using the arbiter data register */\r
- for (i = 0u; i < length; i++)\r
- {\r
- CY_SET_REG8(p, pData[i]);\r
- }\r
- }\r
- USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
- /* Write the Mode register */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);\r
- #else\r
- /* Init DMA if it was not initialized */\r
- if (USBFS_DmaTd[epNumber] == DMA_INVALID_TD)\r
+ /* Arm IN endpoint. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode;\r
+\r
+ #else\r
+\r
+ #if (CY_PSOC3 || CY_PSOC5LP)\r
+ /* Initialize DMA if it was not initialized. */\r
+ if (DMA_INVALID_TD == USBFS_DmaTd[epNumber])\r
{\r
USBFS_InitEP_DMA(epNumber, pData);\r
}\r
- #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
\r
- #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
+ #if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ /* IN endpoint buffer will be fully loaded by DMA shortly. */\r
USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
+\r
if ((pData != NULL) && (length > 0u))\r
{\r
- /* Enable DMA in mode2 for transferring data */\r
+ #if (CY_PSOC4)\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+\r
+ /* Disable DMA channel: start configuration. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Configure source and destination. */\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData);\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr);\r
+\r
+ /* Configure DMA descriptor. */\r
+ --length;\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | length |\r
+ CYDMA_BYTE | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE);\r
+\r
+ /* Validate descriptor to execute on following DMA request. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+ #else\r
+ /* Configure DMA to transfer data. */\r
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);\r
- (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD,\r
- TD_TERMIN_EN | TD_INC_SRC_ADR);\r
- (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));\r
- /* Enable the DMA */\r
+ (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, TD_TERMIN_EN | TD_INC_SRC_ADR);\r
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) pData), LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr));\r
+\r
+ /* Enable DMA channel. */\r
(void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);\r
(void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);\r
- /* Generate DMA request */\r
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ;\r
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ));\r
- /* Mode register will be written in arb ISR after DMA transfer complete */\r
+ #endif /* (CY_PSOC4) */\r
+\r
+ /* Generate DMA request. */\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint8) USBFS_ARB_EPX_CFG_DMA_REQ;\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_DMA_REQ;\r
+\r
+ /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */\r
}\r
else\r
{\r
- /* When zero-length packet - write the Mode register directly */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);\r
+ /* When zero-length packet: arm IN endpoint directly. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode;\r
}\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
if (pData != NULL)\r
{\r
- /* Enable DMA in mode3 for transferring data */\r
+ #if (CY_PSOC4)\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+\r
+ /* Store address of buffer. */\r
+ USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData;\r
+\r
+ /* Disable DMA channel: start configuration. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Set destination address. */\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr);\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr);\r
+\r
+ /* Configure DMA descriptor. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG |\r
+ CYDMA_BYTE | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN);\r
+\r
+ /* Configure DMA descriptor. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG |\r
+ CYDMA_BYTE | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN);\r
+\r
+ /* Enable interrupt from DMA channel. */\r
+ USBFS_CyDmaSetInterruptMask(channelNum);\r
+\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+\r
+ #else\r
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);\r
- #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
- USBFS_inLength[epNumber] = length;\r
- USBFS_inDataPointer[epNumber] = pData;\r
- /* Configure DMA to send the data only for the first burst */\r
- (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber],\r
- (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length,\r
- USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);\r
- (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));\r
- /* The second TD will be executed only when the first one fails.\r
- * The intention of this TD is to generate NRQ interrupt\r
- * and repeat 2 last bytes of the first burst.\r
- */\r
- (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u,\r
- USBFS_DmaNextTd[epNumber],\r
- USBFS_epX_TD_TERMOUT_EN[epNumber]);\r
- /* Configure DmaNextTd to clear Data ready status */\r
- (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber], LO16((uint32)&clearInDataRdyStatus),\r
- LO16((uint32)(USBFS_ARB_EP1_CFG_IND + ri)));\r
- #else /* Configure DMA to send all data*/\r
- (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length,\r
- USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);\r
- (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));\r
- #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */\r
-\r
- /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */\r
- (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);\r
- /* Enable the DMA */\r
+\r
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ USBFS_inLength[epNumber] = length;\r
+ USBFS_inDataPointer[epNumber] = pData;\r
+\r
+ /* Configure DMA to send data only for first burst */\r
+ (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber],\r
+ (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length,\r
+ USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);\r
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) pData),\r
+ LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr));\r
+\r
+ /* The second TD will be executed only when the first one fails.\r
+ * The intention of this TD is to generate NRQ interrupt\r
+ * and repeat 2 last bytes of the first burst.\r
+ */\r
+ (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u,\r
+ USBFS_DmaNextTd[epNumber],\r
+ USBFS_epX_TD_TERMOUT_EN[epNumber]);\r
+\r
+ /* Configure DmaNextTd to clear Data Ready status. */\r
+ (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber], LO16((uint32) &clearInDataRdyStatus),\r
+ LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg));\r
+ #else\r
+ /* Configure DMA to send all data. */\r
+ (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length,\r
+ USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);\r
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) pData),\r
+ LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr));\r
+ #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+\r
+ /* Clear any potential pending DMA requests before starting DMA channel to transfer data. */\r
+ (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);\r
+ /* Enable DMA. */\r
(void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);\r
(void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);\r
+ #endif /* (CY_PSOC4) */\r
}\r
else\r
{\r
+ /* IN endpoint buffer (32 bytes) will shortly be preloaded by DMA. */\r
USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
- if(length > 0u)\r
+\r
+ if (length > 0u)\r
{\r
- #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
- USBFS_inLength[epNumber] = length;\r
+ #if (CY_PSOC4)\r
+ uint32 lengthDescr0, lengthDescr1;\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+\r
+ /* Get number of full bursts. */\r
+ USBFS_DmaEpBurstCnt[epNumber] = (uint8) (length / USBFS_DMA_BYTES_PER_BURST);\r
+\r
+ /* Get number of elements in the last burst. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (length % USBFS_DMA_BYTES_PER_BURST);\r
+\r
+ /* Get total number of bursts. */\r
+ USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u;\r
+\r
+ /* Adjust number of data elements transferred in last burst. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ?\r
+ (USBFS_DmaEpLastBurstEl[epNumber] - 1u) :\r
+ (USBFS_DMA_BYTES_PER_BURST - 1u);\r
+\r
+ /* Get number of data elements to transfer for descriptor 0 and 1. */\r
+ lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u);\r
+ lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u);\r
+\r
+\r
+ /* Mark which descriptor is last one to execute. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ?\r
+ USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK;\r
+\r
+ /* Restore DMA settings for current transfer. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Restore destination address for input endpoint. */\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber]));\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber] +\r
+ USBFS_DMA_BYTES_PER_BURST));\r
+\r
+ /* Set number of elements to transfer. */\r
+ USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR0, lengthDescr0);\r
+ USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR1, lengthDescr1);\r
+\r
+ /* Validate descriptor 0 and command to start with it. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
+ USBFS_CyDmaSetDescriptor0Next(channelNum);\r
+\r
+ /* Validate descriptor 1. */\r
+ if (USBFS_DmaEpBurstCnt[epNumber] > 1u)\r
+ {\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1); \r
+ } \r
+\r
+ /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */\r
+ USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]);\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+\r
+ #elif (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ USBFS_inLength[epNumber] = length;\r
USBFS_inBufFull[epNumber] = 0u;\r
+\r
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);\r
- /* Configure DMA to send the data only for the first burst */\r
+ /* Configure DMA to send data only for first burst. */\r
(void) CyDmaTdSetConfiguration(\r
USBFS_DmaTd[epNumber], (length > USBFS_DMA_BYTES_PER_BURST) ?\r
USBFS_DMA_BYTES_PER_BURST : length,\r
USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR );\r
- (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],\r
- LO16((uint32)USBFS_inDataPointer[epNumber]), LO16((uint32)p));\r
- /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */\r
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) USBFS_inDataPointer[epNumber]),\r
+ LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr));\r
+ /* Clear Any potential pending DMA requests before starting DMA channel to transfer data. */\r
(void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);\r
- /* Enable the DMA */\r
+ /* Enable DMA. */\r
(void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);\r
(void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);\r
- #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+ #endif /* (CY_PSOC4) */\r
+\r
+ #if !defined (USBFS_MANUAL_IN_EP_ARM)\r
+ /* Set IN data ready to generate DMA request to load data into endpoint buffer. */\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+ #endif /* (USBFS_MANUAL_IN_EP_ARM) */\r
\r
- /* Set Data ready status, This will generate DMA request */\r
- #ifndef USBFS_MANUAL_IN_EP_ARM\r
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
- #endif /* USBFS_MANUAL_IN_EP_ARM */\r
- /* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */\r
+ /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */\r
}\r
else\r
{\r
- /* When zero-length packet - write the Mode register directly */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);\r
+ /* When zero-length packet: arm IN endpoint directly. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode;\r
}\r
}\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */\r
}\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ReadOutEP\r
-********************************************************************************\r
+****************************************************************************//**\r
+*\r
+* This function performs different functionality depending on the Component’s\r
+* configured Endpoint Buffer Management. This parameter is defined in the\r
+* Descriptor Root in Component Configure window.\r
+*\r
+* *Manual (Static/Dynamic Allocation):*\r
+* This function moves the specified number of bytes from endpoint buffer to\r
+* system RAM. The number of bytes actually transferred from endpoint buffer to\r
+* system RAM is the lesser of the actual number of bytes sent by the host or\r
+* the number of bytes requested by the length parameter.\r
+*\r
+* *DMA with Manual Buffer Management:*\r
+* Configure DMA to transfer data from endpoint buffer to system RAM. Generate\r
+* a DMA request. The firmware must wait until the DMA completes the data\r
+* transfer after calling the USBFS_ReadOutEP() API. For example,\r
+* by checking EPstate:\r
+*\r
+* \snippet /USBFS_sut_02.cydsn/main.c checking EPstatey\r
+*\r
+* The USBFS_EnableOutEP() has to be called to allow host to write data into\r
+* the endpoint buffer after DMA has completed transfer data from OUT endpoint\r
+* buffer to SRAM.\r
*\r
-* Summary:\r
-* Read data from an endpoint. The application must call\r
-* USBFS_GetEPState to see if an event is pending.\r
+* *DMA with Automatic Buffer Management:*\r
+* Configure DMA. This is required only once and automatically generates DMA\r
+* requests as data arrives\r
*\r
-* Parameters:\r
-* epNumber: Contains the data endpoint number.\r
+* \param epNumber: Contains the data endpoint number.\r
* Valid values are between 1 and 8.\r
-* pData: A pointer to a data array from which the data for the endpoint space\r
-* is loaded.\r
-* length: The number of bytes to transfer from the USB Out endpoint and loads\r
-* it into data array. Valid values are between 0 and 1023. The function\r
-* moves fewer than the requested number of bytes if the host sends\r
-* fewer bytes than requested.\r
-*\r
-* Returns:\r
+* \param pData: A pointer to a data array from which the data for the endpoint\r
+* space is loaded.\r
+* \param length: The number of bytes to transfer from the USB Out endpoint and\r
+* loads it into data array. Valid values are between 0 and 1023. The\r
+* function moves fewer than the requested number of bytes if the host\r
+* sends fewer bytes than requested.\r
+*\r
+* \return\r
* Number of bytes received, 0 for an invalid endpoint.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)\r
\r
{\r
- uint8 ri;\r
- reg8 *p;\r
- #if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
- uint16 i;\r
- #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- uint16 xferCount;\r
- #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
-\r
- if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL))\r
+ if ((pData != NULL) && (epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
- ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
- p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri);\r
+ #if (!USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Adjust requested length to available data. */\r
+ length = (length > USBFS_GetEPCount(epNumber)) ? USBFS_GetEPCount(epNumber) : length;\r
+ #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- /* Determine which is smaller the requested data or the available data */\r
- xferCount = USBFS_GetEPCount(epNumber);\r
- if (length > xferCount)\r
+ #if (USBFS_EP_MANAGEMENT_MANUAL)\r
+ {\r
+ /* Copy data using arbiter data register. */\r
+ uint16 i;\r
+ for (i = 0u; i < length; ++i)\r
{\r
- length = xferCount;\r
+ pData[i] = (uint8) USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr;\r
}\r
- #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ }\r
\r
- #if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
- /* Copy the data using the arbiter data register */\r
- for (i = 0u; i < length; i++)\r
- {\r
- pData[i] = CY_GET_REG8(p);\r
- }\r
+ /* Arm OUT endpoint after data has been copied from endpoint buffer. */\r
+ USBFS_EnableOutEP(epNumber);\r
+ #else\r
\r
- /* (re)arming of OUT endpoint */\r
- USBFS_EnableOutEP(epNumber);\r
- #else\r
- /*Init DMA if it was not initialized */\r
- if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD)\r
+ #if (CY_PSOC3 || CY_PSOC5LP)\r
+ /* Initialize DMA if it was not initialized. */\r
+ if (DMA_INVALID_TD == USBFS_DmaTd[epNumber])\r
{\r
USBFS_InitEP_DMA(epNumber, pData);\r
}\r
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
\r
- #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
+ #if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ #if (CY_PSOC4)\r
+ {\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
\r
- #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
- /* Enable DMA in mode2 for transferring data */\r
+ /* Disable DMA channel: start configuration. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Configure source and destination. */\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr);\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData);\r
+\r
+ /* Configure DMA descriptor. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | (uint16)(length - 1u) |\r
+ CYDMA_BYTE | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE);\r
+\r
+ /* Validate descriptor to execute on following DMA request. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+ }\r
+ #else\r
+ /* Configure DMA to transfer data. */\r
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);\r
- (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD,\r
- TD_TERMIN_EN | TD_INC_DST_ADR);\r
- (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData));\r
- /* Enable the DMA */\r
+ (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, TD_TERMIN_EN | TD_INC_DST_ADR);\r
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr), LO16((uint32)pData));\r
+\r
+ /* Enable DMA channel. */\r
(void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);\r
(void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);\r
+ #endif /* (CY_PSOC4) */\r
+\r
+ /* Generate DMA request. */\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint8) USBFS_ARB_EPX_CFG_DMA_REQ;\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_DMA_REQ;\r
+\r
+ /* OUT endpoint has to be armed again by user when DMA transfers have been completed.\r
+ * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer.\r
+ */\r
+\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ #if (CY_PSOC4)\r
+ {\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+ uint32 lengthDescr0, lengthDescr1;\r
+\r
+ /* Get number of full bursts. */\r
+ USBFS_DmaEpBurstCnt[epNumber] = (uint8) (length / USBFS_DMA_BYTES_PER_BURST);\r
+\r
+ /* Get number of elements in the last burst. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (length % USBFS_DMA_BYTES_PER_BURST);\r
+\r
+ /* Get total number of bursts. */\r
+ USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u;\r
+\r
+ /* Adjust number of the data elements transfered in last burst. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ?\r
+ (USBFS_DmaEpLastBurstEl[epNumber] - 1u) :\r
+ (USBFS_DMA_BYTES_PER_BURST - 1u);\r
+\r
+ /* Get number of data elements to transfer for descriptor 0 and 1. */\r
+ lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u);\r
+ lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u);\r
+\r
+ /* Mark if revert number of data elements in descriptor after transfer completion. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] |= (USBFS_DmaEpBurstCnt[epNumber] > 2u) ? USBFS_DMA_DESCR_REVERT : 0u;\r
+\r
+ /* Mark last descriptor to be executed. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ?\r
+ USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK;\r
+\r
+ /* Store address of buffer and burst counter for endpoint. */\r
+ USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData;\r
+ USBFS_DmaEpBurstCntBackup[epNumber] = USBFS_DmaEpBurstCnt[epNumber];\r
+\r
+ /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */\r
+ USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]);\r
+\r
+ /* Disable DMA channel: start configuration. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Set destination address. */\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr);\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr);\r
+\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) pData));\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) pData + USBFS_DMA_BYTES_PER_BURST));\r
+\r
+ /* Configure DMA descriptor. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | lengthDescr0 |\r
+ CYDMA_BYTE | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN);\r
+\r
+ /* Configure DMA descriptor. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG | lengthDescr1 |\r
+ CYDMA_BYTE | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN);\r
+\r
+ /* Enable interrupt from DMA channel. */\r
+ USBFS_CyDmaSetInterruptMask(channelNum);\r
\r
- /* Generate DMA request */\r
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ;\r
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ));\r
- /* Out EP will be (re)armed in arb ISR after transfer complete */\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
+ /* Validate DMA descriptor 0 and 1. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- /* Enable DMA in mode3 for transferring data */\r
+ if (USBFS_DmaEpBurstCntBackup[epNumber] > 1u)\r
+ {\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1);\r
+ }\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+ }\r
+ #else\r
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);\r
- (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, USBFS_DmaTd[epNumber],\r
- TD_TERMIN_EN | TD_INC_DST_ADR);\r
- (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData));\r
+ (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_DST_ADR);\r
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr), LO16((uint32) pData));\r
\r
- /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */\r
+ /* Clear Any potential pending DMA requests before starting DMA channel to transfer data. */\r
(void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);\r
- /* Enable the DMA */\r
+\r
+ /* Enable DMA channel. */\r
(void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);\r
(void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);\r
- /* Out EP will be (re)armed in arb ISR after transfer complete */\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* (CY_PSOC4) */\r
+\r
+ /* OUT endpoint has to be armed again by user when DMA transfers have been completed.\r
+ * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer.\r
+ */\r
+\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */\r
+ }\r
+ else\r
+ {\r
+ length = 0u;\r
+ }\r
+\r
+ return (length);\r
+}\r
+\r
+\r
+#if (USBFS_16BITS_EP_ACCESS_ENABLE)\r
+/*******************************************************************************\r
+* Function Name: USBFS_LoadInEP16\r
+****************************************************************************//**\r
+*\r
+* This function performs different functionality depending on the Component’s\r
+* configured Endpoint Buffer Management. This parameter is defined in\r
+* the Descriptor Root in Component Configure window.\r
+*\r
+* *Manual (Static/Dynamic Allocation):*\r
+* This function loads and enables the specified USB data endpoint for an IN\r
+* data transfer.\r
+*\r
+* *DMA with Manual Buffer Management:*\r
+* Configures DMA for a data transfer from system RAM to endpoint buffer.\r
+* Generates request for a transfer.\r
+*\r
+* *DMA with Automatic Buffer Management:*\r
+* Configures DMA. This is required only once, so it is done only when parameter\r
+* pData is not NULL. When the pData pointer is NULL, the function skips this\r
+* task. Sets Data ready status: This generates the first DMA transfer and\r
+* prepares data in endpoint buffer.\r
+*\r
+* \param epNumber Contains the data endpoint number.\r
+* Valid values are between 1 and 8.\r
+* \param *pData A pointer to a data array from which the data for the endpoint\r
+* space is loaded. It shall be ensured that this pointer address is even\r
+* to ensure the 16-bit transfer is aligned to even address. Else, a hard\r
+* fault condition can occur.\r
+* \param length The number of bytes to transfer from the array and then send as\r
+* a result of an IN request. Valid values are between 0 and 512 (1023 for\r
+* DMA with Automatic Buffer Management mode). The value 512 is applicable\r
+* if only one endpoint is used.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void USBFS_LoadInEP16(uint8 epNumber, const uint8 pData[], uint16 length)\r
+{\r
+ /* Check array alignment on half-word boundary. */\r
+ CYASSERT(0u == (((uint32) pData) & 0x01u));\r
+\r
+ if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
+ {\r
+ #if (!USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Limit length to available buffer USB IP buffer size. */\r
+ if (length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset))\r
+ {\r
+ length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset;\r
+ }\r
+ #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+\r
+ /* Set count and data toggle. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt0 = (uint32) HI8(length) | USBFS_EP[epNumber].epToggle;\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt1 = (uint32) LO8(length);\r
+\r
+ /* Adjust requested length: 2 bytes are handled at one data register access. */\r
+ length += (length & 0x01u);\r
+\r
+ #if (USBFS_EP_MANAGEMENT_MANUAL)\r
+ if (NULL != pData)\r
+ {\r
+ /* Convert uint8 array to uint16. */\r
+ const uint16 *dataBuf = (uint16 *) pData;\r
+\r
+ /* Copy data using 16-bits arbiter data register. */\r
+ uint16 i;\r
+ for (i = 0u; i < (length >> 1u); ++i)\r
+ {\r
+ USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16 = dataBuf[i];\r
+ }\r
+ }\r
+\r
+ /* IN endpoint buffer is full - read to be read. */\r
+ USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
+\r
+ /* Arm IN endpoint. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode;\r
+\r
+ #else\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ /* IN endpoint buffer will be fully loaded by DMA shortly. */\r
+ USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
+\r
+ if ((pData != NULL) && (length > 0u))\r
+ {\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+\r
+ /* Disable DMA channel: start configuration. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Configure source and destination. */\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData);\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16);\r
+\r
+ /* Configure DMA descriptor. */\r
+ length = (length >> 1u) - 1u;\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | length |\r
+ CYDMA_HALFWORD | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE);\r
+\r
+ /* Validate descriptor to execute on following DMA request. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+\r
+ /* Generate DMA request. */\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint32) USBFS_ARB_EPX_CFG_DMA_REQ;\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint32) ~USBFS_ARB_EPX_CFG_DMA_REQ;\r
+\r
+ /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */\r
+ }\r
+ else\r
+ {\r
+ /* When zero-length packet: arm IN endpoint directly. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode;\r
+ }\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (pData != NULL)\r
+ {\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+\r
+ /* Store address of buffer. */\r
+ USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData;\r
+\r
+ /* Disable DMA channel: start configuration. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Set destination address. */\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16);\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16);\r
+\r
+ /* Configure DMA descriptor. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG |\r
+ CYDMA_HALFWORD | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN);\r
+\r
+ /* Configure DMA descriptor. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG |\r
+ CYDMA_HALFWORD | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN);\r
+\r
+ /* Enable interrupt from DMA channel. */\r
+ USBFS_CyDmaSetInterruptMask(channelNum);\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+ }\r
+ else\r
+ {\r
+ /* IN endpoint buffer (32 bytes) will shortly be preloaded by DMA. */\r
+ USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
+\r
+ if (length > 0u)\r
+ {\r
+ uint32 lengthDescr0, lengthDescr1;\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+\r
+ /* Get number of full bursts. */\r
+ USBFS_DmaEpBurstCnt[epNumber] = (uint8) (length / USBFS_DMA_BYTES_PER_BURST);\r
+\r
+ /* Get number of elements in the last burst. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (length % USBFS_DMA_BYTES_PER_BURST);\r
+\r
+ /* Get total number of bursts. */\r
+ USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u;\r
+\r
+ /* Adjust number of data elements transferred in last burst. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ?\r
+ ((USBFS_DmaEpLastBurstEl[epNumber] >> 1u) - 1u) :\r
+ (USBFS_DMA_HALFWORDS_PER_BURST - 1u);\r
+\r
+ /* Get number of data elements to transfer for descriptor 0 and 1. */\r
+ lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u);\r
+ lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u);\r
+\r
+ /* Mark which descriptor is last one to execute. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ?\r
+ USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK;\r
+\r
+ /* Restore DMA settings for current transfer. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Restore destination address for input endpoint. */\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber]));\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber] +\r
+ USBFS_DMA_BYTES_PER_BURST));\r
+\r
+ /* Set number of elements to transfer. */\r
+ USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR0, lengthDescr0);\r
+ USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR1, lengthDescr1);\r
+\r
+ /* Validate descriptor 0 and command to start with it. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
+ USBFS_CyDmaSetDescriptor0Next(channelNum);\r
+\r
+ /* Validate descriptor 1. */\r
+ if (USBFS_DmaEpBurstCnt[epNumber] > 1u)\r
+ {\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1);\r
+ }\r
+\r
+ /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */\r
+ USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]);\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+\r
+ #if !defined (USBFS_MANUAL_IN_EP_ARM)\r
+ /* Set IN data ready to generate DMA request to load data into endpoint buffer. */\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+ #endif /* (USBFS_MANUAL_IN_EP_ARM) */\r
+\r
+ /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */\r
+ }\r
+ else\r
+ {\r
+ /* When zero-length packet: arm IN endpoint directly. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode;\r
+ }\r
+ }\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_ReadOutEP16\r
+****************************************************************************//**\r
+*\r
+* This function performs different functionality depending on the Component’s\r
+* configured Endpoint Buffer Management. This parameter is defined in the\r
+* Descriptor Root in Component Configure window.\r
+*\r
+* *Manual (Static/Dynamic Allocation):*\r
+* This function moves the specified number of bytes from endpoint buffer to\r
+* system RAM. The number of bytes actually transferred from endpoint buffer to\r
+* system RAM is the lesser of the actual number of bytes sent by the host or\r
+* the number of bytes requested by the length parameter.\r
+*\r
+* *DMA with Manual Buffer Management:*\r
+* Configure DMA to transfer data from endpoint buffer to system RAM. Generate\r
+* a DMA request. The firmware must wait until the DMA completes the data\r
+* transfer after calling the USBFS_ReadOutEP() API. For example,\r
+* by checking EPstate:\r
+*\r
+* \snippet /USBFS_sut_02.cydsn/main.c checking EPstatey\r
+*\r
+* The USBFS_EnableOutEP() has to be called to allow host to write data into\r
+* the endpoint buffer after DMA has completed transfer data from OUT endpoint\r
+* buffer to SRAM.\r
+*\r
+* *DMA with Automatic Buffer Management:*\r
+* Configure DMA. This is required only once and automatically generates DMA\r
+* requests as data arrives\r
+*\r
+* \param epNumber: Contains the data endpoint number.\r
+* Valid values are between 1 and 8.\r
+* \param pData: A pointer to a data array into which the data for the endpoint\r
+* space is copied. It shall be ensured that this pointer address is\r
+* even to ensure the 16-bit transfer is aligned to even address. Else,\r
+* a hard fault condition can occur.\r
+* \param length: The number of bytes to transfer from the USB Out endpoint and\r
+* loads it into data array. Valid values are between 0 and 1023. The\r
+* function moves fewer than the requested number of bytes if the host\r
+* sends fewer bytes than requested.\r
+*\r
+* \return\r
+* Number of bytes received, 0 for an invalid endpoint.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+*******************************************************************************/\r
+uint16 USBFS_ReadOutEP16(uint8 epNumber, uint8 pData[], uint16 length)\r
+{\r
+ uint32 adjLength;\r
+\r
+ /* Check array alignment on half-word boundary */\r
+ CYASSERT(0u == (((uint32) pData) & 0x01u));\r
+\r
+ if ((pData != NULL) && (epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
+ {\r
+ #if (!USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Adjust requested length to available data. */\r
+ length = (length > USBFS_GetEPCount(epNumber)) ? USBFS_GetEPCount(epNumber) : length;\r
+ #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+\r
+ /* Adjust requested length: 2 bytes are handled at one data register access. */\r
+ adjLength = length + ((uint32)length & 1u);\r
+\r
+ #if (USBFS_EP_MANAGEMENT_MANUAL)\r
+ {\r
+ /* Convert uint8 array to uint16. */\r
+ uint16 *dataBuf = (uint16 *) pData;\r
+\r
+ /* Copy data using 16-bits arbiter data register. */\r
+ uint16 i;\r
+ for (i = 0u; i < (adjLength >> 1u); ++i)\r
+ {\r
+ dataBuf[i] = (uint16) USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16;\r
+ }\r
+ }\r
+\r
+ /* Arm OUT endpoint after data has been read from endpoint buffer. */\r
+ USBFS_EnableOutEP(epNumber);\r
+ #else\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ {\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+\r
+ /* Disable DMA channel: start configuration. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Configure source and destination. */\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16);\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData);\r
+\r
+ /* Configure DMA descriptor. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | (uint16)((adjLength >> 1u) - 1u) |\r
+ CYDMA_HALFWORD | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE);\r
+\r
+ /* Validate descriptor to execute on following DMA request. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+\r
+ /* Generate DMA request. */\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint32) USBFS_ARB_EPX_CFG_DMA_REQ;\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint32) ~USBFS_ARB_EPX_CFG_DMA_REQ;\r
+\r
+ /* OUT endpoint has to be armed again by user when DMA transfers have been completed.\r
+ * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer.\r
+ */\r
+ }\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ {\r
+ uint32 lengthDescr0, lengthDescr1;\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+\r
+ /* Get number of full bursts. */\r
+ USBFS_DmaEpBurstCnt[epNumber] = (uint8) (adjLength / USBFS_DMA_BYTES_PER_BURST);\r
+\r
+ /* Get number of elements in last burst. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (adjLength % USBFS_DMA_BYTES_PER_BURST);\r
+\r
+ /* Get total number of bursts. */\r
+ USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u;\r
+\r
+ /* Adjust number of data elements transferred in last burst. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ?\r
+ ((USBFS_DmaEpLastBurstEl[epNumber] >> 1u) - 1u) :\r
+ (USBFS_DMA_HALFWORDS_PER_BURST - 1u);\r
+\r
+ /* Get number of data elements to transfer for descriptor 0 and 1. */\r
+ lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u);\r
+ lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u);\r
+\r
+ /* Mark last descriptor to be executed. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ?\r
+ USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK;\r
+\r
+ /* Mark if revert number of data elements in descriptor after transfer completion. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] |= (USBFS_DmaEpBurstCnt[epNumber] > 2u) ? USBFS_DMA_DESCR_REVERT : 0u;\r
+\r
+ /* Mark that 16-bits access to data register is performed. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] |= USBFS_DMA_DESCR_16BITS;\r
\r
+ /* Store address of buffer and burst counter for endpoint. */\r
+ USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData;\r
+ USBFS_DmaEpBurstCntBackup[epNumber] = USBFS_DmaEpBurstCnt[epNumber];\r
+\r
+ /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */\r
+ USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]);\r
+\r
+ /* Disable DMA channel: start configuration. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Set destination address. */\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16);\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16);\r
+\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) pData));\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) pData + USBFS_DMA_BYTES_PER_BURST));\r
+\r
+ /* Configure DMA descriptor 0. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | lengthDescr0 |\r
+ CYDMA_HALFWORD | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN);\r
+\r
+ /* Configure DMA descriptor 1. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG | lengthDescr1 |\r
+ CYDMA_HALFWORD | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN);\r
+\r
+ /* Enable interrupt from DMA channel. */\r
+ USBFS_CyDmaSetInterruptMask(channelNum);\r
+\r
+ /* Validate DMA descriptor 0 and 1. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
+ \r
+ if (USBFS_DmaEpBurstCntBackup[epNumber] > 1u)\r
+ {\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1);\r
+ }\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+\r
+ /* OUT endpoint has to be armed again by user when DMA transfers have been completed.\r
+ * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer.\r
+ */\r
+ }\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */\r
}\r
else\r
{\r
length = 0u;\r
}\r
\r
- return(length);\r
+ return (length);\r
}\r
+#endif /* (USBFS_16BITS_EP_ACCESS_ENABLE) */\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_EnableOutEP\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* This function enables an OUT endpoint. It should not be\r
-* called for an IN endpoint.\r
+* This function enables the specified endpoint for OUT transfers. Do not call\r
+* this function for IN endpoints.\r
*\r
-* Parameters:\r
-* epNumber: Endpoint Number\r
-* Valid values are between 1 and 8.\r
+* \param epNumber: Contains the data endpoint number. Valid values are between\r
+* 1 and 8.\r
*\r
-* Return:\r
-* None.\r
+* \globalvars\r
*\r
-* Global variables:\r
-* USBFS_EP[epNumber].apiEpState - set to NO_EVENT_PENDING\r
+* \ref USBFS_EP[epNumber].apiEpState - set to NO_EVENT_PENDING\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_EnableOutEP(uint8 epNumber) \r
{\r
- uint8 ri;\r
-\r
- if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
+ if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
- ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
- /* Write the Mode register */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);\r
+\r
+ /* Enable OUT endpoint to be written by Host. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode;\r
+ \r
}\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_DisableOutEP\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* This function disables an OUT endpoint. It should not be\r
-* called for an IN endpoint.\r
+* This function disables the specified USBFS OUT endpoint. Do not call this\r
+* function for IN endpoints.\r
*\r
-* Parameters:\r
-* epNumber: Endpoint Number\r
+* \param epNumber: Contains the data endpoint number.\r
* Valid values are between 1 and 8.\r
*\r
-* Return:\r
-* None.\r
-*\r
*******************************************************************************/\r
void USBFS_DisableOutEP(uint8 epNumber) \r
{\r
- uint8 ri ;\r
-\r
- if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
+ if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
- ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
- /* Write the Mode register */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT);\r
+ /* Set NAK response for OUT endpoint. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_MODE_NAK_OUT;\r
}\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Force\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Forces the bus state\r
+* This function forces a USB J, K, or SE0 state on the D+/D– lines. It provides\r
+* the necessary mechanism for a USB device application to perform a USB Remote\r
+* Wakeup. For more information, see the USB 2.0 Specification for details on\r
+* Suspend and Resume.\r
*\r
-* Parameters:\r
-* bState\r
-* USBFS_FORCE_J\r
-* USBFS_FORCE_K\r
-* USBFS_FORCE_SE0\r
-* USBFS_FORCE_NONE\r
+* \param state A byte indicating which of the four bus states to enable.\r
+* Symbolic names and their associated values are listed here:\r
+* State |Description\r
+* ---------------------------|----------------------------------------------\r
+* USBFS_FORCE_J | Force a J State onto the D+/D– lines\r
+* USBFS_FORCE_K | Force a K State onto the D+/D– lines\r
+* USBFS_FORCE_SE0 | Force a Single Ended 0 onto the D+/D– lines\r
+* USBFS_FORCE_NONE| Return bus to SIE control\r
*\r
-* Return:\r
-* None.\r
*\r
*******************************************************************************/\r
void USBFS_Force(uint8 bState) \r
{\r
- CY_SET_REG8(USBFS_USBIO_CR0_PTR, bState);\r
+ /* This registers is used only for manual control of SIE (no masking is\r
+ * needed before write into it).\r
+ */\r
+ USBFS_USBIO_CR0_REG = bState;\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_GetEPAckState\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Returns the ACK of the CR0 Register (ACKD)\r
+* This function determines whether an ACK transaction occurred on this endpoint\r
+* by reading the ACK bit in the control register of the endpoint. It does not\r
+* clear the ACK bit.\r
*\r
-* Parameters:\r
-* epNumber: Endpoint Number\r
+* \param epNumber Contains the data endpoint number.\r
* Valid values are between 1 and 8.\r
*\r
-* Returns\r
-* 0 if nothing has been ACKD, non-=zero something has been ACKD\r
+* \return\r
+* If an ACKed transaction occurred, this function returns a non-zero value.\r
+* Otherwise, it returns zero.\r
*\r
*******************************************************************************/\r
uint8 USBFS_GetEPAckState(uint8 epNumber) \r
{\r
- uint8 ri;\r
uint8 cr = 0u;\r
\r
- if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
+ if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
- ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
- cr = CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri)) & USBFS_MODE_ACKD;\r
+ cr = USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 & USBFS_MODE_ACKD;\r
}\r
\r
- return(cr);\r
+ return ((uint8) cr);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_SetPowerStatus\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Sets the device power status for reporting in the Get Device Status\r
-* request\r
+* This function sets the current power status. The device replies to USB\r
+* GET_STATUS requests based on this value. This allows the device to properly\r
+* report its status for USB Chapter 9 compliance. Devices can change their\r
+* power source from self powered to bus powered at any time and report their\r
+* current power source as part of the device status. You should call this\r
+* function any time your device changes from self powered to bus powered or\r
+* vice versa, and set the status appropriately.\r
*\r
-* Parameters:\r
-* powerStatus: USBFS_DEVICE_STATUS_BUS_POWERED(0) - Bus Powered,\r
-* USBFS_DEVICE_STATUS_SELF_POWERED(1) - Self Powered\r
+* \param powerStatus: Contains the desired power status, one for self powered\r
+* or zero for bus powered. Symbolic names and their associated values are\r
+* given here:\r
+* Power Status |Description\r
+* --------------------------------------------|---------------------------\r
+* USBFS_DEVICE_STATUS_BUS_POWERED | Set the device to bus powered\r
+* USBFS_DEVICE_STATUS_SELF_POWERED | Set the device to self powered\r
*\r
-* Return:\r
-* None.\r
+* \globalvars\r
*\r
-* Global variables:\r
-* USBFS_deviceStatus - set power status\r
+* \ref USBFS_deviceStatus - set power status\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
{\r
if (powerStatus != USBFS_DEVICE_STATUS_BUS_POWERED)\r
{\r
- USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED;\r
+ USBFS_deviceStatus |= (uint8) USBFS_DEVICE_STATUS_SELF_POWERED;\r
}\r
else\r
{\r
- USBFS_deviceStatus &= ((uint8)(~USBFS_DEVICE_STATUS_SELF_POWERED));\r
+ USBFS_deviceStatus &= (uint8) ~USBFS_DEVICE_STATUS_SELF_POWERED;\r
}\r
}\r
\r
\r
-#if (USBFS_MON_VBUS == 1u)\r
-\r
- /*******************************************************************************\r
+#if (USBFS_VBUS_MONITORING_ENABLE)\r
+ /***************************************************************************\r
* Function Name: USBFS_VBusPresent\r
- ********************************************************************************\r
+ ************************************************************************//**\r
*\r
- * Summary:\r
- * Determines VBUS presence for Self Powered Devices.\r
+ * Determines VBUS presence for self-powered devices. This function is\r
+ * available when the VBUS Monitoring option is enabled in the Advanced tab.\r
*\r
- * Parameters:\r
- * None.\r
+ * \return\r
+ * The return value can be the following:\r
+ * Return Value | Description\r
+ * -------------|-----------------\r
+ * 1 | VBUS is present\r
+ * 0 | VBUS is absent\r
*\r
- * Return:\r
- * 1 if VBUS is present, otherwise 0.\r
*\r
- *******************************************************************************/\r
+ ***************************************************************************/\r
uint8 USBFS_VBusPresent(void) \r
{\r
- return((0u != (CY_GET_REG8(USBFS_VBUS_PS_PTR) & USBFS_VBUS_MASK)) ? 1u : 0u);\r
+ return ((0u != (USBFS_VBUS_STATUS_REG & USBFS_VBUS_VALID)) ? (uint8) 1u : (uint8) 0u);\r
}\r
-\r
-#endif /* USBFS_MON_VBUS */\r
+#endif /* (USBFS_VBUS_MONITORING_ENABLE) */\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_RWUEnabled\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Returns TRUE if Remote Wake Up is enabled, otherwise FALSE\r
+* This function returns the current remote wakeup status.\r
+* If the device supports remote wakeup, the application should use this\r
+* function to determine if remote wakeup was enabled by the host. When the\r
+* device is suspended and it determines the conditions to initiate a remote\r
+* wakeup are met, the application should use the USBFS_Force() function to\r
+* force the appropriate J and K states onto the USB bus, signaling a remote\r
+* wakeup.\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
-* TRUE - Remote Wake Up Enabled\r
-* FALSE - Remote Wake Up Disabled\r
+* \return\r
+* Returns non-zero value if remote wakeup is enabled and zero otherwise.\r
*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_deviceStatus - checked to determine remote status\r
*\r
*******************************************************************************/\r
uint8 USBFS_RWUEnabled(void) \r
{\r
uint8 result = USBFS_FALSE;\r
- if((USBFS_deviceStatus & USBFS_DEVICE_STATUS_REMOTE_WAKEUP) != 0u)\r
+\r
+ if (0u != (USBFS_deviceStatus & USBFS_DEVICE_STATUS_REMOTE_WAKEUP))\r
{\r
result = USBFS_TRUE;\r
}\r
\r
- return(result);\r
+ return (result);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_GetDeviceAddress\r
+****************************************************************************//**\r
+*\r
+* This function returns the currently assigned address for the USB device.\r
+*\r
+* \return\r
+* Returns the currently assigned address.\r
+* Returns 0 if the device has not yet been assigned an address.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_GetDeviceAddress(void) \r
+{\r
+ return (uint8)(USBFS_CR0_REG & USBFS_CR0_DEVICE_ADDRESS_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_EnableSofInt\r
+****************************************************************************//**\r
+*\r
+* This function enables interrupt generation when a Start-of-Frame (SOF)\r
+* packet is received from the host.\r
+*\r
+*******************************************************************************/\r
+void USBFS_EnableSofInt(void) \r
+{\r
+#if (CY_PSOC4)\r
+ /* Enable SOF interrupt interrupt source. */\r
+ USBFS_INTR_SIE_MASK_REG |= (uint32) USBFS_INTR_SIE_SOF_INTR;\r
+#else\r
+ /* Enable SOF interrupt if it is present. */\r
+ #if (USBFS_SOF_ISR_ACTIVE)\r
+ CyIntEnable(USBFS_SOF_VECT_NUM);\r
+ #endif /* (USBFS_SOF_ISR_ACTIVE) */\r
+#endif /* (CY_PSOC4) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_DisableSofInt\r
+****************************************************************************//**\r
+*\r
+* This function disables interrupt generation when a Start-of-Frame (SOF)\r
+* packet is received from the host.\r
+*\r
+*******************************************************************************/\r
+void USBFS_DisableSofInt(void) \r
+{\r
+#if (CY_PSOC4)\r
+ /* Disable SOF interrupt interrupt source. */\r
+ USBFS_INTR_SIE_MASK_REG &= (uint32) ~USBFS_INTR_SIE_SOF_INTR;\r
+#else\r
+ /* Disable SOF interrupt if it is present. */\r
+ #if (USBFS_SOF_ISR_ACTIVE)\r
+ CyIntDisable(USBFS_SOF_VECT_NUM);\r
+ #endif /* (USBFS_SOF_ISR_ACTIVE) */\r
+#endif /* (CY_PSOC4) */\r
}\r
\r
\r
+#if (USBFS_BATT_CHARG_DET_ENABLE)\r
+ /***************************************************************************\r
+ * Function Name: USBFS_DetectPortType\r
+ ************************************************************************//**\r
+ *\r
+ * This function implements the USB Battery Charger Detection (BCD)\r
+ * algorithm to determine the type of USB host downstream port. This API\r
+ * is available only for PSoC 4 devices, and should be called when the VBUS\r
+ * voltage transition (OFF to ON) is detected on the bus. If the USB device\r
+ * functionality is enabled, this API first calls USBFS_Stop() API\r
+ * internally to disable the USB device functionality, and then proceeds to\r
+ * implement the BCD algorithm to detect the USB host port type.\r
+ * The USBFS_Start() API should be called after this API if the USB\r
+ * communication needs to be initiated with the host.\r
+ * *Note* This API is generated only if the “Enable Battery Charging \r
+ * Detection” option is enabled in the “Advanced” tab of the component GUI.\r
+ * *Note* API implements the steps 2-4 of the BCD algorithm which are \r
+ * - Data Contact Detect\r
+ * - Primary Detection \r
+ * - Secondary Detection \r
+ * \r
+ * The first step of BCD algorithm, namely, VBUS detection shall be handled \r
+ * at the application firmware level.\r
+ *\r
+ * \return\r
+ * The return value can be the following:\r
+ * Return Value |Description\r
+ * ----------------------------------|-------------------------------------\r
+ * USBFS_BCD_PORT_SDP | Standard downstream port detected\r
+ * USBFS_BCD_PORT_CDP | Charging downstream port detected\r
+ * USBFS_BCD_PORT_DCP | Dedicated charging port detected\r
+ * USBFS_BCD_PORT_UNKNOWN | Unable to detect charging port type (proprietary charger type)\r
+ * USBFS_BCD_PORT_ERR | Error condition in detection process\r
+ *\r
+ *\r
+ * \sideeffects\r
+ *\r
+ * USB device functionality is disabled by this API if not already disabled.\r
+ *\r
+ ***************************************************************************/\r
+ uint8 USBFS_Bcd_DetectPortType(void)\r
+ {\r
+ uint32 bkPwrCtrl;\r
+ uint32 cr1RegVal;\r
+ uint32 secondaryDetection = 0u;\r
+ uint8 result = USBFS_BCD_PORT_UNKNOWN;\r
+\r
+ /*Check USB Started and Stop it*/\r
+ if(0u != USBFS_initVar)\r
+ {\r
+ USBFS_Stop();\r
+ }\r
+ /*Initialize USBFS IP for Charger detection*/\r
+\r
+ /*Enable clock to USB IP. */\r
+ USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_CSR_CLK_EN;\r
+\r
+ /* Enable USBIO control on drive mode of D+ and D- pins. */\r
+ USBFS_USBIO_CR1_REG &= ~ (uint32) USBFS_USBIO_CR1_IOMODE;\r
+\r
+ /* Select VBUS detection source and clear PHY isolate. The application\r
+ * level must ensure that VBUS is valid. There is no need to wait 2us\r
+ * before VBUS is valid.\r
+ */\r
+ bkPwrCtrl = USBFS_POWER_CTRL_REG;\r
+ USBFS_POWER_CTRL_REG = USBFS_DEFAULT_POWER_CTRL_VBUS\\r
+ & (~USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN)\\r
+ & (~USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN);\r
+\r
+\r
+ /* Enable PHY detector and single-ended and differential receivers.\r
+ * Enable charger detection. */\r
+ USBFS_POWER_CTRL_REG |= USBFS_DEFAULT_POWER_CTRL_PHY\\r
+ | USBFS_POWER_CTRL_ENABLE_CHGDET;\r
+\r
+ /* Suspend clear sequence. */\r
+ USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND;\r
+ CyDelayUs(USBFS_WAIT_SUSPEND_DEL_DISABLE);\r
+ USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND_DEL;\r
+\r
+ /* Data connection detection\r
+ * Realization with delay as Hard IP does not support DCD 300 ms.\r
+ */\r
+ #if defined (USBFS_NO_DCD)\r
+ CyDelay(USBFS_BCD_TIMEOUT);\r
+ #else\r
+ /* DCD implementation:*/\r
+\r
+ {\r
+ uint16 timeout = USBFS_BCD_TIMEOUT;\r
+ uint8 connectionApproved = 0u;\r
+ uint8 connected = 0u;\r
+\r
+ /* BCD spec 1.2: Turns on Idp_src and D- pull-down resistor */\r
+ USBFS_POWER_CTRL_REG |= USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN;\r
+ USBFS_CHGDET_CTRL_REG |= USBFS_CHGDET_CTRL_DCD_SRC_EN;\r
+\r
+ /* BCD spec 1.2: Waits for D+ to be low for a time of Tdcd_dbnc*/\r
+ while ((0u != timeout) && (0u == connectionApproved))\r
+ {\r
+ if (0u == (USBFS_USBIO_CR1_REG & USBFS_USBIO_CR1_DP0))\r
+ {\r
+ connected++;\r
+ }\r
+ else\r
+ {\r
+ connected = 0u;\r
+ }\r
+ connectionApproved = (USBFS_BCD_TDCD_DBNC < connected) ? 1u:0u;\r
+ CyDelay(1u);\r
+ timeout--;\r
+ }\r
+\r
+ /* BCD spec 1.2: Turns off Idp_src. */\r
+ USBFS_CHGDET_CTRL_REG &= ~USBFS_CHGDET_CTRL_DCD_SRC_EN;\r
+ }\r
+ #endif /*(USBFS_NO_DCD)*/\r
+\r
+ /* Primary detection: enable VDP_SRC on D+ and IDM_SINK on D-. */\r
+ USBFS_CHGDET_CTRL_REG = USBFS_CHGDET_CTRL_PRIMARY;\r
+ CyDelay(USBFS_BCD_PRIMARY_WAIT);\r
+ cr1RegVal = USBFS_USBIO_CR1_REG;\r
+\r
+ /* Check is it SDP or DCP/CDP, read comparator 2 output. */\r
+ if (0u == (USBFS_CHGDET_CTRL_REG & USBFS_CHGDET_CTRL_COMP_OUT))\r
+ {\r
+ /* Check status of D- line. */\r
+ if (0u == (cr1RegVal & USBFS_USBIO_CR1_DM0))\r
+ {\r
+ result = USBFS_BCD_PORT_SDP;\r
+ }\r
+ else\r
+ {\r
+ /* ERROR: such combination is impossible. Abort charger\r
+ * detection.\r
+ */\r
+ result = USBFS_BCD_PORT_ERR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Need Secondary detection. Charging port: DCP or proprietary*/\r
+ secondaryDetection = 1u;\r
+ }\r
+\r
+ /* Secondary detection: Set CHGDET_CTRL register to enable VDM_SRC on D- and IDP_SINK on D+. */\r
+\r
+ if (0u != secondaryDetection)\r
+ {\r
+ USBFS_CHGDET_CTRL_REG = USBFS_CHGDET_CTRL_DEFAULT \\r
+ | USBFS_CHGDET_CTRL_SECONDARY;\r
+ CyDelay(USBFS_BCD_SECONDARY_WAIT);\r
+ cr1RegVal = USBFS_USBIO_CR1_REG;\r
+\r
+ /* Check is it SDP or DCP/CDP, read comparator 1 output. */\r
+ if (0u == (USBFS_CHGDET_CTRL_REG & USBFS_CHGDET_CTRL_COMP_OUT))\r
+ {\r
+ /* Check status of D+ line. */\r
+ if (0u == (cr1RegVal & USBFS_USBIO_CR1_DP0))\r
+ {\r
+ result = USBFS_BCD_PORT_CDP;\r
+ }\r
+ else\r
+ {\r
+ /* ERROR: such combination is impossible. Abort charger\r
+ * detection.\r
+ */\r
+ result = USBFS_BCD_PORT_ERR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Check status of D+ line. */\r
+ if (0u == (cr1RegVal & USBFS_USBIO_CR1_DP0))\r
+ {\r
+ result = USBFS_BCD_PORT_DCP;\r
+ }\r
+ else\r
+ {\r
+ /* It is may be proprietary charger. Proprietary charge is\r
+ * not supported byHardware IP block.\r
+ */\r
+ result = USBFS_BCD_PORT_UNKNOWN;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Restore CHGDET_CTRL. */\r
+ USBFS_CHGDET_CTRL_REG = 0u;\r
+\r
+ /*Revert registers back*/\r
+ USBFS_POWER_CTRL_REG = bkPwrCtrl;\r
+ USBFS_USBIO_CR1_REG |= (uint32) USBFS_USBIO_CR1_IOMODE;\r
+ USBFS_USB_CLK_EN_REG = ~USBFS_USB_CLK_CSR_CLK_EN;\r
+\r
+ return (result);\r
+ }\r
+#endif /* (USBFS_BATT_CHARG_DET_ENABLE) */\r
+\r
+\r
+#if (USBFS_LPM_ACTIVE)\r
+ /***************************************************************************\r
+ * Function Name: USBFS_Lpm_GetBeslValue\r
+ ************************************************************************//**\r
+ *\r
+ * This function returns the Best Effort Service Latency (BESL) value\r
+ * sent by the host as part of the LPM token transaction.\r
+ *\r
+ * \return\r
+ * 4-bit BESL value received in the LPM token packet from the host\r
+ *\r
+ *\r
+ ***************************************************************************/\r
+ uint32 USBFS_Lpm_GetBeslValue(void)\r
+ {\r
+ return (uint32) (USBFS_LPM_STAT_REG & USBFS_LPM_STAT_LPM_BESL_MASK);\r
+ }\r
+\r
+\r
+ /***************************************************************************\r
+ * Function Name: USBFS_Lpm_RemoteWakeUpAllowed\r
+ ************************************************************************//**\r
+ *\r
+ * This function returns the remote wakeup permission set for the device by\r
+ * the host as part of the LPM token transaction.\r
+ *\r
+ * \return\r
+ * 0 - remote wakeup not allowed, 1 - remote wakeup allowed\r
+ *\r
+ *\r
+ ***************************************************************************/\r
+ uint32 USBFS_Lpm_RemoteWakeUpAllowed(void)\r
+ {\r
+ return (uint32) (USBFS_LPM_STAT_REG & USBFS_LPM_STAT_LPM_REMOTE_WAKE);\r
+ }\r
+\r
+\r
+ /***************************************************************************\r
+ * Function Name: USBFS_Lpm_SetResponse\r
+ ************************************************************************//**\r
+ *\r
+ * This function configures the response in the handshake packet the device\r
+ * has to send when an LPM token packet is received.\r
+ *\r
+ * \param response\r
+ * type of response to return for an LPM token packet\r
+ * Allowed response values:\r
+ * - USBFS_LPM_REQ_ACK - next LPM request will be\r
+ * responded with ACK\r
+ * - USBFS_LPM_REQ_NACK - next LPM request will be\r
+ * responded with NACK\r
+ * - USBFS_LPM_REQ_NYET - next LPM request will be\r
+ * responded with NYET\r
+ *\r
+ ***************************************************************************/\r
+ void USBFS_Lpm_SetResponse(uint32 response)\r
+ {\r
+ uint32 lpmCtrl = USBFS_LPM_CTRL_REG & (uint32) ~USBFS_LPM_CTRL_ACK_NYET_MASK;\r
+\r
+ USBFS_LPM_CTRL_REG = lpmCtrl | ((uint32) response & USBFS_LPM_CTRL_ACK_NYET_MASK);\r
+ }\r
+\r
+\r
+ /***************************************************************************\r
+ * Function Name: USBFS_Lpm_GetResponse\r
+ ************************************************************************//**\r
+ *\r
+ * This function returns the currently configured response value that the\r
+ * device will send as part of the handshake packet when an LPM token\r
+ * packet is received.\r
+ *\r
+ * \return\r
+ * type of handshake response that will be returned by the device\r
+ * for an LPM token packet\r
+ * Possible response values:\r
+ * - USBFS_LPM_REQ_ACK - next LPM request will be responded\r
+ * with ACK\r
+ * - USBFS_LPM_REQ_NACK - next LPM request will be responded\r
+ * with NACK\r
+ * - USBFS_LPM_REQ_NYET - next LPM request will be responded\r
+ * with NYET\r
+ *\r
+ ***************************************************************************/\r
+ uint32 USBFS_Lpm_GetResponse(void)\r
+ {\r
+\r
+ return ((uint32) USBFS_LPM_CTRL_REG & (uint32)USBFS_LPM_CTRL_ACK_NYET_MASK);\r
+ }\r
+\r
+\r
+#endif /* (USBFS_LPM_ACTIVE) */\r
+\r
+\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: USBFS.h\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS.h\r
+* \version 3.10\r
*\r
-* Description:\r
-* Header File for the USBFS component. Contains prototypes and constant values.\r
+* \brief\r
+* This file provides function prototypes and constants for the USBFS component. \r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#if !defined(CY_USBFS_USBFS_H)\r
#define CY_USBFS_USBFS_H\r
\r
-#include "cytypes.h"\r
#include "cydevice_trm.h"\r
#include "cyfitter.h"\r
+#include "cytypes.h"\r
#include "CyLib.h"\r
\r
+\r
/* User supplied definitions. */\r
/* `#START USER_DEFINITIONS` Place your declaration here */\r
\r
/* `#END` */\r
\r
-\r
-/***************************************\r
-* Conditional Compilation Parameters\r
-***************************************/\r
-\r
-/* Check to see if required defines such as CY_PSOC5LP are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5LP)\r
- #error Component USBFS_v2_80 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5LP) */\r
-\r
-\r
-/***************************************\r
-* Memory Type Definitions\r
-***************************************/\r
-\r
-/* Renamed Type Definitions for backward compatibility.\r
-* Should not be used in new designs.\r
-*/\r
-#define USBFS_CODE CYCODE\r
-#define USBFS_FAR CYFAR\r
-#if defined(__C51__) || defined(__CX51__)\r
- #define USBFS_DATA data\r
- #define USBFS_XDATA xdata\r
-#else\r
- #define USBFS_DATA\r
- #define USBFS_XDATA\r
-#endif /* __C51__ */\r
-#define USBFS_NULL NULL\r
-\r
-\r
/***************************************\r
* Enumerated Types and Parameters\r
***************************************/\r
\r
-#define USBFS__EP_MANUAL 0\r
-#define USBFS__EP_DMAMANUAL 1\r
-#define USBFS__EP_DMAAUTO 2\r
-\r
-#define USBFS__MA_STATIC 0\r
-#define USBFS__MA_DYNAMIC 1\r
+/* USB IP memory management options. */\r
+#define USBFS__EP_MANUAL (0u)\r
+#define USBFS__EP_DMAMANUAL (1u)\r
+#define USBFS__EP_DMAAUTO (2u)\r
\r
+/* USB IP memory allocation options. */\r
+#define USBFS__MA_STATIC (0u)\r
+#define USBFS__MA_DYNAMIC (1u)\r
\r
\r
/***************************************\r
* Initial Parameter Constants\r
***************************************/\r
\r
-#define USBFS_NUM_DEVICES (1u)\r
-#define USBFS_ENABLE_DESCRIPTOR_STRINGS \r
-#define USBFS_ENABLE_SN_STRING \r
-#define USBFS_ENABLE_STRINGS \r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE (65u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_IN_RPTS (1u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE (65u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_OUT_RPTS (1u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT (1u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE (65u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_IN_RPTS (1u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE (65u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_OUT_RPTS (1u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_COUNT (1u)\r
-#define USBFS_ENABLE_HID_CLASS \r
-#define USBFS_HID_RPT_1_SIZE_LSB (0x25u)\r
-#define USBFS_HID_RPT_1_SIZE_MSB (0x00u)\r
-#define USBFS_HID_RPT_2_SIZE_LSB (0x25u)\r
-#define USBFS_HID_RPT_2_SIZE_MSB (0x00u)\r
-#define USBFS_MAX_REPORTID_NUMBER (0u)\r
-\r
-#define USBFS_MON_VBUS (0u)\r
-#define USBFS_EXTERN_VBUS (0u)\r
-#define USBFS_EXTERN_VND (0u)\r
-#define USBFS_EXTERN_CLS (0u)\r
-#define USBFS_MAX_INTERFACES_NUMBER (2u)\r
-#define USBFS_EP0_ISR_REMOVE (0u)\r
-#define USBFS_EP1_ISR_REMOVE (0u)\r
-#define USBFS_EP2_ISR_REMOVE (0u)\r
-#define USBFS_EP3_ISR_REMOVE (0u)\r
-#define USBFS_EP4_ISR_REMOVE (0u)\r
-#define USBFS_EP5_ISR_REMOVE (1u)\r
-#define USBFS_EP6_ISR_REMOVE (1u)\r
-#define USBFS_EP7_ISR_REMOVE (1u)\r
-#define USBFS_EP8_ISR_REMOVE (1u)\r
-#define USBFS_EP_MM (0u)\r
-#define USBFS_EP_MA (0u)\r
-#define USBFS_EP_DMA_AUTO_OPT (0u)\r
-#define USBFS_DMA1_REMOVE (1u)\r
-#define USBFS_DMA2_REMOVE (1u)\r
-#define USBFS_DMA3_REMOVE (1u)\r
-#define USBFS_DMA4_REMOVE (1u)\r
-#define USBFS_DMA5_REMOVE (1u)\r
-#define USBFS_DMA6_REMOVE (1u)\r
-#define USBFS_DMA7_REMOVE (1u)\r
-#define USBFS_DMA8_REMOVE (1u)\r
-#define USBFS_SOF_ISR_REMOVE (0u)\r
-#define USBFS_ARB_ISR_REMOVE (0u)\r
-#define USBFS_DP_ISR_REMOVE (0u)\r
-#define USBFS_ENABLE_CDC_CLASS_API (1u)\r
-#define USBFS_ENABLE_MIDI_API (1u)\r
-#define USBFS_MIDI_EXT_MODE (0u)\r
+#define USBFS_NUM_DEVICES (1u)\r
+#define USBFS_ENABLE_MIDI_CLASS (0u)\r
+#define USBFS_ENABLE_MSC_CLASS (0u)\r
+#define USBFS_BOS_ENABLE (0u)\r
+#define USBFS_ENABLE_DESCRIPTOR_STRINGS \r
+#define USBFS_ENABLE_SN_STRING \r
+#define USBFS_ENABLE_STRINGS \r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE (65u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_IN_RPTS (1u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE (65u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_OUT_RPTS (1u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT (1u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE (65u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_IN_RPTS (1u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE (65u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_OUT_RPTS (1u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_COUNT (1u)\r
+#define USBFS_ENABLE_HID_CLASS \r
+#define USBFS_HID_RPT_1_SIZE_LSB (0x25u)\r
+#define USBFS_HID_RPT_1_SIZE_MSB (0x00u)\r
+#define USBFS_HID_RPT_2_SIZE_LSB (0x25u)\r
+#define USBFS_HID_RPT_2_SIZE_MSB (0x00u)\r
+#define USBFS_MAX_REPORTID_NUMBER (0u)\r
+\r
+#define USBFS_MON_VBUS (0u)\r
+#define USBFS_EXTERN_VBUS (0u)\r
+#define USBFS_POWER_PAD_VBUS (0u)\r
+#define USBFS_EXTERN_VND (0u)\r
+#define USBFS_EXTERN_CLS (0u)\r
+#define USBFS_MAX_INTERFACES_NUMBER (2u)\r
+#define USBFS_EP_MM (0u)\r
+#define USBFS_EP_MA (0u)\r
+#define USBFS_ENABLE_BATT_CHARG_DET (0u)\r
+#define USBFS_GEN_16BITS_EP_ACCESS (0u)\r
+\r
+/* Enable Class APIs: MIDI, CDC, MSC. */ \r
+#define USBFS_ENABLE_CDC_CLASS_API (0u != (1u))\r
+\r
+/* General parameters */\r
+#define USBFS_EP_ALLOC_STATIC (USBFS_EP_MA == USBFS__MA_STATIC)\r
+#define USBFS_EP_ALLOC_DYNAMIC (USBFS_EP_MA == USBFS__MA_DYNAMIC)\r
+#define USBFS_EP_MANAGEMENT_MANUAL (USBFS_EP_MM == USBFS__EP_MANUAL)\r
+#define USBFS_EP_MANAGEMENT_DMA (USBFS_EP_MM != USBFS__EP_MANUAL)\r
+#define USBFS_EP_MANAGEMENT_DMA_MANUAL (USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
+#define USBFS_EP_MANAGEMENT_DMA_AUTO (USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
+#define USBFS_BATT_CHARG_DET_ENABLE (CY_PSOC4 && (0u != USBFS_ENABLE_BATT_CHARG_DET))\r
+#define USBFS_16BITS_EP_ACCESS_ENABLE (CY_PSOC4 && (0u != USBFS_GEN_16BITS_EP_ACCESS))\r
+#define USBFS_VBUS_MONITORING_ENABLE (0u != USBFS_MON_VBUS)\r
+#define USBFS_VBUS_MONITORING_INTERNAL (0u == USBFS_EXTERN_VBUS)\r
+#define USBFS_VBUS_POWER_PAD_ENABLE (0u != USBFS_POWER_PAD_VBUS)\r
+\r
+/* Control endpoints availability */\r
+#define USBFS_SOF_ISR_REMOVE (0u)\r
+#define USBFS_BUS_RESET_ISR_REMOVE (0u)\r
+#define USBFS_EP0_ISR_REMOVE (0u)\r
+#define USBFS_ARB_ISR_REMOVE (0u)\r
+#define USBFS_DP_ISR_REMOVE (0u)\r
+#define USBFS_LPM_REMOVE (1u)\r
+#define USBFS_SOF_ISR_ACTIVE ((0u == USBFS_SOF_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_BUS_RESET_ISR_ACTIVE ((0u == USBFS_BUS_RESET_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_EP0_ISR_ACTIVE ((0u == USBFS_EP0_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_ARB_ISR_ACTIVE ((0u == USBFS_ARB_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_DP_ISR_ACTIVE ((0u == USBFS_DP_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_LPM_ACTIVE ((CY_PSOC4 && (0u == USBFS_LPM_REMOVE)) ? 1u: 0u)\r
+\r
+/* Data endpoints availability */\r
+#define USBFS_EP1_ISR_REMOVE (0u)\r
+#define USBFS_EP2_ISR_REMOVE (0u)\r
+#define USBFS_EP3_ISR_REMOVE (0u)\r
+#define USBFS_EP4_ISR_REMOVE (0u)\r
+#define USBFS_EP5_ISR_REMOVE (1u)\r
+#define USBFS_EP6_ISR_REMOVE (1u)\r
+#define USBFS_EP7_ISR_REMOVE (1u)\r
+#define USBFS_EP8_ISR_REMOVE (1u)\r
+#define USBFS_EP1_ISR_ACTIVE ((0u == USBFS_EP1_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_EP2_ISR_ACTIVE ((0u == USBFS_EP2_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_EP3_ISR_ACTIVE ((0u == USBFS_EP3_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_EP4_ISR_ACTIVE ((0u == USBFS_EP4_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_EP5_ISR_ACTIVE ((0u == USBFS_EP5_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_EP6_ISR_ACTIVE ((0u == USBFS_EP6_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_EP7_ISR_ACTIVE ((0u == USBFS_EP7_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_EP8_ISR_ACTIVE ((0u == USBFS_EP8_ISR_REMOVE) ? 1u: 0u)\r
+\r
+#define USBFS_EP_DMA_AUTO_OPT ((CY_PSOC4) ? (1u) : (0u))\r
+#define USBFS_DMA1_REMOVE (1u)\r
+#define USBFS_DMA2_REMOVE (1u)\r
+#define USBFS_DMA3_REMOVE (1u)\r
+#define USBFS_DMA4_REMOVE (1u)\r
+#define USBFS_DMA5_REMOVE (1u)\r
+#define USBFS_DMA6_REMOVE (1u)\r
+#define USBFS_DMA7_REMOVE (1u)\r
+#define USBFS_DMA8_REMOVE (1u)\r
+#define USBFS_DMA1_ACTIVE ((0u == USBFS_DMA1_REMOVE) ? 1u: 0u)\r
+#define USBFS_DMA2_ACTIVE ((0u == USBFS_DMA2_REMOVE) ? 1u: 0u)\r
+#define USBFS_DMA3_ACTIVE ((0u == USBFS_DMA3_REMOVE) ? 1u: 0u)\r
+#define USBFS_DMA4_ACTIVE ((0u == USBFS_DMA4_REMOVE) ? 1u: 0u)\r
+#define USBFS_DMA5_ACTIVE ((0u == USBFS_DMA5_REMOVE) ? 1u: 0u)\r
+#define USBFS_DMA6_ACTIVE ((0u == USBFS_DMA6_REMOVE) ? 1u: 0u)\r
+#define USBFS_DMA7_ACTIVE ((0u == USBFS_DMA7_REMOVE) ? 1u: 0u)\r
+#define USBFS_DMA8_ACTIVE ((0u == USBFS_DMA8_REMOVE) ? 1u: 0u)\r
\r
\r
/***************************************\r
-* Data Struct Definition\r
+* Data Structures Definition\r
***************************************/\r
\r
typedef struct\r
T_USBFS_XFER_STATUS_BLOCK *pStatusBlock;\r
} T_USBFS_TD;\r
\r
-\r
typedef struct\r
{\r
uint8 c;\r
{\r
uint8 enableState;\r
uint8 mode;\r
+#if (CY_PSOC4)\r
+ uint8 intrSeiMask;\r
+#endif /* (CY_PSOC4) */\r
} USBFS_BACKUP_STRUCT;\r
\r
+/* Number of endpoint 0 data registers. */\r
+#define USBFS_EP0_DR_MAPPED_REG_CNT (8u)\r
\r
-/* Renamed structure fields for backward compatibility.\r
-* Should not be used in new designs.\r
-*/\r
-#define wBuffOffset buffOffset\r
-#define wBufferSize bufferSize\r
-#define bStatus status\r
-#define wLength length\r
-#define wCount count\r
+/* Structure to access data registers for EP0. */\r
+typedef struct\r
+{\r
+ uint8 epData[USBFS_EP0_DR_MAPPED_REG_CNT];\r
+} USBFS_ep0_data_struct;\r
\r
-/* Renamed global variable for backward compatibility.\r
-* Should not be used in new designs.\r
-*/\r
-#define CurrentTD USBFS_currentTD\r
+/* Number of SIE endpoint registers group. */\r
+#define USBFS_SIE_EP_REG_SIZE (USBFS_USB__SIE_EP1_CR0 - \\r
+ USBFS_USB__SIE_EP1_CNT0)\r
+\r
+/* Size of gap between SIE endpoint registers groups. */\r
+#define USBFS_SIE_GAP_CNT (((USBFS_USB__SIE_EP2_CNT0 - \\r
+ (USBFS_USB__SIE_EP1_CNT0 + \\r
+ USBFS_SIE_EP_REG_SIZE)) / sizeof(reg8)) - 1u)\r
+\r
+/* Structure to access to SIE registers for endpoint. */\r
+typedef struct\r
+{\r
+ uint8 epCnt0;\r
+ uint8 epCnt1;\r
+ uint8 epCr0;\r
+ uint8 gap[USBFS_SIE_GAP_CNT];\r
+} USBFS_sie_ep_struct;\r
+\r
+/* Number of ARB endpoint registers group. */\r
+#define USBFS_ARB_EP_REG_SIZE (USBFS_USB__ARB_RW1_DR - \\r
+ USBFS_USB__ARB_EP1_CFG)\r
+\r
+/* Size of gap between ARB endpoint registers groups. */\r
+#define USBFS_ARB_GAP_CNT (((USBFS_USB__ARB_EP2_CFG - \\r
+ (USBFS_USB__ARB_EP1_CFG + \\r
+ USBFS_ARB_EP_REG_SIZE)) / sizeof(reg8)) - 1u)\r
+\r
+/* Structure to access to ARB registers for endpoint. */\r
+typedef struct\r
+{\r
+ uint8 epCfg;\r
+ uint8 epIntEn;\r
+ uint8 epSr;\r
+ uint8 reserved;\r
+ uint8 rwWa;\r
+ uint8 rwWaMsb;\r
+ uint8 rwRa;\r
+ uint8 rwRaMsb;\r
+ uint8 rwDr;\r
+ uint8 gap[USBFS_ARB_GAP_CNT];\r
+} USBFS_arb_ep_struct;\r
+\r
+#if (CY_PSOC4)\r
+ /* Number of ARB endpoint registers group (16-bits access). */\r
+ #define USBFS_ARB_EP_REG16_SIZE (USBFS_USB__ARB_RW1_DR16 - \\r
+ USBFS_USB__ARB_RW1_WA16)\r
+\r
+ /* Size of gap between ARB endpoint registers groups (16-bits access). */\r
+ #define USBFS_ARB_EP_REG16_GAP_CNT (((USBFS_USB__ARB_RW2_WA16 - \\r
+ (USBFS_USB__ARB_RW1_WA16 + \\r
+ USBFS_ARB_EP_REG16_SIZE)) / sizeof(reg8)) - 1u)\r
+\r
+ /* Structure to access to ARB registers for endpoint (16-bits access). */\r
+ typedef struct\r
+ {\r
+ uint8 rwWa16;\r
+ uint8 reserved0;\r
+ uint8 rwRa16;\r
+ uint8 reserved1;\r
+ uint8 rwDr16;\r
+ uint8 gap[USBFS_ARB_EP_REG16_GAP_CNT];\r
+ } USBFS_arb_ep_reg16_struct;\r
+#endif /* (CY_PSOC4) */\r
+\r
+/* Number of endpoint (takes to account that endpoints numbers are 1-8). */\r
+#define USBFS_NUMBER_EP (9u)\r
+\r
+/* Consoled SIE register groups for endpoints 1-8. */\r
+typedef struct\r
+{\r
+ USBFS_sie_ep_struct sieEp[USBFS_NUMBER_EP];\r
+} USBFS_sie_eps_struct;\r
+\r
+/* Consolidate ARB register groups for endpoints 1-8.*/\r
+typedef struct\r
+{\r
+ USBFS_arb_ep_struct arbEp[USBFS_NUMBER_EP];\r
+} USBFS_arb_eps_struct;\r
+\r
+#if (CY_PSOC4)\r
+ /* Consolidate ARB register groups for endpoints 1-8 (16-bits access). */\r
+ typedef struct\r
+ {\r
+ USBFS_arb_ep_reg16_struct arbEp[USBFS_NUMBER_EP];\r
+ } USBFS_arb_eps_reg16_struct;\r
+#endif /* (CY_PSOC4) */\r
\r
\r
/***************************************\r
* Function Prototypes\r
***************************************/\r
-\r
-void USBFS_Start(uint8 device, uint8 mode) ;\r
-void USBFS_Init(void) ;\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
void USBFS_InitComponent(uint8 device, uint8 mode) ;\r
-void USBFS_Stop(void) ;\r
-uint8 USBFS_CheckActivity(void) ;\r
-uint8 USBFS_GetConfiguration(void) ;\r
-uint8 USBFS_IsConfigurationChanged(void) ;\r
-uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber)\r
- ;\r
-uint8 USBFS_GetEPState(uint8 epNumber) ;\r
-uint16 USBFS_GetEPCount(uint8 epNumber) ;\r
+void USBFS_Start(uint8 device, uint8 mode) ;\r
+void USBFS_Init(void) ;\r
+void USBFS_Stop(void) ;\r
+uint8 USBFS_GetConfiguration(void) ;\r
+uint8 USBFS_IsConfigurationChanged(void) ;\r
+uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) ;\r
+uint8 USBFS_GetEPState(uint8 epNumber) ;\r
+uint16 USBFS_GetEPCount(uint8 epNumber) ;\r
void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)\r
- ;\r
+ ;\r
uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)\r
- ;\r
-void USBFS_EnableOutEP(uint8 epNumber) ;\r
-void USBFS_DisableOutEP(uint8 epNumber) ;\r
-void USBFS_Force(uint8 bState) ;\r
-uint8 USBFS_GetEPAckState(uint8 epNumber) ;\r
-void USBFS_SetPowerStatus(uint8 powerStatus) ;\r
-uint8 USBFS_RWUEnabled(void) ;\r
-void USBFS_TerminateEP(uint8 ep) ;\r
-\r
-void USBFS_Suspend(void) ;\r
-void USBFS_Resume(void) ;\r
+ ;\r
+void USBFS_EnableOutEP(uint8 epNumber) ;\r
+void USBFS_DisableOutEP(uint8 epNumber) ;\r
+void USBFS_Force(uint8 bState) ;\r
+uint8 USBFS_GetEPAckState(uint8 epNumber) ;\r
+void USBFS_SetPowerStatus(uint8 powerStatus) ;\r
+void USBFS_TerminateEP(uint8 epNumber) ;\r
+\r
+uint8 USBFS_GetDeviceAddress(void) ;\r
+\r
+void USBFS_EnableSofInt(void) ;\r
+void USBFS_DisableSofInt(void) ;\r
+\r
\r
#if defined(USBFS_ENABLE_FWSN_STRING)\r
void USBFS_SerialNumString(uint8 snString[]) ;\r
#endif /* USBFS_ENABLE_FWSN_STRING */\r
-#if (USBFS_MON_VBUS == 1u)\r
+\r
+#if (USBFS_VBUS_MONITORING_ENABLE)\r
uint8 USBFS_VBusPresent(void) ;\r
-#endif /* USBFS_MON_VBUS */\r
+#endif /* (USBFS_VBUS_MONITORING_ENABLE) */\r
+\r
+#if (USBFS_16BITS_EP_ACCESS_ENABLE)\r
+ /* PSoC4 specific functions for 16-bit data register access. */\r
+ void USBFS_LoadInEP16 (uint8 epNumber, const uint8 pData[], uint16 length);\r
+ uint16 USBFS_ReadOutEP16(uint8 epNumber, uint8 pData[], uint16 length);\r
+#endif /* (USBFS_16BITS_EP_ACCESS_ENABLE) */\r
+\r
+#if (USBFS_BATT_CHARG_DET_ENABLE)\r
+ uint8 USBFS_Bcd_DetectPortType(void);\r
+#endif /* (USBFS_BATT_CHARG_DET_ENABLE) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+ void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData) ; \r
+ void USBFS_Stop_DMA(uint8 epNumber) ;\r
+/** @} general */ \r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+/**\r
+* \addtogroup group_power\r
+* @{\r
+*/\r
+uint8 USBFS_CheckActivity(void) ;\r
+void USBFS_Suspend(void) ;\r
+void USBFS_Resume(void) ;\r
+uint8 USBFS_RWUEnabled(void) ;\r
+\r
+#if (USBFS_LPM_ACTIVE)\r
+ uint32 USBFS_Lpm_GetBeslValue(void);\r
+ uint32 USBFS_Lpm_RemoteWakeUpAllowed(void);\r
+ void USBFS_Lpm_SetResponse(uint32 response);\r
+ uint32 USBFS_Lpm_GetResponse(void);\r
+#endif /* (USBFS_LPM_ACTIVE) */\r
+\r
+/** @} power */\r
+\r
\r
#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \\r
(CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))\r
-\r
- void USBFS_CyBtldrCommStart(void) ;\r
- void USBFS_CyBtldrCommStop(void) ;\r
- void USBFS_CyBtldrCommReset(void) ;\r
+/**\r
+* \addtogroup group_bootloader\r
+* @{\r
+*/\r
+ void USBFS_CyBtldrCommStart(void) ;\r
+ void USBFS_CyBtldrCommStop(void) ;\r
+ void USBFS_CyBtldrCommReset(void) ;\r
cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
;\r
cystatus USBFS_CyBtldrCommRead (uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
;\r
+/** @} bootloader */\r
\r
- #define USBFS_BTLDR_OUT_EP (0x01u)\r
- #define USBFS_BTLDR_IN_EP (0x02u)\r
+ #define USBFS_BTLDR_OUT_EP (0x01u)\r
+ #define USBFS_BTLDR_IN_EP (0x02u)\r
\r
- #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* EP 1 OUT */\r
- #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* EP 2 IN */\r
+ #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* Endpoint 1 (OUT) buffer size. */\r
+ #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* Endpoint 2 (IN) buffer size. */\r
#define USBFS_BTLDR_MAX_PACKET_SIZE USBFS_BTLDR_SIZEOF_WRITE_BUFFER\r
\r
#define USBFS_BTLDR_WAIT_1_MS (1u) /* Time Out quantity equal 1mS */\r
\r
- /* These defines active if used USBFS interface as an\r
- * IO Component for bootloading. When Custom_Interface selected\r
- * in Bootloder configuration as the IO Component, user must\r
- * provide these functions.\r
- */\r
+ /* Map-specific USB bootloader communication functions to common bootloader functions */\r
#if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS)\r
#define CyBtldrCommStart USBFS_CyBtldrCommStart\r
#define CyBtldrCommStop USBFS_CyBtldrCommStop\r
#define CyBtldrCommReset USBFS_CyBtldrCommReset\r
#define CyBtldrCommWrite USBFS_CyBtldrCommWrite\r
#define CyBtldrCommRead USBFS_CyBtldrCommRead\r
- #endif /*End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */\r
-\r
-#endif /* CYDEV_BOOTLOADER_IO_COMP */\r
-\r
-#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)\r
- ;\r
- void USBFS_Stop_DMA(uint8 epNumber) ;\r
-#endif /* USBFS_EP_MM != USBFS__EP_MANUAL) */\r
-\r
-#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)\r
- void USBFS_MIDI_EP_Init(void) ;\r
-\r
- #if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
- void USBFS_MIDI_IN_Service(void) ;\r
- uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable)\r
- ;\r
- #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */\r
-\r
- #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
- void USBFS_MIDI_OUT_EP_Service(void) ;\r
- #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */\r
-\r
-#endif /* USBFS_ENABLE_MIDI_API != 0u */\r
-\r
-/* Renamed Functions for backward compatibility.\r
-* Should not be used in new designs.\r
-*/\r
-\r
-#define USBFS_bCheckActivity USBFS_CheckActivity\r
-#define USBFS_bGetConfiguration USBFS_GetConfiguration\r
-#define USBFS_bGetInterfaceSetting USBFS_GetInterfaceSetting\r
-#define USBFS_bGetEPState USBFS_GetEPState\r
-#define USBFS_wGetEPCount USBFS_GetEPCount\r
-#define USBFS_bGetEPAckState USBFS_GetEPAckState\r
-#define USBFS_bRWUEnabled USBFS_RWUEnabled\r
-#define USBFS_bVBusPresent USBFS_VBusPresent\r
-\r
-#define USBFS_bConfiguration USBFS_configuration\r
-#define USBFS_bInterfaceSetting USBFS_interfaceSetting\r
-#define USBFS_bDeviceAddress USBFS_deviceAddress\r
-#define USBFS_bDeviceStatus USBFS_deviceStatus\r
-#define USBFS_bDevice USBFS_device\r
-#define USBFS_bTransferState USBFS_transferState\r
-#define USBFS_bLastPacketSize USBFS_lastPacketSize\r
-\r
-#define USBFS_LoadEP USBFS_LoadInEP\r
-#define USBFS_LoadInISOCEP USBFS_LoadInEP\r
-#define USBFS_EnableOutISOCEP USBFS_EnableOutEP\r
-\r
-#define USBFS_SetVector CyIntSetVector\r
-#define USBFS_SetPriority CyIntSetPriority\r
-#define USBFS_EnableInt CyIntEnable\r
+ #endif /* (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) */\r
+#endif /* CYDEV_BOOTLOADER_IO_COMP */\r
\r
\r
/***************************************\r
\r
#define USBFS_3V_OPERATION (0x00u)\r
#define USBFS_5V_OPERATION (0x01u)\r
-#define USBFS_DWR_VDDD_OPERATION (0x02u)\r
+#define USBFS_DWR_POWER_OPERATION (0x02u)\r
\r
#define USBFS_MODE_DISABLE (0x00u)\r
#define USBFS_MODE_NAK_IN_OUT (0x01u)\r
#define USBFS_RQST_RCPT_EP (0x02u)\r
#define USBFS_RQST_RCPT_OTHER (0x03u)\r
\r
+#if (USBFS_LPM_ACTIVE)\r
+ #define USBFS_LPM_REQ_ACK (0x01u << USBFS_LPM_CTRL_LPM_ACK_RESP_POS)\r
+ #define USBFS_LPM_REQ_NACK (0x00u)\r
+ #define USBFS_LPM_REQ_NYET (0x01u << USBFS_LPM_CTRL_NYET_EN_POS)\r
+#endif /*(USBFS_LPM_ACTIVE)*/\r
+\r
/* USB Class Codes */\r
#define USBFS_CLASS_DEVICE (0x00u) /* Use class code info from Interface Descriptors */\r
#define USBFS_CLASS_AUDIO (0x01u) /* Audio device */\r
#define USBFS_CLASS_SMART_CARD (0x0Bu) /* Smart Card device */\r
#define USBFS_CLASS_CSD (0x0Du) /* Content Security device */\r
#define USBFS_CLASS_VIDEO (0x0Eu) /* Video device */\r
-#define USBFS_CLASS_PHD (0x0Fu) /* Personal Healthcare device */\r
+#define USBFS_CLASS_PHD (0x0Fu) /* Personal Health care device */\r
#define USBFS_CLASS_WIRELESSD (0xDCu) /* Wireless Controller */\r
#define USBFS_CLASS_MIS (0xE0u) /* Miscellaneous */\r
#define USBFS_CLASS_APP (0xEFu) /* Application Specific */\r
#define USBFS_CLASS_VENDOR (0xFFu) /* Vendor specific */\r
\r
-\r
/* Standard Request Types (Table 9-4) */\r
#define USBFS_GET_STATUS (0x00u)\r
#define USBFS_CLEAR_FEATURE (0x01u)\r
#define USBFS_DESCR_DEVICE_QUALIFIER (6u)\r
#define USBFS_DESCR_OTHER_SPEED (7u)\r
#define USBFS_DESCR_INTERFACE_POWER (8u)\r
-\r
+#if (USBFS_BOS_ENABLE)\r
+ #define USBFS_DESCR_BOS (15u)\r
+#endif /* (USBFS_BOS_ENABLE) */\r
/* Device Descriptor Defines */\r
#define USBFS_DEVICE_DESCR_LENGTH (18u)\r
#define USBFS_DEVICE_DESCR_SN_SHIFT (16u)\r
#define USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED (0x40u)\r
#define USBFS_CONFIG_DESCR_ATTRIB_RWU_EN (0x20u)\r
\r
+#if (USBFS_BOS_ENABLE)\r
+ /* Config Descriptor BOS */\r
+ #define USBFS_BOS_DESCR_LENGTH (0u)\r
+ #define USBFS_BOS_DESCR_TYPE (1u)\r
+ #define USBFS_BOS_DESCR_TOTAL_LENGTH_LOW (2u)\r
+ #define USBFS_BOS_DESCR_TOTAL_LENGTH_HI (3u)\r
+ #define USBFS_BOS_DESCR_NUM_DEV_CAPS (4u)\r
+#endif /* (USBFS_BOS_ENABLE) */\r
+\r
/* Feature Selectors (Table 9-6) */\r
#define USBFS_DEVICE_REMOTE_WAKEUP (0x01u)\r
#define USBFS_ENDPOINT_HALT (0x00u)\r
#define USBFS_EP_USAGE_TYPE_RESERVED (0x30u)\r
#define USBFS_EP_USAGE_TYPE_MASK (0x30u)\r
\r
-/* point Status defines */\r
+/* Point Status defines */\r
#define USBFS_EP_STATUS_LENGTH (0x02u)\r
\r
-/* point Device defines */\r
+/* Point Device defines */\r
#define USBFS_DEVICE_STATUS_LENGTH (0x02u)\r
\r
#define USBFS_STATUS_LENGTH_MAX \\r
- ( (USBFS_EP_STATUS_LENGTH > USBFS_DEVICE_STATUS_LENGTH) ? \\r
- USBFS_EP_STATUS_LENGTH : USBFS_DEVICE_STATUS_LENGTH )\r
+ ((USBFS_EP_STATUS_LENGTH > USBFS_DEVICE_STATUS_LENGTH) ? \\r
+ USBFS_EP_STATUS_LENGTH : USBFS_DEVICE_STATUS_LENGTH)\r
+\r
/* Transfer Completion Notification */\r
#define USBFS_XFER_IDLE (0x00u)\r
#define USBFS_XFER_STATUS_ACK (0x01u)\r
#define USBFS_MSOS_DESCRIPTOR_LENGTH (18u)\r
#define USBFS_MSOS_CONF_DESCR_LENGTH (40u)\r
\r
-#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
- /* DMA manual mode defines */\r
- #define USBFS_DMA_BYTES_PER_BURST (0u)\r
- #define USBFS_DMA_REQUEST_PER_BURST (0u)\r
-#endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
-#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- /* DMA automatic mode defines */\r
- #define USBFS_DMA_BYTES_PER_BURST (32u)\r
- #define USBFS_DMA_BYTES_REPEAT (2u)\r
- /* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */\r
- #define USBFS_DMA_BUF_SIZE (0x55u)\r
- #define USBFS_DMA_REQUEST_PER_BURST (1u)\r
-\r
- #if(USBFS_DMA1_REMOVE == 0u)\r
- #define USBFS_ep1_TD_TERMOUT_EN USBFS_ep1__TD_TERMOUT_EN\r
- #else\r
- #define USBFS_ep1_TD_TERMOUT_EN (0u)\r
- #endif /* USBFS_DMA1_REMOVE == 0u */\r
- #if(USBFS_DMA2_REMOVE == 0u)\r
- #define USBFS_ep2_TD_TERMOUT_EN USBFS_ep2__TD_TERMOUT_EN\r
- #else\r
- #define USBFS_ep2_TD_TERMOUT_EN (0u)\r
- #endif /* USBFS_DMA2_REMOVE == 0u */\r
- #if(USBFS_DMA3_REMOVE == 0u)\r
- #define USBFS_ep3_TD_TERMOUT_EN USBFS_ep3__TD_TERMOUT_EN\r
- #else\r
- #define USBFS_ep3_TD_TERMOUT_EN (0u)\r
- #endif /* USBFS_DMA3_REMOVE == 0u */\r
- #if(USBFS_DMA4_REMOVE == 0u)\r
- #define USBFS_ep4_TD_TERMOUT_EN USBFS_ep4__TD_TERMOUT_EN\r
- #else\r
- #define USBFS_ep4_TD_TERMOUT_EN (0u)\r
- #endif /* USBFS_DMA4_REMOVE == 0u */\r
- #if(USBFS_DMA5_REMOVE == 0u)\r
- #define USBFS_ep5_TD_TERMOUT_EN USBFS_ep5__TD_TERMOUT_EN\r
- #else\r
- #define USBFS_ep5_TD_TERMOUT_EN (0u)\r
- #endif /* USBFS_DMA5_REMOVE == 0u */\r
- #if(USBFS_DMA6_REMOVE == 0u)\r
- #define USBFS_ep6_TD_TERMOUT_EN USBFS_ep6__TD_TERMOUT_EN\r
- #else\r
- #define USBFS_ep6_TD_TERMOUT_EN (0u)\r
- #endif /* USBFS_DMA6_REMOVE == 0u */\r
- #if(USBFS_DMA7_REMOVE == 0u)\r
- #define USBFS_ep7_TD_TERMOUT_EN USBFS_ep7__TD_TERMOUT_EN\r
- #else\r
- #define USBFS_ep7_TD_TERMOUT_EN (0u)\r
- #endif /* USBFS_DMA7_REMOVE == 0u */\r
- #if(USBFS_DMA8_REMOVE == 0u)\r
- #define USBFS_ep8_TD_TERMOUT_EN USBFS_ep8__TD_TERMOUT_EN\r
- #else\r
- #define USBFS_ep8_TD_TERMOUT_EN (0u)\r
- #endif /* USBFS_DMA8_REMOVE == 0u */\r
-\r
- #define USBFS_EP17_SR_MASK (0x7fu)\r
- #define USBFS_EP8_SR_MASK (0x03u)\r
-\r
-#endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+/* Return values */\r
+#define USBFS_BCD_PORT_SDP (1u) /* Standard downstream port detected */\r
+#define USBFS_BCD_PORT_CDP (2u) /* Charging downstream port detected */\r
+#define USBFS_BCD_PORT_DCP (3u) /* Dedicated charging port detected */\r
+#define USBFS_BCD_PORT_UNKNOWN (0u) /* Unable to detect charging port */\r
+#define USBFS_BCD_PORT_ERR (4u) /* Error condition in detection process*/\r
+\r
+\r
+/* Timeouts for BCD */\r
+#define USBFS_BCD_TIMEOUT (400u) /* Copied from PBK#163 TIMEOUT (300 ms) */\r
+#define USBFS_BCD_TDCD_DBNC (10u) /*BCD v1.2: DCD debounce time 10 ms*/\r
+#define USBFS_BCD_PRIMARY_WAIT (40u) /* Copied from PBK#163 TIMEOUT (40 ms) */\r
+#define USBFS_BCD_SECONDARY_WAIT (47u) /* Copied from PBK#163 TIMEOUT (40 ms) */\r
+#define USBFS_BCD_SUSPEND_DISABLE_WAIT (2u) /* Copied from PBK#163 TIMEOUT (2 us) */\r
+\r
+/* Wait cycles required before clearing SUSPEND_DEL in POWER_CTRL: 2us */\r
+#define USBFS_WAIT_SUSPEND_DEL_DISABLE (2u)\r
+\r
+/* Wait cycles required for USB regulator stabilization after it is enabled : 50ns */\r
+#define USBFS_WAIT_VREF_STABILITY (0u)\r
+\r
+#if (CY_PSOC3 || CY_PSOC5LP)\r
+/* Wait cycles required for USB reference restore: 40us */\r
+#define USBFS_WAIT_VREF_RESTORE (40u)\r
+\r
+/* Wait cycles required for stabilization after register is written : 50ns */\r
+#define USBFS_WAIT_REG_STABILITY_50NS (0u)\r
+#define USBFS_WAIT_REG_STABILITY_1US (1u)\r
+\r
+/* Wait cycles required after CR0 register write: 1 cycle */\r
+#define USBFS_WAIT_CR0_REG_STABILITY (1u)\r
+\r
+/* Wait cycles required after PD_PULLUP_N bit is set in PM_USB_CR0: 2us */\r
+#define USBFS_WAIT_PD_PULLUP_N_ENABLE (2u)\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+#if (CY_PSOC4)\r
+ #if (USBFS_EP_MANAGEMENT_DMA)\r
+ #define USBFS_DMA_DESCR0 (0u)\r
+ #define USBFS_DMA_DESCR1 (1u)\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* BUF_SIZE-BYTES_PER_BURST examples: 0x55 - 32 bytes, 0x44 - 16 bytes, 0x33 - 8 bytes, etc. */\r
+ #define USBFS_DMA_BUF_SIZE (0x55u)\r
+ #define USBFS_DMA_BYTES_PER_BURST (32u)\r
+ #define USBFS_DMA_HALFWORDS_PER_BURST (16u)\r
+ #define USBFS_DMA_BURST_BYTES_MASK (USBFS_DMA_BYTES_PER_BURST - 1u)\r
+\r
+ #define USBFS_DMA_DESCR0_MASK (0x00u)\r
+ #define USBFS_DMA_DESCR1_MASK (0x80u)\r
+ #define USBFS_DMA_DESCR_REVERT (0x40u)\r
+ #define USBFS_DMA_DESCR_16BITS (0x20u)\r
+ #define USBFS_DMA_DESCR_SHIFT (7u)\r
+\r
+ #define USBFS_DMA_GET_DESCR_NUM(desrc)\r
+ #define USBFS_DMA_GET_BURST_CNT(dmaBurstCnt) \\r
+ (((dmaBurstCnt) > 2u)? ((dmaBurstCnt) - 2u) : 0u)\r
+\r
+ #define USBFS_DMA_GET_MAX_ELEM_PER_BURST(dmaLastBurstEl) \\r
+ ((0u != ((dmaLastBurstEl) & USBFS_DMA_DESCR_16BITS)) ? \\r
+ (USBFS_DMA_HALFWORDS_PER_BURST - 1u) : (USBFS_DMA_BYTES_PER_BURST - 1u))\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+#else\r
+ #if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ #define USBFS_DMA_BYTES_PER_BURST (0u)\r
+ #define USBFS_DMA_REQUEST_PER_BURST (0u)\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ #define USBFS_DMA_BYTES_PER_BURST (32u)\r
+ #define USBFS_DMA_BYTES_REPEAT (2u)\r
+\r
+ /* BUF_SIZE-BYTES_PER_BURST examples: 0x55 - 32 bytes, 0x44 - 16 bytes, 0x33 - 8 bytes, etc. */\r
+ #define USBFS_DMA_BUF_SIZE (0x55u)\r
+ #define USBFS_DMA_REQUEST_PER_BURST (1u)\r
+\r
+ #define USBFS_EP17_SR_MASK (0x7Fu)\r
+ #define USBFS_EP8_SR_MASK (0x03u)\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+#endif /* (CY_PSOC4) */\r
\r
/* DIE ID string descriptor defines */\r
#if defined(USBFS_ENABLE_IDSN_STRING)\r
- #define USBFS_IDSN_DESCR_LENGTH (0x22u)\r
-#endif /* USBFS_ENABLE_IDSN_STRING */\r
+ #define USBFS_IDSN_DESCR_LENGTH (0x22u)\r
+#endif /* (USBFS_ENABLE_IDSN_STRING) */\r
\r
\r
/***************************************\r
-* External data references\r
+* Vars with External Linkage\r
***************************************/\r
\r
+/**\r
+* \addtogroup group_globals\r
+* @{\r
+*/\r
extern uint8 USBFS_initVar;\r
extern volatile uint8 USBFS_device;\r
extern volatile uint8 USBFS_transferState;\r
extern volatile uint8 USBFS_configuration;\r
extern volatile uint8 USBFS_configurationChanged;\r
extern volatile uint8 USBFS_deviceStatus;\r
+/** @} globals */\r
\r
+/**\r
+* \addtogroup group_hid\r
+* @{\r
+*/\r
/* HID Variables */\r
#if defined(USBFS_ENABLE_HID_CLASS)\r
- extern volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER];\r
- extern volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER];\r
+ extern volatile uint8 USBFS_hidProtocol [USBFS_MAX_INTERFACES_NUMBER]; \r
+ extern volatile uint8 USBFS_hidIdleRate [USBFS_MAX_INTERFACES_NUMBER];\r
extern volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER];\r
-#endif /* USBFS_ENABLE_HID_CLASS */\r
+#endif /* (USBFS_ENABLE_HID_CLASS) */\r
+/** @} hid */\r
\r
\r
/***************************************\r
* Registers\r
***************************************/\r
\r
-#define USBFS_ARB_CFG_PTR ( (reg8 *) USBFS_USB__ARB_CFG)\r
-#define USBFS_ARB_CFG_REG (* (reg8 *) USBFS_USB__ARB_CFG)\r
+/* Common registers for all PSoCs: 3/4/5LP */\r
+#define USBFS_ARB_CFG_PTR ( (reg8 *) USBFS_USB__ARB_CFG)\r
+#define USBFS_ARB_CFG_REG (*(reg8 *) USBFS_USB__ARB_CFG)\r
\r
-#define USBFS_ARB_EP1_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP1_CFG)\r
-#define USBFS_ARB_EP1_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP1_CFG)\r
+#define USBFS_ARB_EP1_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP1_CFG)\r
+#define USBFS_ARB_EP1_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP1_CFG)\r
+#define USBFS_ARB_EP1_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP1_INT_EN)\r
+#define USBFS_ARB_EP1_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP1_INT_EN)\r
+#define USBFS_ARB_EP1_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP1_SR)\r
+#define USBFS_ARB_EP1_SR_REG (*(reg8 *) USBFS_USB__ARB_EP1_SR)\r
#define USBFS_ARB_EP1_CFG_IND USBFS_USB__ARB_EP1_CFG\r
-#define USBFS_ARB_EP1_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP1_INT_EN)\r
-#define USBFS_ARB_EP1_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP1_INT_EN)\r
#define USBFS_ARB_EP1_INT_EN_IND USBFS_USB__ARB_EP1_INT_EN\r
-#define USBFS_ARB_EP1_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP1_SR)\r
-#define USBFS_ARB_EP1_SR_REG (* (reg8 *) USBFS_USB__ARB_EP1_SR)\r
#define USBFS_ARB_EP1_SR_IND USBFS_USB__ARB_EP1_SR\r
-\r
-#define USBFS_ARB_EP2_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP2_CFG)\r
-#define USBFS_ARB_EP2_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP2_CFG)\r
-#define USBFS_ARB_EP2_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP2_INT_EN)\r
-#define USBFS_ARB_EP2_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP2_INT_EN)\r
-#define USBFS_ARB_EP2_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP2_SR)\r
-#define USBFS_ARB_EP2_SR_REG (* (reg8 *) USBFS_USB__ARB_EP2_SR)\r
-\r
-#define USBFS_ARB_EP3_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP3_CFG)\r
-#define USBFS_ARB_EP3_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP3_CFG)\r
-#define USBFS_ARB_EP3_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP3_INT_EN)\r
-#define USBFS_ARB_EP3_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP3_INT_EN)\r
-#define USBFS_ARB_EP3_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP3_SR)\r
-#define USBFS_ARB_EP3_SR_REG (* (reg8 *) USBFS_USB__ARB_EP3_SR)\r
-\r
-#define USBFS_ARB_EP4_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP4_CFG)\r
-#define USBFS_ARB_EP4_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP4_CFG)\r
-#define USBFS_ARB_EP4_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP4_INT_EN)\r
-#define USBFS_ARB_EP4_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP4_INT_EN)\r
-#define USBFS_ARB_EP4_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP4_SR)\r
-#define USBFS_ARB_EP4_SR_REG (* (reg8 *) USBFS_USB__ARB_EP4_SR)\r
-\r
-#define USBFS_ARB_EP5_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP5_CFG)\r
-#define USBFS_ARB_EP5_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP5_CFG)\r
-#define USBFS_ARB_EP5_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP5_INT_EN)\r
-#define USBFS_ARB_EP5_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP5_INT_EN)\r
-#define USBFS_ARB_EP5_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP5_SR)\r
-#define USBFS_ARB_EP5_SR_REG (* (reg8 *) USBFS_USB__ARB_EP5_SR)\r
-\r
-#define USBFS_ARB_EP6_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP6_CFG)\r
-#define USBFS_ARB_EP6_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP6_CFG)\r
-#define USBFS_ARB_EP6_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP6_INT_EN)\r
-#define USBFS_ARB_EP6_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP6_INT_EN)\r
-#define USBFS_ARB_EP6_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP6_SR)\r
-#define USBFS_ARB_EP6_SR_REG (* (reg8 *) USBFS_USB__ARB_EP6_SR)\r
-\r
-#define USBFS_ARB_EP7_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP7_CFG)\r
-#define USBFS_ARB_EP7_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP7_CFG)\r
-#define USBFS_ARB_EP7_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP7_INT_EN)\r
-#define USBFS_ARB_EP7_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP7_INT_EN)\r
-#define USBFS_ARB_EP7_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP7_SR)\r
-#define USBFS_ARB_EP7_SR_REG (* (reg8 *) USBFS_USB__ARB_EP7_SR)\r
-\r
-#define USBFS_ARB_EP8_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP8_CFG)\r
-#define USBFS_ARB_EP8_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP8_CFG)\r
-#define USBFS_ARB_EP8_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP8_INT_EN)\r
-#define USBFS_ARB_EP8_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP8_INT_EN)\r
-#define USBFS_ARB_EP8_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP8_SR)\r
-#define USBFS_ARB_EP8_SR_REG (* (reg8 *) USBFS_USB__ARB_EP8_SR)\r
-\r
-#define USBFS_ARB_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_INT_EN)\r
-#define USBFS_ARB_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_INT_EN)\r
-#define USBFS_ARB_INT_SR_PTR ( (reg8 *) USBFS_USB__ARB_INT_SR)\r
-#define USBFS_ARB_INT_SR_REG (* (reg8 *) USBFS_USB__ARB_INT_SR)\r
-\r
-#define USBFS_ARB_RW1_DR_PTR ((reg8 *) USBFS_USB__ARB_RW1_DR)\r
+#define USBFS_ARB_EP_BASE (*(volatile USBFS_arb_eps_struct CYXDATA *) \\r
+ (USBFS_USB__ARB_EP1_CFG - sizeof(USBFS_arb_ep_struct)))\r
+\r
+#define USBFS_ARB_EP2_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP2_CFG)\r
+#define USBFS_ARB_EP2_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP2_CFG)\r
+#define USBFS_ARB_EP2_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP2_INT_EN)\r
+#define USBFS_ARB_EP2_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP2_INT_EN)\r
+#define USBFS_ARB_EP2_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP2_SR)\r
+#define USBFS_ARB_EP2_SR_REG (*(reg8 *) USBFS_USB__ARB_EP2_SR)\r
+\r
+#define USBFS_ARB_EP3_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP3_CFG)\r
+#define USBFS_ARB_EP3_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP3_CFG)\r
+#define USBFS_ARB_EP3_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP3_INT_EN)\r
+#define USBFS_ARB_EP3_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP3_INT_EN)\r
+#define USBFS_ARB_EP3_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP3_SR)\r
+#define USBFS_ARB_EP3_SR_REG (*(reg8 *) USBFS_USB__ARB_EP3_SR)\r
+\r
+#define USBFS_ARB_EP4_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP4_CFG)\r
+#define USBFS_ARB_EP4_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP4_CFG)\r
+#define USBFS_ARB_EP4_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP4_INT_EN)\r
+#define USBFS_ARB_EP4_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP4_INT_EN)\r
+#define USBFS_ARB_EP4_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP4_SR)\r
+#define USBFS_ARB_EP4_SR_REG (*(reg8 *) USBFS_USB__ARB_EP4_SR)\r
+\r
+#define USBFS_ARB_EP5_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP5_CFG)\r
+#define USBFS_ARB_EP5_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP5_CFG)\r
+#define USBFS_ARB_EP5_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP5_INT_EN)\r
+#define USBFS_ARB_EP5_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP5_INT_EN)\r
+#define USBFS_ARB_EP5_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP5_SR)\r
+#define USBFS_ARB_EP5_SR_REG (*(reg8 *) USBFS_USB__ARB_EP5_SR)\r
+\r
+#define USBFS_ARB_EP6_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP6_CFG)\r
+#define USBFS_ARB_EP6_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP6_CFG)\r
+#define USBFS_ARB_EP6_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP6_INT_EN)\r
+#define USBFS_ARB_EP6_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP6_INT_EN)\r
+#define USBFS_ARB_EP6_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP6_SR)\r
+#define USBFS_ARB_EP6_SR_REG (*(reg8 *) USBFS_USB__ARB_EP6_SR)\r
+\r
+#define USBFS_ARB_EP7_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP7_CFG)\r
+#define USBFS_ARB_EP7_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP7_CFG)\r
+#define USBFS_ARB_EP7_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP7_INT_EN)\r
+#define USBFS_ARB_EP7_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP7_INT_EN)\r
+#define USBFS_ARB_EP7_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP7_SR)\r
+#define USBFS_ARB_EP7_SR_REG (*(reg8 *) USBFS_USB__ARB_EP7_SR)\r
+\r
+#define USBFS_ARB_EP8_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP8_CFG)\r
+#define USBFS_ARB_EP8_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP8_CFG)\r
+#define USBFS_ARB_EP8_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP8_INT_EN)\r
+#define USBFS_ARB_EP8_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP8_INT_EN)\r
+#define USBFS_ARB_EP8_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP8_SR)\r
+#define USBFS_ARB_EP8_SR_REG (*(reg8 *) USBFS_USB__ARB_EP8_SR)\r
+\r
+#define USBFS_ARB_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_INT_EN)\r
+#define USBFS_ARB_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_INT_EN)\r
+#define USBFS_ARB_INT_SR_PTR ( (reg8 *) USBFS_USB__ARB_INT_SR)\r
+#define USBFS_ARB_INT_SR_REG (*(reg8 *) USBFS_USB__ARB_INT_SR)\r
+\r
+#define USBFS_ARB_RW1_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW1_DR)\r
+#define USBFS_ARB_RW1_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW1_RA)\r
+\r
+#define USBFS_ARB_RW1_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW1_RA_MSB)\r
+#define USBFS_ARB_RW1_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW1_WA)\r
+#define USBFS_ARB_RW1_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW1_WA_MSB)\r
#define USBFS_ARB_RW1_DR_IND USBFS_USB__ARB_RW1_DR\r
-#define USBFS_ARB_RW1_RA_PTR ((reg8 *) USBFS_USB__ARB_RW1_RA)\r
#define USBFS_ARB_RW1_RA_IND USBFS_USB__ARB_RW1_RA\r
-#define USBFS_ARB_RW1_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_RA_MSB)\r
#define USBFS_ARB_RW1_RA_MSB_IND USBFS_USB__ARB_RW1_RA_MSB\r
-#define USBFS_ARB_RW1_WA_PTR ((reg8 *) USBFS_USB__ARB_RW1_WA)\r
#define USBFS_ARB_RW1_WA_IND USBFS_USB__ARB_RW1_WA\r
-#define USBFS_ARB_RW1_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_WA_MSB)\r
#define USBFS_ARB_RW1_WA_MSB_IND USBFS_USB__ARB_RW1_WA_MSB\r
\r
-#define USBFS_ARB_RW2_DR_PTR ((reg8 *) USBFS_USB__ARB_RW2_DR)\r
-#define USBFS_ARB_RW2_RA_PTR ((reg8 *) USBFS_USB__ARB_RW2_RA)\r
-#define USBFS_ARB_RW2_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_RA_MSB)\r
-#define USBFS_ARB_RW2_WA_PTR ((reg8 *) USBFS_USB__ARB_RW2_WA)\r
-#define USBFS_ARB_RW2_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_WA_MSB)\r
-\r
-#define USBFS_ARB_RW3_DR_PTR ((reg8 *) USBFS_USB__ARB_RW3_DR)\r
-#define USBFS_ARB_RW3_RA_PTR ((reg8 *) USBFS_USB__ARB_RW3_RA)\r
-#define USBFS_ARB_RW3_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_RA_MSB)\r
-#define USBFS_ARB_RW3_WA_PTR ((reg8 *) USBFS_USB__ARB_RW3_WA)\r
-#define USBFS_ARB_RW3_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_WA_MSB)\r
-\r
-#define USBFS_ARB_RW4_DR_PTR ((reg8 *) USBFS_USB__ARB_RW4_DR)\r
-#define USBFS_ARB_RW4_RA_PTR ((reg8 *) USBFS_USB__ARB_RW4_RA)\r
-#define USBFS_ARB_RW4_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_RA_MSB)\r
-#define USBFS_ARB_RW4_WA_PTR ((reg8 *) USBFS_USB__ARB_RW4_WA)\r
-#define USBFS_ARB_RW4_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_WA_MSB)\r
-\r
-#define USBFS_ARB_RW5_DR_PTR ((reg8 *) USBFS_USB__ARB_RW5_DR)\r
-#define USBFS_ARB_RW5_RA_PTR ((reg8 *) USBFS_USB__ARB_RW5_RA)\r
-#define USBFS_ARB_RW5_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_RA_MSB)\r
-#define USBFS_ARB_RW5_WA_PTR ((reg8 *) USBFS_USB__ARB_RW5_WA)\r
-#define USBFS_ARB_RW5_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_WA_MSB)\r
-\r
-#define USBFS_ARB_RW6_DR_PTR ((reg8 *) USBFS_USB__ARB_RW6_DR)\r
-#define USBFS_ARB_RW6_RA_PTR ((reg8 *) USBFS_USB__ARB_RW6_RA)\r
-#define USBFS_ARB_RW6_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_RA_MSB)\r
-#define USBFS_ARB_RW6_WA_PTR ((reg8 *) USBFS_USB__ARB_RW6_WA)\r
-#define USBFS_ARB_RW6_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_WA_MSB)\r
-\r
-#define USBFS_ARB_RW7_DR_PTR ((reg8 *) USBFS_USB__ARB_RW7_DR)\r
-#define USBFS_ARB_RW7_RA_PTR ((reg8 *) USBFS_USB__ARB_RW7_RA)\r
-#define USBFS_ARB_RW7_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_RA_MSB)\r
-#define USBFS_ARB_RW7_WA_PTR ((reg8 *) USBFS_USB__ARB_RW7_WA)\r
-#define USBFS_ARB_RW7_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_WA_MSB)\r
-\r
-#define USBFS_ARB_RW8_DR_PTR ((reg8 *) USBFS_USB__ARB_RW8_DR)\r
-#define USBFS_ARB_RW8_RA_PTR ((reg8 *) USBFS_USB__ARB_RW8_RA)\r
-#define USBFS_ARB_RW8_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_RA_MSB)\r
-#define USBFS_ARB_RW8_WA_PTR ((reg8 *) USBFS_USB__ARB_RW8_WA)\r
-#define USBFS_ARB_RW8_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_WA_MSB)\r
-\r
-#define USBFS_BUF_SIZE_PTR ( (reg8 *) USBFS_USB__BUF_SIZE)\r
-#define USBFS_BUF_SIZE_REG (* (reg8 *) USBFS_USB__BUF_SIZE)\r
-#define USBFS_BUS_RST_CNT_PTR ( (reg8 *) USBFS_USB__BUS_RST_CNT)\r
-#define USBFS_BUS_RST_CNT_REG (* (reg8 *) USBFS_USB__BUS_RST_CNT)\r
-#define USBFS_CWA_PTR ( (reg8 *) USBFS_USB__CWA)\r
-#define USBFS_CWA_REG (* (reg8 *) USBFS_USB__CWA)\r
-#define USBFS_CWA_MSB_PTR ( (reg8 *) USBFS_USB__CWA_MSB)\r
-#define USBFS_CWA_MSB_REG (* (reg8 *) USBFS_USB__CWA_MSB)\r
-#define USBFS_CR0_PTR ( (reg8 *) USBFS_USB__CR0)\r
-#define USBFS_CR0_REG (* (reg8 *) USBFS_USB__CR0)\r
-#define USBFS_CR1_PTR ( (reg8 *) USBFS_USB__CR1)\r
-#define USBFS_CR1_REG (* (reg8 *) USBFS_USB__CR1)\r
-\r
-#define USBFS_DMA_THRES_PTR ( (reg8 *) USBFS_USB__DMA_THRES)\r
-#define USBFS_DMA_THRES_REG (* (reg8 *) USBFS_USB__DMA_THRES)\r
-#define USBFS_DMA_THRES_MSB_PTR ( (reg8 *) USBFS_USB__DMA_THRES_MSB)\r
-#define USBFS_DMA_THRES_MSB_REG (* (reg8 *) USBFS_USB__DMA_THRES_MSB)\r
-\r
-#define USBFS_EP_ACTIVE_PTR ( (reg8 *) USBFS_USB__EP_ACTIVE)\r
-#define USBFS_EP_ACTIVE_REG (* (reg8 *) USBFS_USB__EP_ACTIVE)\r
-#define USBFS_EP_TYPE_PTR ( (reg8 *) USBFS_USB__EP_TYPE)\r
-#define USBFS_EP_TYPE_REG (* (reg8 *) USBFS_USB__EP_TYPE)\r
-\r
-#define USBFS_EP0_CNT_PTR ( (reg8 *) USBFS_USB__EP0_CNT)\r
-#define USBFS_EP0_CNT_REG (* (reg8 *) USBFS_USB__EP0_CNT)\r
-#define USBFS_EP0_CR_PTR ( (reg8 *) USBFS_USB__EP0_CR)\r
-#define USBFS_EP0_CR_REG (* (reg8 *) USBFS_USB__EP0_CR)\r
-#define USBFS_EP0_DR0_PTR ( (reg8 *) USBFS_USB__EP0_DR0)\r
-#define USBFS_EP0_DR0_REG (* (reg8 *) USBFS_USB__EP0_DR0)\r
+#define USBFS_ARB_RW2_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW2_DR)\r
+#define USBFS_ARB_RW2_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW2_RA)\r
+#define USBFS_ARB_RW2_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW2_RA_MSB)\r
+#define USBFS_ARB_RW2_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW2_WA)\r
+#define USBFS_ARB_RW2_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW2_WA_MSB)\r
+\r
+#define USBFS_ARB_RW3_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW3_DR)\r
+#define USBFS_ARB_RW3_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW3_RA)\r
+#define USBFS_ARB_RW3_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW3_RA_MSB)\r
+#define USBFS_ARB_RW3_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW3_WA)\r
+#define USBFS_ARB_RW3_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW3_WA_MSB)\r
+\r
+#define USBFS_ARB_RW4_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW4_DR)\r
+#define USBFS_ARB_RW4_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW4_RA)\r
+#define USBFS_ARB_RW4_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW4_RA_MSB)\r
+#define USBFS_ARB_RW4_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW4_WA)\r
+#define USBFS_ARB_RW4_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW4_WA_MSB)\r
+\r
+#define USBFS_ARB_RW5_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW5_DR)\r
+#define USBFS_ARB_RW5_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW5_RA)\r
+#define USBFS_ARB_RW5_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW5_RA_MSB)\r
+#define USBFS_ARB_RW5_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW5_WA)\r
+#define USBFS_ARB_RW5_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW5_WA_MSB)\r
+\r
+#define USBFS_ARB_RW6_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW6_DR)\r
+#define USBFS_ARB_RW6_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW6_RA)\r
+#define USBFS_ARB_RW6_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW6_RA_MSB)\r
+#define USBFS_ARB_RW6_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW6_WA)\r
+#define USBFS_ARB_RW6_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW6_WA_MSB)\r
+\r
+#define USBFS_ARB_RW7_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW7_DR)\r
+#define USBFS_ARB_RW7_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW7_RA)\r
+#define USBFS_ARB_RW7_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW7_RA_MSB)\r
+#define USBFS_ARB_RW7_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW7_WA)\r
+#define USBFS_ARB_RW7_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW7_WA_MSB)\r
+\r
+#define USBFS_ARB_RW8_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW8_DR)\r
+#define USBFS_ARB_RW8_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW8_RA)\r
+#define USBFS_ARB_RW8_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW8_RA_MSB)\r
+#define USBFS_ARB_RW8_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW8_WA)\r
+#define USBFS_ARB_RW8_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW8_WA_MSB)\r
+\r
+#define USBFS_BUF_SIZE_PTR ( (reg8 *) USBFS_USB__BUF_SIZE)\r
+#define USBFS_BUF_SIZE_REG (*(reg8 *) USBFS_USB__BUF_SIZE)\r
+#define USBFS_BUS_RST_CNT_PTR ( (reg8 *) USBFS_USB__BUS_RST_CNT)\r
+#define USBFS_BUS_RST_CNT_REG (*(reg8 *) USBFS_USB__BUS_RST_CNT)\r
+#define USBFS_CWA_PTR ( (reg8 *) USBFS_USB__CWA)\r
+#define USBFS_CWA_REG (*(reg8 *) USBFS_USB__CWA)\r
+#define USBFS_CWA_MSB_PTR ( (reg8 *) USBFS_USB__CWA_MSB)\r
+#define USBFS_CWA_MSB_REG (*(reg8 *) USBFS_USB__CWA_MSB)\r
+#define USBFS_CR0_PTR ( (reg8 *) USBFS_USB__CR0)\r
+#define USBFS_CR0_REG (*(reg8 *) USBFS_USB__CR0)\r
+#define USBFS_CR1_PTR ( (reg8 *) USBFS_USB__CR1)\r
+#define USBFS_CR1_REG (*(reg8 *) USBFS_USB__CR1)\r
+\r
+#define USBFS_DMA_THRES_PTR ( (reg8 *) USBFS_USB__DMA_THRES)\r
+#define USBFS_DMA_THRES_REG (*(reg8 *) USBFS_USB__DMA_THRES)\r
+#define USBFS_DMA_THRES_MSB_PTR ( (reg8 *) USBFS_USB__DMA_THRES_MSB)\r
+#define USBFS_DMA_THRES_MSB_REG (*(reg8 *) USBFS_USB__DMA_THRES_MSB)\r
+\r
+#define USBFS_EP_ACTIVE_PTR ( (reg8 *) USBFS_USB__EP_ACTIVE)\r
+#define USBFS_EP_ACTIVE_REG (*(reg8 *) USBFS_USB__EP_ACTIVE)\r
+#define USBFS_EP_TYPE_PTR ( (reg8 *) USBFS_USB__EP_TYPE)\r
+#define USBFS_EP_TYPE_REG (*(reg8 *) USBFS_USB__EP_TYPE)\r
+\r
+#define USBFS_EP0_CNT_PTR ( (reg8 *) USBFS_USB__EP0_CNT)\r
+#define USBFS_EP0_CNT_REG (*(reg8 *) USBFS_USB__EP0_CNT)\r
+#define USBFS_EP0_CR_PTR ( (reg8 *) USBFS_USB__EP0_CR)\r
+#define USBFS_EP0_CR_REG (*(reg8 *) USBFS_USB__EP0_CR)\r
+#define USBFS_EP0_DR0_PTR ( (reg8 *) USBFS_USB__EP0_DR0)\r
+#define USBFS_EP0_DR0_REG (*(reg8 *) USBFS_USB__EP0_DR0)\r
+#define USBFS_EP0_DR1_PTR ( (reg8 *) USBFS_USB__EP0_DR1)\r
+#define USBFS_EP0_DR1_REG (*(reg8 *) USBFS_USB__EP0_DR1)\r
+#define USBFS_EP0_DR2_PTR ( (reg8 *) USBFS_USB__EP0_DR2)\r
+#define USBFS_EP0_DR2_REG (*(reg8 *) USBFS_USB__EP0_DR2)\r
+#define USBFS_EP0_DR3_PTR ( (reg8 *) USBFS_USB__EP0_DR3)\r
+#define USBFS_EP0_DR3_REG (*(reg8 *) USBFS_USB__EP0_DR3)\r
+#define USBFS_EP0_DR4_PTR ( (reg8 *) USBFS_USB__EP0_DR4)\r
+#define USBFS_EP0_DR4_REG (*(reg8 *) USBFS_USB__EP0_DR4)\r
+#define USBFS_EP0_DR5_PTR ( (reg8 *) USBFS_USB__EP0_DR5)\r
+#define USBFS_EP0_DR5_REG (*(reg8 *) USBFS_USB__EP0_DR5)\r
+#define USBFS_EP0_DR6_PTR ( (reg8 *) USBFS_USB__EP0_DR6)\r
+#define USBFS_EP0_DR6_REG (*(reg8 *) USBFS_USB__EP0_DR6)\r
+#define USBFS_EP0_DR7_PTR ( (reg8 *) USBFS_USB__EP0_DR7)\r
+#define USBFS_EP0_DR7_REG (*(reg8 *) USBFS_USB__EP0_DR7)\r
#define USBFS_EP0_DR0_IND USBFS_USB__EP0_DR0\r
-#define USBFS_EP0_DR1_PTR ( (reg8 *) USBFS_USB__EP0_DR1)\r
-#define USBFS_EP0_DR1_REG (* (reg8 *) USBFS_USB__EP0_DR1)\r
-#define USBFS_EP0_DR2_PTR ( (reg8 *) USBFS_USB__EP0_DR2)\r
-#define USBFS_EP0_DR2_REG (* (reg8 *) USBFS_USB__EP0_DR2)\r
-#define USBFS_EP0_DR3_PTR ( (reg8 *) USBFS_USB__EP0_DR3)\r
-#define USBFS_EP0_DR3_REG (* (reg8 *) USBFS_USB__EP0_DR3)\r
-#define USBFS_EP0_DR4_PTR ( (reg8 *) USBFS_USB__EP0_DR4)\r
-#define USBFS_EP0_DR4_REG (* (reg8 *) USBFS_USB__EP0_DR4)\r
-#define USBFS_EP0_DR5_PTR ( (reg8 *) USBFS_USB__EP0_DR5)\r
-#define USBFS_EP0_DR5_REG (* (reg8 *) USBFS_USB__EP0_DR5)\r
-#define USBFS_EP0_DR6_PTR ( (reg8 *) USBFS_USB__EP0_DR6)\r
-#define USBFS_EP0_DR6_REG (* (reg8 *) USBFS_USB__EP0_DR6)\r
-#define USBFS_EP0_DR7_PTR ( (reg8 *) USBFS_USB__EP0_DR7)\r
-#define USBFS_EP0_DR7_REG (* (reg8 *) USBFS_USB__EP0_DR7)\r
-\r
-#define USBFS_OSCLK_DR0_PTR ( (reg8 *) USBFS_USB__OSCLK_DR0)\r
-#define USBFS_OSCLK_DR0_REG (* (reg8 *) USBFS_USB__OSCLK_DR0)\r
-#define USBFS_OSCLK_DR1_PTR ( (reg8 *) USBFS_USB__OSCLK_DR1)\r
-#define USBFS_OSCLK_DR1_REG (* (reg8 *) USBFS_USB__OSCLK_DR1)\r
-\r
-#define USBFS_PM_ACT_CFG_PTR ( (reg8 *) USBFS_USB__PM_ACT_CFG)\r
-#define USBFS_PM_ACT_CFG_REG (* (reg8 *) USBFS_USB__PM_ACT_CFG)\r
-#define USBFS_PM_STBY_CFG_PTR ( (reg8 *) USBFS_USB__PM_STBY_CFG)\r
-#define USBFS_PM_STBY_CFG_REG (* (reg8 *) USBFS_USB__PM_STBY_CFG)\r
-\r
-#define USBFS_SIE_EP_INT_EN_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_EN)\r
-#define USBFS_SIE_EP_INT_EN_REG (* (reg8 *) USBFS_USB__SIE_EP_INT_EN)\r
-#define USBFS_SIE_EP_INT_SR_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_SR)\r
-#define USBFS_SIE_EP_INT_SR_REG (* (reg8 *) USBFS_USB__SIE_EP_INT_SR)\r
-\r
-#define USBFS_SIE_EP1_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT0)\r
-#define USBFS_SIE_EP1_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP1_CNT0)\r
-#define USBFS_SIE_EP1_CNT0_IND USBFS_USB__SIE_EP1_CNT0\r
-#define USBFS_SIE_EP1_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT1)\r
-#define USBFS_SIE_EP1_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP1_CNT1)\r
+#define USBFS_EP0_DR_BASE (*(volatile USBFS_ep0_data_struct CYXDATA *) USBFS_USB__EP0_DR0)\r
+\r
+#define USBFS_OSCLK_DR0_PTR ( (reg8 *) USBFS_USB__OSCLK_DR0)\r
+#define USBFS_OSCLK_DR0_REG (*(reg8 *) USBFS_USB__OSCLK_DR0)\r
+#define USBFS_OSCLK_DR1_PTR ( (reg8 *) USBFS_USB__OSCLK_DR1)\r
+#define USBFS_OSCLK_DR1_REG (*(reg8 *) USBFS_USB__OSCLK_DR1)\r
+\r
+#define USBFS_SIE_EP_INT_EN_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_EN)\r
+#define USBFS_SIE_EP_INT_EN_REG (*(reg8 *) USBFS_USB__SIE_EP_INT_EN)\r
+#define USBFS_SIE_EP_INT_SR_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_SR)\r
+#define USBFS_SIE_EP_INT_SR_REG (*(reg8 *) USBFS_USB__SIE_EP_INT_SR)\r
+\r
+#define USBFS_SIE_EP1_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT0)\r
+#define USBFS_SIE_EP1_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP1_CNT0)\r
+#define USBFS_SIE_EP1_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT1)\r
+#define USBFS_SIE_EP1_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP1_CNT1)\r
+#define USBFS_SIE_EP1_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CR0)\r
+#define USBFS_SIE_EP1_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP1_CR0)\r
#define USBFS_SIE_EP1_CNT1_IND USBFS_USB__SIE_EP1_CNT1\r
-#define USBFS_SIE_EP1_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CR0)\r
-#define USBFS_SIE_EP1_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP1_CR0)\r
+#define USBFS_SIE_EP1_CNT0_IND USBFS_USB__SIE_EP1_CNT0\r
#define USBFS_SIE_EP1_CR0_IND USBFS_USB__SIE_EP1_CR0\r
+#define USBFS_SIE_EP_BASE (*(volatile USBFS_sie_eps_struct CYXDATA *) \\r
+ (USBFS_USB__SIE_EP1_CNT0 - sizeof(USBFS_sie_ep_struct)))\r
+\r
+#define USBFS_SIE_EP2_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT0)\r
+#define USBFS_SIE_EP2_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP2_CNT0)\r
+#define USBFS_SIE_EP2_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT1)\r
+#define USBFS_SIE_EP2_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP2_CNT1)\r
+#define USBFS_SIE_EP2_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CR0)\r
+#define USBFS_SIE_EP2_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP2_CR0)\r
+\r
+#define USBFS_SIE_EP3_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT0)\r
+#define USBFS_SIE_EP3_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP3_CNT0)\r
+#define USBFS_SIE_EP3_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT1)\r
+#define USBFS_SIE_EP3_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP3_CNT1)\r
+#define USBFS_SIE_EP3_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CR0)\r
+#define USBFS_SIE_EP3_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP3_CR0)\r
+\r
+#define USBFS_SIE_EP4_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT0)\r
+#define USBFS_SIE_EP4_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP4_CNT0)\r
+#define USBFS_SIE_EP4_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT1)\r
+#define USBFS_SIE_EP4_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP4_CNT1)\r
+#define USBFS_SIE_EP4_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CR0)\r
+#define USBFS_SIE_EP4_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP4_CR0)\r
+\r
+#define USBFS_SIE_EP5_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT0)\r
+#define USBFS_SIE_EP5_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP5_CNT0)\r
+#define USBFS_SIE_EP5_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT1)\r
+#define USBFS_SIE_EP5_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP5_CNT1)\r
+#define USBFS_SIE_EP5_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CR0)\r
+#define USBFS_SIE_EP5_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP5_CR0)\r
+\r
+#define USBFS_SIE_EP6_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT0)\r
+#define USBFS_SIE_EP6_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP6_CNT0)\r
+#define USBFS_SIE_EP6_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT1)\r
+#define USBFS_SIE_EP6_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP6_CNT1)\r
+#define USBFS_SIE_EP6_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CR0)\r
+#define USBFS_SIE_EP6_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP6_CR0)\r
+\r
+#define USBFS_SIE_EP7_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT0)\r
+#define USBFS_SIE_EP7_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP7_CNT0)\r
+#define USBFS_SIE_EP7_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT1)\r
+#define USBFS_SIE_EP7_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP7_CNT1)\r
+#define USBFS_SIE_EP7_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CR0)\r
+#define USBFS_SIE_EP7_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP7_CR0)\r
+\r
+#define USBFS_SIE_EP8_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT0)\r
+#define USBFS_SIE_EP8_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP8_CNT0)\r
+#define USBFS_SIE_EP8_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT1)\r
+#define USBFS_SIE_EP8_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP8_CNT1)\r
+#define USBFS_SIE_EP8_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CR0)\r
+#define USBFS_SIE_EP8_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP8_CR0)\r
+\r
+#define USBFS_SOF0_PTR ( (reg8 *) USBFS_USB__SOF0)\r
+#define USBFS_SOF0_REG (*(reg8 *) USBFS_USB__SOF0)\r
+#define USBFS_SOF1_PTR ( (reg8 *) USBFS_USB__SOF1)\r
+#define USBFS_SOF1_REG (*(reg8 *) USBFS_USB__SOF1)\r
+\r
+#define USBFS_USB_CLK_EN_PTR ( (reg8 *) USBFS_USB__USB_CLK_EN)\r
+#define USBFS_USB_CLK_EN_REG (*(reg8 *) USBFS_USB__USB_CLK_EN)\r
+\r
+#define USBFS_USBIO_CR0_PTR ( (reg8 *) USBFS_USB__USBIO_CR0)\r
+#define USBFS_USBIO_CR0_REG (*(reg8 *) USBFS_USB__USBIO_CR0)\r
+#define USBFS_USBIO_CR1_PTR ( (reg8 *) USBFS_USB__USBIO_CR1)\r
+#define USBFS_USBIO_CR1_REG (*(reg8 *) USBFS_USB__USBIO_CR1)\r
+\r
+#define USBFS_DYN_RECONFIG_PTR ( (reg8 *) USBFS_USB__DYN_RECONFIG)\r
+#define USBFS_DYN_RECONFIG_REG (*(reg8 *) USBFS_USB__DYN_RECONFIG)\r
+\r
+#if (CY_PSOC4)\r
+ #define USBFS_ARB_RW1_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_RA16)\r
+ #define USBFS_ARB_RW1_RA16_REG (*(reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_RA16)\r
+ #define USBFS_ARB_RW1_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_WA16)\r
+ #define USBFS_ARB_RW1_WA16_REG (*(reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_WA16)\r
+ #define USBFS_ARB_RW1_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_DR16)\r
+ #define USBFS_ARB_RW1_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_DR16)\r
+ #define USBFS_ARB_EP16_BASE (*(volatile USBFS_arb_eps_reg16_struct CYXDATA *) \\r
+ (USBFS_USB__ARB_RW1_WA16 - sizeof(USBFS_arb_ep_reg16_struct)))\r
+\r
+ #define USBFS_ARB_RW2_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW2_DR16)\r
+ #define USBFS_ARB_RW2_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW2_RA16)\r
+ #define USBFS_ARB_RW2_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW2_WA16)\r
+\r
+ #define USBFS_ARB_RW3_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW3_DR16)\r
+ #define USBFS_ARB_RW3_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW3_RA16)\r
+ #define USBFS_ARB_RW3_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW3_WA16)\r
+\r
+ #define USBFS_ARB_RW4_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW4_DR16)\r
+ #define USBFS_ARB_RW4_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW4_RA16)\r
+ #define USBFS_ARB_RW4_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW4_WA16)\r
+\r
+ #define USBFS_ARB_RW5_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW5_DR16)\r
+ #define USBFS_ARB_RW5_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW5_RA16)\r
+ #define USBFS_ARB_RW5_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW5_WA16)\r
+\r
+ #define USBFS_ARB_RW6_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW6_DR16)\r
+ #define USBFS_ARB_RW6_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW6_RA16)\r
+ #define USBFS_ARB_RW6_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW6_WA16)\r
+\r
+ #define USBFS_ARB_RW7_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW7_DR16)\r
+ #define USBFS_ARB_RW7_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW7_RA16)\r
+ #define USBFS_ARB_RW7_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW7_WA16)\r
+\r
+ #define USBFS_ARB_RW8_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW8_DR16)\r
+ #define USBFS_ARB_RW8_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW8_RA16)\r
+ #define USBFS_ARB_RW8_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW8_WA16)\r
+\r
+ #define USBFS_OSCLK_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__OSCLK_DR16)\r
+ #define USBFS_OSCLK_DR16_REG (*(reg32 *) USBFS_cy_m0s8_usb__OSCLK_DR16)\r
+\r
+ #define USBFS_SOF16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__SOF16)\r
+ #define USBFS_SOF16_REG (*(reg32 *) USBFS_cy_m0s8_usb__SOF16)\r
+ \r
+ #define USBFS_CWA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__CWA16)\r
+ #define USBFS_CWA16_REG (*(reg32 *) USBFS_cy_m0s8_usb__CWA16)\r
+\r
+ #define USBFS_DMA_THRES16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__DMA_THRES16)\r
+ #define USBFS_DMA_THRES16_REG (*(reg32 *) USBFS_cy_m0s8_usb__DMA_THRES16)\r
+\r
+ #define USBFS_USB_CLK_EN_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_CLK_EN)\r
+ #define USBFS_USB_CLK_EN_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_CLK_EN)\r
+\r
+ #define USBFS_USBIO_CR2_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USBIO_CR2)\r
+ #define USBFS_USBIO_CR2_REG (*(reg32 *) USBFS_cy_m0s8_usb__USBIO_CR2)\r
+\r
+ #define USBFS_USB_MEM ( (reg32 *) USBFS_cy_m0s8_usb__MEM_DATA0)\r
+\r
+ #define USBFS_POWER_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_POWER_CTRL)\r
+ #define USBFS_POWER_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_POWER_CTRL)\r
+\r
+ #define USBFS_CHGDET_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_CHGDET_CTRL)\r
+ #define USBFS_CHGDET_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_CHGDET_CTRL)\r
+\r
+ #define USBFS_USBIO_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_USBIO_CTRL)\r
+ #define USBFS_USBIO_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_USBIO_CTRL)\r
+\r
+ #define USBFS_FLOW_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_FLOW_CTRL)\r
+ #define USBFS_FLOW_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_FLOW_CTRL)\r
+\r
+ #define USBFS_LPM_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_LPM_CTRL)\r
+ #define USBFS_LPM_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_LPM_CTRL)\r
+\r
+ #define USBFS_LPM_STAT_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_LPM_STAT)\r
+ #define USBFS_LPM_STAT_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_LPM_STAT)\r
+\r
+ #define USBFS_PHY_CONTROL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_PHY_CONTROL)\r
+ #define USBFS_PHY_CONTROL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_PHY_CONTROL)\r
+\r
+ #define USBFS_INTR_SIE_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE)\r
+ #define USBFS_INTR_SIE_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE)\r
+\r
+ #define USBFS_INTR_SIE_SET_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_SET)\r
+ #define USBFS_INTR_SIE_SET_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_SET)\r
+\r
+ #define USBFS_INTR_SIE_MASK_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASK)\r
+ #define USBFS_INTR_SIE_MASK_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASK)\r
+\r
+ #define USBFS_INTR_SIE_MASKED_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASKED)\r
+ #define USBFS_INTR_SIE_MASKED_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASKED)\r
+\r
+ #define USBFS_INTR_LVL_SEL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_LVL_SEL)\r
+ #define USBFS_INTR_LVL_SEL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_LVL_SEL)\r
+\r
+ #define USBFS_INTR_CAUSE_HI_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_HI)\r
+ #define USBFS_INTR_CAUSE_HI_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_HI)\r
+\r
+ #define USBFS_INTR_CAUSE_LO_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_LO)\r
+ #define USBFS_INTR_CAUSE_LO_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_LO)\r
+\r
+ #define USBFS_INTR_CAUSE_MED_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_MED)\r
+ #define USBFS_INTR_CAUSE_MED_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_MED)\r
+\r
+ #define USBFS_DFT_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_DFT_CTRL)\r
+ #define USBFS_DFT_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_DFT_CTRL)\r
+\r
+ #if (USBFS_VBUS_MONITORING_ENABLE)\r
+ #if (USBFS_VBUS_POWER_PAD_ENABLE)\r
+ /* Vbus power pad pin is hard wired to P13[2] */\r
+ #define USBFS_VBUS_STATUS_REG (*(reg32 *) CYREG_GPIO_PRT13_PS)\r
+ #define USBFS_VBUS_STATUS_PTR ( (reg32 *) CYREG_GPIO_PRT13_PS)\r
+ #define USBFS_VBUS_VALID (0x04u)\r
+ #else\r
+ /* Vbus valid pin is hard wired to P0[0] */\r
+ #define USBFS_VBUS_STATUS_REG (*(reg32 *) CYREG_GPIO_PRT0_PS)\r
+ #define USBFS_VBUS_STATUS_PTR ( (reg32 *) CYREG_GPIO_PRT0_PS)\r
+ #define USBFS_VBUS_VALID (0x01u)\r
+ #endif\r
+ #endif /*(USBFS_VBUS_MONITORING_ENABLE) */\r
+\r
+ #define USBFS_BURSTEND_0_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND0_TR_OUTPUT)\r
+ #define USBFS_BURSTEND_1_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND1_TR_OUTPUT)\r
+ #define USBFS_BURSTEND_2_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND2_TR_OUTPUT)\r
+ #define USBFS_BURSTEND_3_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND3_TR_OUTPUT)\r
+ #define USBFS_BURSTEND_4_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND4_TR_OUTPUT)\r
+ #define USBFS_BURSTEND_5_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND5_TR_OUTPUT)\r
+ #define USBFS_BURSTEND_6_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND6_TR_OUTPUT)\r
+ #define USBFS_BURSTEND_7_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND7_TR_OUTPUT)\r
+ \r
+#else /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+ /* USBFS_PM_USB_CR0 */\r
+ #define USBFS_PM_USB_CR0_PTR ( (reg8 *) CYREG_PM_USB_CR0)\r
+ #define USBFS_PM_USB_CR0_REG (*(reg8 *) CYREG_PM_USB_CR0)\r
+\r
+ /* USBFS_PM_ACT/STBY_CFG */\r
+ #define USBFS_PM_ACT_CFG_PTR ( (reg8 *) USBFS_USB__PM_ACT_CFG)\r
+ #define USBFS_PM_ACT_CFG_REG (*(reg8 *) USBFS_USB__PM_ACT_CFG)\r
+ #define USBFS_PM_STBY_CFG_PTR ( (reg8 *) USBFS_USB__PM_STBY_CFG)\r
+ #define USBFS_PM_STBY_CFG_REG (*(reg8 *) USBFS_USB__PM_STBY_CFG)\r
+\r
+ #if (!CY_PSOC5LP)\r
+ #define USBFS_USBIO_CR2_PTR ( (reg8 *) USBFS_USB__USBIO_CR2)\r
+ #define USBFS_USBIO_CR2_REG (* (reg8 *) USBFS_USB__USBIO_CR2)\r
+ #endif /* (!CY_PSOC5LP) */\r
+\r
+ /* USBFS_USB_MEM - USB IP memory buffer */\r
+ #define USBFS_USB_MEM ((reg8 *) CYDEV_USB_MEM_BASE)\r
+\r
+ #if (USBFS_VBUS_MONITORING_ENABLE)\r
+ #if (USBFS_VBUS_MONITORING_INTERNAL)\r
+ #define USBFS_VBUS_STATUS_REG (*(reg8 *) USBFS_VBUS__PS)\r
+ #define USBFS_VBUS_STATUS_PTR ( (reg8 *) USBFS_VBUS__PS)\r
+ #define USBFS_VBUS_VALID (USBFS_VBUS__MASK)\r
+ #else\r
+ #define USBFS_VBUS_STATUS_REG (*(reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG)\r
+ #define USBFS_VBUS_STATUS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG)\r
+ #define USBFS_VBUS_VALID (USBFS_Vbus_ps_sts_sts_reg__MASK)\r
+ #endif /* (USBFS_VBUS_MONITORING_INTERNAL) */\r
+ #endif /*(USBFS_VBUS_MONITORING_ENABLE) */\r
+#endif /* (CY_PSOC4) */\r
+\r
+\r
+/***************************************\r
+* Interrupt source constants\r
+***************************************/\r
+\r
+#define USBFS_DP_INTC_PRIORITY USBFS_dp_int__INTC_PRIOR_NUM\r
+#define USBFS_DP_INTC_VECT_NUM USBFS_dp_int__INTC_NUMBER\r
+\r
+#if (CY_PSOC4)\r
+ #define USBFS_DMA_AUTO_INTR_PRIO (0u)\r
+ \r
+ #define USBFS_INTR_HI_PRIORITY USBFS_high_int__INTC_PRIOR_NUM\r
+ #define USBFS_INTR_HI_VECT_NUM USBFS_high_int__INTC_NUMBER\r
+\r
+ #define USBFS_INTR_MED_PRIORITY USBFS_med_int__INTC_PRIOR_NUM\r
+ #define USBFS_INTR_MED_VECT_NUM USBFS_med_int__INTC_NUMBER\r
+\r
+ #define USBFS_INTR_LO_PRIORITY USBFS_lo_int__INTC_PRIOR_NUM\r
+ #define USBFS_INTR_LO_VECT_NUM USBFS_lo_int__INTC_NUMBER\r
+\r
+ /* Interrupt sources in USBFS_isrCallbacks[] table */\r
+ #define USBFS_SOF_INTR_NUM (0u)\r
+ #define USBFS_BUS_RESET_INT_NUM (1u)\r
+ #define USBFS_EP0_INTR_NUM (2u)\r
+ #define USBFS_LPM_INTR_NUM (3u)\r
+ #define USBFS_ARB_EP_INTR_NUM (4u)\r
+ #define USBFS_EP1_INTR_NUM (5u)\r
+ #define USBFS_EP2_INTR_NUM (6u)\r
+ #define USBFS_EP3_INTR_NUM (7u)\r
+ #define USBFS_EP4_INTR_NUM (8u)\r
+ #define USBFS_EP5_INTR_NUM (9u)\r
+ #define USBFS_EP6_INTR_NUM (10u)\r
+ #define USBFS_EP7_INTR_NUM (11u)\r
+ #define USBFS_EP8_INTR_NUM (12u)\r
+\r
+#else\r
+ #define USBFS_BUS_RESET_PRIOR USBFS_bus_reset__INTC_PRIOR_NUM\r
+ #define USBFS_BUS_RESET_MASK USBFS_bus_reset__INTC_MASK\r
+ #define USBFS_BUS_RESET_VECT_NUM USBFS_bus_reset__INTC_NUMBER\r
+\r
+ #define USBFS_SOF_PRIOR USBFS_sof_int__INTC_PRIOR_NUM\r
+ #define USBFS_SOF_MASK USBFS_sof_int__INTC_MASK\r
+ #define USBFS_SOF_VECT_NUM USBFS_sof_int__INTC_NUMBER\r
+\r
+ #define USBFS_EP_0_PRIOR USBFS_ep_0__INTC_PRIOR_NUM\r
+ #define USBFS_EP_0_MASK USBFS_ep_0__INTC_MASK\r
+ #define USBFS_EP_0_VECT_NUM USBFS_ep_0__INTC_NUMBER\r
+\r
+ #define USBFS_EP_1_PRIOR USBFS_ep_1__INTC_PRIOR_NUM\r
+ #define USBFS_EP_1_MASK USBFS_ep_1__INTC_MASK\r
+ #define USBFS_EP_1_VECT_NUM USBFS_ep_1__INTC_NUMBER\r
+\r
+ #define USBFS_EP_2_PRIOR USBFS_ep_2__INTC_PRIOR_NUM\r
+ #define USBFS_EP_2_MASK USBFS_ep_2__INTC_MASK\r
+ #define USBFS_EP_2_VECT_NUM USBFS_ep_2__INTC_NUMBER\r
+\r
+ #define USBFS_EP_3_PRIOR USBFS_ep_3__INTC_PRIOR_NUM\r
+ #define USBFS_EP_3_MASK USBFS_ep_3__INTC_MASK\r
+ #define USBFS_EP_3_VECT_NUM USBFS_ep_3__INTC_NUMBER\r
+\r
+ #define USBFS_EP_4_PRIOR USBFS_ep_4__INTC_PRIOR_NUM\r
+ #define USBFS_EP_4_MASK USBFS_ep_4__INTC_MASK\r
+ #define USBFS_EP_4_VECT_NUM USBFS_ep_4__INTC_NUMBER\r
+\r
+ #define USBFS_EP_5_PRIOR USBFS_ep_5__INTC_PRIOR_NUM\r
+ #define USBFS_EP_5_MASK USBFS_ep_5__INTC_MASK\r
+ #define USBFS_EP_5_VECT_NUM USBFS_ep_5__INTC_NUMBER\r
+\r
+ #define USBFS_EP_6_PRIOR USBFS_ep_6__INTC_PRIOR_NUM\r
+ #define USBFS_EP_6_MASK USBFS_ep_6__INTC_MASK\r
+ #define USBFS_EP_6_VECT_NUM USBFS_ep_6__INTC_NUMBER\r
+\r
+ #define USBFS_EP_7_PRIOR USBFS_ep_7__INTC_PRIOR_NUM\r
+ #define USBFS_EP_7_MASK USBFS_ep_7__INTC_MASK\r
+ #define USBFS_EP_7_VECT_NUM USBFS_ep_7__INTC_NUMBER\r
+\r
+ #define USBFS_EP_8_PRIOR USBFS_ep_8__INTC_PRIOR_NUM\r
+ #define USBFS_EP_8_MASK USBFS_ep_8__INTC_MASK\r
+ #define USBFS_EP_8_VECT_NUM USBFS_ep_8__INTC_NUMBER\r
+\r
+ /* Set ARB ISR priority 0 to be highest for all EPX ISRs. */\r
+ #define USBFS_ARB_PRIOR (0u)\r
+ #define USBFS_ARB_MASK USBFS_arb_int__INTC_MASK\r
+ #define USBFS_ARB_VECT_NUM USBFS_arb_int__INTC_NUMBER\r
+#endif /* (CY_PSOC4) */\r
+\r
+\r
+/***************************************\r
+* Endpoint 0 offsets (Table 9-2)\r
+***************************************/\r
+#define USBFS_bmRequestTypeReg USBFS_EP0_DR_BASE.epData[0u]\r
+#define USBFS_bRequestReg USBFS_EP0_DR_BASE.epData[1u]\r
+#define USBFS_wValueLoReg USBFS_EP0_DR_BASE.epData[2u]\r
+#define USBFS_wValueHiReg USBFS_EP0_DR_BASE.epData[3u]\r
+#define USBFS_wIndexLoReg USBFS_EP0_DR_BASE.epData[4u]\r
+#define USBFS_wIndexHiReg USBFS_EP0_DR_BASE.epData[5u]\r
+#define USBFS_wLengthLoReg USBFS_EP0_DR_BASE.epData[6u]\r
+#define USBFS_wLengthHiReg USBFS_EP0_DR_BASE.epData[7u]\r
+\r
+/* Compatibility defines */\r
+#define USBFS_lengthLoReg USBFS_EP0_DR_BASE.epData[6u]\r
+#define USBFS_lengthHiReg USBFS_EP0_DR_BASE.epData[7u]\r
+\r
+\r
+/***************************************\r
+* Register Constants\r
+***************************************/\r
+\r
+#define USBFS_3500MV (3500u)\r
+#if (CY_PSOC4)\r
+ #define USBFS_VDDD_MV (CYDEV_VBUS_MV)\r
+#else\r
+ #define USBFS_VDDD_MV (CYDEV_VDDD_MV)\r
+#endif /* (CY_PSOC4) */\r
+\r
+\r
+/* USBFS_USB_CLK */\r
+#define USBFS_USB_CLK_CSR_CLK_EN_POS (0u)\r
+#define USBFS_USB_CLK_CSR_CLK_EN ((uint8) ((uint8) 0x1u << USBFS_USB_CLK_CSR_CLK_EN_POS))\r
+#define USBFS_USB_CLK_ENABLE (USBFS_USB_CLK_CSR_CLK_EN)\r
+\r
+/* USBFS_CR0 */\r
+#define USBFS_CR0_DEVICE_ADDRESS_POS (0u)\r
+#define USBFS_CR0_ENABLE_POS (7u)\r
+#define USBFS_CR0_DEVICE_ADDRESS_MASK ((uint8) ((uint8) 0x7Fu << USBFS_CR0_DEVICE_ADDRESS_POS))\r
+#define USBFS_CR0_ENABLE ((uint8) ((uint8) 0x01u << USBFS_CR0_ENABLE_POS))\r
+\r
+\r
+/* USBFS_CR1 */\r
+#define USBFS_CR1_REG_ENABLE_POS (0u)\r
+#define USBFS_CR1_ENABLE_LOCK_POS (1u)\r
+#define USBFS_CR1_BUS_ACTIVITY_POS (2u)\r
+#define USBFS_CR1_TRIM_OFFSET_MSB_POS (3u)\r
+#define USBFS_CR1_REG_ENABLE ((uint8) ((uint8) 0x1u << USBFS_CR1_REG_ENABLE_POS))\r
+#define USBFS_CR1_ENABLE_LOCK ((uint8) ((uint8) 0x1u << USBFS_CR1_ENABLE_LOCK_POS))\r
+#define USBFS_CR1_BUS_ACTIVITY ((uint8) ((uint8) 0x1u << USBFS_CR1_BUS_ACTIVITY_POS))\r
+#define USBFS_CR1_TRIM_OFFSET_MSB ((uint8) ((uint8) 0x1u << USBFS_CR1_TRIM_OFFSET_MSB_POS))\r
+\r
+/* USBFS_EPX_CNT */\r
+#define USBFS_EP0_CNT_DATA_TOGGLE (0x80u)\r
+#define USBFS_EPX_CNT_DATA_TOGGLE (0x80u)\r
+#define USBFS_EPX_CNT0_MASK (0x0Fu)\r
+#define USBFS_EPX_CNTX_MSB_MASK (0x07u)\r
+#define USBFS_EPX_CNTX_ADDR_SHIFT (0x04u)\r
+#define USBFS_EPX_CNTX_ADDR_OFFSET (0x10u)\r
+#define USBFS_EPX_CNTX_CRC_COUNT (0x02u)\r
+#define USBFS_EPX_DATA_BUF_MAX (512u)\r
+\r
+/* USBFS_USBIO_CR0 */\r
+\r
+#define USBFS_USBIO_CR0_TEN (0x80u)\r
+#define USBFS_USBIO_CR0_TSE0 (0x40u)\r
+#define USBFS_USBIO_CR0_TD (0x20u)\r
+#define USBFS_USBIO_CR0_RD (0x01u)\r
+\r
+/* USBFS_USBIO_CR1 */\r
+#define USBFS_USBIO_CR1_DM0_POS (0u)\r
+#define USBFS_USBIO_CR1_DP0_POS (1u)\r
+#define USBFS_USBIO_CR1_USBPUEN_POS (2u)\r
+#define USBFS_USBIO_CR1_IOMODE_POS (5u)\r
+#define USBFS_USBIO_CR1_DM0 ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_DM0_POS))\r
+#define USBFS_USBIO_CR1_DP0 ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_DP0_POS))\r
+#define USBFS_USBIO_CR1_USBPUEN ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_USBPUEN_POS))\r
+#define USBFS_USBIO_CR1_IOMODE ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_IOMODE_POS))\r
+\r
+/* USBFS_FASTCLK_IMO_CR */\r
+#define USBFS_FASTCLK_IMO_CR_USBCLK_ON (0x40u)\r
+#define USBFS_FASTCLK_IMO_CR_XCLKEN (0x20u)\r
+#define USBFS_FASTCLK_IMO_CR_FX2ON (0x10u)\r
\r
-#define USBFS_SIE_EP2_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT0)\r
-#define USBFS_SIE_EP2_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP2_CNT0)\r
-#define USBFS_SIE_EP2_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT1)\r
-#define USBFS_SIE_EP2_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP2_CNT1)\r
-#define USBFS_SIE_EP2_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CR0)\r
-#define USBFS_SIE_EP2_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP2_CR0)\r
-\r
-#define USBFS_SIE_EP3_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT0)\r
-#define USBFS_SIE_EP3_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP3_CNT0)\r
-#define USBFS_SIE_EP3_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT1)\r
-#define USBFS_SIE_EP3_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP3_CNT1)\r
-#define USBFS_SIE_EP3_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CR0)\r
-#define USBFS_SIE_EP3_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP3_CR0)\r
-\r
-#define USBFS_SIE_EP4_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT0)\r
-#define USBFS_SIE_EP4_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP4_CNT0)\r
-#define USBFS_SIE_EP4_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT1)\r
-#define USBFS_SIE_EP4_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP4_CNT1)\r
-#define USBFS_SIE_EP4_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CR0)\r
-#define USBFS_SIE_EP4_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP4_CR0)\r
-\r
-#define USBFS_SIE_EP5_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT0)\r
-#define USBFS_SIE_EP5_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP5_CNT0)\r
-#define USBFS_SIE_EP5_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT1)\r
-#define USBFS_SIE_EP5_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP5_CNT1)\r
-#define USBFS_SIE_EP5_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CR0)\r
-#define USBFS_SIE_EP5_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP5_CR0)\r
-\r
-#define USBFS_SIE_EP6_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT0)\r
-#define USBFS_SIE_EP6_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP6_CNT0)\r
-#define USBFS_SIE_EP6_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT1)\r
-#define USBFS_SIE_EP6_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP6_CNT1)\r
-#define USBFS_SIE_EP6_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CR0)\r
-#define USBFS_SIE_EP6_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP6_CR0)\r
-\r
-#define USBFS_SIE_EP7_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT0)\r
-#define USBFS_SIE_EP7_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP7_CNT0)\r
-#define USBFS_SIE_EP7_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT1)\r
-#define USBFS_SIE_EP7_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP7_CNT1)\r
-#define USBFS_SIE_EP7_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CR0)\r
-#define USBFS_SIE_EP7_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP7_CR0)\r
-\r
-#define USBFS_SIE_EP8_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT0)\r
-#define USBFS_SIE_EP8_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP8_CNT0)\r
-#define USBFS_SIE_EP8_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT1)\r
-#define USBFS_SIE_EP8_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP8_CNT1)\r
-#define USBFS_SIE_EP8_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CR0)\r
-#define USBFS_SIE_EP8_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP8_CR0)\r
-\r
-#define USBFS_SOF0_PTR ( (reg8 *) USBFS_USB__SOF0)\r
-#define USBFS_SOF0_REG (* (reg8 *) USBFS_USB__SOF0)\r
-#define USBFS_SOF1_PTR ( (reg8 *) USBFS_USB__SOF1)\r
-#define USBFS_SOF1_REG (* (reg8 *) USBFS_USB__SOF1)\r
-\r
-#define USBFS_USB_CLK_EN_PTR ( (reg8 *) USBFS_USB__USB_CLK_EN)\r
-#define USBFS_USB_CLK_EN_REG (* (reg8 *) USBFS_USB__USB_CLK_EN)\r
-\r
-#define USBFS_USBIO_CR0_PTR ( (reg8 *) USBFS_USB__USBIO_CR0)\r
-#define USBFS_USBIO_CR0_REG (* (reg8 *) USBFS_USB__USBIO_CR0)\r
-#define USBFS_USBIO_CR1_PTR ( (reg8 *) USBFS_USB__USBIO_CR1)\r
-#define USBFS_USBIO_CR1_REG (* (reg8 *) USBFS_USB__USBIO_CR1)\r
-#if(!CY_PSOC5LP)\r
- #define USBFS_USBIO_CR2_PTR ( (reg8 *) USBFS_USB__USBIO_CR2)\r
- #define USBFS_USBIO_CR2_REG (* (reg8 *) USBFS_USB__USBIO_CR2)\r
-#endif /* CY_PSOC5LP */\r
-\r
-#define USBFS_DIE_ID CYDEV_FLSHID_CUST_TABLES_BASE\r
-\r
-#define USBFS_PM_USB_CR0_PTR ( (reg8 *) CYREG_PM_USB_CR0)\r
-#define USBFS_PM_USB_CR0_REG (* (reg8 *) CYREG_PM_USB_CR0)\r
-#define USBFS_DYN_RECONFIG_PTR ( (reg8 *) USBFS_USB__DYN_RECONFIG)\r
-#define USBFS_DYN_RECONFIG_REG (* (reg8 *) USBFS_USB__DYN_RECONFIG)\r
-\r
-#define USBFS_DM_INP_DIS_PTR ( (reg8 *) USBFS_Dm__INP_DIS)\r
-#define USBFS_DM_INP_DIS_REG (* (reg8 *) USBFS_Dm__INP_DIS)\r
-#define USBFS_DP_INP_DIS_PTR ( (reg8 *) USBFS_Dp__INP_DIS)\r
-#define USBFS_DP_INP_DIS_REG (* (reg8 *) USBFS_Dp__INP_DIS)\r
-#define USBFS_DP_INTSTAT_PTR ( (reg8 *) USBFS_Dp__INTSTAT)\r
-#define USBFS_DP_INTSTAT_REG (* (reg8 *) USBFS_Dp__INTSTAT)\r
-\r
-#if (USBFS_MON_VBUS == 1u)\r
- #if (USBFS_EXTERN_VBUS == 0u)\r
- #define USBFS_VBUS_DR_PTR ( (reg8 *) USBFS_VBUS__DR)\r
- #define USBFS_VBUS_DR_REG (* (reg8 *) USBFS_VBUS__DR)\r
- #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_VBUS__PS)\r
- #define USBFS_VBUS_PS_REG (* (reg8 *) USBFS_VBUS__PS)\r
- #define USBFS_VBUS_MASK USBFS_VBUS__MASK\r
- #else\r
- #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG )\r
- #define USBFS_VBUS_MASK (0x01u)\r
- #endif /* USBFS_EXTERN_VBUS == 0u */\r
-#endif /* USBFS_MON_VBUS */\r
-\r
-/* Renamed Registers for backward compatibility.\r
-* Should not be used in new designs.\r
+/* USBFS_ARB_EPX_CFG */\r
+#define USBFS_ARB_EPX_CFG_IN_DATA_RDY_POS (0u)\r
+#define USBFS_ARB_EPX_CFG_DMA_REQ_POS (1u)\r
+#define USBFS_ARB_EPX_CFG_CRC_BYPASS_POS (2u)\r
+#define USBFS_ARB_EPX_CFG_RESET_POS (3u)\r
+#define USBFS_ARB_EPX_CFG_IN_DATA_RDY ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_IN_DATA_RDY_POS))\r
+#define USBFS_ARB_EPX_CFG_DMA_REQ ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_DMA_REQ_POS))\r
+#define USBFS_ARB_EPX_CFG_CRC_BYPASS ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_CRC_BYPASS_POS))\r
+#define USBFS_ARB_EPX_CFG_RESET ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_RESET_POS))\r
+\r
+/* USBFS_ARB_EPX_INT / SR */\r
+#define USBFS_ARB_EPX_INT_IN_BUF_FULL_POS (0u)\r
+#define USBFS_ARB_EPX_INT_DMA_GNT_POS (1u)\r
+#define USBFS_ARB_EPX_INT_BUF_OVER_POS (2u)\r
+#define USBFS_ARB_EPX_INT_BUF_UNDER_POS (3u)\r
+#define USBFS_ARB_EPX_INT_ERR_INT_POS (4u)\r
+#define USBFS_ARB_EPX_INT_IN_BUF_FULL ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_IN_BUF_FULL_POS))\r
+#define USBFS_ARB_EPX_INT_DMA_GNT ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_DMA_GNT_POS))\r
+#define USBFS_ARB_EPX_INT_BUF_OVER ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_BUF_OVER_POS))\r
+#define USBFS_ARB_EPX_INT_BUF_UNDER ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_BUF_UNDER_POS))\r
+#define USBFS_ARB_EPX_INT_ERR_INT ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_ERR_INT_POS))\r
+\r
+#if (CY_PSOC4)\r
+#define USBFS_ARB_EPX_INT_DMA_TERMIN_POS (5u)\r
+#define USBFS_ARB_EPX_INT_DMA_TERMIN ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_DMA_TERMIN_POS))\r
+#endif /* (CY_PSOC4) */\r
+\r
+/* Common arbiter interrupt sources for all PSoC devices. */\r
+#define USBFS_ARB_EPX_INT_COMMON (USBFS_ARB_EPX_INT_IN_BUF_FULL | \\r
+ USBFS_ARB_EPX_INT_DMA_GNT | \\r
+ USBFS_ARB_EPX_INT_BUF_OVER | \\r
+ USBFS_ARB_EPX_INT_BUF_UNDER | \\r
+ USBFS_ARB_EPX_INT_ERR_INT)\r
+\r
+#if (CY_PSOC4)\r
+ #define USBFS_ARB_EPX_INT_ALL (USBFS_ARB_EPX_INT_COMMON | USBFS_ARB_EPX_INT_DMA_TERMIN)\r
+#else\r
+ #define USBFS_ARB_EPX_INT_ALL (USBFS_ARB_EPX_INT_COMMON)\r
+#endif /* (CY_PSOC4) */\r
+\r
+/* USBFS_ARB_CFG */\r
+#define USBFS_ARB_CFG_AUTO_MEM_POS (4u)\r
+#define USBFS_ARB_CFG_DMA_CFG_POS (5u)\r
+#define USBFS_ARB_CFG_CFG_CMP_POS (7u)\r
+#define USBFS_ARB_CFG_AUTO_MEM ((uint8) ((uint8) 0x1u << USBFS_ARB_CFG_AUTO_MEM_POS))\r
+#define USBFS_ARB_CFG_DMA_CFG_MASK ((uint8) ((uint8) 0x3u << USBFS_ARB_CFG_DMA_CFG_POS))\r
+#define USBFS_ARB_CFG_DMA_CFG_NONE ((uint8) ((uint8) 0x0u << USBFS_ARB_CFG_DMA_CFG_POS))\r
+#define USBFS_ARB_CFG_DMA_CFG_MANUAL ((uint8) ((uint8) 0x1u << USBFS_ARB_CFG_DMA_CFG_POS))\r
+#define USBFS_ARB_CFG_DMA_CFG_AUTO ((uint8) ((uint8) 0x2u << USBFS_ARB_CFG_DMA_CFG_POS))\r
+#define USBFS_ARB_CFG_CFG_CMP ((uint8) ((uint8) 0x1u << USBFS_ARB_CFG_CFG_CMP_POS))\r
+\r
+/* USBFS_DYN_RECONFIG */\r
+#define USBFS_DYN_RECONFIG_EP_SHIFT (1u)\r
+#define USBFS_DYN_RECONFIG_ENABLE_POS (0u)\r
+#define USBFS_DYN_RECONFIG_EPNO_POS (1u)\r
+#define USBFS_DYN_RECONFIG_RDY_STS_POS (4u)\r
+#define USBFS_DYN_RECONFIG_ENABLE ((uint8) ((uint8) 0x1u << USBFS_DYN_RECONFIG_ENABLE_POS))\r
+#define USBFS_DYN_RECONFIG_EPNO_MASK ((uint8) ((uint8) 0x7u << USBFS_DYN_RECONFIG_EPNO_POS))\r
+#define USBFS_DYN_RECONFIG_RDY_STS ((uint8) ((uint8) 0x1u << USBFS_DYN_RECONFIG_RDY_STS_POS))\r
+\r
+/* USBFS_ARB_INT */\r
+#define USBFS_ARB_INT_EP1_INTR_POS (0u) /* [0] Interrupt for USB EP1 */\r
+#define USBFS_ARB_INT_EP2_INTR_POS (1u) /* [1] Interrupt for USB EP2 */\r
+#define USBFS_ARB_INT_EP3_INTR_POS (2u) /* [2] Interrupt for USB EP3 */\r
+#define USBFS_ARB_INT_EP4_INTR_POS (3u) /* [3] Interrupt for USB EP4 */\r
+#define USBFS_ARB_INT_EP5_INTR_POS (4u) /* [4] Interrupt for USB EP5 */\r
+#define USBFS_ARB_INT_EP6_INTR_POS (5u) /* [5] Interrupt for USB EP6 */\r
+#define USBFS_ARB_INT_EP7_INTR_POS (6u) /* [6] Interrupt for USB EP7 */\r
+#define USBFS_ARB_INT_EP8_INTR_POS (7u) /* [7] Interrupt for USB EP8 */\r
+#define USBFS_ARB_INT_EP1_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP1_INTR_POS))\r
+#define USBFS_ARB_INT_EP2_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP2_INTR_POS))\r
+#define USBFS_ARB_INT_EP3_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP3_INTR_POS))\r
+#define USBFS_ARB_INT_EP4_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP4_INTR_POS))\r
+#define USBFS_ARB_INT_EP5_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP5_INTR_POS))\r
+#define USBFS_ARB_INT_EP6_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP6_INTR_POS))\r
+#define USBFS_ARB_INT_EP7_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP7_INTR_POS))\r
+#define USBFS_ARB_INT_EP8_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP8_INTR_POS))\r
+\r
+/* USBFS_SIE_INT */\r
+#define USBFS_SIE_INT_EP1_INTR_POS (0u) /* [0] Interrupt for USB EP1 */\r
+#define USBFS_SIE_INT_EP2_INTR_POS (1u) /* [1] Interrupt for USB EP2 */\r
+#define USBFS_SIE_INT_EP3_INTR_POS (2u) /* [2] Interrupt for USB EP3 */\r
+#define USBFS_SIE_INT_EP4_INTR_POS (3u) /* [3] Interrupt for USB EP4 */\r
+#define USBFS_SIE_INT_EP5_INTR_POS (4u) /* [4] Interrupt for USB EP5 */\r
+#define USBFS_SIE_INT_EP6_INTR_POS (5u) /* [5] Interrupt for USB EP6 */\r
+#define USBFS_SIE_INT_EP7_INTR_POS (6u) /* [6] Interrupt for USB EP7 */\r
+#define USBFS_SIE_INT_EP8_INTR_POS (7u) /* [7] Interrupt for USB EP8 */\r
+#define USBFS_SIE_INT_EP1_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP1_INTR_POS))\r
+#define USBFS_SIE_INT_EP2_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP2_INTR_POS))\r
+#define USBFS_SIE_INT_EP3_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP3_INTR_POS))\r
+#define USBFS_SIE_INT_EP4_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP4_INTR_POS))\r
+#define USBFS_SIE_INT_EP5_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP5_INTR_POS))\r
+#define USBFS_SIE_INT_EP6_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP6_INTR_POS))\r
+#define USBFS_SIE_INT_EP7_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP7_INTR_POS))\r
+#define USBFS_SIE_INT_EP8_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP8_INTR_POS))\r
+\r
+#if (CY_PSOC4)\r
+ /* USBFS_POWER_CTRL_REG */\r
+ #define USBFS_POWER_CTRL_VBUS_VALID_OVR_POS (0u) /* [0] */\r
+ #define USBFS_POWER_CTRL_SUSPEND_POS (2u) /* [1] */\r
+ #define USBFS_POWER_CTRL_SUSPEND_DEL_POS (3u) /* [3] */\r
+ #define USBFS_POWER_CTRL_ISOLATE_POS (4u) /* [4] */\r
+ #define USBFS_POWER_CTRL_CHDET_PWR_CTL_POS (5u) /* [5] */\r
+ #define USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN_POS (25u) /* [25] */\r
+ #define USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN_POS (26u) /* [26] */\r
+ #define USBFS_POWER_CTRL_ENABLE_RCVR_POS (27u) /* [27] */\r
+ #define USBFS_POWER_CTRL_ENABLE_DPO_POS (28u) /* [28] */\r
+ #define USBFS_POWER_CTRL_ENABLE_DMO_POS (29u) /* [29] */\r
+ #define USBFS_POWER_CTRL_ENABLE_CHGDET_POS (30u) /* [30] */\r
+ #define USBFS_POWER_CTRL_ENABLE_POS (31u) /* [31] */\r
+ #define USBFS_POWER_CTRL_VBUS_VALID_OVR_MASK ((uint32) 0x03u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS)\r
+ #define USBFS_POWER_CTRL_VBUS_VALID_OVR_0 ((uint32) 0x00u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS)\r
+ #define USBFS_POWER_CTRL_VBUS_VALID_OVR_1 ((uint32) 0x01u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS)\r
+ #define USBFS_POWER_CTRL_VBUS_VALID_OVR_GPIO ((uint32) 0x02u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS)\r
+ #define USBFS_POWER_CTRL_VBUS_VALID_OVR_PHY ((uint32) 0x03u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS)\r
+ #define USBFS_POWER_CTRL_SUSPEND ((uint32) 0x01u << USBFS_POWER_CTRL_SUSPEND_POS)\r
+ #define USBFS_POWER_CTRL_SUSPEND_DEL ((uint32) 0x01u << USBFS_POWER_CTRL_SUSPEND_DEL_POS)\r
+ #define USBFS_POWER_CTRL_ISOLATE ((uint32) 0x01u << USBFS_POWER_CTRL_ISOLATE_POS)\r
+ #define USBFS_POWER_CTRL_CHDET_PWR_CTL_MASK ((uint32) 0x03u << USBFS_POWER_CTRL_CHDET_PWR_CTL_POS)\r
+ #define USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN_POS)\r
+ #define USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN_POS)\r
+ #define USBFS_POWER_CTRL_ENABLE_RCVR ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_RCVR_POS)\r
+ #define USBFS_POWER_CTRL_ENABLE_DPO ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_DPO_POS)\r
+ #define USBFS_POWER_CTRL_ENABLE_DMO ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_DMO_POS)\r
+ #define USBFS_POWER_CTRL_ENABLE_CHGDET ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_CHGDET_POS)\r
+ #define USBFS_POWER_CTRL_ENABLE ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_POS)\r
+\r
+ /* USBFS_CHGDET_CTRL_REG */\r
+ #define USBFS_CHGDET_CTRL_COMP_DP_POS (0u) /* [0] */\r
+ #define USBFS_CHGDET_CTRL_COMP_DM_POS (1u) /* [1] */\r
+ #define USBFS_CHGDET_CTRL_COMP_EN_POS (2u) /* [2] */\r
+ #define USBFS_CHGDET_CTRL_REF_DP_POS (3u) /* [3] */\r
+ #define USBFS_CHGDET_CTRL_REF_DM_POS (4u) /* [4] */\r
+ #define USBFS_CHGDET_CTRL_REF_EN_POS (5u) /* [5] */\r
+ #define USBFS_CHGDET_CTRL_DCD_SRC_EN_POS (6u) /* [6] */\r
+ #define USBFS_CHGDET_CTRL_ADFT_CTRL_POS (12u) /* [12] */\r
+ #define USBFS_CHGDET_CTRL_COMP_OUT_POS (31u) /* [31] */\r
+ #define USBFS_CHGDET_CTRL_COMP_DP ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_DP_POS)\r
+ #define USBFS_CHGDET_CTRL_COMP_DM ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_DM_POS)\r
+ #define USBFS_CHGDET_CTRL_COMP_EN ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_EN_POS)\r
+ #define USBFS_CHGDET_CTRL_REF_DP ((uint32) 0x01u << USBFS_CHGDET_CTRL_REF_DP_POS)\r
+ #define USBFS_CHGDET_CTRL_REF_DM ((uint32) 0x01u << USBFS_CHGDET_CTRL_REF_DM_POS)\r
+ #define USBFS_CHGDET_CTRL_REF_EN ((uint32) 0x01u << USBFS_CHGDET_CTRL_REF_EN_POS)\r
+ #define USBFS_CHGDET_CTRL_DCD_SRC_EN ((uint32) 0x01u << USBFS_CHGDET_CTRL_DCD_SRC_EN_POS)\r
+ #define USBFS_CHGDET_CTRL_ADFT_CTRL_MASK ((uint32) 0x03u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS)\r
+ #define USBFS_CHGDET_CTRL_ADFT_CTRL_NORMAL ((uint32) 0x00u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS)\r
+ #define USBFS_CHGDET_CTRL_ADFT_CTRL_VBG ((uint32) 0x01u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS)\r
+ #define USBFS_CHGDET_CTRL_ADFT_CTRL_DONTUSE ((uint32) 0x02u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS)\r
+ #define USBFS_CHGDET_CTRL_ADFT_CTRL_ADFTIN ((uint32) 0x03u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS)\r
+ #define USBFS_CHGDET_CTRL_COMP_OUT ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_OUT_POS)\r
+\r
+ /* USBFS_LPM_CTRL */\r
+ #define USBFS_LPM_CTRL_LPM_EN_POS (0u)\r
+ #define USBFS_LPM_CTRL_LPM_ACK_RESP_POS (1u)\r
+ #define USBFS_LPM_CTRL_NYET_EN_POS (2u)\r
+ #define USBFS_LPM_CTRL_SUB_RESP_POS (4u)\r
+ #define USBFS_LPM_CTRL_LPM_EN ((uint32) 0x01u << USBFS_LPM_CTRL_LPM_EN_POS)\r
+ #define USBFS_LPM_CTRL_LPM_ACK_RESP ((uint32) 0x01u << USBFS_LPM_CTRL_LPM_ACK_RESP_POS)\r
+ #define USBFS_LPM_CTRL_NYET_EN ((uint32) 0x01u << USBFS_LPM_CTRL_NYET_EN_POS)\r
+ #define USBFS_LPM_CTRL_ACK_NYET_MASK ((uint32) 0x03u << USBFS_LPM_CTRL_LPM_ACK_RESP_POS)\r
+ #define USBFS_LPM_CTRL_SUB_RESP ((uint32) 0x01u << USBFS_LPM_CTRL_SUB_RESP_POS)\r
+\r
+ #define USBFS_LPM_STAT_LPM_BESL_POS (0u)\r
+ #define USBFS_LPM_STAT_LPM_REMOTE_WAKE_POS (4u)\r
+ #define USBFS_LPM_STAT_LPM_BESL_MASK ((uint32) 0x0Fu << USBFS_LPM_STAT_LPM_BESL_POS)\r
+ #define USBFS_LPM_STAT_LPM_REMOTE_WAKE ((uint32) 0x01u << USBFS_LPM_STAT_LPM_REMOTE_WAKE_POS)\r
+\r
+ /* USBFS_INTR_SIE */\r
+ #define USBFS_INTR_SIE_SOF_INTR_POS (0u) /* [0] Interrupt for USB SOF */\r
+ #define USBFS_INTR_SIE_BUS_RESET_INTR_POS (1u) /* [1] Interrupt for BUS RESET */\r
+ #define USBFS_INTR_SIE_EP0_INTR_POS (2u) /* [2] Interrupt for EP0 */\r
+ #define USBFS_INTR_SIE_LPM_INTR_POS (3u) /* [3] Interrupt for LPM */\r
+ #define USBFS_INTR_SIE_RESUME_INTR_POS (4u) /* [4] Interrupt for RESUME (not used by component) */\r
+ #define USBFS_INTR_SIE_SOF_INTR ((uint32) 0x01u << USBFS_INTR_SIE_SOF_INTR_POS)\r
+ #define USBFS_INTR_SIE_BUS_RESET_INTR ((uint32) 0x01u << USBFS_INTR_SIE_BUS_RESET_INTR_POS)\r
+ #define USBFS_INTR_SIE_EP0_INTR ((uint32) 0x01u << USBFS_INTR_SIE_EP0_INTR_POS)\r
+ #define USBFS_INTR_SIE_LPM_INTR ((uint32) 0x01u << USBFS_INTR_SIE_LPM_INTR_POS)\r
+ #define USBFS_INTR_SIE_RESUME_INTR ((uint32) 0x01u << USBFS_INTR_SIE_RESUME_INTR_POS)\r
+\r
+ /* USBFS_INTR_CAUSE_LO, MED and HI */\r
+ #define USBFS_INTR_CAUSE_SOF_INTR_POS (0u) /* [0] Interrupt status for USB SOF */\r
+ #define USBFS_INTR_CAUSE_BUS_RESET_INTR_POS (1u) /* [1] Interrupt status for USB BUS RSET */\r
+ #define USBFS_INTR_CAUSE_EP0_INTR_POS (2u) /* [2] Interrupt status for USB EP0 */\r
+ #define USBFS_INTR_CAUSE_LPM_INTR_POS (3u) /* [3] Interrupt status for USB LPM */\r
+ #define USBFS_INTR_CAUSE_RESUME_INTR_POS (4u) /* [4] Interrupt status for USB RESUME */\r
+ #define USBFS_INTR_CAUSE_ARB_INTR_POS (7u) /* [7] Interrupt status for USB ARB */\r
+ #define USBFS_INTR_CAUSE_EP1_INTR_POS (8u) /* [8] Interrupt status for USB EP1 */\r
+ #define USBFS_INTR_CAUSE_EP2_INTR_POS (9u) /* [9] Interrupt status for USB EP2 */\r
+ #define USBFS_INTR_CAUSE_EP3_INTR_POS (10u) /* [10] Interrupt status for USB EP3 */\r
+ #define USBFS_INTR_CAUSE_EP4_INTR_POS (11u) /* [11] Interrupt status for USB EP4 */\r
+ #define USBFS_INTR_CAUSE_EP5_INTR_POS (12u) /* [12] Interrupt status for USB EP5 */\r
+ #define USBFS_INTR_CAUSE_EP6_INTR_POS (13u) /* [13] Interrupt status for USB EP6 */\r
+ #define USBFS_INTR_CAUSE_EP7_INTR_POS (14u) /* [14] Interrupt status for USB EP7 */\r
+ #define USBFS_INTR_CAUSE_EP8_INTR_POS (15u) /* [15] Interrupt status for USB EP8 */\r
+ #define USBFS_INTR_CAUSE_SOF_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_SOF_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_BUS_RESET_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_BUS_RESET_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP0_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP0_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_LPM_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_LPM_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_RESUME_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_RESUME_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_ARB_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_ARB_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP1_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP1_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP2_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP2_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP3_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP3_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP4_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP4_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP5_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP5_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP6_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP6_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP7_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP7_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP8_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP8_INTR_POS)\r
+\r
+ #define USBFS_INTR_CAUSE_CTRL_INTR_MASK (USBFS_INTR_CAUSE_SOF_INTR | \\r
+ USBFS_INTR_CAUSE_BUS_RESET_INTR | \\r
+ USBFS_INTR_CAUSE_EP0_INTR | \\r
+ USBFS_INTR_CAUSE_LPM_INTR)\r
+\r
+ #define USBFS_INTR_CAUSE_EP1_8_INTR_MASK (USBFS_INTR_CAUSE_EP1_INTR | \\r
+ USBFS_INTR_CAUSE_EP2_INTR | \\r
+ USBFS_INTR_CAUSE_EP3_INTR | \\r
+ USBFS_INTR_CAUSE_EP4_INTR | \\r
+ USBFS_INTR_CAUSE_EP5_INTR | \\r
+ USBFS_INTR_CAUSE_EP6_INTR | \\r
+ USBFS_INTR_CAUSE_EP7_INTR | \\r
+ USBFS_INTR_CAUSE_EP8_INTR)\r
+\r
+ #define USBFS_INTR_CAUSE_EP_INTR_SHIFT (USBFS_INTR_CAUSE_ARB_INTR_POS - \\r
+ (USBFS_INTR_CAUSE_LPM_INTR_POS + 1u))\r
+ #define USBFS_INTR_CAUSE_SRC_COUNT (13u)\r
+\r
+ #define USBFS_CHGDET_CTRL_PRIMARY (USBFS_CHGDET_CTRL_COMP_EN | \\r
+ USBFS_CHGDET_CTRL_COMP_DM | \\r
+ USBFS_CHGDET_CTRL_REF_EN | \\r
+ USBFS_CHGDET_CTRL_REF_DP)\r
+\r
+ #define USBFS_CHGDET_CTRL_SECONDARY (USBFS_CHGDET_CTRL_COMP_EN | \\r
+ USBFS_CHGDET_CTRL_COMP_DP | \\r
+ USBFS_CHGDET_CTRL_REF_EN | \\r
+ USBFS_CHGDET_CTRL_REF_DM)\r
+\r
+ #define USBFS_CHGDET_CTRL_DEFAULT (0x00000900u)\r
+\r
+\r
+#else /* (CY_PSOC3 || CY_PSOC5LP) */\r
+ #define USBFS_PM_ACT_EN_FSUSB USBFS_USB__PM_ACT_MSK\r
+ #define USBFS_PM_STBY_EN_FSUSB USBFS_USB__PM_STBY_MSK\r
+ #define USBFS_PM_AVAIL_EN_FSUSBIO (0x10u)\r
+\r
+ #define USBFS_PM_USB_CR0_REF_EN (0x01u)\r
+ #define USBFS_PM_USB_CR0_PD_N (0x02u)\r
+ #define USBFS_PM_USB_CR0_PD_PULLUP_N (0x04u)\r
+#endif /* (CY_PSOC4) */\r
+\r
+\r
+/***************************************\r
+* Macros Definitions\r
+***************************************/\r
+\r
+#if (CY_PSOC4)\r
+ #define USBFS_ClearSieInterruptSource(intMask) \\r
+ do{ \\r
+ USBFS_INTR_SIE_REG = (uint32) (intMask); \\r
+ }while(0)\r
+#else\r
+ #define USBFS_ClearSieInterruptSource(intMask) \\r
+ do{ /* Does nothing. */ }while(0)\r
+#endif /* (CY_PSOC4) */\r
+\r
+#define USBFS_ClearSieEpInterruptSource(intMask) \\r
+ do{ \\r
+ USBFS_SIE_EP_INT_SR_REG = (uint8) (intMask); \\r
+ }while(0)\r
+\r
+#define USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType) (((epType) == USBFS_EP_TYPE_ISOC) ? \\r
+ (USBFS_MODE_ISO_IN) : (USBFS_MODE_ACK_IN))\r
+\r
+#define USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType) (((epType) == USBFS_EP_TYPE_ISOC) ? \\r
+ (USBFS_MODE_ISO_OUT) : (USBFS_MODE_ACK_OUT))\r
+\r
+#define USBFS_GET_EP_TYPE(epNumber) (USBFS_EP[epNumber].attrib & USBFS_EP_TYPE_MASK)\r
+\r
+#define USBFS_GET_UINT16(hi, low) (((uint16) ((uint16) (hi) << 8u)) | ((uint16) (low) & 0xFFu))\r
+\r
+\r
+/***************************************\r
+* Initialization Register Settings\r
+***************************************/\r
+\r
+/* Clear device address and enable USB IP respond to USB traffic. */\r
+#define USBFS_DEFUALT_CR0 (USBFS_CR0_ENABLE)\r
+\r
+/* Arbiter configuration depends on memory management mode. */\r
+#define USBFS_DEFAULT_ARB_CFG ((USBFS_EP_MANAGEMENT_MANUAL) ? (USBFS_ARB_CFG_DMA_CFG_NONE) : \\r
+ ((USBFS_EP_MANAGEMENT_DMA_MANUAL) ? \\r
+ (USBFS_ARB_CFG_DMA_CFG_MANUAL) : \\r
+ (USBFS_ARB_CFG_AUTO_MEM | USBFS_ARB_CFG_DMA_CFG_AUTO)))\r
+\r
+/* Enable arbiter interrupt for active endpoints only */\r
+#define USBFS_DEFAULT_ARB_INT_EN \\r
+ ((uint8) ((uint8) USBFS_DMA1_ACTIVE << USBFS_ARB_INT_EP1_INTR_POS) | \\r
+ (uint8) ((uint8) USBFS_DMA2_ACTIVE << USBFS_ARB_INT_EP2_INTR_POS) | \\r
+ (uint8) ((uint8) USBFS_DMA3_ACTIVE << USBFS_ARB_INT_EP3_INTR_POS) | \\r
+ (uint8) ((uint8) USBFS_DMA4_ACTIVE << USBFS_ARB_INT_EP4_INTR_POS) | \\r
+ (uint8) ((uint8) USBFS_DMA5_ACTIVE << USBFS_ARB_INT_EP5_INTR_POS) | \\r
+ (uint8) ((uint8) USBFS_DMA6_ACTIVE << USBFS_ARB_INT_EP6_INTR_POS) | \\r
+ (uint8) ((uint8) USBFS_DMA7_ACTIVE << USBFS_ARB_INT_EP7_INTR_POS) | \\r
+ (uint8) ((uint8) USBFS_DMA8_ACTIVE << USBFS_ARB_INT_EP8_INTR_POS))\r
+\r
+/* Enable all SIE endpoints interrupts */\r
+#define USBFS_DEFAULT_SIE_EP_INT_EN (USBFS_SIE_INT_EP1_INTR | \\r
+ USBFS_SIE_INT_EP2_INTR | \\r
+ USBFS_SIE_INT_EP3_INTR | \\r
+ USBFS_SIE_INT_EP4_INTR | \\r
+ USBFS_SIE_INT_EP5_INTR | \\r
+ USBFS_SIE_INT_EP6_INTR | \\r
+ USBFS_SIE_INT_EP7_INTR | \\r
+ USBFS_SIE_INT_EP8_INTR)\r
+\r
+#define USBFS_ARB_EPX_CFG_DEFAULT (USBFS_ARB_EPX_CFG_RESET | \\r
+ USBFS_ARB_EPX_CFG_CRC_BYPASS)\r
+\r
+/* Default EP arbiter interrupt source register */\r
+#define USBFS_ARB_EPX_INT_COMMON_MASK (USBFS_ARB_EPX_INT_IN_BUF_FULL | \\r
+ USBFS_ARB_EPX_INT_BUF_OVER | \\r
+ USBFS_ARB_EPX_INT_BUF_UNDER | \\r
+ USBFS_ARB_EPX_INT_ERR_INT | \\r
+ (USBFS_EP_MANAGEMENT_DMA_MANUAL ? USBFS_ARB_EPX_INT_DMA_GNT : 0u))\r
+\r
+#define USBFS_CLEAR_REG (0u)\r
+\r
+#if (CY_PSOC4)\r
+ /* Set USB lock option when IMO is locked to USB traffic. */\r
+ #define USBFS_DEFUALT_CR1 ((0u != CySysClkImoGetUsbLock()) ? (USBFS_CR1_ENABLE_LOCK) : (0u))\r
+\r
+ /* Recommended value is increased from 3 to 10 due to suppress glitch on \r
+ * RSE0 with USB2.0 hubs (LF CLK = 32kHz equal to 350us). */\r
+ #define USBFS_DEFUALT_BUS_RST_CNT (10u)\r
+\r
+ /* Select VBUS sources as: valid, PHY of GPIO, and clears isolate bit. */\r
+ /* Application level must ensure that VBUS is valid valid to use. */\r
+ #define USBFS_DEFAULT_POWER_CTRL_VBUS (USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN | \\r
+ ((!USBFS_VBUS_MONITORING_ENABLE) ? \\r
+ (USBFS_POWER_CTRL_VBUS_VALID_OVR_1) : \\r
+ (USBFS_VBUS_POWER_PAD_ENABLE ? \\r
+ (USBFS_POWER_CTRL_VBUS_VALID_OVR_PHY) : \\r
+ (USBFS_POWER_CTRL_VBUS_VALID_OVR_GPIO))))\r
+ /* Enable USB IP. */\r
+ #define USBFS_DEFAULT_POWER_CTRL_PHY (USBFS_POWER_CTRL_SUSPEND | \\r
+ USBFS_POWER_CTRL_SUSPEND_DEL | \\r
+ USBFS_POWER_CTRL_ENABLE_RCVR | \\r
+ USBFS_POWER_CTRL_ENABLE_DPO | \\r
+ USBFS_POWER_CTRL_ENABLE_DMO | \\r
+ USBFS_POWER_CTRL_ENABLE)\r
+\r
+ /* Assign interrupt between levels lo, med, hi. */\r
+ #define USBFS_DEFAULT_INTR_LVL_SEL ((uint32) (USBFS_INTR_LVL_SEL))\r
+\r
+ /* Enable interrupt source in the INTR_SIE. The SOF is always disabled and EP0 is enabled. */\r
+ #define USBFS_DEFAULT_INTR_SIE_MASK \\r
+ ((uint32) ((uint32) USBFS_BUS_RESET_ISR_ACTIVE << USBFS_INTR_SIE_BUS_RESET_INTR_POS) | \\r
+ (uint32) ((uint32) USBFS_SOF_ISR_ACTIVE << USBFS_INTR_SIE_SOF_INTR_POS) | \\r
+ (uint32) ((uint32) USBFS_LPM_ACTIVE << USBFS_INTR_SIE_LPM_INTR_POS) | \\r
+ (uint32) ((uint32) USBFS_INTR_SIE_EP0_INTR))\r
+\r
+ /* Arbiter interrupt sources */\r
+ #define USBFS_ARB_EPX_INT_MASK (USBFS_ARB_EPX_INT_COMMON_MASK | \\r
+ (USBFS_EP_MANAGEMENT_DMA_AUTO ? USBFS_ARB_EPX_INT_DMA_TERMIN : 0u))\r
+\r
+ /* Common DMA configuration */\r
+ #define USBFS_DMA_COMMON_CFG (CYDMA_PULSE | CYDMA_ENTIRE_DESCRIPTOR | \\r
+ CYDMA_NON_PREEMPTABLE)\r
+\r
+\r
+#else\r
+ #define USBFS_ARB_EPX_INT_MASK (USBFS_ARB_EPX_INT_COMMON_MASK)\r
+\r
+ #define USBFS_DEFUALT_CR1 (USBFS_CR1_ENABLE_LOCK)\r
+\r
+ /* Recommended value is 3 for LF CLK = 100kHz equal to 100us. */\r
+ #define USBFS_DEFUALT_BUS_RST_CNT (10u)\r
+#endif /* (CY_PSOC4) */\r
+\r
+/*\r
+* \addtogroup group_deprecated\r
+* @{\r
*/\r
+\r
+/***************************************\r
+* The following code is DEPRECATED and\r
+* must not be used.\r
+***************************************/\r
+\r
+/* Renamed type definitions */\r
+#define USBFS_CODE CYCODE\r
+#define USBFS_FAR CYFAR\r
+#if defined(__C51__) || defined(__CX51__)\r
+ #define USBFS_DATA data\r
+ #define USBFS_XDATA xdata\r
+#else\r
+ #define USBFS_DATA\r
+ #define USBFS_XDATA\r
+#endif /* __C51__ */\r
+#define USBFS_NULL NULL\r
+/** @} deprecated */\r
+/* Renamed structure fields */\r
+#define wBuffOffset buffOffset\r
+#define wBufferSize bufferSize\r
+#define bStatus status\r
+#define wLength length\r
+#define wCount count\r
+\r
+/* Renamed global variable */\r
+#define CurrentTD USBFS_currentTD\r
+#define USBFS_interfaceSetting_last USBFS_interfaceSettingLast\r
+\r
+/* Renamed global constants */\r
+#define USBFS_DWR_VDDD_OPERATION (USBFS_DWR_POWER_OPERATION)\r
+\r
+/* Renamed functions */\r
+#define USBFS_bCheckActivity USBFS_CheckActivity\r
+#define USBFS_bGetConfiguration USBFS_GetConfiguration\r
+#define USBFS_bGetInterfaceSetting USBFS_GetInterfaceSetting\r
+#define USBFS_bGetEPState USBFS_GetEPState\r
+#define USBFS_wGetEPCount USBFS_GetEPCount\r
+#define USBFS_bGetEPAckState USBFS_GetEPAckState\r
+#define USBFS_bRWUEnabled USBFS_RWUEnabled\r
+#define USBFS_bVBusPresent USBFS_VBusPresent\r
+\r
+#define USBFS_bConfiguration USBFS_configuration\r
+#define USBFS_bInterfaceSetting USBFS_interfaceSetting\r
+#define USBFS_bDeviceAddress USBFS_deviceAddress\r
+#define USBFS_bDeviceStatus USBFS_deviceStatus\r
+#define USBFS_bDevice USBFS_device\r
+#define USBFS_bTransferState USBFS_transferState\r
+#define USBFS_bLastPacketSize USBFS_lastPacketSize\r
+\r
+#define USBFS_LoadEP USBFS_LoadInEP\r
+#define USBFS_LoadInISOCEP USBFS_LoadInEP\r
+#define USBFS_EnableOutISOCEP USBFS_EnableOutEP\r
+\r
+#define USBFS_SetVector CyIntSetVector\r
+#define USBFS_SetPriority CyIntSetPriority\r
+#define USBFS_EnableInt CyIntEnable\r
+\r
+/* Replace with register access. */\r
+#define USBFS_bmRequestType USBFS_EP0_DR0_PTR\r
+#define USBFS_bRequest USBFS_EP0_DR1_PTR\r
+#define USBFS_wValue USBFS_EP0_DR2_PTR\r
+#define USBFS_wValueHi USBFS_EP0_DR3_PTR\r
+#define USBFS_wValueLo USBFS_EP0_DR2_PTR\r
+#define USBFS_wIndex USBFS_EP0_DR4_PTR\r
+#define USBFS_wIndexHi USBFS_EP0_DR5_PTR\r
+#define USBFS_wIndexLo USBFS_EP0_DR4_PTR\r
+#define USBFS_length USBFS_EP0_DR6_PTR\r
+#define USBFS_lengthHi USBFS_EP0_DR7_PTR\r
+#define USBFS_lengthLo USBFS_EP0_DR6_PTR\r
+\r
+/* Rename VBUS monitoring registers. */\r
+#if (CY_PSOC3 || CY_PSOC5LP)\r
+ #if (USBFS_VBUS_MONITORING_ENABLE)\r
+ #if (USBFS_VBUS_MONITORING_INTERNAL)\r
+ #define USBFS_VBUS_DR_PTR ( (reg8 *) USBFS_VBUS__DR)\r
+ #define USBFS_VBUS_DR_REG (*(reg8 *) USBFS_VBUS__DR)\r
+ #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_VBUS__PS)\r
+ #define USBFS_VBUS_PS_REG (*(reg8 *) USBFS_VBUS__PS)\r
+ #define USBFS_VBUS_MASK USBFS_VBUS__MASK\r
+ #else\r
+ #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG)\r
+ #define USBFS_VBUS_MASK (0x01u)\r
+ #endif /* (USBFS_VBUS_MONITORING_INTERNAL) */\r
+ #endif /*(USBFS_VBUS_MONITORING_ENABLE) */\r
+ \r
+ /* Pointer DIE structure in flash (8 bytes): Y and X location, wafer, lot msb, lot lsb, \r
+ * work week, fab/year, minor. */\r
+ #define USBFS_DIE_ID CYDEV_FLSHID_CUST_TABLES_BASE\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ #if (USBFS_DMA1_ACTIVE)\r
+ #define USBFS_ep1_TD_TERMOUT_EN (USBFS_ep1__TD_TERMOUT_EN)\r
+ #else\r
+ #define USBFS_ep1_TD_TERMOUT_EN (0u)\r
+ #endif /* (USBFS_DMA1_ACTIVE) */\r
+\r
+ #if (USBFS_DMA2_ACTIVE)\r
+ #define USBFS_ep2_TD_TERMOUT_EN (USBFS_ep2__TD_TERMOUT_EN)\r
+ #else\r
+ #define USBFS_ep2_TD_TERMOUT_EN (0u)\r
+ #endif /* (USBFS_DMA2_ACTIVE) */\r
+\r
+ #if (USBFS_DMA3_ACTIVE)\r
+ #define USBFS_ep3_TD_TERMOUT_EN (USBFS_ep3__TD_TERMOUT_EN)\r
+ #else\r
+ #define USBFS_ep3_TD_TERMOUT_EN (0u)\r
+ #endif /* (USBFS_DMA3_ACTIVE) */\r
+\r
+ #if (USBFS_DMA4_ACTIVE)\r
+ #define USBFS_ep4_TD_TERMOUT_EN (USBFS_ep4__TD_TERMOUT_EN)\r
+ #else\r
+ #define USBFS_ep4_TD_TERMOUT_EN (0u)\r
+ #endif /* (USBFS_DMA4_ACTIVE) */\r
+\r
+ #if (USBFS_DMA5_ACTIVE)\r
+ #define USBFS_ep5_TD_TERMOUT_EN (USBFS_ep5__TD_TERMOUT_EN)\r
+ #else\r
+ #define USBFS_ep5_TD_TERMOUT_EN (0u)\r
+ #endif /* (USBFS_DMA5_ACTIVE) */\r
+\r
+ #if (USBFS_DMA6_ACTIVE)\r
+ #define USBFS_ep6_TD_TERMOUT_EN (USBFS_ep6__TD_TERMOUT_EN)\r
+ #else\r
+ #define USBFS_ep6_TD_TERMOUT_EN (0u)\r
+ #endif /* (USBFS_DMA6_ACTIVE) */\r
+\r
+ #if (USBFS_DMA7_ACTIVE)\r
+ #define USBFS_ep7_TD_TERMOUT_EN (USBFS_ep7__TD_TERMOUT_EN)\r
+ #else\r
+ #define USBFS_ep7_TD_TERMOUT_EN (0u)\r
+ #endif /* (USBFS_DMA7_ACTIVE) */\r
+\r
+ #if (USBFS_DMA8_ACTIVE)\r
+ #define USBFS_ep8_TD_TERMOUT_EN (USBFS_ep8__TD_TERMOUT_EN)\r
+ #else\r
+ #define USBFS_ep8_TD_TERMOUT_EN (0u)\r
+ #endif /* (USBFS_DMA8_ACTIVE) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ \r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+/* Rename USB IP registers. */\r
#define USBFS_ARB_CFG USBFS_ARB_CFG_PTR\r
\r
#define USBFS_ARB_EP1_CFG USBFS_ARB_EP1_CFG_PTR\r
#define USBFS_USBIO_CR1 USBFS_USBIO_CR1_PTR\r
#define USBFS_USBIO_CR2 USBFS_USBIO_CR2_PTR\r
\r
-#define USBFS_USB_MEM ((reg8 *) CYDEV_USB_MEM_BASE)\r
-\r
-#if(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_LEOPARD)\r
- /* PSoC3 interrupt registers*/\r
- #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_INTC_PRIOR0)\r
- #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_INTC_SET_EN0)\r
- #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_INTC_CLR_EN0)\r
- #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_INTC_VECT_MBASE)\r
-#elif(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_PANTHER)\r
- /* PSoC5 interrupt registers*/\r
- #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_NVIC_PRI_0)\r
- #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0)\r
- #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0)\r
- #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET)\r
-#endif /* CYDEV_CHIP_DIE_EXPECT */\r
-\r
-\r
-/***************************************\r
-* Interrupt vectors, masks and priorities\r
-***************************************/\r
-\r
-#define USBFS_BUS_RESET_PRIOR USBFS_bus_reset__INTC_PRIOR_NUM\r
-#define USBFS_BUS_RESET_MASK USBFS_bus_reset__INTC_MASK\r
-#define USBFS_BUS_RESET_VECT_NUM USBFS_bus_reset__INTC_NUMBER\r
-\r
-#define USBFS_SOF_PRIOR USBFS_sof_int__INTC_PRIOR_NUM\r
-#define USBFS_SOF_MASK USBFS_sof_int__INTC_MASK\r
-#define USBFS_SOF_VECT_NUM USBFS_sof_int__INTC_NUMBER\r
-\r
-#define USBFS_EP_0_PRIOR USBFS_ep_0__INTC_PRIOR_NUM\r
-#define USBFS_EP_0_MASK USBFS_ep_0__INTC_MASK\r
-#define USBFS_EP_0_VECT_NUM USBFS_ep_0__INTC_NUMBER\r
-\r
-#define USBFS_EP_1_PRIOR USBFS_ep_1__INTC_PRIOR_NUM\r
-#define USBFS_EP_1_MASK USBFS_ep_1__INTC_MASK\r
-#define USBFS_EP_1_VECT_NUM USBFS_ep_1__INTC_NUMBER\r
-\r
-#define USBFS_EP_2_PRIOR USBFS_ep_2__INTC_PRIOR_NUM\r
-#define USBFS_EP_2_MASK USBFS_ep_2__INTC_MASK\r
-#define USBFS_EP_2_VECT_NUM USBFS_ep_2__INTC_NUMBER\r
-\r
-#define USBFS_EP_3_PRIOR USBFS_ep_3__INTC_PRIOR_NUM\r
-#define USBFS_EP_3_MASK USBFS_ep_3__INTC_MASK\r
-#define USBFS_EP_3_VECT_NUM USBFS_ep_3__INTC_NUMBER\r
-\r
-#define USBFS_EP_4_PRIOR USBFS_ep_4__INTC_PRIOR_NUM\r
-#define USBFS_EP_4_MASK USBFS_ep_4__INTC_MASK\r
-#define USBFS_EP_4_VECT_NUM USBFS_ep_4__INTC_NUMBER\r
-\r
-#define USBFS_EP_5_PRIOR USBFS_ep_5__INTC_PRIOR_NUM\r
-#define USBFS_EP_5_MASK USBFS_ep_5__INTC_MASK\r
-#define USBFS_EP_5_VECT_NUM USBFS_ep_5__INTC_NUMBER\r
-\r
-#define USBFS_EP_6_PRIOR USBFS_ep_6__INTC_PRIOR_NUM\r
-#define USBFS_EP_6_MASK USBFS_ep_6__INTC_MASK\r
-#define USBFS_EP_6_VECT_NUM USBFS_ep_6__INTC_NUMBER\r
-\r
-#define USBFS_EP_7_PRIOR USBFS_ep_7__INTC_PRIOR_NUM\r
-#define USBFS_EP_7_MASK USBFS_ep_7__INTC_MASK\r
-#define USBFS_EP_7_VECT_NUM USBFS_ep_7__INTC_NUMBER\r
-\r
-#define USBFS_EP_8_PRIOR USBFS_ep_8__INTC_PRIOR_NUM\r
-#define USBFS_EP_8_MASK USBFS_ep_8__INTC_MASK\r
-#define USBFS_EP_8_VECT_NUM USBFS_ep_8__INTC_NUMBER\r
-\r
-#define USBFS_DP_INTC_PRIOR USBFS_dp_int__INTC_PRIOR_NUM\r
-#define USBFS_DP_INTC_MASK USBFS_dp_int__INTC_MASK\r
-#define USBFS_DP_INTC_VECT_NUM USBFS_dp_int__INTC_NUMBER\r
-\r
-/* ARB ISR should have higher priority from EP_X ISR, therefore it is defined to highest (0) */\r
-#define USBFS_ARB_PRIOR (0u)\r
-#define USBFS_ARB_MASK USBFS_arb_int__INTC_MASK\r
-#define USBFS_ARB_VECT_NUM USBFS_arb_int__INTC_NUMBER\r
-\r
-/***************************************\r
- * Endpoint 0 offsets (Table 9-2)\r
- **************************************/\r
-\r
-#define USBFS_bmRequestType USBFS_EP0_DR0_PTR\r
-#define USBFS_bRequest USBFS_EP0_DR1_PTR\r
-#define USBFS_wValue USBFS_EP0_DR2_PTR\r
-#define USBFS_wValueHi USBFS_EP0_DR3_PTR\r
-#define USBFS_wValueLo USBFS_EP0_DR2_PTR\r
-#define USBFS_wIndex USBFS_EP0_DR4_PTR\r
-#define USBFS_wIndexHi USBFS_EP0_DR5_PTR\r
-#define USBFS_wIndexLo USBFS_EP0_DR4_PTR\r
-#define USBFS_length USBFS_EP0_DR6_PTR\r
-#define USBFS_lengthHi USBFS_EP0_DR7_PTR\r
-#define USBFS_lengthLo USBFS_EP0_DR6_PTR\r
-\r
-\r
-/***************************************\r
-* Register Constants\r
-***************************************/\r
-#define USBFS_VDDD_MV CYDEV_VDDD_MV\r
-#define USBFS_3500MV (3500u)\r
-\r
-#define USBFS_CR1_REG_ENABLE (0x01u)\r
-#define USBFS_CR1_ENABLE_LOCK (0x02u)\r
-#define USBFS_CR1_BUS_ACTIVITY_SHIFT (0x02u)\r
-#define USBFS_CR1_BUS_ACTIVITY ((uint8)(0x01u << USBFS_CR1_BUS_ACTIVITY_SHIFT))\r
-#define USBFS_CR1_TRIM_MSB_EN (0x08u)\r
-\r
-#define USBFS_EP0_CNT_DATA_TOGGLE (0x80u)\r
-#define USBFS_EPX_CNT_DATA_TOGGLE (0x80u)\r
-#define USBFS_EPX_CNT0_MASK (0x0Fu)\r
-#define USBFS_EPX_CNTX_MSB_MASK (0x07u)\r
-#define USBFS_EPX_CNTX_ADDR_SHIFT (0x04u)\r
-#define USBFS_EPX_CNTX_ADDR_OFFSET (0x10u)\r
-#define USBFS_EPX_CNTX_CRC_COUNT (0x02u)\r
-#define USBFS_EPX_DATA_BUF_MAX (512u)\r
-\r
-#define USBFS_CR0_ENABLE (0x80u)\r
-\r
-/* A 100 KHz clock is used for BUS reset count. Recommended is to count 10 pulses */\r
-#define USBFS_BUS_RST_COUNT (0x0au)\r
-\r
-#define USBFS_USBIO_CR1_IOMODE (0x20u)\r
-#define USBFS_USBIO_CR1_USBPUEN (0x04u)\r
-#define USBFS_USBIO_CR1_DP0 (0x02u)\r
-#define USBFS_USBIO_CR1_DM0 (0x01u)\r
-\r
-#define USBFS_USBIO_CR0_TEN (0x80u)\r
-#define USBFS_USBIO_CR0_TSE0 (0x40u)\r
-#define USBFS_USBIO_CR0_TD (0x20u)\r
-#define USBFS_USBIO_CR0_RD (0x01u)\r
-\r
-#define USBFS_FASTCLK_IMO_CR_USBCLK_ON (0x40u)\r
-#define USBFS_FASTCLK_IMO_CR_XCLKEN (0x20u)\r
-#define USBFS_FASTCLK_IMO_CR_FX2ON (0x10u)\r
-\r
-#define USBFS_ARB_EPX_CFG_RESET (0x08u)\r
-#define USBFS_ARB_EPX_CFG_CRC_BYPASS (0x04u)\r
-#define USBFS_ARB_EPX_CFG_DMA_REQ (0x02u)\r
-#define USBFS_ARB_EPX_CFG_IN_DATA_RDY (0x01u)\r
-#define USBFS_ARB_EPX_CFG_DEFAULT (USBFS_ARB_EPX_CFG_RESET | \\r
- USBFS_ARB_EPX_CFG_CRC_BYPASS)\r
-\r
-#define USBFS_ARB_EPX_SR_IN_BUF_FULL (0x01u)\r
-#define USBFS_ARB_EPX_SR_DMA_GNT (0x02u)\r
-#define USBFS_ARB_EPX_SR_BUF_OVER (0x04u)\r
-#define USBFS_ARB_EPX_SR_BUF_UNDER (0x08u)\r
-\r
-#define USBFS_ARB_CFG_AUTO_MEM (0x10u)\r
-#define USBFS_ARB_CFG_MANUAL_DMA (0x20u)\r
-#define USBFS_ARB_CFG_AUTO_DMA (0x40u)\r
-#define USBFS_ARB_CFG_CFG_CPM (0x80u)\r
-\r
-#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- #define USBFS_ARB_EPX_INT_MASK (0x1Du)\r
-#else\r
- #define USBFS_ARB_EPX_INT_MASK (0x1Fu)\r
-#endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
-#define USBFS_ARB_INT_MASK (uint8)((USBFS_DMA1_REMOVE ^ 1u) | \\r
- (uint8)((USBFS_DMA2_REMOVE ^ 1u) << 1u) | \\r
- (uint8)((USBFS_DMA3_REMOVE ^ 1u) << 2u) | \\r
- (uint8)((USBFS_DMA4_REMOVE ^ 1u) << 3u) | \\r
- (uint8)((USBFS_DMA5_REMOVE ^ 1u) << 4u) | \\r
- (uint8)((USBFS_DMA6_REMOVE ^ 1u) << 5u) | \\r
- (uint8)((USBFS_DMA7_REMOVE ^ 1u) << 6u) | \\r
- (uint8)((USBFS_DMA8_REMOVE ^ 1u) << 7u) )\r
+#define USBFS_DM_INP_DIS_PTR ( (reg8 *) USBFS_Dm__INP_DIS)\r
+#define USBFS_DM_INP_DIS_REG (*(reg8 *) USBFS_Dm__INP_DIS)\r
+#define USBFS_DP_INP_DIS_PTR ( (reg8 *) USBFS_Dp__INP_DIS)\r
+#define USBFS_DP_INP_DIS_REG (*(reg8 *) USBFS_Dp__INP_DIS)\r
+#define USBFS_DP_INTSTAT_PTR ( (reg8 *) USBFS_Dp__INTSTAT)\r
+#define USBFS_DP_INTSTAT_REG (*(reg8 *) USBFS_Dp__INTSTAT)\r
+#define USBFS_DM_MASK USBFS_Dm__0__MASK\r
+#define USBFS_DP_MASK USBFS_Dp__0__MASK\r
\r
#define USBFS_SIE_EP_INT_EP1_MASK (0x01u)\r
#define USBFS_SIE_EP_INT_EP2_MASK (0x02u)\r
#define USBFS_SIE_EP_INT_EP7_MASK (0x40u)\r
#define USBFS_SIE_EP_INT_EP8_MASK (0x80u)\r
\r
-#define USBFS_PM_ACT_EN_FSUSB USBFS_USB__PM_ACT_MSK\r
-#define USBFS_PM_STBY_EN_FSUSB USBFS_USB__PM_STBY_MSK\r
-#define USBFS_PM_AVAIL_EN_FSUSBIO (0x10u)\r
+#define USBFS_ARB_EPX_SR_IN_BUF_FULL (0x01u)\r
+#define USBFS_ARB_EPX_SR_DMA_GNT (0x02u)\r
+#define USBFS_ARB_EPX_SR_BUF_OVER (0x04u)\r
+#define USBFS_ARB_EPX_SR_BUF_UNDER (0x08u)\r
+\r
+#define USBFS_ARB_EPX_INT_EN_ALL USBFS_ARB_EPX_INT_ALL\r
\r
-#define USBFS_PM_USB_CR0_REF_EN (0x01u)\r
-#define USBFS_PM_USB_CR0_PD_N (0x02u)\r
-#define USBFS_PM_USB_CR0_PD_PULLUP_N (0x04u)\r
+#define USBFS_CR1_BUS_ACTIVITY_SHIFT (0x02u)\r
\r
-#define USBFS_USB_CLK_ENABLE (0x01u)\r
+#define USBFS_BUS_RST_COUNT USBFS_DEFUALT_BUS_RST_CNT\r
\r
-#define USBFS_DM_MASK USBFS_Dm__0__MASK\r
-#define USBFS_DP_MASK USBFS_Dp__0__MASK\r
+#define USBFS_ARB_INT_MASK USBFS_DEFAULT_ARB_INT_EN\r
\r
-#define USBFS_DYN_RECONFIG_ENABLE (0x01u)\r
-#define USBFS_DYN_RECONFIG_EP_SHIFT (0x01u)\r
-#define USBFS_DYN_RECONFIG_RDY_STS (0x10u)\r
+#if (CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_LEOPARD)\r
+ /* CY_PSOC3 interrupt registers */\r
+ #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_INTC_PRIOR0)\r
+ #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_INTC_SET_EN0)\r
+ #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_INTC_CLR_EN0)\r
+ #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_INTC_VECT_MBASE)\r
+#elif (CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_PANTHER)\r
+ /* CY_PSOC5LP interrupt registers */\r
+ #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_NVIC_PRI_0)\r
+ #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0)\r
+ #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0)\r
+ #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET)\r
+#endif /* CYDEV_CHIP_DIE_EXPECT */\r
\r
\r
-#endif /* CY_USBFS_USBFS_H */\r
+#endif /* (CY_USBFS_USBFS_H) */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_Dm.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Dm_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_Write\r
*******************************************************************************/\r
-void USBFS_Dm_Write(uint8 value) \r
+void USBFS_Dm_Write(uint8 value)\r
{\r
uint8 staticBits = (USBFS_Dm_DR & (uint8)(~USBFS_Dm_MASK));\r
USBFS_Dm_DR = staticBits | ((uint8)(value << USBFS_Dm_SHIFT) & USBFS_Dm_MASK);\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Dm_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* USBFS_Dm_DM_STRONG Strong Drive \r
-* USBFS_Dm_DM_OD_HI Open Drain, Drives High \r
-* USBFS_Dm_DM_OD_LO Open Drain, Drives Low \r
-* USBFS_Dm_DM_RES_UP Resistive Pull Up \r
-* USBFS_Dm_DM_RES_DWN Resistive Pull Down \r
-* USBFS_Dm_DM_RES_UPDWN Resistive Pull Up/Down \r
-* USBFS_Dm_DM_DIG_HIZ High Impedance Digital \r
-* USBFS_Dm_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_SetDriveMode\r
*******************************************************************************/\r
-void USBFS_Dm_SetDriveMode(uint8 mode) \r
+void USBFS_Dm_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(USBFS_Dm_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Dm_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro USBFS_Dm_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_Read \r
*******************************************************************************/\r
-uint8 USBFS_Dm_Read(void) \r
+uint8 USBFS_Dm_Read(void)\r
{\r
return (USBFS_Dm_PS & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Dm_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred USBFS_Dm_Read() API because the \r
+* USBFS_Dm_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_ReadDataReg \r
*******************************************************************************/\r
-uint8 USBFS_Dm_ReadDataReg(void) \r
+uint8 USBFS_Dm_ReadDataReg(void)\r
{\r
return (USBFS_Dm_DR & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(USBFS_Dm_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: USBFS_Dm_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use USBFS_Dm_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - USBFS_Dm_0_INTR (First pin in the list)\r
+ * - USBFS_Dm_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - USBFS_Dm_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_SetInterruptMode\r
+ *******************************************************************************/\r
+ void USBFS_Dm_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & USBFS_Dm_0_INTR) != 0u) \r
+ { \r
+ USBFS_Dm_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: USBFS_Dm_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_ClearInterrupt\r
*******************************************************************************/\r
- uint8 USBFS_Dm_ClearInterrupt(void) \r
+ uint8 USBFS_Dm_ClearInterrupt(void)\r
{\r
return (USBFS_Dm_INTSTAT & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: USBFS_Dm.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "USBFS_Dm_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void USBFS_Dm_Write(uint8 value) ;\r
-void USBFS_Dm_SetDriveMode(uint8 mode) ;\r
-uint8 USBFS_Dm_ReadDataReg(void) ;\r
-uint8 USBFS_Dm_Read(void) ;\r
-uint8 USBFS_Dm_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void USBFS_Dm_Write(uint8 value);\r
+void USBFS_Dm_SetDriveMode(uint8 mode);\r
+uint8 USBFS_Dm_ReadDataReg(void);\r
+uint8 USBFS_Dm_Read(void);\r
+void USBFS_Dm_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 USBFS_Dm_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define USBFS_Dm_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define USBFS_Dm_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define USBFS_Dm_DM_RES_UP PIN_DM_RES_UP\r
-#define USBFS_Dm_DM_RES_DWN PIN_DM_RES_DWN\r
-#define USBFS_Dm_DM_OD_LO PIN_DM_OD_LO\r
-#define USBFS_Dm_DM_OD_HI PIN_DM_OD_HI\r
-#define USBFS_Dm_DM_STRONG PIN_DM_STRONG\r
-#define USBFS_Dm_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the USBFS_Dm_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define USBFS_Dm_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define USBFS_Dm_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define USBFS_Dm_DM_RES_UP PIN_DM_RES_UP\r
+ #define USBFS_Dm_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define USBFS_Dm_DM_OD_LO PIN_DM_OD_LO\r
+ #define USBFS_Dm_DM_OD_HI PIN_DM_OD_HI\r
+ #define USBFS_Dm_DM_STRONG PIN_DM_STRONG\r
+ #define USBFS_Dm_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define USBFS_Dm_MASK USBFS_Dm__MASK\r
#define USBFS_Dm_SHIFT USBFS_Dm__SHIFT\r
#define USBFS_Dm_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(USBFS_Dm__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in USBFS_Dm_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define USBFS_Dm_INTR_NONE (uint16)(0x0000u)\r
+ #define USBFS_Dm_INTR_RISING (uint16)(0x0001u)\r
+ #define USBFS_Dm_INTR_FALLING (uint16)(0x0002u)\r
+ #define USBFS_Dm_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define USBFS_Dm_INTR_MASK (0x01u) \r
+#endif /* (USBFS_Dm__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define USBFS_Dm_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_Dm__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(USBFS_Dm__INTSTAT) /* Interrupt Registers */\r
-\r
- #define USBFS_Dm_INTSTAT (* (reg8 *) USBFS_Dm__INTSTAT)\r
- #define USBFS_Dm_SNAP (* (reg8 *) USBFS_Dm__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(USBFS_Dm__SIO_CFG)\r
+ #define USBFS_Dm_SIO_HYST_EN (* (reg8 *) USBFS_Dm__SIO_HYST_EN)\r
+ #define USBFS_Dm_SIO_REG_HIFREQ (* (reg8 *) USBFS_Dm__SIO_REG_HIFREQ)\r
+ #define USBFS_Dm_SIO_CFG (* (reg8 *) USBFS_Dm__SIO_CFG)\r
+ #define USBFS_Dm_SIO_DIFF (* (reg8 *) USBFS_Dm__SIO_DIFF)\r
+#endif /* (USBFS_Dm__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(USBFS_Dm__INTSTAT)\r
+ #define USBFS_Dm_INTSTAT (* (reg8 *) USBFS_Dm__INTSTAT)\r
+ #define USBFS_Dm_SNAP (* (reg8 *) USBFS_Dm__SNAP)\r
+ \r
+ #define USBFS_Dm_0_INTTYPE_REG (* (reg8 *) USBFS_Dm__0__INTTYPE)\r
+#endif /* (USBFS_Dm__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: USBFS_Dm.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define USBFS_Dm_0 (USBFS_Dm__0__PC)\r
+#define USBFS_Dm_0 (USBFS_Dm__0__PC)\r
+#define USBFS_Dm_0_INTR ((uint16)((uint16)0x0001u << USBFS_Dm__0__SHIFT))\r
+\r
+#define USBFS_Dm_INTR_ALL ((uint16)(USBFS_Dm_0_INTR))\r
\r
#endif /* End Pins USBFS_Dm_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_Dp.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Dp_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_Write\r
*******************************************************************************/\r
-void USBFS_Dp_Write(uint8 value) \r
+void USBFS_Dp_Write(uint8 value)\r
{\r
uint8 staticBits = (USBFS_Dp_DR & (uint8)(~USBFS_Dp_MASK));\r
USBFS_Dp_DR = staticBits | ((uint8)(value << USBFS_Dp_SHIFT) & USBFS_Dp_MASK);\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Dp_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* USBFS_Dp_DM_STRONG Strong Drive \r
-* USBFS_Dp_DM_OD_HI Open Drain, Drives High \r
-* USBFS_Dp_DM_OD_LO Open Drain, Drives Low \r
-* USBFS_Dp_DM_RES_UP Resistive Pull Up \r
-* USBFS_Dp_DM_RES_DWN Resistive Pull Down \r
-* USBFS_Dp_DM_RES_UPDWN Resistive Pull Up/Down \r
-* USBFS_Dp_DM_DIG_HIZ High Impedance Digital \r
-* USBFS_Dp_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_SetDriveMode\r
*******************************************************************************/\r
-void USBFS_Dp_SetDriveMode(uint8 mode) \r
+void USBFS_Dp_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(USBFS_Dp_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Dp_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro USBFS_Dp_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_Read \r
*******************************************************************************/\r
-uint8 USBFS_Dp_Read(void) \r
+uint8 USBFS_Dp_Read(void)\r
{\r
return (USBFS_Dp_PS & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Dp_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred USBFS_Dp_Read() API because the \r
+* USBFS_Dp_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_ReadDataReg \r
*******************************************************************************/\r
-uint8 USBFS_Dp_ReadDataReg(void) \r
+uint8 USBFS_Dp_ReadDataReg(void)\r
{\r
return (USBFS_Dp_DR & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(USBFS_Dp_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: USBFS_Dp_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use USBFS_Dp_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - USBFS_Dp_0_INTR (First pin in the list)\r
+ * - USBFS_Dp_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - USBFS_Dp_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_SetInterruptMode\r
+ *******************************************************************************/\r
+ void USBFS_Dp_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & USBFS_Dp_0_INTR) != 0u) \r
+ { \r
+ USBFS_Dp_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: USBFS_Dp_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_ClearInterrupt\r
*******************************************************************************/\r
- uint8 USBFS_Dp_ClearInterrupt(void) \r
+ uint8 USBFS_Dp_ClearInterrupt(void)\r
{\r
return (USBFS_Dp_INTSTAT & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: USBFS_Dp.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "USBFS_Dp_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
USBFS_Dp__PORT == 15 && ((USBFS_Dp__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void USBFS_Dp_Write(uint8 value) ;\r
-void USBFS_Dp_SetDriveMode(uint8 mode) ;\r
-uint8 USBFS_Dp_ReadDataReg(void) ;\r
-uint8 USBFS_Dp_Read(void) ;\r
-uint8 USBFS_Dp_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void USBFS_Dp_Write(uint8 value);\r
+void USBFS_Dp_SetDriveMode(uint8 mode);\r
+uint8 USBFS_Dp_ReadDataReg(void);\r
+uint8 USBFS_Dp_Read(void);\r
+void USBFS_Dp_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 USBFS_Dp_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define USBFS_Dp_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define USBFS_Dp_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define USBFS_Dp_DM_RES_UP PIN_DM_RES_UP\r
-#define USBFS_Dp_DM_RES_DWN PIN_DM_RES_DWN\r
-#define USBFS_Dp_DM_OD_LO PIN_DM_OD_LO\r
-#define USBFS_Dp_DM_OD_HI PIN_DM_OD_HI\r
-#define USBFS_Dp_DM_STRONG PIN_DM_STRONG\r
-#define USBFS_Dp_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the USBFS_Dp_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define USBFS_Dp_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define USBFS_Dp_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define USBFS_Dp_DM_RES_UP PIN_DM_RES_UP\r
+ #define USBFS_Dp_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define USBFS_Dp_DM_OD_LO PIN_DM_OD_LO\r
+ #define USBFS_Dp_DM_OD_HI PIN_DM_OD_HI\r
+ #define USBFS_Dp_DM_STRONG PIN_DM_STRONG\r
+ #define USBFS_Dp_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define USBFS_Dp_MASK USBFS_Dp__MASK\r
#define USBFS_Dp_SHIFT USBFS_Dp__SHIFT\r
#define USBFS_Dp_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(USBFS_Dp__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in USBFS_Dp_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define USBFS_Dp_INTR_NONE (uint16)(0x0000u)\r
+ #define USBFS_Dp_INTR_RISING (uint16)(0x0001u)\r
+ #define USBFS_Dp_INTR_FALLING (uint16)(0x0002u)\r
+ #define USBFS_Dp_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define USBFS_Dp_INTR_MASK (0x01u) \r
+#endif /* (USBFS_Dp__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define USBFS_Dp_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_Dp__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(USBFS_Dp__INTSTAT) /* Interrupt Registers */\r
-\r
- #define USBFS_Dp_INTSTAT (* (reg8 *) USBFS_Dp__INTSTAT)\r
- #define USBFS_Dp_SNAP (* (reg8 *) USBFS_Dp__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(USBFS_Dp__SIO_CFG)\r
+ #define USBFS_Dp_SIO_HYST_EN (* (reg8 *) USBFS_Dp__SIO_HYST_EN)\r
+ #define USBFS_Dp_SIO_REG_HIFREQ (* (reg8 *) USBFS_Dp__SIO_REG_HIFREQ)\r
+ #define USBFS_Dp_SIO_CFG (* (reg8 *) USBFS_Dp__SIO_CFG)\r
+ #define USBFS_Dp_SIO_DIFF (* (reg8 *) USBFS_Dp__SIO_DIFF)\r
+#endif /* (USBFS_Dp__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(USBFS_Dp__INTSTAT)\r
+ #define USBFS_Dp_INTSTAT (* (reg8 *) USBFS_Dp__INTSTAT)\r
+ #define USBFS_Dp_SNAP (* (reg8 *) USBFS_Dp__SNAP)\r
+ \r
+ #define USBFS_Dp_0_INTTYPE_REG (* (reg8 *) USBFS_Dp__0__INTTYPE)\r
+#endif /* (USBFS_Dp__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: USBFS_Dp.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define USBFS_Dp_0 (USBFS_Dp__0__PC)\r
+#define USBFS_Dp_0 (USBFS_Dp__0__PC)\r
+#define USBFS_Dp_0_INTR ((uint16)((uint16)0x0001u << USBFS_Dp__0__SHIFT))\r
+\r
+#define USBFS_Dp_INTR_ALL ((uint16)(USBFS_Dp_0_INTR))\r
\r
#endif /* End Pins USBFS_Dp_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: USBFS_audio.c\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_audio.c\r
+* \version 3.10\r
*\r
-* Description:\r
-* USB AUDIO Class request handler.\r
+* \brief\r
+* This file contains the USB AUDIO Class request handler.\r
*\r
* Related Document:\r
* Universal Serial Bus Device Class Definition for Audio Devices Release 1.0\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
-\r
-\r
-#if defined(USBFS_ENABLE_AUDIO_CLASS)\r
-\r
#include "USBFS_audio.h"\r
#include "USBFS_pvt.h"\r
-#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
- #include "USBFS_midi.h"\r
-#endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
\r
\r
+#if defined(USBFS_ENABLE_AUDIO_CLASS)\r
+\r
/***************************************\r
* Custom Declarations\r
***************************************/\r
\r
#if !defined(USER_SUPPLIED_AUDIO_HANDLER)\r
\r
-\r
/***************************************\r
* AUDIO Variables\r
***************************************/\r
\r
#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
+ /** Contains the current audio sample frequency. It is set by the host using a SET_CUR request to the endpoint.*/\r
volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP][USBFS_SAMPLE_FREQ_LEN];\r
+ /** Used as a flag for the user code, to inform it that the host has been sent a request \r
+ * to change the sample frequency. The sample frequency will be sent on the next OUT transaction. \r
+ * It contains the endpoint address when set. The following code is recommended for \r
+ * detecting new sample frequency in main code:\r
+ * \snippet /USBFS_sut_02.cydsn/main.c Detecting new Sample Frequency\r
+ * \r
+ * The USBFS_transferState variable is checked to make sure that the transfer completes. */\r
volatile uint8 USBFS_frequencyChanged;\r
+ /** Contains the mute configuration set by the host.*/\r
volatile uint8 USBFS_currentMute;\r
+ /** Contains the volume level set by the host.*/\r
volatile uint8 USBFS_currentVolume[USBFS_VOLUME_LEN];\r
volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_MIN_LSB,\r
USBFS_VOL_MIN_MSB};\r
\r
/*******************************************************************************\r
* Function Name: USBFS_DispatchAUDIOClassRqst\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine dispatches class requests\r
*\r
-* Parameters:\r
-* None.\r
+* \return\r
+* Results of Audio Class request handling: \r
+* - USBFS_TRUE - request was handled without errors\r
+* - USBFS_FALSE - error occurs during handling of request \r
*\r
-* Return:\r
-* requestHandled\r
-*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_currentSampleFrequency: Contains the current audio Sample\r
* Frequency. It is set by the Host using SET_CUR request to the endpoint.\r
* USBFS_frequencyChanged: This variable is used as a flag for the\r
* Sample Frequency. Sample frequency will be sent on the next OUT\r
* transaction. It is contains endpoint address when set. The following\r
* code is recommended for detecting new Sample Frequency in main code:\r
-* if((USBFS_frequencyChanged != 0) &&\r
-* (USBFS_transferState == USBFS_TRANS_STATE_IDLE))\r
-* {\r
-* USBFS_frequencyChanged = 0;\r
-* }\r
-* USBFS_transferState variable is checked to be sure that\r
-* transfer completes.\r
+* \r
+* \snippet /USBFS_sut_02.cydsn/main.c Detecting new Sample Frequency\r
+* \r
+* USBFS_transferState variable is checked to be sure that transfer\r
+* completes.\r
* USBFS_currentMute: Contains mute configuration set by Host.\r
* USBFS_currentVolume: Contains volume level set by Host.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_DispatchAUDIOClassRqst(void) \r
{\r
uint8 requestHandled = USBFS_FALSE;\r
- uint8 bmRequestType = CY_GET_REG8(USBFS_bmRequestType);\r
-\r
- #if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
- uint8 epNumber;\r
- epNumber = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED;\r
- #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
-\r
-\r
- if ((bmRequestType & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)\r
+ \r
+ uint8 RqstRcpt = (uint8)(USBFS_bmRequestTypeReg & USBFS_RQST_RCPT_MASK);\r
+#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
+ uint8 wValueHi = (uint8) USBFS_wValueHiReg;\r
+ uint8 epNumber = (uint8) USBFS_wIndexLoReg & USBFS_DIR_UNUSED;\r
+#endif /* (USBFS_ENABLE_AUDIO_STREAMING) */\r
+ \r
+ /* Check request direction: D2H or H2D. */\r
+ if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H))\r
{\r
- /* Control Read */\r
- if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)\r
+ /* Handle direction from device to host. */\r
+ \r
+ if (USBFS_RQST_RCPT_EP == RqstRcpt)\r
{\r
- /* Endpoint */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ /* Request recipient is to endpoint. */\r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_GET_CUR:\r
#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
- if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)\r
+ if (wValueHi == USBFS_SAMPLING_FREQ_CONTROL)\r
{\r
/* point Control Selector is Sampling Frequency */\r
USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;\r
USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber];\r
+ \r
requestHandled = USBFS_InitControlRead();\r
}\r
- #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
-\r
- /* `#START AUDIO_READ_REQUESTS` Place other request handler here */\r
+ #endif /* (USBFS_ENABLE_AUDIO_STREAMING) */\r
+ \r
+ /* `#START AUDIO_READ_REQUESTS` Place other request handler here */\r
\r
- /* `#END` */\r
+ /* `#END` */\r
\r
- #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK\r
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK \r
USBFS_DispatchAUDIOClass_AUDIO_READ_REQUESTS_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK */\r
-\r
- break;\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK) */ \r
+ break;\r
+ \r
default:\r
+ /* Do not handle this request unless callback is defined. */\r
break;\r
}\r
+ \r
}\r
- else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)\r
+ else if (USBFS_RQST_RCPT_IFC == RqstRcpt)\r
{\r
- /* Interface or Entity ID */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ /* Request recipient is interface or entity ID. */\r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_GET_CUR:\r
#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
- if(CY_GET_REG8(USBFS_wValueHi) == USBFS_MUTE_CONTROL)\r
+ if (wValueHi == USBFS_MUTE_CONTROL)\r
{\r
/* `#START MUTE_CONTROL_GET_REQUEST` Place multi-channel handler here */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK\r
- USBFS_DispatchAUDIOClass_MUTE_CONTROL_GET_REQUEST_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK */\r
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK\r
+ USBFS_DispatchAUDIOClass_MUTE_CONTROL_GET_REQUEST_Callback();\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK) */\r
\r
/* Entity ID Control Selector is MUTE */\r
USBFS_currentTD.wCount = 1u;\r
USBFS_currentTD.pData = &USBFS_currentMute;\r
- requestHandled = USBFS_InitControlRead();\r
+ \r
+ requestHandled = USBFS_InitControlRead();\r
}\r
- else if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL)\r
+ else if (wValueHi == USBFS_VOLUME_CONTROL)\r
{\r
/* `#START VOLUME_CONTROL_GET_REQUEST` Place multi-channel handler here */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK\r
- USBFS_DispatchAUDIOClass_VOLUME_CONTROL_GET_REQUEST_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK */\r
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK\r
+ USBFS_DispatchAUDIOClass_VOLUME_CONTROL_GET_REQUEST_Callback();\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK) */\r
\r
/* Entity ID Control Selector is VOLUME, */\r
USBFS_currentTD.wCount = USBFS_VOLUME_LEN;\r
USBFS_currentTD.pData = USBFS_currentVolume;\r
- requestHandled = USBFS_InitControlRead();\r
+ \r
+ requestHandled = USBFS_InitControlRead();\r
}\r
else\r
{\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK\r
- USBFS_DispatchAUDIOClass_OTHER_GET_CUR_REQUESTS_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK */\r
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK\r
+ USBFS_DispatchAUDIOClass_OTHER_GET_CUR_REQUESTS_Callback();\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK) */\r
}\r
break;\r
- case USBFS_GET_MIN: /* GET_MIN */\r
- if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL)\r
+ \r
+ case USBFS_GET_MIN:\r
+ if (wValueHi == USBFS_VOLUME_CONTROL)\r
{\r
/* Entity ID Control Selector is VOLUME, */\r
USBFS_currentTD.wCount = USBFS_VOLUME_LEN;\r
USBFS_currentTD.pData = &USBFS_minimumVolume[0];\r
- requestHandled = USBFS_InitControlRead();\r
+ \r
+ requestHandled = USBFS_InitControlRead();\r
}\r
break;\r
- case USBFS_GET_MAX: /* GET_MAX */\r
- if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL)\r
+ \r
+ case USBFS_GET_MAX:\r
+ if (wValueHi == USBFS_VOLUME_CONTROL)\r
{\r
/* Entity ID Control Selector is VOLUME, */\r
USBFS_currentTD.wCount = USBFS_VOLUME_LEN;\r
USBFS_currentTD.pData = &USBFS_maximumVolume[0];\r
- requestHandled = USBFS_InitControlRead();\r
+ \r
+ requestHandled = USBFS_InitControlRead();\r
}\r
break;\r
- case USBFS_GET_RES: /* GET_RES */\r
- if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL)\r
+ \r
+ case USBFS_GET_RES:\r
+ if (wValueHi == USBFS_VOLUME_CONTROL)\r
{\r
/* Entity ID Control Selector is VOLUME, */\r
USBFS_currentTD.wCount = USBFS_VOLUME_LEN;\r
USBFS_currentTD.pData = &USBFS_resolutionVolume[0];\r
+ \r
requestHandled = USBFS_InitControlRead();\r
}\r
break;\r
+ \r
/* The contents of the status message is reserved for future use.\r
- * For the time being, a null packet should be returned in the data stage of the\r
- * control transfer, and the received null packet should be ACKed.\r
+ * For the time being, a null packet should be returned in the data stage of the\r
+ * control transfer, and the received null packet should be ACKed.\r
*/\r
case USBFS_GET_STAT:\r
- USBFS_currentTD.wCount = 0u;\r
- requestHandled = USBFS_InitControlWrite();\r
-\r
- #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
-\r
- /* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */\r
+ USBFS_currentTD.wCount = 0u; \r
+ \r
+ requestHandled = USBFS_InitControlWrite();\r
\r
- /* `#END` */\r
+ #endif /* (USBFS_ENABLE_AUDIO_STREAMING) */\r
+ \r
+ /* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */\r
\r
+ /* `#END` */\r
+ \r
#ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_WRITE_REQUESTS_CALLBACK\r
USBFS_DispatchAUDIOClass_AUDIO_WRITE_REQUESTS_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_WRITE_REQUESTS_CALLBACK */\r
-\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_AUDIO_WRITE_REQUESTS_CALLBACK) */\r
break;\r
+ \r
default:\r
+ /* Do not handle this request. */\r
break;\r
}\r
}\r
else\r
- { /* USBFS_RQST_RCPT_OTHER */\r
+ { \r
+ /* Do not handle other requests recipients. */\r
}\r
}\r
else\r
{\r
- /* Control Write */\r
- if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)\r
+ /* Handle direction from host to device. */\r
+ \r
+ if (USBFS_RQST_RCPT_EP == RqstRcpt)\r
{\r
- /* point */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ /* Request recipient is endpoint. */\r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_SET_CUR:\r
#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
- if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)\r
+ if (wValueHi == USBFS_SAMPLING_FREQ_CONTROL)\r
{\r
/* point Control Selector is Sampling Frequency */\r
USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;\r
USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber];\r
+ USBFS_frequencyChanged = (uint8) epNumber;\r
+ \r
requestHandled = USBFS_InitControlWrite();\r
- USBFS_frequencyChanged = epNumber;\r
}\r
- #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
+ #endif /* (USBFS_ENABLE_AUDIO_STREAMING) */\r
\r
- /* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */\r
+ /* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */\r
\r
- /* `#END` */\r
+ /* `#END` */\r
\r
#ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_SAMPLING_FREQ_REQUESTS_CALLBACK\r
USBFS_DispatchAUDIOClass_AUDIO_SAMPLING_FREQ_REQUESTS_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_SAMPLING_FREQ_REQUESTS_CALLBACK */\r
-\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_AUDIO_SAMPLING_FREQ_REQUESTS_CALLBACK) */\r
break;\r
+ \r
default:\r
+ /* Do not handle this request. */\r
break;\r
}\r
}\r
- else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)\r
+ else if(USBFS_RQST_RCPT_IFC == RqstRcpt)\r
{\r
- /* Interface or Entity ID */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ /* Request recipient is interface or entity ID. */\r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_SET_CUR:\r
#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
- if(CY_GET_REG8(USBFS_wValueHi) == USBFS_MUTE_CONTROL)\r
+ if (wValueHi == USBFS_MUTE_CONTROL)\r
{\r
/* `#START MUTE_SET_REQUEST` Place multi-channel handler here */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK\r
- USBFS_DispatchAUDIOClass_MUTE_SET_REQUEST_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK */\r
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK\r
+ USBFS_DispatchAUDIOClass_MUTE_SET_REQUEST_Callback();\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK) */\r
\r
/* Entity ID Control Selector is MUTE */\r
USBFS_currentTD.wCount = 1u;\r
USBFS_currentTD.pData = &USBFS_currentMute;\r
- requestHandled = USBFS_InitControlWrite();\r
+ \r
+ requestHandled = USBFS_InitControlWrite();\r
}\r
- else if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL)\r
+ else if (wValueHi == USBFS_VOLUME_CONTROL)\r
{\r
/* `#START VOLUME_CONTROL_SET_REQUEST` Place multi-channel handler here */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK\r
- USBFS_DispatchAUDIOClass_VOLUME_CONTROL_SET_REQUEST_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK */\r
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK\r
+ USBFS_DispatchAUDIOClass_VOLUME_CONTROL_SET_REQUEST_Callback();\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK) */\r
\r
/* Entity ID Control Selector is VOLUME */\r
USBFS_currentTD.wCount = USBFS_VOLUME_LEN;\r
USBFS_currentTD.pData = USBFS_currentVolume;\r
- requestHandled = USBFS_InitControlWrite();\r
+ \r
+ requestHandled = USBFS_InitControlWrite();\r
}\r
else\r
{\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK\r
- USBFS_DispatchAUDIOClass_OTHER_SET_CUR_REQUESTS_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK */\r
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK\r
+ USBFS_DispatchAUDIOClass_OTHER_SET_CUR_REQUESTS_Callback();\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK) */\r
}\r
#endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
+ \r
+ \r
+ /* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */\r
\r
- /* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */\r
-\r
- /* `#END` */\r
-\r
+ /* `#END` */\r
+ \r
#ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_CONTROL_SEL_REQUESTS_CALLBACK\r
USBFS_DispatchAUDIOClass_AUDIO_CONTROL_SEL_REQUESTS_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_CONTROL_SEL_REQUESTS_CALLBACK */\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_AUDIO_CONTROL_SEL_REQUESTS_CALLBACK) */\r
+ break;\r
\r
- break;\r
default:\r
- break;\r
+ /* Do not handle this request. */\r
+ break;\r
}\r
}\r
else\r
{\r
- /* USBFS_RQST_RCPT_OTHER */\r
+ /* Do not handle other requests recipients. */\r
}\r
}\r
\r
- return(requestHandled);\r
+ return (requestHandled);\r
}\r
-\r
-#endif /* USER_SUPPLIED_AUDIO_HANDLER */\r
+#endif /* (USER_SUPPLIED_AUDIO_HANDLER) */\r
\r
\r
/*******************************************************************************\r
\r
/* `#END` */\r
\r
-#endif /* USBFS_ENABLE_AUDIO_CLASS */\r
+#endif /* (USBFS_ENABLE_AUDIO_CLASS) */\r
\r
\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: USBFS_audio.h\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_audio.h\r
+* \version 3.10\r
*\r
-* Description:\r
-* Header File for the USBFS component. Contains prototypes and constant values.\r
+* \brief\r
+* This file provides function prototypes and constants for the USBFS component \r
+* Audio class.\r
*\r
* Related Document:\r
* Universal Serial Bus Device Class Definition for Audio Devices Release 1.0\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#if !defined(CY_USBFS_USBFS_audio_H)\r
#define CY_USBFS_USBFS_audio_H\r
\r
-#include "cytypes.h"\r
+#include "USBFS.h"\r
\r
\r
/***************************************\r
/***************************************\r
* External data references\r
***************************************/\r
-\r
-extern volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP]\r
- [USBFS_SAMPLE_FREQ_LEN];\r
+/**\r
+* \addtogroup group_audio\r
+* @{\r
+*/\r
+extern volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP][USBFS_SAMPLE_FREQ_LEN];\r
extern volatile uint8 USBFS_frequencyChanged;\r
extern volatile uint8 USBFS_currentMute;\r
extern volatile uint8 USBFS_currentVolume[USBFS_VOLUME_LEN];\r
+/** @} audio */\r
+\r
extern volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN];\r
extern volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN];\r
extern volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN];\r
-/*******************************************************************************\r
-* File Name: USBFS_boot.c\r
-* Version 2.80\r
-*\r
-* Description:\r
-* Boot loader API for USBFS Component.\r
+/***************************************************************************//**\r
+* \file USBFS_boot.c\r
+* \version 3.10\r
*\r
-* Note:\r
+* \brief\r
+* This file contains the Bootloader API for USBFS Component.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
+#include "USBFS_pvt.h"\r
\r
#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \\r
- (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))\r
-\r
+ (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)) \r
\r
/***************************************\r
* Bootloader Variables\r
***************************************/\r
+ \r
\r
static uint8 USBFS_started = 0u;\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_CyBtldrCommStart\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Starts the component and enables the interrupt.\r
+* This function performs all required initialization for the USBFS component, \r
+* waits on enumeration, and enables communication.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* This function starts the USB with 3V or 5V operation.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_CyBtldrCommStart(void) \r
{\r
- CyGlobalIntEnable; /* Enable Global Interrupts */\r
+ /* Enable Global Interrupts. Interrupts are mandatory for USBFS component operation. */\r
+ CyGlobalIntEnable;\r
\r
- /*Start USBFS Operation/device 0 and with 5V or 3V operation depend on Voltage Configuration in DWR */\r
- USBFS_Start(0u, USBFS_DWR_VDDD_OPERATION);\r
+ /* Start USBFS Operation: device 0 and with 5V or 3V operation depend on Voltage Configuration in DWR. */\r
+ USBFS_Start(0u, USBFS_DWR_POWER_OPERATION);\r
\r
- /* USB component started, the correct enumeration will be checked in first Read operation */\r
+ /* USB component started, the correct enumeration will be checked in the first Read operation. */\r
USBFS_started = 1u;\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_CyBtldrCommStop.\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Disable the component and disable the interrupt.\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
+* This function performs all necessary shutdown tasks required for the USBFS \r
+* component.\r
+* \r
+* \sideeffect\r
+* Calls the USBFS_Stop() function.\r
*\r
*******************************************************************************/\r
void USBFS_CyBtldrCommStop(void) \r
\r
/*******************************************************************************\r
* Function Name: USBFS_CyBtldrCommReset.\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Resets the receive and transmit communication Buffers.\r
-*\r
-* Parameters:\r
-* None\r
+****************************************************************************//**\r
*\r
-* Return:\r
-* None\r
+* This function resets receive and transmit communication buffers.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No\r
*\r
*******************************************************************************/\r
void USBFS_CyBtldrCommReset(void) \r
{\r
- USBFS_EnableOutEP(USBFS_BTLDR_OUT_EP); /* Enable the OUT endpoint */\r
+ USBFS_EnableOutEP(USBFS_BTLDR_OUT_EP); \r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_CyBtldrCommWrite.\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Allows the caller to write data to the boot loader host. The function will\r
-* handle polling to allow a block of data to be completely sent to the host\r
+* This function allows the caller to write data to the bootloader host. It \r
+* handles polling to allow a block of data to be completely sent to the host \r
* device.\r
*\r
-* Parameters:\r
-* pData: A pointer to the block of data to send to the device\r
-* size: The number of bytes to write.\r
-* count: Pointer to an unsigned short variable to write the number of\r
-* bytes actually written.\r
-* timeOut: Number of units to wait before returning because of a timeout.\r
+* \param pData A pointer to the block of data to send to the device\r
+* \param size The number of bytes to write.\r
+* \param count Pointer to an unsigned short variable to write the number of\r
+* bytes actually written.\r
+* \param timeOut Number of units to wait before returning because of a timeout.\r
*\r
-* Return:\r
-* Returns the value that best describes the problem.\r
+* \return\r
+* Returns CYRET_SUCCESS if no problem was encountered or returns the value that \r
+* best describes the problem. For more information, see the “Return Codes” \r
+* section of the System Reference Guide.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No\r
*\r
*******************************************************************************/\r
cystatus retCode;\r
uint16 timeoutMs;\r
\r
- timeoutMs = ((uint16) 10u * timeOut); /* Convert from 10mS check to number 1mS checks */\r
+ /* Convert 10mS checks into 1mS checks. */\r
+ timeoutMs = ((uint16) 10u * timeOut);\r
\r
- /* Enable IN transfer */\r
+ /* Load data into IN endpoint to be read by host. */\r
USBFS_LoadInEP(USBFS_BTLDR_IN_EP, pData, USBFS_BTLDR_SIZEOF_READ_BUFFER);\r
\r
- /* Wait for the master to read it. */\r
+ /* Wait unitl host reads data from IN endpoint. */\r
while ((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) &&\r
(0u != timeoutMs))\r
{\r
retCode = CYRET_SUCCESS;\r
}\r
\r
- return(retCode);\r
+ return (retCode);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_CyBtldrCommRead.\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Allows the caller to read data from the boot loader host. The function will\r
-* handle polling to allow a block of data to be completely received from the\r
+* This function allows the caller to read data from the bootloader host. It \r
+* handles polling to allow a block of data to be completely received from the \r
* host device.\r
*\r
-* Parameters:\r
-* pData: A pointer to the area to store the block of data received\r
-* from the device.\r
-* size: The number of bytes to read.\r
-* count: Pointer to an unsigned short variable to write the number\r
-* of bytes actually read.\r
-* timeOut: Number of units to wait before returning because of a timeOut.\r
-* Timeout is measured in 10s of ms.\r
+* \param pData A pointer to the area to store the block of data received\r
+* from the device.\r
+* \param size The number of bytes to read.\r
+* \param count Pointer to an unsigned short variable to write the number\r
+* of bytes actually read.\r
+* \param timeOut Number of units to wait before returning because of a timeOut.\r
+* Timeout is measured in 10s of ms.\r
*\r
-* Return:\r
-* Returns the value that best describes the problem.\r
+* \return\r
+* Returns CYRET_SUCCESS if no problem was encountered or returns the value that \r
+* best describes the problem. For more information, see the “Return Codes” \r
+* section of the System Reference Guide.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No\r
*\r
*******************************************************************************/\r
cystatus retCode;\r
uint16 timeoutMs;\r
\r
- timeoutMs = ((uint16) 10u * timeOut); /* Convert from 10mS check to number 1mS checks */\r
+ /* Convert 10mS checks into 1mS checks. */\r
+ timeoutMs = ((uint16) 10u * timeOut);\r
\r
if (size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)\r
{\r
size = USBFS_BTLDR_SIZEOF_WRITE_BUFFER;\r
}\r
\r
- /* Wait on enumeration in first time */\r
+ /* Wait for enumeration first time. */\r
if (0u != USBFS_started)\r
{\r
- /* Wait for Device to enumerate */\r
- while ((0u ==USBFS_GetConfiguration()) && (0u != timeoutMs))\r
+ /* Wait for device enumeration. */\r
+ while ((0u == USBFS_GetConfiguration()) && (0u != timeoutMs))\r
{\r
CyDelay(USBFS_BTLDR_WAIT_1_MS);\r
timeoutMs--;\r
}\r
\r
- /* Enable first OUT, if enumeration complete */\r
+ /* Enable OUT after enumeration. */\r
if (0u != USBFS_GetConfiguration())\r
{\r
- (void) USBFS_IsConfigurationChanged(); /* Clear configuration changes state status */\r
+ (void) USBFS_IsConfigurationChanged(); /* Clear configuration changes state status. */\r
USBFS_CyBtldrCommReset();\r
+ \r
USBFS_started = 0u;\r
}\r
}\r
- else /* Check for configuration changes, has been done by Host */\r
+ else /* Check for configuration changes, has been done by Host. */\r
{\r
- if (0u != USBFS_IsConfigurationChanged()) /* Host could send double SET_INTERFACE request or RESET */\r
+ if (0u != USBFS_IsConfigurationChanged()) /* Host could send double SET_INTERFACE request or RESET. */\r
{\r
- if (0u != USBFS_GetConfiguration()) /* Init OUT endpoints when device reconfigured */\r
+ if (0u != USBFS_GetConfiguration()) /* Init OUT endpoints when device reconfigured. */\r
{\r
USBFS_CyBtldrCommReset();\r
}\r
\r
timeoutMs = ((uint16) 10u * timeOut); /* Re-arm timeout */\r
\r
- /* Wait on next packet */\r
- while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \\r
- (0u != timeoutMs))\r
+ /* Wait unitl host writes data into OUT endpoint. */\r
+ while ((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \\r
+ (0u != timeoutMs))\r
{\r
CyDelay(USBFS_BTLDR_WAIT_1_MS);\r
timeoutMs--;\r
}\r
\r
- /* OUT EP has completed */\r
+ /* Read data from OUT endpoint if host wrote data into it. */\r
if (USBFS_GetEPState(USBFS_BTLDR_OUT_EP) == USBFS_OUT_BUFFER_FULL)\r
{\r
*count = USBFS_ReadOutEP(USBFS_BTLDR_OUT_EP, pData, size);\r
retCode = CYRET_TIMEOUT;\r
}\r
\r
- return(retCode);\r
+ return (retCode);\r
}\r
\r
-#endif /* CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */\r
+#endif /* (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) */\r
\r
\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: USBFS_cdc.c\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_cdc.c\r
+* \version 3.10\r
*\r
-* Description:\r
-* USB CDC class request handler.\r
+* \brief\r
+* This file contains the USB CDC class request handler.\r
*\r
* Related Document:\r
* Universal Serial Bus Class Definitions for Communication Devices Version 1.1\r
*\r
********************************************************************************\r
-* Copyright 2012-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2012-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
-\r
-#if defined(USBFS_ENABLE_CDC_CLASS)\r
-\r
#include "USBFS_cdc.h"\r
#include "USBFS_pvt.h"\r
\r
\r
+#if defined(USBFS_ENABLE_CDC_CLASS)\r
\r
-/***************************************\r
+/*******************************************************************************\r
* CDC Variables\r
-***************************************/\r
+*******************************************************************************/\r
\r
-volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE] =\r
+/*PUBLIC*/\r
+/** Contains the current line coding structure. The host sets it using a\r
+ * SET_LINE_CODING request and returns it to the user code using the\r
+ * USBFS_GetDTERate(), USBFS_GetCharFormat(),\r
+ * USBFS_GetParityType(), and USBFS_GetDataBits() APIs.\r
+ * It is an array of 2 elements for COM port 1 and COM port 2 for MultiCOM port\r
+ * support. In case of 1 COM port, data is in 0 element.*/\r
+volatile uint8 USBFS_linesCoding[USBFS_MAX_MULTI_COM_NUM][USBFS_LINE_CODING_SIZE] =\r
{\r
+ /*COM Port 1*/\r
+ {\r
+ 0x00u, 0xC2u, 0x01u, 0x00u, /* Data terminal rate 115200 */\r
+ 0x00u, /* 1 Stop bit */\r
+ 0x00u, /* None parity */\r
+ 0x08u /* 8 data bits */\r
+ },\r
+ /*COM Port 2*/\r
+ {\r
0x00u, 0xC2u, 0x01u, 0x00u, /* Data terminal rate 115200 */\r
0x00u, /* 1 Stop bit */\r
0x00u, /* None parity */\r
0x08u /* 8 data bits */\r
+ }\r
};\r
-volatile uint8 USBFS_lineChanged;\r
-volatile uint16 USBFS_lineControlBitmap;\r
-volatile uint8 USBFS_cdc_data_in_ep;\r
-volatile uint8 USBFS_cdc_data_out_ep;\r
+\r
+/**Used as a flag for the USBFS_IsLineChanged() API, to inform it that the\r
+ * host has been sent a request to change line coding or control bitmap. It is \r
+ * an array of 2 elements for COM port 1 and COM port 2 for MultiCOM port \r
+ * support. In case of 1 COM port, data is in 0 element.*/\r
+volatile uint8 USBFS_linesChanged[USBFS_MAX_MULTI_COM_NUM];\r
+/** Contains the current control-signal bitmap. The host sets it using a\r
+ * SET_CONTROL_LINE request and returns it to the user code using the \r
+ * USBFS_GetLineControl() API. It is an array of 2 elements for COM \r
+ * port 1 and COM port 2 for MultiCOM port support. In case of 1 COM port, data \r
+ * is in 0 element.*/\r
+volatile uint16 USBFS_linesControlBitmap[USBFS_MAX_MULTI_COM_NUM];\r
+/** Contains the 16-bit serial state value that was sent using the \r
+ * \ref USBFS_SendSerialState() API. . It is an array of 2 elements \r
+ * for COM port 1 and COM port 2 for MultiCOM port support. In case of 1 COM \r
+ * port, data is in 0 element.*/\r
+volatile uint16 USBFS_serialStateBitmap[USBFS_MAX_MULTI_COM_NUM];\r
+/** Contains the data IN endpoint number. It is initialized after a \r
+ * SET_CONFIGURATION request based on a user descriptor. It is used in CDC APIs \r
+ * to send data to the PC. It is an array of 2 elements for COM port 1 and COM \r
+ * port 2 for MultiCOM port support. In case of 1 COM port, data is in 0 element.*/\r
+volatile uint8 USBFS_cdcDataInEp[USBFS_MAX_MULTI_COM_NUM];\r
+/** Contains the data OUT endpoint number. It is initialized after a \r
+ * SET_CONFIGURATION request based on user descriptor. It is used in CDC APIs to \r
+ * receive data from the PC. It is an array of 2 elements for COM port 1 and COM \r
+ * port 2 for MultiCOM port support. In case of 1 COM port, data is in 0 element.*/\r
+volatile uint8 USBFS_cdcDataOutEp[USBFS_MAX_MULTI_COM_NUM];\r
+/** Contains the data IN endpoint number for COMMUNICATION interface. It is \r
+ * initialized after a SET_CONFIGURATION request based on a user descriptor. It \r
+ * is used in CDC APIs to send data to the PC. It is an array of 2 elements for \r
+ * COM port 1 and COM port 2 for MultiCOM port support. In case of 1 COM port, \r
+ * data is in 0 element.*/\r
+volatile uint8 USBFS_cdcCommInInterruptEp[USBFS_MAX_MULTI_COM_NUM];\r
+\r
+/*PRIVATE*/\r
+\r
+#define USBFS_CDC_IN_EP (0u)\r
+#define USBFS_CDC_OUT_EP (1u)\r
+#define USBFS_CDC_NOTE_EP (2u)\r
+\r
+#define USBFS_CDC_EP_MASK (0x01u)\r
+\r
+#define USBFS_GET_EP_COM_NUM(cdcComNums, epType) (((cdcComNums) >> (epType)) & USBFS_CDC_EP_MASK)\r
\r
\r
/***************************************\r
***************************************/\r
#if (USBFS_ENABLE_CDC_CLASS_API != 0u)\r
static uint16 USBFS_StrLen(const char8 string[]) ;\r
+ static t_USBFS_cdc_notification USBFS_serialStateNotification =\r
+ {\r
+\r
+ USBFS_SERIAL_STATE_REQUEST_TYPE, /* bRequestType */\r
+ USBFS_SERIAL_STATE, /* bNotification */\r
+ 0u, /* wValue */\r
+ 0u, /* wValueMSB */\r
+ 0u, /* wIndex */\r
+ 0u, /* wIndexMSB */\r
+ USBFS_SERIAL_STATE_LENGTH, /* wLength */\r
+ 0u, /* wLengthMSB */\r
+ 0u, /* wSerialState */\r
+ 0u, /* wSerialStateMSB */\r
+ };\r
+ static uint8 USBFS_activeCom = 0u;\r
#endif /* (USBFS_ENABLE_CDC_CLASS_API != 0u) */\r
\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_DispatchCDCClassRqst\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine dispatches CDC class requests.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled\r
*\r
-* Global variables:\r
-* USBFS_lineCoding: Contains the current line coding structure.\r
+* \globalvars\r
+* USBFS_linesCoding: Contains the current line coding structure.\r
* It is set by the Host using SET_LINE_CODING request and returned to the\r
* user code by the USBFS_GetDTERate(), USBFS_GetCharFormat(),\r
* USBFS_GetParityType(), USBFS_GetDataBits() APIs.\r
-* USBFS_lineControlBitmap: Contains the current control signal\r
+* USBFS_linesControlBitmap: Contains the current control signal\r
* bitmap. It is set by the Host using SET_CONTROL_LINE request and returned\r
* to the user code by the USBFS_GetLineControl() API.\r
-* USBFS_lineChanged: This variable is used as a flag for the\r
+* USBFS_linesChanged: This variable is used as a flag for the\r
* USBFS_IsLineChanged() API, to be aware that Host has been sent request\r
* for changing Line Coding or Control Bitmap.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_DispatchCDCClassRqst(void) \r
{\r
uint8 requestHandled = USBFS_FALSE;\r
+ uint8 comPort;\r
+\r
+ comPort = USBFS_GetInterfaceComPort((uint8)USBFS_wIndexLoReg);\r
\r
- if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)\r
- { /* Control Read */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ /* Check request direction: D2H or H2D. */\r
+ if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H))\r
+ {\r
+ /* Handle direction from device to host. */\r
+\r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_CDC_GET_LINE_CODING:\r
USBFS_currentTD.count = USBFS_LINE_CODING_SIZE;\r
- USBFS_currentTD.pData = USBFS_lineCoding;\r
+ USBFS_currentTD.pData = USBFS_linesCoding[comPort];\r
requestHandled = USBFS_InitControlRead();\r
break;\r
\r
\r
/* `#END` */\r
\r
+ default:\r
+ /* Do not handle this request unless callback is defined. */\r
#ifdef USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK\r
- USBFS_DispatchCDCClass_CDC_READ_REQUESTS_Callback();\r
- #endif /* USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK */\r
-\r
- default: /* requestHandled is initialized as FALSE by default */\r
+ requestHandled = USBFS_DispatchCDCClass_CDC_READ_REQUESTS_Callback();\r
+ #endif /* (USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK) */\r
break;\r
}\r
}\r
- else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \\r
- USBFS_RQST_DIR_H2D)\r
- { /* Control Write */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ else\r
+ {\r
+ /* Handle direction from host to device. */\r
+\r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_CDC_SET_LINE_CODING:\r
- USBFS_currentTD.count = USBFS_LINE_CODING_SIZE;\r
- USBFS_currentTD.pData = USBFS_lineCoding;\r
- USBFS_lineChanged |= USBFS_LINE_CODING_CHANGED;\r
+ USBFS_currentTD.count = USBFS_LINE_CODING_SIZE;\r
+ USBFS_currentTD.pData = USBFS_linesCoding[comPort];\r
+ USBFS_linesChanged[comPort] |= USBFS_LINE_CODING_CHANGED;\r
+\r
requestHandled = USBFS_InitControlWrite();\r
break;\r
\r
case USBFS_CDC_SET_CONTROL_LINE_STATE:\r
- USBFS_lineControlBitmap = CY_GET_REG8(USBFS_wValueLo);\r
- USBFS_lineChanged |= USBFS_LINE_CONTROL_CHANGED;\r
+ USBFS_linesControlBitmap[comPort] = (uint8) USBFS_wValueLoReg;\r
+ USBFS_linesChanged[comPort] |= USBFS_LINE_CONTROL_CHANGED;\r
+\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
break;\r
\r
\r
/* `#END` */\r
\r
+ default:\r
+ /* Do not handle this request unless callback is defined. */\r
#ifdef USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK\r
- USBFS_DispatchCDCClass_CDC_WRITE_REQUESTS_Callback();\r
- #endif /* USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK */\r
-\r
- default: /* requestHandled is initialized as FALSE by default */\r
+ requestHandled = USBFS_DispatchCDCClass_CDC_WRITE_REQUESTS_Callback();\r
+ #endif /* (USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK) */\r
break;\r
}\r
}\r
- else\r
- { /* requestHandled is initialized as FALSE by default */\r
- }\r
\r
return(requestHandled);\r
}\r
\r
\r
+/***************************************************************************\r
+* Function Name: USBFS_GetInterfaceComPort\r
+************************************************************************//**\r
+* \internal\r
+* Internal function which gets number of COM port by specified interface\r
+* number.\r
+*\r
+* \param uint8 interface\r
+* Interface number\r
+*\r
+* \return\r
+* COM port number (0 or 1) or error 0xFF\r
+*\r
+***************************************************************************/\r
+uint8 USBFS_GetInterfaceComPort(uint8 interface) \r
+{\r
+ uint8 comPort = 0u;\r
+ uint8 res = 0xFFu;\r
+ uint8 notEp;\r
+\r
+ while (comPort < USBFS_MAX_MULTI_COM_NUM)\r
+ {\r
+ notEp = USBFS_cdcCommInInterruptEp[comPort];\r
+\r
+ if (USBFS_EP[notEp].interface == interface)\r
+ {\r
+ res = comPort;\r
+ comPort = USBFS_MAX_MULTI_COM_NUM;\r
+ }\r
+\r
+ comPort++;\r
+ }\r
+ return (res);\r
+}\r
+\r
+\r
/***************************************\r
* Optional CDC APIs\r
***************************************/\r
#if (USBFS_ENABLE_CDC_CLASS_API != 0u)\r
+/***************************************************************************\r
+* Function Name: USBFS_CDC_Init\r
+************************************************************************//**\r
+*\r
+* This function initializes the CDC interface to be ready to receive data\r
+* from the PC. The API set active communication port to 0 in the case of \r
+* multiple communication port support.This API should be called after the \r
+* device has been started and configured using USBUART_Start() API to \r
+* initialize and start the USBFS component operation. Then call the \r
+* USBUART_GetConfiguration() API to wait until the host has enumerated and \r
+* configured the device. For example:\r
+*\r
+* \snippet /USBFS_sut_02.cydsn/main.c wait for enumeration\r
+*\r
+* \return\r
+* cystatus:\r
+* Return Value Description\r
+* USBFS_SUCCESS CDC interface was initialized correctly\r
+* USBFS_FAILURE CDC interface was not initialized\r
+*\r
+* \globalvars\r
+* USBFS_linesChanged: Initialized to zero.\r
+* USBFS_cdcDataOutEp: Used as an OUT endpoint number.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_CDC_Init(void) \r
+{\r
+ uint8 comPort;\r
+ uint8 outEp;\r
+ uint8 ret = USBFS_SUCCESS;\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_CDC_Init\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function initialize the CDC interface to be ready for the receive data\r
- * from the PC.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Global variables:\r
- * USBFS_lineChanged: Initialized to zero.\r
- * USBFS_cdc_data_out_ep: Used as an OUT endpoint number.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- void USBFS_CDC_Init(void) \r
- {\r
- USBFS_lineChanged = 0u;\r
- USBFS_EnableOutEP(USBFS_cdc_data_out_ep);\r
- }\r
-\r
+ USBFS_activeCom = 0u;\r
+ USBFS_linesChanged[USBFS_COM_PORT1] = 0u;\r
+ USBFS_linesChanged[USBFS_COM_PORT2] = 0u;\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_PutData\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function sends a specified number of bytes from the location specified\r
- * by a pointer to the PC. The USBFS_CDCIsReady() function should be\r
- * called before sending new data, to be sure that the previous data has\r
- * finished sending.\r
- * If the last sent packet is less than maximum packet size the USB transfer\r
- * of this short packet will identify the end of the segment. If the last sent\r
- * packet is exactly maximum packet size, it shall be followed by a zero-length\r
- * packet (which is a short packet) to assure the end of segment is properly\r
- * identified. To send zero-length packet, use USBFS_PutData() API\r
- * with length parameter set to zero.\r
- *\r
- * Parameters:\r
- * pData: pointer to the buffer containing data to be sent.\r
- * length: Specifies the number of bytes to send from the pData\r
- * buffer. Maximum length will be limited by the maximum packet\r
- * size for the endpoint. Data will be lost if length is greater than Max\r
- * Packet Size.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending\r
- * data.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- void USBFS_PutData(const uint8* pData, uint16 length) \r
+ for(comPort = 0u; comPort<USBFS_MAX_MULTI_COM_NUM; comPort++)\r
{\r
- /* Limits length to maximum packet size for the EP */\r
- if(length > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize)\r
+ outEp = USBFS_cdcDataOutEp[comPort];\r
+ if((0u != outEp) && (USBFS_MAX_EP > outEp))\r
{\r
- /* Caution: Data will be lost if length is greater than Max Packet Length */\r
- length = USBFS_EP[USBFS_cdc_data_in_ep].bufferSize;\r
- /* Halt CPU in debug mode */\r
- CYASSERT(0u != 0u);\r
+ USBFS_EnableOutEP(outEp);\r
}\r
- USBFS_LoadInEP(USBFS_cdc_data_in_ep, pData, length);\r
- }\r
\r
+ }\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_StrLen\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Calculates length of a null terminated string.\r
- *\r
- * Parameters:\r
- * string: pointer to the string.\r
- *\r
- * Return:\r
- * Length of the string\r
- *\r
- *******************************************************************************/\r
- static uint16 USBFS_StrLen(const char8 string[]) \r
+ /* COM Port 1 should be correct to proceed. */\r
+ if ((0u == USBFS_cdcDataInEp[USBFS_COM_PORT1]) \\r
+ || (0u == USBFS_cdcDataOutEp[USBFS_COM_PORT1]) \\r
+ || (0u == USBFS_cdcCommInInterruptEp[USBFS_COM_PORT1])\r
+ || (USBFS_cdcDataInEp[USBFS_COM_PORT1] >= USBFS_MAX_EP)\r
+ || (USBFS_cdcDataOutEp[USBFS_COM_PORT1] >= USBFS_MAX_EP)\r
+ || (USBFS_cdcCommInInterruptEp[USBFS_COM_PORT1] >= USBFS_MAX_EP))\r
{\r
- uint16 len = 0u;\r
+ ret = USBFS_FAILURE;\r
+ }\r
\r
- while (string[len] != (char8)0)\r
- {\r
- len++;\r
- }\r
+ return (ret);\r
+}\r
\r
- return (len);\r
- }\r
\r
+/*******************************************************************************\r
+* Function Name: USBFS_PutData\r
+****************************************************************************//**\r
+*\r
+* This function sends a specified number of bytes from the location specified\r
+* by a pointer to the PC. The USBFS_CDCIsReady() function should be\r
+* called before sending new data, to be sure that the previous data has\r
+* finished sending.\r
+* If the last sent packet is less than maximum packet size the USB transfer\r
+* of this short packet will identify the end of the segment. If the last sent\r
+* packet is exactly maximum packet size, it shall be followed by a zero-length\r
+* packet (which is a short packet) to assure the end of segment is properly\r
+* identified. To send zero-length packet, use USBFS_PutData() API\r
+* with length parameter set to zero.\r
+*\r
+* \param pData: pointer to the buffer containing data to be sent.\r
+* \param length: Specifies the number of bytes to send from the pData\r
+* buffer. Maximum length will be limited by the maximum packet\r
+* size for the endpoint. Data will be lost if length is greater than Max\r
+* Packet Size.\r
+*\r
+* \globalvars\r
+*\r
+* USBFS_cdcDataInEp: CDC IN endpoint number used for sending\r
+* data.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void USBFS_PutData(const uint8* pData, uint16 length) \r
+{\r
+ uint8 epNumber = USBFS_cdcDataInEp[USBFS_activeCom];\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_PutString\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function sends a null terminated string to the PC. This function will\r
- * block if there is not enough memory to place the whole string. It will block\r
- * until the entire string has been written to the transmit buffer.\r
- * The USBUART_CDCIsReady() function should be called before sending data with\r
- * a new call to USBFS_PutString(), to be sure that the previous data\r
- * has finished sending.\r
- *\r
- * Parameters:\r
- * string: pointer to the string to be sent to the PC.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending\r
- * data.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- void USBFS_PutString(const char8 string[]) \r
+ /* Limit length to maximum packet size for endpoint. */\r
+ if (length > USBFS_EP[epNumber].bufferSize)\r
{\r
- uint16 strLength;\r
- uint16 sendLength;\r
- uint16 bufIndex = 0u;\r
+ /* Caution: Data will be lost if length is greater than Max Packet Size. */\r
+ length = USBFS_EP[epNumber].bufferSize;\r
\r
- /* Get length of the null terminated string */\r
- strLength = USBFS_StrLen(string);\r
- do\r
- {\r
- /* Limits length to maximum packet size for the EP */\r
- sendLength = (strLength > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?\r
- USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : strLength;\r
- /* Enable IN transfer */\r
- USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[bufIndex], sendLength);\r
- strLength -= sendLength;\r
-\r
- /* If more data are present to send or full packet was sent */\r
- if((strLength > 0u) || (sendLength == USBFS_EP[USBFS_cdc_data_in_ep].bufferSize))\r
- {\r
- bufIndex += sendLength;\r
- /* Wait for the Host to read it. */\r
- while(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState ==\r
- USBFS_IN_BUFFER_FULL)\r
- {\r
- ;\r
- }\r
- /* If the last sent packet is exactly maximum packet size,\r
- * it shall be followed by a zero-length packet to assure the\r
- * end of segment is properly identified by the terminal.\r
- */\r
- if(strLength == 0u)\r
- {\r
- USBFS_LoadInEP(USBFS_cdc_data_in_ep, NULL, 0u);\r
- }\r
- }\r
- }while(strLength > 0u);\r
+ /* Halt CPU in debug mode */\r
+ CYASSERT(0u != 0u);\r
}\r
\r
+ USBFS_LoadInEP(epNumber, pData, length);\r
+}\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_PutChar\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Writes a single character to the PC.\r
- *\r
- * Parameters:\r
- * txDataByte: Character to be sent to the PC.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending\r
- * data.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- void USBFS_PutChar(char8 txDataByte) \r
- {\r
- uint8 dataByte;\r
- dataByte = (uint8)txDataByte;\r
\r
- USBFS_LoadInEP(USBFS_cdc_data_in_ep, &dataByte, 1u);\r
+/*******************************************************************************\r
+* Function Name: USBFS_StrLen\r
+****************************************************************************//**\r
+*\r
+* Calculates length of a null terminated string.\r
+*\r
+* \param string: pointer to the string.\r
+*\r
+* \return\r
+* Length of the string\r
+*\r
+*******************************************************************************/\r
+static uint16 USBFS_StrLen(const char8 string[]) \r
+{\r
+ uint16 len = 0u;\r
+\r
+ while (string[len] != (char8)0)\r
+ {\r
+ len++;\r
}\r
\r
+ return ((uint16) len);\r
+}\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_PutCRLF\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Sends a carriage return (0x0D) and line feed (0x0A) to the PC\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending\r
- * data.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- void USBFS_PutCRLF(void) \r
- {\r
- const uint8 CYCODE txData[] = {0x0Du, 0x0Au};\r
\r
- USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)txData, 2u);\r
- }\r
+/***************************************************************************\r
+* Function Name: USBFS_PutString\r
+************************************************************************//**\r
+*\r
+* This function sends a null terminated string to the PC. This function will\r
+* block if there is not enough memory to place the whole string. It will block\r
+* until the entire string has been written to the transmit buffer.\r
+* The USBFS_CDCIsReady() function should be called before\r
+* sending data with a new call to USBFS_PutString(), to be sure\r
+* that the previous data has finished sending. This function sends\r
+* zero-length packet automatically, if the length of the last packet, sent\r
+* by this API, is equal to Max Packet Size\r
+*\r
+* \param string: pointer to the string to be sent to the PC.\r
+*\r
+* \globalvars\r
+*\r
+* USBFS_cdcDataInEp: CDC IN endpoint number used for sending\r
+* data.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+***************************************************************************/\r
+void USBFS_PutString(const char8 string[]) \r
+{\r
+ uint16 strLength;\r
+ uint16 sendLength;\r
+ uint16 bufIndex = 0u;\r
+\r
+ uint8 epNumber = USBFS_cdcDataInEp[USBFS_activeCom];\r
\r
+ /* Get length string length (it is terminated with zero). */\r
+ strLength = USBFS_StrLen(string);\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetCount\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function returns the number of bytes that were received from the PC.\r
- * The returned length value should be passed to USBFS_GetData() as\r
- * a parameter to read all received data. If all of the received data is not\r
- * read at one time by the USBFS_GetData() API, the unread data will\r
- * be lost.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns the number of received bytes. The maximum amount of received data at\r
- * a time is limited by the maximum packet size for the endpoint.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_out_ep: CDC OUT endpoint number used.\r
- *\r
- *******************************************************************************/\r
- uint16 USBFS_GetCount(void) \r
+ do\r
{\r
- uint16 bytesCount;\r
+ /* Limit length to maximum packet size of endpoint. */\r
+ sendLength = (strLength > USBFS_EP[epNumber].bufferSize) ?\r
+ USBFS_EP[epNumber].bufferSize : strLength;\r
\r
- if (USBFS_EP[USBFS_cdc_data_out_ep].apiEpState == USBFS_OUT_BUFFER_FULL)\r
- {\r
- bytesCount = USBFS_GetEPCount(USBFS_cdc_data_out_ep);\r
- }\r
- else\r
+ /* Load IN endpoint and expose it to host. */\r
+ USBFS_LoadInEP(epNumber, (const uint8 *)&string[bufIndex], sendLength);\r
+ strLength -= sendLength;\r
+\r
+ /* If more data are present to send or full packet was sent */\r
+ if ((strLength > 0u) || (sendLength == USBFS_EP[epNumber].bufferSize))\r
{\r
- bytesCount = 0u;\r
- }\r
+ bufIndex += sendLength;\r
\r
- return(bytesCount);\r
+ /* Wait until host read data from IN endpoint buffer. */\r
+ while (USBFS_IN_BUFFER_FULL == USBFS_EP[epNumber].apiEpState)\r
+ {\r
+ }\r
+\r
+ /* If last packet is exactly maximum packet size, it shall be followed\r
+ * by a zero-length packet to assure the end of segment is properly\r
+ * identified by the terminal.\r
+ */\r
+ if (0u == strLength)\r
+ {\r
+ USBFS_LoadInEP(epNumber, NULL, 0u);\r
+ }\r
+ }\r
}\r
+ while (strLength > 0u);\r
+}\r
+\r
+\r
+/***************************************************************************\r
+* Function Name: USBFS_PutChar\r
+************************************************************************//**\r
+*\r
+* This function writes a single character to the PC at a time. This is an\r
+* inefficient way to send large amounts of data.\r
+*\r
+* \param txDataByte: Character to be sent to the PC.\r
+*\r
+* \globalvars\r
+*\r
+* USBFS_cdcDataInEp: CDC IN endpoint number used for sending\r
+* data.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+***************************************************************************/\r
+void USBFS_PutChar(char8 txDataByte) \r
+{\r
+ uint8 dataByte;\r
+ dataByte = (uint8) txDataByte;\r
+\r
+ USBFS_LoadInEP(USBFS_cdcDataInEp[USBFS_activeCom], &dataByte, 1u);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_PutCRLF\r
+****************************************************************************//**\r
+*\r
+* This function sends a carriage return (0x0D) and line feed (0x0A) to the\r
+* PC. This APIis provided to mimic API provided by our other UART components\r
+*\r
+* \globalvars\r
+*\r
+* USBFS_cdcDataInEp: CDC IN endpoint number used for sending\r
+* data.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void USBFS_PutCRLF(void) \r
+{\r
+ const uint8 CYCODE txData[] = {0x0Du, 0x0Au};\r
+\r
+ USBFS_LoadInEP(USBFS_cdcDataInEp[USBFS_activeCom], (const uint8 *)txData, 2u);\r
+}\r
+\r
\r
+/*******************************************************************************\r
+* Function Name: USBFS_GetCount\r
+****************************************************************************//**\r
+*\r
+* This function returns the number of bytes that were received from the PC.\r
+* The returned length value should be passed to USBFS_GetData() as\r
+* a parameter to read all received data. If all of the received data is not\r
+* read at one time by the USBFS_GetData() API, the unread data will\r
+* be lost.\r
+*\r
+* \return\r
+* Returns the number of received bytes. The maximum amount of received data at\r
+* a time is limited by the maximum packet size for the endpoint.\r
+*\r
+* \globalvars\r
+* USBFS_cdcDataOutEp: CDC OUT endpoint number used.\r
+*\r
+*******************************************************************************/\r
+uint16 USBFS_GetCount(void) \r
+{\r
+ uint16 bytesCount;\r
+\r
+ uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom];\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_DataIsReady\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns a nonzero value if the component received data or received\r
- * zero-length packet. The USBFS_GetAll() or\r
- * USBFS_GetData() API should be called to read data from the buffer\r
- * and re-init OUT endpoint even when zero-length packet received.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * If the OUT packet received this function returns a nonzero value.\r
- * Otherwise zero is returned.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_out_ep: CDC OUT endpoint number used.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_DataIsReady(void) \r
+ if (USBFS_OUT_BUFFER_FULL == USBFS_EP[epNumber].apiEpState)\r
+ {\r
+ bytesCount = USBFS_GetEPCount(epNumber);\r
+ }\r
+ else\r
{\r
- return(USBFS_EP[USBFS_cdc_data_out_ep].apiEpState);\r
+ bytesCount = 0u;\r
}\r
\r
+ return (bytesCount);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_DataIsReady\r
+****************************************************************************//**\r
+*\r
+* This function returns a non-zero value if the component received data or\r
+* received zero-length packet. The USBFS_GetAll() or\r
+* USBFS_GetData() API should be called to read data from the buffer\r
+* and reinitialize the OUT endpoint even when a zero-length packet is\r
+* received. These APIs will return zero value when zero-length packet is\r
+* received.\r
+*\r
+* \return\r
+* If the OUT packet is received, this function returns a non-zero value.\r
+* Otherwise, it returns zero.\r
+*\r
+* \globalvars\r
+* USBFS_cdcDataOutEp: CDC OUT endpoint number used.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_DataIsReady(void) \r
+{\r
+ return (USBFS_GetEPState(USBFS_cdcDataOutEp[USBFS_activeCom]));\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_CDCIsReady\r
+****************************************************************************//**\r
+*\r
+* This function returns a non-zero value if the component is ready to send more\r
+* data to the PC; otherwise, it returns zero. The function should be called\r
+* before sending new data when using any of the following APIs:\r
+* USBFS_PutData(),USBFS_PutString(),\r
+* USBFS_PutChar or USBFS_PutCRLF(),\r
+* to be sure that the previous data has finished sending.\r
+*\r
+* \return\r
+* If the buffer can accept new data, this function returns a non-zero value.\r
+* Otherwise, it returns zero.\r
+*\r
+* \globalvars\r
+* USBFS_cdcDataInEp: CDC IN endpoint number used.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_CDCIsReady(void) \r
+{\r
+ return (USBFS_GetEPState(USBFS_cdcDataInEp[USBFS_activeCom]));\r
+}\r
+\r
+\r
+/***************************************************************************\r
+* Function Name: USBFS_GetData\r
+************************************************************************//**\r
+*\r
+* This function gets a specified number of bytes from the input buffer and\r
+* places them in a data array specified by the passed pointer.\r
+* The USBFS_DataIsReady() API should be called first, to be sure\r
+* that data is received from the host. If all received data will not be read at\r
+* once, the unread data will be lost. The USBFS_GetData() API should\r
+* be called to get the number of bytes that were received.\r
+*\r
+* \param pData: Pointer to the data array where data will be placed.\r
+* \param Length: Number of bytes to read into the data array from the RX buffer.\r
+* Maximum length is limited by the the number of received bytes\r
+* or 64 bytes.\r
+*\r
+* \return\r
+* Number of bytes which function moves from endpoint RAM into the\r
+* data array. The function moves fewer than the requested number\r
+* of bytes if the host sends fewer bytes than requested or sends\r
+* zero-length packet.\r
+*\r
+* \globalvars\r
+* USBFS_cdcDataOutEp: CDC OUT endpoint number used.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+***************************************************************************/\r
+uint16 USBFS_GetData(uint8* pData, uint16 length) \r
+{\r
+ uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom];\r
+\r
+ /* Read data from OUT endpoint buffer. */\r
+ length = USBFS_ReadOutEP(epNumber, pData, length);\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_CDCIsReady\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function returns a nonzero value if the component is ready to send more\r
- * data to the PC; otherwise, it returns zero. The function should be called\r
- * before sending new data when using any of the following APIs:\r
- * USBFS_PutData(),USBFS_PutString(),\r
- * USBFS_PutChar or USBFS_PutCRLF(),\r
- * to be sure that the previous data has finished sending.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * If the buffer can accept new data, this function returns a nonzero value.\r
- * Otherwise, it returns zero.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_in_ep: CDC IN endpoint number used.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_CDCIsReady(void) \r
+#if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ /* Wait until DMA complete transferring data from OUT endpoint buffer. */\r
+ while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(epNumber))\r
{\r
- return(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState);\r
}\r
\r
+ /* Enable OUT endpoint to communicate with host. */\r
+ USBFS_EnableOutEP(epNumber);\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
+\r
+ return (length);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_GetAll\r
+****************************************************************************//**\r
+*\r
+* This function gets all bytes of received data from the input buffer and\r
+* places them into a specified data array. The\r
+* USBFS_DataIsReady() API should be called first, to be sure\r
+* that data is received from the host.\r
+*\r
+* \param pData: Pointer to the data array where data will be placed.\r
+*\r
+* \return\r
+* Number of bytes received. The maximum amount of the received at a time\r
+* data is 64 bytes.\r
+*\r
+* \globalvars\r
+* - \ref USBFS_cdcDataOutEp: CDC OUT endpoint number used.\r
+* - \ref USBFS_EP[].bufferSize: EP max packet size is used as a\r
+* length to read all data from the EP buffer.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+*******************************************************************************/\r
+uint16 USBFS_GetAll(uint8* pData) \r
+{\r
+ uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom];\r
+ uint16 dataLength;\r
+\r
+ /* Read data from OUT endpoint buffer. */\r
+ dataLength = USBFS_ReadOutEP(epNumber, pData, USBFS_EP[epNumber].bufferSize);\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetData\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function gets a specified number of bytes from the input buffer and\r
- * places them in a data array specified by the passed pointer.\r
- * The USBFS_DataIsReady() API should be called first, to be sure\r
- * that data is received from the host. If all received data will not be read at\r
- * once, the unread data will be lost. The USBFS_GetData() API should\r
- * be called to get the number of bytes that were received.\r
- *\r
- * Parameters:\r
- * pData: Pointer to the data array where data will be placed.\r
- * Length: Number of bytes to read into the data array from the RX buffer.\r
- * Maximum length is limited by the the number of received bytes.\r
- *\r
- * Return:\r
- * Number of bytes received.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_out_ep: CDC OUT endpoint number used.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- uint16 USBFS_GetData(uint8* pData, uint16 length) \r
+#if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ /* Wait until DMA complete transferring data from OUT endpoint buffer. */\r
+ while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(epNumber))\r
{\r
- return(USBFS_ReadOutEP(USBFS_cdc_data_out_ep, pData, length));\r
}\r
\r
+ /* Enable OUT endpoint to communicate with host. */\r
+ USBFS_EnableOutEP(epNumber);\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
+\r
+ return (dataLength);\r
+}\r
+\r
+\r
+/***************************************************************************\r
+* Function Name: USBFS_GetChar\r
+************************************************************************//**\r
+*\r
+* This function reads one byte of received data from the buffer. If more than\r
+* one byte has been received from the host, the rest of the data will be lost.\r
+*\r
+* \return\r
+* Received one character.\r
+*\r
+* \globalvars\r
+* USBFS_cdcDataOutEp: CDC OUT endpoint number used.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+***************************************************************************/\r
+uint8 USBFS_GetChar(void) \r
+{\r
+ uint8 rxData;\r
+ uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom];\r
+\r
+ (void) USBFS_ReadOutEP(epNumber, &rxData, 1u);\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetAll\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Gets all bytes of received data from the input buffer and places it into a\r
- * specified data array. USBFS_DataIsReady() API should be called\r
- * before, to be sure that data is received from the Host.\r
- *\r
- * Parameters:\r
- * pData: Pointer to the data array where data will be placed.\r
- *\r
- * Return:\r
- * Number of bytes received.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_out_ep: CDC OUT endpoint number used.\r
- * USBFS_EP[].bufferSize: EP max packet size is used as a length\r
- * to read all data from the EP buffer.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- uint16 USBFS_GetAll(uint8* pData) \r
+#if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ /* Wait until DMA complete transferring data from OUT endpoint buffer. */\r
+ while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(epNumber))\r
{\r
- return (USBFS_ReadOutEP(USBFS_cdc_data_out_ep, pData,\r
- USBFS_EP[USBFS_cdc_data_out_ep].bufferSize));\r
}\r
\r
+ /* Enable OUT endpoint to communicate with host. */\r
+ USBFS_EnableOutEP(epNumber);\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetChar\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function reads one byte of received data from the buffer. If more than\r
- * one byte has been received from the host, the rest of the data will be lost.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Received one character.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_out_ep: CDC OUT endpoint number used.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_GetChar(void) \r
- {\r
- uint8 rxData;\r
+ return (rxData);\r
+}\r
\r
- (void) USBFS_ReadOutEP(USBFS_cdc_data_out_ep, &rxData, 1u);\r
\r
- return(rxData);\r
- }\r
+/*******************************************************************************\r
+* Function Name: USBFS_IsLineChanged\r
+****************************************************************************//**\r
+*\r
+* This function returns clear on read status of the line. It returns not zero\r
+* value when the host sends updated coding or control information to the\r
+* device. The USBFS_GetDTERate(), USBFS_GetCharFormat()\r
+* or USBFS_GetParityType() or USBFS_GetDataBits() API\r
+* should be called to read data coding information.\r
+* The USBFS_GetLineControl() API should be called to read line\r
+* control information.\r
+*\r
+* \return\r
+* If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE requests are received, it\r
+* returns a non-zero value. Otherwise, it returns zero.\r
+* Return Value | Description\r
+* -----------------------------|--------------------------\r
+* USBUART_LINE_CODING_CHANGED | Line coding changed\r
+* USBUART_LINE_CONTROL_CHANGED | Line control changed\r
+*\r
+* \globalvars\r
+* - \ref USBFS_transferState: it is checked to be sure then OUT\r
+* data phase has been complete, and data written to the lineCoding or\r
+* Control Bitmap buffer.\r
+* - \ref USBFS_linesChanged: used as a flag to be aware that\r
+* Host has been sent request for changing Line Coding or Control Bitmap.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_IsLineChanged(void) \r
+{\r
+ uint8 state = 0u;\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_IsLineChanged\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function returns clear on read status of the line. It returns not zero\r
- * value when the host sends updated coding or control information to the\r
- * device. The USBFS_GetDTERate(), USBFS_GetCharFormat()\r
- * or USBFS_GetParityType() or USBFS_GetDataBits() API\r
- * should be called to read data coding information.\r
- * The USBFS_GetLineControl() API should be called to read line\r
- * control information.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE requests are received, it\r
- * returns a nonzero value. Otherwise, it returns zero.\r
- *\r
- * Global variables:\r
- * USBFS_transferState: it is checked to be sure then OUT data\r
- * phase has been complete, and data written to the lineCoding or Control\r
- * Bitmap buffer.\r
- * USBFS_lineChanged: used as a flag to be aware that Host has been\r
- * sent request for changing Line Coding or Control Bitmap.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_IsLineChanged(void) \r
+ /* transferState is checked to be sure then OUT data phase has been complete */\r
+ if (USBFS_transferState == USBFS_TRANS_STATE_IDLE)\r
{\r
- uint8 state = 0u;\r
-\r
- /* transferState is checked to be sure then OUT data phase has been complete */\r
- if(USBFS_transferState == USBFS_TRANS_STATE_IDLE)\r
+ if (USBFS_linesChanged[USBFS_activeCom] != 0u)\r
{\r
- if(USBFS_lineChanged != 0u)\r
- {\r
- state = USBFS_lineChanged;\r
- USBFS_lineChanged = 0u;\r
- }\r
+ state = USBFS_linesChanged[USBFS_activeCom];\r
+ USBFS_linesChanged[USBFS_activeCom] = 0u;\r
}\r
-\r
- return(state);\r
}\r
\r
+ return (state);\r
+}\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetDTERate\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns the data terminal rate set for this port in bits per second.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns a uint32 value of the data rate in bits per second.\r
- *\r
- * Global variables:\r
- * USBFS_lineCoding: First four bytes converted to uint32\r
- * depend on compiler, and returned as a data rate.\r
- *\r
- *******************************************************************************/\r
- uint32 USBFS_GetDTERate(void) \r
- {\r
- uint32 rate;\r
\r
- rate = USBFS_lineCoding[USBFS_LINE_CODING_RATE + 3u];\r
- rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE + 2u];\r
- rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE + 1u];\r
- rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE];\r
+/***************************************************************************\r
+* Function Name: USBFS_GetDTERate\r
+************************************************************************//**\r
+*\r
+* This function returns the data terminal rate set for this port in bits\r
+* per second.\r
+*\r
+* \return\r
+* Returns a uint32 value of the data rate in bits per second.\r
+*\r
+* \globalvars\r
+* USBFS_linesCoding: First four bytes converted to uint32\r
+* depend on compiler, and returned as a data rate.\r
+*\r
+*******************************************************************************/\r
+uint32 USBFS_GetDTERate(void) \r
+{\r
+ uint32 rate;\r
\r
- return(rate);\r
- }\r
+ rate = USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE + 3u];\r
+ rate = (rate << 8u) | USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE + 2u];\r
+ rate = (rate << 8u) | USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE + 1u];\r
+ rate = (rate << 8u) | USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE];\r
\r
+ return (rate);\r
+}\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetCharFormat\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns the number of stop bits.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns the number of stop bits.\r
- *\r
- * Global variables:\r
- * USBFS_lineCoding: used to get a parameter.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_GetCharFormat(void) \r
- {\r
- return(USBFS_lineCoding[USBFS_LINE_CODING_STOP_BITS]);\r
- }\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_GetCharFormat\r
+****************************************************************************//**\r
+*\r
+* Returns the number of stop bits.\r
+*\r
+* \return\r
+* Returns the number of stop bits.\r
+* Return |Value Description\r
+* ---------------------|-------------------\r
+* USBUART_1_STOPBIT | 1 stop bit\r
+* USBUART_1_5_STOPBITS | 1,5 stop bits\r
+* USBUART_2_STOPBITS | 2 stop bits\r
+*\r
+*\r
+* \globalvars\r
+* USBFS_linesCoding: used to get a parameter.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_GetCharFormat(void) \r
+{\r
+ return (USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_STOP_BITS]);\r
+}\r
\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetParityType\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns the parity type for the CDC port.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns the parity type.\r
- *\r
- * Global variables:\r
- * USBFS_lineCoding: used to get a parameter.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_GetParityType(void) \r
+/*******************************************************************************\r
+* Function Name: USBFS_GetParityType\r
+****************************************************************************//**\r
+*\r
+* This function returns the parity type for the CDC port.\r
+*\r
+* \return\r
+* Returns the parity type.\r
+* Return | Value Description\r
+* ----------------------|-------------------\r
+* USBUART_PARITY_NONE | 1 stop bit\r
+* USBUART_PARITY_ODD | 1,5 stop bits\r
+* USBUART_PARITY_EVEN | 2 stop bits\r
+* USBUART_PARITY_MARK | Mark\r
+* USBUART_PARITY_SPACE | Space\r
+*\r
+* \globalvars\r
+* USBFS_linesCoding: used to get a parameter.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_GetParityType(void) \r
+{\r
+ return (USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_PARITY]);\r
+}\r
+\r
+\r
+/***************************************************************************\r
+* Function Name: USBFS_GetDataBits\r
+************************************************************************//**\r
+*\r
+* This function returns the number of data bits for the CDC port.\r
+*\r
+* \return\r
+* Returns the number of data bits.\r
+* The number of data bits can be 5, 6, 7, 8 or 16.\r
+*\r
+* \globalvars\r
+* USBFS_linesCoding: used to get a parameter.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_GetDataBits(void) \r
+{\r
+ return (USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_DATA_BITS]);\r
+}\r
+\r
+\r
+/***************************************************************************\r
+* Function Name: USBFS_GetLineControl\r
+************************************************************************//**\r
+*\r
+* This function returns Line control bitmap that the host sends to the\r
+* device.\r
+*\r
+* \return\r
+* Returns Line control bitmap.\r
+* Return |Value Notes\r
+* -------------------------|-----------------------------------------------\r
+* USBUART_LINE_CONTROL_DTR |Indicates that a DTR signal is present. This signal corresponds to V.24 signal 108/2 and RS232 signal DTR.\r
+* USBUART_LINE_CONTROL_RTS |Carrier control for half-duplex modems. This signal corresponds to V.24 signal 105 and RS232 signal RTS.\r
+* RESERVED |The rest of the bits are reserved.\r
+*\r
+* *Note* Some terminal emulation programs do not properly handle these\r
+* control signals. They update information about DTR and RTS state only\r
+* when the RTS signal changes the state.\r
+*\r
+* \globalvars\r
+* USBFS_linesControlBitmap: used to get a parameter.\r
+*\r
+*******************************************************************************/\r
+uint16 USBFS_GetLineControl(void) \r
+{\r
+ return (USBFS_linesControlBitmap[USBFS_activeCom]);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_SendSerialState\r
+****************************************************************************//**\r
+*\r
+* Sends the serial state notification to the host using the interrupt\r
+* endpoint for the COM port selected using the API SetComPort().The\r
+* USBFS_NotificationIsReady() API must be called to check if the\r
+* Component is ready to send more serial state to the host. The API will\r
+* not send the notification data if the interrupt endpoint Max Packet Size\r
+* is less than the required 10 bytes.\r
+*\r
+* \param uint16 serialState\r
+* 16-bit value that will be sent from the device to the\r
+* host as SERIAL_STATE notification using the IN interrupt endpoint. Refer\r
+* to revision 1.2 of the CDC PSTN Subclass specification for bit field\r
+* definitions of the 16-bit serial state value.\r
+*\r
+*******************************************************************************/\r
+void USBFS_SendSerialState (uint16 serialState) \r
+{\r
+ uint8 epNumber = USBFS_cdcCommInInterruptEp[USBFS_activeCom];\r
+\r
+ if(USBFS_SERIAL_STATE_SIZE <= USBFS_EP[epNumber].bufferSize)\r
{\r
- return(USBFS_lineCoding[USBFS_LINE_CODING_PARITY]);\r
+ /* Save current SERIAL_STATE bitmap. */\r
+ USBFS_serialStateBitmap[USBFS_activeCom] = serialState;\r
+\r
+ /* Add interface number */\r
+ USBFS_serialStateNotification.wIndex = USBFS_EP[epNumber].interface;\r
+\r
+ /*Form SERIAL_STATE data*/\r
+ USBFS_serialStateNotification.wSerialState = LO8(USBFS_serialStateBitmap[USBFS_activeCom]);\r
+ USBFS_serialStateNotification.wSerialStateMSB = HI8(USBFS_serialStateBitmap[USBFS_activeCom]);\r
+\r
+ USBFS_LoadInEP(epNumber, (uint8 *) &USBFS_serialStateNotification, sizeof(USBFS_serialStateNotification));\r
}\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_GetSerialState\r
+****************************************************************************//**\r
+*\r
+* This function returns the current serial state value for the COM port\r
+* selected using the API SetComPort().\r
+*\r
+* \return\r
+* 16-bit serial state value. Refer to revision 1.2 of the CDC PSTN Subclass\r
+* specification for bit field definitions of the 16-bit serial state value.\r
+*\r
+*******************************************************************************/\r
+uint16 USBFS_GetSerialState(void) \r
+{\r
+ return USBFS_serialStateBitmap[USBFS_activeCom];\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_NotificationIsReady\r
+****************************************************************************//**\r
+*\r
+* This function returns a non-zero value if the Component is ready to send\r
+* more notifications to the host; otherwise, it returns zero. The function\r
+* should be called before sending new notifications when using\r
+* USBFS_SendSerialState() to ensure that any previous\r
+* notification data has been already sent to the host.\r
+*\r
+* \return\r
+* If the buffer can accept new data(endpoint buffer not full), this\r
+* function returns a non-zero value. Otherwise, it returns zero.\r
+*\r
+* \globalvars\r
+* USBFS_cdcDataInEp: CDC IN endpoint number used.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_NotificationIsReady(void) \r
+{\r
+ return (USBFS_EP[USBFS_cdcCommInInterruptEp[USBFS_activeCom]].apiEpState);\r
+}\r
\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetDataBits\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns the number of data bits for the CDC port.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns the number of data bits.\r
- * The number of data bits can be 5, 6, 7, 8 or 16.\r
- *\r
- * Global variables:\r
- * USBFS_lineCoding: used to get a parameter.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_GetDataBits(void) \r
+/*******************************************************************************\r
+* Function Name: USBFS_SetComPort\r
+****************************************************************************//**\r
+*\r
+* This function allows the user to select from one of the two COM ports\r
+* they wish to address in the instance of having multiple COM ports\r
+* instantiated though the use of a composite device. Once set, all future\r
+* function calls related to the USBUART will be affected. This addressed\r
+* COM port can be changed during run time.\r
+*\r
+* \param comNumber\r
+* Contains the COM interface the user wishes to address. Value can either\r
+* be 0 or 1 since a maximum of only 2 COM ports can be supported. Note that\r
+* this COM port number is not the COM port number assigned on the PC side\r
+* for the UART communication. If a value greater than 1 is passed, the\r
+* function returns without performing any action.\r
+*\r
+*******************************************************************************/\r
+void USBFS_SetComPort(uint8 comNumber) \r
+{\r
+ if ((USBFS_activeCom != comNumber) && \\r
+ (comNumber < USBFS_MAX_MULTI_COM_NUM ))\r
{\r
- return(USBFS_lineCoding[USBFS_LINE_CODING_DATA_BITS]);\r
+ USBFS_activeCom = comNumber;\r
}\r
+}\r
+\r
\r
+/*******************************************************************************\r
+* Function Name: USBFS_GetComPort\r
+****************************************************************************//**\r
+*\r
+* This function returns the current selected COM port that the user is\r
+* currently addressing in the instance of having multiple COM ports\r
+* instantiated though the use of a composite device.\r
+*\r
+* \return\r
+* Returns the currently selected COM port. Value can either be 0 or 1 since\r
+* a maximum of only 2 COM ports can be supported. . Note that this COM port\r
+* number is not the COM port number assigned on the PC side for the UART\r
+* communication.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_GetComPort(void) \r
+{\r
+ return (USBFS_activeCom);\r
+}\r
+\r
+\r
+#endif /* (USBFS_ENABLE_CDC_CLASS_API) */\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetLineControl\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns Line control bitmap.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns Line control bitmap.\r
- *\r
- * Global variables:\r
- * USBFS_lineControlBitmap: used to get a parameter.\r
- *\r
- *******************************************************************************/\r
- uint16 USBFS_GetLineControl(void) \r
+\r
+/***************************************************************************\r
+* Function Name: USBFS_Cdc_EpInit\r
+************************************************************************//**\r
+*\r
+* \internal\r
+* This routine decide type of endpoint (IN, OUT, Notification) and same to\r
+* appropriate global variables according to COM port number.\r
+* USBFS_cdcDataInEp[], USBFS_cdcCommInInterruptEp[],\r
+* USBFS_cdcDataOutEp[]\r
+*\r
+* \param pEP: Pointer to structure with current EP description.\r
+* \param epNum: EP number\r
+* \param cdcComNums: Bit array of current COM ports for CDC IN, OUT,\r
+* and notification EPs(0 - COM port 1, 1- COM port 2)\r
+*\r
+* \return\r
+* Updated cdcComNums\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+***************************************************************************/\r
+uint8 USBFS_Cdc_EpInit(const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP, uint8 epNum, uint8 cdcComNums) \r
+{\r
+ uint8 epType;\r
+\r
+ epType = pEP->attributes & USBFS_EP_TYPE_MASK;\r
+\r
+ if (0u != (pEP->addr & USBFS_DIR_IN))\r
{\r
- return(USBFS_lineControlBitmap);\r
- }\r
+ if (epType != USBFS_EP_TYPE_INT)\r
+ {\r
+ USBFS_cdcDataInEp[USBFS_GET_EP_COM_NUM(cdcComNums, USBFS_CDC_IN_EP)] = epNum;\r
+ cdcComNums |= (uint8)(USBFS_COM_PORT2 << USBFS_CDC_IN_EP);\r
+ }\r
+ else\r
+ {\r
\r
-#endif /* USBFS_ENABLE_CDC_CLASS_API*/\r
+ USBFS_cdcCommInInterruptEp[USBFS_GET_EP_COM_NUM(cdcComNums, USBFS_CDC_NOTE_EP)] = epNum;\r
+ cdcComNums |= (uint8)(USBFS_COM_PORT2 << USBFS_CDC_NOTE_EP);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (epType != USBFS_EP_TYPE_INT)\r
+ {\r
+ USBFS_cdcDataOutEp[USBFS_GET_EP_COM_NUM(cdcComNums, USBFS_CDC_OUT_EP)] = epNum;\r
+ cdcComNums |= (uint8)(USBFS_COM_PORT2 << USBFS_CDC_OUT_EP);\r
+ }\r
+ }\r
+ return (cdcComNums);\r
+}\r
\r
\r
/*******************************************************************************\r
\r
/* `#END` */\r
\r
-#endif /* USBFS_ENABLE_CDC_CLASS*/\r
+#endif /* (USBFS_ENABLE_CDC_CLASS) */\r
\r
\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: USBFS_cdc.h\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_cdc.h\r
+* \version 3.10\r
*\r
-* Description:\r
-* Header File for the USBFS component.\r
-* Contains CDC class prototypes and constant values.\r
+* \brief\r
+* This file provides function prototypes and constants for the USBFS component \r
+* CDC class.\r
*\r
* Related Document:\r
* Universal Serial Bus Class Definitions for Communication Devices Version 1.1\r
*\r
********************************************************************************\r
-* Copyright 2012-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2012-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#if !defined(CY_USBFS_USBFS_cdc_H)\r
#define CY_USBFS_USBFS_cdc_H\r
\r
-#include "cytypes.h"\r
+#include "USBFS.h"\r
\r
\r
-/***************************************\r
+/*******************************************************************************\r
* Prototypes of the USBFS_cdc API.\r
-***************************************/\r
-\r
+*******************************************************************************/\r
+/**\r
+* \addtogroup group_cdc\r
+* @{\r
+*/\r
#if (USBFS_ENABLE_CDC_CLASS_API != 0u)\r
- void USBFS_CDC_Init(void) ;\r
+ uint8 USBFS_CDC_Init(void) ;\r
void USBFS_PutData(const uint8* pData, uint16 length) ;\r
- void USBFS_PutString(const char8 string[]) ;\r
+ void USBFS_PutString(const char8 string[]) ;\r
void USBFS_PutChar(char8 txDataByte) ;\r
- void USBFS_PutCRLF(void) ;\r
- uint16 USBFS_GetCount(void) ;\r
- uint8 USBFS_CDCIsReady(void) ;\r
- uint8 USBFS_DataIsReady(void) ;\r
- uint16 USBFS_GetData(uint8* pData, uint16 length) ;\r
- uint16 USBFS_GetAll(uint8* pData) ;\r
- uint8 USBFS_GetChar(void) ;\r
- uint8 USBFS_IsLineChanged(void) ;\r
- uint32 USBFS_GetDTERate(void) ;\r
- uint8 USBFS_GetCharFormat(void) ;\r
- uint8 USBFS_GetParityType(void) ;\r
- uint8 USBFS_GetDataBits(void) ;\r
- uint16 USBFS_GetLineControl(void) ;\r
-#endif /* USBFS_ENABLE_CDC_CLASS_API */\r
-\r
-\r
-/***************************************\r
+ void USBFS_PutCRLF(void) ;\r
+ uint16 USBFS_GetCount(void) ;\r
+ uint8 USBFS_CDCIsReady(void) ;\r
+ uint8 USBFS_DataIsReady(void) ;\r
+ uint16 USBFS_GetData(uint8* pData, uint16 length) ;\r
+ uint16 USBFS_GetAll(uint8* pData) ;\r
+ uint8 USBFS_GetChar(void) ;\r
+ uint8 USBFS_IsLineChanged(void) ;\r
+ uint32 USBFS_GetDTERate(void) ;\r
+ uint8 USBFS_GetCharFormat(void) ;\r
+ uint8 USBFS_GetParityType(void) ;\r
+ uint8 USBFS_GetDataBits(void) ;\r
+ uint16 USBFS_GetLineControl(void) ;\r
+ void USBFS_SendSerialState (uint16 serialState) ;\r
+ uint16 USBFS_GetSerialState (void) ;\r
+ void USBFS_SetComPort (uint8 comNumber) ;\r
+ uint8 USBFS_GetComPort (void) ;\r
+ uint8 USBFS_NotificationIsReady(void) ;\r
+\r
+#endif /* (USBFS_ENABLE_CDC_CLASS_API) */\r
+/** @} cdc */\r
+\r
+/*******************************************************************************\r
* Constants for USBFS_cdc API.\r
-***************************************/\r
+*******************************************************************************/\r
\r
/* CDC Class-Specific Request Codes (CDC ver 1.2 Table 19) */\r
#define USBFS_CDC_SET_LINE_CODING (0x20u)\r
#define USBFS_CDC_GET_LINE_CODING (0x21u)\r
#define USBFS_CDC_SET_CONTROL_LINE_STATE (0x22u)\r
\r
+/*PSTN Subclass Specific Notifications (CDC ver 1.2 Table 30)*/\r
+#define USBFS_SERIAL_STATE (0x20u)\r
+\r
#define USBFS_LINE_CODING_CHANGED (0x01u)\r
#define USBFS_LINE_CONTROL_CHANGED (0x02u)\r
\r
#define USBFS_LINE_CONTROL_DTR (0x01u)\r
#define USBFS_LINE_CONTROL_RTS (0x02u)\r
\r
+#define USBFS_MAX_MULTI_COM_NUM (2u) \r
+\r
+#define USBFS_COM_PORT1 (0u) \r
+#define USBFS_COM_PORT2 (1u) \r
\r
-/***************************************\r
+#define USBFS_SUCCESS (0u)\r
+#define USBFS_FAILURE (1u)\r
+\r
+#define USBFS_SERIAL_STATE_SIZE (10u)\r
+\r
+/* SerialState constants*/\r
+#define USBFS_SERIAL_STATE_REQUEST_TYPE (0xA1u)\r
+#define USBFS_SERIAL_STATE_LENGTH (0x2u)\r
+\r
+/*******************************************************************************\r
* External data references\r
-***************************************/\r
+*******************************************************************************/\r
+/**\r
+* \addtogroup group_cdc\r
+* @{\r
+*/\r
+extern volatile uint8 USBFS_linesCoding[USBFS_MAX_MULTI_COM_NUM][USBFS_LINE_CODING_SIZE];\r
+extern volatile uint8 USBFS_linesChanged[USBFS_MAX_MULTI_COM_NUM];\r
+extern volatile uint16 USBFS_linesControlBitmap[USBFS_MAX_MULTI_COM_NUM];\r
+extern volatile uint16 USBFS_serialStateBitmap[USBFS_MAX_MULTI_COM_NUM];\r
+extern volatile uint8 USBFS_cdcDataInEp[USBFS_MAX_MULTI_COM_NUM];\r
+extern volatile uint8 USBFS_cdcDataOutEp[USBFS_MAX_MULTI_COM_NUM];\r
+extern volatile uint8 USBFS_cdcCommInInterruptEp[USBFS_MAX_MULTI_COM_NUM];\r
+/** @} cdc */\r
+\r
+/*******************************************************************************\r
+* The following code is DEPRECATED and\r
+* must not be used.\r
+*******************************************************************************/\r
+\r
\r
-extern volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE];\r
-extern volatile uint8 USBFS_lineChanged;\r
-extern volatile uint16 USBFS_lineControlBitmap;\r
-extern volatile uint8 USBFS_cdc_data_in_ep;\r
-extern volatile uint8 USBFS_cdc_data_out_ep;\r
+#define USBFS_lineCoding USBFS_linesCoding[0]\r
+#define USBFS_lineChanged USBFS_linesChanged[0]\r
+#define USBFS_lineControlBitmap USBFS_linesControlBitmap[0]\r
+#define USBFS_cdc_data_in_ep USBFS_cdcDataInEp[0]\r
+#define USBFS_cdc_data_out_ep USBFS_cdcDataOutEp[0]\r
\r
-#endif /* CY_USBFS_USBFS_cdc_H */\r
+#endif /* (CY_USBFS_USBFS_cdc_H) */\r
\r
\r
/* [] END OF FILE */\r
;******************************************************************************\r
; File Name: USBFS_cdc.inf\r
-; Version 2.80\r
+; Version 3.10\r
;\r
; Description:\r
; Windows USB CDC setup file for USBUART Device.\r
;\r
;******************************************************************************\r
-; Copyright 2007-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright 2007-2016, Cypress Semiconductor Corporation. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions,\r
; disclaimers, and limitations in the end user license agreement accompanying\r
; the software package with which this file was provided.\r
\r
[DeviceList.NTx86]\r
%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_00\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_01\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_02\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_03\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_04\r
\r
[DeviceList.NTia64]\r
%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_00\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_01\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_02\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_03\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_04\r
\r
[DeviceList.NTamd64]\r
%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_00\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_01\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_02\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_03\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_04\r
\r
\r
;------------------------------------------------------------------------------\r
-/*******************************************************************************\r
-* File Name: USBFS_cls.c\r
-* Version 2.80\r
-*\r
-* Description:\r
-* USB Class request handler.\r
+/***************************************************************************//**\r
+* \file USBFS_cls.c\r
+* \version 3.10\r
*\r
-* Note:\r
+* \brief\r
+* This file contains the USB Class request handler.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
-\r
-#if(USBFS_EXTERN_CLS == USBFS_FALSE)\r
-\r
#include "USBFS_pvt.h"\r
\r
\r
+#if(USBFS_EXTERN_CLS == USBFS_FALSE)\r
\r
/***************************************\r
* User Implemented Class Driver Declarations.\r
\r
/*******************************************************************************\r
* Function Name: USBFS_DispatchClassRqst\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* This routine dispatches class specific requests depend on interface class.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_DispatchClassRqst(void) \r
{\r
- uint8 requestHandled = USBFS_FALSE;\r
- uint8 interfaceNumber = 0u;\r
+ uint8 requestHandled;\r
+ uint8 interfaceNumber;\r
\r
- switch(CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK)\r
+ /* Get interface to which request is intended. */\r
+ switch (USBFS_bmRequestTypeReg & USBFS_RQST_RCPT_MASK)\r
{\r
- case USBFS_RQST_RCPT_IFC: /* Class-specific request directed to an interface */\r
- interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); /* wIndexLo contain Interface number */\r
+ case USBFS_RQST_RCPT_IFC:\r
+ /* Class-specific request directed to interface: wIndexLoReg \r
+ * contains interface number.\r
+ */\r
+ interfaceNumber = (uint8) USBFS_wIndexLoReg;\r
break;\r
- case USBFS_RQST_RCPT_EP: /* Class-specific request directed to the endpoint */\r
- /* Find related interface to the endpoint, wIndexLo contain EP number */\r
- interfaceNumber = USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) &\r
- USBFS_DIR_UNUSED].interface;\r
+ \r
+ case USBFS_RQST_RCPT_EP:\r
+ /* Class-specific request directed to endpoint: wIndexLoReg contains \r
+ * endpoint number. Find interface related to endpoint, \r
+ */\r
+ interfaceNumber = USBFS_EP[USBFS_wIndexLoReg & USBFS_DIR_UNUSED].interface;\r
break;\r
- default: /* RequestHandled is initialized as FALSE by default */\r
+ \r
+ default:\r
+ /* Default interface is zero. */\r
+ interfaceNumber = 0u;\r
break;\r
}\r
- /* Handle Class request depend on interface type */\r
- switch(USBFS_interfaceClass[interfaceNumber])\r
+\r
+#if (defined(USBFS_ENABLE_HID_CLASS) ||\\r
+ defined(USBFS_ENABLE_AUDIO_CLASS) ||\\r
+ defined(USBFS_ENABLE_CDC_CLASS) ||\\r
+ USBFS_ENABLE_MSC_CLASS)\r
+\r
+ /* Handle class request depends on interface type. */\r
+ switch (USBFS_interfaceClass[interfaceNumber])\r
{\r
+ #if defined(USBFS_ENABLE_HID_CLASS)\r
case USBFS_CLASS_HID:\r
- #if defined(USBFS_ENABLE_HID_CLASS)\r
- requestHandled = USBFS_DispatchHIDClassRqst();\r
- #endif /* USBFS_ENABLE_HID_CLASS */\r
+ requestHandled = USBFS_DispatchHIDClassRqst();\r
break;\r
+ #endif /* (USBFS_ENABLE_HID_CLASS) */\r
+ \r
+ #if defined(USBFS_ENABLE_AUDIO_CLASS)\r
case USBFS_CLASS_AUDIO:\r
- #if defined(USBFS_ENABLE_AUDIO_CLASS)\r
- requestHandled = USBFS_DispatchAUDIOClassRqst();\r
- #endif /* USBFS_CLASS_AUDIO */\r
+ requestHandled = USBFS_DispatchAUDIOClassRqst();\r
break;\r
+ #endif /* (USBFS_CLASS_AUDIO) */\r
+ \r
+ #if defined(USBFS_ENABLE_CDC_CLASS)\r
case USBFS_CLASS_CDC:\r
- #if defined(USBFS_ENABLE_CDC_CLASS)\r
- requestHandled = USBFS_DispatchCDCClassRqst();\r
- #endif /* USBFS_ENABLE_CDC_CLASS */\r
+ requestHandled = USBFS_DispatchCDCClassRqst();\r
break;\r
- default: /* requestHandled is initialized as FALSE by default */\r
+ #endif /* (USBFS_ENABLE_CDC_CLASS) */\r
+ \r
+ #if (USBFS_ENABLE_MSC_CLASS)\r
+ case USBFS_CLASS_MSD:\r
+ #if (USBFS_HANDLE_MSC_REQUESTS)\r
+ /* MSC requests are handled by the component. */\r
+ requestHandled = USBFS_DispatchMSCClassRqst();\r
+ #elif defined(USBFS_DISPATCH_MSC_CLASS_RQST_CALLBACK)\r
+ /* MSC requests are handled by user defined callbcak. */\r
+ requestHandled = USBFS_DispatchMSCClassRqst_Callback();\r
+ #else\r
+ /* MSC requests are not handled. */\r
+ requestHandled = USBFS_FALSE;\r
+ #endif /* (USBFS_HANDLE_MSC_REQUESTS) */\r
+ break;\r
+ #endif /* (USBFS_ENABLE_MSC_CLASS) */\r
+ \r
+ default:\r
+ /* Request is not handled: unknown class request type. */\r
+ requestHandled = USBFS_FALSE;\r
break;\r
}\r
+#else /*No class is defined*/\r
+ if (0u != interfaceNumber)\r
+ {\r
+ /* Suppress warning message */\r
+ }\r
+ requestHandled = USBFS_FALSE;\r
+#endif /*HID or AUDIO or MSC or CDC class enabled*/\r
\r
/* `#START USER_DEFINED_CLASS_CODE` Place your Class request here */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_DISPATCH_CLASS_RQST_CALLBACK\r
- USBFS_DispatchClassRqst_Callback();\r
- #endif /* USBFS_DISPATCH_CLASS_RQST_CALLBACK */\r
+#ifdef USBFS_DISPATCH_CLASS_RQST_CALLBACK\r
+ if (USBFS_FALSE == requestHandled)\r
+ {\r
+ requestHandled = USBFS_DispatchClassRqst_Callback(interfaceNumber);\r
+ }\r
+#endif /* (USBFS_DISPATCH_CLASS_RQST_CALLBACK) */\r
\r
- return(requestHandled);\r
+ return (requestHandled);\r
}\r
\r
\r
--- /dev/null
+/***************************************************************************//**
+* \file USBFS_cydmac.h
+* \version 3.10
+*
+* \brief
+* This file provides macros implemenation of DMA_P4 functions.
+*
+********************************************************************************
+* \copyright
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_USBFS_USBFS_cydmac_H)
+#define CY_USBFS_USBFS_cydmac_H
+
+#include "USBFS_pvt.h"
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaSetConfiguration
+****************************************************************************//**
+*
+* Sets configuration information for the specified descriptor.
+*
+* \param ch: DMA ch modified by this function.
+* \param descr: Descriptor (0 or 1) modified by this function.
+* \param cfg: Descriptor control register.
+*
+* \sideeffect
+* The status register associated with the specified descriptor is reset to
+* zero after this function call. This function should not be called while
+* the descriptor is active. This can be checked by calling CyDmaGetStatus().
+*
+*******************************************************************************/
+#define USBFS_CyDmaSetConfiguration(ch, descr, cfg) \
+ do{ \
+ CYDMA_DESCR_BASE.descriptor[ch][descr].ctl = (cfg); \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaSetInterruptMask
+****************************************************************************//**
+*
+* Enables the DMA channel interrupt.
+*
+* \param ch: Channel used by this function.
+*
+*
+*******************************************************************************/
+#define USBFS_CyDmaSetInterruptMask(ch) \
+ do{ \
+ CYDMA_INTR_MASK_REG |= ((uint32)(1UL << (ch))); \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name:USBFS_CyDmaSetDescriptor0Next
+****************************************************************************//**
+*
+* Sets the descriptor 0 that should be run the next time the channel is
+* triggered.
+*
+* \param channel: Channel used by this function.
+*
+*
+*******************************************************************************/
+#define USBFS_CyDmaSetDescriptor0Next(ch) \
+ do{ \
+ CYDMA_CH_CTL_BASE.ctl[(ch)] &= (uint32) ~CYDMA_DESCRIPTOR; \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaSetNumDataElements
+****************************************************************************//**
+*
+* Sets the number of data elements to transfer for specified descriptor.
+*
+* \param ch: Channel used by this function.
+* \param descr: Descriptor (0 or 1) modified by this function.
+* \param numEl: Total number of data elements this descriptor transfers - 1u.
+* Valid ranges are 0 to 65535.
+*
+*
+* \sideeffect
+* This function should not be called when the specified descriptor is active
+* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus().
+*
+*******************************************************************************/
+#define USBFS_CyDmaSetNumDataElements(ch, descr, numEl) \
+ do{ \
+ CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].ctl = \
+ ((CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].ctl & (uint32) ~CYDMA_DATA_NR) | ((uint32) (numEl))); \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaGetSrcAddress
+****************************************************************************//**
+*
+* Returns the source address for the specified descriptor.
+*
+* \param ch: Channel used by this function.
+* \param descr: Specifies descriptor (0 or 1) used by this function.
+*
+* \return
+* Source address written to specified descriptor.
+*
+*******************************************************************************/
+#define USBFS_CyDmaGetSrcAddress(ch, descr) CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].src
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaSetSrcAddress
+****************************************************************************//**
+*
+* Configures the source address for the specified descriptor.
+*
+* \param ch: Channel used by this function.
+* \param descr: Descriptor (0 or 1) modified by this function.
+* \param srcAddress: Address of DMA transfer source.
+*
+*
+* \sideeffect
+* This function should not be called when the specified descriptor is active
+* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus().
+*
+*******************************************************************************/
+#define USBFS_CyDmaSetSrcAddress(ch, descr, srcAddress) \
+ do{ \
+ CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].src = (srcAddress); \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaGetDstAddress
+****************************************************************************//**
+*
+* Returns the destination address for the specified descriptor, set by
+* CyDmaSetDstAddress().
+*
+* \param ch: Channel used by this function.
+* \param descr: Specifies descriptor (0 or 1) used by this function.
+*
+* \return
+* Destination address written to specified descriptor.
+*
+*******************************************************************************/
+#define USBFS_CyDmaGetDstAddress(ch, descr) CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].dst
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaSetDstAddress
+****************************************************************************//**
+*
+* Configures the destination address for the specified descriptor.
+*
+* \param ch: Channel used by this function.
+* \param descr: Descriptor (0 or 1) modified by this function.
+* \param dstAddress: Address of DMA transfer destination.
+*
+*
+* \sideeffect
+* This function should not be called when the specified descriptor is active
+* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus().
+*
+*******************************************************************************/
+#define USBFS_CyDmaSetDstAddress(ch, descr, dstAddress) \
+ do{ \
+ CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].dst = (dstAddress); \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaValidateDescriptor
+****************************************************************************//**
+*
+* Validates the specified descriptor after it has been invalidated.
+*
+* \param ch: Channel used by this function.
+* \param descr: Descriptor (0 or 1) modified by this function.
+*
+*
+* \sideeffect
+* The status register associated with the specified descriptor is reset to
+* zero after this function call.
+* This function should not be called when the specified descriptor is active
+* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus().
+*
+*******************************************************************************/
+#define USBFS_CyDmaValidateDescriptor(ch, descr) \
+ do{ \
+ CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].status = CYDMA_VALID; \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaChEnable
+****************************************************************************//**
+*
+* Enables the DMA ch.
+*
+* \param ch: Channel used by this function.
+*
+*
+* \sideeffect
+* If this function is called before DMA is completely configured the operation
+* of the DMA is undefined and could result in system data corruption.
+*
+*******************************************************************************/
+#define USBFS_CyDmaChEnable(ch) \
+ do{ \
+ CYDMA_CH_CTL_BASE.ctl[(ch)] |= CYDMA_ENABLED; \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: CyDmaChDisable
+****************************************************************************//**
+*
+* Disables the DMA ch.
+*
+* \param ch: Channel used by this function.
+*
+*
+* \sideeffect
+* If this function is called during a DMA transfer the transfer is aborted.
+*
+*******************************************************************************/
+#define USBFS_CyDmaChDisable(ch) \
+ do{ \
+ CYDMA_CH_CTL_BASE.ctl[(ch)] &= (uint32) ~CYDMA_ENABLED; \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaTriggerIn
+****************************************************************************//**
+*
+* Triggers the DMA channel to execute a transfer. The tr_in signal is
+* triggered.
+*
+* \param trSel: trigger to be activated.
+*
+*
+*******************************************************************************/
+#define USBFS_DMA_USB_REQ_TR_OUT (0xC0020100U)
+#define USBFS_CyDmaTriggerIn(trSel) \
+ do{ \
+ CYDMA_TR_CTL_REG = USBFS_DMA_USB_REQ_TR_OUT | (uint32)(trSel); \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaTriggerOut
+****************************************************************************//**
+*
+* Triggers the DMA channel to generate a transfer completion signal without
+* actual transfer executed. The tr_out signal is triggered.
+*
+* \param trSel: trigger to be activated.
+*
+*
+*******************************************************************************/
+#define USBFS_DMA_USB_BURST_END_TR_OUT (0xC0020300U)
+#define USBFS_CyDmaTriggerOut(trSel) \
+ do{ \
+ CYDMA_TR_CTL_REG = USBFS_DMA_USB_BURST_END_TR_OUT | (uint32)(trSel); \
+ }while(0)
+
+
+#endif /* (CY_USBFS_USBFS_cydmac_H) */
+
+
+/* [] END OF FILE */
-/*******************************************************************************\r
-* File Name: USBFS_descr.c\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_descr.c\r
+* \version 3.10\r
*\r
-* Description:\r
-* USB descriptors and storage.\r
-*\r
-* Note:\r
+* \brief\r
+* This file contains the USB descriptors and storage.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
#include "USBFS_pvt.h"\r
\r
\r
* Device Dispatch Table -- Points to the Device Descriptor and each of\r
* and Configuration Tables for this Device \r
*********************************************************************/\r
-const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[2u] = {\r
+const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[3u] = {\r
{0x01u, &USBFS_DEVICE0_DESCR},\r
+ {0x00u, NULL},\r
{0x01u, &USBFS_DEVICE0_CONFIGURATION0_TABLE}\r
};\r
/*********************************************************************\r
-/*******************************************************************************\r
-* File Name: USBFS_drv.c\r
-* Version 2.80\r
-*\r
-* Description:\r
-* Endpoint 0 Driver for the USBFS Component.\r
+/***************************************************************************//**\r
+* \file USBFS_drv.c\r
+* \version 3.10\r
*\r
-* Note:\r
+* \brief\r
+* This file contains the Endpoint 0 Driver for the USBFS Component. \r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
#include "USBFS_pvt.h"\r
\r
\r
***************************************/\r
\r
volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP];\r
+\r
+/** Contains the current configuration number, which is set by the host using a \r
+ * SET_CONFIGURATION request. This variable is initialized to zero in \r
+ * USBFS_InitComponent() API and can be read by the USBFS_GetConfiguration() \r
+ * API.*/\r
volatile uint8 USBFS_configuration;\r
+\r
+/** Contains the current interface number.*/\r
volatile uint8 USBFS_interfaceNumber;\r
+\r
+/** This variable is set to one after SET_CONFIGURATION and SET_INTERFACE \r
+ *requests. It can be read by the USBFS_IsConfigurationChanged() API */\r
volatile uint8 USBFS_configurationChanged;\r
+\r
+/** Contains the current device address.*/\r
volatile uint8 USBFS_deviceAddress;\r
+\r
+/** This is a two-bit variable that contains power status in the bit 0 \r
+ * (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote wakeup \r
+ * status (DEVICE_STATUS_REMOTE_WAKEUP) in the bit 1. This variable is \r
+ * initialized to zero in USBFS_InitComponent() API, configured by the \r
+ * USBFS_SetPowerStatus() API. The remote wakeup status cannot be set using the \r
+ * API SetPowerStatus(). */\r
volatile uint8 USBFS_deviceStatus;\r
+\r
volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER];\r
volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER];\r
volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER];\r
+\r
+/** Contains the started device number. This variable is set by the \r
+ * USBFS_Start() or USBFS_InitComponent() APIs.*/\r
volatile uint8 USBFS_device;\r
+\r
+/** Initialized class array for each interface. It is used for handling Class \r
+ * specific requests depend on interface class. Different classes in multiple \r
+ * alternate settings are not supported.*/\r
const uint8 CYCODE *USBFS_interfaceClass;\r
\r
\r
* Local data allocation\r
***************************************/\r
\r
-volatile uint8 USBFS_ep0Toggle;\r
-volatile uint8 USBFS_lastPacketSize;\r
-volatile uint8 USBFS_transferState;\r
+volatile uint8 USBFS_ep0Toggle;\r
+volatile uint8 USBFS_lastPacketSize;\r
+\r
+/** This variable is used by the communication functions to handle the current \r
+* transfer state.\r
+* Initialized to TRANS_STATE_IDLE in the USBFS_InitComponent() API and after a \r
+* complete transfer in the status stage.\r
+* Changed to the TRANS_STATE_CONTROL_READ or TRANS_STATE_CONTROL_WRITE in setup \r
+* transaction depending on the request type.\r
+*/\r
+volatile uint8 USBFS_transferState;\r
volatile T_USBFS_TD USBFS_currentTD;\r
-volatile uint8 USBFS_ep0Mode;\r
-volatile uint8 USBFS_ep0Count;\r
+volatile uint8 USBFS_ep0Mode;\r
+volatile uint8 USBFS_ep0Count;\r
volatile uint16 USBFS_transferByteCount;\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ep_0_Interrupt\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This Interrupt Service Routine handles Endpoint 0 (Control Pipe) traffic.\r
* It dispatches setup requests and handles the data and status stages.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_0_ISR)\r
{\r
- uint8 bRegTemp;\r
+ uint8 tempReg;\r
uint8 modifyReg;\r
\r
- #ifdef USBFS_EP_0_ISR_ENTRY_CALLBACK\r
- USBFS_EP_0_ISR_EntryCallback();\r
- #endif /* USBFS_EP_0_ISR_ENTRY_CALLBACK */\r
+#ifdef USBFS_EP_0_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_0_ISR_EntryCallback();\r
+#endif /* (USBFS_EP_0_ISR_ENTRY_CALLBACK) */\r
\r
- bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR);\r
- if ((bRegTemp & USBFS_MODE_ACKD) != 0u)\r
+ tempReg = USBFS_EP0_CR_REG;\r
+ if ((tempReg & USBFS_MODE_ACKD) != 0u)\r
{\r
modifyReg = 1u;\r
- if ((bRegTemp & USBFS_MODE_SETUP_RCVD) != 0u)\r
+ if ((tempReg & USBFS_MODE_SETUP_RCVD) != 0u)\r
{\r
- if((bRegTemp & USBFS_MODE_MASK) != USBFS_MODE_NAK_IN_OUT)\r
+ if ((tempReg & USBFS_MODE_MASK) != USBFS_MODE_NAK_IN_OUT)\r
{\r
- modifyReg = 0u; /* When mode not NAK_IN_OUT => invalid setup */\r
+ /* Mode not equal to NAK_IN_OUT: invalid setup */\r
+ modifyReg = 0u;\r
}\r
else\r
{\r
USBFS_HandleSetup();\r
- if((USBFS_ep0Mode & USBFS_MODE_SETUP_RCVD) != 0u)\r
+ \r
+ if ((USBFS_ep0Mode & USBFS_MODE_SETUP_RCVD) != 0u)\r
{\r
- modifyReg = 0u; /* if SETUP bit set -> exit without modifying the mode */\r
+ /* SETUP bit set: exit without mode modificaiton */\r
+ modifyReg = 0u;\r
}\r
-\r
}\r
}\r
- else if ((bRegTemp & USBFS_MODE_IN_RCVD) != 0u)\r
+ else if ((tempReg & USBFS_MODE_IN_RCVD) != 0u)\r
{\r
USBFS_HandleIN();\r
}\r
- else if ((bRegTemp & USBFS_MODE_OUT_RCVD) != 0u)\r
+ else if ((tempReg & USBFS_MODE_OUT_RCVD) != 0u)\r
{\r
USBFS_HandleOUT();\r
}\r
{\r
modifyReg = 0u;\r
}\r
- if(modifyReg != 0u)\r
+ \r
+ /* Modify the EP0_CR register */\r
+ if (modifyReg != 0u)\r
{\r
- bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */\r
- if((bRegTemp & USBFS_MODE_SETUP_RCVD) == 0u) /* Check if SETUP bit is not set, otherwise exit */\r
+ \r
+ tempReg = USBFS_EP0_CR_REG;\r
+ \r
+ /* Make sure that SETUP bit is cleared before modification */\r
+ if ((tempReg & USBFS_MODE_SETUP_RCVD) == 0u)\r
{\r
- /* Update the count register */\r
- bRegTemp = USBFS_ep0Toggle | USBFS_ep0Count;\r
- CY_SET_REG8(USBFS_EP0_CNT_PTR, bRegTemp);\r
- if(bRegTemp == CY_GET_REG8(USBFS_EP0_CNT_PTR)) /* continue if writing was successful */\r
+ /* Update count register */\r
+ tempReg = (uint8) USBFS_ep0Toggle | USBFS_ep0Count;\r
+ USBFS_EP0_CNT_REG = tempReg;\r
+ \r
+ /* Make sure that previous write operaiton was successful */\r
+ if (tempReg == USBFS_EP0_CNT_REG)\r
{\r
+ /* Repeat until next successful write operation */\r
do\r
{\r
- modifyReg = USBFS_ep0Mode; /* Init temporary variable */\r
- /* Unlock registers */\r
- bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_SETUP_RCVD;\r
- if(bRegTemp == 0u) /* Check if SETUP bit is not set */\r
+ /* Init temporary variable */\r
+ modifyReg = USBFS_ep0Mode;\r
+ \r
+ /* Unlock register */\r
+ tempReg = (uint8) (USBFS_EP0_CR_REG & USBFS_MODE_SETUP_RCVD);\r
+ \r
+ /* Check if SETUP bit is not set */\r
+ if (0u == tempReg)\r
{\r
/* Set the Mode Register */\r
- CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_ep0Mode);\r
+ USBFS_EP0_CR_REG = USBFS_ep0Mode;\r
+ \r
/* Writing check */\r
- modifyReg = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_MASK;\r
+ modifyReg = USBFS_EP0_CR_REG & USBFS_MODE_MASK;\r
}\r
- }while(modifyReg != USBFS_ep0Mode); /* Repeat if writing was not successful */\r
+ }\r
+ while (modifyReg != USBFS_ep0Mode);\r
}\r
}\r
}\r
}\r
- #ifdef USBFS_EP_0_ISR_EXIT_CALLBACK\r
- USBFS_EP_0_ISR_ExitCallback();\r
- #endif /* USBFS_EP_0_ISR_EXIT_CALLBACK */\r
+\r
+ USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_EP0_INTR);\r
+ \r
+#ifdef USBFS_EP_0_ISR_EXIT_CALLBACK\r
+ USBFS_EP_0_ISR_ExitCallback();\r
+#endif /* (USBFS_EP_0_ISR_EXIT_CALLBACK) */\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_HandleSetup\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This Routine dispatches requests for the four USB request types\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_HandleSetup(void) \r
{\r
uint8 requestHandled;\r
-\r
- requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */\r
- CY_SET_REG8(USBFS_EP0_CR_PTR, requestHandled); /* clear setup bit */\r
- requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* reread register */\r
- if((requestHandled & USBFS_MODE_SETUP_RCVD) != 0u)\r
+ \r
+ /* Clear register lock by SIE (read register) and clear setup bit \r
+ * (write any value in register).\r
+ */\r
+ requestHandled = (uint8) USBFS_EP0_CR_REG;\r
+ USBFS_EP0_CR_REG = (uint8) requestHandled;\r
+ requestHandled = (uint8) USBFS_EP0_CR_REG;\r
+\r
+ if ((requestHandled & USBFS_MODE_SETUP_RCVD) != 0u)\r
{\r
- USBFS_ep0Mode = requestHandled; /* if SETUP bit set -> exit without modifying the mode */\r
+ /* SETUP bit is set: exit without mode modification. */\r
+ USBFS_ep0Mode = requestHandled;\r
}\r
else\r
{\r
/* In case the previous transfer did not complete, close it out */\r
USBFS_UpdateStatusBlock(USBFS_XFER_PREMATURE);\r
\r
- switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_TYPE_MASK)\r
+ /* Check request type. */\r
+ switch (USBFS_bmRequestTypeReg & USBFS_RQST_TYPE_MASK)\r
{\r
case USBFS_RQST_TYPE_STD:\r
requestHandled = USBFS_HandleStandardRqst();\r
break;\r
+ \r
case USBFS_RQST_TYPE_CLS:\r
requestHandled = USBFS_DispatchClassRqst();\r
break;\r
+ \r
case USBFS_RQST_TYPE_VND:\r
requestHandled = USBFS_HandleVendorRqst();\r
break;\r
+ \r
default:\r
requestHandled = USBFS_FALSE;\r
break;\r
}\r
+ \r
+ /* If request is not recognized. Stall endpoint 0 IN and OUT. */\r
if (requestHandled == USBFS_FALSE)\r
{\r
USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT;\r
\r
/*******************************************************************************\r
* Function Name: USBFS_HandleIN\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine handles EP0 IN transfers.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
{\r
case USBFS_TRANS_STATE_IDLE:\r
break;\r
+ \r
case USBFS_TRANS_STATE_CONTROL_READ:\r
USBFS_ControlReadDataStage();\r
break;\r
+ \r
case USBFS_TRANS_STATE_CONTROL_WRITE:\r
USBFS_ControlWriteStatusStage();\r
break;\r
+ \r
case USBFS_TRANS_STATE_NO_DATA_CONTROL:\r
USBFS_NoDataControlStatusStage();\r
break;\r
+ \r
default: /* there are no more states */\r
break;\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_HandleOUT\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine handles EP0 OUT transfers.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
{\r
case USBFS_TRANS_STATE_IDLE:\r
break;\r
+ \r
case USBFS_TRANS_STATE_CONTROL_READ:\r
USBFS_ControlReadStatusStage();\r
break;\r
+ \r
case USBFS_TRANS_STATE_CONTROL_WRITE:\r
USBFS_ControlWriteDataStage();\r
break;\r
+ \r
case USBFS_TRANS_STATE_NO_DATA_CONTROL:\r
/* Update the completion block */\r
USBFS_UpdateStatusBlock(USBFS_XFER_ERROR);\r
+ \r
/* We expect no more data, so stall INs and OUTs */\r
USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT;\r
break;\r
- default: /* There are no more states */\r
+ \r
+ default: \r
+ /* There are no more states */\r
break;\r
}\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_LoadEP0\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* This routine loads the EP0 data registers for OUT transfers. It uses the\r
+* This routine loads the EP0 data registers for OUT transfers. It uses the\r
* currentTD (previously initialized by the _InitControlWrite function and\r
* updated for each OUT transfer, and the bLastPacketSize) to determine how\r
* many uint8s to transfer on the current OUT.\r
* of the control endpoint size (8) or remaining number of uint8s for the\r
* transaction.\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_transferByteCount - Update the transfer byte count from the\r
* last transaction.\r
* USBFS_ep0Count - counts the data loaded to the SIE memory in\r
* USBFS_ep0Mode - prepare for mode register content.\r
* USBFS_transferState - set to TRANS_STATE_CONTROL_READ\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
\r
/* Update the transfer byte count from the last transaction */\r
USBFS_transferByteCount += USBFS_lastPacketSize;\r
+\r
/* Now load the next transaction */\r
while ((USBFS_currentTD.count > 0u) && (ep0Count < 8u))\r
{\r
- CY_SET_REG8((reg8 *)(USBFS_EP0_DR0_IND + ep0Count), *USBFS_currentTD.pData);\r
+ USBFS_EP0_DR_BASE.epData[ep0Count] = (uint8) *USBFS_currentTD.pData;\r
USBFS_currentTD.pData = &USBFS_currentTD.pData[1u];\r
ep0Count++;\r
USBFS_currentTD.count--;\r
}\r
- /* Support zero-length packet*/\r
- if( (USBFS_lastPacketSize == 8u) || (ep0Count > 0u) )\r
+\r
+ /* Support zero-length packet */\r
+ if ((USBFS_lastPacketSize == 8u) || (ep0Count > 0u))\r
{\r
/* Update the data toggle */\r
USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE;\r
}\r
\r
/* Save the packet size for next time */\r
- USBFS_lastPacketSize = ep0Count;\r
- USBFS_ep0Count = ep0Count;\r
+ USBFS_ep0Count = (uint8) ep0Count;\r
+ USBFS_lastPacketSize = (uint8) ep0Count;\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_InitControlRead\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Initialize a control read transaction, usable to send data to the host.\r
+* Initialize a control read transaction. It is used to send data to the host.\r
* The following global variables should be initialized before this function\r
* called. To send zero length packet use InitZeroLengthControlTransfer\r
* function.\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
+* \return\r
* requestHandled state.\r
*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_currentTD.count - counts of data to be sent.\r
* USBFS_currentTD.pData - data pointer.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_InitControlRead(void) \r
{\r
uint16 xferCount;\r
- if(USBFS_currentTD.count == 0u)\r
+\r
+ if (USBFS_currentTD.count == 0u)\r
{\r
(void) USBFS_InitZeroLengthControlTransfer();\r
}\r
{\r
/* Set up the state machine */\r
USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ;\r
+ \r
/* Set the toggle, it gets updated in LoadEP */\r
USBFS_ep0Toggle = 0u;\r
+ \r
/* Initialize the Status Block */\r
USBFS_InitializeStatusBlock();\r
- xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo)));\r
+ \r
+ xferCount = ((uint16)((uint16) USBFS_lengthHiReg << 8u) | ((uint16) USBFS_lengthLoReg));\r
\r
if (USBFS_currentTD.count > xferCount)\r
{\r
USBFS_currentTD.count = xferCount;\r
}\r
+ \r
USBFS_LoadEP0();\r
}\r
\r
- return(USBFS_TRUE);\r
+ return (USBFS_TRUE);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_InitZeroLengthControlTransfer\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Initialize a zero length data IN transfer.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled state.\r
*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE\r
* USBFS_ep0Mode - prepare for mode register content.\r
* USBFS_transferState - set to TRANS_STATE_CONTROL_READ\r
* USBFS_ep0Count - cleared, means the zero-length packet.\r
* USBFS_lastPacketSize - cleared.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
{\r
/* Update the state */\r
USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ;\r
+ \r
/* Set the data toggle */\r
USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE;\r
+ \r
/* Set the Mode Register */\r
USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT;\r
+ \r
/* Save the packet size for next time */\r
USBFS_lastPacketSize = 0u;\r
+ \r
USBFS_ep0Count = 0u;\r
\r
- return(USBFS_TRUE);\r
+ return (USBFS_TRUE);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ControlReadDataStage\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Handle the Data Stage of a control read transfer.\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ControlReadStatusStage\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Handle the Status Stage of a control read transfer.\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_USBFS_transferByteCount - updated with last packet size.\r
* USBFS_transferState - set to TRANS_STATE_IDLE.\r
* USBFS_ep0Mode - set to MODE_STALL_IN_OUT.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
{\r
/* Update the transfer byte count */\r
USBFS_transferByteCount += USBFS_lastPacketSize;\r
+ \r
/* Go Idle */\r
USBFS_transferState = USBFS_TRANS_STATE_IDLE;\r
+ \r
/* Update the completion block */\r
USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK);\r
+ \r
/* We expect no more data, so stall INs and OUTs */\r
- USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT;\r
+ USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT;\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_InitControlWrite\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Initialize a control write transaction\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled state.\r
*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_USBFS_transferState - set to TRANS_STATE_CONTROL_WRITE\r
* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE\r
* USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
\r
/* Set up the state machine */\r
USBFS_transferState = USBFS_TRANS_STATE_CONTROL_WRITE;\r
+ \r
/* This might not be necessary */\r
USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE;\r
+ \r
/* Initialize the Status Block */\r
USBFS_InitializeStatusBlock();\r
\r
- xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo)));\r
+ xferCount = ((uint16)((uint16) USBFS_lengthHiReg << 8u) | ((uint16) USBFS_lengthLoReg));\r
\r
if (USBFS_currentTD.count > xferCount)\r
{\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ControlWriteDataStage\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Handle the Data Stage of a control write transfer\r
* 1. Get the data (We assume the destination was validated previously)\r
* 2. Update the count and data toggle\r
* 3. Update the mode register for the next transaction\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_transferByteCount - Update the transfer byte count from the\r
* last transaction.\r
* USBFS_ep0Count - counts the data loaded from the SIE memory\r
* USBFS_ep0Toggle - inverted\r
* USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 ep0Count;\r
uint8 regIndex = 0u;\r
\r
- ep0Count = (CY_GET_REG8(USBFS_EP0_CNT_PTR) & USBFS_EPX_CNT0_MASK) -\r
- USBFS_EPX_CNTX_CRC_COUNT;\r
+ ep0Count = (USBFS_EP0_CNT_REG & USBFS_EPX_CNT0_MASK) - USBFS_EPX_CNTX_CRC_COUNT;\r
\r
- USBFS_transferByteCount += ep0Count;\r
+ USBFS_transferByteCount += (uint8)ep0Count;\r
\r
while ((USBFS_currentTD.count > 0u) && (ep0Count > 0u))\r
{\r
- *USBFS_currentTD.pData = CY_GET_REG8((reg8 *)(USBFS_EP0_DR0_IND + regIndex));\r
+ *USBFS_currentTD.pData = (uint8) USBFS_EP0_DR_BASE.epData[regIndex];\r
USBFS_currentTD.pData = &USBFS_currentTD.pData[1u];\r
regIndex++;\r
ep0Count--;\r
USBFS_currentTD.count--;\r
}\r
- USBFS_ep0Count = ep0Count;\r
+ \r
+ USBFS_ep0Count = (uint8)ep0Count;\r
+ \r
/* Update the data toggle */\r
USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE;\r
+ \r
/* Expect Data or Status Stage */\r
USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN;\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ControlWriteStatusStage\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Handle the Status Stage of a control write transfer\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_transferState - set to TRANS_STATE_IDLE.\r
* USBFS_USBFS_ep0Mode - set to MODE_STALL_IN_OUT.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
{\r
/* Go Idle */\r
USBFS_transferState = USBFS_TRANS_STATE_IDLE;\r
- /* Update the completion block */\r
+ \r
+ /* Update the completion block */ \r
USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK);\r
+ \r
/* We expect no more data, so stall INs and OUTs */\r
USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_InitNoDataControlTransfer\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Initialize a no data control transfer\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled state.\r
*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_transferState - set to TRANS_STATE_NO_DATA_CONTROL.\r
* USBFS_ep0Mode - set to MODE_STATUS_IN_ONLY.\r
* USBFS_ep0Count - cleared.\r
* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_InitNoDataControlTransfer(void) \r
{\r
USBFS_transferState = USBFS_TRANS_STATE_NO_DATA_CONTROL;\r
- USBFS_ep0Mode = USBFS_MODE_STATUS_IN_ONLY;\r
- USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE;\r
- USBFS_ep0Count = 0u;\r
+ USBFS_ep0Mode = USBFS_MODE_STATUS_IN_ONLY;\r
+ USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE;\r
+ USBFS_ep0Count = 0u;\r
\r
- return(USBFS_TRUE);\r
+ return (USBFS_TRUE);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_NoDataControlStatusStage\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Handle the Status Stage of a no data control transfer.\r
*\r
* SET_ADDRESS is special, since we need to receive the status stage with\r
* the old address.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_transferState - set to TRANS_STATE_IDLE.\r
* USBFS_ep0Mode - set to MODE_STALL_IN_OUT.\r
* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE\r
* USBFS_deviceAddress - used to set new address and cleared\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_NoDataControlStatusStage(void) \r
{\r
- /* Change the USB address register if we got a SET_ADDRESS. */\r
- if (USBFS_deviceAddress != 0u)\r
+ if (0u != USBFS_deviceAddress)\r
{\r
- CY_SET_REG8(USBFS_CR0_PTR, USBFS_deviceAddress | USBFS_CR0_ENABLE);\r
+ /* Update device address if we got new address. */\r
+ USBFS_CR0_REG = (uint8) USBFS_deviceAddress | USBFS_CR0_ENABLE;\r
USBFS_deviceAddress = 0u;\r
}\r
- /* Go Idle */\r
+\r
USBFS_transferState = USBFS_TRANS_STATE_IDLE;\r
- /* Update the completion block */\r
+ \r
+ /* Update the completion block. */\r
USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK);\r
- /* We expect no more data, so stall INs and OUTs */\r
+ \r
+ /* Stall IN and OUT, no more data is expected. */\r
USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT;\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_UpdateStatusBlock\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Update the Completion Status Block for a Request. The block is updated\r
* with the completion code the USBFS_transferByteCount. The\r
* StatusBlock Pointer is set to NULL.\r
*\r
-* Parameters:\r
* completionCode - status.\r
*\r
-* Return:\r
-* None.\r
*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_currentTD.pStatusBlock->status - updated by the\r
* completionCode parameter.\r
* USBFS_currentTD.pStatusBlock->length - updated.\r
* USBFS_currentTD.pStatusBlock - cleared.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: USBFS_InitializeStatusBlock\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Initialize the Completion Status Block for a Request. The completion\r
* code is set to USB_XFER_IDLE.\r
*\r
* Also, initializes USBFS_transferByteCount. Save some space,\r
* this is the only consumer.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_currentTD.pStatusBlock->status - set to XFER_IDLE.\r
* USBFS_currentTD.pStatusBlock->length - cleared.\r
* USBFS_transferByteCount - cleared.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_InitializeStatusBlock(void) \r
{\r
USBFS_transferByteCount = 0u;\r
- if(USBFS_currentTD.pStatusBlock != NULL)\r
+ \r
+ if (USBFS_currentTD.pStatusBlock != NULL)\r
{\r
USBFS_currentTD.pStatusBlock->status = USBFS_XFER_IDLE;\r
USBFS_currentTD.pStatusBlock->length = 0u;\r
-/*******************************************************************************\r
-* File Name: USBFS_episr.c\r
-* Version 2.80\r
-*\r
-* Description:\r
-* Data endpoint Interrupt Service Routines\r
+/***************************************************************************//**\r
+* \file USBFS_episr.c\r
+* \version 3.10\r
*\r
-* Note:\r
+* \brief\r
+* This file contains the Data endpoint Interrupt Service Routines.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
#include "USBFS_pvt.h"\r
+#include "USBFS_cydmac.h"\r
\r
-#if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u))\r
- #include "USBFS_midi.h"\r
-#endif /* (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)) */\r
-#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- #include "USBFS_EP8_DMA_Done_SR.h"\r
- #include "USBFS_EP17_DMA_Done_SR.h"\r
-#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
\r
\r
/***************************************\r
/* `#END` */\r
\r
\r
-#if(USBFS_EP1_ISR_REMOVE == 0u)\r
-\r
-\r
+#if (USBFS_EP1_ISR_ACTIVE)\r
/******************************************************************************\r
* Function Name: USBFS_EP_1_ISR\r
- *******************************************************************************\r
+ ***************************************************************************//**\r
*\r
- * Summary:\r
* Endpoint 1 Interrupt Service Routine\r
*\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
******************************************************************************/\r
CY_ISR(USBFS_EP_1_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
\r
- #ifdef USBFS_EP_1_ISR_ENTRY_CALLBACK\r
- USBFS_EP_1_ISR_EntryCallback();\r
- #endif /* USBFS_EP_1_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_EP_1_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_1_ISR_EntryCallback();\r
+ #endif /* (USBFS_EP_1_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START EP1_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
-\r
- CY_GET_REG8(USBFS_SIE_EP1_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_EP[USBFS_EP1].attrib & USBFS_EP_TYPE_MASK) !=\r
- USBFS_EP_TYPE_ISOC)\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
{\r
- USBFS_EP[USBFS_EP1].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ uint8 intEn = EA;\r
+ CyGlobalIntEnable; /* Enable nested interrupts. */\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ \r
+ USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP1_INTR);\r
+ \r
+ /* Notifies user that transfer IN or OUT transfer is completed.\r
+ * IN endpoint: endpoint buffer can be reloaded, Host is read data.\r
+ * OUT endpoint: data is ready to be read from endpoint buffer. \r
+ */\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (0u != (USBFS_EP[USBFS_EP1].addr & USBFS_DIR_IN))\r
+ #endif /* (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ {\r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP1].epCr0;\r
+ \r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(USBFS_EP1) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[USBFS_EP1].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+\r
+ /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify\r
+ * user that DMA has completed copying data from OUT endpoint which is not completely true.\r
+ * Because last chunk of data is being copied.\r
+ * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast.\r
+ * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN).\r
+ */\r
+ USBFS_EP[USBFS_EP1].apiEpState = USBFS_EVENT_PENDING;\r
}\r
- USBFS_EP[USBFS_EP1].apiEpState = USBFS_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) &\r
- (uint8)~USBFS_SIE_EP_INT_EP1_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_midi_out_ep == USBFS_EP1)\r
+ #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO))\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ if (USBFS_midi_out_ep == USBFS_EP1)\r
{\r
- USBFS_MIDI_OUT_EP_Service();\r
+ USBFS_MIDI_OUT_Service();\r
}\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */\r
+ \r
/* `#START EP1_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_EP_1_ISR_EXIT_CALLBACK\r
- USBFS_EP_1_ISR_ExitCallback();\r
- #endif /* USBFS_EP_1_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_EP_1_ISR_EXIT_CALLBACK\r
+ USBFS_EP_1_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_1_ISR_EXIT_CALLBACK) */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ \r
+ EA = intEn; /* Restore nested interrupt configuration. */\r
+ }\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
}\r
\r
-#endif /* USBFS_EP1_ISR_REMOVE */\r
-\r
+#endif /* (USBFS_EP1_ISR_ACTIVE) */\r
\r
-#if(USBFS_EP2_ISR_REMOVE == 0u)\r
\r
+#if (USBFS_EP2_ISR_ACTIVE)\r
/*******************************************************************************\r
* Function Name: USBFS_EP_2_ISR\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Endpoint 2 Interrupt Service Routine\r
- *\r
- * Parameters:\r
- * None.\r
+ ****************************************************************************//**\r
*\r
- * Return:\r
- * None.\r
+ * Endpoint 2 Interrupt Service Routine.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_2_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
-\r
- #ifdef USBFS_EP_2_ISR_ENTRY_CALLBACK\r
- USBFS_EP_2_ISR_EntryCallback();\r
- #endif /* USBFS_EP_2_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_EP_2_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_2_ISR_EntryCallback();\r
+ #endif /* (USBFS_EP_2_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START EP2_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
-\r
- CY_GET_REG8(USBFS_SIE_EP2_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_EP[USBFS_EP2].attrib & USBFS_EP_TYPE_MASK) !=\r
- USBFS_EP_TYPE_ISOC)\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
{\r
- USBFS_EP[USBFS_EP2].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ uint8 intEn = EA;\r
+ CyGlobalIntEnable; /* Enable nested interrupts. */\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
+\r
+ USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP2_INTR);\r
+\r
+ /* Notifies user that transfer IN or OUT transfer is completed.\r
+ * IN endpoint: endpoint buffer can be reloaded, Host is read data.\r
+ * OUT endpoint: data is ready to be read from endpoint buffer. \r
+ */\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (0u != (USBFS_EP[USBFS_EP2].addr & USBFS_DIR_IN))\r
+ #endif /* (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ { \r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP2].epCr0;\r
+ \r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(USBFS_EP2) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[USBFS_EP2].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+\r
+ /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify\r
+ * user that DMA has completed copying data from OUT endpoint which is not completely true.\r
+ * Because last chunk of data is being copied.\r
+ * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast.\r
+ * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN).\r
+ */\r
+ USBFS_EP[USBFS_EP2].apiEpState = USBFS_EVENT_PENDING;\r
}\r
- USBFS_EP[USBFS_EP2].apiEpState = USBFS_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_SIE_EP_INT_EP2_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_midi_out_ep == USBFS_EP2)\r
+ #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO))\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ if (USBFS_midi_out_ep == USBFS_EP2)\r
{\r
- USBFS_MIDI_OUT_EP_Service();\r
+ USBFS_MIDI_OUT_Service();\r
}\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ \r
+ \r
/* `#START EP2_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_EP_2_ISR_EXIT_CALLBACK\r
- USBFS_EP_2_ISR_ExitCallback();\r
- #endif /* USBFS_EP_2_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_EP_2_ISR_EXIT_CALLBACK\r
+ USBFS_EP_2_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_2_ISR_EXIT_CALLBACK) */\r
+\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
+ EA = intEn; /* Restore nested interrupt configuration. */\r
+ }\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
}\r
+#endif /* (USBFS_EP2_ISR_ACTIVE) */\r
\r
-#endif /* USBFS_EP2_ISR_REMOVE */\r
-\r
-\r
-#if(USBFS_EP3_ISR_REMOVE == 0u)\r
\r
+#if (USBFS_EP3_ISR_ACTIVE)\r
/*******************************************************************************\r
* Function Name: USBFS_EP_3_ISR\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Endpoint 3 Interrupt Service Routine\r
- *\r
- * Parameters:\r
- * None.\r
+ ****************************************************************************//**\r
*\r
- * Return:\r
- * None.\r
+ * Endpoint 3 Interrupt Service Routine.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_3_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
-\r
- #ifdef USBFS_EP_3_ISR_ENTRY_CALLBACK\r
- USBFS_EP_3_ISR_EntryCallback();\r
- #endif /* USBFS_EP_3_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_EP_3_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_3_ISR_EntryCallback();\r
+ #endif /* (USBFS_EP_3_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START EP3_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
- CY_GET_REG8(USBFS_SIE_EP3_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_EP[USBFS_EP3].attrib & USBFS_EP_TYPE_MASK) !=\r
- USBFS_EP_TYPE_ISOC)\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
{\r
- USBFS_EP[USBFS_EP3].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ uint8 intEn = EA;\r
+ CyGlobalIntEnable; /* Enable nested interrupts. */\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
+\r
+ USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP3_INTR); \r
+\r
+ /* Notifies user that transfer IN or OUT transfer is completed.\r
+ * IN endpoint: endpoint buffer can be reloaded, Host is read data.\r
+ * OUT endpoint: data is ready to be read from endpoint buffer. \r
+ */\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (0u != (USBFS_EP[USBFS_EP3].addr & USBFS_DIR_IN))\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ { \r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP3].epCr0;\r
+\r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(USBFS_EP3) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[USBFS_EP3].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+\r
+ /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify\r
+ * user that DMA has completed copying data from OUT endpoint which is not completely true.\r
+ * Because last chunk of data is being copied.\r
+ * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast.\r
+ * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN).\r
+ */\r
+ USBFS_EP[USBFS_EP3].apiEpState = USBFS_EVENT_PENDING;\r
}\r
- USBFS_EP[USBFS_EP3].apiEpState = USBFS_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_SIE_EP_INT_EP3_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_midi_out_ep == USBFS_EP3)\r
+ #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO))\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ if (USBFS_midi_out_ep == USBFS_EP3)\r
{\r
- USBFS_MIDI_OUT_EP_Service();\r
+ USBFS_MIDI_OUT_Service();\r
}\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ \r
\r
/* `#START EP3_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_EP_3_ISR_EXIT_CALLBACK\r
- USBFS_EP_3_ISR_ExitCallback();\r
- #endif /* USBFS_EP_3_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_EP_3_ISR_EXIT_CALLBACK\r
+ USBFS_EP_3_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_3_ISR_EXIT_CALLBACK) */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ \r
+ EA = intEn; /* Restore nested interrupt configuration. */\r
+ }\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
}\r
+#endif /* (USBFS_EP3_ISR_ACTIVE) */\r
\r
-#endif /* USBFS_EP3_ISR_REMOVE */\r
-\r
-\r
-#if(USBFS_EP4_ISR_REMOVE == 0u)\r
\r
+#if (USBFS_EP4_ISR_ACTIVE)\r
/*******************************************************************************\r
* Function Name: USBFS_EP_4_ISR\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
- * Endpoint 4 Interrupt Service Routine\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
+ * Endpoint 4 Interrupt Service Routine.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_4_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
- #ifdef USBFS_EP_4_ISR_ENTRY_CALLBACK\r
- USBFS_EP_4_ISR_EntryCallback();\r
- #endif /* USBFS_EP_4_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_EP_4_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_4_ISR_EntryCallback();\r
+ #endif /* (USBFS_EP_4_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START EP4_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ {\r
+ uint8 intEn = EA;\r
+ CyGlobalIntEnable; /* Enable nested interrupts. */\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
\r
- CY_GET_REG8(USBFS_SIE_EP4_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_EP[USBFS_EP4].attrib & USBFS_EP_TYPE_MASK) !=\r
- USBFS_EP_TYPE_ISOC)\r
+ USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP4_INTR);\r
+ \r
+ /* Notifies user that transfer IN or OUT transfer is completed.\r
+ * IN endpoint: endpoint buffer can be reloaded, Host is read data.\r
+ * OUT endpoint: data is ready to read from endpoint buffer. \r
+ */\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (0u != (USBFS_EP[USBFS_EP4].addr & USBFS_DIR_IN))\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
{\r
- USBFS_EP[USBFS_EP4].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP4].epCr0;\r
+\r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(USBFS_EP4) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[USBFS_EP4].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+\r
+ /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify\r
+ * user that DMA has completed copying data from OUT endpoint which is not completely true.\r
+ * Because last chunk of data is being copied.\r
+ * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast.\r
+ * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN).\r
+ */\r
+ USBFS_EP[USBFS_EP4].apiEpState = USBFS_EVENT_PENDING;\r
}\r
- USBFS_EP[USBFS_EP4].apiEpState = USBFS_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_SIE_EP_INT_EP4_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT)\r
+ #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO))\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP4)\r
{\r
- USBFS_MIDI_OUT_EP_Service();\r
+ USBFS_MIDI_OUT_Service();\r
}\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ \r
\r
/* `#START EP4_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_EP_4_ISR_EXIT_CALLBACK\r
- USBFS_EP_4_ISR_ExitCallback();\r
- #endif /* USBFS_EP_4_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_EP_4_ISR_EXIT_CALLBACK\r
+ USBFS_EP_4_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_4_ISR_EXIT_CALLBACK) */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ \r
+ EA = intEn; /* Restore nested interrupt configuration. */\r
+ }\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
}\r
-\r
-#endif /* USBFS_EP4_ISR_REMOVE */\r
+#endif /* (USBFS_EP4_ISR_ACTIVE) */\r
\r
\r
-#if(USBFS_EP5_ISR_REMOVE == 0u)\r
-\r
+#if (USBFS_EP5_ISR_ACTIVE)\r
/*******************************************************************************\r
* Function Name: USBFS_EP_5_ISR\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Endpoint 5 Interrupt Service Routine\r
*\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_5_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
- #ifdef USBFS_EP_5_ISR_ENTRY_CALLBACK\r
- USBFS_EP_5_ISR_EntryCallback();\r
- #endif /* USBFS_EP_5_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_EP_5_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_5_ISR_EntryCallback();\r
+ #endif /* (USBFS_EP_5_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START EP5_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
- CY_GET_REG8(USBFS_SIE_EP5_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_EP[USBFS_EP5].attrib & USBFS_EP_TYPE_MASK) !=\r
- USBFS_EP_TYPE_ISOC)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
{\r
- USBFS_EP[USBFS_EP5].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ uint8 intEn = EA;\r
+ CyGlobalIntEnable; /* Enable nested interrupts. */\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
+\r
+ USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP5_INTR);\r
+ \r
+ /* Notifies user that transfer IN or OUT transfer is completed.\r
+ * IN endpoint: endpoint buffer can be reloaded, Host is read data.\r
+ * OUT endpoint: data is ready to read from endpoint buffer. \r
+ */\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (0u != (USBFS_EP[USBFS_EP5].addr & USBFS_DIR_IN))\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ { \r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP5].epCr0;\r
+\r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(USBFS_EP5) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[USBFS_EP5].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+\r
+ /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify\r
+ * user that DMA has completed copying data from OUT endpoint which is not completely true.\r
+ * Because last chunk of data is being copied.\r
+ * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast.\r
+ * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN).\r
+ */\r
+ USBFS_EP[USBFS_EP5].apiEpState = USBFS_EVENT_PENDING;\r
}\r
- USBFS_EP[USBFS_EP5].apiEpState = USBFS_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_SIE_EP_INT_EP5_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_midi_out_ep == USBFS_EP5)\r
+ #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) \r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ if (USBFS_midi_out_ep == USBFS_EP5)\r
{\r
- USBFS_MIDI_OUT_EP_Service();\r
+ USBFS_MIDI_OUT_Service();\r
}\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */\r
\r
/* `#START EP5_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_EP_5_ISR_EXIT_CALLBACK\r
- USBFS_EP_5_ISR_ExitCallback();\r
- #endif /* USBFS_EP_5_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_EP_5_ISR_EXIT_CALLBACK\r
+ USBFS_EP_5_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_5_ISR_EXIT_CALLBACK) */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ \r
+ EA = intEn; /* Restore nested interrupt configuration. */\r
+ }\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
}\r
-#endif /* USBFS_EP5_ISR_REMOVE */\r
-\r
+#endif /* (USBFS_EP5_ISR_ACTIVE) */\r
\r
-#if(USBFS_EP6_ISR_REMOVE == 0u)\r
\r
+#if (USBFS_EP6_ISR_ACTIVE)\r
/*******************************************************************************\r
* Function Name: USBFS_EP_6_ISR\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
- * Endpoint 6 Interrupt Service Routine\r
+ * Endpoint 6 Interrupt Service Routine.\r
*\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_6_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
- #ifdef USBFS_EP_6_ISR_ENTRY_CALLBACK\r
- USBFS_EP_6_ISR_EntryCallback();\r
- #endif /* USBFS_EP_6_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_EP_6_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_6_ISR_EntryCallback();\r
+ #endif /* (USBFS_EP_6_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START EP6_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ {\r
+ uint8 intEn = EA;\r
+ CyGlobalIntEnable; /* Enable nested interrupts. */\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
\r
- CY_GET_REG8(USBFS_SIE_EP6_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_EP[USBFS_EP6].attrib & USBFS_EP_TYPE_MASK) !=\r
- USBFS_EP_TYPE_ISOC)\r
+ USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP6_INTR);\r
+ \r
+ /* Notifies user that transfer IN or OUT transfer is completed.\r
+ * IN endpoint: endpoint buffer can be reloaded, Host is read data.\r
+ * OUT endpoint: data is ready to read from endpoint buffer. \r
+ */\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (0u != (USBFS_EP[USBFS_EP6].addr & USBFS_DIR_IN))\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
{\r
- USBFS_EP[USBFS_EP6].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP6].epCr0;\r
+\r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(USBFS_EP6) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[USBFS_EP6].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+ \r
+ /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify\r
+ * user that DMA has completed copying data from OUT endpoint which is not completely true.\r
+ * Because last chunk of data is being copied.\r
+ * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast.\r
+ * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN).\r
+ */\r
+ USBFS_EP[USBFS_EP6].apiEpState = USBFS_EVENT_PENDING;\r
}\r
- USBFS_EP[USBFS_EP6].apiEpState = USBFS_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_SIE_EP_INT_EP6_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_midi_out_ep == USBFS_EP6)\r
+ #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO))\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ if (USBFS_midi_out_ep == USBFS_EP6)\r
{\r
- USBFS_MIDI_OUT_EP_Service();\r
+ USBFS_MIDI_OUT_Service();\r
}\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */\r
\r
/* `#START EP6_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_EP_6_ISR_EXIT_CALLBACK\r
- USBFS_EP_6_ISR_ExitCallback();\r
- #endif /* USBFS_EP_6_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_EP_6_ISR_EXIT_CALLBACK\r
+ USBFS_EP_6_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_6_ISR_EXIT_CALLBACK) */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ \r
+ EA = intEn; /* Restore nested interrupt configuration. */\r
+ }\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
}\r
+#endif /* (USBFS_EP6_ISR_ACTIVE) */\r
\r
-#endif /* USBFS_EP6_ISR_REMOVE */\r
-\r
-\r
-#if(USBFS_EP7_ISR_REMOVE == 0u)\r
\r
+#if (USBFS_EP7_ISR_ACTIVE)\r
/*******************************************************************************\r
* Function Name: USBFS_EP_7_ISR\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
- * Endpoint 7 Interrupt Service Routine\r
+ * Endpoint 7 Interrupt Service Routine.\r
*\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_7_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
- #ifdef USBFS_EP_7_ISR_ENTRY_CALLBACK\r
- USBFS_EP_7_ISR_EntryCallback();\r
- #endif /* USBFS_EP_7_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_EP_7_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_7_ISR_EntryCallback();\r
+ #endif /* (USBFS_EP_7_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START EP7_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
- CY_GET_REG8(USBFS_SIE_EP7_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_EP[USBFS_EP7].attrib & USBFS_EP_TYPE_MASK) !=\r
- USBFS_EP_TYPE_ISOC)\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
{\r
- USBFS_EP[USBFS_EP7].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ uint8 intEn = EA;\r
+ CyGlobalIntEnable; /* Enable nested interrupts. */\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ \r
+ USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP7_INTR);\r
+ \r
+ /* Notifies user that transfer IN or OUT transfer is completed.\r
+ * IN endpoint: endpoint buffer can be reloaded, Host is read data.\r
+ * OUT endpoint: data is ready to read from endpoint buffer. \r
+ */\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (0u != (USBFS_EP[USBFS_EP7].addr & USBFS_DIR_IN))\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ { \r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP7].epCr0;\r
+\r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(USBFS_EP7) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[USBFS_EP7].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+ \r
+ /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify\r
+ * user that DMA has completed copying data from OUT endpoint which is not completely true.\r
+ * Because last chunk of data is being copied.\r
+ * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast.\r
+ * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN).\r
+ */\r
+ USBFS_EP[USBFS_EP7].apiEpState = USBFS_EVENT_PENDING;\r
}\r
- USBFS_EP[USBFS_EP7].apiEpState = USBFS_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_SIE_EP_INT_EP7_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT)\r
+\r
+ #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO))\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP7)\r
{\r
- USBFS_MIDI_OUT_EP_Service();\r
+ USBFS_MIDI_OUT_Service();\r
}\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */\r
\r
/* `#START EP7_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_EP_7_ISR_EXIT_CALLBACK\r
- USBFS_EP_7_ISR_ExitCallback();\r
- #endif /* USBFS_EP_7_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_EP_7_ISR_EXIT_CALLBACK\r
+ USBFS_EP_7_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_7_ISR_EXIT_CALLBACK) */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ \r
+ EA = intEn; /* Restore nested interrupt configuration. */\r
+ }\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
}\r
-\r
-#endif /* USBFS_EP7_ISR_REMOVE */\r
+#endif /* (USBFS_EP7_ISR_ACTIVE) */\r
\r
\r
-#if(USBFS_EP8_ISR_REMOVE == 0u)\r
-\r
+#if (USBFS_EP8_ISR_ACTIVE)\r
/*******************************************************************************\r
* Function Name: USBFS_EP_8_ISR\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Endpoint 8 Interrupt Service Routine\r
*\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_8_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
- #ifdef USBFS_EP_8_ISR_ENTRY_CALLBACK\r
- USBFS_EP_8_ISR_EntryCallback();\r
- #endif /* USBFS_EP_8_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_EP_8_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_8_ISR_EntryCallback();\r
+ #endif /* (USBFS_EP_8_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START EP8_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ {\r
+ uint8 intEn = EA;\r
+ CyGlobalIntEnable; /* Enable nested interrupts. */\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
\r
- CY_GET_REG8(USBFS_SIE_EP8_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_EP[USBFS_EP8].attrib & USBFS_EP_TYPE_MASK) !=\r
- USBFS_EP_TYPE_ISOC)\r
+ USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP8_INTR);\r
+ \r
+ /* Notifies user that transfer IN or OUT transfer is completed.\r
+ * IN endpoint: endpoint buffer can be reloaded, Host is read data.\r
+ * OUT endpoint: data is ready to read from endpoint buffer. \r
+ */\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (0u != (USBFS_EP[USBFS_EP8].addr & USBFS_DIR_IN))\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
{\r
- USBFS_EP[USBFS_EP8].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP8].epCr0;\r
+\r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(USBFS_EP8) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[USBFS_EP8].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+\r
+ /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify\r
+ * user that DMA has completed copying data from OUT endpoint which is not completely true.\r
+ * Because last chunk of data is being copied.\r
+ * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast.\r
+ * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN).\r
+ */\r
+ USBFS_EP[USBFS_EP8].apiEpState = USBFS_EVENT_PENDING;\r
}\r
- USBFS_EP[USBFS_EP8].apiEpState = USBFS_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_SIE_EP_INT_EP8_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_midi_out_ep == USBFS_EP8)\r
+ #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO))\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ if (USBFS_midi_out_ep == USBFS_EP8)\r
{\r
- USBFS_MIDI_OUT_EP_Service();\r
+ USBFS_MIDI_OUT_Service();\r
}\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */\r
\r
/* `#START EP8_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_EP_8_ISR_EXIT_CALLBACK\r
- USBFS_EP_8_ISR_ExitCallback();\r
- #endif /* USBFS_EP_8_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_EP_8_ISR_EXIT_CALLBACK\r
+ USBFS_EP_8_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_8_ISR_EXIT_CALLBACK) */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ \r
+ EA = intEn; /* Restore nested interrupt configuration. */\r
+ }\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
}\r
+#endif /* (USBFS_EP8_ISR_ACTIVE) */\r
\r
-#endif /* USBFS_EP8_ISR_REMOVE */\r
\r
+#if (USBFS_SOF_ISR_ACTIVE)\r
+ /*******************************************************************************\r
+ * Function Name: USBFS_SOF_ISR\r
+ ****************************************************************************//**\r
+ *\r
+ * Start of Frame Interrupt Service Routine.\r
+ *\r
+ *\r
+ *******************************************************************************/\r
+ CY_ISR(USBFS_SOF_ISR)\r
+ {\r
+ #ifdef USBFS_SOF_ISR_ENTRY_CALLBACK\r
+ USBFS_SOF_ISR_EntryCallback();\r
+ #endif /* (USBFS_SOF_ISR_ENTRY_CALLBACK) */\r
\r
-/*******************************************************************************\r
-* Function Name: USBFS_SOF_ISR\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Start of Frame Interrupt Service Routine\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-*******************************************************************************/\r
-CY_ISR(USBFS_SOF_ISR)\r
-{\r
- #ifdef USBFS_SOF_ISR_INTERRUPT_CALLBACK\r
- USBFS_SOF_ISR_InterruptCallback();\r
- #endif /* USBFS_SOF_ISR_INTERRUPT_CALLBACK */\r
+ /* `#START SOF_USER_CODE` Place your code here */\r
+\r
+ /* `#END` */\r
\r
- /* `#START SOF_USER_CODE` Place your code here */\r
+ USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_SOF_INTR);\r
\r
- /* `#END` */\r
-}\r
+ #ifdef USBFS_SOF_ISR_EXIT_CALLBACK\r
+ USBFS_SOF_ISR_ExitCallback();\r
+ #endif /* (USBFS_SOF_ISR_EXIT_CALLBACK) */\r
+ }\r
+#endif /* (USBFS_SOF_ISR_ACTIVE) */\r
\r
\r
+#if (USBFS_BUS_RESET_ISR_ACTIVE)\r
/*******************************************************************************\r
* Function Name: USBFS_BUS_RESET_ISR\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* USB Bus Reset Interrupt Service Routine. Calls _Start with the same\r
* parameters as the last USER call to _Start\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_BUS_RESET_ISR)\r
{\r
- #ifdef USBFS_BUS_RESET_ISR_ENTRY_CALLBACK\r
- USBFS_BUS_RESET_ISR_EntryCallback();\r
- #endif /* USBFS_BUS_RESET_ISR_ENTRY_CALLBACK */\r
+#ifdef USBFS_BUS_RESET_ISR_ENTRY_CALLBACK\r
+ USBFS_BUS_RESET_ISR_EntryCallback();\r
+#endif /* (USBFS_BUS_RESET_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START BUS_RESET_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
+ USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_BUS_RESET_INTR);\r
+\r
USBFS_ReInitComponent();\r
\r
- #ifdef USBFS_BUS_RESET_ISR_EXIT_CALLBACK\r
- USBFS_BUS_RESET_ISR_ExitCallback();\r
- #endif /* USBFS_BUS_RESET_ISR_EXIT_CALLBACK */ \r
+#ifdef USBFS_BUS_RESET_ISR_EXIT_CALLBACK\r
+ USBFS_BUS_RESET_ISR_ExitCallback();\r
+#endif /* (USBFS_BUS_RESET_ISR_EXIT_CALLBACK) */\r
}\r
+#endif /* (USBFS_BUS_RESET_ISR_ACTIVE) */\r
+\r
\r
+#if (USBFS_LPM_ACTIVE)\r
+/***************************************************************************\r
+* Function Name: USBFS_INTR_LPM_ISR\r
+************************************************************************//**\r
+*\r
+* Interrupt Service Routine for LPM of the interrupt sources.\r
+*\r
+*\r
+***************************************************************************/\r
+CY_ISR(USBFS_LPM_ISR)\r
+{\r
+#ifdef USBFS_LPM_ISR_ENTRY_CALLBACK\r
+ USBFS_LPM_ISR_EntryCallback();\r
+#endif /* (USBFS_LPM_ISR_ENTRY_CALLBACK) */\r
\r
-#if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))\r
+ /* `#START LPM_BEGIN_USER_CODE` Place your code here */\r
\r
+ /* `#END` */\r
\r
- /*******************************************************************************\r
+ USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_LPM_INTR);\r
+\r
+ /* `#START LPM_END_USER_CODE` Place your code here */\r
+\r
+ /* `#END` */\r
+\r
+#ifdef USBFS_LPM_ISR_EXIT_CALLBACK\r
+ USBFS_LPM_ISR_ExitCallback();\r
+#endif /* (USBFS_LPM_ISR_EXIT_CALLBACK) */\r
+}\r
+#endif /* (USBFS_LPM_ACTIVE) */\r
+\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE)\r
+ /***************************************************************************\r
* Function Name: USBFS_ARB_ISR\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Arbiter Interrupt Service Routine\r
+ ************************************************************************//**\r
*\r
- * Parameters:\r
- * None.\r
+ * Arbiter Interrupt Service Routine.\r
*\r
- * Return:\r
- * None.\r
*\r
- * Side effect:\r
- * Search for EP8 int_status will be much slower than search for EP1 int_status.\r
- *\r
- *******************************************************************************/\r
+ ***************************************************************************/\r
CY_ISR(USBFS_ARB_ISR)\r
{\r
- uint8 int_status;\r
- uint8 ep_status;\r
+ uint8 arbIntrStatus;\r
+ uint8 epStatus;\r
uint8 ep = USBFS_EP1;\r
- uint8 ptr = 0u;\r
\r
- #ifdef USBFS_ARB_ISR_ENTRY_CALLBACK\r
- USBFS_ARB_ISR_EntryCallback();\r
- #endif /* USBFS_ARB_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_ARB_ISR_ENTRY_CALLBACK\r
+ USBFS_ARB_ISR_EntryCallback();\r
+ #endif /* (USBFS_ARB_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START ARB_BEGIN_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- int_status = USBFS_ARB_INT_SR_REG; /* read Arbiter Status Register */\r
- USBFS_ARB_INT_SR_REG = int_status; /* Clear Serviced Interrupts */\r
+ /* Get pending ARB interrupt sources. */\r
+ arbIntrStatus = USBFS_ARB_INT_SR_REG;\r
\r
- while(int_status != 0u)\r
+ while (0u != arbIntrStatus)\r
{\r
- if((int_status & 1u) != 0u) /* If EpX interrupt present */\r
- { /* read Endpoint Status Register */\r
- ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr));\r
- /* If In Buffer Full */\r
- if((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) != 0u)\r
+ /* Check which EP is interrupt source. */\r
+ if (0u != (arbIntrStatus & 0x01u))\r
+ {\r
+ /* Get endpoint enable interrupt sources. */\r
+ epStatus = (USBFS_ARB_EP_BASE.arbEp[ep].epSr & USBFS_ARB_EP_BASE.arbEp[ep].epIntEn);\r
+\r
+ /* Handle IN endpoint buffer full event: happens only once when endpoint buffer is loaded. */\r
+ if (0u != (epStatus & USBFS_ARB_EPX_INT_IN_BUF_FULL))\r
{\r
- if((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u)\r
+ if (0u != (USBFS_EP[ep].addr & USBFS_DIR_IN))\r
{\r
- /* Clear Data ready status */\r
- *(reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) &=\r
- (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
- #if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- /* Setup common area DMA with rest of the data */\r
+ /* Clear data ready status. */\r
+ USBFS_ARB_EP_BASE.arbEp[ep].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+\r
+ #if (CY_PSOC3 || CY_PSOC5LP)\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ /* Set up common area DMA with rest of data. */\r
if(USBFS_inLength[ep] > USBFS_DMA_BYTES_PER_BURST)\r
{\r
USBFS_LoadNextInEP(ep, 0u);\r
{\r
USBFS_inBufFull[ep] = 1u;\r
}\r
- #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
- /* Write the Mode register */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), USBFS_EP[ep].epMode);\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN)\r
- if(ep == USBFS_midi_in_ep)\r
- { /* Clear MIDI input pointer */\r
- USBFS_midiInPointer = 0u;\r
- }\r
- #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+ /* Arm IN endpoint. */\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_EP[ep].epMode;\r
+\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN)\r
+ if (ep == USBFS_midi_in_ep)\r
+ {\r
+ /* Clear MIDI input pointer. */\r
+ USBFS_midiInPointer = 0u;\r
+ }\r
+ #endif /* (USBFS_ENABLE_MIDI_STREAMING) */\r
}\r
}\r
- /* (re)arm Out EP only for mode2 */\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- /* If DMA Grant */\r
- if((ep_status & USBFS_ARB_EPX_SR_DMA_GNT) != 0u)\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ /* Handle DMA completion event for OUT endpoints. */\r
+ if (0u != (epStatus & USBFS_ARB_EPX_SR_DMA_GNT))\r
+ {\r
+ if (0u == (USBFS_EP[ep].addr & USBFS_DIR_IN))\r
{\r
- if((USBFS_EP[ep].addr & USBFS_DIR_IN) == 0u)\r
- {\r
- USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING;\r
- /* Write the Mode register */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr),\r
- USBFS_EP[ep].epMode);\r
- }\r
+ /* Notify user that data has been copied from endpoint buffer. */\r
+ USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING;\r
+\r
+ /* DMA done coping data: OUT endpoint has to be re-armed by user. */\r
}\r
- #endif /* USBFS_EP_MM */\r
+ }\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
+\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Handle DMA completion event for OUT endpoints. */\r
+ if (0u != (epStatus & USBFS_ARB_EPX_INT_DMA_TERMIN))\r
+ {\r
+ uint32 channelNum = USBFS_DmaChan[ep];\r
+\r
+ /* Restore burst counter for endpoint. */\r
+ USBFS_DmaEpBurstCnt[ep] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCntBackup[ep]);\r
+\r
+ /* Disable DMA channel to restore descriptor configuration. The on-going transfer is aborted. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Generate DMA tr_out signal to notify USB IP that DMA is done. This signal is not generated\r
+ * when transfer was aborted (it occurs when host writes less bytes than buffer size).\r
+ */\r
+ USBFS_CyDmaTriggerOut(USBFS_DmaBurstEndOut[ep]);\r
+\r
+ /* Restore destination address for output endpoint. */\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[ep]));\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[ep] +\r
+ USBFS_DMA_BYTES_PER_BURST));\r
+\r
+ /* Restore number of data elements to transfer which was adjusted for last burst. */\r
+ if (0u != (USBFS_DmaEpLastBurstEl[ep] & USBFS_DMA_DESCR_REVERT))\r
+ {\r
+ USBFS_CyDmaSetNumDataElements(channelNum, (USBFS_DmaEpLastBurstEl[ep] >> USBFS_DMA_DESCR_SHIFT),\r
+ USBFS_DMA_GET_MAX_ELEM_PER_BURST(USBFS_DmaEpLastBurstEl[ep]));\r
+ }\r
+\r
+ /* Validate descriptor 0 and 1 (also reset current state). Command to start with descriptor 0. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
+ if (USBFS_DmaEpBurstCntBackup[ep] > 1u)\r
+ {\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1);\r
+ }\r
+ USBFS_CyDmaSetDescriptor0Next(channelNum);\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+ \r
+ \r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[ep].epCr0;\r
+ \r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(ep) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[ep].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+ \r
+ /* Notify user that data has been copied from endpoint buffer. */\r
+ USBFS_EP[ep].apiEpState = USBFS_EVENT_PENDING;\r
+ \r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ if (USBFS_midi_out_ep == ep)\r
+ {\r
+ USBFS_MIDI_OUT_Service();\r
+ }\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ }\r
+ #endif /* (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+\r
\r
/* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_ARB_ISR_CALLBACK\r
- USBFS_ARB_ISR_Callback();\r
- #endif /* USBFS_ARB_ISR_CALLBACK */\r
+ #ifdef USBFS_ARB_ISR_CALLBACK\r
+ USBFS_ARB_ISR_Callback(ep, epStatus);\r
+ #endif /* (USBFS_ARB_ISR_CALLBACK) */\r
\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr), ep_status); /* Clear Serviced events */\r
+ /* Clear serviced endpoint interrupt sources. */\r
+ USBFS_ARB_EP_BASE.arbEp[ep].epSr = epStatus;\r
}\r
- ptr += USBFS_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */\r
- ep++;\r
- int_status >>= 1u;\r
+\r
+ ++ep;\r
+ arbIntrStatus >>= 1u;\r
}\r
\r
/* `#START ARB_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_ARB_ISR_EXIT_CALLBACK\r
- USBFS_ARB_ISR_ExitCallback();\r
- #endif /* USBFS_ARB_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_ARB_ISR_EXIT_CALLBACK\r
+ USBFS_ARB_ISR_ExitCallback();\r
+ #endif /* (USBFS_ARB_ISR_EXIT_CALLBACK) */\r
}\r
\r
-#endif /* USBFS_EP_MM */\r
+#endif /* (USBFS_ARB_ISR_ACTIVE && USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+#if (CY_PSOC4)\r
\r
-#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
/******************************************************************************\r
- * Function Name: USBFS_EP_DMA_DONE_ISR\r
- *******************************************************************************\r
- *\r
- * Summary:\r
- * Endpoint 1 DMA Done Interrupt Service Routine\r
+ * Function Name: USBFS_EPxDmaDone\r
+ ***************************************************************************//**\r
*\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
+ * \internal\r
+ * Endpoint DMA Done Interrupt Service Routine basic function .\r
+ * \r
+ * \param dmaCh\r
+ * number of DMA channel\r
+ * \r
+ * \param ep\r
+ * number of USB end point\r
+ * \r
+ * \param dmaDone\r
+ * transfer completion flag\r
+ * \r
+ * \return\r
+ * updated transfer completion flag\r
*\r
******************************************************************************/\r
- CY_ISR(USBFS_EP_DMA_DONE_ISR)\r
+ CY_INLINE static void USBFS_EPxDmaDone(uint8 dmaCh, uint8 ep)\r
{\r
- uint8 int8Status;\r
- uint8 int17Status;\r
- uint8 ep_status;\r
- uint8 ep = USBFS_EP1;\r
- uint8 ptr = 0u;\r
+ uint32 nextAddr;\r
+\r
+ /* Manage data elements which remain to transfer. */\r
+ if (0u != USBFS_DmaEpBurstCnt[ep])\r
+ {\r
+ if(USBFS_DmaEpBurstCnt[ep] <= 2u)\r
+ {\r
+ /* Adjust length of last burst. */\r
+ USBFS_CyDmaSetNumDataElements(dmaCh,\r
+ ((uint32) USBFS_DmaEpLastBurstEl[ep] >> USBFS_DMA_DESCR_SHIFT),\r
+ ((uint32) USBFS_DmaEpLastBurstEl[ep] & USBFS_DMA_BURST_BYTES_MASK));\r
+ }\r
+ \r
+\r
+ /* Advance source for input endpoint or destination for output endpoint. */\r
+ if (0u != (USBFS_EP[ep].addr & USBFS_DIR_IN))\r
+ {\r
+ /* Change source for descriptor 0. */\r
+ nextAddr = (uint32) USBFS_CyDmaGetSrcAddress(dmaCh, USBFS_DMA_DESCR0);\r
+ nextAddr += (2u * USBFS_DMA_BYTES_PER_BURST);\r
+ USBFS_CyDmaSetSrcAddress(dmaCh, USBFS_DMA_DESCR0, (void *) nextAddr);\r
+\r
+ /* Change source for descriptor 1. */\r
+ nextAddr += USBFS_DMA_BYTES_PER_BURST;\r
+ USBFS_CyDmaSetSrcAddress(dmaCh, USBFS_DMA_DESCR1, (void *) nextAddr);\r
+ }\r
+ else\r
+ {\r
+ /* Change destination for descriptor 0. */\r
+ nextAddr = (uint32) USBFS_CyDmaGetDstAddress(dmaCh, USBFS_DMA_DESCR0);\r
+ nextAddr += (2u * USBFS_DMA_BYTES_PER_BURST);\r
+ USBFS_CyDmaSetDstAddress(dmaCh, USBFS_DMA_DESCR0, (void *) nextAddr);\r
+\r
+ /* Change destination for descriptor 1. */\r
+ nextAddr += USBFS_DMA_BYTES_PER_BURST;\r
+ USBFS_CyDmaSetDstAddress(dmaCh, USBFS_DMA_DESCR1, (void *) nextAddr);\r
+ }\r
+\r
+ /* Enable DMA to execute transfer as it was disabled because there were no valid descriptor. */\r
+ USBFS_CyDmaValidateDescriptor(dmaCh, USBFS_DMA_DESCR0);\r
+ \r
+ --USBFS_DmaEpBurstCnt[ep];\r
+ if (0u != USBFS_DmaEpBurstCnt[ep])\r
+ {\r
+ USBFS_CyDmaValidateDescriptor(dmaCh, USBFS_DMA_DESCR1);\r
+ --USBFS_DmaEpBurstCnt[ep];\r
+ }\r
+ \r
+ USBFS_CyDmaChEnable (dmaCh);\r
+ USBFS_CyDmaTriggerIn(USBFS_DmaReqOut[ep]);\r
+ }\r
+ else\r
+ {\r
+ /* No data to transfer. False DMA trig. Ignore. */\r
+ }\r
+\r
+ }\r
+\r
+ #if (USBFS_DMA1_ACTIVE)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP1_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * Endpoint 1 DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ void USBFS_EP1_DMA_DONE_ISR(void)\r
+ {\r
+\r
+ USBFS_EPxDmaDone((uint8)USBFS_EP1_DMA_CH,\r
+ USBFS_EP1);\r
+ \r
+ }\r
+ #endif /* (USBFS_DMA1_ACTIVE) */\r
+\r
+\r
+ #if (USBFS_DMA2_ACTIVE)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP2_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * Endpoint 2 DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ void USBFS_EP2_DMA_DONE_ISR(void)\r
+ {\r
+\r
+ USBFS_EPxDmaDone((uint8)USBFS_EP2_DMA_CH,\r
+ USBFS_EP2);\r
+ }\r
+ #endif /* (USBFS_DMA2_ACTIVE) */\r
+\r
+\r
+ #if (USBFS_DMA3_ACTIVE)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP3_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * Endpoint 3 DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ void USBFS_EP3_DMA_DONE_ISR(void)\r
+ {\r
+\r
+ USBFS_EPxDmaDone((uint8)USBFS_EP3_DMA_CH,\r
+ USBFS_EP3);\r
+ }\r
+ #endif /* (USBFS_DMA3_ACTIVE) */\r
+\r
+\r
+ #if (USBFS_DMA4_ACTIVE)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP4_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * Endpoint 4 DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ void USBFS_EP4_DMA_DONE_ISR(void)\r
+ {\r
+\r
+ USBFS_EPxDmaDone((uint8)USBFS_EP4_DMA_CH,\r
+ USBFS_EP4);\r
+ }\r
+ #endif /* (USBFS_DMA4_ACTIVE) */\r
+\r
+\r
+ #if (USBFS_DMA5_ACTIVE)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP5_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * Endpoint 5 DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ void USBFS_EP5_DMA_DONE_ISR(void)\r
+ {\r
+\r
+ USBFS_EPxDmaDone((uint8)USBFS_EP5_DMA_CH,\r
+ USBFS_EP5);\r
+ }\r
+ #endif /* (USBFS_DMA5_ACTIVE) */\r
+\r
+\r
+ #if (USBFS_DMA6_ACTIVE)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP6_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * Endpoint 6 DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ void USBFS_EP6_DMA_DONE_ISR(void)\r
+ {\r
+\r
+ USBFS_EPxDmaDone((uint8)USBFS_EP6_DMA_CH,\r
+ USBFS_EP6);\r
+ }\r
+ #endif /* (USBFS_DMA6_ACTIVE) */\r
+\r
+\r
+ #if (USBFS_DMA7_ACTIVE)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP7_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * Endpoint 7 DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ void USBFS_EP7_DMA_DONE_ISR(void)\r
+ {\r
+\r
+ USBFS_EPxDmaDone((uint8)USBFS_EP7_DMA_CH,\r
+ USBFS_EP7);\r
+ }\r
+ #endif /* (USBFS_DMA7_ACTIVE) */\r
+\r
+\r
+ #if (USBFS_DMA8_ACTIVE)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP8_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * Endpoint 8 DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ void USBFS_EP8_DMA_DONE_ISR(void)\r
+ {\r
+\r
+ USBFS_EPxDmaDone((uint8)USBFS_EP8_DMA_CH,\r
+ USBFS_EP8);\r
+ }\r
+ #endif /* (USBFS_DMA8_ACTIVE) */\r
+\r
+\r
+#else\r
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ CY_ISR(USBFS_EP_DMA_DONE_ISR)\r
+ {\r
+ uint8 int8Status;\r
+ uint8 int17Status;\r
+ uint8 ep_status;\r
+ uint8 ep = USBFS_EP1;\r
\r
#ifdef USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK\r
USBFS_EP_DMA_DONE_ISR_EntryCallback();\r
- #endif /* USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK */\r
+ #endif /* (USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK) */\r
\r
- /* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */\r
+ /* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */\r
\r
- /* `#END` */\r
+ /* `#END` */\r
\r
- /* Read clear on read status register with the EP source of interrupt */\r
- int17Status = USBFS_EP17_DMA_Done_SR_Read() & USBFS_EP17_SR_MASK;\r
- int8Status = USBFS_EP8_DMA_Done_SR_Read() & USBFS_EP8_SR_MASK;\r
+ /* Read clear on read status register with EP source of interrupt. */\r
+ int17Status = USBFS_EP17_DMA_Done_SR_Read() & USBFS_EP17_SR_MASK;\r
+ int8Status = USBFS_EP8_DMA_Done_SR_Read() & USBFS_EP8_SR_MASK;\r
\r
- while(int8Status != 0u)\r
- {\r
- while(int17Status != 0u)\r
+ while (int8Status != 0u)\r
{\r
- if((int17Status & 1u) != 0u) /* If EpX interrupt present */\r
+ while (int17Status != 0u)\r
{\r
- /* Read Endpoint Status Register */\r
- ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr));\r
- if( ((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) == 0u) &&\r
- (USBFS_inBufFull[ep] == 0u))\r
+ if ((int17Status & 1u) != 0u) /* If EpX interrupt present. */\r
{\r
- /* `#START EP_DMA_DONE_USER_CODE` Place your code here */\r
+ /* Read Endpoint Status Register. */\r
+ ep_status = USBFS_ARB_EP_BASE.arbEp[ep].epSr;\r
\r
- /* `#END` */\r
+ if ((0u == (ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL)) &&\r
+ (0u ==USBFS_inBufFull[ep]))\r
+ {\r
+ /* `#START EP_DMA_DONE_USER_CODE` Place your code here */\r
+\r
+ /* `#END` */\r
\r
#ifdef USBFS_EP_DMA_DONE_ISR_CALLBACK\r
USBFS_EP_DMA_DONE_ISR_Callback();\r
- #endif /* USBFS_EP_DMA_DONE_ISR_CALLBACK */\r
-\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ptr), 0x00u);\r
- /* repeat 2 last bytes to prefetch endpoint area */\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ptr),\r
- USBFS_DMA_BYTES_PER_BURST * ep - USBFS_DMA_BYTES_REPEAT);\r
- USBFS_LoadNextInEP(ep, 1);\r
- /* Set Data ready status, This will generate DMA request */\r
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+ #endif /* (USBFS_EP_DMA_DONE_ISR_CALLBACK) */\r
+\r
+ /* Transfer again 2 last bytes into pre-fetch endpoint area. */\r
+ USBFS_ARB_EP_BASE.arbEp[ep].rwWaMsb = 0u;\r
+ USBFS_ARB_EP_BASE.arbEp[ep].rwWa = (USBFS_DMA_BYTES_PER_BURST * ep) - USBFS_DMA_BYTES_REPEAT;\r
+ USBFS_LoadNextInEP(ep, 1u);\r
+\r
+ /* Set Data ready status to generate DMA request. */\r
+ USBFS_ARB_EP_BASE.arbEp[ep].epCfg |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+ }\r
}\r
+\r
+ ep++;\r
+ int17Status >>= 1u;\r
+ }\r
+\r
+ int8Status >>= 1u;\r
+\r
+ if (int8Status != 0u)\r
+ {\r
+ /* Prepare pointer for EP8. */\r
+ ep = USBFS_EP8;\r
+ int17Status = int8Status & 0x01u;\r
}\r
- ptr += USBFS_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */\r
- ep++;\r
- int17Status >>= 1u;\r
}\r
- int8Status >>= 1u;\r
- if(int8Status != 0u)\r
+\r
+ /* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */\r
+\r
+ /* `#END` */\r
+\r
+ #ifdef USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK\r
+ USBFS_EP_DMA_DONE_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK) */\r
+ }\r
+ #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+#endif /* (CY_PSOC4) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+\r
+\r
+#if (CY_PSOC4)\r
+ /***************************************************************************\r
+ * Function Name: USBFS_IntrHandler\r
+ ************************************************************************//**\r
+ *\r
+ * Interrupt handler for Hi/Mid/Low ISRs.\r
+ *\r
+ * regCause - The cause register of interrupt. One of the three variants:\r
+ * USBFS_INTR_CAUSE_LO_REG - Low interrupts.\r
+ * USBFS_INTR_CAUSE_MED_REG - Med interrupts.\r
+ * USBFS_INTR_CAUSE_HI_REG - - High interrupts.\r
+ *\r
+ *\r
+ ***************************************************************************/\r
+ CY_INLINE static void USBFS_IntrHandler(uint32 intrCause)\r
+ {\r
+ /* Array of pointers to component interrupt handlers. */\r
+ static const cyisraddress USBFS_isrCallbacks[] =\r
+ {\r
+\r
+ };\r
+\r
+ uint32 cbIdx = 0u;\r
+\r
+ /* Check arbiter interrupt source first. */\r
+ if (0u != (intrCause & USBFS_INTR_CAUSE_ARB_INTR))\r
+ {\r
+ USBFS_isrCallbacks[USBFS_ARB_EP_INTR_NUM]();\r
+ }\r
+\r
+ /* Check all other interrupt sources (except arbiter and resume). */\r
+ intrCause = (intrCause & USBFS_INTR_CAUSE_CTRL_INTR_MASK) |\r
+ ((intrCause & USBFS_INTR_CAUSE_EP1_8_INTR_MASK) >>\r
+ USBFS_INTR_CAUSE_EP_INTR_SHIFT);\r
+\r
+ /* Call interrupt handlers for active interrupt sources. */\r
+ while (0u != intrCause)\r
+ {\r
+ if (0u != (intrCause & 0x1u))\r
{\r
- /* Prepare pointer for EP8 */\r
- ptr = ((USBFS_EP8 - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
- ep = USBFS_EP8;\r
- int17Status = int8Status & 0x01u;\r
+ USBFS_isrCallbacks[cbIdx]();\r
}\r
+\r
+ intrCause >>= 1u;\r
+ ++cbIdx;\r
}\r
+ }\r
\r
- /* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */\r
\r
- /* `#END` */\r
+ /***************************************************************************\r
+ * Function Name: USBFS_INTR_HI_ISR\r
+ ************************************************************************//**\r
+ *\r
+ * Interrupt Service Routine for the high group of the interrupt sources.\r
+ *\r
+ *\r
+ ***************************************************************************/\r
+ CY_ISR(USBFS_INTR_HI_ISR)\r
+ {\r
+ USBFS_IntrHandler(USBFS_INTR_CAUSE_HI_REG);\r
+ }\r
+\r
+ /***************************************************************************\r
+ * Function Name: USBFS_INTR_MED_ISR\r
+ ************************************************************************//**\r
+ *\r
+ * Interrupt Service Routine for the medium group of the interrupt sources.\r
+ *\r
+ *\r
+ ***************************************************************************/\r
+ CY_ISR(USBFS_INTR_MED_ISR)\r
+ {\r
+ USBFS_IntrHandler(USBFS_INTR_CAUSE_MED_REG);\r
+ }\r
\r
- #ifdef USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK\r
- USBFS_EP_DMA_DONE_ISR_ExitCallback();\r
- #endif /* USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK */\r
+ /***************************************************************************\r
+ * Function Name: USBFS_INTR_LO_ISR\r
+ ************************************************************************//**\r
+ *\r
+ * Interrupt Service Routine for the low group of the interrupt sources.\r
+ *\r
+ *\r
+ ***************************************************************************/\r
+ CY_ISR(USBFS_INTR_LO_ISR)\r
+ {\r
+ USBFS_IntrHandler(USBFS_INTR_CAUSE_LO_REG);\r
}\r
-#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+#endif /* (CY_PSOC4) */\r
\r
\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: USBFS_hid.c\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_hid.c\r
+* \version 3.10\r
*\r
-* Description:\r
-* USB HID Class request handler.\r
+* \brief\r
+* This file contains the USB HID Class request handler. \r
*\r
* Related Document:\r
* Device Class Definition for Human Interface Devices (HID) Version 1.11\r
*\r
-* Note:\r
-*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
-\r
-#if defined(USBFS_ENABLE_HID_CLASS)\r
-\r
-#include "USBFS_pvt.h"\r
#include "USBFS_hid.h"\r
+#include "USBFS_pvt.h"\r
+\r
\r
\r
+#if defined(USBFS_ENABLE_HID_CLASS)\r
\r
/***************************************\r
* HID Variables\r
***************************************/\r
-\r
-volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER]; /* HID device protocol status */\r
-volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER]; /* HID device idle reload value */\r
+/** This variable is initialized in the USBFS_InitComponent() API to the \r
+ * PROTOCOL_REPORT value. It is controlled by the host using the \r
+ * HID_SET_PROTOCOL request. The value is returned to the user code by the \r
+ * USBFS_GetProtocol() API.*/\r
+volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER];\r
+\r
+/** This variable controls the HID report rate. It is controlled by the host \r
+ * using the HID_SET_IDLE request and used by the USBFS_UpdateHIDTimer() API to \r
+ * reload timer.*/\r
+volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER];\r
+\r
+/** This variable contains the timer counter, which is decremented and reloaded \r
+ * by the USBFS_UpdateHIDTimer() API.*/\r
volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER]; /* HID device idle rate value */\r
\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_UpdateHIDTimer\r
-********************************************************************************\r
+****************************************************************************//**\r
+*\r
+* This function updates the HID Report idle timer and returns the status and \r
+* reloads the timer if it expires.\r
*\r
-* Summary:\r
-* Updates the HID report timer and reloads it if expired\r
+* \param interface Contains the interface number.\r
*\r
-* Parameters:\r
-* interface: Interface Number.\r
+* \return\r
+* Returns the state of the HID timer. Symbolic names and their associated values are given here:\r
+* Return Value |Notes\r
+* ---------------------------|------------------------------------------------\r
+* USBFS_IDLE_TIMER_EXPIRED | The timer expired.\r
+* USBFS_IDLE_TIMER_RUNNING | The timer is running.\r
+* USBFS_IDLE_TIMER_IDEFINITE | The report is sent when data or state changes.\r
*\r
-* Return:\r
-* status.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
}\r
}\r
\r
- return(stat);\r
+ return((uint8)stat);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_GetProtocol\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Returns the selected protocol value to the application\r
+* This function returns the HID protocol value for the selected interface.\r
*\r
-* Parameters:\r
-* interface: Interface Number.\r
+* \param interface: Contains the interface number.\r
*\r
-* Return:\r
-* Interface protocol.\r
+* \return\r
+* Returns the protocol value. \r
*\r
*******************************************************************************/\r
uint8 USBFS_GetProtocol(uint8 interface) \r
\r
/*******************************************************************************\r
* Function Name: USBFS_DispatchHIDClassRqst\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine dispatches class requests\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* requestHandled\r
+* \return\r
+* Results of HID Class request handling: \r
+* - USBFS_TRUE - request was handled without errors\r
+* - USBFS_FALSE - error occurs during handling of request \r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_DispatchHIDClassRqst(void) \r
{\r
uint8 requestHandled = USBFS_FALSE;\r
- uint8 interfaceNumber;\r
\r
- interfaceNumber = CY_GET_REG8(USBFS_wIndexLo);\r
- if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)\r
- { /* Control Read */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ uint8 interfaceNumber = (uint8) USBFS_wIndexLoReg;\r
+ \r
+ /* Check request direction: D2H or H2D. */\r
+ if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H))\r
+ {\r
+ /* Handle direction from device to host. */\r
+ \r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_GET_DESCRIPTOR:\r
- if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_CLASS)\r
+ if (USBFS_wValueHiReg == USBFS_DESCR_HID_CLASS)\r
{\r
USBFS_FindHidClassDecriptor();\r
if (USBFS_currentTD.count != 0u)\r
requestHandled = USBFS_InitControlRead();\r
}\r
}\r
- else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_REPORT)\r
+ else if (USBFS_wValueHiReg == USBFS_DESCR_HID_REPORT)\r
{\r
USBFS_FindReportDescriptor();\r
if (USBFS_currentTD.count != 0u)\r
}\r
}\r
else\r
- { /* requestHandled is initialezed as FALSE by default */\r
+ { \r
+ /* Do not handle this request. */\r
}\r
break;\r
+ \r
case USBFS_HID_GET_REPORT:\r
USBFS_FindReport();\r
if (USBFS_currentTD.count != 0u)\r
\r
case USBFS_HID_GET_IDLE:\r
/* This function does not support multiple reports per interface*/\r
- /* Validate interfaceNumber and Report ID (should be 0) */\r
- if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) &&\r
- (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */\r
+ /* Validate interfaceNumber and Report ID (should be 0): Do not support Idle per Report ID */\r
+ if ((interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && (USBFS_wValueLoReg == 0u)) \r
{\r
USBFS_currentTD.count = 1u;\r
USBFS_currentTD.pData = &USBFS_hidIdleRate[interfaceNumber];\r
requestHandled = USBFS_InitControlRead();\r
}\r
break;\r
+ \r
case USBFS_HID_GET_PROTOCOL:\r
/* Validate interfaceNumber */\r
if( interfaceNumber < USBFS_MAX_INTERFACES_NUMBER)\r
requestHandled = USBFS_InitControlRead();\r
}\r
break;\r
+ \r
default: /* requestHandled is initialized as FALSE by default */\r
break;\r
}\r
}\r
- else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) ==\r
- USBFS_RQST_DIR_H2D)\r
- { /* Control Write */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ else\r
+ { \r
+ /* Handle direction from host to device. */\r
+ \r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_HID_SET_REPORT:\r
USBFS_FindReport();\r
requestHandled = USBFS_InitControlWrite();\r
}\r
break;\r
+ \r
case USBFS_HID_SET_IDLE:\r
/* This function does not support multiple reports per interface */\r
- /* Validate interfaceNumber and Report ID (should be 0) */\r
- if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) &&\r
- (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */\r
+ /* Validate interfaceNumber and Report ID (should be 0): Do not support Idle per Report ID */\r
+ if ((interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && (USBFS_wValueLoReg == 0u))\r
{\r
- USBFS_hidIdleRate[interfaceNumber] = CY_GET_REG8(USBFS_wValueHi);\r
+ USBFS_hidIdleRate[interfaceNumber] = (uint8)USBFS_wValueHiReg;\r
/* With regards to HID spec: "7.2.4 Set_Idle Request"\r
* Latency. If the current period has gone past the\r
* newly proscribed time duration, then a report\r
\r
case USBFS_HID_SET_PROTOCOL:\r
/* Validate interfaceNumber and protocol (must be 0 or 1) */\r
- if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) &&\r
- (CY_GET_REG8(USBFS_wValueLo) <= 1u) )\r
+ if ((interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && (USBFS_wValueLoReg <= 1u))\r
{\r
- USBFS_hidProtocol[interfaceNumber] = CY_GET_REG8(USBFS_wValueLo);\r
+ USBFS_hidProtocol[interfaceNumber] = (uint8)USBFS_wValueLoReg;\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
}\r
break;\r
- default: /* requestHandled is initialized as FALSE by default */\r
+ \r
+ default: \r
+ /* Unknown class request is not handled. */\r
break;\r
}\r
}\r
- else\r
- { /* requestHandled is initialized as FALSE by default */\r
- }\r
\r
- return(requestHandled);\r
+ return (requestHandled);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USB_FindHidClassDescriptor\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine find Hid Class Descriptor pointer based on the Interface number\r
* and Alternate setting then loads the currentTD structure with the address of\r
* the buffer and the size.\r
* The HID Class Descriptor resides inside the config descriptor.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* currentTD\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 interfaceN;\r
\r
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);\r
- interfaceN = CY_GET_REG8(USBFS_wIndexLo);\r
+ \r
+ interfaceN = (uint8) USBFS_wIndexLoReg;\r
/* Third entry in the LUT starts the Interface Table pointers */\r
/* Now use the request interface number*/\r
pTmp = &pTmp[interfaceN + 2u];\r
+ \r
/* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */\r
pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list;\r
+ \r
/* Now use Alternate setting number */\r
pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]];\r
+ \r
/* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */\r
pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list;\r
+ \r
/* Fifth entry in the LUT points to Hid Class Descriptor in Configuration Descriptor */\r
pTmp = &pTmp[4u];\r
pDescr = (volatile uint8 *)pTmp->p_list;\r
+ \r
/* The first byte contains the descriptor length */\r
USBFS_currentTD.count = *pDescr;\r
USBFS_currentTD.pData = pDescr;\r
\r
/*******************************************************************************\r
* Function Name: USB_FindReportDescriptor\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine find Hid Report Descriptor pointer based on the Interface\r
* number, then loads the currentTD structure with the address of the buffer\r
* and the size.\r
* Hid Report Descriptor is located after IN/OUT/FEATURE reports.\r
*\r
-* Parameters:\r
-* void\r
-*\r
-* Return:\r
+* \return\r
* currentTD\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 interfaceN;\r
\r
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);\r
- interfaceN = CY_GET_REG8(USBFS_wIndexLo);\r
+ interfaceN = (uint8) USBFS_wIndexLoReg;\r
+ \r
/* Third entry in the LUT starts the Interface Table pointers */\r
/* Now use the request interface number */\r
pTmp = &pTmp[interfaceN + 2u];\r
+ \r
/* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */\r
pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list;\r
+ \r
/* Now use Alternate setting number */\r
pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]];\r
+ \r
/* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */\r
pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list;\r
+ \r
/* Fourth entry in the LUT starts the Hid Report Descriptor */\r
pTmp = &pTmp[3u];\r
pDescr = (volatile uint8 *)pTmp->p_list;\r
+ \r
/* The 1st and 2nd bytes of descriptor contain its length. LSB is 1st. */\r
- USBFS_currentTD.count = (((uint16)pDescr[1u] << 8u) | pDescr[0u]);\r
+ USBFS_currentTD.count = ((uint16)((uint16) pDescr[1u] << 8u) | pDescr[0u]);\r
USBFS_currentTD.pData = &pDescr[2u];\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_FindReport\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine sets up a transfer based on the Interface number, Report Type\r
* and Report ID, then loads the currentTD structure with the address of the\r
* buffer and the size. The caller has to decide if it is a control read or\r
* control write.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* currentTD\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
{\r
const T_USBFS_LUT CYCODE *pTmp;\r
T_USBFS_TD *pTD;\r
- uint8 interfaceN;\r
uint8 reportType;\r
-\r
+ uint8 interfaceN;\r
+ \r
/* `#START HID_FINDREPORT` Place custom handling here */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_FIND_REPORT_CALLBACK\r
- USBFS_FindReport_Callback();\r
- #endif /* USBFS_FIND_REPORT_CALLBACK */\r
+#ifdef USBFS_FIND_REPORT_CALLBACK\r
+ USBFS_FindReport_Callback();\r
+#endif /* (USBFS_FIND_REPORT_CALLBACK) */\r
\r
USBFS_currentTD.count = 0u; /* Init not supported condition */\r
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);\r
- reportType = CY_GET_REG8(USBFS_wValueHi);\r
- interfaceN = CY_GET_REG8(USBFS_wIndexLo);\r
- /* Third entry in the LUT COnfiguration Table starts the Interface Table pointers */\r
+ reportType = (uint8) USBFS_wValueHiReg;\r
+ interfaceN = (uint8) USBFS_wIndexLoReg;\r
+ \r
+ /* Third entry in the LUT Configuration Table starts the Interface Table pointers */\r
/* Now use the request interface number */\r
pTmp = &pTmp[interfaceN + 2u];\r
- /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE*/\r
+ \r
+ /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */\r
pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list;\r
- if(interfaceN < USBFS_MAX_INTERFACES_NUMBER)\r
+ if (interfaceN < USBFS_MAX_INTERFACES_NUMBER)\r
{\r
/* Now use Alternate setting number */\r
pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]];\r
+ \r
/* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */\r
pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list;\r
+ \r
/* Validate reportType to comply with "7.2.1 Get_Report Request" */\r
- if((reportType >= USBFS_HID_GET_REPORT_INPUT) &&\r
- (reportType <= USBFS_HID_GET_REPORT_FEATURE))\r
+ if ((reportType >= USBFS_HID_GET_REPORT_INPUT) &&\r
+ (reportType <= USBFS_HID_GET_REPORT_FEATURE))\r
{\r
/* Get the entry proper TD (IN, OUT or Feature Report Table)*/\r
pTmp = &pTmp[reportType - 1u];\r
- reportType = CY_GET_REG8(USBFS_wValueLo); /* Get reportID */\r
+ \r
+ /* Get reportID */\r
+ reportType = (uint8) USBFS_wValueLoReg;\r
+ \r
/* Validate table support by the HID descriptor, compare table count with reportID */\r
- if(pTmp->c >= reportType)\r
+ if (pTmp->c >= reportType)\r
{\r
pTD = (T_USBFS_TD *) pTmp->p_list;\r
pTD = &pTD[reportType]; /* select entry depend on report ID*/\r
-/*******************************************************************************\r
-* File Name: USBFS_hid.h\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_hid.h\r
+* \version 3.10\r
*\r
-* Description:\r
-* Header File for the USBFS component. Contains prototypes and constant values.\r
+* \brief\r
+* This file provides function prototypes and constants for the USBFS component \r
+* HID class.\r
*\r
* Related Document:\r
* Device Class Definition for Human Interface Devices (HID) Version 1.11\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#if !defined(CY_USBFS_USBFS_hid_H)\r
#define CY_USBFS_USBFS_hid_H\r
\r
-#include "cytypes.h"\r
-\r
+#include "USBFS.h"\r
\r
/***************************************\r
* Prototypes of the USBFS_hid API.\r
***************************************/\r
-\r
+/**\r
+* \addtogroup group_hid\r
+* @{\r
+*/\r
uint8 USBFS_UpdateHIDTimer(uint8 interface) ;\r
-uint8 USBFS_GetProtocol(uint8 interface) ;\r
-\r
+uint8 USBFS_GetProtocol(uint8 interface) ;\r
+/** @} hid */\r
\r
/***************************************\r
*Renamed Functions for backward compatible\r
***************************************/\r
\r
-#define USBFS_bGetProtocol USBFS_GetProtocol\r
+#define USBFS_bGetProtocol USBFS_GetProtocol\r
\r
\r
/***************************************\r
-/*******************************************************************************\r
-* File Name: USBFS_midi.c\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_midi.c\r
+* \version 3.10\r
*\r
-* Description:\r
+* \brief\r
* MIDI Streaming request handler.\r
* This file contains routines for sending and receiving MIDI\r
* messages, and handles running status in both directions.\r
* MIDI 1.0 Detailed Specification Document Version 4.2\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
-\r
-#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
-\r
#include "USBFS_midi.h"\r
#include "USBFS_pvt.h"\r
\r
\r
+#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
\r
/***************************************\r
* MIDI Constants\r
* Global variables\r
***************************************/\r
\r
+\r
#if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
#if (USBFS_MIDI_IN_BUFF_SIZE >= 256)\r
+ /** Input endpoint buffer pointer. This pointer is used as an index for the\r
+ * USBMIDI_midiInBuffer to write data. It is cleared to zero by the\r
+ * USBMIDI_MIDI_EP_Init() function.*/\r
volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */\r
#else\r
volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */\r
#endif /* (USBFS_MIDI_IN_BUFF_SIZE >= 256) */\r
- volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */\r
+ /** Contains the midi IN endpoint number, It is initialized after a\r
+ * SET_CONFIGURATION request based on a user descriptor. It is used in MIDI\r
+ * APIs to send data to the host.*/\r
+ volatile uint8 USBFS_midi_in_ep;\r
+ /** Input endpoint buffer with a length equal to MIDI IN EP Max Packet Size.\r
+ * This buffer is used to save and combine the data received from the UARTs,\r
+ * generated internally by USBMIDI_PutUsbMidiIn() function messages, or both.\r
+ * The USBMIDI_MIDI_IN_Service() function transfers the data from this buffer to the host.*/\r
uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */\r
#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
\r
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
+ /** Contains the midi OUT endpoint number. It is initialized after a\r
+ * SET_CONFIGURATION request based on a user descriptor. It is used in\r
+ * MIDI APIs to receive data from the host.*/\r
volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */\r
+ /** Output endpoint buffer with a length equal to MIDI OUT EP Max Packet Size.\r
+ * This buffer is used by the USBMIDI_MIDI_OUT_EP_Service() function to save\r
+ * the data received from the host. The received data is then parsed. The\r
+ * parsed data is transferred to the UARTs buffer and also used for internal\r
+ * processing by the USBMIDI_callbackLocalMidiEvent() function.*/\r
uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */\r
#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
+\r
static USBFS_MIDI_RX_STATUS USBFS_MIDI1_Event; /* MIDI RX status structure */\r
static volatile uint8 USBFS_MIDI1_TxRunStat; /* MIDI Output running status */\r
+ /** The USBFS supports a maximum of two external Jacks. The two flag variables\r
+ * are used to represent the status of two external Jacks. These optional variables\r
+ * are allocated when External Mode is enabled. The following flags help to\r
+ * detect and generate responses for SysEx messages. The USBMIDI_MIDI2_InqFlags\r
+ * is optional and is not available when only one external Jack is configured.\r
+ * Flag | Description\r
+ * ------------------------------|---------------------------------------\r
+ * USBMIDI_INQ_SYSEX_FLAG | Non-real-time SysEx message received.\r
+ * USBMIDI_INQ_IDENTITY_REQ_FLAG | Identity Request received. You should clear this bit when an Identity Reply message is generated.\r
+ * SysEX messages are intended for local device and shouldn't go out on the\r
+ * external MIDI jack, this flag indicates when a MIDI SysEx OUT message is\r
+ * in progress for the application */\r
volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
static USBFS_MIDI_RX_STATUS USBFS_MIDI2_Event; /* MIDI RX status structure */\r
static volatile uint8 USBFS_MIDI2_TxRunStat; /* MIDI Output running status */\r
+ /** See description of \ref USBFS_MIDI1_InqFlags*/\r
volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */\r
#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
/* `#END` */\r
\r
\r
-/***************************************\r
-* Optional MIDI APIs\r
-***************************************/\r
#if (USBFS_ENABLE_MIDI_API != 0u)\r
-\r
-\r
/*******************************************************************************\r
-* Function Name: USBFS_MIDI_EP_Init\r
-********************************************************************************\r
+* Function Name: USBFS_MIDI_Init\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function initializes the MIDI interface and UART(s) to be ready to\r
* receive data from the PC and MIDI ports.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
+* \globalvars\r
*\r
-* Global variables:\r
-* USBFS_midiInBuffer: This buffer is used for saving and combining\r
+* \ref USBFS_midiInBuffer: This buffer is used for saving and combining\r
* the received data from UART(s) and(or) generated internally by\r
* PutUsbMidiIn() function messages. USBFS_MIDI_IN_EP_Service()\r
* function transfers the data from this buffer to the PC.\r
-* USBFS_midiOutBuffer: This buffer is used by the\r
-* USBFS_MIDI_OUT_EP_Service() function for saving the received\r
+*\r
+* \ref USBFS_midiOutBuffer: This buffer is used by the\r
+* USBFS_MIDI_OUT_Service() function for saving the received\r
* from the PC data, then the data are parsed and transferred to UART(s)\r
* buffer and to the internal processing by the\r
-* USBFS_callbackLocalMidiEvent function.\r
-* USBFS_midi_out_ep: Used as an OUT endpoint number.\r
-* USBFS_midi_in_ep: Used as an IN endpoint number.\r
-* USBFS_midiInPointer: Initialized to zero.\r
*\r
-* Reentrant:\r
+* \ref USBFS_callbackLocalMidiEvent function.\r
+*\r
+* \ref USBFS_midi_out_ep: Used as an OUT endpoint number.\r
+*\r
+* \ref USBFS_midi_in_ep: Used as an IN endpoint number.\r
+*\r
+* \ref USBFS_midiInPointer: Initialized to zero.\r
+*\r
+* \sideeffect\r
+* The priority of the UART RX ISR should be higher than UART TX ISR. To do\r
+* that this function changes the priority of the UARTs TX and RX interrupts.\r
+*\r
+* \reentrant\r
* No\r
*\r
*******************************************************************************/\r
-void USBFS_MIDI_EP_Init(void) \r
+void USBFS_MIDI_Init(void) \r
{\r
+#if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
+ USBFS_midiInPointer = 0u;\r
+#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
#if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
- USBFS_midiInPointer = 0u;\r
- #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
-\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- #if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
- /* Init DMA configurations for IN EP*/\r
- USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer,\r
- USBFS_MIDI_IN_BUFF_SIZE);\r
-\r
- #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
- #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
- /* Init DMA configurations for OUT EP*/\r
- (void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer,\r
- USBFS_MIDI_OUT_BUFF_SIZE);\r
- #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
- #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */\r
+ /* Provide buffer for IN endpoint. */\r
+ USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer,\r
+ USBFS_MIDI_IN_BUFF_SIZE);\r
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
\r
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
- USBFS_EnableOutEP(USBFS_midi_out_ep);\r
+ /* Provide buffer for OUT endpoint. */\r
+ (void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer,\r
+ USBFS_MIDI_OUT_BUFF_SIZE);\r
#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+\r
+#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
+ USBFS_EnableOutEP(USBFS_midi_out_ep);\r
+#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
\r
/* Initialize the MIDI port(s) */\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
- USBFS_MIDI_Init();\r
- #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
+#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
+ USBFS_MIDI_InitInterface();\r
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
}\r
\r
-#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
-\r
\r
+#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
/*******************************************************************************\r
- * Function Name: USBFS_MIDI_OUT_EP_Service\r
- ********************************************************************************\r
+ * Function Name: USBFS_MIDI_OUT_Service\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
- * Services the USB MIDI OUT endpoints.\r
- * This function is called from OUT EP ISR. It transfers the received from PC\r
- * data to the external MIDI port(UART TX buffer) and calls the\r
- * USBFS_callbackLocalMidiEvent() function to internal process\r
- * of the MIDI data.\r
- * This function is blocked by UART, if not enough space is available in UART\r
- * TX buffer. Therefore it is recommended to use large UART TX buffer size.\r
+ * This function services the traffic from the USBMIDI OUT endpoint and\r
+ * sends the data to the MIDI output ports (TX UARTs). It is blocked by the\r
+ * UART when not enough space is available in the UART TX buffer.\r
+ * This function is automatically called from OUT EP ISR in DMA with\r
+ * Automatic Memory Management mode. In Manual and DMA with Manual EP\r
+ * Management modes you must call it from the main foreground task.\r
*\r
- * Parameters:\r
- * None\r
+ * \globalvars\r
*\r
- * Return:\r
- * None\r
+ * \ref USBFS_midiOutBuffer: Used as temporary buffer between USB\r
+ * internal memory and UART TX buffer.\r
*\r
- * Global variables:\r
- * USBFS_midiOutBuffer: Used as temporary buffer between USB internal\r
- * memory and UART TX buffer.\r
- * USBFS_midi_out_ep: Used as an OUT endpoint number.\r
+ * \ref USBFS_midi_out_ep: Used as an OUT endpoint number.\r
*\r
- * Reentrant:\r
+ * \reentrant\r
* No\r
*\r
*******************************************************************************/\r
- void USBFS_MIDI_OUT_EP_Service(void) \r
+ void USBFS_MIDI_OUT_Service(void) \r
{\r
- #if USBFS_MIDI_OUT_BUFF_SIZE >= 256\r
- uint16 outLength;\r
- uint16 outPointer;\r
- #else\r
- uint8 outLength;\r
- uint8 outPointer;\r
- #endif /* USBFS_MIDI_OUT_BUFF_SIZE >=256 */\r
-\r
- uint8 dmaState = 0u;\r
+ #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256)\r
+ uint16 outLength;\r
+ uint16 outPointer;\r
+ #else\r
+ uint8 outLength;\r
+ uint8 outPointer;\r
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */\r
\r
- /* Service the USB MIDI output endpoint */\r
- if (USBFS_GetEPState(USBFS_midi_out_ep) == USBFS_OUT_BUFFER_FULL)\r
+ /* Service the USB MIDI output endpoint. */\r
+ if (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(USBFS_midi_out_ep))\r
{\r
- #if(USBFS_MIDI_OUT_BUFF_SIZE >= 256)\r
- outLength = USBFS_GetEPCount(USBFS_midi_out_ep);\r
+ #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256)\r
+ outLength = USBFS_GetEPCount(USBFS_midi_out_ep);\r
+ #else\r
+ outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep);\r
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */\r
+\r
+ #if (!USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256)\r
+ outLength = USBFS_ReadOutEP(USBFS_midi_out_ep,\r
+ USBFS_midiOutBuffer, outLength);\r
#else\r
- outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep);\r
+ outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep,\r
+ USBFS_midiOutBuffer, (uint16) outLength);\r
#endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */\r
\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256)\r
- outLength = USBFS_ReadOutEP(USBFS_midi_out_ep,\r
- USBFS_midiOutBuffer, outLength);\r
- #else\r
- outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep,\r
- USBFS_midiOutBuffer, (uint16)outLength);\r
- #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */\r
-\r
- #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
- do /* wait for DMA transfer complete */\r
- {\r
- (void) CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);\r
- }\r
- while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);\r
- #endif /* (USBFS_EP_MM == USBFS__EP_DMAMANUAL) */\r
-\r
- #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */\r
+ #if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ /* Wait until DMA complete transferring data from OUT endpoint buffer. */\r
+ while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(USBFS_midi_out_ep))\r
+ {\r
+ }\r
\r
- if(dmaState != 0u)\r
- {\r
- /* Suppress compiler warning */\r
- }\r
+ /* Enable OUT endpoint for communication with host. */\r
+ USBFS_EnableOutEP(USBFS_midi_out_ep);\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
+ #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
\r
if (outLength >= USBFS_EVENT_LENGTH)\r
{\r
outPointer = 0u;\r
while (outPointer < outLength)\r
{\r
- /* In some OS OUT packet could be appended by nulls which could be skipped */\r
+ /* In some OS OUT packet could be appended by nulls which could be skipped. */\r
if (USBFS_midiOutBuffer[outPointer] == 0u)\r
{\r
break;\r
}\r
- /* Route USB MIDI to the External connection */\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
- if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) ==\r
- USBFS_MIDI_CABLE_00)\r
- {\r
- USBFS_MIDI1_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]);\r
- }\r
- else if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) ==\r
- USBFS_MIDI_CABLE_01)\r
- {\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]);\r
- #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
- }\r
- else\r
- {\r
- /* `#START CUSTOM_MIDI_OUT_EP_SERV` Place your code here */\r
\r
- /* `#END` */\r
+ /* Route USB MIDI to the External connection */\r
+ #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
+ if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) ==\r
+ USBFS_MIDI_CABLE_00)\r
+ {\r
+ USBFS_MIDI1_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]);\r
+ }\r
+ else if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) ==\r
+ USBFS_MIDI_CABLE_01)\r
+ {\r
+ #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
+ USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]);\r
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
+ }\r
+ else\r
+ {\r
+ /* `#START CUSTOM_MIDI_OUT_EP_SERV` Place your code here */\r
+\r
+ /* `#END` */\r
\r
- #ifdef USBFS_MIDI_OUT_EP_SERVICE_CALLBACK\r
- USBFS_MIDI_OUT_EP_Service_Callback();\r
- #endif /* USBFS_MIDI_OUT_EP_SERVICE_CALLBACK */\r
- }\r
- #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
+ #ifdef USBFS_MIDI_OUT_EP_SERVICE_CALLBACK\r
+ USBFS_MIDI_OUT_EP_Service_Callback();\r
+ #endif /* USBFS_MIDI_OUT_EP_SERVICE_CALLBACK */\r
+ }\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
/* Process any local MIDI output functions */\r
- USBFS_callbackLocalMidiEvent(\r
- USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK,\r
- &USBFS_midiOutBuffer[outPointer + USBFS_EVENT_BYTE1]);\r
+ USBFS_callbackLocalMidiEvent(USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK,\r
+ &USBFS_midiOutBuffer[outPointer + USBFS_EVENT_BYTE1]);\r
outPointer += USBFS_EVENT_LENGTH;\r
}\r
}\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- /* Enable Out EP*/\r
- USBFS_EnableOutEP(USBFS_midi_out_ep);\r
- #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Enable OUT endpoint for communiation. */\r
+ USBFS_EnableOutEP(USBFS_midi_out_ep);\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
}\r
}\r
+#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
\r
-#endif /* #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
\r
#if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
-\r
-\r
/*******************************************************************************\r
* Function Name: USBFS_MIDI_IN_EP_Service\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Services the USB MIDI IN endpoint. Non-blocking.\r
* Checks that previous packet was processed by HOST, otherwise service the\r
* input endpoint on the subsequent call. It is called from the\r
* USBFS_MIDI_IN_Service() and from the\r
* USBFS_PutUsbMidiIn() function.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Global variables:\r
+ * \globalvars\r
* USBFS_midi_in_ep: Used as an IN endpoint number.\r
* USBFS_midiInBuffer: Function loads the data from this buffer to\r
* the USB IN endpoint.\r
* USBFS_midiInPointer: Cleared to zero when data are sent.\r
*\r
- * Reentrant:\r
+ * \reentrant\r
* No\r
*\r
*******************************************************************************/\r
{\r
if(USBFS_GetEPState(USBFS_midi_in_ep) == USBFS_EVENT_PENDING)\r
{\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer,\r
- (uint16)USBFS_midiInPointer);\r
- #else /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
- /* rearm IN EP */\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
USBFS_LoadInEP(USBFS_midi_in_ep, NULL, (uint16)USBFS_midiInPointer);\r
- #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */\r
+ #else\r
+ USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer,\r
+ (uint16) USBFS_midiInPointer);\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
\r
/* Clear the midiInPointer. For DMA mode, clear this pointer in the ARB ISR when data are moved by DMA */\r
- #if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
+ #if (USBFS_EP_MANAGEMENT_MANUAL)\r
USBFS_midiInPointer = 0u;\r
- #endif /* (USBFS_EP_MM == USBFS__EP_MANUAL) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */\r
}\r
}\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_MIDI_IN_Service\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
- * Services the traffic from the MIDI input ports (RX UART) and prepare data\r
- * in USB MIDI IN endpoint buffer.\r
+ * This function services the traffic from the MIDI input ports (RX UART)\r
+ * and prepare data in USB MIDI IN endpoint buffer.\r
* Calls the USBFS_MIDI_IN_EP_Service() function to sent the\r
* data from buffer to PC. Non-blocking. Should be called from main foreground\r
* task.\r
* This function is not protected from the reentrant calls. When it is required\r
* to use this function in UART RX ISR to guaranty low latency, care should be\r
* taken to protect from reentrant calls.\r
+ * In PSoC 3, if this function is called from an ISR, you must declare this\r
+ * function as re-entrant so that different variable storage space is\r
+ * created by the compiler. This is automatically taken care for PSoC 4 and\r
+ * PSoC 5LP devices by the compiler.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
+ * \globalvars\r
*\r
- * Global variables:\r
* USBFS_midiInPointer: Cleared to zero when data are sent.\r
*\r
- * Reentrant:\r
+ * \reentrant\r
* No\r
*\r
*******************************************************************************/\r
/* Service the MIDI UART inputs until either both receivers have no more\r
* events or until the input endpoint buffer fills up.\r
*/\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
+ #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
uint8 m1 = 0u;\r
uint8 m2 = 0u;\r
+\r
+ if (0u == USBFS_midiInPointer)\r
+ {\r
do\r
{\r
- if (USBFS_midiInPointer <=\r
- (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
+ if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
{\r
/* Check MIDI1 input port for a complete event */\r
m1 = USBFS_MIDI1_GetEvent();\r
if (m1 != 0u)\r
{\r
USBFS_PrepareInBuffer(m1, (uint8 *)&USBFS_MIDI1_Event.msgBuff[0],\r
- USBFS_MIDI1_Event.size, USBFS_MIDI_CABLE_00);\r
+ USBFS_MIDI1_Event.size, USBFS_MIDI_CABLE_00);\r
}\r
}\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- if (USBFS_midiInPointer <=\r
- (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
+ if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
{\r
/* Check MIDI2 input port for a complete event */\r
m2 = USBFS_MIDI2_GetEvent();\r
if (m2 != 0u)\r
{\r
USBFS_PrepareInBuffer(m2, (uint8 *)&USBFS_MIDI2_Event.msgBuff[0],\r
- USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01);\r
+ USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01);\r
}\r
}\r
#endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
-\r
- }while( (USBFS_midiInPointer <=\r
- (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) &&\r
- ((m1 != 0u) || (m2 != 0u)) );\r
- #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
+ }\r
+ while((USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) &&\r
+ ((m1 != 0u) || (m2 != 0u)));\r
+ }\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
/* Service the USB MIDI input endpoint */\r
USBFS_MIDI_IN_EP_Service();\r
}\r
\r
\r
- /*******************************************************************************\r
+ /***************************************************************************\r
* Function Name: USBFS_PutUsbMidiIn\r
- ********************************************************************************\r
+ ************************************************************************//**\r
*\r
- * Summary:\r
- * Puts one MIDI messages into the USB MIDI In endpoint buffer. These are\r
- * MIDI input messages to the host. This function is only used if the device\r
- * has internal MIDI input functionality. USBMIDI_MIDI_IN_Service() function\r
- * should additionally be called to send the message from local buffer to\r
- * IN endpoint.\r
+ * This function puts one MIDI message into the USB MIDI In endpoint buffer.\r
+ * This is a MIDI input message to the host. This function is used only if\r
+ * the device has internal MIDI input functionality.\r
+ * The USBFS_MIDI_IN_Service() function should also be called to\r
+ * send the message from local buffer to the IN endpoint.\r
*\r
- * Parameters:\r
- * ic: 0 = No message (should never happen)\r
- * 1 - 3 = Complete MIDI message in midiMsg\r
- * 3 - IN EP LENGTH = Complete SySEx message(without EOSEX byte) in\r
- * midiMsg. The length is limited by the max BULK EP size(64)\r
- * MIDI_SYSEX = Start or continuation of SysEx message\r
- * (put event bytes in midiMsg buffer)\r
- * MIDI_EOSEX = End of SysEx message\r
- * (put event bytes in midiMsg buffer)\r
- * MIDI_TUNEREQ = Tune Request message (single byte system common msg)\r
- * 0xf8 - 0xff = Single byte real-time message\r
- * midiMsg: pointer to MIDI message.\r
- * cable: cable number.\r
+ * \param ic: The length of the MIDI message or command is described on the\r
+ * following table.\r
+ * Value | Description\r
+ * ---------------|---------------------------------------------------------\r
+ * 0 | No message (should never happen)\r
+ * 1 - 3 | Complete MIDI message in midiMsg\r
+ * 3 IN EP LENGTH | Complete SySEx message(without EOSEX byte) in midiMsg. The length is limited by the max BULK EP size(64)\r
+ * MIDI_SYSEX | Start or continuation of SysEx message (put event bytes in midiMsg buffer)\r
+ * MIDI_EOSEX | End of SysEx message (put event bytes in midiMsg buffer)\r
+ * MIDI_TUNEREQ | Tune Request message (single byte system common msg)\r
+ * 0xF8 - 0xFF | Single byte real-time message\r
*\r
- * Return:\r
- * USBFS_TRUE if error.\r
- * USBFS_FALSE if success.\r
+ * \param midiMsg: pointer to MIDI message.\r
+ * \param cable: cable number.\r
*\r
- * Global variables:\r
- * USBFS_midi_in_ep: MIDI IN endpoint number used for sending data.\r
- * USBFS_midiInPointer: Checked this variable to see if there is\r
- * enough free space in the IN endpoint buffer. If buffer is full, initiate\r
- * sending to PC.\r
+ * \return\r
+ * Return Value | Description\r
+ * ----------------------|-----------------------------------------\r
+ * USBFS_TRUE | Host is not ready to receive this message\r
+ * USBFS_FALSE | Success transfer\r
*\r
- * Reentrant:\r
+ * \globalvars\r
+ *\r
+ * \ref USBFS_midi_in_ep: MIDI IN endpoint number used for\r
+ * sending data.\r
+ *\r
+ * \ref USBFS_midiInPointer: Checked this variable to see if\r
+ * there is enough free space in the IN endpoint buffer. If buffer is\r
+ * full, initiate sending to PC.\r
+ *\r
+ * \reentrant\r
* No\r
*\r
- *******************************************************************************/\r
+ ***************************************************************************/\r
uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable)\r
\r
{\r
uint8 msgIndex;\r
\r
/* Protect PrepareInBuffer() function from concurrent calls */\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
- MIDI1_UART_DisableRxInt();\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- MIDI2_UART_DisableRxInt();\r
- #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
- #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
+ #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
+ MIDI1_UART_DisableRxInt();\r
+ #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
+ MIDI2_UART_DisableRxInt();\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
if (USBFS_midiInPointer >\r
(USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
{\r
USBFS_MIDI_IN_EP_Service();\r
}\r
+\r
if (USBFS_midiInPointer <=\r
(USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
{\r
USBFS_PrepareInBuffer(ic, midiMsg, ic, cable);\r
}\r
else\r
- { /* Only SysEx message is greater than 4 bytes */\r
+ {\r
+ /* Only SysEx message is greater than 4 bytes */\r
msgIndex = 0u;\r
+\r
do\r
{\r
USBFS_PrepareInBuffer(USBFS_MIDI_SYSEX, &midiMsg[msgIndex],\r
USBFS_EVENT_BYTE3, cable);\r
+\r
ic -= USBFS_EVENT_BYTE3;\r
msgIndex += USBFS_EVENT_BYTE3;\r
+\r
if (USBFS_midiInPointer >\r
(USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
{\r
USBFS_MIDI_IN_EP_Service();\r
- if(USBFS_midiInPointer >\r
- (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
+\r
+ if (USBFS_midiInPointer >\r
+ (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
{\r
/* Error condition. HOST is not ready to receive this packet. */\r
retError = USBFS_TRUE;\r
}\r
}\r
}\r
- while(ic > USBFS_EVENT_BYTE3);\r
+ while (ic > USBFS_EVENT_BYTE3);\r
\r
- if(retError == USBFS_FALSE)\r
+ if (retError == USBFS_FALSE)\r
{\r
USBFS_PrepareInBuffer(USBFS_MIDI_EOSEX, midiMsg, ic, cable);\r
}\r
retError = USBFS_TRUE;\r
}\r
\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
- MIDI1_UART_EnableRxInt();\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- MIDI2_UART_EnableRxInt();\r
- #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
- #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
+ #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
+ MIDI1_UART_EnableRxInt();\r
+ #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
+ MIDI2_UART_EnableRxInt();\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
return (retError);\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_PrepareInBuffer\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Builds a USB MIDI event in the input endpoint buffer at the current pointer.\r
* Puts one MIDI message into the USB MIDI In endpoint buffer.\r
*\r
- * Parameters:\r
- * ic: 0 = No message (should never happen)\r
+ * \param ic: 0 = No message (should never happen)\r
* 1 - 3 = Complete MIDI message at pMdat[0]\r
* MIDI_SYSEX = Start or continuation of SysEx message\r
* (put eventLen bytes in buffer)\r
* MIDI_TUNEREQ = Tune Request message (single byte system common msg)\r
* 0xf8 - 0xff = Single byte real-time message\r
*\r
- * srcBuff: pointer to MIDI data\r
- * eventLen: number of bytes in MIDI event\r
- * cable: MIDI source port number\r
- *\r
- * Return:\r
- * None\r
+ * \param srcBuff: pointer to MIDI data\r
+ * \param eventLen: number of bytes in MIDI event\r
+ * \param cable: MIDI source port number\r
*\r
- * Global variables:\r
+ * \globalvars\r
* USBFS_midiInBuffer: This buffer is used for saving and combine the\r
* received from UART(s) and(or) generated internally by\r
* USBFS_PutUsbMidiIn() function messages.\r
* USBFS_midiInPointer: Used as an index for midiInBuffer to\r
* write data.\r
*\r
- * Reentrant:\r
+ * \reentrant\r
* No\r
*\r
*******************************************************************************/\r
}\r
}\r
\r
-#endif /* #if (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
+#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
\r
\r
/* The implementation for external serial input and output connections\r
* to route USB MIDI data to and from those connections.\r
*/\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
-\r
-\r
/*******************************************************************************\r
- * Function Name: USBFS_MIDI_Init\r
- ********************************************************************************\r
+ * Function Name: USBFS_MIDI_InitInterface\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Initializes MIDI variables and starts the UART(s) hardware block(s).\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Side Effects:\r
+ * \sideeffect\r
* Change the priority of the UART(s) TX interrupts to be higher than the\r
* default EP ISR priority.\r
*\r
- * Global variables:\r
+ * \globalvars\r
* USBFS_MIDI_Event: initialized to zero.\r
* USBFS_MIDI_TxRunStat: initialized to zero.\r
*\r
*******************************************************************************/\r
- void USBFS_MIDI_Init(void) \r
+ void USBFS_MIDI_InitInterface(void) \r
{\r
- USBFS_MIDI1_Event.length = 0u;\r
- USBFS_MIDI1_Event.count = 0u;\r
- USBFS_MIDI1_Event.size = 0u;\r
+ USBFS_MIDI1_Event.length = 0u;\r
+ USBFS_MIDI1_Event.count = 0u;\r
+ USBFS_MIDI1_Event.size = 0u;\r
USBFS_MIDI1_Event.runstat = 0u;\r
- USBFS_MIDI1_TxRunStat = 0u;\r
- USBFS_MIDI1_InqFlags = 0u;\r
+ USBFS_MIDI1_TxRunStat = 0u;\r
+ USBFS_MIDI1_InqFlags = 0u;\r
+\r
/* Start UART block */\r
MIDI1_UART_Start();\r
+\r
/* Change the priority of the UART TX and RX interrupt */\r
CyIntSetPriority(MIDI1_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM);\r
CyIntSetPriority(MIDI1_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM);\r
\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- USBFS_MIDI2_Event.length = 0u;\r
- USBFS_MIDI2_Event.count = 0u;\r
- USBFS_MIDI2_Event.size = 0u;\r
- USBFS_MIDI2_Event.runstat = 0u;\r
- USBFS_MIDI2_TxRunStat = 0u;\r
- USBFS_MIDI2_InqFlags = 0u;\r
- /* Start second UART block */\r
- MIDI2_UART_Start();\r
- /* Change the priority of the UART TX interrupt */\r
- CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM);\r
- CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM);\r
- #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/\r
+ #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
+ USBFS_MIDI2_Event.length = 0u;\r
+ USBFS_MIDI2_Event.count = 0u;\r
+ USBFS_MIDI2_Event.size = 0u;\r
+ USBFS_MIDI2_Event.runstat = 0u;\r
+ USBFS_MIDI2_TxRunStat = 0u;\r
+ USBFS_MIDI2_InqFlags = 0u;\r
+\r
+ /* Start second UART block */\r
+ MIDI2_UART_Start();\r
+\r
+ /* Change the priority of the UART TX interrupt */\r
+ CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM);\r
+ CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM);\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
\r
/* `#START MIDI_INIT_CUSTOM` Init other extended UARTs here */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_MIDI_INIT_CALLBACK\r
- USBFS_MIDI_Init_Callback();\r
- #endif /* USBFS_MIDI_INIT_CALLBACK */\r
+ #ifdef USBFS_MIDI_INIT_CALLBACK\r
+ USBFS_MIDI_Init_Callback();\r
+ #endif /* (USBFS_MIDI_INIT_CALLBACK) */\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ProcessMidiIn\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Processes one byte of incoming MIDI data.\r
*\r
- * Parameters:\r
* mData = current MIDI input data byte\r
* *rxStat = pointer to a MIDI_RX_STATUS structure\r
*\r
- * Return:\r
+ * \return\r
* 0, if no complete message\r
* 1 - 4, if message complete\r
* MIDI_SYSEX, if start or continuation of system exclusive\r
break;\r
case USBFS_MIDI_PROGRAM_CHANGE:\r
case USBFS_MIDI_CHANNEL_PRESSURE:\r
- rxStat->size =rxStat->count;\r
+ rxStat->size = rxStat->count;\r
rxStat->count = 0u;\r
midiReturn = rxStat->size;\r
break;\r
\r
/*******************************************************************************\r
* Function Name: USBFS_MIDI1_GetEvent\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Checks for incoming MIDI data, calls the MIDI event builder if so.\r
* Returns either empty or with a complete event.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
+ * \return\r
* 0, if no complete message\r
* 1 - 4, if message complete\r
* MIDI_SYSEX, if start or continuation of system exclusive\r
* MIDI_EOSEX, if end of system exclusive\r
* 0xf8 - 0xff, if single byte real time message\r
*\r
- * Global variables:\r
+ * \globalvars\r
* USBFS_MIDI1_Event: RX status structure used to parse received\r
* data.\r
*\r
/* Read buffer loop condition to the local variable */\r
rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect;\r
\r
- if ( (MIDI1_UART_rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u) )\r
+ if ((MIDI1_UART_rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u))\r
{\r
/* Protect variables that could change on interrupt by disabling Rx interrupt.*/\r
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
#endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+\r
rxBufferRead = MIDI1_UART_rxBufferRead;\r
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
rxBufferWrite = MIDI1_UART_rxBufferWrite;\r
rxData = MIDI1_UART_rxBuffer[rxBufferRead];\r
/* Increment pointer with a wrap */\r
rxBufferRead++;\r
- if(rxBufferRead >= MIDI1_UART_RXBUFFERSIZE)\r
+ if (rxBufferRead >= MIDI1_UART_RXBUFFERSIZE)\r
{\r
rxBufferRead = 0u;\r
}\r
+\r
/* If loop condition was set - update real read buffer pointer\r
* to avoid overflow status\r
*/\r
- if(rxBufferLoopDetect != 0u )\r
+ if (rxBufferLoopDetect != 0u )\r
{\r
MIDI1_UART_rxBufferLoopDetect = 0u;\r
- #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
+ CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
+ #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+\r
MIDI1_UART_rxBufferRead = rxBufferRead;\r
- #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntEnable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
+ CyIntEnable(MIDI1_UART_RX_VECT_NUM);\r
+ #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */\r
}\r
\r
msgRtn = USBFS_ProcessMidiIn(rxData,\r
/* Finally, update the real output pointer, then return with\r
* an indication as to whether there's a complete message in the buffer.\r
*/\r
- #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
- MIDI1_UART_rxBufferRead = rxBufferRead;\r
- #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntEnable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+ #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
+ CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+\r
+ MIDI1_UART_rxBufferRead = rxBufferRead;\r
+ #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
+ CyIntEnable(MIDI1_UART_RX_VECT_NUM);\r
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
}\r
\r
return (msgRtn);\r
\r
/*******************************************************************************\r
* Function Name: USBFS_MIDI1_ProcessUsbOut\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Process a USB MIDI output event.\r
* Puts data into the MIDI TX output buffer.\r
*\r
- * Parameters:\r
- * *epBuf: pointer on MIDI event.\r
+ * \param *epBuf: pointer on MIDI event.\r
*\r
- * Return:\r
- * None\r
- *\r
- * Global variables:\r
+ * \globalvars\r
* USBFS_MIDI1_TxRunStat: This variable used to save the MIDI\r
* status byte and skip to send the repeated status byte in subsequent event.\r
* USBFS_MIDI1_InqFlags: The following flags are set when SysEx\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK\r
- USBFS_MIDI1_ProcessUsbOut_EntryCallback();\r
- #endif /* USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK */\r
+ #ifdef USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK\r
+ USBFS_MIDI1_ProcessUsbOut_EntryCallback();\r
+ #endif /* (USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK) */\r
\r
cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK;\r
- if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1))\r
+\r
+ if ((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1))\r
{\r
len = USBFS_MIDI_SIZE[cmd];\r
i = USBFS_EVENT_BYTE1;\r
/* Universal System Exclusive message parsing */\r
- if(cmd == USBFS_SYSEX)\r
+ if (cmd == USBFS_SYSEX)\r
{\r
- if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) &&\r
- (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME))\r
- { /* Non-Real Time SySEx starts */\r
+ if ((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) &&\r
+ (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME))\r
+ {\r
+ /* Non-Real Time SySEx starts */\r
USBFS_MIDI1_InqFlags |= USBFS_INQ_SYSEX_FLAG;\r
}\r
else\r
USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG;\r
}\r
}\r
- else if(cmd == USBFS_SYSEX_ENDS_WITH1)\r
+ else if (cmd == USBFS_SYSEX_ENDS_WITH1)\r
{\r
USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG;\r
}\r
- else if(cmd == USBFS_SYSEX_ENDS_WITH2)\r
+ else if (cmd == USBFS_SYSEX_ENDS_WITH2)\r
{\r
USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG;\r
}\r
- else if(cmd == USBFS_SYSEX_ENDS_WITH3)\r
+ else if (cmd == USBFS_SYSEX_ENDS_WITH3)\r
{\r
/* Identify Request support */\r
- if((USBFS_MIDI1_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u)\r
+ if ((USBFS_MIDI1_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u)\r
{\r
USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG;\r
- if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) &&\r
- (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ))\r
- { /* Set the flag about received the Identity Request.\r
+ if ((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) &&\r
+ (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ))\r
+ {\r
+ /* Set the flag about received the Identity Request.\r
* The Identity Reply message may be send by user code.\r
*/\r
USBFS_MIDI1_InqFlags |= USBFS_INQ_IDENTITY_REQ_FLAG;\r
else /* Do nothing for other command */\r
{\r
}\r
+\r
/* Running Status for Voice and Mode messages only. */\r
- if((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE))\r
+ if ((cmd >= USBFS_NOTE_OFF) && (cmd <= USBFS_PITCH_BEND_CHANGE))\r
{\r
- if(USBFS_MIDI1_TxRunStat == epBuf[USBFS_EVENT_BYTE1])\r
- { /* Skip the repeated Status byte */\r
+ if (USBFS_MIDI1_TxRunStat == epBuf[USBFS_EVENT_BYTE1])\r
+ {\r
+ /* Skip the repeated Status byte */\r
i++;\r
}\r
else\r
- { /* Save Status byte for next event */\r
+ {\r
+ /* Save Status byte for next event */\r
USBFS_MIDI1_TxRunStat = epBuf[USBFS_EVENT_BYTE1];\r
}\r
}\r
else\r
- { /* Clear Running Status */\r
+ {\r
+ /* Clear Running Status */\r
USBFS_MIDI1_TxRunStat = 0u;\r
}\r
+\r
/* Puts data into the MIDI TX output buffer.*/\r
do\r
{\r
MIDI1_UART_PutChar(epBuf[i]);\r
i++;\r
- } while (i <= len);\r
+ }\r
+ while (i <= len);\r
}\r
\r
/* User code is required at the end of the procedure */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK\r
- USBFS_MIDI1_ProcessUsbOut_ExitCallback();\r
- #endif /* USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK */\r
+ #ifdef USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK\r
+ USBFS_MIDI1_ProcessUsbOut_ExitCallback();\r
+ #endif /* (USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK) */\r
}\r
\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
-\r
-\r
/*******************************************************************************\r
* Function Name: USBFS_MIDI2_GetEvent\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Checks for incoming MIDI data, calls the MIDI event builder if so.\r
* Returns either empty or with a complete event.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
+ * \return\r
* 0, if no complete message\r
* 1 - 4, if message complete\r
* MIDI_SYSEX, if start or continuation of system exclusive\r
* MIDI_EOSEX, if end of system exclusive\r
* 0xf8 - 0xff, if single byte real time message\r
*\r
- * Global variables:\r
+ * \globalvars\r
* USBFS_MIDI2_Event: RX status structure used to parse received\r
* data.\r
*\r
{\r
uint8 msgRtn = 0u;\r
uint8 rxData;\r
+\r
#if (MIDI2_UART_RXBUFFERSIZE >= 256u)\r
uint16 rxBufferRead;\r
#if (CY_PSOC3) /* This local variable required only for PSOC3 and large buffer */\r
{\r
rxBufferRead = 0u;\r
}\r
+\r
/* If loop condition was set - update real read buffer pointer\r
* to avoid overflow status\r
*/\r
- if(rxBufferLoopDetect != 0u )\r
+ if (rxBufferLoopDetect != 0u)\r
{\r
MIDI2_UART_rxBufferLoopDetect = 0u;\r
- #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntDisable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+ #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
+ CyIntDisable(MIDI2_UART_RX_VECT_NUM);\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+\r
MIDI2_UART_rxBufferRead = rxBufferRead;\r
- #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntEnable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+ #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
+ CyIntEnable(MIDI2_UART_RX_VECT_NUM);\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
}\r
\r
msgRtn = USBFS_ProcessMidiIn(rxData,\r
/* Finally, update the real output pointer, then return with\r
* an indication as to whether there's a complete message in the buffer.\r
*/\r
- #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntDisable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+ #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
+ CyIntDisable(MIDI2_UART_RX_VECT_NUM);\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+\r
MIDI2_UART_rxBufferRead = rxBufferRead;\r
- #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntEnable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+ #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
+ CyIntEnable(MIDI2_UART_RX_VECT_NUM);\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
}\r
\r
return (msgRtn);\r
\r
/*******************************************************************************\r
* Function Name: USBFS_MIDI2_ProcessUsbOut\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Process a USB MIDI output event.\r
* Puts data into the MIDI TX output buffer.\r
*\r
- * Parameters:\r
- * *epBuf: pointer on MIDI event.\r
- *\r
- * Return:\r
- * None\r
+ * \param *epBuf: pointer on MIDI event.\r
*\r
- * Global variables:\r
+ * \globalvars\r
* USBFS_MIDI2_TxRunStat: This variable used to save the MIDI\r
* status byte and skip to send the repeated status byte in subsequent event.\r
* USBFS_MIDI2_InqFlags: The following flags are set when SysEx\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK\r
- USBFS_MIDI2_ProcessUsbOut_EntryCallback();\r
- #endif /* USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK */\r
+ #ifdef USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK\r
+ USBFS_MIDI2_ProcessUsbOut_EntryCallback();\r
+ #endif /* (USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK) */\r
\r
cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK;\r
- if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1))\r
+\r
+ if ((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1))\r
{\r
len = USBFS_MIDI_SIZE[cmd];\r
i = USBFS_EVENT_BYTE1;\r
+\r
/* Universal System Exclusive message parsing */\r
if(cmd == USBFS_SYSEX)\r
{\r
if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) &&\r
(epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME))\r
- { /* SySEx starts */\r
+ {\r
+ /* SySEx starts */\r
USBFS_MIDI2_InqFlags |= USBFS_INQ_SYSEX_FLAG;\r
}\r
else\r
else if(cmd == USBFS_SYSEX_ENDS_WITH3)\r
{\r
/* Identify Request support */\r
- if((USBFS_MIDI2_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u)\r
+ if ((USBFS_MIDI2_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u)\r
{\r
USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG;\r
+\r
if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) &&\r
(epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ))\r
{ /* Set the flag about received the Identity Request.\r
else /* Do nothing for other command */\r
{\r
}\r
+\r
/* Running Status for Voice and Mode messages only. */\r
- if((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE))\r
+ if ((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE))\r
{\r
- if(USBFS_MIDI2_TxRunStat == epBuf[USBFS_EVENT_BYTE1])\r
+ if (USBFS_MIDI2_TxRunStat == epBuf[USBFS_EVENT_BYTE1])\r
{ /* Skip the repeated Status byte */\r
i++;\r
}\r
{ /* Clear Running Status */\r
USBFS_MIDI2_TxRunStat = 0u;\r
}\r
+\r
/* Puts data into the MIDI TX output buffer.*/\r
do\r
{\r
MIDI2_UART_PutChar(epBuf[i]);\r
i++;\r
- } while (i <= len);\r
+ }\r
+ while (i <= len);\r
}\r
\r
/* User code is required at the end of the procedure */\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK\r
- USBFS_MIDI2_ProcessUsbOut_ExitCallback();\r
- #endif /* USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK */\r
+ #ifdef USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK\r
+ USBFS_MIDI2_ProcessUsbOut_ExitCallback();\r
+ #endif /* (USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK) */\r
}\r
#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
/* `#END` */\r
\r
-#endif /* defined(USBFS_ENABLE_MIDI_STREAMING) */\r
+#endif /* defined(USBFS_ENABLE_MIDI_STREAMING) */\r
\r
\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: USBFS_midi.h\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_midi.h\r
+* \version 3.10\r
*\r
-* Description:\r
-* Header File for the USBFS MIDI module.\r
-* Contains prototypes and constant values.\r
+* \brief\r
+* This file provides function prototypes and constants for the USBFS component \r
+* MIDI class support.\r
*\r
* Related Document:\r
* Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0\r
* MIDI 1.0 Detailed Specification Document Version 4.2\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#if !defined(CY_USBFS_USBFS_midi_H)\r
#define CY_USBFS_USBFS_midi_H\r
\r
-#include "cytypes.h"\r
#include "USBFS.h"\r
\r
+/***************************************\r
+* Initial Parameter Constants\r
+***************************************/\r
+\r
+#define USBFS_ENABLE_MIDI_API (0u != (1u))\r
+#define USBFS_MIDI_EXT_MODE (0u)\r
+\r
+\r
+/* Number of external interfaces (UARTs). */\r
+#define USBFS_ONE_EXT_INTRF (0x01u)\r
+#define USBFS_TWO_EXT_INTRF (0x02u)\r
+ \r
+#define USBFS_ISR_SERVICE_MIDI_OUT \\r
+ ((USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_OUT_BUFF_SIZE > 0) && \\r
+ (USBFS_EP_MANAGEMENT_DMA_AUTO))\r
+\r
+#define USBFS_ISR_SERVICE_MIDI_IN \\r
+ ((USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0))\r
+\r
+\r
+/***************************************\r
+* External References\r
+***************************************/\r
+\r
+#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
+ #include "MIDI1_UART.h"\r
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
+\r
+#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
+ #include "MIDI2_UART.h"\r
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+\r
\r
/***************************************\r
* Data Structure Definition\r
***************************************/\r
\r
/* The following structure is used to hold status information for\r
- building and parsing incoming MIDI messages. */\r
+* building and parsing incoming MIDI messages. \r
+*/\r
typedef struct\r
{\r
uint8 length; /* expected length */\r
uint8 count; /* current byte count */\r
uint8 size; /* complete size */\r
uint8 runstat; /* running status */\r
- uint8 msgBuff[4]; /* message buffer */\r
+ uint8 msgBuff[4u]; /* message buffer */\r
} USBFS_MIDI_RX_STATUS;\r
\r
\r
/***************************************\r
-* MIDI Constants.\r
+* Function Prototypes\r
***************************************/\r
+/**\r
+* \addtogroup group_midi\r
+* @{\r
+*/\r
+#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)\r
+ void USBFS_MIDI_Init(void) ;\r
+\r
+ #if (USBFS_MIDI_IN_BUFF_SIZE > 0u)\r
+ void USBFS_MIDI_IN_Service(void) ;\r
+ uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable) ;\r
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0u) */\r
+\r
+ #if (USBFS_MIDI_OUT_BUFF_SIZE > 0u)\r
+ void USBFS_MIDI_OUT_Service(void) ;\r
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0u) */\r
+#endif /* (USBFS_ENABLE_MIDI_API != 0u) */\r
+\r
+\r
+/*******************************************************************************\r
+* Callback Function Prototypes\r
+*******************************************************************************/\r
\r
-#define USBFS_ONE_EXT_INTRF (0x01u)\r
-#define USBFS_TWO_EXT_INTRF (0x02u)\r
+/*******************************************************************************\r
+* Function Name: USBFS_callbackLocalMidiEvent\r
+****************************************************************************//**\r
+*\r
+* This is a callback function that locally processes data received from the PC \r
+* in main.c. You should implement this function if you want to use it. It is \r
+* called from the USB output processing routine for each MIDI output event \r
+* processed (decoded) from the output endpoint buffer. \r
+*\r
+* \param cable: Cable number\r
+* \r
+* \param midiMsg: Pointer to the 3-byte MIDI message\r
+*\r
+*\r
+***************************************************************************/\r
+void USBFS_callbackLocalMidiEvent(uint8 cable, uint8 *midiMsg)\r
+ ;\r
+/** @} midi */\r
+ \r
+/***************************************\r
+* MIDI Constants.\r
+***************************************/\r
\r
/* Flag definitions for use with MIDI device inquiry */\r
#define USBFS_INQ_SYSEX_FLAG (0x01u)\r
/* MIDI Universal System Exclusive defines */\r
#define USBFS_MIDI_SYSEX_NON_REAL_TIME (0x7Eu)\r
#define USBFS_MIDI_SYSEX_REALTIME (0x7Fu)\r
+\r
/* ID of target device */\r
#define USBFS_MIDI_SYSEX_ID_ALL (0x7Fu)\r
+\r
/* Sub-ID#1*/\r
#define USBFS_MIDI_SYSEX_GEN_INFORMATION (0x06u)\r
#define USBFS_MIDI_SYSEX_GEN_MESSAGE (0x09u)\r
+\r
/* Sub-ID#2*/\r
#define USBFS_MIDI_SYSEX_IDENTITY_REQ (0x01u)\r
#define USBFS_MIDI_SYSEX_IDENTITY_REPLY (0x02u)\r
#define USBFS_MIDI_SYSEX_SYSTEM_ON (0x01u)\r
#define USBFS_MIDI_SYSEX_SYSTEM_OFF (0x02u)\r
\r
-#define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x04u)\r
-#define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x02u)\r
-\r
-#define USBFS_ISR_SERVICE_MIDI_OUT \\r
- ( (USBFS_ENABLE_MIDI_API != 0u) && \\r
- (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO))\r
-#define USBFS_ISR_SERVICE_MIDI_IN \\r
- ( (USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0) )\r
-\r
-\r
-/***************************************\r
-* External function references\r
-***************************************/\r
-\r
-void USBFS_callbackLocalMidiEvent(uint8 cable, uint8 *midiMsg)\r
- ;\r
-\r
-\r
-/***************************************\r
-* External references\r
-***************************************/\r
-\r
-#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
- #include "MIDI1_UART.h"\r
-#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
-#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- #include "MIDI2_UART.h"\r
-#endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
-#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- #include <CyDmac.h>\r
-#endif /* USBFS_EP_MM */\r
+/* UART TX and RX interrupt priority. */\r
+#if (CY_PSOC4)\r
+ #define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x01u)\r
+ #define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x02u)\r
+#else\r
+ #define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x02u)\r
+ #define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x04u)\r
+#endif /* (CYPSOC4) */\r
\r
\r
/***************************************\r
-* Private function prototypes\r
+* Private Function Prototypes\r
***************************************/\r
\r
void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint8 cable)\r
- ;\r
+ ;\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
- void USBFS_MIDI_Init(void) ;\r
+ void USBFS_MIDI_InitInterface(void) ;\r
uint8 USBFS_ProcessMidiIn(uint8 mData, USBFS_MIDI_RX_STATUS *rxStat)\r
;\r
- uint8 USBFS_MIDI1_GetEvent(void) ;\r
- void USBFS_MIDI1_ProcessUsbOut(const uint8 epBuf[])\r
- ;\r
+ uint8 USBFS_MIDI1_GetEvent(void) ;\r
+ void USBFS_MIDI1_ProcessUsbOut(const uint8 epBuf[])\r
+ ;\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- uint8 USBFS_MIDI2_GetEvent(void) ;\r
- void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[])\r
- ;\r
- #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
-#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ uint8 USBFS_MIDI2_GetEvent(void) ;\r
+ void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[])\r
+ ;\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
\r
/***************************************\r
-* External data references\r
+* Vars with External Linkage\r
***************************************/\r
\r
#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
\r
#if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
#if (USBFS_MIDI_IN_BUFF_SIZE >= 256)\r
+/**\r
+* \addtogroup group_midi\r
+* @{\r
+*/ \r
extern volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */\r
+/** @} midi*/\r
#else\r
extern volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */\r
- #endif /* USBFS_MIDI_IN_BUFF_SIZE >=256 */\r
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE >=256) */\r
+/**\r
+* \addtogroup group_midi\r
+* @{\r
+*/ \r
extern volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */\r
extern uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */\r
-#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */\r
+#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
\r
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
extern volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */\r
extern uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */\r
-#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */\r
+#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
- extern volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */\r
+ extern volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */\r
+ \r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- extern volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */\r
- #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
-#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ extern volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
+/** @} midi */\r
+#endif /* (USBFS_ENABLE_MIDI_STREAMING) */\r
+\r
\r
-#endif /* USBFS_ENABLE_MIDI_STREAMING */\r
+/***************************************\r
+* The following code is DEPRECATED and\r
+* must not be used.\r
+***************************************/\r
\r
+#define USBFS_MIDI_EP_Init USBFS_MIDI_Init\r
+#define USBFS_MIDI_OUT_EP_Service USBFS_MIDI_OUT_Service\r
\r
-#endif /* CY_USBFS_USBFS_midi_H */\r
+#endif /* (CY_USBFS_USBFS_midi_H) */\r
\r
\r
/* [] END OF FILE */\r
--- /dev/null
+/***************************************************************************//**
+* \file USBFS_cdc.c
+* \version 3.10
+*
+* \brief
+* This file contains the USB MSC Class request handler and global API for MSC
+* class.
+*
+* Related Document:
+* Universal Serial Bus Class Definitions for Communication Devices Version 1.1
+*
+********************************************************************************
+* \copyright
+* Copyright 2012-2016, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "USBFS_msc.h"
+#include "USBFS_pvt.h"
+
+
+#if (USBFS_HANDLE_MSC_REQUESTS)
+
+/***************************************
+* Internal variables
+***************************************/
+
+static uint8 USBFS_lunCount = USBFS_MSC_LUN_NUMBER;
+
+
+/*******************************************************************************
+* Function Name: USBFS_DispatchMSCClassRqst
+****************************************************************************//**
+*
+* \internal
+* This routine dispatches MSC class requests.
+*
+* \return
+* Status of request processing: handled or not handled.
+*
+* \globalvars
+* USBFS_lunCount - stores number of LUN (logical units).
+*
+* \reentrant
+* No.
+*
+*******************************************************************************/
+uint8 USBFS_DispatchMSCClassRqst(void)
+{
+ uint8 requestHandled = USBFS_FALSE;
+
+ /* Get request data. */
+ uint16 value = USBFS_GET_UINT16(USBFS_wValueHiReg, USBFS_wValueLoReg);
+ uint16 dataLength = USBFS_GET_UINT16(USBFS_wLengthHiReg, USBFS_wLengthLoReg);
+
+ /* Check request direction: D2H or H2D. */
+ if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H))
+ {
+ /* Handle direction from device to host. */
+
+ if (USBFS_MSC_GET_MAX_LUN == USBFS_bRequestReg)
+ {
+ /* Check request fields. */
+ if ((value == USBFS_MSC_GET_MAX_LUN_WVALUE) &&
+ (dataLength == USBFS_MSC_GET_MAX_LUN_WLENGTH))
+ {
+ /* Reply to Get Max LUN request: setup control read. */
+ USBFS_currentTD.pData = &USBFS_lunCount;
+ USBFS_currentTD.count = USBFS_MSC_GET_MAX_LUN_WLENGTH;
+
+ requestHandled = USBFS_InitControlRead();
+ }
+ }
+ }
+ else
+ {
+ /* Handle direction from host to device. */
+
+ if (USBFS_MSC_RESET == USBFS_bRequestReg)
+ {
+ /* Check request fields. */
+ if ((value == USBFS_MSC_RESET_WVALUE) &&
+ (dataLength == USBFS_MSC_RESET_WLENGTH))
+ {
+ /* Handle to Bulk-Only Reset request: no data control transfer. */
+ USBFS_currentTD.count = USBFS_MSC_RESET_WLENGTH;
+
+ #ifdef USBFS_DISPATCH_MSC_CLASS_MSC_RESET_RQST_CALLBACK
+ USBFS_DispatchMSCClass_MSC_RESET_RQST_Callback();
+ #endif /* (USBFS_DISPATCH_MSC_CLASS_MSC_RESET_RQST_CALLBACK) */
+
+ requestHandled = USBFS_InitNoDataControlTransfer();
+ }
+ }
+ }
+
+ return (requestHandled);
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_MSC_SetLunCount
+****************************************************************************//**
+*
+* This function sets the number of logical units supported in the application.
+* The default number of logical units is set in the component customizer.
+*
+* \param lunCount: Count of the logical units. Valid range is between 1 and 16.
+*
+*
+* \globalvars
+* USBFS_lunCount - stores number of LUN (logical units).
+*
+* \reentrant
+* No.
+*
+*******************************************************************************/
+void USBFS_MSC_SetLunCount(uint8 lunCount)
+{
+ USBFS_lunCount = (lunCount - 1u);
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_MSC_GetLunCount
+****************************************************************************//**
+*
+* This function returns the number of logical units.
+*
+* \return
+* Number of the logical units.
+*
+* \globalvars
+* USBFS_lunCount - stores number of LUN (logical units).
+*
+* \reentrant
+* No.
+*
+*******************************************************************************/
+uint8 USBFS_MSC_GetLunCount(void)
+{
+ return (USBFS_lunCount + 1u);
+}
+
+#endif /* (USBFS_HANDLE_MSC_REQUESTS) */
+
+
+/* [] END OF FILE */
--- /dev/null
+/***************************************************************************//**
+* \file USBFS_msc.h
+* \version 3.10
+*
+* \brief
+* This file provides function prototypes and constants for the USBFS component
+* MSC class support.
+*
+* Related Document:
+* Device Class Definition for Mass Storage (MSC) Version TDB
+*
+********************************************************************************
+* \copyright
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_USBFS_USBFS_msc_H)
+#define CY_USBFS_USBFS_msc_H
+
+#include "USBFS.h"
+
+/***************************************
+* Initial Parameter Constants
+***************************************/
+
+#define USBFS_HANDLE_MSC_REQUESTS (0u != (1u))
+#define USBFS_MSC_LUN_NUMBER (1u - 1u)
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+/**
+* \addtogroup group_msc
+* @{
+*/
+#if (USBFS_HANDLE_MSC_REQUESTS)
+ void USBFS_MSC_SetLunCount(uint8 lunCount) ;
+ uint8 USBFS_MSC_GetLunCount(void) ;
+#endif /* (USBFS_HANDLE_MSC_REQUESTS) */
+/** @} msc */
+
+/***************************************
+* Constants
+***************************************/
+
+/* MSC Class-Specific requests */
+#define USBFS_MSC_RESET (0xFFu)
+#define USBFS_MSC_GET_MAX_LUN (0xFEu)
+
+/* MSC Class-Specific requests constant fields. */
+#define USBFS_MSC_RESET_WVALUE (0u)
+#define USBFS_MSC_RESET_WLENGTH (0u)
+
+#define USBFS_MSC_GET_MAX_LUN_WVALUE (0u)
+#define USBFS_MSC_GET_MAX_LUN_WLENGTH (1u)
+
+#endif /* CY_USBFS_USBFS_msc_H */
+
+
+/* [] END OF FILE */
-/*******************************************************************************\r
-* File Name: USBFS_pm.c\r
-* Version 2.80\r
-*\r
-* Description:\r
-* This file provides Suspend/Resume APIs functionality.\r
+/***************************************************************************//**\r
+* \file USBFS_pm.c\r
+* \version 3.10\r
*\r
-* Note:\r
+* \brief\r
+* This file provides Suspend/Resume APIs implementation.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "project.h"\r
-#include "USBFS.h"\r
#include "USBFS_pvt.h"\r
-\r
+#include "USBFS_Dp.h"\r
\r
\r
/***************************************\r
\r
static USBFS_BACKUP_STRUCT USBFS_backup;\r
\r
-\r
-#if(USBFS_DP_ISR_REMOVE == 0u)\r
-\r
+#if (USBFS_DP_ISR_ACTIVE)\r
/*******************************************************************************\r
- * Function Name: USBFS_DP_Interrupt\r
- ********************************************************************************\r
+ * Function Name: USBFS_DP_ISR\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* This Interrupt Service Routine handles DP pin changes for wake-up from\r
* the sleep mode.\r
*\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
*******************************************************************************/\r
CY_ISR(USBFS_DP_ISR)\r
{\r
- #ifdef USBFS_DP_ISR_ENTRY_CALLBACK\r
- USBFS_DP_ISR_EntryCallback();\r
- #endif /* USBFS_DP_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_DP_ISR_ENTRY_CALLBACK\r
+ USBFS_DP_ISR_EntryCallback();\r
+ #endif /* (USBFS_DP_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START DP_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- /* Clears active interrupt */\r
- CY_GET_REG8(USBFS_DP_INTSTAT_PTR);\r
-\r
- #ifdef USBFS_DP_ISR_EXIT_CALLBACK\r
- USBFS_DP_ISR_ExitCallback();\r
- #endif /* USBFS_DP_ISR_EXIT_CALLBACK */\r
+ (void) USBFS_Dp_ClearInterrupt();\r
+ \r
+ #ifdef USBFS_DP_ISR_EXIT_CALLBACK\r
+ USBFS_DP_ISR_ExitCallback();\r
+ #endif /* (USBFS_DP_ISR_EXIT_CALLBACK) */\r
}\r
-\r
-#endif /* (USBFS_DP_ISR_REMOVE == 0u) */\r
+#endif /* (USBFS_DP_ISR_ACTIVE) */\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_SaveConfig\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Saves the current user configuration.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_SaveConfig(void) \r
{\r
-\r
+ /* Empty function added for the compatibility purpose. */\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_RestoreConfig\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Restores the current user configuration.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_RestoreConfig(void) \r
{\r
- if(USBFS_configuration != 0u)\r
+ if (USBFS_configuration != 0u)\r
{\r
USBFS_ConfigReg();\r
+ USBFS_EpStateInit();\r
}\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Suspend\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This function disables the USBFS block and prepares for power down mode.\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None.\r
+* This function prepares the USBFS component to enter low power mode. The \r
+* interrupt on falling edge on Dp pin is configured to wakeup device when the \r
+* host drives resume condition. The pull-up is enabled on the Dp line while \r
+* device is in low power mode. The supported low power modes are Deep Sleep \r
+* (PSoC 4200L) and Sleep (PSoC 3/ PSoC 5LP).\r
+* \r
+* *Note* For PSoC 4200L devices, this function should not be called before \r
+* entering Sleep.\r
+* \r
+* *Note* After enter low power mode, the data which is left in the IN or OUT \r
+* endpoint buffers is not restored after wakeup and lost. Therefore it should \r
+* be stored in the SRAM for OUT endpoint or read by the host for IN endpoint \r
+* before enter low power mode.\r
*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_backup.enable: modified.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_Suspend(void) \r
{\r
uint8 enableInterrupts;\r
+\r
enableInterrupts = CyEnterCriticalSection();\r
\r
- if((CY_GET_REG8(USBFS_CR0_PTR) & USBFS_CR0_ENABLE) != 0u)\r
- { /* USB block is enabled */\r
+ if (0u != (USBFS_CR0_REG & USBFS_CR0_ENABLE))\r
+ {\r
+ /* USB block is enabled. */\r
USBFS_backup.enableState = 1u;\r
\r
- #if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #if (USBFS_EP_MANAGEMENT_DMA)\r
+ USBFS_Stop_DMA(USBFS_MAX_EP);\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+ #if (CY_PSOC4)\r
+ /* Suspend enter sequence. */\r
+ USBFS_POWER_CTRL_REG |= (USBFS_POWER_CTRL_SUSPEND |\r
+ USBFS_POWER_CTRL_SUSPEND_DEL);\r
+\r
+ /* Store state of USB regulator and disable it. */\r
+ USBFS_backup.mode = (uint8) (USBFS_CR1_REG & USBFS_CR1_REG_ENABLE);\r
+ USBFS_CR1_REG &= (uint32) ~USBFS_CR1_REG_ENABLE;\r
+ \r
+ /* Store SIE interrupt sources. Valid bits are 0 - 4. */\r
+ USBFS_backup.intrSeiMask = (uint8) USBFS_INTR_SIE_MASK_REG;\r
\r
- /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */\r
- USBFS_USBIO_CR0_REG &= (uint8)~USBFS_USBIO_CR0_TEN;\r
- CyDelayUs(0u); /*~50ns delay */\r
+ #else\r
+ /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled. */\r
+ USBFS_USBIO_CR0_REG &= (uint8) ~USBFS_USBIO_CR0_TEN;\r
+ CyDelayUs(USBFS_WAIT_REG_STABILITY_50NS); /*~50ns delay. */\r
\r
/* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) and pd_pullup_hv(Inverted) high. */\r
- USBFS_PM_USB_CR0_REG &=\r
- (uint8)~(USBFS_PM_USB_CR0_PD_N | USBFS_PM_USB_CR0_PD_PULLUP_N);\r
+ USBFS_PM_USB_CR0_REG &= (uint8) ~(USBFS_PM_USB_CR0_PD_N |\r
+ USBFS_PM_USB_CR0_PD_PULLUP_N);\r
\r
- /* Disable the SIE */\r
- USBFS_CR0_REG &= (uint8)~USBFS_CR0_ENABLE;\r
+ /* Disable the SIE. */\r
+ USBFS_CR0_REG &= (uint8) ~USBFS_CR0_ENABLE;\r
\r
- CyDelayUs(0u); /* ~50ns delay */\r
- /* Store mode and Disable VRegulator*/\r
- USBFS_backup.mode = USBFS_CR1_REG & USBFS_CR1_REG_ENABLE;\r
- USBFS_CR1_REG &= (uint8)~USBFS_CR1_REG_ENABLE;\r
+ CyDelayUs(USBFS_WAIT_REG_STABILITY_50NS); /* ~50ns delay. */\r
+ /* Store mode and disable VRegulator. */\r
+ USBFS_backup.mode = (uint8) (USBFS_CR1_REG & USBFS_CR1_REG_ENABLE);\r
+ USBFS_CR1_REG &= (uint8) ~USBFS_CR1_REG_ENABLE;\r
+\r
+ CyDelayUs(USBFS_WAIT_REG_STABILITY_1US); /* min 0.5us delay required. */\r
\r
- CyDelayUs(1u); /* 0.5 us min delay */\r
/* Disable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/\r
- USBFS_PM_USB_CR0_REG &= (uint8)~USBFS_PM_USB_CR0_REF_EN;\r
+ USBFS_PM_USB_CR0_REG &= (uint8) ~USBFS_PM_USB_CR0_REF_EN;\r
\r
- /* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pullup*/\r
+ /* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pull-up. */\r
USBFS_USBIO_CR1_REG |= USBFS_USBIO_CR1_IOMODE;\r
\r
- /* Disable USB in ACT PM */\r
- USBFS_PM_ACT_CFG_REG &= (uint8)~USBFS_PM_ACT_EN_FSUSB;\r
- /* Disable USB block for Standby Power Mode */\r
- USBFS_PM_STBY_CFG_REG &= (uint8)~USBFS_PM_STBY_EN_FSUSB;\r
- CyDelayUs(1u); /* min 0.5us delay required */\r
+ /* Disable USBFS block. */\r
+ /* Clear power active and standby mode templates: disable USB block. */\r
+ USBFS_PM_ACT_CFG_REG &= (uint8) ~USBFS_PM_ACT_EN_FSUSB;\r
+ USBFS_PM_STBY_CFG_REG &= (uint8) ~USBFS_PM_STBY_EN_FSUSB;\r
\r
+ CyDelayUs(USBFS_WAIT_REG_STABILITY_1US); /* min 0.5us delay required. */\r
+ #endif /* (CY_PSOC4) */\r
}\r
else\r
{\r
\r
CyExitCriticalSection(enableInterrupts);\r
\r
- /* Set the DP Interrupt for wake-up from sleep mode. */\r
- #if(USBFS_DP_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR);\r
- CyIntSetPriority(USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIOR);\r
- CyIntClearPending(USBFS_DP_INTC_VECT_NUM);\r
- CyIntEnable(USBFS_DP_INTC_VECT_NUM);\r
- #endif /* (USBFS_DP_ISR_REMOVE == 0u) */\r
+#if (USBFS_DP_ISR_ACTIVE)\r
+ /* Clear active mode Dp interrupt source history. */\r
+ (void) USBFS_Dp_ClearInterrupt();\r
+ CyIntClearPending(USBFS_DP_INTC_VECT_NUM);\r
+\r
+ CyIntEnable (USBFS_DP_INTC_VECT_NUM);\r
+#endif /* (USBFS_DP_ISR_ACTIVE). */\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Resume\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This function enables the USBFS block after power down mode.\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None.\r
+* This function prepares the USBFS component for active mode operation after \r
+* exit low power mode. It restores the component active mode configuration such \r
+* as device address assigned previously by the host, endpoints buffer and disables \r
+* interrupt on Dp pin.\r
+* The supported low power modes are Deep Sleep (PSoC 4200L) and Sleep \r
+* (PSoC 3/ PSoC 5LP).\r
+* \r
+* *Note* For PSoC 4200L devices, this function should not be called after \r
+* exiting Sleep.\r
+* \r
+* *Note* To resume communication with the host, the data endpoints must be \r
+* managed: the OUT endpoints must be enabled and IN endpoints must be loaded \r
+* with data. For DMA with Automatic Buffer Management, all endpoints buffers \r
+* must be initialized again before making them available to the host.\r
*\r
-* Return:\r
-* None.\r
*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_backup - checked.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_Resume(void) \r
{\r
uint8 enableInterrupts;\r
+\r
enableInterrupts = CyEnterCriticalSection();\r
\r
- if(USBFS_backup.enableState != 0u)\r
+ if (0u != USBFS_backup.enableState)\r
{\r
- #if(USBFS_DP_ISR_REMOVE == 0u)\r
- CyIntDisable(USBFS_DP_INTC_VECT_NUM);\r
- #endif /* USBFS_DP_ISR_REMOVE */\r
+ #if (USBFS_DP_ISR_ACTIVE)\r
+ CyIntDisable(USBFS_DP_INTC_VECT_NUM);\r
+ #endif /* (USBFS_DP_ISR_ACTIVE) */\r
+\r
+ #if (CY_PSOC4)\r
+ /* Enable clock to USB IP. */\r
+ USBFS_USB_CLK_EN_REG |= USBFS_USB_CLK_CSR_CLK_EN;\r
+\r
+ /* Restore arbiter configuration for DMA transfers. */\r
+ #if (USBFS_EP_MANAGEMENT_DMA)\r
+ #if (USBFS_ARB_ISR_ACTIVE)\r
+ /* Enable ARB EP interrupt sources. */\r
+ USBFS_ARB_INT_EN_REG = USBFS_DEFAULT_ARB_INT_EN;\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+ /* Configure arbiter for Manual or Auto DMA operation and clear \r
+ * configuration completion. \r
+ */\r
+ USBFS_ARB_CFG_REG = USBFS_DEFAULT_ARB_CFG;\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+ /* Restore level (hi, lo, med) for each interrupt source. */\r
+ USBFS_INTR_LVL_SEL_REG = USBFS_DEFAULT_INTR_LVL_SEL;\r
+ \r
+ /* Store SIE interrupt sources. */\r
+ USBFS_INTR_SIE_MASK_REG = (uint32) USBFS_backup.intrSeiMask;\r
+\r
+ /* Set EP0.CR: ACK Setup, NAK IN/OUT. */\r
+ USBFS_EP0_CR_REG = USBFS_MODE_NAK_IN_OUT;\r
+\r
+ /* Restore data EP1-8 configuration. */\r
+ USBFS_RestoreConfig();\r
\r
- /* Enable USB block */\r
- USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB;\r
- /* Enable USB block for Standby Power Mode */\r
+ /* Restore state of USB regulator and wait until it supples stable power. */\r
+ USBFS_CR1_REG |= USBFS_backup.mode;\r
+ CyDelayUs(USBFS_WAIT_VREF_STABILITY);\r
+\r
+ /* Suspend exit sequence. */\r
+ USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND;\r
+ CyDelayUs(USBFS_WAIT_SUSPEND_DEL_DISABLE);\r
+ USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND_DEL;\r
+\r
+ #else\r
+ /* Set power active and standby mode templates: enable USB block. */\r
+ USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB;\r
USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB;\r
- /* Enable core clock */\r
+\r
+ /* Enable core clock. */\r
USBFS_USB_CLK_EN_REG |= USBFS_USB_CLK_ENABLE;\r
\r
/* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/\r
USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN;\r
- /* The reference will be available ~40us after power restored */\r
- CyDelayUs(40u);\r
- /* Return VRegulator*/\r
+\r
+ /* The reference is available ~40us after power restored. */\r
+ CyDelayUs(USBFS_WAIT_VREF_RESTORE);\r
+ /* Restore state of USB regulator and wait until it supples stable power. */\r
USBFS_CR1_REG |= USBFS_backup.mode;\r
- CyDelayUs(0u); /*~50ns delay */\r
- /* Enable USBIO */\r
+ CyDelayUs(USBFS_WAIT_VREF_STABILITY); /*~50ns delay. */\r
+\r
+ /* Enable USBIO. */\r
USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N;\r
- CyDelayUs(2u);\r
- /* Set the USBIO pull-up enable */\r
+ CyDelayUs(USBFS_WAIT_PD_PULLUP_N_ENABLE);\r
+ /* Set the USBIO pull-up enable. */\r
USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N;\r
\r
- /* Re-init Arbiter configuration for DMA transfers */\r
- #if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- /* Usb arb interrupt enable */\r
- USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;\r
- #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
- USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- /*Set cfg cmplt this rises DMA request when the full configuration is done */\r
- USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
-\r
- /* STALL_IN_OUT */\r
- CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);\r
- /* Enable the SIE with a last address */\r
+ /* Restore arbiter configuration for DMA transfers. */\r
+ #if (USBFS_EP_MANAGEMENT_DMA)\r
+ #if (USBFS_ARB_ISR_ACTIVE)\r
+ /* Enable ARB EP interrupt sources. */\r
+ USBFS_ARB_INT_EN_REG = USBFS_DEFAULT_ARB_INT_EN;\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+ /* Configure arbiter for Manual or Auto DMA operation and clear \r
+ * configuration completion. \r
+ */\r
+ USBFS_ARB_CFG_REG = USBFS_DEFAULT_ARB_CFG;\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+ /* Set EP0.CR: ACK Setup, STALL IN/OUT. */\r
+ USBFS_EP0_CR_REG = USBFS_MODE_STALL_IN_OUT;\r
+\r
+ /* Enable the USB IP to respond to USB traffic with the last address. */\r
USBFS_CR0_REG |= USBFS_CR0_ENABLE;\r
- CyDelayCycles(1u);\r
- /* Finally, Enable d+ pullup and select iomode to USB mode*/\r
- CY_SET_REG8(USBFS_USBIO_CR1_PTR, USBFS_USBIO_CR1_USBPUEN);\r
+ CyDelayCycles(USBFS_WAIT_CR0_REG_STABILITY);\r
+\r
+ /* Enable D+ pull-up and keep USB control on IO. */\r
+ USBFS_USBIO_CR1_REG = USBFS_USBIO_CR1_USBPUEN;\r
\r
- /* Restore USB register settings */\r
+ /* Restore data EP1-8 configuration. */\r
USBFS_RestoreConfig();\r
+ #endif /* (CY_PSOC4) */\r
}\r
\r
CyExitCriticalSection(enableInterrupts);\r
-/*******************************************************************************\r
-* File Name: .h\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file .h\r
+* \version 3.10\r
*\r
-* Description:\r
-* This private file provides constants and parameter values for the\r
-* USBFS Component.\r
-* Please do not use this file or its content in your project.\r
-*\r
-* Note:\r
+* \brief\r
+* This file provides private function prototypes and constants for the \r
+* USBFS component. It is not intended to be used in the user project.\r
*\r
********************************************************************************\r
-* Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2013-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#if !defined(CY_USBFS_USBFS_pvt_H)\r
#define CY_USBFS_USBFS_pvt_H\r
\r
+#include "USBFS.h"\r
+ \r
+#ifdef USBFS_ENABLE_AUDIO_CLASS\r
+ #include "USBFS_audio.h"\r
+#endif /* USBFS_ENABLE_AUDIO_CLASS */\r
+\r
+#ifdef USBFS_ENABLE_CDC_CLASS\r
+ #include "USBFS_cdc.h"\r
+#endif /* USBFS_ENABLE_CDC_CLASS */\r
+\r
+#if (USBFS_ENABLE_MIDI_CLASS)\r
+ #include "USBFS_midi.h"\r
+#endif /* (USBFS_ENABLE_MIDI_CLASS) */\r
+\r
+#if (USBFS_ENABLE_MSC_CLASS)\r
+ #include "USBFS_msc.h"\r
+#endif /* (USBFS_ENABLE_MSC_CLASS) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+ #if (CY_PSOC4)\r
+ #include <CyDMA.h>\r
+ #else\r
+ #include <CyDmac.h>\r
+ #if ((USBFS_EP_MANAGEMENT_DMA_AUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ #include "USBFS_EP_DMA_Done_isr.h"\r
+ #include "USBFS_EP8_DMA_Done_SR.h"\r
+ #include "USBFS_EP17_DMA_Done_SR.h"\r
+ #endif /* ((USBFS_EP_MANAGEMENT_DMA_AUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+ #endif /* (CY_PSOC4) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+#if (USBFS_DMA1_ACTIVE)\r
+ #include "USBFS_ep1_dma.h"\r
+ #define USBFS_EP1_DMA_CH (USBFS_ep1_dma_CHANNEL)\r
+#endif /* (USBFS_DMA1_ACTIVE) */\r
+\r
+#if (USBFS_DMA2_ACTIVE)\r
+ #include "USBFS_ep2_dma.h"\r
+ #define USBFS_EP2_DMA_CH (USBFS_ep2_dma_CHANNEL)\r
+#endif /* (USBFS_DMA2_ACTIVE) */\r
+\r
+#if (USBFS_DMA3_ACTIVE)\r
+ #include "USBFS_ep3_dma.h"\r
+ #define USBFS_EP3_DMA_CH (USBFS_ep3_dma_CHANNEL)\r
+#endif /* (USBFS_DMA3_ACTIVE) */\r
+\r
+#if (USBFS_DMA4_ACTIVE)\r
+ #include "USBFS_ep4_dma.h"\r
+ #define USBFS_EP4_DMA_CH (USBFS_ep4_dma_CHANNEL)\r
+#endif /* (USBFS_DMA4_ACTIVE) */\r
+\r
+#if (USBFS_DMA5_ACTIVE)\r
+ #include "USBFS_ep5_dma.h"\r
+ #define USBFS_EP5_DMA_CH (USBFS_ep5_dma_CHANNEL)\r
+#endif /* (USBFS_DMA5_ACTIVE) */\r
+\r
+#if (USBFS_DMA6_ACTIVE)\r
+ #include "USBFS_ep6_dma.h"\r
+ #define USBFS_EP6_DMA_CH (USBFS_ep6_dma_CHANNEL)\r
+#endif /* (USBFS_DMA6_ACTIVE) */\r
+\r
+#if (USBFS_DMA7_ACTIVE)\r
+ #include "USBFS_ep7_dma.h"\r
+ #define USBFS_EP7_DMA_CH (USBFS_ep7_dma_CHANNEL)\r
+#endif /* (USBFS_DMA7_ACTIVE) */\r
+\r
+#if (USBFS_DMA8_ACTIVE)\r
+ #include "USBFS_ep8_dma.h"\r
+ #define USBFS_EP8_DMA_CH (USBFS_ep8_dma_CHANNEL)\r
+#endif /* (USBFS_DMA8_ACTIVE) */\r
+\r
\r
/***************************************\r
* Private Variables\r
***************************************/\r
\r
-/* Generated external references for descriptors*/\r
+/* Generated external references for descriptors. */\r
extern const uint8 CYCODE USBFS_DEVICE0_DESCR[18u];\r
extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[73u];\r
extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE[1u];\r
extern const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[4u];\r
extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[2u];\r
extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[5u];\r
-extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[2u];\r
+extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[3u];\r
extern const T_USBFS_LUT CYCODE USBFS_TABLE[1u];\r
extern const uint8 CYCODE USBFS_SN_STRING_DESCRIPTOR[10];\r
extern const uint8 CYCODE USBFS_STRING_DESCRIPTORS[45u];\r
extern const uint8 CYCODE USBFS_MSOS_CONFIGURATION_DESCR[USBFS_MSOS_CONF_DESCR_LENGTH];\r
#if defined(USBFS_ENABLE_IDSN_STRING)\r
extern uint8 USBFS_idSerialNumberStringDescriptor[USBFS_IDSN_DESCR_LENGTH];\r
-#endif /* USBFS_ENABLE_IDSN_STRING */\r
+#endif /* (USBFS_ENABLE_IDSN_STRING) */\r
\r
extern volatile uint8 USBFS_interfaceNumber;\r
extern volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER];\r
-extern volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER];\r
+extern volatile uint8 USBFS_interfaceSettingLast[USBFS_MAX_INTERFACES_NUMBER];\r
extern volatile uint8 USBFS_deviceAddress;\r
extern volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER];\r
extern const uint8 CYCODE *USBFS_interfaceClass;\r
extern volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP];\r
extern volatile T_USBFS_TD USBFS_currentTD;\r
\r
-#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- extern uint8 USBFS_DmaChan[USBFS_MAX_EP];\r
- extern uint8 USBFS_DmaTd[USBFS_MAX_EP];\r
-#endif /* USBFS_EP_MM */\r
-#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- extern uint8 USBFS_DmaNextTd[USBFS_MAX_EP];\r
- extern const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP];\r
- extern volatile uint16 USBFS_inLength[USBFS_MAX_EP];\r
- extern const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];\r
- extern volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];\r
-#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+ #if (CY_PSOC4)\r
+ extern const uint8 USBFS_DmaChan[USBFS_MAX_EP];\r
+ #else\r
+ extern uint8 USBFS_DmaChan[USBFS_MAX_EP];\r
+ extern uint8 USBFS_DmaTd [USBFS_MAX_EP];\r
+ #endif /* (CY_PSOC4) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+#if (CY_PSOC4)\r
+ extern uint8 USBFS_DmaEpBurstCnt [USBFS_MAX_EP];\r
+ extern uint8 USBFS_DmaEpLastBurstEl[USBFS_MAX_EP];\r
+\r
+ extern uint8 USBFS_DmaEpBurstCntBackup [USBFS_MAX_EP];\r
+ extern uint32 USBFS_DmaEpBufferAddrBackup[USBFS_MAX_EP];\r
+ \r
+ extern const uint8 USBFS_DmaReqOut [USBFS_MAX_EP]; \r
+ extern const uint8 USBFS_DmaBurstEndOut[USBFS_MAX_EP];\r
+#else\r
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ extern uint8 USBFS_DmaNextTd[USBFS_MAX_EP];\r
+ extern volatile uint16 USBFS_inLength [USBFS_MAX_EP];\r
+ extern volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];\r
+ extern const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP];\r
+ extern const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];\r
+ #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+#endif /* CY_PSOC4 */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
\r
extern volatile uint8 USBFS_ep0Toggle;\r
extern volatile uint8 USBFS_lastPacketSize;\r
/***************************************\r
* Private Function Prototypes\r
***************************************/\r
-void USBFS_ReInitComponent(void) ;\r
-void USBFS_HandleSetup(void) ;\r
-void USBFS_HandleIN(void) ;\r
-void USBFS_HandleOUT(void) ;\r
-void USBFS_LoadEP0(void) ;\r
-uint8 USBFS_InitControlRead(void) ;\r
-uint8 USBFS_InitControlWrite(void) ;\r
-void USBFS_ControlReadDataStage(void) ;\r
-void USBFS_ControlReadStatusStage(void) ;\r
-void USBFS_ControlReadPrematureStatus(void)\r
- ;\r
-uint8 USBFS_InitControlWrite(void) ;\r
-uint8 USBFS_InitZeroLengthControlTransfer(void)\r
- ;\r
-void USBFS_ControlWriteDataStage(void) ;\r
-void USBFS_ControlWriteStatusStage(void) ;\r
-void USBFS_ControlWritePrematureStatus(void)\r
- ;\r
-uint8 USBFS_InitNoDataControlTransfer(void) ;\r
-void USBFS_NoDataControlStatusStage(void) ;\r
-void USBFS_InitializeStatusBlock(void) ;\r
+void USBFS_ReInitComponent(void) ;\r
+void USBFS_HandleSetup(void) ;\r
+void USBFS_HandleIN(void) ;\r
+void USBFS_HandleOUT(void) ;\r
+void USBFS_LoadEP0(void) ;\r
+uint8 USBFS_InitControlRead(void) ;\r
+uint8 USBFS_InitControlWrite(void) ;\r
+void USBFS_ControlReadDataStage(void) ;\r
+void USBFS_ControlReadStatusStage(void) ;\r
+void USBFS_ControlReadPrematureStatus(void) ;\r
+uint8 USBFS_InitControlWrite(void) ;\r
+uint8 USBFS_InitZeroLengthControlTransfer(void) ;\r
+void USBFS_ControlWriteDataStage(void) ;\r
+void USBFS_ControlWriteStatusStage(void) ;\r
+void USBFS_ControlWritePrematureStatus(void);\r
+uint8 USBFS_InitNoDataControlTransfer(void) ;\r
+void USBFS_NoDataControlStatusStage(void) ;\r
+void USBFS_InitializeStatusBlock(void) ;\r
void USBFS_UpdateStatusBlock(uint8 completionCode) ;\r
-uint8 USBFS_DispatchClassRqst(void) ;\r
+uint8 USBFS_DispatchClassRqst(void) ;\r
\r
void USBFS_Config(uint8 clearAltSetting) ;\r
-void USBFS_ConfigAltChanged(void) ;\r
-void USBFS_ConfigReg(void) ;\r
-\r
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)\r
- ;\r
-const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void)\r
- ;\r
-const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void)\r
- ;\r
-uint8 USBFS_ClearEndpointHalt(void) ;\r
-uint8 USBFS_SetEndpointHalt(void) ;\r
-uint8 USBFS_ValidateAlternateSetting(void) ;\r
-\r
-void USBFS_SaveConfig(void) ;\r
-void USBFS_RestoreConfig(void) ;\r
-\r
-#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) ;\r
-#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+void USBFS_ConfigAltChanged(void) ;\r
+void USBFS_ConfigReg(void) ;\r
+void USBFS_EpStateInit(void) ;\r
+\r
+\r
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex);\r
+const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) ;\r
+#if (USBFS_BOS_ENABLE)\r
+ const T_USBFS_LUT CYCODE *USBFS_GetBOSPtr(void) ;\r
+#endif /* (USBFS_BOS_ENABLE) */\r
+const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) ;uint8 USBFS_ClearEndpointHalt(void) ;\r
+uint8 USBFS_SetEndpointHalt(void) ;\r
+uint8 USBFS_ValidateAlternateSetting(void) ;\r
+\r
+void USBFS_SaveConfig(void) ;\r
+void USBFS_RestoreConfig(void) ;\r
+\r
+#if (CY_PSOC3 || CY_PSOC5LP)\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) ;\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
\r
#if defined(USBFS_ENABLE_IDSN_STRING)\r
- void USBFS_ReadDieID(uint8 descr[]) ;\r
+ void USBFS_ReadDieID(uint8 descr[]) ;\r
#endif /* USBFS_ENABLE_IDSN_STRING */\r
\r
#if defined(USBFS_ENABLE_HID_CLASS)\r
- uint8 USBFS_DispatchHIDClassRqst(void);\r
-#endif /* USBFS_ENABLE_HID_CLASS */\r
+ uint8 USBFS_DispatchHIDClassRqst(void) ;\r
+#endif /* (USBFS_ENABLE_HID_CLASS) */\r
+\r
#if defined(USBFS_ENABLE_AUDIO_CLASS)\r
- uint8 USBFS_DispatchAUDIOClassRqst(void);\r
-#endif /* USBFS_ENABLE_HID_CLASS */\r
+ uint8 USBFS_DispatchAUDIOClassRqst(void) ;\r
+#endif /* (USBFS_ENABLE_AUDIO_CLASS) */\r
+\r
#if defined(USBFS_ENABLE_CDC_CLASS)\r
- uint8 USBFS_DispatchCDCClassRqst(void);\r
-#endif /* USBFS_ENABLE_CDC_CLASS */\r
+ uint8 USBFS_DispatchCDCClassRqst(void) ;\r
+#endif /* (USBFS_ENABLE_CDC_CLASS) */\r
+\r
+#if (USBFS_ENABLE_MSC_CLASS)\r
+ #if (USBFS_HANDLE_MSC_REQUESTS)\r
+ uint8 USBFS_DispatchMSCClassRqst(void) ;\r
+ #endif /* (USBFS_HANDLE_MSC_REQUESTS) */\r
+#endif /* (USBFS_ENABLE_MSC_CLASS */\r
\r
CY_ISR_PROTO(USBFS_EP_0_ISR);\r
-#if(USBFS_EP1_ISR_REMOVE == 0u)\r
+CY_ISR_PROTO(USBFS_BUS_RESET_ISR);\r
+\r
+#if (USBFS_SOF_ISR_ACTIVE)\r
+ CY_ISR_PROTO(USBFS_SOF_ISR);\r
+#endif /* (USBFS_SOF_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP1_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_EP_1_ISR);\r
-#endif /* USBFS_EP1_ISR_REMOVE */\r
-#if(USBFS_EP2_ISR_REMOVE == 0u)\r
+#endif /* (USBFS_EP1_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP2_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_EP_2_ISR);\r
-#endif /* USBFS_EP2_ISR_REMOVE */\r
-#if(USBFS_EP3_ISR_REMOVE == 0u)\r
+#endif /* (USBFS_EP2_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP3_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_EP_3_ISR);\r
-#endif /* USBFS_EP3_ISR_REMOVE */\r
-#if(USBFS_EP4_ISR_REMOVE == 0u)\r
+#endif /* (USBFS_EP3_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP4_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_EP_4_ISR);\r
-#endif /* USBFS_EP4_ISR_REMOVE */\r
-#if(USBFS_EP5_ISR_REMOVE == 0u)\r
+#endif /* (USBFS_EP4_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP5_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_EP_5_ISR);\r
-#endif /* USBFS_EP5_ISR_REMOVE */\r
-#if(USBFS_EP6_ISR_REMOVE == 0u)\r
+#endif /* (USBFS_EP5_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP6_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_EP_6_ISR);\r
-#endif /* USBFS_EP6_ISR_REMOVE */\r
-#if(USBFS_EP7_ISR_REMOVE == 0u)\r
+#endif /* (USBFS_EP6_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP7_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_EP_7_ISR);\r
-#endif /* USBFS_EP7_ISR_REMOVE */\r
-#if(USBFS_EP8_ISR_REMOVE == 0u)\r
+#endif /* (USBFS_EP7_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP8_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_EP_8_ISR);\r
-#endif /* USBFS_EP8_ISR_REMOVE */\r
-CY_ISR_PROTO(USBFS_BUS_RESET_ISR);\r
-#if(USBFS_SOF_ISR_REMOVE == 0u)\r
- CY_ISR_PROTO(USBFS_SOF_ISR);\r
-#endif /* USBFS_SOF_ISR_REMOVE */\r
-#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
+#endif /* (USBFS_EP8_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
CY_ISR_PROTO(USBFS_ARB_ISR);\r
-#endif /* USBFS_EP_MM */\r
-#if(USBFS_DP_ISR_REMOVE == 0u)\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+#if (USBFS_DP_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_DP_ISR);\r
-#endif /* USBFS_DP_ISR_REMOVE */\r
-#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- CY_ISR_PROTO(USBFS_EP_DMA_DONE_ISR);\r
-#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+#endif /* (USBFS_DP_ISR_ACTIVE) */\r
+\r
+#if (CY_PSOC4)\r
+ CY_ISR_PROTO(USBFS_INTR_HI_ISR);\r
+ CY_ISR_PROTO(USBFS_INTR_MED_ISR);\r
+ CY_ISR_PROTO(USBFS_INTR_LO_ISR);\r
+ #if (USBFS_LPM_ACTIVE)\r
+ CY_ISR_PROTO(USBFS_LPM_ISR);\r
+ #endif /* (USBFS_LPM_ACTIVE) */\r
+#endif /* (CY_PSOC4) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+#if (CY_PSOC4)\r
+ #if (USBFS_DMA1_ACTIVE)\r
+ void USBFS_EP1_DMA_DONE_ISR(void);\r
+ #endif /* (USBFS_DMA1_ACTIVE) */\r
+\r
+ #if (USBFS_DMA2_ACTIVE)\r
+ void USBFS_EP2_DMA_DONE_ISR(void);\r
+ #endif /* (USBFS_DMA2_ACTIVE) */\r
+\r
+ #if (USBFS_DMA3_ACTIVE)\r
+ void USBFS_EP3_DMA_DONE_ISR(void);\r
+ #endif /* (USBFS_DMA3_ACTIVE) */\r
+\r
+ #if (USBFS_DMA4_ACTIVE)\r
+ void USBFS_EP4_DMA_DONE_ISR(void);\r
+ #endif /* (USBFS_DMA4_ACTIVE) */\r
+\r
+ #if (USBFS_DMA5_ACTIVE)\r
+ void USBFS_EP5_DMA_DONE_ISR(void);\r
+ #endif /* (USBFS_DMA5_ACTIVE) */\r
+\r
+ #if (USBFS_DMA6_ACTIVE)\r
+ void USBFS_EP6_DMA_DONE_ISR(void);\r
+ #endif /* (USBFS_DMA6_ACTIVE) */\r
+\r
+ #if (USBFS_DMA7_ACTIVE)\r
+ void USBFS_EP7_DMA_DONE_ISR(void);\r
+ #endif /* (USBFS_DMA7_ACTIVE) */\r
+\r
+ #if (USBFS_DMA8_ACTIVE)\r
+ void USBFS_EP8_DMA_DONE_ISR(void);\r
+ #endif /* (USBFS_DMA8_ACTIVE) */\r
+\r
+#else\r
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ CY_ISR_PROTO(USBFS_EP_DMA_DONE_ISR);\r
+ #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+#endif /* (CY_PSOC4) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+\r
\r
/***************************************\r
-* Request Handlers\r
+* Request Handlers\r
***************************************/\r
\r
uint8 USBFS_HandleStandardRqst(void) ;\r
-uint8 USBFS_DispatchClassRqst(void) ;\r
-uint8 USBFS_HandleVendorRqst(void) ;\r
+uint8 USBFS_DispatchClassRqst(void) ;\r
+uint8 USBFS_HandleVendorRqst(void) ;\r
\r
\r
/***************************************\r
***************************************/\r
\r
#if defined(USBFS_ENABLE_HID_CLASS)\r
- void USBFS_FindReport(void) ;\r
- void USBFS_FindReportDescriptor(void) ;\r
+ void USBFS_FindReport(void) ;\r
+ void USBFS_FindReportDescriptor(void) ;\r
void USBFS_FindHidClassDecriptor(void) ;\r
#endif /* USBFS_ENABLE_HID_CLASS */\r
\r
***************************************/\r
\r
#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
- void USBFS_MIDI_IN_EP_Service(void) ;\r
-#endif /* USBFS_ENABLE_MIDI_STREAMING */\r
+ void USBFS_MIDI_IN_EP_Service(void) ;\r
+#endif /* (USBFS_ENABLE_MIDI_STREAMING) */\r
+\r
+\r
+/***************************************\r
+* CDC Internal references\r
+***************************************/\r
+\r
+#if defined(USBFS_ENABLE_CDC_CLASS)\r
+\r
+ typedef struct\r
+ {\r
+ uint8 bRequestType;\r
+ uint8 bNotification;\r
+ uint8 wValue;\r
+ uint8 wValueMSB;\r
+ uint8 wIndex;\r
+ uint8 wIndexMSB;\r
+ uint8 wLength;\r
+ uint8 wLengthMSB;\r
+ uint8 wSerialState;\r
+ uint8 wSerialStateMSB;\r
+ } t_USBFS_cdc_notification;\r
+\r
+ uint8 USBFS_GetInterfaceComPort(uint8 interface) ;\r
+ uint8 USBFS_Cdc_EpInit( const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP, uint8 epNum, uint8 cdcComNums) ;\r
+\r
+ extern volatile uint8 USBFS_cdc_dataInEpList[USBFS_MAX_MULTI_COM_NUM];\r
+ extern volatile uint8 USBFS_cdc_dataOutEpList[USBFS_MAX_MULTI_COM_NUM];\r
+ extern volatile uint8 USBFS_cdc_commInEpList[USBFS_MAX_MULTI_COM_NUM];\r
+#endif /* (USBFS_ENABLE_CDC_CLASS) */\r
\r
\r
#endif /* CY_USBFS_USBFS_pvt_H */\r
-/*******************************************************************************\r
-* File Name: USBFS_std.c\r
-* Version 2.80\r
-*\r
-* Description:\r
-* USB Standard request handler.\r
+/***************************************************************************//**\r
+* \file USBFS_std.c\r
+* \version 3.10\r
*\r
-* Note:\r
+* \brief\r
+* This file contains the USB Standard request handler.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
-#include "USBFS_cdc.h"\r
#include "USBFS_pvt.h"\r
-#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
- #include "USBFS_midi.h"\r
-#endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
-\r
\r
/***************************************\r
* Static data allocation\r
***************************************/\r
\r
#if defined(USBFS_ENABLE_FWSN_STRING)\r
- static volatile uint8 *USBFS_fwSerialNumberStringDescriptor;\r
- static volatile uint8 USBFS_snStringConfirm = USBFS_FALSE;\r
-#endif /* USBFS_ENABLE_FWSN_STRING */\r
+ static volatile uint8* USBFS_fwSerialNumberStringDescriptor;\r
+ static volatile uint8 USBFS_snStringConfirm = USBFS_FALSE;\r
+#endif /* (USBFS_ENABLE_FWSN_STRING) */\r
\r
#if defined(USBFS_ENABLE_FWSN_STRING)\r
-\r
- /*******************************************************************************\r
+ /***************************************************************************\r
* Function Name: USBFS_SerialNumString\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Application firmware may supply the source of the USB device descriptors\r
- * serial number string during runtime.\r
+ ************************************************************************//**\r
*\r
- * Parameters:\r
- * snString: pointer to string.\r
+ * This function is available only when the User Call Back option in the \r
+ * Serial Number String descriptor properties is selected. Application \r
+ * firmware can provide the source of the USB device serial number string \r
+ * descriptor during run time. The default string is used if the application \r
+ * firmware does not use this function or sets the wrong string descriptor.\r
*\r
- * Return:\r
- * None.\r
+ * \param snString: Pointer to the user-defined string descriptor. The \r
+ * string descriptor should meet the Universal Serial Bus Specification \r
+ * revision 2.0 chapter 9.6.7\r
+ * Offset|Size|Value|Description\r
+ * ------|----|------|---------------------------------\r
+ * 0 |1 |N |Size of this descriptor in bytes\r
+ * 1 |1 |0x03 |STRING Descriptor Type\r
+ * 2 |N-2 |Number|UNICODE encoded string\r
+ * \r
+ * *For example:* uint8 snString[16]={0x0E,0x03,'F',0,'W',0,'S',0,'N',0,'0',0,'1',0};\r
*\r
- * Reentrant:\r
+ * \reentrant\r
* No.\r
*\r
- *******************************************************************************/\r
+ ***************************************************************************/\r
void USBFS_SerialNumString(uint8 snString[]) \r
{\r
USBFS_snStringConfirm = USBFS_FALSE;\r
- if(snString != NULL)\r
+ \r
+ if (snString != NULL)\r
{\r
/* Check descriptor validation */\r
- if( (snString[0u] > 1u ) && (snString[1u] == USBFS_DESCR_STRING) )\r
+ if ((snString[0u] > 1u) && (snString[1u] == USBFS_DESCR_STRING))\r
{\r
USBFS_fwSerialNumberStringDescriptor = snString;\r
USBFS_snStringConfirm = USBFS_TRUE;\r
}\r
}\r
}\r
-\r
#endif /* USBFS_ENABLE_FWSN_STRING */\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_HandleStandardRqst\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This Routine dispatches standard requests\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
+* \return\r
* TRUE if request handled.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 requestHandled = USBFS_FALSE;\r
uint8 interfaceNumber;\r
uint8 configurationN;\r
- #if defined(USBFS_ENABLE_STRINGS)\r
- volatile uint8 *pStr = 0u;\r
- #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS)\r
- uint8 nStr;\r
- uint8 descrLength;\r
- #endif /* USBFS_ENABLE_DESCRIPTOR_STRINGS */\r
- #endif /* USBFS_ENABLE_STRINGS */\r
+ uint8 bmRequestType = USBFS_bmRequestTypeReg;\r
+\r
+#if defined(USBFS_ENABLE_STRINGS)\r
+ volatile uint8 *pStr = 0u;\r
+ #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS)\r
+ uint8 nStr;\r
+ uint8 descrLength;\r
+ #endif /* (USBFS_ENABLE_DESCRIPTOR_STRINGS) */\r
+#endif /* (USBFS_ENABLE_STRINGS) */\r
+ \r
static volatile uint8 USBFS_tBuffer[USBFS_STATUS_LENGTH_MAX];\r
const T_USBFS_LUT CYCODE *pTmp;\r
+\r
USBFS_currentTD.count = 0u;\r
\r
- if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)\r
+ if (USBFS_RQST_DIR_D2H == (bmRequestType & USBFS_RQST_DIR_MASK))\r
{\r
/* Control Read */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_GET_DESCRIPTOR:\r
- if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_DEVICE)\r
+ if (USBFS_DESCR_DEVICE ==USBFS_wValueHiReg)\r
{\r
pTmp = USBFS_GetDeviceTablePtr();\r
USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;\r
USBFS_currentTD.count = USBFS_DEVICE_DESCR_LENGTH;\r
+ \r
requestHandled = USBFS_InitControlRead();\r
}\r
- else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_CONFIG)\r
+ else if (USBFS_DESCR_CONFIG == USBFS_wValueHiReg)\r
{\r
- pTmp = USBFS_GetConfigTablePtr(CY_GET_REG8(USBFS_wValueLo));\r
- if( pTmp != NULL ) /* Verify that requested descriptor exists */\r
+ pTmp = USBFS_GetConfigTablePtr((uint8) USBFS_wValueLoReg);\r
+ \r
+ /* Verify that requested descriptor exists */\r
+ if (pTmp != NULL)\r
{\r
USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;\r
- USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \\r
- USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \\r
- (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];\r
+ USBFS_currentTD.count = (uint16)((uint16)(USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \\r
+ (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];\r
requestHandled = USBFS_InitControlRead();\r
}\r
}\r
- #if defined(USBFS_ENABLE_STRINGS)\r
- else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_STRING)\r
+ \r
+ #if(USBFS_BOS_ENABLE)\r
+ else if (USBFS_DESCR_BOS == USBFS_wValueHiReg)\r
{\r
- /* Descriptor Strings*/\r
- #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS)\r
- nStr = 0u;\r
- pStr = (volatile uint8 *)&USBFS_STRING_DESCRIPTORS[0u];\r
- while ( (CY_GET_REG8(USBFS_wValueLo) > nStr) && (*pStr != 0u) )\r
- {\r
- /* Read descriptor length from 1st byte */\r
- descrLength = *pStr;\r
- /* Move to next string descriptor */\r
- pStr = &pStr[descrLength];\r
- nStr++;\r
- }\r
- #endif /* USBFS_ENABLE_DESCRIPTOR_STRINGS */\r
- /* Microsoft OS String*/\r
- #if defined(USBFS_ENABLE_MSOS_STRING)\r
- if( CY_GET_REG8(USBFS_wValueLo) == USBFS_STRING_MSOS )\r
+ pTmp = USBFS_GetBOSPtr();\r
+ \r
+ /* Verify that requested descriptor exists */\r
+ if (pTmp != NULL)\r
+ {\r
+ USBFS_currentTD.pData = (volatile uint8 *)pTmp;\r
+ USBFS_currentTD.count = ((uint16)((uint16)(USBFS_currentTD.pData)[USBFS_BOS_DESCR_TOTAL_LENGTH_HI] << 8u)) | \\r
+ (USBFS_currentTD.pData)[USBFS_BOS_DESCR_TOTAL_LENGTH_LOW];\r
+ requestHandled = USBFS_InitControlRead();\r
+ }\r
+ }\r
+ #endif /*(USBFS_BOS_ENABLE)*/\r
+ \r
+ #if defined(USBFS_ENABLE_STRINGS)\r
+ else if (USBFS_DESCR_STRING == USBFS_wValueHiReg)\r
+ {\r
+ /* Descriptor Strings */\r
+ #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS)\r
+ nStr = 0u;\r
+ pStr = (volatile uint8 *) &USBFS_STRING_DESCRIPTORS[0u];\r
+ \r
+ while ((USBFS_wValueLoReg > nStr) && (*pStr != 0u))\r
+ {\r
+ /* Read descriptor length from 1st byte */\r
+ descrLength = *pStr;\r
+ /* Move to next string descriptor */\r
+ pStr = &pStr[descrLength];\r
+ nStr++;\r
+ }\r
+ #endif /* (USBFS_ENABLE_DESCRIPTOR_STRINGS) */\r
+ \r
+ /* Microsoft OS String */\r
+ #if defined(USBFS_ENABLE_MSOS_STRING)\r
+ if (USBFS_STRING_MSOS == USBFS_wValueLoReg)\r
+ {\r
+ pStr = (volatile uint8 *)& USBFS_MSOS_DESCRIPTOR[0u];\r
+ }\r
+ #endif /* (USBFS_ENABLE_MSOS_STRING) */\r
+ \r
+ /* SN string */\r
+ #if defined(USBFS_ENABLE_SN_STRING)\r
+ if ((USBFS_wValueLoReg != 0u) && \r
+ (USBFS_wValueLoReg == USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]))\r
+ {\r
+ #if defined(USBFS_ENABLE_IDSN_STRING)\r
+ /* Read DIE ID and generate string descriptor in RAM */\r
+ USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor);\r
+ pStr = USBFS_idSerialNumberStringDescriptor;\r
+ #elif defined(USBFS_ENABLE_FWSN_STRING)\r
+ \r
+ if(USBFS_snStringConfirm != USBFS_FALSE)\r
{\r
- pStr = (volatile uint8 *)&USBFS_MSOS_DESCRIPTOR[0u];\r
+ pStr = USBFS_fwSerialNumberStringDescriptor;\r
}\r
- #endif /* USBFS_ENABLE_MSOS_STRING*/\r
- /* SN string */\r
- #if defined(USBFS_ENABLE_SN_STRING)\r
- if( (CY_GET_REG8(USBFS_wValueLo) != 0u) &&\r
- (CY_GET_REG8(USBFS_wValueLo) ==\r
- USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]) )\r
+ else\r
{\r
-\r
- #if defined(USBFS_ENABLE_IDSN_STRING)\r
- /* Read DIE ID and generate string descriptor in RAM */\r
- USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor);\r
- pStr = USBFS_idSerialNumberStringDescriptor;\r
- #elif defined(USBFS_ENABLE_FWSN_STRING)\r
- if(USBFS_snStringConfirm != USBFS_FALSE)\r
- {\r
- pStr = USBFS_fwSerialNumberStringDescriptor;\r
- }\r
- else\r
- {\r
- pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];\r
- }\r
- #else\r
- pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];\r
- #endif /* defined(USBFS_ENABLE_IDSN_STRING) */\r
+ pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];\r
}\r
- #endif /* USBFS_ENABLE_SN_STRING */\r
+ #else\r
+ pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];\r
+ #endif /* (USBFS_ENABLE_IDSN_STRING) */\r
+ }\r
+ #endif /* (USBFS_ENABLE_SN_STRING) */\r
+ \r
if (*pStr != 0u)\r
{\r
USBFS_currentTD.count = *pStr;\r
requestHandled = USBFS_InitControlRead();\r
}\r
}\r
- #endif /* USBFS_ENABLE_STRINGS */\r
+ #endif /* USBFS_ENABLE_STRINGS */\r
else\r
{\r
requestHandled = USBFS_DispatchClassRqst();\r
}\r
break;\r
+ \r
case USBFS_GET_STATUS:\r
- switch ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK))\r
+ switch (bmRequestType & USBFS_RQST_RCPT_MASK)\r
{\r
case USBFS_RQST_RCPT_EP:\r
USBFS_currentTD.count = USBFS_EP_STATUS_LENGTH;\r
- USBFS_tBuffer[0u] = USBFS_EP[ \\r
- CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].hwEpState;\r
- USBFS_tBuffer[1u] = 0u;\r
+ USBFS_tBuffer[0u] = USBFS_EP[USBFS_wIndexLoReg & USBFS_DIR_UNUSED].hwEpState;\r
+ USBFS_tBuffer[1u] = 0u;\r
USBFS_currentTD.pData = &USBFS_tBuffer[0u];\r
+ \r
requestHandled = USBFS_InitControlRead();\r
break;\r
case USBFS_RQST_RCPT_DEV:\r
USBFS_currentTD.count = USBFS_DEVICE_STATUS_LENGTH;\r
- USBFS_tBuffer[0u] = USBFS_deviceStatus;\r
- USBFS_tBuffer[1u] = 0u;\r
+ USBFS_tBuffer[0u] = USBFS_deviceStatus;\r
+ USBFS_tBuffer[1u] = 0u;\r
USBFS_currentTD.pData = &USBFS_tBuffer[0u];\r
+ \r
requestHandled = USBFS_InitControlRead();\r
break;\r
default: /* requestHandled is initialized as FALSE by default */\r
break;\r
}\r
break;\r
+ \r
case USBFS_GET_CONFIGURATION:\r
USBFS_currentTD.count = 1u;\r
- USBFS_currentTD.pData = (volatile uint8 *)&USBFS_configuration;\r
+ USBFS_currentTD.pData = (volatile uint8 *) &USBFS_configuration;\r
requestHandled = USBFS_InitControlRead();\r
break;\r
+ \r
case USBFS_GET_INTERFACE:\r
USBFS_currentTD.count = 1u;\r
- USBFS_currentTD.pData = (volatile uint8 *)&USBFS_interfaceSetting[ \\r
- CY_GET_REG8(USBFS_wIndexLo)];\r
+ USBFS_currentTD.pData = (volatile uint8 *) &USBFS_interfaceSetting[USBFS_wIndexLoReg];\r
requestHandled = USBFS_InitControlRead();\r
break;\r
+ \r
default: /* requestHandled is initialized as FALSE by default */\r
break;\r
}\r
}\r
- else {\r
+ else\r
+ {\r
/* Control Write */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_SET_ADDRESS:\r
- USBFS_deviceAddress = CY_GET_REG8(USBFS_wValueLo);\r
+ /* Store address to be set in USBFS_NoDataControlStatusStage(). */\r
+ USBFS_deviceAddress = (uint8) USBFS_wValueLoReg;\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
break;\r
+ \r
case USBFS_SET_CONFIGURATION:\r
- configurationN = CY_GET_REG8(USBFS_wValueLo);\r
+ configurationN = USBFS_wValueLoReg;\r
+ \r
+ /* Verify that configuration descriptor exists */\r
if(configurationN > 0u)\r
- { /* Verify that configuration descriptor exists */\r
- pTmp = USBFS_GetConfigTablePtr(configurationN - 1u);\r
+ {\r
+ pTmp = USBFS_GetConfigTablePtr((uint8) configurationN - 1u);\r
}\r
+ \r
/* Responds with a Request Error when configuration number is invalid */\r
if (((configurationN > 0u) && (pTmp != NULL)) || (configurationN == 0u))\r
{\r
/* Set new configuration if it has been changed */\r
if(configurationN != USBFS_configuration)\r
{\r
- USBFS_configuration = configurationN;\r
+ USBFS_configuration = (uint8) configurationN;\r
USBFS_configurationChanged = USBFS_TRUE;\r
USBFS_Config(USBFS_TRUE);\r
}\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
}\r
break;\r
+ \r
case USBFS_SET_INTERFACE:\r
- if (USBFS_ValidateAlternateSetting() != 0u)\r
+ if (0u != USBFS_ValidateAlternateSetting())\r
{\r
- interfaceNumber = CY_GET_REG8(USBFS_wIndexLo);\r
- USBFS_interfaceNumber = interfaceNumber;\r
- USBFS_configurationChanged = USBFS_TRUE;\r
- #if ((USBFS_EP_MA == USBFS__MA_DYNAMIC) && \\r
- (USBFS_EP_MM == USBFS__EP_MANUAL) )\r
+ /* Get interface number from the request. */\r
+ interfaceNumber = USBFS_wIndexLoReg;\r
+ USBFS_interfaceNumber = (uint8) USBFS_wIndexLoReg;\r
+ \r
+ /* Check if alternate settings is changed for interface. */\r
+ if (USBFS_interfaceSettingLast[interfaceNumber] != USBFS_interfaceSetting[interfaceNumber])\r
+ {\r
+ USBFS_configurationChanged = USBFS_TRUE;\r
+ \r
+ /* Change alternate setting for the endpoints. */\r
+ #if (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC)\r
USBFS_Config(USBFS_FALSE);\r
#else\r
USBFS_ConfigAltChanged();\r
- #endif /* (USBFS_EP_MA == USBFS__MA_DYNAMIC) */\r
- /* Update handled Alt setting changes status */\r
- USBFS_interfaceSetting_last[interfaceNumber] =\r
- USBFS_interfaceSetting[interfaceNumber];\r
+ #endif /* (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC) */\r
+ }\r
+ \r
requestHandled = USBFS_InitNoDataControlTransfer();\r
}\r
break;\r
+ \r
case USBFS_CLEAR_FEATURE:\r
- switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK)\r
+ switch (bmRequestType & USBFS_RQST_RCPT_MASK)\r
{\r
case USBFS_RQST_RCPT_EP:\r
- if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT)\r
+ if (USBFS_wValueLoReg == USBFS_ENDPOINT_HALT)\r
{\r
requestHandled = USBFS_ClearEndpointHalt();\r
}\r
break;\r
case USBFS_RQST_RCPT_DEV:\r
/* Clear device REMOTE_WAKEUP */\r
- if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP)\r
+ if (USBFS_wValueLoReg == USBFS_DEVICE_REMOTE_WAKEUP)\r
{\r
USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_REMOTE_WAKEUP;\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
break;\r
case USBFS_RQST_RCPT_IFC:\r
/* Validate interfaceNumber */\r
- if (CY_GET_REG8(USBFS_wIndexLo) < USBFS_MAX_INTERFACES_NUMBER)\r
+ if (USBFS_wIndexLoReg < USBFS_MAX_INTERFACES_NUMBER)\r
{\r
- USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &=\r
- (uint8)~(CY_GET_REG8(USBFS_wValueLo));\r
+ USBFS_interfaceStatus[USBFS_wIndexLoReg] &= (uint8) ~USBFS_wValueLoReg;\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
}\r
break;\r
break;\r
}\r
break;\r
+ \r
case USBFS_SET_FEATURE:\r
- switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK)\r
+ switch (bmRequestType & USBFS_RQST_RCPT_MASK)\r
{\r
case USBFS_RQST_RCPT_EP:\r
- if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT)\r
+ if (USBFS_wValueLoReg == USBFS_ENDPOINT_HALT)\r
{\r
requestHandled = USBFS_SetEndpointHalt();\r
}\r
break;\r
+ \r
case USBFS_RQST_RCPT_DEV:\r
/* Set device REMOTE_WAKEUP */\r
- if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP)\r
+ if (USBFS_wValueLoReg == USBFS_DEVICE_REMOTE_WAKEUP)\r
{\r
USBFS_deviceStatus |= USBFS_DEVICE_STATUS_REMOTE_WAKEUP;\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
}\r
break;\r
+ \r
case USBFS_RQST_RCPT_IFC:\r
/* Validate interfaceNumber */\r
- if (CY_GET_REG8(USBFS_wIndexLo) < USBFS_MAX_INTERFACES_NUMBER)\r
+ if (USBFS_wIndexLoReg < USBFS_MAX_INTERFACES_NUMBER)\r
{\r
- USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &=\r
- (uint8)~(CY_GET_REG8(USBFS_wValueLo));\r
+ USBFS_interfaceStatus[USBFS_wIndexLoReg] &= (uint8) ~USBFS_wValueLoReg;\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
}\r
break;\r
+ \r
default: /* requestHandled is initialized as FALSE by default */\r
break;\r
}\r
break;\r
+ \r
default: /* requestHandled is initialized as FALSE by default */\r
break;\r
}\r
}\r
- return(requestHandled);\r
+ \r
+ return (requestHandled);\r
}\r
\r
\r
#if defined(USBFS_ENABLE_IDSN_STRING)\r
-\r
/***************************************************************************\r
* Function Name: USBFS_ReadDieID\r
- ****************************************************************************\r
+ ************************************************************************//**\r
*\r
- * Summary:\r
* This routine read Die ID and generate Serial Number string descriptor.\r
*\r
- * Parameters:\r
- * descr: pointer on string descriptor.\r
+ * \param descr: pointer on string descriptor. This string size has to be equal or\r
+ * greater than USBFS_IDSN_DESCR_LENGTH.\r
*\r
- * Return:\r
- * None.\r
*\r
- * Reentrant:\r
+ * \reentrant\r
* No.\r
*\r
***************************************************************************/\r
void USBFS_ReadDieID(uint8 descr[]) \r
{\r
+ const char8 CYCODE hex[] = "0123456789ABCDEF";\r
uint8 i;\r
uint8 j = 0u;\r
- uint8 value;\r
- const char8 CYCODE hex[16u] = "0123456789ABCDEF";\r
+ uint8 uniqueId[8u];\r
\r
- /* Check descriptor validation */\r
- if( descr != NULL)\r
+ if (NULL != descr)\r
{\r
+ /* Initialize descriptor header. */\r
descr[0u] = USBFS_IDSN_DESCR_LENGTH;\r
descr[1u] = USBFS_DESCR_STRING;\r
+ \r
+ /* Unique ID size is 8 bytes. */\r
+ CyGetUniqueId((uint32 *) uniqueId);\r
\r
- /* fill descriptor */\r
- for(i = 2u; i < USBFS_IDSN_DESCR_LENGTH; i += 4u)\r
+ /* Fill descriptor with unique device ID. */\r
+ for (i = 2u; i < USBFS_IDSN_DESCR_LENGTH; i += 4u)\r
{\r
- value = CY_GET_XTND_REG8((void CYFAR *)(USBFS_DIE_ID + j));\r
- j++;\r
- descr[i] = (uint8)hex[value >> 4u];\r
- descr[i + 2u] = (uint8)hex[value & 0x0Fu];\r
+ descr[i] = (uint8) hex[(uniqueId[j] >> 4u)];\r
+ descr[i + 1u] = 0u;\r
+ descr[i + 2u] = (uint8) hex[(uniqueId[j] & 0x0Fu)];\r
+ descr[i + 3u] = 0u;\r
+ ++j;\r
}\r
}\r
}\r
-\r
-#endif /* USBFS_ENABLE_IDSN_STRING */\r
+#endif /* (USBFS_ENABLE_IDSN_STRING) */\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ConfigReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine configures hardware registers from the variables.\r
* It is called from USBFS_Config() function and from RestoreConfig\r
* after Wakeup.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
*******************************************************************************/\r
void USBFS_ConfigReg(void) \r
{\r
uint8 ep;\r
- uint8 i;\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- uint8 epType = 0u;\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
\r
- /* Set the endpoint buffer addresses */\r
- ep = USBFS_EP1;\r
- for (i = 0u; i < 0x80u; i+= 0x10u)\r
- {\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_DEFAULT);\r
- #if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- /* Enable all Arbiter EP Interrupts : err, buf under, buf over, dma gnt(mode2 only), in buf full */\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_INT_EN_IND + i), USBFS_ARB_EPX_INT_MASK);\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
+#if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ uint8 epType = 0u;\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
\r
- if(USBFS_EP[ep].epMode != USBFS_MODE_DISABLE)\r
+ /* Go thought all endpoints and set hardware configuration */\r
+ for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ++ep)\r
+ {\r
+ USBFS_ARB_EP_BASE.arbEp[ep].epCfg = USBFS_ARB_EPX_CFG_DEFAULT;\r
+ \r
+ #if (USBFS_EP_MANAGEMENT_DMA)\r
+ /* Enable arbiter endpoint interrupt sources */\r
+ USBFS_ARB_EP_BASE.arbEp[ep].epIntEn = USBFS_ARB_EPX_INT_MASK;\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+ \r
+ if (USBFS_EP[ep].epMode != USBFS_MODE_DISABLE)\r
{\r
- if((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u )\r
+ if (0u != (USBFS_EP[ep].addr & USBFS_DIR_IN))\r
{\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_IN);\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_IN;\r
+ \r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO && CY_PSOC4)\r
+ /* Clear DMA_TERMIN for IN endpoint. */\r
+ USBFS_ARB_EP_BASE.arbEp[ep].epIntEn &= (uint32) ~USBFS_ARB_EPX_INT_DMA_TERMIN;\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && CY_PSOC4) */\r
}\r
else\r
{\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_OUT);\r
- /* Prepare EP type mask for automatic memory allocation */\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- epType |= (uint8)(0x01u << (ep - USBFS_EP1));\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_OUT;\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* (CY_PSOC4): DMA_TERMIN for OUT endpoint is set above. */\r
+ \r
+ /* Prepare endpoint type mask. */\r
+ epType |= (uint8) (0x01u << (ep - USBFS_EP1));\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
}\r
}\r
else\r
{\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_STALL_DATA_EP);\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_STALL_DATA_EP;\r
}\r
+ \r
+ #if (!USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ #if (CY_PSOC4)\r
+ USBFS_ARB_EP16_BASE.arbEp[ep].rwRa16 = (uint32) USBFS_EP[ep].buffOffset;\r
+ USBFS_ARB_EP16_BASE.arbEp[ep].rwWa16 = (uint32) USBFS_EP[ep].buffOffset;\r
+ #else\r
+ USBFS_ARB_EP_BASE.arbEp[ep].rwRa = LO8(USBFS_EP[ep].buffOffset);\r
+ USBFS_ARB_EP_BASE.arbEp[ep].rwRaMsb = HI8(USBFS_EP[ep].buffOffset);\r
+ USBFS_ARB_EP_BASE.arbEp[ep].rwWa = LO8(USBFS_EP[ep].buffOffset);\r
+ USBFS_ARB_EP_BASE.arbEp[ep].rwWaMsb = HI8(USBFS_EP[ep].buffOffset);\r
+ #endif /* (CY_PSOC4) */\r
+ #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ }\r
\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + i), USBFS_EP[ep].bufferSize >> 8u);\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + i), USBFS_EP[ep].bufferSize & 0xFFu);\r
+#if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* BUF_SIZE depend on DMA_THRESS value:0x55-32 bytes 0x44-16 bytes 0x33-8 bytes 0x22-4 bytes 0x11-2 bytes */\r
+ USBFS_BUF_SIZE_REG = USBFS_DMA_BUF_SIZE;\r
+\r
+ /* Configure DMA burst threshold */\r
+#if (CY_PSOC4)\r
+ USBFS_DMA_THRES16_REG = USBFS_DMA_BYTES_PER_BURST;\r
+#else\r
+ USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST;\r
+ USBFS_DMA_THRES_MSB_REG = 0u;\r
+#endif /* (CY_PSOC4) */\r
+ USBFS_EP_ACTIVE_REG = USBFS_DEFAULT_ARB_INT_EN;\r
+ USBFS_EP_TYPE_REG = epType;\r
+ \r
+ /* Cfg_cmp bit set to 1 once configuration is complete. */\r
+ /* Lock arbiter configtuation */\r
+ USBFS_ARB_CFG_REG |= (uint8) USBFS_ARB_CFG_CFG_CMP;\r
+ /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */\r
+ USBFS_ARB_CFG_REG &= (uint8) ~USBFS_ARB_CFG_CFG_CMP;\r
+\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+\r
+ /* Enable interrupt SIE interurpt source from EP0-EP1 */\r
+ USBFS_SIE_EP_INT_EN_REG = (uint8) USBFS_DEFAULT_SIE_EP_INT_EN;\r
+}\r
\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu);\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu);\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);\r
- #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
\r
- ep++;\r
- }\r
+/*******************************************************************************\r
+* Function Name: USBFS_EpStateInit\r
+****************************************************************************//**\r
+*\r
+* This routine initialize state of Data end points based of its type: \r
+* IN - USBFS_IN_BUFFER_EMPTY (USBFS_EVENT_PENDING)\r
+* OUT - USBFS_OUT_BUFFER_EMPTY (USBFS_NO_EVENT_PENDING)\r
+*\r
+*******************************************************************************/\r
+void USBFS_EpStateInit(void) \r
+{\r
+ uint8 i;\r
\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- /* BUF_SIZE depend on DMA_THRESS value: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */\r
- USBFS_BUF_SIZE_REG = USBFS_DMA_BUF_SIZE;\r
- USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST; /* DMA burst threshold */\r
- USBFS_DMA_THRES_MSB_REG = 0u;\r
- USBFS_EP_ACTIVE_REG = USBFS_ARB_INT_MASK;\r
- USBFS_EP_TYPE_REG = epType;\r
- /* Cfg_cmp bit set to 1 once configuration is complete. */\r
- USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM |\r
- USBFS_ARB_CFG_CFG_CPM;\r
- /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */\r
- USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
-\r
- CY_SET_REG8(USBFS_SIE_EP_INT_EN_PTR, 0xFFu);\r
+ for (i = USBFS_EP1; i < USBFS_MAX_EP; i++)\r
+ { \r
+ if (0u != (USBFS_EP[i].addr & USBFS_DIR_IN))\r
+ {\r
+ /* IN Endpoint */\r
+ USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING;\r
+ }\r
+ else\r
+ {\r
+ /* OUT Endpoint */\r
+ USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING;\r
+ }\r
+ }\r
+ \r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Config\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine configures endpoints for the entire configuration by scanning\r
* the configuration descriptor.\r
*\r
-* Parameters:\r
-* clearAltSetting: It configures the bAlternateSetting 0 for each interface.\r
-*\r
-* Return:\r
-* None.\r
+* \param clearAltSetting: It configures the bAlternateSetting 0 for each interface.\r
*\r
* USBFS_interfaceClass - Initialized class array for each interface.\r
* It is used for handling Class specific requests depend on interface class.\r
* Different classes in multiple Alternate settings does not supported.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_Config(uint8 clearAltSetting) \r
{\r
uint8 ep;\r
- uint8 cur_ep;\r
+ uint8 curEp;\r
uint8 i;\r
uint8 epType;\r
const uint8 *pDescr;\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
+ \r
+ #if (!USBFS_EP_MANAGEMENT_DMA_AUTO)\r
uint16 buffCount = 0u;\r
- #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
\r
const T_USBFS_LUT CYCODE *pTmp;\r
const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP;\r
\r
- /* Clear all of the endpoints */\r
- for (ep = 0u; ep < USBFS_MAX_EP; ep++)\r
+ /* Clear endpoints settings */\r
+ for (ep = 0u; ep < USBFS_MAX_EP; ++ep)\r
{\r
- USBFS_EP[ep].attrib = 0u;\r
- USBFS_EP[ep].hwEpState = 0u;\r
- USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING;\r
- USBFS_EP[ep].epToggle = 0u;\r
- USBFS_EP[ep].epMode = USBFS_MODE_DISABLE;\r
+ USBFS_EP[ep].attrib = 0u;\r
+ USBFS_EP[ep].hwEpState = 0u;\r
+ USBFS_EP[ep].epToggle = 0u;\r
USBFS_EP[ep].bufferSize = 0u;\r
- USBFS_EP[ep].interface = 0u;\r
-\r
+ USBFS_EP[ep].interface = 0u;\r
+ USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING;\r
+ USBFS_EP[ep].epMode = USBFS_MODE_DISABLE; \r
}\r
\r
- /* Clear Alternate settings for all interfaces */\r
- if(clearAltSetting != 0u)\r
+ /* Clear Alternate settings for all interfaces. */\r
+ if (0u != clearAltSetting)\r
{\r
- for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++)\r
+ for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; ++i)\r
{\r
- USBFS_interfaceSetting[i] = 0x00u;\r
- USBFS_interfaceSetting_last[i] = 0x00u;\r
+ USBFS_interfaceSetting[i] = 0u;\r
+ USBFS_interfaceSettingLast[i] = 0u;\r
}\r
}\r
\r
/* Init Endpoints and Device Status if configured */\r
- if(USBFS_configuration > 0u)\r
+ if (USBFS_configuration > 0u)\r
{\r
+ #if defined(USBFS_ENABLE_CDC_CLASS)\r
+ uint8 cdcComNums = 0u;\r
+ #endif /* (USBFS_ENABLE_CDC_CLASS) */ \r
+\r
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);\r
+ \r
/* Set Power status for current configuration */\r
pDescr = (const uint8 *)pTmp->p_list;\r
- if((pDescr[USBFS_CONFIG_DESCR_ATTRIB] & USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED) != 0u)\r
+ if ((pDescr[USBFS_CONFIG_DESCR_ATTRIB] & USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED) != 0u)\r
{\r
- USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED;\r
+ USBFS_deviceStatus |= (uint8) USBFS_DEVICE_STATUS_SELF_POWERED;\r
}\r
else\r
{\r
- USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_SELF_POWERED;\r
+ USBFS_deviceStatus &= (uint8) ~USBFS_DEVICE_STATUS_SELF_POWERED;\r
}\r
+ \r
/* Move to next element */\r
pTmp = &pTmp[1u];\r
ep = pTmp->c; /* For this table, c is the number of endpoints configurations */\r
\r
- #if ((USBFS_EP_MA == USBFS__MA_DYNAMIC) && \\r
- (USBFS_EP_MM == USBFS__EP_MANUAL) )\r
+ #if (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC)\r
/* Configure for dynamic EP memory allocation */\r
/* p_list points the endpoint setting table. */\r
pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list;\r
+ \r
for (i = 0u; i < ep; i++)\r
- {\r
+ { \r
/* Compare current Alternate setting with EP Alt */\r
- if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)\r
- {\r
- cur_ep = pEP->addr & USBFS_DIR_UNUSED;\r
+ if (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)\r
+ { \r
+ curEp = pEP->addr & USBFS_DIR_UNUSED;\r
epType = pEP->attributes & USBFS_EP_TYPE_MASK;\r
- if (pEP->addr & USBFS_DIR_IN)\r
+ \r
+ USBFS_EP[curEp].addr = pEP->addr;\r
+ USBFS_EP[curEp].attrib = pEP->attributes;\r
+ USBFS_EP[curEp].bufferSize = pEP->bufferSize;\r
+\r
+ if (0u != (pEP->addr & USBFS_DIR_IN))\r
{\r
/* IN Endpoint */\r
- USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;\r
- USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
- USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;\r
- #if defined(USBFS_ENABLE_CDC_CLASS)\r
- if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||\r
- (pEP->bMisc == USBFS_CLASS_CDC)) &&\r
- (epType != USBFS_EP_TYPE_INT))\r
- {\r
- USBFS_cdc_data_in_ep = cur_ep;\r
- }\r
- #endif /* USBFS_ENABLE_CDC_CLASS*/\r
- #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
- (USBFS_MIDI_IN_BUFF_SIZE > 0) )\r
- if((pEP->bMisc == USBFS_CLASS_AUDIO) &&\r
- (epType == USBFS_EP_TYPE_BULK))\r
- {\r
- USBFS_midi_in_ep = cur_ep;\r
- }\r
- #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
+ USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType);\r
+ USBFS_EP[curEp].apiEpState = USBFS_EVENT_PENDING;\r
+ \r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_IN_BUFF_SIZE > 0))\r
+ if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK))\r
+ {\r
+ USBFS_midi_in_ep = curEp;\r
+ }\r
+ #endif /* (USBFS_ENABLE_MIDI_STREAMING) */\r
}\r
else\r
{\r
/* OUT Endpoint */\r
- USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;\r
- USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
- USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;\r
- #if defined(USBFS_ENABLE_CDC_CLASS)\r
- if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||\r
- (pEP->bMisc == USBFS_CLASS_CDC)) &&\r
- (epType != USBFS_EP_TYPE_INT))\r
- {\r
- USBFS_cdc_data_out_ep = cur_ep;\r
- }\r
- #endif /* USBFS_ENABLE_CDC_CLASS*/\r
- #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
- (USBFS_MIDI_OUT_BUFF_SIZE > 0) )\r
- if((pEP->bMisc == USBFS_CLASS_AUDIO) &&\r
- (epType == USBFS_EP_TYPE_BULK))\r
- {\r
- USBFS_midi_out_ep = cur_ep;\r
- }\r
- #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
+ USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType);\r
+ USBFS_EP[curEp].apiEpState = USBFS_NO_EVENT_PENDING;\r
+ \r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_OUT_BUFF_SIZE > 0))\r
+ if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK))\r
+ {\r
+ USBFS_midi_out_ep = curEp;\r
+ }\r
+ #endif /* (USBFS_ENABLE_MIDI_STREAMING) */\r
+ }\r
+\r
+ #if(defined (USBFS_ENABLE_CDC_CLASS))\r
+ if((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||(pEP->bMisc == USBFS_CLASS_CDC))\r
+ {\r
+ cdcComNums = USBFS_Cdc_EpInit(pEP, curEp, cdcComNums);\r
}\r
- USBFS_EP[cur_ep].bufferSize = pEP->bufferSize;\r
- USBFS_EP[cur_ep].addr = pEP->addr;\r
- USBFS_EP[cur_ep].attrib = pEP->attributes;\r
+ #endif /* (USBFS_ENABLE_CDC_CLASS) */\r
}\r
+ \r
pEP = &pEP[1u];\r
}\r
- #else /* Configure for static EP memory allocation */\r
- for (i = USBFS_EP1; i < USBFS_MAX_EP; i++)\r
+ \r
+ #else\r
+ for (i = USBFS_EP1; i < USBFS_MAX_EP; ++i)\r
{\r
/* p_list points the endpoint setting table. */\r
pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list;\r
/* Find max length for each EP and select it (length could be different in different Alt settings) */\r
/* but other settings should be correct with regards to Interface alt Setting */\r
- for (cur_ep = 0u; cur_ep < ep; cur_ep++)\r
+ \r
+ for (curEp = 0u; curEp < ep; ++curEp)\r
{\r
- /* EP count is equal to EP # in table and we found larger EP length than have before*/\r
- if(i == (pEP->addr & USBFS_DIR_UNUSED))\r
+ if (i == (pEP->addr & USBFS_DIR_UNUSED))\r
{\r
- if(USBFS_EP[i].bufferSize < pEP->bufferSize)\r
+ /* Compare endpoint buffers size with current size to find greater. */\r
+ if (USBFS_EP[i].bufferSize < pEP->bufferSize)\r
{\r
USBFS_EP[i].bufferSize = pEP->bufferSize;\r
}\r
- /* Compare current Alternate setting with EP Alt*/\r
- if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)\r
- {\r
+ \r
+ /* Compare current Alternate setting with EP Alt */\r
+ if (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)\r
+ { \r
+ USBFS_EP[i].addr = pEP->addr;\r
+ USBFS_EP[i].attrib = pEP->attributes;\r
+ \r
epType = pEP->attributes & USBFS_EP_TYPE_MASK;\r
- if ((pEP->addr & USBFS_DIR_IN) != 0u)\r
+ \r
+ if (0u != (pEP->addr & USBFS_DIR_IN))\r
{\r
/* IN Endpoint */\r
+ USBFS_EP[i].epMode = USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType);\r
USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING;\r
- USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
- USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;\r
- /* Find and initialize CDC IN endpoint number */\r
- #if defined(USBFS_ENABLE_CDC_CLASS)\r
- if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||\r
- (pEP->bMisc == USBFS_CLASS_CDC)) &&\r
- (epType != USBFS_EP_TYPE_INT))\r
- {\r
- USBFS_cdc_data_in_ep = i;\r
- }\r
- #endif /* USBFS_ENABLE_CDC_CLASS*/\r
- #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
- (USBFS_MIDI_IN_BUFF_SIZE > 0) )\r
- if((pEP->bMisc == USBFS_CLASS_AUDIO) &&\r
- (epType == USBFS_EP_TYPE_BULK))\r
- {\r
- USBFS_midi_in_ep = i;\r
- }\r
- #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
+ \r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_IN_BUFF_SIZE > 0))\r
+ if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK))\r
+ {\r
+ USBFS_midi_in_ep = i;\r
+ }\r
+ #endif /* (USBFS_ENABLE_MIDI_STREAMING) */\r
}\r
else\r
{\r
/* OUT Endpoint */\r
+ USBFS_EP[i].epMode = USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType);\r
USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING;\r
- USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
- USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;\r
- /* Find and initialize CDC IN endpoint number */\r
- #if defined(USBFS_ENABLE_CDC_CLASS)\r
- if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||\r
- (pEP->bMisc == USBFS_CLASS_CDC)) &&\r
- (epType != USBFS_EP_TYPE_INT))\r
- {\r
- USBFS_cdc_data_out_ep = i;\r
- }\r
- #endif /* USBFS_ENABLE_CDC_CLASS*/\r
- #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
- (USBFS_MIDI_OUT_BUFF_SIZE > 0) )\r
- if((pEP->bMisc == USBFS_CLASS_AUDIO) &&\r
- (epType == USBFS_EP_TYPE_BULK))\r
- {\r
- USBFS_midi_out_ep = i;\r
- }\r
- #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
+ \r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_OUT_BUFF_SIZE > 0))\r
+ if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK))\r
+ {\r
+ USBFS_midi_out_ep = i;\r
+ }\r
+ #endif /* (USBFS_ENABLE_MIDI_STREAMING) */\r
}\r
- USBFS_EP[i].addr = pEP->addr;\r
- USBFS_EP[i].attrib = pEP->attributes;\r
\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- break; /* use first EP setting in Auto memory managment */\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #if (defined(USBFS_ENABLE_CDC_CLASS))\r
+ if((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||(pEP->bMisc == USBFS_CLASS_CDC))\r
+ {\r
+ cdcComNums = USBFS_Cdc_EpInit(pEP, i, cdcComNums);\r
+ }\r
+ #endif /* (USBFS_ENABLE_CDC_CLASS) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ break; /* Use first EP setting in Auto memory management */\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
}\r
}\r
+ \r
pEP = &pEP[1u];\r
}\r
}\r
- #endif /* (USBFS_EP_MA == USBFS__MA_DYNAMIC) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC) */\r
\r
/* Init class array for each interface and interface number for each EP.\r
* It is used for handling Class specific requests directed to either an\r
pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list;\r
for (i = 0u; i < ep; i++)\r
{\r
- /* Configure interface number for each EP*/\r
+ /* Configure interface number for each EP */\r
USBFS_EP[pEP->addr & USBFS_DIR_UNUSED].interface = pEP->interface;\r
pEP = &pEP[1u];\r
}\r
- /* Init pointer on interface class table*/\r
+ \r
+ /* Init pointer on interface class table */\r
USBFS_interfaceClass = USBFS_GetInterfaceClassTablePtr();\r
- /* Set the endpoint buffer addresses */\r
-\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ep++)\r
- {\r
- USBFS_EP[ep].buffOffset = buffCount;\r
- buffCount += USBFS_EP[ep].bufferSize;\r
- }\r
- #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ \r
+ /* Set the endpoint buffer addresses */\r
+ #if (!USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ buffCount = 0u;\r
+ for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ++ep)\r
+ {\r
+ USBFS_EP[ep].buffOffset = buffCount; \r
+ buffCount += USBFS_EP[ep].bufferSize;\r
+ \r
+ #if (USBFS_GEN_16BITS_EP_ACCESS)\r
+ /* Align EP buffers to be event size to access 16-bits DR register. */\r
+ buffCount += (0u != (buffCount & 0x01u)) ? 1u : 0u;\r
+ #endif /* (USBFS_GEN_16BITS_EP_ACCESS) */ \r
+ }\r
+ #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
\r
/* Configure hardware registers */\r
USBFS_ConfigReg();\r
- } /* USBFS_configuration > 0 */\r
+ }\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ConfigAltChanged\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine update configuration for the required endpoints only.\r
* It is called after SET_INTERFACE request when Static memory allocation used.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_ConfigAltChanged(void) \r
{\r
uint8 ep;\r
- uint8 cur_ep;\r
- uint8 i;\r
+ uint8 curEp;\r
uint8 epType;\r
- uint8 ri;\r
+ uint8 i;\r
+ uint8 interfaceNum;\r
\r
const T_USBFS_LUT CYCODE *pTmp;\r
const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP;\r
\r
-\r
/* Init Endpoints and Device Status if configured */\r
- if(USBFS_configuration > 0u)\r
+ if (USBFS_configuration > 0u)\r
{\r
+ /* Get number of endpoints configurations (ep). */\r
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);\r
pTmp = &pTmp[1u];\r
- ep = pTmp->c; /* For this table, c is the number of endpoints configurations */\r
+ ep = pTmp->c;\r
\r
- /* Do not touch EP which doesn't need reconfiguration */\r
- /* When Alt setting changed, the only required endpoints need to be reconfigured */\r
- /* p_list points the endpoint setting table. */\r
+ /* Get pointer to endpoints setting table (pEP). */\r
pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list;\r
+ \r
+ /* Look through all possible endpoint configurations. Find endpoints \r
+ * which belong to current interface and alternate settings for \r
+ * re-configuration.\r
+ */\r
+ interfaceNum = USBFS_interfaceNumber;\r
for (i = 0u; i < ep; i++)\r
{\r
- /*If Alt setting changed and new is same with EP Alt */\r
- if((USBFS_interfaceSetting[pEP->interface] !=\r
- USBFS_interfaceSetting_last[pEP->interface] ) &&\r
- (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) &&\r
- (pEP->interface == CY_GET_REG8(USBFS_wIndexLo)))\r
+ /* Find endpoints which belong to current interface and alternate settings. */\r
+ if ((interfaceNum == pEP->interface) && \r
+ (USBFS_interfaceSetting[interfaceNum] == pEP->altSetting))\r
{\r
- cur_ep = pEP->addr & USBFS_DIR_UNUSED;\r
- ri = ((cur_ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
- epType = pEP->attributes & USBFS_EP_TYPE_MASK;\r
- if ((pEP->addr & USBFS_DIR_IN) != 0u)\r
+ curEp = ((uint8) pEP->addr & USBFS_DIR_UNUSED);\r
+ epType = ((uint8) pEP->attributes & USBFS_EP_TYPE_MASK);\r
+ \r
+ /* Change the SIE mode for the selected EP to NAK ALL */\r
+ USBFS_EP[curEp].epToggle = 0u;\r
+ USBFS_EP[curEp].addr = pEP->addr;\r
+ USBFS_EP[curEp].attrib = pEP->attributes;\r
+ USBFS_EP[curEp].bufferSize = pEP->bufferSize;\r
+\r
+ if (0u != (pEP->addr & USBFS_DIR_IN))\r
{\r
/* IN Endpoint */\r
- USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;\r
- USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
- USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;\r
+ USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType);\r
+ USBFS_EP[curEp].apiEpState = USBFS_EVENT_PENDING;\r
}\r
else\r
{\r
/* OUT Endpoint */\r
- USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;\r
- USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
- USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;\r
+ USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType);\r
+ USBFS_EP[curEp].apiEpState = USBFS_NO_EVENT_PENDING;\r
}\r
- /* Change the SIE mode for the selected EP to NAK ALL */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN_OUT);\r
- USBFS_EP[cur_ep].bufferSize = pEP->bufferSize;\r
- USBFS_EP[cur_ep].addr = pEP->addr;\r
- USBFS_EP[cur_ep].attrib = pEP->attributes;\r
-\r
- /* Clear the data toggle */\r
- USBFS_EP[cur_ep].epToggle = 0u;\r
-\r
- /* Dynamic reconfiguration for mode 3 transfer */\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- /* In_data_rdy for selected EP should be set to 0 */\r
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
-\r
- /* write the EP number for which reconfiguration is required */\r
- USBFS_DYN_RECONFIG_REG = (cur_ep - USBFS_EP1) <<\r
- USBFS_DYN_RECONFIG_EP_SHIFT;\r
- /* Set the dyn_config_en bit in dynamic reconfiguration register */\r
+ \r
+ /* Make SIE to NAK any endpoint requests */\r
+ USBFS_SIE_EP_BASE.sieEp[curEp].epCr0 = USBFS_MODE_NAK_IN_OUT;\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Clear IN data ready. */\r
+ USBFS_ARB_EP_BASE.arbEp[curEp].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+\r
+ /* Select endpoint number of reconfiguration */\r
+ USBFS_DYN_RECONFIG_REG = (uint8) ((curEp - 1u) << USBFS_DYN_RECONFIG_EP_SHIFT);\r
+ \r
+ /* Request for dynamic re-configuration of endpoint. */\r
USBFS_DYN_RECONFIG_REG |= USBFS_DYN_RECONFIG_ENABLE;\r
- /* wait for the dyn_config_rdy bit to set by the block,\r
- * this bit will be set to 1 when block is ready for reconfiguration.\r
- */\r
- while((USBFS_DYN_RECONFIG_REG & USBFS_DYN_RECONFIG_RDY_STS) == 0u)\r
+ \r
+ /* Wait until block is ready for re-configuration */\r
+ while (0u == (USBFS_DYN_RECONFIG_REG & USBFS_DYN_RECONFIG_RDY_STS))\r
{\r
- ;\r
}\r
- /* Once dyn_config_rdy bit is set, FW can change the EP configuration. */\r
+ \r
+ /* Once DYN_RECONFIG_RDY_STS bit is set, FW can change the EP configuration. */\r
/* Change EP Type with new direction */\r
- if((pEP->addr & USBFS_DIR_IN) == 0u)\r
+ if (0u != (pEP->addr & USBFS_DIR_IN))\r
{\r
- USBFS_EP_TYPE_REG |= (uint8)(0x01u << (cur_ep - USBFS_EP1));\r
+ /* Set endpoint type: 0 - IN and 1 - OUT. */\r
+ USBFS_EP_TYPE_REG &= (uint8) ~(uint8)((uint8) 0x01u << (curEp - 1u));\r
+ \r
+ #if (CY_PSOC4)\r
+ /* Clear DMA_TERMIN for IN endpoint */\r
+ USBFS_ARB_EP_BASE.arbEp[curEp].epIntEn &= (uint32) ~USBFS_ARB_EPX_INT_DMA_TERMIN;\r
+ #endif /* (CY_PSOC4) */\r
}\r
else\r
{\r
- USBFS_EP_TYPE_REG &= (uint8)~(uint8)(0x01u << (cur_ep - USBFS_EP1));\r
+ /* Set endpoint type: 0 - IN and 1- OUT. */\r
+ USBFS_EP_TYPE_REG |= (uint8) ((uint8) 0x01u << (curEp - 1u));\r
+ \r
+ #if (CY_PSOC4)\r
+ /* Set DMA_TERMIN for OUT endpoint */\r
+ USBFS_ARB_EP_BASE.arbEp[curEp].epIntEn |= (uint32) USBFS_ARB_EPX_INT_DMA_TERMIN;\r
+ #endif /* (CY_PSOC4) */\r
}\r
- /* dynamic reconfiguration enable bit cleared, pointers and control/status\r
- * signals for the selected EP is cleared/re-initialized on negative edge\r
- * of dynamic reconfiguration enable bit).\r
+ \r
+ /* Complete dynamic re-configuration: all endpoint related status and signals \r
+ * are set into the default state.\r
*/\r
- USBFS_DYN_RECONFIG_REG &= (uint8)~USBFS_DYN_RECONFIG_ENABLE;\r
- /* The main loop has to re-enable DMA and OUT endpoint*/\r
+ USBFS_DYN_RECONFIG_REG &= (uint8) ~USBFS_DYN_RECONFIG_ENABLE;\r
+\r
#else\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri),\r
- USBFS_EP[cur_ep].bufferSize >> 8u);\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri),\r
- USBFS_EP[cur_ep].bufferSize & 0xFFu);\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + ri),\r
- USBFS_EP[cur_ep].buffOffset & 0xFFu);\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + ri),\r
- USBFS_EP[cur_ep].buffOffset >> 8u);\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ri),\r
- USBFS_EP[cur_ep].buffOffset & 0xFFu);\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ri),\r
- USBFS_EP[cur_ep].buffOffset >> 8u);\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ USBFS_SIE_EP_BASE.sieEp[curEp].epCnt0 = HI8(USBFS_EP[curEp].bufferSize);\r
+ USBFS_SIE_EP_BASE.sieEp[curEp].epCnt1 = LO8(USBFS_EP[curEp].bufferSize);\r
+ \r
+ #if (CY_PSOC4)\r
+ USBFS_ARB_EP16_BASE.arbEp[curEp].rwRa16 = (uint32) USBFS_EP[curEp].buffOffset;\r
+ USBFS_ARB_EP16_BASE.arbEp[curEp].rwWa16 = (uint32) USBFS_EP[curEp].buffOffset;\r
+ #else\r
+ USBFS_ARB_EP_BASE.arbEp[curEp].rwRa = LO8(USBFS_EP[curEp].buffOffset);\r
+ USBFS_ARB_EP_BASE.arbEp[curEp].rwRaMsb = HI8(USBFS_EP[curEp].buffOffset);\r
+ USBFS_ARB_EP_BASE.arbEp[curEp].rwWa = LO8(USBFS_EP[curEp].buffOffset);\r
+ USBFS_ARB_EP_BASE.arbEp[curEp].rwWaMsb = HI8(USBFS_EP[curEp].buffOffset);\r
+ #endif /* (CY_PSOC4) */ \r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
}\r
- /* Get next EP element */\r
- pEP = &pEP[1u];\r
+ \r
+ pEP = &pEP[1u]; /* Get next EP element */\r
}\r
- } /* USBFS_configuration > 0 */\r
+ \r
+ /* The main loop has to re-enable DMA and OUT endpoint */\r
+ }\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_GetConfigTablePtr\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine returns a pointer a configuration table entry\r
*\r
-* Parameters:\r
-* confIndex: Configuration Index\r
+* \param confIndex: Configuration Index\r
*\r
-* Return:\r
-* Device Descriptor pointer or NULL when descriptor isn't exists.\r
+* \return\r
+* Device Descriptor pointer or NULL when descriptor does not exist.\r
*\r
*******************************************************************************/\r
const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)\r
pTmp = (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list;\r
\r
/* The first entry points to the Device Descriptor,\r
+ * the second entry point to the BOS Descriptor\r
* the rest configuration entries.\r
* Set pointer to the first Configuration Descriptor\r
*/\r
- pTmp = &pTmp[1u];\r
+ pTmp = &pTmp[2u];\r
/* For this table, c is the number of configuration descriptors */\r
if(confIndex >= pTmp->c) /* Verify that required configuration descriptor exists */\r
{\r
pTmp = (const T_USBFS_LUT CYCODE *) pTmp[confIndex].p_list;\r
}\r
\r
- return( pTmp );\r
+ return (pTmp);\r
}\r
\r
\r
+#if (USBFS_BOS_ENABLE)\r
+ /*******************************************************************************\r
+ * Function Name: USBFS_GetBOSPtr\r
+ ****************************************************************************//**\r
+ *\r
+ * This routine returns a pointer a BOS table entry\r
+ *\r
+ * \r
+ *\r
+ * \return\r
+ * BOS Descriptor pointer or NULL when descriptor does not exist.\r
+ *\r
+ *******************************************************************************/\r
+ const T_USBFS_LUT CYCODE *USBFS_GetBOSPtr(void)\r
+ \r
+ {\r
+ /* Device Table */\r
+ const T_USBFS_LUT CYCODE *pTmp;\r
+\r
+ pTmp = (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list;\r
+\r
+ /* The first entry points to the Device Descriptor,\r
+ * the second entry points to the BOS Descriptor\r
+ */\r
+ pTmp = &pTmp[1u];\r
+ pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list;\r
+ return (pTmp);\r
+ }\r
+#endif /* (USBFS_BOS_ENABLE) */\r
+\r
+\r
/*******************************************************************************\r
* Function Name: USBFS_GetDeviceTablePtr\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine returns a pointer to the Device table\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* Device Table pointer\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: USB_GetInterfaceClassTablePtr\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine returns Interface Class table pointer, which contains\r
* the relation between interface number and interface class.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* Interface Class table pointer.\r
*\r
*******************************************************************************/\r
uint8 currentInterfacesNum;\r
\r
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);\r
- if( pTmp != NULL )\r
+ if (pTmp != NULL)\r
{\r
currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];\r
/* Third entry in the LUT starts the Interface Table pointers */\r
pInterfaceClass = (const uint8 CYCODE *) NULL;\r
}\r
\r
- return( pInterfaceClass );\r
+ return (pInterfaceClass);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_TerminateEP\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function terminates the specified USBFS endpoint.\r
* This function should be used before endpoint reconfiguration.\r
*\r
-* Parameters:\r
-* Endpoint number.\r
+* \param ep Contains the data endpoint number.\r
*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
+* \sideeffect\r
+* \r
+* The device responds with a NAK for any transactions on the selected endpoint.\r
+* \r
*******************************************************************************/\r
-void USBFS_TerminateEP(uint8 ep) \r
+void USBFS_TerminateEP(uint8 epNumber) \r
{\r
- uint8 ri;\r
-\r
- ep &= USBFS_DIR_UNUSED;\r
- ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
+ /* Get endpoint number */\r
+ epNumber &= USBFS_DIR_UNUSED;\r
\r
- if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP))\r
+ if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
/* Set the endpoint Halt */\r
- USBFS_EP[ep].hwEpState |= (USBFS_ENDPOINT_STATUS_HALT);\r
+ USBFS_EP[epNumber].hwEpState |= USBFS_ENDPOINT_STATUS_HALT;\r
\r
/* Clear the data toggle */\r
- USBFS_EP[ep].epToggle = 0u;\r
- USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_ALLOWED;\r
+ USBFS_EP[epNumber].epToggle = 0u;\r
+ USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_ALLOWED;\r
\r
- if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u)\r
- {\r
+ if ((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u)\r
+ { \r
/* IN Endpoint */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN);\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_MODE_NAK_IN;\r
}\r
else\r
{\r
/* OUT Endpoint */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT);\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_MODE_NAK_OUT;\r
}\r
}\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_SetEndpointHalt\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine handles set endpoint halt.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_SetEndpointHalt(void) \r
{\r
- uint8 ep;\r
- uint8 ri;\r
uint8 requestHandled = USBFS_FALSE;\r
-\r
+ uint8 ep;\r
+ \r
/* Set endpoint halt */\r
- ep = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED;\r
- ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
+ ep = USBFS_wIndexLoReg & USBFS_DIR_UNUSED;\r
\r
if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP))\r
{\r
if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u)\r
{\r
/* IN Endpoint */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_STALL_DATA_EP |\r
- USBFS_MODE_ACK_IN);\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = (USBFS_MODE_STALL_DATA_EP | \r
+ USBFS_MODE_ACK_IN);\r
}\r
else\r
{\r
/* OUT Endpoint */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_STALL_DATA_EP |\r
- USBFS_MODE_ACK_OUT);\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = (USBFS_MODE_STALL_DATA_EP | \r
+ USBFS_MODE_ACK_OUT);\r
}\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
}\r
\r
- return(requestHandled);\r
+ return (requestHandled);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ClearEndpointHalt\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine handles clear endpoint halt.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_ClearEndpointHalt(void) \r
{\r
- uint8 ep;\r
- uint8 ri;\r
uint8 requestHandled = USBFS_FALSE;\r
+ uint8 ep;\r
\r
/* Clear endpoint halt */\r
- ep = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED;\r
- ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
+ ep = USBFS_wIndexLoReg & USBFS_DIR_UNUSED;\r
\r
if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP))\r
{\r
/* Clear the endpoint Halt */\r
- USBFS_EP[ep].hwEpState &= (uint8)~(USBFS_ENDPOINT_STATUS_HALT);\r
+ USBFS_EP[ep].hwEpState &= (uint8) ~USBFS_ENDPOINT_STATUS_HALT;\r
\r
/* Clear the data toggle */\r
USBFS_EP[ep].epToggle = 0u;\r
+ \r
/* Clear toggle bit for already armed packet */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), CY_GET_REG8(\r
- (reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) & (uint8)~USBFS_EPX_CNT_DATA_TOGGLE);\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCnt0 = (uint8) ~(uint8)USBFS_EPX_CNT_DATA_TOGGLE;\r
+ \r
/* Return API State as it was defined before */\r
- USBFS_EP[ep].apiEpState &= (uint8)~USBFS_NO_EVENT_ALLOWED;\r
+ USBFS_EP[ep].apiEpState &= (uint8) ~USBFS_NO_EVENT_ALLOWED;\r
\r
if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u)\r
{\r
/* IN Endpoint */\r
if(USBFS_EP[ep].apiEpState == USBFS_IN_BUFFER_EMPTY)\r
- { /* Wait for next packet from application */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN);\r
+ { \r
+ /* Wait for next packet from application */\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_IN;\r
}\r
else /* Continue armed transfer */\r
{\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_ACK_IN);\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_ACK_IN;\r
}\r
}\r
else\r
{\r
/* OUT Endpoint */\r
- if(USBFS_EP[ep].apiEpState == USBFS_OUT_BUFFER_FULL)\r
- { /* Allow application to read full buffer */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT);\r
+ if (USBFS_EP[ep].apiEpState == USBFS_OUT_BUFFER_FULL)\r
+ { \r
+ /* Allow application to read full buffer */\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_OUT;\r
}\r
else /* Mark endpoint as empty, so it will be reloaded */\r
{\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_ACK_OUT);\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_ACK_OUT;\r
}\r
}\r
+ \r
requestHandled = USBFS_InitNoDataControlTransfer();\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ValidateAlternateSetting\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Validates (and records) a SET INTERFACE request.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_ValidateAlternateSetting(void) \r
{\r
- uint8 requestHandled = USBFS_TRUE;\r
+ uint8 requestHandled = USBFS_FALSE;\r
+ \r
uint8 interfaceNum;\r
+ uint8 curInterfacesNum;\r
const T_USBFS_LUT CYCODE *pTmp;\r
- uint8 currentInterfacesNum;\r
-\r
- interfaceNum = CY_GET_REG8(USBFS_wIndexLo);\r
- /* Validate interface setting, stall if invalid. */\r
+ \r
+ /* Get interface number from the request. */\r
+ interfaceNum = (uint8) USBFS_wIndexLoReg;\r
+ \r
+ /* Get number of interfaces for current configuration. */\r
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);\r
- currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];\r
+ curInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];\r
\r
- if((interfaceNum >= currentInterfacesNum) || (interfaceNum >= USBFS_MAX_INTERFACES_NUMBER))\r
- { /* Wrong interface number */\r
- requestHandled = USBFS_FALSE;\r
- }\r
- else\r
+ /* Validate that interface number is within range. */\r
+ if ((interfaceNum <= curInterfacesNum) || (interfaceNum <= USBFS_MAX_INTERFACES_NUMBER))\r
{\r
- /* Save current Alt setting to find out the difference in Config() function */\r
- USBFS_interfaceSetting_last[interfaceNum] = USBFS_interfaceSetting[interfaceNum];\r
- USBFS_interfaceSetting[interfaceNum] = CY_GET_REG8(USBFS_wValueLo);\r
+ /* Save current and new alternate settings (come with request) to make \r
+ * desicion about following endpoint re-configuration.\r
+ */\r
+ USBFS_interfaceSettingLast[interfaceNum] = USBFS_interfaceSetting[interfaceNum];\r
+ USBFS_interfaceSetting[interfaceNum] = (uint8) USBFS_wValueLoReg;\r
+ \r
+ requestHandled = USBFS_TRUE;\r
}\r
\r
return (requestHandled);\r
-/*******************************************************************************\r
-* File Name: USBFS_vnd.c\r
-* Version 2.80\r
-*\r
-* Description:\r
-* USB vendor request handler.\r
+/***************************************************************************//**\r
+* \file USBFS_vnd.c\r
+* \version 3.10\r
*\r
-* Note:\r
+* \brief\r
+* This file contains the USB vendor request handler.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
#include "USBFS_pvt.h"\r
\r
\r
#if(USBFS_EXTERN_VND == USBFS_FALSE)\r
\r
-\r
/***************************************\r
* Vendor Specific Declarations\r
***************************************/\r
\r
/*******************************************************************************\r
* Function Name: USBFS_HandleVendorRqst\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine provide users with a method to implement vendor specific\r
* requests.\r
*\r
* must set the variable "requestHandled" to TRUE, indicating that the\r
* request has been handled.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
{\r
uint8 requestHandled = USBFS_FALSE;\r
\r
- if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)\r
+ /* Check request direction: D2H or H2D. */\r
+ if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H))\r
{\r
- /* Control Read */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ /* Handle direction from device to host. */\r
+ \r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR:\r
- #if defined(USBFS_ENABLE_MSOS_STRING)\r
- USBFS_currentTD.pData = (volatile uint8 *)&USBFS_MSOS_CONFIGURATION_DESCR[0u];\r
- USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u];\r
- requestHandled = USBFS_InitControlRead();\r
- #endif /* USBFS_ENABLE_MSOS_STRING */\r
+ #if defined(USBFS_ENABLE_MSOS_STRING)\r
+ USBFS_currentTD.pData = (volatile uint8 *) &USBFS_MSOS_CONFIGURATION_DESCR[0u];\r
+ USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u];\r
+ requestHandled = USBFS_InitControlRead();\r
+ #endif /* (USBFS_ENABLE_MSOS_STRING) */\r
break;\r
+ \r
default:\r
break;\r
}\r
\r
/* `#END` */\r
\r
- #ifdef USBFS_HANDLE_VENDOR_RQST_CALLBACK\r
- USBFS_HandleVendorRqst_Callback();\r
- #endif /* USBFS_HANDLE_VENDOR_RQST_CALLBACK */\r
+#ifdef USBFS_HANDLE_VENDOR_RQST_CALLBACK\r
+ if (USBFS_FALSE == requestHandled)\r
+ {\r
+ requestHandled = USBFS_HandleVendorRqst_Callback();\r
+ }\r
+#endif /* (USBFS_HANDLE_VENDOR_RQST_CALLBACK) */\r
\r
- return(requestHandled);\r
+ return (requestHandled);\r
}\r
\r
\r
\r
/* `#END` */\r
\r
+\r
#endif /* USBFS_EXTERN_VND */\r
\r
\r
SEARCH_DIR(.)\r
GROUP(-lgcc -lc -lnosys)\r
\r
+/* Code sharing support */\r
+INCLUDE cycodeshareexport.ld\r
+INCLUDE cycodeshareimport.ld\r
+\r
\r
MEMORY\r
{\r
- rom (rx) : ORIGIN = 0x0, LENGTH = 131072\r
- ram (rwx) : ORIGIN = 0x20000000 - (32768 / 2), LENGTH = 32768\r
+ rom (rx) : ORIGIN = 0x0, LENGTH = 131072\r
+ ram (rwx) : ORIGIN = 0x20000000 - (32768 / 2), LENGTH = 32768\r
}\r
\r
\r
-CY_APPL_ORIGIN = 0; \r
+CY_APPL_ORIGIN = 0;\r
CY_FLASH_ROW_SIZE = 256;\r
CY_ECC_ROW_SIZE = 32;\r
CY_EE_IN_BTLDR = 0x00;\r
CY_APPL_NUM = 1;\r
CY_APPL_MAX = 1;\r
CY_METADATA_SIZE = 64;\r
+CY_APPL_LOADABLE = 1;\r
+CY_CHECKSUM_EXCLUDE_SIZE = ALIGN(0, CY_FLASH_ROW_SIZE);\r
\r
\r
/* These force the linker to search for particular symbols from\r
\r
SECTIONS\r
{\r
- /* The bootloader location */\r
- .cybootloader 0x0 : { KEEP(*(.cybootloader)) } >rom\r
-\r
- /* Calculate where the loadables should start */\r
- appl1_start = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : ALIGN(CY_FLASH_ROW_SIZE);\r
- appl2_start = appl1_start + ALIGN((LENGTH(rom) - appl1_start - 2 * CY_FLASH_ROW_SIZE) / 2, CY_FLASH_ROW_SIZE);\r
- appl_start = (CY_APPL_NUM == 1) ? appl1_start : appl2_start;\r
- ecc_offset = (appl_start / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE;\r
- ee_offset = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0;\r
- ee_size = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE;\r
- PROVIDE(CY_ECC_OFFSET = ecc_offset);\r
- \r
- .text appl_start :\r
- {\r
- CREATE_OBJECT_SYMBOLS\r
- PROVIDE(__cy_interrupt_vector = RomVectors);\r
-\r
- *(.romvectors)\r
-\r
- /* Make sure we pulled in an interrupt vector. */\r
- ASSERT (. != __cy_interrupt_vector, "No interrupt vector");\r
-\r
- ASSERT (CY_APPL_ORIGIN ? (SIZEOF(.cybootloader) <= CY_APPL_ORIGIN) : 1, "Wrong image location");\r
-\r
- PROVIDE(__cy_reset = Reset);\r
- *(.text.Reset)\r
- /* Make sure we pulled in some reset code. */\r
- ASSERT (. != __cy_reset, "No reset code");\r
-\r
- /* Place DMA initialization before text to ensure it gets placed in first 64K of flash */\r
- *(.dma_init)\r
- ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");\r
- \r
- *(.text .text.* .gnu.linkonce.t.*)\r
- *(.plt)\r
- *(.gnu.warning)\r
- *(.glue_7t) *(.glue_7) *(.vfp11_veneer)\r
- \r
- KEEP(*(.bootloader)) /* necessary for bootloader's, but doesn't impact non-bootloaders */\r
-\r
- *(.ARM.extab* .gnu.linkonce.armextab.*)\r
- *(.gcc_except_table)\r
- } >rom\r
- .eh_frame_hdr : ALIGN (4)\r
- {\r
- KEEP (*(.eh_frame_hdr))\r
- } >rom\r
- .eh_frame : ALIGN (4)\r
- {\r
- KEEP (*(.eh_frame))\r
- } >rom\r
- /* .ARM.exidx is sorted, so has to go in its own output section. */\r
- PROVIDE_HIDDEN (__exidx_start = .);\r
- .ARM.exidx :\r
- {\r
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
- } >rom\r
- __exidx_end = .;\r
- .rodata : ALIGN (4)\r
- {\r
- *(.rodata .rodata.* .gnu.linkonce.r.*)\r
-\r
- . = ALIGN(4);\r
- KEEP(*(.init))\r
-\r
- . = ALIGN(4);\r
- __preinit_array_start = .;\r
- KEEP (*(.preinit_array))\r
- __preinit_array_end = .;\r
-\r
- . = ALIGN(4);\r
- __init_array_start = .;\r
- KEEP (*(SORT(.init_array.*)))\r
- KEEP (*(.init_array))\r
- __init_array_end = .;\r
-\r
- . = ALIGN(4);\r
- KEEP(*(.fini))\r
-\r
- . = ALIGN(4);\r
- __fini_array_start = .;\r
- KEEP (*(.fini_array))\r
- KEEP (*(SORT(.fini_array.*)))\r
- __fini_array_end = .;\r
-\r
- . = ALIGN(0x4);\r
- KEEP (*crtbegin.o(.ctors))\r
- KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r
- KEEP (*(SORT(.ctors.*)))\r
- KEEP (*crtend.o(.ctors))\r
-\r
- . = ALIGN(0x4);\r
- KEEP (*crtbegin.o(.dtors))\r
- KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r
- KEEP (*(SORT(.dtors.*)))\r
- KEEP (*crtend.o(.dtors))\r
-\r
- . = ALIGN(4);\r
- __cy_regions = .;\r
- LONG (__cy_region_init_ram)\r
- LONG (__cy_region_start_data)\r
- LONG (__cy_region_init_size_ram)\r
- LONG (__cy_region_zero_size_ram)\r
- __cy_regions_end = .;\r
-\r
- . = ALIGN (8);\r
- _etext = .;\r
- } >rom\r
+ /* The bootloader location */\r
+ .cybootloader 0x0 : { KEEP(*(.cybootloader)) } >rom\r
+\r
+ /* Calculate where the loadables should start */\r
+ appl1_start = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : ALIGN(CY_FLASH_ROW_SIZE);\r
+ appl2_start = appl1_start + ALIGN((LENGTH(rom) - appl1_start - 2 * CY_FLASH_ROW_SIZE) / 2, CY_FLASH_ROW_SIZE);\r
+ appl_start = (CY_APPL_NUM == 1) ? appl1_start : appl2_start;\r
+ ecc_offset = (appl_start / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE;\r
+ ee_offset = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0;\r
+ ee_size = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE;\r
+ PROVIDE(CY_ECC_OFFSET = ecc_offset);\r
+\r
+ .text appl_start :\r
+ {\r
+ CREATE_OBJECT_SYMBOLS\r
+ PROVIDE(__cy_interrupt_vector = RomVectors);\r
+\r
+ *(.romvectors)\r
+\r
+ /* Make sure we pulled in an interrupt vector. */\r
+ ASSERT (. != __cy_interrupt_vector, "No interrupt vector");\r
+\r
+ ASSERT (CY_APPL_ORIGIN ? (SIZEOF(.cybootloader) <= CY_APPL_ORIGIN) : 1, "Wrong image location");\r
+\r
+ PROVIDE(__cy_reset = Reset);\r
+ *(.text.Reset)\r
+ /* Make sure we pulled in some reset code. */\r
+ ASSERT (. != __cy_reset, "No reset code");\r
\r
- .ramvectors (NOLOAD) : ALIGN(8)\r
- {\r
- __cy_region_start_ram = .;\r
- KEEP(*(.ramvectors))\r
- }\r
-\r
- .noinit (NOLOAD) : ALIGN(8)\r
- {\r
- KEEP(*(.noinit))\r
- }\r
-\r
- .data : ALIGN(8)\r
- {\r
- __cy_region_start_data = .;\r
-\r
- KEEP(*(.jcr))\r
- *(.got.plt) *(.got)\r
- *(.shdata)\r
- *(.data .data.* .gnu.linkonce.d.*)\r
- . = ALIGN (8);\r
- *(.ram)\r
- _edata = .;\r
- } >ram AT>rom\r
- .bss : ALIGN(8)\r
- {\r
- PROVIDE(__bss_start__ = .);\r
- *(.shbss)\r
- *(.bss .bss.* .gnu.linkonce.b.*)\r
- *(COMMON)\r
- . = ALIGN (8);\r
- *(.ram.b)\r
- _end = .;\r
- __end = .;\r
- } >ram AT>rom\r
- PROVIDE(end = .);\r
- PROVIDE(__bss_end__ = .);\r
- \r
- __cy_region_init_ram = LOADADDR (.data);\r
- __cy_region_init_size_ram = _edata - ADDR (.data);\r
- __cy_region_zero_size_ram = _end - _edata;\r
- \r
- /* The .stack and .heap sections don't contain any symbols. \r
- * They are only used for linker to calculate RAM utilization.\r
- */\r
- .heap (NOLOAD) :\r
- {\r
- . = _end;\r
- . += 0x0400;\r
- __cy_heap_limit = .;\r
- } >ram\r
-\r
- .stack (__cy_stack - 0x1000) (NOLOAD) :\r
- {\r
- __cy_stack_limit = .;\r
- . += 0x1000;\r
- } >ram\r
- \r
- /* Check if data + heap + stack exceeds RAM limit */\r
- ASSERT(__cy_stack_limit >= __cy_heap_limit, "region RAM overflowed with stack")\r
-\r
- .cyloadermeta ((appl_start == 0) ? (LENGTH(rom) - CY_METADATA_SIZE) : 0xF0000000) :\r
- {\r
- KEEP(*(.cyloadermeta))\r
- } :NONE\r
-\r
- .cyloadablemeta (LENGTH(rom) - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) :\r
- {\r
- KEEP(*(.cyloadablemeta))\r
+ /* Place DMA initialization before text to ensure it gets placed in first 64K of flash */\r
+ *(.dma_init)\r
+ ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");\r
+\r
+ *(.text .text.* .gnu.linkonce.t.*)\r
+ *(.plt)\r
+ *(.gnu.warning)\r
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)\r
+\r
+ KEEP(*(.bootloader)) /* necessary for bootloader's, but doesn't impact non-bootloaders */\r
+\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+ *(.gcc_except_table)\r
} >rom\r
\r
- .cyconfigecc (0x80000000 + ecc_offset) : \r
- {\r
- KEEP(*(.cyconfigecc))\r
- } :NONE \r
-\r
- .cycustnvl 0x90000000 : { KEEP(*(.cycustnvl)) } :NONE \r
- .cywolatch 0x90100000 : { KEEP(*(.cywolatch)) } :NONE \r
-\r
- .cyeeprom (0x90200000 + ee_offset) : \r
- {\r
- KEEP(*(.cyeeprom))\r
- ASSERT(. <= (0x90200000 + ee_offset + ee_size), ".cyeeprom data will not fit in EEPROM");\r
- } :NONE \r
-\r
- .cyflashprotect 0x90400000 : { KEEP(*(.cyflashprotect)) } :NONE \r
- .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE \r
-\r
- .stab 0 (NOLOAD) : { *(.stab) }\r
- .stabstr 0 (NOLOAD) : { *(.stabstr) }\r
- /* DWARF debug sections.\r
- * Symbols in the DWARF debugging sections are relative to the beginning\r
- * of the section so we begin them at 0.\r
- */\r
- /* DWARF 1 */\r
- .debug 0 : { *(.debug) }\r
- .line 0 : { *(.line) }\r
- /* GNU DWARF 1 extensions */\r
- .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
- .debug_sfnames 0 : { *(.debug_sfnames) }\r
- /* DWARF 1.1 and DWARF 2 */\r
- .debug_aranges 0 : { *(.debug_aranges) }\r
- .debug_pubnames 0 : { *(.debug_pubnames) }\r
- /* DWARF 2 */\r
- .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
- .debug_abbrev 0 : { *(.debug_abbrev) }\r
- .debug_line 0 : { *(.debug_line) }\r
- .debug_frame 0 : { *(.debug_frame) }\r
- .debug_str 0 : { *(.debug_str) }\r
- .debug_loc 0 : { *(.debug_loc) }\r
- .debug_macinfo 0 : { *(.debug_macinfo) }\r
- /* DWARF 2.1 */\r
- .debug_ranges 0 : { *(.debug_ranges) }\r
- /* SGI/MIPS DWARF 2 extensions */\r
- .debug_weaknames 0 : { *(.debug_weaknames) }\r
- .debug_funcnames 0 : { *(.debug_funcnames) }\r
- .debug_typenames 0 : { *(.debug_typenames) }\r
- .debug_varnames 0 : { *(.debug_varnames) }\r
-\r
- .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\r
- .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }\r
- /DISCARD/ : { *(.note.GNU-stack) }\r
+\r
+ .eh_frame_hdr : ALIGN (4)\r
+ {\r
+ KEEP (*(.eh_frame_hdr))\r
+ } >rom\r
+\r
+\r
+ .eh_frame : ALIGN (4)\r
+ {\r
+ KEEP (*(.eh_frame))\r
+ } >rom\r
+\r
+\r
+ /* .ARM.exidx is sorted, so has to go in its own output section. */\r
+ PROVIDE_HIDDEN (__exidx_start = .);\r
+ .ARM.exidx :\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } >rom\r
+ __exidx_end = .;\r
+\r
+\r
+ .rodata : ALIGN (4)\r
+ {\r
+ *(.rodata .rodata.* .gnu.linkonce.r.*)\r
+\r
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+ . = ALIGN(0x4);\r
+ KEEP (*crtbegin.o(.ctors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r
+ KEEP (*(SORT(.ctors.*)))\r
+ KEEP (*crtend.o(.ctors))\r
+\r
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+ KEEP (*crtbegin.o(.dtors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r
+ KEEP (*(SORT(.dtors.*)))\r
+ KEEP (*crtend.o(.dtors))\r
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+ LONG (__cy_region_init_ram)\r
+ LONG (__cy_region_start_data)\r
+ LONG (__cy_region_init_size_ram)\r
+ LONG (__cy_region_zero_size_ram)\r
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+ {\r
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+ *(.ram)\r
+ _edata = .;\r
+ } >ram AT>rom\r
+\r
+\r
+ .bss : ALIGN(8)\r
+ {\r
+ PROVIDE(__bss_start__ = .);\r
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+ *(.bss .bss.* .gnu.linkonce.b.*)\r
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+ .heap (NOLOAD) :\r
+ {\r
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+ /* Check if data + heap + stack exceeds RAM limit */\r
+ ASSERT(__cy_stack_limit >= __cy_heap_limit, "region RAM overflowed with stack")\r
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+ * Case # 1. Bootloadable application\r
+ *\r
+ * _______________________________\r
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+ * | |\r
+ * | |\r
+ * | |\r
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+ * | |\r
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+ *\r
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+ */\r
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+ /DISCARD/ : { *(.note.GNU-stack) }\r
}\r
\r
--- /dev/null
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
--- /dev/null
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03U)
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03U) */
+
+
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* __CMSIS_GCC_H */
/**************************************************************************//**\r
* @file core_cm3.h\r
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
- * @version V3.20\r
- * @date 25. February 2013\r
- *\r
- * @note\r
- *\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
******************************************************************************/\r
-/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
\r
All rights reserved.\r
Redistribution and use in source and binary forms, with or without\r
---------------------------------------------------------------------------*/\r
\r
\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
#endif\r
\r
+#ifndef __CORE_CM3_H_GENERIC\r
+#define __CORE_CM3_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
#ifdef __cplusplus\r
extern "C" {\r
#endif\r
\r
-#ifndef __CORE_CM3_H_GENERIC\r
-#define __CORE_CM3_H_GENERIC\r
-\r
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
CMSIS violates the following MISRA-C:2004 rules:\r
\r
\li Required Rule 8.5, object/function definition in header file.<br>\r
/*******************************************************************************\r
* CMSIS definitions\r
******************************************************************************/\r
-/** \ingroup Cortex_M3\r
+/**\r
+ \ingroup Cortex_M3\r
@{\r
*/\r
\r
/* CMSIS CM3 definitions */\r
-#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \\r
- __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
\r
-#define __CORTEX_M (0x03) /*!< Cortex-M Core */\r
+#define __CORTEX_M (0x03U) /*!< Cortex-M Core */\r
\r
\r
#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
#define __STATIC_INLINE static __inline\r
\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
#define __STATIC_INLINE static inline\r
\r
#elif defined ( __TMS470__ )\r
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
#define __STATIC_INLINE static inline\r
\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
#define __STATIC_INLINE static inline\r
\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+#elif defined ( __CSMC__ )\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r
#define __STATIC_INLINE static inline\r
\r
+#else\r
+ #error Unknown compiler\r
#endif\r
\r
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
*/\r
-#define __FPU_USED 0\r
+#define __FPU_USED 0U\r
\r
#if defined ( __CC_ARM )\r
#if defined __TARGET_FPU_VFP\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
#endif\r
\r
#elif defined ( __ICCARM__ )\r
#if defined __ARMVFP__\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
#endif\r
\r
#elif defined ( __TMS470__ )\r
- #if defined __TI__VFP_SUPPORT____\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
#endif\r
\r
#elif defined ( __TASKING__ )\r
#if defined __FPU_VFP__\r
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
#endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
#endif\r
\r
-#include <stdint.h> /* standard types definitions */\r
-#include <core_cmInstr.h> /* Core Instruction Access */\r
-#include <core_cmFunc.h> /* Core Function Access */\r
+#include "core_cmInstr.h" /* Core Instruction Access */\r
+#include "core_cmFunc.h" /* Core Function Access */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
\r
#endif /* __CORE_CM3_H_GENERIC */\r
\r
#ifndef __CORE_CM3_H_DEPENDANT\r
#define __CORE_CM3_H_DEPENDANT\r
\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
/* check device defines and use defaults */\r
#if defined __CHECK_DEVICE_DEFINES\r
#ifndef __CM3_REV\r
- #define __CM3_REV 0x0200\r
+ #define __CM3_REV 0x0200U\r
#warning "__CM3_REV not defined in device header file; using default!"\r
#endif\r
\r
#ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0\r
+ #define __MPU_PRESENT 0U\r
#warning "__MPU_PRESENT not defined in device header file; using default!"\r
#endif\r
\r
#ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 4\r
+ #define __NVIC_PRIO_BITS 4U\r
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
#endif\r
\r
#ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0\r
+ #define __Vendor_SysTickConfig 0U\r
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
#endif\r
#endif\r
\li for automatic generation of peripheral register debug information.\r
*/\r
#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
\r
/*@} end of group Cortex_M3 */\r
\r
- Core Debug Register\r
- Core MPU Register\r
******************************************************************************/\r
-/** \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
*/\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
@{\r
*/\r
\r
-/** \brief Union type to access the Application Program Status Register (APSR).\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
*/\r
typedef union\r
{\r
struct\r
{\r
-#if (__CORTEX_M != 0x04)\r
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
-#else\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
-#endif\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
} APSR_Type;\r
\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
\r
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
*/\r
typedef union\r
{\r
struct\r
{\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
} IPSR_Type;\r
\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
\r
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
*/\r
typedef union\r
{\r
struct\r
{\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
-#if (__CORTEX_M != 0x04)\r
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
-#else\r
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
-#endif\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
} xPSR_Type;\r
\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
\r
-/** \brief Union type to access the Control Registers (CONTROL).\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
*/\r
typedef union\r
{\r
struct\r
{\r
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
} CONTROL_Type;\r
\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
/*@} end of group CMSIS_CORE */\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
@{\r
*/\r
\r
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
*/\r
typedef struct\r
{\r
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24];\r
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24];\r
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24];\r
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24];\r
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
- uint32_t RESERVED4[56];\r
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644];\r
- __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
} NVIC_Type;\r
\r
/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
\r
/*@} end of group CMSIS_NVIC */\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
@{\r
*/\r
\r
-/** \brief Structure type to access the System Control Block (SCB).\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
*/\r
typedef struct\r
{\r
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
- __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
- __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
- __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
- __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
- __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
- __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
- __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
- __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
- uint32_t RESERVED0[5];\r
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5U];\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
} SCB_Type;\r
\r
/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
\r
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
\r
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
\r
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
\r
/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
\r
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
\r
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
\r
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
\r
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
\r
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
\r
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
\r
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
\r
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
\r
/* SCB Vector Table Offset Register Definitions */\r
-#if (__CM3_REV < 0x0201) /* core r2p1 */\r
-#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#if (__CM3_REV < 0x0201U) /* core r2p1 */\r
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */\r
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
\r
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
#else\r
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
#endif\r
\r
/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
\r
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
\r
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
\r
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
\r
/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
\r
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
\r
/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
\r
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
\r
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
\r
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
\r
/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
\r
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
\r
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
\r
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
\r
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
\r
-/* SCB Configurable Fault Status Registers Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
\r
-/* SCB Hard Fault Status Registers Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
\r
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
\r
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
\r
/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
\r
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
\r
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
\r
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
\r
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
\r
/*@} end of group CMSIS_SCB */\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
- \brief Type definitions for the System Control and ID Register not in the SCB\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
@{\r
*/\r
\r
-/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
*/\r
typedef struct\r
{\r
- uint32_t RESERVED0[1];\r
- __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
- __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
#else\r
- uint32_t RESERVED1[1];\r
+ uint32_t RESERVED1[1U];\r
#endif\r
} SCnSCB_Type;\r
\r
/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
\r
/* Auxiliary Control Register Definitions */\r
\r
-#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */\r
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
\r
/*@} end of group CMSIS_SCnotSCB */\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
@{\r
*/\r
\r
-/** \brief Structure type to access the System Timer (SysTick).\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
*/\r
typedef struct\r
{\r
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
} SysTick_Type;\r
\r
/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
\r
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
\r
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
\r
/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
\r
/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
\r
/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
\r
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
\r
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
\r
/*@} end of group CMSIS_SysTick */\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
@{\r
*/\r
\r
-/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
*/\r
typedef struct\r
{\r
- __O union\r
+ __OM union\r
{\r
- __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
- __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
- __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
- } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864];\r
- __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
- uint32_t RESERVED1[15];\r
- __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15];\r
- __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
- uint32_t RESERVED3[29];\r
- __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
- __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
- __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43];\r
- __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
- __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
- uint32_t RESERVED5[6];\r
- __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
- __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
- __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
- __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
- __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
- __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
- __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
- __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
- __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
- __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
- __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
- __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
} ITM_Type;\r
\r
/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
\r
/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
\r
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
\r
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
\r
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
\r
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
\r
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
\r
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
\r
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
\r
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
\r
/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
\r
/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
\r
/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
\r
/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
\r
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
\r
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
\r
/*@}*/ /* end of group CMSIS_ITM */\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
- \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
@{\r
*/\r
\r
-/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
*/\r
typedef struct\r
{\r
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
- __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
- __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
- __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
- __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
- __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
- __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
- __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
- __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
- __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
- __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
- uint32_t RESERVED0[1];\r
- __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
- __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
- __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
- uint32_t RESERVED1[1];\r
- __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
- __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
- __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
- uint32_t RESERVED2[1];\r
- __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
- __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
- __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
} DWT_Type;\r
\r
/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
\r
-#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
\r
-#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
\r
-#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
\r
-#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
\r
-#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
\r
-#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
\r
-#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
\r
-#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
\r
-#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
\r
-#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
\r
-#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
\r
-#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
\r
-#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
\r
-#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
\r
-#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
\r
-#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
\r
-#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
\r
/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
\r
/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
\r
/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
\r
/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
\r
/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
\r
/* DWT Comparator Mask Register Definitions */\r
-#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
\r
/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
\r
-#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
\r
-#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
\r
-#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
\r
-#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
\r
-#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
\r
-#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
\r
-#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
\r
-#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
\r
/*@}*/ /* end of group CMSIS_DWT */\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
- \brief Type definitions for the Trace Port Interface (TPI)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
@{\r
*/\r
\r
-/** \brief Structure type to access the Trace Port Interface Register (TPI).\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
*/\r
typedef struct\r
{\r
- __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
- __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
- uint32_t RESERVED0[2];\r
- __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
- uint32_t RESERVED1[55];\r
- __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
- uint32_t RESERVED2[131];\r
- __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
- __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
- __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
- uint32_t RESERVED3[759];\r
- __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
- __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
- __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
- uint32_t RESERVED4[1];\r
- __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
- __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
- __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
- uint32_t RESERVED5[39];\r
- __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
- __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
- uint32_t RESERVED7[8];\r
- __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
- __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
} TPI_Type;\r
\r
/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
\r
/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
\r
/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
\r
-#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
\r
-#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
\r
-#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
\r
/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
\r
-#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
\r
/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
\r
/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
-#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
\r
-#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
\r
-#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
\r
-#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
\r
-#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
\r
-#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
\r
-#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
\r
/* TPI ITATBCTR2 Register Definitions */\r
-#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
\r
/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
-#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
\r
-#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
\r
-#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
\r
-#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
\r
-#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
\r
-#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
\r
-#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
\r
/* TPI ITATBCTR0 Register Definitions */\r
-#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
\r
/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
\r
/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
\r
-#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
\r
-#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
\r
-#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
\r
-#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
\r
-#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
\r
/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
\r
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
/*@}*/ /* end of group CMSIS_TPI */\r
\r
\r
-#if (__MPU_PRESENT == 1)\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
+#if (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
@{\r
*/\r
\r
-/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
*/\r
typedef struct\r
{\r
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
- __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
- __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
- __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
} MPU_Type;\r
\r
-/* MPU Type Register */\r
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
\r
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
\r
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
\r
-/* MPU Control Register */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
\r
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
\r
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
\r
-/* MPU Region Number Register */\r
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
\r
-/* MPU Region Base Address Register */\r
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
\r
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
\r
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
\r
-/* MPU Region Attribute and Size Register */\r
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
\r
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
\r
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
\r
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
\r
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
\r
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
\r
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
\r
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
\r
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
\r
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
\r
/*@} end of group CMSIS_MPU */\r
#endif\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Type definitions for the Core Debug Registers\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
@{\r
*/\r
\r
-/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
*/\r
typedef struct\r
{\r
- __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
- __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
- __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
- __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
} CoreDebug_Type;\r
\r
-/* Debug Halting Control and Status Register */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
\r
-/* Debug Core Register Selector Register */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
\r
-/* Debug Exception and Monitor Control Register */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
\r
/*@} end of group CMSIS_CoreDebug */\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
@{\r
*/\r
\r
/* Memory mapping of Cortex-M3 Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
\r
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if (__MPU_PRESENT == 1)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
#endif\r
\r
/*@} */\r
- Core Debug Functions\r
- Core Register Access Functions\r
******************************************************************************/\r
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
*/\r
\r
\r
\r
/* ########################## NVIC functions #################################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
*/\r
\r
-/** \brief Set Priority Grouping\r
-\r
- The function sets the priority grouping field using the required unlock sequence.\r
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
- Only values from 0..7 are used.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-\r
- \param [in] PriorityGroup Priority grouping field.\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
*/\r
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
{\r
uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
\r
reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
SCB->AIRCR = reg_value;\r
}\r
\r
\r
-/** \brief Get Priority Grouping\r
-\r
- The function reads the priority grouping field from the NVIC Interrupt Controller.\r
-\r
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
{\r
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
}\r
\r
\r
-/** \brief Enable External Interrupt\r
-\r
- The function enables a device-specific interrupt in the NVIC interrupt controller.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
+/**\r
+ \brief Enable External Interrupt\r
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
*/\r
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
-/** \brief Disable External Interrupt\r
-\r
- The function disables a device-specific interrupt in the NVIC interrupt controller.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
+/**\r
+ \brief Disable External Interrupt\r
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
*/\r
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
-/** \brief Get Pending Interrupt\r
-\r
- The function reads the pending register in the NVIC and returns the pending bit\r
- for the specified interrupt.\r
-\r
- \param [in] IRQn Interrupt number.\r
-\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
}\r
\r
\r
-/** \brief Set Pending Interrupt\r
-\r
- The function sets the pending bit of an external interrupt.\r
-\r
- \param [in] IRQn Interrupt number. Value cannot be negative.\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of an external interrupt.\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
*/\r
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
-/** \brief Clear Pending Interrupt\r
-\r
- The function clears the pending bit of an external interrupt.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of an external interrupt.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
*/\r
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
-/** \brief Get Active Interrupt\r
-\r
- The function reads the active register in NVIC and returns the active bit.\r
-\r
- \param [in] IRQn Interrupt number.\r
-\r
- \return 0 Interrupt status is not active.\r
- \return 1 Interrupt status is active.\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in NVIC and returns the active bit.\r
+ \param [in] IRQn Interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
}\r
\r
\r
-/** \brief Set Interrupt Priority\r
-\r
- The function sets the priority of an interrupt.\r
-\r
- \note The priority cannot be set for every core interrupt.\r
-\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of an interrupt.\r
+ \note The priority cannot be set for every core interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
*/\r
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
{\r
- if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
- else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+ if ((int32_t)(IRQn) < 0)\r
+ {\r
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
}\r
\r
\r
-/** \brief Get Interrupt Priority\r
-\r
- The function reads the priority of an interrupt. The interrupt\r
- number can be positive to specify an external (device specific)\r
- interrupt, or negative to specify an internal (core) interrupt.\r
-\r
-\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority. Value is aligned automatically to the implemented\r
- priority bits of the microcontroller.\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of an interrupt.\r
+ The interrupt number can be positive to specify an external (device specific) interrupt,\r
+ or negative to specify an internal (core) interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
{\r
\r
- if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
- else {\r
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+ if ((int32_t)(IRQn) < 0)\r
+ {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
}\r
\r
\r
-/** \brief Encode Priority\r
-\r
- The function encodes the priority for an interrupt with the given priority group,\r
- preemptive priority value, and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.\r
-\r
- \param [in] PriorityGroup Used priority group.\r
- \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
- \param [in] SubPriority Subpriority value (starting from 0).\r
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
*/\r
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
uint32_t PreemptPriorityBits;\r
uint32_t SubPriorityBits;\r
\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
\r
return (\r
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
);\r
}\r
\r
\r
-/** \brief Decode Priority\r
-\r
- The function decodes an interrupt priority value with a given priority group to\r
- preemptive priority value and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
-\r
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
- \param [in] PriorityGroup Used priority group.\r
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
- \param [out] pSubPriority Subpriority value (starting from 0).\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
*/\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
uint32_t PreemptPriorityBits;\r
uint32_t SubPriorityBits;\r
\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
}\r
\r
\r
-/** \brief System Reset\r
-\r
- The function initiates a system reset request to reset the MCU.\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
*/\r
__STATIC_INLINE void NVIC_SystemReset(void)\r
{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
- while(1); /* wait until reset */\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
}\r
\r
/*@} end of CMSIS_Core_NVICFunctions */\r
\r
\r
/* ################################## SysTick function ############################################ */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
@{\r
*/\r
\r
-#if (__Vendor_SysTickConfig == 0)\r
-\r
-/** \brief System Tick Configuration\r
-\r
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
-\r
- \param [in] ticks Number of ticks between two interrupts.\r
-\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
-\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
+#if (__Vendor_SysTickConfig == 0U)\r
\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
*/\r
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
{\r
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
\r
- SysTick->LOAD = ticks - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
}\r
\r
#endif\r
\r
\r
/* ##################################### Debug In/Output function ########################################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_core_DebugFunctions ITM Functions\r
- \brief Functions that access the ITM debug interface.\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
@{\r
*/\r
\r
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/** \brief ITM Send Character\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
\r
- The function transmits a character via the ITM channel 0, and\r
- \li Just returns when no debugger is connected that has booked the output.\r
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
\r
- \param [in] ch Character to transmit.\r
-\r
- \returns Character to transmit.\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
*/\r
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
{\r
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
{\r
- while (ITM->PORT[0].u32 == 0);\r
- ITM->PORT[0].u8 = (uint8_t) ch;\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
}\r
return (ch);\r
}\r
\r
\r
-/** \brief ITM Receive Character\r
-\r
- The function inputs a character via the external variable \ref ITM_RxBuffer.\r
-\r
- \return Received character.\r
- \return -1 No character pending.\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
*/\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
int32_t ch = -1; /* no character available */\r
\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
ch = ITM_RxBuffer;\r
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
}\r
}\r
\r
\r
-/** \brief ITM Check Character\r
-\r
- The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
-\r
- \return 0 No character available.\r
- \return 1 Character available.\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
*/\r
-__STATIC_INLINE int32_t ITM_CheckChar (void) {\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
- return (0); /* no character available */\r
- } else {\r
- return (1); /* character available */\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
}\r
}\r
\r
/*@} end of CMSIS_core_DebugFunctions */\r
\r
-#endif /* __CORE_CM3_H_DEPENDANT */\r
\r
-#endif /* __CMSIS_GENERIC */\r
+\r
\r
#ifdef __cplusplus\r
}\r
#endif\r
+\r
+#endif /* __CORE_CM3_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
/*******************************************************************************\r
-* File Name: core_cm3_psoc5.h\r
-* Version 4.20\r
+* \file core_cm3_psoc5.h\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides important type information for the PSoC5. This includes types\r
-* necessary for core_cm3.h.\r
+* \brief Provides important type information for the PSoC5. This includes types\r
+* necessary for core_cm3.h.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the\r
-* System Reference Guide provided with PSoC Creator.\r
+* \note Documentation of the API's in this file is located in the\r
+* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
/**************************************************************************//**\r
* @file core_cmFunc.h\r
* @brief CMSIS Cortex-M Core Function Access Header File\r
- * @version V3.20\r
- * @date 25. February 2013\r
- *\r
- * @note\r
- *\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
******************************************************************************/\r
-/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
\r
All rights reserved.\r
Redistribution and use in source and binary forms, with or without\r
---------------------------------------------------------------------------*/\r
\r
\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
#ifndef __CORE_CMFUNC_H\r
#define __CORE_CMFUNC_H\r
\r
/** \ingroup CMSIS_Core_FunctionInterface\r
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
@{\r
- */\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#if (__ARMCC_VERSION < 400677)\r
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
-#endif\r
-\r
-/* intrinsic void __enable_irq(); */\r
-/* intrinsic void __disable_irq(); */\r
-\r
-/** \brief Get Control Register\r
-\r
- This function returns the content of the Control Register.\r
-\r
- \return Control Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_CONTROL(void)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- return(__regControl);\r
-}\r
-\r
-\r
-/** \brief Set Control Register\r
-\r
- This function writes the given value to the Control Register.\r
-\r
- \param [in] control Control Register value to set\r
- */\r
-__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- __regControl = control;\r
-}\r
-\r
-\r
-/** \brief Get IPSR Register\r
-\r
- This function returns the content of the IPSR Register.\r
-\r
- \return IPSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_IPSR(void)\r
-{\r
- register uint32_t __regIPSR __ASM("ipsr");\r
- return(__regIPSR);\r
-}\r
-\r
-\r
-/** \brief Get APSR Register\r
-\r
- This function returns the content of the APSR Register.\r
-\r
- \return APSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_APSR(void)\r
-{\r
- register uint32_t __regAPSR __ASM("apsr");\r
- return(__regAPSR);\r
-}\r
-\r
-\r
-/** \brief Get xPSR Register\r
-\r
- This function returns the content of the xPSR Register.\r
-\r
- \return xPSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_xPSR(void)\r
-{\r
- register uint32_t __regXPSR __ASM("xpsr");\r
- return(__regXPSR);\r
-}\r
-\r
-\r
-/** \brief Get Process Stack Pointer\r
-\r
- This function returns the current value of the Process Stack Pointer (PSP).\r
-\r
- \return PSP Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_PSP(void)\r
-{\r
- register uint32_t __regProcessStackPointer __ASM("psp");\r
- return(__regProcessStackPointer);\r
-}\r
-\r
-\r
-/** \brief Set Process Stack Pointer\r
-\r
- This function assigns the given value to the Process Stack Pointer (PSP).\r
-\r
- \param [in] topOfProcStack Process Stack Pointer value to set\r
- */\r
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- register uint32_t __regProcessStackPointer __ASM("psp");\r
- __regProcessStackPointer = topOfProcStack;\r
-}\r
-\r
-\r
-/** \brief Get Main Stack Pointer\r
-\r
- This function returns the current value of the Main Stack Pointer (MSP).\r
-\r
- \return MSP Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_MSP(void)\r
-{\r
- register uint32_t __regMainStackPointer __ASM("msp");\r
- return(__regMainStackPointer);\r
-}\r
-\r
-\r
-/** \brief Set Main Stack Pointer\r
-\r
- This function assigns the given value to the Main Stack Pointer (MSP).\r
-\r
- \param [in] topOfMainStack Main Stack Pointer value to set\r
- */\r
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- register uint32_t __regMainStackPointer __ASM("msp");\r
- __regMainStackPointer = topOfMainStack;\r
-}\r
-\r
-\r
-/** \brief Get Priority Mask\r
-\r
- This function returns the current state of the priority mask bit from the Priority Mask Register.\r
-\r
- \return Priority Mask value\r
- */\r
-__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- return(__regPriMask);\r
-}\r
-\r
-\r
-/** \brief Set Priority Mask\r
+*/\r
\r
- This function assigns the given value to the Priority Mask Register.\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
\r
- \param [in] priMask Priority Mask\r
- */\r
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- __regPriMask = (priMask);\r
-}\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
\r
-#if (__CORTEX_M >= 0x03)\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
\r
-/** \brief Enable FIQ\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
\r
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-#define __enable_fault_irq __enable_fiq\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
\r
-\r
-/** \brief Disable FIQ\r
-\r
- This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-#define __disable_fault_irq __disable_fiq\r
-\r
-\r
-/** \brief Get Base Priority\r
-\r
- This function returns the current value of the Base Priority register.\r
-\r
- \return Base Priority register value\r
- */\r
-__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- return(__regBasePri);\r
-}\r
-\r
-\r
-/** \brief Set Base Priority\r
-\r
- This function assigns the given value to the Base Priority register.\r
-\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- __regBasePri = (basePri & 0xff);\r
-}\r
-\r
-\r
-/** \brief Get Fault Mask\r
-\r
- This function returns the current value of the Fault Mask register.\r
-\r
- \return Fault Mask register value\r
- */\r
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- return(__regFaultMask);\r
-}\r
-\r
-\r
-/** \brief Set Fault Mask\r
-\r
- This function assigns the given value to the Fault Mask register.\r
-\r
- \param [in] faultMask Fault Mask value to set\r
- */\r
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- __regFaultMask = (faultMask & (uint32_t)1);\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-#if (__CORTEX_M == 0x04)\r
-\r
-/** \brief Get FPSCR\r
-\r
- This function returns the current value of the Floating Point Status/Control register.\r
-\r
- \return Floating Point Status/Control register value\r
- */\r
-__STATIC_INLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- register uint32_t __regfpscr __ASM("fpscr");\r
- return(__regfpscr);\r
-#else\r
- return(0);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Set FPSCR\r
-\r
- This function assigns the given value to the Floating Point Status/Control register.\r
-\r
- \param [in] fpscr Floating Point Status/Control value to set\r
- */\r
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- register uint32_t __regfpscr __ASM("fpscr");\r
- __regfpscr = (fpscr);\r
-#endif\r
-}\r
-\r
-#endif /* (__CORTEX_M == 0x04) */\r
-\r
-\r
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#include <cmsis_iar.h>\r
-\r
-\r
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
-/* TI CCS specific functions */\r
-\r
-#include <cmsis_ccs.h>\r
-\r
-\r
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-/** \brief Enable IRQ Interrupts\r
-\r
- This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
-{\r
- __ASM volatile ("cpsie i" : : : "memory");\r
-}\r
-\r
-\r
-/** \brief Disable IRQ Interrupts\r
-\r
- This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
-{\r
- __ASM volatile ("cpsid i" : : : "memory");\r
-}\r
-\r
-\r
-/** \brief Get Control Register\r
-\r
- This function returns the content of the Control Register.\r
-\r
- \return Control Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, control" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Control Register\r
-\r
- This function writes the given value to the Control Register.\r
-\r
- \param [in] control Control Register value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
-}\r
-\r
-\r
-/** \brief Get IPSR Register\r
-\r
- This function returns the content of the IPSR Register.\r
-\r
- \return IPSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Get APSR Register\r
-\r
- This function returns the content of the APSR Register.\r
-\r
- \return APSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Get xPSR Register\r
-\r
- This function returns the content of the xPSR Register.\r
-\r
- \return xPSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Get Process Stack Pointer\r
-\r
- This function returns the current value of the Process Stack Pointer (PSP).\r
-\r
- \return PSP Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Process Stack Pointer\r
-\r
- This function assigns the given value to the Process Stack Pointer (PSP).\r
-\r
- \param [in] topOfProcStack Process Stack Pointer value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");\r
-}\r
-\r
-\r
-/** \brief Get Main Stack Pointer\r
-\r
- This function returns the current value of the Main Stack Pointer (MSP).\r
-\r
- \return MSP Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Main Stack Pointer\r
-\r
- This function assigns the given value to the Main Stack Pointer (MSP).\r
-\r
- \param [in] topOfMainStack Main Stack Pointer value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");\r
-}\r
-\r
-\r
-/** \brief Get Priority Mask\r
-\r
- This function returns the current state of the priority mask bit from the Priority Mask Register.\r
-\r
- \return Priority Mask value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Priority Mask\r
-\r
- This function assigns the given value to the Priority Mask Register.\r
-\r
- \param [in] priMask Priority Mask\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
-}\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Enable FIQ\r
-\r
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsie f" : : : "memory");\r
-}\r
-\r
-\r
-/** \brief Disable FIQ\r
-\r
- This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsid f" : : : "memory");\r
-}\r
-\r
-\r
-/** \brief Get Base Priority\r
-\r
- This function returns the current value of the Base Priority register.\r
-\r
- \return Base Priority register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Base Priority\r
-\r
- This function assigns the given value to the Base Priority register.\r
-\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
-}\r
-\r
-\r
-/** \brief Get Fault Mask\r
-\r
- This function returns the current value of the Fault Mask register.\r
-\r
- \return Fault Mask register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Fault Mask\r
-\r
- This function assigns the given value to the Fault Mask register.\r
-\r
- \param [in] faultMask Fault Mask value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-#if (__CORTEX_M == 0x04)\r
-\r
-/** \brief Get FPSCR\r
-\r
- This function returns the current value of the Floating Point Status/Control register.\r
-\r
- \return Floating Point Status/Control register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- uint32_t result;\r
-\r
- /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("");\r
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
- __ASM volatile ("");\r
- return(result);\r
-#else\r
- return(0);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Set FPSCR\r
-\r
- This function assigns the given value to the Floating Point Status/Control register.\r
-\r
- \param [in] fpscr Floating Point Status/Control value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("");\r
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
- __ASM volatile ("");\r
-#endif\r
-}\r
-\r
-#endif /* (__CORTEX_M == 0x04) */\r
-\r
-\r
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
\r
#endif\r
\r
/*@} end of CMSIS_Core_RegAccFunctions */\r
\r
-\r
#endif /* __CORE_CMFUNC_H */\r
/**************************************************************************//**\r
* @file core_cmInstr.h\r
* @brief CMSIS Cortex-M Core Instruction Access Header File\r
- * @version V3.20\r
- * @date 05. March 2013\r
- *\r
- * @note\r
- *\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
******************************************************************************/\r
-/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
\r
All rights reserved.\r
Redistribution and use in source and binary forms, with or without\r
---------------------------------------------------------------------------*/\r
\r
\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
#ifndef __CORE_CMINSTR_H\r
#define __CORE_CMINSTR_H\r
\r
@{\r
*/\r
\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#if (__ARMCC_VERSION < 400677)\r
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
-#endif\r
-\r
-\r
-/** \brief No Operation\r
-\r
- No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-#define __NOP __nop\r
-\r
-\r
-/** \brief Wait For Interrupt\r
-\r
- Wait For Interrupt is a hint instruction that suspends execution\r
- until one of a number of events occurs.\r
- */\r
-#define __WFI __wfi\r
-\r
-\r
-/** \brief Wait For Event\r
-\r
- Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-#define __WFE __wfe\r
-\r
-\r
-/** \brief Send Event\r
-\r
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-#define __SEV __sev\r
-\r
-\r
-/** \brief Instruction Synchronization Barrier\r
-\r
- Instruction Synchronization Barrier flushes the pipeline in the processor,\r
- so that all instructions following the ISB are fetched from cache or\r
- memory, after the instruction has been completed.\r
- */\r
-#define __ISB() __isb(0xF)\r
-\r
-\r
-/** \brief Data Synchronization Barrier\r
-\r
- This function acts as a special kind of Data Memory Barrier.\r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-#define __DSB() __dsb(0xF)\r
-\r
-\r
-/** \brief Data Memory Barrier\r
-\r
- This function ensures the apparent order of the explicit memory operations before\r
- and after the instruction, without ensuring their completion.\r
- */\r
-#define __DMB() __dmb(0xF)\r
-\r
-\r
-/** \brief Reverse byte order (32 bit)\r
-\r
- This function reverses the byte order in integer value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#define __REV __rev\r
-\r
-\r
-/** \brief Reverse byte order (16 bit)\r
-\r
- This function reverses the byte order in two unsigned short values.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
-{\r
- rev16 r0, r0\r
- bx lr\r
-}\r
-#endif\r
-\r
-/** \brief Reverse byte order in signed short value\r
-\r
- This function reverses the byte order in a signed short value with sign extension to integer.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
-{\r
- revsh r0, r0\r
- bx lr\r
-}\r
-#endif\r
-\r
-\r
-/** \brief Rotate Right in unsigned value (32 bit)\r
-\r
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
-\r
- \param [in] value Value to rotate\r
- \param [in] value Number of Bits to rotate\r
- \return Rotated value\r
- */\r
-#define __ROR __ror\r
-\r
-\r
-/** \brief Breakpoint\r
-\r
- This function causes the processor to enter Debug state.\r
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
-\r
- \param [in] value is ignored by the processor.\r
- If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value) __breakpoint(value)\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Reverse bit order of value\r
-\r
- This function reverses the bit order of the given value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#define __RBIT __rbit\r
-\r
-\r
-/** \brief LDR Exclusive (8 bit)\r
-\r
- This function performs a exclusive LDR command for 8 bit value.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
-\r
-\r
-/** \brief LDR Exclusive (16 bit)\r
-\r
- This function performs a exclusive LDR command for 16 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
-\r
-\r
-/** \brief LDR Exclusive (32 bit)\r
-\r
- This function performs a exclusive LDR command for 32 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
-\r
-\r
-/** \brief STR Exclusive (8 bit)\r
-\r
- This function performs a exclusive STR command for 8 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXB(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief STR Exclusive (16 bit)\r
-\r
- This function performs a exclusive STR command for 16 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXH(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief STR Exclusive (32 bit)\r
-\r
- This function performs a exclusive STR command for 32 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXW(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief Remove the exclusive lock\r
-\r
- This function removes the exclusive lock which is created by LDREX.\r
-\r
- */\r
-#define __CLREX __clrex\r
-\r
-\r
-/** \brief Signed Saturate\r
-\r
- This function saturates a signed value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-#define __SSAT __ssat\r
-\r
-\r
-/** \brief Unsigned Saturate\r
-\r
- This function saturates an unsigned value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT __usat\r
-\r
-\r
-/** \brief Count leading zeros\r
-\r
- This function counts the number of leading zeros of a data value.\r
-\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-#define __CLZ __clz\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-\r
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#include <cmsis_iar.h>\r
-\r
-\r
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
-/* TI CCS specific functions */\r
-\r
-#include <cmsis_ccs.h>\r
-\r
-\r
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-/* Define macros for porting to both thumb1 and thumb2.\r
- * For thumb1, use low register (r0-r7), specified by constrant "l"\r
- * Otherwise, use general registers, specified by constrant "r" */\r
-#if defined (__thumb__) && !defined (__thumb2__)\r
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
-#else\r
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
-#endif\r
-\r
-/** \brief No Operation\r
-\r
- No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)\r
-{\r
- __ASM volatile ("nop");\r
-}\r
-\r
-\r
-/** \brief Wait For Interrupt\r
-\r
- Wait For Interrupt is a hint instruction that suspends execution\r
- until one of a number of events occurs.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)\r
-{\r
- __ASM volatile ("wfi");\r
-}\r
-\r
-\r
-/** \brief Wait For Event\r
-\r
- Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)\r
-{\r
- __ASM volatile ("wfe");\r
-}\r
-\r
-\r
-/** \brief Send Event\r
-\r
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)\r
-{\r
- __ASM volatile ("sev");\r
-}\r
-\r
-\r
-/** \brief Instruction Synchronization Barrier\r
-\r
- Instruction Synchronization Barrier flushes the pipeline in the processor,\r
- so that all instructions following the ISB are fetched from cache or\r
- memory, after the instruction has been completed.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)\r
-{\r
- __ASM volatile ("isb");\r
-}\r
-\r
-\r
-/** \brief Data Synchronization Barrier\r
-\r
- This function acts as a special kind of Data Memory Barrier.\r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)\r
-{\r
- __ASM volatile ("dsb");\r
-}\r
-\r
-\r
-/** \brief Data Memory Barrier\r
-\r
- This function ensures the apparent order of the explicit memory operations before\r
- and after the instruction, without ensuring their completion.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)\r
-{\r
- __ASM volatile ("dmb");\r
-}\r
-\r
-\r
-/** \brief Reverse byte order (32 bit)\r
-\r
- This function reverses the byte order in integer value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
- return __builtin_bswap32(value);\r
-#else\r
- uint32_t result;\r
-\r
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Reverse byte order (16 bit)\r
-\r
- This function reverses the byte order in two unsigned short values.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Reverse byte order in signed short value\r
-\r
- This function reverses the byte order in a signed short value with sign extension to integer.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- return (short)__builtin_bswap16(value);\r
-#else\r
- uint32_t result;\r
-\r
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Rotate Right in unsigned value (32 bit)\r
-\r
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
-\r
- \param [in] value Value to rotate\r
- \param [in] value Number of Bits to rotate\r
- \return Rotated value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
-{\r
- return (op1 >> op2) | (op1 << (32 - op2));\r
-}\r
-\r
-\r
-/** \brief Breakpoint\r
-\r
- This function causes the processor to enter Debug state.\r
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
-\r
- \param [in] value is ignored by the processor.\r
- If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Reverse bit order of value\r
-\r
- This function reverses the bit order of the given value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (8 bit)\r
-\r
- This function performs a exclusive LDR command for 8 bit value.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (16 bit)\r
-\r
- This function performs a exclusive LDR command for 16 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (32 bit)\r
-\r
- This function performs a exclusive LDR command for 32 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (8 bit)\r
-\r
- This function performs a exclusive STR command for 8 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (16 bit)\r
-\r
- This function performs a exclusive STR command for 16 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (32 bit)\r
-\r
- This function performs a exclusive STR command for 32 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Remove the exclusive lock\r
-\r
- This function removes the exclusive lock which is created by LDREX.\r
-\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)\r
-{\r
- __ASM volatile ("clrex" ::: "memory");\r
-}\r
-\r
-\r
-/** \brief Signed Saturate\r
-\r
- This function saturates a signed value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-#define __SSAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/** \brief Unsigned Saturate\r
-\r
- This function saturates an unsigned value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/** \brief Count leading zeros\r
-\r
- This function counts the number of leading zeros of a data value.\r
-\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-\r
-\r
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all intrinsics,\r
- * Including the CMSIS ones.\r
- */\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
\r
#endif\r
\r
-/*******************************************************************************\r
-* File Name: cyPm.c\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file cyPm.c\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides an API for the power management.\r
+* \brief Provides an API for the power management.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the\r
+* \note Documentation of the API's in this file is located in the\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#include "cyPm.h"\r
\r
\r
+\r
/*******************************************************************\r
* Place your includes, defines, and code here. Do not use the merge\r
* region below unless any component datasheet suggests doing so.\r
\r
/*******************************************************************************\r
* Function Name: CyPmSaveClocks\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function is called in preparation for entering sleep or hibernate low\r
* power modes. Saves all the states of the clocking system that do not persist\r
* during sleep/hibernate or that need to be altered in preparation for\r
* must be set manually to another source before using the\r
* CyPmSaveClocks()/CyPmRestoreClocks() functions.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* All peripheral clocks are going to be off after this API method call.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyPmRestoreClocks\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Restores any state that was preserved by the last call to CyPmSaveClocks().\r
* The Flash wait state setting is also restored.\r
*\r
* The 130 ms is given for the megahertz crystal to stabilize. Its readiness is\r
* not verified after a hold-off timeout.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyPmRestoreClocks(void) \r
{\r
/* `#START_MHZ_ECO_TIMEOUT` */\r
\r
/* `#END` */\r
+\r
+ #ifdef CY_BOOT_CY_PM_RESTORE_CLOCKS_ECO_TIMEOUT_CALLBACK\r
+ CyBoot_CyPmRestoreClocks_EcoTimeout_Callback();\r
+ #endif /* CY_BOOT_CY_PM_RESTORE_CLOCKS_ECO_TIMEOUT_CALLBACK */\r
}\r
} /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */\r
\r
\r
- /* Temprorary set maximum flash wait cycles */\r
+ /* Temporary set maximum flash wait cycles */\r
CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES);\r
\r
/* XTAL and DSI clocks are ready to be source for Master clock. */\r
/* `#START_PLL_TIMEOUT` */\r
\r
/* `#END` */\r
+\r
+ #ifdef CY_BOOT_CY_PM_RESTORE_CLOCKS_PLL_TIMEOUT_CALLBACK\r
+ CyBoot_CyPmRestoreClocks_PllTimeout_Callback();\r
+ #endif /* CY_BOOT_CY_PM_RESTORE_CLOCKS_PLL_TIMEOUT_CALLBACK */\r
}\r
} /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */\r
\r
\r
/*******************************************************************************\r
* Function Name: CyPmAltAct\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Puts the part into the Alternate Active (Standby) state. The Alternate Active\r
* state can allow for any of the capabilities of the device to be active, but\r
* the operation of this function is dependent on the CPU being disabled during\r
* PM_ALT_ACT_SRC_NONE) is called and PICU interrupt occurs, the CPU will be\r
* started while device remains in Alternate Active mode.\r
*\r
-* Parameters:\r
-* wakeupTime: Specifies a timer wakeup source and the frequency of that\r
+* \param wakeupTime: Specifies a timer wakeup source and the frequency of that\r
* source. For PSoC 5LP this parameter is ignored.\r
*\r
* Define Time\r
* PM_ALT_ACT_TIME_NONE None\r
-* PM_ALT_ACT_TIME_ONE_PPS One PPS: 1 second\r
-* PM_ALT_ACT_TIME_CTW_2MS CTW: 2 ms\r
-* PM_ALT_ACT_TIME_CTW_4MS CTW: 4 ms\r
-* PM_ALT_ACT_TIME_CTW_8MS CTW: 8 ms\r
-* PM_ALT_ACT_TIME_CTW_16MS CTW: 16 ms\r
-* PM_ALT_ACT_TIME_CTW_32MS CTW: 32 ms\r
-* PM_ALT_ACT_TIME_CTW_64MS CTW: 64 ms\r
-* PM_ALT_ACT_TIME_CTW_128MS CTW: 128 ms\r
-* PM_ALT_ACT_TIME_CTW_256MS CTW: 256 ms\r
-* PM_ALT_ACT_TIME_CTW_512MS CTW: 512 ms\r
-* PM_ALT_ACT_TIME_CTW_1024MS CTW: 1024 ms\r
-* PM_ALT_ACT_TIME_CTW_2048MS CTW: 2048 ms\r
-* PM_ALT_ACT_TIME_CTW_4096MS CTW: 4096 ms\r
+* \param PM_ALT_ACT_TIME_ONE_PPS One PPS: 1 second\r
+* \param PM_ALT_ACT_TIME_CTW_2MS CTW: 2 ms\r
+* \param PM_ALT_ACT_TIME_CTW_4MS CTW: 4 ms\r
+* \param PM_ALT_ACT_TIME_CTW_8MS CTW: 8 ms\r
+* \param PM_ALT_ACT_TIME_CTW_16MS CTW: 16 ms\r
+* \param PM_ALT_ACT_TIME_CTW_32MS CTW: 32 ms\r
+* \param PM_ALT_ACT_TIME_CTW_64MS CTW: 64 ms\r
+* \param PM_ALT_ACT_TIME_CTW_128MS CTW: 128 ms\r
+* \param PM_ALT_ACT_TIME_CTW_256MS CTW: 256 ms\r
+* \param PM_ALT_ACT_TIME_CTW_512MS CTW: 512 ms\r
+* \param PM_ALT_ACT_TIME_CTW_1024MS CTW: 1024 ms\r
+* \param PM_ALT_ACT_TIME_CTW_2048MS CTW: 2048 ms\r
+* \param PM_ALT_ACT_TIME_CTW_4096MS CTW: 4096 ms\r
* PM_ALT_ACT_TIME_FTW(1-256)* FTW: 10us to 2.56 ms\r
*\r
-* *Note: PM_ALT_ACT_TIME_FTW() is a macro that takes an argument that\r
+* \param *Note: PM_ALT_ACT_TIME_FTW() is a macro that takes an argument that\r
* specifies how many increments of 10 us to delay.\r
For PSoC 3 silicon the valid range of values is 1 to 256.\r
*\r
-* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if\r
-* a wakeupTime has been specified, the associated timer will be\r
-* included as a wakeup source.\r
+* \param wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if\r
+* a wakeupTime has been specified, the associated timer will\r
+* be included as a wakeup source.\r
*\r
* Define Source\r
* PM_ALT_ACT_SRC_NONE None\r
* PM_ALT_ACT_SRC_ONE_PPS One PPS**\r
* PM_ALT_ACT_SRC_LCD LCD\r
*\r
-* *Note : FTW and HVI/LVI wakeup signals are in the same mask bit.\r
-* **Note: CTW and One PPS wakeup signals are in the same mask bit.\r
+* \param *Note : FTW and HVI/LVI wakeup signals are in the same mask bit.\r
+* \param **Note: CTW and One PPS wakeup signals are in the same mask bit.\r
*\r
* When specifying a Comparator as the wakeupSource, an instance specific define\r
* that will track with the specific comparator that the instance\r
-* is placed into should be used. As an example, for a Comparator instance named MyComp the\r
-* value to OR into the mask is: MyComp_ctComp__CMP_MASK.\r
+* is placed into should be used. As an example, for a Comparator instance named\r
+* \param MyComp the value to OR into the mask is: MyComp_ctComp__CMP_MASK.\r
*\r
* When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus()\r
* function must be called upon wakeup with a corresponding parameter. Please\r
* refer to the CyPmReadStatus() API in the System Reference Guide for more\r
* information.\r
*\r
-* Return:\r
-* None\r
-*\r
* Reentrant:\r
* No\r
*\r
-* Side Effects:\r
+* \sideeffect\r
* If a wakeupTime other than NONE is specified, then upon exit the state of the\r
* specified timer will be left as specified by wakeupTime with the timer\r
* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is\r
\r
/*******************************************************************************\r
* Function Name: CyPmSleep\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Puts the part into the Sleep state.\r
*\r
* Note Before calling this function, you must manually configure the power\r
* intervals and RTC for 1PPS interval. The component must be configured to\r
* generate interrupt.\r
*\r
-* Parameters:\r
-* wakeupTime: Specifies a timer wakeup source and the frequency of that\r
+* \param wakeupTime: Specifies a timer wakeup source and the frequency of that\r
* source. For PSoC 5LP, this parameter is ignored.\r
*\r
* Define Time\r
* PM_SLEEP_TIME_NONE None\r
-* PM_SLEEP_TIME_ONE_PPS One PPS: 1 second\r
-* PM_SLEEP_TIME_CTW_2MS CTW: 2 ms\r
-* PM_SLEEP_TIME_CTW_4MS CTW: 4 ms\r
-* PM_SLEEP_TIME_CTW_8MS CTW: 8 ms\r
-* PM_SLEEP_TIME_CTW_16MS CTW: 16 ms\r
-* PM_SLEEP_TIME_CTW_32MS CTW: 32 ms\r
-* PM_SLEEP_TIME_CTW_64MS CTW: 64 ms\r
-* PM_SLEEP_TIME_CTW_128MS CTW: 128 ms\r
-* PM_SLEEP_TIME_CTW_256MS CTW: 256 ms\r
-* PM_SLEEP_TIME_CTW_512MS CTW: 512 ms\r
-* PM_SLEEP_TIME_CTW_1024MS CTW: 1024 ms\r
-* PM_SLEEP_TIME_CTW_2048MS CTW: 2048 ms\r
-* PM_SLEEP_TIME_CTW_4096MS CTW: 4096 ms\r
-*\r
-* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if\r
+* \param PM_SLEEP_TIME_ONE_PPS One PPS: 1 second\r
+* \param PM_SLEEP_TIME_CTW_2MS CTW: 2 ms\r
+* \param PM_SLEEP_TIME_CTW_4MS CTW: 4 ms\r
+* \param PM_SLEEP_TIME_CTW_8MS CTW: 8 ms\r
+* \param PM_SLEEP_TIME_CTW_16MS CTW: 16 ms\r
+* \param PM_SLEEP_TIME_CTW_32MS CTW: 32 ms\r
+* \param PM_SLEEP_TIME_CTW_64MS CTW: 64 ms\r
+* \param PM_SLEEP_TIME_CTW_128MS CTW: 128 ms\r
+* \param PM_SLEEP_TIME_CTW_256MS CTW: 256 ms\r
+* \param PM_SLEEP_TIME_CTW_512MS CTW: 512 ms\r
+* \param PM_SLEEP_TIME_CTW_1024MS CTW: 1024 ms\r
+* \param PM_SLEEP_TIME_CTW_2048MS CTW: 2048 ms\r
+* \param PM_SLEEP_TIME_CTW_4096MS CTW: 4096 ms\r
+*\r
+* \param wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if\r
* a wakeupTime has been specified the associated timer will be\r
* included as a wakeup source.\r
*\r
* PM_SLEEP_SRC_ONE_PPS One PPS*\r
* PM_SLEEP_SRC_LCD LCD\r
*\r
-* *Note: CTW and One PPS wakeup signals are in the same mask bit.\r
+* \param *Note: CTW and One PPS wakeup signals are in the same mask bit.\r
*\r
* When specifying a Comparator as the wakeupSource an instance specific define\r
* should be used that will track with the specific comparator that the instance\r
* is placed into. As an example for a Comparator instance named MyComp the\r
-* value to OR into the mask is: MyComp_ctComp__CMP_MASK.\r
+* \param value to OR into the mask is: MyComp_ctComp__CMP_MASK.\r
*\r
* When CTW or One PPS is used as a wakeup source, the CyPmReadStatus()\r
* function must be called upon wakeup with corresponding parameter. Please\r
* refer to the CyPmReadStatus() API in the System Reference Guide for more\r
* information.\r
*\r
-* Return:\r
-* None\r
-*\r
* Reentrant:\r
* No\r
*\r
\r
/* `#END` */\r
\r
+ #ifdef CY_BOOT_CY_PM_SLEEP_BEFORE_SLEEP_CALLBACK\r
+ CyBoot_CyPmSleep_BeforeSleep_Callback();\r
+ #endif /* CY_BOOT_CY_PM_SLEEP_BEFORE_SLEEP_CALLBACK */\r
\r
/* Last moment IMO frequency change */\r
if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK))\r
\r
/* `#END` */\r
\r
+ #ifdef CY_BOOT_CY_PM_SLEEP_AFTER_SLEEP_CALLBACK\r
+ CyBoot_CyPmSleep_AfterSleep_Callback();\r
+ #endif /* CY_BOOT_CY_PM_SLEEP_AFTER_SLEEP_CALLBACK */\r
\r
/* Restore hardware configuration */\r
CyPmHibSlpRestore();\r
\r
/*******************************************************************************\r
* Function Name: CyPmHibernate\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Puts the part into the Hibernate state.\r
*\r
-* PSoC 3 and PSoC 5LP:\r
* Before switching to Hibernate, the current status of the PICU wakeup source\r
* bit is saved and then set. This configures the device to wake up from the\r
* PICU. Make sure you have at least one pin configured to generate PICU\r
* option. Once the wakeup occurs, the PICU wakeup source bit is restored and\r
* the PSoC returns to the Active state.\r
*\r
-* Parameters:\r
-* None\r
+* Reentrant:\r
+* No\r
+*\r
+* \sideeffect\r
+* Applications must wait 20 us before re-entering hibernate or sleep after\r
+* waking up from hibernate. The 20 us allows the sleep regulator time to\r
+* stabilize before the next hibernate / sleep event occurs. The 20 us\r
+* requirement begins when the device wakes up. There is no hardware check that\r
+* this requirement is met. The specified delay should be done on ISR entry.\r
*\r
-* Return:\r
-* None\r
+* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin\r
+* is instance name of the Pins component) function must be called to clear the\r
+* latched pin events to allow the proper Hibernate mode entry and to enable\r
+* detection of future events.\r
+*\r
+* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to\r
+* measure Hibernate/Sleep regulator settling time after a reset. The holdoff\r
+* delay is measured using the rising edges of the 1 kHz ILO.\r
+*\r
+*******************************************************************************/\r
+void CyPmHibernate(void) \r
+{\r
+ CyPmHibernateEx(CY_PM_HIB_SRC_PICU);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmHibernateEx\r
+****************************************************************************//**\r
+*\r
+* Puts the part into the Hibernate state.\r
+*\r
+* The following wake up sources can be configured: PICU interrupt, Comparator0,\r
+* Comparator1, Comparator2, and Comparator3 output.\r
+*\r
+* Before switching to Hibernate, the current status of the PICU wakeup source\r
+* bit is saved and then set.\r
+*\r
+* If using PICU as the wake up source, make sure you have at least one pin\r
+* configured to generate a PICU interrupt. For pin Px.y, the register\r
+* "PICU_INTTYPE_PICUx_INTTYPEy" controls the PICU behavior. In the TRM, this\r
+* register is "PICU[0..15]_INTTYPE[0..7]." In the Pins component datasheet,\r
+* this register is referred to as the IRQ option. Once the wakeup occurs, the\r
+* PICU wakeup source bit is restored and the PSoC returns to the Active state.\r
+*\r
+* If using a comparator as the wake up source, make sure you call this function\r
+* with the 'wakeupSource' parameter set to the appropriate comparator. The part\r
+* is configured for the requested wakeup source by setting the corresponding\r
+* bits in PM_WAKEUP_CFG1 register.\r
+*\r
+* Function call CyPmHibernateEx(CY_PM_HIB_SRC_PICU) will act in the same way as\r
+* CyPmHibernate().\r
+*\r
+* \param wakeupSource:\r
+* Parameter Value Description\r
+* CY_PM_HIB_SRC_PICU PICU interrupt is set as the wake up source.\r
+* CY_PM_HIB_SRC_COMPARATOR0 Comparator 0 is set as the wake up source.\r
+* CY_PM_HIB_SRC_COMPARATOR1 Comparator 1 is set as the wake up source.\r
+* CY_PM_HIB_SRC_COMPARATOR2 Comparator 2 is set as the wake up source.\r
+* CY_PM_HIB_SRC_COMPARATOR3 Comparator 3 is set as the wake up source.\r
*\r
* Reentrant:\r
* No\r
*\r
-* Side Effects:\r
+* \sideeffect\r
* Applications must wait 20 us before re-entering hibernate or sleep after\r
* waking up from hibernate. The 20 us allows the sleep regulator time to\r
* stabilize before the next hibernate / sleep event occurs. The 20 us\r
* requirement begins when the device wakes up. There is no hardware check that\r
* this requirement is met. The specified delay should be done on ISR entry.\r
*\r
-* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is\r
-* instance name of the Pins component) function must be called to clear the\r
+* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin\r
+* is instance name of the Pins component) function must be called to clear the\r
* latched pin events to allow the proper Hibernate mode entry and to enable\r
* detection of future events.\r
*\r
* delay is measured using the rising edges of the 1 kHz ILO.\r
*\r
*******************************************************************************/\r
-void CyPmHibernate(void) \r
+void CyPmHibernateEx(uint16 wakeupSource) \r
{\r
uint8 interruptState;\r
\r
CyPmHibSaveSet();\r
\r
\r
+ /* Save and set new wake up configuration */\r
+\r
/* Save and enable only wakeup on PICU */\r
cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG;\r
- CY_PM_WAKEUP_CFG0_REG = CY_PM_WAKEUP_PICU;\r
+ CY_PM_WAKEUP_CFG0_REG = ((uint8) (wakeupSource >> 4u) & CY_PM_WAKEUP_PICU);\r
\r
+ /* Comparators */\r
cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG;\r
- CY_PM_WAKEUP_CFG1_REG = 0x00u;\r
+ CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK);\r
\r
cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG;\r
CY_PM_WAKEUP_CFG2_REG = 0x00u;\r
\r
/*******************************************************************************\r
* Function Name: CyPmReadStatus\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Manages the Power Manager Interrupt Status Register. This register has the\r
* interrupt status for the one pulse per second, central timewheel and fast\r
* timewheel timers. This hardware register clears on read. To allow for only\r
* Note You must call this function within 1 ms (1 clock cycle of the ILO)\r
* after a CTW event has occurred.\r
*\r
-* Parameters:\r
-* mask: Bits in the shadow register to clear.\r
+* \param mask: Bits in the shadow register to clear.\r
*\r
* Define Source\r
* CY_PM_FTW_INT Fast Timewheel\r
* CY_PM_CTW_INT Central Timewheel\r
* CY_PM_ONEPPS_INT One Pulse Per Second\r
*\r
-* Return:\r
+* \return\r
* Status. Same bits values as the mask parameter.\r
*\r
*******************************************************************************/\r
\r
/* Save value of register, copy it and clear desired bit */\r
interruptStatus |= CY_PM_INT_SR_REG;\r
- tmpStatus = interruptStatus;\r
+ tmpStatus = interruptStatus & (CY_PM_FTW_INT | CY_PM_CTW_INT | CY_PM_ONEPPS_INT);\r
interruptStatus &= ((uint8)(~mask));\r
\r
/* Exit critical section */\r
\r
/*******************************************************************************\r
* Function Name: CyPmHibSaveSet\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Prepare device for proper Hibernate low power mode entry:\r
* - Disables I2C backup regulator\r
* - Saves ILO power down mode state and enable it\r
* - Save LVI/HVI configuration and disable them - CyPmHviLviSaveDisable()\r
* - CyPmHibSlpSaveSet() function is called\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
* Reentrant:\r
* No\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyPmHibRestore\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Restores the device for the proper Hibernate mode exit:\r
* - Restores LVI/HVI configuration - calsl CyPmHviLviRestore()\r
* - CyPmHibSlpSaveRestore() function is called\r
* - Restores the state of 1 kHz and 100 kHz ILO and disables them\r
* - Restores the sleep regulator settings\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
static void CyPmHibRestore(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyPmCtwSetInterval\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Performs the CTW configuration:\r
* - Disables the CTW interrupt\r
* - Enables 1 kHz ILO\r
* - Sets a new CTW interval\r
*\r
-* Parameters:\r
-* ctwInterval: the CTW interval to be set.\r
+* \param ctwInterval: the CTW interval to be set.\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* Enables ILO 1 KHz clock and leaves it enabled.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyPmOppsSet\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Performs 1PPS configuration:\r
* - Starts 32 KHz XTAL\r
* - Disables 1PPS interrupts\r
* - Enables 1PPS\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyPmOppsSet(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyPmFtwSetInterval\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Performs the FTW configuration:\r
* - Disables the FTW interrupt\r
* - Enables 100 kHz ILO\r
* - Sets a new FTW interval.\r
*\r
-* Parameters:\r
-* ftwInterval - FTW counter interval.\r
+* \param ftwInterval The FTW counter interval.\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* Enables the ILO 100 KHz clock and leaves it enabled.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyPmHibSlpSaveSet\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* This API is used for preparing the device for the Sleep and Hibernate low power\r
-* modes entry:\r
+* This API is used for preparing the device for the Sleep and Hibernate low\r
+* power modes entry:\r
* - Saves the COMP, VIDAC, DSM, and SAR routing connections (PSoC 5)\r
* - Saves the SC/CT routing connections (PSoC 3/5/5LP)\r
* - Disables the Serial Wire Viewer (SWV) (PSoC 3)\r
* - Saves the boost reference selection and sets it to internal\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
* Reentrant:\r
* No\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyPmHibSlpRestore\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* This API is used for restoring the device configurations after wakeup from the Sleep\r
-* and Hibernate low power modes:\r
+* This API is used for restoring the device configurations after wakeup from\r
+* the Sleep and Hibernate low power modes:\r
* - Restores the SC/CT routing connections\r
* - Restores the enable state of the Serial Wire Viewer (SWV) (PSoC 3)\r
* - Restores the boost reference selection\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
static void CyPmHibSlpRestore(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyPmHviLviSaveDisable\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Saves analog and digital LVI and HVI configuration and disables them.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
* Reentrant:\r
* No\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyPmHviLviRestore\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Restores the analog and digital LVI and HVI configuration.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
* Reentrant:\r
* No\r
*\r
-/*******************************************************************************\r
-* File Name: cyPm.h\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file cyPm.h\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides the function definitions for the power management API.\r
+* \brief Provides the function definitions for the power management API.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the\r
+* \note Documentation of the API's in this file is located in the\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) ;\r
void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) ;\r
void CyPmHibernate(void) ;\r
+void CyPmHibernateEx(uint16 wakeupSource) ;\r
\r
uint8 CyPmReadStatus(uint8 mask) ;\r
\r
#define PM_SLEEP_SRC_ONE_PPS (0x0800u)\r
#define PM_SLEEP_SRC_LCD (0x1000u)\r
\r
+/* Wake up sources for Hibernate mode */\r
+#define CY_PM_HIB_SRC_PICU (0x0040u)\r
+#define CY_PM_HIB_SRC_COMPARATOR0 (0x0001u)\r
+#define CY_PM_HIB_SRC_COMPARATOR1 (0x0002u)\r
+#define CY_PM_HIB_SRC_COMPARATOR2 (0x0004u)\r
+#define CY_PM_HIB_SRC_COMPARATOR3 (0x0008u)\r
+\r
/* Wake up sources for Alternate Active mode */\r
#define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u)\r
#define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u)\r
#if defined(__ARMCC_VERSION) /* Instristic for Keil compilers */\r
#define CY_PM_WFI __wfi()\r
#else /* ASM for GCC & IAR */\r
- #define CY_PM_WFI asm volatile ("WFI \n")\r
+ #define CY_PM_WFI __asm volatile ("WFI \n")\r
#endif /* (__ARMCC_VERSION) */\r
\r
#else\r
/*******************************************************************************\r
* File Name: cydevice.h\r
* OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator 3.3\r
+* PSoC Creator 4.0 Update 1\r
*\r
* Description:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: cydevice_trm.h\r
* \r
-* PSoC Creator 3.3\r
+* PSoC Creator 4.0 Update 1\r
*\r
* Description:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: cydevicegnu.inc\r
* OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator 3.3\r
+* PSoC Creator 4.0 Update 1\r
*\r
* Description:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: cydevicegnu_trm.inc\r
* \r
-* PSoC Creator 3.3\r
+* PSoC Creator 4.0 Update 1\r
*\r
* Description:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
;\r
; File Name: cydeviceiar.inc\r
; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator 3.3\r
+; PSoC Creator 4.0 Update 1\r
;\r
; Description:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
;\r
; File Name: cydeviceiar_trm.inc\r
; \r
-; PSoC Creator 3.3\r
+; PSoC Creator 4.0 Update 1\r
;\r
; Description:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
;\r
; File Name: cydevicerv.inc\r
; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator 3.3\r
+; PSoC Creator 4.0 Update 1\r
;\r
; Description:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
;\r
; File Name: cydevicerv_trm.inc\r
; \r
-; PSoC Creator 3.3\r
+; PSoC Creator 4.0 Update 1\r
;\r
; Description:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
#define LED1__0__MASK 0x08u\r
#define LED1__0__PC CYREG_PRT12_PC3\r
#define LED1__0__PORT 12u\r
-#define LED1__0__SHIFT 3\r
+#define LED1__0__SHIFT 3u\r
#define LED1__AG CYREG_PRT12_AG\r
#define LED1__BIE CYREG_PRT12_BIE\r
#define LED1__BIT_MASK CYREG_PRT12_BIT_MASK\r
#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
#define LED1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
#define LED1__PS CYREG_PRT12_PS\r
-#define LED1__SHIFT 3\r
+#define LED1__SHIFT 3u\r
#define LED1__SIO_CFG CYREG_PRT12_SIO_CFG\r
#define LED1__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
#define LED1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
#define SD_CD__0__MASK 0x40u\r
#define SD_CD__0__PC CYREG_PRT3_PC6\r
#define SD_CD__0__PORT 3u\r
-#define SD_CD__0__SHIFT 6\r
+#define SD_CD__0__SHIFT 6u\r
#define SD_CD__AG CYREG_PRT3_AG\r
#define SD_CD__AMUX CYREG_PRT3_AMUX\r
#define SD_CD__BIE CYREG_PRT3_BIE\r
#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
#define SD_CD__PS CYREG_PRT3_PS\r
-#define SD_CD__SHIFT 6\r
+#define SD_CD__SHIFT 6u\r
#define SD_CD__SLW CYREG_PRT3_SLW\r
\r
/* SD_CS */\r
#define SD_CS__0__MASK 0x10u\r
#define SD_CS__0__PC CYREG_PRT3_PC4\r
#define SD_CS__0__PORT 3u\r
-#define SD_CS__0__SHIFT 4\r
+#define SD_CS__0__SHIFT 4u\r
#define SD_CS__AG CYREG_PRT3_AG\r
#define SD_CS__AMUX CYREG_PRT3_AMUX\r
#define SD_CS__BIE CYREG_PRT3_BIE\r
#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
#define SD_CS__PS CYREG_PRT3_PS\r
-#define SD_CS__SHIFT 4\r
+#define SD_CS__SHIFT 4u\r
#define SD_CS__SLW CYREG_PRT3_SLW\r
\r
/* USBFS_arb_int */\r
#define USBFS_Dm__0__MASK 0x80u\r
#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1\r
#define USBFS_Dm__0__PORT 15u\r
-#define USBFS_Dm__0__SHIFT 7\r
+#define USBFS_Dm__0__SHIFT 7u\r
#define USBFS_Dm__AG CYREG_PRT15_AG\r
#define USBFS_Dm__AMUX CYREG_PRT15_AMUX\r
#define USBFS_Dm__BIE CYREG_PRT15_BIE\r
#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
#define USBFS_Dm__PS CYREG_PRT15_PS\r
-#define USBFS_Dm__SHIFT 7\r
+#define USBFS_Dm__SHIFT 7u\r
#define USBFS_Dm__SLW CYREG_PRT15_SLW\r
\r
/* USBFS_Dp */\r
#define USBFS_Dp__0__MASK 0x40u\r
#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0\r
#define USBFS_Dp__0__PORT 15u\r
-#define USBFS_Dp__0__SHIFT 6\r
+#define USBFS_Dp__0__SHIFT 6u\r
#define USBFS_Dp__AG CYREG_PRT15_AG\r
#define USBFS_Dp__AMUX CYREG_PRT15_AMUX\r
#define USBFS_Dp__BIE CYREG_PRT15_BIE\r
#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
#define USBFS_Dp__PS CYREG_PRT15_PS\r
-#define USBFS_Dp__SHIFT 6\r
+#define USBFS_Dp__SHIFT 6u\r
#define USBFS_Dp__SLW CYREG_PRT15_SLW\r
#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15\r
\r
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB05_MSK\r
+#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB05_ST\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__2__POS 2\r
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
-#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB05_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB05_ST\r
\r
/* SD_SCK */\r
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2\r
#define SD_SCK__0__MASK 0x04u\r
#define SD_SCK__0__PC CYREG_PRT3_PC2\r
#define SD_SCK__0__PORT 3u\r
-#define SD_SCK__0__SHIFT 2\r
+#define SD_SCK__0__SHIFT 2u\r
#define SD_SCK__AG CYREG_PRT3_AG\r
#define SD_SCK__AMUX CYREG_PRT3_AMUX\r
#define SD_SCK__BIE CYREG_PRT3_BIE\r
#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
#define SD_SCK__PS CYREG_PRT3_PS\r
-#define SD_SCK__SHIFT 2\r
+#define SD_SCK__SHIFT 2u\r
#define SD_SCK__SLW CYREG_PRT3_SLW\r
\r
/* SCSI_In */\r
#define SCSI_In__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In__0__PS CYREG_PRT2_PS\r
-#define SCSI_In__0__SHIFT 0\r
+#define SCSI_In__0__SHIFT 0u\r
#define SCSI_In__0__SLW CYREG_PRT2_SLW\r
#define SCSI_In__1__AG CYREG_PRT6_AG\r
#define SCSI_In__1__AMUX CYREG_PRT6_AMUX\r
#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_In__1__PS CYREG_PRT6_PS\r
-#define SCSI_In__1__SHIFT 7\r
+#define SCSI_In__1__SHIFT 7u\r
#define SCSI_In__1__SLW CYREG_PRT6_SLW\r
#define SCSI_In__2__AG CYREG_PRT5_AG\r
#define SCSI_In__2__AMUX CYREG_PRT5_AMUX\r
#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_In__2__PS CYREG_PRT5_PS\r
-#define SCSI_In__2__SHIFT 1\r
+#define SCSI_In__2__SHIFT 1u\r
#define SCSI_In__2__SLW CYREG_PRT5_SLW\r
#define SCSI_In__3__AG CYREG_PRT5_AG\r
#define SCSI_In__3__AMUX CYREG_PRT5_AMUX\r
#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_In__3__PS CYREG_PRT5_PS\r
-#define SCSI_In__3__SHIFT 2\r
+#define SCSI_In__3__SHIFT 2u\r
#define SCSI_In__3__SLW CYREG_PRT5_SLW\r
#define SCSI_In__4__AG CYREG_PRT5_AG\r
#define SCSI_In__4__AMUX CYREG_PRT5_AMUX\r
#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_In__4__PS CYREG_PRT5_PS\r
-#define SCSI_In__4__SHIFT 3\r
+#define SCSI_In__4__SHIFT 3u\r
#define SCSI_In__4__SLW CYREG_PRT5_SLW\r
#define SCSI_In__CD__AG CYREG_PRT5_AG\r
#define SCSI_In__CD__AMUX CYREG_PRT5_AMUX\r
#define SCSI_In__CD__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_In__CD__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_In__CD__PS CYREG_PRT5_PS\r
-#define SCSI_In__CD__SHIFT 1\r
+#define SCSI_In__CD__SHIFT 1u\r
#define SCSI_In__CD__SLW CYREG_PRT5_SLW\r
#define SCSI_In__DBP__AG CYREG_PRT2_AG\r
#define SCSI_In__DBP__AMUX CYREG_PRT2_AMUX\r
#define SCSI_In__DBP__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In__DBP__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In__DBP__PS CYREG_PRT2_PS\r
-#define SCSI_In__DBP__SHIFT 0\r
+#define SCSI_In__DBP__SHIFT 0u\r
#define SCSI_In__DBP__SLW CYREG_PRT2_SLW\r
#define SCSI_In__IO__AG CYREG_PRT5_AG\r
#define SCSI_In__IO__AMUX CYREG_PRT5_AMUX\r
#define SCSI_In__IO__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_In__IO__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_In__IO__PS CYREG_PRT5_PS\r
-#define SCSI_In__IO__SHIFT 3\r
+#define SCSI_In__IO__SHIFT 3u\r
#define SCSI_In__IO__SLW CYREG_PRT5_SLW\r
#define SCSI_In__MSG__AG CYREG_PRT6_AG\r
#define SCSI_In__MSG__AMUX CYREG_PRT6_AMUX\r
#define SCSI_In__MSG__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_In__MSG__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_In__MSG__PS CYREG_PRT6_PS\r
-#define SCSI_In__MSG__SHIFT 7\r
+#define SCSI_In__MSG__SHIFT 7u\r
#define SCSI_In__MSG__SLW CYREG_PRT6_SLW\r
#define SCSI_In__REQ__AG CYREG_PRT5_AG\r
#define SCSI_In__REQ__AMUX CYREG_PRT5_AMUX\r
#define SCSI_In__REQ__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_In__REQ__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_In__REQ__PS CYREG_PRT5_PS\r
-#define SCSI_In__REQ__SHIFT 2\r
+#define SCSI_In__REQ__SHIFT 2u\r
#define SCSI_In__REQ__SLW CYREG_PRT5_SLW\r
\r
/* SCSI_In_DBx */\r
#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
#define SCSI_In_DBx__0__PS CYREG_PRT12_PS\r
-#define SCSI_In_DBx__0__SHIFT 4\r
+#define SCSI_In_DBx__0__SHIFT 4u\r
#define SCSI_In_DBx__0__SIO_CFG CYREG_PRT12_SIO_CFG\r
#define SCSI_In_DBx__0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
#define SCSI_In_DBx__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__1__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__1__SHIFT 7\r
+#define SCSI_In_DBx__1__SHIFT 7u\r
#define SCSI_In_DBx__1__SLW CYREG_PRT2_SLW\r
#define SCSI_In_DBx__2__AG CYREG_PRT2_AG\r
#define SCSI_In_DBx__2__AMUX CYREG_PRT2_AMUX\r
#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__2__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__2__SHIFT 6\r
+#define SCSI_In_DBx__2__SHIFT 6u\r
#define SCSI_In_DBx__2__SLW CYREG_PRT2_SLW\r
#define SCSI_In_DBx__3__AG CYREG_PRT2_AG\r
#define SCSI_In_DBx__3__AMUX CYREG_PRT2_AMUX\r
#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__3__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__3__SHIFT 5\r
+#define SCSI_In_DBx__3__SHIFT 5u\r
#define SCSI_In_DBx__3__SLW CYREG_PRT2_SLW\r
#define SCSI_In_DBx__4__AG CYREG_PRT2_AG\r
#define SCSI_In_DBx__4__AMUX CYREG_PRT2_AMUX\r
#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__4__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__4__SHIFT 4\r
+#define SCSI_In_DBx__4__SHIFT 4u\r
#define SCSI_In_DBx__4__SLW CYREG_PRT2_SLW\r
#define SCSI_In_DBx__5__AG CYREG_PRT2_AG\r
#define SCSI_In_DBx__5__AMUX CYREG_PRT2_AMUX\r
#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__5__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__5__SHIFT 3\r
+#define SCSI_In_DBx__5__SHIFT 3u\r
#define SCSI_In_DBx__5__SLW CYREG_PRT2_SLW\r
#define SCSI_In_DBx__6__AG CYREG_PRT2_AG\r
#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX\r
#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__6__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__6__SHIFT 2\r
+#define SCSI_In_DBx__6__SHIFT 2u\r
#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW\r
#define SCSI_In_DBx__7__AG CYREG_PRT2_AG\r
#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX\r
#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__7__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__7__SHIFT 1\r
+#define SCSI_In_DBx__7__SHIFT 1u\r
#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW\r
#define SCSI_In_DBx__DB0__AG CYREG_PRT12_AG\r
#define SCSI_In_DBx__DB0__BIE CYREG_PRT12_BIE\r
#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
#define SCSI_In_DBx__DB0__PS CYREG_PRT12_PS\r
-#define SCSI_In_DBx__DB0__SHIFT 4\r
+#define SCSI_In_DBx__DB0__SHIFT 4u\r
#define SCSI_In_DBx__DB0__SIO_CFG CYREG_PRT12_SIO_CFG\r
#define SCSI_In_DBx__DB0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
#define SCSI_In_DBx__DB0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__DB1__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB1__SHIFT 7\r
+#define SCSI_In_DBx__DB1__SHIFT 7u\r
#define SCSI_In_DBx__DB1__SLW CYREG_PRT2_SLW\r
#define SCSI_In_DBx__DB2__AG CYREG_PRT2_AG\r
#define SCSI_In_DBx__DB2__AMUX CYREG_PRT2_AMUX\r
#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__DB2__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB2__SHIFT 6\r
+#define SCSI_In_DBx__DB2__SHIFT 6u\r
#define SCSI_In_DBx__DB2__SLW CYREG_PRT2_SLW\r
#define SCSI_In_DBx__DB3__AG CYREG_PRT2_AG\r
#define SCSI_In_DBx__DB3__AMUX CYREG_PRT2_AMUX\r
#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__DB3__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB3__SHIFT 5\r
+#define SCSI_In_DBx__DB3__SHIFT 5u\r
#define SCSI_In_DBx__DB3__SLW CYREG_PRT2_SLW\r
#define SCSI_In_DBx__DB4__AG CYREG_PRT2_AG\r
#define SCSI_In_DBx__DB4__AMUX CYREG_PRT2_AMUX\r
#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__DB4__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB4__SHIFT 4\r
+#define SCSI_In_DBx__DB4__SHIFT 4u\r
#define SCSI_In_DBx__DB4__SLW CYREG_PRT2_SLW\r
#define SCSI_In_DBx__DB5__AG CYREG_PRT2_AG\r
#define SCSI_In_DBx__DB5__AMUX CYREG_PRT2_AMUX\r
#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__DB5__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB5__SHIFT 3\r
+#define SCSI_In_DBx__DB5__SHIFT 3u\r
#define SCSI_In_DBx__DB5__SLW CYREG_PRT2_SLW\r
#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG\r
#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX\r
#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB6__SHIFT 2\r
+#define SCSI_In_DBx__DB6__SHIFT 2u\r
#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW\r
#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG\r
#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX\r
#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB7__SHIFT 1\r
+#define SCSI_In_DBx__DB7__SHIFT 1u\r
#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW\r
\r
/* SD_DAT1 */\r
#define SD_DAT1__0__MASK 0x01u\r
#define SD_DAT1__0__PC CYREG_PRT3_PC0\r
#define SD_DAT1__0__PORT 3u\r
-#define SD_DAT1__0__SHIFT 0\r
+#define SD_DAT1__0__SHIFT 0u\r
#define SD_DAT1__AG CYREG_PRT3_AG\r
#define SD_DAT1__AMUX CYREG_PRT3_AMUX\r
#define SD_DAT1__BIE CYREG_PRT3_BIE\r
#define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
#define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
#define SD_DAT1__PS CYREG_PRT3_PS\r
-#define SD_DAT1__SHIFT 0\r
+#define SD_DAT1__SHIFT 0u\r
#define SD_DAT1__SLW CYREG_PRT3_SLW\r
\r
/* SD_DAT2 */\r
#define SD_DAT2__0__MASK 0x20u\r
#define SD_DAT2__0__PC CYREG_PRT3_PC5\r
#define SD_DAT2__0__PORT 3u\r
-#define SD_DAT2__0__SHIFT 5\r
+#define SD_DAT2__0__SHIFT 5u\r
#define SD_DAT2__AG CYREG_PRT3_AG\r
#define SD_DAT2__AMUX CYREG_PRT3_AMUX\r
#define SD_DAT2__BIE CYREG_PRT3_BIE\r
#define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
#define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
#define SD_DAT2__PS CYREG_PRT3_PS\r
-#define SD_DAT2__SHIFT 5\r
+#define SD_DAT2__SHIFT 5u\r
#define SD_DAT2__SLW CYREG_PRT3_SLW\r
\r
/* SD_MISO */\r
#define SD_MISO__0__MASK 0x02u\r
#define SD_MISO__0__PC CYREG_PRT3_PC1\r
#define SD_MISO__0__PORT 3u\r
-#define SD_MISO__0__SHIFT 1\r
+#define SD_MISO__0__SHIFT 1u\r
#define SD_MISO__AG CYREG_PRT3_AG\r
#define SD_MISO__AMUX CYREG_PRT3_AMUX\r
#define SD_MISO__BIE CYREG_PRT3_BIE\r
#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
#define SD_MISO__PS CYREG_PRT3_PS\r
-#define SD_MISO__SHIFT 1\r
+#define SD_MISO__SHIFT 1u\r
#define SD_MISO__SLW CYREG_PRT3_SLW\r
\r
/* SD_MOSI */\r
#define SD_MOSI__0__MASK 0x08u\r
#define SD_MOSI__0__PC CYREG_PRT3_PC3\r
#define SD_MOSI__0__PORT 3u\r
-#define SD_MOSI__0__SHIFT 3\r
+#define SD_MOSI__0__SHIFT 3u\r
#define SD_MOSI__AG CYREG_PRT3_AG\r
#define SD_MOSI__AMUX CYREG_PRT3_AMUX\r
#define SD_MOSI__BIE CYREG_PRT3_BIE\r
#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
#define SD_MOSI__PS CYREG_PRT3_PS\r
-#define SD_MOSI__SHIFT 3\r
+#define SD_MOSI__SHIFT 3u\r
#define SD_MOSI__SLW CYREG_PRT3_SLW\r
\r
/* SCSI_CLK */\r
#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Out__0__PS CYREG_PRT4_PS\r
-#define SCSI_Out__0__SHIFT 3\r
+#define SCSI_Out__0__SHIFT 3u\r
#define SCSI_Out__0__SLW CYREG_PRT4_SLW\r
#define SCSI_Out__1__AG CYREG_PRT4_AG\r
#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Out__1__PS CYREG_PRT4_PS\r
-#define SCSI_Out__1__SHIFT 2\r
+#define SCSI_Out__1__SHIFT 2u\r
#define SCSI_Out__1__SLW CYREG_PRT4_SLW\r
#define SCSI_Out__2__AG CYREG_PRT0_AG\r
#define SCSI_Out__2__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__2__PS CYREG_PRT0_PS\r
-#define SCSI_Out__2__SHIFT 7\r
+#define SCSI_Out__2__SHIFT 7u\r
#define SCSI_Out__2__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__3__AG CYREG_PRT0_AG\r
#define SCSI_Out__3__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__3__PS CYREG_PRT0_PS\r
-#define SCSI_Out__3__SHIFT 6\r
+#define SCSI_Out__3__SHIFT 6u\r
#define SCSI_Out__3__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__4__AG CYREG_PRT0_AG\r
#define SCSI_Out__4__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__4__PS CYREG_PRT0_PS\r
-#define SCSI_Out__4__SHIFT 5\r
+#define SCSI_Out__4__SHIFT 5u\r
#define SCSI_Out__4__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__5__AG CYREG_PRT0_AG\r
#define SCSI_Out__5__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__5__PS CYREG_PRT0_PS\r
-#define SCSI_Out__5__SHIFT 4\r
+#define SCSI_Out__5__SHIFT 4u\r
#define SCSI_Out__5__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__6__AG CYREG_PRT0_AG\r
#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__6__PS CYREG_PRT0_PS\r
-#define SCSI_Out__6__SHIFT 3\r
+#define SCSI_Out__6__SHIFT 3u\r
#define SCSI_Out__6__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__7__AG CYREG_PRT0_AG\r
#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__7__PS CYREG_PRT0_PS\r
-#define SCSI_Out__7__SHIFT 2\r
+#define SCSI_Out__7__SHIFT 2u\r
#define SCSI_Out__7__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__8__AG CYREG_PRT0_AG\r
#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__8__PS CYREG_PRT0_PS\r
-#define SCSI_Out__8__SHIFT 1\r
+#define SCSI_Out__8__SHIFT 1u\r
#define SCSI_Out__8__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__9__AG CYREG_PRT0_AG\r
#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__9__PS CYREG_PRT0_PS\r
-#define SCSI_Out__9__SHIFT 0\r
+#define SCSI_Out__9__SHIFT 0u\r
#define SCSI_Out__9__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__ACK__AG CYREG_PRT0_AG\r
#define SCSI_Out__ACK__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__ACK__PS CYREG_PRT0_PS\r
-#define SCSI_Out__ACK__SHIFT 6\r
+#define SCSI_Out__ACK__SHIFT 6u\r
#define SCSI_Out__ACK__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__ATN__AG CYREG_PRT4_AG\r
#define SCSI_Out__ATN__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Out__ATN__PS CYREG_PRT4_PS\r
-#define SCSI_Out__ATN__SHIFT 2\r
+#define SCSI_Out__ATN__SHIFT 2u\r
#define SCSI_Out__ATN__SLW CYREG_PRT4_SLW\r
#define SCSI_Out__BSY__AG CYREG_PRT0_AG\r
#define SCSI_Out__BSY__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__BSY__PS CYREG_PRT0_PS\r
-#define SCSI_Out__BSY__SHIFT 7\r
+#define SCSI_Out__BSY__SHIFT 7u\r
#define SCSI_Out__BSY__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG\r
#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS\r
-#define SCSI_Out__CD_raw__SHIFT 2\r
+#define SCSI_Out__CD_raw__SHIFT 2u\r
#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG\r
#define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Out__DBP_raw__PS CYREG_PRT4_PS\r
-#define SCSI_Out__DBP_raw__SHIFT 3\r
+#define SCSI_Out__DBP_raw__SHIFT 3u\r
#define SCSI_Out__DBP_raw__SLW CYREG_PRT4_SLW\r
#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG\r
#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS\r
-#define SCSI_Out__IO_raw__SHIFT 0\r
+#define SCSI_Out__IO_raw__SHIFT 0u\r
#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG\r
#define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS\r
-#define SCSI_Out__MSG_raw__SHIFT 4\r
+#define SCSI_Out__MSG_raw__SHIFT 4u\r
#define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__REQ__AG CYREG_PRT0_AG\r
#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__REQ__PS CYREG_PRT0_PS\r
-#define SCSI_Out__REQ__SHIFT 1\r
+#define SCSI_Out__REQ__SHIFT 1u\r
#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__RST__AG CYREG_PRT0_AG\r
#define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__RST__PS CYREG_PRT0_PS\r
-#define SCSI_Out__RST__SHIFT 5\r
+#define SCSI_Out__RST__SHIFT 5u\r
#define SCSI_Out__RST__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__SEL__AG CYREG_PRT0_AG\r
#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__SEL__PS CYREG_PRT0_PS\r
-#define SCSI_Out__SEL__SHIFT 3\r
+#define SCSI_Out__SEL__SHIFT 3u\r
#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW\r
\r
/* SCSI_Out_Bits */\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
\r
/* SCSI_Out_Ctl */\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB09_MSK\r
\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__0__SHIFT 3\r
+#define SCSI_Out_DBx__0__SHIFT 3u\r
#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW\r
#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG\r
#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__1__SHIFT 2\r
+#define SCSI_Out_DBx__1__SHIFT 2u\r
#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW\r
#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG\r
#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__2__SHIFT 1\r
+#define SCSI_Out_DBx__2__SHIFT 1u\r
#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW\r
#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG\r
#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__3__SHIFT 0\r
+#define SCSI_Out_DBx__3__SHIFT 0u\r
#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW\r
#define SCSI_Out_DBx__4__AG CYREG_PRT4_AG\r
#define SCSI_Out_DBx__4__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Out_DBx__4__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__4__SHIFT 7\r
+#define SCSI_Out_DBx__4__SHIFT 7u\r
#define SCSI_Out_DBx__4__SLW CYREG_PRT4_SLW\r
#define SCSI_Out_DBx__5__AG CYREG_PRT4_AG\r
#define SCSI_Out_DBx__5__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Out_DBx__5__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__5__SHIFT 6\r
+#define SCSI_Out_DBx__5__SHIFT 6u\r
#define SCSI_Out_DBx__5__SLW CYREG_PRT4_SLW\r
#define SCSI_Out_DBx__6__AG CYREG_PRT4_AG\r
#define SCSI_Out_DBx__6__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Out_DBx__6__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__6__SHIFT 5\r
+#define SCSI_Out_DBx__6__SHIFT 5u\r
#define SCSI_Out_DBx__6__SLW CYREG_PRT4_SLW\r
#define SCSI_Out_DBx__7__AG CYREG_PRT4_AG\r
#define SCSI_Out_DBx__7__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Out_DBx__7__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__7__SHIFT 4\r
+#define SCSI_Out_DBx__7__SHIFT 4u\r
#define SCSI_Out_DBx__7__SLW CYREG_PRT4_SLW\r
#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG\r
#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB0__SHIFT 3\r
+#define SCSI_Out_DBx__DB0__SHIFT 3u\r
#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW\r
#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG\r
#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB1__SHIFT 2\r
+#define SCSI_Out_DBx__DB1__SHIFT 2u\r
#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW\r
#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG\r
#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB2__SHIFT 1\r
+#define SCSI_Out_DBx__DB2__SHIFT 1u\r
#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW\r
#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG\r
#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB3__SHIFT 0\r
+#define SCSI_Out_DBx__DB3__SHIFT 0u\r
#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW\r
#define SCSI_Out_DBx__DB4__AG CYREG_PRT4_AG\r
#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Out_DBx__DB4__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB4__SHIFT 7\r
+#define SCSI_Out_DBx__DB4__SHIFT 7u\r
#define SCSI_Out_DBx__DB4__SLW CYREG_PRT4_SLW\r
#define SCSI_Out_DBx__DB5__AG CYREG_PRT4_AG\r
#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Out_DBx__DB5__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB5__SHIFT 6\r
+#define SCSI_Out_DBx__DB5__SHIFT 6u\r
#define SCSI_Out_DBx__DB5__SLW CYREG_PRT4_SLW\r
#define SCSI_Out_DBx__DB6__AG CYREG_PRT4_AG\r
#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Out_DBx__DB6__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB6__SHIFT 5\r
+#define SCSI_Out_DBx__DB6__SHIFT 5u\r
#define SCSI_Out_DBx__DB6__SLW CYREG_PRT4_SLW\r
#define SCSI_Out_DBx__DB7__AG CYREG_PRT4_AG\r
#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Out_DBx__DB7__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB7__SHIFT 4\r
+#define SCSI_Out_DBx__DB7__SHIFT 4u\r
#define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW\r
\r
/* SD_RX_DMA */\r
#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
#define SCSI_Noise__0__PS CYREG_PRT12_PS\r
-#define SCSI_Noise__0__SHIFT 5\r
+#define SCSI_Noise__0__SHIFT 5u\r
#define SCSI_Noise__0__SIO_CFG CYREG_PRT12_SIO_CFG\r
#define SCSI_Noise__0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
#define SCSI_Noise__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Noise__1__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__1__SHIFT 4\r
+#define SCSI_Noise__1__SHIFT 4u\r
#define SCSI_Noise__1__SLW CYREG_PRT6_SLW\r
#define SCSI_Noise__2__AG CYREG_PRT5_AG\r
#define SCSI_Noise__2__AMUX CYREG_PRT5_AMUX\r
#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_Noise__2__PS CYREG_PRT5_PS\r
-#define SCSI_Noise__2__SHIFT 0\r
+#define SCSI_Noise__2__SHIFT 0u\r
#define SCSI_Noise__2__SLW CYREG_PRT5_SLW\r
#define SCSI_Noise__3__AG CYREG_PRT6_AG\r
#define SCSI_Noise__3__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Noise__3__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__3__SHIFT 6\r
+#define SCSI_Noise__3__SHIFT 6u\r
#define SCSI_Noise__3__SLW CYREG_PRT6_SLW\r
#define SCSI_Noise__4__AG CYREG_PRT6_AG\r
#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Noise__4__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__4__SHIFT 5\r
+#define SCSI_Noise__4__SHIFT 5u\r
#define SCSI_Noise__4__SLW CYREG_PRT6_SLW\r
#define SCSI_Noise__ACK__AG CYREG_PRT6_AG\r
#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Noise__ACK__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__ACK__SHIFT 5\r
+#define SCSI_Noise__ACK__SHIFT 5u\r
#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW\r
#define SCSI_Noise__ATN__AG CYREG_PRT12_AG\r
#define SCSI_Noise__ATN__BIE CYREG_PRT12_BIE\r
#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
#define SCSI_Noise__ATN__PS CYREG_PRT12_PS\r
-#define SCSI_Noise__ATN__SHIFT 5\r
+#define SCSI_Noise__ATN__SHIFT 5u\r
#define SCSI_Noise__ATN__SIO_CFG CYREG_PRT12_SIO_CFG\r
#define SCSI_Noise__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
#define SCSI_Noise__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Noise__BSY__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__BSY__SHIFT 4\r
+#define SCSI_Noise__BSY__SHIFT 4u\r
#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW\r
#define SCSI_Noise__RST__AG CYREG_PRT6_AG\r
#define SCSI_Noise__RST__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Noise__RST__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__RST__SHIFT 6\r
+#define SCSI_Noise__RST__SHIFT 6u\r
#define SCSI_Noise__RST__SLW CYREG_PRT6_SLW\r
#define SCSI_Noise__SEL__AG CYREG_PRT5_AG\r
#define SCSI_Noise__SEL__AMUX CYREG_PRT5_AMUX\r
#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_Noise__SEL__PS CYREG_PRT5_PS\r
-#define SCSI_Noise__SEL__SHIFT 0\r
+#define SCSI_Noise__SEL__SHIFT 0u\r
#define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW\r
\r
/* scsiTarget */\r
#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB12_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB12_ST\r
\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B1_UDB07_ST\r
\r
/* Miscellaneous */\r
#define BCLK__BUS_CLK__HZ 50000000U\r
#define BCLK__BUS_CLK__KHZ 50000U\r
#define BCLK__BUS_CLK__MHZ 50U\r
#define CY_PROJECT_NAME "SCSI2SD"\r
-#define CY_VERSION "PSoC Creator 3.3"\r
+#define CY_VERSION "PSoC Creator 4.0 Update 1"\r
#define CYDEV_CHIP_DIE_LEOPARD 1u\r
-#define CYDEV_CHIP_DIE_PANTHER 18u\r
-#define CYDEV_CHIP_DIE_PSOC4A 10u\r
-#define CYDEV_CHIP_DIE_PSOC5LP 17u\r
+#define CYDEV_CHIP_DIE_PSOC4A 12u\r
+#define CYDEV_CHIP_DIE_PSOC5LP 19u\r
+#define CYDEV_CHIP_DIE_PSOC5TM 20u\r
#define CYDEV_CHIP_DIE_TMA4 2u\r
#define CYDEV_CHIP_DIE_UNKNOWN 0u\r
+#define CYDEV_CHIP_FAMILY_FM0P 4u\r
+#define CYDEV_CHIP_FAMILY_FM3 5u\r
+#define CYDEV_CHIP_FAMILY_FM4 6u\r
#define CYDEV_CHIP_FAMILY_PSOC3 1u\r
#define CYDEV_CHIP_FAMILY_PSOC4 2u\r
#define CYDEV_CHIP_FAMILY_PSOC5 3u\r
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5\r
#define CYDEV_CHIP_JTAG_ID 0x2E133069u\r
#define CYDEV_CHIP_MEMBER_3A 1u\r
-#define CYDEV_CHIP_MEMBER_4A 10u\r
-#define CYDEV_CHIP_MEMBER_4C 15u\r
-#define CYDEV_CHIP_MEMBER_4D 6u\r
+#define CYDEV_CHIP_MEMBER_4A 12u\r
+#define CYDEV_CHIP_MEMBER_4C 18u\r
+#define CYDEV_CHIP_MEMBER_4D 8u\r
#define CYDEV_CHIP_MEMBER_4E 4u\r
-#define CYDEV_CHIP_MEMBER_4F 11u\r
+#define CYDEV_CHIP_MEMBER_4F 13u\r
#define CYDEV_CHIP_MEMBER_4G 2u\r
-#define CYDEV_CHIP_MEMBER_4H 9u\r
-#define CYDEV_CHIP_MEMBER_4I 14u\r
-#define CYDEV_CHIP_MEMBER_4J 7u\r
-#define CYDEV_CHIP_MEMBER_4K 8u\r
-#define CYDEV_CHIP_MEMBER_4L 13u\r
-#define CYDEV_CHIP_MEMBER_4M 12u\r
-#define CYDEV_CHIP_MEMBER_4N 5u\r
+#define CYDEV_CHIP_MEMBER_4H 11u\r
+#define CYDEV_CHIP_MEMBER_4I 17u\r
+#define CYDEV_CHIP_MEMBER_4J 9u\r
+#define CYDEV_CHIP_MEMBER_4K 10u\r
+#define CYDEV_CHIP_MEMBER_4L 16u\r
+#define CYDEV_CHIP_MEMBER_4M 15u\r
+#define CYDEV_CHIP_MEMBER_4N 6u\r
+#define CYDEV_CHIP_MEMBER_4O 5u\r
+#define CYDEV_CHIP_MEMBER_4P 14u\r
+#define CYDEV_CHIP_MEMBER_4Q 7u\r
#define CYDEV_CHIP_MEMBER_4U 3u\r
-#define CYDEV_CHIP_MEMBER_5A 17u\r
-#define CYDEV_CHIP_MEMBER_5B 16u\r
+#define CYDEV_CHIP_MEMBER_5A 20u\r
+#define CYDEV_CHIP_MEMBER_5B 19u\r
+#define CYDEV_CHIP_MEMBER_FM3 24u\r
+#define CYDEV_CHIP_MEMBER_FM4 25u\r
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 21u\r
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 22u\r
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 23u\r
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u\r
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B\r
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED\r
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u\r
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u\r
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u\r
-#define CYDEV_CHIP_REV_PANTHER_ES0 0u\r
-#define CYDEV_CHIP_REV_PANTHER_ES1 1u\r
-#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u\r
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u\r
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u\r
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u\r
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u\r
+#define CYDEV_CHIP_REV_PSOC5TM_ES0 0u\r
+#define CYDEV_CHIP_REV_PSOC5TM_ES1 1u\r
+#define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1u\r
#define CYDEV_CHIP_REV_TMA4_ES 17u\r
#define CYDEV_CHIP_REV_TMA4_ES2 33u\r
#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u\r
#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_5A_ES0 0u\r
#define CYDEV_CHIP_REVISION_5A_ES1 1u\r
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u\r
#define CYDEV_CHIP_REVISION_5B_ES0 0u\r
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION\r
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED\r
#define CYDEV_CONFIG_FASTBOOT_ENABLED 1\r
/*******************************************************************************\r
* File Name: cyfitter_cfg.c\r
* \r
-* PSoC Creator 3.3\r
+* PSoC Creator 4.0 Update 1\r
*\r
* Description:\r
* This file contains device initialization code.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#define CYPACKED_ATTR __attribute__ ((packed))\r
#define CYALIGNED __attribute__ ((aligned))\r
#define CY_CFG_UNUSED __attribute__ ((unused))\r
- #define CY_CFG_SECTION __attribute__ ((section(".psocinit")))\r
+ #ifndef CY_CFG_SECTION\r
+ #define CY_CFG_SECTION __attribute__ ((section(".psocinit")))\r
+ #endif\r
\r
#if defined(__ARMCC_VERSION)\r
#define CY_CFG_MEMORY_BARRIER() __memory_changed()\r
\r
\r
\r
+\r
/* Clock startup error codes */\r
#define CYCLOCKSTART_NO_ERROR 0u\r
#define CYCLOCKSTART_XTAL_ERROR 1u\r
#define CYCLOCKSTART_32KHZ_ERROR 2u\r
#define CYCLOCKSTART_PLL_ERROR 3u\r
\r
+\r
#ifdef CY_NEED_CYCLOCKSTARTUPERROR\r
/*******************************************************************************\r
* Function Name: CyClockStartupError\r
/* To remove the compiler warning if errorCode not used. */\r
errorCode = errorCode;\r
\r
+ /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */\r
+ /* we will end up here to allow the customer to implement something to */\r
+ /* deal with the clock condition. */\r
+\r
+#ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK\r
+ CY_CFG_Clock_Startup_ErrorCallback();\r
+#else\r
+ /* If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */\r
/* `#START CyClockStartupError` */\r
\r
/* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */\r
/* If nothing else, stop here since the clocks have not started */\r
/* correctly. */\r
while(1) {}\r
+#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ \r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 40u\r
+#define CY_CFG_BASE_ADDR_COUNT 41u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
\r
/* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */\r
static const uint8 CYCODE BS_IOPINS0_8_VAL[] = {\r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u};\r
+ 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u};\r
+\r
+ /* IOPINS0_1 Address: CYREG_PRT1_DM0 Size (bytes): 8 */\r
+ static const uint8 CYCODE BS_IOPINS0_1_VAL[] = {\r
+ 0x00u, 0x0Bu, 0x0Bu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
\r
/* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */\r
static const uint8 CYCODE BS_IOPINS0_2_VAL[] = {\r
0x4000520Bu, /* Base address: 0x40005200 Count: 11 */\r
0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
- 0x40010054u, /* Base address: 0x40010000 Count: 84 */\r
- 0x40010141u, /* Base address: 0x40010100 Count: 65 */\r
- 0x40010243u, /* Base address: 0x40010200 Count: 67 */\r
- 0x40010350u, /* Base address: 0x40010300 Count: 80 */\r
- 0x40010454u, /* Base address: 0x40010400 Count: 84 */\r
- 0x40010553u, /* Base address: 0x40010500 Count: 83 */\r
- 0x40010651u, /* Base address: 0x40010600 Count: 81 */\r
- 0x40010755u, /* Base address: 0x40010700 Count: 85 */\r
- 0x40010916u, /* Base address: 0x40010900 Count: 22 */\r
- 0x40010A56u, /* Base address: 0x40010A00 Count: 86 */\r
- 0x40010B4Du, /* Base address: 0x40010B00 Count: 77 */\r
- 0x40010C50u, /* Base address: 0x40010C00 Count: 80 */\r
- 0x40010D51u, /* Base address: 0x40010D00 Count: 81 */\r
- 0x40010E4Au, /* Base address: 0x40010E00 Count: 74 */\r
- 0x40010F3Cu, /* Base address: 0x40010F00 Count: 60 */\r
- 0x40011421u, /* Base address: 0x40011400 Count: 33 */\r
- 0x40011551u, /* Base address: 0x40011500 Count: 81 */\r
- 0x4001165Bu, /* Base address: 0x40011600 Count: 91 */\r
- 0x40011747u, /* Base address: 0x40011700 Count: 71 */\r
- 0x40011907u, /* Base address: 0x40011900 Count: 7 */\r
- 0x40011B05u, /* Base address: 0x40011B00 Count: 5 */\r
- 0x4001401Bu, /* Base address: 0x40014000 Count: 27 */\r
- 0x4001411Eu, /* Base address: 0x40014100 Count: 30 */\r
- 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */\r
- 0x40014310u, /* Base address: 0x40014300 Count: 16 */\r
- 0x40014412u, /* Base address: 0x40014400 Count: 18 */\r
- 0x40014516u, /* Base address: 0x40014500 Count: 22 */\r
- 0x4001460Fu, /* Base address: 0x40014600 Count: 15 */\r
- 0x4001470Bu, /* Base address: 0x40014700 Count: 11 */\r
- 0x40014806u, /* Base address: 0x40014800 Count: 6 */\r
- 0x40014909u, /* Base address: 0x40014900 Count: 9 */\r
- 0x40014C03u, /* Base address: 0x40014C00 Count: 3 */\r
- 0x40014D03u, /* Base address: 0x40014D00 Count: 3 */\r
- 0x40015004u, /* Base address: 0x40015000 Count: 4 */\r
+ 0x40010040u, /* Base address: 0x40010000 Count: 64 */\r
+ 0x4001013Bu, /* Base address: 0x40010100 Count: 59 */\r
+ 0x4001024Au, /* Base address: 0x40010200 Count: 74 */\r
+ 0x40010354u, /* Base address: 0x40010300 Count: 84 */\r
+ 0x40010441u, /* Base address: 0x40010400 Count: 65 */\r
+ 0x4001054Cu, /* Base address: 0x40010500 Count: 76 */\r
+ 0x4001064Eu, /* Base address: 0x40010600 Count: 78 */\r
+ 0x40010753u, /* Base address: 0x40010700 Count: 83 */\r
+ 0x4001091Du, /* Base address: 0x40010900 Count: 29 */\r
+ 0x40010A4Du, /* Base address: 0x40010A00 Count: 77 */\r
+ 0x40010B54u, /* Base address: 0x40010B00 Count: 84 */\r
+ 0x40010C4Fu, /* Base address: 0x40010C00 Count: 79 */\r
+ 0x40010D4Bu, /* Base address: 0x40010D00 Count: 75 */\r
+ 0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */\r
+ 0x40010F38u, /* Base address: 0x40010F00 Count: 56 */\r
+ 0x4001145Eu, /* Base address: 0x40011400 Count: 94 */\r
+ 0x40011555u, /* Base address: 0x40011500 Count: 85 */\r
+ 0x40011658u, /* Base address: 0x40011600 Count: 88 */\r
+ 0x4001174Bu, /* Base address: 0x40011700 Count: 75 */\r
+ 0x40011850u, /* Base address: 0x40011800 Count: 80 */\r
+ 0x40011948u, /* Base address: 0x40011900 Count: 72 */\r
+ 0x40011B0Au, /* Base address: 0x40011B00 Count: 10 */\r
+ 0x4001401Au, /* Base address: 0x40014000 Count: 26 */\r
+ 0x4001411Fu, /* Base address: 0x40014100 Count: 31 */\r
+ 0x40014217u, /* Base address: 0x40014200 Count: 23 */\r
+ 0x4001430Eu, /* Base address: 0x40014300 Count: 14 */\r
+ 0x4001440Fu, /* Base address: 0x40014400 Count: 15 */\r
+ 0x40014515u, /* Base address: 0x40014500 Count: 21 */\r
+ 0x40014610u, /* Base address: 0x40014600 Count: 16 */\r
+ 0x40014716u, /* Base address: 0x40014700 Count: 22 */\r
+ 0x4001480Bu, /* Base address: 0x40014800 Count: 11 */\r
+ 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */\r
+ 0x40014C08u, /* Base address: 0x40014C00 Count: 8 */\r
+ 0x40014D05u, /* Base address: 0x40014D00 Count: 5 */\r
+ 0x40015005u, /* Base address: 0x40015000 Count: 5 */\r
0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
\r
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
- {0x0Au, 0x1Bu},\r
- {0x00u, 0x11u},\r
- {0x01u, 0x02u},\r
+ {0x0Au, 0x4Bu},\r
+ {0x00u, 0x12u},\r
+ {0x01u, 0x03u},\r
{0x18u, 0x04u},\r
{0x1Cu, 0x71u},\r
- {0x20u, 0x38u},\r
- {0x21u, 0x60u},\r
+ {0x20u, 0xC0u},\r
+ {0x21u, 0x58u},\r
{0x2Cu, 0x0Eu},\r
- {0x30u, 0x0Cu},\r
+ {0x30u, 0x09u},\r
{0x31u, 0x0Au},\r
{0x34u, 0x80u},\r
{0x7Cu, 0x40u},\r
{0x20u, 0x01u},\r
- {0x85u, 0x0Fu},\r
- {0x00u, 0x20u},\r
- {0x04u, 0x01u},\r
- {0x08u, 0x51u},\r
- {0x0Au, 0x2Cu},\r
+ {0x86u, 0x0Fu},\r
+ {0x01u, 0x33u},\r
+ {0x03u, 0xCCu},\r
+ {0x04u, 0x3Fu},\r
+ {0x08u, 0x04u},\r
+ {0x0Au, 0x08u},\r
+ {0x0Bu, 0xFFu},\r
{0x0Eu, 0x3Fu},\r
- {0x10u, 0x4Au},\r
- {0x12u, 0x15u},\r
- {0x1Cu, 0x4Bu},\r
- {0x1Eu, 0x34u},\r
- {0x20u, 0x06u},\r
- {0x22u, 0x40u},\r
- {0x26u, 0x10u},\r
- {0x30u, 0x3Fu},\r
- {0x32u, 0x40u},\r
- {0x3Eu, 0x04u},\r
- {0x40u, 0x34u},\r
- {0x41u, 0x05u},\r
- {0x42u, 0x20u},\r
- {0x45u, 0xCFu},\r
- {0x46u, 0xD2u},\r
- {0x47u, 0x0Eu},\r
+ {0x0Fu, 0xFFu},\r
+ {0x10u, 0x10u},\r
+ {0x12u, 0x20u},\r
+ {0x14u, 0x01u},\r
+ {0x15u, 0xFFu},\r
+ {0x16u, 0x02u},\r
+ {0x18u, 0x3Fu},\r
+ {0x19u, 0xFFu},\r
+ {0x1Cu, 0x01u},\r
+ {0x1Du, 0x0Fu},\r
+ {0x1Eu, 0x02u},\r
+ {0x1Fu, 0xF0u},\r
+ {0x20u, 0x10u},\r
+ {0x21u, 0x69u},\r
+ {0x22u, 0x20u},\r
+ {0x23u, 0x96u},\r
+ {0x24u, 0x04u},\r
+ {0x25u, 0x55u},\r
+ {0x26u, 0x08u},\r
+ {0x27u, 0xAAu},\r
+ {0x2Au, 0x3Fu},\r
+ {0x2Eu, 0x3Fu},\r
+ {0x2Fu, 0xFFu},\r
+ {0x30u, 0x30u},\r
+ {0x32u, 0x03u},\r
+ {0x34u, 0x0Cu},\r
+ {0x37u, 0xFFu},\r
+ {0x3Au, 0x2Au},\r
+ {0x3Bu, 0x80u},\r
+ {0x40u, 0x52u},\r
+ {0x41u, 0x06u},\r
+ {0x42u, 0x30u},\r
+ {0x45u, 0xDCu},\r
+ {0x46u, 0xE2u},\r
+ {0x47u, 0x0Fu},\r
{0x48u, 0x1Fu},\r
{0x49u, 0xFFu},\r
{0x4Au, 0xFFu},\r
{0x4Fu, 0x2Cu},\r
{0x56u, 0x01u},\r
{0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
{0x5Au, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x01u},\r
+ {0x5Cu, 0x11u},\r
{0x5Du, 0x01u},\r
{0x5Fu, 0x01u},\r
{0x60u, 0x08u},\r
{0x68u, 0x40u},\r
{0x69u, 0x40u},\r
{0x6Eu, 0x08u},\r
- {0x80u, 0xC0u},\r
- {0x81u, 0x69u},\r
- {0x82u, 0x18u},\r
- {0x83u, 0x12u},\r
- {0x84u, 0x40u},\r
- {0x86u, 0x80u},\r
- {0x8Cu, 0x25u},\r
- {0x8Du, 0x20u},\r
- {0x8Eu, 0xD8u},\r
- {0x8Fu, 0x40u},\r
- {0x93u, 0x67u},\r
- {0x94u, 0x10u},\r
- {0x95u, 0x03u},\r
- {0x96u, 0x20u},\r
- {0x97u, 0x1Cu},\r
- {0x9Bu, 0x01u},\r
- {0x9Cu, 0xC4u},\r
- {0x9Du, 0x64u},\r
- {0x9Eu, 0x18u},\r
- {0xA0u, 0x02u},\r
- {0xA1u, 0x08u},\r
- {0xA2u, 0xD0u},\r
- {0xA3u, 0x77u},\r
- {0xA4u, 0x21u},\r
- {0xA5u, 0x02u},\r
- {0xA6u, 0xD8u},\r
- {0xA9u, 0x0Bu},\r
- {0xAAu, 0x01u},\r
- {0xABu, 0x74u},\r
- {0xACu, 0x40u},\r
- {0xADu, 0x20u},\r
- {0xAEu, 0x80u},\r
- {0xAFu, 0x40u},\r
- {0xB1u, 0x60u},\r
- {0xB2u, 0x30u},\r
- {0xB4u, 0xC0u},\r
- {0xB5u, 0x1Fu},\r
- {0xB6u, 0x0Fu},\r
- {0xB8u, 0x80u},\r
- {0xBAu, 0x28u},\r
- {0xBBu, 0x22u},\r
+ {0xD6u, 0x08u},\r
+ {0xDBu, 0x04u},\r
+ {0xDDu, 0x90u},\r
+ {0x01u, 0x80u},\r
+ {0x02u, 0x08u},\r
+ {0x03u, 0x10u},\r
+ {0x08u, 0x81u},\r
+ {0x0Au, 0x18u},\r
+ {0x10u, 0x40u},\r
+ {0x12u, 0x22u},\r
+ {0x13u, 0x10u},\r
+ {0x19u, 0x04u},\r
+ {0x1Au, 0x90u},\r
+ {0x1Bu, 0x10u},\r
+ {0x20u, 0x02u},\r
+ {0x21u, 0x80u},\r
+ {0x28u, 0x80u},\r
+ {0x29u, 0x80u},\r
+ {0x2Au, 0x04u},\r
+ {0x31u, 0x80u},\r
+ {0x32u, 0x04u},\r
+ {0x33u, 0x10u},\r
+ {0x34u, 0x10u},\r
+ {0x35u, 0x10u},\r
+ {0x39u, 0x80u},\r
+ {0x3Bu, 0x12u},\r
+ {0x43u, 0x14u},\r
+ {0x48u, 0x40u},\r
+ {0x49u, 0x80u},\r
+ {0x4Bu, 0x18u},\r
+ {0x53u, 0x58u},\r
+ {0x58u, 0x40u},\r
+ {0x59u, 0x24u},\r
+ {0x5Au, 0x82u},\r
+ {0x5Fu, 0x80u},\r
+ {0x61u, 0x22u},\r
+ {0x62u, 0x88u},\r
+ {0x63u, 0x20u},\r
+ {0x64u, 0x01u},\r
+ {0x67u, 0x02u},\r
+ {0x68u, 0x94u},\r
+ {0x69u, 0x40u},\r
+ {0x71u, 0x10u},\r
+ {0x72u, 0x82u},\r
+ {0x73u, 0x20u},\r
+ {0x83u, 0x80u},\r
+ {0x85u, 0x04u},\r
+ {0x88u, 0x44u},\r
+ {0x8Du, 0x40u},\r
+ {0xC0u, 0x07u},\r
+ {0xC2u, 0x0Fu},\r
+ {0xC4u, 0x0Fu},\r
+ {0xCAu, 0x0Bu},\r
+ {0xCCu, 0x0Eu},\r
+ {0xCEu, 0x0Du},\r
+ {0xD0u, 0x06u},\r
+ {0xD2u, 0x0Cu},\r
+ {0xD6u, 0x1Fu},\r
+ {0xD8u, 0x1Fu},\r
+ {0xE2u, 0x01u},\r
+ {0xE4u, 0x02u},\r
+ {0xE6u, 0x40u},\r
+ {0x05u, 0x20u},\r
+ {0x07u, 0x40u},\r
+ {0x09u, 0x64u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Eu, 0x02u},\r
+ {0x11u, 0x20u},\r
+ {0x13u, 0x40u},\r
+ {0x15u, 0x03u},\r
+ {0x17u, 0x1Cu},\r
+ {0x19u, 0x69u},\r
+ {0x1Au, 0x01u},\r
+ {0x1Bu, 0x12u},\r
+ {0x23u, 0x01u},\r
+ {0x27u, 0x67u},\r
+ {0x28u, 0x01u},\r
+ {0x29u, 0x08u},\r
+ {0x2Au, 0x02u},\r
+ {0x2Bu, 0x77u},\r
+ {0x2Du, 0x0Bu},\r
+ {0x2Fu, 0x74u},\r
+ {0x31u, 0x60u},\r
+ {0x34u, 0x03u},\r
+ {0x35u, 0x1Fu},\r
+ {0x3Bu, 0x22u},\r
+ {0x3Eu, 0x10u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Cu, 0x10u},\r
+ {0x5Fu, 0x01u},\r
+ {0x81u, 0x01u},\r
+ {0x83u, 0x02u},\r
+ {0x84u, 0xFFu},\r
+ {0x85u, 0x3Fu},\r
+ {0x8Bu, 0x3Fu},\r
+ {0x8Eu, 0xFFu},\r
+ {0x8Fu, 0x3Fu},\r
+ {0x90u, 0x0Fu},\r
+ {0x92u, 0xF0u},\r
+ {0x94u, 0x55u},\r
+ {0x95u, 0x3Fu},\r
+ {0x96u, 0xAAu},\r
+ {0x98u, 0xFFu},\r
+ {0x99u, 0x10u},\r
+ {0x9Bu, 0x20u},\r
+ {0x9Cu, 0x96u},\r
+ {0x9Du, 0x04u},\r
+ {0x9Eu, 0x69u},\r
+ {0x9Fu, 0x08u},\r
+ {0xA1u, 0x04u},\r
+ {0xA3u, 0x08u},\r
+ {0xA4u, 0x33u},\r
+ {0xA5u, 0x10u},\r
+ {0xA6u, 0xCCu},\r
+ {0xA7u, 0x20u},\r
+ {0xA9u, 0x01u},\r
+ {0xAAu, 0xFFu},\r
+ {0xABu, 0x02u},\r
+ {0xAEu, 0xFFu},\r
+ {0xAFu, 0x3Fu},\r
+ {0xB0u, 0xFFu},\r
+ {0xB1u, 0x03u},\r
+ {0xB5u, 0x30u},\r
+ {0xB7u, 0x0Cu},\r
+ {0xB8u, 0x08u},\r
+ {0xBAu, 0x02u},\r
+ {0xBBu, 0xA2u},\r
+ {0xBEu, 0x04u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
{0xDCu, 0x11u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x03u, 0x59u},\r
- {0x05u, 0x44u},\r
- {0x07u, 0x40u},\r
- {0x0Au, 0x41u},\r
- {0x0Eu, 0x20u},\r
- {0x0Fu, 0x02u},\r
- {0x12u, 0x90u},\r
- {0x14u, 0x02u},\r
- {0x15u, 0x08u},\r
- {0x17u, 0x11u},\r
- {0x1Au, 0xD0u},\r
- {0x1Bu, 0x01u},\r
- {0x1Du, 0x40u},\r
- {0x1Eu, 0x27u},\r
- {0x1Fu, 0x40u},\r
- {0x24u, 0x40u},\r
- {0x27u, 0x88u},\r
- {0x2Du, 0x08u},\r
- {0x2Fu, 0x69u},\r
- {0x36u, 0x20u},\r
- {0x37u, 0x49u},\r
- {0x3Cu, 0x40u},\r
- {0x3Fu, 0x02u},\r
- {0x40u, 0x08u},\r
- {0x41u, 0x04u},\r
- {0x42u, 0x40u},\r
- {0x43u, 0x08u},\r
- {0x48u, 0x10u},\r
- {0x4Au, 0x81u},\r
- {0x51u, 0x80u},\r
- {0x52u, 0x18u},\r
- {0x53u, 0x20u},\r
- {0x59u, 0x06u},\r
- {0x5Au, 0x24u},\r
- {0x5Bu, 0x80u},\r
- {0x61u, 0x10u},\r
- {0x63u, 0x91u},\r
- {0x68u, 0x24u},\r
- {0x69u, 0x40u},\r
- {0x6Au, 0x02u},\r
- {0x70u, 0x80u},\r
- {0x72u, 0xA8u},\r
- {0x78u, 0x08u},\r
- {0x7Au, 0x10u},\r
- {0x82u, 0x50u},\r
- {0x83u, 0x08u},\r
- {0x86u, 0x01u},\r
- {0x88u, 0x14u},\r
- {0x8Du, 0x40u},\r
- {0x8Eu, 0x08u},\r
- {0x8Fu, 0x08u},\r
- {0xC0u, 0xBFu},\r
- {0xC2u, 0xA9u},\r
- {0xC4u, 0xFCu},\r
- {0xCAu, 0xF0u},\r
- {0xCCu, 0xF0u},\r
- {0xCEu, 0x90u},\r
- {0xD0u, 0x07u},\r
- {0xD2u, 0x08u},\r
+ {0x01u, 0x80u},\r
+ {0x03u, 0x10u},\r
+ {0x06u, 0x01u},\r
+ {0x08u, 0x08u},\r
+ {0x09u, 0x80u},\r
+ {0x0Au, 0x88u},\r
+ {0x0Eu, 0x04u},\r
+ {0x12u, 0x22u},\r
+ {0x13u, 0x10u},\r
+ {0x17u, 0x20u},\r
+ {0x18u, 0x20u},\r
+ {0x1Au, 0x80u},\r
+ {0x1Fu, 0x20u},\r
+ {0x21u, 0x21u},\r
+ {0x22u, 0x81u},\r
+ {0x25u, 0x02u},\r
+ {0x26u, 0x01u},\r
+ {0x27u, 0x08u},\r
+ {0x28u, 0x40u},\r
+ {0x29u, 0x90u},\r
+ {0x2Bu, 0x10u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Du, 0x80u},\r
+ {0x2Eu, 0x20u},\r
+ {0x2Fu, 0x40u},\r
+ {0x31u, 0x20u},\r
+ {0x32u, 0x84u},\r
+ {0x36u, 0x01u},\r
+ {0x37u, 0x18u},\r
+ {0x38u, 0x04u},\r
+ {0x39u, 0x82u},\r
+ {0x3Au, 0x20u},\r
+ {0x3Bu, 0x10u},\r
+ {0x3Cu, 0xA0u},\r
+ {0x3Fu, 0x08u},\r
+ {0x59u, 0x04u},\r
+ {0x5Au, 0x11u},\r
+ {0x5Bu, 0x40u},\r
+ {0x60u, 0x88u},\r
+ {0x61u, 0x80u},\r
+ {0x62u, 0x04u},\r
+ {0x63u, 0x08u},\r
+ {0x80u, 0x10u},\r
+ {0x82u, 0x02u},\r
+ {0x85u, 0x80u},\r
+ {0x89u, 0x04u},\r
+ {0x8Bu, 0x10u},\r
+ {0x8Cu, 0x04u},\r
+ {0x8Du, 0x04u},\r
+ {0x8Eu, 0x10u},\r
+ {0x8Fu, 0x10u},\r
+ {0x93u, 0x88u},\r
+ {0x95u, 0x84u},\r
+ {0x96u, 0x0Au},\r
+ {0x97u, 0x10u},\r
+ {0x98u, 0x10u},\r
+ {0x9Au, 0x82u},\r
+ {0x9Cu, 0x80u},\r
+ {0x9Du, 0xA2u},\r
+ {0x9Eu, 0x04u},\r
+ {0x9Fu, 0x14u},\r
+ {0xA0u, 0xC1u},\r
+ {0xA5u, 0x22u},\r
+ {0xA6u, 0xA2u},\r
+ {0xA9u, 0x80u},\r
+ {0xACu, 0x10u},\r
+ {0xAFu, 0x34u},\r
+ {0xB5u, 0x02u},\r
+ {0xB7u, 0x08u},\r
+ {0xC0u, 0x85u},\r
+ {0xC2u, 0x4Fu},\r
+ {0xC4u, 0x47u},\r
+ {0xCAu, 0xFFu},\r
+ {0xCCu, 0xEEu},\r
+ {0xCEu, 0x7Fu},\r
{0xD6u, 0x0Fu},\r
{0xD8u, 0x0Fu},\r
- {0xE0u, 0x05u},\r
- {0xE2u, 0x08u},\r
- {0xE4u, 0x03u},\r
- {0xE6u, 0xC0u},\r
- {0x0Du, 0x02u},\r
- {0x0Fu, 0x01u},\r
- {0x10u, 0x0Au},\r
- {0x11u, 0x04u},\r
- {0x12u, 0x05u},\r
+ {0xE0u, 0x08u},\r
+ {0xE2u, 0x20u},\r
+ {0xE4u, 0x04u},\r
+ {0xE6u, 0x21u},\r
+ {0xE8u, 0x0Eu},\r
+ {0xEAu, 0x10u},\r
+ {0xECu, 0x0Au},\r
+ {0x02u, 0x1Cu},\r
+ {0x04u, 0x28u},\r
+ {0x05u, 0x10u},\r
+ {0x06u, 0x14u},\r
+ {0x07u, 0x08u},\r
+ {0x0Cu, 0x10u},\r
+ {0x0Du, 0x01u},\r
+ {0x0Eu, 0x20u},\r
+ {0x0Fu, 0x02u},\r
+ {0x11u, 0x10u},\r
{0x13u, 0x08u},\r
- {0x15u, 0x02u},\r
- {0x16u, 0x07u},\r
- {0x17u, 0x11u},\r
- {0x19u, 0x01u},\r
- {0x1Bu, 0x06u},\r
- {0x1Cu, 0x09u},\r
- {0x1Du, 0x02u},\r
+ {0x19u, 0x08u},\r
+ {0x1Bu, 0x11u},\r
+ {0x1Du, 0x10u},\r
{0x1Eu, 0x02u},\r
- {0x1Fu, 0x09u},\r
- {0x22u, 0x08u},\r
- {0x24u, 0x04u},\r
- {0x25u, 0x02u},\r
- {0x26u, 0x08u},\r
- {0x27u, 0x21u},\r
- {0x31u, 0x0Cu},\r
- {0x32u, 0x0Fu},\r
+ {0x1Fu, 0x0Eu},\r
+ {0x22u, 0x20u},\r
+ {0x28u, 0x24u},\r
+ {0x2Au, 0x08u},\r
+ {0x2Du, 0x10u},\r
+ {0x2Eu, 0x01u},\r
+ {0x2Fu, 0x08u},\r
+ {0x30u, 0x02u},\r
+ {0x31u, 0x04u},\r
{0x33u, 0x03u},\r
- {0x35u, 0x20u},\r
- {0x37u, 0x10u},\r
- {0x3Bu, 0x08u},\r
- {0x3Fu, 0x01u},\r
+ {0x34u, 0x01u},\r
+ {0x35u, 0x18u},\r
+ {0x36u, 0x3Cu},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Fu, 0x04u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x83u, 0x70u},\r
- {0x86u, 0x01u},\r
- {0x87u, 0x07u},\r
- {0x88u, 0x40u},\r
- {0x8Bu, 0x80u},\r
- {0x8Eu, 0x10u},\r
- {0x95u, 0x99u},\r
- {0x96u, 0x04u},\r
- {0x97u, 0x22u},\r
- {0x9Bu, 0x08u},\r
- {0x9Du, 0xAAu},\r
- {0x9Eu, 0x02u},\r
- {0x9Fu, 0x55u},\r
- {0xA6u, 0x20u},\r
- {0xA9u, 0x44u},\r
- {0xAAu, 0x08u},\r
- {0xABu, 0x88u},\r
- {0xACu, 0x15u},\r
- {0xAEu, 0x2Au},\r
- {0xB0u, 0x40u},\r
- {0xB1u, 0xF0u},\r
- {0xB2u, 0x30u},\r
- {0xB3u, 0x0Fu},\r
- {0xB4u, 0x03u},\r
- {0xB6u, 0x0Cu},\r
- {0xBEu, 0x54u},\r
- {0xD6u, 0x08u},\r
+ {0x81u, 0x01u},\r
+ {0x84u, 0x04u},\r
+ {0x86u, 0x43u},\r
+ {0x8Cu, 0x21u},\r
+ {0x8Eu, 0x02u},\r
+ {0x8Fu, 0x01u},\r
+ {0x92u, 0x01u},\r
+ {0x96u, 0xECu},\r
+ {0x98u, 0x88u},\r
+ {0x9Au, 0x03u},\r
+ {0x9Cu, 0xE0u},\r
+ {0x9Du, 0x01u},\r
+ {0xA5u, 0x01u},\r
+ {0xA6u, 0x12u},\r
+ {0xA9u, 0x01u},\r
+ {0xAFu, 0x01u},\r
+ {0xB0u, 0x10u},\r
+ {0xB2u, 0x0Fu},\r
+ {0xB4u, 0xE0u},\r
+ {0xB5u, 0x01u},\r
+ {0xBEu, 0x10u},\r
+ {0xBFu, 0x10u},\r
+ {0xD4u, 0x40u},\r
+ {0xD6u, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x19u},\r
- {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x24u},\r
- {0x02u, 0x02u},\r
- {0x08u, 0x80u},\r
- {0x0Au, 0x10u},\r
- {0x0Eu, 0x62u},\r
- {0x0Fu, 0x20u},\r
- {0x10u, 0x06u},\r
- {0x12u, 0x20u},\r
- {0x14u, 0x10u},\r
- {0x16u, 0x80u},\r
- {0x18u, 0x20u},\r
- {0x19u, 0x80u},\r
- {0x1Bu, 0x22u},\r
- {0x1Eu, 0x30u},\r
- {0x21u, 0x05u},\r
- {0x22u, 0x02u},\r
- {0x24u, 0x80u},\r
- {0x25u, 0x41u},\r
- {0x27u, 0x68u},\r
- {0x2Bu, 0x08u},\r
- {0x2Fu, 0x10u},\r
- {0x30u, 0x20u},\r
- {0x31u, 0x04u},\r
- {0x32u, 0x40u},\r
- {0x36u, 0x80u},\r
- {0x37u, 0x2Au},\r
- {0x38u, 0x04u},\r
- {0x39u, 0x0Au},\r
- {0x3Au, 0x2Au},\r
- {0x3Du, 0x80u},\r
- {0x58u, 0x60u},\r
- {0x5Au, 0x04u},\r
- {0x5Du, 0x20u},\r
- {0x5Fu, 0x40u},\r
- {0x60u, 0x0Au},\r
- {0x62u, 0x08u},\r
- {0x67u, 0x0Au},\r
- {0x6Bu, 0x02u},\r
- {0x6Cu, 0x04u},\r
- {0x6Du, 0x40u},\r
- {0x6Fu, 0x10u},\r
- {0x80u, 0x04u},\r
- {0x81u, 0x40u},\r
- {0x84u, 0xA0u},\r
- {0x88u, 0x18u},\r
- {0x8Bu, 0x0Au},\r
- {0x8Du, 0x0Cu},\r
- {0x8Eu, 0x01u},\r
- {0x8Fu, 0x30u},\r
- {0x92u, 0xC0u},\r
- {0x93u, 0x40u},\r
- {0x96u, 0x20u},\r
- {0x97u, 0x13u},\r
- {0x99u, 0x20u},\r
- {0x9Au, 0xB0u},\r
- {0x9Cu, 0x02u},\r
- {0x9Du, 0x12u},\r
- {0x9Fu, 0x50u},\r
- {0xA0u, 0xA0u},\r
- {0xA1u, 0x80u},\r
- {0xA2u, 0x01u},\r
- {0xA7u, 0x48u},\r
- {0xA9u, 0x28u},\r
- {0xAFu, 0x01u},\r
- {0xB2u, 0x08u},\r
- {0xB3u, 0x40u},\r
- {0xB5u, 0x80u},\r
- {0xB6u, 0xA0u},\r
- {0xC0u, 0x07u},\r
- {0xC2u, 0xB5u},\r
- {0xC4u, 0x37u},\r
- {0xCAu, 0x44u},\r
- {0xCCu, 0xFEu},\r
- {0xCEu, 0x17u},\r
- {0xD6u, 0x3Eu},\r
- {0xD8u, 0x3Eu},\r
- {0xE6u, 0xCAu},\r
- {0xEAu, 0x02u},\r
- {0xECu, 0x04u},\r
- {0xEEu, 0x81u},\r
- {0x00u, 0x3Fu},\r
- {0x01u, 0x01u},\r
- {0x03u, 0x02u},\r
- {0x04u, 0x04u},\r
- {0x06u, 0x08u},\r
- {0x08u, 0x01u},\r
- {0x09u, 0x10u},\r
+ {0x01u, 0x80u},\r
+ {0x03u, 0x90u},\r
+ {0x04u, 0x44u},\r
{0x0Au, 0x02u},\r
- {0x0Bu, 0x20u},\r
- {0x0Cu, 0x10u},\r
- {0x0Du, 0x10u},\r
- {0x0Eu, 0x20u},\r
- {0x0Fu, 0x20u},\r
- {0x10u, 0x3Fu},\r
- {0x13u, 0x3Fu},\r
- {0x14u, 0x04u},\r
- {0x15u, 0x04u},\r
- {0x16u, 0x08u},\r
- {0x17u, 0x08u},\r
- {0x19u, 0x04u},\r
- {0x1Au, 0x3Fu},\r
- {0x1Bu, 0x08u},\r
- {0x1Cu, 0x10u},\r
- {0x1Du, 0x3Fu},\r
- {0x1Eu, 0x20u},\r
- {0x22u, 0x3Fu},\r
- {0x23u, 0x3Fu},\r
- {0x25u, 0x01u},\r
- {0x27u, 0x02u},\r
+ {0x0Eu, 0xA8u},\r
+ {0x0Fu, 0x01u},\r
+ {0x10u, 0x81u},\r
+ {0x13u, 0x10u},\r
+ {0x15u, 0x08u},\r
+ {0x18u, 0x08u},\r
+ {0x1Bu, 0xC1u},\r
+ {0x1Eu, 0xA0u},\r
+ {0x1Fu, 0x10u},\r
+ {0x20u, 0x20u},\r
+ {0x22u, 0x1Du},\r
+ {0x25u, 0x20u},\r
{0x28u, 0x01u},\r
- {0x2Au, 0x02u},\r
- {0x2Bu, 0x3Fu},\r
- {0x2Du, 0x3Fu},\r
- {0x2Eu, 0x3Fu},\r
- {0x30u, 0x03u},\r
- {0x33u, 0x30u},\r
- {0x34u, 0x0Cu},\r
- {0x35u, 0x0Cu},\r
- {0x36u, 0x30u},\r
- {0x37u, 0x03u},\r
- {0x3Au, 0xA2u},\r
- {0x3Bu, 0xA8u},\r
- {0x56u, 0x08u},\r
+ {0x2Bu, 0x01u},\r
+ {0x2Cu, 0x08u},\r
+ {0x2Fu, 0x21u},\r
+ {0x32u, 0x91u},\r
+ {0x37u, 0x40u},\r
+ {0x38u, 0x08u},\r
+ {0x39u, 0x40u},\r
+ {0x3Eu, 0x42u},\r
+ {0x45u, 0x20u},\r
+ {0x46u, 0x08u},\r
+ {0x58u, 0x80u},\r
+ {0x5Bu, 0x28u},\r
+ {0x61u, 0x14u},\r
+ {0x62u, 0x80u},\r
+ {0x63u, 0x20u},\r
+ {0x66u, 0x18u},\r
+ {0x67u, 0x42u},\r
+ {0x69u, 0x40u},\r
+ {0x6Du, 0x94u},\r
+ {0x80u, 0x08u},\r
+ {0x85u, 0x50u},\r
+ {0x88u, 0x80u},\r
+ {0x8Eu, 0x10u},\r
+ {0x8Fu, 0x41u},\r
+ {0x91u, 0x80u},\r
+ {0x92u, 0x80u},\r
+ {0x93u, 0x88u},\r
+ {0x95u, 0x04u},\r
+ {0x96u, 0x0Cu},\r
+ {0x97u, 0x10u},\r
+ {0x98u, 0x10u},\r
+ {0x9Au, 0x84u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Du, 0xB2u},\r
+ {0x9Eu, 0x01u},\r
+ {0x9Fu, 0x14u},\r
+ {0xA0u, 0xC1u},\r
+ {0xA1u, 0x01u},\r
+ {0xA4u, 0x10u},\r
+ {0xA6u, 0x20u},\r
+ {0xA7u, 0x10u},\r
+ {0xA8u, 0x20u},\r
+ {0xA9u, 0x40u},\r
+ {0xAAu, 0x02u},\r
+ {0xABu, 0x60u},\r
+ {0xB2u, 0x01u},\r
+ {0xB5u, 0x01u},\r
+ {0xB7u, 0x28u},\r
+ {0xC0u, 0xADu},\r
+ {0xC2u, 0xF1u},\r
+ {0xC4u, 0x2Bu},\r
+ {0xCAu, 0x78u},\r
+ {0xCCu, 0x1Du},\r
+ {0xCEu, 0x9Au},\r
+ {0xD6u, 0x0Eu},\r
+ {0xD8u, 0xFEu},\r
+ {0xE6u, 0x04u},\r
+ {0xEAu, 0x01u},\r
+ {0xEEu, 0x49u},\r
+ {0x02u, 0x10u},\r
+ {0x04u, 0x01u},\r
+ {0x05u, 0x0Au},\r
+ {0x07u, 0x55u},\r
+ {0x08u, 0x01u},\r
+ {0x09u, 0x8Bu},\r
+ {0x0Bu, 0x74u},\r
+ {0x0Cu, 0x01u},\r
+ {0x0Fu, 0x10u},\r
+ {0x12u, 0x01u},\r
+ {0x14u, 0x12u},\r
+ {0x15u, 0x20u},\r
+ {0x16u, 0x04u},\r
+ {0x17u, 0x40u},\r
+ {0x19u, 0x40u},\r
+ {0x1Au, 0x0Eu},\r
+ {0x1Bu, 0x80u},\r
+ {0x1Cu, 0x08u},\r
+ {0x1Eu, 0x10u},\r
+ {0x23u, 0x7Fu},\r
+ {0x25u, 0x01u},\r
+ {0x28u, 0x14u},\r
+ {0x29u, 0x06u},\r
+ {0x2Au, 0x0Au},\r
+ {0x2Cu, 0x01u},\r
+ {0x2Du, 0x91u},\r
+ {0x2Fu, 0x6Cu},\r
+ {0x32u, 0x01u},\r
+ {0x33u, 0x3Fu},\r
+ {0x34u, 0x1Eu},\r
+ {0x35u, 0xC0u},\r
+ {0x36u, 0x01u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Eu, 0x44u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
{0x5Cu, 0x11u},\r
- {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x82u, 0x70u},\r
- {0x84u, 0x0Fu},\r
- {0x8Du, 0x02u},\r
- {0x8Fu, 0x01u},\r
- {0x90u, 0x40u},\r
- {0x91u, 0x01u},\r
- {0x92u, 0x1Fu},\r
- {0x93u, 0x02u},\r
- {0x94u, 0x06u},\r
- {0x95u, 0x02u},\r
- {0x96u, 0x09u},\r
- {0x97u, 0x05u},\r
- {0x98u, 0x05u},\r
- {0x99u, 0x02u},\r
- {0x9Au, 0x0Au},\r
- {0x9Bu, 0x09u},\r
- {0x9Cu, 0x10u},\r
- {0x9Eu, 0x2Fu},\r
- {0xA4u, 0x03u},\r
- {0xA6u, 0x0Cu},\r
- {0xA9u, 0x02u},\r
- {0xABu, 0x11u},\r
- {0xACu, 0x20u},\r
- {0xAEu, 0x4Fu},\r
- {0xB0u, 0x7Fu},\r
- {0xB1u, 0x03u},\r
- {0xB3u, 0x08u},\r
- {0xB5u, 0x10u},\r
- {0xB7u, 0x04u},\r
+ {0x82u, 0x7Fu},\r
+ {0x84u, 0x78u},\r
+ {0x86u, 0x03u},\r
+ {0x88u, 0x20u},\r
+ {0x8Au, 0x40u},\r
+ {0x8Bu, 0xFFu},\r
+ {0x8Cu, 0x02u},\r
+ {0x8Fu, 0xFFu},\r
+ {0x91u, 0x0Fu},\r
+ {0x92u, 0x08u},\r
+ {0x93u, 0xF0u},\r
+ {0x94u, 0x01u},\r
+ {0x95u, 0xFFu},\r
+ {0x96u, 0x6Eu},\r
+ {0x98u, 0x64u},\r
+ {0x99u, 0xFFu},\r
+ {0x9Cu, 0x03u},\r
+ {0x9Eu, 0x74u},\r
+ {0xA1u, 0x55u},\r
+ {0xA3u, 0xAAu},\r
+ {0xA5u, 0x69u},\r
+ {0xA6u, 0x01u},\r
+ {0xA7u, 0x96u},\r
+ {0xA8u, 0x20u},\r
+ {0xA9u, 0x33u},\r
+ {0xAAu, 0x40u},\r
+ {0xABu, 0xCCu},\r
+ {0xAFu, 0xFFu},\r
+ {0xB1u, 0xFFu},\r
+ {0xB4u, 0x60u},\r
+ {0xB6u, 0x1Fu},\r
+ {0xBAu, 0x20u},\r
{0xBBu, 0x02u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
{0xDCu, 0x11u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x04u},\r
- {0x01u, 0x60u},\r
- {0x03u, 0x40u},\r
- {0x05u, 0x01u},\r
- {0x07u, 0x13u},\r
- {0x08u, 0x08u},\r
- {0x0Au, 0x46u},\r
- {0x0Cu, 0x60u},\r
- {0x0Du, 0x08u},\r
- {0x0Eu, 0x02u},\r
- {0x0Fu, 0x40u},\r
- {0x10u, 0x40u},\r
- {0x11u, 0x10u},\r
- {0x13u, 0x40u},\r
- {0x14u, 0x01u},\r
- {0x17u, 0x04u},\r
- {0x18u, 0x04u},\r
- {0x19u, 0x12u},\r
- {0x1Au, 0x02u},\r
- {0x1Bu, 0x40u},\r
- {0x1Du, 0x01u},\r
- {0x1Eu, 0x80u},\r
- {0x22u, 0x10u},\r
- {0x23u, 0x11u},\r
- {0x24u, 0x40u},\r
- {0x25u, 0x40u},\r
- {0x26u, 0x16u},\r
- {0x28u, 0x51u},\r
- {0x2Bu, 0x08u},\r
- {0x2Cu, 0x01u},\r
- {0x2Eu, 0x40u},\r
- {0x2Fu, 0x04u},\r
- {0x32u, 0x18u},\r
- {0x33u, 0x41u},\r
- {0x36u, 0x16u},\r
+ {0x00u, 0x80u},\r
+ {0x01u, 0x20u},\r
+ {0x02u, 0x40u},\r
+ {0x03u, 0x10u},\r
+ {0x04u, 0xA8u},\r
+ {0x06u, 0x80u},\r
+ {0x0Au, 0x09u},\r
+ {0x0Bu, 0x90u},\r
+ {0x0Eu, 0x45u},\r
+ {0x0Fu, 0x10u},\r
+ {0x11u, 0x04u},\r
+ {0x12u, 0x04u},\r
+ {0x16u, 0x02u},\r
+ {0x17u, 0x10u},\r
+ {0x19u, 0xA0u},\r
+ {0x1Au, 0x01u},\r
+ {0x1Eu, 0x06u},\r
+ {0x1Fu, 0x08u},\r
+ {0x22u, 0x02u},\r
+ {0x25u, 0x04u},\r
+ {0x26u, 0x10u},\r
+ {0x27u, 0x14u},\r
+ {0x28u, 0x40u},\r
+ {0x29u, 0x94u},\r
+ {0x2Du, 0x84u},\r
+ {0x2Fu, 0x84u},\r
+ {0x32u, 0x06u},\r
+ {0x33u, 0x10u},\r
+ {0x36u, 0x18u},\r
{0x39u, 0x80u},\r
- {0x3Bu, 0x11u},\r
- {0x3Du, 0x80u},\r
- {0x5Au, 0x80u},\r
- {0x5Cu, 0x60u},\r
- {0x5Fu, 0x0Au},\r
- {0x62u, 0xC0u},\r
- {0x66u, 0x80u},\r
- {0x84u, 0x30u},\r
- {0x85u, 0x12u},\r
- {0x8Au, 0x08u},\r
- {0x8Du, 0x40u},\r
- {0x8Eu, 0x40u},\r
- {0x90u, 0x80u},\r
- {0x91u, 0x80u},\r
- {0x92u, 0x40u},\r
- {0x93u, 0x0Au},\r
- {0x96u, 0x20u},\r
- {0x97u, 0x31u},\r
- {0x98u, 0x0Au},\r
- {0x9Au, 0x1Au},\r
- {0x9Bu, 0x70u},\r
- {0x9Cu, 0x04u},\r
- {0x9Du, 0x12u},\r
- {0xA0u, 0x80u},\r
- {0xA1u, 0x89u},\r
- {0xA2u, 0x09u},\r
- {0xA3u, 0x10u},\r
- {0xA4u, 0x12u},\r
- {0xA6u, 0xA0u},\r
- {0xA7u, 0x48u},\r
- {0xA9u, 0x40u},\r
- {0xACu, 0x40u},\r
- {0xB1u, 0x80u},\r
- {0xB2u, 0x04u},\r
- {0xB4u, 0x50u},\r
- {0xC0u, 0x3Fu},\r
- {0xC2u, 0xFFu},\r
- {0xC4u, 0xABu},\r
- {0xCAu, 0x2Fu},\r
- {0xCCu, 0xEFu},\r
- {0xCEu, 0x1Du},\r
- {0xD6u, 0xF8u},\r
- {0xD8u, 0x18u},\r
- {0xE2u, 0x02u},\r
- {0xE6u, 0x02u},\r
- {0xEAu, 0x03u},\r
- {0xEEu, 0xC8u},\r
- {0x00u, 0x01u},\r
- {0x01u, 0xFFu},\r
- {0x02u, 0x0Eu},\r
- {0x04u, 0x02u},\r
- {0x07u, 0xFFu},\r
- {0x09u, 0x0Fu},\r
- {0x0Bu, 0xF0u},\r
- {0x0Cu, 0x04u},\r
- {0x0Du, 0xFFu},\r
- {0x10u, 0x18u},\r
- {0x11u, 0x69u},\r
- {0x12u, 0x03u},\r
- {0x13u, 0x96u},\r
- {0x14u, 0x03u},\r
- {0x15u, 0x55u},\r
- {0x16u, 0x14u},\r
- {0x17u, 0xAAu},\r
- {0x1Au, 0x1Fu},\r
- {0x1Eu, 0x08u},\r
- {0x22u, 0x20u},\r
- {0x23u, 0xFFu},\r
- {0x2Au, 0x01u},\r
- {0x2Bu, 0xFFu},\r
- {0x2Du, 0x33u},\r
- {0x2Fu, 0xCCu},\r
- {0x32u, 0x1Fu},\r
- {0x34u, 0x20u},\r
- {0x35u, 0xFFu},\r
- {0x3Bu, 0x20u},\r
- {0x54u, 0x01u},\r
- {0x58u, 0x04u},\r
- {0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
- {0x5Du, 0x10u},\r
- {0x5Fu, 0x01u},\r
- {0x81u, 0x04u},\r
- {0x82u, 0x10u},\r
+ {0x3Au, 0x40u},\r
+ {0x3Bu, 0x10u},\r
+ {0x3Cu, 0x80u},\r
+ {0x3Du, 0x08u},\r
+ {0x3Fu, 0x10u},\r
+ {0x41u, 0x40u},\r
+ {0x43u, 0x80u},\r
+ {0x58u, 0x80u},\r
+ {0x5Bu, 0x20u},\r
+ {0x62u, 0x20u},\r
+ {0x63u, 0x02u},\r
+ {0x78u, 0x40u},\r
+ {0x7Bu, 0x01u},\r
{0x83u, 0x20u},\r
- {0x85u, 0x01u},\r
- {0x87u, 0x5Eu},\r
- {0x88u, 0x04u},\r
- {0x89u, 0x39u},\r
- {0x8Au, 0x08u},\r
- {0x8Bu, 0x06u},\r
- {0x8Du, 0x46u},\r
- {0x8Eu, 0x07u},\r
- {0x90u, 0x0Au},\r
- {0x91u, 0x46u},\r
- {0x92u, 0x05u},\r
- {0x97u, 0x46u},\r
- {0x99u, 0x42u},\r
- {0x9Bu, 0x04u},\r
- {0x9Cu, 0x09u},\r
- {0x9Du, 0x46u},\r
- {0x9Eu, 0x02u},\r
- {0xA1u, 0x42u},\r
+ {0x84u, 0x80u},\r
+ {0x8Fu, 0x10u},\r
+ {0x91u, 0x85u},\r
+ {0x92u, 0x88u},\r
+ {0x93u, 0x88u},\r
+ {0x94u, 0x44u},\r
+ {0x95u, 0x08u},\r
+ {0x96u, 0x44u},\r
+ {0x97u, 0x12u},\r
+ {0x98u, 0x18u},\r
+ {0x99u, 0x14u},\r
+ {0x9Au, 0x85u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Du, 0xA2u},\r
+ {0x9Eu, 0x12u},\r
+ {0x9Fu, 0x54u},\r
+ {0xA0u, 0x41u},\r
+ {0xA1u, 0x01u},\r
{0xA2u, 0x08u},\r
- {0xA4u, 0x10u},\r
- {0xA6u, 0x20u},\r
- {0xAAu, 0x20u},\r
- {0xADu, 0x77u},\r
- {0xAFu, 0x08u},\r
- {0xB0u, 0x0Fu},\r
- {0xB1u, 0x08u},\r
- {0xB2u, 0x30u},\r
- {0xB3u, 0x70u},\r
- {0xB5u, 0x0Fu},\r
- {0xB7u, 0x01u},\r
- {0xB8u, 0x80u},\r
- {0xB9u, 0x20u},\r
- {0xBBu, 0x0Cu},\r
- {0xBEu, 0x44u},\r
- {0xBFu, 0x41u},\r
- {0xD4u, 0x09u},\r
- {0xD6u, 0x04u},\r
- {0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x01u},\r
- {0xDFu, 0x01u},\r
- {0x00u, 0x40u},\r
- {0x02u, 0x80u},\r
- {0x03u, 0x08u},\r
- {0x04u, 0x80u},\r
- {0x05u, 0x02u},\r
- {0x06u, 0x10u},\r
- {0x0Au, 0x41u},\r
- {0x0Du, 0x80u},\r
- {0x0Eu, 0x64u},\r
- {0x10u, 0x80u},\r
- {0x13u, 0x28u},\r
- {0x16u, 0x40u},\r
- {0x17u, 0x10u},\r
- {0x18u, 0x40u},\r
- {0x1Au, 0x20u},\r
- {0x1Bu, 0x40u},\r
- {0x1Eu, 0x20u},\r
- {0x1Fu, 0x18u},\r
- {0x20u, 0x08u},\r
- {0x21u, 0x14u},\r
- {0x23u, 0x95u},\r
- {0x25u, 0x10u},\r
- {0x27u, 0x04u},\r
- {0x29u, 0x41u},\r
- {0x2Eu, 0x01u},\r
- {0x2Fu, 0x09u},\r
- {0x30u, 0x28u},\r
- {0x33u, 0x41u},\r
- {0x34u, 0x02u},\r
- {0x36u, 0x08u},\r
- {0x38u, 0x02u},\r
- {0x39u, 0x6Au},\r
- {0x3Du, 0x22u},\r
- {0x3Eu, 0x44u},\r
- {0x58u, 0x20u},\r
- {0x59u, 0x04u},\r
- {0x5Au, 0x02u},\r
- {0x5Bu, 0x80u},\r
- {0x5Du, 0x02u},\r
- {0x5Eu, 0x83u},\r
- {0x62u, 0x01u},\r
- {0x63u, 0x01u},\r
- {0x68u, 0x02u},\r
- {0x80u, 0x21u},\r
- {0x83u, 0x40u},\r
- {0x8Au, 0xA0u},\r
- {0x8Cu, 0x40u},\r
- {0x90u, 0x80u},\r
- {0x92u, 0x44u},\r
- {0x93u, 0x02u},\r
- {0x97u, 0x20u},\r
- {0x98u, 0x06u},\r
- {0x9Au, 0x52u},\r
- {0x9Bu, 0x10u},\r
- {0x9Fu, 0x04u},\r
- {0xA0u, 0x80u},\r
- {0xA1u, 0x81u},\r
- {0xA2u, 0x49u},\r
- {0xA3u, 0x10u},\r
- {0xA4u, 0x12u},\r
- {0xA6u, 0x20u},\r
- {0xA7u, 0x08u},\r
- {0xA8u, 0x20u},\r
- {0xA9u, 0x20u},\r
- {0xAAu, 0x80u},\r
+ {0xA4u, 0x08u},\r
+ {0xA6u, 0x24u},\r
+ {0xA7u, 0x20u},\r
+ {0xAAu, 0x01u},\r
{0xABu, 0x20u},\r
- {0xACu, 0x10u},\r
- {0xAEu, 0x04u},\r
- {0xAFu, 0x09u},\r
- {0xB0u, 0x04u},\r
- {0xB3u, 0x48u},\r
- {0xB6u, 0x01u},\r
- {0xB7u, 0x10u},\r
- {0xC0u, 0xBBu},\r
- {0xC2u, 0xF9u},\r
- {0xC4u, 0x5Eu},\r
- {0xCAu, 0xB9u},\r
- {0xCCu, 0xCFu},\r
- {0xCEu, 0xFFu},\r
- {0xD6u, 0x1Fu},\r
- {0xD8u, 0x09u},\r
- {0xE2u, 0x09u},\r
- {0xE6u, 0x02u},\r
- {0xEAu, 0x02u},\r
- {0xEEu, 0x07u},\r
- {0x88u, 0x04u},\r
+ {0xAFu, 0x18u},\r
+ {0xB1u, 0x03u},\r
+ {0xB3u, 0x40u},\r
+ {0xC0u, 0xFFu},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0xC6u},\r
+ {0xCAu, 0xFFu},\r
+ {0xCCu, 0x67u},\r
+ {0xCEu, 0x7Cu},\r
+ {0xD6u, 0x0Cu},\r
+ {0xD8u, 0x0Cu},\r
+ {0xE2u, 0x01u},\r
+ {0xE6u, 0x06u},\r
+ {0xEAu, 0x2Fu},\r
+ {0xEEu, 0x20u},\r
+ {0x65u, 0x08u},\r
+ {0x66u, 0x08u},\r
+ {0x81u, 0x01u},\r
+ {0x82u, 0x04u},\r
{0x89u, 0x40u},\r
- {0x8Fu, 0x04u},\r
- {0x99u, 0x40u},\r
- {0x9Cu, 0x84u},\r
- {0xA0u, 0x24u},\r
- {0xA7u, 0x04u},\r
- {0xA8u, 0x02u},\r
- {0xA9u, 0x10u},\r
- {0xAAu, 0x40u},\r
- {0xAEu, 0x20u},\r
- {0xAFu, 0x04u},\r
- {0xB0u, 0x42u},\r
- {0xB6u, 0x08u},\r
- {0xB7u, 0x08u},\r
- {0xE0u, 0x40u},\r
- {0xE2u, 0xA9u},\r
+ {0x8Du, 0x04u},\r
+ {0x8Eu, 0x21u},\r
+ {0x91u, 0x60u},\r
+ {0x94u, 0x30u},\r
+ {0x95u, 0x92u},\r
+ {0x98u, 0x0Cu},\r
+ {0x9Au, 0x04u},\r
+ {0x9Bu, 0x42u},\r
+ {0x9Du, 0x48u},\r
+ {0x9Eu, 0x1Au},\r
+ {0xA0u, 0x30u},\r
+ {0xA2u, 0x04u},\r
+ {0xA3u, 0x08u},\r
+ {0xA5u, 0x40u},\r
+ {0xA9u, 0x01u},\r
+ {0xB2u, 0x20u},\r
+ {0xB3u, 0x04u},\r
+ {0xE0u, 0x04u},\r
+ {0xE2u, 0x01u},\r
+ {0xE4u, 0x40u},\r
{0xE6u, 0x02u},\r
- {0xE8u, 0x10u},\r
- {0xEAu, 0x04u},\r
- {0xECu, 0x40u},\r
- {0xEEu, 0x80u},\r
- {0x02u, 0xFFu},\r
- {0x05u, 0x10u},\r
- {0x06u, 0xFFu},\r
- {0x08u, 0x50u},\r
- {0x0Au, 0xA0u},\r
- {0x0Bu, 0x08u},\r
+ {0xE8u, 0x80u},\r
+ {0xEAu, 0x0Bu},\r
+ {0xEEu, 0xA0u},\r
+ {0x00u, 0xFFu},\r
+ {0x03u, 0x02u},\r
+ {0x04u, 0x03u},\r
+ {0x06u, 0x0Cu},\r
+ {0x07u, 0x04u},\r
+ {0x08u, 0x09u},\r
+ {0x0Au, 0x06u},\r
+ {0x0Du, 0x02u},\r
{0x0Fu, 0x04u},\r
- {0x10u, 0x05u},\r
- {0x12u, 0x0Au},\r
- {0x13u, 0x02u},\r
- {0x14u, 0x0Fu},\r
- {0x15u, 0x05u},\r
- {0x16u, 0xF0u},\r
- {0x17u, 0x0Au},\r
- {0x18u, 0x03u},\r
- {0x1Au, 0x0Cu},\r
- {0x1Cu, 0x06u},\r
- {0x1Eu, 0x09u},\r
- {0x20u, 0xFFu},\r
- {0x23u, 0x01u},\r
+ {0x10u, 0x0Fu},\r
+ {0x12u, 0xF0u},\r
+ {0x16u, 0xFFu},\r
+ {0x18u, 0xFFu},\r
+ {0x20u, 0x05u},\r
+ {0x22u, 0x0Au},\r
{0x24u, 0x30u},\r
{0x26u, 0xC0u},\r
- {0x2Cu, 0x60u},\r
- {0x2Eu, 0x90u},\r
- {0x31u, 0x0Cu},\r
- {0x33u, 0x03u},\r
- {0x35u, 0x10u},\r
- {0x36u, 0xFFu},\r
- {0x3Eu, 0x40u},\r
- {0x3Fu, 0x05u},\r
+ {0x28u, 0x50u},\r
+ {0x2Au, 0xA0u},\r
+ {0x2Cu, 0x90u},\r
+ {0x2Eu, 0x60u},\r
+ {0x2Fu, 0x01u},\r
+ {0x30u, 0xFFu},\r
+ {0x33u, 0x06u},\r
+ {0x35u, 0x01u},\r
+ {0x3Eu, 0x01u},\r
+ {0x3Fu, 0x04u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x90u},\r
+ {0x5Cu, 0x10u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x02u},\r
- {0x81u, 0x09u},\r
- {0x82u, 0x01u},\r
- {0x83u, 0x06u},\r
- {0x85u, 0x30u},\r
- {0x86u, 0x80u},\r
- {0x87u, 0xC0u},\r
- {0x88u, 0x01u},\r
- {0x89u, 0x50u},\r
- {0x8Au, 0x02u},\r
- {0x8Bu, 0xA0u},\r
- {0x8Du, 0x03u},\r
- {0x8Eu, 0x70u},\r
- {0x8Fu, 0x0Cu},\r
- {0x93u, 0xFFu},\r
- {0x94u, 0x02u},\r
- {0x96u, 0x05u},\r
- {0x97u, 0xFFu},\r
- {0x9Cu, 0x02u},\r
- {0x9Eu, 0x01u},\r
- {0x9Fu, 0xFFu},\r
- {0xA0u, 0x40u},\r
- {0xA1u, 0x05u},\r
- {0xA2u, 0x80u},\r
- {0xA3u, 0x0Au},\r
- {0xA4u, 0xA0u},\r
- {0xA6u, 0x50u},\r
- {0xA8u, 0x90u},\r
- {0xA9u, 0x0Fu},\r
- {0xAAu, 0x20u},\r
- {0xABu, 0xF0u},\r
+ {0x80u, 0x40u},\r
+ {0x81u, 0x08u},\r
+ {0x82u, 0x20u},\r
+ {0x83u, 0x10u},\r
+ {0x84u, 0x01u},\r
+ {0x86u, 0x02u},\r
+ {0x88u, 0x08u},\r
+ {0x8Au, 0x10u},\r
+ {0x8Bu, 0x10u},\r
+ {0x8Du, 0x01u},\r
+ {0x8Fu, 0x66u},\r
+ {0x91u, 0x04u},\r
+ {0x93u, 0x03u},\r
+ {0x94u, 0x06u},\r
+ {0x97u, 0x20u},\r
+ {0x98u, 0x10u},\r
+ {0x9Au, 0x08u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Cu, 0x18u},\r
+ {0x9Eu, 0x60u},\r
+ {0xA0u, 0x20u},\r
+ {0xA1u, 0xC5u},\r
+ {0xA2u, 0x40u},\r
+ {0xA3u, 0x02u},\r
+ {0xA8u, 0x01u},\r
+ {0xA9u, 0x03u},\r
+ {0xAAu, 0x04u},\r
+ {0xABu, 0xA4u},\r
{0xACu, 0x02u},\r
- {0xADu, 0x90u},\r
- {0xAEu, 0x09u},\r
- {0xAFu, 0x60u},\r
- {0xB0u, 0x04u},\r
- {0xB2u, 0x08u},\r
- {0xB4u, 0x03u},\r
- {0xB5u, 0xFFu},\r
- {0xB6u, 0xF0u},\r
- {0xBAu, 0x20u},\r
+ {0xAEu, 0x01u},\r
+ {0xB2u, 0x07u},\r
+ {0xB3u, 0xE0u},\r
+ {0xB5u, 0x18u},\r
+ {0xB6u, 0x78u},\r
+ {0xB7u, 0x07u},\r
+ {0xB8u, 0x08u},\r
+ {0xBBu, 0x80u},\r
+ {0xBEu, 0x40u},\r
{0xBFu, 0x10u},\r
- {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x01u},\r
- {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x18u},\r
- {0x03u, 0x40u},\r
- {0x05u, 0x55u},\r
- {0x08u, 0x14u},\r
- {0x0Au, 0x01u},\r
- {0x0Bu, 0x80u},\r
- {0x0Du, 0x80u},\r
- {0x0Eu, 0x20u},\r
- {0x11u, 0x44u},\r
- {0x13u, 0x02u},\r
- {0x15u, 0x82u},\r
- {0x16u, 0x28u},\r
- {0x18u, 0x02u},\r
- {0x1Du, 0x51u},\r
- {0x1Eu, 0x20u},\r
- {0x20u, 0x80u},\r
- {0x22u, 0x28u},\r
- {0x27u, 0x04u},\r
- {0x2Au, 0x02u},\r
- {0x2Cu, 0x04u},\r
- {0x2Fu, 0x42u},\r
- {0x30u, 0x04u},\r
- {0x33u, 0x02u},\r
- {0x34u, 0x80u},\r
- {0x35u, 0x08u},\r
- {0x37u, 0x49u},\r
- {0x39u, 0x10u},\r
- {0x3Bu, 0x84u},\r
- {0x3Du, 0x14u},\r
- {0x3Eu, 0x03u},\r
- {0x3Fu, 0x40u},\r
- {0x58u, 0x40u},\r
- {0x5Eu, 0x40u},\r
- {0x5Fu, 0x10u},\r
+ {0x01u, 0x08u},\r
+ {0x02u, 0x04u},\r
+ {0x03u, 0x80u},\r
+ {0x04u, 0x20u},\r
+ {0x06u, 0x10u},\r
+ {0x07u, 0x40u},\r
+ {0x0Bu, 0xA8u},\r
+ {0x0Du, 0x70u},\r
+ {0x0Eu, 0x10u},\r
+ {0x0Fu, 0x02u},\r
+ {0x10u, 0x28u},\r
+ {0x11u, 0x41u},\r
+ {0x15u, 0x10u},\r
+ {0x16u, 0x02u},\r
+ {0x17u, 0x02u},\r
+ {0x19u, 0x02u},\r
+ {0x1Eu, 0x10u},\r
+ {0x1Fu, 0x80u},\r
+ {0x23u, 0x14u},\r
+ {0x24u, 0x02u},\r
+ {0x26u, 0x14u},\r
+ {0x27u, 0x01u},\r
+ {0x28u, 0x02u},\r
+ {0x2Du, 0x10u},\r
+ {0x2Eu, 0x02u},\r
+ {0x36u, 0x24u},\r
+ {0x37u, 0x01u},\r
+ {0x38u, 0x08u},\r
+ {0x39u, 0x83u},\r
+ {0x3Bu, 0x80u},\r
+ {0x3Du, 0x80u},\r
+ {0x3Eu, 0x20u},\r
+ {0x3Fu, 0x02u},\r
+ {0x59u, 0x40u},\r
{0x60u, 0x02u},\r
- {0x63u, 0x02u},\r
- {0x65u, 0x20u},\r
- {0x66u, 0x80u},\r
- {0x67u, 0x02u},\r
- {0x85u, 0x20u},\r
- {0x86u, 0x04u},\r
- {0x88u, 0x50u},\r
- {0x8Bu, 0x48u},\r
- {0x8Eu, 0x08u},\r
+ {0x6Cu, 0x2Cu},\r
+ {0x6Du, 0x40u},\r
+ {0x6Eu, 0x40u},\r
+ {0x6Fu, 0x46u},\r
+ {0x74u, 0x10u},\r
+ {0x75u, 0x01u},\r
+ {0x76u, 0x20u},\r
+ {0x77u, 0x02u},\r
+ {0x80u, 0x01u},\r
+ {0x8Bu, 0x10u},\r
+ {0x8Du, 0x20u},\r
+ {0x8Eu, 0x10u},\r
{0x8Fu, 0x01u},\r
- {0x91u, 0xD6u},\r
- {0x92u, 0x05u},\r
- {0x93u, 0x94u},\r
- {0x94u, 0x02u},\r
- {0x99u, 0x04u},\r
- {0x9Au, 0x20u},\r
- {0x9Bu, 0x03u},\r
- {0x9Cu, 0x14u},\r
- {0x9Du, 0x28u},\r
- {0x9Eu, 0x82u},\r
- {0x9Fu, 0x44u},\r
- {0xA0u, 0x26u},\r
- {0xA1u, 0x80u},\r
- {0xA3u, 0x02u},\r
- {0xA7u, 0x0Du},\r
- {0xABu, 0x01u},\r
- {0xAEu, 0x40u},\r
- {0xAFu, 0x20u},\r
- {0xB3u, 0x10u},\r
- {0xB7u, 0x80u},\r
- {0xC0u, 0xFEu},\r
- {0xC2u, 0xAFu},\r
- {0xC4u, 0xFDu},\r
- {0xCAu, 0xB1u},\r
- {0xCCu, 0xD3u},\r
- {0xCEu, 0xFEu},\r
- {0xD6u, 0x38u},\r
- {0xD8u, 0x38u},\r
- {0xE0u, 0x20u},\r
- {0xE2u, 0x50u},\r
- {0xECu, 0x10u},\r
- {0xEEu, 0x2Au},\r
- {0x04u, 0xFFu},\r
- {0x05u, 0x01u},\r
- {0x07u, 0x12u},\r
- {0x08u, 0x55u},\r
- {0x0Au, 0xAAu},\r
- {0x0Du, 0x04u},\r
- {0x0Fu, 0x28u},\r
- {0x15u, 0x53u},\r
- {0x16u, 0xFFu},\r
- {0x17u, 0xACu},\r
- {0x18u, 0x0Fu},\r
- {0x19u, 0x02u},\r
- {0x1Au, 0xF0u},\r
- {0x1Bu, 0x41u},\r
- {0x1Cu, 0x33u},\r
- {0x1Eu, 0xCCu},\r
- {0x21u, 0x08u},\r
- {0x22u, 0xFFu},\r
- {0x23u, 0x84u},\r
- {0x24u, 0x69u},\r
- {0x26u, 0x96u},\r
- {0x2Au, 0xFFu},\r
- {0x2Cu, 0xFFu},\r
- {0x31u, 0xC0u},\r
- {0x33u, 0x30u},\r
- {0x34u, 0xFFu},\r
- {0x37u, 0x0Fu},\r
- {0x3Au, 0x20u},\r
- {0x3Fu, 0x45u},\r
- {0x56u, 0x08u},\r
+ {0x93u, 0x20u},\r
+ {0x94u, 0x10u},\r
+ {0x95u, 0x83u},\r
+ {0x96u, 0x40u},\r
+ {0x97u, 0x0Eu},\r
+ {0x98u, 0x0Cu},\r
+ {0x9Au, 0x04u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Du, 0x0Au},\r
+ {0x9Eu, 0x08u},\r
+ {0x9Fu, 0x04u},\r
+ {0xA2u, 0x20u},\r
+ {0xA3u, 0x08u},\r
+ {0xA4u, 0x28u},\r
+ {0xA6u, 0x10u},\r
+ {0xA7u, 0x82u},\r
+ {0xABu, 0x21u},\r
+ {0xAEu, 0x10u},\r
+ {0xB1u, 0x04u},\r
+ {0xB3u, 0x40u},\r
+ {0xB5u, 0x40u},\r
+ {0xB6u, 0x22u},\r
+ {0xC0u, 0x7Eu},\r
+ {0xC2u, 0xEEu},\r
+ {0xC4u, 0xDFu},\r
+ {0xCAu, 0xA8u},\r
+ {0xCCu, 0xE0u},\r
+ {0xCEu, 0xBBu},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x08u},\r
+ {0xE0u, 0x40u},\r
+ {0xE2u, 0x20u},\r
+ {0xE4u, 0x40u},\r
+ {0xE6u, 0x10u},\r
+ {0xEAu, 0x10u},\r
+ {0xEEu, 0x91u},\r
+ {0x01u, 0x04u},\r
+ {0x03u, 0x03u},\r
+ {0x07u, 0x38u},\r
+ {0x09u, 0x04u},\r
+ {0x0Bu, 0x02u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Fu, 0x04u},\r
+ {0x10u, 0x02u},\r
+ {0x11u, 0x04u},\r
+ {0x13u, 0x82u},\r
+ {0x15u, 0x20u},\r
+ {0x17u, 0x40u},\r
+ {0x19u, 0x04u},\r
+ {0x1Bu, 0x02u},\r
+ {0x21u, 0x48u},\r
+ {0x23u, 0x10u},\r
+ {0x28u, 0x01u},\r
+ {0x29u, 0x50u},\r
+ {0x2Bu, 0x28u},\r
+ {0x2Fu, 0x40u},\r
+ {0x30u, 0x02u},\r
+ {0x31u, 0x06u},\r
+ {0x33u, 0x80u},\r
+ {0x34u, 0x01u},\r
+ {0x35u, 0x78u},\r
+ {0x37u, 0x01u},\r
+ {0x3Bu, 0x02u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x01u},\r
- {0x5Du, 0x90u},\r
+ {0x5Cu, 0x19u},\r
{0x5Fu, 0x01u},\r
{0x80u, 0xFFu},\r
- {0x81u, 0xFFu},\r
- {0x85u, 0x30u},\r
- {0x86u, 0xFFu},\r
- {0x87u, 0xC0u},\r
- {0x88u, 0x03u},\r
- {0x89u, 0x50u},\r
- {0x8Au, 0x0Cu},\r
- {0x8Bu, 0xA0u},\r
- {0x8Du, 0x05u},\r
- {0x8Fu, 0x0Au},\r
- {0x90u, 0x05u},\r
- {0x91u, 0x60u},\r
- {0x92u, 0x0Au},\r
- {0x93u, 0x90u},\r
- {0x94u, 0x0Fu},\r
- {0x96u, 0xF0u},\r
- {0x99u, 0x03u},\r
- {0x9Bu, 0x0Cu},\r
- {0x9Cu, 0x09u},\r
- {0x9Eu, 0x06u},\r
- {0x9Fu, 0xFFu},\r
- {0xA0u, 0xFFu},\r
- {0xA1u, 0x06u},\r
- {0xA3u, 0x09u},\r
+ {0x84u, 0x03u},\r
+ {0x85u, 0x04u},\r
+ {0x86u, 0x0Cu},\r
+ {0x87u, 0x12u},\r
+ {0x88u, 0x50u},\r
+ {0x89u, 0x04u},\r
+ {0x8Au, 0xA0u},\r
+ {0x8Bu, 0x02u},\r
+ {0x8Du, 0x02u},\r
+ {0x8Fu, 0x04u},\r
+ {0x90u, 0x60u},\r
+ {0x92u, 0x90u},\r
+ {0x95u, 0x01u},\r
+ {0x96u, 0xFFu},\r
+ {0x99u, 0x04u},\r
+ {0x9Au, 0xFFu},\r
+ {0x9Bu, 0x0Au},\r
+ {0x9Du, 0x01u},\r
+ {0xA0u, 0x05u},\r
+ {0xA1u, 0x01u},\r
+ {0xA2u, 0x0Au},\r
{0xA4u, 0x30u},\r
{0xA6u, 0xC0u},\r
- {0xA7u, 0xFFu},\r
- {0xA8u, 0x50u},\r
- {0xA9u, 0x0Fu},\r
- {0xAAu, 0xA0u},\r
- {0xABu, 0xF0u},\r
- {0xACu, 0x90u},\r
- {0xAEu, 0x60u},\r
- {0xB2u, 0xFFu},\r
- {0xB7u, 0xFFu},\r
- {0xBEu, 0x04u},\r
+ {0xA8u, 0x06u},\r
+ {0xA9u, 0x01u},\r
+ {0xAAu, 0x09u},\r
+ {0xACu, 0x0Fu},\r
+ {0xADu, 0x04u},\r
+ {0xAEu, 0xF0u},\r
+ {0xAFu, 0x02u},\r
+ {0xB1u, 0x06u},\r
+ {0xB3u, 0x08u},\r
+ {0xB4u, 0xFFu},\r
+ {0xB5u, 0x10u},\r
+ {0xB7u, 0x01u},\r
+ {0xB9u, 0x80u},\r
+ {0xBBu, 0x02u},\r
+ {0xBEu, 0x10u},\r
{0xBFu, 0x40u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDCu, 0x10u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x09u},\r
- {0x03u, 0x48u},\r
- {0x05u, 0x20u},\r
- {0x06u, 0x20u},\r
- {0x08u, 0x04u},\r
- {0x0Au, 0x01u},\r
- {0x0Bu, 0x80u},\r
- {0x0Cu, 0x08u},\r
- {0x0Eu, 0x04u},\r
- {0x0Fu, 0x22u},\r
- {0x11u, 0x54u},\r
- {0x13u, 0x02u},\r
- {0x14u, 0x20u},\r
- {0x15u, 0x22u},\r
- {0x17u, 0x80u},\r
- {0x18u, 0x20u},\r
+ {0x01u, 0x08u},\r
+ {0x03u, 0x84u},\r
+ {0x0Au, 0x40u},\r
+ {0x0Bu, 0x28u},\r
+ {0x0Fu, 0x40u},\r
+ {0x10u, 0x20u},\r
+ {0x11u, 0x01u},\r
+ {0x12u, 0x06u},\r
+ {0x17u, 0x20u},\r
+ {0x19u, 0x10u},\r
+ {0x1Du, 0x01u},\r
{0x1Eu, 0x04u},\r
- {0x22u, 0x40u},\r
- {0x25u, 0x02u},\r
- {0x26u, 0x80u},\r
- {0x27u, 0x23u},\r
- {0x28u, 0x04u},\r
- {0x29u, 0x08u},\r
- {0x2Au, 0x02u},\r
- {0x2Cu, 0x80u},\r
- {0x30u, 0x10u},\r
- {0x32u, 0x80u},\r
- {0x33u, 0x02u},\r
- {0x34u, 0x04u},\r
- {0x36u, 0x10u},\r
- {0x39u, 0x15u},\r
- {0x3Bu, 0x80u},\r
- {0x3Cu, 0x80u},\r
- {0x3Fu, 0x08u},\r
- {0x5Au, 0x40u},\r
- {0x5Eu, 0x80u},\r
- {0x61u, 0xC0u},\r
- {0x64u, 0x01u},\r
- {0x67u, 0x01u},\r
- {0x6Cu, 0x80u},\r
- {0x6Du, 0x54u},\r
- {0x6Fu, 0x02u},\r
- {0x74u, 0x66u},\r
- {0x85u, 0x04u},\r
- {0x88u, 0x20u},\r
- {0x89u, 0x03u},\r
- {0x8Cu, 0x80u},\r
- {0x8Du, 0x10u},\r
- {0x8Fu, 0x10u},\r
- {0x91u, 0xA0u},\r
- {0x92u, 0x41u},\r
- {0x93u, 0x84u},\r
- {0x94u, 0x22u},\r
- {0x96u, 0x80u},\r
- {0x99u, 0x04u},\r
- {0x9Au, 0x20u},\r
- {0x9Cu, 0x81u},\r
- {0x9Du, 0x40u},\r
- {0x9Eu, 0x80u},\r
- {0x9Fu, 0x84u},\r
- {0xA1u, 0x10u},\r
- {0xA2u, 0x10u},\r
- {0xA4u, 0x08u},\r
- {0xA9u, 0x02u},\r
- {0xAFu, 0x04u},\r
- {0xB1u, 0x80u},\r
- {0xB5u, 0x08u},\r
- {0xC0u, 0x6Eu},\r
- {0xC2u, 0xEDu},\r
- {0xC4u, 0xFFu},\r
- {0xCAu, 0x87u},\r
- {0xCCu, 0x6Du},\r
- {0xCEu, 0x5Fu},\r
- {0xD6u, 0x18u},\r
+ {0x21u, 0xA0u},\r
+ {0x23u, 0x50u},\r
+ {0x24u, 0x44u},\r
+ {0x25u, 0x08u},\r
+ {0x26u, 0x20u},\r
+ {0x27u, 0x11u},\r
+ {0x28u, 0x02u},\r
+ {0x29u, 0x12u},\r
+ {0x2Cu, 0x01u},\r
+ {0x2Eu, 0x21u},\r
+ {0x31u, 0x20u},\r
+ {0x32u, 0x84u},\r
+ {0x36u, 0x08u},\r
+ {0x37u, 0x11u},\r
+ {0x3Bu, 0x54u},\r
+ {0x3Cu, 0x44u},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x02u},\r
+ {0x58u, 0x40u},\r
+ {0x5Cu, 0x50u},\r
+ {0x5Du, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x63u, 0x02u},\r
+ {0x67u, 0x02u},\r
+ {0x80u, 0x08u},\r
+ {0x81u, 0x80u},\r
+ {0x84u, 0x40u},\r
+ {0x86u, 0x08u},\r
+ {0x8Au, 0x05u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Eu, 0x20u},\r
+ {0x92u, 0x18u},\r
+ {0x93u, 0x20u},\r
+ {0x95u, 0x82u},\r
+ {0x96u, 0x40u},\r
+ {0x98u, 0x05u},\r
+ {0x9Au, 0x04u},\r
+ {0x9Bu, 0x20u},\r
+ {0x9Du, 0x01u},\r
+ {0x9Eu, 0x28u},\r
+ {0x9Fu, 0x0Cu},\r
+ {0xA2u, 0x80u},\r
+ {0xA3u, 0x08u},\r
+ {0xA4u, 0x28u},\r
+ {0xA5u, 0x08u},\r
+ {0xA7u, 0x82u},\r
+ {0xABu, 0x10u},\r
+ {0xACu, 0x4Du},\r
+ {0xAFu, 0x40u},\r
+ {0xB5u, 0x60u},\r
+ {0xB7u, 0x04u},\r
+ {0xC0u, 0x0Eu},\r
+ {0xC2u, 0x1Eu},\r
+ {0xC4u, 0x4Fu},\r
+ {0xCAu, 0xBDu},\r
+ {0xCCu, 0xEEu},\r
+ {0xCEu, 0xFEu},\r
+ {0xD6u, 0xF8u},\r
{0xD8u, 0x18u},\r
- {0xE0u, 0xF0u},\r
- {0xE6u, 0x18u},\r
- {0xE8u, 0x40u},\r
- {0xEAu, 0x20u},\r
- {0xECu, 0x80u},\r
- {0xEEu, 0x01u},\r
- {0x01u, 0x10u},\r
- {0x02u, 0x07u},\r
- {0x05u, 0x08u},\r
- {0x07u, 0x06u},\r
- {0x09u, 0x10u},\r
- {0x0Du, 0x08u},\r
- {0x0Eu, 0x10u},\r
- {0x0Fu, 0x04u},\r
- {0x10u, 0x04u},\r
- {0x12u, 0x08u},\r
- {0x15u, 0x10u},\r
- {0x19u, 0x04u},\r
- {0x1Bu, 0x08u},\r
- {0x1Du, 0x10u},\r
- {0x1Eu, 0x20u},\r
- {0x21u, 0x08u},\r
- {0x22u, 0x08u},\r
- {0x23u, 0x04u},\r
- {0x28u, 0x09u},\r
- {0x29u, 0x08u},\r
- {0x2Au, 0x02u},\r
- {0x2Bu, 0x04u},\r
- {0x2Cu, 0x0Au},\r
- {0x2Eu, 0x05u},\r
- {0x2Fu, 0x01u},\r
- {0x30u, 0x20u},\r
- {0x31u, 0x02u},\r
- {0x33u, 0x10u},\r
- {0x34u, 0x10u},\r
- {0x35u, 0x0Cu},\r
- {0x36u, 0x0Fu},\r
- {0x37u, 0x01u},\r
- {0x39u, 0x08u},\r
- {0x3Bu, 0x20u},\r
- {0x3Fu, 0x04u},\r
+ {0xE2u, 0x10u},\r
+ {0xE4u, 0xC0u},\r
+ {0xE6u, 0x38u},\r
+ {0xE8u, 0x50u},\r
+ {0x01u, 0x05u},\r
+ {0x02u, 0xFFu},\r
+ {0x03u, 0x0Au},\r
+ {0x05u, 0x03u},\r
+ {0x07u, 0x0Cu},\r
+ {0x08u, 0x50u},\r
+ {0x0Au, 0xA0u},\r
+ {0x0Bu, 0xFFu},\r
+ {0x0Cu, 0xFFu},\r
+ {0x0Du, 0x0Fu},\r
+ {0x0Fu, 0xF0u},\r
+ {0x10u, 0x60u},\r
+ {0x11u, 0x90u},\r
+ {0x12u, 0x90u},\r
+ {0x13u, 0x60u},\r
+ {0x15u, 0x50u},\r
+ {0x16u, 0xFFu},\r
+ {0x17u, 0xA0u},\r
+ {0x18u, 0x30u},\r
+ {0x19u, 0x30u},\r
+ {0x1Au, 0xC0u},\r
+ {0x1Bu, 0xC0u},\r
+ {0x20u, 0x0Fu},\r
+ {0x22u, 0xF0u},\r
+ {0x23u, 0xFFu},\r
+ {0x24u, 0x03u},\r
+ {0x25u, 0x09u},\r
+ {0x26u, 0x0Cu},\r
+ {0x27u, 0x06u},\r
+ {0x28u, 0x06u},\r
+ {0x2Au, 0x09u},\r
+ {0x2Bu, 0xFFu},\r
+ {0x2Cu, 0x05u},\r
+ {0x2Eu, 0x0Au},\r
+ {0x34u, 0xFFu},\r
+ {0x37u, 0xFFu},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x40u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x96u},\r
- {0x83u, 0x69u},\r
- {0x84u, 0xAAu},\r
- {0x86u, 0x55u},\r
- {0x87u, 0xFFu},\r
- {0x89u, 0xFFu},\r
- {0x8Au, 0x80u},\r
- {0x8Du, 0x55u},\r
- {0x8Fu, 0xAAu},\r
- {0x91u, 0x33u},\r
- {0x93u, 0xCCu},\r
- {0x95u, 0x0Fu},\r
- {0x96u, 0x70u},\r
- {0x97u, 0xF0u},\r
- {0x9Bu, 0xFFu},\r
- {0x9Du, 0xFFu},\r
- {0x9Eu, 0x07u},\r
- {0xA0u, 0x99u},\r
- {0xA2u, 0x22u},\r
- {0xA6u, 0x08u},\r
- {0xA8u, 0x44u},\r
- {0xAAu, 0x88u},\r
- {0xABu, 0xFFu},\r
- {0xB2u, 0xF0u},\r
- {0xB5u, 0xFFu},\r
- {0xB6u, 0x0Fu},\r
- {0xBBu, 0x20u},\r
+ {0x81u, 0x02u},\r
+ {0x83u, 0x05u},\r
+ {0x84u, 0x1Au},\r
+ {0x86u, 0x05u},\r
+ {0x89u, 0x02u},\r
+ {0x8Au, 0x08u},\r
+ {0x8Bu, 0x01u},\r
+ {0x8Eu, 0x40u},\r
+ {0x91u, 0x02u},\r
+ {0x93u, 0x01u},\r
+ {0x96u, 0x20u},\r
+ {0x99u, 0x01u},\r
+ {0x9Au, 0x07u},\r
+ {0x9Bu, 0x02u},\r
+ {0x9Eu, 0x10u},\r
+ {0xA1u, 0x02u},\r
+ {0xA3u, 0x09u},\r
+ {0xA4u, 0x19u},\r
+ {0xA6u, 0x02u},\r
+ {0xA8u, 0x14u},\r
+ {0xAAu, 0x08u},\r
+ {0xB0u, 0x10u},\r
+ {0xB2u, 0x20u},\r
+ {0xB3u, 0x03u},\r
+ {0xB4u, 0x0Fu},\r
+ {0xB5u, 0x08u},\r
+ {0xB6u, 0x40u},\r
+ {0xB7u, 0x04u},\r
+ {0xBBu, 0x08u},\r
+ {0xBEu, 0x01u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
{0xDCu, 0x11u},\r
{0xDFu, 0x01u},\r
- {0x03u, 0x82u},\r
- {0x05u, 0x20u},\r
+ {0x01u, 0x40u},\r
+ {0x03u, 0x84u},\r
+ {0x05u, 0x10u},\r
{0x06u, 0x20u},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0x02u},\r
- {0x0Eu, 0x22u},\r
- {0x10u, 0x0Au},\r
- {0x12u, 0x80u},\r
- {0x14u, 0x80u},\r
- {0x15u, 0x04u},\r
- {0x16u, 0x08u},\r
- {0x19u, 0x11u},\r
- {0x1Au, 0x01u},\r
- {0x1Bu, 0x82u},\r
- {0x1Eu, 0x22u},\r
- {0x1Fu, 0x40u},\r
- {0x20u, 0x60u},\r
- {0x21u, 0x50u},\r
- {0x22u, 0x31u},\r
- {0x23u, 0x04u},\r
+ {0x07u, 0x01u},\r
+ {0x08u, 0x10u},\r
+ {0x0Au, 0x40u},\r
+ {0x0Bu, 0x20u},\r
+ {0x0Cu, 0x40u},\r
+ {0x0Du, 0x08u},\r
+ {0x0Eu, 0x08u},\r
+ {0x12u, 0x45u},\r
+ {0x13u, 0x04u},\r
+ {0x17u, 0x18u},\r
+ {0x1Au, 0x08u},\r
+ {0x1Eu, 0x18u},\r
+ {0x1Fu, 0x61u},\r
+ {0x22u, 0x80u},\r
{0x25u, 0x10u},\r
- {0x27u, 0x08u},\r
- {0x29u, 0x51u},\r
- {0x2Cu, 0x08u},\r
- {0x32u, 0x50u},\r
- {0x33u, 0x04u},\r
- {0x34u, 0x01u},\r
- {0x36u, 0x20u},\r
- {0x37u, 0x88u},\r
- {0x38u, 0x66u},\r
- {0x3Eu, 0xA8u},\r
- {0x3Fu, 0x02u},\r
- {0x58u, 0x60u},\r
- {0x5Du, 0x8Au},\r
- {0x5Fu, 0x10u},\r
- {0x60u, 0x04u},\r
- {0x63u, 0x02u},\r
- {0x67u, 0x01u},\r
- {0x80u, 0x02u},\r
- {0x81u, 0x01u},\r
- {0x82u, 0x28u},\r
- {0x83u, 0x01u},\r
- {0x84u, 0x30u},\r
- {0x85u, 0x20u},\r
- {0x88u, 0x40u},\r
- {0x89u, 0x04u},\r
- {0x8Bu, 0x10u},\r
- {0x8Du, 0x04u},\r
- {0x8Eu, 0xC0u},\r
- {0xC0u, 0x69u},\r
- {0xC2u, 0xA9u},\r
- {0xC4u, 0x7Bu},\r
- {0xCAu, 0x2Du},\r
- {0xCCu, 0xFEu},\r
- {0xCEu, 0xFFu},\r
- {0xD6u, 0xFCu},\r
- {0xD8u, 0x1Cu},\r
- {0xE0u, 0x70u},\r
- {0xE4u, 0x80u},\r
- {0xE6u, 0x08u},\r
- {0x85u, 0x0Bu},\r
- {0x86u, 0x82u},\r
- {0x87u, 0x24u},\r
- {0x88u, 0x04u},\r
- {0x89u, 0x15u},\r
- {0x8Au, 0x23u},\r
- {0x8Bu, 0x0Au},\r
- {0x8Cu, 0x70u},\r
- {0x91u, 0x30u},\r
- {0x95u, 0x04u},\r
- {0x96u, 0x7Cu},\r
- {0x97u, 0x03u},\r
- {0x9Au, 0x01u},\r
- {0x9Cu, 0x11u},\r
- {0x9Eu, 0x02u},\r
- {0xA1u, 0x09u},\r
- {0xA3u, 0x16u},\r
- {0xA4u, 0x48u},\r
- {0xA6u, 0x03u},\r
- {0xB2u, 0x0Fu},\r
- {0xB3u, 0x07u},\r
- {0xB4u, 0x80u},\r
- {0xB6u, 0x70u},\r
- {0xB7u, 0x38u},\r
- {0xB9u, 0x80u},\r
- {0xBBu, 0x08u},\r
- {0xBEu, 0x40u},\r
- {0xD6u, 0x02u},\r
- {0xD7u, 0x28u},\r
+ {0x27u, 0x21u},\r
+ {0x2Au, 0x04u},\r
+ {0x2Bu, 0xA4u},\r
+ {0x2Fu, 0x40u},\r
+ {0x30u, 0x38u},\r
+ {0x33u, 0x02u},\r
+ {0x37u, 0x21u},\r
+ {0x39u, 0x82u},\r
+ {0x3Au, 0x49u},\r
+ {0x3Bu, 0x24u},\r
+ {0x3Du, 0x20u},\r
+ {0x3Fu, 0x01u},\r
+ {0x44u, 0x02u},\r
+ {0x45u, 0x40u},\r
+ {0x5Au, 0x80u},\r
+ {0x5Cu, 0x0Au},\r
+ {0x5Du, 0x20u},\r
+ {0x5Fu, 0x40u},\r
+ {0x63u, 0x01u},\r
+ {0x67u, 0x02u},\r
+ {0x82u, 0x40u},\r
+ {0x87u, 0x10u},\r
+ {0x89u, 0x40u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Du, 0x11u},\r
+ {0xC0u, 0xEBu},\r
+ {0xC2u, 0xEEu},\r
+ {0xC4u, 0x6Fu},\r
+ {0xCAu, 0x87u},\r
+ {0xCCu, 0xA7u},\r
+ {0xCEu, 0xAFu},\r
+ {0xD6u, 0xF8u},\r
+ {0xD8u, 0x18u},\r
+ {0xE0u, 0x60u},\r
+ {0xE2u, 0x01u},\r
+ {0xE4u, 0x20u},\r
+ {0xE6u, 0x41u},\r
+ {0x00u, 0x03u},\r
+ {0x02u, 0x0Cu},\r
+ {0x04u, 0x20u},\r
+ {0x06u, 0x4Fu},\r
+ {0x0Cu, 0x40u},\r
+ {0x0Eu, 0x1Fu},\r
+ {0x10u, 0x06u},\r
+ {0x12u, 0x09u},\r
+ {0x16u, 0x70u},\r
+ {0x1Eu, 0x80u},\r
+ {0x24u, 0x0Fu},\r
+ {0x28u, 0x10u},\r
+ {0x2Au, 0x2Fu},\r
+ {0x2Cu, 0x05u},\r
+ {0x2Eu, 0x0Au},\r
+ {0x30u, 0x80u},\r
+ {0x32u, 0x7Fu},\r
+ {0x40u, 0x26u},\r
+ {0x41u, 0x04u},\r
+ {0x42u, 0x30u},\r
+ {0x44u, 0x05u},\r
+ {0x45u, 0xCEu},\r
+ {0x46u, 0xF0u},\r
+ {0x47u, 0xDBu},\r
+ {0x48u, 0x3Bu},\r
+ {0x49u, 0xFFu},\r
+ {0x4Au, 0xFFu},\r
+ {0x4Bu, 0xFFu},\r
+ {0x4Cu, 0x22u},\r
+ {0x4Eu, 0xF0u},\r
+ {0x4Fu, 0x08u},\r
+ {0x50u, 0x04u},\r
+ {0x58u, 0x04u},\r
+ {0x5Au, 0x04u},\r
+ {0x5Cu, 0x01u},\r
+ {0x5Fu, 0x01u},\r
+ {0x62u, 0xC0u},\r
+ {0x64u, 0x40u},\r
+ {0x65u, 0x01u},\r
+ {0x66u, 0x10u},\r
+ {0x67u, 0x11u},\r
+ {0x68u, 0xC0u},\r
+ {0x69u, 0x01u},\r
+ {0x6Bu, 0x11u},\r
+ {0x6Cu, 0x40u},\r
+ {0x6Du, 0x01u},\r
+ {0x6Eu, 0x40u},\r
+ {0x6Fu, 0x01u},\r
+ {0x80u, 0x40u},\r
+ {0x84u, 0x88u},\r
+ {0x86u, 0x21u},\r
+ {0x87u, 0xFFu},\r
+ {0x88u, 0x01u},\r
+ {0x89u, 0x80u},\r
+ {0x8Cu, 0x01u},\r
+ {0x8Du, 0x1Fu},\r
+ {0x8Fu, 0x20u},\r
+ {0x90u, 0x87u},\r
+ {0x91u, 0xC0u},\r
+ {0x92u, 0x18u},\r
+ {0x93u, 0x01u},\r
+ {0x94u, 0x01u},\r
+ {0x97u, 0x9Fu},\r
+ {0x98u, 0xA2u},\r
+ {0x99u, 0x7Fu},\r
+ {0x9Au, 0x08u},\r
+ {0x9Bu, 0x80u},\r
+ {0x9Cu, 0x04u},\r
+ {0x9Du, 0xC0u},\r
+ {0x9Fu, 0x02u},\r
+ {0xA0u, 0x01u},\r
+ {0xA3u, 0x60u},\r
+ {0xA4u, 0x10u},\r
+ {0xA5u, 0xC0u},\r
+ {0xA7u, 0x04u},\r
+ {0xA8u, 0x40u},\r
+ {0xA9u, 0xC0u},\r
+ {0xABu, 0x08u},\r
+ {0xACu, 0x01u},\r
+ {0xADu, 0x90u},\r
+ {0xAFu, 0x40u},\r
+ {0xB0u, 0x3Fu},\r
+ {0xB2u, 0x80u},\r
+ {0xB3u, 0xFFu},\r
+ {0xB6u, 0x40u},\r
+ {0xB8u, 0x82u},\r
+ {0xBEu, 0x05u},\r
+ {0xBFu, 0x04u},\r
+ {0xD4u, 0x09u},\r
+ {0xD6u, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x48u},\r
- {0x03u, 0x40u},\r
- {0x05u, 0x20u},\r
- {0x06u, 0x10u},\r
+ {0x00u, 0x02u},\r
+ {0x01u, 0x80u},\r
+ {0x03u, 0x10u},\r
+ {0x04u, 0x24u},\r
+ {0x05u, 0x01u},\r
{0x07u, 0x01u},\r
- {0x0Au, 0x41u},\r
- {0x0Bu, 0x14u},\r
- {0x0Eu, 0x19u},\r
- {0x10u, 0x28u},\r
- {0x13u, 0x02u},\r
+ {0x08u, 0x80u},\r
+ {0x0Au, 0xA0u},\r
+ {0x0Du, 0x0Au},\r
+ {0x0Eu, 0x09u},\r
+ {0x11u, 0x04u},\r
+ {0x12u, 0x02u},\r
+ {0x13u, 0x10u},\r
{0x15u, 0x08u},\r
- {0x18u, 0x04u},\r
+ {0x17u, 0x62u},\r
+ {0x18u, 0x80u},\r
{0x19u, 0x08u},\r
- {0x1Au, 0x42u},\r
- {0x1Eu, 0x18u},\r
- {0x1Fu, 0x80u},\r
- {0x21u, 0x80u},\r
- {0x26u, 0x08u},\r
- {0x27u, 0x11u},\r
- {0x2Au, 0x82u},\r
- {0x2Bu, 0x10u},\r
- {0x2Eu, 0x01u},\r
- {0x30u, 0x06u},\r
- {0x32u, 0xA0u},\r
+ {0x1Au, 0x20u},\r
+ {0x1Du, 0x05u},\r
+ {0x1Eu, 0x01u},\r
+ {0x27u, 0x20u},\r
+ {0x2Cu, 0x08u},\r
+ {0x2Eu, 0x41u},\r
+ {0x2Fu, 0x20u},\r
+ {0x35u, 0x10u},\r
{0x36u, 0x08u},\r
- {0x37u, 0x01u},\r
- {0x3Fu, 0x14u},\r
- {0x40u, 0x06u},\r
- {0x41u, 0x04u},\r
- {0x46u, 0x08u},\r
- {0x47u, 0x10u},\r
- {0x48u, 0x04u},\r
- {0x49u, 0x64u},\r
- {0x4Bu, 0x02u},\r
- {0x51u, 0x01u},\r
- {0x52u, 0x11u},\r
- {0x53u, 0x48u},\r
- {0x66u, 0x08u},\r
- {0x6Cu, 0x38u},\r
- {0x6Du, 0x44u},\r
- {0x6Eu, 0x20u},\r
- {0x6Fu, 0x60u},\r
- {0x77u, 0x02u},\r
- {0x82u, 0x80u},\r
- {0x83u, 0x80u},\r
- {0x89u, 0x80u},\r
+ {0x37u, 0x42u},\r
+ {0x3Cu, 0xA4u},\r
+ {0x40u, 0x04u},\r
+ {0x41u, 0x02u},\r
+ {0x43u, 0x08u},\r
+ {0x48u, 0x82u},\r
+ {0x49u, 0x12u},\r
+ {0x4Bu, 0x04u},\r
+ {0x51u, 0x04u},\r
+ {0x52u, 0x18u},\r
+ {0x53u, 0x01u},\r
+ {0x5Du, 0x10u},\r
+ {0x5Eu, 0x82u},\r
+ {0x5Fu, 0x04u},\r
+ {0x64u, 0x02u},\r
+ {0x67u, 0x40u},\r
+ {0x80u, 0x40u},\r
+ {0x84u, 0x02u},\r
+ {0x85u, 0x48u},\r
+ {0x89u, 0x12u},\r
+ {0x8Bu, 0x40u},\r
{0x8Cu, 0x02u},\r
- {0x8Du, 0x10u},\r
- {0x8Eu, 0x40u},\r
- {0x8Fu, 0x01u},\r
- {0x91u, 0x08u},\r
- {0x92u, 0x01u},\r
- {0x93u, 0x14u},\r
- {0x94u, 0x20u},\r
- {0x95u, 0x46u},\r
- {0x96u, 0x02u},\r
- {0x97u, 0x80u},\r
- {0x98u, 0x04u},\r
- {0x99u, 0x40u},\r
- {0x9Au, 0x02u},\r
- {0x9Du, 0x14u},\r
- {0x9Eu, 0x11u},\r
- {0x9Fu, 0x42u},\r
- {0xA0u, 0x06u},\r
- {0xA2u, 0xA0u},\r
- {0xA3u, 0x10u},\r
- {0xA4u, 0x28u},\r
- {0xA6u, 0x10u},\r
- {0xA7u, 0x28u},\r
- {0xC0u, 0xEDu},\r
- {0xC2u, 0xEFu},\r
- {0xC4u, 0x2Eu},\r
- {0xCAu, 0x8Bu},\r
- {0xCCu, 0xCFu},\r
- {0xCEu, 0x60u},\r
- {0xD0u, 0x0Eu},\r
- {0xD2u, 0x0Cu},\r
- {0xD8u, 0x40u},\r
- {0xE0u, 0x10u},\r
- {0xE2u, 0x01u},\r
- {0xE6u, 0x40u},\r
- {0x00u, 0xC0u},\r
- {0x01u, 0x01u},\r
- {0x02u, 0x02u},\r
- {0x05u, 0x08u},\r
- {0x06u, 0x9Fu},\r
- {0x07u, 0x21u},\r
- {0x08u, 0xC0u},\r
- {0x09u, 0x22u},\r
- {0x0Au, 0x04u},\r
- {0x0Bu, 0x08u},\r
- {0x0Cu, 0x1Fu},\r
- {0x0Du, 0x04u},\r
- {0x0Eu, 0x20u},\r
- {0x11u, 0x01u},\r
- {0x12u, 0x60u},\r
- {0x14u, 0xC0u},\r
- {0x15u, 0x40u},\r
- {0x16u, 0x08u},\r
- {0x19u, 0x40u},\r
- {0x1Au, 0xFFu},\r
- {0x1Cu, 0x80u},\r
- {0x1Du, 0x01u},\r
- {0x20u, 0xC0u},\r
- {0x21u, 0x07u},\r
- {0x22u, 0x01u},\r
- {0x23u, 0x18u},\r
- {0x24u, 0x7Fu},\r
- {0x25u, 0x01u},\r
- {0x26u, 0x80u},\r
- {0x29u, 0x10u},\r
- {0x2Cu, 0x90u},\r
- {0x2Du, 0x01u},\r
- {0x2Eu, 0x40u},\r
- {0x33u, 0x3Fu},\r
- {0x34u, 0xFFu},\r
- {0x37u, 0x40u},\r
- {0x39u, 0x88u},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x04u},\r
- {0x56u, 0x08u},\r
+ {0x8Du, 0x04u},\r
+ {0x90u, 0x24u},\r
+ {0x91u, 0x04u},\r
+ {0x92u, 0xC0u},\r
+ {0x93u, 0x10u},\r
+ {0x95u, 0x08u},\r
+ {0x97u, 0x02u},\r
+ {0x98u, 0x80u},\r
+ {0x99u, 0x90u},\r
+ {0x9Bu, 0x53u},\r
+ {0x9Du, 0x40u},\r
+ {0x9Eu, 0x10u},\r
+ {0xA0u, 0x59u},\r
+ {0xA1u, 0x0Au},\r
+ {0xA2u, 0x47u},\r
+ {0xA3u, 0x28u},\r
+ {0xA4u, 0x80u},\r
+ {0xA8u, 0x80u},\r
+ {0xABu, 0x01u},\r
+ {0xAEu, 0x10u},\r
+ {0xB3u, 0x10u},\r
+ {0xB5u, 0x10u},\r
+ {0xC0u, 0xFDu},\r
+ {0xC2u, 0xFDu},\r
+ {0xC4u, 0xF7u},\r
+ {0xCAu, 0xF0u},\r
+ {0xCCu, 0xF0u},\r
+ {0xCEu, 0x70u},\r
+ {0xD0u, 0x07u},\r
+ {0xD2u, 0x0Cu},\r
+ {0xD6u, 0xF0u},\r
+ {0xD8u, 0x90u},\r
+ {0xE0u, 0x01u},\r
+ {0xE2u, 0x20u},\r
+ {0xEAu, 0x01u},\r
+ {0xECu, 0x08u},\r
+ {0xEEu, 0x01u},\r
+ {0x00u, 0x6Cu},\r
+ {0x01u, 0xD6u},\r
+ {0x04u, 0x40u},\r
+ {0x05u, 0x29u},\r
+ {0x06u, 0x2Cu},\r
+ {0x07u, 0x46u},\r
+ {0x08u, 0x64u},\r
+ {0x09u, 0x02u},\r
+ {0x0Au, 0x08u},\r
+ {0x0Cu, 0x2Cu},\r
+ {0x0Du, 0xD6u},\r
+ {0x0Eu, 0x40u},\r
+ {0x10u, 0x71u},\r
+ {0x12u, 0x82u},\r
+ {0x14u, 0xA4u},\r
+ {0x15u, 0x21u},\r
+ {0x16u, 0x40u},\r
+ {0x17u, 0x8Eu},\r
+ {0x18u, 0xC0u},\r
+ {0x19u, 0x20u},\r
+ {0x1Au, 0x2Fu},\r
+ {0x1Bu, 0xD0u},\r
+ {0x1Cu, 0x08u},\r
+ {0x1Du, 0xD6u},\r
+ {0x1Eu, 0x10u},\r
+ {0x20u, 0x6Cu},\r
+ {0x21u, 0x04u},\r
+ {0x24u, 0x91u},\r
+ {0x25u, 0xD2u},\r
+ {0x26u, 0x4Eu},\r
+ {0x27u, 0x04u},\r
+ {0x29u, 0xD0u},\r
+ {0x2Bu, 0x06u},\r
+ {0x2Du, 0x17u},\r
+ {0x2Fu, 0x28u},\r
+ {0x30u, 0x0Fu},\r
+ {0x32u, 0xC0u},\r
+ {0x33u, 0xF0u},\r
+ {0x34u, 0x31u},\r
+ {0x35u, 0x0Fu},\r
+ {0x37u, 0x08u},\r
+ {0x39u, 0x20u},\r
+ {0x3Au, 0x38u},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Fu, 0x40u},\r
+ {0x56u, 0x02u},\r
+ {0x57u, 0x24u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x65u},\r
- {0x81u, 0x04u},\r
- {0x83u, 0x12u},\r
- {0x84u, 0x25u},\r
- {0x86u, 0x40u},\r
- {0x88u, 0x22u},\r
- {0x8Au, 0x01u},\r
- {0x8Cu, 0x60u},\r
- {0x8Du, 0x04u},\r
- {0x8Eu, 0x05u},\r
- {0x8Fu, 0x0Au},\r
- {0x92u, 0x04u},\r
- {0x94u, 0x03u},\r
- {0x95u, 0x02u},\r
- {0x96u, 0x78u},\r
- {0x97u, 0x04u},\r
- {0x98u, 0x0Au},\r
- {0x99u, 0x04u},\r
- {0x9Au, 0x71u},\r
- {0x9Bu, 0x02u},\r
- {0x9Cu, 0x09u},\r
- {0x9Du, 0x04u},\r
- {0x9Eu, 0x12u},\r
- {0x9Fu, 0x03u},\r
- {0xA0u, 0x65u},\r
- {0xA8u, 0x05u},\r
- {0xAAu, 0x60u},\r
- {0xACu, 0x40u},\r
- {0xB0u, 0x03u},\r
- {0xB1u, 0x10u},\r
- {0xB2u, 0x04u},\r
- {0xB3u, 0x06u},\r
- {0xB4u, 0x03u},\r
- {0xB5u, 0x01u},\r
- {0xB6u, 0x78u},\r
- {0xB7u, 0x08u},\r
- {0xBAu, 0x22u},\r
- {0xBBu, 0x08u},\r
- {0xBEu, 0x04u},\r
- {0xD4u, 0x40u},\r
- {0xD6u, 0x04u},\r
+ {0x80u, 0x06u},\r
+ {0x82u, 0x09u},\r
+ {0x87u, 0x01u},\r
+ {0x88u, 0x60u},\r
+ {0x89u, 0x95u},\r
+ {0x8Au, 0x90u},\r
+ {0x8Bu, 0x28u},\r
+ {0x8Cu, 0x30u},\r
+ {0x8Du, 0x02u},\r
+ {0x8Eu, 0xC0u},\r
+ {0x90u, 0x05u},\r
+ {0x92u, 0x0Au},\r
+ {0x97u, 0x08u},\r
+ {0x98u, 0x03u},\r
+ {0x99u, 0xA4u},\r
+ {0x9Au, 0x0Cu},\r
+ {0x9Bu, 0x58u},\r
+ {0x9Cu, 0x0Fu},\r
+ {0x9Eu, 0xF0u},\r
+ {0x9Fu, 0x70u},\r
+ {0xA0u, 0x50u},\r
+ {0xA2u, 0xA0u},\r
+ {0xA7u, 0x80u},\r
+ {0xADu, 0x41u},\r
+ {0xAFu, 0x88u},\r
+ {0xB0u, 0xFFu},\r
+ {0xB3u, 0x0Fu},\r
+ {0xB7u, 0xF0u},\r
+ {0xB9u, 0x08u},\r
+ {0xBEu, 0x01u},\r
+ {0xD4u, 0x01u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
{0xDCu, 0x10u},\r
+ {0xDDu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x64u},\r
- {0x03u, 0x40u},\r
- {0x04u, 0x20u},\r
- {0x05u, 0x40u},\r
- {0x06u, 0x10u},\r
- {0x07u, 0x40u},\r
- {0x08u, 0x02u},\r
- {0x0Au, 0x01u},\r
- {0x0Bu, 0x94u},\r
- {0x0Eu, 0xA0u},\r
- {0x0Fu, 0x06u},\r
- {0x10u, 0x08u},\r
- {0x12u, 0x01u},\r
- {0x13u, 0x02u},\r
- {0x15u, 0x48u},\r
- {0x17u, 0x03u},\r
- {0x18u, 0x10u},\r
- {0x19u, 0x61u},\r
- {0x1Au, 0x01u},\r
- {0x1Bu, 0x81u},\r
+ {0x02u, 0x89u},\r
+ {0x04u, 0x28u},\r
+ {0x07u, 0x41u},\r
+ {0x09u, 0x01u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Bu, 0x01u},\r
+ {0x0Cu, 0x80u},\r
+ {0x0Du, 0x0Au},\r
+ {0x0Eu, 0x08u},\r
+ {0x11u, 0x01u},\r
+ {0x17u, 0x0Au},\r
+ {0x19u, 0x02u},\r
+ {0x1Cu, 0xE0u},\r
+ {0x1Du, 0x1Au},\r
{0x1Eu, 0x08u},\r
- {0x20u, 0x60u},\r
- {0x21u, 0x08u},\r
- {0x22u, 0x50u},\r
- {0x25u, 0x40u},\r
- {0x26u, 0x40u},\r
- {0x27u, 0x20u},\r
- {0x2Du, 0x40u},\r
- {0x2Fu, 0xA8u},\r
- {0x31u, 0x08u},\r
- {0x32u, 0x50u},\r
+ {0x1Fu, 0x02u},\r
+ {0x22u, 0x80u},\r
+ {0x23u, 0x10u},\r
+ {0x24u, 0x04u},\r
+ {0x26u, 0x50u},\r
+ {0x27u, 0x28u},\r
+ {0x28u, 0x10u},\r
+ {0x29u, 0x80u},\r
+ {0x2Cu, 0x88u},\r
+ {0x2Fu, 0x22u},\r
+ {0x32u, 0x84u},\r
+ {0x33u, 0x10u},\r
{0x36u, 0x04u},\r
- {0x37u, 0x62u},\r
+ {0x37u, 0x60u},\r
+ {0x39u, 0x84u},\r
+ {0x3Bu, 0x10u},\r
+ {0x3Cu, 0x24u},\r
+ {0x3Eu, 0x42u},\r
+ {0x59u, 0x40u},\r
+ {0x64u, 0x08u},\r
+ {0x6Cu, 0x5Cu},\r
+ {0x6Eu, 0x40u},\r
+ {0x6Fu, 0x61u},\r
+ {0x76u, 0x02u},\r
+ {0x77u, 0x02u},\r
+ {0x86u, 0x88u},\r
+ {0x88u, 0x40u},\r
+ {0x91u, 0x85u},\r
+ {0x92u, 0x8Cu},\r
+ {0x94u, 0xECu},\r
+ {0x95u, 0x08u},\r
+ {0x96u, 0x40u},\r
+ {0x97u, 0x12u},\r
+ {0x98u, 0x18u},\r
+ {0x99u, 0x80u},\r
+ {0x9Au, 0x01u},\r
+ {0x9Bu, 0x10u},\r
+ {0x9Du, 0x02u},\r
+ {0x9Eu, 0x12u},\r
+ {0x9Fu, 0x40u},\r
+ {0xA0u, 0x01u},\r
+ {0xA1u, 0x01u},\r
+ {0xA2u, 0x03u},\r
+ {0xA3u, 0x08u},\r
+ {0xA4u, 0x08u},\r
+ {0xA6u, 0x04u},\r
+ {0xA7u, 0x20u},\r
+ {0xB1u, 0x80u},\r
+ {0xC0u, 0xFBu},\r
+ {0xC2u, 0xFBu},\r
+ {0xC4u, 0x38u},\r
+ {0xCAu, 0xFAu},\r
+ {0xCCu, 0x7Eu},\r
+ {0xCEu, 0xFEu},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x20u},\r
+ {0xE2u, 0x8Au},\r
+ {0xE4u, 0x08u},\r
+ {0xEAu, 0x02u},\r
+ {0xEEu, 0x08u},\r
+ {0x02u, 0x08u},\r
+ {0x03u, 0x02u},\r
+ {0x06u, 0x10u},\r
+ {0x08u, 0x01u},\r
+ {0x09u, 0x28u},\r
+ {0x0Au, 0x02u},\r
+ {0x0Bu, 0x14u},\r
+ {0x0Du, 0x01u},\r
+ {0x0Eu, 0x20u},\r
+ {0x0Fu, 0x02u},\r
+ {0x10u, 0x14u},\r
+ {0x12u, 0x28u},\r
+ {0x14u, 0x02u},\r
+ {0x16u, 0x01u},\r
+ {0x17u, 0x20u},\r
+ {0x1Bu, 0x1Cu},\r
+ {0x1Cu, 0x02u},\r
+ {0x1Eu, 0x01u},\r
+ {0x1Fu, 0x01u},\r
+ {0x20u, 0x02u},\r
+ {0x21u, 0x10u},\r
+ {0x22u, 0x41u},\r
+ {0x23u, 0x20u},\r
+ {0x24u, 0x02u},\r
+ {0x26u, 0x01u},\r
+ {0x2Au, 0x04u},\r
+ {0x2Bu, 0x40u},\r
+ {0x2Du, 0x24u},\r
+ {0x2Fu, 0x08u},\r
+ {0x30u, 0x0Cu},\r
+ {0x32u, 0x03u},\r
+ {0x33u, 0x3Cu},\r
+ {0x34u, 0x30u},\r
+ {0x35u, 0x40u},\r
+ {0x36u, 0x40u},\r
+ {0x37u, 0x03u},\r
+ {0x3Au, 0x08u},\r
+ {0x3Eu, 0x11u},\r
+ {0x3Fu, 0x40u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Cu, 0x11u},\r
+ {0x5Fu, 0x01u},\r
+ {0x81u, 0x0Au},\r
+ {0x83u, 0x05u},\r
+ {0x86u, 0x07u},\r
+ {0x8Cu, 0x09u},\r
+ {0x8Eu, 0x02u},\r
+ {0x8Fu, 0x07u},\r
+ {0x90u, 0x10u},\r
+ {0x92u, 0x20u},\r
+ {0x95u, 0x10u},\r
+ {0x96u, 0x08u},\r
+ {0x97u, 0x20u},\r
+ {0x9Bu, 0x20u},\r
+ {0x9Du, 0x04u},\r
+ {0x9Fu, 0x08u},\r
+ {0xA0u, 0x04u},\r
+ {0xA2u, 0x08u},\r
+ {0xA4u, 0x0Au},\r
+ {0xA6u, 0x05u},\r
+ {0xA7u, 0x10u},\r
+ {0xAAu, 0x10u},\r
+ {0xABu, 0x08u},\r
+ {0xADu, 0x09u},\r
+ {0xAEu, 0x20u},\r
+ {0xAFu, 0x02u},\r
+ {0xB0u, 0x30u},\r
+ {0xB1u, 0x0Fu},\r
+ {0xB2u, 0x0Fu},\r
+ {0xB5u, 0x30u},\r
+ {0xBEu, 0x01u},\r
+ {0xBFu, 0x10u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x11u},\r
+ {0xDDu, 0x90u},\r
+ {0xDFu, 0x01u},\r
+ {0x01u, 0x88u},\r
+ {0x04u, 0x10u},\r
+ {0x07u, 0x62u},\r
+ {0x08u, 0x04u},\r
+ {0x0Au, 0x40u},\r
+ {0x0Eu, 0x52u},\r
+ {0x10u, 0x80u},\r
+ {0x11u, 0x48u},\r
+ {0x12u, 0x04u},\r
+ {0x15u, 0x20u},\r
+ {0x16u, 0x40u},\r
+ {0x17u, 0x08u},\r
+ {0x19u, 0x09u},\r
+ {0x1Cu, 0x10u},\r
+ {0x1Eu, 0x06u},\r
+ {0x1Fu, 0x02u},\r
+ {0x20u, 0x40u},\r
+ {0x21u, 0x01u},\r
+ {0x22u, 0x10u},\r
+ {0x24u, 0x20u},\r
+ {0x26u, 0x80u},\r
+ {0x27u, 0x28u},\r
+ {0x29u, 0x88u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Cu, 0x80u},\r
+ {0x2Du, 0x80u},\r
+ {0x2Eu, 0x10u},\r
+ {0x30u, 0xA0u},\r
+ {0x33u, 0x04u},\r
+ {0x34u, 0x08u},\r
+ {0x35u, 0x40u},\r
+ {0x37u, 0x20u},\r
{0x38u, 0x40u},\r
- {0x3Bu, 0x02u},\r
- {0x3Du, 0x80u},\r
- {0x3Fu, 0x16u},\r
- {0x5Cu, 0x80u},\r
- {0x60u, 0x12u},\r
- {0x61u, 0x10u},\r
- {0x63u, 0x80u},\r
- {0x67u, 0x02u},\r
- {0x88u, 0x80u},\r
- {0x8Fu, 0x40u},\r
- {0x91u, 0x08u},\r
- {0x93u, 0x14u},\r
- {0x95u, 0x42u},\r
- {0x96u, 0x02u},\r
- {0x98u, 0x04u},\r
- {0x9Au, 0x02u},\r
- {0x9Du, 0x45u},\r
- {0x9Fu, 0x41u},\r
- {0xA0u, 0x06u},\r
- {0xA2u, 0xA0u},\r
- {0xA3u, 0x10u},\r
- {0xA4u, 0x38u},\r
- {0xB0u, 0x02u},\r
- {0xB3u, 0x08u},\r
- {0xB6u, 0x11u},\r
- {0xB7u, 0x20u},\r
- {0xC0u, 0xFFu},\r
- {0xC2u, 0xFFu},\r
- {0xC4u, 0xBBu},\r
- {0xCAu, 0xF0u},\r
- {0xCCu, 0xFEu},\r
- {0xCEu, 0xF9u},\r
- {0xD6u, 0x10u},\r
- {0xD8u, 0x1Fu},\r
- {0xE6u, 0x40u},\r
- {0xEAu, 0x40u},\r
- {0xEEu, 0x48u},\r
- {0x9Cu, 0x80u},\r
- {0xA0u, 0x20u},\r
- {0xB0u, 0x04u},\r
- {0xB4u, 0x20u},\r
- {0xE2u, 0x20u},\r
+ {0x3Au, 0x01u},\r
+ {0x3Eu, 0x61u},\r
+ {0x5Au, 0x80u},\r
+ {0x62u, 0x40u},\r
+ {0x69u, 0x80u},\r
+ {0x6Au, 0x40u},\r
+ {0x82u, 0x10u},\r
+ {0x84u, 0x10u},\r
+ {0x85u, 0x40u},\r
+ {0x86u, 0x05u},\r
+ {0x89u, 0x40u},\r
+ {0x8Au, 0x90u},\r
+ {0x8Fu, 0x02u},\r
+ {0x91u, 0x60u},\r
+ {0x94u, 0x30u},\r
+ {0x95u, 0x92u},\r
+ {0x98u, 0x0Cu},\r
+ {0x9Au, 0x25u},\r
+ {0x9Bu, 0x42u},\r
+ {0x9Du, 0x09u},\r
+ {0x9Eu, 0x12u},\r
+ {0xA0u, 0xB0u},\r
+ {0xA1u, 0x04u},\r
+ {0xA3u, 0x08u},\r
+ {0xA5u, 0x40u},\r
+ {0xB0u, 0x80u},\r
+ {0xC0u, 0xF5u},\r
+ {0xC2u, 0xBCu},\r
+ {0xC4u, 0x7Fu},\r
+ {0xCAu, 0xBEu},\r
+ {0xCCu, 0x7Eu},\r
+ {0xCEu, 0xB9u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x08u},\r
+ {0xE2u, 0x80u},\r
+ {0xE4u, 0x24u},\r
+ {0xEAu, 0x02u},\r
{0xECu, 0x80u},\r
- {0xEEu, 0x18u},\r
- {0x80u, 0x20u},\r
- {0x88u, 0x80u},\r
- {0x9Cu, 0x80u},\r
- {0xA0u, 0x20u},\r
- {0xE0u, 0x20u},\r
- {0x13u, 0x20u},\r
+ {0xEEu, 0x08u},\r
+ {0x82u, 0x10u},\r
+ {0x96u, 0x10u},\r
+ {0xA9u, 0x40u},\r
+ {0xAAu, 0x01u},\r
+ {0xABu, 0x04u},\r
+ {0xADu, 0x10u},\r
+ {0xB1u, 0x80u},\r
+ {0xB6u, 0x42u},\r
+ {0xE8u, 0x40u},\r
+ {0xECu, 0x80u},\r
+ {0x13u, 0x10u},\r
{0x16u, 0x80u},\r
- {0x17u, 0x40u},\r
- {0x33u, 0x08u},\r
+ {0x17u, 0x20u},\r
+ {0x30u, 0x08u},\r
+ {0x35u, 0x01u},\r
{0x36u, 0x80u},\r
- {0x37u, 0x08u},\r
- {0x39u, 0x08u},\r
+ {0x39u, 0x04u},\r
{0x3Au, 0x80u},\r
- {0x3Cu, 0x04u},\r
- {0x3Fu, 0x10u},\r
- {0x41u, 0x20u},\r
- {0x56u, 0x20u},\r
- {0x5Au, 0x04u},\r
- {0x60u, 0x40u},\r
- {0x65u, 0x01u},\r
- {0x66u, 0x40u},\r
- {0x86u, 0x20u},\r
- {0x8Bu, 0x10u},\r
- {0x8Eu, 0x40u},\r
+ {0x3Cu, 0x08u},\r
+ {0x3Fu, 0x20u},\r
+ {0x42u, 0x08u},\r
+ {0x49u, 0x10u},\r
+ {0x4Bu, 0x10u},\r
+ {0x5Bu, 0x40u},\r
+ {0x5Eu, 0x04u},\r
+ {0x61u, 0x40u},\r
+ {0x63u, 0x08u},\r
+ {0x64u, 0x40u},\r
+ {0x8Du, 0x01u},\r
{0xC4u, 0xE0u},\r
{0xCCu, 0xE0u},\r
{0xCEu, 0xF0u},\r
{0xD0u, 0x10u},\r
- {0xD4u, 0x40u},\r
+ {0xD4u, 0x80u},\r
{0xD6u, 0xC0u},\r
{0xD8u, 0xC0u},\r
- {0xE2u, 0x10u},\r
- {0x30u, 0x20u},\r
- {0x32u, 0x01u},\r
- {0x37u, 0x44u},\r
- {0x3Bu, 0x10u},\r
- {0x52u, 0x20u},\r
- {0x56u, 0x20u},\r
- {0x5Au, 0x40u},\r
- {0x5Du, 0x02u},\r
- {0x68u, 0x20u},\r
- {0x6Bu, 0x20u},\r
- {0x81u, 0x02u},\r
- {0x82u, 0x20u},\r
- {0x8Bu, 0x08u},\r
- {0x8Eu, 0x20u},\r
- {0x92u, 0x40u},\r
- {0x94u, 0x44u},\r
+ {0x31u, 0x10u},\r
+ {0x33u, 0x01u},\r
+ {0x34u, 0x01u},\r
+ {0x37u, 0x20u},\r
+ {0x39u, 0x20u},\r
+ {0x53u, 0x04u},\r
+ {0x57u, 0x02u},\r
+ {0x58u, 0x80u},\r
+ {0x66u, 0x80u},\r
+ {0x81u, 0x01u},\r
+ {0x83u, 0x40u},\r
+ {0x88u, 0x88u},\r
{0x96u, 0x04u},\r
- {0x9Bu, 0x60u},\r
- {0x9Du, 0x01u},\r
- {0x9Eu, 0x40u},\r
- {0x9Fu, 0x08u},\r
- {0xA5u, 0x20u},\r
+ {0x99u, 0x10u},\r
+ {0x9Bu, 0x20u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Du, 0x40u},\r
+ {0x9Eu, 0x08u},\r
+ {0x9Fu, 0x40u},\r
+ {0xA4u, 0x0Cu},\r
{0xA6u, 0x80u},\r
- {0xA7u, 0x08u},\r
- {0xB1u, 0x04u},\r
+ {0xA7u, 0x04u},\r
+ {0xADu, 0x04u},\r
+ {0xB7u, 0x10u},\r
{0xCCu, 0xF0u},\r
{0xCEu, 0x10u},\r
- {0xD4u, 0xE0u},\r
- {0xD6u, 0x80u},\r
- {0xE6u, 0xA0u},\r
+ {0xD4u, 0xA0u},\r
+ {0xD6u, 0xA0u},\r
+ {0xE2u, 0x20u},\r
+ {0xE6u, 0x80u},\r
+ {0xEEu, 0x40u},\r
{0x12u, 0x80u},\r
{0x33u, 0x80u},\r
- {0x94u, 0x44u},\r
- {0x96u, 0x02u},\r
- {0x97u, 0x10u},\r
- {0x9Fu, 0x04u},\r
- {0xA5u, 0x20u},\r
+ {0x59u, 0x01u},\r
+ {0x86u, 0x80u},\r
+ {0x87u, 0x04u},\r
+ {0x95u, 0x20u},\r
+ {0x96u, 0x04u},\r
+ {0x97u, 0x08u},\r
+ {0x99u, 0x01u},\r
+ {0x9Cu, 0x41u},\r
+ {0x9Eu, 0x88u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA4u, 0x04u},\r
{0xA6u, 0x80u},\r
- {0xA7u, 0x08u},\r
- {0xAEu, 0x04u},\r
- {0xB2u, 0x40u},\r
- {0xB5u, 0x01u},\r
+ {0xABu, 0x04u},\r
+ {0xADu, 0x40u},\r
+ {0xB7u, 0x02u},\r
{0xC4u, 0x10u},\r
{0xCCu, 0x10u},\r
- {0xEAu, 0x40u},\r
- {0x61u, 0x01u},\r
- {0x81u, 0x01u},\r
- {0x83u, 0x04u},\r
- {0x86u, 0x01u},\r
- {0x87u, 0x10u},\r
- {0x94u, 0x44u},\r
- {0x96u, 0x02u},\r
- {0x97u, 0x10u},\r
- {0x9Fu, 0x04u},\r
- {0xA5u, 0x20u},\r
+ {0xD6u, 0x40u},\r
+ {0xE2u, 0x40u},\r
+ {0xE6u, 0x10u},\r
+ {0xEEu, 0x30u},\r
+ {0x83u, 0x20u},\r
+ {0x96u, 0x04u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Eu, 0x08u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA2u, 0x20u},\r
{0xA7u, 0x80u},\r
- {0xAFu, 0x08u},\r
- {0xD8u, 0x40u},\r
- {0xE2u, 0xB0u},\r
- {0xE6u, 0x40u},\r
+ {0xACu, 0x01u},\r
+ {0xAEu, 0x20u},\r
+ {0xB0u, 0x04u},\r
+ {0xB1u, 0x10u},\r
+ {0xE6u, 0x20u},\r
+ {0xEAu, 0x40u},\r
{0xEEu, 0x40u},\r
- {0x09u, 0x04u},\r
- {0x0Au, 0x08u},\r
- {0x0Fu, 0x20u},\r
- {0x10u, 0x10u},\r
- {0x14u, 0x80u},\r
- {0x51u, 0x08u},\r
- {0x53u, 0x01u},\r
- {0x55u, 0x40u},\r
- {0x5Du, 0x80u},\r
- {0x86u, 0x04u},\r
- {0x8Bu, 0x80u},\r
- {0x8Du, 0x04u},\r
+ {0x08u, 0x02u},\r
+ {0x09u, 0x80u},\r
+ {0x0Du, 0x01u},\r
+ {0x10u, 0x20u},\r
+ {0x14u, 0x20u},\r
+ {0x51u, 0x04u},\r
+ {0x56u, 0x01u},\r
+ {0x57u, 0x40u},\r
+ {0x59u, 0x10u},\r
+ {0x80u, 0x20u},\r
+ {0x81u, 0x80u},\r
{0xC2u, 0x0Eu},\r
{0xC4u, 0x0Cu},\r
{0xD4u, 0x07u},\r
{0xD6u, 0x04u},\r
- {0xE2u, 0x01u},\r
- {0xE6u, 0x02u},\r
- {0x03u, 0x88u},\r
- {0x05u, 0x40u},\r
- {0x06u, 0x20u},\r
- {0x0Au, 0x08u},\r
- {0x0Bu, 0x80u},\r
- {0x0Du, 0x10u},\r
- {0x0Eu, 0x20u},\r
- {0x85u, 0x40u},\r
- {0x89u, 0x08u},\r
- {0x8Fu, 0x01u},\r
- {0x97u, 0x02u},\r
- {0x9Du, 0x80u},\r
- {0xA3u, 0x10u},\r
- {0xA5u, 0x48u},\r
- {0xA7u, 0x80u},\r
- {0xA8u, 0x80u},\r
- {0xB0u, 0x10u},\r
- {0xC0u, 0x0Fu},\r
- {0xC2u, 0x0Fu},\r
- {0xE0u, 0x02u},\r
- {0xE4u, 0x04u},\r
- {0xEAu, 0x04u},\r
- {0x8Au, 0x10u},\r
- {0x8Du, 0x80u},\r
- {0x8Fu, 0x10u},\r
- {0x9Au, 0x20u},\r
- {0x9Du, 0x80u},\r
- {0xA2u, 0x10u},\r
- {0xA3u, 0x10u},\r
- {0xA5u, 0x40u},\r
- {0xAEu, 0x04u},\r
- {0xAFu, 0x08u},\r
- {0xB1u, 0x10u},\r
- {0xB3u, 0x40u},\r
- {0xE2u, 0x09u},\r
- {0xE4u, 0x02u},\r
- {0xEEu, 0x05u},\r
+ {0x02u, 0x04u},\r
+ {0x03u, 0x40u},\r
+ {0x04u, 0x01u},\r
+ {0x07u, 0x08u},\r
{0x0Au, 0x01u},\r
{0x0Bu, 0x20u},\r
+ {0x0Cu, 0x08u},\r
+ {0x0Du, 0x80u},\r
+ {0x84u, 0x20u},\r
+ {0x8Cu, 0x01u},\r
+ {0x8Du, 0x80u},\r
+ {0x91u, 0x02u},\r
+ {0x95u, 0x08u},\r
+ {0x98u, 0x22u},\r
+ {0x9Du, 0x10u},\r
+ {0x9Eu, 0x01u},\r
+ {0xA7u, 0x40u},\r
+ {0xC0u, 0x0Fu},\r
+ {0xC2u, 0x0Fu},\r
+ {0xE2u, 0x08u},\r
+ {0xE6u, 0x08u},\r
+ {0x89u, 0x05u},\r
+ {0x91u, 0x02u},\r
+ {0x93u, 0x20u},\r
+ {0x95u, 0x08u},\r
+ {0x98u, 0x02u},\r
+ {0x9Au, 0x04u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Du, 0x10u},\r
+ {0x9Eu, 0x01u},\r
+ {0xA0u, 0x08u},\r
+ {0xA7u, 0x40u},\r
+ {0xABu, 0x40u},\r
+ {0xB2u, 0x01u},\r
+ {0xE2u, 0x04u},\r
+ {0xE4u, 0x01u},\r
+ {0xEEu, 0x01u},\r
+ {0x09u, 0x08u},\r
+ {0x0Bu, 0x04u},\r
{0x0Du, 0x02u},\r
{0x0Fu, 0x02u},\r
- {0x81u, 0x02u},\r
- {0x86u, 0x01u},\r
+ {0x82u, 0x05u},\r
{0x87u, 0x10u},\r
- {0xAAu, 0x20u},\r
- {0xB1u, 0x40u},\r
+ {0x8Bu, 0x20u},\r
+ {0x93u, 0x20u},\r
+ {0x97u, 0x04u},\r
+ {0x98u, 0x02u},\r
+ {0x9Au, 0x04u},\r
+ {0x9Du, 0x10u},\r
+ {0x9Eu, 0x01u},\r
+ {0xA5u, 0x02u},\r
+ {0xA7u, 0x40u},\r
+ {0xA8u, 0x08u},\r
+ {0xADu, 0x02u},\r
+ {0xAFu, 0x08u},\r
+ {0xB3u, 0x04u},\r
{0xC2u, 0x0Fu},\r
- {0xECu, 0x04u},\r
- {0x8Cu, 0x04u},\r
- {0x94u, 0x04u},\r
- {0xAFu, 0x80u},\r
- {0xB4u, 0x40u},\r
- {0xB5u, 0x20u},\r
+ {0xE2u, 0x01u},\r
+ {0xEEu, 0x04u},\r
+ {0x86u, 0x04u},\r
+ {0x88u, 0x40u},\r
+ {0x96u, 0x04u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Eu, 0x08u},\r
+ {0xA2u, 0x20u},\r
+ {0xA3u, 0x20u},\r
+ {0xAFu, 0x81u},\r
+ {0xE2u, 0x40u},\r
+ {0xEAu, 0x40u},\r
{0xEEu, 0x10u},\r
- {0x04u, 0x08u},\r
- {0x52u, 0x80u},\r
- {0x56u, 0x20u},\r
- {0x82u, 0x80u},\r
- {0x8Cu, 0x04u},\r
- {0x8Eu, 0x20u},\r
+ {0x06u, 0x40u},\r
+ {0x52u, 0x20u},\r
+ {0x57u, 0x20u},\r
+ {0x86u, 0x40u},\r
+ {0x8Au, 0x08u},\r
+ {0x9Eu, 0x08u},\r
+ {0xA2u, 0x20u},\r
+ {0xA3u, 0x20u},\r
{0xC0u, 0x20u},\r
{0xD4u, 0x60u},\r
- {0xE6u, 0x20u},\r
- {0x88u, 0x04u},\r
+ {0xE0u, 0x10u},\r
+ {0x81u, 0x10u},\r
+ {0x8Fu, 0x40u},\r
+ {0x98u, 0x02u},\r
+ {0x9Du, 0x10u},\r
+ {0xA7u, 0x60u},\r
+ {0xADu, 0x08u},\r
{0xAFu, 0x01u},\r
- {0xE2u, 0x04u},\r
- {0x00u, 0x08u},\r
- {0xA4u, 0x04u},\r
+ {0xE4u, 0x02u},\r
+ {0x03u, 0x20u},\r
+ {0xA7u, 0x20u},\r
+ {0xB4u, 0x02u},\r
{0xC0u, 0x08u},\r
+ {0xEAu, 0x08u},\r
{0x10u, 0x03u},\r
{0x11u, 0x01u},\r
{0x1Au, 0x03u},\r
- {0x1Bu, 0x01u},\r
+ {0x1Cu, 0x02u},\r
+ {0x1Du, 0x01u},\r
{0x00u, 0xFDu},\r
{0x01u, 0xBFu},\r
{0x02u, 0x2Au},\r
static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
/* address, size */\r
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
- {(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
{(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},\r
};\r
\r
- /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */\r
- static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {\r
- 0x8Du, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x0Du, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Du, 0x00u, 0x80u, 0x00u, \r
- 0x00u, 0x0Fu, 0x10u, 0xF0u, 0x62u, 0x30u, 0x08u, 0xC0u, 0x02u, 0x50u, 0x54u, 0xA0u, 0x01u, 0x06u, 0x32u, 0x09u, \r
- 0x8Du, 0x05u, 0x00u, 0x0Au, 0x8Du, 0x03u, 0x00u, 0x0Cu, 0x8Du, 0x00u, 0x00u, 0x00u, 0x00u, 0x60u, 0x00u, 0x90u, \r
- 0x70u, 0x00u, 0x0Fu, 0x00u, 0x80u, 0x00u, 0x80u, 0xFFu, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x50u, 0x40u, \r
- 0x63u, 0x05u, 0x20u, 0x00u, 0x01u, 0xFEu, 0xBDu, 0xCBu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, \r
- 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
-\r
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u};\r
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u},\r
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},\r
};\r
\r
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR), (const void CYCODE *)(BS_IOPINS0_7_VAL), 10u);\r
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR + 0x0000000Bu), (const void CYCODE *)(BS_IOPINS1_7_VAL), 5u);\r
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u);\r
+ CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT1_DM0), (const void CYCODE *)(BS_IOPINS0_1_VAL), 8u);\r
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u);\r
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DR), (const void CYCODE *)(BS_IOPINS0_3_VAL), 10u);\r
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u);\r
/*******************************************************************************\r
* File Name: cyfitter_cfg.h\r
* \r
-* PSoC Creator 3.3\r
+* PSoC Creator 4.0 Update 1\r
*\r
* Description:\r
* This file provides basic startup and mux configration settings\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB05_MSK\r
+.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB05_ST\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST\r
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
.set SDCard_BSPIM_TxStsReg__2__POS, 2\r
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08\r
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
-.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB05_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB05_ST\r
\r
/* SD_SCK */\r
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL\r
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK\r
\r
/* SCSI_Out_Ctl */\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB09_10_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB09_10_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB09_10_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB09_10_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB09_10_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB09_10_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB09_10_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB09_10_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB09_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB09_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB09_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB09_ST_CTL\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB09_MSK\r
\r
/* SCSI_Out_DBx */\r
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST\r
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB12_MSK\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB12_ST\r
\r
/* SCSI_CTL_PHASE */\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B1_UDB07_ST\r
\r
/* Miscellaneous */\r
.set BCLK__BUS_CLK__HZ, 50000000\r
.set BCLK__BUS_CLK__KHZ, 50000\r
.set BCLK__BUS_CLK__MHZ, 50\r
.set CYDEV_CHIP_DIE_LEOPARD, 1\r
-.set CYDEV_CHIP_DIE_PANTHER, 18\r
-.set CYDEV_CHIP_DIE_PSOC4A, 10\r
-.set CYDEV_CHIP_DIE_PSOC5LP, 17\r
+.set CYDEV_CHIP_DIE_PSOC4A, 12\r
+.set CYDEV_CHIP_DIE_PSOC5LP, 19\r
+.set CYDEV_CHIP_DIE_PSOC5TM, 20\r
.set CYDEV_CHIP_DIE_TMA4, 2\r
.set CYDEV_CHIP_DIE_UNKNOWN, 0\r
+.set CYDEV_CHIP_FAMILY_FM0P, 4\r
+.set CYDEV_CHIP_FAMILY_FM3, 5\r
+.set CYDEV_CHIP_FAMILY_FM4, 6\r
.set CYDEV_CHIP_FAMILY_PSOC3, 1\r
.set CYDEV_CHIP_FAMILY_PSOC4, 2\r
.set CYDEV_CHIP_FAMILY_PSOC5, 3\r
.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5\r
.set CYDEV_CHIP_JTAG_ID, 0x2E133069\r
.set CYDEV_CHIP_MEMBER_3A, 1\r
-.set CYDEV_CHIP_MEMBER_4A, 10\r
-.set CYDEV_CHIP_MEMBER_4C, 15\r
-.set CYDEV_CHIP_MEMBER_4D, 6\r
+.set CYDEV_CHIP_MEMBER_4A, 12\r
+.set CYDEV_CHIP_MEMBER_4C, 18\r
+.set CYDEV_CHIP_MEMBER_4D, 8\r
.set CYDEV_CHIP_MEMBER_4E, 4\r
-.set CYDEV_CHIP_MEMBER_4F, 11\r
+.set CYDEV_CHIP_MEMBER_4F, 13\r
.set CYDEV_CHIP_MEMBER_4G, 2\r
-.set CYDEV_CHIP_MEMBER_4H, 9\r
-.set CYDEV_CHIP_MEMBER_4I, 14\r
-.set CYDEV_CHIP_MEMBER_4J, 7\r
-.set CYDEV_CHIP_MEMBER_4K, 8\r
-.set CYDEV_CHIP_MEMBER_4L, 13\r
-.set CYDEV_CHIP_MEMBER_4M, 12\r
-.set CYDEV_CHIP_MEMBER_4N, 5\r
+.set CYDEV_CHIP_MEMBER_4H, 11\r
+.set CYDEV_CHIP_MEMBER_4I, 17\r
+.set CYDEV_CHIP_MEMBER_4J, 9\r
+.set CYDEV_CHIP_MEMBER_4K, 10\r
+.set CYDEV_CHIP_MEMBER_4L, 16\r
+.set CYDEV_CHIP_MEMBER_4M, 15\r
+.set CYDEV_CHIP_MEMBER_4N, 6\r
+.set CYDEV_CHIP_MEMBER_4O, 5\r
+.set CYDEV_CHIP_MEMBER_4P, 14\r
+.set CYDEV_CHIP_MEMBER_4Q, 7\r
.set CYDEV_CHIP_MEMBER_4U, 3\r
-.set CYDEV_CHIP_MEMBER_5A, 17\r
-.set CYDEV_CHIP_MEMBER_5B, 16\r
+.set CYDEV_CHIP_MEMBER_5A, 20\r
+.set CYDEV_CHIP_MEMBER_5B, 19\r
+.set CYDEV_CHIP_MEMBER_FM3, 24\r
+.set CYDEV_CHIP_MEMBER_FM4, 25\r
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 21\r
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 22\r
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 23\r
.set CYDEV_CHIP_MEMBER_UNKNOWN, 0\r
.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B\r
.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED\r
.set CYDEV_CHIP_REV_LEOPARD_ES2, 1\r
.set CYDEV_CHIP_REV_LEOPARD_ES3, 3\r
.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3\r
-.set CYDEV_CHIP_REV_PANTHER_ES0, 0\r
-.set CYDEV_CHIP_REV_PANTHER_ES1, 1\r
-.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1\r
.set CYDEV_CHIP_REV_PSOC4A_ES0, 17\r
.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17\r
.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0\r
.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0\r
+.set CYDEV_CHIP_REV_PSOC5TM_ES0, 0\r
+.set CYDEV_CHIP_REV_PSOC5TM_ES1, 1\r
+.set CYDEV_CHIP_REV_PSOC5TM_PRODUCTION, 1\r
.set CYDEV_CHIP_REV_TMA4_ES, 17\r
.set CYDEV_CHIP_REV_TMA4_ES2, 33\r
.set CYDEV_CHIP_REV_TMA4_PRODUCTION, 17\r
.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_4N_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_5A_ES0, 0\r
.set CYDEV_CHIP_REVISION_5A_ES1, 1\r
.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1\r
.set CYDEV_CHIP_REVISION_5B_ES0, 0\r
.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION\r
.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED\r
.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST\r
\r
/* SD_SCK */\r
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
\r
/* SCSI_Out_Ctl */\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK\r
\r
/* SCSI_Out_DBx */\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
\r
/* SCSI_CTL_PHASE */\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
\r
/* Miscellaneous */\r
BCLK__BUS_CLK__HZ EQU 50000000\r
BCLK__BUS_CLK__KHZ EQU 50000\r
BCLK__BUS_CLK__MHZ EQU 50\r
CYDEV_CHIP_DIE_LEOPARD EQU 1\r
-CYDEV_CHIP_DIE_PANTHER EQU 18\r
-CYDEV_CHIP_DIE_PSOC4A EQU 10\r
-CYDEV_CHIP_DIE_PSOC5LP EQU 17\r
+CYDEV_CHIP_DIE_PSOC4A EQU 12\r
+CYDEV_CHIP_DIE_PSOC5LP EQU 19\r
+CYDEV_CHIP_DIE_PSOC5TM EQU 20\r
CYDEV_CHIP_DIE_TMA4 EQU 2\r
CYDEV_CHIP_DIE_UNKNOWN EQU 0\r
+CYDEV_CHIP_FAMILY_FM0P EQU 4\r
+CYDEV_CHIP_FAMILY_FM3 EQU 5\r
+CYDEV_CHIP_FAMILY_FM4 EQU 6\r
CYDEV_CHIP_FAMILY_PSOC3 EQU 1\r
CYDEV_CHIP_FAMILY_PSOC4 EQU 2\r
CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
CYDEV_CHIP_JTAG_ID EQU 0x2E133069\r
CYDEV_CHIP_MEMBER_3A EQU 1\r
-CYDEV_CHIP_MEMBER_4A EQU 10\r
-CYDEV_CHIP_MEMBER_4C EQU 15\r
-CYDEV_CHIP_MEMBER_4D EQU 6\r
+CYDEV_CHIP_MEMBER_4A EQU 12\r
+CYDEV_CHIP_MEMBER_4C EQU 18\r
+CYDEV_CHIP_MEMBER_4D EQU 8\r
CYDEV_CHIP_MEMBER_4E EQU 4\r
-CYDEV_CHIP_MEMBER_4F EQU 11\r
+CYDEV_CHIP_MEMBER_4F EQU 13\r
CYDEV_CHIP_MEMBER_4G EQU 2\r
-CYDEV_CHIP_MEMBER_4H EQU 9\r
-CYDEV_CHIP_MEMBER_4I EQU 14\r
-CYDEV_CHIP_MEMBER_4J EQU 7\r
-CYDEV_CHIP_MEMBER_4K EQU 8\r
-CYDEV_CHIP_MEMBER_4L EQU 13\r
-CYDEV_CHIP_MEMBER_4M EQU 12\r
-CYDEV_CHIP_MEMBER_4N EQU 5\r
+CYDEV_CHIP_MEMBER_4H EQU 11\r
+CYDEV_CHIP_MEMBER_4I EQU 17\r
+CYDEV_CHIP_MEMBER_4J EQU 9\r
+CYDEV_CHIP_MEMBER_4K EQU 10\r
+CYDEV_CHIP_MEMBER_4L EQU 16\r
+CYDEV_CHIP_MEMBER_4M EQU 15\r
+CYDEV_CHIP_MEMBER_4N EQU 6\r
+CYDEV_CHIP_MEMBER_4O EQU 5\r
+CYDEV_CHIP_MEMBER_4P EQU 14\r
+CYDEV_CHIP_MEMBER_4Q EQU 7\r
CYDEV_CHIP_MEMBER_4U EQU 3\r
-CYDEV_CHIP_MEMBER_5A EQU 17\r
-CYDEV_CHIP_MEMBER_5B EQU 16\r
+CYDEV_CHIP_MEMBER_5A EQU 20\r
+CYDEV_CHIP_MEMBER_5B EQU 19\r
+CYDEV_CHIP_MEMBER_FM3 EQU 24\r
+CYDEV_CHIP_MEMBER_FM4 EQU 25\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23\r
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED\r
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1\r
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3\r
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3\r
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0\r
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1\r
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1\r
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17\r
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17\r
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0\r
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0\r
+CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0\r
+CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1\r
+CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1\r
CYDEV_CHIP_REV_TMA4_ES EQU 17\r
CYDEV_CHIP_REV_TMA4_ES2 EQU 33\r
CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17\r
CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
CYDEV_CHIP_REVISION_5B_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION\r
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED\r
CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
\r
; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST\r
\r
; SD_SCK\r
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
\r
; SCSI_Out_Ctl\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK\r
\r
; SCSI_Out_DBx\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
\r
; SCSI_CTL_PHASE\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
\r
; SCSI_Glitch_Ctl\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
\r
; SCSI_Parity_Error\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
\r
; Miscellaneous\r
BCLK__BUS_CLK__HZ EQU 50000000\r
BCLK__BUS_CLK__KHZ EQU 50000\r
BCLK__BUS_CLK__MHZ EQU 50\r
CYDEV_CHIP_DIE_LEOPARD EQU 1\r
-CYDEV_CHIP_DIE_PANTHER EQU 18\r
-CYDEV_CHIP_DIE_PSOC4A EQU 10\r
-CYDEV_CHIP_DIE_PSOC5LP EQU 17\r
+CYDEV_CHIP_DIE_PSOC4A EQU 12\r
+CYDEV_CHIP_DIE_PSOC5LP EQU 19\r
+CYDEV_CHIP_DIE_PSOC5TM EQU 20\r
CYDEV_CHIP_DIE_TMA4 EQU 2\r
CYDEV_CHIP_DIE_UNKNOWN EQU 0\r
+CYDEV_CHIP_FAMILY_FM0P EQU 4\r
+CYDEV_CHIP_FAMILY_FM3 EQU 5\r
+CYDEV_CHIP_FAMILY_FM4 EQU 6\r
CYDEV_CHIP_FAMILY_PSOC3 EQU 1\r
CYDEV_CHIP_FAMILY_PSOC4 EQU 2\r
CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
CYDEV_CHIP_JTAG_ID EQU 0x2E133069\r
CYDEV_CHIP_MEMBER_3A EQU 1\r
-CYDEV_CHIP_MEMBER_4A EQU 10\r
-CYDEV_CHIP_MEMBER_4C EQU 15\r
-CYDEV_CHIP_MEMBER_4D EQU 6\r
+CYDEV_CHIP_MEMBER_4A EQU 12\r
+CYDEV_CHIP_MEMBER_4C EQU 18\r
+CYDEV_CHIP_MEMBER_4D EQU 8\r
CYDEV_CHIP_MEMBER_4E EQU 4\r
-CYDEV_CHIP_MEMBER_4F EQU 11\r
+CYDEV_CHIP_MEMBER_4F EQU 13\r
CYDEV_CHIP_MEMBER_4G EQU 2\r
-CYDEV_CHIP_MEMBER_4H EQU 9\r
-CYDEV_CHIP_MEMBER_4I EQU 14\r
-CYDEV_CHIP_MEMBER_4J EQU 7\r
-CYDEV_CHIP_MEMBER_4K EQU 8\r
-CYDEV_CHIP_MEMBER_4L EQU 13\r
-CYDEV_CHIP_MEMBER_4M EQU 12\r
-CYDEV_CHIP_MEMBER_4N EQU 5\r
+CYDEV_CHIP_MEMBER_4H EQU 11\r
+CYDEV_CHIP_MEMBER_4I EQU 17\r
+CYDEV_CHIP_MEMBER_4J EQU 9\r
+CYDEV_CHIP_MEMBER_4K EQU 10\r
+CYDEV_CHIP_MEMBER_4L EQU 16\r
+CYDEV_CHIP_MEMBER_4M EQU 15\r
+CYDEV_CHIP_MEMBER_4N EQU 6\r
+CYDEV_CHIP_MEMBER_4O EQU 5\r
+CYDEV_CHIP_MEMBER_4P EQU 14\r
+CYDEV_CHIP_MEMBER_4Q EQU 7\r
CYDEV_CHIP_MEMBER_4U EQU 3\r
-CYDEV_CHIP_MEMBER_5A EQU 17\r
-CYDEV_CHIP_MEMBER_5B EQU 16\r
+CYDEV_CHIP_MEMBER_5A EQU 20\r
+CYDEV_CHIP_MEMBER_5B EQU 19\r
+CYDEV_CHIP_MEMBER_FM3 EQU 24\r
+CYDEV_CHIP_MEMBER_FM4 EQU 25\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23\r
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED\r
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1\r
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3\r
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3\r
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0\r
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1\r
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1\r
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17\r
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17\r
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0\r
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0\r
+CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0\r
+CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1\r
+CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1\r
CYDEV_CHIP_REV_TMA4_ES EQU 17\r
CYDEV_CHIP_REV_TMA4_ES2 EQU 33\r
CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17\r
CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
CYDEV_CHIP_REVISION_5B_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION\r
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED\r
CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1\r
/*******************************************************************************\r
* File Name: cymetadata.c\r
* \r
-* PSoC Creator 3.3\r
+* PSoC Creator 4.0 Update 1\r
*\r
* Description:\r
* This file defines all extra memory spaces that need to be included.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
\r
#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
-__attribute__ ((__section__(".cyloadablemeta"), used))\r
+#ifndef CY_LOADABLE_META_SECTION\r
+#define CY_LOADABLE_META_SECTION __attribute__ ((__section__(".cyloadablemeta"), used))\r
+#endif\r
+CY_LOADABLE_META_SECTION\r
#elif defined(__ICCARM__)\r
#pragma location=".cyloadablemeta"\r
#else\r
const uint8 cy_meta_loadable[] = {\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x60u, 0x04u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x71u, 0x04u,\r
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
};\r
\r
#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
-__attribute__ ((__section__(".cyconfigecc"), used))\r
+#ifndef CY_CONFIG_ECC_SECTION\r
+#define CY_CONFIG_ECC_SECTION __attribute__ ((__section__(".cyconfigecc"), used))\r
+#endif\r
+CY_CONFIG_ECC_SECTION\r
#elif defined(__ICCARM__)\r
#pragma location=".cyconfigecc"\r
#else\r
-/*******************************************************************************\r
-* File Name: cypins.h\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file cypins.h\r
+* \version 5.50\r
*\r
-* Description:\r
-* This file contains the function prototypes and constants used for a port/pin\r
-* in access and control.\r
+* \brief This file contains the function prototypes and constants used for a\r
+* port/pin in access and control.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the\r
-* System Reference Guide provided with PSoC Creator.\r
+* \note Documentation of the API's in this file is located in the\r
+* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Macro Name: CyPins_ReadPin\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Reads the current value on the pin (pin state, PS).\r
*\r
-* Parameters:\r
-* pinPC: Port pin configuration register (uint16).\r
+* \param pinPC: Port pin configuration register (uint16).\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
-* in the form:\r
+* \param in the form:\r
* CYREG_PRTx_PCy\r
*\r
* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
*\r
-* Return:\r
+* \return\r
* Pin state\r
* 0: Logic low value\r
* Non-0: Logic high value\r
\r
/*******************************************************************************\r
* Macro Name: CyPins_SetPin\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Set the output value for the pin (data register, DR) to a logic high.\r
*\r
* Note that this only has an effect for pins configured as software pins that\r
* interrupt is disabled or within critical section (all interrupts are\r
* disabled).\r
*\r
-* Parameters:\r
-* pinPC: Port pin configuration register (uint16).\r
+* \param pinPC: Port pin configuration register (uint16).\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
-* in the form:\r
+* \param in the form:\r
* CYREG_PRTx_PCy\r
*\r
* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
#define CyPins_SetPin(pinPC) ( *(reg8 *)(pinPC) |= CY_PINS_PC_DATAOUT)\r
\r
\r
/*******************************************************************************\r
* Macro Name: CyPins_ClearPin\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This macro sets the state of the specified pin to 0.\r
*\r
* The macro operation is not atomic. It is not guaranteed that shared register\r
* interrupt is disabled or within critical section (all interrupts are\r
* disabled).\r
*\r
-* Parameters:\r
-* pinPC: address of a Pin Configuration register.\r
+* \param pinPC: address of a Pin Configuration register.\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
-* in the form:\r
+* \param in the form:\r
* CYREG_PRTx_PCy\r
*\r
* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
#define CyPins_ClearPin(pinPC) ( *(reg8 *)(pinPC) &= ((uint8)(~CY_PINS_PC_DATAOUT)))\r
\r
\r
/*******************************************************************************\r
* Macro Name: CyPins_SetPinDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the drive mode for the pin (DM).\r
*\r
* The macro operation is not atomic. It is not guaranteed that shared register\r
* interrupt is disabled or within critical section (all interrupts are\r
* disabled).\r
*\r
-* Parameters:\r
-* pinPC: Port pin configuration register (uint16)\r
+* \param pinPC: Port pin configuration register (uint16)\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
-* in the form:\r
+* \param in the form:\r
* CYREG_PRTx_PCy\r
*\r
* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
*\r
-* mode: Desired drive mode\r
+* \param mode: Desired drive mode\r
*\r
* Define Source\r
* PIN_DM_ALG_HIZ Analog HiZ\r
* PIN_DM_STRONG Strong CMOS Output\r
* PIN_DM_RES_UPDWN Resistive pull up/down\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
#define CyPins_SetPinDriveMode(pinPC, mode) \\r
( *(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & ((uint8)(~CY_PINS_PC_DRIVE_MODE_MASK))) | \\r
\r
/*******************************************************************************\r
* Macro Name: CyPins_ReadPinDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Reads the drive mode for the pin (DM).\r
*\r
-* Parameters:\r
-* pinPC: Port pin configuration register (uint16)\r
+* \param pinPC: Port pin configuration register (uint16)\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
-* in the form:\r
+* \param in the form:\r
* CYREG_PRTx_PCy\r
*\r
* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
*\r
*\r
-* Return:\r
+* \return\r
* mode: The current drive mode for the pin\r
*\r
* Define Source\r
\r
/*******************************************************************************\r
* Macro Name: CyPins_FastSlew\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Set the slew rate for the pin to fast the edge rate.\r
* Note that this only applies for pins in strong output drive modes,\r
* not to resistive drive modes.\r
* interrupt is disabled or within critical section (all interrupts are\r
* disabled).\r
*\r
-* Parameters:\r
-* pinPC: address of a Pin Configuration register.\r
+* \param pinPC: address of a Pin Configuration register.\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
-* in the form:\r
+* \param in the form:\r
* CYREG_PRTx_PCy\r
*\r
* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
*\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
#define CyPins_FastSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & CY_PINS_PC_PIN_FASTSLEW))\r
\r
\r
/*******************************************************************************\r
* Macro Name: CyPins_SlowSlew\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Set the slew rate for the pin to slow the edge rate.\r
* Note that this only applies for pins in strong output drive modes,\r
* not to resistive drive modes.\r
* interrupt is disabled or within critical section (all interrupts are\r
* disabled).\r
*\r
-* Parameters:\r
-* pinPC: address of a Pin Configuration register.\r
+* \param pinPC: address of a Pin Configuration register.\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
-* in the form:\r
+* \param in the form:\r
* CYREG_PRTx_PCy\r
*\r
* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
#define CyPins_SlowSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) | CY_PINS_PC_PIN_SLOWSLEW))\r
\r
-/*******************************************************************************\r
-* FILENAME: cytypes.h\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file cytypes.h\r
+* \version 5.50\r
*\r
-* Description:\r
-* CyTypes provides register access macros and approved types for use in\r
-* firmware.\r
+* \brief CyTypes provides register access macros and approved types for use in\r
+* firmware.\r
*\r
-* Note:\r
-* Due to endiannesses of the hardware and some compilers, the register\r
-* access macros for big endian compilers use some library calls to arrange\r
-* data the correct way.\r
+* \note Due to endiannesses of the hardware and some compilers, the register\r
+* access macros for big endian compilers use some library calls to arrange\r
+* data the correct way.\r
*\r
-* Register Access macros and functions perform their operations on an\r
-* input of the type pointer to void. The arguments passed to it should be\r
-* pointers to the type associated with the register size.\r
-* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value)\r
+* Register Access macros and functions perform their operations on an\r
+* input of the type pointer to void. The arguments passed to it should be\r
+* pointers to the type associated with the register size.\r
+* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value)\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#define CY_PSOC4_4200BL (0u != 0u)\r
#endif /* CYDEV_CHIP_MEMBER_4F */\r
\r
+#ifdef CYDEV_CHIP_MEMBER_4M\r
+ #define CY_PSOC4_4100M (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4M)\r
+ #define CY_PSOC4_4200M (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4M)\r
+#else\r
+ #define CY_PSOC4_4100M (0u != 0u)\r
+ #define CY_PSOC4_4200M (0u != 0u)\r
+#endif /* CYDEV_CHIP_MEMBER_4M */\r
+\r
+#ifdef CYDEV_CHIP_MEMBER_4H\r
+ #define CY_PSOC4_4200D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4H)\r
+#else\r
+ #define CY_PSOC4_4200D (0u != 0u)\r
+#endif /* CYDEV_CHIP_MEMBER_4H */\r
+\r
+#ifdef CYDEV_CHIP_MEMBER_4L\r
+ #define CY_PSOC4_4200L (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4L)\r
+#else\r
+ #define CY_PSOC4_4200L (0u != 0u)\r
+#endif /* CYDEV_CHIP_MEMBER_4L */\r
+\r
+#ifdef CYDEV_CHIP_MEMBER_4U\r
+ #define CY_PSOC4_4000U (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4U)\r
+#else\r
+ #define CY_PSOC4_4000U (0u != 0u)\r
+#endif /* CYDEV_CHIP_MEMBER_4U */\r
+\r
+#ifdef CYDEV_CHIP_MEMBER_4J\r
+ #define CY_PSOC4_4000S (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4J)\r
+#else\r
+ #define CY_PSOC4_4000S (0u != 0u)\r
+#endif /* CYDEV_CHIP_MEMBER_4J */\r
+\r
+#ifdef CYDEV_CHIP_MEMBER_4K\r
+ #define CY_PSOC4_4100S (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4K)\r
+#else\r
+ #define CY_PSOC4_4100S (0u != 0u)\r
+#endif /* CYDEV_CHIP_MEMBER_4K */\r
+\r
+\r
+#define CY_IP_HOBTO_DEVICE (!(0 == 1))\r
+\r
\r
/*******************************************************************************\r
* IP blocks\r
#if (CY_PSOC4)\r
\r
/* Using SRSSv2 or SRS-Lite */\r
- #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
- #define CY_IP_SRSSV2 (0u == 0u)\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #define CY_IP_SRSSV2 (0 != 0)\r
#define CY_IP_SRSSLT (!CY_IP_SRSSV2)\r
#else\r
- #define CY_IP_SRSSV2 (0u != 0u)\r
+ #define CY_IP_SRSSV2 (0 == 0)\r
#define CY_IP_SRSSLT (!CY_IP_SRSSV2)\r
- #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #define CY_IP_CPUSSV3 (0 == 1)\r
+ #define CY_IP_CPUSSV2 (0 == 1)\r
+ #define CY_IP_CPUSS (0 == 1)\r
+ #else\r
+ #define CY_IP_CPUSSV3 (0 != 0)\r
+ #define CY_IP_CPUSSV2 (0 != 0)\r
+ #define CY_IP_CPUSS (0 == 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+ /* CM0 present or CM0+ present (1=CM0, 0=CM0+) */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_IP_CPUSS_CM0 (0 == 0)\r
+ #else /* CY_IP_CPUSSV3 */\r
+ #define CY_IP_CPUSS_CM0 (-1 == 1)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
+ #define CY_IP_CPUSS_CM0PLUS (!CY_IP_CPUSS_CM0)\r
+ #else\r
+ #define CY_IP_CPUSS_CM0 (0 == 0)\r
+ #define CY_IP_CPUSS_CM0PLUS (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
\r
- #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
- #define CY_IP_CPUSSV2 (0u != 0u)\r
- #define CY_IP_CPUSS (0u == 0u)\r
+\r
+ /* Flash memory present or not (1=Flash present, 0=Flash not present) */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #define CY_IP_CPUSS_FLASHC_PRESENT (0 == 0)\r
#else\r
- #define CY_IP_CPUSSV2 (0u != 0u)\r
- #define CY_IP_CPUSS (!CY_IP_CPUSSV2)\r
- #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+ #define CY_IP_CPUSS_FLASHC_PRESENT (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
\r
/* Product uses FLASH-Lite or regular FLASH */\r
- #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
- #define CY_IP_FMLT (0u != 0u) /* FLASH-Lite */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_IP_FM (-1 == 0)\r
+ #define CY_IP_FMLT (-1 == 1)\r
+ #define CY_IP_FS (-1 == 2)\r
+ #define CY_IP_FSLT (-1 == 3)\r
+ #else /* CY_IP_CPUSSV3 */\r
+ #define CY_IP_FM (-1 == 0)\r
+ #define CY_IP_FMLT (-1 == 1)\r
+ #define CY_IP_FS (-1 == 2)\r
+ #define CY_IP_FSLT (-1 == 3)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
+ #else\r
#define CY_IP_FM (!CY_IP_FMLT) /* Regular FLASH */\r
+ #define CY_IP_FMLT (0 != 0) /* FLASH-Lite */\r
+ #define CY_IP_FS (0 != 0) /* FS */\r
+ #define CY_IP_FSLT (0 != 0) /* FSLT */\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+\r
+ /* Enable simultaneous execution/programming in multi-macro devices */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_IP_FLASH_PARALLEL_PGM_EN (-1 == 1)\r
+ #else /* CY_IP_CPUSSV3 */\r
+ #define CY_IP_FLASH_PARALLEL_PGM_EN (-1 == 1)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
#else\r
- #define CY_IP_FMLT (-1u != 0u)\r
- #define CY_IP_FM (!CY_IP_FMLT)\r
- #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+ #define CY_IP_FLASH_PARALLEL_PGM_EN (0u != 0u)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+\r
+ /* Number of Flash macros used in the device (0, 1 or 2) */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_IP_FLASH_MACROS (-1u)\r
+ #else /* CY_IP_CPUSSV3 */\r
+ #define CY_IP_FLASH_MACROS (-1u)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
+ #else\r
+ #define CY_IP_FLASH_MACROS (1u)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
\r
/* Number of interrupt request inputs to CM0 */\r
- #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_IP_INT_NR (-1u)\r
+ #else /* CY_IP_CPUSSV3 */\r
+ #define CY_IP_INT_NR (-1u)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
+ #else\r
#define CY_IP_INT_NR (32u)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+\r
+ /* Presence of the BLESS IP block */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #define CY_IP_BLESS (0 != 0)\r
#else\r
- #define CY_IP_INT_NR (-1u)\r
- #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+ #define CY_IP_BLESS (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
\r
- /* Number of Flash macros used in the device (0, 1 or 2) */\r
- #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
- #define CY_IP_FLASH_MACROS (1u)\r
+\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #define CY_IP_USBDEV (0 != 0)\r
#else\r
- #define CY_IP_FLASH_MACROS (-1u)\r
- #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+ #define CY_IP_USBDEV (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
\r
\r
- /* Number of Flash macros used in the device (0, 1 or 2) */\r
- #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
- #define CY_IP_BLESS (0u != 0u)\r
+ /***************************************************************************\r
+ * Devices with the SPCIF_SYNCHRONOUS parameter set to one will not use\r
+ * the 36MHz Oscillator for Flash operation. Instead, flash write function\r
+ * ensures that the charge pump clock and the higher frequency clock (HFCLK)\r
+ * are set to the IMO at 48MHz prior to writing the flash.\r
+ ***************************************************************************/\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_IP_SPCIF_SYNCHRONOUS (-1 == 1)\r
+ #else /* CY_IP_CPUSSV3 */\r
+ #define CY_IP_SPCIF_SYNCHRONOUS (-1 == 1)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
#else\r
- #define CY_IP_BLESS (0u != 0u)\r
- #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+ #define CY_IP_SPCIF_SYNCHRONOUS (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
\r
/* Watch Crystal Oscillator (WCO) is present (32kHz) */\r
- #if (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200)\r
- #define CY_IP_WCO (0u != 0u)\r
- #elif CY_IP_BLESS || defined (CYIPBLOCK_s8swco_VERSION)\r
- #define CY_IP_WCO (0u == 0u)\r
- #elif (CY_IP_SRSSV2)\r
- #define CY_IP_WCO (-1u)\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_BLESS)\r
+ #define CY_IP_WCO_BLESS (0 == 0)\r
+ #define CY_IP_WCO_WCO (0 != 0)\r
+ #define CY_IP_WCO_SRSSV2 (0 != 0)\r
+ #else\r
+ #define CY_IP_WCO_BLESS (0 != 0)\r
+ #define CY_IP_WCO_WCO (0 == 1)\r
+ #define CY_IP_WCO_SRSSV2 (-1 == 1)\r
+ #endif /* (CY_IP_BLESS) */\r
#else\r
- #define CY_IP_WCO (0u != 0u)\r
- #endif /* (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+ #define CY_IP_WCO_BLESS (0 != 0)\r
+ #define CY_IP_WCO_WCO (0 != 0)\r
+ #define CY_IP_WCO_SRSSV2 (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+ #define CY_IP_WCO (CY_IP_WCO_BLESS || CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2)\r
+\r
+\r
+ /* PLL is present */\r
+ #if (CY_IP_HOBTO_DEVICE && CY_IP_SRSSV2)\r
+ #define CY_IP_PLL ((-1 != 0) || \\r
+ (-1 != 0))\r
+\r
+ #define CY_IP_PLL_NR (-1u + \\r
+ -1u)\r
+ #else\r
+ #define CY_IP_PLL (0 != 0)\r
+ #define CY_IP_PLL_NR (0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE && CY_IP_SRSSV2) */\r
+\r
+\r
+ /* External Crystal Oscillator is present (high frequency) */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_BLESS)\r
+ #define CY_IP_ECO_BLESS (0 == 0)\r
+ #define CY_IP_ECO_SRSSV2 (0 != 0)\r
+ #else\r
+ #define CY_IP_ECO_BLESS (0 != 0)\r
+ #define CY_IP_ECO_SRSSV2 (-1 == 1)\r
+ #endif /* (CY_IP_BLESS) */\r
+ #else\r
+ #define CY_IP_ECO_BLESS (0 != 0)\r
+ #define CY_IP_ECO_SRSSV2 (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+ #define CY_IP_ECO (CY_IP_ECO_BLESS || CY_IP_ECO_SRSSV2)\r
+\r
+\r
+ /* Clock Source clk_lf implemented in SysTick Counter. When 0, not implemented, 1=implemented */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_SYSTICK_LFCLK_SOURCE (-1 != 0)\r
+ #else /* CY_IP_CPUSSV3 */\r
+ #define CY_SYSTICK_LFCLK_SOURCE (-1 != 0)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
+ #else\r
+ #define CY_SYSTICK_LFCLK_SOURCE (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+\r
+ /* Flash Macro 0 has extra rows */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #ifdef CYREG_SFLASH_MACRO_0_FREE_SFLASH0\r
+ #define CY_SFLASH_XTRA_ROWS (0 == 0)\r
+ #else\r
+ #define CY_SFLASH_XTRA_ROWS (0 != 0)\r
+ #endif /* CYREG_SFLASH_MACRO_0_FREE_SFLASH0 */\r
+\r
+ #else\r
+ #define CY_SFLASH_XTRA_ROWS (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+\r
+ #if (CY_IP_USBDEV)\r
+ #define CY_IP_IMO_TRIMMABLE_BY_USB (0 == 0)\r
+ #else\r
+ #define CY_IP_IMO_TRIMMABLE_BY_USB (0 != 0)\r
+ #endif /* (CY_IP_USBDEV) */\r
+\r
+\r
+ #if (CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2)\r
+ #define CY_IP_IMO_TRIMMABLE_BY_WCO (0 == 0)\r
+ #else\r
+ #define CY_IP_IMO_TRIMMABLE_BY_WCO (0 != 0)\r
+ #endif /* (CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2) */\r
+\r
+\r
+ /* DW/DMA Controller present (0=No, 1=Yes) */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_IP_DMAC_PRESENT (-1 == 1)\r
+ #else\r
+ #define CY_IP_DMAC_PRESENT (-1 == 1)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
+ #else\r
+ #define CY_IP_DMAC_PRESENT (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #define CY_IP_PASS (0 == 1)\r
+ #else\r
+ #define CY_IP_PASS (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+\r
+\r
+ /* Number of external slave ports on System Interconnect */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_IP_SL_NR (-1)\r
+ #else\r
+ #define CY_IP_SL_NR (-1)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
+ #else\r
+ #define CY_IP_SL_NR (0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+#else\r
+\r
+ #if (CY_PSOC3)\r
+ #define CY_SYSTICK_LFCLK_SOURCE (0 != 0)\r
+ #else /* PSoC 5LP */\r
+ #define CY_SYSTICK_LFCLK_SOURCE (0 == 0)\r
+ #endif /* (CY_PSOC3) */\r
\r
#endif /* (CY_PSOC4) */\r
\r
* (defined(CY_BOOT_VERSION) && CY_BOOT_VERSION >= CY_BOOT_4_20)\r
*******************************************************************************/\r
#define CY_BOOT_4_20 (420u)\r
-#define CY_BOOT_VERSION (CY_BOOT_4_20)\r
+#define CY_BOOT_5_0 (500u)\r
+#define CY_BOOT_5_10 (510u)\r
+#define CY_BOOT_5_20 (520u)\r
+#define CY_BOOT_5_30 (530u)\r
+#define CY_BOOT_5_40 (540u)\r
+#define CY_BOOT_VERSION (CY_BOOT_5_40)\r
\r
\r
/*******************************************************************************\r
#endif /* (CY_PSOC3) */\r
\r
\r
-/*******************************************************************************\r
-* Register Access\r
-*******************************************************************************/\r
-#if(CY_PSOC3)\r
+#define CY_M_PI (3.14159265358979323846264338327)\r
+\r
+\r
+/**\r
+* \addtogroup group_register_access\r
+A library of macros provides read and write access to the registers of the device. These macros are used with the\r
+defined values made available in the generated cydevice_trm.h and cyfitter.h files. Access to registers should be made\r
+using these macros and not the functions that are used to implement the macros. This allows for device independent code\r
+generation.\r
+\r
+The PSoC 4 processor architecture use little endian ordering.\r
+\r
+SRAM and Flash storage in all architectures is done using the endianness of the architecture and compilers. However,\r
+the registers in all these chips are laid out in little endian order. These macros allow register accesses to match this\r
+little endian ordering. If you perform operations on multi-byte registers without using these macros, you must consider\r
+the byte ordering of the specific architecture. Examples include usage of DMA to transfer between memory and registers,\r
+as well as function calls that are passed an array of bytes in memory.\r
+\r
+The PSoC 4 requires these accesses to be aligned to the width of the transaction.\r
+\r
+The PSoC 4 requires peripheral register accesses to match the hardware register size. Otherwise, the peripheral might\r
+ignore the transfer and Hard Fault exception will be generated.\r
+\r
+*/\r
\r
+/** @} group_register_access */\r
\r
+\r
+/**\r
+* \addtogroup group_register_access_macros Register Access\r
+* \ingroup group_register_access\r
+* @{\r
+*/\r
+\r
+#if(CY_PSOC3)\r
/*******************************************************************************\r
- * KEIL for the 8051 is a big endian compiler This causes problems as the on chip\r
- * registers are little endian. Byte swapping for two and four byte registers is\r
- * implemented in the functions below. This will require conditional compilation\r
- * of function prototypes in the code.\r
+ * Macro Name: CY_GET_REG8(addr)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the 8-bit value from the specified register.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Read value.\r
+ *\r
*******************************************************************************/\r
+ #define CY_GET_REG8(addr) (*((const reg8 *)(addr)))\r
\r
- /* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */\r
\r
- #define CY_GET_REG8(addr) (*((const reg8 *)(addr)))\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_REG8(addr, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Writes the 8-bit value to the specified register.\r
+ *\r
+ * \param reg Register address.\r
+ * \param value Value to write.\r
+ *\r
+ *******************************************************************************/\r
#define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value))\r
\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_REG16(addr)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the 16-bit value from the specified register. This macro implements the\r
+ * byte swapping required for proper operation.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Read value.\r
+ *\r
+ *******************************************************************************/\r
#define CY_GET_REG16(addr) cyread16_nodpx ((const volatile void far *)(const reg16 *)(addr))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_REG16(addr, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Writes the 16-bit value to the specified register. This macro implements the\r
+ * byte swapping required for proper operation.\r
+ *\r
+ * \param reg Register address.\r
+ * \param value Value to write.\r
+ *\r
+ *******************************************************************************/\r
#define CY_SET_REG16(addr, value) cywrite16_nodpx((volatile void far *)(reg16 *)(addr), value)\r
\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_REG24(addr)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the 24-bit value from the specified register. This macro implements the\r
+ * byte swapping required for proper operation.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Read value.\r
+ *\r
+ *******************************************************************************/\r
#define CY_GET_REG24(addr) cyread24_nodpx ((const volatile void far *)(const reg32 *)(addr))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_REG24(addr, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Writes the 24-bit value to the specified register. This macro implements the\r
+ * byte swapping required for proper operation.\r
+ *\r
+ * \param reg Register address.\r
+ * \param value Value to write.\r
+ *\r
+ *******************************************************************************/\r
#define CY_SET_REG24(addr, value) cywrite24_nodpx((volatile void far *)(reg32 *)(addr),value)\r
\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_REG32(addr)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the 32-bit value from the specified register. This macro implements the\r
+ * byte swapping required for proper operation.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Read value.\r
+ *\r
+ *******************************************************************************/\r
#define CY_GET_REG32(addr) cyread32_nodpx ((const volatile void far *)(const reg32 *)(addr))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_REG32(addr, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Writes the 32-bit value to the specified register. This macro implements the\r
+ * byte swapping required for proper operation.\r
+ *\r
+ * \param reg Register address.\r
+ * \param value Value to write.\r
+ *\r
+ *******************************************************************************/\r
#define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value)\r
\r
- /* Access 8, 16, 24 and 32-bit registers, ABOVE THE FIRST 64K OF XDATA */\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_XTND_REG8(addr)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the 8-bit value from the specified register.\r
+ * Identical to \ref CY_GET_REG8 for PSoC 4.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Read value.\r
+ *\r
+ *******************************************************************************/\r
#define CY_GET_XTND_REG8(addr) cyread8((const volatile void far *)(addr))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_XTND_REG8(addr, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Writes the 8-bit value to the specified register.\r
+ * Identical to \ref CY_SET_REG8 for PSoC 4.\r
+ *\r
+ * \param reg Register address.\r
+ * \param value Value to write.\r
+ *\r
+ *******************************************************************************/\r
#define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value)\r
\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_XTND_REG16(addr)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the 16-bit value from the specified register. This macro implements the\r
+ * byte swapping required for proper operation. Identical to \ref CY_GET_REG16\r
+ * for PSoC 4.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Read value.\r
+ *\r
+ *******************************************************************************/\r
#define CY_GET_XTND_REG16(addr) cyread16((const volatile void far *)(addr))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_XTND_REG16(addr, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Writes the 16-bit value to the specified register. This macro implements the\r
+ * byte swapping required for proper operation. Identical to \ref CY_SET_REG16\r
+ * for PSoC 4.\r
+ *\r
+ * \param reg Register address.\r
+ * \param value Value to write.\r
+ *\r
+ *******************************************************************************/\r
#define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value)\r
\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_XTND_REG24(addr)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the 24-bit value from the specified register. This macro implements the\r
+ * byte swapping required for proper operation. Identical to \ref CY_GET_REG24\r
+ * for PSoC 4.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Read value.\r
+ *\r
+ *******************************************************************************/\r
#define CY_GET_XTND_REG24(addr) cyread24((const volatile void far *)(addr))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_XTND_REG24(addr, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Writes the 24-bit value to the specified register. This macro implements the\r
+ * byte swapping required for proper operation. Identical to \ref CY_SET_REG24\r
+ * for PSoC 4.\r
+ *\r
+ * \param reg Register address.\r
+ * \param value Value to write.\r
+ *\r
+ *******************************************************************************/\r
#define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value)\r
\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_XTND_REG32(addr)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the 32-bit value from the specified register. This macro implements the\r
+ * byte swapping required for proper operation. Identical to \ref CY_GET_REG32\r
+ * for PSoC 4.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Read value.\r
+ *\r
+ *******************************************************************************/\r
#define CY_GET_XTND_REG32(addr) cyread32((const volatile void far *)(addr))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_XTND_REG32(addr, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Writes the 32-bit value to the specified register. This macro implements the\r
+ * byte swapping required for proper operation. Identical to \ref CY_SET_REG32\r
+ * for PSoC 4.\r
+ *\r
+ * \param reg Register address.\r
+ * \param value Value to write.\r
+ *\r
+ *******************************************************************************/\r
#define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value)\r
\r
#else\r
\r
- /* 8, 16, 24 and 32-bit register access macros */\r
#define CY_GET_REG8(addr) (*((const reg8 *)(addr)))\r
#define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value))\r
\r
#define CY_GET_REG32(addr) (*((const reg32 *)(addr)))\r
#define CY_SET_REG32(addr, value) (*((reg32 *)(addr)) = (uint32)(value))\r
\r
-\r
/* To allow code to be 8051-ARM agnostic. */\r
#define CY_GET_XTND_REG8(addr) CY_GET_REG8(addr)\r
#define CY_SET_XTND_REG8(addr, value) CY_SET_REG8(addr, value)\r
#define CY_SET_XTND_REG32(addr, value) CY_SET_REG32(addr, value)\r
\r
#endif /* (CY_PSOC3) */\r
+/** @} group_register_access_macros */\r
+\r
+\r
+/**\r
+* \addtogroup group_register_access_bits Bit Manipulation\r
+* \ingroup group_register_access\r
+* @{\r
+*/\r
+\r
+#if(CY_PSOC4)\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_FIELD_MASK(regSize, bitFieldName)\r
+ ****************************************************************************//**\r
+ *\r
+ * Returns the bit field mask for the specified register size and bit field\r
+ * name.\r
+ *\r
+ * \param regSize Size of the register in bits.\r
+ * \param bitFieldName Fully qualified name of the bit field. The biFieldName\r
+ * is automatically appended with __OFFSET and __SIZE by the macro for usage.\r
+ *\r
+ * \return Returns the bit mask.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_GET_FIELD_MASK(regSize, bitFieldName) \\r
+ ((((uint ## regSize) 0xFFFFFFFFu << ((uint32)(regSize) - bitFieldName ## __SIZE - bitFieldName ## __OFFSET)) >>\\r
+ ((uint32)(regSize) - bitFieldName ## __SIZE)) << bitFieldName ## __OFFSET)\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_REG8_FIELD(registerName, bitFieldName)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the specified bit field value from the specified 8-bit register.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register will remain uncorrupted during simultaneous read-modify-write\r
+ * operation performed by two threads (main and interrupt threads). To\r
+ * guarantee data integrity in such cases, the macro should be invoked while\r
+ * the specific interrupt is disabled or within a critical section (all\r
+ * interrupts are disabled).\r
+ *\r
+ * Using this macro on 32-bit and 16-bit width registers will generate a\r
+ * hard fault exception. Examples of 8-bit registers are the UDB registers.\r
+ *\r
+ * \param registerName: The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName: fully qualified name of the bit field. The biFieldName is\r
+ * automatically appended with __OFFSET and __SIZE by the macro for usage.\r
+ *\r
+ * For fully qualified names of the register and bit fields and the possible\r
+ * values the field can take, please, refer to a respective PSoC family\r
+ * register TRM.\r
+ *\r
+ * \return Zero if the specified bit field is zero, and a non-zero value,\r
+ * otherwise. The return value is of type uint32.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_GET_REG8_FIELD(registerName, bitFieldName) \\r
+ ((CY_GET_REG8((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFu << bitFieldName ## __SIZE)))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_REG8_FIELD(registerName, bitFieldName, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Sets the specified bit field value of the specified 8-bit register to the\r
+ * required value.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write\r
+ * operation performed by two threads (main and interrupt threads). To\r
+ * guarantee data integrity in such cases, the macro should be invoked while\r
+ * the specific interrupt is disabled or within a critical section (all\r
+ * interrupts are disabled).\r
+ *\r
+ * Using this macro on the 32-bit and 16-bit width registers, generates a\r
+ * hard fault exception. Examples of 8-bit registers are the UDB registers.\r
+ *\r
+ * \param registerName The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName fully qualified name of the bit field. The biFieldName is\r
+ * automatically appended with __OFFSET and __SIZE by the macro for usage.\r
+ * \param value The value that the field must be configured for.\r
+ *\r
+ * For fully qualified names of the register and bit fields and the possible\r
+ * values the field can take, please, refer to a respective PSoC family\r
+ * register TRM.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_SET_REG8_FIELD(registerName, bitFieldName, value) \\r
+ CY_SET_REG8((registerName), \\r
+ ((CY_GET_REG8((registerName)) & ~CY_GET_FIELD_MASK(8, bitFieldName)) | \\r
+ (((uint8)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(8, bitFieldName))))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_CLEAR_REG8_FIELD(registerName, bitFieldName)\r
+ ****************************************************************************//**\r
+ *\r
+ * Clears the specified bit field of the specified 8-bit register.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write\r
+ * operation performed by two threads (main and interrupt threads). To\r
+ * guarantee data integrity in such cases, the macro should be invoked while\r
+ * the specific interrupt is disabled or within a critical section (all\r
+ * interrupts are disabled).\r
+ *\r
+ * Using this macro on the 32-bit and 16-bit width registers generates a\r
+ * hard fault exception. Examples of 8-bit registers are the UDB registers.\r
+ *\r
+ * \param registerName The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName fully qualified name of the bit field. The biFieldName is\r
+ * automatically appended with __OFFSET and __SIZE by the macro for usage.\r
+ *\r
+ * For fully qualified names of the register and bit fields and the\r
+ * possible values the field can take, please, refer to a respective PSoC\r
+ * family register TRM.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_CLEAR_REG8_FIELD(registerName, bitFieldName) \\r
+ (CY_SET_REG8((registerName), (CY_GET_REG8((registerName)) & ~CY_GET_FIELD_MASK(8, bitFieldName))))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_REG16_FIELD(registerName, bitFieldName)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the specified bit field value from the specified 16-bit register.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write\r
+ * operation performed by two threads (main and interrupt threads). To\r
+ * guarantee data integrity in such cases, the macro should be invoked while\r
+ * the specific interrupt is disabled or within a critical section (all\r
+ * interrupts are disabled).\r
+ *\r
+ * Using this macro on the 32-bit and 16-bit width registers generates a\r
+ * hardfault exception. Examples of 8-bit registers are the UDB registers.\r
+ *\r
+ * \param registerName The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName fully qualified name of the bit field. The biFieldName is\r
+ * automatically appended with __OFFSET and __SIZE by the macro for usage.\r
+ *\r
+ * For fully qualified names of the register and bit fields and the\r
+ * possible values the field can take, please, refer to a respective PSoC\r
+ * family register TRM.\r
+ *\r
+ * \return Zero if the specified bit field is zero, and a non-zero value,\r
+ * otherwise. The return value is of type uint32.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_GET_REG16_FIELD(registerName, bitFieldName) \\r
+ ((CY_GET_REG16((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFFFu << bitFieldName ## __SIZE)))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_REG16_FIELD(registerName, bitFieldName, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Sets the specified bit field value of the specified 16-bit register to the\r
+ * required value.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write operation\r
+ * performed by two threads (main and interrupt threads). To guarantee data\r
+ * integrity in such cases, the macro should be invoked while the specific\r
+ * interrupt is disabled or within a critical section (all interrupts are\r
+ * disabled).\r
+ *\r
+ * Using this macro on the 32-bit and 16-bit width registers generates a hard\r
+ * fault exception. Examples of 8-bit registers are the UDB registers.\r
+ *\r
+ * \param registerNam The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName: fully qualified name of the bit field. The biFieldName is\r
+ * automatically appended with __OFFSET and __SIZE by the macro for usage.\r
+ * \param value The value that the field must be configured for.\r
+ *\r
+ * For fully qualified names of the register and bit fields and the possible\r
+ * values the field can take, please, refer to a respective PSoC family\r
+ * register TRM.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_SET_REG16_FIELD(registerName, bitFieldName, value) \\r
+ CY_SET_REG16((registerName), \\r
+ ((CY_GET_REG16((registerName)) & ~CY_GET_FIELD_MASK(16, bitFieldName)) | \\r
+ (((uint16)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(16, bitFieldName))))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_CLEAR_REG16_FIELD(registerName, bitFieldName)\r
+ ****************************************************************************//**\r
+ *\r
+ * Clears the specified bit field of the specified 16-bit register.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write operation\r
+ * performed by two threads (main and interrupt threads). To guarantee data\r
+ * integrity in such cases, the macro should be invoked while the specific\r
+ * interrupt is disabled or within a critical section (all interrupts are\r
+ * disabled).\r
+ *\r
+ * Using this macro on the 32-bit and 16-bit width registers generates a hard\r
+ * fault exception. Examples of 8-bit registers are the UDB registers.\r
+ *\r
+ * \param registerName: The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName: fully qualified name of the bit field. The biFieldName is\r
+ * automatically appended with __OFFSET and __SIZE by the macro for usage.\r
+ *\r
+ * For fully qualified names of the register and bit fields and the possible\r
+ * values the field can take, please, refer to a respective PSoC family register\r
+ * TRM.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_CLEAR_REG16_FIELD(registerName, bitFieldName)\\r
+ (CY_SET_REG16((registerName), (CY_GET_REG16((registerName)) & ~CY_GET_FIELD_MASK(16, bitFieldName))))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_REG32_FIELD(registerName, bitFieldName)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the specified bit field value from the specified 32-bit register.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write operation\r
+ * performed by two threads (main and interrupt threads). To guarantee data\r
+ * integrity in such cases, the macro should be invoked while the specific\r
+ * interrupt is disabled or within a critical section (all interrupts are\r
+ * disabled).\r
+ *\r
+ * Using this macro on the 16-bit and 8-bit width registers generates a hard\r
+ * fault exception.\r
+ *\r
+ * \param registerName The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName The Fully qualified name of the bit field. The\r
+ * biFieldName is automatically appended with __OFFSET and __SIZE by the macro\r
+ * for usage.\r
+ *\r
+ * For fully qualified names of the register and bit fields, please, refer to\r
+ * a respective PSoC family register TRM.\r
+ *\r
+ * \return Zero if the specified bit field is zero, and a non-zero value, otherwise.\r
+ * The return value is of type uint32.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_GET_REG32_FIELD(registerName, bitFieldName) \\r
+ ((CY_GET_REG32((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFFFFFFFu << bitFieldName ## __SIZE)))\r
+\r
\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_REG32_FIELD(registerName, bitFieldName, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Sets the specified bit field value of the specified 32-bit register to the\r
+ * required value.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write operation\r
+ * performed by two threads (main and interrupt threads). To guarantee data\r
+ * integrity in such cases, the macro should be invoked while the specific\r
+ * interrupt is disabled or within a critical section (all interrupts are\r
+ * disabled).\r
+ *\r
+ * Using this macro on the 16-bit and 8-bit width registers generates a hard\r
+ * fault exception.\r
+ *\r
+ * \param registerName The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName The fully qualified name of the bit field. The\r
+ * biFieldName is automatically appended with __OFFSET and __SIZE by the macro\r
+ * for usage.\r
+ * \param value The value that the field must be configured for.\r
+ *\r
+ * For fully qualified names of the register and bit fields and the possible\r
+ * values the field can take, please, refer to a respective PSoC family register\r
+ * TRM.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_SET_REG32_FIELD(registerName, bitFieldName, value) \\r
+ CY_SET_REG32((registerName), \\r
+ ((CY_GET_REG32((registerName)) & ~CY_GET_FIELD_MASK(32, bitFieldName)) | \\r
+ (((uint32)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(32, bitFieldName))))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_CLEAR_REG32_FIELD(registerName, bitFieldName)\r
+ ****************************************************************************//**\r
+ *\r
+ * Clears the specified bit field of the specified 32-bit register.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write operation\r
+ * performed by two threads (main and interrupt threads). To guarantee data\r
+ * integrity in such cases, the macro should be invoked while the specific\r
+ * interrupt is disabled or within a critical section (all interrupts are\r
+ * disabled).\r
+ *\r
+ * Using this macro on the 16-bit and 8-bit width registers generates a hard\r
+ * fault exception.\r
+ *\r
+ * \param registerName The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName The fully qualified name of the bit field. The\r
+ * biFieldName is automatically appended with __OFFSET and __SIZE by the macro\r
+ * for usage.\r
+ *\r
+ * For fully qualified names of the register and bit fields and the possible\r
+ * values the field can take, please, refer to a respective PSoC family register\r
+ * TRM.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_CLEAR_REG32_FIELD(registerName, bitFieldName) \\r
+ (CY_SET_REG32((registerName), (CY_GET_REG32((registerName)) & ~CY_GET_FIELD_MASK(32, bitFieldName))))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_FIELD(regValue, bitFieldName)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the specified bit field value from the given 32-bit value.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write operation\r
+ * performed by two threads (main and interrupt threads). To guarantee data\r
+ * integrity in such cases, the macro should be invoked while the specific\r
+ * interrupt is disabled or within a critical section (all interrupts are\r
+ * disabled).\r
+ *\r
+ * This macro has to be used in conjunction with \ref CY_GET_REG32 for atomic\r
+ * reads.\r
+ *\r
+ * \param regValue The value as read by \ref CY_GET_REG32.\r
+ * \param bitFieldName The fully qualified name of the bit field. The\r
+ * biFieldName is automatically appended with __OFFSET and __SIZE by the macro\r
+ * for usage.\r
+ *\r
+ * For fully qualified names of the bit field and the possible values the field\r
+ * can take, please, refer to a respective PSoC family register TRM.\r
+ *\r
+ * \return Zero if the specified bit field is zero, and a non-zero value,\r
+ * otherwise. The return value is of type uint32.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_GET_FIELD(regValue, bitFieldName) \\r
+ (((regValue) >> bitFieldName ## __OFFSET) & (~(0xFFFFFFFFu << bitFieldName ## __SIZE)))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_FIELD(regValue, bitFieldName, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Sets the specified bit field value within a given 32-bit value.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write operation\r
+ * performed by two threads (main and interrupt threads). To guarantee data\r
+ * integrity in such cases, the macro should be invoked while the specific\r
+ * interrupt is disabled or within a critical section (all interrupts are\r
+ * disabled).\r
+ *\r
+ * This macro has to be used in conjunction with \ref CY_GET_REG32 for atomic\r
+ * reads and \ref CY_SET_REG32 for atomic writes.\r
+ *\r
+ * \param regValue The value as read by \ref CY_GET_REG32.\r
+ * \param bitFieldName The fully qualified name of the bit field. The\r
+ * biFieldName is automatically appended with __OFFSET and __SIZE by the macro\r
+ * for usage.\r
+ * \param value The value that the field must be configured for.\r
+ *\r
+ * For fully qualified names of the bit field and the possible values the field\r
+ * can take, please, refer to the respective PSoC family register TRM.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_SET_FIELD(regValue, bitFieldName, value) \\r
+ ((regValue) = \\r
+ ((((uint32)(value) & (~(0xFFFFFFu << bitFieldName ## __SIZE))) << bitFieldName ## __OFFSET)) | \\r
+ ((uint32)(regValue) & (((~(0xFFu << bitFieldName ## __SIZE))) << bitFieldName ## __OFFSET)))\r
+\r
+#endif /* (CY_PSOC4) */\r
+\r
+/** @} group_register_access_bits */\r
\r
\r
/*******************************************************************************\r
\r
/* Swap the byte ordering of 32 bit value */\r
#define CYSWAP_ENDIAN32(x) \\r
- ((uint32)(((x) >> 24) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24)))\r
+ ((uint32)((((x) >> 24) & 0x000000FFu) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24)))\r
\r
/* Swap the byte ordering of 16 bit value */\r
-#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | ((x) >> 8)))\r
+#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | (((x) >> 8) & 0x00FFu)))\r
\r
\r
/*******************************************************************************\r
\r
\r
/*******************************************************************************\r
-* The following code is OBSOLETE and must not be used starting from cy_boot 3.10\r
+* The following code is OBSOLETE and must not be used starting from cy_boot 5.10\r
*\r
* If the obsoleted macro definitions intended for use in the application use the\r
* following scheme, redefine your own versions of these definitions:\r
* used in the application and their modification might lead to unexpected\r
* consequences.\r
*******************************************************************************/\r
+#define CY_IP_S8FS CY_IP_FS\r
+\r
+\r
+/*******************************************************************************\r
+* The following code is OBSOLETE and must not be used starting from cy_boot 3.10\r
+*******************************************************************************/\r
#define CY_UDB_V0 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)\r
#define CY_UDB_V1 (!CY_UDB_V0)\r
#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)\r
-/*******************************************************************************\r
-* FILENAME: cyutils.c\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file cyutils.c\r
+* \version 5.50\r
*\r
-* Description:\r
-* CyUtils provides a function to handle 24-bit value writes.\r
+* \brief Provides a function to handle 24-bit value writes.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
/***************************************************************************\r
* Function Name: CySetReg24\r
- ****************************************************************************\r
+ ************************************************************************//**\r
*\r
- * Summary:\r
- * Writes a 24-bit value to the specified register.\r
+ * Writes a 24-bit value to the specified register.\r
*\r
- * Parameters:\r
- * addr : the address where data must be written.\r
- * value: the data that must be written.\r
- *\r
- * Return:\r
- * None\r
+ * \param add The address where data must be written.\r
+ * \param value The data that must be written.\r
*\r
* Reentrant:\r
* No\r
\r
/***************************************************************************\r
* Function Name: CyGetReg24\r
- ****************************************************************************\r
+ ************************************************************************//**\r
*\r
- * Summary:\r
* Reads the 24-bit value from the specified register.\r
*\r
- * Parameters:\r
- * addr : the address where data must be read.\r
- *\r
- * Return:\r
- * None\r
+ * \param addr : the address where data must be read.\r
*\r
* Reentrant:\r
* No\r
/*******************************************************************************\r
* File Name: project.h\r
* \r
-* PSoC Creator 3.3\r
+* PSoC Creator 4.0 Update 1\r
*\r
* Description:\r
* It contains references to all generated header files and should not be modified.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "USBFS_hid.h"\r
#include "USBFS_midi.h"\r
#include "USBFS_pvt.h"\r
+#include "USBFS_cydmac.h"\r
+#include "USBFS_msc.h"\r
#include "Bootloadable_1.h"\r
#include "SCSI_Out_Bits.h"\r
#include "SCSI_Out_Ctl.h"\r
#include "USBFS_Dp_aliases.h"\r
#include "USBFS_Dp.h"\r
#include "core_cm3_psoc5.h"\r
-#include "core_cm3.h"\r
#include "CyDmac.h"\r
#include "CyFlash.h"\r
#include "CyLib.h"\r
#include "cyPm.h"\r
#include "CySpc.h"\r
#include "cytypes.h"\r
-#include "core_cmFunc.h"\r
-#include "core_cmInstr.h"\r
\r
/*[]*/\r
\r
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG" hidden="false">\r
- <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />\r
+ <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." hidden="false" />\r
</register>\r
<register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0" hidden="false">\r
- <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />\r
- <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">\r
+ <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." hidden="false" />\r
+ <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)" hidden="false">\r
<value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />\r
<value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />\r
</field>\r
- <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />\r
- <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />\r
- <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />\r
- <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">\r
+ <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." hidden="false" />\r
+ <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." hidden="false" />\r
+ <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" hidden="false" />\r
+ <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively." hidden="false">\r
<value name="Timer" value="0" desc="CMP and TC are output." />\r
<value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />\r
</field>\r
- <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />\r
+ <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" hidden="false" />\r
</register>\r
<register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1" hidden="false">\r
- <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />\r
- <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">\r
+ <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" hidden="false" />\r
+ <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled." hidden="false">\r
<value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />\r
<value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />\r
</field>\r
- <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />\r
- <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />\r
- <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />\r
- <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />\r
+ <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." hidden="false" />\r
+ <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." hidden="false" />\r
+ <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." hidden="false" />\r
+ <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." hidden="false" />\r
</register>\r
<register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2" hidden="false">\r
- <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">\r
+ <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ" hidden="false">\r
<value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />\r
<value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />\r
<value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />\r
<value name="Irq" value="11" desc="Timer runs until IRQ." />\r
</field>\r
- <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />\r
- <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />\r
- <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">\r
+ <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." hidden="false" />\r
+ <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" hidden="false" />\r
+ <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations" hidden="false">\r
<value name="Equal" value="0" desc="Compare Equal " />\r
<value name="Less than" value="1" desc="Compare Less Than " />\r
<value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />\r
<value name="Greater" value="11" desc="Compare Greater Than ." />\r
<value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />\r
</field>\r
- <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />\r
+ <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." hidden="false" />\r
</register>\r
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />\r
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />\r
</block>\r
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006477" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006579" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Filtered_STATUS_REG" address="0x40006465" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Filtered_MASK_REG" address="0x40006485" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="" hidden="false">\r
- <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
+ <register name="SCSI_Filtered_STATUS_REG" address="0x4000646C" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Filtered_MASK_REG" address="0x4000648C" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649C" bitWidth="8" desc="" hidden="false">\r
+ <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
</field>\r
- <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">\r
+ <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt" hidden="false">\r
<value name="ENABLED" value="1" desc="Interrupt enabled" />\r
<value name="DISABLED" value="0" desc="Interrupt disabled" />\r
</field>\r
- <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">\r
+ <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level" hidden="false">\r
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
</field>\r
- <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">\r
+ <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level" hidden="false">\r
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
</field>\r
- <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">\r
+ <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear" hidden="false">\r
<value name="ENABLED" value="1" desc="Clear FIFO state" />\r
<value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
</field>\r
- <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">\r
+ <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear" hidden="false">\r
<value name="ENABLED" value="1" desc="Clear FIFO state" />\r
<value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
</field>\r
</register>\r
</block>\r
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006466" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_MASK_REG" address="0x40006486" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006496" bitWidth="8" desc="" hidden="false">\r
- <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006567" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x40006587" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006597" bitWidth="8" desc="" hidden="false">\r
+ <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
</field>\r
- <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">\r
+ <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt" hidden="false">\r
<value name="ENABLED" value="1" desc="Interrupt enabled" />\r
<value name="DISABLED" value="0" desc="Interrupt disabled" />\r
</field>\r
- <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">\r
+ <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level" hidden="false">\r
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
</field>\r
- <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">\r
+ <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level" hidden="false">\r
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
</field>\r
- <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">\r
+ <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear" hidden="false">\r
<value name="ENABLED" value="1" desc="Clear FIFO state" />\r
<value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
</field>\r
- <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">\r
+ <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear" hidden="false">\r
<value name="ENABLED" value="1" desc="Clear FIFO state" />\r
<value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
</field>\r
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true" hidden="false">\r
- <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="ZeroTerminal_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="ZeroTerminal_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0" hidden="false">\r
- <field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />\r
- <field name="fsusbio_pd_n" from="1" to="1" access="RW" resetVal="" desc="" />\r
- <field name="fsusbio_pd_pullup_n" from="2" to="2" access="RW" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_PM_ACT_CFG" address="0x400043A5" bitWidth="8" desc="Active Power Mode Configuration Register" hidden="false" />\r
- <register name="USBFS_PM_STBY_CFG" address="0x400043B5" bitWidth="8" desc="Standby Power Mode Configuration Register" hidden="false" />\r
- <register name="USBFS_PRT.PS" address="0x400051F1" bitWidth="8" desc="Port Pin State Register" hidden="false">\r
- <field name="PinState_DP" from="6" to="6" access="R" resetVal="" desc="" />\r
- <field name="PinState_DM" from="7" to="7" access="R" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_PRT_DM0" address="0x400051F2" bitWidth="8" desc="Port Drive Mode Register" hidden="false">\r
- <field name="DriveMode_DP" from="6" to="6" access="RW" resetVal="" desc="" />\r
- <field name="DriveMode_DM" from="7" to="7" access="RW" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_PRT_DM1" address="0x400051F3" bitWidth="8" desc="Port Drive Mode Register" hidden="false">\r
- <field name="PullUp_en_DP" from="6" to="6" access="RW" resetVal="" desc="" />\r
- <field name="PullUp_en_DM" from="7" to="7" access="RW" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_PRT.INP_DIS" address="0x400051F8" bitWidth="8" desc="Input buffer disable override" hidden="false">\r
- <field name="seinput_dis_dp" from="6" to="6" access="RW" resetVal="" desc="" />\r
- <field name="seinput_dis_dm" from="7" to="7" access="RW" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_EP0_DR0" address="0x40006000" bitWidth="8" desc="bmRequestType" hidden="false" />\r
- <register name="USBFS_EP0_DR1" address="0x40006001" bitWidth="8" desc="bRequest" hidden="false" />\r
- <register name="USBFS_EP0_DR2" address="0x40006002" bitWidth="8" desc="wValueLo" hidden="false" />\r
- <register name="USBFS_EP0_DR3" address="0x40006003" bitWidth="8" desc="wValueHi" hidden="false" />\r
- <register name="USBFS_EP0_DR4" address="0x40006004" bitWidth="8" desc="wIndexLo" hidden="false" />\r
- <register name="USBFS_EP0_DR5" address="0x40006005" bitWidth="8" desc="wIndexHi" hidden="false" />\r
- <register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" hidden="false" />\r
- <register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" hidden="false" />\r
- <register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0" hidden="false">\r
- <field name="device_address" from="6" to="0" access="R" resetVal="" desc="" />\r
- <field name="usb_enable" from="7" to="7" access="RW" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1" hidden="false">\r
- <field name="reg_enable" from="0" to="0" access="RW" resetVal="" desc="" />\r
- <field name="enable_lock" from="1" to="1" access="RW" resetVal="" desc="" />\r
- <field name="bus_activity" from="2" to="2" access="RW" resetVal="" desc="" />\r
- <field name="trim_offset_msb" from="3" to="3" access="RW" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_SIE_EP1_CR0" address="0x4000600E" bitWidth="8" desc="The Endpoint1 Control Register" hidden="false" />\r
- <register name="USBFS_USBIO_CR0" address="0x40006010" bitWidth="8" desc="USBIO Control Register 0" hidden="false">\r
- <field name="rd" from="0" to="0" access="R" resetVal="" desc="" />\r
- <field name="td" from="5" to="5" access="RW" resetVal="" desc="" />\r
- <field name="tse0" from="6" to="6" access="RW" resetVal="" desc="" />\r
- <field name="ten" from="7" to="7" access="RW" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_USBIO_CR1" address="0x40006012" bitWidth="8" desc="USBIO Control Register 1" hidden="false">\r
- <field name="dmo" from="0" to="0" access="R" resetVal="" desc="" />\r
- <field name="dpo" from="1" to="1" access="R" resetVal="" desc="" />\r
- <field name="usbpuen" from="2" to="2" access="RW" resetVal="" desc="" />\r
- <field name="iomode" from="5" to="5" access="RW" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_SIE_EP2_CR0" address="0x4000601E" bitWidth="8" desc="The Endpoint2 Control Register" hidden="false" />\r
- <register name="USBFS_SIE_EP3_CR0" address="0x4000602E" bitWidth="8" desc="The Endpoint3 Control Register" hidden="false" />\r
- <register name="USBFS_SIE_EP4_CR0" address="0x4000603E" bitWidth="8" desc="The Endpoint4 Control Register" hidden="false" />\r
- <register name="USBFS_SIE_EP5_CR0" address="0x4000604E" bitWidth="8" desc="The Endpoint5 Control Register" hidden="false" />\r
- <register name="USBFS_SIE_EP6_CR0" address="0x4000605E" bitWidth="8" desc="The Endpoint6 Control Register" hidden="false" />\r
- <register name="USBFS_SIE_EP7_CR0" address="0x4000606E" bitWidth="8" desc="The Endpoint7 Control Register" hidden="false" />\r
- <register name="USBFS_SIE_EP8_CR0" address="0x4000607E" bitWidth="8" desc="The Endpoint8 Control Register" hidden="false" />\r
- <register name="USBFS_BUF_SIZE" address="0x4000608C" bitWidth="8" desc="Dedicated Endpoint Buffer Size Register" hidden="false" />\r
- <register name="USBFS_EP_ACTIVE" address="0x4000608E" bitWidth="8" desc="Endpoint Active Indication Register" hidden="false" />\r
- <register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" hidden="false" />\r
- <register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" hidden="false" />\r
+ <block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <register name="POWER_CTRL" address="0x40006008" bitWidth="32" desc="Power Control Register" hidden="true">\r
+ <field name="VBUS_VALID_OVR" from="1" to="0" access="RW" resetVal="" desc="Overrides the value received from the GPIO input buffer connected to VBUS" hidden="false">\r
+ <value name="FORCE_VALID_0" value="00" desc="Force vbus_valid = 0." />\r
+ <value name="FORCE_VALID_1" value="01" desc="Force vbus_valid = 1." />\r
+ <value name="GPIO_VALID" value="10" desc="Use vbus_valid signal from GPIO input." />\r
+ <value name="PHY_VALID" value="11" desc="Use vbus_valid signal from PHY detector." />\r
+ </field>\r
+ <field name="SUSPEND" from="2" to="2" access="RW" resetVal="" desc="Put PHY into Suspend mode. If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep/Hibernate)." hidden="false" />\r
+ <field name="SUSPEND_DEL" from="3" to="3" access="RW" resetVal="" desc="Delayed version of SUSPEND. Always set SUSPEND and SUSPEND_DEL together in a single register write. When taking PHY out of suspend mode, first clear SUSPEND, then clear SUSPEND_DEL at least 2us later." hidden="false" />\r
+ <field name="ISOLATE" from="4" to="4" access="RW" resetVal="" desc="Isolates the PHY outputs. Clear this bit at least 2us after vbus is known to be valid (vbus_valid=1). Isolation will be forced when vbus_valid goes low (see VBUS_VALID_OVR)." hidden="false" />\r
+ <field name="CHDET_PWR_CTL" from="6" to="5" access="RW" resetVal="" desc="Power programmability for bandgap voltage buffer in the charger detect block. See s8bg_vrefbuf public cell for more information. Default '0' is low power mode." hidden="false" />\r
+ <field name="ENABLE_DM_PULLDOWN" from="26" to="26" access="RW" resetVal="" desc="Enables the ~15k pull down on the DM, default off. The 15k pull down is needed for Data Contact Detection (DCD)." hidden="false" />\r
+ <field name="ENABLE_VBUS_PULLDOWN" from="26" to="26" access="RW" resetVal="" desc="Enables the weak pull down on the VBUS, default on, to prevent floating node crow bar currents." hidden="false" />\r
+ <field name="ENABLE_RCVR" from="27" to="27" access="RW" resetVal="" desc="Enables the differential USB receiver." hidden="false" />\r
+ <field name="ENABLE_DPO" from="28" to="28" access="RW" resetVal="" desc="Enables the single ended receiver on D+." hidden="false" />\r
+ <field name="ENABLE_DMO" from="29" to="29" access="RW" resetVal="" desc="Enables the signle ended receiver on D-." hidden="false" />\r
+ <field name="ENABLE_CHGDET" from="30" to="30" access="RW" resetVal="" desc="Enables the charger detection circuitry. After USB has connected, this circuitry can be disabled to save power." hidden="false" />\r
+ <field name="ENABLE" from="31" to="31" access="RW" resetVal="" desc="Mast enable of PHY and Charger Detector. Nothing will work until this bit is set." hidden="false" />\r
+ </register>\r
+ <register name="CR0" address="0x40006008" bitWidth="8" desc="USB Control 0 Register" hidden="false">\r
+ <field name="DEVICE_ADDRESS" from="6" to="0" access="R" resetVal="" desc="These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware." hidden="false" />\r
+ <field name="USB_ENABLE" from="7" to="7" access="RW" resetVal="" desc="This bit enables the device to respond to USB traffic." hidden="false">\r
+ <value name="Disabled" value="0" desc="Block responds to USB traffic." />\r
+ <value name="Enabled" value="1" desc="Block does not respond to USB traffic." />\r
+ </field>\r
+ </register>\r
+ <register name="INTR_CAUSE_HIGH" address="0x40006008" bitWidth="32" desc="High priority interrupt Cause register" hidden="true">\r
+ <field name="SOF_INTR" from="0" to="0" access="RW" resetVal="" desc="USB SOF Interrupt." hidden="false" />\r
+ <field name="BUS_RESET_INTR" from="1" to="1" access="RW" resetVal="" desc="BUS RESET Interrupt." hidden="false" />\r
+ <field name="EP0_INTR" from="2" to="2" access="RW" resetVal="" desc="EP0 Interrupt." hidden="false" />\r
+ <field name="LPM_INTR" from="3" to="3" access="RW" resetVal="" desc="LPM Interrupt." hidden="false" />\r
+ <field name="RESUME_INTR" from="4" to="4" access="RW" resetVal="" desc="Resume Interrupt." hidden="false" />\r
+ <field name="ARB_EP_INTR" from="7" to="7" access="RW" resetVal="" desc="Arbiter Endpoint Interrupt." hidden="false" />\r
+ <field name="EP1_INTR" from="8" to="8" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP2_INTR" from="9" to="9" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP3_INTR" from="10" to="10" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP4_INTR" from="11" to="11" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP5_INTR" from="12" to="12" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP6_INTR" from="13" to="13" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP7_INTR" from="14" to="14" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP8_INTR" from="15" to="15" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ </register>\r
+ <register name="LPM_STAT" address="0x40006008" bitWidth="32" desc="LPM Status register" hidden="true">\r
+ <field name="LPM_BESL" from="3" to="0" access="RW" resetVal="" desc="Best Effort Service Latency. This value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor." hidden="false" />\r
+ <field name="LPM_REMOTEWAKE" from="4" to="4" access="RW" resetVal="" desc="LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request." hidden="false">\r
+ <value name="Prohibited" value="0" desc="Device is prohibited from initiating a remote wake." />\r
+ <value name="Allowed" value="1" desc="Device is allow to wake the host." />\r
+ </field>\r
+ </register>\r
+ <register name="INTR_LVL_SEL" address="0x40006008" bitWidth="32" desc="Select interrupt level for each interrupt source" hidden="true">\r
+ <field name="SOF_LVL_SEL" from="1" to="0" access="RW" resetVal="" desc="USB SOF Interrupt level select." hidden="false" />\r
+ <field name="BUS_RESET_LVL_SEL" from="3" to="2" access="RW" resetVal="" desc="BUS RESET Interrupt level select." hidden="false" />\r
+ <field name="EP0_LVL_SEL" from="5" to="4" access="RW" resetVal="" desc="EP0 Interrupt level select." hidden="false" />\r
+ <field name="LPM_LVL_SEL" from="7" to="6" access="RW" resetVal="" desc="LPM Interrupt level select." hidden="false" />\r
+ <field name="RESUME_LVL_SEL" from="9" to="8" access="RW" resetVal="" desc="Resume Interrupt level select." hidden="false" />\r
+ <field name="ARB_EP_LVL_SEL" from="15" to="14" access="RW" resetVal="" desc="Arbiter Endpoint Interrupt level select." hidden="false" />\r
+ <field name="EP1_LVL_SEL" from="17" to="16" access="RW" resetVal="" desc="EP1 Interrupt level select." hidden="false" />\r
+ <field name="EP2_LVL_SEL" from="19" to="18" access="RW" resetVal="" desc="EP2 Interrupt level select." hidden="false" />\r
+ <field name="EP3_LVL_SEL" from="21" to="20" access="RW" resetVal="" desc="EP3 Interrupt level select." hidden="false" />\r
+ <field name="EP4_LVL_SEL" from="23" to="22" access="RW" resetVal="" desc="EP4 Interrupt level select." hidden="false" />\r
+ <field name="EP5_LVL_SEL" from="25" to="24" access="RW" resetVal="" desc="EP5 Interrupt level select." hidden="false" />\r
+ <field name="EP6_LVL_SEL" from="27" to="26" access="RW" resetVal="" desc="EP6 Interrupt level select." hidden="false" />\r
+ <field name="EP7_LVL_SEL" from="29" to="28" access="RW" resetVal="" desc="EP7 Interrupt level select." hidden="false" />\r
+ <field name="EP8_LVL_SEL" from="31" to="30" access="RW" resetVal="" desc="EP8 Interrupt level select." hidden="false" />\r
+ </register>\r
+ <register name="CHGDET_CTRL" address="0x40006008" bitWidth="32" desc="Charger Detection Control Register" hidden="true">\r
+ <field name="COMP_DP" from="0" to="0" access="RW" resetVal="" desc="Connect the primary/secondary detection comparator and current sink to D+." hidden="false" />\r
+ <field name="COMP_DM" from="1" to="1" access="RW" resetVal="" desc="Connect the primary/secondary detection comparator and current sink to D-." hidden="false" />\r
+ <field name="COMP_EN" from="2" to="2" access="RW" resetVal="" desc="Enable the primary/secondary detection comparator and current sink. This bit can be written concurrently with COMP_DP/COMP_DM. Note that REF_EN must also be 1 for the comparator to work (because it receives a reference from it)." hidden="false" />\r
+ <field name="REF_DP" from="3" to="3" access="RW" resetVal="" desc="Connect the primary/secondary detection reference driver to D+." hidden="false" />\r
+ <field name="REF_DM" from="4" to="4" access="RW" resetVal="" desc="Connect the primary/secondary detection reference driver to D-." hidden="false" />\r
+ <field name="REF_EN" from="5" to="5" access="RW" resetVal="" desc="Enable the primary/secondary reference driver. This bit can be written concurrently with REF_DP/REF_DM." hidden="false" />\r
+ <field name="DCD_SRC_EN" from="6" to="6" access="RW" resetVal="" desc="Enable the Data Contact Detect current source on D+." hidden="false" />\r
+ <field name="ADFT_CTRL" from="13" to="12" access="RW" resetVal="" desc="ADFT option to bring out buffered version of voltage reference input or adft intput to ADFT output (adft_out)." hidden="false">\r
+ <value name="ADFT_NORMAL" value="00" desc="Normal operating mode, reference buffer used to generate internal references. adft_out pulled low." />\r
+ <value name="ADFT_VBG" value="01" desc="Use reference buffer to bring out voltage reference input (vbg) onto adft_out." />\r
+ <value name="ADFT_DONTUSE" value="10" desc="Illegal - do not use." />\r
+ <value name="ADFT_ADFTIN" value="11" desc="Use reference buffer to bring out buffered version of system level adft input (adft_in) onto adft_out." />\r
+ </field>\r
+ <field name="COMP_OUT" from="31" to="31" access="RW" resetVal="" desc="Output of the primary/secondary detection comparator. This output is not filtered or debounced and must be polled in software." hidden="false" />\r
+ </register>\r
+ <register name="LPM_CTRL" address="0x40006008" bitWidth="32" desc="LPM Control Register" hidden="true">\r
+ <field name="LPM_EN" from="0" to="0" access="RW" resetVal="" desc="LPM enable." hidden="false">\r
+ <value name="Disable" value="0" desc="LPM token will not get a response (backward compatibility mode)." />\r
+ <value name="Enable" value="1" desc="LPM token will get a handshake response (ACK, STALL, NYET or NAK). A STALL will be sent if the bLinkState is not 0001b. A NYET, NAK or ACK response will be sent depending on the NYET_EN and LPM_ACK_RESP bits below." />\r
+ </field>\r
+ <field name="LPM_ACK_RESP" from="1" to="1" access="RW" resetVal="" desc="LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request." hidden="false">\r
+ <value name="NYET_NACK" value="0" desc="A LPM token will get a NYET or NAK (depending on NYET_EN bit below) response and the device will NOT go to a low power mode." />\r
+ <value name="ACK" value="1" desc="A LPM token will get an ACK response and the device will go to the requested low power mode." />\r
+ </field>\r
+ <field name="NYET_EN" from="2" to="2" access="RW" resetVal="" desc="Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0)." hidden="false">\r
+ <value name="NYET" value="0" desc="A LPM token will get an NAK response (indicating a CRC error), the host is expected to repeat the LPM token." />\r
+ <value name="NACK" value="1" desc="A LPM token will get a NYET response." />\r
+ </field>\r
+ <field name="SUB_RESP" from="4" to="4" access="RW" resetVal="" desc="Enable a STALL response for all undefined SubPIDs, i.e. other than LPM (0011b). If not enabled then there will be no response (Error) for the undefined SubPIDs." hidden="false" />\r
+ </register>\r
+ <register name="INTR_SIE_MASK" address="0x40006008" bitWidth="32" desc="USB SOF, BUS RESET and EP0 Interrupt Mask" hidden="true">\r
+ <field name="SOF_INTR" from="0" to="0" access="RW" resetVal="" desc="USB SOF Interrupt." hidden="false" />\r
+ <field name="BUS_RESET_INTR" from="1" to="1" access="RW" resetVal="" desc="BUS RESET Interrupt." hidden="false" />\r
+ <field name="EP0_INTR" from="2" to="2" access="RW" resetVal="" desc="EP0 Interrupt." hidden="false" />\r
+ <field name="LPM_INTR" from="3" to="3" access="RW" resetVal="" desc="LPM Interrupt." hidden="false" />\r
+ <field name="RESUME_INTR" from="4" to="4" access="RW" resetVal="" desc="Resume Interrupt." hidden="false" />\r
+ </register>\r
+ <register name="INTR_CAUSE_LO" address="0x40006008" bitWidth="32" desc="Low priority interrupt Cause register" hidden="true">\r
+ <field name="SOF_INTR" from="0" to="0" access="RW" resetVal="" desc="USB SOF Interrupt." hidden="false" />\r
+ <field name="BUS_RESET_INTR" from="1" to="1" access="RW" resetVal="" desc="BUS RESET Interrupt." hidden="false" />\r
+ <field name="EP0_INTR" from="2" to="2" access="RW" resetVal="" desc="EP0 Interrupt." hidden="false" />\r
+ <field name="LPM_INTR" from="3" to="3" access="RW" resetVal="" desc="LPM Interrupt." hidden="false" />\r
+ <field name="RESUME_INTR" from="4" to="4" access="RW" resetVal="" desc="Resume Interrupt." hidden="false" />\r
+ <field name="ARB_EP_INTR" from="7" to="7" access="RW" resetVal="" desc="Arbiter Endpoint Interrupt." hidden="false" />\r
+ <field name="EP1_INTR" from="8" to="8" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP2_INTR" from="9" to="9" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP3_INTR" from="10" to="10" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP4_INTR" from="11" to="11" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP5_INTR" from="12" to="12" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP6_INTR" from="13" to="13" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP7_INTR" from="14" to="14" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP8_INTR" from="15" to="15" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ </register>\r
+ <register name="INTR_CAUSE_MED" address="0x40006008" bitWidth="32" desc="Medium priority interrupt Cause register" hidden="true">\r
+ <field name="SOF_INTR" from="0" to="0" access="RW" resetVal="" desc="USB SOF Interrupt." hidden="false" />\r
+ <field name="BUS_RESET_INTR" from="1" to="1" access="RW" resetVal="" desc="BUS RESET Interrupt." hidden="false" />\r
+ <field name="EP0_INTR" from="2" to="2" access="RW" resetVal="" desc="EP0 Interrupt." hidden="false" />\r
+ <field name="LPM_INTR" from="3" to="3" access="RW" resetVal="" desc="LPM Interrupt." hidden="false" />\r
+ <field name="RESUME_INTR" from="4" to="4" access="RW" resetVal="" desc="Resume Interrupt." hidden="false" />\r
+ <field name="ARB_EP_INTR" from="7" to="7" access="RW" resetVal="" desc="Arbiter Endpoint Interrupt." hidden="false" />\r
+ <field name="EP1_INTR" from="8" to="8" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP2_INTR" from="9" to="9" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP3_INTR" from="10" to="10" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP4_INTR" from="11" to="11" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP5_INTR" from="12" to="12" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP6_INTR" from="13" to="13" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP7_INTR" from="14" to="14" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP8_INTR" from="15" to="15" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ </register>\r
+ <register name="`INTR_SIE" address="0x40006008" bitWidth="32" desc="USB SOF, BUS RESET and EP0 Interrupt Status" hidden="true">\r
+ <field name="SOF_INTR" from="0" to="0" access="RW" resetVal="" desc="USB SOF Interrupt." hidden="false" />\r
+ <field name="BUS_RESET_INTR" from="1" to="1" access="RW" resetVal="" desc="BUS RESET Interrupt." hidden="false" />\r
+ <field name="EP0_INTR" from="2" to="2" access="RW" resetVal="" desc="EP0 Interrupt." hidden="false" />\r
+ <field name="LPM_INTR" from="3" to="3" access="RW" resetVal="" desc="LPM Interrupt." hidden="false" />\r
+ <field name="RESUME_INTR" from="4" to="4" access="RW" resetVal="" desc="Resume Interrupt." hidden="false" />\r
+ </register>\r
+ <register name="CR1" address="0x40006009" bitWidth="8" desc="USB Control 1 Register" hidden="false">\r
+ <field name="REG_ENABLE" from="0" to="0" access="R" resetVal="" desc="This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply." hidden="false">\r
+ <value name="Disabled" value="0" desc="Regulator for 5V is disabled." />\r
+ <value name="Enabled" value="1" desc="Regulator for 5V is enabled." />\r
+ </field>\r
+ <field name="ENABLE_LOCK" from="1" to="1" access="RW" resetVal="" desc="This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation." hidden="false" />\r
+ <field name="BUS_ACTIVITY" from="2" to="2" access="RW" resetVal="" desc="The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High value until firmware clears it." hidden="false" />\r
+ <field name="TRIM_OFFSET_MSB" from="3" to="3" access="RW" resetVal="" desc="This bit enables trim bit[7]." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP_INT_EN" address="0x4000600A" bitWidth="8" desc="USB SIE Data Endpoints Interrupt Enable Register" hidden="false">\r
+ <field name="EP1_INTR_EN" from="0" to="0" access="RW" resetVal="" desc="Enables interrupt for EP1." hidden="false" />\r
+ <field name="EP2_INTR_EN" from="1" to="1" access="RW" resetVal="" desc="Enables interrupt for EP2." hidden="false" />\r
+ <field name="EP3_INTR_EN" from="2" to="2" access="RW" resetVal="" desc="Enables interrupt for EP3." hidden="false" />\r
+ <field name="EP4_INTR_EN" from="3" to="3" access="RW" resetVal="" desc="Enables interrupt for EP4." hidden="false" />\r
+ <field name="EP5_INTR_EN" from="4" to="4" access="RW" resetVal="" desc="Enables interrupt for EP5." hidden="false" />\r
+ <field name="EP6_INTR_EN" from="5" to="5" access="RW" resetVal="" desc="Enables interrupt for EP6." hidden="false" />\r
+ <field name="EP7_INTR_EN" from="6" to="6" access="RW" resetVal="" desc="Enables interrupt for EP7." hidden="false" />\r
+ <field name="EP8_INTR_EN" from="7" to="7" access="RW" resetVal="" desc="Enables interrupt for EP8." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP_INT_SR" address="0x4000600B" bitWidth="8" desc="SIE Data Endpoint Interrupt Status Register" hidden="false">\r
+ <field name="EP1_INTR" from="0" to="0" access="RW" resetVal="" desc="Interrupt status for EP1." hidden="false" />\r
+ <field name="EP2_INTR" from="1" to="1" access="RW" resetVal="" desc="Interrupt status for EP2." hidden="false" />\r
+ <field name="EP3_INTR" from="2" to="2" access="RW" resetVal="" desc="Interrupt status for EP3." hidden="false" />\r
+ <field name="EP4_INTR" from="3" to="3" access="RW" resetVal="" desc="Interrupt status for EP4." hidden="false" />\r
+ <field name="EP5_INTR" from="4" to="4" access="RW" resetVal="" desc="Interrupt status for EP5." hidden="false" />\r
+ <field name="EP6_INTR" from="5" to="5" access="RW" resetVal="" desc="Interrupt status for EP6." hidden="false" />\r
+ <field name="EP7_INTR" from="6" to="6" access="RW" resetVal="" desc="Interrupt status for EP7." hidden="false" />\r
+ <field name="EP8_INTR" from="7" to="7" access="RW" resetVal="" desc="Interrupt status for EP8." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP1_CNT0" address="0x4000600C" bitWidth="8" desc="SIE Endpoint 1 Count0 Register" hidden="false">\r
+ <field name="DATA_COUNT_MSB" from="2" to="0" access="RW" resetVal="" desc="These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="DATA_ERROR - 0, DATA_VALID - 1." hidden="false" />\r
+ <field name="DATA_TOGGLE" from="7" to="7" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP1_CNT1" address="0x4000600D" bitWidth="8" desc="SIE Endpoint 1 Count1 Register" hidden="false">\r
+ <field name="DATA_COUNT" from="7" to="0" access="RW" resetVal="" desc="These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP1_CR0" address="0x4000600E" bitWidth="8" desc="SIE Endpoint 1 Control Register" hidden="false">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="USBIO_CR0" address="0x40006010" bitWidth="8" desc="USBIO Control 0 Register" hidden="false">\r
+ <field name="RD" from="0" to="0" access="R" resetVal="" desc="Received Data. This read only bit gives the state of the USB differential receiver." hidden="false">\r
+ <value name="DIFF_LOW" value="0" desc="D+ less than D- (K state), or D+=D-=0 (SE0)." />\r
+ <value name="DIFF_HIGH" value="1" desc="D+ greater than D- (J state)." />\r
+ </field>\r
+ <field name="TD" from="5" to="5" access="RW" resetVal="" desc="Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1." hidden="false">\r
+ <value name="DIFF_K" value="0" desc="Force USB K state (D+ is low D- is high)." />\r
+ <value name="DIFF_J" value="1" desc="Force USB J state (D+ is high D- is low)." />\r
+ </field>\r
+ <field name="TSE0" from="6" to="6" access="RW" resetVal="" desc="Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0." hidden="false" />\r
+ <field name="TEN" from="7" to="7" access="RW" resetVal="" desc="USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually transmitting is to force a resume state on the bus." hidden="false" />\r
+ </register>\r
+ <register name="USBIO_CR1" address="0x40006012" bitWidth="8" desc="USBIO Control 1 Register" hidden="false">\r
+ <field name="DMO" from="0" to="0" access="R" resetVal="" desc="This read only bit gives the state of the D- pin." hidden="false" />\r
+ <field name="DPO" from="1" to="1" access="R" resetVal="" desc="This read only bit gives the state of the D+ pin." hidden="false" />\r
+ <field name="USBPUEN" from="2" to="2" access="RW" resetVal="" desc="This bit enables the connection of the internal 1.5 k pull up resistor on the D+ pin." hidden="false" />\r
+ <field name="IOMODE" from="5" to="5" access="RW" resetVal="" desc="This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins." hidden="false">\r
+ <value name="Bit-banged" value="0" desc="Bit-banged mode for Dm and Dp." />\r
+ <value name="USB" value="1" desc="USB block controls Dm and Dp." />\r
+ </field>\r
+ </register>\r
+ <register name="DYN_RECONFIG" address="0x40006014" bitWidth="8" desc="USB Dynamic reconfiguration Register" hidden="true">\r
+ <field name="DYN_CONFIG_EN" from="0" to="0" access="RW" resetVal="" desc="This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1, indicates the reconfiguration required for selected EP. Use 0 for EP1, 1 for EP2, etc." hidden="false" />\r
+ <field name="DYN_RECONFIG_EPNO" from="3" to="1" access="RW" resetVal="" desc="These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1." hidden="false" />\r
+ <field name="DYN_RECONFIG_RDY_STS" from="4" to="4" access="R" resetVal="" desc="This bit indicates the ready status for the dynamic reconfiguration, when set to 1, indicates the block is ready for reconfiguration." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP2_CNT0" address="0x4000601C" bitWidth="8" desc="SIE Endpoint 1 Count0 Register" hidden="false">\r
+ <field name="DATA_COUNT_MSB" from="2" to="0" access="RW" resetVal="" desc="These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="DATA_ERROR - 0, DATA_VALID - 1." hidden="false" />\r
+ <field name="DATA_TOGGLE" from="7" to="7" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP2_CNT1" address="0x4000601D" bitWidth="8" desc="SIE Endpoint 1 Count1 Register" hidden="false">\r
+ <field name="DATA_COUNT" from="7" to="0" access="RW" resetVal="" desc="These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP2_CR0" address="0x4000601E" bitWidth="8" desc="SIE Endpoint 1 Control Register" hidden="false">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="EP0_CR" address="0x40006028" bitWidth="8" desc="Endpoint0 control Register" hidden="false">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="EP0_CNT" address="0x40006029" bitWidth="8" desc="Endpoint0 control Register" hidden="false">\r
+ <field name="BYTE_COUNT" from="3" to="0" access="RW" resetVal="" desc="These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." hidden="false">\r
+ <value name="DATA_ERROR" value="0" desc="No ACK'd transactions since bit was last cleared." />\r
+ <value name="DATA_VALID" value="1" desc="Indicates a transaction ended with an ACK." />\r
+ </field>\r
+ <field name="DATA_TOGGLE" from="5" to="5" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP3_CNT0" address="0x4000602C" bitWidth="8" desc="SIE Endpoint 1 Count0 Register" hidden="false">\r
+ <field name="DATA_COUNT_MSB" from="2" to="0" access="RW" resetVal="" desc="These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="DATA_ERROR - 0, DATA_VALID - 1." hidden="false" />\r
+ <field name="DATA_TOGGLE" from="7" to="7" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP3_CNT1" address="0x4000602D" bitWidth="8" desc="SIE Endpoint 1 Count1 Register" hidden="false">\r
+ <field name="DATA_COUNT" from="7" to="0" access="RW" resetVal="" desc="These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP3_CR0" address="0x4000602E" bitWidth="8" desc="SIE Endpoint 1 Control Register" hidden="false">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP4_CNT0" address="0x4000603C" bitWidth="8" desc="SIE Endpoint 1 Count0 Register" hidden="false">\r
+ <field name="DATA_COUNT_MSB" from="2" to="0" access="RW" resetVal="" desc="These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="DATA_ERROR - 0, DATA_VALID - 1." hidden="false" />\r
+ <field name="DATA_TOGGLE" from="7" to="7" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP4_CNT1" address="0x4000603D" bitWidth="8" desc="SIE Endpoint 1 Count1 Register" hidden="false">\r
+ <field name="DATA_COUNT" from="7" to="0" access="RW" resetVal="" desc="These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP4_CR0" address="0x4000603E" bitWidth="8" desc="SIE Endpoint 1 Control Register" hidden="false">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP5_CNT0" address="0x4000604C" bitWidth="8" desc="SIE Endpoint 1 Count0 Register" hidden="true">\r
+ <field name="DATA_COUNT_MSB" from="2" to="0" access="RW" resetVal="" desc="These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="DATA_ERROR - 0, DATA_VALID - 1." hidden="false" />\r
+ <field name="DATA_TOGGLE" from="7" to="7" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP5_CNT1" address="0x4000604D" bitWidth="8" desc="SIE Endpoint 1 Count1 Register" hidden="true">\r
+ <field name="DATA_COUNT" from="7" to="0" access="RW" resetVal="" desc="These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP5_CR0" address="0x4000604E" bitWidth="8" desc="SIE Endpoint 1 Control Register" hidden="true">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP6_CNT0" address="0x4000605C" bitWidth="8" desc="SIE Endpoint 1 Count0 Register" hidden="true">\r
+ <field name="DATA_COUNT_MSB" from="2" to="0" access="RW" resetVal="" desc="These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="DATA_ERROR - 0, DATA_VALID - 1." hidden="false" />\r
+ <field name="DATA_TOGGLE" from="7" to="7" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP6_CNT1" address="0x4000605D" bitWidth="8" desc="SIE Endpoint 1 Count1 Register" hidden="true">\r
+ <field name="DATA_COUNT" from="7" to="0" access="RW" resetVal="" desc="These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP6_CR0" address="0x4000605E" bitWidth="8" desc="SIE Endpoint 1 Control Register" hidden="true">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP7_CNT0" address="0x4000606C" bitWidth="8" desc="SIE Endpoint 1 Count0 Register" hidden="true">\r
+ <field name="DATA_COUNT_MSB" from="2" to="0" access="RW" resetVal="" desc="These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="DATA_ERROR - 0, DATA_VALID - 1." hidden="false" />\r
+ <field name="DATA_TOGGLE" from="7" to="7" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP7_CNT1" address="0x4000606D" bitWidth="8" desc="SIE Endpoint 1 Count1 Register" hidden="true">\r
+ <field name="DATA_COUNT" from="7" to="0" access="RW" resetVal="" desc="These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP7_CR0" address="0x4000606E" bitWidth="8" desc="SIE Endpoint 1 Control Register" hidden="true">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP8_CNT0" address="0x4000607C" bitWidth="8" desc="SIE Endpoint 1 Count0 Register" hidden="true">\r
+ <field name="DATA_COUNT_MSB" from="2" to="0" access="RW" resetVal="" desc="These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="DATA_ERROR - 0, DATA_VALID - 1." hidden="false" />\r
+ <field name="DATA_TOGGLE" from="7" to="7" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP8_CNT1" address="0x4000607D" bitWidth="8" desc="SIE Endpoint 1 Count1 Register" hidden="true">\r
+ <field name="DATA_COUNT" from="7" to="0" access="RW" resetVal="" desc="These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP8_CR0" address="0x4000607E" bitWidth="8" desc="SIE Endpoint 1 Control Register" hidden="true">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP1_CFG" address="0x40006080" bitWidth="8" desc="Arbiter Endpoint 1 Configuration Register" hidden="false">\r
+ <field name="IN_DATA_RDY" from="0" to="0" access="RW" resetVal="" desc="Indication that Endpoint Packet Data is Ready in Main memory" hidden="false" />\r
+ <field name="DMA_REQ" from="1" to="1" access="RW" resetVal="" desc="Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." hidden="false" />\r
+ <field name="CRC_BYPASS" from="2" to="2" access="RW" resetVal="" desc="CRC_NORMAL - 0, CRC_BYPASS - 1" hidden="false" />\r
+ <field name="RESET_PTR" from="3" to="3" access="RW" resetVal="" desc="RESET_KRYPTON - 0, RESET_NORMAL - 1" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP1_INT_EN" address="0x40006081" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Enable Register" hidden="false">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP1_INT_SR" address="0x40006082" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Status Register" hidden="false">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW1_WA" address="0x40006084" bitWidth="8" desc="Arbiter Endpoint 1 Write Address LSB Register" hidden="false">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for EP." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW1_WA_MSB" address="0x40006085" bitWidth="8" desc="Arbiter Endpoint 1 Write Address MSB Register" hidden="false">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW1_RA" address="0x40006086" bitWidth="8" desc="Arbiter Endpoint 1 Read Address LSB Register" hidden="false">\r
+ <field name="RA8" from="7" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW1_RA_MSB" address="0x40006087" bitWidth="8" desc="Arbiter Endpoint 1 Read Address MSB Register" hidden="false">\r
+ <field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="BUF_SIZE" address="0x4000608C" bitWidth="8" desc="Dedicated Endpoint Buffer Size Register" hidden="true">\r
+ <field name="IN_BUF" from="3" to="0" access="RW" resetVal="" desc="Buffer size for IN Endpoints: 1 - 2 bytes, 2 - 4 bytes; 9 - 512 bytes." hidden="false" />\r
+ <field name="OUT_BUF" from="7" to="4" access="RW" resetVal="" desc="Buffer size for OUT Endpoints: 1 - 2 bytes, 2 - 4 bytes; 9 - 512 bytes." hidden="false" />\r
+ </register>\r
+ <register name="EP_ACTIVE" address="0x4000608E" bitWidth="8" desc="Endpoint Active Indication Register" hidden="true">\r
+ <field name="EP1_ACT" from="0" to="0" access="R" resetVal="" desc="Indicates that EP1 is currently active" hidden="false" />\r
+ <field name="EP2_ACT" from="1" to="1" access="R" resetVal="" desc="Indicates that EP2 is currently active" hidden="false" />\r
+ <field name="EP3_ACT" from="2" to="2" access="R" resetVal="" desc="Indicates that EP3 is currently active" hidden="false" />\r
+ <field name="EP4_ACT" from="3" to="3" access="R" resetVal="" desc="Indicates that EP4 is currently active" hidden="false" />\r
+ <field name="EP5_ACT" from="4" to="4" access="R" resetVal="" desc="Indicates that EP5 is currently active" hidden="false" />\r
+ <field name="EP6_ACT" from="5" to="5" access="R" resetVal="" desc="Indicates that EP6 is currently active6" hidden="false" />\r
+ <field name="EP7_ACT" from="6" to="6" access="R" resetVal="" desc="Indicates that EP7 is currently active" hidden="false" />\r
+ <field name="EP8_ACT" from="7" to="7" access="R" resetVal="" desc="Indicates that EP8 is currently active" hidden="false" />\r
+ </register>\r
+ <register name="EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" hidden="true">\r
+ <field name="EP1_TYP" from="0" to="0" access="RW" resetVal="" desc="Endpoint Type Indication." hidden="false">\r
+ <value name="EP_IN" value="0" desc="IN outpoint." />\r
+ <value name="EP_OUT" value="1" desc="OUT outpoint." />\r
+ </field>\r
+ <field name="EP2_TYP" from="1" to="1" access="RW" resetVal="" desc="Endpoint Type Indication." hidden="false">\r
+ <value name="EP_IN" value="0" desc="IN outpoint." />\r
+ <value name="EP_OUT" value="1" desc="OUT outpoint." />\r
+ </field>\r
+ <field name="EP3_TYP" from="2" to="2" access="RW" resetVal="" desc="Endpoint Type Indication." hidden="false">\r
+ <value name="EP_IN" value="0" desc="IN outpoint." />\r
+ <value name="EP_OUT" value="1" desc="OUT outpoint." />\r
+ </field>\r
+ <field name="EP4_TYP" from="3" to="3" access="RW" resetVal="" desc="Endpoint Type Indication." hidden="false">\r
+ <value name="EP_IN" value="0" desc="IN outpoint." />\r
+ <value name="EP_OUT" value="1" desc="OUT outpoint." />\r
+ </field>\r
+ <field name="EP5_TYP" from="4" to="4" access="RW" resetVal="" desc="Endpoint Type Indication." hidden="false">\r
+ <value name="EP_IN" value="0" desc="IN outpoint." />\r
+ <value name="EP_OUT" value="1" desc="OUT outpoint." />\r
+ </field>\r
+ <field name="EP6_TYP" from="5" to="5" access="RW" resetVal="" desc="Endpoint Type Indication." hidden="false">\r
+ <value name="EP_IN" value="0" desc="IN outpoint." />\r
+ <value name="EP_OUT" value="1" desc="OUT outpoint." />\r
+ </field>\r
+ <field name="EP7_TYP" from="6" to="6" access="RW" resetVal="" desc="Endpoint Type Indication." hidden="false">\r
+ <value name="EP_IN" value="0" desc="IN outpoint." />\r
+ <value name="EP_OUT" value="1" desc="OUT outpoint." />\r
+ </field>\r
+ <field name="EP8_TYP" from="7" to="7" access="RW" resetVal="" desc="Endpoint Type Indication." hidden="false">\r
+ <value name="EP_IN" value="0" desc="IN outpoint." />\r
+ <value name="EP_OUT" value="1" desc="OUT outpoint." />\r
+ </field>\r
+ </register>\r
+ <register name="ARB_EP2_CFG" address="0x40006090" bitWidth="8" desc="Arbiter Endpoint 1 Configuration Register" hidden="false">\r
+ <field name="IN_DATA_RDY" from="0" to="0" access="RW" resetVal="" desc="Indication that Endpoint Packet Data is Ready in Main memory" hidden="false" />\r
+ <field name="DMA_REQ" from="1" to="1" access="RW" resetVal="" desc="Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." hidden="false" />\r
+ <field name="CRC_BYPASS" from="2" to="2" access="RW" resetVal="" desc="CRC_NORMAL - 0, CRC_BYPASS - 1" hidden="false" />\r
+ <field name="RESET_PTR" from="3" to="3" access="RW" resetVal="" desc="RESET_KRYPTON - 0, RESET_NORMAL - 1" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP2_INT_EN" address="0x40006091" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Enable Register" hidden="false">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP2_INT_SR" address="0x40006092" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Status Register" hidden="false">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW2_WA" address="0x40006094" bitWidth="8" desc="Arbiter Endpoint 1 Write Address LSB Register" hidden="false">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for EP." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW2_WA_MSB" address="0x40006095" bitWidth="8" desc="Arbiter Endpoint 1 Write Address MSB Register" hidden="false">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW2_RA" address="0x40006096" bitWidth="8" desc="Arbiter Endpoint 1 Read Address LSB Register" hidden="false">\r
+ <field name="RA8" from="7" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW2_RA_MSB" address="0x40006097" bitWidth="8" desc="Arbiter Endpoint 1 Read Address MSB Register" hidden="false">\r
+ <field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_CFG" address="0x4000609C" bitWidth="8" desc="Arbiter configuration register" hidden="false">\r
+ <field name="AUTO_MEM" from="4" to="4" access="RW" resetVal="" desc="Enables Auto Memory Configuration. Manual memory configuration by default." hidden="false" />\r
+ <field name="DMA_CFG" from="6" to="5" access="RW" resetVal="" desc="DMA Access Configuration." hidden="false">\r
+ <value name="DMA_NONE" value="00" desc="No DMA." />\r
+ <value name="DMA_MANUAL" value="01" desc="Manual DMA." />\r
+ <value name="DMA_AUTO" value="10" desc="Auto DMA." />\r
+ </field>\r
+ <field name="CFG_CMP" from="7" to="7" access="RW" resetVal="" desc="Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required." hidden="false" />\r
+ </register>\r
+ <register name="USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Control 0 Register" hidden="false">\r
+ <field name="CSR_CLK_EN" from="7" to="7" access="RW" resetVal="" desc="Clock Enable for Core Logic clocked by AHB bus clock." hidden="false">\r
+ <value name="Disabled" value="0" desc="Disables clock to UBS block." />\r
+ <value name="Enabled" value="1" desc="Enables clock to UBS block." />\r
+ </field>\r
+ </register>\r
+ <register name="ARB_INT_EN" address="0x4000609E" bitWidth="8" desc="Arbiter Interrupt Enable Register" hidden="false">\r
+ <field name="EP1_INTR_EN" from="0" to="0" access="RW" resetVal="" desc="Enables interrupt for EP1." hidden="false" />\r
+ <field name="EP2_INTR_EN" from="1" to="1" access="RW" resetVal="" desc="Enables interrupt for EP2." hidden="false" />\r
+ <field name="EP3_INTR_EN" from="2" to="2" access="RW" resetVal="" desc="Enables interrupt for EP3." hidden="false" />\r
+ <field name="EP4_INTR_EN" from="3" to="3" access="RW" resetVal="" desc="Enables interrupt for EP4." hidden="false" />\r
+ <field name="EP5_INTR_EN" from="4" to="4" access="RW" resetVal="" desc="Enables interrupt for EP5." hidden="false" />\r
+ <field name="EP6_INTR_EN" from="5" to="5" access="RW" resetVal="" desc="Enables interrupt for EP6." hidden="false" />\r
+ <field name="EP7_INTR_EN" from="6" to="6" access="RW" resetVal="" desc="Enables interrupt for EP7." hidden="false" />\r
+ <field name="EP8_INTR_EN" from="7" to="7" access="RW" resetVal="" desc="Enables interrupt for EP8." hidden="false" />\r
+ </register>\r
+ <register name="ARB_INT_SR" address="0x4000609F" bitWidth="8" desc="Arbiter Interrupt Status" hidden="false">\r
+ <field name="EP1_INTR" from="0" to="0" access="R" resetVal="" desc="Interrupt status for EP1." hidden="false" />\r
+ <field name="EP2_INTR" from="1" to="1" access="R" resetVal="" desc="Interrupt status for EP2." hidden="false" />\r
+ <field name="EP3_INTR" from="2" to="2" access="R" resetVal="" desc="Interrupt status for EP3." hidden="false" />\r
+ <field name="EP4_INTR" from="3" to="3" access="R" resetVal="" desc="Interrupt status for EP4." hidden="false" />\r
+ <field name="EP5_INTR" from="4" to="4" access="R" resetVal="" desc="Interrupt status for EP5." hidden="false" />\r
+ <field name="EP6_INTR" from="5" to="5" access="R" resetVal="" desc="Interrupt status for EP6." hidden="false" />\r
+ <field name="EP7_INTR" from="6" to="6" access="R" resetVal="" desc="Interrupt status for EP7." hidden="false" />\r
+ <field name="EP8_INTR" from="7" to="7" access="R" resetVal="" desc="Interrupt status for EP8." hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP3_CFG" address="0x400060A0" bitWidth="8" desc="Arbiter Endpoint 1 Configuration Register" hidden="false">\r
+ <field name="IN_DATA_RDY" from="0" to="0" access="RW" resetVal="" desc="Indication that Endpoint Packet Data is Ready in Main memory" hidden="false" />\r
+ <field name="DMA_REQ" from="1" to="1" access="RW" resetVal="" desc="Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." hidden="false" />\r
+ <field name="CRC_BYPASS" from="2" to="2" access="RW" resetVal="" desc="CRC_NORMAL - 0, CRC_BYPASS - 1" hidden="false" />\r
+ <field name="RESET_PTR" from="3" to="3" access="RW" resetVal="" desc="RESET_KRYPTON - 0, RESET_NORMAL - 1" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP3_INT_EN" address="0x400060A1" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Enable Register" hidden="false">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP3_INT_SR" address="0x400060A2" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Status Register" hidden="false">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW3_WA" address="0x400060A4" bitWidth="8" desc="Arbiter Endpoint 1 Write Address LSB Register" hidden="false">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for EP." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW3_WA_MSB" address="0x400060A5" bitWidth="8" desc="Arbiter Endpoint 1 Write Address MSB Register" hidden="false">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW3_RA" address="0x400060A6" bitWidth="8" desc="Arbiter Endpoint 1 Read Address LSB Register" hidden="false">\r
+ <field name="RA8" from="7" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW3_RA_MSB" address="0x400060A7" bitWidth="8" desc="Arbiter Endpoint 1 Read Address MSB Register" hidden="false">\r
+ <field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="CWA" address="0x400060AC" bitWidth="8" desc="Common Area Write Address LSB Register" hidden="true">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for Common Area." hidden="false" />\r
+ </register>\r
+ <register name="CWA_MSB" address="0x400060AD" bitWidth="8" desc="Common Area Write Address LSB Register" hidden="true">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for Common Area MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP4_CFG" address="0x400060B0" bitWidth="8" desc="Arbiter Endpoint 1 Configuration Register" hidden="false">\r
+ <field name="IN_DATA_RDY" from="0" to="0" access="RW" resetVal="" desc="Indication that Endpoint Packet Data is Ready in Main memory" hidden="false" />\r
+ <field name="DMA_REQ" from="1" to="1" access="RW" resetVal="" desc="Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." hidden="false" />\r
+ <field name="CRC_BYPASS" from="2" to="2" access="RW" resetVal="" desc="CRC_NORMAL - 0, CRC_BYPASS - 1" hidden="false" />\r
+ <field name="RESET_PTR" from="3" to="3" access="RW" resetVal="" desc="RESET_KRYPTON - 0, RESET_NORMAL - 1" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP4_INT_EN" address="0x400060B1" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Enable Register" hidden="false">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP4_INT_SR" address="0x400060B2" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Status Register" hidden="false">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW4_WA" address="0x400060B4" bitWidth="8" desc="Arbiter Endpoint 1 Write Address LSB Register" hidden="false">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for EP." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW4_WA_MSB" address="0x400060B5" bitWidth="8" desc="Arbiter Endpoint 1 Write Address MSB Register" hidden="false">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW4_RA" address="0x400060B6" bitWidth="8" desc="Arbiter Endpoint 1 Read Address LSB Register" hidden="false">\r
+ <field name="RA8" from="7" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW4_RA_MSB" address="0x400060B7" bitWidth="8" desc="Arbiter Endpoint 1 Read Address MSB Register" hidden="false">\r
+ <field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="DMA_THRES" address="0x400060BC" bitWidth="8" desc="DMA Burst / Threshold Configuration LSB Register" hidden="true">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="DMA Threshold count." hidden="false" />\r
+ </register>\r
+ <register name="DMA_THRES_MSB" address="0x400060BD" bitWidth="8" desc="DMA Burst / Threshold Configuration LSB Register" hidden="true">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="DMA Threshold count MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP5_CFG" address="0x400060C0" bitWidth="8" desc="Arbiter Endpoint 1 Configuration Register" hidden="true">\r
+ <field name="IN_DATA_RDY" from="0" to="0" access="RW" resetVal="" desc="Indication that Endpoint Packet Data is Ready in Main memory" hidden="false" />\r
+ <field name="DMA_REQ" from="1" to="1" access="RW" resetVal="" desc="Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." hidden="false" />\r
+ <field name="CRC_BYPASS" from="2" to="2" access="RW" resetVal="" desc="CRC_NORMAL - 0, CRC_BYPASS - 1" hidden="false" />\r
+ <field name="RESET_PTR" from="3" to="3" access="RW" resetVal="" desc="RESET_KRYPTON - 0, RESET_NORMAL - 1" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP5_INT_EN" address="0x400060C1" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Enable Register" hidden="true">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP5_INT_SR" address="0x400060C2" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Status Register" hidden="true">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW5_WA" address="0x400060C4" bitWidth="8" desc="Arbiter Endpoint 1 Write Address LSB Register" hidden="true">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for EP." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW5_WA_MSB" address="0x400060C5" bitWidth="8" desc="Arbiter Endpoint 1 Write Address MSB Register" hidden="true">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW5_RA" address="0x400060C6" bitWidth="8" desc="Arbiter Endpoint 1 Read Address LSB Register" hidden="true">\r
+ <field name="RA8" from="7" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW5_RA_MSB" address="0x400060C7" bitWidth="8" desc="Arbiter Endpoint 1 Read Address MSB Register" hidden="true">\r
+ <field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="BUS_RST_CNT" address="0x400060CC" bitWidth="8" desc="Bus Reset Count Register" hidden="true">\r
+ <field name="BUS_RST_CNT" from="3" to="0" access="RW" resetVal="" desc="Bus Reset Count Length. Bus Reset Count register ; For USB bus reset length; The value in this register determines the no. of pulses of the low freq. clock which will be counted to determine if an SE0 condition has been held for long enough to declare a USB Bus reset condition. In krypton, 3 pulses of a 32 KHz clock were counted to declare a usb bus reset condition. In leopard, a 100 KHz clock is used. Recommended is to count 10 pulses of this clock to remain equivalent to Krypton." hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP6_CFG" address="0x400060D0" bitWidth="8" desc="Arbiter Endpoint 1 Configuration Register" hidden="true">\r
+ <field name="IN_DATA_RDY" from="0" to="0" access="RW" resetVal="" desc="Indication that Endpoint Packet Data is Ready in Main memory" hidden="false" />\r
+ <field name="DMA_REQ" from="1" to="1" access="RW" resetVal="" desc="Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." hidden="false" />\r
+ <field name="CRC_BYPASS" from="2" to="2" access="RW" resetVal="" desc="CRC_NORMAL - 0, CRC_BYPASS - 1" hidden="false" />\r
+ <field name="RESET_PTR" from="3" to="3" access="RW" resetVal="" desc="RESET_KRYPTON - 0, RESET_NORMAL - 1" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP6_INT_EN" address="0x400060D1" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Enable Register" hidden="true">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP6_INT_SR" address="0x400060D2" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Status Register" hidden="true">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW6_WA" address="0x400060D4" bitWidth="8" desc="Arbiter Endpoint 1 Write Address LSB Register" hidden="true">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for EP." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW6_WA_MSB" address="0x400060D5" bitWidth="8" desc="Arbiter Endpoint 1 Write Address MSB Register" hidden="true">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW6_RA" address="0x400060D6" bitWidth="8" desc="Arbiter Endpoint 1 Read Address LSB Register" hidden="true">\r
+ <field name="RA8" from="7" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW6_RA_MSB" address="0x400060D7" bitWidth="8" desc="Arbiter Endpoint 1 Read Address MSB Register" hidden="true">\r
+ <field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP7_CFG" address="0x400060E0" bitWidth="8" desc="Arbiter Endpoint 1 Configuration Register" hidden="true">\r
+ <field name="IN_DATA_RDY" from="0" to="0" access="RW" resetVal="" desc="Indication that Endpoint Packet Data is Ready in Main memory" hidden="false" />\r
+ <field name="DMA_REQ" from="1" to="1" access="RW" resetVal="" desc="Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." hidden="false" />\r
+ <field name="CRC_BYPASS" from="2" to="2" access="RW" resetVal="" desc="CRC_NORMAL - 0, CRC_BYPASS - 1" hidden="false" />\r
+ <field name="RESET_PTR" from="3" to="3" access="RW" resetVal="" desc="RESET_KRYPTON - 0, RESET_NORMAL - 1" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP7_INT_EN" address="0x400060E1" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Enable Register" hidden="true">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP7_INT_SR" address="0x400060E2" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Status Register" hidden="true">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW7_WA" address="0x400060E4" bitWidth="8" desc="Arbiter Endpoint 1 Write Address LSB Register" hidden="true">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for EP." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW7_WA_MSB" address="0x400060E5" bitWidth="8" desc="Arbiter Endpoint 1 Write Address MSB Register" hidden="true">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW7_RA" address="0x400060E6" bitWidth="8" desc="Arbiter Endpoint 1 Read Address LSB Register" hidden="true">\r
+ <field name="RA8" from="7" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW7_RA_MSB" address="0x400060E7" bitWidth="8" desc="Arbiter Endpoint 1 Read Address MSB Register" hidden="true">\r
+ <field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP8_CFG" address="0x400060F0" bitWidth="8" desc="Arbiter Endpoint 1 Configuration Register" hidden="true">\r
+ <field name="IN_DATA_RDY" from="0" to="0" access="RW" resetVal="" desc="Indication that Endpoint Packet Data is Ready in Main memory" hidden="false" />\r
+ <field name="DMA_REQ" from="1" to="1" access="RW" resetVal="" desc="Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." hidden="false" />\r
+ <field name="CRC_BYPASS" from="2" to="2" access="RW" resetVal="" desc="CRC_NORMAL - 0, CRC_BYPASS - 1" hidden="false" />\r
+ <field name="RESET_PTR" from="3" to="3" access="RW" resetVal="" desc="RESET_KRYPTON - 0, RESET_NORMAL - 1" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP8_INT_EN" address="0x400060F1" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Enable Register" hidden="true">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP8_INT_SR" address="0x400060F2" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Status Register" hidden="true">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW8_WA" address="0x400060F4" bitWidth="8" desc="Arbiter Endpoint 1 Write Address LSB Register" hidden="true">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for EP." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW8_WA_MSB" address="0x400060F5" bitWidth="8" desc="Arbiter Endpoint 1 Write Address MSB Register" hidden="true">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW8_RA" address="0x400060F6" bitWidth="8" desc="Arbiter Endpoint 1 Read Address LSB Register" hidden="true">\r
+ <field name="RA8" from="7" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW8_RA_MSB" address="0x400060F7" bitWidth="8" desc="Arbiter Endpoint 1 Read Address MSB Register" hidden="true">\r
+ <field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
</block>\r
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
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</block>\r
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- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />\r
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</block>\r
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
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<Hidden v="False" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
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+<CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtComponentSerialize" version="1">\r
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<dependencies>\r
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<project_current_platform v="c9323d49-d323-40b8-9b59-cc008d68a989" />\r
<project_current_processor v="CortexM3" />\r
<last_selected_tab v="Cypress" />\r
-<WriteAppVersionLastSavedWith v="3.3.0.410" />\r
-<WriteAppMarketingVersionLastSavedWith v=" 3.3" />\r
-<project_id v="6e1f5cbb-a0ca-4f55-a1fa-7b20c5be3a3e" /><custom_data><CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1"><CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997 type_name="CyDesigner.Common.Base.CyCustomData" version="2"><userData /></CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997><properties /></CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111></custom_data></CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>\r
+<WriteAppVersionLastSavedWith v="4.0.0.432" />\r
+<WriteAppMarketingVersionLastSavedWith v=" 4.0 Update 1" />\r
+<project_id v="6e1f5cbb-a0ca-4f55-a1fa-7b20c5be3a3e" />\r
+<GenerateDescriptionFiles v="False" />\r
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</CyGuid_60697ce6-dce2-4816-8680-4de0635742eb>\r
<top_block v="TopDesign" />\r
<selected_device v="CY8C5267AXI-LP051" />\r
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+<pdl_path v="" />\r
+<include_paths />\r
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<library_deps>\r
<library_dep persistent="${CyRoot}\psoc\content\default\CyAnnotationLibrary\CyAnnotationLibrary.cylib\CyAnnotationLibrary.cyprj" />\r
<library_dep persistent="${CyRoot}\psoc\content\default\CyReferenceLibrary\CyReferenceLibrary.cylib\CyReferenceLibrary.cyprj" />\r
<ignored_deps />\r
</CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>\r
<boot_component v="cy_boot_v4_20" />\r
-<current_generation v="7" /><BootloaderTag hexFile="" elfFile="" /></CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>\r
+<current_generation v="7" />\r
+</CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>\r
</CyXmlSerializer>
\ No newline at end of file
<peripheral>\r
<name>SCSI_Out_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006477</baseAddress>\r
+ <baseAddress>0x40006579</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_Glitch_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006473</baseAddress>\r
+ <baseAddress>0x40006474</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_Filtered</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006465</baseAddress>\r
+ <baseAddress>0x4000646C</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_Parity_Error</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006466</baseAddress>\r
+ <baseAddress>0x40006567</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_CTL_PHASE</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006472</baseAddress>\r
+ <baseAddress>0x40006475</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
</addressBlock>\r
<registers>\r
<register>\r
- <name>USBFS_PM_USB_CR0</name>\r
- <description>USB Power Mode Control Register 0</description>\r
- <addressOffset>0x40004394</addressOffset>\r
+ <name>CR0</name>\r
+ <description>USB Control 0 Register</description>\r
+ <addressOffset>0x40006008</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DEVICE_ADDRESS</name>\r
+ <description>These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware.</description>\r
+ <lsb>0</lsb>\r
+ <msb>6</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>USB_ENABLE</name>\r
+ <description>This bit enables the device to respond to USB traffic.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Disabled</name>\r
+ <description>Block responds to USB traffic.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Enabled</name>\r
+ <description>Block does not respond to USB traffic.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>CR1</name>\r
+ <description>USB Control 1 Register</description>\r
+ <addressOffset>0x40006009</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>REG_ENABLE</name>\r
+ <description>This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-only</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Disabled</name>\r
+ <description>Regulator for 5V is disabled.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Enabled</name>\r
+ <description>Regulator for 5V is enabled.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>ENABLE_LOCK</name>\r
+ <description>This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUS_ACTIVITY</name>\r
+ <description>The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High value until firmware clears it.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>TRIM_OFFSET_MSB</name>\r
+ <description>This bit enables trim bit[7].</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP_INT_EN</name>\r
+ <description>USB SIE Data Endpoints Interrupt Enable Register</description>\r
+ <addressOffset>0x4000600A</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>EP1_INTR_EN</name>\r
+ <description>Enables interrupt for EP1.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP2_INTR_EN</name>\r
+ <description>Enables interrupt for EP2.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP3_INTR_EN</name>\r
+ <description>Enables interrupt for EP3.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP4_INTR_EN</name>\r
+ <description>Enables interrupt for EP4.</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP5_INTR_EN</name>\r
+ <description>Enables interrupt for EP5.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP6_INTR_EN</name>\r
+ <description>Enables interrupt for EP6.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP7_INTR_EN</name>\r
+ <description>Enables interrupt for EP7.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP8_INTR_EN</name>\r
+ <description>Enables interrupt for EP8.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP_INT_SR</name>\r
+ <description>SIE Data Endpoint Interrupt Status Register</description>\r
+ <addressOffset>0x4000600B</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>EP1_INTR</name>\r
+ <description>Interrupt status for EP1.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP2_INTR</name>\r
+ <description>Interrupt status for EP2.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP3_INTR</name>\r
+ <description>Interrupt status for EP3.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP4_INTR</name>\r
+ <description>Interrupt status for EP4.</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP5_INTR</name>\r
+ <description>Interrupt status for EP5.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP6_INTR</name>\r
+ <description>Interrupt status for EP6.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP7_INTR</name>\r
+ <description>Interrupt status for EP7.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP8_INTR</name>\r
+ <description>Interrupt status for EP8.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP1_CNT0</name>\r
+ <description>SIE Endpoint 1 Count0 Register</description>\r
+ <addressOffset>0x4000600C</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DATA_COUNT_MSB</name>\r
+ <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>\r
+ <lsb>0</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_VALID</name>\r
+ <description>DATA_ERROR - 0, DATA_VALID - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_TOGGLE</name>\r
+ <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP1_CNT1</name>\r
+ <description>SIE Endpoint 1 Count1 Register</description>\r
+ <addressOffset>0x4000600D</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DATA_COUNT</name>\r
+ <description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP1_CR0</name>\r
+ <description>SIE Endpoint 1 Control Register</description>\r
+ <addressOffset>0x4000600E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>MODE</name>\r
+ <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>\r
+ <lsb>0</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DISABLE</name>\r
+ <description>Ignore all USB traffic to this endpoint.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_INOUT</name>\r
+ <description>SETUP: Accept, IN: NAK, OUT: NAK.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_OUT_ONLY</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STALL_INOUT</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: STALL.</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>\r
+ <value>5</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_IN_ONLY</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Stall.</description>\r
+ <value>6</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_IN</name>\r
+ <description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>\r
+ <value>7</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>\r
+ <value>8</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>\r
+ <value>9</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT_STATUS_IN</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Accept data.</description>\r
+ <value>11</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_IN</name>\r
+ <description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>\r
+ <value>12</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN</name>\r
+ <description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>\r
+ <value>13</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN_STATUS_OUT</name>\r
+ <description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>15</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>ACKED_TXN</name>\r
+ <description>ACKED_NO - 0, ACKED_YES - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>NAK_INT_EN</name>\r
+ <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_IN_TXN</name>\r
+ <description>The Error in transaction bit is set whenever an error is detected.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>STALL</name>\r
+ <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>USBIO_CR0</name>\r
+ <description>USBIO Control 0 Register</description>\r
+ <addressOffset>0x40006010</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>RD</name>\r
+ <description>Received Data. This read only bit gives the state of the USB differential receiver.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-only</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DIFF_LOW</name>\r
+ <description>D+ less than D- (K state), or D+=D-=0 (SE0).</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DIFF_HIGH</name>\r
+ <description>D+ greater than D- (J state).</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>TD</name>\r
+ <description>Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DIFF_K</name>\r
+ <description>Force USB K state (D+ is low D- is high).</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DIFF_J</name>\r
+ <description>Force USB J state (D+ is high D- is low).</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>TSE0</name>\r
+ <description>Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>TEN</name>\r
+ <description>USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually transmitting is to force a resume state on the bus.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>USBIO_CR1</name>\r
+ <description>USBIO Control 1 Register</description>\r
+ <addressOffset>0x40006012</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DMO</name>\r
+ <description>This read only bit gives the state of the D- pin.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>DPO</name>\r
+ <description>This read only bit gives the state of the D+ pin.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>USBPUEN</name>\r
+ <description>This bit enables the connection of the internal 1.5 k pull up resistor on the D+ pin.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>IOMODE</name>\r
+ <description>This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Bit_banged</name>\r
+ <description>Bit-banged mode for Dm and Dp.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>USB</name>\r
+ <description>USB block controls Dm and Dp.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP2_CNT0</name>\r
+ <description>SIE Endpoint 1 Count0 Register</description>\r
+ <addressOffset>0x4000601C</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DATA_COUNT_MSB</name>\r
+ <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>\r
+ <lsb>0</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_VALID</name>\r
+ <description>DATA_ERROR - 0, DATA_VALID - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_TOGGLE</name>\r
+ <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP2_CNT1</name>\r
+ <description>SIE Endpoint 1 Count1 Register</description>\r
+ <addressOffset>0x4000601D</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DATA_COUNT</name>\r
+ <description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP2_CR0</name>\r
+ <description>SIE Endpoint 1 Control Register</description>\r
+ <addressOffset>0x4000601E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>MODE</name>\r
+ <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>\r
+ <lsb>0</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DISABLE</name>\r
+ <description>Ignore all USB traffic to this endpoint.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_INOUT</name>\r
+ <description>SETUP: Accept, IN: NAK, OUT: NAK.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_OUT_ONLY</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STALL_INOUT</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: STALL.</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>\r
+ <value>5</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_IN_ONLY</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Stall.</description>\r
+ <value>6</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_IN</name>\r
+ <description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>\r
+ <value>7</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>\r
+ <value>8</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>\r
+ <value>9</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT_STATUS_IN</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Accept data.</description>\r
+ <value>11</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_IN</name>\r
+ <description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>\r
+ <value>12</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN</name>\r
+ <description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>\r
+ <value>13</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN_STATUS_OUT</name>\r
+ <description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>15</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>ACKED_TXN</name>\r
+ <description>ACKED_NO - 0, ACKED_YES - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>NAK_INT_EN</name>\r
+ <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_IN_TXN</name>\r
+ <description>The Error in transaction bit is set whenever an error is detected.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>STALL</name>\r
+ <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>EP0_CR</name>\r
+ <description>Endpoint0 control Register</description>\r
+ <addressOffset>0x40006028</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>MODE</name>\r
+ <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>\r
+ <lsb>0</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DISABLE</name>\r
+ <description>Ignore all USB traffic to this endpoint.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_INOUT</name>\r
+ <description>SETUP: Accept, IN: NAK, OUT: NAK.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_OUT_ONLY</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STALL_INOUT</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: STALL.</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>\r
+ <value>5</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_IN_ONLY</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Stall.</description>\r
+ <value>6</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_IN</name>\r
+ <description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>\r
+ <value>7</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>\r
+ <value>8</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>\r
+ <value>9</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT_STATUS_IN</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Accept data.</description>\r
+ <value>11</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_IN</name>\r
+ <description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>\r
+ <value>12</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN</name>\r
+ <description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>\r
+ <value>13</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN_STATUS_OUT</name>\r
+ <description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>15</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>ACKED_TXN</name>\r
+ <description>ACKED_NO - 0, ACKED_YES - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>NAK_INT_EN</name>\r
+ <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_IN_TXN</name>\r
+ <description>The Error in transaction bit is set whenever an error is detected.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>STALL</name>\r
+ <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>EP0_CNT</name>\r
+ <description>Endpoint0 control Register</description>\r
+ <addressOffset>0x40006029</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>BYTE_COUNT</name>\r
+ <description>These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10.</description>\r
+ <lsb>0</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_VALID</name>\r
+ <description>This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DATA_ERROR</name>\r
+ <description>No ACK'd transactions since bit was last cleared.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DATA_VALID</name>\r
+ <description>Indicates a transaction ended with an ACK.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>DATA_TOGGLE</name>\r
+ <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP3_CNT0</name>\r
+ <description>SIE Endpoint 1 Count0 Register</description>\r
+ <addressOffset>0x4000602C</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DATA_COUNT_MSB</name>\r
+ <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>\r
+ <lsb>0</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_VALID</name>\r
+ <description>DATA_ERROR - 0, DATA_VALID - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_TOGGLE</name>\r
+ <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP3_CNT1</name>\r
+ <description>SIE Endpoint 1 Count1 Register</description>\r
+ <addressOffset>0x4000602D</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DATA_COUNT</name>\r
+ <description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP3_CR0</name>\r
+ <description>SIE Endpoint 1 Control Register</description>\r
+ <addressOffset>0x4000602E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>MODE</name>\r
+ <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>\r
+ <lsb>0</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DISABLE</name>\r
+ <description>Ignore all USB traffic to this endpoint.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_INOUT</name>\r
+ <description>SETUP: Accept, IN: NAK, OUT: NAK.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_OUT_ONLY</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STALL_INOUT</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: STALL.</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>\r
+ <value>5</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_IN_ONLY</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Stall.</description>\r
+ <value>6</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_IN</name>\r
+ <description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>\r
+ <value>7</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>\r
+ <value>8</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>\r
+ <value>9</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT_STATUS_IN</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Accept data.</description>\r
+ <value>11</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_IN</name>\r
+ <description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>\r
+ <value>12</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN</name>\r
+ <description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>\r
+ <value>13</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN_STATUS_OUT</name>\r
+ <description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>15</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>ACKED_TXN</name>\r
+ <description>ACKED_NO - 0, ACKED_YES - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>NAK_INT_EN</name>\r
+ <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_IN_TXN</name>\r
+ <description>The Error in transaction bit is set whenever an error is detected.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>STALL</name>\r
+ <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP4_CNT0</name>\r
+ <description>SIE Endpoint 1 Count0 Register</description>\r
+ <addressOffset>0x4000603C</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DATA_COUNT_MSB</name>\r
+ <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>\r
+ <lsb>0</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_VALID</name>\r
+ <description>DATA_ERROR - 0, DATA_VALID - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_TOGGLE</name>\r
+ <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP4_CNT1</name>\r
+ <description>SIE Endpoint 1 Count1 Register</description>\r
+ <addressOffset>0x4000603D</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DATA_COUNT</name>\r
+ <description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP4_CR0</name>\r
+ <description>SIE Endpoint 1 Control Register</description>\r
+ <addressOffset>0x4000603E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>MODE</name>\r
+ <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>\r
+ <lsb>0</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DISABLE</name>\r
+ <description>Ignore all USB traffic to this endpoint.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_INOUT</name>\r
+ <description>SETUP: Accept, IN: NAK, OUT: NAK.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_OUT_ONLY</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STALL_INOUT</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: STALL.</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>\r
+ <value>5</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_IN_ONLY</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Stall.</description>\r
+ <value>6</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_IN</name>\r
+ <description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>\r
+ <value>7</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>\r
+ <value>8</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>\r
+ <value>9</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT_STATUS_IN</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Accept data.</description>\r
+ <value>11</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_IN</name>\r
+ <description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>\r
+ <value>12</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN</name>\r
+ <description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>\r
+ <value>13</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN_STATUS_OUT</name>\r
+ <description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>15</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>ACKED_TXN</name>\r
+ <description>ACKED_NO - 0, ACKED_YES - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>NAK_INT_EN</name>\r
+ <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_IN_TXN</name>\r
+ <description>The Error in transaction bit is set whenever an error is detected.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>STALL</name>\r
+ <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_EP1_CFG</name>\r
+ <description>Arbiter Endpoint 1 Configuration Register</description>\r
+ <addressOffset>0x40006080</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>IN_DATA_RDY</name>\r
+ <description>Indication that Endpoint Packet Data is Ready in Main memory</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_REQ</name>\r
+ <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>CRC_BYPASS</name>\r
+ <description>CRC_NORMAL - 0, CRC_BYPASS - 1</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>RESET_PTR</name>\r
+ <description>RESET_KRYPTON - 0, RESET_NORMAL - 1</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_EP1_INT_EN</name>\r
+ <description>Arbiter Endpoint 1 Interrupt Enable Register</description>\r
+ <addressOffset>0x40006081</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>IN_BUF_FULL_EN</name>\r
+ <description>IN Endpoint Local Buffer Full</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_GNT_EN</name>\r
+ <description>Endpoint DMA Grant</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_OVER_EN</name>\r
+ <description>Endpoint Buffer Overflow</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_UNDER_EN</name>\r
+ <description>Endpoint Buffer Underflow</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_INT_EN</name>\r
+ <description>Endpoint Error in Transaction Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_TERMIN_EN</name>\r
+ <description>Endpoint DMA Terminated Enable</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_EP1_INT_SR</name>\r
+ <description>Arbiter Endpoint 1 Interrupt Status Register</description>\r
+ <addressOffset>0x40006082</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>IN_BUF_FULL_EN</name>\r
+ <description>IN Endpoint Local Buffer Full</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_GNT_EN</name>\r
+ <description>Endpoint DMA Grant</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_OVER_EN</name>\r
+ <description>Endpoint Buffer Overflow</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_UNDER_EN</name>\r
+ <description>Endpoint Buffer Underflow</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_INT_EN</name>\r
+ <description>Endpoint Error in Transaction Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_TERMIN_EN</name>\r
+ <description>Endpoint DMA Terminated Enable</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_RW1_WA</name>\r
+ <description>Arbiter Endpoint 1 Write Address LSB Register</description>\r
+ <addressOffset>0x40006084</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>WA8</name>\r
+ <description>Write Address for EP.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_RW1_WA_MSB</name>\r
+ <description>Arbiter Endpoint 1 Write Address MSB Register</description>\r
+ <addressOffset>0x40006085</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>WA9</name>\r
+ <description>Write Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_RW1_RA</name>\r
+ <description>Arbiter Endpoint 1 Read Address LSB Register</description>\r
+ <addressOffset>0x40006086</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>RA8</name>\r
+ <description>Read Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_RW1_RA_MSB</name>\r
+ <description>Arbiter Endpoint 1 Read Address MSB Register</description>\r
+ <addressOffset>0x40006087</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>RA9</name>\r
+ <description>Read Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_EP2_CFG</name>\r
+ <description>Arbiter Endpoint 1 Configuration Register</description>\r
+ <addressOffset>0x40006090</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>IN_DATA_RDY</name>\r
+ <description>Indication that Endpoint Packet Data is Ready in Main memory</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_REQ</name>\r
+ <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>CRC_BYPASS</name>\r
+ <description>CRC_NORMAL - 0, CRC_BYPASS - 1</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>RESET_PTR</name>\r
+ <description>RESET_KRYPTON - 0, RESET_NORMAL - 1</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_EP2_INT_EN</name>\r
+ <description>Arbiter Endpoint 1 Interrupt Enable Register</description>\r
+ <addressOffset>0x40006091</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>IN_BUF_FULL_EN</name>\r
+ <description>IN Endpoint Local Buffer Full</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_GNT_EN</name>\r
+ <description>Endpoint DMA Grant</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_OVER_EN</name>\r
+ <description>Endpoint Buffer Overflow</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_UNDER_EN</name>\r
+ <description>Endpoint Buffer Underflow</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_INT_EN</name>\r
+ <description>Endpoint Error in Transaction Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_TERMIN_EN</name>\r
+ <description>Endpoint DMA Terminated Enable</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_EP2_INT_SR</name>\r
+ <description>Arbiter Endpoint 1 Interrupt Status Register</description>\r
+ <addressOffset>0x40006092</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>fsusbio_ref_en</name>\r
- <description>No description available</description>\r
+ <name>IN_BUF_FULL_EN</name>\r
+ <description>IN Endpoint Local Buffer Full</description>\r
<lsb>0</lsb>\r
<msb>0</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>fsusbio_pd_n</name>\r
- <description>No description available</description>\r
+ <name>DMA_GNT_EN</name>\r
+ <description>Endpoint DMA Grant</description>\r
<lsb>1</lsb>\r
<msb>1</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>fsusbio_pd_pullup_n</name>\r
- <description>No description available</description>\r
+ <name>BUF_OVER_EN</name>\r
+ <description>Endpoint Buffer Overflow</description>\r
<lsb>2</lsb>\r
<msb>2</msb>\r
<access>read-write</access>\r
</field>\r
+ <field>\r
+ <name>BUF_UNDER_EN</name>\r
+ <description>Endpoint Buffer Underflow</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_INT_EN</name>\r
+ <description>Endpoint Error in Transaction Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_TERMIN_EN</name>\r
+ <description>Endpoint DMA Terminated Enable</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_RW2_WA</name>\r
+ <description>Arbiter Endpoint 1 Write Address LSB Register</description>\r
+ <addressOffset>0x40006094</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>WA8</name>\r
+ <description>Write Address for EP.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_RW2_WA_MSB</name>\r
+ <description>Arbiter Endpoint 1 Write Address MSB Register</description>\r
+ <addressOffset>0x40006095</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>WA9</name>\r
+ <description>Write Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_RW2_RA</name>\r
+ <description>Arbiter Endpoint 1 Read Address LSB Register</description>\r
+ <addressOffset>0x40006096</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>RA8</name>\r
+ <description>Read Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_RW2_RA_MSB</name>\r
+ <description>Arbiter Endpoint 1 Read Address MSB Register</description>\r
+ <addressOffset>0x40006097</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>RA9</name>\r
+ <description>Read Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_CFG</name>\r
+ <description>Arbiter configuration register</description>\r
+ <addressOffset>0x4000609C</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>AUTO_MEM</name>\r
+ <description>Enables Auto Memory Configuration. Manual memory configuration by default.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_CFG</name>\r
+ <description>DMA Access Configuration.</description>\r
+ <lsb>5</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DMA_NONE</name>\r
+ <description>No DMA.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DMA_MANUAL</name>\r
+ <description>Manual DMA.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DMA_AUTO</name>\r
+ <description>Auto DMA.</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>CFG_CMP</name>\r
+ <description>Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_PM_ACT_CFG</name>\r
- <description>Active Power Mode Configuration Register</description>\r
- <addressOffset>0x400043A5</addressOffset>\r
+ <name>USB_CLK_EN</name>\r
+ <description>USB Control 0 Register</description>\r
+ <addressOffset>0x4000609D</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>CSR_CLK_EN</name>\r
+ <description>Clock Enable for Core Logic clocked by AHB bus clock.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Disabled</name>\r
+ <description>Disables clock to UBS block.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Enabled</name>\r
+ <description>Enables clock to UBS block.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_PM_STBY_CFG</name>\r
- <description>Standby Power Mode Configuration Register</description>\r
- <addressOffset>0x400043B5</addressOffset>\r
+ <name>ARB_INT_EN</name>\r
+ <description>Arbiter Interrupt Enable Register</description>\r
+ <addressOffset>0x4000609E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>EP1_INTR_EN</name>\r
+ <description>Enables interrupt for EP1.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP2_INTR_EN</name>\r
+ <description>Enables interrupt for EP2.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP3_INTR_EN</name>\r
+ <description>Enables interrupt for EP3.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP4_INTR_EN</name>\r
+ <description>Enables interrupt for EP4.</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP5_INTR_EN</name>\r
+ <description>Enables interrupt for EP5.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP6_INTR_EN</name>\r
+ <description>Enables interrupt for EP6.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP7_INTR_EN</name>\r
+ <description>Enables interrupt for EP7.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP8_INTR_EN</name>\r
+ <description>Enables interrupt for EP8.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_PRT_PS</name>\r
- <description>Port Pin State Register</description>\r
- <addressOffset>0x400051F1</addressOffset>\r
+ <name>ARB_INT_SR</name>\r
+ <description>Arbiter Interrupt Status</description>\r
+ <addressOffset>0x4000609F</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>PinState_DP</name>\r
- <description>No description available</description>\r
+ <name>EP1_INTR</name>\r
+ <description>Interrupt status for EP1.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>EP2_INTR</name>\r
+ <description>Interrupt status for EP2.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>EP3_INTR</name>\r
+ <description>Interrupt status for EP3.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>EP4_INTR</name>\r
+ <description>Interrupt status for EP4.</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>EP5_INTR</name>\r
+ <description>Interrupt status for EP5.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>EP6_INTR</name>\r
+ <description>Interrupt status for EP6.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>EP7_INTR</name>\r
+ <description>Interrupt status for EP7.</description>\r
<lsb>6</lsb>\r
<msb>6</msb>\r
<access>read-only</access>\r
</field>\r
<field>\r
- <name>PinState_DM</name>\r
- <description>No description available</description>\r
+ <name>EP8_INTR</name>\r
+ <description>Interrupt status for EP8.</description>\r
<lsb>7</lsb>\r
<msb>7</msb>\r
<access>read-only</access>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_PRT_DM0</name>\r
- <description>Port Drive Mode Register</description>\r
- <addressOffset>0x400051F2</addressOffset>\r
+ <name>ARB_EP3_CFG</name>\r
+ <description>Arbiter Endpoint 1 Configuration Register</description>\r
+ <addressOffset>0x400060A0</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>DriveMode_DP</name>\r
- <description>No description available</description>\r
- <lsb>6</lsb>\r
- <msb>6</msb>\r
+ <name>IN_DATA_RDY</name>\r
+ <description>Indication that Endpoint Packet Data is Ready in Main memory</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>DriveMode_DM</name>\r
- <description>No description available</description>\r
- <lsb>7</lsb>\r
- <msb>7</msb>\r
+ <name>DMA_REQ</name>\r
+ <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>CRC_BYPASS</name>\r
+ <description>CRC_NORMAL - 0, CRC_BYPASS - 1</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>RESET_PTR</name>\r
+ <description>RESET_KRYPTON - 0, RESET_NORMAL - 1</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_PRT_DM1</name>\r
- <description>Port Drive Mode Register</description>\r
- <addressOffset>0x400051F3</addressOffset>\r
+ <name>ARB_EP3_INT_EN</name>\r
+ <description>Arbiter Endpoint 1 Interrupt Enable Register</description>\r
+ <addressOffset>0x400060A1</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>PullUp_en_DP</name>\r
- <description>No description available</description>\r
- <lsb>6</lsb>\r
- <msb>6</msb>\r
+ <name>IN_BUF_FULL_EN</name>\r
+ <description>IN Endpoint Local Buffer Full</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>PullUp_en_DM</name>\r
- <description>No description available</description>\r
- <lsb>7</lsb>\r
- <msb>7</msb>\r
+ <name>DMA_GNT_EN</name>\r
+ <description>Endpoint DMA Grant</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_OVER_EN</name>\r
+ <description>Endpoint Buffer Overflow</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_UNDER_EN</name>\r
+ <description>Endpoint Buffer Underflow</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_INT_EN</name>\r
+ <description>Endpoint Error in Transaction Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_TERMIN_EN</name>\r
+ <description>Endpoint DMA Terminated Enable</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_PRT_INP_DIS</name>\r
- <description>Input buffer disable override</description>\r
- <addressOffset>0x400051F8</addressOffset>\r
+ <name>ARB_EP3_INT_SR</name>\r
+ <description>Arbiter Endpoint 1 Interrupt Status Register</description>\r
+ <addressOffset>0x400060A2</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>seinput_dis_dp</name>\r
- <description>No description available</description>\r
- <lsb>6</lsb>\r
- <msb>6</msb>\r
+ <name>IN_BUF_FULL_EN</name>\r
+ <description>IN Endpoint Local Buffer Full</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>seinput_dis_dm</name>\r
- <description>No description available</description>\r
- <lsb>7</lsb>\r
- <msb>7</msb>\r
+ <name>DMA_GNT_EN</name>\r
+ <description>Endpoint DMA Grant</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_OVER_EN</name>\r
+ <description>Endpoint Buffer Overflow</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_UNDER_EN</name>\r
+ <description>Endpoint Buffer Underflow</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_INT_EN</name>\r
+ <description>Endpoint Error in Transaction Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_TERMIN_EN</name>\r
+ <description>Endpoint DMA Terminated Enable</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_EP0_DR0</name>\r
- <description>bmRequestType</description>\r
- <addressOffset>0x40006000</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_EP0_DR1</name>\r
- <description>bRequest</description>\r
- <addressOffset>0x40006001</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_EP0_DR2</name>\r
- <description>wValueLo</description>\r
- <addressOffset>0x40006002</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_EP0_DR3</name>\r
- <description>wValueHi</description>\r
- <addressOffset>0x40006003</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_EP0_DR4</name>\r
- <description>wIndexLo</description>\r
- <addressOffset>0x40006004</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_EP0_DR5</name>\r
- <description>wIndexHi</description>\r
- <addressOffset>0x40006005</addressOffset>\r
+ <name>ARB_RW3_WA</name>\r
+ <description>Arbiter Endpoint 1 Write Address LSB Register</description>\r
+ <addressOffset>0x400060A4</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>WA8</name>\r
+ <description>Write Address for EP.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_EP0_DR6</name>\r
- <description>lengthLo</description>\r
- <addressOffset>0x40006006</addressOffset>\r
+ <name>ARB_RW3_WA_MSB</name>\r
+ <description>Arbiter Endpoint 1 Write Address MSB Register</description>\r
+ <addressOffset>0x400060A5</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>WA9</name>\r
+ <description>Write Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_EP0_DR7</name>\r
- <description>lengthHi</description>\r
- <addressOffset>0x40006007</addressOffset>\r
+ <name>ARB_RW3_RA</name>\r
+ <description>Arbiter Endpoint 1 Read Address LSB Register</description>\r
+ <addressOffset>0x400060A6</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>RA8</name>\r
+ <description>Read Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_CR0</name>\r
- <description>USB Control Register 0</description>\r
- <addressOffset>0x40006008</addressOffset>\r
+ <name>ARB_RW3_RA_MSB</name>\r
+ <description>Arbiter Endpoint 1 Read Address MSB Register</description>\r
+ <addressOffset>0x400060A7</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>device_address</name>\r
- <description>No description available</description>\r
+ <name>RA9</name>\r
+ <description>Read Address for EP MSB.</description>\r
<lsb>0</lsb>\r
- <msb>6</msb>\r
- <access>read-only</access>\r
- </field>\r
- <field>\r
- <name>usb_enable</name>\r
- <description>No description available</description>\r
- <lsb>7</lsb>\r
- <msb>7</msb>\r
+ <msb>0</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_CR1</name>\r
- <description>USB Control Register 1</description>\r
- <addressOffset>0x40006009</addressOffset>\r
+ <name>ARB_EP4_CFG</name>\r
+ <description>Arbiter Endpoint 1 Configuration Register</description>\r
+ <addressOffset>0x400060B0</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>reg_enable</name>\r
- <description>No description available</description>\r
+ <name>IN_DATA_RDY</name>\r
+ <description>Indication that Endpoint Packet Data is Ready in Main memory</description>\r
<lsb>0</lsb>\r
<msb>0</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>enable_lock</name>\r
- <description>No description available</description>\r
+ <name>DMA_REQ</name>\r
+ <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>\r
<lsb>1</lsb>\r
<msb>1</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>bus_activity</name>\r
- <description>No description available</description>\r
+ <name>CRC_BYPASS</name>\r
+ <description>CRC_NORMAL - 0, CRC_BYPASS - 1</description>\r
<lsb>2</lsb>\r
<msb>2</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>trim_offset_msb</name>\r
- <description>No description available</description>\r
+ <name>RESET_PTR</name>\r
+ <description>RESET_KRYPTON - 0, RESET_NORMAL - 1</description>\r
<lsb>3</lsb>\r
<msb>3</msb>\r
<access>read-write</access>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_SIE_EP1_CR0</name>\r
- <description>The Endpoint1 Control Register</description>\r
- <addressOffset>0x4000600E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_USBIO_CR0</name>\r
- <description>USBIO Control Register 0</description>\r
- <addressOffset>0x40006010</addressOffset>\r
+ <name>ARB_EP4_INT_EN</name>\r
+ <description>Arbiter Endpoint 1 Interrupt Enable Register</description>\r
+ <addressOffset>0x400060B1</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>rd</name>\r
- <description>No description available</description>\r
+ <name>IN_BUF_FULL_EN</name>\r
+ <description>IN Endpoint Local Buffer Full</description>\r
<lsb>0</lsb>\r
<msb>0</msb>\r
- <access>read-only</access>\r
+ <access>read-write</access>\r
</field>\r
<field>\r
- <name>td</name>\r
- <description>No description available</description>\r
- <lsb>5</lsb>\r
- <msb>5</msb>\r
+ <name>DMA_GNT_EN</name>\r
+ <description>Endpoint DMA Grant</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>tse0</name>\r
- <description>No description available</description>\r
- <lsb>6</lsb>\r
- <msb>6</msb>\r
+ <name>BUF_OVER_EN</name>\r
+ <description>Endpoint Buffer Overflow</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>ten</name>\r
- <description>No description available</description>\r
- <lsb>7</lsb>\r
- <msb>7</msb>\r
+ <name>BUF_UNDER_EN</name>\r
+ <description>Endpoint Buffer Underflow</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_INT_EN</name>\r
+ <description>Endpoint Error in Transaction Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_TERMIN_EN</name>\r
+ <description>Endpoint DMA Terminated Enable</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_USBIO_CR1</name>\r
- <description>USBIO Control Register 1</description>\r
- <addressOffset>0x40006012</addressOffset>\r
+ <name>ARB_EP4_INT_SR</name>\r
+ <description>Arbiter Endpoint 1 Interrupt Status Register</description>\r
+ <addressOffset>0x400060B2</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>dmo</name>\r
- <description>No description available</description>\r
+ <name>IN_BUF_FULL_EN</name>\r
+ <description>IN Endpoint Local Buffer Full</description>\r
<lsb>0</lsb>\r
<msb>0</msb>\r
- <access>read-only</access>\r
+ <access>read-write</access>\r
</field>\r
<field>\r
- <name>dpo</name>\r
- <description>No description available</description>\r
+ <name>DMA_GNT_EN</name>\r
+ <description>Endpoint DMA Grant</description>\r
<lsb>1</lsb>\r
<msb>1</msb>\r
- <access>read-only</access>\r
+ <access>read-write</access>\r
</field>\r
<field>\r
- <name>usbpuen</name>\r
- <description>No description available</description>\r
+ <name>BUF_OVER_EN</name>\r
+ <description>Endpoint Buffer Overflow</description>\r
<lsb>2</lsb>\r
<msb>2</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>iomode</name>\r
- <description>No description available</description>\r
+ <name>BUF_UNDER_EN</name>\r
+ <description>Endpoint Buffer Underflow</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_INT_EN</name>\r
+ <description>Endpoint Error in Transaction Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_TERMIN_EN</name>\r
+ <description>Endpoint DMA Terminated Enable</description>\r
<lsb>5</lsb>\r
<msb>5</msb>\r
<access>read-write</access>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_SIE_EP2_CR0</name>\r
- <description>The Endpoint2 Control Register</description>\r
- <addressOffset>0x4000601E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_SIE_EP3_CR0</name>\r
- <description>The Endpoint3 Control Register</description>\r
- <addressOffset>0x4000602E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_SIE_EP4_CR0</name>\r
- <description>The Endpoint4 Control Register</description>\r
- <addressOffset>0x4000603E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_SIE_EP5_CR0</name>\r
- <description>The Endpoint5 Control Register</description>\r
- <addressOffset>0x4000604E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_SIE_EP6_CR0</name>\r
- <description>The Endpoint6 Control Register</description>\r
- <addressOffset>0x4000605E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_SIE_EP7_CR0</name>\r
- <description>The Endpoint7 Control Register</description>\r
- <addressOffset>0x4000606E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_SIE_EP8_CR0</name>\r
- <description>The Endpoint8 Control Register</description>\r
- <addressOffset>0x4000607E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_BUF_SIZE</name>\r
- <description>Dedicated Endpoint Buffer Size Register</description>\r
- <addressOffset>0x4000608C</addressOffset>\r
+ <name>ARB_RW4_WA</name>\r
+ <description>Arbiter Endpoint 1 Write Address LSB Register</description>\r
+ <addressOffset>0x400060B4</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>WA8</name>\r
+ <description>Write Address for EP.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_EP_ACTIVE</name>\r
- <description>Endpoint Active Indication Register</description>\r
- <addressOffset>0x4000608E</addressOffset>\r
+ <name>ARB_RW4_WA_MSB</name>\r
+ <description>Arbiter Endpoint 1 Write Address MSB Register</description>\r
+ <addressOffset>0x400060B5</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>WA9</name>\r
+ <description>Write Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_EP_TYPE</name>\r
- <description>Endpoint Type (IN/OUT) Indication</description>\r
- <addressOffset>0x4000608F</addressOffset>\r
+ <name>ARB_RW4_RA</name>\r
+ <description>Arbiter Endpoint 1 Read Address LSB Register</description>\r
+ <addressOffset>0x400060B6</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>RA8</name>\r
+ <description>Read Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_USB_CLK_EN</name>\r
- <description>USB Block Clock Enable Register</description>\r
- <addressOffset>0x4000609D</addressOffset>\r
+ <name>ARB_RW4_RA_MSB</name>\r
+ <description>Arbiter Endpoint 1 Read Address MSB Register</description>\r
+ <addressOffset>0x400060B7</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>RA9</name>\r
+ <description>Read Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
</registers>\r
</peripheral>\r
<peripheral>\r
<name>SCSI_Out_Bits</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000647C</baseAddress>\r
+ <baseAddress>0x4000647B</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
-/*******************************************************************************\r
-* File Name: Bootloadable_1.c\r
-* Version 1.30\r
+/****************************************************************************//**\r
+* \file Bootloadable_1.c\r
+* \version 1.50\r
*\r
-* Description:\r
-* Provides an API for the Bootloadable application. The API includes a\r
-* single function for starting the bootloader.\r
+* \brief\r
+* Provides an API for the Bootloadable application.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#include "Bootloadable_1.h"\r
\r
+/**\r
+ \defgroup functions_group Functions\r
+ @{\r
+*/\r
+\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
+static cystatus Bootloadable_1_WriteFlashByte(const uint32 address, const uint8 inputValue) CYLARGE \\r
+ ;\r
+#endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/\r
\r
/*******************************************************************************\r
* Function Name: Bootloadable_1_Load\r
-********************************************************************************\r
-* Summary:\r
-* Begins the bootloading algorithm downloading a new ACD image from the host.\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None\r
+* \brief\r
+* Schedules the Bootloader/Launcher to be launched and then performs\r
+* a software reset to launch it\r
*\r
-* Returns:\r
+* \return\r
* This method will never return. It will load a new application and reset\r
* the device.\r
*\r
void Bootloadable_1_Load(void) \r
{\r
/* Schedule Bootloader to start after reset */\r
- Bootloadable_1_SET_RUN_TYPE(Bootloadable_1_START_BTLDR);\r
+ Bootloadable_1_SET_RUN_TYPE(Bootloadable_1_SCHEDULE_BTLDR);\r
\r
CySoftwareReset();\r
}\r
\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
+/*******************************************************************************\r
+* Function Name: Bootloadable_1_GetActiveApplication\r
+****************************************************************************//**\r
+*\r
+* \brief\r
+* Gets the application which will be loaded after a next reset event.\r
+* NOTE Intended for the combination project type ONLY!\r
+*\r
+* \return \r
+* A number of the current active application set in the metadata section.\r
+* \n 0 - app#0 is set as active.\r
+* \n 1 - app#1 is set as active.\r
+*\r
+* \note If neither of the applications is set active, then the API returns 0x02.\r
+*\r
+*******************************************************************************/\r
+uint8 Bootloadable_1_GetActiveApplication(void) CYSMALL \\r
+ \r
+{ \r
+ uint8 result = Bootloadable_1_MD_BTLDB_ACTIVE_NONE;\r
+ \r
+ if (0u != Bootloadable_1_GET_CODE_DATA( \\r
+ Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(Bootloadable_1_MD_BTLDB_ACTIVE_0))) \r
+ {\r
+ result = Bootloadable_1_MD_BTLDB_ACTIVE_0;\r
+ }\r
+ else if (0u != Bootloadable_1_GET_CODE_DATA( \\r
+ Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(Bootloadable_1_MD_BTLDB_ACTIVE_1)))\r
+ {\r
+ result = Bootloadable_1_MD_BTLDB_ACTIVE_1; \r
+ }\r
+ else\r
+ {\r
+ /*Do nothing, result is none*/\r
+ }\r
+ \r
+ return (result);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name: Bootloadable_1_SetActiveApplication\r
+****************************************************************************//**\r
+*\r
+* \brief \r
+* Sets the application which will be loaded after a next reset event. \r
+* \r
+* \details\r
+* Theory: \r
+* This API sets in the Flash (metadata section) the given active application \r
+* number.\r
+* \r
+* NOTE The active application number is not set directly, but the boolean \r
+* mark instead means that the application is active or not for the relative \r
+* metadata. Both metadata sections are updated. For example, if the second \r
+* application is to be set active, then in the metadata section for the first \r
+* application there will be a "0" written, which means that it is not active, and \r
+* for the second metadata section there will be a "1" written, which means that it is \r
+* active. \r
+*\r
+* NOTE Intended for the combination project type ONLY!\r
+*\r
+* \param appId \r
+* The active application number to be written to flash (metadata section) \r
+* NOTE Possible values are:\r
+* 0 - for the first application\r
+* 1 - for the second application.\r
+* Any other number is considered invalid. \r
+*\r
+* \return \r
+* A status of writing to flash operation.\r
+* \n CYRET_SUCCESS - Returned if appId was successfully changed. \r
+* \n CYRET_BAD_PARAM - Returned if the parameter appID passed to the function has the \r
+* same value as the active application ID. \r
+* \note - The other non-zero value is considered as a failure during writing to flash. \r
+*\r
+* \note - This API does not update Bootloader_activeApp variable.\r
+*\r
+*******************************************************************************/\r
+cystatus Bootloadable_1_SetActiveApplication(uint8 appId) CYSMALL \\r
+ \r
+{\r
+ cystatus result = CYRET_SUCCESS;\r
+\r
+ uint8 CYDATA idx;\r
+ \r
+ /* If invalid application number */\r
+ if (appId > Bootloadable_1_MD_BTLDB_ACTIVE_1)\r
+ {\r
+ result = CYRET_BAD_PARAM;\r
+ }\r
+ else\r
+ {\r
+ /* If appID has same value as active application ID */\r
+ if (1u == Bootloadable_1_GET_CODE_DATA(Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(appId)))\r
+ {\r
+ result = CYRET_BAD_PARAM;\r
+ }\r
+ else\r
+ {\r
+ /* Updating metadata section */\r
+ for(idx = 0u; idx < Bootloadable_1_MAX_NUM_OF_BTLDB; idx++)\r
+ {\r
+ result |= Bootloadable_1_WriteFlashByte((uint32) Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(idx), \\r
+ (uint8)(idx == appId));\r
+ }\r
+ }\r
+ }\r
+ \r
+ return (result);\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name: Bootloadable_1_WriteFlashByte\r
+****************************************************************************//**\r
+*\r
+* \brief \r
+* This API writes to flash the specified data.\r
+*\r
+* \param address \r
+* The address in flash.\r
+*\r
+* \param inputValue \r
+* One-byte data.\r
+*\r
+* \return \r
+* A status of the writing to flash procedure.\r
+*\r
+*******************************************************************************/\r
+static cystatus Bootloadable_1_WriteFlashByte(const uint32 address, const uint8 inputValue) CYLARGE \\r
+ \r
+{\r
+ cystatus result = CYRET_SUCCESS;\r
+ uint32 flsAddr = address - CYDEV_FLASH_BASE;\r
+ uint8 rowData[CYDEV_FLS_ROW_SIZE];\r
+\r
+ #if !(CY_PSOC4)\r
+ uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE);\r
+ #endif /* !(CY_PSOC4) */\r
+\r
+ #if (CY_PSOC4)\r
+ uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE);\r
+ #else\r
+ uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);\r
+ #endif /* (CY_PSOC4) */\r
+\r
+ uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE);\r
+ uint16 idx;\r
+\r
+ for(idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++)\r
+ {\r
+ rowData[idx] = (uint8)Bootloadable_1_GET_CODE_DATA(baseAddr + idx);\r
+ }\r
+\r
+ rowData[address % CYDEV_FLS_ROW_SIZE] = inputValue;\r
+\r
+ #if(CY_PSOC4)\r
+ result = CySysFlashWriteRow((uint32) rowNum, rowData);\r
+ #else\r
+ result = CyWriteRowData(arrayId, rowNum, rowData);\r
+ #endif /* (CY_PSOC4) */\r
+\r
+ #if(CY_PSOC5)\r
+ /***************************************************************************\r
+ * When writing to flash, data in the instruction cache can become stale.\r
+ * Therefore, the cache data does not correlate to the data just written to\r
+ * flash. A call to CyFlushCache() is required to invalidate the data in the\r
+ * cache and force fresh information to be loaded from flash.\r
+ ***************************************************************************/\r
+ CyFlushCache();\r
+ #endif /* (CY_PSOC5) */\r
+ return (result);\r
+}\r
+#endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/\r
+/** @} functions_group */\r
\r
/*******************************************************************************\r
* The following code is OBSOLETE and must not be used.\r
\r
#if(CY_PSOC5)\r
/***************************************************************************\r
- * When writing Flash, data in the instruction cache can become stale.\r
+ * When writing to flash, data in the instruction cache can become obsolete.\r
* Therefore, the cache data does not correlate to the data just written to\r
- * Flash. A call to CyFlushCache() is required to invalidate the data in the\r
- * cache and force fresh information to be loaded from Flash.\r
+ * flash. A call to CyFlushCache() is required to invalidate the data in the\r
+ * cache and force fresh information to be loaded from flash.\r
***************************************************************************/\r
CyFlushCache();\r
#endif /* (CY_PSOC5) */\r
}\r
\r
-\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: Bootloadable_1.h\r
-* Version 1.30\r
+/****************************************************************************//**\r
+* \file Bootloadable_1.c\r
+* \version 1.50\r
*\r
-* Description:\r
+* \brief\r
* Provides an API for the Bootloadable application. The API includes a\r
-* single function for starting bootloader.\r
+* single function for starting the Bootloader.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
/* Check to see if required defines such as CY_PSOC5LP are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5LP)\r
- #error Component Bootloadable_v1_30 requires cy_boot v3.0 or later\r
+ #error Component Bootloadable_v1_50 requires cy_boot v3.0 or later\r
#endif /* !defined (CY_PSOC5LP) */\r
\r
\r
\r
\r
/*******************************************************************************\r
-* This variable is used by Bootloader/Bootloadable components to schedule what\r
-* application will be started after software reset.\r
+* This variable is used by the Bootloader/Bootloadable components to schedule which\r
+* application will be started after a software reset.\r
*******************************************************************************/\r
#if (CY_PSOC4)\r
#if defined(__ARMCC_VERSION)\r
\r
\r
/*******************************************************************************\r
-* Get the reason of the device reset\r
+* Gets the reason for a device reset\r
*******************************************************************************/\r
#if(CY_PSOC4)\r
#define Bootloadable_1_RES_CAUSE_RESET_SOFT (0x10u)\r
\r
\r
/*******************************************************************************\r
-* Schedule Bootloader/Bootloadable to be run after software reset\r
+* Schedule the Bootloader/Bootloadable to be run after a software reset.\r
*******************************************************************************/\r
#if(CY_PSOC4)\r
#define Bootloadable_1_SET_RUN_TYPE(x) (cyBtldrRunType = (x))\r
\r
\r
/*******************************************************************************\r
-* The following code is OBSOLETE and must not be used starting from version 1.10\r
+* The following code is OBSOLETE and must not be used starting from version 1.10.\r
*******************************************************************************/\r
#define CYBTDLR_SET_RUN_TYPE(x) Bootloadable_1_SET_RUN_TYPE(x)\r
\r
+/*******************************************************************************\r
+* Bootloadable's declarations for in-app bootloading.\r
+*******************************************************************************/\r
+#define Bootloadable_1_MD_BTLDB_ACTIVE_0 (0x00u)\r
+\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
+ #define Bootloadable_1_MAX_NUM_OF_BTLDB (0x02u)\r
+ #define Bootloadable_1_MD_BTLDB_ACTIVE_1 (0x01u)\r
+ #define Bootloadable_1_MD_BTLDB_ACTIVE_NONE (0x02u)\r
+ #define Bootloadable_1_MD_SIZEOF (64u)\r
+ #define Bootloadable_1_MD_BASE_ADDR(appId) (CYDEV_FLASH_BASE + (CYDEV_FLASH_SIZE - ((uint32)(appId) * CYDEV_FLS_ROW_SIZE) - \\r
+ Bootloadable_1_MD_SIZEOF))\r
+ #define Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(appId) (Bootloadable_1_MD_BASE_ADDR(appId) + 16u)\r
+ \r
+#else\r
+ #define Bootloadable_1_MAX_NUM_OF_BTLDB (0x01u)\r
+#endif /* (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/\r
+\r
+/* Mask used to indicate starting application */\r
+#define Bootloadable_1_SCHEDULE_BTLDB (0x80u)\r
+#define Bootloadable_1_SCHEDULE_BTLDR (0x40u)\r
+#define Bootloadable_1_SCHEDULE_MASK (0xC0u)\r
+/*******************************************************************************\r
+* API prototypes\r
+*******************************************************************************/\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) \r
+ uint8 Bootloadable_1_GetActiveApplication(void) CYSMALL \\r
+ ;\r
+ cystatus Bootloadable_1_SetActiveApplication(uint8 appId) CYSMALL \\r
+ ;\r
+#endif /* (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/\r
\r
/*******************************************************************************\r
* The following code is OBSOLETE and must not be used starting from version 1.20\r
#define Bootloadable_1_APP_ADDRESS uint16\r
#define Bootloadable_1_GET_CODE_WORD(idx) (*((uint32 CYCODE *) (idx)))\r
\r
- /* Offset by 2 from 32 bit start because only need 16 bits */\r
+ /* Offset by 2 from 32 bit start because only 16 bits are needed */\r
#define Bootloadable_1_META_APP_ADDR_OFFSET (3u)\r
#define Bootloadable_1_META_APP_BL_LAST_ROW_OFFSET (7u)\r
#define Bootloadable_1_META_APP_BYTE_LEN_OFFSET (11u)\r
#define Bootloadable_1_SetFlashRunType(runType) \\r
Bootloadable_1_SetFlashByte(Bootloadable_1_MD_APP_RUN_ADDR(0), (runType))\r
\r
-\r
/*******************************************************************************\r
* The following code is OBSOLETE and must not be used.\r
*\r
-* If the obsoleted macro definitions intended for use in the application use the\r
+* If the obsoleted macro definitions are intended for the application, use the\r
* following scheme, redefine your own versions of these definitions:\r
* #ifdef <OBSOLETED_DEFINE>\r
* #undef <OBSOLETED_DEFINE>\r
* #define <OBSOLETED_DEFINE> (<New Value>)\r
* #endif\r
*\r
-* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* NOTE Redefine obsoleted macro definitions with caution. They might still be\r
* used in the application and their modification might lead to unexpected\r
* consequences.\r
*******************************************************************************/\r
define symbol CY_APPL_NUM = 1;\r
define symbol CY_APPL_MAX = 1;\r
define symbol CY_METADATA_SIZE = 64;\r
+define symbol CY_CHECKSUM_EXCLUDE_SIZE = 0;\r
define symbol CY_EE_IN_BTLDR = 0x00;\r
define symbol CY_EE_SIZE = 2048;\r
include "cybootloader.icf";\r
}\r
\r
define symbol CY_FLASH_SIZE = 131072;\r
-define symbol CY_APPL_ORIGIN = 0; \r
+define symbol CY_APPL_ORIGIN = 0;\r
define symbol CY_FLASH_ROW_SIZE = 256;\r
define symbol CY_ECC_ROW_SIZE = 32;\r
\r
}\r
define block APPL with fixed order {readonly section .romvectors, readonly};\r
\r
-/* The address of Flash row next after Bootloader image */\r
+/* The address of the Flash row next after the Bootloader image */\r
define symbol CY_BTLDR_END = CYDEV_BTLDR_SIZE +\r
((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ?\r
(CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0);\r
"readwrite" : place in RAM_region { readwrite };\r
"HSTACK" : place at end of RAM_region { block HSTACK};\r
\r
-keep { section .cybootloader, \r
- section .cyloadermeta, \r
+keep { section .cybootloader,\r
+ section .cyloadermeta,\r
section .cyloadablemeta,\r
- section .cyconfigecc, \r
- section .cycustnvl, \r
+ section .cyconfigecc,\r
+ section .cy_checksum_exclude,\r
+ section .cycustnvl,\r
section .cywolatch,\r
- section .cyeeprom, \r
+ section .cyeeprom,\r
section .cyflashprotect,\r
section .cymeta };\r
\r
-".cyloadermeta" : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };\r
+".cyloadermeta" : place at address mem : ((CY_APPL_LOADER && !CY_APPL_LOADABLE) ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };\r
if (CY_APPL_LOADABLE)\r
{\r
-".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };\r
+".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };\r
}\r
+\r
+\r
+/*******************************************************************************\r
+* Checksum Exclude Section. See cm0gcc.ld on placement details.\r
+*******************************************************************************/\r
+if (CY_APPL_LOADABLE)\r
+{\r
+ /* Align size to the flash row size */\r
+ define symbol CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED = CY_CHECKSUM_EXCLUDE_SIZE + ((CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE)) : 0);\r
+\r
+ if (CY_CHECKSUM_EXCLUDE_SIZE != 0)\r
+ {\r
+\r
+ /* General case */\r
+ if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2))\r
+ {\r
+ define symbol CY_CHECKSUM_EXCLUDE_START = CY_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED;\r
+ }\r
+ else\r
+ {\r
+ define symbol CY_CHECKSUM_EXCLUDE_START = (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED;\r
+ }\r
+\r
+ define symbol CY_CHECKSUM_EXCLUDE_START_ALIGNED = CY_CHECKSUM_EXCLUDE_START + ((CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE)) : 0);\r
+\r
+ ".cy_checksum_exclude" : place at address mem : (CY_CHECKSUM_EXCLUDE_START_ALIGNED) { readonly section .cy_checksum_exclude };\r
+\r
+ } /* (CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED != 0) */\r
+}\r
+else\r
+{\r
+ ".cy_checksum_exclude" : place in ROM_region { readonly section .cy_checksum_exclude };\r
+}\r
+\r
+\r
".cyconfigecc" : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };\r
".cycustnvl" : place at address mem : 0x90000000 { readonly section .cycustnvl };\r
".cywolatch" : place at address mem : 0x90100000 { readonly section .cywolatch };\r
#! armcc -E\r
-; The first line specifies a preprocessor command that the linker invokes \r
+; The first line specifies a preprocessor command that the linker invokes\r
; to pass a scatter file through a C preprocessor.\r
\r
;********************************************************************************\r
-;* File Name: Cm3RealView.scat\r
-;* Version 4.20\r
+;* \file Cm3RealView.scat\r
+;* \version 5.50\r
;*\r
-;* Description:\r
-;* This Linker Descriptor file describes the memory layout of the PSoC5\r
-;* device. The memory layout of the final binary and hex images as well as\r
-;* the placement in PSoC5 memory is described.\r
-;*\r
-;*\r
-;* Note:\r
+;* \brief\r
+;* This Linker Descriptor file describes the memory layout of the PSoC5\r
+;* device. The memory layout of the final binary and hex images as well as\r
+;* the placement in PSoC5 memory is described.\r
;*\r
;* romvectors: Cypress default Interrupt service routine vector table.\r
-;*\r
;* This is the ISR vector table at bootup. Used only for the reset vector.\r
;*\r
-;*\r
;* ramvectors: Cypress ram interrupt service routine vector table.\r
-;*\r
;* This is the ISR vector table used by the application.\r
;*\r
-;*\r
;********************************************************************************\r
-;* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+;* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
;* You may use this file only in accordance with the license, terms, conditions,\r
;* disclaimers, and limitations in the end user license agreement accompanying\r
;* the software package with which this file was provided.\r
#define CY_EE_SIZE 2048\r
#define CY_METADATA_SIZE 64\r
\r
+#define CY_CHECKSUM_EXCLUDE_SIZE AlignExpr(0, CY_FLASH_ROW_SIZE)\r
+#define CY_APPL_NUM 1\r
+#define CY_APPL_MAX 1\r
+\r
\r
; Define application base address\r
-#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)\r
- #define CY_APPL_NUM 1\r
- #define CY_APPL_MAX 1\r
- #define CY_EE_IN_BTLDR 0\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \\r
+ CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
+\r
+ #define CY_EE_IN_BTLDR 0\r
\r
#if CY_APPL_ORIGIN\r
#define APPL1_START CY_APPL_ORIGIN\r
\r
\r
; Place Bootloader at the beginning of Flash\r
-#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \\r
+ CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
\r
CYBOOTLOADER 0\r
{\r
}\r
\r
#if CY_APPL_ORIGIN\r
- ScatterAssert(APPL_START > LoadLimit(CYBOOTLOADER))\r
+ ScatterAssert(APPL_START >= LoadLimit(CYBOOTLOADER))\r
#endif\r
\r
#endif\r
}\r
\r
\r
-#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER)\r
+/*******************************************************************************\r
+* Bootloader Metadata Section. See cm0gcc.ld on placement details.\r
+*******************************************************************************/\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || \\r
+ CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER || \\r
+ CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LAUNCHER)\r
\r
CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE)\r
{\r
.cyloadermeta +0 { * (.cyloadermeta) }\r
}\r
\r
-#else\r
+#endif\r
+\r
+\r
+/*******************************************************************************\r
+* Bootloadable Metadata Section. See cm0gcc.ld on placement details.\r
+*******************************************************************************/\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \\r
+ CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
\r
- #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)\r
+ CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE)\r
+ {\r
+ .cyloadablemeta +0 { * (.cyloadablemeta) }\r
+ }\r
+\r
+#endif\r
+\r
+\r
+/*******************************************************************************\r
+* Checksum Exclude Section. See cm0gcc.ld on placement details.\r
+*******************************************************************************/\r
+#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) || (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))\r
\r
- CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE)\r
+ #if (0 != 0)\r
+\r
+ #if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2))\r
+ #define CY_CHECKSUM_APPL2_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ), CY_FLASH_ROW_SIZE))\r
+ #define CY_CHECKSUM_EXCLUDE_START AlignExpr(CY_CHECKSUM_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE)\r
+ #else\r
+ #define CY_CHECKSUM_EXCLUDE_START AlignExpr((CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE)\r
+ #endif\r
+\r
+ CY_CHECKSUM_EXCLUDE (CY_CHECKSUM_EXCLUDE_START)\r
{\r
- .cyloadablemeta +0 { * (.cyloadablemeta) }\r
+ .cy_checksum_exclude +0\r
+ {\r
+ * (.cy_checksum_exclude)\r
+ }\r
}\r
- \r
- #endif\r
+\r
+ #endif /* (0 != 0) */\r
\r
#endif\r
\r
+\r
#if (CYDEV_ECC_ENABLE == 0)\r
\r
CYCONFIGECC (0x80000000 + ECC_OFFSET)\r
.cymeta +0 { * (.cymeta) }\r
}\r
\r
-#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)\r
+\r
+/*******************************************************************************\r
+* Bootloader Metadata Section. Must be part of the image, but beyond rom memory.\r
+*******************************************************************************/\r
+#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) || (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))\r
\r
CYLOADERMETA +0\r
{\r
-/*******************************************************************************\r
-* File Name: Cm3Start.c\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file Cm3Start.c\r
+* \version 5.50\r
*\r
-* Description:\r
+* \brief\r
* Startup code for the ARM CM3.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#include "CyDmac.h"\r
#include "cyfitter.h"\r
\r
+\r
#define CY_NUM_INTERRUPTS (32u)\r
#define CY_NUM_VECTORS (CYINT_IRQ_BASE + CY_NUM_INTERRUPTS)\r
#define CY_NUM_ROM_VECTORS (4u)\r
#define CY_NVIC_APINT_VECTKEY (0x05FA0000u) /* This key is required in order to write the NVIC_APINT register */\r
#define CY_NVIC_CFG_STACKALIGN (0x00000200u) /* This specifies that the exception stack must be 8 byte aligned */\r
\r
-\r
-/* Extern functions */\r
-extern void CyBtldr_CheckLaunch(void);\r
-\r
-/* Function prototypes */\r
-void initialize_psoc(void);\r
-CY_ISR(IntDefaultHandler);\r
-void Reset(void);\r
-CY_ISR(IntDefaultHandler);\r
-\r
#if defined(__ARMCC_VERSION)\r
#define INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit)\r
#elif defined (__GNUC__)\r
extern int end;\r
#endif /* defined(__GNUC__) */\r
\r
+/* Extern functions */\r
+extern void CyBtldr_CheckLaunch(void);\r
+\r
+/* Function prototypes */\r
+void initialize_psoc(void);\r
+CY_ISR(IntDefaultHandler);\r
+void Reset(void);\r
+\r
/* Global variables */\r
#if !defined (__ICCARM__)\r
CY_NOINIT static uint32 cySysNoInitDataValid;\r
\r
/*******************************************************************************\r
* Function Name: IntDefaultHandler\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function is called for all interrupts, other than a reset that gets\r
* called before the system is setup.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
* Theory:\r
* Any value other than zero is acceptable.\r
*\r
*******************************************************************************/\r
CY_ISR(IntDefaultHandler)\r
{\r
+ /***************************************************************************\r
+ * We must not get here. If we do, a serious problem occurs, so go into\r
+ * an infinite loop.\r
+ ***************************************************************************/\r
\r
- while(1)\r
- {\r
- /***********************************************************************\r
- * We must not get here. If we do, a serious problem occurs, so go\r
- * into an infinite loop.\r
- ***********************************************************************/\r
- }\r
+ #if defined(__GNUC__)\r
+ if (errno == ENOMEM)\r
+ {\r
+ #ifdef CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK\r
+ CyBoot_IntDefaultHandler_Enomem_Exception_Callback();\r
+ #endif /* CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK */\r
+ \r
+ while(1)\r
+ {\r
+ /* Out Of Heap Space\r
+ * This can be increased in the System tab of the Design Wide Resources.\r
+ */\r
+ }\r
+ }\r
+ else\r
+ #endif\r
+ {\r
+ #ifdef CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK\r
+ CyBoot_IntDefaultHandler_Exception_EntryCallback();\r
+ #endif /* CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK */\r
+\r
+ while(1)\r
+ {\r
+\r
+ }\r
+ }\r
}\r
\r
\r
\r
/*******************************************************************************\r
* Function Name: Reset\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function handles the reset interrupt for the RVDS/MDK toolchains.\r
* This is the first bit of code that is executed at startup.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void Reset(void)\r
{\r
- #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)\r
+ #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
\r
/* For PSoC 5LP, debugging is enabled by default */\r
#if(CYDEV_DEBUGGING_ENABLE == 0)\r
*/\r
*(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);\r
\r
- #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */\r
+ #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */\r
\r
- #if(CYDEV_BOOTLOADER_ENABLE)\r
+ #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))\r
CyBtldr_CheckLaunch();\r
- #endif /* (CYDEV_BOOTLOADER_ENABLE) */\r
+ #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */\r
\r
__main();\r
}\r
\r
/*******************************************************************************\r
* Function Name: $Sub$$main\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function is called immediately before the users main\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void $Sub$$main(void)\r
{\r
\r
/*******************************************************************************\r
* Function Name: _exit\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Exit a program without cleaning up files. If your system doesn't provide\r
* this, it is best to avoid linking with subroutines that require it (exit,\r
* system).\r
*\r
-* Parameters:\r
-* status: Status caused program exit.\r
-*\r
-* Return:\r
-* None\r
+* \param status: Status caused program exit.\r
*\r
*******************************************************************************/\r
__attribute__((weak))\r
void _exit(int status)\r
{\r
- /* Cause divide by 0 exception */\r
- int x = status / (int) INT_MAX;\r
- x = 4 / x;\r
-\r
+ CyHalt((uint8) status);\r
while(1)\r
{\r
\r
\r
/*******************************************************************************\r
* Function Name: _sbrk\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Increase program data space. As malloc and related functions depend on this,\r
* it is useful to have a working implementation. The following suffices for a\r
* standalone system; it exploits the symbol end automatically defined by the\r
* GNU linker.\r
*\r
-* Parameters:\r
-* nbytes: The number of bytes requested (if the parameter value is positive)\r
+* \param nbytes: The number of bytes requested (if the parameter value is positive)\r
* from the heap or returned back to the heap (if the parameter value is\r
* negative).\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
__attribute__((weak))\r
void * _sbrk (int nbytes)\r
\r
/*******************************************************************************\r
* Function Name: Reset\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function handles the reset interrupt for the GCC toolchain. This is the\r
* first bit of code that is executed at startup.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void Reset(void)\r
{\r
- #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)\r
+ #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
\r
/* For PSoC 5LP, debugging is enabled by default */\r
#if(CYDEV_DEBUGGING_ENABLE == 0)\r
*/\r
*(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);\r
\r
- #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */\r
+ #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */\r
\r
- #if(CYDEV_BOOTLOADER_ENABLE)\r
+ #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))\r
CyBtldr_CheckLaunch();\r
- #endif /* (CYDEV_BOOTLOADER_ENABLE) */\r
+ #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */\r
\r
Start_c();\r
}\r
\r
/*******************************************************************************\r
* Function Name: Start_c\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function handles initializing the .data and .bss sections in\r
* preparation for running the standard C code. Once initialization is complete\r
* it will call main(). This function will never return.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void Start_c(void) __attribute__ ((noreturn));\r
void Start_c(void)\r
\r
/*******************************************************************************\r
* Function Name: __low_level_init\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function performs early initializations for the IAR Embedded\r
* Workbench IDE. It is executed in the context of a reset interrupt handler\r
* before the data sections are initialized.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* The value that determines whether or not data sections should be initialized\r
* by the system startup code:\r
* 0 - skip data sections initialization;\r
*******************************************************************************/\r
int __low_level_init(void)\r
{\r
- #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)\r
+ #if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)\r
\r
/* For PSoC 5LP, debugging is enabled by default */\r
#if(CYDEV_DEBUGGING_ENABLE == 0)\r
*/\r
*(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);\r
\r
- #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */\r
+ #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */\r
\r
- #if (CYDEV_BOOTLOADER_ENABLE)\r
+ #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER))\r
CyBtldr_CheckLaunch();\r
- #endif /* CYDEV_BOOTLOADER_ENABLE */\r
+ #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */\r
\r
/* Initialize data sections */\r
__iar_data_init3();\r
\r
/*******************************************************************************\r
* Function Name: initialize_psoc\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function used to initialize the PSoC chip before calling main.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
#if (defined(__GNUC__) && !defined(__ARMCC_VERSION))\r
__attribute__ ((constructor(101)))\r
-/*******************************************************************************\r
-* File Name: CyBootAsmGnu.s\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file CyBootAsmGnu.s\r
+* \version 5.50\r
*\r
-* Description:\r
+* \brief\r
* Assembly routines for GNU as.\r
*\r
********************************************************************************\r
-* Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2010-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: CyDelayCycles\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Delays for the specified number of cycles.\r
*\r
-* Parameters:\r
-* uint32 cycles: number of cycles to delay.\r
-*\r
-* Return:\r
-* None\r
+* \param uint32 cycles: number of cycles to delay.\r
*\r
*******************************************************************************/\r
/* void CyDelayCycles(uint32 cycles) */\r
\r
/*******************************************************************************\r
* Function Name: CyEnterCriticalSection\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* CyEnterCriticalSection disables interrupts and returns a value indicating\r
* whether interrupts were previously enabled (the actual value depends on\r
* whether the device is PSoC 3 or PSoC 5).\r
* corrupting processor state, it must be the policy that all interrupt routines\r
* restore the interrupt enable bits as they were found on entry.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* uint8\r
* Returns 0 if interrupts were previously enabled or 1 if interrupts\r
* were previously disabled.\r
\r
/*******************************************************************************\r
* Function Name: CyExitCriticalSection\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* CyExitCriticalSection re-enables interrupts if they were enabled before\r
* CyEnterCriticalSection was called. The argument should be the value returned\r
* from CyEnterCriticalSection.\r
*\r
-* Parameters:\r
-* uint8 savedIntrStatus:\r
+* \param uint8 savedIntrStatus:\r
* Saved interrupt status returned by the CyEnterCriticalSection function.\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
/* void CyExitCriticalSection(uint8 savedIntrStatus) */\r
.global CyExitCriticalSection\r
;-------------------------------------------------------------------------------\r
; FILENAME: CyBootAsmIar.s\r
-; Version 4.20\r
+; Version 5.50\r
;\r
; DESCRIPTION:\r
; Assembly routines for IAR Embedded Workbench IDE.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright 2013-2015, Cypress Semiconductor Corporation. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions,\r
; disclaimers, and limitations in the end user license agreement accompanying\r
; the software package with which this file was provided.\r
;-------------------------------------------------------------------------------\r
; FILENAME: CyBootAsmRv.s\r
-; Version 4.20\r
+; Version 5.50\r
;\r
; DESCRIPTION:\r
; Assembly routines for RealView.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright 2010-2015, Cypress Semiconductor Corporation. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions,\r
; disclaimers, and limitations in the end user license agreement accompanying\r
; the software package with which this file was provided.\r
-/*******************************************************************************\r
-* File Name: CyDmac.c\r
-* Version 4.20\r
-*\r
-* Description:\r
-* Provides an API for the DMAC component. The API includes functions for the\r
-* DMA controller, DMA channels and Transfer Descriptors.\r
+/***************************************************************************//**\r
+* \file CyDmac.c\r
+* \version 5.50\r
*\r
-* This API is the library version not the auto generated code that gets\r
-* generated when the user places a DMA component on the schematic.\r
+* \brief\r
+* Provides an API for the DMAC component. The API includes functions for the\r
+* DMA controller, DMA channels and Transfer Descriptors. This API is the library\r
+* version not the auto generated code that gets generated when the user places a\r
+* DMA component on the schematic.\r
*\r
-* The auto generated code would use the APi's in this module.\r
+* The auto generated code would use the APi's in this module.\r
*\r
-* Note:\r
-* This code is endian agnostic.\r
+* \note This code is endian agnostic.\r
*\r
-* The Transfer Descriptor memory can be used as regular memory if the TD's are\r
-* not being used.\r
+* \note The Transfer Descriptor memory can be used as regular memory if the\r
+* TD's are not being used.\r
*\r
-* This code uses the first byte of each TD to manage the free list of TD's.\r
-* The user can overwrite this once the TD is allocated.\r
+* \note This code uses the first byte of each TD to manage the free list of\r
+* TD's. The user can overwrite this once the TD is allocated.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: CyDmacConfigure\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Creates a linked list of all the TDs to be allocated. This function is called\r
-* by the startup code; you do not normally need to call it. You can call this\r
-* function if all of the DMA channels are inactive.\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
+* Creates a linked list of all the TDs to be allocated. This function is called\r
+* by the startup code; you do not normally need to call it. You can call this\r
+* function if all of the DMA channels are inactive.\r
*\r
*******************************************************************************/\r
void CyDmacConfigure(void) \r
\r
/*******************************************************************************\r
* Function Name: CyDmacError\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Returns errors of the last failed DMA transaction.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* Errors of the last failed DMA transaction.\r
+* \return Errors of the last failed DMA transaction.\r
*\r
* DMAC_PERIPH_ERR:\r
* Set to 1 when a peripheral responds to a bus transaction with an error\r
* are determined by the BUS_TIMEOUT field in the PHUBCFG register.\r
*\r
* Theory:\r
-* Once an error occurs the error bits are sticky and are only cleared by \r
+* Once an error occurs the error bits are sticky and are only cleared by\r
* writing 1 to the error register.\r
*\r
*******************************************************************************/\r
uint8 CyDmacError(void) \r
{\r
- return((uint8)(((uint32) 0x0Fu) & *CY_DMA_ERR_PTR));\r
+ return((uint8)(((uint32) 0x0Eu) & *CY_DMA_ERR_PTR));\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: CyDmacClearError\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Clears the error bits in the error register of the DMAC.\r
*\r
-* Parameters:\r
-* error:\r
+* \param error:\r
* Clears the error bits in the DMAC error register.\r
*\r
-* DMAC_PERIPH_ERR:\r
+* \param DMAC_PERIPH_ERR:\r
* Set to 1 when a peripheral responds to a bus transaction with an error\r
* response.\r
*\r
-* DMAC_UNPOP_ACC:\r
+* \param DMAC_UNPOP_ACC:\r
* Set to 1 when an access is attempted to an invalid address.\r
*\r
-* DMAC_BUS_TIMEOUT:\r
+* \param DMAC_BUS_TIMEOUT:\r
* Set to 1 when a bus timeout occurs. Cleared by writing 1. Timeout values\r
* are determined by the BUS_TIMEOUT field in the PHUBCFG register.\r
*\r
-* Return:\r
-* None\r
-*\r
* Theory:\r
-* Once an error occurs the error bits are sticky and are only cleared by \r
+* Once an error occurs the error bits are sticky and are only cleared by\r
* writing 1 to the error register.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyDmacErrorAddress\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* When DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC, and DMAC_PERIPH_ERR occur the\r
* address of the error is written to the error address register and can be read\r
* with this function.\r
*\r
* If there are multiple errors, only the address of the first is saved.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* The address that caused the error.\r
+* \return The address that caused the error.\r
*\r
*******************************************************************************/\r
uint32 CyDmacErrorAddress(void) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaChAlloc\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Allocates a channel from the DMAC to be used in all functions that require a\r
* channel handle.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* The allocated channel number. Zero is a valid channel number.\r
+* \return The allocated channel number. Zero is a valid channel number.\r
* DMA_INVALID_CHANNEL is returned if there are no channels available.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyDmaChFree\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Frees a channel allocated by DmaChAlloc().\r
+* Frees a channel allocated by \ref DmaChAlloc().\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* The handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+* \param chHandle The handle previously returned by \ref CyDmaChAlloc() or \ref\r
+* DMA_DmaInitalize().\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChFree(uint8 chHandle) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaChEnable\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the DMA channel. A software or hardware request still must happen\r
* before the channel is executed.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref\r
+* DMA_DmaInitalize().\r
*\r
-* uint8 preserveTds:\r
-* Preserves the original TD state when the TD has completed. This parameter\r
-* applies to all TDs in the channel.\r
+* \param preserveTds Preserves the original TD state when the TD has completed.\r
+* This parameter applies to all TDs in the channel.\r
*\r
* 0 - When TD is completed, the DMAC leaves the TD configuration values in\r
* their current state, and does not restore them to their original state.\r
* if you are using CH06 and preserveTds is set, you are not allowed to use TD\r
* slot 6. That is reclaimed by the DMA engine for its private use.\r
*\r
-* Note Do not chain back to a completed TD if the preserveTds for the channel\r
+* \note Do not chain back to a completed TD if the preserveTds for the channel\r
* is set to 0. When a TD has completed preserveTds for the channel set to 0,\r
* the transfer count will be at 0. If a TD with a transfer count of 0 is\r
* started, the TD will transfer an indefinite amount of data.\r
* Take extra precautions when using the hardware request (DRQ) option when the\r
* preserveTds is set to 0, as you might be requesting the wrong data.\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaChDisable\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Disables the DMA channel. Once this function is called, CyDmaChStatus() may\r
-* be called to determine when the channel is disabled and which TDs were being\r
-* executed.\r
+* Disables the DMA channel. Once this function is called, CyDmaChStatus() may\r
+* be called to determine when the channel is disabled and which TDs were being\r
+* executed.\r
*\r
-* If it is currently executing it will allow the current burst to finish\r
-* naturally.\r
+* If it is currently executing it will allow the current burst to finish\r
+* naturally.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref\r
+* DMA_DmaInitalize().\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChDisable(uint8 chHandle) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaClearPendingDrq\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Clears pending the DMA data request.\r
+* Clears pending the DMA data request.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* Handle to the dma channel.\r
+* \param chHandle Handle to the dma channel.\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaClearPendingDrq(uint8 chHandle) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaChPriority\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the priority of a DMA channel. You can use this function when you want\r
* to change the priority at run time. If the priority remains the same for a\r
* DMA channel, then you can configure the priority in the .cydwr file.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref\r
+* DMA_DmaInitalize().\r
*\r
-* uint8 priority:\r
-* Priority to set the channel to, 0 - 7.\r
+* \param priority Priority to set the channel to, 0 - 7.\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaChSetExtendedAddress\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the high 16 bits of the source and destination addresses for the DMA\r
* channel (valid for all TDs in the chain).\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref\r
+* DMA_DmaInitalize().\r
*\r
-* uint16 source:\r
-* Upper 16 bit address of the DMA transfer source.\r
+* \param source Upper 16 bit address of the DMA transfer source.\r
*\r
-* uint16 destination:\r
-* Upper 16 bit address of the DMA transfer destination.\r
+* \param destination Upper 16 bit address of the DMA transfer destination.\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination) \\r
\r
/*******************************************************************************\r
* Function Name: CyDmaChSetInitialTd\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Sets the initial TD to be executed for the channel when the CyDmaChEnable()\r
-* function is called.\r
+* Sets the initial TD to be executed for the channel when the \ref CyDmaChEnable()\r
+* function is called.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().\r
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or\r
+* \ref DMA_DmaInitialize().\r
*\r
-* uint8 startTd:\r
-* Set the TD index as the first TD associated with the channel. Zero is\r
-* a valid TD index.\r
+* \param startTd Set the TD index as the first TD associated with the\r
+* channel. Zero is a valid TD index.\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaChSetRequest\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Allows the caller to terminate a chain of TDs, terminate one TD, or create a\r
* direct request to start the DMA channel.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
-*\r
-* uint8 request:\r
-* One of the following constants. Each of the constants is a three-bit value.\r
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref\r
+* DMA_DmaInitalize().\r
*\r
+* \param request One of the following constants. Each of the constants is a\r
+* three-bit value.\r
* CPU_REQ - Create a direct request to start the DMA channel\r
* CPU_TERM_TD - Terminate one TD\r
* CPU_TERM_CHAIN - Terminate a chain of TDs\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaChGetRequest\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* This function allows the caller of CyDmaChSetRequest() to determine if the\r
-* request was completed.\r
+* This function allows the caller of \ref CyDmaChSetRequest() to determine if the\r
+* request was completed.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref\r
+* DMA_DmaInitalize().\r
*\r
-* Return:\r
-* Returns a three-bit field, corresponding to the three bits of the request,\r
-* which describes the state of the previously posted request. If the value is\r
-* zero, the request was completed. CY_DMA_INVALID_CHANNEL if the handle is\r
-* invalid.\r
+* \return Returns a three-bit field, corresponding to the three bits of the\r
+* request, which describes the state of the previously posted request. If the\r
+* value is zero, the request was completed. CY_DMA_INVALID_CHANNEL if the handle\r
+* is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChGetRequest(uint8 chHandle) \r
\r
/*******************************************************************************\r
* Function Name: CyDmaChStatus\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Determines the status of the DMA channel.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref\r
+* DMA_DmaInitalize().\r
*\r
-* uint8 * currentTd:\r
-* The address to store the index of the current TD. Can be NULL if the value\r
-* is not needed.\r
+* \param currentTd The address to store the index of the current TD. Can be NULL\r
+* if the value is not needed.\r
*\r
-* uint8 * state:\r
-* The address to store the state of the channel. Can be NULL if the value is\r
-* not needed.\r
+* \param state The address to store the state of the channel. Can be NULL if the\r
+* value is not needed.\r
*\r
* STATUS_TD_ACTIVE\r
-* 0: Channel is not currently being serviced by DMAC\r
-* 1: Channel is currently being serviced by DMAC\r
+* \param 0: Channel is not currently being serviced by DMAC\r
+* \param 1: Channel is currently being serviced by DMAC\r
*\r
* STATUS_CHAIN_ACTIVE\r
-* 0: TD chain is inactive; either no DMA requests have triggered a new chain\r
+* \param 0: TD chain is inactive; either no DMA requests have triggered a new chain\r
* or the previous chain has completed.\r
-* 1: TD chain has been triggered by a DMA request\r
+* \param 1: TD chain has been triggered by a DMA request\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return CYRET_SUCCESS if successful.\r
+* \return CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
* Theory:\r
* The caller can check on the activity of the Current TD and the Chain.\r
\r
/*******************************************************************************\r
* Function Name: CyDmaChSetConfiguration\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets configuration information of the channel.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
+* \param uint8 chHandle:\r
* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().\r
*\r
-* uint8 burstCount:\r
+* \param uint8 burstCount:\r
* Specifies the size of bursts (1 to 127) the data transfer should be divided\r
* into. If this value is zero then the whole transfer is done in one burst.\r
*\r
-* uint8 requestPerBurst:\r
+* \param uint8 requestPerBurst:\r
* The whole of the data can be split into multiple bursts, if this is\r
-* required to complete the transaction:\r
-* 0: All subsequent bursts after the first burst will be automatically\r
+* \param required to complete the transaction:\r
+* \param 0: All subsequent bursts after the first burst will be automatically\r
* requested and carried out\r
-* 1: All subsequent bursts after the first burst must also be individually\r
+* \param 1: All subsequent bursts after the first burst must also be individually\r
* requested.\r
*\r
-* uint8 tdDone0:\r
+* \param uint8 tdDone0:\r
* Selects one of the TERMOUT0 interrupt lines to signal completion. The line\r
* connected to the nrq terminal will determine the TERMOUT0_SEL definition and\r
* should be used as supplied by cyfitter.h\r
*\r
-* uint8 tdDone1:\r
+* \param uint8 tdDone1:\r
* Selects one of the TERMOUT1 interrupt lines to signal completion. The line\r
* connected to the nrq terminal will determine the TERMOUT1_SEL definition and\r
* should be used as supplied by cyfitter.h\r
*\r
-* uint8 tdStop:\r
+* \param uint8 tdStop:\r
* Selects one of the TERMIN interrupt lines to signal to the DMAC that the TD\r
* should terminate. The signal connected to the trq terminal will determine\r
* which TERMIN (termination request) is used.\r
*\r
-* Return:\r
+* \return\r
* CYRET_SUCCESS if successful.\r
* CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyDmaTdAllocate\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Allocates a TD for use with an allocated DMA channel.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* Zero-based index of the TD to be used by the caller. Since there are 128 TDs\r
* minus the reserved TDs (0 to 23), the value returned would range from 24 to\r
* 127 not 24 to 128. DMA_INVALID_TD is returned if there are no free TDs\r
\r
/*******************************************************************************\r
* Function Name: CyDmaTdFree\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Returns a TD to the free list.\r
*\r
-* Parameters:\r
-* uint8 tdHandle:\r
+* \param uint8 tdHandle:\r
* The TD handle returned by the CyDmaTdAllocate().\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyDmaTdFree(uint8 tdHandle) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyDmaTdFreeCount\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Returns the number of free TDs available to be allocated.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* The number of free TDs.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyDmaTdSetConfiguration\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Configures the TD.\r
*\r
-* Parameters:\r
-* uint8 tdHandle:\r
+* \param uint8 tdHandle:\r
* A handle previously returned by CyDmaTdAlloc().\r
*\r
-* uint16 transferCount:\r
+* \param uint16 transferCount:\r
* The size of the data transfer (in bytes) for this TD. A size of zero will\r
* cause the transfer to continue indefinitely. This parameter is limited to\r
* 4095 bytes; the TD is not initialized at all when a higher value is passed.\r
*\r
-* uint8 nextTd:\r
+* \param uint8 nextTd:\r
* Zero based index of the next Transfer Descriptor in the TD chain. Zero is a\r
* valid pointer to the next TD; DMA_END_CHAIN_TD is the end of the chain.\r
* DMA_DISABLE_TD indicates an end to the chain and the DMA is disabled. No\r
* further TDs are fetched. DMA_DISABLE_TD is only supported on PSoC3 and\r
* PSoC 5LP silicons.\r
*\r
-* uint8 configuration:\r
+* \param uint8 configuration:\r
* Stores the Bit field of configuration bits.\r
*\r
* CY_DMA_TD_SWAP_EN - Perform endian swap\r
* CY_DMA_TD_INC_SRC_ADR - Increment SRC_ADR according to the size of each\r
* data transaction in the burst.\r
*\r
-* Return:\r
+* \return\r
* CYRET_SUCCESS if successful.\r
* CYRET_BAD_PARAM if tdHandle or transferCount is invalid.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyDmaTdGetConfiguration\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Retrieves the configuration of the TD. If a NULL pointer is passed as a\r
* parameter, that parameter is skipped. You may request only the values you are\r
* interested in.\r
*\r
-* Parameters:\r
-* uint8 tdHandle:\r
+* \param uint8 tdHandle:\r
* A handle previously returned by CyDmaTdAlloc().\r
*\r
-* uint16 * transferCount:\r
+* \param uint16 * transferCount:\r
* The address to store the size of the data transfer (in bytes) for this TD.\r
* A size of zero could indicate that the TD has completed its transfer, or\r
* that the TD is doing an indefinite transfer.\r
*\r
-* uint8 * nextTd:\r
+* \param uint8 * nextTd:\r
* The address to store the index of the next TD in the TD chain.\r
*\r
-* uint8 * configuration:\r
+* \param uint8 * configuration:\r
* The address to store the Bit field of configuration bits.\r
* See CyDmaTdSetConfiguration() function description.\r
*\r
-* Return:\r
+* \return\r
* CYRET_SUCCESS if successful.\r
* CYRET_BAD_PARAM if tdHandle is invalid.\r
*\r
-* Side Effects:\r
+* \sideeffect\r
* If TD has a transfer count of N and is executed, the transfer count becomes\r
* 0. If it is reexecuted, the Transfer count of zero will be interpreted as a\r
* request for indefinite transfer. Be careful when requesting TD with a\r
\r
/*******************************************************************************\r
* Function Name: CyDmaTdSetAddress\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the lower 16 bits of the source and destination addresses for this TD\r
* only.\r
*\r
-* Parameters:\r
-* uint8 tdHandle:\r
+* \param uint8 tdHandle:\r
* A handle previously returned by CyDmaTdAlloc().\r
*\r
-* uint16 source:\r
+* \param uint16 source:\r
* The lower 16 address bits of the source of the data transfer.\r
*\r
-* uint16 destination:\r
+* \param uint16 destination:\r
* The lower 16 address bits of the destination of the data transfer.\r
*\r
-* Return:\r
+* \return\r
* CYRET_SUCCESS if successful.\r
* CYRET_BAD_PARAM if tdHandle is invalid.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyDmaTdGetAddress\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Retrieves the lower 16 bits of the source and/or destination addresses for\r
* this TD only. If NULL is passed for a pointer parameter, that value is\r
* skipped. You may request only the values of interest.\r
*\r
-* Parameters:\r
-* uint8 tdHandle:\r
+* \param uint8 tdHandle:\r
* A handle previously returned by CyDmaTdAlloc().\r
*\r
-* uint16 * source:\r
+* \param uint16 * source:\r
* The address to store the lower 16 address bits of the source of the data\r
* transfer.\r
*\r
-* uint16 * destination:\r
+* \param uint16 * destination:\r
* The address to store the lower 16 address bits of the destination of the\r
* data transfer.\r
*\r
-* Return:\r
+* \return\r
* CYRET_SUCCESS if successful.\r
* CYRET_BAD_PARAM if tdHandle is invalid.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyDmaChRoundRobin\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Either enables or disables the Round-Robin scheduling enforcement algorithm.\r
-* Within a priority level a Round-Robin fairness algorithm is enforced.\r
+* Either enables or disables the Round-Robin scheduling enforcement algorithm.\r
+* Within a priority level a Round-Robin fairness algorithm is enforced.\r
*\r
-* Parameters:\r
-* uint8 chHandle:\r
-* A handle previously returned by CyDmaChAlloc() or Dma_DmaInitialize().\r
+* \param uint8 chHandle:\r
+* A handle previously returned by CyDmaChAlloc() or Dma_DmaInitialize().\r
*\r
-* uint8 enableRR:\r
-* 0: Disable Round-Robin fairness algorithm\r
-* 1: Enable Round-Robin fairness algorithm\r
+* \param uint8 enableRR:\r
+* \param 0: Disable Round-Robin fairness algorithm\r
+* \param 1: Enable Round-Robin fairness algorithm\r
*\r
-* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_BAD_PARAM if chHandle is invalid.\r
+* \return\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if chHandle is invalid.\r
*\r
*******************************************************************************/\r
cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) \r
-/*******************************************************************************\r
-* File Name: CyDmac.h\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file CyDmac.h\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides the function definitions for the DMA Controller.\r
+* \brief Provides the function definitions for the DMA Controller.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the\r
-* System Reference Guide provided with PSoC Creator.\r
+* \note Documentation of the API's in this file is located in the System\r
+* Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
-/*******************************************************************************\r
-* File Name: CyFlash.c\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file CyFlash.c\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides an API for the FLASH/EEPROM.\r
+* \brief Provides an API for the FLASH/EEPROM.\r
*\r
-* Note:\r
-* This code is endian agnostic.\r
+* \note This code is endian agnostic.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the\r
-* System Reference Guide provided with PSoC Creator.\r
+* \note Documentation of the API's in this file is located in the System\r
+* Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: CyFlash_Start\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enable the Flash.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyFlash_Start(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyFlash_Stop\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disable the Flash.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* This setting is ignored as long as the CPU is currently running. This will\r
* only take effect when the CPU is later disabled.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CySetTempInt\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sends a command to the SPC to read the die temperature. Sets a global value\r
* used by the Write function. This function must be called once before\r
* executing a series of Flash writing functions.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* status:\r
* CYRET_SUCCESS - if successful\r
* CYRET_LOCKED - if Flash writing already in use\r
\r
/*******************************************************************************\r
* Function Name: CyFlashGetSpcAlgorithm\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sends a command to the SPC to download code into RAM.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* status:\r
* CYRET_SUCCESS - if successful\r
* CYRET_LOCKED - if Flash writing already in use\r
\r
/*******************************************************************************\r
* Function Name: CySetTemp\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This is a wraparound for CySetTempInt(). It is used to return the second\r
* successful read of the temperature value.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* status:\r
* CYRET_SUCCESS if successful.\r
* CYRET_LOCKED if Flash writing already in use\r
\r
/*******************************************************************************\r
* Function Name: CySetFlashEEBuffer\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the user supplied temporary buffer to store SPC data while performing\r
-* Flash and EEPROM commands. This buffer is only necessary when the Flash ECC is\r
-* disabled.\r
+* Flash and EEPROM commands. This buffer is only necessary when the Flash ECC\r
+* is disabled.\r
*\r
-* Parameters:\r
-* buffer:\r
-* The address of a block of memory to store temporary memory. The size of the block\r
-* of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.\r
+* \param buffer:\r
+* The address of a block of memory to store temporary memory. The size of the\r
+* block of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.\r
*\r
-* Return:\r
+* \return\r
* status:\r
* CYRET_SUCCESS if successful.\r
* CYRET_BAD_PARAM if the buffer is NULL\r
\r
/*******************************************************************************\r
* Function Name: CyWriteRowData\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sends a command to the SPC to load and program a row of data in\r
* Flash or EEPROM.\r
*\r
-* Parameters:\r
-* arrayID: ID of the array to write.\r
+* \param arrayID: ID of the array to write.\r
* The type of write, Flash or EEPROM, is determined from the array ID.\r
* The arrays in the part are sequential starting at the first ID for the\r
* specific memory type. The array ID for the Flash memory lasts from 0x00 to\r
* 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.\r
-* rowAddress: rowAddress of flash row to program.\r
-* rowData: Array of bytes to write.\r
+* \param rowAddress: rowAddress of flash row to program.\r
+* \param rowData: Array of bytes to write.\r
*\r
-* Return:\r
+* \return\r
* status:\r
* CYRET_SUCCESS if successful.\r
* CYRET_LOCKED if the SPC is already in use.\r
\r
/*******************************************************************************\r
* Function Name: CyWriteRowConfig\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
- * Sends a command to the SPC to load and program a row of config data in the Flash.\r
- * This function is only valid for Flash array IDs (not for EEPROM).\r
+ * Sends a command to the SPC to load and program a row of config data in the\r
+ * Flash. This function is only valid for Flash array IDs (not for EEPROM).\r
*\r
- * Parameters:\r
- * arrayId: ID of the array to write\r
+ * \param arrayId: ID of the array to write\r
* The arrays in the part are sequential starting at the first ID for the\r
* specific memory type. The array ID for the Flash memory lasts\r
* from 0x00 to 0x3F.\r
- * rowAddress: The address of the sector to erase.\r
- * rowECC: The array of bytes to write.\r
+ * \param rowAddress: The address of the sector to erase.\r
+ * \param rowECC: The array of bytes to write.\r
*\r
- * Return:\r
+ * \return\r
* status:\r
* CYRET_SUCCESS if successful.\r
* CYRET_LOCKED if the SPC is already in use.\r
\r
/*******************************************************************************\r
* Function Name: CyWriteRowFull\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Sends a command to the SPC to load and program a row of data in the Flash.\r
* rowData array is expected to contain Flash and ECC data if needed.\r
*\r
-* Parameters:\r
-* arrayId: FLASH or EEPROM array id.\r
-* rowData: Pointer to a row of data to write.\r
-* rowNumber: Zero based number of the row.\r
-* rowSize: Size of the row.\r
+* \param arrayId: FLASH or EEPROM array id.\r
+* \param rowData: Pointer to a row of data to write.\r
+* \param rowNumber: Zero based number of the row.\r
+* \param rowSize: Size of the row.\r
*\r
-* Return:\r
+* \return\r
* CYRET_SUCCESS if successful.\r
* CYRET_LOCKED if the SPC is already in use.\r
* CYRET_CANCELED if command not accepted\r
\r
/*******************************************************************************\r
* Function Name: CyFlash_SetWaitCycles\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the number of clock cycles the cache will wait before it samples data\r
-* coming back from the Flash. This function must be called before increasing the CPU\r
-* clock frequency. It can optionally be called after lowering the CPU clock\r
-* frequency in order to improve the CPU performance.\r
+* coming back from the Flash. This function must be called before increasing\r
+* the CPU clock frequency. It can optionally be called after lowering the CPU\r
+* clock frequency in order to improve the CPU performance.\r
*\r
-* Parameters:\r
-* uint8 freq:\r
+* \param uint8 freq:\r
* Frequency of operation in Megahertz.\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyFlash_SetWaitCycles(uint8 freq) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyEEPROM_Start\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enable the EEPROM.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyEEPROM_Start(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyEEPROM_Stop\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disable the EEPROM.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyEEPROM_Stop (void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyEEPROM_ReadReserve\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Request access to the EEPROM for reading and wait until access is available.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyEEPROM_ReadReserve(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyEEPROM_ReadRelease\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Release the read reservation of the EEPROM.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyEEPROM_ReadRelease(void) \r
{\r
-/*******************************************************************************\r
-* File Name: CyFlash.h\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file CyFlash.h\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides the function definitions for the FLASH/EEPROM.\r
+* \brief Provides the function definitions for the FLASH/EEPROM.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the\r
-* System Reference Guide provided with PSoC Creator.\r
+* \note Documentation of the API's in this file is located in the System\r
+* Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#endif /* (CYDEV_ECC_ENABLE == 0) */\r
#define CY_EEPROM_BASE (CYDEV_EE_BASE)\r
#define CY_EEPROM_SIZE (CYDEV_EE_SIZE)\r
-#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EEPROM_SECTOR_SIZE)\r
+#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EE_SIZE) /* EEPROM has one array */\r
#define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE)\r
#define CY_EEPROM_NUMBER_ROWS (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE)\r
#define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY)\r
#define FLASH_NUMBER_ROWS (CY_FLASH_NUMBER_ROWS)\r
#define FLASH_NUMBER_SECTORS (CY_FLASH_NUMBER_ARRAYS)\r
#define EEPROM_SIZE (CY_EEPROM_SIZE)\r
-#define EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY)\r
+#define EEPROM_SIZEOF_SECTOR (CYDEV_EEPROM_SECTOR_SIZE)\r
#define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS)\r
-#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS)\r
+#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_SECTORS)\r
\r
\r
/*******************************************************************************\r
-/*******************************************************************************\r
-* File Name: CyLib.c\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file CyLib.c\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides a system API for the clocking, interrupts and watchdog timer.\r
+* \brief Provides a system API for the clocking, interrupts and watchdog timer.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the\r
-* System Reference Guide provided with PSoC Creator.\r
+* \note Documentation of the API's in this file is located in the System\r
+* Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
static void CyBusClk_Internal_SetDivider(uint16 divider);\r
\r
#if(CY_PSOC5)\r
- static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];\r
+ static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];\r
static void CySysTickServiceCallbacks(void);\r
uint32 CySysTickInitVar = 0u;\r
#endif /* (CY_PSOC5) */\r
\r
\r
+#if(CY_PSOC3)\r
+ CY_ISR_PROTO(IntDefaultHandler);\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
/*******************************************************************************\r
* Function Name: CyPLL_OUT_Start\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the PLL. Optionally waits for it to become stable.\r
* Waits at least 250 us or until it is detected that the PLL is stable.\r
*\r
-* Parameters:\r
-* wait:\r
-* 0: Return immediately after configuration\r
-* 1: Wait for PLL lock or timeout.\r
+* \param wait:\r
+* \param 0: Return immediately after configuration\r
+* \param 1: Wait for PLL lock or timeout.\r
*\r
-* Return:\r
+* \return\r
* Status\r
* CYRET_SUCCESS - Completed successfully\r
* CYRET_TIMEOUT - Timeout occurred without detecting a stable clock.\r
* may not occur. However, after the timeout has expired the generated PLL\r
* clock can still be used.\r
*\r
-* Side Effects:\r
+* \sideeffect\r
* If wait is enabled: This function uses the Fast Time Wheel to time the wait.\r
* Any other use of the Fast Time Wheel will be stopped during the period of\r
* this function and then restored. This function also uses the 100 KHz ILO.\r
\r
/*******************************************************************************\r
* Function Name: CyPLL_OUT_Stop\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the PLL.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyPLL_OUT_Stop(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyPLL_OUT_SetPQ\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the P and Q dividers and the charge pump current.\r
* The Frequency Out will be P/Q * Frequency In.\r
* The PLL must be disabled before calling this function.\r
*\r
-* Parameters:\r
-* uint8 pDiv:\r
+* \param uint8 pDiv:\r
* Valid range [8 - 255].\r
*\r
-* uint8 qDiv:\r
+* \param uint8 qDiv:\r
* Valid range [1 - 16]. Input Frequency / Q must be in range of 1 to 3 MHz.\r
\r
-* uint8 current:\r
+* \param uint8 current:\r
* Valid range [1 - 7]. Charge pump current in uA. Refer to the device TRM and\r
* datasheet for more information.\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* If this function execution results in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with an appropriate parameter. It can be optionally called if the CPU clock\r
-* frequency is lowered in order to improve the CPU performance.\r
-* See CyFlash_SetWaitCycles() description for more information.\r
+* coming back from the Flash must be adjusted by calling\r
+* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally\r
+* called if the CPU clock frequency is lowered in order to improve the CPU\r
+* performance. See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) \r
\r
/*******************************************************************************\r
* Function Name: CyPLL_OUT_SetSource\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the input clock source to the PLL. The PLL must be disabled before\r
* calling this function.\r
*\r
-* Parameters:\r
-* source: One of the three available PLL clock sources\r
-* CY_PLL_SOURCE_IMO : IMO\r
-* CY_PLL_SOURCE_XTAL : MHz Crystal\r
-* CY_PLL_SOURCE_DSI : DSI\r
-*\r
-* Return:\r
-* None\r
+* \param source: One of the three available PLL clock sources\r
+* \param CY_PLL_SOURCE_IMO : IMO\r
+* \param CY_PLL_SOURCE_XTAL : MHz Crystal\r
+* \param CY_PLL_SOURCE_DSI : DSI\r
*\r
-* Side Effects:\r
+* \sideeffect\r
* If this function execution results in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from the3 Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with an appropriate parameter. It can be optionally called if the CPU clock\r
-* frequency is lowered in order to improve the CPU performance.\r
-* See CyFlash_SetWaitCycles() description for more information.\r
+* coming back from the3 Flash must be adjusted by calling\r
+* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally\r
+* called if the CPU clock frequency is lowered in order to improve the CPU\r
+* performance. See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
void CyPLL_OUT_SetSource(uint8 source) \r
\r
/*******************************************************************************\r
* Function Name: CyIMO_Start\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the IMO. Optionally waits at least 6 us for it to settle.\r
*\r
-* Parameters:\r
-* uint8 wait:\r
-* 0: Return immediately after configuration\r
-* 1: Wait for at least 6 us for the IMO to settle.\r
-*\r
-* Return:\r
-* None\r
+* \param uint8 wait:\r
+* \param 0: Return immediately after configuration\r
+* \param 1: Wait for at least 6 us for the IMO to settle.\r
*\r
-* Side Effects:\r
+* \sideeffect\r
* If wait is enabled: This function uses the Fast Time Wheel to time the wait.\r
* Any other use of the Fast Time Wheel will be stopped during the period of\r
* this function and then restored. This function also uses the 100 KHz ILO.\r
\r
/*******************************************************************************\r
* Function Name: CyIMO_Stop\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the IMO.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyIMO_Stop(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyUSB_PowerOnCheck\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Returns the USB power status value. A private function to cy_boot.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* uint8: one if the USB is enabled, 0 if not enabled.\r
*\r
*******************************************************************************/\r
{\r
uint8 poweredOn = 0u;\r
\r
- /* Check whether device is in Active or AltActiv and if USB is powered on */\r
+ /* Check whether device is in Active or AltActive and if USB is powered on */\r
if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) &&\r
(0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) ||\r
(((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) &&\r
\r
/*******************************************************************************\r
* Function Name: CyIMO_SetTrimValue\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the IMO factory trim values.\r
*\r
-* Parameters:\r
* uint8 freq - frequency for which trims must be set\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
static void CyIMO_SetTrimValue(uint8 freq) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyIMO_SetFreq\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the frequency of the IMO. Changes may be made while the IMO is running.\r
*\r
-* Parameters:\r
-* freq: Frequency of IMO operation\r
+* \param freq: Frequency of IMO operation\r
* CY_IMO_FREQ_3MHZ to set 3 MHz\r
* CY_IMO_FREQ_6MHZ to set 6 MHz\r
* CY_IMO_FREQ_12MHZ to set 12 MHz\r
* CY_IMO_FREQ_74MHZ to set 74.7 MHz (not applicable for PSoC 3)\r
* CY_IMO_FREQ_USB to set 24 MHz (Trimmed for USB operation)\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* If this function execution results in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with an appropriate parameter. It can be optionally called if the CPU clock\r
-* frequency is lowered in order to improve the CPU performance.\r
-* See CyFlash_SetWaitCycles() description for more information.\r
+* coming back from the Flash must be adjusted by calling\r
+* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally\r
+* called if the CPU clock frequency is lowered in order to improve the CPU\r
+* performance. See CyFlash_SetWaitCycles() description for more information.\r
*\r
* When the USB setting is chosen, the USB clock locking circuit is enabled.\r
* Otherwise this circuit is disabled. The USB block must be powered before\r
\r
/*******************************************************************************\r
* Function Name: CyIMO_SetSource\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the source of the clock output from the IMO block.\r
*\r
* The output from the IMO is by default the IMO itself. Optionally the MHz\r
* Crystal or DSI input can be the source of the IMO output instead.\r
*\r
-* Parameters:\r
-* source: CY_IMO_SOURCE_DSI to set the DSI as source.\r
+* \param source: CY_IMO_SOURCE_DSI to set the DSI as source.\r
* CY_IMO_SOURCE_XTAL to set the MHz as source.\r
* CY_IMO_SOURCE_IMO to set the IMO itself.\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with an appropriate parameter. It can be optionally called if the CPU clock\r
-* frequency is lowered in order to improve the CPU performance.\r
-* See CyFlash_SetWaitCycles() description for more information.\r
+* coming back from the Flash must be adjusted by calling\r
+* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally\r
+* called if the CPU clock frequency is lowered in order to improve the CPU\r
+* performance. See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
void CyIMO_SetSource(uint8 source) \r
\r
/*******************************************************************************\r
* Function Name: CyIMO_EnableDoubler\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the IMO doubler. The 2x frequency clock is used to convert a 24 MHz\r
* input to a 48 MHz output for use by the USB block.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyIMO_EnableDoubler(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyIMO_DisableDoubler\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the IMO doubler.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyIMO_DisableDoubler(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyMasterClk_SetSource\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the source of the master clock.\r
*\r
-* Parameters:\r
-* source: One of the four available Master clock sources.\r
+* \param source: One of the four available Master clock sources.\r
* CY_MASTER_SOURCE_IMO\r
* CY_MASTER_SOURCE_PLL\r
* CY_MASTER_SOURCE_XTAL\r
* CY_MASTER_SOURCE_DSI\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* The current source and the new source must both be running and stable before\r
* calling this function.\r
*\r
* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with an appropriate parameter. It can be optionally called if the CPU clock\r
-* frequency is lowered in order to improve the CPU performance.\r
-* See CyFlash_SetWaitCycles() description for more information.\r
+* coming back from the Flash must be adjusted by calling\r
+* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally\r
+* called if the CPU clock frequency is lowered in order to improve the CPU\r
+* performance. See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
void CyMasterClk_SetSource(uint8 source) \r
\r
/*******************************************************************************\r
* Function Name: CyMasterClk_SetDivider\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the divider value used to generate Master Clock.\r
*\r
-* Parameters:\r
-* uint8 divider:\r
+* \param uint8 divider:\r
* The valid range is [0-255]. The clock will be divided by this value + 1.\r
* For example to divide this parameter by two should be set to 1.\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with an appropriate parameter. It can be optionally called if the CPU clock\r
-* frequency is lowered in order to improve the CPU performance.\r
-* See CyFlash_SetWaitCycles() description for more information.\r
+* coming back from the Flash must be adjusted by calling\r
+* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally\r
+* called if the CPU clock frequency is lowered in order to improve the CPU\r
+* performance. See CyFlash_SetWaitCycles() description for more information.\r
*\r
* When changing the Master or Bus clock divider value from div-by-n to div-by-1\r
* the first clock cycle output after the div-by-1 can be up to 4 ns shorter\r
\r
/*******************************************************************************\r
* Function Name: CyBusClk_Internal_SetDivider\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* The function used by CyBusClk_SetDivider(). For internal use only.\r
*\r
-* Parameters:\r
-* divider: Valid range [0-65535].\r
+* \param divider: Valid range [0-65535].\r
* The clock will be divided by this value + 1.\r
* For example, to divide this parameter by two should be set to 1.\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
static void CyBusClk_Internal_SetDivider(uint16 divider)\r
{\r
\r
/*******************************************************************************\r
* Function Name: CyBusClk_SetDivider\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the divider value used to generate the Bus Clock.\r
*\r
-* Parameters:\r
-* divider: Valid range [0-65535]. The clock will be divided by this value + 1.\r
+* \param divider: Valid range [0-65535]. The clock will be divided by this value + 1.\r
* For example, to divide this parameter by two should be set to 1.\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with an appropriate parameter. It can be optionally called if the CPU clock\r
-* frequency is lowered in order to improve the CPU performance.\r
-* See CyFlash_SetWaitCycles() description for more information.\r
+* coming back from the Flash must be adjusted by calling\r
+* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally\r
+* called if the CPU clock frequency is lowered in order to improve the CPU\r
+* performance. See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
void CyBusClk_SetDivider(uint16 divider) \r
\r
/*******************************************************************************\r
* Function Name: CyCpuClk_SetDivider\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Sets the divider value used to generate the CPU Clock. Only applicable for\r
* PSoC 3 parts.\r
*\r
- * Parameters:\r
- * divider: Valid range [0-15]. The clock will be divided by this value + 1.\r
+ * \param divider: Valid range [0-15]. The clock will be divided by this value + 1.\r
* For example, to divide this parameter by two should be set to 1.\r
*\r
- * Return:\r
- * None\r
- *\r
- * Side Effects:\r
+ * \sideeffect\r
* If this function execution resulted in the CPU clock frequency increasing,\r
-* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with an appropriate parameter. It can be optionally called if the CPU clock\r
-* frequency is lowered in order to improve the CPU performance.\r
- * See CyFlash_SetWaitCycles() description for more information.\r
+ * then the number of clock cycles the cache will wait before it samples data\r
+ * coming back from the Flash must be adjusted by calling\r
+ * CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally\r
+ * called if the CPU clock frequency is lowered in order to improve the CPU\r
+ * performance. See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
void CyCpuClk_SetDivider(uint8 divider) \r
\r
/*******************************************************************************\r
* Function Name: CyUsbClk_SetSource\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the source of the USB clock.\r
*\r
-* Parameters:\r
-* source: One of the four available USB clock sources\r
+* \param source: One of the four available USB clock sources\r
* CY_LIB_USB_CLK_IMO2X - IMO 2x\r
* CY_LIB_USB_CLK_IMO - IMO\r
* CY_LIB_USB_CLK_PLL - PLL\r
* CY_LIB_USB_CLK_DSI - DSI\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyUsbClk_SetSource(uint8 source) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyILO_Start1K\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the ILO 1 KHz oscillator.\r
*\r
* Note The ILO 1 KHz oscillator is always enabled by default, regardless of the\r
* selection in the Clock Editor. Therefore, this API is only needed if the\r
* oscillator was turned off manually.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyILO_Start1K(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyILO_Stop1K\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the ILO 1 KHz oscillator.\r
*\r
-* Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low power\r
-* mode APIs are expected to be used. For more information, refer to the Power\r
-* Management section of this document.\r
-*\r
-* Parameters:\r
-* None\r
+* Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low\r
+* power mode APIs are expected to be used. For more information, refer to the\r
+* Power Management section of this document.\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* PSoC5: Stopping the ILO 1 kHz could break the active WDT functionality.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyILO_Start100K\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the ILO 100 KHz oscillator.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyILO_Start100K(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyILO_Stop100K\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the ILO 100 KHz oscillator.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyILO_Stop100K(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyILO_Enable33K\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the ILO 33 KHz divider.\r
*\r
* Note that the 33 KHz clock is generated from the 100 KHz oscillator,\r
* so it must also be running in order to generate the 33 KHz output.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyILO_Enable33K(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyILO_Disable33K\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the ILO 33 KHz divider.\r
*\r
* Note that the 33 KHz clock is generated from the 100 KHz oscillator, but this\r
* API does not disable the 100 KHz clock.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyILO_Disable33K(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyILO_SetSource\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the source of the clock output from the ILO block.\r
*\r
-* Parameters:\r
-* source: One of the three available ILO output sources\r
+* \param source: One of the three available ILO output sources\r
* Value Define Source\r
* 0 CY_ILO_SOURCE_100K ILO 100 KHz\r
* 1 CY_ILO_SOURCE_33K ILO 33 KHz\r
* 2 CY_ILO_SOURCE_1K ILO 1 KHz\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyILO_SetSource(uint8 source) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyILO_SetPowerMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Sets the power mode used by the ILO during power down. Allows for lower power\r
-* down power usage resulting in a slower startup time.\r
+* Sets the power mode used by the ILO during power down. Allows for lower power\r
+* down power usage resulting in a slower startup time.\r
*\r
-* Parameters:\r
-* uint8 mode\r
-* CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down\r
-* CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down\r
+* \param mode\r
+* CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down\r
+* CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down\r
*\r
-* Return:\r
-* Prevous power mode state.\r
+* \return Prevous power mode state.\r
*\r
*******************************************************************************/\r
uint8 CyILO_SetPowerMode(uint8 mode) \r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_32KHZ_Start\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the 32 KHz Crystal Oscillator.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_32KHZ_Start(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_32KHZ_Stop\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the 32KHz Crystal Oscillator.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_32KHZ_Stop(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_32KHZ_ReadStatus\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Returns status of the 32 KHz oscillator.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* Value Define Source\r
* 20 CY_XTAL32K_ANA_STAT Analog measurement\r
* 1: Stable\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_32KHZ_SetPowerMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the power mode for the 32 KHz oscillator used during the sleep mode.\r
* Allows for lower power during sleep when there are fewer sources of noise.\r
* During the active mode the oscillator is always run in the high power mode.\r
*\r
-* Parameters:\r
* uint8 mode\r
-* 0: High power mode\r
-* 1: Low power mode during sleep\r
+* \param 0: High power mode\r
+* \param 1: Low power mode during sleep\r
*\r
-* Return:\r
+* \return\r
* Previous power mode.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_Start\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the megahertz crystal.\r
*\r
* PSoC 3:\r
* Waits until the XERR bit is low (no error) for a millisecond or until the\r
* number of milliseconds specified by the wait parameter has expired.\r
*\r
-* Parameters:\r
-* wait: Valid range [0-255].\r
+* \param wait: Valid range [0-255].\r
* This is the timeout value in milliseconds.\r
* The appropriate value is crystal specific.\r
*\r
-* Return:\r
+* \return\r
* CYRET_SUCCESS - Completed successfully\r
* CYRET_TIMEOUT - Timeout occurred without detecting a low value on XERR.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_Stop\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the megahertz crystal oscillator.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_Stop(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_EnableErrStatus\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the generation of the XERR status bit for the megahertz crystal.\r
* This function is not available for PSoC5.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_EnableErrStatus(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_DisableErrStatus\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the generation of the XERR status bit for the megahertz crystal.\r
* This function is not available for PSoC5.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_DisableErrStatus(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_ReadStatus\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Reads the XERR status bit for the megahertz crystal. This status bit is a\r
* sticky, clear on read. This function is not available for PSoC5.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* Status\r
* 0: No error\r
* 1: Error\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_EnableFaultRecovery\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the fault recovery circuit which will switch to the IMO in the case\r
* of a fault in the megahertz crystal circuit. The crystal must be up and\r
* running with the XERR bit at 0, before calling this function to prevent\r
* an immediate fault switchover. This function is not available for PSoC5.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_EnableFaultRecovery(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_DisableFaultRecovery\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the fault recovery circuit which will switch to the IMO in the case\r
* of a fault in the megahertz crystal circuit. This function is not available\r
* for PSoC5.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_DisableFaultRecovery(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_SetStartup\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Sets the startup settings for the crystal. The logic model outputs a frequency\r
-* (setting + 4) MHz when enabled.\r
+* Sets the startup settings for the crystal. The logic model outputs a\r
+* frequency (setting + 4) MHz when enabled.\r
*\r
* This is artificial as the actual frequency is determined by an attached\r
* external crystal.\r
*\r
-* Parameters:\r
-* setting: Valid range [0-31].\r
-* The value is dependent on the frequency and quality of the crystal being used.\r
-* Refer to the device TRM and datasheet for more information.\r
-*\r
-* Return:\r
-* None\r
+* \param setting: Valid range [0-31].\r
+* The value is dependent on the frequency and quality of the crystal being\r
+* used. Refer to the device TRM and datasheet for more information.\r
*\r
*******************************************************************************/\r
void CyXTAL_SetStartup(uint8 setting) \r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_SetFbVoltage\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the feedback reference voltage to use for the crystal circuit.\r
* This function is only available for PSoC3 and PSoC 5LP.\r
*\r
-* Parameters:\r
-* setting: Valid range [0-15].\r
+* \param setting: Valid range [0-15].\r
* Refer to the device TRM and datasheet for more information.\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_SetFbVoltage(uint8 setting) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_SetWdVoltage\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the reference voltage used by the watchdog to detect a failure in the\r
* crystal circuit. This function is only available for PSoC3 and PSoC 5LP.\r
*\r
-* Parameters:\r
-* setting: Valid range [0-7].\r
+* \param setting: Valid range [0-7].\r
* Refer to the device TRM and datasheet for more information.\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyXTAL_SetWdVoltage(uint8 setting) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyHalt\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Halts the CPU.\r
*\r
-* Parameters:\r
-* uint8 reason: Value to be used during debugging.\r
-*\r
-* Return:\r
-* None\r
+* \param uint8 reason: Value to be used during debugging.\r
*\r
*******************************************************************************/\r
void CyHalt(uint8 reason) CYREENTRANT\r
\r
/*******************************************************************************\r
* Function Name: CySoftwareReset\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Forces a device software reset.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CySoftwareReset(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyDelay\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Blocks for milliseconds.\r
*\r
* Note:\r
* For example, with instruction cache disabled CyDelay(100) would result in\r
* about 200 ms delay instead of 100 ms.\r
*\r
-* Parameters:\r
-* milliseconds: number of milliseconds to delay.\r
-*\r
-* Return:\r
-* None\r
+* \param milliseconds: number of milliseconds to delay.\r
*\r
*******************************************************************************/\r
void CyDelay(uint32 milliseconds) CYREENTRANT\r
\r
/*******************************************************************************\r
* Function Name: CyDelayUs\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Blocks for microseconds.\r
*\r
* Note:\r
* larger. Ex: With instruction cache disabled CyDelayUs(100) would result\r
* in about 200us delay instead of 100us.\r
*\r
- * Parameters:\r
- * uint16 microseconds: number of microseconds to delay.\r
- *\r
- * Return:\r
- * None\r
+ * \param uint16 microseconds: number of microseconds to delay.\r
*\r
- * Side Effects:\r
+ * \sideeffect\r
* CyDelayUS has been implemented with the instruction cache assumed enabled.\r
* When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times\r
* larger. For example, with the instruction cache disabled CyDelayUs(100) would\r
\r
/*******************************************************************************\r
* Function Name: CyDelayFreq\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the clock frequency for CyDelay.\r
*\r
-* Parameters:\r
-* freq: The frequency of the bus clock in Hertz.\r
-*\r
-* Return:\r
-* None\r
+* \param freq: The frequency of the bus clock in Hertz.\r
*\r
*******************************************************************************/\r
void CyDelayFreq(uint32 freq) CYREENTRANT\r
\r
/*******************************************************************************\r
* Function Name: CyWdtStart\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables the watchdog timer.\r
*\r
* The timer is configured for the specified count interval, the central\r
-* timewheel is cleared, the setting for the low power mode is configured and the\r
-* watchdog timer is enabled.\r
+* timewheel is cleared, the setting for the low power mode is configured and\r
+* the watchdog timer is enabled.\r
*\r
* Once enabled the watchdog cannot be disabled. The watchdog counts each time\r
* the Central Time Wheel (CTW) reaches the period specified. The watchdog must\r
* set to be greater than the sleep wakeup period, then feed the dog on each\r
* wakeup from Sleep.\r
*\r
-* Parameters:\r
-* ticks: One of the four available timer periods. Once WDT enabled, the\r
+* \param ticks: One of the four available timer periods. Once WDT enabled, the\r
interval cannot be changed.\r
* CYWDT_2_TICKS - 4 - 6 ms\r
* CYWDT_16_TICKS - 32 - 48 ms\r
* CYWDT_128_TICKS - 256 - 384 ms\r
* CYWDT_1024_TICKS - 2.048 - 3.072 s\r
*\r
-* lpMode: Low power mode configuration. This parameter is ignored for PSoC 5.\r
+* \param lpMode: Low power mode configuration. This parameter is ignored for PSoC 5.\r
* The WDT always acts as if CYWDT_LPMODE_NOCHANGE is passed.\r
*\r
* CYWDT_LPMODE_NOCHANGE - No Change\r
* mode\r
* CYWDT_LPMODE_DISABLED - Disable WDT during low power mode\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* PSoC5: The ILO 1 KHz must be enabled for proper WDT operation. Stopping the\r
* ILO 1 kHz could break the active WDT functionality.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyWdtClear\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Clears (feeds) the watchdog timer.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyWdtClear(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyVdLvDigitEnable\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Enables the digital low voltage monitors to generate interrupt on Vddd\r
-* archives specified threshold and optionally resets the device.\r
+* Sets the voltage trip level, enables the output of the digital low-voltage\r
+* monitor, and optionally configures voltage monitor to reset device upon the\r
+* low-voltage event instead of generating an interrupt.\r
*\r
-* Parameters:\r
-* reset: The option to reset the device at a specified Vddd threshold:\r
-* 0 - Device is not reset.\r
-* 1 - Device is reset.\r
+* Note The associated interrupt enable/disable state is not changed by the\r
+* function. The Interrupt component API should be used to register the\r
+* interrupt service routine and to enable/disable associated interrupt.\r
*\r
-* threshold: Sets the trip level for the voltage monitor.\r
-* Values from 1.70 V to 5.45 V are accepted with an interval of approximately\r
-* 250 mV.\r
+* \param reset: Enables device reset on digital low-voltage event:\r
+* Zero - Interrupt on digital low-voltage event\r
+* Non-zero - Reset on digital low-voltage event\r
*\r
-* Return:\r
-* None\r
+* \param threshold: Sets the trip point of the digital low-voltage monitoring circuit\r
+* in steps of approximately 250 mV in range from 1.70 V (0x00) to 5.45 V\r
+* (0x0F). For example, the trip point is set to 1.80 V when the threshold\r
+* parameter value is 0x04. Refer to the device TRM for the exact trip voltage\r
+* values.\r
+*\r
+* Side Effects and Restrictions:\r
+* The voltage resets are momentary. When a voltage reset (analog/digital\r
+* low-voltage and analog high-voltage) occurs, the RESET_CR1 and RESET_CR3\r
+* registers are restored to their default values. This means that the voltage\r
+* monitor circuit is no longer enabled and the device exits reset. If the\r
+* supply is below the trip level and firmware enables the voltage reset\r
+* functionality, the device will reset again. This will continue as long as the\r
+* supply is below the trip level or as long as the user enables the reset\r
+* functionality of the voltage monitor functionality.\r
+*\r
+* When any voltage reset occurs, the RESET_SR0 and RESET_SR2 status registers\r
+* are cleared. This means that analog low-voltage, digital low-voltage and\r
+* analog high-voltage status bits are not persistent across any voltage reset.\r
*\r
*******************************************************************************/\r
void CyVdLvDigitEnable(uint8 reset, uint8 threshold) \r
{\r
- *CY_INT_CLEAR_PTR = 0x01u;\r
+ uint32 intRegTmp;\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ /* Store interrupt enable state */\r
+ intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK;\r
+\r
+ /* Disable VD interrupt (write 1) to protect against glitches */\r
+ CY_INT_CLEAR_REG = CY_VD_INT_MASK;\r
\r
CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));\r
\r
(CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK)));\r
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN;\r
\r
- /* Timeout to eliminate glitches on LVI/HVI when enabling */\r
+ /* Timeout to eliminate glitches on LVI/HVI when enabling (ID # 127412) */\r
CyDelayUs(1u);\r
\r
- (void)CY_VD_PERSISTENT_STATUS_REG;\r
+ (void) CyVdStickyStatus(CY_VD_LVID);\r
\r
if(0u != reset)\r
{\r
CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));\r
}\r
\r
- *CY_INT_CLR_PEND_PTR = 0x01u;\r
- *CY_INT_ENABLE_PTR = 0x01u;\r
+ /* Clear pending interrupt */\r
+ CY_INT_CLR_PEND_REG = CY_VD_INT_MASK;\r
+\r
+ /* Restore interrupt enable state */\r
+ CY_INT_ENABLE_REG = intRegTmp;\r
+\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: CyVdLvAnalogEnable\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Enables the analog low voltage monitors to generate interrupt on Vdda\r
-* archives specified threshold and optionally resets the device.\r
+* Sets the voltage trip level, enables the output of the analog low-voltage\r
+* monitor, and optionally configures voltage monitor to reset device upon the\r
+* low-voltage event instead of generating an interrupt.\r
*\r
-* Parameters:\r
-* reset: The option to reset the device at a specified Vdda threshold:\r
-* 0 - Device is not reset.\r
-* 1 - Device is reset.\r
+* Note The associated interrupt enable/disable state is not changed by the\r
+* function. The Interrupt component API should be used to register the\r
+* interrupt service routine and to enable/disable associated interrupt.\r
*\r
-* threshold: Sets the trip level for the voltage monitor.\r
-* Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV\r
-* interval.\r
+* \param reset: Enables device reset on analog low-voltage event:\r
+* Zero - Interrupt on analog low-voltage event\r
+* Non-zero - Reset on analog low-voltage event\r
*\r
-* Return:\r
-* None\r
+* \param threshold: Sets the trip point of the analog low-voltage monitoring circuit\r
+* in steps of approximately 250 mV in range from 1.70 V (0x00) to 5.45 V\r
+* (0x0F). For example, the trip point is set to 1.80 V when value of the\r
+* threshold parameter is 0x04. Please refer to the device TRM for the exact\r
+* trip voltage values.\r
+*\r
+* Side Effects and Restrictions:\r
+* The voltage resets are momentary. When a voltage reset (analog/digital\r
+* low-voltage and analog high-voltage) occurs, the RESET_CR1 and RESET_CR3\r
+* registers are restored to their default values. This means that the voltage\r
+* monitor circuit is no longer enabled and the device exits reset. If the\r
+* supply is below the trip level and firmware enables the voltage reset\r
+* functionality, the device will reset again. This will continue as long as\r
+* the supply is below the trip level or as long as the user enables the reset\r
+* functionality of the voltage monitor functionality.\r
+*\r
+* When any voltage reset occurs, the RESET_SR0 and RESET_SR2 status registers\r
+* are cleared. This means that analog low-voltage, digital low-voltage and\r
+* analog high-voltage status bits are not persistent across any voltage reset.\r
*\r
*******************************************************************************/\r
void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) \r
{\r
- *CY_INT_CLEAR_PTR = 0x01u;\r
+ uint32 intRegTmp;\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ /* Store interrupt enable state */\r
+ intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK;\r
+\r
+ /* Disable VD interrupt (write 1) to protect against glitches */\r
+ CY_INT_CLEAR_REG = CY_VD_INT_MASK;\r
\r
CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
\r
CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu);\r
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN;\r
\r
- /* Timeout to eliminate glitches on LVI/HVI when enabling */\r
+ /* Timeout to eliminate glitches on LVI/HVI when enabling (ID # 127412) */\r
CyDelayUs(1u);\r
\r
- (void)CY_VD_PERSISTENT_STATUS_REG;\r
+ (void) CyVdStickyStatus(CY_VD_LVIA);\r
\r
if(0u != reset)\r
{\r
CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
}\r
\r
- *CY_INT_CLR_PEND_PTR = 0x01u;\r
- *CY_INT_ENABLE_PTR = 0x01u;\r
+ /* Clear pending interrupt */\r
+ CY_INT_CLR_PEND_REG = CY_VD_INT_MASK;\r
+\r
+ /* Restore interrupt enable state */\r
+ CY_INT_ENABLE_REG = intRegTmp;\r
+\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: CyVdLvDigitDisable\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Disables the digital low voltage monitor (interrupt and device reset are\r
-* disabled).\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None\r
+* Disables the digital low-voltage monitor, turns off device reset upon the\r
+* digital low-voltage event, and clears the associated persistent status bit.\r
*\r
-* Return:\r
-* None\r
+* Note The associated interrupt enable/disable state is not changed by the\r
+* function. The pending interrupt status is not cleared. The Interrupt\r
+* component API should be used to manipulate with the associated interrupts.\r
*\r
*******************************************************************************/\r
void CyVdLvDigitDisable(void) \r
{\r
CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVID_EN));\r
-\r
CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));\r
+ (void) CyVdStickyStatus(CY_VD_LVID);\r
\r
- while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u))\r
+ while(0u != (CyVdStickyStatus(CY_VD_LVID) & CY_VD_LVID))\r
{\r
\r
}\r
\r
/*******************************************************************************\r
* Function Name: CyVdLvAnalogDisable\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Disables the analog low voltage monitor (interrupt and device reset are\r
-* disabled).\r
+* Disables the analog low-voltage monitor, turns off device reset upon the\r
+* analog low-voltage event, and clears the associated persistent status bit.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
+* Note The associated interrupt enable/disable state is not changed by the\r
+* function. The pending interrupt status is not cleared. The Interrupt\r
+* component API should be used to manipulate with the associated interrupts.\r
*\r
*******************************************************************************/\r
void CyVdLvAnalogDisable(void) \r
{\r
CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVIA_EN));\r
-\r
CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
-\r
- while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u))\r
+ while(0u != (CyVdStickyStatus(CY_VD_LVIA) & CY_VD_LVIA))\r
{\r
\r
}\r
\r
/*******************************************************************************\r
* Function Name: CyVdHvAnalogEnable\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Enables the analog high voltage monitors to generate interrupt on\r
-* Vdda archives 5.75 V threshold and optionally resets device.\r
+* Enables the output of the analog high-voltage monitor and sets 5.75 V\r
+* threshold detection for Vdda.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
+* Note The associated interrupt enable/disable state is not changed by the\r
+* function. The Interrupt component API should be used to register the\r
+* interrupt service routine and to enable/disable associated interrupt.\r
*\r
*******************************************************************************/\r
void CyVdHvAnalogEnable(void) \r
{\r
- *CY_INT_CLEAR_PTR = 0x01u;\r
+ uint32 intRegTmp;\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ /* Store interrupt enable state */\r
+ intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK;\r
+\r
+ /* Disable VD interrupt (write 1) to protect against glitches */\r
+ CY_INT_CLEAR_REG = CY_VD_INT_MASK;\r
\r
CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
\r
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_HVIA_EN;\r
\r
- /* Timeout to eliminate glitches on the LVI/HVI when enabling */\r
+ /* Timeout to eliminate glitches on the LVI/HVI when enabling (ID # 127412) */\r
CyDelayUs(1u);\r
\r
- (void) CY_VD_PERSISTENT_STATUS_REG;\r
+ (void) CyVdStickyStatus(CY_VD_HVIA);\r
+\r
+ /* Clear pending interrupt */\r
+ CY_INT_CLR_PEND_REG = CY_VD_INT_MASK;\r
+\r
+ /* Restore interrupt enable state */\r
+ CY_INT_ENABLE_REG = intRegTmp;\r
\r
- *CY_INT_CLR_PEND_PTR = 0x01u;\r
- *CY_INT_ENABLE_PTR = 0x01u;\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: CyVdHvAnalogDisable\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Disables the analog low voltage monitor\r
-* (interrupt and device reset are disabled).\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None\r
+* Disables the analog high-voltage monitor and clears the associated persistent\r
+* status bit.\r
*\r
-* Return:\r
-* None\r
+* Note The associated interrupt enable/disable state is not changed by the\r
+* function. The pending interrupt status is not cleared. The Interrupt\r
+* component API should be used to manipulate with the associated interrupts.\r
*\r
*******************************************************************************/\r
void CyVdHvAnalogDisable(void) \r
{\r
CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_HVIA_EN));\r
+ while(0u != (CyVdStickyStatus(CY_VD_HVIA) & CY_VD_HVIA))\r
+ {\r
+\r
+ }\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: CyVdStickyStatus\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Manages the Reset and Voltage Detection Status Register 0.\r
-* This register has the interrupt status for the HVIA, LVID and LVIA.\r
-* This hardware register clears on read.\r
+* Reads and clears the voltage detection status bits in the RESET_SR0 register.\r
+* The bits are set to 1 by the voltage monitor circuit when the supply is\r
+* outside the detector trip point. They stay set to 1 until they are read or\r
+* a POR / LVI / PRES reset occurs. This function uses a shadow register, so\r
+* only the bits passed in the parameter will be cleared in the shadow register.\r
*\r
-* Parameters:\r
-* mask: Bits in the shadow register to clear.\r
+* \param mask: Bits in the RESET_SR0 shadow register to clear and return.\r
* Define Definition\r
* CY_VD_LVID Persistent status of digital LVI.\r
* CY_VD_LVIA Persistent status of analog LVI.\r
* CY_VD_HVIA Persistent status of analog HVI.\r
*\r
-* Return:\r
-* Status. Same enumerated bit values as used for the mask parameter.\r
+* \return\r
+* Status. Same enumerated bit values as used for the mask parameter. A zero is\r
+* returned for bits not used in the mask parameter.\r
+*\r
+* Side Effects and Restrictions:\r
+* When an LVI reset occurs, the RESET_SR0 status registers are cleared. This\r
+* means that the voltage detection status bits are not persistent across an LVI\r
+* reset and cannot be used to determine a reset source.\r
*\r
*******************************************************************************/\r
uint8 CyVdStickyStatus(uint8 mask) \r
{\r
- uint8 status;\r
+ static uint8 interruptStatus;\r
+ uint8 interruptState;\r
+ uint8 tmpStatus;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
\r
- status = CY_VD_PERSISTENT_STATUS_REG;\r
- CY_VD_PERSISTENT_STATUS_REG &= ((uint8)(~mask));\r
+ interruptStatus |= CY_VD_PERSISTENT_STATUS_REG;\r
+ tmpStatus = interruptStatus & (uint8)(CY_VD_LVID | CY_VD_LVIA | CY_VD_HVIA);\r
+ interruptStatus &= ((uint8)(~mask));\r
\r
- return(status);\r
+ CyExitCriticalSection(interruptState);\r
+\r
+ return(tmpStatus);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: CyVdRealTimeStatus\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Returns the real time voltage detection status.\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None\r
+* Reads the real-time voltage detection status bits in the RESET_SR2 register.\r
+* The bits are set to 1 by the voltage monitor circuit when the supply is\r
+* outside the detector’s trip point, and set to 0 when the supply is inside the\r
+* trip point.\r
*\r
-* Return:\r
-* Status:\r
+* \return\r
+* Status of the LVID, LVIA, and HVIA bits in the RESET_SR2 register.\r
* Define Definition\r
-* CY_VD_LVID Persistent status of digital LVI.\r
-* CY_VD_LVIA Persistent status of analog LVI.\r
-* CY_VD_HVIA Persistent status of analog HVI.\r
+* CY_VD_LVID Real-time status of digital LVI.\r
+* CY_VD_LVIA Real-time status of analog LVI.\r
+* CY_VD_HVIA Real-time status of analog HVI.\r
+*\r
+* Side Effects and Restrictions:\r
+* When an LVI reset occurs, the RESET_SR2 status registers are cleared. This\r
+* means that the voltage detection status bits are not persistent across an LVI\r
+* reset and cannot be used to determine a reset source.\r
*\r
*******************************************************************************/\r
uint8 CyVdRealTimeStatus(void) \r
uint8 vdFlagsState;\r
\r
interruptState = CyEnterCriticalSection();\r
- vdFlagsState = CY_VD_RT_STATUS_REG;\r
+ vdFlagsState = CY_VD_RT_STATUS_REG & (CY_VD_LVID | CY_VD_LVIA | CY_VD_HVIA);\r
CyExitCriticalSection(interruptState);\r
\r
return(vdFlagsState);\r
\r
/*******************************************************************************\r
* Function Name: CyDisableInts\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Disables the interrupt enable for each interrupt.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* 32 bit mask of previously enabled interrupts.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyEnableInts\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Enables interrupts to a given state.\r
*\r
-* Parameters:\r
-* uint32 mask: 32 bit mask of interrupts to enable.\r
-*\r
-* Return:\r
-* None\r
+* \param uint32 mask: 32 bit mask of interrupts to enable.\r
*\r
*******************************************************************************/\r
void CyEnableInts(uint32 mask) \r
\r
/*******************************************************************************\r
* Function Name: CyFlushCache\r
- ********************************************************************************\r
- * Summary:\r
- * Flushes the PSoC 5/5LP cache by invalidating all entries.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
+ ****************************************************************************//**\r
+ * Call this API after a flash row erase/write operation to invalidate or flush\r
+ * any of that particular flash region content already present in the cache.\r
+ * After a cache flush operation, any access to that flash region after the\r
+ * erase/write operation would reload the cache with the modified data from the\r
+ * flash region. If the flash region update involves multiple flash row write\r
+ * operations, then the flushing of the cache can be done once at the end of\r
+ * the operation as long as the flash data would not be accessed in the middle\r
+ * of the multiple row update process. Else, flush the cache after every flash\r
+ * row write.\r
*\r
*******************************************************************************/\r
void CyFlushCache(void)\r
\r
/*******************************************************************************\r
* Function Name: CyIntSetSysVector\r
- ********************************************************************************\r
- * Summary:\r
+ ****************************************************************************//**\r
* Sets the interrupt vector of the specified system interrupt number. System\r
* interrupts are present only for the ARM platform. These interrupts are for\r
* SysTick, PendSV and others.\r
*\r
- * Parameters:\r
- * number: System interrupt number:\r
+ * \param number: System interrupt number:\r
* CY_INT_NMI_IRQN - Non Maskable Interrupt\r
* CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt\r
* CY_INT_MEM_MANAGE_IRQN - Memory Management Interrupt\r
* CY_INT_PEND_SV_IRQN - Pend SV Interrupt\r
* CY_INT_SYSTICK_IRQN - System Tick Interrupt\r
*\r
- * address: Pointer to an interrupt service routine.\r
+ * \param address: Pointer to an interrupt service routine.\r
*\r
- * Return:\r
+ * \return\r
* The old ISR vector at this location.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyIntGetSysVector\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Gets the interrupt vector of the specified system interrupt number. System\r
* interrupts are present only for the ARM platform. These interrupts are for\r
* SysTick, PendSV and others.\r
*\r
- * Parameters:\r
- * number: System interrupt number:\r
+ * \param number: System interrupt number:\r
* CY_INT_NMI_IRQN - Non Maskable Interrupt\r
* CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt\r
* CY_INT_MEMORY_MANAGEMENT_IRQN - Memory Management Interrupt\r
* CY_INT_PEND_SV_IRQN - Pend SV Interrupt\r
* CY_INT_SYSTICK_IRQN - System Tick Interrupt\r
*\r
- * Return:\r
+ * \return\r
* Address of the ISR in the interrupt vector table.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyIntSetVector\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Sets the interrupt vector of the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number\r
- * address: Pointer to an interrupt service routine\r
+ * \param number: Valid range [0-31]. Interrupt number\r
+ * \param address: Pointer to an interrupt service routine\r
*\r
- * Return:\r
+ * \return\r
* Previous interrupt vector value.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyIntGetVector\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Gets the interrupt vector of the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number\r
+ * \param number: Valid range [0-31]. Interrupt number\r
*\r
- * Return:\r
+ * \return\r
* The address of the ISR in the interrupt vector table.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyIntSetPriority\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Sets the Priority of the Interrupt.\r
*\r
- * Parameters:\r
- * priority: Priority of the interrupt. 0 - 7, 0 being the highest.\r
- * number: The number of the interrupt, 0 - 31.\r
- *\r
- * Return:\r
- * None\r
+ * \param priority: Priority of the interrupt. 0 - 7, 0 being the highest.\r
+ * \param number: The number of the interrupt, 0 - 31.\r
*\r
*******************************************************************************/\r
void CyIntSetPriority(uint8 number, uint8 priority)\r
\r
/*******************************************************************************\r
* Function Name: CyIntGetPriority\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Gets the Priority of the Interrupt.\r
*\r
- * Parameters:\r
- * number: The number of the interrupt, 0 - 31.\r
+ * \param number: The number of the interrupt, 0 - 31.\r
*\r
- * Return:\r
+ * \return\r
* Priority of the interrupt. 0 - 7, 0 being the highest.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyIntGetState\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Gets the enable state of the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number.\r
+ * \param number: Valid range [0-31]. Interrupt number.\r
*\r
- * Return:\r
+ * \return\r
* Enable status: 1 if enabled, 0 if disabled\r
*\r
*******************************************************************************/\r
\r
#else /* PSoC3 */\r
\r
+ /*******************************************************************************\r
+ * Function Name: IntDefaultHandler\r
+ ****************************************************************************//**\r
+ *\r
+ * This function is called for all interrupts, other than a reset that gets\r
+ * called before the system is setup.\r
+ *\r
+ * Theory:\r
+ * Any value other than zero is acceptable.\r
+ *\r
+ *******************************************************************************/\r
+ CY_ISR(IntDefaultHandler)\r
+ {\r
+ #ifdef CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK\r
+ CyBoot_IntDefaultHandler_Exception_EntryCallback();\r
+ #endif /* CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK */\r
+\r
+ while(1)\r
+ {\r
+ /***********************************************************************\r
+ * We must not get here. If we do, a serious problem occurs, so go\r
+ * into an infinite loop.\r
+ ***********************************************************************/\r
+ }\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: IntDefaultHandler\r
+ ****************************************************************************//**\r
+ *\r
+ * This function is called during startup to initialize interrupt address vector\r
+ * registers with the address of the IntDefaultHandler().\r
+ *\r
+ *******************************************************************************/\r
+ void CyIntInitVectors(void) \r
+ {\r
+ uint8 i;\r
+\r
+ for (i = 0; i <= CY_INT_NUMBER_MAX; i++)\r
+ {\r
+ CY_SET_REG16(&CY_INT_VECT_TABLE[i], (uint16) &IntDefaultHandler);\r
+ }\r
+ }\r
+\r
\r
/*******************************************************************************\r
* Function Name: CyIntSetVector\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Sets the interrupt vector of the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number\r
- * address: Pointer to an interrupt service routine\r
+ * \param number: Valid range [0-31]. Interrupt number\r
+ * \param address: Pointer to an interrupt service routine\r
*\r
- * Return:\r
+ * \return\r
* Previous interrupt vector value.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyIntGetVector\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Gets the interrupt vector of the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number\r
+ * \param number: Valid range [0-31]. Interrupt number\r
*\r
- * Return:\r
+ * \return\r
* Address of the ISR in the interrupt vector table.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyIntSetPriority\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Sets the Priority of the Interrupt.\r
*\r
- * Parameters:\r
- * priority: Priority of the interrupt. 0 - 7, 0 being the highest.\r
- * number: The number of the interrupt, 0 - 31.\r
- *\r
- * Return:\r
- * None\r
+ * \param priority: Priority of the interrupt. 0 - 7, 0 being the highest.\r
+ * \param number: The number of the interrupt, 0 - 31.\r
*\r
*******************************************************************************/\r
void CyIntSetPriority(uint8 number, uint8 priority) \r
\r
/*******************************************************************************\r
* Function Name: CyIntGetPriority\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Gets the Priority of the Interrupt.\r
*\r
- * Parameters:\r
- * number: The number of the interrupt, 0 - 31.\r
+ * \param number: The number of the interrupt, 0 - 31.\r
*\r
- * Return:\r
+ * \return\r
* Priority of the interrupt. 0 - 7, 0 being the highest.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyIntGetState\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Gets the enable state of the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number.\r
+ * \param number: Valid range [0-31]. Interrupt number.\r
*\r
- * Return:\r
+ * \return\r
* Enable status: 1 if enabled, 0 if disabled\r
*\r
*******************************************************************************/\r
return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u)));\r
}\r
\r
-\r
#endif /* (CY_PSOC5) */\r
\r
\r
\r
/*******************************************************************************\r
* Function Name: CySetScPumps\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* If 1 is passed as a parameter:\r
* - if any of the SC blocks are used - enable pumps for the SC blocks and\r
* start boost clock.\r
* If non-1 value is passed as a parameter:\r
* - If all SC blocks are not used - disable pumps for the SC blocks and\r
* stop the boost clock.\r
- * - For each enabled SC block clear the boost clock index and disable the boost\r
- * clock.\r
+ * - For each enabled SC block clear the boost clock index and disable the\r
+ * boost clock.\r
*\r
* The global variable CyScPumpEnabled is updated to be equal to passed the\r
* parameter.\r
*\r
- * Parameters:\r
- * uint8 enable: Enable/disable SC pumps and the boost clock for the enabled SC block.\r
+ * \param uint8 enable: Enable/disable SC pumps and the boost clock for the enabled\r
+ * \param SC block:\r
* 1 - Enable\r
* 0 - Disable\r
*\r
- * Return:\r
- * None\r
- *\r
*******************************************************************************/\r
void CySetScPumps(uint8 enable) \r
{\r
#if(CY_PSOC5)\r
/*******************************************************************************\r
* Function Name: CySysTickStart\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Configures the SysTick timer to generate interrupt every 1 ms by call to the\r
* CySysTickInit() function and starts it by calling CySysTickEnable() function.\r
* Refer to the corresponding function description for the details.\r
\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Side Effects:\r
+ * \sideeffect\r
* Clears SysTick count flag if it was set\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CySysTickInit\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Initializes the callback addresses with pointers to NULL, associates the\r
* SysTick system vector with the function that is responsible for calling\r
* registered callback functions, configures SysTick timer to generate interrupt\r
* every 1 ms.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Side Effects:\r
+ * \sideeffect\r
* Clears SysTick count flag if it was set.\r
*\r
* The 1 ms interrupt interval is configured based on the frequency determined\r
CySysTickCallbacks[i] = (void *) 0;\r
}\r
\r
- (void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks);\r
+ (void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks);\r
CySysTickSetClockSource(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK);\r
CySysTickSetReload(cydelay_freq_hz/1000u);\r
CySysTickClear();\r
\r
/*******************************************************************************\r
* Function Name: CySysTickEnable\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Enables the SysTick timer and its interrupt.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Side Effects:\r
+ * \sideeffect\r
* Clears SysTick count flag if it was set\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CySysTickStop\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Stops the system timer (SysTick).\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Side Effects:\r
+ * \sideeffect\r
* Clears SysTick count flag if it was set\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CySysTickEnableInterrupt\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Enables the SysTick interrupt.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Side Effects:\r
+ * \sideeffect\r
* Clears SysTick count flag if it was set\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CySysTickDisableInterrupt\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Disables the SysTick interrupt.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Side Effects:\r
+ * \sideeffect\r
* Clears SysTick count flag if it was set\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CySysTickSetReload\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Sets value the counter is set to on startup and after it reaches zero. This\r
* function do not change or reset current sysTick counter value, so it should\r
* be cleared using CySysTickClear() API.\r
*\r
- * Parameters:\r
- * value: Valid range [0x0-0x00FFFFFF]. Counter reset value.\r
- *\r
- * Return:\r
- * None\r
+ * \param value: Valid range [0x0-0x00FFFFFF]. Counter reset value.\r
*\r
*******************************************************************************/\r
void CySysTickSetReload(uint32 value)\r
\r
/*******************************************************************************\r
* Function Name: CySysTickGetReload\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Sets value the counter is set to on startup and after it reaches zero.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
+ * \return\r
* Counter reset value\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CySysTickGetValue\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Gets current SysTick counter value.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
+ * \return\r
* Current SysTick counter value\r
*\r
*******************************************************************************/\r
uint32 CySysTickGetValue(void)\r
{\r
- return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_CVR_REG);\r
+ return(CY_SYS_SYST_CVR_REG & CY_SYS_SYST_CVR_CNT_MASK);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: CySysTickSetClockSource\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Sets the clock source for the SysTick counter.\r
*\r
- * Parameters:\r
- * clockSource: Clock source for SysTick counter\r
+ * \param clockSource: Clock source for SysTick counter\r
* Define Clock Source\r
* CY_SYS_SYST_CSR_CLK_SRC_SYSCLK SysTick is clocked by CPU clock.\r
* CY_SYS_SYST_CSR_CLK_SRC_LFCLK SysTick is clocked by the low frequency\r
- * clock (ILO 100 KHz for PSoC 5LP, LFCLK for PSoC 4).\r
- *\r
- * Return:\r
- * None\r
+ * clock (ILO 100 KHz for PSoC 5LP, and\r
+ * LFCLK for PSoC 4).\r
*\r
- * Side Effects:\r
+ * \sideeffect\r
* Clears SysTick count flag if it was set. If clock source is not ready this\r
- * function call will have no effect. After changing clock source to the low frequency\r
- * clock the counter and reload register values will remain unchanged so time to\r
- * the interrupt will be significantly bigger and vice versa.\r
+ * function call will have no effect. After changing clock source to the low\r
+ * frequency clock the counter and reload register values will remain unchanged\r
+ * so time to the interrupt will be significantly bigger and vice versa.\r
*\r
*******************************************************************************/\r
void CySysTickSetClockSource(uint32 clockSource)\r
}\r
else\r
{\r
- CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT));\r
+ CY_SYS_SYST_CSR_REG &= ((uint32) ~((uint32)(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT)));\r
}\r
}\r
\r
+ \r
+ /*******************************************************************************\r
+ * Function Name: CySysTickGetClockSource\r
+ ****************************************************************************//**\r
+ *\r
+ * Returns the current clock source of the SysTick counter.\r
+ *\r
+ * \return \r
+ * CY_SYS_SYST_CSR_CLK_SRC_SYSCLK SysTick is clocked by CPU clock.\r
+ * CY_SYS_SYST_CSR_CLK_SRC_LFCLK SysTick is clocked by the low frequency\r
+ * clock. (ILO 100 KHz for PSoC 5LP, and\r
+ * LFCLK for PSoC 4).\r
+ *******************************************************************************/\r
+ uint32 CySysTickGetClockSource(void)\r
+ {\r
+ return ((CY_SYS_SYST_CSR_REG >> CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT) & CY_SYS_SYST_CSR_CLK_SRC_SYSCLK );\r
+ }\r
\r
+ \r
/*******************************************************************************\r
* Function Name: CySysTickGetCountFlag\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* The count flag is set once SysTick counter reaches zero.\r
* The flag cleared on read.\r
*\r
- * Parameters:\r
- * None\r
+ * \return\r
+ * Returns non-zero value if flag is set, otherwise zero is returned.\r
*\r
- * Return:\r
- * Returns non-zero value if counter is set, otherwise zero is returned.\r
+ *\r
+ * \sideeffect\r
+ * Clears SysTick count flag if it was set.\r
*\r
*******************************************************************************/\r
uint32 CySysTickGetCountFlag(void)\r
{\r
- return ((CY_SYS_SYST_CSR_REG>>CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u);\r
+ return ((CY_SYS_SYST_CSR_REG >> CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: CySysTickClear\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Clears the SysTick counter for well-defined startup.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
*******************************************************************************/\r
void CySysTickClear(void)\r
{\r
\r
/*******************************************************************************\r
* Function Name: CySysTickSetCallback\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
+ *\r
+ * This function allows up to five user-defined interrupt service routine\r
+ * functions to be associated with the SysTick interrupt. These are specified\r
+ * through the use of pointers to the function.\r
+ *\r
+ * To set a custom callback function without the overhead of the system provided\r
+ * one, use CyIntSetSysVector(CY_INT_SYSTICK_IRQN, cyisraddress <address>),\r
+ * where <address> is address of the custom defined interrupt service routine.\r
+ * Note: a custom callback function overrides the system defined callback\r
+ * functions.\r
*\r
- * Summary:\r
- * The function set the pointers to the functions that will be called on\r
- * SysTick interrupt.\r
+ * \param number: The number of the callback function addresses to be set. The valid\r
+ * range is from 0 to 4.\r
*\r
- * Parameters:\r
- * number: The number of callback function address to be set.\r
- * The valid range is from 0 to 4.\r
- * CallbackFunction: Function address.\r
+ * void(*CallbackFunction(void): A pointer to the function that will be\r
+ * associated with the SysTick ISR for the\r
+ * specified number.\r
*\r
- * Return:\r
+ * \return\r
* Returns the address of the previous callback function.\r
* The NULL is returned if the specified address in not set.\r
*\r
+ * \sideeffect\r
+ * The registered callback functions will be executed in the interrupt.\r
+ *\r
*******************************************************************************/\r
cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function)\r
{\r
\r
/*******************************************************************************\r
* Function Name: CySysTickGetCallback\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* The function get the specified callback pointer.\r
*\r
- * Parameters:\r
- * None\r
+ * \param number: The number of callback function address to get. The valid\r
+ * range is from 0 to 4.\r
*\r
- * Return:\r
- * None\r
+ * \return\r
+ * Returns the address of the specified callback function.\r
+ * The NULL is returned if the specified address in not initialized.\r
*\r
*******************************************************************************/\r
cySysTickCallback CySysTickGetCallback(uint32 number)\r
\r
/*******************************************************************************\r
* Function Name: CySysTickServiceCallbacks\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* System Tick timer interrupt routine\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
*******************************************************************************/\r
static void CySysTickServiceCallbacks(void)\r
{\r
#endif /* (CY_PSOC5) */\r
\r
\r
+/*******************************************************************************\r
+* Function Name: CyGetUniqueId\r
+****************************************************************************//**\r
+*\r
+* Returns the 64-bit unique ID of the device. The uniqueness of the number is\r
+* guaranteed for 10 years due to the die lot number having a cycle life of 10\r
+* years and even after 10 years, the probability of getting two identical\r
+* numbers is very small.\r
+*\r
+* \param uniqueId: The pointer to a two element 32-bit unsigned integer array. Returns\r
+* the 64-bit unique ID of the device by loading them into the integer array\r
+* pointed to by uniqueId.\r
+*\r
+*******************************************************************************/\r
+void CyGetUniqueId(uint32* uniqueId)\r
+{\r
+#if(CY_PSOC4)\r
+ uniqueId[0u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT0 );\r
+ uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT1 ) << 8u);\r
+ uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT2 ) << 16u);\r
+ uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_WAFER ) << 24u);\r
+\r
+ uniqueId[1u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_X );\r
+ uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_Y ) << 8u);\r
+ uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_SORT ) << 16u);\r
+ uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_MINOR ) << 24u);\r
+#else\r
+ uniqueId[0u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_LSB ));\r
+ uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_MSB )) << 8u);\r
+ uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_MLOGIC_REV_ID )) << 16u);\r
+ uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WAFER_NUM )) << 24u);\r
+\r
+ uniqueId[1u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_X_LOC ));\r
+ uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_Y_LOC )) << 8u);\r
+ uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WRK_WK )) << 16u);\r
+ uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_FAB_YR )) << 24u);\r
+#endif /* (CY_PSOC4) */\r
+}\r
+\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: CyLib.h\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file CyLib.h\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides the function definitions for the system, clocking, interrupts and\r
-* watchdog timer API.\r
+* \brief Provides the function definitions for the system, clocking, interrupts\r
+* and watchdog timer API.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the System Reference\r
-* Guide provided with PSoC Creator.\r
+* \note Documentation of the API's in this file is located in the System\r
+* Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#endif /* (CY_PSOC5) */\r
\r
#if(CY_PSOC5)\r
- /* System tick timer APIs */\r
+ /** System tick timer APIs */\r
typedef void (*cySysTickCallback)(void);\r
\r
void CySysTickStart(void);\r
void CySysTickClear(void);\r
#endif /* (CY_PSOC5) */\r
\r
+void CyGetUniqueId(uint32* uniqueId);\r
+\r
+\r
/***************************************\r
* API Constants\r
***************************************/\r
#define CY_VD_HVIA (0x04u)\r
\r
#define CY_VD_LVI_TRIP_LVID_MASK (0x0Fu)\r
+#define CY_VD_INT_MASK ((uint32) (0x01u))\r
\r
\r
/*******************************************************************************\r
#if defined(__ARMCC_VERSION)\r
#define CY_SYS_ISB __isb(0x0f)\r
#else /* ASM for GCC & IAR */\r
- #define CY_SYS_ISB asm volatile ("isb \n")\r
+ #define CY_SYS_ISB __asm volatile ("isb \n")\r
#endif /* (__ARMCC_VERSION) */\r
\r
#endif /* (CY_PSOC5) */\r
\r
/*******************************************************************************\r
* Macro Name: CyAssert\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* The macro that evaluates the expression and if it is false (evaluates to 0)\r
* then the processor is halted.\r
*\r
* defined by default for a Release build setting and not defined for a Debug\r
* build setting.\r
*\r
-* Parameters:\r
-* expr: Logical expression. Asserts if false.\r
-*\r
-* Return:\r
-* None\r
+* \param expr: Logical expression. Asserts if false.\r
*\r
*******************************************************************************/\r
#if !defined(NDEBUG)\r
#define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ((uint32) (1u))\r
#define CY_SYS_SYST_CSR_CLK_SRC_LFCLK ((uint32) (0u))\r
#define CY_SYS_SYST_RVR_CNT_MASK ((uint32) (0x00FFFFFFu))\r
+ #define CY_SYS_SYST_CVR_CNT_MASK ((uint32) (0x00FFFFFFu))\r
#define CY_SYS_SYST_NUM_OF_CALLBACKS ((uint32) (5u))\r
#endif /* (CY_PSOC5) */\r
\r
\r
/*******************************************************************************\r
* Macro Name: CyIntEnable\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Enables the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number\r
- *\r
- * Return:\r
- * None\r
+ * \param number: Valid range [0-31]. Interrupt number\r
*\r
*******************************************************************************/\r
#define CyIntEnable(number) CY_SET_REG32(CY_INT_ENABLE_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))\r
\r
/*******************************************************************************\r
* Macro Name: CyIntDisable\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Disables the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number.\r
- *\r
- * Return:\r
- * None\r
+ * \param number: Valid range [0-31]. Interrupt number.\r
*\r
*******************************************************************************/\r
#define CyIntDisable(number) CY_SET_REG32(CY_INT_CLEAR_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))\r
\r
/*******************************************************************************\r
* Macro Name: CyIntSetPending\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Forces the specified interrupt number to be pending.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number.\r
- *\r
- * Return:\r
- * None\r
+ * \param number: Valid range [0-31]. Interrupt number.\r
*\r
*******************************************************************************/\r
#define CyIntSetPending(number) CY_SET_REG32(CY_INT_SET_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))\r
\r
/*******************************************************************************\r
* Macro Name: CyIntClearPending\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Clears any pending interrupt for the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number.\r
- *\r
- * Return:\r
- * None\r
+ * \param number: Valid range [0-31]. Interrupt number.\r
*\r
*******************************************************************************/\r
#define CyIntClearPending(number) CY_SET_REG32(CY_INT_CLR_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))\r
\r
/*******************************************************************************\r
* Macro Name: CyIntEnable\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Enables the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number\r
- *\r
- * Return:\r
- * None\r
+ * \param number: Valid range [0-31]. Interrupt number\r
*\r
*******************************************************************************/\r
#define CyIntEnable(number) CY_SET_REG8(CY_INT_SET_EN_INDX_PTR((number)), \\r
\r
/*******************************************************************************\r
* Macro Name: CyIntDisable\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Disables the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number.\r
- *\r
- * Return:\r
- * None\r
+ * \param number: Valid range [0-31]. Interrupt number.\r
*\r
*******************************************************************************/\r
#define CyIntDisable(number) CY_SET_REG8(CY_INT_CLR_EN_INDX_PTR((number)), \\r
\r
/*******************************************************************************\r
* Macro Name: CyIntSetPending\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Forces the specified interrupt number to be pending.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number.\r
- *\r
- * Return:\r
- * None\r
+ * \param number: Valid range [0-31]. Interrupt number.\r
*\r
*******************************************************************************/\r
#define CyIntSetPending(number) CY_SET_REG8(CY_INT_SET_PEND_INDX_PTR((number)), \\r
\r
/*******************************************************************************\r
* Macro Name: CyIntClearPending\r
- ********************************************************************************\r
- * Summary:\r
+ ****************************************************************************//**\r
* Clears any pending interrupt for the specified interrupt number.\r
*\r
- * Parameters:\r
- * number: Valid range [0-31]. Interrupt number.\r
- *\r
- * Return:\r
- * None\r
+ * \param number: Valid range [0-31]. Interrupt number.\r
*\r
*******************************************************************************/\r
#define CyIntClearPending(number) CY_SET_REG8(CY_INT_CLR_PEND_INDX_PTR((number)), \\r
-/*******************************************************************************\r
-* File Name: CySpc.c\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file CySpc.c\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides an API for the System Performance Component.\r
-* The SPC functions are not meant to be called directly by the user\r
-* application.\r
+* \brief Provides an API for the System Performance Component.\r
+* The SPC functions are not meant to be called directly by the user\r
+* application.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: CySpcStart\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Starts the SPC.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CySpcStart(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CySpcStop\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Stops the SPC.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CySpcStop(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CySpcReadData\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Reads data from the SPC.\r
*\r
-* Parameters:\r
-* uint8 buffer:\r
+* \param uint8 buffer:\r
* Address to store data read.\r
*\r
-* uint8 size:\r
+* \param uint8 size:\r
* Number of bytes to read from the SPC.\r
*\r
-* Return:\r
+* \return\r
* uint8:\r
* The number of bytes read from the SPC.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CySpcLoadMultiByte\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Loads 1 to 32 bytes of data into the row latch of a Flash/EEPROM array.\r
*\r
-* Parameters:\r
-* uint8 array:\r
+* \param uint8 array:\r
* Id of the array.\r
*\r
-* uint16 address:\r
+* \param uint16 address:\r
* Flash/eeprom addrress\r
*\r
-* uint8* buffer:\r
+* \param uint8* buffer:\r
* Data to load to the row latch\r
*\r
-* uint16 number:\r
+* \param uint16 number:\r
* Number bytes to load.\r
*\r
-* Return:\r
+* \return\r
* CYRET_STARTED\r
* CYRET_CANCELED\r
* CYRET_LOCKED\r
\r
/*******************************************************************************\r
* Function Name: CySpcLoadRow\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Loads a row of data into the row latch of a Flash/EEPROM array.\r
*\r
* The buffer pointer should point to the data that should be written to the\r
* responsibility to prepare data: the preserved data are copied from flash into\r
* array with the modified data.\r
*\r
-* Parameters:\r
-* uint8 array:\r
+* \param uint8 array:\r
* Id of the array.\r
*\r
-* uint8* buffer:\r
+* \param uint8* buffer:\r
* Data to be loaded to the row latch\r
*\r
-* uint8 size:\r
+* \param uint8 size:\r
* The number of data bytes that the SPC expects to be written. Depends on the\r
* type of the array and, if the array is Flash, whether ECC is being enabled\r
* or not. There are following values: flash row latch size with ECC enabled,\r
* flash row latch size with ECC disabled and EEPROM row latch size.\r
*\r
-* Return:\r
+* \return\r
* CYRET_STARTED\r
* CYRET_CANCELED\r
* CYRET_LOCKED\r
\r
/*******************************************************************************\r
* Function Name: CySpcLoadRowFull\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Loads a row of data into the row latch of a Flash/EEPROM array.\r
*\r
* The only data that are going to be changed should be passed. The function\r
* will handle unmodified data preservation based on DWR settings and input\r
* parameters.\r
*\r
-* Parameters:\r
-* uint8 array:\r
+* \param uint8 array:\r
* Id of the array.\r
*\r
-* uint16 row:\r
+* \param uint16 row:\r
* Flash row number to be loaded.\r
*\r
-* uint8* buffer:\r
+* \param uint8* buffer:\r
* Data to be loaded to the row latch\r
*\r
-* uint8 size:\r
+* \param uint8 size:\r
* The number of data bytes that the SPC expects to be written. Depends on the\r
* type of the array and, if the array is Flash, whether ECC is being enabled\r
* or not. There are following values: flash row latch size with ECC enabled,\r
* flash row latch size with ECC disabled and EEPROM row latch size.\r
*\r
-* Return:\r
+* \return\r
* CYRET_STARTED\r
* CYRET_CANCELED\r
* CYRET_LOCKED\r
\r
/*******************************************************************************\r
* Function Name: CySpcWriteRow\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Erases then programs a row in Flash/EEPROM with data in row latch.\r
*\r
-* Parameters:\r
-* uint8 array:\r
+* \param uint8 array:\r
* Id of the array.\r
*\r
-* uint16 address:\r
+* \param uint16 address:\r
* flash/eeprom addrress\r
*\r
-* uint8 tempPolarity:\r
+* \param uint8 tempPolarity:\r
* temperature polarity.\r
-* 1: the Temp Magnitude is interpreted as a positive value\r
-* 0: the Temp Magnitude is interpreted as a negative value\r
+* \param 1: the Temp Magnitude is interpreted as a positive value\r
+* \param 0: the Temp Magnitude is interpreted as a negative value\r
*\r
-* uint8 tempMagnitude:\r
+* \param uint8 tempMagnitude:\r
* temperature magnitude.\r
*\r
-* Return:\r
+* \return\r
* CYRET_STARTED\r
* CYRET_CANCELED\r
* CYRET_LOCKED\r
\r
/*******************************************************************************\r
* Function Name: CySpcEraseSector\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Erases all data in the addressed sector (block of 64 rows).\r
*\r
-* Parameters:\r
-* uint8 array:\r
+* \param uint8 array:\r
* Id of the array.\r
*\r
-* uint8 sectorNumber:\r
+* \param uint8 sectorNumber:\r
* Zero based sector number within Flash/EEPROM array\r
*\r
-* Return:\r
+* \return\r
* CYRET_STARTED\r
* CYRET_CANCELED\r
* CYRET_LOCKED\r
\r
/*******************************************************************************\r
* Function Name: CySpcGetTemp\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Returns the internal die temperature\r
*\r
-* Parameters:\r
-* uint8 numSamples:\r
+* \param uint8 numSamples:\r
* Number of samples. Valid values are 1-5, resulting in 2 - 32 samples\r
* respectively.\r
*\r
-* uint16 timerPeriod:\r
+* \param uint16 timerPeriod:\r
* Number of ADC ACLK cycles. A valid 14 bit value is accepted, higher 2 bits\r
* of 16 bit values are ignored.\r
*\r
-* uint8 clkDivSelect:\r
+* \param uint8 clkDivSelect:\r
* ADC ACLK clock divide value. Valid values are 2 - 225.\r
*\r
-* Return:\r
+* \return\r
* CYRET_STARTED\r
* CYRET_CANCELED\r
* CYRET_LOCKED\r
\r
/*******************************************************************************\r
* Function Name: CySpcLock\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Locks the SPC so it can not be used by someone else:\r
* - Saves wait-pipeline enable state and enable pipeline (PSoC5)\r
*\r
-* Parameters:\r
-* Note\r
-*\r
-* Return:\r
+* \return\r
* CYRET_SUCCESS - if the resource was free.\r
* CYRET_LOCKED - if the SPC is in use.\r
*\r
\r
/*******************************************************************************\r
* Function Name: CySpcUnlock\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Unlocks the SPC so it can be used by someone else:\r
* - Restores wait-pipeline enable state (PSoC5)\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CySpcUnlock(void)\r
{\r
\r
/*******************************************************************************\r
* Function Name: CySpcGetAlgorithm\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Downloads SPC algorithm from SPC SROM into SRAM.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
+* \return\r
* CYRET_STARTED\r
* CYRET_LOCKED\r
*\r
-/*******************************************************************************\r
-* File Name: CySpc.c\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file CySpc.c\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides definitions for the System Performance Component API.\r
+* \brief Provides definitions for the System Performance Component API.\r
* The SPC functions are not meant to be called directly by the user\r
* application.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: EXTLED.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: EXTLED_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet EXTLED_SUT.c usage_EXTLED_Write\r
*******************************************************************************/\r
-void EXTLED_Write(uint8 value) \r
+void EXTLED_Write(uint8 value)\r
{\r
uint8 staticBits = (EXTLED_DR & (uint8)(~EXTLED_MASK));\r
EXTLED_DR = staticBits | ((uint8)(value << EXTLED_SHIFT) & EXTLED_MASK);\r
\r
/*******************************************************************************\r
* Function Name: EXTLED_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* EXTLED_DM_STRONG Strong Drive \r
-* EXTLED_DM_OD_HI Open Drain, Drives High \r
-* EXTLED_DM_OD_LO Open Drain, Drives Low \r
-* EXTLED_DM_RES_UP Resistive Pull Up \r
-* EXTLED_DM_RES_DWN Resistive Pull Down \r
-* EXTLED_DM_RES_UPDWN Resistive Pull Up/Down \r
-* EXTLED_DM_DIG_HIZ High Impedance Digital \r
-* EXTLED_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet EXTLED_SUT.c usage_EXTLED_SetDriveMode\r
*******************************************************************************/\r
-void EXTLED_SetDriveMode(uint8 mode) \r
+void EXTLED_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(EXTLED_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: EXTLED_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro EXTLED_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet EXTLED_SUT.c usage_EXTLED_Read \r
*******************************************************************************/\r
-uint8 EXTLED_Read(void) \r
+uint8 EXTLED_Read(void)\r
{\r
return (EXTLED_PS & EXTLED_MASK) >> EXTLED_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: EXTLED_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred EXTLED_Read() API because the \r
+* EXTLED_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet EXTLED_SUT.c usage_EXTLED_ReadDataReg \r
*******************************************************************************/\r
-uint8 EXTLED_ReadDataReg(void) \r
+uint8 EXTLED_ReadDataReg(void)\r
{\r
return (EXTLED_DR & EXTLED_MASK) >> EXTLED_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(EXTLED_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: EXTLED_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use EXTLED_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - EXTLED_0_INTR (First pin in the list)\r
+ * - EXTLED_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - EXTLED_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet EXTLED_SUT.c usage_EXTLED_SetInterruptMode\r
+ *******************************************************************************/\r
+ void EXTLED_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & EXTLED_0_INTR) != 0u) \r
+ { \r
+ EXTLED_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: EXTLED_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet EXTLED_SUT.c usage_EXTLED_ClearInterrupt\r
*******************************************************************************/\r
- uint8 EXTLED_ClearInterrupt(void) \r
+ uint8 EXTLED_ClearInterrupt(void)\r
{\r
return (EXTLED_INTSTAT & EXTLED_MASK) >> EXTLED_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: EXTLED.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "EXTLED_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
EXTLED__PORT == 15 && ((EXTLED__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void EXTLED_Write(uint8 value) ;\r
-void EXTLED_SetDriveMode(uint8 mode) ;\r
-uint8 EXTLED_ReadDataReg(void) ;\r
-uint8 EXTLED_Read(void) ;\r
-uint8 EXTLED_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void EXTLED_Write(uint8 value);\r
+void EXTLED_SetDriveMode(uint8 mode);\r
+uint8 EXTLED_ReadDataReg(void);\r
+uint8 EXTLED_Read(void);\r
+void EXTLED_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 EXTLED_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define EXTLED_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define EXTLED_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define EXTLED_DM_RES_UP PIN_DM_RES_UP\r
-#define EXTLED_DM_RES_DWN PIN_DM_RES_DWN\r
-#define EXTLED_DM_OD_LO PIN_DM_OD_LO\r
-#define EXTLED_DM_OD_HI PIN_DM_OD_HI\r
-#define EXTLED_DM_STRONG PIN_DM_STRONG\r
-#define EXTLED_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the EXTLED_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define EXTLED_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define EXTLED_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define EXTLED_DM_RES_UP PIN_DM_RES_UP\r
+ #define EXTLED_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define EXTLED_DM_OD_LO PIN_DM_OD_LO\r
+ #define EXTLED_DM_OD_HI PIN_DM_OD_HI\r
+ #define EXTLED_DM_STRONG PIN_DM_STRONG\r
+ #define EXTLED_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define EXTLED_MASK EXTLED__MASK\r
#define EXTLED_SHIFT EXTLED__SHIFT\r
#define EXTLED_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(EXTLED__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in EXTLED_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define EXTLED_INTR_NONE (uint16)(0x0000u)\r
+ #define EXTLED_INTR_RISING (uint16)(0x0001u)\r
+ #define EXTLED_INTR_FALLING (uint16)(0x0002u)\r
+ #define EXTLED_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define EXTLED_INTR_MASK (0x01u) \r
+#endif /* (EXTLED__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define EXTLED_PRTDSI__SYNC_OUT (* (reg8 *) EXTLED__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(EXTLED__INTSTAT) /* Interrupt Registers */\r
-\r
- #define EXTLED_INTSTAT (* (reg8 *) EXTLED__INTSTAT)\r
- #define EXTLED_SNAP (* (reg8 *) EXTLED__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(EXTLED__SIO_CFG)\r
+ #define EXTLED_SIO_HYST_EN (* (reg8 *) EXTLED__SIO_HYST_EN)\r
+ #define EXTLED_SIO_REG_HIFREQ (* (reg8 *) EXTLED__SIO_REG_HIFREQ)\r
+ #define EXTLED_SIO_CFG (* (reg8 *) EXTLED__SIO_CFG)\r
+ #define EXTLED_SIO_DIFF (* (reg8 *) EXTLED__SIO_DIFF)\r
+#endif /* (EXTLED__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(EXTLED__INTSTAT)\r
+ #define EXTLED_INTSTAT (* (reg8 *) EXTLED__INTSTAT)\r
+ #define EXTLED_SNAP (* (reg8 *) EXTLED__SNAP)\r
+ \r
+ #define EXTLED_0_INTTYPE_REG (* (reg8 *) EXTLED__0__INTTYPE)\r
+#endif /* (EXTLED__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: EXTLED.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define EXTLED_0 (EXTLED__0__PC)\r
+#define EXTLED_0 (EXTLED__0__PC)\r
+#define EXTLED_0_INTR ((uint16)((uint16)0x0001u << EXTLED__0__SHIFT))\r
+\r
+#define EXTLED_INTR_ALL ((uint16)(EXTLED_0_INTR))\r
\r
#endif /* End Pins EXTLED_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: LED1.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: LED1_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet LED1_SUT.c usage_LED1_Write\r
*******************************************************************************/\r
-void LED1_Write(uint8 value) \r
+void LED1_Write(uint8 value)\r
{\r
uint8 staticBits = (LED1_DR & (uint8)(~LED1_MASK));\r
LED1_DR = staticBits | ((uint8)(value << LED1_SHIFT) & LED1_MASK);\r
\r
/*******************************************************************************\r
* Function Name: LED1_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* LED1_DM_STRONG Strong Drive \r
-* LED1_DM_OD_HI Open Drain, Drives High \r
-* LED1_DM_OD_LO Open Drain, Drives Low \r
-* LED1_DM_RES_UP Resistive Pull Up \r
-* LED1_DM_RES_DWN Resistive Pull Down \r
-* LED1_DM_RES_UPDWN Resistive Pull Up/Down \r
-* LED1_DM_DIG_HIZ High Impedance Digital \r
-* LED1_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet LED1_SUT.c usage_LED1_SetDriveMode\r
*******************************************************************************/\r
-void LED1_SetDriveMode(uint8 mode) \r
+void LED1_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(LED1_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: LED1_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro LED1_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet LED1_SUT.c usage_LED1_Read \r
*******************************************************************************/\r
-uint8 LED1_Read(void) \r
+uint8 LED1_Read(void)\r
{\r
return (LED1_PS & LED1_MASK) >> LED1_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: LED1_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred LED1_Read() API because the \r
+* LED1_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet LED1_SUT.c usage_LED1_ReadDataReg \r
*******************************************************************************/\r
-uint8 LED1_ReadDataReg(void) \r
+uint8 LED1_ReadDataReg(void)\r
{\r
return (LED1_DR & LED1_MASK) >> LED1_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(LED1_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: LED1_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use LED1_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - LED1_0_INTR (First pin in the list)\r
+ * - LED1_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - LED1_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet LED1_SUT.c usage_LED1_SetInterruptMode\r
+ *******************************************************************************/\r
+ void LED1_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & LED1_0_INTR) != 0u) \r
+ { \r
+ LED1_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: LED1_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet LED1_SUT.c usage_LED1_ClearInterrupt\r
*******************************************************************************/\r
- uint8 LED1_ClearInterrupt(void) \r
+ uint8 LED1_ClearInterrupt(void)\r
{\r
return (LED1_INTSTAT & LED1_MASK) >> LED1_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: LED1.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "LED1_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void LED1_Write(uint8 value) ;\r
-void LED1_SetDriveMode(uint8 mode) ;\r
-uint8 LED1_ReadDataReg(void) ;\r
-uint8 LED1_Read(void) ;\r
-uint8 LED1_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void LED1_Write(uint8 value);\r
+void LED1_SetDriveMode(uint8 mode);\r
+uint8 LED1_ReadDataReg(void);\r
+uint8 LED1_Read(void);\r
+void LED1_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 LED1_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define LED1_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define LED1_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define LED1_DM_RES_UP PIN_DM_RES_UP\r
-#define LED1_DM_RES_DWN PIN_DM_RES_DWN\r
-#define LED1_DM_OD_LO PIN_DM_OD_LO\r
-#define LED1_DM_OD_HI PIN_DM_OD_HI\r
-#define LED1_DM_STRONG PIN_DM_STRONG\r
-#define LED1_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the LED1_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define LED1_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define LED1_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define LED1_DM_RES_UP PIN_DM_RES_UP\r
+ #define LED1_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define LED1_DM_OD_LO PIN_DM_OD_LO\r
+ #define LED1_DM_OD_HI PIN_DM_OD_HI\r
+ #define LED1_DM_STRONG PIN_DM_STRONG\r
+ #define LED1_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define LED1_MASK LED1__MASK\r
#define LED1_SHIFT LED1__SHIFT\r
#define LED1_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(LED1__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in LED1_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define LED1_INTR_NONE (uint16)(0x0000u)\r
+ #define LED1_INTR_RISING (uint16)(0x0001u)\r
+ #define LED1_INTR_FALLING (uint16)(0x0002u)\r
+ #define LED1_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define LED1_INTR_MASK (0x01u) \r
+#endif /* (LED1__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define LED1_PRTDSI__SYNC_OUT (* (reg8 *) LED1__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(LED1__INTSTAT) /* Interrupt Registers */\r
-\r
- #define LED1_INTSTAT (* (reg8 *) LED1__INTSTAT)\r
- #define LED1_SNAP (* (reg8 *) LED1__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(LED1__SIO_CFG)\r
+ #define LED1_SIO_HYST_EN (* (reg8 *) LED1__SIO_HYST_EN)\r
+ #define LED1_SIO_REG_HIFREQ (* (reg8 *) LED1__SIO_REG_HIFREQ)\r
+ #define LED1_SIO_CFG (* (reg8 *) LED1__SIO_CFG)\r
+ #define LED1_SIO_DIFF (* (reg8 *) LED1__SIO_DIFF)\r
+#endif /* (LED1__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(LED1__INTSTAT)\r
+ #define LED1_INTSTAT (* (reg8 *) LED1__INTSTAT)\r
+ #define LED1_SNAP (* (reg8 *) LED1__SNAP)\r
+ \r
+ #define LED1_0_INTTYPE_REG (* (reg8 *) LED1__0__INTTYPE)\r
+#endif /* (LED1__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: LED1.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define LED1_0 (LED1__0__PC)\r
+#define LED1_0 (LED1__0__PC)\r
+#define LED1_0_INTR ((uint16)((uint16)0x0001u << LED1__0__SHIFT))\r
+\r
+#define LED1_INTR_ALL ((uint16)(LED1_0_INTR))\r
\r
#endif /* End Pins LED1_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SCSI_In_DBx.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SCSI_In_DBx_0 (SCSI_In_DBx__0__PC)\r
-#define SCSI_In_DBx_1 (SCSI_In_DBx__1__PC)\r
-#define SCSI_In_DBx_2 (SCSI_In_DBx__2__PC)\r
-#define SCSI_In_DBx_3 (SCSI_In_DBx__3__PC)\r
-#define SCSI_In_DBx_4 (SCSI_In_DBx__4__PC)\r
-#define SCSI_In_DBx_5 (SCSI_In_DBx__5__PC)\r
-#define SCSI_In_DBx_6 (SCSI_In_DBx__6__PC)\r
-#define SCSI_In_DBx_7 (SCSI_In_DBx__7__PC)\r
-\r
-#define SCSI_In_DBx_DB0 (SCSI_In_DBx__DB0__PC)\r
-#define SCSI_In_DBx_DB1 (SCSI_In_DBx__DB1__PC)\r
-#define SCSI_In_DBx_DB2 (SCSI_In_DBx__DB2__PC)\r
-#define SCSI_In_DBx_DB3 (SCSI_In_DBx__DB3__PC)\r
-#define SCSI_In_DBx_DB4 (SCSI_In_DBx__DB4__PC)\r
-#define SCSI_In_DBx_DB5 (SCSI_In_DBx__DB5__PC)\r
-#define SCSI_In_DBx_DB6 (SCSI_In_DBx__DB6__PC)\r
-#define SCSI_In_DBx_DB7 (SCSI_In_DBx__DB7__PC)\r
+#define SCSI_In_DBx_0 (SCSI_In_DBx__0__PC)\r
+#define SCSI_In_DBx_0_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__0__SHIFT))\r
+\r
+#define SCSI_In_DBx_1 (SCSI_In_DBx__1__PC)\r
+#define SCSI_In_DBx_1_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__1__SHIFT))\r
+\r
+#define SCSI_In_DBx_2 (SCSI_In_DBx__2__PC)\r
+#define SCSI_In_DBx_2_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__2__SHIFT))\r
+\r
+#define SCSI_In_DBx_3 (SCSI_In_DBx__3__PC)\r
+#define SCSI_In_DBx_3_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__3__SHIFT))\r
+\r
+#define SCSI_In_DBx_4 (SCSI_In_DBx__4__PC)\r
+#define SCSI_In_DBx_4_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__4__SHIFT))\r
+\r
+#define SCSI_In_DBx_5 (SCSI_In_DBx__5__PC)\r
+#define SCSI_In_DBx_5_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__5__SHIFT))\r
+\r
+#define SCSI_In_DBx_6 (SCSI_In_DBx__6__PC)\r
+#define SCSI_In_DBx_6_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__6__SHIFT))\r
+\r
+#define SCSI_In_DBx_7 (SCSI_In_DBx__7__PC)\r
+#define SCSI_In_DBx_7_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__7__SHIFT))\r
+\r
+#define SCSI_In_DBx_INTR_ALL ((uint16)(SCSI_In_DBx_0_INTR| SCSI_In_DBx_1_INTR| SCSI_In_DBx_2_INTR| SCSI_In_DBx_3_INTR| SCSI_In_DBx_4_INTR| SCSI_In_DBx_5_INTR| SCSI_In_DBx_6_INTR| SCSI_In_DBx_7_INTR))\r
+#define SCSI_In_DBx_DB0 (SCSI_In_DBx__DB0__PC)\r
+#define SCSI_In_DBx_DB0_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__0__SHIFT))\r
+\r
+#define SCSI_In_DBx_DB1 (SCSI_In_DBx__DB1__PC)\r
+#define SCSI_In_DBx_DB1_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__1__SHIFT))\r
+\r
+#define SCSI_In_DBx_DB2 (SCSI_In_DBx__DB2__PC)\r
+#define SCSI_In_DBx_DB2_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__2__SHIFT))\r
+\r
+#define SCSI_In_DBx_DB3 (SCSI_In_DBx__DB3__PC)\r
+#define SCSI_In_DBx_DB3_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__3__SHIFT))\r
+\r
+#define SCSI_In_DBx_DB4 (SCSI_In_DBx__DB4__PC)\r
+#define SCSI_In_DBx_DB4_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__4__SHIFT))\r
+\r
+#define SCSI_In_DBx_DB5 (SCSI_In_DBx__DB5__PC)\r
+#define SCSI_In_DBx_DB5_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__5__SHIFT))\r
+\r
+#define SCSI_In_DBx_DB6 (SCSI_In_DBx__DB6__PC)\r
+#define SCSI_In_DBx_DB6_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__6__SHIFT))\r
+\r
+#define SCSI_In_DBx_DB7 (SCSI_In_DBx__DB7__PC)\r
+#define SCSI_In_DBx_DB7_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__7__SHIFT))\r
\r
#endif /* End Pins SCSI_In_DBx_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SCSI_In.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SCSI_In_0 (SCSI_In__0__PC)\r
-#define SCSI_In_1 (SCSI_In__1__PC)\r
-#define SCSI_In_2 (SCSI_In__2__PC)\r
-#define SCSI_In_3 (SCSI_In__3__PC)\r
-#define SCSI_In_4 (SCSI_In__4__PC)\r
-\r
-#define SCSI_In_DBP (SCSI_In__DBP__PC)\r
-#define SCSI_In_MSG (SCSI_In__MSG__PC)\r
-#define SCSI_In_CD (SCSI_In__CD__PC)\r
-#define SCSI_In_REQ (SCSI_In__REQ__PC)\r
-#define SCSI_In_IO (SCSI_In__IO__PC)\r
+#define SCSI_In_0 (SCSI_In__0__PC)\r
+#define SCSI_In_0_INTR ((uint16)((uint16)0x0001u << SCSI_In__0__SHIFT))\r
+\r
+#define SCSI_In_1 (SCSI_In__1__PC)\r
+#define SCSI_In_1_INTR ((uint16)((uint16)0x0001u << SCSI_In__1__SHIFT))\r
+\r
+#define SCSI_In_2 (SCSI_In__2__PC)\r
+#define SCSI_In_2_INTR ((uint16)((uint16)0x0001u << SCSI_In__2__SHIFT))\r
+\r
+#define SCSI_In_3 (SCSI_In__3__PC)\r
+#define SCSI_In_3_INTR ((uint16)((uint16)0x0001u << SCSI_In__3__SHIFT))\r
+\r
+#define SCSI_In_4 (SCSI_In__4__PC)\r
+#define SCSI_In_4_INTR ((uint16)((uint16)0x0001u << SCSI_In__4__SHIFT))\r
+\r
+#define SCSI_In_INTR_ALL ((uint16)(SCSI_In_0_INTR| SCSI_In_1_INTR| SCSI_In_2_INTR| SCSI_In_3_INTR| SCSI_In_4_INTR))\r
+#define SCSI_In_DBP (SCSI_In__DBP__PC)\r
+#define SCSI_In_DBP_INTR ((uint16)((uint16)0x0001u << SCSI_In__0__SHIFT))\r
+\r
+#define SCSI_In_MSG (SCSI_In__MSG__PC)\r
+#define SCSI_In_MSG_INTR ((uint16)((uint16)0x0001u << SCSI_In__1__SHIFT))\r
+\r
+#define SCSI_In_CD (SCSI_In__CD__PC)\r
+#define SCSI_In_CD_INTR ((uint16)((uint16)0x0001u << SCSI_In__2__SHIFT))\r
+\r
+#define SCSI_In_REQ (SCSI_In__REQ__PC)\r
+#define SCSI_In_REQ_INTR ((uint16)((uint16)0x0001u << SCSI_In__3__SHIFT))\r
+\r
+#define SCSI_In_IO (SCSI_In__IO__PC)\r
+#define SCSI_In_IO_INTR ((uint16)((uint16)0x0001u << SCSI_In__4__SHIFT))\r
\r
#endif /* End Pins SCSI_In_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SCSI_Noise.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SCSI_Noise_0 (SCSI_Noise__0__PC)\r
-#define SCSI_Noise_1 (SCSI_Noise__1__PC)\r
-#define SCSI_Noise_2 (SCSI_Noise__2__PC)\r
-#define SCSI_Noise_3 (SCSI_Noise__3__PC)\r
-#define SCSI_Noise_4 (SCSI_Noise__4__PC)\r
-\r
-#define SCSI_Noise_ATN (SCSI_Noise__ATN__PC)\r
-#define SCSI_Noise_BSY (SCSI_Noise__BSY__PC)\r
-#define SCSI_Noise_SEL (SCSI_Noise__SEL__PC)\r
-#define SCSI_Noise_RST (SCSI_Noise__RST__PC)\r
-#define SCSI_Noise_ACK (SCSI_Noise__ACK__PC)\r
+#define SCSI_Noise_0 (SCSI_Noise__0__PC)\r
+#define SCSI_Noise_0_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__0__SHIFT))\r
+\r
+#define SCSI_Noise_1 (SCSI_Noise__1__PC)\r
+#define SCSI_Noise_1_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__1__SHIFT))\r
+\r
+#define SCSI_Noise_2 (SCSI_Noise__2__PC)\r
+#define SCSI_Noise_2_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__2__SHIFT))\r
+\r
+#define SCSI_Noise_3 (SCSI_Noise__3__PC)\r
+#define SCSI_Noise_3_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__3__SHIFT))\r
+\r
+#define SCSI_Noise_4 (SCSI_Noise__4__PC)\r
+#define SCSI_Noise_4_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__4__SHIFT))\r
+\r
+#define SCSI_Noise_INTR_ALL ((uint16)(SCSI_Noise_0_INTR| SCSI_Noise_1_INTR| SCSI_Noise_2_INTR| SCSI_Noise_3_INTR| SCSI_Noise_4_INTR))\r
+#define SCSI_Noise_ATN (SCSI_Noise__ATN__PC)\r
+#define SCSI_Noise_ATN_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__0__SHIFT))\r
+\r
+#define SCSI_Noise_BSY (SCSI_Noise__BSY__PC)\r
+#define SCSI_Noise_BSY_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__1__SHIFT))\r
+\r
+#define SCSI_Noise_SEL (SCSI_Noise__SEL__PC)\r
+#define SCSI_Noise_SEL_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__2__SHIFT))\r
+\r
+#define SCSI_Noise_RST (SCSI_Noise__RST__PC)\r
+#define SCSI_Noise_RST_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__3__SHIFT))\r
+\r
+#define SCSI_Noise_ACK (SCSI_Noise__ACK__PC)\r
+#define SCSI_Noise_ACK_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__4__SHIFT))\r
\r
#endif /* End Pins SCSI_Noise_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SCSI_Out_DBx.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SCSI_Out_DBx_0 (SCSI_Out_DBx__0__PC)\r
-#define SCSI_Out_DBx_1 (SCSI_Out_DBx__1__PC)\r
-#define SCSI_Out_DBx_2 (SCSI_Out_DBx__2__PC)\r
-#define SCSI_Out_DBx_3 (SCSI_Out_DBx__3__PC)\r
-#define SCSI_Out_DBx_4 (SCSI_Out_DBx__4__PC)\r
-#define SCSI_Out_DBx_5 (SCSI_Out_DBx__5__PC)\r
-#define SCSI_Out_DBx_6 (SCSI_Out_DBx__6__PC)\r
-#define SCSI_Out_DBx_7 (SCSI_Out_DBx__7__PC)\r
-\r
-#define SCSI_Out_DBx_DB0 (SCSI_Out_DBx__DB0__PC)\r
-#define SCSI_Out_DBx_DB1 (SCSI_Out_DBx__DB1__PC)\r
-#define SCSI_Out_DBx_DB2 (SCSI_Out_DBx__DB2__PC)\r
-#define SCSI_Out_DBx_DB3 (SCSI_Out_DBx__DB3__PC)\r
-#define SCSI_Out_DBx_DB4 (SCSI_Out_DBx__DB4__PC)\r
-#define SCSI_Out_DBx_DB5 (SCSI_Out_DBx__DB5__PC)\r
-#define SCSI_Out_DBx_DB6 (SCSI_Out_DBx__DB6__PC)\r
-#define SCSI_Out_DBx_DB7 (SCSI_Out_DBx__DB7__PC)\r
+#define SCSI_Out_DBx_0 (SCSI_Out_DBx__0__PC)\r
+#define SCSI_Out_DBx_0_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__0__SHIFT))\r
+\r
+#define SCSI_Out_DBx_1 (SCSI_Out_DBx__1__PC)\r
+#define SCSI_Out_DBx_1_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__1__SHIFT))\r
+\r
+#define SCSI_Out_DBx_2 (SCSI_Out_DBx__2__PC)\r
+#define SCSI_Out_DBx_2_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__2__SHIFT))\r
+\r
+#define SCSI_Out_DBx_3 (SCSI_Out_DBx__3__PC)\r
+#define SCSI_Out_DBx_3_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__3__SHIFT))\r
+\r
+#define SCSI_Out_DBx_4 (SCSI_Out_DBx__4__PC)\r
+#define SCSI_Out_DBx_4_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__4__SHIFT))\r
+\r
+#define SCSI_Out_DBx_5 (SCSI_Out_DBx__5__PC)\r
+#define SCSI_Out_DBx_5_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__5__SHIFT))\r
+\r
+#define SCSI_Out_DBx_6 (SCSI_Out_DBx__6__PC)\r
+#define SCSI_Out_DBx_6_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__6__SHIFT))\r
+\r
+#define SCSI_Out_DBx_7 (SCSI_Out_DBx__7__PC)\r
+#define SCSI_Out_DBx_7_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__7__SHIFT))\r
+\r
+#define SCSI_Out_DBx_INTR_ALL ((uint16)(SCSI_Out_DBx_0_INTR| SCSI_Out_DBx_1_INTR| SCSI_Out_DBx_2_INTR| SCSI_Out_DBx_3_INTR| SCSI_Out_DBx_4_INTR| SCSI_Out_DBx_5_INTR| SCSI_Out_DBx_6_INTR| SCSI_Out_DBx_7_INTR))\r
+#define SCSI_Out_DBx_DB0 (SCSI_Out_DBx__DB0__PC)\r
+#define SCSI_Out_DBx_DB0_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__0__SHIFT))\r
+\r
+#define SCSI_Out_DBx_DB1 (SCSI_Out_DBx__DB1__PC)\r
+#define SCSI_Out_DBx_DB1_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__1__SHIFT))\r
+\r
+#define SCSI_Out_DBx_DB2 (SCSI_Out_DBx__DB2__PC)\r
+#define SCSI_Out_DBx_DB2_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__2__SHIFT))\r
+\r
+#define SCSI_Out_DBx_DB3 (SCSI_Out_DBx__DB3__PC)\r
+#define SCSI_Out_DBx_DB3_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__3__SHIFT))\r
+\r
+#define SCSI_Out_DBx_DB4 (SCSI_Out_DBx__DB4__PC)\r
+#define SCSI_Out_DBx_DB4_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__4__SHIFT))\r
+\r
+#define SCSI_Out_DBx_DB5 (SCSI_Out_DBx__DB5__PC)\r
+#define SCSI_Out_DBx_DB5_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__5__SHIFT))\r
+\r
+#define SCSI_Out_DBx_DB6 (SCSI_Out_DBx__DB6__PC)\r
+#define SCSI_Out_DBx_DB6_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__6__SHIFT))\r
+\r
+#define SCSI_Out_DBx_DB7 (SCSI_Out_DBx__DB7__PC)\r
+#define SCSI_Out_DBx_DB7_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__7__SHIFT))\r
\r
#endif /* End Pins SCSI_Out_DBx_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SCSI_Out.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SCSI_Out_0 (SCSI_Out__0__PC)\r
-#define SCSI_Out_1 (SCSI_Out__1__PC)\r
-#define SCSI_Out_2 (SCSI_Out__2__PC)\r
-#define SCSI_Out_3 (SCSI_Out__3__PC)\r
-#define SCSI_Out_4 (SCSI_Out__4__PC)\r
-#define SCSI_Out_5 (SCSI_Out__5__PC)\r
-#define SCSI_Out_6 (SCSI_Out__6__PC)\r
-#define SCSI_Out_7 (SCSI_Out__7__PC)\r
-#define SCSI_Out_8 (SCSI_Out__8__PC)\r
-#define SCSI_Out_9 (SCSI_Out__9__PC)\r
-\r
-#define SCSI_Out_DBP_raw (SCSI_Out__DBP_raw__PC)\r
-#define SCSI_Out_ATN (SCSI_Out__ATN__PC)\r
-#define SCSI_Out_BSY (SCSI_Out__BSY__PC)\r
-#define SCSI_Out_ACK (SCSI_Out__ACK__PC)\r
-#define SCSI_Out_RST (SCSI_Out__RST__PC)\r
-#define SCSI_Out_MSG_raw (SCSI_Out__MSG_raw__PC)\r
-#define SCSI_Out_SEL (SCSI_Out__SEL__PC)\r
-#define SCSI_Out_CD_raw (SCSI_Out__CD_raw__PC)\r
-#define SCSI_Out_REQ (SCSI_Out__REQ__PC)\r
-#define SCSI_Out_IO_raw (SCSI_Out__IO_raw__PC)\r
+#define SCSI_Out_0 (SCSI_Out__0__PC)\r
+#define SCSI_Out_0_INTR ((uint16)((uint16)0x0001u << SCSI_Out__0__SHIFT))\r
+\r
+#define SCSI_Out_1 (SCSI_Out__1__PC)\r
+#define SCSI_Out_1_INTR ((uint16)((uint16)0x0001u << SCSI_Out__1__SHIFT))\r
+\r
+#define SCSI_Out_2 (SCSI_Out__2__PC)\r
+#define SCSI_Out_2_INTR ((uint16)((uint16)0x0001u << SCSI_Out__2__SHIFT))\r
+\r
+#define SCSI_Out_3 (SCSI_Out__3__PC)\r
+#define SCSI_Out_3_INTR ((uint16)((uint16)0x0001u << SCSI_Out__3__SHIFT))\r
+\r
+#define SCSI_Out_4 (SCSI_Out__4__PC)\r
+#define SCSI_Out_4_INTR ((uint16)((uint16)0x0001u << SCSI_Out__4__SHIFT))\r
+\r
+#define SCSI_Out_5 (SCSI_Out__5__PC)\r
+#define SCSI_Out_5_INTR ((uint16)((uint16)0x0001u << SCSI_Out__5__SHIFT))\r
+\r
+#define SCSI_Out_6 (SCSI_Out__6__PC)\r
+#define SCSI_Out_6_INTR ((uint16)((uint16)0x0001u << SCSI_Out__6__SHIFT))\r
+\r
+#define SCSI_Out_7 (SCSI_Out__7__PC)\r
+#define SCSI_Out_7_INTR ((uint16)((uint16)0x0001u << SCSI_Out__7__SHIFT))\r
+\r
+#define SCSI_Out_8 (SCSI_Out__8__PC)\r
+#define SCSI_Out_8_INTR ((uint16)((uint16)0x0001u << SCSI_Out__8__SHIFT))\r
+\r
+#define SCSI_Out_9 (SCSI_Out__9__PC)\r
+#define SCSI_Out_9_INTR ((uint16)((uint16)0x0001u << SCSI_Out__9__SHIFT))\r
+\r
+#define SCSI_Out_INTR_ALL ((uint16)(SCSI_Out_0_INTR| SCSI_Out_1_INTR| SCSI_Out_2_INTR| SCSI_Out_3_INTR| SCSI_Out_4_INTR| SCSI_Out_5_INTR| SCSI_Out_6_INTR| SCSI_Out_7_INTR| SCSI_Out_8_INTR| SCSI_Out_9_INTR))\r
+#define SCSI_Out_DBP_raw (SCSI_Out__DBP_raw__PC)\r
+#define SCSI_Out_DBP_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__0__SHIFT))\r
+\r
+#define SCSI_Out_ATN (SCSI_Out__ATN__PC)\r
+#define SCSI_Out_ATN_INTR ((uint16)((uint16)0x0001u << SCSI_Out__1__SHIFT))\r
+\r
+#define SCSI_Out_BSY (SCSI_Out__BSY__PC)\r
+#define SCSI_Out_BSY_INTR ((uint16)((uint16)0x0001u << SCSI_Out__2__SHIFT))\r
+\r
+#define SCSI_Out_ACK (SCSI_Out__ACK__PC)\r
+#define SCSI_Out_ACK_INTR ((uint16)((uint16)0x0001u << SCSI_Out__3__SHIFT))\r
+\r
+#define SCSI_Out_RST (SCSI_Out__RST__PC)\r
+#define SCSI_Out_RST_INTR ((uint16)((uint16)0x0001u << SCSI_Out__4__SHIFT))\r
+\r
+#define SCSI_Out_MSG_raw (SCSI_Out__MSG_raw__PC)\r
+#define SCSI_Out_MSG_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__5__SHIFT))\r
+\r
+#define SCSI_Out_SEL (SCSI_Out__SEL__PC)\r
+#define SCSI_Out_SEL_INTR ((uint16)((uint16)0x0001u << SCSI_Out__6__SHIFT))\r
+\r
+#define SCSI_Out_CD_raw (SCSI_Out__CD_raw__PC)\r
+#define SCSI_Out_CD_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__7__SHIFT))\r
+\r
+#define SCSI_Out_REQ (SCSI_Out__REQ__PC)\r
+#define SCSI_Out_REQ_INTR ((uint16)((uint16)0x0001u << SCSI_Out__8__SHIFT))\r
+\r
+#define SCSI_Out_IO_raw (SCSI_Out__IO_raw__PC)\r
+#define SCSI_Out_IO_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__9__SHIFT))\r
\r
#endif /* End Pins SCSI_Out_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SD_CD.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: SD_CD_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_CD_SUT.c usage_SD_CD_Write\r
*******************************************************************************/\r
-void SD_CD_Write(uint8 value) \r
+void SD_CD_Write(uint8 value)\r
{\r
uint8 staticBits = (SD_CD_DR & (uint8)(~SD_CD_MASK));\r
SD_CD_DR = staticBits | ((uint8)(value << SD_CD_SHIFT) & SD_CD_MASK);\r
\r
/*******************************************************************************\r
* Function Name: SD_CD_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* SD_CD_DM_STRONG Strong Drive \r
-* SD_CD_DM_OD_HI Open Drain, Drives High \r
-* SD_CD_DM_OD_LO Open Drain, Drives Low \r
-* SD_CD_DM_RES_UP Resistive Pull Up \r
-* SD_CD_DM_RES_DWN Resistive Pull Down \r
-* SD_CD_DM_RES_UPDWN Resistive Pull Up/Down \r
-* SD_CD_DM_DIG_HIZ High Impedance Digital \r
-* SD_CD_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_CD_SUT.c usage_SD_CD_SetDriveMode\r
*******************************************************************************/\r
-void SD_CD_SetDriveMode(uint8 mode) \r
+void SD_CD_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(SD_CD_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_CD_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro SD_CD_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet SD_CD_SUT.c usage_SD_CD_Read \r
*******************************************************************************/\r
-uint8 SD_CD_Read(void) \r
+uint8 SD_CD_Read(void)\r
{\r
return (SD_CD_PS & SD_CD_MASK) >> SD_CD_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_CD_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred SD_CD_Read() API because the \r
+* SD_CD_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet SD_CD_SUT.c usage_SD_CD_ReadDataReg \r
*******************************************************************************/\r
-uint8 SD_CD_ReadDataReg(void) \r
+uint8 SD_CD_ReadDataReg(void)\r
{\r
return (SD_CD_DR & SD_CD_MASK) >> SD_CD_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(SD_CD_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: SD_CD_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use SD_CD_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - SD_CD_0_INTR (First pin in the list)\r
+ * - SD_CD_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - SD_CD_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_CD_SUT.c usage_SD_CD_SetInterruptMode\r
+ *******************************************************************************/\r
+ void SD_CD_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & SD_CD_0_INTR) != 0u) \r
+ { \r
+ SD_CD_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: SD_CD_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_CD_SUT.c usage_SD_CD_ClearInterrupt\r
*******************************************************************************/\r
- uint8 SD_CD_ClearInterrupt(void) \r
+ uint8 SD_CD_ClearInterrupt(void)\r
{\r
return (SD_CD_INTSTAT & SD_CD_MASK) >> SD_CD_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: SD_CD.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "SD_CD_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
SD_CD__PORT == 15 && ((SD_CD__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void SD_CD_Write(uint8 value) ;\r
-void SD_CD_SetDriveMode(uint8 mode) ;\r
-uint8 SD_CD_ReadDataReg(void) ;\r
-uint8 SD_CD_Read(void) ;\r
-uint8 SD_CD_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void SD_CD_Write(uint8 value);\r
+void SD_CD_SetDriveMode(uint8 mode);\r
+uint8 SD_CD_ReadDataReg(void);\r
+uint8 SD_CD_Read(void);\r
+void SD_CD_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 SD_CD_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define SD_CD_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define SD_CD_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define SD_CD_DM_RES_UP PIN_DM_RES_UP\r
-#define SD_CD_DM_RES_DWN PIN_DM_RES_DWN\r
-#define SD_CD_DM_OD_LO PIN_DM_OD_LO\r
-#define SD_CD_DM_OD_HI PIN_DM_OD_HI\r
-#define SD_CD_DM_STRONG PIN_DM_STRONG\r
-#define SD_CD_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the SD_CD_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define SD_CD_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define SD_CD_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define SD_CD_DM_RES_UP PIN_DM_RES_UP\r
+ #define SD_CD_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define SD_CD_DM_OD_LO PIN_DM_OD_LO\r
+ #define SD_CD_DM_OD_HI PIN_DM_OD_HI\r
+ #define SD_CD_DM_STRONG PIN_DM_STRONG\r
+ #define SD_CD_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define SD_CD_MASK SD_CD__MASK\r
#define SD_CD_SHIFT SD_CD__SHIFT\r
#define SD_CD_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(SD_CD__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in SD_CD_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define SD_CD_INTR_NONE (uint16)(0x0000u)\r
+ #define SD_CD_INTR_RISING (uint16)(0x0001u)\r
+ #define SD_CD_INTR_FALLING (uint16)(0x0002u)\r
+ #define SD_CD_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define SD_CD_INTR_MASK (0x01u) \r
+#endif /* (SD_CD__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define SD_CD_PRTDSI__SYNC_OUT (* (reg8 *) SD_CD__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(SD_CD__INTSTAT) /* Interrupt Registers */\r
-\r
- #define SD_CD_INTSTAT (* (reg8 *) SD_CD__INTSTAT)\r
- #define SD_CD_SNAP (* (reg8 *) SD_CD__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(SD_CD__SIO_CFG)\r
+ #define SD_CD_SIO_HYST_EN (* (reg8 *) SD_CD__SIO_HYST_EN)\r
+ #define SD_CD_SIO_REG_HIFREQ (* (reg8 *) SD_CD__SIO_REG_HIFREQ)\r
+ #define SD_CD_SIO_CFG (* (reg8 *) SD_CD__SIO_CFG)\r
+ #define SD_CD_SIO_DIFF (* (reg8 *) SD_CD__SIO_DIFF)\r
+#endif /* (SD_CD__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(SD_CD__INTSTAT)\r
+ #define SD_CD_INTSTAT (* (reg8 *) SD_CD__INTSTAT)\r
+ #define SD_CD_SNAP (* (reg8 *) SD_CD__SNAP)\r
+ \r
+ #define SD_CD_0_INTTYPE_REG (* (reg8 *) SD_CD__0__INTTYPE)\r
+#endif /* (SD_CD__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: SD_CD.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_CD_0 (SD_CD__0__PC)\r
+#define SD_CD_0 (SD_CD__0__PC)\r
+#define SD_CD_0_INTR ((uint16)((uint16)0x0001u << SD_CD__0__SHIFT))\r
+\r
+#define SD_CD_INTR_ALL ((uint16)(SD_CD_0_INTR))\r
\r
#endif /* End Pins SD_CD_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SD_CS.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: SD_CS_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_CS_SUT.c usage_SD_CS_Write\r
*******************************************************************************/\r
-void SD_CS_Write(uint8 value) \r
+void SD_CS_Write(uint8 value)\r
{\r
uint8 staticBits = (SD_CS_DR & (uint8)(~SD_CS_MASK));\r
SD_CS_DR = staticBits | ((uint8)(value << SD_CS_SHIFT) & SD_CS_MASK);\r
\r
/*******************************************************************************\r
* Function Name: SD_CS_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* SD_CS_DM_STRONG Strong Drive \r
-* SD_CS_DM_OD_HI Open Drain, Drives High \r
-* SD_CS_DM_OD_LO Open Drain, Drives Low \r
-* SD_CS_DM_RES_UP Resistive Pull Up \r
-* SD_CS_DM_RES_DWN Resistive Pull Down \r
-* SD_CS_DM_RES_UPDWN Resistive Pull Up/Down \r
-* SD_CS_DM_DIG_HIZ High Impedance Digital \r
-* SD_CS_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_CS_SUT.c usage_SD_CS_SetDriveMode\r
*******************************************************************************/\r
-void SD_CS_SetDriveMode(uint8 mode) \r
+void SD_CS_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(SD_CS_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_CS_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro SD_CS_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet SD_CS_SUT.c usage_SD_CS_Read \r
*******************************************************************************/\r
-uint8 SD_CS_Read(void) \r
+uint8 SD_CS_Read(void)\r
{\r
return (SD_CS_PS & SD_CS_MASK) >> SD_CS_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_CS_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred SD_CS_Read() API because the \r
+* SD_CS_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet SD_CS_SUT.c usage_SD_CS_ReadDataReg \r
*******************************************************************************/\r
-uint8 SD_CS_ReadDataReg(void) \r
+uint8 SD_CS_ReadDataReg(void)\r
{\r
return (SD_CS_DR & SD_CS_MASK) >> SD_CS_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(SD_CS_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: SD_CS_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use SD_CS_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - SD_CS_0_INTR (First pin in the list)\r
+ * - SD_CS_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - SD_CS_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_CS_SUT.c usage_SD_CS_SetInterruptMode\r
+ *******************************************************************************/\r
+ void SD_CS_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & SD_CS_0_INTR) != 0u) \r
+ { \r
+ SD_CS_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: SD_CS_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_CS_SUT.c usage_SD_CS_ClearInterrupt\r
*******************************************************************************/\r
- uint8 SD_CS_ClearInterrupt(void) \r
+ uint8 SD_CS_ClearInterrupt(void)\r
{\r
return (SD_CS_INTSTAT & SD_CS_MASK) >> SD_CS_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: SD_CS.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "SD_CS_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
SD_CS__PORT == 15 && ((SD_CS__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void SD_CS_Write(uint8 value) ;\r
-void SD_CS_SetDriveMode(uint8 mode) ;\r
-uint8 SD_CS_ReadDataReg(void) ;\r
-uint8 SD_CS_Read(void) ;\r
-uint8 SD_CS_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void SD_CS_Write(uint8 value);\r
+void SD_CS_SetDriveMode(uint8 mode);\r
+uint8 SD_CS_ReadDataReg(void);\r
+uint8 SD_CS_Read(void);\r
+void SD_CS_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 SD_CS_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define SD_CS_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define SD_CS_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define SD_CS_DM_RES_UP PIN_DM_RES_UP\r
-#define SD_CS_DM_RES_DWN PIN_DM_RES_DWN\r
-#define SD_CS_DM_OD_LO PIN_DM_OD_LO\r
-#define SD_CS_DM_OD_HI PIN_DM_OD_HI\r
-#define SD_CS_DM_STRONG PIN_DM_STRONG\r
-#define SD_CS_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the SD_CS_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define SD_CS_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define SD_CS_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define SD_CS_DM_RES_UP PIN_DM_RES_UP\r
+ #define SD_CS_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define SD_CS_DM_OD_LO PIN_DM_OD_LO\r
+ #define SD_CS_DM_OD_HI PIN_DM_OD_HI\r
+ #define SD_CS_DM_STRONG PIN_DM_STRONG\r
+ #define SD_CS_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define SD_CS_MASK SD_CS__MASK\r
#define SD_CS_SHIFT SD_CS__SHIFT\r
#define SD_CS_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(SD_CS__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in SD_CS_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define SD_CS_INTR_NONE (uint16)(0x0000u)\r
+ #define SD_CS_INTR_RISING (uint16)(0x0001u)\r
+ #define SD_CS_INTR_FALLING (uint16)(0x0002u)\r
+ #define SD_CS_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define SD_CS_INTR_MASK (0x01u) \r
+#endif /* (SD_CS__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define SD_CS_PRTDSI__SYNC_OUT (* (reg8 *) SD_CS__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(SD_CS__INTSTAT) /* Interrupt Registers */\r
-\r
- #define SD_CS_INTSTAT (* (reg8 *) SD_CS__INTSTAT)\r
- #define SD_CS_SNAP (* (reg8 *) SD_CS__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(SD_CS__SIO_CFG)\r
+ #define SD_CS_SIO_HYST_EN (* (reg8 *) SD_CS__SIO_HYST_EN)\r
+ #define SD_CS_SIO_REG_HIFREQ (* (reg8 *) SD_CS__SIO_REG_HIFREQ)\r
+ #define SD_CS_SIO_CFG (* (reg8 *) SD_CS__SIO_CFG)\r
+ #define SD_CS_SIO_DIFF (* (reg8 *) SD_CS__SIO_DIFF)\r
+#endif /* (SD_CS__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(SD_CS__INTSTAT)\r
+ #define SD_CS_INTSTAT (* (reg8 *) SD_CS__INTSTAT)\r
+ #define SD_CS_SNAP (* (reg8 *) SD_CS__SNAP)\r
+ \r
+ #define SD_CS_0_INTTYPE_REG (* (reg8 *) SD_CS__0__INTTYPE)\r
+#endif /* (SD_CS__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: SD_CS.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_CS_0 (SD_CS__0__PC)\r
+#define SD_CS_0 (SD_CS__0__PC)\r
+#define SD_CS_0_INTR ((uint16)((uint16)0x0001u << SD_CS__0__SHIFT))\r
+\r
+#define SD_CS_INTR_ALL ((uint16)(SD_CS_0_INTR))\r
\r
#endif /* End Pins SD_CS_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SD_MISO.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: SD_MISO_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_MISO_SUT.c usage_SD_MISO_Write\r
*******************************************************************************/\r
-void SD_MISO_Write(uint8 value) \r
+void SD_MISO_Write(uint8 value)\r
{\r
uint8 staticBits = (SD_MISO_DR & (uint8)(~SD_MISO_MASK));\r
SD_MISO_DR = staticBits | ((uint8)(value << SD_MISO_SHIFT) & SD_MISO_MASK);\r
\r
/*******************************************************************************\r
* Function Name: SD_MISO_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* SD_MISO_DM_STRONG Strong Drive \r
-* SD_MISO_DM_OD_HI Open Drain, Drives High \r
-* SD_MISO_DM_OD_LO Open Drain, Drives Low \r
-* SD_MISO_DM_RES_UP Resistive Pull Up \r
-* SD_MISO_DM_RES_DWN Resistive Pull Down \r
-* SD_MISO_DM_RES_UPDWN Resistive Pull Up/Down \r
-* SD_MISO_DM_DIG_HIZ High Impedance Digital \r
-* SD_MISO_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_MISO_SUT.c usage_SD_MISO_SetDriveMode\r
*******************************************************************************/\r
-void SD_MISO_SetDriveMode(uint8 mode) \r
+void SD_MISO_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(SD_MISO_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_MISO_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro SD_MISO_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet SD_MISO_SUT.c usage_SD_MISO_Read \r
*******************************************************************************/\r
-uint8 SD_MISO_Read(void) \r
+uint8 SD_MISO_Read(void)\r
{\r
return (SD_MISO_PS & SD_MISO_MASK) >> SD_MISO_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_MISO_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred SD_MISO_Read() API because the \r
+* SD_MISO_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet SD_MISO_SUT.c usage_SD_MISO_ReadDataReg \r
*******************************************************************************/\r
-uint8 SD_MISO_ReadDataReg(void) \r
+uint8 SD_MISO_ReadDataReg(void)\r
{\r
return (SD_MISO_DR & SD_MISO_MASK) >> SD_MISO_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(SD_MISO_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: SD_MISO_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use SD_MISO_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - SD_MISO_0_INTR (First pin in the list)\r
+ * - SD_MISO_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - SD_MISO_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_MISO_SUT.c usage_SD_MISO_SetInterruptMode\r
+ *******************************************************************************/\r
+ void SD_MISO_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & SD_MISO_0_INTR) != 0u) \r
+ { \r
+ SD_MISO_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: SD_MISO_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_MISO_SUT.c usage_SD_MISO_ClearInterrupt\r
*******************************************************************************/\r
- uint8 SD_MISO_ClearInterrupt(void) \r
+ uint8 SD_MISO_ClearInterrupt(void)\r
{\r
return (SD_MISO_INTSTAT & SD_MISO_MASK) >> SD_MISO_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: SD_MISO.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "SD_MISO_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
SD_MISO__PORT == 15 && ((SD_MISO__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void SD_MISO_Write(uint8 value) ;\r
-void SD_MISO_SetDriveMode(uint8 mode) ;\r
-uint8 SD_MISO_ReadDataReg(void) ;\r
-uint8 SD_MISO_Read(void) ;\r
-uint8 SD_MISO_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void SD_MISO_Write(uint8 value);\r
+void SD_MISO_SetDriveMode(uint8 mode);\r
+uint8 SD_MISO_ReadDataReg(void);\r
+uint8 SD_MISO_Read(void);\r
+void SD_MISO_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 SD_MISO_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define SD_MISO_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define SD_MISO_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define SD_MISO_DM_RES_UP PIN_DM_RES_UP\r
-#define SD_MISO_DM_RES_DWN PIN_DM_RES_DWN\r
-#define SD_MISO_DM_OD_LO PIN_DM_OD_LO\r
-#define SD_MISO_DM_OD_HI PIN_DM_OD_HI\r
-#define SD_MISO_DM_STRONG PIN_DM_STRONG\r
-#define SD_MISO_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the SD_MISO_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define SD_MISO_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define SD_MISO_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define SD_MISO_DM_RES_UP PIN_DM_RES_UP\r
+ #define SD_MISO_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define SD_MISO_DM_OD_LO PIN_DM_OD_LO\r
+ #define SD_MISO_DM_OD_HI PIN_DM_OD_HI\r
+ #define SD_MISO_DM_STRONG PIN_DM_STRONG\r
+ #define SD_MISO_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define SD_MISO_MASK SD_MISO__MASK\r
#define SD_MISO_SHIFT SD_MISO__SHIFT\r
#define SD_MISO_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(SD_MISO__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in SD_MISO_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define SD_MISO_INTR_NONE (uint16)(0x0000u)\r
+ #define SD_MISO_INTR_RISING (uint16)(0x0001u)\r
+ #define SD_MISO_INTR_FALLING (uint16)(0x0002u)\r
+ #define SD_MISO_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define SD_MISO_INTR_MASK (0x01u) \r
+#endif /* (SD_MISO__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define SD_MISO_PRTDSI__SYNC_OUT (* (reg8 *) SD_MISO__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(SD_MISO__INTSTAT) /* Interrupt Registers */\r
-\r
- #define SD_MISO_INTSTAT (* (reg8 *) SD_MISO__INTSTAT)\r
- #define SD_MISO_SNAP (* (reg8 *) SD_MISO__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(SD_MISO__SIO_CFG)\r
+ #define SD_MISO_SIO_HYST_EN (* (reg8 *) SD_MISO__SIO_HYST_EN)\r
+ #define SD_MISO_SIO_REG_HIFREQ (* (reg8 *) SD_MISO__SIO_REG_HIFREQ)\r
+ #define SD_MISO_SIO_CFG (* (reg8 *) SD_MISO__SIO_CFG)\r
+ #define SD_MISO_SIO_DIFF (* (reg8 *) SD_MISO__SIO_DIFF)\r
+#endif /* (SD_MISO__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(SD_MISO__INTSTAT)\r
+ #define SD_MISO_INTSTAT (* (reg8 *) SD_MISO__INTSTAT)\r
+ #define SD_MISO_SNAP (* (reg8 *) SD_MISO__SNAP)\r
+ \r
+ #define SD_MISO_0_INTTYPE_REG (* (reg8 *) SD_MISO__0__INTTYPE)\r
+#endif /* (SD_MISO__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: SD_MISO.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_MISO_0 (SD_MISO__0__PC)\r
+#define SD_MISO_0 (SD_MISO__0__PC)\r
+#define SD_MISO_0_INTR ((uint16)((uint16)0x0001u << SD_MISO__0__SHIFT))\r
+\r
+#define SD_MISO_INTR_ALL ((uint16)(SD_MISO_0_INTR))\r
\r
#endif /* End Pins SD_MISO_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SD_MOSI.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: SD_MOSI_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_MOSI_SUT.c usage_SD_MOSI_Write\r
*******************************************************************************/\r
-void SD_MOSI_Write(uint8 value) \r
+void SD_MOSI_Write(uint8 value)\r
{\r
uint8 staticBits = (SD_MOSI_DR & (uint8)(~SD_MOSI_MASK));\r
SD_MOSI_DR = staticBits | ((uint8)(value << SD_MOSI_SHIFT) & SD_MOSI_MASK);\r
\r
/*******************************************************************************\r
* Function Name: SD_MOSI_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* SD_MOSI_DM_STRONG Strong Drive \r
-* SD_MOSI_DM_OD_HI Open Drain, Drives High \r
-* SD_MOSI_DM_OD_LO Open Drain, Drives Low \r
-* SD_MOSI_DM_RES_UP Resistive Pull Up \r
-* SD_MOSI_DM_RES_DWN Resistive Pull Down \r
-* SD_MOSI_DM_RES_UPDWN Resistive Pull Up/Down \r
-* SD_MOSI_DM_DIG_HIZ High Impedance Digital \r
-* SD_MOSI_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_MOSI_SUT.c usage_SD_MOSI_SetDriveMode\r
*******************************************************************************/\r
-void SD_MOSI_SetDriveMode(uint8 mode) \r
+void SD_MOSI_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(SD_MOSI_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_MOSI_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro SD_MOSI_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet SD_MOSI_SUT.c usage_SD_MOSI_Read \r
*******************************************************************************/\r
-uint8 SD_MOSI_Read(void) \r
+uint8 SD_MOSI_Read(void)\r
{\r
return (SD_MOSI_PS & SD_MOSI_MASK) >> SD_MOSI_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_MOSI_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred SD_MOSI_Read() API because the \r
+* SD_MOSI_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet SD_MOSI_SUT.c usage_SD_MOSI_ReadDataReg \r
*******************************************************************************/\r
-uint8 SD_MOSI_ReadDataReg(void) \r
+uint8 SD_MOSI_ReadDataReg(void)\r
{\r
return (SD_MOSI_DR & SD_MOSI_MASK) >> SD_MOSI_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(SD_MOSI_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: SD_MOSI_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use SD_MOSI_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - SD_MOSI_0_INTR (First pin in the list)\r
+ * - SD_MOSI_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - SD_MOSI_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_MOSI_SUT.c usage_SD_MOSI_SetInterruptMode\r
+ *******************************************************************************/\r
+ void SD_MOSI_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & SD_MOSI_0_INTR) != 0u) \r
+ { \r
+ SD_MOSI_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: SD_MOSI_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_MOSI_SUT.c usage_SD_MOSI_ClearInterrupt\r
*******************************************************************************/\r
- uint8 SD_MOSI_ClearInterrupt(void) \r
+ uint8 SD_MOSI_ClearInterrupt(void)\r
{\r
return (SD_MOSI_INTSTAT & SD_MOSI_MASK) >> SD_MOSI_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: SD_MOSI.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "SD_MOSI_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
SD_MOSI__PORT == 15 && ((SD_MOSI__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void SD_MOSI_Write(uint8 value) ;\r
-void SD_MOSI_SetDriveMode(uint8 mode) ;\r
-uint8 SD_MOSI_ReadDataReg(void) ;\r
-uint8 SD_MOSI_Read(void) ;\r
-uint8 SD_MOSI_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void SD_MOSI_Write(uint8 value);\r
+void SD_MOSI_SetDriveMode(uint8 mode);\r
+uint8 SD_MOSI_ReadDataReg(void);\r
+uint8 SD_MOSI_Read(void);\r
+void SD_MOSI_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 SD_MOSI_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define SD_MOSI_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define SD_MOSI_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define SD_MOSI_DM_RES_UP PIN_DM_RES_UP\r
-#define SD_MOSI_DM_RES_DWN PIN_DM_RES_DWN\r
-#define SD_MOSI_DM_OD_LO PIN_DM_OD_LO\r
-#define SD_MOSI_DM_OD_HI PIN_DM_OD_HI\r
-#define SD_MOSI_DM_STRONG PIN_DM_STRONG\r
-#define SD_MOSI_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the SD_MOSI_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define SD_MOSI_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define SD_MOSI_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define SD_MOSI_DM_RES_UP PIN_DM_RES_UP\r
+ #define SD_MOSI_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define SD_MOSI_DM_OD_LO PIN_DM_OD_LO\r
+ #define SD_MOSI_DM_OD_HI PIN_DM_OD_HI\r
+ #define SD_MOSI_DM_STRONG PIN_DM_STRONG\r
+ #define SD_MOSI_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define SD_MOSI_MASK SD_MOSI__MASK\r
#define SD_MOSI_SHIFT SD_MOSI__SHIFT\r
#define SD_MOSI_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(SD_MOSI__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in SD_MOSI_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define SD_MOSI_INTR_NONE (uint16)(0x0000u)\r
+ #define SD_MOSI_INTR_RISING (uint16)(0x0001u)\r
+ #define SD_MOSI_INTR_FALLING (uint16)(0x0002u)\r
+ #define SD_MOSI_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define SD_MOSI_INTR_MASK (0x01u) \r
+#endif /* (SD_MOSI__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define SD_MOSI_PRTDSI__SYNC_OUT (* (reg8 *) SD_MOSI__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(SD_MOSI__INTSTAT) /* Interrupt Registers */\r
-\r
- #define SD_MOSI_INTSTAT (* (reg8 *) SD_MOSI__INTSTAT)\r
- #define SD_MOSI_SNAP (* (reg8 *) SD_MOSI__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(SD_MOSI__SIO_CFG)\r
+ #define SD_MOSI_SIO_HYST_EN (* (reg8 *) SD_MOSI__SIO_HYST_EN)\r
+ #define SD_MOSI_SIO_REG_HIFREQ (* (reg8 *) SD_MOSI__SIO_REG_HIFREQ)\r
+ #define SD_MOSI_SIO_CFG (* (reg8 *) SD_MOSI__SIO_CFG)\r
+ #define SD_MOSI_SIO_DIFF (* (reg8 *) SD_MOSI__SIO_DIFF)\r
+#endif /* (SD_MOSI__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(SD_MOSI__INTSTAT)\r
+ #define SD_MOSI_INTSTAT (* (reg8 *) SD_MOSI__INTSTAT)\r
+ #define SD_MOSI_SNAP (* (reg8 *) SD_MOSI__SNAP)\r
+ \r
+ #define SD_MOSI_0_INTTYPE_REG (* (reg8 *) SD_MOSI__0__INTTYPE)\r
+#endif /* (SD_MOSI__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: SD_MOSI.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_MOSI_0 (SD_MOSI__0__PC)\r
+#define SD_MOSI_0 (SD_MOSI__0__PC)\r
+#define SD_MOSI_0_INTR ((uint16)((uint16)0x0001u << SD_MOSI__0__SHIFT))\r
+\r
+#define SD_MOSI_INTR_ALL ((uint16)(SD_MOSI_0_INTR))\r
\r
#endif /* End Pins SD_MOSI_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: SD_SCK.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: SD_SCK_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_SCK_SUT.c usage_SD_SCK_Write\r
*******************************************************************************/\r
-void SD_SCK_Write(uint8 value) \r
+void SD_SCK_Write(uint8 value)\r
{\r
uint8 staticBits = (SD_SCK_DR & (uint8)(~SD_SCK_MASK));\r
SD_SCK_DR = staticBits | ((uint8)(value << SD_SCK_SHIFT) & SD_SCK_MASK);\r
\r
/*******************************************************************************\r
* Function Name: SD_SCK_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* SD_SCK_DM_STRONG Strong Drive \r
-* SD_SCK_DM_OD_HI Open Drain, Drives High \r
-* SD_SCK_DM_OD_LO Open Drain, Drives Low \r
-* SD_SCK_DM_RES_UP Resistive Pull Up \r
-* SD_SCK_DM_RES_DWN Resistive Pull Down \r
-* SD_SCK_DM_RES_UPDWN Resistive Pull Up/Down \r
-* SD_SCK_DM_DIG_HIZ High Impedance Digital \r
-* SD_SCK_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet SD_SCK_SUT.c usage_SD_SCK_SetDriveMode\r
*******************************************************************************/\r
-void SD_SCK_SetDriveMode(uint8 mode) \r
+void SD_SCK_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(SD_SCK_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_SCK_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro SD_SCK_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet SD_SCK_SUT.c usage_SD_SCK_Read \r
*******************************************************************************/\r
-uint8 SD_SCK_Read(void) \r
+uint8 SD_SCK_Read(void)\r
{\r
return (SD_SCK_PS & SD_SCK_MASK) >> SD_SCK_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: SD_SCK_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred SD_SCK_Read() API because the \r
+* SD_SCK_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet SD_SCK_SUT.c usage_SD_SCK_ReadDataReg \r
*******************************************************************************/\r
-uint8 SD_SCK_ReadDataReg(void) \r
+uint8 SD_SCK_ReadDataReg(void)\r
{\r
return (SD_SCK_DR & SD_SCK_MASK) >> SD_SCK_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(SD_SCK_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: SD_SCK_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use SD_SCK_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - SD_SCK_0_INTR (First pin in the list)\r
+ * - SD_SCK_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - SD_SCK_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_SCK_SUT.c usage_SD_SCK_SetInterruptMode\r
+ *******************************************************************************/\r
+ void SD_SCK_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & SD_SCK_0_INTR) != 0u) \r
+ { \r
+ SD_SCK_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: SD_SCK_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet SD_SCK_SUT.c usage_SD_SCK_ClearInterrupt\r
*******************************************************************************/\r
- uint8 SD_SCK_ClearInterrupt(void) \r
+ uint8 SD_SCK_ClearInterrupt(void)\r
{\r
return (SD_SCK_INTSTAT & SD_SCK_MASK) >> SD_SCK_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: SD_SCK.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "SD_SCK_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
SD_SCK__PORT == 15 && ((SD_SCK__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void SD_SCK_Write(uint8 value) ;\r
-void SD_SCK_SetDriveMode(uint8 mode) ;\r
-uint8 SD_SCK_ReadDataReg(void) ;\r
-uint8 SD_SCK_Read(void) ;\r
-uint8 SD_SCK_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void SD_SCK_Write(uint8 value);\r
+void SD_SCK_SetDriveMode(uint8 mode);\r
+uint8 SD_SCK_ReadDataReg(void);\r
+uint8 SD_SCK_Read(void);\r
+void SD_SCK_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 SD_SCK_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define SD_SCK_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define SD_SCK_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define SD_SCK_DM_RES_UP PIN_DM_RES_UP\r
-#define SD_SCK_DM_RES_DWN PIN_DM_RES_DWN\r
-#define SD_SCK_DM_OD_LO PIN_DM_OD_LO\r
-#define SD_SCK_DM_OD_HI PIN_DM_OD_HI\r
-#define SD_SCK_DM_STRONG PIN_DM_STRONG\r
-#define SD_SCK_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the SD_SCK_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define SD_SCK_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define SD_SCK_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define SD_SCK_DM_RES_UP PIN_DM_RES_UP\r
+ #define SD_SCK_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define SD_SCK_DM_OD_LO PIN_DM_OD_LO\r
+ #define SD_SCK_DM_OD_HI PIN_DM_OD_HI\r
+ #define SD_SCK_DM_STRONG PIN_DM_STRONG\r
+ #define SD_SCK_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define SD_SCK_MASK SD_SCK__MASK\r
#define SD_SCK_SHIFT SD_SCK__SHIFT\r
#define SD_SCK_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(SD_SCK__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in SD_SCK_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define SD_SCK_INTR_NONE (uint16)(0x0000u)\r
+ #define SD_SCK_INTR_RISING (uint16)(0x0001u)\r
+ #define SD_SCK_INTR_FALLING (uint16)(0x0002u)\r
+ #define SD_SCK_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define SD_SCK_INTR_MASK (0x01u) \r
+#endif /* (SD_SCK__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define SD_SCK_PRTDSI__SYNC_OUT (* (reg8 *) SD_SCK__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(SD_SCK__INTSTAT) /* Interrupt Registers */\r
-\r
- #define SD_SCK_INTSTAT (* (reg8 *) SD_SCK__INTSTAT)\r
- #define SD_SCK_SNAP (* (reg8 *) SD_SCK__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(SD_SCK__SIO_CFG)\r
+ #define SD_SCK_SIO_HYST_EN (* (reg8 *) SD_SCK__SIO_HYST_EN)\r
+ #define SD_SCK_SIO_REG_HIFREQ (* (reg8 *) SD_SCK__SIO_REG_HIFREQ)\r
+ #define SD_SCK_SIO_CFG (* (reg8 *) SD_SCK__SIO_CFG)\r
+ #define SD_SCK_SIO_DIFF (* (reg8 *) SD_SCK__SIO_DIFF)\r
+#endif /* (SD_SCK__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(SD_SCK__INTSTAT)\r
+ #define SD_SCK_INTSTAT (* (reg8 *) SD_SCK__INTSTAT)\r
+ #define SD_SCK_SNAP (* (reg8 *) SD_SCK__SNAP)\r
+ \r
+ #define SD_SCK_0_INTTYPE_REG (* (reg8 *) SD_SCK__0__INTTYPE)\r
+#endif /* (SD_SCK__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: SD_SCK.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_SCK_0 (SD_SCK__0__PC)\r
+#define SD_SCK_0 (SD_SCK__0__PC)\r
+#define SD_SCK_0_INTR ((uint16)((uint16)0x0001u << SD_SCK__0__SHIFT))\r
+\r
+#define SD_SCK_INTR_ALL ((uint16)(SD_SCK_0_INTR))\r
\r
#endif /* End Pins SD_SCK_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: USBFS.c\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS.c\r
+* \version 3.10\r
*\r
-* Description:\r
-* API for USBFS Component.\r
+* \brief\r
+* This file contains the global USBFS API functions.\r
*\r
* Note:\r
-* Many of the functions use endpoint number. RAM arrays are sized with 9\r
-* elements so they are indexed directly by epNumber. The SIE and ARB\r
+* Many of the functions use an endpoint number. SRAM arrays are sized with 9\r
+* elements, so they are indexed directly by epNumber. The SIE and ARB\r
* registers are indexed by variations of epNumber - 1.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include <CyDmac.h>\r
-#include "USBFS.h"\r
#include "USBFS_pvt.h"\r
+#include "USBFS_cydmac.h"\r
#include "USBFS_hid.h"\r
-#if(USBFS_DMA1_REMOVE == 0u)\r
- #include "USBFS_ep1_dma.h"\r
-#endif /* USBFS_DMA1_REMOVE */\r
-#if(USBFS_DMA2_REMOVE == 0u)\r
- #include "USBFS_ep2_dma.h"\r
-#endif /* USBFS_DMA2_REMOVE */\r
-#if(USBFS_DMA3_REMOVE == 0u)\r
- #include "USBFS_ep3_dma.h"\r
-#endif /* USBFS_DMA3_REMOVE */\r
-#if(USBFS_DMA4_REMOVE == 0u)\r
- #include "USBFS_ep4_dma.h"\r
-#endif /* USBFS_DMA4_REMOVE */\r
-#if(USBFS_DMA5_REMOVE == 0u)\r
- #include "USBFS_ep5_dma.h"\r
-#endif /* USBFS_DMA5_REMOVE */\r
-#if(USBFS_DMA6_REMOVE == 0u)\r
- #include "USBFS_ep6_dma.h"\r
-#endif /* USBFS_DMA6_REMOVE */\r
-#if(USBFS_DMA7_REMOVE == 0u)\r
- #include "USBFS_ep7_dma.h"\r
-#endif /* USBFS_DMA7_REMOVE */\r
-#if(USBFS_DMA8_REMOVE == 0u)\r
- #include "USBFS_ep8_dma.h"\r
-#endif /* USBFS_DMA8_REMOVE */\r
-#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- #include "USBFS_EP_DMA_Done_isr.h"\r
- #include "USBFS_EP8_DMA_Done_SR.h"\r
- #include "USBFS_EP17_DMA_Done_SR.h"\r
-#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+#include "USBFS_Dp.h"\r
\r
\r
/***************************************\r
* Global data allocation\r
***************************************/\r
\r
+/** Indicates whether the USBFS has been initialized. The variable is\r
+* initialized to 0 after device reset and set to 1 the first time USBFS_Start()\r
+* is called. This allows the Component to restart without reinitialization after\r
+* the first call to the USBFS_Start() routine.\r
+* If re-initialization of the Component is required, the variable should be set\r
+* to 0 before the USBFS_Start() routine is called. Alternatively, the USBFS can\r
+* be reinitialized by calling both USBFS_Init() and USBFS_InitComponent()\r
+* functions.\r
+*/\r
uint8 USBFS_initVar = 0u;\r
-#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- uint8 USBFS_DmaChan[USBFS_MAX_EP];\r
- uint8 USBFS_DmaTd[USBFS_MAX_EP];\r
-#endif /* USBFS_EP_MM */\r
-#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT;\r
- uint8 USBFS_DmaNextTd[USBFS_MAX_EP];\r
- const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] =\r
- { 0u,\r
- USBFS_ep1_TD_TERMOUT_EN,\r
- USBFS_ep2_TD_TERMOUT_EN,\r
- USBFS_ep3_TD_TERMOUT_EN,\r
- USBFS_ep4_TD_TERMOUT_EN,\r
- USBFS_ep5_TD_TERMOUT_EN,\r
- USBFS_ep6_TD_TERMOUT_EN,\r
- USBFS_ep7_TD_TERMOUT_EN,\r
- USBFS_ep8_TD_TERMOUT_EN\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+ #if (CY_PSOC4)\r
+ static void USBFS_InitEpDma(void);\r
+\r
+ /* DMA chanels assigend for endpoints. */\r
+ const uint8 USBFS_DmaChan[USBFS_MAX_EP] =\r
+ {\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ }; \r
+ #else\r
+ /* DMA chanels assigend for endpoints. */\r
+ uint8 USBFS_DmaChan[USBFS_MAX_EP];\r
+ \r
+ /* DMA TDs require for PSoC 3/5LP operation. */\r
+ uint8 USBFS_DmaTd[USBFS_MAX_EP];\r
+ #endif /* (CY_PSOC4) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+#if (CY_PSOC4)\r
+ /* Number of DMA bursts. */\r
+ uint8 USBFS_DmaEpBurstCnt [USBFS_MAX_EP];\r
+ \r
+ /* Number of bytes to transfer in last DMA burst. */\r
+ uint8 USBFS_DmaEpLastBurstEl[USBFS_MAX_EP];\r
+\r
+ /* Storage for arrays above. */\r
+ uint8 USBFS_DmaEpBurstCntBackup [USBFS_MAX_EP];\r
+ uint32 USBFS_DmaEpBufferAddrBackup[USBFS_MAX_EP];\r
+ \r
+ /* DMA trigger mux output for usb.dma_req[0-7]. */\r
+ const uint8 USBFS_DmaReqOut[USBFS_MAX_EP] =\r
+ {\r
+ 0u,\r
+ USBFS_ep1_dma__TR_OUTPUT,\r
+ USBFS_ep2_dma__TR_OUTPUT,\r
+ USBFS_ep3_dma__TR_OUTPUT,\r
+ USBFS_ep4_dma__TR_OUTPUT,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ };\r
+\r
+ /* DMA trigger mux output for usb.dma_burstend[0-7]. */\r
+ const uint8 USBFS_DmaBurstEndOut[USBFS_MAX_EP] =\r
+ {\r
+ 0u,\r
+ USBFS_BURSTEND_0_TR_OUTPUT,\r
+ USBFS_BURSTEND_1_TR_OUTPUT,\r
+ USBFS_BURSTEND_2_TR_OUTPUT,\r
+ USBFS_BURSTEND_3_TR_OUTPUT,\r
+ USBFS_BURSTEND_4_TR_OUTPUT,\r
+ USBFS_BURSTEND_5_TR_OUTPUT,\r
+ USBFS_BURSTEND_6_TR_OUTPUT,\r
+ USBFS_BURSTEND_7_TR_OUTPUT\r
};\r
- volatile uint16 USBFS_inLength[USBFS_MAX_EP];\r
- const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];\r
- volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];\r
-#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+ \r
+#else\r
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT;\r
+ uint8 USBFS_DmaNextTd[USBFS_MAX_EP];\r
+ const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] =\r
+ {\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ 0u,\r
+ };\r
+\r
+ volatile uint16 USBFS_inLength[USBFS_MAX_EP];\r
+ const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];\r
+ volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];\r
+ #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+#endif /* (CY_PSOC4) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Start\r
-********************************************************************************\r
+****************************************************************************//**\r
+*\r
+* This function performs all required initialization for the USBFS component.\r
+* After this function call, the USB device initiates communication with the\r
+* host by pull-up D+ line. This is the preferred method to begin component\r
+* operation.\r
+*\r
+* Note that global interrupts have to be enabled because interrupts are\r
+* required for USBFS component operation.\r
*\r
-* Summary:\r
-* This function initialize the USB SIE, arbiter and the\r
-* endpoint APIs, including setting the D+ Pullup\r
+* PSoC 4200L devices: when USBFS component configured to DMA with Automatic\r
+* Buffer Management, the DMA interrupt priority is changed to the highest\r
+* (priority 0) inside this function.\r
*\r
-* Parameters:\r
-* device: Contains the device number of the desired device descriptor.\r
+* PSoC 3/PSoC 5LP devices: when USBFS component configured to DMA with\r
+* Automatic Buffer Management, the Arbiter interrupt priority is changed to\r
+* the highest (priority 0) inside this function.\r
+*\r
+* \param device\r
+* Contains the device number of the desired device descriptor.\r
* The device number can be found in the Device Descriptor Tab of\r
* "Configure" dialog, under the settings of desired Device Descriptor,\r
* in the "Device Number" field.\r
-* mode: The operating voltage. This determines whether the voltage regulator\r
-* is enabled for 5V operation or if pass through mode is used for 3.3V\r
-* operation. Symbolic names and their associated values are given in the\r
-* following table.\r
-* USBFS_3V_OPERATION - Disable voltage regulator and pass-thru\r
-* Vcc for pull-up\r
-* USBFS_5V_OPERATION - Enable voltage regulator and use\r
-* regulator for pull-up\r
-* USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage\r
-* regulator depend on Vddd Voltage configuration in DWR.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* The USBFS_intiVar variable is used to indicate initial\r
-* configuration of this component. The variable is initialized to zero (0u)\r
-* and set to one (1u) the first time USBFS_Start() is called.\r
-* This allows for component Re-Start without unnecessary re-initialization\r
-* in all subsequent calls to the USBFS_Start() routine.\r
-* If re-initialization of the component is required the variable should be set\r
-* to zero before call of UART_Start() routine, or the user may call\r
-* USBFS_Init() and USBFS_InitComponent() as done\r
-* in the USBFS_Start() routine.\r
-*\r
-* Side Effects:\r
+* \param mode:\r
+* The operating voltage. This determines whether the voltage regulator\r
+* is enabled for 5V operation or if pass through mode is used for 3.3V\r
+* operation. Symbolic names and their associated values are given in the\r
+* following list.\r
+*\r
+* *USBFS_3V_OPERATION* - Disable voltage regulator and pass-\r
+* through Vcc for pull-up\r
+*\r
+* *USBFS_5V_OPERATION* - Enable voltage regulator and use\r
+* regulator for pull-up\r
+*\r
+* *USBFS_DWR_POWER_OPERATION* - Enable or disable the voltage\r
+* regulator depending on the power supply\r
+* voltage configuration in the DWR tab.\r
+* For PSoC 3/5LP devices, the VDDD supply\r
+* voltage is considered and for PSoC 4A-L,\r
+* the VBUS supply voltage is considered.*\r
+* \globalvars\r
+* \ref USBFS_initVar\r
+*\r
+* \sideeffect\r
* This function will reset all communication states to default.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_Start(uint8 device, uint8 mode) \r
{\r
- /* If not Initialized then initialize all required hardware and software */\r
- if(USBFS_initVar == 0u)\r
+ if (0u == USBFS_initVar)\r
{\r
USBFS_Init();\r
USBFS_initVar = 1u;\r
}\r
+\r
USBFS_InitComponent(device, mode);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Init\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Initialize component's hardware. Usually called in USBFS_Start().\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None.\r
+* This function initializes or restores the component according to the\r
+* customizer Configure dialog settings. It is not necessary to call\r
+* USBFS_Init() because the USBFS_Start() routine calls\r
+* this function and is the preferred method to begin component operation.\r
*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_Init(void) \r
{\r
- uint8 enableInterrupts;\r
- #if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- uint16 i;\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
+#if (CY_PSOC4)\r
+ /* Enable clock to USB IP. */\r
+ USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_CSR_CLK_EN;\r
\r
- enableInterrupts = CyEnterCriticalSection();\r
+ /* The internal regulator (CR1.REG_ENABLE) is enabled in\r
+ * USBFS_InitComponent() if it is required.\r
+ */\r
+\r
+ /* Enable USBIO control on drive mode of D+ and D- pins. */\r
+ USBFS_USBIO_CR1_REG &= ~ (uint32) USBFS_USBIO_CR1_IOMODE;\r
+\r
+ /* Set number of LF CLK to detect UBS bus reset. */\r
+ USBFS_BUS_RST_CNT_REG = USBFS_DEFUALT_BUS_RST_CNT;\r
+\r
+ /* Select VBUS detection source and clear PHY isolate. The application level\r
+ * must ensure that VBUS is valid. There is no need to wait 2us before VBUS is valid.\r
+ */\r
+ USBFS_POWER_CTRL_REG = USBFS_DEFAULT_POWER_CTRL_VBUS;\r
\r
- /* Enable USB block */\r
+ /* Enable PHY detector and single-ended and differential receivers. */\r
+ USBFS_POWER_CTRL_REG |= USBFS_DEFAULT_POWER_CTRL_PHY;\r
+\r
+ /* Suspend clear sequence. */\r
+ USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND;\r
+ CyDelayUs(USBFS_WAIT_SUSPEND_DEL_DISABLE);\r
+ USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND_DEL;\r
+\r
+ /* Sets IMO lock options and clear all other bits. */\r
+ USBFS_CR1_REG = USBFS_DEFUALT_CR1;\r
+\r
+ /* Configure level (hi, lo, med) for each interrupt source. */\r
+ USBFS_INTR_LVL_SEL_REG = USBFS_DEFAULT_INTR_LVL_SEL;\r
+\r
+ /* Configure interrupt sources from: SOF, Bus Reset and EP0. */\r
+ USBFS_INTR_SIE_MASK_REG = USBFS_DEFAULT_INTR_SIE_MASK;\r
+\r
+#else\r
+ uint8 enableInterrupts = CyEnterCriticalSection();\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+ uint16 i;\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+ /* Enable USB block. */\r
USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB;\r
- /* Enable USB block for Standby Power Mode */\r
+ /* Enable USB block for Standby Power Mode. */\r
USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB;\r
\r
- /* Enable core clock */\r
+ /* Enable core clock. */\r
USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_ENABLE;\r
\r
USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;\r
\r
- /* ENABLING USBIO PADS IN USB MODE FROM I/O MODE */\r
- /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */\r
- USBFS_USBIO_CR0_REG &= ((uint8)(~USBFS_USBIO_CR0_TEN));\r
- CyDelayUs(0u); /*~50ns delay */\r
- /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted)\r
- * high. This will have been set low by the power manger out of reset.\r
- * Also confirm USBIO pull-up disabled\r
+ /* ENABLING USBIO PADS IN USB MODE FROM I/O MODE. */\r
+ /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled. */\r
+ USBFS_USBIO_CR0_REG &= (uint8) ~USBFS_USBIO_CR0_TEN;\r
+ CyDelayUs(USBFS_WAIT_REG_STABILITY_50NS); /* ~50ns delay. */\r
+ /* Disable USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted.\r
+ * high. These bits will be set low by the power manager out-of-reset.\r
+ * Also confirm USBIO pull-up is disabled.\r
*/\r
- USBFS_PM_USB_CR0_REG &= ((uint8)(~(USBFS_PM_USB_CR0_PD_N |\r
- USBFS_PM_USB_CR0_PD_PULLUP_N)));\r
+ USBFS_PM_USB_CR0_REG &= (uint8) ~(USBFS_PM_USB_CR0_PD_N |\r
+ USBFS_PM_USB_CR0_PD_PULLUP_N);\r
\r
- /* Select iomode to USB mode*/\r
- USBFS_USBIO_CR1_REG &= ((uint8)(~USBFS_USBIO_CR1_IOMODE));\r
+ /* Select IOMODE to USB mode. */\r
+ USBFS_USBIO_CR1_REG &= (uint8) ~USBFS_USBIO_CR1_IOMODE;\r
\r
- /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/\r
+ /* Enable USBIO reference by setting PM.USB_CR0.fsusbio_ref_en. */\r
USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN;\r
- /* The reference will be available 1 us after the regulator is enabled */\r
- CyDelayUs(1u);\r
- /* OR 40us after power restored */\r
- CyDelayUs(40u);\r
- /* Ensure the single ended disable bits are low (PRT15.INP_DIS[7:6])(input receiver enabled). */\r
- USBFS_DM_INP_DIS_REG &= ((uint8)(~USBFS_DM_MASK));\r
- USBFS_DP_INP_DIS_REG &= ((uint8)(~USBFS_DP_MASK));\r
-\r
- /* Enable USBIO */\r
+ /* Reference is available for 1us after regulator is enabled. */\r
+ CyDelayUs(USBFS_WAIT_REG_STABILITY_1US);\r
+ /* OR 40us after power is restored. */\r
+ CyDelayUs(USBFS_WAIT_VREF_RESTORE);\r
+ /* Ensure single-ended disable bits are low (PRT15.INP_DIS[7:6])(input receiver enabled). */\r
+ USBFS_DM_INP_DIS_REG &= (uint8) ~USBFS_DM_MASK;\r
+ USBFS_DP_INP_DIS_REG &= (uint8) ~USBFS_DP_MASK;\r
+\r
+ /* Enable USBIO. */\r
USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N;\r
- CyDelayUs(2u);\r
- /* Set the USBIO pull-up enable */\r
+ CyDelayUs(USBFS_WAIT_PD_PULLUP_N_ENABLE);\r
+ /* Set USBIO pull-up enable. */\r
USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N;\r
\r
- /* Write WAx */\r
+ /* Reset Arbiter Write Address register for endpoint 1. */\r
CY_SET_REG8(USBFS_ARB_RW1_WA_PTR, 0u);\r
CY_SET_REG8(USBFS_ARB_RW1_WA_MSB_PTR, 0u);\r
\r
- #if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- /* Init transfer descriptor. This will be used to detect the DMA state - initialized or not. */\r
- for (i = 0u; i < USBFS_MAX_EP; i++)\r
- {\r
- USBFS_DmaTd[i] = DMA_INVALID_TD;\r
- #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- USBFS_DmaNextTd[i] = DMA_INVALID_TD;\r
- #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
- }\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+ /* Initialize transfer descriptor. This will be used to detect DMA state - initialized or not. */\r
+ for (i = 0u; i < USBFS_MAX_EP; ++i)\r
+ {\r
+ USBFS_DmaTd[i] = DMA_INVALID_TD;\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ USBFS_DmaNextTd[i] = DMA_INVALID_TD;\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+ }\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
\r
CyExitCriticalSection(enableInterrupts);\r
+#endif /* (CY_PSOC4) */\r
\r
+ /* Configure interrupts from USB block. */\r
+#if (CY_PSOC4)\r
+ /* Configure hi_int: set handler and priority. */\r
+ CyIntSetPriority (USBFS_INTR_HI_VECT_NUM, USBFS_INTR_HI_PRIORITY);\r
+ (void) CyIntSetVector(USBFS_INTR_HI_VECT_NUM, &USBFS_INTR_HI_ISR);\r
\r
- /* Set the bus reset Interrupt. */\r
- (void) CyIntSetVector(USBFS_BUS_RESET_VECT_NUM, &USBFS_BUS_RESET_ISR);\r
- CyIntSetPriority(USBFS_BUS_RESET_VECT_NUM, USBFS_BUS_RESET_PRIOR);\r
+ /* Configure lo_int: set handler and priority. */\r
+ CyIntSetPriority (USBFS_INTR_LO_VECT_NUM, USBFS_INTR_LO_PRIORITY);\r
+ (void) CyIntSetVector(USBFS_INTR_LO_VECT_NUM, &USBFS_INTR_LO_ISR);\r
\r
- /* Set the SOF Interrupt. */\r
- #if(USBFS_SOF_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_SOF_VECT_NUM, &USBFS_SOF_ISR);\r
- CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR);\r
- #endif /* USBFS_SOF_ISR_REMOVE */\r
+ /* Configure med_int: set handler and priority (routed through DSI). */\r
+ CyIntSetPriority (USBFS_INTR_MED_VECT_NUM, USBFS_INTR_MED_PRIORITY);\r
+ (void) CyIntSetVector(USBFS_INTR_MED_VECT_NUM, &USBFS_INTR_MED_ISR);\r
\r
- /* Set the Control Endpoint Interrupt. */\r
- (void) CyIntSetVector(USBFS_EP_0_VECT_NUM, &USBFS_EP_0_ISR);\r
- CyIntSetPriority(USBFS_EP_0_VECT_NUM, USBFS_EP_0_PRIOR);\r
+#else\r
+ /* Set bus reset interrupt. */\r
+ CyIntSetPriority(USBFS_BUS_RESET_VECT_NUM, USBFS_BUS_RESET_PRIOR);\r
+ (void) CyIntSetVector(USBFS_BUS_RESET_VECT_NUM, &USBFS_BUS_RESET_ISR);\r
\r
- /* Set the Data Endpoint 1 Interrupt. */\r
- #if(USBFS_EP1_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_EP_1_VECT_NUM, &USBFS_EP_1_ISR);\r
- CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR);\r
- #endif /* USBFS_EP1_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 2 Interrupt. */\r
- #if(USBFS_EP2_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_EP_2_VECT_NUM, &USBFS_EP_2_ISR);\r
- CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR);\r
- #endif /* USBFS_EP2_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 3 Interrupt. */\r
- #if(USBFS_EP3_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_EP_3_VECT_NUM, &USBFS_EP_3_ISR);\r
- CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR);\r
- #endif /* USBFS_EP3_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 4 Interrupt. */\r
- #if(USBFS_EP4_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_EP_4_VECT_NUM, &USBFS_EP_4_ISR);\r
- CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR);\r
- #endif /* USBFS_EP4_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 5 Interrupt. */\r
- #if(USBFS_EP5_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_EP_5_VECT_NUM, &USBFS_EP_5_ISR);\r
- CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR);\r
- #endif /* USBFS_EP5_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 6 Interrupt. */\r
- #if(USBFS_EP6_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_EP_6_VECT_NUM, &USBFS_EP_6_ISR);\r
- CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR);\r
- #endif /* USBFS_EP6_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 7 Interrupt. */\r
- #if(USBFS_EP7_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_EP_7_VECT_NUM, &USBFS_EP_7_ISR);\r
- CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR);\r
- #endif /* USBFS_EP7_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 8 Interrupt. */\r
- #if(USBFS_EP8_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR);\r
- CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR);\r
- #endif /* USBFS_EP8_ISR_REMOVE */\r
-\r
- #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))\r
- /* Set the ARB Interrupt. */\r
- (void) CyIntSetVector(USBFS_ARB_VECT_NUM, &USBFS_ARB_ISR);\r
- CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR);\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ /* Set Control Endpoint Interrupt. */\r
+ CyIntSetPriority(USBFS_EP_0_VECT_NUM, USBFS_EP_0_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_0_VECT_NUM, &USBFS_EP_0_ISR);\r
\r
+ /* Set SOF interrupt. */\r
+ #if (USBFS_SOF_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR);\r
+ (void) CyIntSetVector(USBFS_SOF_VECT_NUM, &USBFS_SOF_ISR);\r
+ #endif /* (USBFS_SOF_ISR_ACTIVE) */\r
+\r
+ /* Set Data Endpoint 1 Interrupt. */\r
+ #if (USBFS_EP1_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_1_VECT_NUM, &USBFS_EP_1_ISR);\r
+ #endif /* (USBFS_EP1_ISR_ACTIVE) */\r
+\r
+ /* Set Data Endpoint 2 Interrupt. */\r
+ #if (USBFS_EP2_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_2_VECT_NUM, &USBFS_EP_2_ISR);\r
+ #endif /* (USBFS_EP2_ISR_ACTIVE) */\r
+\r
+ /* Set Data Endpoint 3 Interrupt. */\r
+ #if (USBFS_EP3_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_3_VECT_NUM, &USBFS_EP_3_ISR);\r
+ #endif /* (USBFS_EP3_ISR_ACTIVE) */\r
+\r
+ /* Set Data Endpoint 4 Interrupt. */\r
+ #if (USBFS_EP4_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_4_VECT_NUM, &USBFS_EP_4_ISR);\r
+ #endif /* (USBFS_EP4_ISR_ACTIVE) */\r
+\r
+ /* Set Data Endpoint 5 Interrupt. */\r
+ #if (USBFS_EP5_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_5_VECT_NUM, &USBFS_EP_5_ISR);\r
+ #endif /* (USBFS_EP5_ISR_ACTIVE) */\r
+\r
+ /* Set Data Endpoint 6 Interrupt. */\r
+ #if (USBFS_EP6_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_6_VECT_NUM, &USBFS_EP_6_ISR);\r
+ #endif /* (USBFS_EP6_ISR_ACTIVE) */\r
+\r
+ /* Set Data Endpoint 7 Interrupt. */\r
+ #if (USBFS_EP7_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_7_VECT_NUM, &USBFS_EP_7_ISR);\r
+ #endif /* (USBFS_EP7_ISR_ACTIVE) */\r
+\r
+ /* Set Data Endpoint 8 Interrupt. */\r
+ #if (USBFS_EP8_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR);\r
+ (void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR);\r
+ #endif /* (USBFS_EP8_ISR_ACTIVE) */\r
+\r
+ /* Set ARB Interrupt. */\r
+ #if (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR);\r
+ (void) CyIntSetVector(USBFS_ARB_VECT_NUM, &USBFS_ARB_ISR);\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) */\r
+#endif /* (CY_PSOC4) */\r
+\r
+ /* Common: Configure GPIO interrupt for wakeup. */\r
+#if (USBFS_DP_ISR_ACTIVE)\r
+ CyIntSetPriority (USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIORITY);\r
+ (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR);\r
+#endif /* (USBFS_DP_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA && CY_PSOC4)\r
+ /* Initialize DMA channels. */\r
+ USBFS_InitEpDma();\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA && CY_PSOC4) */\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_InitComponent\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Initialize the component, except for the HW which is done one time in\r
-* the Start function. This function pulls up D+.\r
-*\r
-* Parameters:\r
-* device: Contains the device number of the desired device descriptor.\r
-* The device number can be found in the Device Descriptor Tab of\r
-* "Configure" dialog, under the settings of desired Device Descriptor,\r
-* in the "Device Number" field.\r
-* mode: The operating voltage. This determines whether the voltage regulator\r
-* is enabled for 5V operation or if pass through mode is used for 3.3V\r
-* operation. Symbolic names and their associated values are given in the\r
-* following table.\r
-* USBFS_3V_OPERATION - Disable voltage regulator and pass-thru\r
-* Vcc for pull-up\r
-* USBFS_5V_OPERATION - Enable voltage regulator and use\r
-* regulator for pull-up\r
-* USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage\r
-* regulator depend on Vddd Voltage configuration in DWR.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_device: Contains the device number of the desired device\r
-* descriptor. The device number can be found in the Device Descriptor Tab\r
-* of "Configure" dialog, under the settings of desired Device Descriptor,\r
-* in the "Device Number" field.\r
-* USBFS_transferState: This variable used by the communication\r
-* functions to handle current transfer state. Initialized to\r
-* TRANS_STATE_IDLE in this API.\r
-* USBFS_configuration: Contains current configuration number\r
-* which is set by the Host using SET_CONFIGURATION request.\r
-* Initialized to zero in this API.\r
-* USBFS_deviceAddress: Contains current device address. This\r
-* variable is initialized to zero in this API. Host starts to communicate\r
-* to device with address 0 and then set it to whatever value using\r
+****************************************************************************//**\r
+*\r
+* This function initializes the component’s global variables and initiates\r
+* communication with the host by pull-up D+ line.\r
+*\r
+* \param device:\r
+* Contains the device number of the desired device descriptor. The device\r
+* number can be found in the Device Descriptor Tab of "Configure" dialog,\r
+* under the settings of desired Device Descriptor, in the *Device Number*\r
+* field.\r
+* \param mode:\r
+* The operating voltage. This determines whether the voltage regulator\r
+* is enabled for 5V operation or if pass through mode is used for 3.3V\r
+* operation. Symbolic names and their associated values are given in the\r
+* following list.\r
+*\r
+* *USBFS_3V_OPERATION* - Disable voltage regulator and pass-\r
+* through Vcc for pull-up\r
+*\r
+* *USBFS_5V_OPERATION* - Enable voltage regulator and use\r
+* regulator for pull-up\r
+*\r
+* *USBFS_DWR_POWER_OPERATION* - Enable or disable the voltage\r
+* regulator depending on the power supply\r
+* voltage configuration in the DWR tab.\r
+* For PSoC 3/5LP devices, the VDDD supply\r
+* voltage is considered and for PSoC 4A-L,\r
+* the VBUS supply voltage is considered.\r
+*\r
+* \globalvars\r
+* \ref USBFS_device\r
+* \ref USBFS_transferState\r
+* \ref USBFS_configuration\r
+* \ref USBFS_deviceStatus\r
+*\r
+* \ref USBFS_deviceAddress - Contains the current device address. This\r
+* variable is initialized to zero in this API. The Host starts to communicate\r
+* to the device with address 0 and then sets it to a whatever value using a\r
* SET_ADDRESS request.\r
-* USBFS_deviceStatus: initialized to 0.\r
-* This is two bit variable which contain power status in first bit\r
-* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote\r
-* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit.\r
-* USBFS_lastPacketSize initialized to 0;\r
*\r
-* Reentrant:\r
+* \ref USBFS_lastPacketSize - Initialized to 0;\r
+*\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
* HID 7.2.6 Set_Protocol Request:\r
* "When initialized, all devices default to report protocol."\r
*/\r
- #if defined(USBFS_ENABLE_HID_CLASS)\r
- uint8 i;\r
+#if defined(USBFS_ENABLE_HID_CLASS)\r
+ uint8 i;\r
\r
- for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++)\r
- {\r
- USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT;\r
- }\r
- #endif /* USBFS_ENABLE_HID_CLASS */\r
+ for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++)\r
+ {\r
+ USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT;\r
+ }\r
+#endif /* USBFS_ENABLE_HID_CLASS */\r
+\r
+ /* Store device number to access descriptor. */\r
+ USBFS_device = device;\r
\r
- /* Enable Interrupts. */\r
+ /* Reset component internal variables. */\r
+ USBFS_transferState = USBFS_TRANS_STATE_IDLE;\r
+ USBFS_configurationChanged = 0u;\r
+ USBFS_configuration = 0u;\r
+ USBFS_interfaceNumber = 0u;\r
+ USBFS_deviceAddress = 0u;\r
+ USBFS_deviceStatus = 0u;\r
+ USBFS_lastPacketSize = 0u;\r
+\r
+ /* Enable component interrupts. */\r
+#if (CY_PSOC4)\r
+ CyIntEnable(USBFS_INTR_HI_VECT_NUM);\r
+ CyIntEnable(USBFS_INTR_MED_VECT_NUM);\r
+ CyIntEnable(USBFS_INTR_LO_VECT_NUM);\r
+#else\r
CyIntEnable(USBFS_BUS_RESET_VECT_NUM);\r
CyIntEnable(USBFS_EP_0_VECT_NUM);\r
- #if(USBFS_EP1_ISR_REMOVE == 0u)\r
+\r
+ #if (USBFS_SOF_ISR_ACTIVE)\r
+ CyIntEnable(USBFS_SOF_VECT_NUM);\r
+ #endif /* (USBFS_SOF_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP1_ISR_ACTIVE)\r
CyIntEnable(USBFS_EP_1_VECT_NUM);\r
- #endif /* USBFS_EP1_ISR_REMOVE */\r
- #if(USBFS_EP2_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP1_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP2_ISR_ACTIVE)\r
CyIntEnable(USBFS_EP_2_VECT_NUM);\r
- #endif /* USBFS_EP2_ISR_REMOVE */\r
- #if(USBFS_EP3_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP5_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP3_ISR_ACTIVE)\r
CyIntEnable(USBFS_EP_3_VECT_NUM);\r
- #endif /* USBFS_EP3_ISR_REMOVE */\r
- #if(USBFS_EP4_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP5_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP4_ISR_ACTIVE)\r
CyIntEnable(USBFS_EP_4_VECT_NUM);\r
- #endif /* USBFS_EP4_ISR_REMOVE */\r
- #if(USBFS_EP5_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP5_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP5_ISR_ACTIVE)\r
CyIntEnable(USBFS_EP_5_VECT_NUM);\r
- #endif /* USBFS_EP5_ISR_REMOVE */\r
- #if(USBFS_EP6_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP5_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP6_ISR_ACTIVE)\r
CyIntEnable(USBFS_EP_6_VECT_NUM);\r
- #endif /* USBFS_EP6_ISR_REMOVE */\r
- #if(USBFS_EP7_ISR_REMOVE == 0u)\r
+ #endif /* USBFS_EP6_ISR_REMOVE */\r
+\r
+ #if (USBFS_EP7_ISR_ACTIVE)\r
CyIntEnable(USBFS_EP_7_VECT_NUM);\r
- #endif /* USBFS_EP7_ISR_REMOVE */\r
- #if(USBFS_EP8_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP7_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP8_ISR_ACTIVE)\r
CyIntEnable(USBFS_EP_8_VECT_NUM);\r
- #endif /* USBFS_EP8_ISR_REMOVE */\r
- #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))\r
- /* usb arb interrupt enable */\r
- USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;\r
+ #endif /* (USBFS_EP8_ISR_ACTIVE) */\r
+#endif /* (CY_PSOC4) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE)\r
+ /* Enable ARB EP interrupt sources. */\r
+ USBFS_ARB_INT_EN_REG = USBFS_DEFAULT_ARB_INT_EN;\r
+\r
+ #if (CY_PSOC3 || CY_PSOC5)\r
CyIntEnable(USBFS_ARB_VECT_NUM);\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
-\r
- /* Arbiter configuration for DMA transfers */\r
- #if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
- USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- /*Set cfg cmplt this rises DMA request when the full configuration is done */\r
- USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;\r
- #if(USBFS_EP_DMA_AUTO_OPT == 0u)\r
- /* Init interrupt which handles verification of the successful DMA transaction */\r
+ #endif /* (CY_PSOC3 || CY_PSOC5) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) */\r
+\r
+/* Arbiter configuration for DMA transfers. */\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+ /* Configure Arbiter for Manual or Auto DMA operation and clear configuration completion. */\r
+ USBFS_ARB_CFG_REG = USBFS_DEFAULT_ARB_CFG;\r
+\r
+ #if (CY_PSOC4)\r
+ /* Enable DMA operation. */\r
+ CyDmaEnable();\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Change DMA priority to be highest. */\r
+ CyIntSetPriority(CYDMA_INTR_NUMBER, USBFS_DMA_AUTO_INTR_PRIO);\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ #endif /* (CY_PSOC4) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ #if (CY_PSOC4)\r
+ /* Enable DMA interrupt to handle DMA management. */\r
+ CyIntEnable(CYDMA_INTR_NUMBER);\r
+ #else\r
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ /* Initialize interrupts which handle verification of successful DMA transaction. */\r
USBFS_EP_DMA_Done_isr_StartEx(&USBFS_EP_DMA_DONE_ISR);\r
USBFS_EP17_DMA_Done_SR_InterruptEnable();\r
USBFS_EP8_DMA_Done_SR_InterruptEnable();\r
- #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
-\r
- USBFS_transferState = USBFS_TRANS_STATE_IDLE;\r
+ #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+ #endif /* (CY_PSOC4) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
\r
- /* USB Locking: Enabled, VRegulator: depend on mode or DWR Voltage configuration*/\r
+ /* Enable USB regulator depends on operation voltage. IMO Locking is enabled in Init(). */\r
switch(mode)\r
{\r
- case USBFS_3V_OPERATION:\r
- USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;\r
- break;\r
- case USBFS_5V_OPERATION:\r
- USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE;\r
- break;\r
- default: /*USBFS_DWR_VDDD_OPERATION */\r
- #if(USBFS_VDDD_MV < USBFS_3500MV)\r
- USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;\r
- #else\r
- USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE;\r
- #endif /* USBFS_VDDD_MV < USBFS_3500MV */\r
- break;\r
+ case USBFS_3V_OPERATION:\r
+ /* Disable regulator for 3V operation. */\r
+ USBFS_CR1_REG &= (uint8) ~USBFS_CR1_REG_ENABLE;\r
+ break;\r
+\r
+ case USBFS_5V_OPERATION:\r
+ /* Enable regulator for 5V operation. */\r
+ USBFS_CR1_REG |= (uint8) USBFS_CR1_REG_ENABLE;\r
+ break;\r
+\r
+ default: /* Check DWR settings of USB power supply. */\r
+ #if (USBFS_VDDD_MV < USBFS_3500MV)\r
+ /* Disable regulator for 3V operation. */\r
+ USBFS_CR1_REG &= (uint8) ~USBFS_CR1_REG_ENABLE;\r
+ #else\r
+ /* Enable regulator for 5V operation. */\r
+ USBFS_CR1_REG |= (uint8) USBFS_CR1_REG_ENABLE;\r
+ #endif /* (USBFS_VDDD_MV < USBFS_3500MV) */\r
+ break;\r
}\r
\r
- /* Record the descriptor selection */\r
- USBFS_device = device;\r
+#if (CY_PSOC4)\r
+ /* Clear bus activity. */\r
+ USBFS_CR1_REG &= (uint32) ~USBFS_CR1_BUS_ACTIVITY;\r
\r
- /* Clear all of the component data */\r
- USBFS_configuration = 0u;\r
- USBFS_interfaceNumber = 0u;\r
- USBFS_configurationChanged = 0u;\r
- USBFS_deviceAddress = 0u;\r
- USBFS_deviceStatus = 0u;\r
+ /* Clear EP0 count register. */\r
+ USBFS_EP0_CNT_REG = USBFS_CLEAR_REG;\r
+\r
+ /* Set EP0.CR: ACK Setup, NAK IN/OUT. */\r
+ USBFS_EP0_CR_REG = USBFS_MODE_NAK_IN_OUT;\r
\r
- USBFS_lastPacketSize = 0u;\r
+ #if (USBFS_LPM_ACTIVE)\r
+ if (NULL != USBFS_GetBOSPtr())\r
+ {\r
+ /* Enable LPM and acknowledge LPM packets for active device.\r
+ * Reset NYET_EN and SUB_RESP bits in the LPM_CTRL register.\r
+ */\r
+ USBFS_LPM_CTRL_REG = (USBFS_LPM_CTRL_LPM_EN | \\r
+ USBFS_LPM_CTRL_LPM_ACK_RESP);\r
+ }\r
+ else\r
+ {\r
+ /* Disable LPM for active device. */\r
+ USBFS_LPM_CTRL_REG &= (uint32) ~USBFS_LPM_CTRL_LPM_EN;\r
+ }\r
+ #endif /* (USBFS_LPM_ACTIVE) */\r
\r
- /* ACK Setup, Stall IN/OUT */\r
- CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);\r
+ /* Enable device to responds to USB traffic with address 0. */\r
+ USBFS_CR0_REG = USBFS_DEFUALT_CR0;\r
\r
- /* Enable the SIE with an address 0 */\r
- CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE);\r
+#else\r
+ /* Set EP0.CR: ACK Setup, STALL IN/OUT. */\r
+ USBFS_EP0_CR_REG = USBFS_MODE_STALL_IN_OUT;\r
\r
- /* Workaround for PSOC5LP */\r
- CyDelayCycles(1u);\r
+ /* Enable device to respond to USB traffic with address 0. */\r
+ USBFS_CR0_REG = USBFS_DEFUALT_CR0;\r
+ CyDelayCycles(USBFS_WAIT_CR0_REG_STABILITY);\r
+#endif /* (CY_PSOC4) */\r
\r
- /* Finally, Enable d+ pullup and select iomode to USB mode*/\r
- CY_SET_REG8(USBFS_USBIO_CR1_PTR, USBFS_USBIO_CR1_USBPUEN);\r
+ /* Enable D+ pull-up and keep USB control on IO. */\r
+ USBFS_USBIO_CR1_REG = USBFS_USBIO_CR1_USBPUEN;\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ReInitComponent\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function reinitialize the component configuration and is\r
* intend to be called from the Reset interrupt.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_device: Contains the device number of the desired device\r
-* descriptor. The device number can be found in the Device Descriptor Tab\r
-* of "Configure" dialog, under the settings of desired Device Descriptor,\r
-* in the "Device Number" field.\r
-* USBFS_transferState: This variable used by the communication\r
-* functions to handle current transfer state. Initialized to\r
+* \globalvars\r
+* USBFS_device - Contains the device number of the desired Device\r
+* Descriptor. The device number can be found in the Device Descriptor tab\r
+* of the Configure dialog, under the settings of the desired Device Descriptor,\r
+* in the Device Number field.\r
+* USBFS_transferState - This variable is used by the communication\r
+* functions to handle the current transfer state. Initialized to\r
* TRANS_STATE_IDLE in this API.\r
-* USBFS_configuration: Contains current configuration number\r
-* which is set by the Host using SET_CONFIGURATION request.\r
+* USBFS_configuration - Contains the current configuration number\r
+* set by the Host using a SET_CONFIGURATION request.\r
* Initialized to zero in this API.\r
-* USBFS_deviceAddress: Contains current device address. This\r
-* variable is initialized to zero in this API. Host starts to communicate\r
-* to device with address 0 and then set it to whatever value using\r
-* SET_ADDRESS request.\r
-* USBFS_deviceStatus: initialized to 0.\r
-* This is two bit variable which contain power status in first bit\r
-* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote\r
-* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit.\r
-* USBFS_lastPacketSize initialized to 0;\r
-*\r
-* Reentrant:\r
+* USBFS_deviceAddress - Contains the current device address. This\r
+* variable is initialized to zero in this API. The Host starts to communicate\r
+* to the device with address 0 and then sets it to a whatever value using\r
+* a SET_ADDRESS request.\r
+* USBFS_deviceStatus - Initialized to 0.\r
+* This is a two-bit variable which contains the power status in the first bit\r
+* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and the remote\r
+* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in the second bit.\r
+* USBFS_lastPacketSize - Initialized to 0;\r
+*\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
/* Initialize _hidProtocol variable to comply with HID 7.2.6 Set_Protocol\r
* Request: "When initialized, all devices default to report protocol."\r
*/\r
- #if defined(USBFS_ENABLE_HID_CLASS)\r
- uint8 i;\r
-\r
- for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++)\r
- {\r
- USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT;\r
- }\r
- #endif /* USBFS_ENABLE_HID_CLASS */\r
+#if defined(USBFS_ENABLE_HID_CLASS)\r
+ uint8 i;\r
\r
- USBFS_transferState = USBFS_TRANS_STATE_IDLE;\r
+ for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++)\r
+ {\r
+ USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT;\r
+ }\r
+#endif /* USBFS_ENABLE_HID_CLASS */\r
\r
- /* Clear all of the component data */\r
- USBFS_configuration = 0u;\r
- USBFS_interfaceNumber = 0u;\r
+ /* Reset component internal variables. */\r
+ USBFS_transferState = USBFS_TRANS_STATE_IDLE;\r
USBFS_configurationChanged = 0u;\r
- USBFS_deviceAddress = 0u;\r
- USBFS_deviceStatus = 0u;\r
-\r
- USBFS_lastPacketSize = 0u;\r
-\r
-\r
- /* ACK Setup, Stall IN/OUT */\r
- CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);\r
-\r
- /* Enable the SIE with an address 0 */\r
- CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE);\r
-\r
+ USBFS_configuration = 0u;\r
+ USBFS_interfaceNumber = 0u;\r
+ USBFS_deviceAddress = 0u;\r
+ USBFS_deviceStatus = 0u;\r
+ USBFS_lastPacketSize = 0u;\r
+\r
+#if (CY_PSOC4)\r
+ /* Set EP0.CR: ACK Setup, NAK IN/OUT. */\r
+ USBFS_EP0_CR_REG = USBFS_MODE_NAK_IN_OUT;\r
+#else\r
+ /* Set EP0.CR: ACK Setup, STALL IN/OUT. */\r
+ USBFS_EP0_CR_REG = USBFS_MODE_STALL_IN_OUT;\r
+#endif /* (CY_PSOC4) */\r
+\r
+ /* Enable device to respond to USB traffic with address 0. */\r
+ USBFS_CR0_REG = USBFS_DEFUALT_CR0;\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Stop\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function shuts down the USB function including to release\r
-* the D+ Pullup and disabling the SIE.\r
+* the D+ pull-up and disabling the SIE.\r
*\r
-* Parameters:\r
-* None.\r
+* \globalvars\r
+* \ref USBFS_configuration\r
*\r
-* Return:\r
-* None.\r
+* USBFS_deviceAddress - Contains the current device address. This\r
+* variable is initialized to zero in this API. The Host starts to communicate\r
+* to the device with address 0 and then sets it to a whatever value using\r
+* a SET_ADDRESS request.\r
*\r
-* Global variables:\r
-* USBFS_configuration: Contains current configuration number\r
-* which is set by the Host using SET_CONFIGURATION request.\r
-* Initialized to zero in this API.\r
-* USBFS_deviceAddress: Contains current device address. This\r
-* variable is initialized to zero in this API. Host starts to communicate\r
-* to device with address 0 and then set it to whatever value using\r
-* SET_ADDRESS request.\r
-* USBFS_deviceStatus: initialized to 0.\r
-* This is two bit variable which contain power status in first bit\r
-* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote\r
-* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit.\r
-* USBFS_configurationChanged: This variable is set to one after\r
-* SET_CONFIGURATION request and cleared in this function.\r
-* USBFS_intiVar variable is set to zero\r
+* \ref USBFS_deviceStatus\r
+*\r
+* \ref USBFS_configurationChanged\r
+*\r
+* USBFS_intiVar - This variable is set to zero\r
*\r
*******************************************************************************/\r
void USBFS_Stop(void) \r
{\r
+ uint8 enableInterrupts;\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+ /* Stop all DMA channels. */\r
+ USBFS_Stop_DMA(USBFS_MAX_EP);\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+ enableInterrupts = CyEnterCriticalSection();\r
+\r
+ /* Disable USB IP to respond to USB traffic. */\r
+ USBFS_CR0_REG &= (uint8) ~USBFS_CR0_ENABLE;\r
+\r
+ /* Disable D+ pull-up. */\r
+ USBFS_USBIO_CR1_REG &= (uint8) ~ USBFS_USBIO_CR1_USBPUEN;\r
+\r
+#if (CY_PSOC4)\r
+ /* Disable USBFS block. */\r
+ USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_ENABLE;\r
+#else\r
+ /* Clear power active and standby mode templates. */\r
+ USBFS_PM_ACT_CFG_REG &= (uint8) ~USBFS_PM_ACT_EN_FSUSB;\r
+ USBFS_PM_STBY_CFG_REG &= (uint8) ~USBFS_PM_STBY_EN_FSUSB;\r
+\r
+ /* Ensure single-ended disable bits are high (PRT15.INP_DIS[7:6])\r
+ * (input receiver disabled). */\r
+ USBFS_DM_INP_DIS_REG |= (uint8) USBFS_DM_MASK;\r
+ USBFS_DP_INP_DIS_REG |= (uint8) USBFS_DP_MASK;\r
\r
- #if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
+#endif /* (CY_PSOC4) */\r
\r
- /* Disable the SIE */\r
- USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE);\r
- /* Disable the d+ pullup */\r
- USBFS_USBIO_CR1_REG &= (uint8)(~USBFS_USBIO_CR1_USBPUEN);\r
- /* Disable USB in ACT PM */\r
- USBFS_PM_ACT_CFG_REG &= (uint8)(~USBFS_PM_ACT_EN_FSUSB);\r
- /* Disable USB block for Standby Power Mode */\r
- USBFS_PM_STBY_CFG_REG &= (uint8)(~USBFS_PM_STBY_EN_FSUSB);\r
+ CyExitCriticalSection(enableInterrupts);\r
+\r
+ /* Disable component interrupts. */\r
+#if (CY_PSOC4)\r
+ CyIntDisable(USBFS_INTR_HI_VECT_NUM);\r
+ CyIntDisable(USBFS_INTR_LO_VECT_NUM);\r
+ CyIntDisable(USBFS_INTR_MED_VECT_NUM);\r
+#else\r
\r
- /* Disable the reset and EP interrupts */\r
CyIntDisable(USBFS_BUS_RESET_VECT_NUM);\r
CyIntDisable(USBFS_EP_0_VECT_NUM);\r
- #if(USBFS_EP1_ISR_REMOVE == 0u)\r
+\r
+ #if (USBFS_SOF_ISR_ACTIVE)\r
+ CyIntDisable(USBFS_SOF_VECT_NUM);\r
+ #endif /* (USBFS_SOF_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP1_ISR_ACTIVE)\r
CyIntDisable(USBFS_EP_1_VECT_NUM);\r
- #endif /* USBFS_EP1_ISR_REMOVE */\r
- #if(USBFS_EP2_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP1_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP2_ISR_ACTIVE)\r
CyIntDisable(USBFS_EP_2_VECT_NUM);\r
- #endif /* USBFS_EP2_ISR_REMOVE */\r
- #if(USBFS_EP3_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP2_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP3_ISR_ACTIVE)\r
CyIntDisable(USBFS_EP_3_VECT_NUM);\r
- #endif /* USBFS_EP3_ISR_REMOVE */\r
- #if(USBFS_EP4_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP3_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP4_ISR_ACTIVE)\r
CyIntDisable(USBFS_EP_4_VECT_NUM);\r
- #endif /* USBFS_EP4_ISR_REMOVE */\r
- #if(USBFS_EP5_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP4_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP5_ISR_ACTIVE)\r
CyIntDisable(USBFS_EP_5_VECT_NUM);\r
- #endif /* USBFS_EP5_ISR_REMOVE */\r
- #if(USBFS_EP6_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP5_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP6_ISR_ACTIVE)\r
CyIntDisable(USBFS_EP_6_VECT_NUM);\r
- #endif /* USBFS_EP6_ISR_REMOVE */\r
- #if(USBFS_EP7_ISR_REMOVE == 0u)\r
+ #endif /* USBFS_EP6_ISR_REMOVE */\r
+\r
+ #if (USBFS_EP7_ISR_ACTIVE)\r
CyIntDisable(USBFS_EP_7_VECT_NUM);\r
- #endif /* USBFS_EP7_ISR_REMOVE */\r
- #if(USBFS_EP8_ISR_REMOVE == 0u)\r
+ #endif /* (USBFS_EP7_ISR_ACTIVE) */\r
+\r
+ #if (USBFS_EP8_ISR_ACTIVE)\r
CyIntDisable(USBFS_EP_8_VECT_NUM);\r
- #endif /* USBFS_EP8_ISR_REMOVE */\r
+ #endif /* (USBFS_EP8_ISR_ACTIVE) */\r
\r
- /* Clear all of the component data */\r
- USBFS_configuration = 0u;\r
- USBFS_interfaceNumber = 0u;\r
+ #if (USBFS_DP_ISR_ACTIVE)\r
+ /* Clear active mode Dp interrupt source history. */\r
+ (void) USBFS_Dp_ClearInterrupt();\r
+ CyIntClearPending(USBFS_DP_INTC_VECT_NUM);\r
+ #endif /* (USBFS_DP_ISR_ACTIVE). */\r
+\r
+#endif /* (CY_PSOC4) */\r
+\r
+ /* Reset component internal variables. */\r
USBFS_configurationChanged = 0u;\r
- USBFS_deviceAddress = 0u;\r
- USBFS_deviceStatus = 0u;\r
- USBFS_initVar = 0u;\r
+ USBFS_configuration = 0u;\r
+ USBFS_interfaceNumber = 0u;\r
+ USBFS_deviceAddress = 0u;\r
+ USBFS_deviceStatus = 0u;\r
\r
+ /* It is mandatory for correct device startup. */\r
+ USBFS_initVar = 0u;\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_CheckActivity\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Returns the activity status of the bus. Clears the status hardware to\r
-* provide fresh activity status on the next call of this routine.\r
+* This function returns the activity status of the bus. It clears the hardware\r
+* status to provide updated status on the next call of this function. It\r
+* provides a way to determine whether any USB bus activity occurred. The\r
+* application should use this function to determine if the USB suspend\r
+* conditions are met.\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
-* 1 - If bus activity was detected since the last call to this function\r
-* 0 - If bus activity not was detected since the last call to this function\r
+* \return\r
+* cystatus: Status of the bus since the last call of the function.\r
+* Return Value | Description\r
+* -------------|---------------------------------------------------------------\r
+* 1 |Bus activity was detected since the last call to this function\r
+* 0 |Bus activity was not detected since the last call to this function\r
+*\r
*\r
*******************************************************************************/\r
uint8 USBFS_CheckActivity(void) \r
{\r
- uint8 r;\r
+ uint8 cr1Reg = USBFS_CR1_REG;\r
\r
- r = CY_GET_REG8(USBFS_CR1_PTR);\r
- CY_SET_REG8(USBFS_CR1_PTR, (r & ((uint8)(~USBFS_CR1_BUS_ACTIVITY))));\r
+ /* Clear bus activity. */\r
+ USBFS_CR1_REG = (cr1Reg & (uint8) ~USBFS_CR1_BUS_ACTIVITY);\r
\r
- return((r & USBFS_CR1_BUS_ACTIVITY) >> USBFS_CR1_BUS_ACTIVITY_SHIFT);\r
+ /* Get bus activity. */\r
+ return ((0u != (cr1Reg & USBFS_CR1_BUS_ACTIVITY)) ? (1u) : (0u));\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_GetConfiguration\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Returns the current configuration setting\r
+* This function gets the current configuration of the USB device.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* configuration.\r
+* \return\r
+* Returns the currently assigned configuration. Returns 0 if the device\r
+* is not configured\r
*\r
*******************************************************************************/\r
uint8 USBFS_GetConfiguration(void) \r
{\r
- return(USBFS_configuration);\r
+ return (USBFS_configuration);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_IsConfigurationChanged\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Returns the clear on read configuration state. It is usefull when PC send\r
-* double SET_CONFIGURATION request with same configuration number.\r
+* This function returns the clear-on-read configuration state. It is useful\r
+* when the host sends double SET_CONFIGURATION request with the same \r
+* configuration number or changes alternate settings of the interface. \r
+* After configuration has been changed the OUT endpoints must be enabled and IN \r
+* endpoint must be loaded with data to start communication with the host.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* Not zero value when new configuration has been changed, otherwise zero is\r
+* \return\r
+* None-zero value when new configuration has been changed, otherwise zero is\r
* returned.\r
*\r
-* Global variables:\r
-* USBFS_configurationChanged: This variable is set to one after\r
-* SET_CONFIGURATION request and cleared in this function.\r
+* \globalvars\r
+*\r
+* \ref USBFS_configurationChanged - This variable is set to 1 after\r
+* a SET_CONFIGURATION request and cleared in this function.\r
*\r
*******************************************************************************/\r
uint8 USBFS_IsConfigurationChanged(void) \r
{\r
uint8 res = 0u;\r
\r
- if(USBFS_configurationChanged != 0u)\r
+ if (USBFS_configurationChanged != 0u)\r
{\r
res = USBFS_configurationChanged;\r
USBFS_configurationChanged = 0u;\r
}\r
\r
- return(res);\r
+ return (res);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_GetInterfaceSetting\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Returns the alternate setting from current interface\r
+* This function gets the current alternate setting for the specified interface.\r
+* It is useful to identify which alternate settings are active in the specified \r
+* interface.\r
*\r
-* Parameters:\r
-* uint8 interfaceNumber, interface number\r
+* \param\r
+* interfaceNumber interface number\r
*\r
-* Return:\r
-* Alternate setting.\r
+* \return\r
+* Returns the current alternate setting for the specified interface.\r
*\r
*******************************************************************************/\r
uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber)\r
\r
{\r
- return(USBFS_interfaceSetting[interfaceNumber]);\r
+ return (USBFS_interfaceSetting[interfaceNumber]);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_GetEPState\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Returned the state of the requested endpoint.\r
+* This function returns the state of the requested endpoint.\r
*\r
-* Parameters:\r
-* epNumber: Endpoint Number\r
+* \param epNumber Data endpoint number\r
*\r
-* Return:\r
-* State of the requested endpoint.\r
+* \return\r
+* Returns the current state of the specified USBFS endpoint. Symbolic names and\r
+* their associated values are given in the following table. Use these constants\r
+* whenever you write code to change the state of the endpoints, such as ISR\r
+* code, to handle data sent or received.\r
+*\r
+* Return Value | Description\r
+* -----------------------|-----------------------------------------------------\r
+* USBFS_NO_EVENT_PENDING |The endpoint is awaiting SIE action\r
+* USBFS_EVENT_PENDING |The endpoint is awaiting CPU action\r
+* USBFS_NO_EVENT_ALLOWED |The endpoint is locked from access\r
+* USBFS_IN_BUFFER_FULL |The IN endpoint is loaded and the mode is set to ACK IN\r
+* USBFS_IN_BUFFER_EMPTY |An IN transaction occurred and more data can be loaded\r
+* USBFS_OUT_BUFFER_EMPTY |The OUT endpoint is set to ACK OUT and is waiting for data\r
+* USBFS_OUT_BUFFER_FULL |An OUT transaction has occurred and data can be read\r
*\r
*******************************************************************************/\r
uint8 USBFS_GetEPState(uint8 epNumber) \r
{\r
- return(USBFS_EP[epNumber].apiEpState);\r
+ return (USBFS_EP[epNumber].apiEpState);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_GetEPCount\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function supports Data Endpoints only(EP1-EP8).\r
* Returns the transfer count for the requested endpoint. The value from\r
* the count registers includes 2 counts for the two byte checksum of the\r
* packet. This function subtracts the two counts.\r
*\r
-* Parameters:\r
-* epNumber: Data Endpoint Number.\r
-* Valid values are between 1 and 8.\r
+* \param epNumber Data Endpoint Number.\r
+* Valid values are between 1 and 8.\r
*\r
-* Return:\r
+* \return\r
* Returns the current byte count from the specified endpoint or 0 for an\r
* invalid endpoint.\r
*\r
*******************************************************************************/\r
uint16 USBFS_GetEPCount(uint8 epNumber) \r
{\r
- uint8 ri;\r
- uint16 result = 0u;\r
+ uint16 cntr = 0u;\r
\r
- if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
+ if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
- ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
-\r
- result = (uint8)(CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) &\r
- USBFS_EPX_CNT0_MASK);\r
- result = (result << 8u) | CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri));\r
- result -= USBFS_EPX_CNTX_CRC_COUNT;\r
+ /* Get 11-bits EP counter where epCnt0 - 3 bits MSB and epCnt1 - 8 bits LSB. */\r
+ cntr = ((uint16) USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt0) & USBFS_EPX_CNT0_MASK;\r
+ cntr = ((uint16) (cntr << 8u)) | ((uint16) USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt1);\r
+ cntr -= USBFS_EPX_CNTX_CRC_COUNT;\r
}\r
- return(result);\r
+\r
+ return (cntr);\r
}\r
\r
\r
-#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+#if (CY_PSOC4)\r
+ /*******************************************************************************\r
+ * Function Name: USBFS_InitEpDma\r
+ ****************************************************************************//**\r
+ *\r
+ * This function configures priority for all DMA channels utilized by the\r
+ * component. Also sets callbacks for DMA auto mode.\r
+ *\r
+ *******************************************************************************/\r
+ static void USBFS_InitEpDma(void)\r
+ {\r
+ #if (USBFS_DMA1_ACTIVE)\r
+ CYDMA_CH_CTL_BASE.ctl[USBFS_ep1_dma_CHANNEL] = USBFS_ep1_dma_CHANNEL_CFG;\r
+ #endif /* (USBFS_DMA1_ACTIVE) */\r
+\r
+ #if (USBFS_DMA2_ACTIVE)\r
+ CYDMA_CH_CTL_BASE.ctl[USBFS_ep2_dma_CHANNEL] = USBFS_ep2_dma_CHANNEL_CFG;\r
+ #endif /* (USBFS_DMA2_ACTIVE) */\r
+\r
+ #if (USBFS_DMA3_ACTIVE)\r
+ CYDMA_CH_CTL_BASE.ctl[USBFS_ep3_dma_CHANNEL] = USBFS_ep3_dma_CHANNEL_CFG;\r
+ #endif /* (USBFS_DMA3_ACTIVE) */\r
+\r
+ #if (USBFS_DMA4_ACTIVE)\r
+ CYDMA_CH_CTL_BASE.ctl[USBFS_ep4_dma_CHANNEL] = USBFS_ep4_dma_CHANNEL_CFG;\r
+ #endif /* (USBFS_DMA4_ACTIVE) */\r
+\r
+ #if (USBFS_DMA5_ACTIVE)\r
+ CYDMA_CH_CTL_BASE.ctl[USBFS_ep5_dma_CHANNEL] = USBFS_ep5_dma_CHANNEL_CFG;\r
+ #endif /* (USBFS_DMA5_ACTIVE) */\r
+\r
+ #if (USBFS_DMA6_ACTIVE)\r
+ CYDMA_CH_CTL_BASE.ctl[USBFS_ep6_dma_CHANNEL] = USBFS_ep6_dma_CHANNEL_CFG;\r
+ #endif /* (USBFS_DMA6_ACTIVE) */\r
+\r
+ #if (USBFS_DMA7_ACTIVE)\r
+ CYDMA_CH_CTL_BASE.ctl[USBFS_ep7_dma_CHANNEL] = USBFS_ep7_dma_CHANNEL_CFG;\r
+ #endif /* (USBFS_DMA7_ACTIVE) */\r
+\r
+ #if (USBFS_DMA8_ACTIVE)\r
+ CYDMA_CH_CTL_BASE.ctl[USBFS_ep8_dma_CHANNEL] = USBFS_ep8_dma_CHANNEL_CFG;\r
+ #endif /* (USBFS_DMA8_ACTIVE) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Initialize DMA channel callbacks. */\r
+ #if (USBFS_DMA1_ACTIVE)\r
+ (void) USBFS_ep1_dma_SetInterruptCallback(&USBFS_EP1_DMA_DONE_ISR);\r
+ #endif /* (USBFS_DMA1_ACTIVE) */\r
+\r
+ #if (USBFS_DMA2_ACTIVE)\r
+ (void) USBFS_ep2_dma_SetInterruptCallback(&USBFS_EP2_DMA_DONE_ISR);\r
+ #endif /* (USBFS_DMA2_ACTIVE) */\r
+\r
+ #if (USBFS_DMA3_ACTIVE)\r
+ (void) USBFS_ep3_dma_SetInterruptCallback(&USBFS_EP3_DMA_DONE_ISR);\r
+ #endif /* (USBFS_DMA3_ACTIVE) */\r
+\r
+ #if (USBFS_DMA4_ACTIVE)\r
+ (void) USBFS_ep4_dma_SetInterruptCallback(&USBFS_EP4_DMA_DONE_ISR);\r
+ #endif /* (USBFS_DMA4_ACTIVE) */\r
+\r
+ #if (USBFS_DMA5_ACTIVE)\r
+ (void) USBFS_ep5_dma_SetInterruptCallback(&USBFS_EP5_DMA_DONE_ISR);\r
+ #endif /* (USBFS_DMA5_ACTIVE) */\r
+\r
+ #if (USBFS_DMA6_ACTIVE)\r
+ (void) USBFS_ep6_dma_SetInterruptCallback(&USBFS_EP6_DMA_DONE_ISR);\r
+ #endif /* (USBFS_DMA6_ACTIVE) */\r
+\r
+ #if (USBFS_DMA7_ACTIVE)\r
+ (void) USBFS_ep7_dma_SetInterruptCallback(&USBFS_EP7_DMA_DONE_ISR);\r
+ #endif /* (USBFS_DMA7_ACTIVE) */\r
+\r
+ #if (USBFS_DMA8_ACTIVE)\r
+ (void) USBFS_ep8_dma_SetInterruptCallback(&USBFS_EP8_DMA_DONE_ISR);\r
+ #endif /* (USBFS_DMA8_ACTIVE) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ }\r
+#else\r
\r
\r
- /*******************************************************************************\r
+ /***************************************************************************\r
* Function Name: USBFS_InitEP_DMA\r
- ********************************************************************************\r
+ ************************************************************************//**\r
*\r
- * Summary:\r
* This function allocates and initializes a DMA channel to be used by the\r
* USBFS_LoadInEP() or USBFS_ReadOutEP() APIs for data\r
- * transfer.\r
+ * transfer. It is available when the Endpoint Memory Management parameter\r
+ * is set to DMA.\r
*\r
- * Parameters:\r
- * epNumber: Contains the data endpoint number.\r
- * Valid values are between 1 and 8.\r
- * *pData: Pointer to a data array that is related to the EP transfers.\r
+ * This function is automatically called from the USBFS_LoadInEP() and USBFS_ReadOutEP() APIs.\r
*\r
- * Return:\r
- * None.\r
+ * \param epNumber Contains the data endpoint number.\r
+ * Valid values are between 1 and 8.\r
+ * \param *pData Pointer to a data array that is related to the EP transfers.\r
*\r
- * Reentrant:\r
- * No.\r
+ * \reentrant No.\r
*\r
- *******************************************************************************/\r
- void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)\r
+ ***************************************************************************/\r
+ void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)\r
\r
{\r
uint16 src;\r
uint16 dst;\r
- #if (CY_PSOC3) /* PSoC 3 */\r
- src = HI16(CYDEV_SRAM_BASE);\r
+\r
+ #if (CY_PSOC3)\r
+ src = HI16(CYDEV_SRAM_BASE);\r
+ dst = HI16(CYDEV_PERIPH_BASE);\r
+ pData = pData;\r
+ #else\r
+ if ((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u)\r
+ {\r
+ /* IN endpoint: source is memory buffer. */\r
+ src = HI16(pData);\r
dst = HI16(CYDEV_PERIPH_BASE);\r
- pData = pData;\r
- #else /* PSoC 5 */\r
- if((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u )\r
- { /* for the IN EP source is the SRAM memory buffer */\r
- src = HI16(pData);\r
- dst = HI16(CYDEV_PERIPH_BASE);\r
- }\r
- else\r
- { /* for the OUT EP source is the SIE register */\r
- src = HI16(CYDEV_PERIPH_BASE);\r
- dst = HI16(pData);\r
- }\r
- #endif /* C51 */\r
+ }\r
+ else\r
+ {\r
+ /* OUT endpoint: source is USB IP memory buffer. */\r
+ src = HI16(CYDEV_PERIPH_BASE);\r
+ dst = HI16(pData);\r
+ }\r
+ #endif /* (CY_PSOC3) */\r
+\r
switch(epNumber)\r
{\r
- case USBFS_EP1:\r
- #if(USBFS_DMA1_REMOVE == 0u)\r
- USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize(\r
- USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* USBFS_DMA1_REMOVE */\r
- break;\r
- case USBFS_EP2:\r
- #if(USBFS_DMA2_REMOVE == 0u)\r
- USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize(\r
- USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* USBFS_DMA2_REMOVE */\r
- break;\r
+ #if (USBFS_DMA1_ACTIVE)\r
+ case USBFS_EP1:\r
+ USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize(USBFS_DMA_BYTES_PER_BURST,\r
+ USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
+ break;\r
+ #endif /* (USBFS_DMA1_ACTIVE) */\r
+\r
+ #if (USBFS_DMA2_ACTIVE)\r
+ case USBFS_EP2:\r
+ USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize(USBFS_DMA_BYTES_PER_BURST,\r
+ USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
+ break;\r
+ #endif /* (USBFS_DMA2_ACTIVE) */\r
+\r
+ #if (USBFS_DMA3_ACTIVE)\r
case USBFS_EP3:\r
- #if(USBFS_DMA3_REMOVE == 0u)\r
- USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize(\r
- USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* USBFS_DMA3_REMOVE */\r
- break;\r
+ USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize(USBFS_DMA_BYTES_PER_BURST,\r
+ USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
+ break;\r
+ #endif /* (USBFS_DMA3_ACTIVE) */\r
+\r
+ #if (USBFS_DMA4_ACTIVE)\r
case USBFS_EP4:\r
- #if(USBFS_DMA4_REMOVE == 0u)\r
- USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize(\r
- USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* USBFS_DMA4_REMOVE */\r
- break;\r
+ USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize(USBFS_DMA_BYTES_PER_BURST,\r
+ USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
+ break;\r
+ #endif /* (USBFS_DMA4_ACTIVE) */\r
+\r
+ #if (USBFS_DMA5_ACTIVE)\r
case USBFS_EP5:\r
- #if(USBFS_DMA5_REMOVE == 0u)\r
- USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize(\r
- USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* USBFS_DMA5_REMOVE */\r
- break;\r
- case USBFS_EP6:\r
- #if(USBFS_DMA6_REMOVE == 0u)\r
- USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize(\r
- USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* USBFS_DMA6_REMOVE */\r
- break;\r
- case USBFS_EP7:\r
- #if(USBFS_DMA7_REMOVE == 0u)\r
- USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize(\r
- USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* USBFS_DMA7_REMOVE */\r
- break;\r
- case USBFS_EP8:\r
- #if(USBFS_DMA8_REMOVE == 0u)\r
- USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize(\r
- USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* USBFS_DMA8_REMOVE */\r
- break;\r
- default:\r
- /* Do not support EP0 DMA transfers */\r
- break;\r
+ USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize(USBFS_DMA_BYTES_PER_BURST,\r
+ USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
+ break;\r
+ #endif /* (USBFS_DMA5_ACTIVE) */\r
+\r
+ #if (USBFS_DMA6_ACTIVE)\r
+ case USBFS_EP6:\r
+ USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize(USBFS_DMA_BYTES_PER_BURST,\r
+ USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
+ break;\r
+ #endif /* (USBFS_DMA6_ACTIVE) */\r
+\r
+ #if (USBFS_DMA7_ACTIVE)\r
+ case USBFS_EP7:\r
+ USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize(USBFS_DMA_BYTES_PER_BURST,\r
+ USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
+ break;\r
+ #endif /* (USBFS_DMA7_ACTIVE) */\r
+\r
+ #if (USBFS_DMA8_ACTIVE)\r
+ case USBFS_EP8:\r
+ USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize(USBFS_DMA_BYTES_PER_BURST,\r
+ USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
+ break;\r
+ #endif /* (USBFS_DMA8_ACTIVE) */\r
+\r
+ default:\r
+ /* Do nothing for endpoints other than 1-8. */\r
+ break;\r
}\r
- if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
+\r
+ if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
USBFS_DmaTd[epNumber] = CyDmaTdAllocate();\r
- #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate();\r
- #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate();\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
}\r
}\r
+#endif /* (CY_PSOC4) */\r
\r
-\r
- /*******************************************************************************\r
+ /***************************************************************************\r
* Function Name: USBFS_Stop_DMA\r
- ********************************************************************************\r
- *\r
- * Summary: Stops and free DMA\r
+ ************************************************************************//**\r
+ * \r
+ * This function stops DMA channel associated with endpoint. It is available \r
+ * when the Endpoint Buffer Management parameter is set to DMA. Call this \r
+ * function when endpoint direction is changed from IN to OUT or vice versa \r
+ * to trigger DMA re-configuration when USBFS_LoadInEP() or \r
+ * USBFS_ReadOutEP() functions are called the first time. \r
+ * \r
+ * \param epNumber: The data endpoint number for which associated DMA \r
+ * channel is stopped. The range of valid values is between 1 and 8. To stop \r
+ * all DMAs associated with endpoints call this function with \r
+ * USBFS_MAX_EP argument.\r
*\r
- * Parameters:\r
- * epNumber: Contains the data endpoint number or\r
- * USBFS_MAX_EP to stop all DMAs\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Reentrant:\r
+ * \reentrant\r
* No.\r
*\r
- *******************************************************************************/\r
+ ***************************************************************************/\r
void USBFS_Stop_DMA(uint8 epNumber) \r
{\r
uint8 i;\r
+\r
i = (epNumber < USBFS_MAX_EP) ? epNumber : USBFS_EP1;\r
+\r
do\r
{\r
+ #if (CY_PSOC4)\r
+ if (0u != USBFS_DmaChan[i])\r
+ {\r
+ USBFS_CyDmaChDisable(USBFS_DmaChan[i]);\r
+ }\r
+ #else\r
if(USBFS_DmaTd[i] != DMA_INVALID_TD)\r
{\r
(void) CyDmaChDisable(USBFS_DmaChan[i]);\r
CyDmaTdFree(USBFS_DmaTd[i]);\r
USBFS_DmaTd[i] = DMA_INVALID_TD;\r
}\r
- #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
if(USBFS_DmaNextTd[i] != DMA_INVALID_TD)\r
{\r
CyDmaTdFree(USBFS_DmaNextTd[i]);\r
USBFS_DmaNextTd[i] = DMA_INVALID_TD;\r
}\r
- #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+\r
+ #endif /* (CY_PSOC4) */\r
i++;\r
- }while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP));\r
+ }\r
+ while ((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP));\r
}\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
\r
-#endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
-\r
-#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
-\r
-\r
- /*******************************************************************************\r
+#if (CY_PSOC3 || CY_PSOC5)\r
+#if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ /***************************************************************************\r
* Function Name: USBFS_LoadNextInEP\r
- ********************************************************************************\r
+ ************************************************************************//**\r
*\r
* Summary:\r
* This internal function is used for IN endpoint DMA reconfiguration in\r
* mode: 0 - Configure DMA to send the the rest of data.\r
* 1 - Configure DMA to repeat 2 last bytes of the first burst.\r
*\r
- * Return:\r
- * None.\r
- *\r
- *******************************************************************************/\r
+ ***************************************************************************/\r
void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) \r
{\r
reg16 *convert;\r
\r
- if(mode == 0u)\r
+ if (mode == 0u)\r
{\r
- /* Configure DMA to send the the rest of data */\r
- /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */\r
+ /* Configure DMA to send rest of data. */\r
+ /* CyDmaTdSetConfiguration API is optimized to change transfer length only and configure TD. */\r
convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];\r
- /* Set transfer length */\r
+ /* Set transfer length. */\r
CY_SET_REG16(convert, USBFS_inLength[epNumber] - USBFS_DMA_BYTES_PER_BURST);\r
- /* CyDmaTdSetAddress API is optimized to change only source address */\r
+ /* CyDmaTdSetAddress API is optimized to change source address only. */\r
convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];\r
CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +\r
USBFS_DMA_BYTES_PER_BURST));\r
else\r
{\r
/* Configure DMA to repeat 2 last bytes of the first burst. */\r
- /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */\r
+ /* CyDmaTdSetConfiguration API is optimized to change transfer length only and configure TD. */\r
convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];\r
- /* Set transfer length */\r
+ /* Set transfer length. */\r
CY_SET_REG16(convert, USBFS_DMA_BYTES_REPEAT);\r
- /* CyDmaTdSetAddress API is optimized to change only source address */\r
+ /* CyDmaTdSetAddress API is optimized to change source address only. */\r
convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];\r
CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +\r
- USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT));\r
+ (USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT)));\r
}\r
\r
- /* CyDmaChSetInitialTd API is optimised to init TD */\r
+ /* CyDmaChSetInitialTd API is optimized to initialize TD. */\r
CY_DMA_CH_STRUCT_PTR[USBFS_DmaChan[epNumber]].basic_status[1u] = USBFS_DmaTd[epNumber];\r
}\r
-#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+#endif /* (CY_PSOC3 || CY_PSOC5) */\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_LoadInEP\r
-********************************************************************************\r
+****************************************************************************//**\r
+*\r
+* This function performs different functionality depending on the Component’s\r
+* configured Endpoint Buffer Management. This parameter is defined in\r
+* the Descriptor Root in Component Configure window.\r
*\r
-* Summary:\r
-* Loads and enables the specified USB data endpoint for an IN transfer.\r
+* *Manual (Static/Dynamic Allocation):*\r
+* This function loads and enables the specified USB data endpoint for an IN\r
+* data transfer.\r
*\r
-* Parameters:\r
-* epNumber: Contains the data endpoint number.\r
+* *DMA with Manual Buffer Management:*\r
+* Configures DMA for a data transfer from system RAM to endpoint buffer.\r
+* Generates request for a transfer.\r
+*\r
+* *DMA with Automatic Buffer Management:*\r
+* Configures DMA. This is required only once, so it is done only when parameter\r
+* pData is not NULL. When the pData pointer is NULL, the function skips this\r
+* task. Sets Data ready status: This generates the first DMA transfer and\r
+* prepares data in endpoint buffer.\r
+*\r
+* \param epNumber Contains the data endpoint number.\r
* Valid values are between 1 and 8.\r
-* *pData: A pointer to a data array from which the data for the endpoint space\r
+* \param *pData A pointer to a data array from which the data for the endpoint space\r
* is loaded.\r
-* length: The number of bytes to transfer from the array and then send as a\r
-* result of an IN request. Valid values are between 0 and 512.\r
+* \param length The number of bytes to transfer from the array and then send as\r
+* a result of an IN request. Valid values are between 0 and 512\r
+* (1023 for DMA with Automatic Buffer Management mode). The value 512\r
+* is applicable if only one endpoint is used.\r
*\r
-* Return:\r
-* None.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)\r
\r
{\r
- uint8 ri;\r
- reg8 *p;\r
- #if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
- uint16 i;\r
- #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
-\r
- if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
+ if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
- ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
- p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri);\r
+ #if (!USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Limit length to available buffer USB IP buffer size.*/\r
+ if (length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset))\r
+ {\r
+ length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset;\r
+ }\r
+ #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+\r
+ /* Set count and data toggle. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt0 = (uint8) HI8(length) | USBFS_EP[epNumber].epToggle;\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt1 = (uint8) LO8(length);\r
\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- /* Limits length to available buffer space, auto MM could send packets up to 1024 bytes */\r
- if(length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset))\r
+ #if (USBFS_EP_MANAGEMENT_MANUAL)\r
+ if (NULL != pData)\r
+ {\r
+ /* Copy data using arbiter data register. */\r
+ uint16 i;\r
+ for (i = 0u; i < length; ++i)\r
{\r
- length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset;\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr = pData[i];\r
}\r
- #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ }\r
\r
- /* Set the count and data toggle */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri),\r
- (length >> 8u) | (USBFS_EP[epNumber].epToggle));\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri), length & 0xFFu);\r
+ /* IN endpoint buffer is full - read to be read. */\r
+ USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
\r
- #if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
- if(pData != NULL)\r
- {\r
- /* Copy the data using the arbiter data register */\r
- for (i = 0u; i < length; i++)\r
- {\r
- CY_SET_REG8(p, pData[i]);\r
- }\r
- }\r
- USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
- /* Write the Mode register */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);\r
- #else\r
- /* Init DMA if it was not initialized */\r
- if (USBFS_DmaTd[epNumber] == DMA_INVALID_TD)\r
+ /* Arm IN endpoint. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode;\r
+\r
+ #else\r
+\r
+ #if (CY_PSOC3 || CY_PSOC5LP)\r
+ /* Initialize DMA if it was not initialized. */\r
+ if (DMA_INVALID_TD == USBFS_DmaTd[epNumber])\r
{\r
USBFS_InitEP_DMA(epNumber, pData);\r
}\r
- #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
\r
- #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
+ #if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ /* IN endpoint buffer will be fully loaded by DMA shortly. */\r
USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
+\r
if ((pData != NULL) && (length > 0u))\r
{\r
- /* Enable DMA in mode2 for transferring data */\r
+ #if (CY_PSOC4)\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+\r
+ /* Disable DMA channel: start configuration. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Configure source and destination. */\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData);\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr);\r
+\r
+ /* Configure DMA descriptor. */\r
+ --length;\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | length |\r
+ CYDMA_BYTE | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE);\r
+\r
+ /* Validate descriptor to execute on following DMA request. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+ #else\r
+ /* Configure DMA to transfer data. */\r
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);\r
- (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD,\r
- TD_TERMIN_EN | TD_INC_SRC_ADR);\r
- (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));\r
- /* Enable the DMA */\r
+ (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, TD_TERMIN_EN | TD_INC_SRC_ADR);\r
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) pData), LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr));\r
+\r
+ /* Enable DMA channel. */\r
(void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);\r
(void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);\r
- /* Generate DMA request */\r
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ;\r
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ));\r
- /* Mode register will be written in arb ISR after DMA transfer complete */\r
+ #endif /* (CY_PSOC4) */\r
+\r
+ /* Generate DMA request. */\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint8) USBFS_ARB_EPX_CFG_DMA_REQ;\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_DMA_REQ;\r
+\r
+ /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */\r
}\r
else\r
{\r
- /* When zero-length packet - write the Mode register directly */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);\r
+ /* When zero-length packet: arm IN endpoint directly. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode;\r
}\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
if (pData != NULL)\r
{\r
- /* Enable DMA in mode3 for transferring data */\r
+ #if (CY_PSOC4)\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+\r
+ /* Store address of buffer. */\r
+ USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData;\r
+\r
+ /* Disable DMA channel: start configuration. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Set destination address. */\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr);\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr);\r
+\r
+ /* Configure DMA descriptor. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG |\r
+ CYDMA_BYTE | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN);\r
+\r
+ /* Configure DMA descriptor. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG |\r
+ CYDMA_BYTE | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN);\r
+\r
+ /* Enable interrupt from DMA channel. */\r
+ USBFS_CyDmaSetInterruptMask(channelNum);\r
+\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+\r
+ #else\r
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);\r
- #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
- USBFS_inLength[epNumber] = length;\r
- USBFS_inDataPointer[epNumber] = pData;\r
- /* Configure DMA to send the data only for the first burst */\r
- (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber],\r
- (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length,\r
- USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);\r
- (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));\r
- /* The second TD will be executed only when the first one fails.\r
- * The intention of this TD is to generate NRQ interrupt\r
- * and repeat 2 last bytes of the first burst.\r
- */\r
- (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u,\r
- USBFS_DmaNextTd[epNumber],\r
- USBFS_epX_TD_TERMOUT_EN[epNumber]);\r
- /* Configure DmaNextTd to clear Data ready status */\r
- (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber], LO16((uint32)&clearInDataRdyStatus),\r
- LO16((uint32)(USBFS_ARB_EP1_CFG_IND + ri)));\r
- #else /* Configure DMA to send all data*/\r
- (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length,\r
- USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);\r
- (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));\r
- #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */\r
-\r
- /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */\r
- (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);\r
- /* Enable the DMA */\r
+\r
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ USBFS_inLength[epNumber] = length;\r
+ USBFS_inDataPointer[epNumber] = pData;\r
+\r
+ /* Configure DMA to send data only for first burst */\r
+ (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber],\r
+ (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length,\r
+ USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);\r
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) pData),\r
+ LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr));\r
+\r
+ /* The second TD will be executed only when the first one fails.\r
+ * The intention of this TD is to generate NRQ interrupt\r
+ * and repeat 2 last bytes of the first burst.\r
+ */\r
+ (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u,\r
+ USBFS_DmaNextTd[epNumber],\r
+ USBFS_epX_TD_TERMOUT_EN[epNumber]);\r
+\r
+ /* Configure DmaNextTd to clear Data Ready status. */\r
+ (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber], LO16((uint32) &clearInDataRdyStatus),\r
+ LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg));\r
+ #else\r
+ /* Configure DMA to send all data. */\r
+ (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length,\r
+ USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);\r
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) pData),\r
+ LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr));\r
+ #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+\r
+ /* Clear any potential pending DMA requests before starting DMA channel to transfer data. */\r
+ (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);\r
+ /* Enable DMA. */\r
(void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);\r
(void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);\r
+ #endif /* (CY_PSOC4) */\r
}\r
else\r
{\r
+ /* IN endpoint buffer (32 bytes) will shortly be preloaded by DMA. */\r
USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
- if(length > 0u)\r
+\r
+ if (length > 0u)\r
{\r
- #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
- USBFS_inLength[epNumber] = length;\r
+ #if (CY_PSOC4)\r
+ uint32 lengthDescr0, lengthDescr1;\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+\r
+ /* Get number of full bursts. */\r
+ USBFS_DmaEpBurstCnt[epNumber] = (uint8) (length / USBFS_DMA_BYTES_PER_BURST);\r
+\r
+ /* Get number of elements in the last burst. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (length % USBFS_DMA_BYTES_PER_BURST);\r
+\r
+ /* Get total number of bursts. */\r
+ USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u;\r
+\r
+ /* Adjust number of data elements transferred in last burst. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ?\r
+ (USBFS_DmaEpLastBurstEl[epNumber] - 1u) :\r
+ (USBFS_DMA_BYTES_PER_BURST - 1u);\r
+\r
+ /* Get number of data elements to transfer for descriptor 0 and 1. */\r
+ lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u);\r
+ lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u);\r
+\r
+\r
+ /* Mark which descriptor is last one to execute. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ?\r
+ USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK;\r
+\r
+ /* Restore DMA settings for current transfer. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Restore destination address for input endpoint. */\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber]));\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber] +\r
+ USBFS_DMA_BYTES_PER_BURST));\r
+\r
+ /* Set number of elements to transfer. */\r
+ USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR0, lengthDescr0);\r
+ USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR1, lengthDescr1);\r
+\r
+ /* Validate descriptor 0 and command to start with it. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
+ USBFS_CyDmaSetDescriptor0Next(channelNum);\r
+\r
+ /* Validate descriptor 1. */\r
+ if (USBFS_DmaEpBurstCnt[epNumber] > 1u)\r
+ {\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1); \r
+ } \r
+\r
+ /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */\r
+ USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]);\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+\r
+ #elif (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ USBFS_inLength[epNumber] = length;\r
USBFS_inBufFull[epNumber] = 0u;\r
+\r
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);\r
- /* Configure DMA to send the data only for the first burst */\r
+ /* Configure DMA to send data only for first burst. */\r
(void) CyDmaTdSetConfiguration(\r
USBFS_DmaTd[epNumber], (length > USBFS_DMA_BYTES_PER_BURST) ?\r
USBFS_DMA_BYTES_PER_BURST : length,\r
USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR );\r
- (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],\r
- LO16((uint32)USBFS_inDataPointer[epNumber]), LO16((uint32)p));\r
- /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */\r
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) USBFS_inDataPointer[epNumber]),\r
+ LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr));\r
+ /* Clear Any potential pending DMA requests before starting DMA channel to transfer data. */\r
(void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);\r
- /* Enable the DMA */\r
+ /* Enable DMA. */\r
(void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);\r
(void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);\r
- #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+ #endif /* (CY_PSOC4) */\r
+\r
+ #if !defined (USBFS_MANUAL_IN_EP_ARM)\r
+ /* Set IN data ready to generate DMA request to load data into endpoint buffer. */\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+ #endif /* (USBFS_MANUAL_IN_EP_ARM) */\r
\r
- /* Set Data ready status, This will generate DMA request */\r
- #ifndef USBFS_MANUAL_IN_EP_ARM\r
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
- #endif /* USBFS_MANUAL_IN_EP_ARM */\r
- /* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */\r
+ /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */\r
}\r
else\r
{\r
- /* When zero-length packet - write the Mode register directly */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);\r
+ /* When zero-length packet: arm IN endpoint directly. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode;\r
}\r
}\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */\r
}\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ReadOutEP\r
-********************************************************************************\r
+****************************************************************************//**\r
+*\r
+* This function performs different functionality depending on the Component’s\r
+* configured Endpoint Buffer Management. This parameter is defined in the\r
+* Descriptor Root in Component Configure window.\r
+*\r
+* *Manual (Static/Dynamic Allocation):*\r
+* This function moves the specified number of bytes from endpoint buffer to\r
+* system RAM. The number of bytes actually transferred from endpoint buffer to\r
+* system RAM is the lesser of the actual number of bytes sent by the host or\r
+* the number of bytes requested by the length parameter.\r
+*\r
+* *DMA with Manual Buffer Management:*\r
+* Configure DMA to transfer data from endpoint buffer to system RAM. Generate\r
+* a DMA request. The firmware must wait until the DMA completes the data\r
+* transfer after calling the USBFS_ReadOutEP() API. For example,\r
+* by checking EPstate:\r
+*\r
+* \snippet /USBFS_sut_02.cydsn/main.c checking EPstatey\r
+*\r
+* The USBFS_EnableOutEP() has to be called to allow host to write data into\r
+* the endpoint buffer after DMA has completed transfer data from OUT endpoint\r
+* buffer to SRAM.\r
*\r
-* Summary:\r
-* Read data from an endpoint. The application must call\r
-* USBFS_GetEPState to see if an event is pending.\r
+* *DMA with Automatic Buffer Management:*\r
+* Configure DMA. This is required only once and automatically generates DMA\r
+* requests as data arrives\r
*\r
-* Parameters:\r
-* epNumber: Contains the data endpoint number.\r
+* \param epNumber: Contains the data endpoint number.\r
* Valid values are between 1 and 8.\r
-* pData: A pointer to a data array from which the data for the endpoint space\r
-* is loaded.\r
-* length: The number of bytes to transfer from the USB Out endpoint and loads\r
-* it into data array. Valid values are between 0 and 1023. The function\r
-* moves fewer than the requested number of bytes if the host sends\r
-* fewer bytes than requested.\r
-*\r
-* Returns:\r
+* \param pData: A pointer to a data array from which the data for the endpoint\r
+* space is loaded.\r
+* \param length: The number of bytes to transfer from the USB Out endpoint and\r
+* loads it into data array. Valid values are between 0 and 1023. The\r
+* function moves fewer than the requested number of bytes if the host\r
+* sends fewer bytes than requested.\r
+*\r
+* \return\r
* Number of bytes received, 0 for an invalid endpoint.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)\r
\r
{\r
- uint8 ri;\r
- reg8 *p;\r
- #if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
- uint16 i;\r
- #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- uint16 xferCount;\r
- #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
-\r
- if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL))\r
+ if ((pData != NULL) && (epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
- ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
- p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri);\r
+ #if (!USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Adjust requested length to available data. */\r
+ length = (length > USBFS_GetEPCount(epNumber)) ? USBFS_GetEPCount(epNumber) : length;\r
+ #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- /* Determine which is smaller the requested data or the available data */\r
- xferCount = USBFS_GetEPCount(epNumber);\r
- if (length > xferCount)\r
+ #if (USBFS_EP_MANAGEMENT_MANUAL)\r
+ {\r
+ /* Copy data using arbiter data register. */\r
+ uint16 i;\r
+ for (i = 0u; i < length; ++i)\r
{\r
- length = xferCount;\r
+ pData[i] = (uint8) USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr;\r
}\r
- #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ }\r
\r
- #if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
- /* Copy the data using the arbiter data register */\r
- for (i = 0u; i < length; i++)\r
- {\r
- pData[i] = CY_GET_REG8(p);\r
- }\r
+ /* Arm OUT endpoint after data has been copied from endpoint buffer. */\r
+ USBFS_EnableOutEP(epNumber);\r
+ #else\r
\r
- /* (re)arming of OUT endpoint */\r
- USBFS_EnableOutEP(epNumber);\r
- #else\r
- /*Init DMA if it was not initialized */\r
- if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD)\r
+ #if (CY_PSOC3 || CY_PSOC5LP)\r
+ /* Initialize DMA if it was not initialized. */\r
+ if (DMA_INVALID_TD == USBFS_DmaTd[epNumber])\r
{\r
USBFS_InitEP_DMA(epNumber, pData);\r
}\r
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
\r
- #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
+ #if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ #if (CY_PSOC4)\r
+ {\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
\r
- #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
- /* Enable DMA in mode2 for transferring data */\r
+ /* Disable DMA channel: start configuration. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Configure source and destination. */\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr);\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData);\r
+\r
+ /* Configure DMA descriptor. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | (uint16)(length - 1u) |\r
+ CYDMA_BYTE | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE);\r
+\r
+ /* Validate descriptor to execute on following DMA request. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+ }\r
+ #else\r
+ /* Configure DMA to transfer data. */\r
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);\r
- (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD,\r
- TD_TERMIN_EN | TD_INC_DST_ADR);\r
- (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData));\r
- /* Enable the DMA */\r
+ (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, TD_TERMIN_EN | TD_INC_DST_ADR);\r
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr), LO16((uint32)pData));\r
+\r
+ /* Enable DMA channel. */\r
(void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);\r
(void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);\r
+ #endif /* (CY_PSOC4) */\r
+\r
+ /* Generate DMA request. */\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint8) USBFS_ARB_EPX_CFG_DMA_REQ;\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_DMA_REQ;\r
+\r
+ /* OUT endpoint has to be armed again by user when DMA transfers have been completed.\r
+ * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer.\r
+ */\r
+\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ #if (CY_PSOC4)\r
+ {\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+ uint32 lengthDescr0, lengthDescr1;\r
+\r
+ /* Get number of full bursts. */\r
+ USBFS_DmaEpBurstCnt[epNumber] = (uint8) (length / USBFS_DMA_BYTES_PER_BURST);\r
+\r
+ /* Get number of elements in the last burst. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (length % USBFS_DMA_BYTES_PER_BURST);\r
+\r
+ /* Get total number of bursts. */\r
+ USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u;\r
+\r
+ /* Adjust number of the data elements transfered in last burst. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ?\r
+ (USBFS_DmaEpLastBurstEl[epNumber] - 1u) :\r
+ (USBFS_DMA_BYTES_PER_BURST - 1u);\r
+\r
+ /* Get number of data elements to transfer for descriptor 0 and 1. */\r
+ lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u);\r
+ lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u);\r
+\r
+ /* Mark if revert number of data elements in descriptor after transfer completion. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] |= (USBFS_DmaEpBurstCnt[epNumber] > 2u) ? USBFS_DMA_DESCR_REVERT : 0u;\r
+\r
+ /* Mark last descriptor to be executed. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ?\r
+ USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK;\r
+\r
+ /* Store address of buffer and burst counter for endpoint. */\r
+ USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData;\r
+ USBFS_DmaEpBurstCntBackup[epNumber] = USBFS_DmaEpBurstCnt[epNumber];\r
+\r
+ /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */\r
+ USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]);\r
+\r
+ /* Disable DMA channel: start configuration. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Set destination address. */\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr);\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr);\r
+\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) pData));\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) pData + USBFS_DMA_BYTES_PER_BURST));\r
+\r
+ /* Configure DMA descriptor. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | lengthDescr0 |\r
+ CYDMA_BYTE | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN);\r
+\r
+ /* Configure DMA descriptor. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG | lengthDescr1 |\r
+ CYDMA_BYTE | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN);\r
+\r
+ /* Enable interrupt from DMA channel. */\r
+ USBFS_CyDmaSetInterruptMask(channelNum);\r
\r
- /* Generate DMA request */\r
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ;\r
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ));\r
- /* Out EP will be (re)armed in arb ISR after transfer complete */\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
+ /* Validate DMA descriptor 0 and 1. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- /* Enable DMA in mode3 for transferring data */\r
+ if (USBFS_DmaEpBurstCntBackup[epNumber] > 1u)\r
+ {\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1);\r
+ }\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+ }\r
+ #else\r
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);\r
- (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, USBFS_DmaTd[epNumber],\r
- TD_TERMIN_EN | TD_INC_DST_ADR);\r
- (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData));\r
+ (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_DST_ADR);\r
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr), LO16((uint32) pData));\r
\r
- /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */\r
+ /* Clear Any potential pending DMA requests before starting DMA channel to transfer data. */\r
(void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);\r
- /* Enable the DMA */\r
+\r
+ /* Enable DMA channel. */\r
(void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);\r
(void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);\r
- /* Out EP will be (re)armed in arb ISR after transfer complete */\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* (CY_PSOC4) */\r
+\r
+ /* OUT endpoint has to be armed again by user when DMA transfers have been completed.\r
+ * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer.\r
+ */\r
+\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */\r
+ }\r
+ else\r
+ {\r
+ length = 0u;\r
+ }\r
+\r
+ return (length);\r
+}\r
+\r
+\r
+#if (USBFS_16BITS_EP_ACCESS_ENABLE)\r
+/*******************************************************************************\r
+* Function Name: USBFS_LoadInEP16\r
+****************************************************************************//**\r
+*\r
+* This function performs different functionality depending on the Component’s\r
+* configured Endpoint Buffer Management. This parameter is defined in\r
+* the Descriptor Root in Component Configure window.\r
+*\r
+* *Manual (Static/Dynamic Allocation):*\r
+* This function loads and enables the specified USB data endpoint for an IN\r
+* data transfer.\r
+*\r
+* *DMA with Manual Buffer Management:*\r
+* Configures DMA for a data transfer from system RAM to endpoint buffer.\r
+* Generates request for a transfer.\r
+*\r
+* *DMA with Automatic Buffer Management:*\r
+* Configures DMA. This is required only once, so it is done only when parameter\r
+* pData is not NULL. When the pData pointer is NULL, the function skips this\r
+* task. Sets Data ready status: This generates the first DMA transfer and\r
+* prepares data in endpoint buffer.\r
+*\r
+* \param epNumber Contains the data endpoint number.\r
+* Valid values are between 1 and 8.\r
+* \param *pData A pointer to a data array from which the data for the endpoint\r
+* space is loaded. It shall be ensured that this pointer address is even\r
+* to ensure the 16-bit transfer is aligned to even address. Else, a hard\r
+* fault condition can occur.\r
+* \param length The number of bytes to transfer from the array and then send as\r
+* a result of an IN request. Valid values are between 0 and 512 (1023 for\r
+* DMA with Automatic Buffer Management mode). The value 512 is applicable\r
+* if only one endpoint is used.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void USBFS_LoadInEP16(uint8 epNumber, const uint8 pData[], uint16 length)\r
+{\r
+ /* Check array alignment on half-word boundary. */\r
+ CYASSERT(0u == (((uint32) pData) & 0x01u));\r
+\r
+ if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
+ {\r
+ #if (!USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Limit length to available buffer USB IP buffer size. */\r
+ if (length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset))\r
+ {\r
+ length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset;\r
+ }\r
+ #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+\r
+ /* Set count and data toggle. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt0 = (uint32) HI8(length) | USBFS_EP[epNumber].epToggle;\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt1 = (uint32) LO8(length);\r
+\r
+ /* Adjust requested length: 2 bytes are handled at one data register access. */\r
+ length += (length & 0x01u);\r
+\r
+ #if (USBFS_EP_MANAGEMENT_MANUAL)\r
+ if (NULL != pData)\r
+ {\r
+ /* Convert uint8 array to uint16. */\r
+ const uint16 *dataBuf = (uint16 *) pData;\r
+\r
+ /* Copy data using 16-bits arbiter data register. */\r
+ uint16 i;\r
+ for (i = 0u; i < (length >> 1u); ++i)\r
+ {\r
+ USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16 = dataBuf[i];\r
+ }\r
+ }\r
+\r
+ /* IN endpoint buffer is full - read to be read. */\r
+ USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
+\r
+ /* Arm IN endpoint. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode;\r
+\r
+ #else\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ /* IN endpoint buffer will be fully loaded by DMA shortly. */\r
+ USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
+\r
+ if ((pData != NULL) && (length > 0u))\r
+ {\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+\r
+ /* Disable DMA channel: start configuration. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Configure source and destination. */\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData);\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16);\r
+\r
+ /* Configure DMA descriptor. */\r
+ length = (length >> 1u) - 1u;\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | length |\r
+ CYDMA_HALFWORD | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE);\r
+\r
+ /* Validate descriptor to execute on following DMA request. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+\r
+ /* Generate DMA request. */\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint32) USBFS_ARB_EPX_CFG_DMA_REQ;\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint32) ~USBFS_ARB_EPX_CFG_DMA_REQ;\r
+\r
+ /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */\r
+ }\r
+ else\r
+ {\r
+ /* When zero-length packet: arm IN endpoint directly. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode;\r
+ }\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (pData != NULL)\r
+ {\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+\r
+ /* Store address of buffer. */\r
+ USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData;\r
+\r
+ /* Disable DMA channel: start configuration. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Set destination address. */\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16);\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16);\r
+\r
+ /* Configure DMA descriptor. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG |\r
+ CYDMA_HALFWORD | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN);\r
+\r
+ /* Configure DMA descriptor. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG |\r
+ CYDMA_HALFWORD | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN);\r
+\r
+ /* Enable interrupt from DMA channel. */\r
+ USBFS_CyDmaSetInterruptMask(channelNum);\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+ }\r
+ else\r
+ {\r
+ /* IN endpoint buffer (32 bytes) will shortly be preloaded by DMA. */\r
+ USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
+\r
+ if (length > 0u)\r
+ {\r
+ uint32 lengthDescr0, lengthDescr1;\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+\r
+ /* Get number of full bursts. */\r
+ USBFS_DmaEpBurstCnt[epNumber] = (uint8) (length / USBFS_DMA_BYTES_PER_BURST);\r
+\r
+ /* Get number of elements in the last burst. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (length % USBFS_DMA_BYTES_PER_BURST);\r
+\r
+ /* Get total number of bursts. */\r
+ USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u;\r
+\r
+ /* Adjust number of data elements transferred in last burst. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ?\r
+ ((USBFS_DmaEpLastBurstEl[epNumber] >> 1u) - 1u) :\r
+ (USBFS_DMA_HALFWORDS_PER_BURST - 1u);\r
+\r
+ /* Get number of data elements to transfer for descriptor 0 and 1. */\r
+ lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u);\r
+ lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u);\r
+\r
+ /* Mark which descriptor is last one to execute. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ?\r
+ USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK;\r
+\r
+ /* Restore DMA settings for current transfer. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Restore destination address for input endpoint. */\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber]));\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber] +\r
+ USBFS_DMA_BYTES_PER_BURST));\r
+\r
+ /* Set number of elements to transfer. */\r
+ USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR0, lengthDescr0);\r
+ USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR1, lengthDescr1);\r
+\r
+ /* Validate descriptor 0 and command to start with it. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
+ USBFS_CyDmaSetDescriptor0Next(channelNum);\r
+\r
+ /* Validate descriptor 1. */\r
+ if (USBFS_DmaEpBurstCnt[epNumber] > 1u)\r
+ {\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1);\r
+ }\r
+\r
+ /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */\r
+ USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]);\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+\r
+ #if !defined (USBFS_MANUAL_IN_EP_ARM)\r
+ /* Set IN data ready to generate DMA request to load data into endpoint buffer. */\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+ #endif /* (USBFS_MANUAL_IN_EP_ARM) */\r
+\r
+ /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */\r
+ }\r
+ else\r
+ {\r
+ /* When zero-length packet: arm IN endpoint directly. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode;\r
+ }\r
+ }\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_ReadOutEP16\r
+****************************************************************************//**\r
+*\r
+* This function performs different functionality depending on the Component’s\r
+* configured Endpoint Buffer Management. This parameter is defined in the\r
+* Descriptor Root in Component Configure window.\r
+*\r
+* *Manual (Static/Dynamic Allocation):*\r
+* This function moves the specified number of bytes from endpoint buffer to\r
+* system RAM. The number of bytes actually transferred from endpoint buffer to\r
+* system RAM is the lesser of the actual number of bytes sent by the host or\r
+* the number of bytes requested by the length parameter.\r
+*\r
+* *DMA with Manual Buffer Management:*\r
+* Configure DMA to transfer data from endpoint buffer to system RAM. Generate\r
+* a DMA request. The firmware must wait until the DMA completes the data\r
+* transfer after calling the USBFS_ReadOutEP() API. For example,\r
+* by checking EPstate:\r
+*\r
+* \snippet /USBFS_sut_02.cydsn/main.c checking EPstatey\r
+*\r
+* The USBFS_EnableOutEP() has to be called to allow host to write data into\r
+* the endpoint buffer after DMA has completed transfer data from OUT endpoint\r
+* buffer to SRAM.\r
+*\r
+* *DMA with Automatic Buffer Management:*\r
+* Configure DMA. This is required only once and automatically generates DMA\r
+* requests as data arrives\r
+*\r
+* \param epNumber: Contains the data endpoint number.\r
+* Valid values are between 1 and 8.\r
+* \param pData: A pointer to a data array into which the data for the endpoint\r
+* space is copied. It shall be ensured that this pointer address is\r
+* even to ensure the 16-bit transfer is aligned to even address. Else,\r
+* a hard fault condition can occur.\r
+* \param length: The number of bytes to transfer from the USB Out endpoint and\r
+* loads it into data array. Valid values are between 0 and 1023. The\r
+* function moves fewer than the requested number of bytes if the host\r
+* sends fewer bytes than requested.\r
+*\r
+* \return\r
+* Number of bytes received, 0 for an invalid endpoint.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+*******************************************************************************/\r
+uint16 USBFS_ReadOutEP16(uint8 epNumber, uint8 pData[], uint16 length)\r
+{\r
+ uint32 adjLength;\r
+\r
+ /* Check array alignment on half-word boundary */\r
+ CYASSERT(0u == (((uint32) pData) & 0x01u));\r
+\r
+ if ((pData != NULL) && (epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
+ {\r
+ #if (!USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Adjust requested length to available data. */\r
+ length = (length > USBFS_GetEPCount(epNumber)) ? USBFS_GetEPCount(epNumber) : length;\r
+ #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+\r
+ /* Adjust requested length: 2 bytes are handled at one data register access. */\r
+ adjLength = length + ((uint32)length & 1u);\r
+\r
+ #if (USBFS_EP_MANAGEMENT_MANUAL)\r
+ {\r
+ /* Convert uint8 array to uint16. */\r
+ uint16 *dataBuf = (uint16 *) pData;\r
+\r
+ /* Copy data using 16-bits arbiter data register. */\r
+ uint16 i;\r
+ for (i = 0u; i < (adjLength >> 1u); ++i)\r
+ {\r
+ dataBuf[i] = (uint16) USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16;\r
+ }\r
+ }\r
+\r
+ /* Arm OUT endpoint after data has been read from endpoint buffer. */\r
+ USBFS_EnableOutEP(epNumber);\r
+ #else\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ {\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+\r
+ /* Disable DMA channel: start configuration. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Configure source and destination. */\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16);\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData);\r
+\r
+ /* Configure DMA descriptor. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | (uint16)((adjLength >> 1u) - 1u) |\r
+ CYDMA_HALFWORD | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE);\r
+\r
+ /* Validate descriptor to execute on following DMA request. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+\r
+ /* Generate DMA request. */\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint32) USBFS_ARB_EPX_CFG_DMA_REQ;\r
+ USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint32) ~USBFS_ARB_EPX_CFG_DMA_REQ;\r
+\r
+ /* OUT endpoint has to be armed again by user when DMA transfers have been completed.\r
+ * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer.\r
+ */\r
+ }\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ {\r
+ uint32 lengthDescr0, lengthDescr1;\r
+ uint32 channelNum = (uint32) USBFS_DmaChan[epNumber];\r
+\r
+ /* Get number of full bursts. */\r
+ USBFS_DmaEpBurstCnt[epNumber] = (uint8) (adjLength / USBFS_DMA_BYTES_PER_BURST);\r
+\r
+ /* Get number of elements in last burst. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (adjLength % USBFS_DMA_BYTES_PER_BURST);\r
+\r
+ /* Get total number of bursts. */\r
+ USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u;\r
+\r
+ /* Adjust number of data elements transferred in last burst. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ?\r
+ ((USBFS_DmaEpLastBurstEl[epNumber] >> 1u) - 1u) :\r
+ (USBFS_DMA_HALFWORDS_PER_BURST - 1u);\r
+\r
+ /* Get number of data elements to transfer for descriptor 0 and 1. */\r
+ lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u);\r
+ lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u);\r
+\r
+ /* Mark last descriptor to be executed. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ?\r
+ USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK;\r
+\r
+ /* Mark if revert number of data elements in descriptor after transfer completion. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] |= (USBFS_DmaEpBurstCnt[epNumber] > 2u) ? USBFS_DMA_DESCR_REVERT : 0u;\r
+\r
+ /* Mark that 16-bits access to data register is performed. */\r
+ USBFS_DmaEpLastBurstEl[epNumber] |= USBFS_DMA_DESCR_16BITS;\r
\r
+ /* Store address of buffer and burst counter for endpoint. */\r
+ USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData;\r
+ USBFS_DmaEpBurstCntBackup[epNumber] = USBFS_DmaEpBurstCnt[epNumber];\r
+\r
+ /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */\r
+ USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]);\r
+\r
+ /* Disable DMA channel: start configuration. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Set destination address. */\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16);\r
+ USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16);\r
+\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) pData));\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) pData + USBFS_DMA_BYTES_PER_BURST));\r
+\r
+ /* Configure DMA descriptor 0. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | lengthDescr0 |\r
+ CYDMA_HALFWORD | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN);\r
+\r
+ /* Configure DMA descriptor 1. */\r
+ USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG | lengthDescr1 |\r
+ CYDMA_HALFWORD | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN);\r
+\r
+ /* Enable interrupt from DMA channel. */\r
+ USBFS_CyDmaSetInterruptMask(channelNum);\r
+\r
+ /* Validate DMA descriptor 0 and 1. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
+ \r
+ if (USBFS_DmaEpBurstCntBackup[epNumber] > 1u)\r
+ {\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1);\r
+ }\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+\r
+ /* OUT endpoint has to be armed again by user when DMA transfers have been completed.\r
+ * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer.\r
+ */\r
+ }\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */\r
}\r
else\r
{\r
length = 0u;\r
}\r
\r
- return(length);\r
+ return (length);\r
}\r
+#endif /* (USBFS_16BITS_EP_ACCESS_ENABLE) */\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_EnableOutEP\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* This function enables an OUT endpoint. It should not be\r
-* called for an IN endpoint.\r
+* This function enables the specified endpoint for OUT transfers. Do not call\r
+* this function for IN endpoints.\r
*\r
-* Parameters:\r
-* epNumber: Endpoint Number\r
-* Valid values are between 1 and 8.\r
+* \param epNumber: Contains the data endpoint number. Valid values are between\r
+* 1 and 8.\r
*\r
-* Return:\r
-* None.\r
+* \globalvars\r
*\r
-* Global variables:\r
-* USBFS_EP[epNumber].apiEpState - set to NO_EVENT_PENDING\r
+* \ref USBFS_EP[epNumber].apiEpState - set to NO_EVENT_PENDING\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_EnableOutEP(uint8 epNumber) \r
{\r
- uint8 ri;\r
-\r
- if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
+ if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
- ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
- /* Write the Mode register */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);\r
+\r
+ /* Enable OUT endpoint to be written by Host. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode;\r
+ \r
}\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_DisableOutEP\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* This function disables an OUT endpoint. It should not be\r
-* called for an IN endpoint.\r
+* This function disables the specified USBFS OUT endpoint. Do not call this\r
+* function for IN endpoints.\r
*\r
-* Parameters:\r
-* epNumber: Endpoint Number\r
+* \param epNumber: Contains the data endpoint number.\r
* Valid values are between 1 and 8.\r
*\r
-* Return:\r
-* None.\r
-*\r
*******************************************************************************/\r
void USBFS_DisableOutEP(uint8 epNumber) \r
{\r
- uint8 ri ;\r
-\r
- if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
+ if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
- ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
- /* Write the Mode register */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT);\r
+ /* Set NAK response for OUT endpoint. */\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_MODE_NAK_OUT;\r
}\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Force\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Forces the bus state\r
+* This function forces a USB J, K, or SE0 state on the D+/D– lines. It provides\r
+* the necessary mechanism for a USB device application to perform a USB Remote\r
+* Wakeup. For more information, see the USB 2.0 Specification for details on\r
+* Suspend and Resume.\r
*\r
-* Parameters:\r
-* bState\r
-* USBFS_FORCE_J\r
-* USBFS_FORCE_K\r
-* USBFS_FORCE_SE0\r
-* USBFS_FORCE_NONE\r
+* \param state A byte indicating which of the four bus states to enable.\r
+* Symbolic names and their associated values are listed here:\r
+* State |Description\r
+* ---------------------------|----------------------------------------------\r
+* USBFS_FORCE_J | Force a J State onto the D+/D– lines\r
+* USBFS_FORCE_K | Force a K State onto the D+/D– lines\r
+* USBFS_FORCE_SE0 | Force a Single Ended 0 onto the D+/D– lines\r
+* USBFS_FORCE_NONE| Return bus to SIE control\r
*\r
-* Return:\r
-* None.\r
*\r
*******************************************************************************/\r
void USBFS_Force(uint8 bState) \r
{\r
- CY_SET_REG8(USBFS_USBIO_CR0_PTR, bState);\r
+ /* This registers is used only for manual control of SIE (no masking is\r
+ * needed before write into it).\r
+ */\r
+ USBFS_USBIO_CR0_REG = bState;\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_GetEPAckState\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Returns the ACK of the CR0 Register (ACKD)\r
+* This function determines whether an ACK transaction occurred on this endpoint\r
+* by reading the ACK bit in the control register of the endpoint. It does not\r
+* clear the ACK bit.\r
*\r
-* Parameters:\r
-* epNumber: Endpoint Number\r
+* \param epNumber Contains the data endpoint number.\r
* Valid values are between 1 and 8.\r
*\r
-* Returns\r
-* 0 if nothing has been ACKD, non-=zero something has been ACKD\r
+* \return\r
+* If an ACKed transaction occurred, this function returns a non-zero value.\r
+* Otherwise, it returns zero.\r
*\r
*******************************************************************************/\r
uint8 USBFS_GetEPAckState(uint8 epNumber) \r
{\r
- uint8 ri;\r
uint8 cr = 0u;\r
\r
- if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
+ if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
- ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
- cr = CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri)) & USBFS_MODE_ACKD;\r
+ cr = USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 & USBFS_MODE_ACKD;\r
}\r
\r
- return(cr);\r
+ return ((uint8) cr);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_SetPowerStatus\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Sets the device power status for reporting in the Get Device Status\r
-* request\r
+* This function sets the current power status. The device replies to USB\r
+* GET_STATUS requests based on this value. This allows the device to properly\r
+* report its status for USB Chapter 9 compliance. Devices can change their\r
+* power source from self powered to bus powered at any time and report their\r
+* current power source as part of the device status. You should call this\r
+* function any time your device changes from self powered to bus powered or\r
+* vice versa, and set the status appropriately.\r
*\r
-* Parameters:\r
-* powerStatus: USBFS_DEVICE_STATUS_BUS_POWERED(0) - Bus Powered,\r
-* USBFS_DEVICE_STATUS_SELF_POWERED(1) - Self Powered\r
+* \param powerStatus: Contains the desired power status, one for self powered\r
+* or zero for bus powered. Symbolic names and their associated values are\r
+* given here:\r
+* Power Status |Description\r
+* --------------------------------------------|---------------------------\r
+* USBFS_DEVICE_STATUS_BUS_POWERED | Set the device to bus powered\r
+* USBFS_DEVICE_STATUS_SELF_POWERED | Set the device to self powered\r
*\r
-* Return:\r
-* None.\r
+* \globalvars\r
*\r
-* Global variables:\r
-* USBFS_deviceStatus - set power status\r
+* \ref USBFS_deviceStatus - set power status\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
{\r
if (powerStatus != USBFS_DEVICE_STATUS_BUS_POWERED)\r
{\r
- USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED;\r
+ USBFS_deviceStatus |= (uint8) USBFS_DEVICE_STATUS_SELF_POWERED;\r
}\r
else\r
{\r
- USBFS_deviceStatus &= ((uint8)(~USBFS_DEVICE_STATUS_SELF_POWERED));\r
+ USBFS_deviceStatus &= (uint8) ~USBFS_DEVICE_STATUS_SELF_POWERED;\r
}\r
}\r
\r
\r
-#if (USBFS_MON_VBUS == 1u)\r
-\r
- /*******************************************************************************\r
+#if (USBFS_VBUS_MONITORING_ENABLE)\r
+ /***************************************************************************\r
* Function Name: USBFS_VBusPresent\r
- ********************************************************************************\r
+ ************************************************************************//**\r
*\r
- * Summary:\r
- * Determines VBUS presence for Self Powered Devices.\r
+ * Determines VBUS presence for self-powered devices. This function is\r
+ * available when the VBUS Monitoring option is enabled in the Advanced tab.\r
*\r
- * Parameters:\r
- * None.\r
+ * \return\r
+ * The return value can be the following:\r
+ * Return Value | Description\r
+ * -------------|-----------------\r
+ * 1 | VBUS is present\r
+ * 0 | VBUS is absent\r
*\r
- * Return:\r
- * 1 if VBUS is present, otherwise 0.\r
*\r
- *******************************************************************************/\r
+ ***************************************************************************/\r
uint8 USBFS_VBusPresent(void) \r
{\r
- return((0u != (CY_GET_REG8(USBFS_VBUS_PS_PTR) & USBFS_VBUS_MASK)) ? 1u : 0u);\r
+ return ((0u != (USBFS_VBUS_STATUS_REG & USBFS_VBUS_VALID)) ? (uint8) 1u : (uint8) 0u);\r
}\r
-\r
-#endif /* USBFS_MON_VBUS */\r
+#endif /* (USBFS_VBUS_MONITORING_ENABLE) */\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_RWUEnabled\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Returns TRUE if Remote Wake Up is enabled, otherwise FALSE\r
+* This function returns the current remote wakeup status.\r
+* If the device supports remote wakeup, the application should use this\r
+* function to determine if remote wakeup was enabled by the host. When the\r
+* device is suspended and it determines the conditions to initiate a remote\r
+* wakeup are met, the application should use the USBFS_Force() function to\r
+* force the appropriate J and K states onto the USB bus, signaling a remote\r
+* wakeup.\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
-* TRUE - Remote Wake Up Enabled\r
-* FALSE - Remote Wake Up Disabled\r
+* \return\r
+* Returns non-zero value if remote wakeup is enabled and zero otherwise.\r
*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_deviceStatus - checked to determine remote status\r
*\r
*******************************************************************************/\r
uint8 USBFS_RWUEnabled(void) \r
{\r
uint8 result = USBFS_FALSE;\r
- if((USBFS_deviceStatus & USBFS_DEVICE_STATUS_REMOTE_WAKEUP) != 0u)\r
+\r
+ if (0u != (USBFS_deviceStatus & USBFS_DEVICE_STATUS_REMOTE_WAKEUP))\r
{\r
result = USBFS_TRUE;\r
}\r
\r
- return(result);\r
+ return (result);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_GetDeviceAddress\r
+****************************************************************************//**\r
+*\r
+* This function returns the currently assigned address for the USB device.\r
+*\r
+* \return\r
+* Returns the currently assigned address.\r
+* Returns 0 if the device has not yet been assigned an address.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_GetDeviceAddress(void) \r
+{\r
+ return (uint8)(USBFS_CR0_REG & USBFS_CR0_DEVICE_ADDRESS_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_EnableSofInt\r
+****************************************************************************//**\r
+*\r
+* This function enables interrupt generation when a Start-of-Frame (SOF)\r
+* packet is received from the host.\r
+*\r
+*******************************************************************************/\r
+void USBFS_EnableSofInt(void) \r
+{\r
+#if (CY_PSOC4)\r
+ /* Enable SOF interrupt interrupt source. */\r
+ USBFS_INTR_SIE_MASK_REG |= (uint32) USBFS_INTR_SIE_SOF_INTR;\r
+#else\r
+ /* Enable SOF interrupt if it is present. */\r
+ #if (USBFS_SOF_ISR_ACTIVE)\r
+ CyIntEnable(USBFS_SOF_VECT_NUM);\r
+ #endif /* (USBFS_SOF_ISR_ACTIVE) */\r
+#endif /* (CY_PSOC4) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_DisableSofInt\r
+****************************************************************************//**\r
+*\r
+* This function disables interrupt generation when a Start-of-Frame (SOF)\r
+* packet is received from the host.\r
+*\r
+*******************************************************************************/\r
+void USBFS_DisableSofInt(void) \r
+{\r
+#if (CY_PSOC4)\r
+ /* Disable SOF interrupt interrupt source. */\r
+ USBFS_INTR_SIE_MASK_REG &= (uint32) ~USBFS_INTR_SIE_SOF_INTR;\r
+#else\r
+ /* Disable SOF interrupt if it is present. */\r
+ #if (USBFS_SOF_ISR_ACTIVE)\r
+ CyIntDisable(USBFS_SOF_VECT_NUM);\r
+ #endif /* (USBFS_SOF_ISR_ACTIVE) */\r
+#endif /* (CY_PSOC4) */\r
}\r
\r
\r
+#if (USBFS_BATT_CHARG_DET_ENABLE)\r
+ /***************************************************************************\r
+ * Function Name: USBFS_DetectPortType\r
+ ************************************************************************//**\r
+ *\r
+ * This function implements the USB Battery Charger Detection (BCD)\r
+ * algorithm to determine the type of USB host downstream port. This API\r
+ * is available only for PSoC 4 devices, and should be called when the VBUS\r
+ * voltage transition (OFF to ON) is detected on the bus. If the USB device\r
+ * functionality is enabled, this API first calls USBFS_Stop() API\r
+ * internally to disable the USB device functionality, and then proceeds to\r
+ * implement the BCD algorithm to detect the USB host port type.\r
+ * The USBFS_Start() API should be called after this API if the USB\r
+ * communication needs to be initiated with the host.\r
+ * *Note* This API is generated only if the “Enable Battery Charging \r
+ * Detection” option is enabled in the “Advanced” tab of the component GUI.\r
+ * *Note* API implements the steps 2-4 of the BCD algorithm which are \r
+ * - Data Contact Detect\r
+ * - Primary Detection \r
+ * - Secondary Detection \r
+ * \r
+ * The first step of BCD algorithm, namely, VBUS detection shall be handled \r
+ * at the application firmware level.\r
+ *\r
+ * \return\r
+ * The return value can be the following:\r
+ * Return Value |Description\r
+ * ----------------------------------|-------------------------------------\r
+ * USBFS_BCD_PORT_SDP | Standard downstream port detected\r
+ * USBFS_BCD_PORT_CDP | Charging downstream port detected\r
+ * USBFS_BCD_PORT_DCP | Dedicated charging port detected\r
+ * USBFS_BCD_PORT_UNKNOWN | Unable to detect charging port type (proprietary charger type)\r
+ * USBFS_BCD_PORT_ERR | Error condition in detection process\r
+ *\r
+ *\r
+ * \sideeffects\r
+ *\r
+ * USB device functionality is disabled by this API if not already disabled.\r
+ *\r
+ ***************************************************************************/\r
+ uint8 USBFS_Bcd_DetectPortType(void)\r
+ {\r
+ uint32 bkPwrCtrl;\r
+ uint32 cr1RegVal;\r
+ uint32 secondaryDetection = 0u;\r
+ uint8 result = USBFS_BCD_PORT_UNKNOWN;\r
+\r
+ /*Check USB Started and Stop it*/\r
+ if(0u != USBFS_initVar)\r
+ {\r
+ USBFS_Stop();\r
+ }\r
+ /*Initialize USBFS IP for Charger detection*/\r
+\r
+ /*Enable clock to USB IP. */\r
+ USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_CSR_CLK_EN;\r
+\r
+ /* Enable USBIO control on drive mode of D+ and D- pins. */\r
+ USBFS_USBIO_CR1_REG &= ~ (uint32) USBFS_USBIO_CR1_IOMODE;\r
+\r
+ /* Select VBUS detection source and clear PHY isolate. The application\r
+ * level must ensure that VBUS is valid. There is no need to wait 2us\r
+ * before VBUS is valid.\r
+ */\r
+ bkPwrCtrl = USBFS_POWER_CTRL_REG;\r
+ USBFS_POWER_CTRL_REG = USBFS_DEFAULT_POWER_CTRL_VBUS\\r
+ & (~USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN)\\r
+ & (~USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN);\r
+\r
+\r
+ /* Enable PHY detector and single-ended and differential receivers.\r
+ * Enable charger detection. */\r
+ USBFS_POWER_CTRL_REG |= USBFS_DEFAULT_POWER_CTRL_PHY\\r
+ | USBFS_POWER_CTRL_ENABLE_CHGDET;\r
+\r
+ /* Suspend clear sequence. */\r
+ USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND;\r
+ CyDelayUs(USBFS_WAIT_SUSPEND_DEL_DISABLE);\r
+ USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND_DEL;\r
+\r
+ /* Data connection detection\r
+ * Realization with delay as Hard IP does not support DCD 300 ms.\r
+ */\r
+ #if defined (USBFS_NO_DCD)\r
+ CyDelay(USBFS_BCD_TIMEOUT);\r
+ #else\r
+ /* DCD implementation:*/\r
+\r
+ {\r
+ uint16 timeout = USBFS_BCD_TIMEOUT;\r
+ uint8 connectionApproved = 0u;\r
+ uint8 connected = 0u;\r
+\r
+ /* BCD spec 1.2: Turns on Idp_src and D- pull-down resistor */\r
+ USBFS_POWER_CTRL_REG |= USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN;\r
+ USBFS_CHGDET_CTRL_REG |= USBFS_CHGDET_CTRL_DCD_SRC_EN;\r
+\r
+ /* BCD spec 1.2: Waits for D+ to be low for a time of Tdcd_dbnc*/\r
+ while ((0u != timeout) && (0u == connectionApproved))\r
+ {\r
+ if (0u == (USBFS_USBIO_CR1_REG & USBFS_USBIO_CR1_DP0))\r
+ {\r
+ connected++;\r
+ }\r
+ else\r
+ {\r
+ connected = 0u;\r
+ }\r
+ connectionApproved = (USBFS_BCD_TDCD_DBNC < connected) ? 1u:0u;\r
+ CyDelay(1u);\r
+ timeout--;\r
+ }\r
+\r
+ /* BCD spec 1.2: Turns off Idp_src. */\r
+ USBFS_CHGDET_CTRL_REG &= ~USBFS_CHGDET_CTRL_DCD_SRC_EN;\r
+ }\r
+ #endif /*(USBFS_NO_DCD)*/\r
+\r
+ /* Primary detection: enable VDP_SRC on D+ and IDM_SINK on D-. */\r
+ USBFS_CHGDET_CTRL_REG = USBFS_CHGDET_CTRL_PRIMARY;\r
+ CyDelay(USBFS_BCD_PRIMARY_WAIT);\r
+ cr1RegVal = USBFS_USBIO_CR1_REG;\r
+\r
+ /* Check is it SDP or DCP/CDP, read comparator 2 output. */\r
+ if (0u == (USBFS_CHGDET_CTRL_REG & USBFS_CHGDET_CTRL_COMP_OUT))\r
+ {\r
+ /* Check status of D- line. */\r
+ if (0u == (cr1RegVal & USBFS_USBIO_CR1_DM0))\r
+ {\r
+ result = USBFS_BCD_PORT_SDP;\r
+ }\r
+ else\r
+ {\r
+ /* ERROR: such combination is impossible. Abort charger\r
+ * detection.\r
+ */\r
+ result = USBFS_BCD_PORT_ERR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Need Secondary detection. Charging port: DCP or proprietary*/\r
+ secondaryDetection = 1u;\r
+ }\r
+\r
+ /* Secondary detection: Set CHGDET_CTRL register to enable VDM_SRC on D- and IDP_SINK on D+. */\r
+\r
+ if (0u != secondaryDetection)\r
+ {\r
+ USBFS_CHGDET_CTRL_REG = USBFS_CHGDET_CTRL_DEFAULT \\r
+ | USBFS_CHGDET_CTRL_SECONDARY;\r
+ CyDelay(USBFS_BCD_SECONDARY_WAIT);\r
+ cr1RegVal = USBFS_USBIO_CR1_REG;\r
+\r
+ /* Check is it SDP or DCP/CDP, read comparator 1 output. */\r
+ if (0u == (USBFS_CHGDET_CTRL_REG & USBFS_CHGDET_CTRL_COMP_OUT))\r
+ {\r
+ /* Check status of D+ line. */\r
+ if (0u == (cr1RegVal & USBFS_USBIO_CR1_DP0))\r
+ {\r
+ result = USBFS_BCD_PORT_CDP;\r
+ }\r
+ else\r
+ {\r
+ /* ERROR: such combination is impossible. Abort charger\r
+ * detection.\r
+ */\r
+ result = USBFS_BCD_PORT_ERR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* Check status of D+ line. */\r
+ if (0u == (cr1RegVal & USBFS_USBIO_CR1_DP0))\r
+ {\r
+ result = USBFS_BCD_PORT_DCP;\r
+ }\r
+ else\r
+ {\r
+ /* It is may be proprietary charger. Proprietary charge is\r
+ * not supported byHardware IP block.\r
+ */\r
+ result = USBFS_BCD_PORT_UNKNOWN;\r
+ }\r
+ }\r
+ }\r
+\r
+ /* Restore CHGDET_CTRL. */\r
+ USBFS_CHGDET_CTRL_REG = 0u;\r
+\r
+ /*Revert registers back*/\r
+ USBFS_POWER_CTRL_REG = bkPwrCtrl;\r
+ USBFS_USBIO_CR1_REG |= (uint32) USBFS_USBIO_CR1_IOMODE;\r
+ USBFS_USB_CLK_EN_REG = ~USBFS_USB_CLK_CSR_CLK_EN;\r
+\r
+ return (result);\r
+ }\r
+#endif /* (USBFS_BATT_CHARG_DET_ENABLE) */\r
+\r
+\r
+#if (USBFS_LPM_ACTIVE)\r
+ /***************************************************************************\r
+ * Function Name: USBFS_Lpm_GetBeslValue\r
+ ************************************************************************//**\r
+ *\r
+ * This function returns the Best Effort Service Latency (BESL) value\r
+ * sent by the host as part of the LPM token transaction.\r
+ *\r
+ * \return\r
+ * 4-bit BESL value received in the LPM token packet from the host\r
+ *\r
+ *\r
+ ***************************************************************************/\r
+ uint32 USBFS_Lpm_GetBeslValue(void)\r
+ {\r
+ return (uint32) (USBFS_LPM_STAT_REG & USBFS_LPM_STAT_LPM_BESL_MASK);\r
+ }\r
+\r
+\r
+ /***************************************************************************\r
+ * Function Name: USBFS_Lpm_RemoteWakeUpAllowed\r
+ ************************************************************************//**\r
+ *\r
+ * This function returns the remote wakeup permission set for the device by\r
+ * the host as part of the LPM token transaction.\r
+ *\r
+ * \return\r
+ * 0 - remote wakeup not allowed, 1 - remote wakeup allowed\r
+ *\r
+ *\r
+ ***************************************************************************/\r
+ uint32 USBFS_Lpm_RemoteWakeUpAllowed(void)\r
+ {\r
+ return (uint32) (USBFS_LPM_STAT_REG & USBFS_LPM_STAT_LPM_REMOTE_WAKE);\r
+ }\r
+\r
+\r
+ /***************************************************************************\r
+ * Function Name: USBFS_Lpm_SetResponse\r
+ ************************************************************************//**\r
+ *\r
+ * This function configures the response in the handshake packet the device\r
+ * has to send when an LPM token packet is received.\r
+ *\r
+ * \param response\r
+ * type of response to return for an LPM token packet\r
+ * Allowed response values:\r
+ * - USBFS_LPM_REQ_ACK - next LPM request will be\r
+ * responded with ACK\r
+ * - USBFS_LPM_REQ_NACK - next LPM request will be\r
+ * responded with NACK\r
+ * - USBFS_LPM_REQ_NYET - next LPM request will be\r
+ * responded with NYET\r
+ *\r
+ ***************************************************************************/\r
+ void USBFS_Lpm_SetResponse(uint32 response)\r
+ {\r
+ uint32 lpmCtrl = USBFS_LPM_CTRL_REG & (uint32) ~USBFS_LPM_CTRL_ACK_NYET_MASK;\r
+\r
+ USBFS_LPM_CTRL_REG = lpmCtrl | ((uint32) response & USBFS_LPM_CTRL_ACK_NYET_MASK);\r
+ }\r
+\r
+\r
+ /***************************************************************************\r
+ * Function Name: USBFS_Lpm_GetResponse\r
+ ************************************************************************//**\r
+ *\r
+ * This function returns the currently configured response value that the\r
+ * device will send as part of the handshake packet when an LPM token\r
+ * packet is received.\r
+ *\r
+ * \return\r
+ * type of handshake response that will be returned by the device\r
+ * for an LPM token packet\r
+ * Possible response values:\r
+ * - USBFS_LPM_REQ_ACK - next LPM request will be responded\r
+ * with ACK\r
+ * - USBFS_LPM_REQ_NACK - next LPM request will be responded\r
+ * with NACK\r
+ * - USBFS_LPM_REQ_NYET - next LPM request will be responded\r
+ * with NYET\r
+ *\r
+ ***************************************************************************/\r
+ uint32 USBFS_Lpm_GetResponse(void)\r
+ {\r
+\r
+ return ((uint32) USBFS_LPM_CTRL_REG & (uint32)USBFS_LPM_CTRL_ACK_NYET_MASK);\r
+ }\r
+\r
+\r
+#endif /* (USBFS_LPM_ACTIVE) */\r
+\r
+\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: USBFS.h\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS.h\r
+* \version 3.10\r
*\r
-* Description:\r
-* Header File for the USBFS component. Contains prototypes and constant values.\r
+* \brief\r
+* This file provides function prototypes and constants for the USBFS component. \r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#if !defined(CY_USBFS_USBFS_H)\r
#define CY_USBFS_USBFS_H\r
\r
-#include "cytypes.h"\r
#include "cydevice_trm.h"\r
#include "cyfitter.h"\r
+#include "cytypes.h"\r
#include "CyLib.h"\r
\r
+\r
/* User supplied definitions. */\r
/* `#START USER_DEFINITIONS` Place your declaration here */\r
/* `#END` */\r
\r
-\r
-/***************************************\r
-* Conditional Compilation Parameters\r
-***************************************/\r
-\r
-/* Check to see if required defines such as CY_PSOC5LP are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5LP)\r
- #error Component USBFS_v2_80 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5LP) */\r
-\r
-\r
-/***************************************\r
-* Memory Type Definitions\r
-***************************************/\r
-\r
-/* Renamed Type Definitions for backward compatibility.\r
-* Should not be used in new designs.\r
-*/\r
-#define USBFS_CODE CYCODE\r
-#define USBFS_FAR CYFAR\r
-#if defined(__C51__) || defined(__CX51__)\r
- #define USBFS_DATA data\r
- #define USBFS_XDATA xdata\r
-#else\r
- #define USBFS_DATA\r
- #define USBFS_XDATA\r
-#endif /* __C51__ */\r
-#define USBFS_NULL NULL\r
-\r
-\r
/***************************************\r
* Enumerated Types and Parameters\r
***************************************/\r
\r
-#define USBFS__EP_MANUAL 0\r
-#define USBFS__EP_DMAMANUAL 1\r
-#define USBFS__EP_DMAAUTO 2\r
-\r
-#define USBFS__MA_STATIC 0\r
-#define USBFS__MA_DYNAMIC 1\r
+/* USB IP memory management options. */\r
+#define USBFS__EP_MANUAL (0u)\r
+#define USBFS__EP_DMAMANUAL (1u)\r
+#define USBFS__EP_DMAAUTO (2u)\r
\r
+/* USB IP memory allocation options. */\r
+#define USBFS__MA_STATIC (0u)\r
+#define USBFS__MA_DYNAMIC (1u)\r
\r
\r
/***************************************\r
* Initial Parameter Constants\r
***************************************/\r
\r
-#define USBFS_NUM_DEVICES (1u)\r
-#define USBFS_ENABLE_DESCRIPTOR_STRINGS \r
-#define USBFS_ENABLE_SN_STRING \r
-#define USBFS_ENABLE_STRINGS \r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE (65u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_IN_RPTS (1u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE (65u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_OUT_RPTS (1u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT (1u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE (65u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_IN_RPTS (1u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE (65u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_OUT_RPTS (1u)\r
-#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_COUNT (1u)\r
-#define USBFS_ENABLE_HID_CLASS \r
-#define USBFS_HID_RPT_1_SIZE_LSB (0x25u)\r
-#define USBFS_HID_RPT_1_SIZE_MSB (0x00u)\r
-#define USBFS_HID_RPT_2_SIZE_LSB (0x25u)\r
-#define USBFS_HID_RPT_2_SIZE_MSB (0x00u)\r
-#define USBFS_MAX_REPORTID_NUMBER (0u)\r
-\r
-#define USBFS_MON_VBUS (0u)\r
-#define USBFS_EXTERN_VBUS (0u)\r
-#define USBFS_EXTERN_VND (0u)\r
-#define USBFS_EXTERN_CLS (0u)\r
-#define USBFS_MAX_INTERFACES_NUMBER (2u)\r
-#define USBFS_EP0_ISR_REMOVE (0u)\r
-#define USBFS_EP1_ISR_REMOVE (0u)\r
-#define USBFS_EP2_ISR_REMOVE (0u)\r
-#define USBFS_EP3_ISR_REMOVE (0u)\r
-#define USBFS_EP4_ISR_REMOVE (0u)\r
-#define USBFS_EP5_ISR_REMOVE (1u)\r
-#define USBFS_EP6_ISR_REMOVE (1u)\r
-#define USBFS_EP7_ISR_REMOVE (1u)\r
-#define USBFS_EP8_ISR_REMOVE (1u)\r
-#define USBFS_EP_MM (0u)\r
-#define USBFS_EP_MA (0u)\r
-#define USBFS_EP_DMA_AUTO_OPT (0u)\r
-#define USBFS_DMA1_REMOVE (1u)\r
-#define USBFS_DMA2_REMOVE (1u)\r
-#define USBFS_DMA3_REMOVE (1u)\r
-#define USBFS_DMA4_REMOVE (1u)\r
-#define USBFS_DMA5_REMOVE (1u)\r
-#define USBFS_DMA6_REMOVE (1u)\r
-#define USBFS_DMA7_REMOVE (1u)\r
-#define USBFS_DMA8_REMOVE (1u)\r
-#define USBFS_SOF_ISR_REMOVE (0u)\r
-#define USBFS_ARB_ISR_REMOVE (0u)\r
-#define USBFS_DP_ISR_REMOVE (0u)\r
-#define USBFS_ENABLE_CDC_CLASS_API (1u)\r
-#define USBFS_ENABLE_MIDI_API (1u)\r
-#define USBFS_MIDI_EXT_MODE (0u)\r
+#define USBFS_NUM_DEVICES (1u)\r
+#define USBFS_ENABLE_MIDI_CLASS (0u)\r
+#define USBFS_ENABLE_MSC_CLASS (0u)\r
+#define USBFS_BOS_ENABLE (0u)\r
+#define USBFS_ENABLE_DESCRIPTOR_STRINGS \r
+#define USBFS_ENABLE_SN_STRING \r
+#define USBFS_ENABLE_STRINGS \r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE (65u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_IN_RPTS (1u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE (65u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_OUT_RPTS (1u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT (1u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE (65u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_IN_RPTS (1u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE (65u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_OUT_RPTS (1u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_COUNT (1u)\r
+#define USBFS_ENABLE_HID_CLASS \r
+#define USBFS_HID_RPT_1_SIZE_LSB (0x25u)\r
+#define USBFS_HID_RPT_1_SIZE_MSB (0x00u)\r
+#define USBFS_HID_RPT_2_SIZE_LSB (0x25u)\r
+#define USBFS_HID_RPT_2_SIZE_MSB (0x00u)\r
+#define USBFS_MAX_REPORTID_NUMBER (0u)\r
+\r
+#define USBFS_MON_VBUS (0u)\r
+#define USBFS_EXTERN_VBUS (0u)\r
+#define USBFS_POWER_PAD_VBUS (0u)\r
+#define USBFS_EXTERN_VND (0u)\r
+#define USBFS_EXTERN_CLS (0u)\r
+#define USBFS_MAX_INTERFACES_NUMBER (2u)\r
+#define USBFS_EP_MM (0u)\r
+#define USBFS_EP_MA (0u)\r
+#define USBFS_ENABLE_BATT_CHARG_DET (0u)\r
+#define USBFS_GEN_16BITS_EP_ACCESS (0u)\r
+\r
+/* Enable Class APIs: MIDI, CDC, MSC. */ \r
+#define USBFS_ENABLE_CDC_CLASS_API (0u != (1u))\r
+\r
+/* General parameters */\r
+#define USBFS_EP_ALLOC_STATIC (USBFS_EP_MA == USBFS__MA_STATIC)\r
+#define USBFS_EP_ALLOC_DYNAMIC (USBFS_EP_MA == USBFS__MA_DYNAMIC)\r
+#define USBFS_EP_MANAGEMENT_MANUAL (USBFS_EP_MM == USBFS__EP_MANUAL)\r
+#define USBFS_EP_MANAGEMENT_DMA (USBFS_EP_MM != USBFS__EP_MANUAL)\r
+#define USBFS_EP_MANAGEMENT_DMA_MANUAL (USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
+#define USBFS_EP_MANAGEMENT_DMA_AUTO (USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
+#define USBFS_BATT_CHARG_DET_ENABLE (CY_PSOC4 && (0u != USBFS_ENABLE_BATT_CHARG_DET))\r
+#define USBFS_16BITS_EP_ACCESS_ENABLE (CY_PSOC4 && (0u != USBFS_GEN_16BITS_EP_ACCESS))\r
+#define USBFS_VBUS_MONITORING_ENABLE (0u != USBFS_MON_VBUS)\r
+#define USBFS_VBUS_MONITORING_INTERNAL (0u == USBFS_EXTERN_VBUS)\r
+#define USBFS_VBUS_POWER_PAD_ENABLE (0u != USBFS_POWER_PAD_VBUS)\r
+\r
+/* Control endpoints availability */\r
+#define USBFS_SOF_ISR_REMOVE (0u)\r
+#define USBFS_BUS_RESET_ISR_REMOVE (0u)\r
+#define USBFS_EP0_ISR_REMOVE (0u)\r
+#define USBFS_ARB_ISR_REMOVE (0u)\r
+#define USBFS_DP_ISR_REMOVE (0u)\r
+#define USBFS_LPM_REMOVE (1u)\r
+#define USBFS_SOF_ISR_ACTIVE ((0u == USBFS_SOF_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_BUS_RESET_ISR_ACTIVE ((0u == USBFS_BUS_RESET_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_EP0_ISR_ACTIVE ((0u == USBFS_EP0_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_ARB_ISR_ACTIVE ((0u == USBFS_ARB_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_DP_ISR_ACTIVE ((0u == USBFS_DP_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_LPM_ACTIVE ((CY_PSOC4 && (0u == USBFS_LPM_REMOVE)) ? 1u: 0u)\r
+\r
+/* Data endpoints availability */\r
+#define USBFS_EP1_ISR_REMOVE (0u)\r
+#define USBFS_EP2_ISR_REMOVE (0u)\r
+#define USBFS_EP3_ISR_REMOVE (0u)\r
+#define USBFS_EP4_ISR_REMOVE (0u)\r
+#define USBFS_EP5_ISR_REMOVE (1u)\r
+#define USBFS_EP6_ISR_REMOVE (1u)\r
+#define USBFS_EP7_ISR_REMOVE (1u)\r
+#define USBFS_EP8_ISR_REMOVE (1u)\r
+#define USBFS_EP1_ISR_ACTIVE ((0u == USBFS_EP1_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_EP2_ISR_ACTIVE ((0u == USBFS_EP2_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_EP3_ISR_ACTIVE ((0u == USBFS_EP3_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_EP4_ISR_ACTIVE ((0u == USBFS_EP4_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_EP5_ISR_ACTIVE ((0u == USBFS_EP5_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_EP6_ISR_ACTIVE ((0u == USBFS_EP6_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_EP7_ISR_ACTIVE ((0u == USBFS_EP7_ISR_REMOVE) ? 1u: 0u)\r
+#define USBFS_EP8_ISR_ACTIVE ((0u == USBFS_EP8_ISR_REMOVE) ? 1u: 0u)\r
+\r
+#define USBFS_EP_DMA_AUTO_OPT ((CY_PSOC4) ? (1u) : (0u))\r
+#define USBFS_DMA1_REMOVE (1u)\r
+#define USBFS_DMA2_REMOVE (1u)\r
+#define USBFS_DMA3_REMOVE (1u)\r
+#define USBFS_DMA4_REMOVE (1u)\r
+#define USBFS_DMA5_REMOVE (1u)\r
+#define USBFS_DMA6_REMOVE (1u)\r
+#define USBFS_DMA7_REMOVE (1u)\r
+#define USBFS_DMA8_REMOVE (1u)\r
+#define USBFS_DMA1_ACTIVE ((0u == USBFS_DMA1_REMOVE) ? 1u: 0u)\r
+#define USBFS_DMA2_ACTIVE ((0u == USBFS_DMA2_REMOVE) ? 1u: 0u)\r
+#define USBFS_DMA3_ACTIVE ((0u == USBFS_DMA3_REMOVE) ? 1u: 0u)\r
+#define USBFS_DMA4_ACTIVE ((0u == USBFS_DMA4_REMOVE) ? 1u: 0u)\r
+#define USBFS_DMA5_ACTIVE ((0u == USBFS_DMA5_REMOVE) ? 1u: 0u)\r
+#define USBFS_DMA6_ACTIVE ((0u == USBFS_DMA6_REMOVE) ? 1u: 0u)\r
+#define USBFS_DMA7_ACTIVE ((0u == USBFS_DMA7_REMOVE) ? 1u: 0u)\r
+#define USBFS_DMA8_ACTIVE ((0u == USBFS_DMA8_REMOVE) ? 1u: 0u)\r
\r
\r
/***************************************\r
-* Data Struct Definition\r
+* Data Structures Definition\r
***************************************/\r
\r
typedef struct\r
T_USBFS_XFER_STATUS_BLOCK *pStatusBlock;\r
} T_USBFS_TD;\r
\r
-\r
typedef struct\r
{\r
uint8 c;\r
{\r
uint8 enableState;\r
uint8 mode;\r
+#if (CY_PSOC4)\r
+ uint8 intrSeiMask;\r
+#endif /* (CY_PSOC4) */\r
} USBFS_BACKUP_STRUCT;\r
\r
+/* Number of endpoint 0 data registers. */\r
+#define USBFS_EP0_DR_MAPPED_REG_CNT (8u)\r
\r
-/* Renamed structure fields for backward compatibility.\r
-* Should not be used in new designs.\r
-*/\r
-#define wBuffOffset buffOffset\r
-#define wBufferSize bufferSize\r
-#define bStatus status\r
-#define wLength length\r
-#define wCount count\r
+/* Structure to access data registers for EP0. */\r
+typedef struct\r
+{\r
+ uint8 epData[USBFS_EP0_DR_MAPPED_REG_CNT];\r
+} USBFS_ep0_data_struct;\r
\r
-/* Renamed global variable for backward compatibility.\r
-* Should not be used in new designs.\r
-*/\r
-#define CurrentTD USBFS_currentTD\r
+/* Number of SIE endpoint registers group. */\r
+#define USBFS_SIE_EP_REG_SIZE (USBFS_USB__SIE_EP1_CR0 - \\r
+ USBFS_USB__SIE_EP1_CNT0)\r
+\r
+/* Size of gap between SIE endpoint registers groups. */\r
+#define USBFS_SIE_GAP_CNT (((USBFS_USB__SIE_EP2_CNT0 - \\r
+ (USBFS_USB__SIE_EP1_CNT0 + \\r
+ USBFS_SIE_EP_REG_SIZE)) / sizeof(reg8)) - 1u)\r
+\r
+/* Structure to access to SIE registers for endpoint. */\r
+typedef struct\r
+{\r
+ uint8 epCnt0;\r
+ uint8 epCnt1;\r
+ uint8 epCr0;\r
+ uint8 gap[USBFS_SIE_GAP_CNT];\r
+} USBFS_sie_ep_struct;\r
+\r
+/* Number of ARB endpoint registers group. */\r
+#define USBFS_ARB_EP_REG_SIZE (USBFS_USB__ARB_RW1_DR - \\r
+ USBFS_USB__ARB_EP1_CFG)\r
+\r
+/* Size of gap between ARB endpoint registers groups. */\r
+#define USBFS_ARB_GAP_CNT (((USBFS_USB__ARB_EP2_CFG - \\r
+ (USBFS_USB__ARB_EP1_CFG + \\r
+ USBFS_ARB_EP_REG_SIZE)) / sizeof(reg8)) - 1u)\r
+\r
+/* Structure to access to ARB registers for endpoint. */\r
+typedef struct\r
+{\r
+ uint8 epCfg;\r
+ uint8 epIntEn;\r
+ uint8 epSr;\r
+ uint8 reserved;\r
+ uint8 rwWa;\r
+ uint8 rwWaMsb;\r
+ uint8 rwRa;\r
+ uint8 rwRaMsb;\r
+ uint8 rwDr;\r
+ uint8 gap[USBFS_ARB_GAP_CNT];\r
+} USBFS_arb_ep_struct;\r
+\r
+#if (CY_PSOC4)\r
+ /* Number of ARB endpoint registers group (16-bits access). */\r
+ #define USBFS_ARB_EP_REG16_SIZE (USBFS_USB__ARB_RW1_DR16 - \\r
+ USBFS_USB__ARB_RW1_WA16)\r
+\r
+ /* Size of gap between ARB endpoint registers groups (16-bits access). */\r
+ #define USBFS_ARB_EP_REG16_GAP_CNT (((USBFS_USB__ARB_RW2_WA16 - \\r
+ (USBFS_USB__ARB_RW1_WA16 + \\r
+ USBFS_ARB_EP_REG16_SIZE)) / sizeof(reg8)) - 1u)\r
+\r
+ /* Structure to access to ARB registers for endpoint (16-bits access). */\r
+ typedef struct\r
+ {\r
+ uint8 rwWa16;\r
+ uint8 reserved0;\r
+ uint8 rwRa16;\r
+ uint8 reserved1;\r
+ uint8 rwDr16;\r
+ uint8 gap[USBFS_ARB_EP_REG16_GAP_CNT];\r
+ } USBFS_arb_ep_reg16_struct;\r
+#endif /* (CY_PSOC4) */\r
+\r
+/* Number of endpoint (takes to account that endpoints numbers are 1-8). */\r
+#define USBFS_NUMBER_EP (9u)\r
+\r
+/* Consoled SIE register groups for endpoints 1-8. */\r
+typedef struct\r
+{\r
+ USBFS_sie_ep_struct sieEp[USBFS_NUMBER_EP];\r
+} USBFS_sie_eps_struct;\r
+\r
+/* Consolidate ARB register groups for endpoints 1-8.*/\r
+typedef struct\r
+{\r
+ USBFS_arb_ep_struct arbEp[USBFS_NUMBER_EP];\r
+} USBFS_arb_eps_struct;\r
+\r
+#if (CY_PSOC4)\r
+ /* Consolidate ARB register groups for endpoints 1-8 (16-bits access). */\r
+ typedef struct\r
+ {\r
+ USBFS_arb_ep_reg16_struct arbEp[USBFS_NUMBER_EP];\r
+ } USBFS_arb_eps_reg16_struct;\r
+#endif /* (CY_PSOC4) */\r
\r
\r
/***************************************\r
* Function Prototypes\r
***************************************/\r
-\r
-void USBFS_Start(uint8 device, uint8 mode) ;\r
-void USBFS_Init(void) ;\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
void USBFS_InitComponent(uint8 device, uint8 mode) ;\r
-void USBFS_Stop(void) ;\r
-uint8 USBFS_CheckActivity(void) ;\r
-uint8 USBFS_GetConfiguration(void) ;\r
-uint8 USBFS_IsConfigurationChanged(void) ;\r
-uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber)\r
- ;\r
-uint8 USBFS_GetEPState(uint8 epNumber) ;\r
-uint16 USBFS_GetEPCount(uint8 epNumber) ;\r
+void USBFS_Start(uint8 device, uint8 mode) ;\r
+void USBFS_Init(void) ;\r
+void USBFS_Stop(void) ;\r
+uint8 USBFS_GetConfiguration(void) ;\r
+uint8 USBFS_IsConfigurationChanged(void) ;\r
+uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) ;\r
+uint8 USBFS_GetEPState(uint8 epNumber) ;\r
+uint16 USBFS_GetEPCount(uint8 epNumber) ;\r
void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)\r
- ;\r
+ ;\r
uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)\r
- ;\r
-void USBFS_EnableOutEP(uint8 epNumber) ;\r
-void USBFS_DisableOutEP(uint8 epNumber) ;\r
-void USBFS_Force(uint8 bState) ;\r
-uint8 USBFS_GetEPAckState(uint8 epNumber) ;\r
-void USBFS_SetPowerStatus(uint8 powerStatus) ;\r
-uint8 USBFS_RWUEnabled(void) ;\r
-void USBFS_TerminateEP(uint8 ep) ;\r
-\r
-void USBFS_Suspend(void) ;\r
-void USBFS_Resume(void) ;\r
+ ;\r
+void USBFS_EnableOutEP(uint8 epNumber) ;\r
+void USBFS_DisableOutEP(uint8 epNumber) ;\r
+void USBFS_Force(uint8 bState) ;\r
+uint8 USBFS_GetEPAckState(uint8 epNumber) ;\r
+void USBFS_SetPowerStatus(uint8 powerStatus) ;\r
+void USBFS_TerminateEP(uint8 epNumber) ;\r
+\r
+uint8 USBFS_GetDeviceAddress(void) ;\r
+\r
+void USBFS_EnableSofInt(void) ;\r
+void USBFS_DisableSofInt(void) ;\r
+\r
\r
#if defined(USBFS_ENABLE_FWSN_STRING)\r
void USBFS_SerialNumString(uint8 snString[]) ;\r
#endif /* USBFS_ENABLE_FWSN_STRING */\r
-#if (USBFS_MON_VBUS == 1u)\r
+\r
+#if (USBFS_VBUS_MONITORING_ENABLE)\r
uint8 USBFS_VBusPresent(void) ;\r
-#endif /* USBFS_MON_VBUS */\r
+#endif /* (USBFS_VBUS_MONITORING_ENABLE) */\r
+\r
+#if (USBFS_16BITS_EP_ACCESS_ENABLE)\r
+ /* PSoC4 specific functions for 16-bit data register access. */\r
+ void USBFS_LoadInEP16 (uint8 epNumber, const uint8 pData[], uint16 length);\r
+ uint16 USBFS_ReadOutEP16(uint8 epNumber, uint8 pData[], uint16 length);\r
+#endif /* (USBFS_16BITS_EP_ACCESS_ENABLE) */\r
+\r
+#if (USBFS_BATT_CHARG_DET_ENABLE)\r
+ uint8 USBFS_Bcd_DetectPortType(void);\r
+#endif /* (USBFS_BATT_CHARG_DET_ENABLE) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+ void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData) ; \r
+ void USBFS_Stop_DMA(uint8 epNumber) ;\r
+/** @} general */ \r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+/**\r
+* \addtogroup group_power\r
+* @{\r
+*/\r
+uint8 USBFS_CheckActivity(void) ;\r
+void USBFS_Suspend(void) ;\r
+void USBFS_Resume(void) ;\r
+uint8 USBFS_RWUEnabled(void) ;\r
+\r
+#if (USBFS_LPM_ACTIVE)\r
+ uint32 USBFS_Lpm_GetBeslValue(void);\r
+ uint32 USBFS_Lpm_RemoteWakeUpAllowed(void);\r
+ void USBFS_Lpm_SetResponse(uint32 response);\r
+ uint32 USBFS_Lpm_GetResponse(void);\r
+#endif /* (USBFS_LPM_ACTIVE) */\r
+\r
+/** @} power */\r
+\r
\r
#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \\r
(CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))\r
-\r
- void USBFS_CyBtldrCommStart(void) ;\r
- void USBFS_CyBtldrCommStop(void) ;\r
- void USBFS_CyBtldrCommReset(void) ;\r
+/**\r
+* \addtogroup group_bootloader\r
+* @{\r
+*/\r
+ void USBFS_CyBtldrCommStart(void) ;\r
+ void USBFS_CyBtldrCommStop(void) ;\r
+ void USBFS_CyBtldrCommReset(void) ;\r
cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
;\r
cystatus USBFS_CyBtldrCommRead (uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
;\r
+/** @} bootloader */\r
\r
- #define USBFS_BTLDR_OUT_EP (0x01u)\r
- #define USBFS_BTLDR_IN_EP (0x02u)\r
+ #define USBFS_BTLDR_OUT_EP (0x01u)\r
+ #define USBFS_BTLDR_IN_EP (0x02u)\r
\r
- #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* EP 1 OUT */\r
- #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* EP 2 IN */\r
+ #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* Endpoint 1 (OUT) buffer size. */\r
+ #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* Endpoint 2 (IN) buffer size. */\r
#define USBFS_BTLDR_MAX_PACKET_SIZE USBFS_BTLDR_SIZEOF_WRITE_BUFFER\r
\r
#define USBFS_BTLDR_WAIT_1_MS (1u) /* Time Out quantity equal 1mS */\r
\r
- /* These defines active if used USBFS interface as an\r
- * IO Component for bootloading. When Custom_Interface selected\r
- * in Bootloder configuration as the IO Component, user must\r
- * provide these functions.\r
- */\r
+ /* Map-specific USB bootloader communication functions to common bootloader functions */\r
#if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS)\r
#define CyBtldrCommStart USBFS_CyBtldrCommStart\r
#define CyBtldrCommStop USBFS_CyBtldrCommStop\r
#define CyBtldrCommReset USBFS_CyBtldrCommReset\r
#define CyBtldrCommWrite USBFS_CyBtldrCommWrite\r
#define CyBtldrCommRead USBFS_CyBtldrCommRead\r
- #endif /*End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */\r
-\r
-#endif /* CYDEV_BOOTLOADER_IO_COMP */\r
-\r
-#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)\r
- ;\r
- void USBFS_Stop_DMA(uint8 epNumber) ;\r
-#endif /* USBFS_EP_MM != USBFS__EP_MANUAL) */\r
-\r
-#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)\r
- void USBFS_MIDI_EP_Init(void) ;\r
-\r
- #if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
- void USBFS_MIDI_IN_Service(void) ;\r
- uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable)\r
- ;\r
- #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */\r
-\r
- #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
- void USBFS_MIDI_OUT_EP_Service(void) ;\r
- #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */\r
-\r
-#endif /* USBFS_ENABLE_MIDI_API != 0u */\r
-\r
-/* Renamed Functions for backward compatibility.\r
-* Should not be used in new designs.\r
-*/\r
-\r
-#define USBFS_bCheckActivity USBFS_CheckActivity\r
-#define USBFS_bGetConfiguration USBFS_GetConfiguration\r
-#define USBFS_bGetInterfaceSetting USBFS_GetInterfaceSetting\r
-#define USBFS_bGetEPState USBFS_GetEPState\r
-#define USBFS_wGetEPCount USBFS_GetEPCount\r
-#define USBFS_bGetEPAckState USBFS_GetEPAckState\r
-#define USBFS_bRWUEnabled USBFS_RWUEnabled\r
-#define USBFS_bVBusPresent USBFS_VBusPresent\r
-\r
-#define USBFS_bConfiguration USBFS_configuration\r
-#define USBFS_bInterfaceSetting USBFS_interfaceSetting\r
-#define USBFS_bDeviceAddress USBFS_deviceAddress\r
-#define USBFS_bDeviceStatus USBFS_deviceStatus\r
-#define USBFS_bDevice USBFS_device\r
-#define USBFS_bTransferState USBFS_transferState\r
-#define USBFS_bLastPacketSize USBFS_lastPacketSize\r
-\r
-#define USBFS_LoadEP USBFS_LoadInEP\r
-#define USBFS_LoadInISOCEP USBFS_LoadInEP\r
-#define USBFS_EnableOutISOCEP USBFS_EnableOutEP\r
-\r
-#define USBFS_SetVector CyIntSetVector\r
-#define USBFS_SetPriority CyIntSetPriority\r
-#define USBFS_EnableInt CyIntEnable\r
+ #endif /* (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) */\r
+#endif /* CYDEV_BOOTLOADER_IO_COMP */\r
\r
\r
/***************************************\r
\r
#define USBFS_3V_OPERATION (0x00u)\r
#define USBFS_5V_OPERATION (0x01u)\r
-#define USBFS_DWR_VDDD_OPERATION (0x02u)\r
+#define USBFS_DWR_POWER_OPERATION (0x02u)\r
\r
#define USBFS_MODE_DISABLE (0x00u)\r
#define USBFS_MODE_NAK_IN_OUT (0x01u)\r
#define USBFS_RQST_RCPT_EP (0x02u)\r
#define USBFS_RQST_RCPT_OTHER (0x03u)\r
\r
+#if (USBFS_LPM_ACTIVE)\r
+ #define USBFS_LPM_REQ_ACK (0x01u << USBFS_LPM_CTRL_LPM_ACK_RESP_POS)\r
+ #define USBFS_LPM_REQ_NACK (0x00u)\r
+ #define USBFS_LPM_REQ_NYET (0x01u << USBFS_LPM_CTRL_NYET_EN_POS)\r
+#endif /*(USBFS_LPM_ACTIVE)*/\r
+\r
/* USB Class Codes */\r
#define USBFS_CLASS_DEVICE (0x00u) /* Use class code info from Interface Descriptors */\r
#define USBFS_CLASS_AUDIO (0x01u) /* Audio device */\r
#define USBFS_CLASS_SMART_CARD (0x0Bu) /* Smart Card device */\r
#define USBFS_CLASS_CSD (0x0Du) /* Content Security device */\r
#define USBFS_CLASS_VIDEO (0x0Eu) /* Video device */\r
-#define USBFS_CLASS_PHD (0x0Fu) /* Personal Healthcare device */\r
+#define USBFS_CLASS_PHD (0x0Fu) /* Personal Health care device */\r
#define USBFS_CLASS_WIRELESSD (0xDCu) /* Wireless Controller */\r
#define USBFS_CLASS_MIS (0xE0u) /* Miscellaneous */\r
#define USBFS_CLASS_APP (0xEFu) /* Application Specific */\r
#define USBFS_CLASS_VENDOR (0xFFu) /* Vendor specific */\r
\r
-\r
/* Standard Request Types (Table 9-4) */\r
#define USBFS_GET_STATUS (0x00u)\r
#define USBFS_CLEAR_FEATURE (0x01u)\r
#define USBFS_DESCR_DEVICE_QUALIFIER (6u)\r
#define USBFS_DESCR_OTHER_SPEED (7u)\r
#define USBFS_DESCR_INTERFACE_POWER (8u)\r
-\r
+#if (USBFS_BOS_ENABLE)\r
+ #define USBFS_DESCR_BOS (15u)\r
+#endif /* (USBFS_BOS_ENABLE) */\r
/* Device Descriptor Defines */\r
#define USBFS_DEVICE_DESCR_LENGTH (18u)\r
#define USBFS_DEVICE_DESCR_SN_SHIFT (16u)\r
#define USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED (0x40u)\r
#define USBFS_CONFIG_DESCR_ATTRIB_RWU_EN (0x20u)\r
\r
+#if (USBFS_BOS_ENABLE)\r
+ /* Config Descriptor BOS */\r
+ #define USBFS_BOS_DESCR_LENGTH (0u)\r
+ #define USBFS_BOS_DESCR_TYPE (1u)\r
+ #define USBFS_BOS_DESCR_TOTAL_LENGTH_LOW (2u)\r
+ #define USBFS_BOS_DESCR_TOTAL_LENGTH_HI (3u)\r
+ #define USBFS_BOS_DESCR_NUM_DEV_CAPS (4u)\r
+#endif /* (USBFS_BOS_ENABLE) */\r
+\r
/* Feature Selectors (Table 9-6) */\r
#define USBFS_DEVICE_REMOTE_WAKEUP (0x01u)\r
#define USBFS_ENDPOINT_HALT (0x00u)\r
#define USBFS_EP_USAGE_TYPE_RESERVED (0x30u)\r
#define USBFS_EP_USAGE_TYPE_MASK (0x30u)\r
\r
-/* point Status defines */\r
+/* Point Status defines */\r
#define USBFS_EP_STATUS_LENGTH (0x02u)\r
\r
-/* point Device defines */\r
+/* Point Device defines */\r
#define USBFS_DEVICE_STATUS_LENGTH (0x02u)\r
\r
#define USBFS_STATUS_LENGTH_MAX \\r
- ( (USBFS_EP_STATUS_LENGTH > USBFS_DEVICE_STATUS_LENGTH) ? \\r
- USBFS_EP_STATUS_LENGTH : USBFS_DEVICE_STATUS_LENGTH )\r
+ ((USBFS_EP_STATUS_LENGTH > USBFS_DEVICE_STATUS_LENGTH) ? \\r
+ USBFS_EP_STATUS_LENGTH : USBFS_DEVICE_STATUS_LENGTH)\r
+\r
/* Transfer Completion Notification */\r
#define USBFS_XFER_IDLE (0x00u)\r
#define USBFS_XFER_STATUS_ACK (0x01u)\r
#define USBFS_MSOS_DESCRIPTOR_LENGTH (18u)\r
#define USBFS_MSOS_CONF_DESCR_LENGTH (40u)\r
\r
-#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
- /* DMA manual mode defines */\r
- #define USBFS_DMA_BYTES_PER_BURST (0u)\r
- #define USBFS_DMA_REQUEST_PER_BURST (0u)\r
-#endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
-#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- /* DMA automatic mode defines */\r
- #define USBFS_DMA_BYTES_PER_BURST (32u)\r
- #define USBFS_DMA_BYTES_REPEAT (2u)\r
- /* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */\r
- #define USBFS_DMA_BUF_SIZE (0x55u)\r
- #define USBFS_DMA_REQUEST_PER_BURST (1u)\r
-\r
- #if(USBFS_DMA1_REMOVE == 0u)\r
- #define USBFS_ep1_TD_TERMOUT_EN USBFS_ep1__TD_TERMOUT_EN\r
- #else\r
- #define USBFS_ep1_TD_TERMOUT_EN (0u)\r
- #endif /* USBFS_DMA1_REMOVE == 0u */\r
- #if(USBFS_DMA2_REMOVE == 0u)\r
- #define USBFS_ep2_TD_TERMOUT_EN USBFS_ep2__TD_TERMOUT_EN\r
- #else\r
- #define USBFS_ep2_TD_TERMOUT_EN (0u)\r
- #endif /* USBFS_DMA2_REMOVE == 0u */\r
- #if(USBFS_DMA3_REMOVE == 0u)\r
- #define USBFS_ep3_TD_TERMOUT_EN USBFS_ep3__TD_TERMOUT_EN\r
- #else\r
- #define USBFS_ep3_TD_TERMOUT_EN (0u)\r
- #endif /* USBFS_DMA3_REMOVE == 0u */\r
- #if(USBFS_DMA4_REMOVE == 0u)\r
- #define USBFS_ep4_TD_TERMOUT_EN USBFS_ep4__TD_TERMOUT_EN\r
- #else\r
- #define USBFS_ep4_TD_TERMOUT_EN (0u)\r
- #endif /* USBFS_DMA4_REMOVE == 0u */\r
- #if(USBFS_DMA5_REMOVE == 0u)\r
- #define USBFS_ep5_TD_TERMOUT_EN USBFS_ep5__TD_TERMOUT_EN\r
- #else\r
- #define USBFS_ep5_TD_TERMOUT_EN (0u)\r
- #endif /* USBFS_DMA5_REMOVE == 0u */\r
- #if(USBFS_DMA6_REMOVE == 0u)\r
- #define USBFS_ep6_TD_TERMOUT_EN USBFS_ep6__TD_TERMOUT_EN\r
- #else\r
- #define USBFS_ep6_TD_TERMOUT_EN (0u)\r
- #endif /* USBFS_DMA6_REMOVE == 0u */\r
- #if(USBFS_DMA7_REMOVE == 0u)\r
- #define USBFS_ep7_TD_TERMOUT_EN USBFS_ep7__TD_TERMOUT_EN\r
- #else\r
- #define USBFS_ep7_TD_TERMOUT_EN (0u)\r
- #endif /* USBFS_DMA7_REMOVE == 0u */\r
- #if(USBFS_DMA8_REMOVE == 0u)\r
- #define USBFS_ep8_TD_TERMOUT_EN USBFS_ep8__TD_TERMOUT_EN\r
- #else\r
- #define USBFS_ep8_TD_TERMOUT_EN (0u)\r
- #endif /* USBFS_DMA8_REMOVE == 0u */\r
-\r
- #define USBFS_EP17_SR_MASK (0x7fu)\r
- #define USBFS_EP8_SR_MASK (0x03u)\r
-\r
-#endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+/* Return values */\r
+#define USBFS_BCD_PORT_SDP (1u) /* Standard downstream port detected */\r
+#define USBFS_BCD_PORT_CDP (2u) /* Charging downstream port detected */\r
+#define USBFS_BCD_PORT_DCP (3u) /* Dedicated charging port detected */\r
+#define USBFS_BCD_PORT_UNKNOWN (0u) /* Unable to detect charging port */\r
+#define USBFS_BCD_PORT_ERR (4u) /* Error condition in detection process*/\r
+\r
+\r
+/* Timeouts for BCD */\r
+#define USBFS_BCD_TIMEOUT (400u) /* Copied from PBK#163 TIMEOUT (300 ms) */\r
+#define USBFS_BCD_TDCD_DBNC (10u) /*BCD v1.2: DCD debounce time 10 ms*/\r
+#define USBFS_BCD_PRIMARY_WAIT (40u) /* Copied from PBK#163 TIMEOUT (40 ms) */\r
+#define USBFS_BCD_SECONDARY_WAIT (47u) /* Copied from PBK#163 TIMEOUT (40 ms) */\r
+#define USBFS_BCD_SUSPEND_DISABLE_WAIT (2u) /* Copied from PBK#163 TIMEOUT (2 us) */\r
+\r
+/* Wait cycles required before clearing SUSPEND_DEL in POWER_CTRL: 2us */\r
+#define USBFS_WAIT_SUSPEND_DEL_DISABLE (2u)\r
+\r
+/* Wait cycles required for USB regulator stabilization after it is enabled : 50ns */\r
+#define USBFS_WAIT_VREF_STABILITY (0u)\r
+\r
+#if (CY_PSOC3 || CY_PSOC5LP)\r
+/* Wait cycles required for USB reference restore: 40us */\r
+#define USBFS_WAIT_VREF_RESTORE (40u)\r
+\r
+/* Wait cycles required for stabilization after register is written : 50ns */\r
+#define USBFS_WAIT_REG_STABILITY_50NS (0u)\r
+#define USBFS_WAIT_REG_STABILITY_1US (1u)\r
+\r
+/* Wait cycles required after CR0 register write: 1 cycle */\r
+#define USBFS_WAIT_CR0_REG_STABILITY (1u)\r
+\r
+/* Wait cycles required after PD_PULLUP_N bit is set in PM_USB_CR0: 2us */\r
+#define USBFS_WAIT_PD_PULLUP_N_ENABLE (2u)\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+#if (CY_PSOC4)\r
+ #if (USBFS_EP_MANAGEMENT_DMA)\r
+ #define USBFS_DMA_DESCR0 (0u)\r
+ #define USBFS_DMA_DESCR1 (1u)\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* BUF_SIZE-BYTES_PER_BURST examples: 0x55 - 32 bytes, 0x44 - 16 bytes, 0x33 - 8 bytes, etc. */\r
+ #define USBFS_DMA_BUF_SIZE (0x55u)\r
+ #define USBFS_DMA_BYTES_PER_BURST (32u)\r
+ #define USBFS_DMA_HALFWORDS_PER_BURST (16u)\r
+ #define USBFS_DMA_BURST_BYTES_MASK (USBFS_DMA_BYTES_PER_BURST - 1u)\r
+\r
+ #define USBFS_DMA_DESCR0_MASK (0x00u)\r
+ #define USBFS_DMA_DESCR1_MASK (0x80u)\r
+ #define USBFS_DMA_DESCR_REVERT (0x40u)\r
+ #define USBFS_DMA_DESCR_16BITS (0x20u)\r
+ #define USBFS_DMA_DESCR_SHIFT (7u)\r
+\r
+ #define USBFS_DMA_GET_DESCR_NUM(desrc)\r
+ #define USBFS_DMA_GET_BURST_CNT(dmaBurstCnt) \\r
+ (((dmaBurstCnt) > 2u)? ((dmaBurstCnt) - 2u) : 0u)\r
+\r
+ #define USBFS_DMA_GET_MAX_ELEM_PER_BURST(dmaLastBurstEl) \\r
+ ((0u != ((dmaLastBurstEl) & USBFS_DMA_DESCR_16BITS)) ? \\r
+ (USBFS_DMA_HALFWORDS_PER_BURST - 1u) : (USBFS_DMA_BYTES_PER_BURST - 1u))\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+#else\r
+ #if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ #define USBFS_DMA_BYTES_PER_BURST (0u)\r
+ #define USBFS_DMA_REQUEST_PER_BURST (0u)\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ #define USBFS_DMA_BYTES_PER_BURST (32u)\r
+ #define USBFS_DMA_BYTES_REPEAT (2u)\r
+\r
+ /* BUF_SIZE-BYTES_PER_BURST examples: 0x55 - 32 bytes, 0x44 - 16 bytes, 0x33 - 8 bytes, etc. */\r
+ #define USBFS_DMA_BUF_SIZE (0x55u)\r
+ #define USBFS_DMA_REQUEST_PER_BURST (1u)\r
+\r
+ #define USBFS_EP17_SR_MASK (0x7Fu)\r
+ #define USBFS_EP8_SR_MASK (0x03u)\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+#endif /* (CY_PSOC4) */\r
\r
/* DIE ID string descriptor defines */\r
#if defined(USBFS_ENABLE_IDSN_STRING)\r
- #define USBFS_IDSN_DESCR_LENGTH (0x22u)\r
-#endif /* USBFS_ENABLE_IDSN_STRING */\r
+ #define USBFS_IDSN_DESCR_LENGTH (0x22u)\r
+#endif /* (USBFS_ENABLE_IDSN_STRING) */\r
\r
\r
/***************************************\r
-* External data references\r
+* Vars with External Linkage\r
***************************************/\r
\r
+/**\r
+* \addtogroup group_globals\r
+* @{\r
+*/\r
extern uint8 USBFS_initVar;\r
extern volatile uint8 USBFS_device;\r
extern volatile uint8 USBFS_transferState;\r
extern volatile uint8 USBFS_configuration;\r
extern volatile uint8 USBFS_configurationChanged;\r
extern volatile uint8 USBFS_deviceStatus;\r
+/** @} globals */\r
\r
+/**\r
+* \addtogroup group_hid\r
+* @{\r
+*/\r
/* HID Variables */\r
#if defined(USBFS_ENABLE_HID_CLASS)\r
- extern volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER];\r
- extern volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER];\r
+ extern volatile uint8 USBFS_hidProtocol [USBFS_MAX_INTERFACES_NUMBER]; \r
+ extern volatile uint8 USBFS_hidIdleRate [USBFS_MAX_INTERFACES_NUMBER];\r
extern volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER];\r
-#endif /* USBFS_ENABLE_HID_CLASS */\r
+#endif /* (USBFS_ENABLE_HID_CLASS) */\r
+/** @} hid */\r
\r
\r
/***************************************\r
* Registers\r
***************************************/\r
\r
-#define USBFS_ARB_CFG_PTR ( (reg8 *) USBFS_USB__ARB_CFG)\r
-#define USBFS_ARB_CFG_REG (* (reg8 *) USBFS_USB__ARB_CFG)\r
+/* Common registers for all PSoCs: 3/4/5LP */\r
+#define USBFS_ARB_CFG_PTR ( (reg8 *) USBFS_USB__ARB_CFG)\r
+#define USBFS_ARB_CFG_REG (*(reg8 *) USBFS_USB__ARB_CFG)\r
\r
-#define USBFS_ARB_EP1_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP1_CFG)\r
-#define USBFS_ARB_EP1_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP1_CFG)\r
+#define USBFS_ARB_EP1_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP1_CFG)\r
+#define USBFS_ARB_EP1_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP1_CFG)\r
+#define USBFS_ARB_EP1_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP1_INT_EN)\r
+#define USBFS_ARB_EP1_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP1_INT_EN)\r
+#define USBFS_ARB_EP1_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP1_SR)\r
+#define USBFS_ARB_EP1_SR_REG (*(reg8 *) USBFS_USB__ARB_EP1_SR)\r
#define USBFS_ARB_EP1_CFG_IND USBFS_USB__ARB_EP1_CFG\r
-#define USBFS_ARB_EP1_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP1_INT_EN)\r
-#define USBFS_ARB_EP1_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP1_INT_EN)\r
#define USBFS_ARB_EP1_INT_EN_IND USBFS_USB__ARB_EP1_INT_EN\r
-#define USBFS_ARB_EP1_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP1_SR)\r
-#define USBFS_ARB_EP1_SR_REG (* (reg8 *) USBFS_USB__ARB_EP1_SR)\r
#define USBFS_ARB_EP1_SR_IND USBFS_USB__ARB_EP1_SR\r
-\r
-#define USBFS_ARB_EP2_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP2_CFG)\r
-#define USBFS_ARB_EP2_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP2_CFG)\r
-#define USBFS_ARB_EP2_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP2_INT_EN)\r
-#define USBFS_ARB_EP2_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP2_INT_EN)\r
-#define USBFS_ARB_EP2_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP2_SR)\r
-#define USBFS_ARB_EP2_SR_REG (* (reg8 *) USBFS_USB__ARB_EP2_SR)\r
-\r
-#define USBFS_ARB_EP3_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP3_CFG)\r
-#define USBFS_ARB_EP3_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP3_CFG)\r
-#define USBFS_ARB_EP3_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP3_INT_EN)\r
-#define USBFS_ARB_EP3_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP3_INT_EN)\r
-#define USBFS_ARB_EP3_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP3_SR)\r
-#define USBFS_ARB_EP3_SR_REG (* (reg8 *) USBFS_USB__ARB_EP3_SR)\r
-\r
-#define USBFS_ARB_EP4_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP4_CFG)\r
-#define USBFS_ARB_EP4_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP4_CFG)\r
-#define USBFS_ARB_EP4_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP4_INT_EN)\r
-#define USBFS_ARB_EP4_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP4_INT_EN)\r
-#define USBFS_ARB_EP4_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP4_SR)\r
-#define USBFS_ARB_EP4_SR_REG (* (reg8 *) USBFS_USB__ARB_EP4_SR)\r
-\r
-#define USBFS_ARB_EP5_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP5_CFG)\r
-#define USBFS_ARB_EP5_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP5_CFG)\r
-#define USBFS_ARB_EP5_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP5_INT_EN)\r
-#define USBFS_ARB_EP5_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP5_INT_EN)\r
-#define USBFS_ARB_EP5_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP5_SR)\r
-#define USBFS_ARB_EP5_SR_REG (* (reg8 *) USBFS_USB__ARB_EP5_SR)\r
-\r
-#define USBFS_ARB_EP6_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP6_CFG)\r
-#define USBFS_ARB_EP6_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP6_CFG)\r
-#define USBFS_ARB_EP6_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP6_INT_EN)\r
-#define USBFS_ARB_EP6_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP6_INT_EN)\r
-#define USBFS_ARB_EP6_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP6_SR)\r
-#define USBFS_ARB_EP6_SR_REG (* (reg8 *) USBFS_USB__ARB_EP6_SR)\r
-\r
-#define USBFS_ARB_EP7_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP7_CFG)\r
-#define USBFS_ARB_EP7_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP7_CFG)\r
-#define USBFS_ARB_EP7_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP7_INT_EN)\r
-#define USBFS_ARB_EP7_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP7_INT_EN)\r
-#define USBFS_ARB_EP7_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP7_SR)\r
-#define USBFS_ARB_EP7_SR_REG (* (reg8 *) USBFS_USB__ARB_EP7_SR)\r
-\r
-#define USBFS_ARB_EP8_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP8_CFG)\r
-#define USBFS_ARB_EP8_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP8_CFG)\r
-#define USBFS_ARB_EP8_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP8_INT_EN)\r
-#define USBFS_ARB_EP8_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP8_INT_EN)\r
-#define USBFS_ARB_EP8_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP8_SR)\r
-#define USBFS_ARB_EP8_SR_REG (* (reg8 *) USBFS_USB__ARB_EP8_SR)\r
-\r
-#define USBFS_ARB_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_INT_EN)\r
-#define USBFS_ARB_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_INT_EN)\r
-#define USBFS_ARB_INT_SR_PTR ( (reg8 *) USBFS_USB__ARB_INT_SR)\r
-#define USBFS_ARB_INT_SR_REG (* (reg8 *) USBFS_USB__ARB_INT_SR)\r
-\r
-#define USBFS_ARB_RW1_DR_PTR ((reg8 *) USBFS_USB__ARB_RW1_DR)\r
+#define USBFS_ARB_EP_BASE (*(volatile USBFS_arb_eps_struct CYXDATA *) \\r
+ (USBFS_USB__ARB_EP1_CFG - sizeof(USBFS_arb_ep_struct)))\r
+\r
+#define USBFS_ARB_EP2_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP2_CFG)\r
+#define USBFS_ARB_EP2_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP2_CFG)\r
+#define USBFS_ARB_EP2_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP2_INT_EN)\r
+#define USBFS_ARB_EP2_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP2_INT_EN)\r
+#define USBFS_ARB_EP2_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP2_SR)\r
+#define USBFS_ARB_EP2_SR_REG (*(reg8 *) USBFS_USB__ARB_EP2_SR)\r
+\r
+#define USBFS_ARB_EP3_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP3_CFG)\r
+#define USBFS_ARB_EP3_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP3_CFG)\r
+#define USBFS_ARB_EP3_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP3_INT_EN)\r
+#define USBFS_ARB_EP3_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP3_INT_EN)\r
+#define USBFS_ARB_EP3_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP3_SR)\r
+#define USBFS_ARB_EP3_SR_REG (*(reg8 *) USBFS_USB__ARB_EP3_SR)\r
+\r
+#define USBFS_ARB_EP4_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP4_CFG)\r
+#define USBFS_ARB_EP4_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP4_CFG)\r
+#define USBFS_ARB_EP4_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP4_INT_EN)\r
+#define USBFS_ARB_EP4_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP4_INT_EN)\r
+#define USBFS_ARB_EP4_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP4_SR)\r
+#define USBFS_ARB_EP4_SR_REG (*(reg8 *) USBFS_USB__ARB_EP4_SR)\r
+\r
+#define USBFS_ARB_EP5_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP5_CFG)\r
+#define USBFS_ARB_EP5_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP5_CFG)\r
+#define USBFS_ARB_EP5_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP5_INT_EN)\r
+#define USBFS_ARB_EP5_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP5_INT_EN)\r
+#define USBFS_ARB_EP5_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP5_SR)\r
+#define USBFS_ARB_EP5_SR_REG (*(reg8 *) USBFS_USB__ARB_EP5_SR)\r
+\r
+#define USBFS_ARB_EP6_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP6_CFG)\r
+#define USBFS_ARB_EP6_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP6_CFG)\r
+#define USBFS_ARB_EP6_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP6_INT_EN)\r
+#define USBFS_ARB_EP6_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP6_INT_EN)\r
+#define USBFS_ARB_EP6_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP6_SR)\r
+#define USBFS_ARB_EP6_SR_REG (*(reg8 *) USBFS_USB__ARB_EP6_SR)\r
+\r
+#define USBFS_ARB_EP7_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP7_CFG)\r
+#define USBFS_ARB_EP7_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP7_CFG)\r
+#define USBFS_ARB_EP7_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP7_INT_EN)\r
+#define USBFS_ARB_EP7_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP7_INT_EN)\r
+#define USBFS_ARB_EP7_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP7_SR)\r
+#define USBFS_ARB_EP7_SR_REG (*(reg8 *) USBFS_USB__ARB_EP7_SR)\r
+\r
+#define USBFS_ARB_EP8_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP8_CFG)\r
+#define USBFS_ARB_EP8_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP8_CFG)\r
+#define USBFS_ARB_EP8_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP8_INT_EN)\r
+#define USBFS_ARB_EP8_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP8_INT_EN)\r
+#define USBFS_ARB_EP8_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP8_SR)\r
+#define USBFS_ARB_EP8_SR_REG (*(reg8 *) USBFS_USB__ARB_EP8_SR)\r
+\r
+#define USBFS_ARB_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_INT_EN)\r
+#define USBFS_ARB_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_INT_EN)\r
+#define USBFS_ARB_INT_SR_PTR ( (reg8 *) USBFS_USB__ARB_INT_SR)\r
+#define USBFS_ARB_INT_SR_REG (*(reg8 *) USBFS_USB__ARB_INT_SR)\r
+\r
+#define USBFS_ARB_RW1_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW1_DR)\r
+#define USBFS_ARB_RW1_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW1_RA)\r
+\r
+#define USBFS_ARB_RW1_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW1_RA_MSB)\r
+#define USBFS_ARB_RW1_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW1_WA)\r
+#define USBFS_ARB_RW1_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW1_WA_MSB)\r
#define USBFS_ARB_RW1_DR_IND USBFS_USB__ARB_RW1_DR\r
-#define USBFS_ARB_RW1_RA_PTR ((reg8 *) USBFS_USB__ARB_RW1_RA)\r
#define USBFS_ARB_RW1_RA_IND USBFS_USB__ARB_RW1_RA\r
-#define USBFS_ARB_RW1_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_RA_MSB)\r
#define USBFS_ARB_RW1_RA_MSB_IND USBFS_USB__ARB_RW1_RA_MSB\r
-#define USBFS_ARB_RW1_WA_PTR ((reg8 *) USBFS_USB__ARB_RW1_WA)\r
#define USBFS_ARB_RW1_WA_IND USBFS_USB__ARB_RW1_WA\r
-#define USBFS_ARB_RW1_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_WA_MSB)\r
#define USBFS_ARB_RW1_WA_MSB_IND USBFS_USB__ARB_RW1_WA_MSB\r
\r
-#define USBFS_ARB_RW2_DR_PTR ((reg8 *) USBFS_USB__ARB_RW2_DR)\r
-#define USBFS_ARB_RW2_RA_PTR ((reg8 *) USBFS_USB__ARB_RW2_RA)\r
-#define USBFS_ARB_RW2_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_RA_MSB)\r
-#define USBFS_ARB_RW2_WA_PTR ((reg8 *) USBFS_USB__ARB_RW2_WA)\r
-#define USBFS_ARB_RW2_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_WA_MSB)\r
-\r
-#define USBFS_ARB_RW3_DR_PTR ((reg8 *) USBFS_USB__ARB_RW3_DR)\r
-#define USBFS_ARB_RW3_RA_PTR ((reg8 *) USBFS_USB__ARB_RW3_RA)\r
-#define USBFS_ARB_RW3_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_RA_MSB)\r
-#define USBFS_ARB_RW3_WA_PTR ((reg8 *) USBFS_USB__ARB_RW3_WA)\r
-#define USBFS_ARB_RW3_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_WA_MSB)\r
-\r
-#define USBFS_ARB_RW4_DR_PTR ((reg8 *) USBFS_USB__ARB_RW4_DR)\r
-#define USBFS_ARB_RW4_RA_PTR ((reg8 *) USBFS_USB__ARB_RW4_RA)\r
-#define USBFS_ARB_RW4_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_RA_MSB)\r
-#define USBFS_ARB_RW4_WA_PTR ((reg8 *) USBFS_USB__ARB_RW4_WA)\r
-#define USBFS_ARB_RW4_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_WA_MSB)\r
-\r
-#define USBFS_ARB_RW5_DR_PTR ((reg8 *) USBFS_USB__ARB_RW5_DR)\r
-#define USBFS_ARB_RW5_RA_PTR ((reg8 *) USBFS_USB__ARB_RW5_RA)\r
-#define USBFS_ARB_RW5_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_RA_MSB)\r
-#define USBFS_ARB_RW5_WA_PTR ((reg8 *) USBFS_USB__ARB_RW5_WA)\r
-#define USBFS_ARB_RW5_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_WA_MSB)\r
-\r
-#define USBFS_ARB_RW6_DR_PTR ((reg8 *) USBFS_USB__ARB_RW6_DR)\r
-#define USBFS_ARB_RW6_RA_PTR ((reg8 *) USBFS_USB__ARB_RW6_RA)\r
-#define USBFS_ARB_RW6_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_RA_MSB)\r
-#define USBFS_ARB_RW6_WA_PTR ((reg8 *) USBFS_USB__ARB_RW6_WA)\r
-#define USBFS_ARB_RW6_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_WA_MSB)\r
-\r
-#define USBFS_ARB_RW7_DR_PTR ((reg8 *) USBFS_USB__ARB_RW7_DR)\r
-#define USBFS_ARB_RW7_RA_PTR ((reg8 *) USBFS_USB__ARB_RW7_RA)\r
-#define USBFS_ARB_RW7_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_RA_MSB)\r
-#define USBFS_ARB_RW7_WA_PTR ((reg8 *) USBFS_USB__ARB_RW7_WA)\r
-#define USBFS_ARB_RW7_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_WA_MSB)\r
-\r
-#define USBFS_ARB_RW8_DR_PTR ((reg8 *) USBFS_USB__ARB_RW8_DR)\r
-#define USBFS_ARB_RW8_RA_PTR ((reg8 *) USBFS_USB__ARB_RW8_RA)\r
-#define USBFS_ARB_RW8_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_RA_MSB)\r
-#define USBFS_ARB_RW8_WA_PTR ((reg8 *) USBFS_USB__ARB_RW8_WA)\r
-#define USBFS_ARB_RW8_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_WA_MSB)\r
-\r
-#define USBFS_BUF_SIZE_PTR ( (reg8 *) USBFS_USB__BUF_SIZE)\r
-#define USBFS_BUF_SIZE_REG (* (reg8 *) USBFS_USB__BUF_SIZE)\r
-#define USBFS_BUS_RST_CNT_PTR ( (reg8 *) USBFS_USB__BUS_RST_CNT)\r
-#define USBFS_BUS_RST_CNT_REG (* (reg8 *) USBFS_USB__BUS_RST_CNT)\r
-#define USBFS_CWA_PTR ( (reg8 *) USBFS_USB__CWA)\r
-#define USBFS_CWA_REG (* (reg8 *) USBFS_USB__CWA)\r
-#define USBFS_CWA_MSB_PTR ( (reg8 *) USBFS_USB__CWA_MSB)\r
-#define USBFS_CWA_MSB_REG (* (reg8 *) USBFS_USB__CWA_MSB)\r
-#define USBFS_CR0_PTR ( (reg8 *) USBFS_USB__CR0)\r
-#define USBFS_CR0_REG (* (reg8 *) USBFS_USB__CR0)\r
-#define USBFS_CR1_PTR ( (reg8 *) USBFS_USB__CR1)\r
-#define USBFS_CR1_REG (* (reg8 *) USBFS_USB__CR1)\r
-\r
-#define USBFS_DMA_THRES_PTR ( (reg8 *) USBFS_USB__DMA_THRES)\r
-#define USBFS_DMA_THRES_REG (* (reg8 *) USBFS_USB__DMA_THRES)\r
-#define USBFS_DMA_THRES_MSB_PTR ( (reg8 *) USBFS_USB__DMA_THRES_MSB)\r
-#define USBFS_DMA_THRES_MSB_REG (* (reg8 *) USBFS_USB__DMA_THRES_MSB)\r
-\r
-#define USBFS_EP_ACTIVE_PTR ( (reg8 *) USBFS_USB__EP_ACTIVE)\r
-#define USBFS_EP_ACTIVE_REG (* (reg8 *) USBFS_USB__EP_ACTIVE)\r
-#define USBFS_EP_TYPE_PTR ( (reg8 *) USBFS_USB__EP_TYPE)\r
-#define USBFS_EP_TYPE_REG (* (reg8 *) USBFS_USB__EP_TYPE)\r
-\r
-#define USBFS_EP0_CNT_PTR ( (reg8 *) USBFS_USB__EP0_CNT)\r
-#define USBFS_EP0_CNT_REG (* (reg8 *) USBFS_USB__EP0_CNT)\r
-#define USBFS_EP0_CR_PTR ( (reg8 *) USBFS_USB__EP0_CR)\r
-#define USBFS_EP0_CR_REG (* (reg8 *) USBFS_USB__EP0_CR)\r
-#define USBFS_EP0_DR0_PTR ( (reg8 *) USBFS_USB__EP0_DR0)\r
-#define USBFS_EP0_DR0_REG (* (reg8 *) USBFS_USB__EP0_DR0)\r
+#define USBFS_ARB_RW2_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW2_DR)\r
+#define USBFS_ARB_RW2_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW2_RA)\r
+#define USBFS_ARB_RW2_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW2_RA_MSB)\r
+#define USBFS_ARB_RW2_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW2_WA)\r
+#define USBFS_ARB_RW2_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW2_WA_MSB)\r
+\r
+#define USBFS_ARB_RW3_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW3_DR)\r
+#define USBFS_ARB_RW3_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW3_RA)\r
+#define USBFS_ARB_RW3_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW3_RA_MSB)\r
+#define USBFS_ARB_RW3_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW3_WA)\r
+#define USBFS_ARB_RW3_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW3_WA_MSB)\r
+\r
+#define USBFS_ARB_RW4_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW4_DR)\r
+#define USBFS_ARB_RW4_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW4_RA)\r
+#define USBFS_ARB_RW4_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW4_RA_MSB)\r
+#define USBFS_ARB_RW4_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW4_WA)\r
+#define USBFS_ARB_RW4_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW4_WA_MSB)\r
+\r
+#define USBFS_ARB_RW5_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW5_DR)\r
+#define USBFS_ARB_RW5_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW5_RA)\r
+#define USBFS_ARB_RW5_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW5_RA_MSB)\r
+#define USBFS_ARB_RW5_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW5_WA)\r
+#define USBFS_ARB_RW5_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW5_WA_MSB)\r
+\r
+#define USBFS_ARB_RW6_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW6_DR)\r
+#define USBFS_ARB_RW6_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW6_RA)\r
+#define USBFS_ARB_RW6_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW6_RA_MSB)\r
+#define USBFS_ARB_RW6_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW6_WA)\r
+#define USBFS_ARB_RW6_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW6_WA_MSB)\r
+\r
+#define USBFS_ARB_RW7_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW7_DR)\r
+#define USBFS_ARB_RW7_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW7_RA)\r
+#define USBFS_ARB_RW7_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW7_RA_MSB)\r
+#define USBFS_ARB_RW7_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW7_WA)\r
+#define USBFS_ARB_RW7_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW7_WA_MSB)\r
+\r
+#define USBFS_ARB_RW8_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW8_DR)\r
+#define USBFS_ARB_RW8_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW8_RA)\r
+#define USBFS_ARB_RW8_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW8_RA_MSB)\r
+#define USBFS_ARB_RW8_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW8_WA)\r
+#define USBFS_ARB_RW8_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW8_WA_MSB)\r
+\r
+#define USBFS_BUF_SIZE_PTR ( (reg8 *) USBFS_USB__BUF_SIZE)\r
+#define USBFS_BUF_SIZE_REG (*(reg8 *) USBFS_USB__BUF_SIZE)\r
+#define USBFS_BUS_RST_CNT_PTR ( (reg8 *) USBFS_USB__BUS_RST_CNT)\r
+#define USBFS_BUS_RST_CNT_REG (*(reg8 *) USBFS_USB__BUS_RST_CNT)\r
+#define USBFS_CWA_PTR ( (reg8 *) USBFS_USB__CWA)\r
+#define USBFS_CWA_REG (*(reg8 *) USBFS_USB__CWA)\r
+#define USBFS_CWA_MSB_PTR ( (reg8 *) USBFS_USB__CWA_MSB)\r
+#define USBFS_CWA_MSB_REG (*(reg8 *) USBFS_USB__CWA_MSB)\r
+#define USBFS_CR0_PTR ( (reg8 *) USBFS_USB__CR0)\r
+#define USBFS_CR0_REG (*(reg8 *) USBFS_USB__CR0)\r
+#define USBFS_CR1_PTR ( (reg8 *) USBFS_USB__CR1)\r
+#define USBFS_CR1_REG (*(reg8 *) USBFS_USB__CR1)\r
+\r
+#define USBFS_DMA_THRES_PTR ( (reg8 *) USBFS_USB__DMA_THRES)\r
+#define USBFS_DMA_THRES_REG (*(reg8 *) USBFS_USB__DMA_THRES)\r
+#define USBFS_DMA_THRES_MSB_PTR ( (reg8 *) USBFS_USB__DMA_THRES_MSB)\r
+#define USBFS_DMA_THRES_MSB_REG (*(reg8 *) USBFS_USB__DMA_THRES_MSB)\r
+\r
+#define USBFS_EP_ACTIVE_PTR ( (reg8 *) USBFS_USB__EP_ACTIVE)\r
+#define USBFS_EP_ACTIVE_REG (*(reg8 *) USBFS_USB__EP_ACTIVE)\r
+#define USBFS_EP_TYPE_PTR ( (reg8 *) USBFS_USB__EP_TYPE)\r
+#define USBFS_EP_TYPE_REG (*(reg8 *) USBFS_USB__EP_TYPE)\r
+\r
+#define USBFS_EP0_CNT_PTR ( (reg8 *) USBFS_USB__EP0_CNT)\r
+#define USBFS_EP0_CNT_REG (*(reg8 *) USBFS_USB__EP0_CNT)\r
+#define USBFS_EP0_CR_PTR ( (reg8 *) USBFS_USB__EP0_CR)\r
+#define USBFS_EP0_CR_REG (*(reg8 *) USBFS_USB__EP0_CR)\r
+#define USBFS_EP0_DR0_PTR ( (reg8 *) USBFS_USB__EP0_DR0)\r
+#define USBFS_EP0_DR0_REG (*(reg8 *) USBFS_USB__EP0_DR0)\r
+#define USBFS_EP0_DR1_PTR ( (reg8 *) USBFS_USB__EP0_DR1)\r
+#define USBFS_EP0_DR1_REG (*(reg8 *) USBFS_USB__EP0_DR1)\r
+#define USBFS_EP0_DR2_PTR ( (reg8 *) USBFS_USB__EP0_DR2)\r
+#define USBFS_EP0_DR2_REG (*(reg8 *) USBFS_USB__EP0_DR2)\r
+#define USBFS_EP0_DR3_PTR ( (reg8 *) USBFS_USB__EP0_DR3)\r
+#define USBFS_EP0_DR3_REG (*(reg8 *) USBFS_USB__EP0_DR3)\r
+#define USBFS_EP0_DR4_PTR ( (reg8 *) USBFS_USB__EP0_DR4)\r
+#define USBFS_EP0_DR4_REG (*(reg8 *) USBFS_USB__EP0_DR4)\r
+#define USBFS_EP0_DR5_PTR ( (reg8 *) USBFS_USB__EP0_DR5)\r
+#define USBFS_EP0_DR5_REG (*(reg8 *) USBFS_USB__EP0_DR5)\r
+#define USBFS_EP0_DR6_PTR ( (reg8 *) USBFS_USB__EP0_DR6)\r
+#define USBFS_EP0_DR6_REG (*(reg8 *) USBFS_USB__EP0_DR6)\r
+#define USBFS_EP0_DR7_PTR ( (reg8 *) USBFS_USB__EP0_DR7)\r
+#define USBFS_EP0_DR7_REG (*(reg8 *) USBFS_USB__EP0_DR7)\r
#define USBFS_EP0_DR0_IND USBFS_USB__EP0_DR0\r
-#define USBFS_EP0_DR1_PTR ( (reg8 *) USBFS_USB__EP0_DR1)\r
-#define USBFS_EP0_DR1_REG (* (reg8 *) USBFS_USB__EP0_DR1)\r
-#define USBFS_EP0_DR2_PTR ( (reg8 *) USBFS_USB__EP0_DR2)\r
-#define USBFS_EP0_DR2_REG (* (reg8 *) USBFS_USB__EP0_DR2)\r
-#define USBFS_EP0_DR3_PTR ( (reg8 *) USBFS_USB__EP0_DR3)\r
-#define USBFS_EP0_DR3_REG (* (reg8 *) USBFS_USB__EP0_DR3)\r
-#define USBFS_EP0_DR4_PTR ( (reg8 *) USBFS_USB__EP0_DR4)\r
-#define USBFS_EP0_DR4_REG (* (reg8 *) USBFS_USB__EP0_DR4)\r
-#define USBFS_EP0_DR5_PTR ( (reg8 *) USBFS_USB__EP0_DR5)\r
-#define USBFS_EP0_DR5_REG (* (reg8 *) USBFS_USB__EP0_DR5)\r
-#define USBFS_EP0_DR6_PTR ( (reg8 *) USBFS_USB__EP0_DR6)\r
-#define USBFS_EP0_DR6_REG (* (reg8 *) USBFS_USB__EP0_DR6)\r
-#define USBFS_EP0_DR7_PTR ( (reg8 *) USBFS_USB__EP0_DR7)\r
-#define USBFS_EP0_DR7_REG (* (reg8 *) USBFS_USB__EP0_DR7)\r
-\r
-#define USBFS_OSCLK_DR0_PTR ( (reg8 *) USBFS_USB__OSCLK_DR0)\r
-#define USBFS_OSCLK_DR0_REG (* (reg8 *) USBFS_USB__OSCLK_DR0)\r
-#define USBFS_OSCLK_DR1_PTR ( (reg8 *) USBFS_USB__OSCLK_DR1)\r
-#define USBFS_OSCLK_DR1_REG (* (reg8 *) USBFS_USB__OSCLK_DR1)\r
-\r
-#define USBFS_PM_ACT_CFG_PTR ( (reg8 *) USBFS_USB__PM_ACT_CFG)\r
-#define USBFS_PM_ACT_CFG_REG (* (reg8 *) USBFS_USB__PM_ACT_CFG)\r
-#define USBFS_PM_STBY_CFG_PTR ( (reg8 *) USBFS_USB__PM_STBY_CFG)\r
-#define USBFS_PM_STBY_CFG_REG (* (reg8 *) USBFS_USB__PM_STBY_CFG)\r
-\r
-#define USBFS_SIE_EP_INT_EN_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_EN)\r
-#define USBFS_SIE_EP_INT_EN_REG (* (reg8 *) USBFS_USB__SIE_EP_INT_EN)\r
-#define USBFS_SIE_EP_INT_SR_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_SR)\r
-#define USBFS_SIE_EP_INT_SR_REG (* (reg8 *) USBFS_USB__SIE_EP_INT_SR)\r
-\r
-#define USBFS_SIE_EP1_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT0)\r
-#define USBFS_SIE_EP1_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP1_CNT0)\r
-#define USBFS_SIE_EP1_CNT0_IND USBFS_USB__SIE_EP1_CNT0\r
-#define USBFS_SIE_EP1_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT1)\r
-#define USBFS_SIE_EP1_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP1_CNT1)\r
+#define USBFS_EP0_DR_BASE (*(volatile USBFS_ep0_data_struct CYXDATA *) USBFS_USB__EP0_DR0)\r
+\r
+#define USBFS_OSCLK_DR0_PTR ( (reg8 *) USBFS_USB__OSCLK_DR0)\r
+#define USBFS_OSCLK_DR0_REG (*(reg8 *) USBFS_USB__OSCLK_DR0)\r
+#define USBFS_OSCLK_DR1_PTR ( (reg8 *) USBFS_USB__OSCLK_DR1)\r
+#define USBFS_OSCLK_DR1_REG (*(reg8 *) USBFS_USB__OSCLK_DR1)\r
+\r
+#define USBFS_SIE_EP_INT_EN_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_EN)\r
+#define USBFS_SIE_EP_INT_EN_REG (*(reg8 *) USBFS_USB__SIE_EP_INT_EN)\r
+#define USBFS_SIE_EP_INT_SR_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_SR)\r
+#define USBFS_SIE_EP_INT_SR_REG (*(reg8 *) USBFS_USB__SIE_EP_INT_SR)\r
+\r
+#define USBFS_SIE_EP1_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT0)\r
+#define USBFS_SIE_EP1_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP1_CNT0)\r
+#define USBFS_SIE_EP1_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT1)\r
+#define USBFS_SIE_EP1_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP1_CNT1)\r
+#define USBFS_SIE_EP1_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CR0)\r
+#define USBFS_SIE_EP1_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP1_CR0)\r
#define USBFS_SIE_EP1_CNT1_IND USBFS_USB__SIE_EP1_CNT1\r
-#define USBFS_SIE_EP1_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CR0)\r
-#define USBFS_SIE_EP1_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP1_CR0)\r
+#define USBFS_SIE_EP1_CNT0_IND USBFS_USB__SIE_EP1_CNT0\r
#define USBFS_SIE_EP1_CR0_IND USBFS_USB__SIE_EP1_CR0\r
+#define USBFS_SIE_EP_BASE (*(volatile USBFS_sie_eps_struct CYXDATA *) \\r
+ (USBFS_USB__SIE_EP1_CNT0 - sizeof(USBFS_sie_ep_struct)))\r
+\r
+#define USBFS_SIE_EP2_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT0)\r
+#define USBFS_SIE_EP2_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP2_CNT0)\r
+#define USBFS_SIE_EP2_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT1)\r
+#define USBFS_SIE_EP2_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP2_CNT1)\r
+#define USBFS_SIE_EP2_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CR0)\r
+#define USBFS_SIE_EP2_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP2_CR0)\r
+\r
+#define USBFS_SIE_EP3_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT0)\r
+#define USBFS_SIE_EP3_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP3_CNT0)\r
+#define USBFS_SIE_EP3_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT1)\r
+#define USBFS_SIE_EP3_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP3_CNT1)\r
+#define USBFS_SIE_EP3_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CR0)\r
+#define USBFS_SIE_EP3_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP3_CR0)\r
+\r
+#define USBFS_SIE_EP4_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT0)\r
+#define USBFS_SIE_EP4_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP4_CNT0)\r
+#define USBFS_SIE_EP4_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT1)\r
+#define USBFS_SIE_EP4_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP4_CNT1)\r
+#define USBFS_SIE_EP4_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CR0)\r
+#define USBFS_SIE_EP4_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP4_CR0)\r
+\r
+#define USBFS_SIE_EP5_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT0)\r
+#define USBFS_SIE_EP5_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP5_CNT0)\r
+#define USBFS_SIE_EP5_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT1)\r
+#define USBFS_SIE_EP5_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP5_CNT1)\r
+#define USBFS_SIE_EP5_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CR0)\r
+#define USBFS_SIE_EP5_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP5_CR0)\r
+\r
+#define USBFS_SIE_EP6_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT0)\r
+#define USBFS_SIE_EP6_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP6_CNT0)\r
+#define USBFS_SIE_EP6_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT1)\r
+#define USBFS_SIE_EP6_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP6_CNT1)\r
+#define USBFS_SIE_EP6_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CR0)\r
+#define USBFS_SIE_EP6_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP6_CR0)\r
+\r
+#define USBFS_SIE_EP7_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT0)\r
+#define USBFS_SIE_EP7_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP7_CNT0)\r
+#define USBFS_SIE_EP7_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT1)\r
+#define USBFS_SIE_EP7_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP7_CNT1)\r
+#define USBFS_SIE_EP7_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CR0)\r
+#define USBFS_SIE_EP7_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP7_CR0)\r
+\r
+#define USBFS_SIE_EP8_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT0)\r
+#define USBFS_SIE_EP8_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP8_CNT0)\r
+#define USBFS_SIE_EP8_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT1)\r
+#define USBFS_SIE_EP8_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP8_CNT1)\r
+#define USBFS_SIE_EP8_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CR0)\r
+#define USBFS_SIE_EP8_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP8_CR0)\r
+\r
+#define USBFS_SOF0_PTR ( (reg8 *) USBFS_USB__SOF0)\r
+#define USBFS_SOF0_REG (*(reg8 *) USBFS_USB__SOF0)\r
+#define USBFS_SOF1_PTR ( (reg8 *) USBFS_USB__SOF1)\r
+#define USBFS_SOF1_REG (*(reg8 *) USBFS_USB__SOF1)\r
+\r
+#define USBFS_USB_CLK_EN_PTR ( (reg8 *) USBFS_USB__USB_CLK_EN)\r
+#define USBFS_USB_CLK_EN_REG (*(reg8 *) USBFS_USB__USB_CLK_EN)\r
+\r
+#define USBFS_USBIO_CR0_PTR ( (reg8 *) USBFS_USB__USBIO_CR0)\r
+#define USBFS_USBIO_CR0_REG (*(reg8 *) USBFS_USB__USBIO_CR0)\r
+#define USBFS_USBIO_CR1_PTR ( (reg8 *) USBFS_USB__USBIO_CR1)\r
+#define USBFS_USBIO_CR1_REG (*(reg8 *) USBFS_USB__USBIO_CR1)\r
+\r
+#define USBFS_DYN_RECONFIG_PTR ( (reg8 *) USBFS_USB__DYN_RECONFIG)\r
+#define USBFS_DYN_RECONFIG_REG (*(reg8 *) USBFS_USB__DYN_RECONFIG)\r
+\r
+#if (CY_PSOC4)\r
+ #define USBFS_ARB_RW1_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_RA16)\r
+ #define USBFS_ARB_RW1_RA16_REG (*(reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_RA16)\r
+ #define USBFS_ARB_RW1_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_WA16)\r
+ #define USBFS_ARB_RW1_WA16_REG (*(reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_WA16)\r
+ #define USBFS_ARB_RW1_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_DR16)\r
+ #define USBFS_ARB_RW1_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_DR16)\r
+ #define USBFS_ARB_EP16_BASE (*(volatile USBFS_arb_eps_reg16_struct CYXDATA *) \\r
+ (USBFS_USB__ARB_RW1_WA16 - sizeof(USBFS_arb_ep_reg16_struct)))\r
+\r
+ #define USBFS_ARB_RW2_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW2_DR16)\r
+ #define USBFS_ARB_RW2_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW2_RA16)\r
+ #define USBFS_ARB_RW2_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW2_WA16)\r
+\r
+ #define USBFS_ARB_RW3_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW3_DR16)\r
+ #define USBFS_ARB_RW3_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW3_RA16)\r
+ #define USBFS_ARB_RW3_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW3_WA16)\r
+\r
+ #define USBFS_ARB_RW4_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW4_DR16)\r
+ #define USBFS_ARB_RW4_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW4_RA16)\r
+ #define USBFS_ARB_RW4_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW4_WA16)\r
+\r
+ #define USBFS_ARB_RW5_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW5_DR16)\r
+ #define USBFS_ARB_RW5_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW5_RA16)\r
+ #define USBFS_ARB_RW5_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW5_WA16)\r
+\r
+ #define USBFS_ARB_RW6_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW6_DR16)\r
+ #define USBFS_ARB_RW6_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW6_RA16)\r
+ #define USBFS_ARB_RW6_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW6_WA16)\r
+\r
+ #define USBFS_ARB_RW7_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW7_DR16)\r
+ #define USBFS_ARB_RW7_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW7_RA16)\r
+ #define USBFS_ARB_RW7_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW7_WA16)\r
+\r
+ #define USBFS_ARB_RW8_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW8_DR16)\r
+ #define USBFS_ARB_RW8_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW8_RA16)\r
+ #define USBFS_ARB_RW8_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW8_WA16)\r
+\r
+ #define USBFS_OSCLK_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__OSCLK_DR16)\r
+ #define USBFS_OSCLK_DR16_REG (*(reg32 *) USBFS_cy_m0s8_usb__OSCLK_DR16)\r
+\r
+ #define USBFS_SOF16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__SOF16)\r
+ #define USBFS_SOF16_REG (*(reg32 *) USBFS_cy_m0s8_usb__SOF16)\r
+ \r
+ #define USBFS_CWA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__CWA16)\r
+ #define USBFS_CWA16_REG (*(reg32 *) USBFS_cy_m0s8_usb__CWA16)\r
+\r
+ #define USBFS_DMA_THRES16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__DMA_THRES16)\r
+ #define USBFS_DMA_THRES16_REG (*(reg32 *) USBFS_cy_m0s8_usb__DMA_THRES16)\r
+\r
+ #define USBFS_USB_CLK_EN_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_CLK_EN)\r
+ #define USBFS_USB_CLK_EN_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_CLK_EN)\r
+\r
+ #define USBFS_USBIO_CR2_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USBIO_CR2)\r
+ #define USBFS_USBIO_CR2_REG (*(reg32 *) USBFS_cy_m0s8_usb__USBIO_CR2)\r
+\r
+ #define USBFS_USB_MEM ( (reg32 *) USBFS_cy_m0s8_usb__MEM_DATA0)\r
+\r
+ #define USBFS_POWER_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_POWER_CTRL)\r
+ #define USBFS_POWER_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_POWER_CTRL)\r
+\r
+ #define USBFS_CHGDET_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_CHGDET_CTRL)\r
+ #define USBFS_CHGDET_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_CHGDET_CTRL)\r
+\r
+ #define USBFS_USBIO_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_USBIO_CTRL)\r
+ #define USBFS_USBIO_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_USBIO_CTRL)\r
+\r
+ #define USBFS_FLOW_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_FLOW_CTRL)\r
+ #define USBFS_FLOW_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_FLOW_CTRL)\r
+\r
+ #define USBFS_LPM_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_LPM_CTRL)\r
+ #define USBFS_LPM_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_LPM_CTRL)\r
+\r
+ #define USBFS_LPM_STAT_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_LPM_STAT)\r
+ #define USBFS_LPM_STAT_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_LPM_STAT)\r
+\r
+ #define USBFS_PHY_CONTROL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_PHY_CONTROL)\r
+ #define USBFS_PHY_CONTROL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_PHY_CONTROL)\r
+\r
+ #define USBFS_INTR_SIE_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE)\r
+ #define USBFS_INTR_SIE_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE)\r
+\r
+ #define USBFS_INTR_SIE_SET_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_SET)\r
+ #define USBFS_INTR_SIE_SET_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_SET)\r
+\r
+ #define USBFS_INTR_SIE_MASK_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASK)\r
+ #define USBFS_INTR_SIE_MASK_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASK)\r
+\r
+ #define USBFS_INTR_SIE_MASKED_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASKED)\r
+ #define USBFS_INTR_SIE_MASKED_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASKED)\r
+\r
+ #define USBFS_INTR_LVL_SEL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_LVL_SEL)\r
+ #define USBFS_INTR_LVL_SEL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_LVL_SEL)\r
+\r
+ #define USBFS_INTR_CAUSE_HI_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_HI)\r
+ #define USBFS_INTR_CAUSE_HI_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_HI)\r
+\r
+ #define USBFS_INTR_CAUSE_LO_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_LO)\r
+ #define USBFS_INTR_CAUSE_LO_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_LO)\r
+\r
+ #define USBFS_INTR_CAUSE_MED_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_MED)\r
+ #define USBFS_INTR_CAUSE_MED_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_MED)\r
+\r
+ #define USBFS_DFT_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_DFT_CTRL)\r
+ #define USBFS_DFT_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_DFT_CTRL)\r
+\r
+ #if (USBFS_VBUS_MONITORING_ENABLE)\r
+ #if (USBFS_VBUS_POWER_PAD_ENABLE)\r
+ /* Vbus power pad pin is hard wired to P13[2] */\r
+ #define USBFS_VBUS_STATUS_REG (*(reg32 *) CYREG_GPIO_PRT13_PS)\r
+ #define USBFS_VBUS_STATUS_PTR ( (reg32 *) CYREG_GPIO_PRT13_PS)\r
+ #define USBFS_VBUS_VALID (0x04u)\r
+ #else\r
+ /* Vbus valid pin is hard wired to P0[0] */\r
+ #define USBFS_VBUS_STATUS_REG (*(reg32 *) CYREG_GPIO_PRT0_PS)\r
+ #define USBFS_VBUS_STATUS_PTR ( (reg32 *) CYREG_GPIO_PRT0_PS)\r
+ #define USBFS_VBUS_VALID (0x01u)\r
+ #endif\r
+ #endif /*(USBFS_VBUS_MONITORING_ENABLE) */\r
+\r
+ #define USBFS_BURSTEND_0_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND0_TR_OUTPUT)\r
+ #define USBFS_BURSTEND_1_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND1_TR_OUTPUT)\r
+ #define USBFS_BURSTEND_2_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND2_TR_OUTPUT)\r
+ #define USBFS_BURSTEND_3_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND3_TR_OUTPUT)\r
+ #define USBFS_BURSTEND_4_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND4_TR_OUTPUT)\r
+ #define USBFS_BURSTEND_5_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND5_TR_OUTPUT)\r
+ #define USBFS_BURSTEND_6_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND6_TR_OUTPUT)\r
+ #define USBFS_BURSTEND_7_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND7_TR_OUTPUT)\r
+ \r
+#else /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+ /* USBFS_PM_USB_CR0 */\r
+ #define USBFS_PM_USB_CR0_PTR ( (reg8 *) CYREG_PM_USB_CR0)\r
+ #define USBFS_PM_USB_CR0_REG (*(reg8 *) CYREG_PM_USB_CR0)\r
+\r
+ /* USBFS_PM_ACT/STBY_CFG */\r
+ #define USBFS_PM_ACT_CFG_PTR ( (reg8 *) USBFS_USB__PM_ACT_CFG)\r
+ #define USBFS_PM_ACT_CFG_REG (*(reg8 *) USBFS_USB__PM_ACT_CFG)\r
+ #define USBFS_PM_STBY_CFG_PTR ( (reg8 *) USBFS_USB__PM_STBY_CFG)\r
+ #define USBFS_PM_STBY_CFG_REG (*(reg8 *) USBFS_USB__PM_STBY_CFG)\r
+\r
+ #if (!CY_PSOC5LP)\r
+ #define USBFS_USBIO_CR2_PTR ( (reg8 *) USBFS_USB__USBIO_CR2)\r
+ #define USBFS_USBIO_CR2_REG (* (reg8 *) USBFS_USB__USBIO_CR2)\r
+ #endif /* (!CY_PSOC5LP) */\r
+\r
+ /* USBFS_USB_MEM - USB IP memory buffer */\r
+ #define USBFS_USB_MEM ((reg8 *) CYDEV_USB_MEM_BASE)\r
+\r
+ #if (USBFS_VBUS_MONITORING_ENABLE)\r
+ #if (USBFS_VBUS_MONITORING_INTERNAL)\r
+ #define USBFS_VBUS_STATUS_REG (*(reg8 *) USBFS_VBUS__PS)\r
+ #define USBFS_VBUS_STATUS_PTR ( (reg8 *) USBFS_VBUS__PS)\r
+ #define USBFS_VBUS_VALID (USBFS_VBUS__MASK)\r
+ #else\r
+ #define USBFS_VBUS_STATUS_REG (*(reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG)\r
+ #define USBFS_VBUS_STATUS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG)\r
+ #define USBFS_VBUS_VALID (USBFS_Vbus_ps_sts_sts_reg__MASK)\r
+ #endif /* (USBFS_VBUS_MONITORING_INTERNAL) */\r
+ #endif /*(USBFS_VBUS_MONITORING_ENABLE) */\r
+#endif /* (CY_PSOC4) */\r
+\r
+\r
+/***************************************\r
+* Interrupt source constants\r
+***************************************/\r
+\r
+#define USBFS_DP_INTC_PRIORITY USBFS_dp_int__INTC_PRIOR_NUM\r
+#define USBFS_DP_INTC_VECT_NUM USBFS_dp_int__INTC_NUMBER\r
+\r
+#if (CY_PSOC4)\r
+ #define USBFS_DMA_AUTO_INTR_PRIO (0u)\r
+ \r
+ #define USBFS_INTR_HI_PRIORITY USBFS_high_int__INTC_PRIOR_NUM\r
+ #define USBFS_INTR_HI_VECT_NUM USBFS_high_int__INTC_NUMBER\r
+\r
+ #define USBFS_INTR_MED_PRIORITY USBFS_med_int__INTC_PRIOR_NUM\r
+ #define USBFS_INTR_MED_VECT_NUM USBFS_med_int__INTC_NUMBER\r
+\r
+ #define USBFS_INTR_LO_PRIORITY USBFS_lo_int__INTC_PRIOR_NUM\r
+ #define USBFS_INTR_LO_VECT_NUM USBFS_lo_int__INTC_NUMBER\r
+\r
+ /* Interrupt sources in USBFS_isrCallbacks[] table */\r
+ #define USBFS_SOF_INTR_NUM (0u)\r
+ #define USBFS_BUS_RESET_INT_NUM (1u)\r
+ #define USBFS_EP0_INTR_NUM (2u)\r
+ #define USBFS_LPM_INTR_NUM (3u)\r
+ #define USBFS_ARB_EP_INTR_NUM (4u)\r
+ #define USBFS_EP1_INTR_NUM (5u)\r
+ #define USBFS_EP2_INTR_NUM (6u)\r
+ #define USBFS_EP3_INTR_NUM (7u)\r
+ #define USBFS_EP4_INTR_NUM (8u)\r
+ #define USBFS_EP5_INTR_NUM (9u)\r
+ #define USBFS_EP6_INTR_NUM (10u)\r
+ #define USBFS_EP7_INTR_NUM (11u)\r
+ #define USBFS_EP8_INTR_NUM (12u)\r
+\r
+#else\r
+ #define USBFS_BUS_RESET_PRIOR USBFS_bus_reset__INTC_PRIOR_NUM\r
+ #define USBFS_BUS_RESET_MASK USBFS_bus_reset__INTC_MASK\r
+ #define USBFS_BUS_RESET_VECT_NUM USBFS_bus_reset__INTC_NUMBER\r
+\r
+ #define USBFS_SOF_PRIOR USBFS_sof_int__INTC_PRIOR_NUM\r
+ #define USBFS_SOF_MASK USBFS_sof_int__INTC_MASK\r
+ #define USBFS_SOF_VECT_NUM USBFS_sof_int__INTC_NUMBER\r
+\r
+ #define USBFS_EP_0_PRIOR USBFS_ep_0__INTC_PRIOR_NUM\r
+ #define USBFS_EP_0_MASK USBFS_ep_0__INTC_MASK\r
+ #define USBFS_EP_0_VECT_NUM USBFS_ep_0__INTC_NUMBER\r
+\r
+ #define USBFS_EP_1_PRIOR USBFS_ep_1__INTC_PRIOR_NUM\r
+ #define USBFS_EP_1_MASK USBFS_ep_1__INTC_MASK\r
+ #define USBFS_EP_1_VECT_NUM USBFS_ep_1__INTC_NUMBER\r
+\r
+ #define USBFS_EP_2_PRIOR USBFS_ep_2__INTC_PRIOR_NUM\r
+ #define USBFS_EP_2_MASK USBFS_ep_2__INTC_MASK\r
+ #define USBFS_EP_2_VECT_NUM USBFS_ep_2__INTC_NUMBER\r
+\r
+ #define USBFS_EP_3_PRIOR USBFS_ep_3__INTC_PRIOR_NUM\r
+ #define USBFS_EP_3_MASK USBFS_ep_3__INTC_MASK\r
+ #define USBFS_EP_3_VECT_NUM USBFS_ep_3__INTC_NUMBER\r
+\r
+ #define USBFS_EP_4_PRIOR USBFS_ep_4__INTC_PRIOR_NUM\r
+ #define USBFS_EP_4_MASK USBFS_ep_4__INTC_MASK\r
+ #define USBFS_EP_4_VECT_NUM USBFS_ep_4__INTC_NUMBER\r
+\r
+ #define USBFS_EP_5_PRIOR USBFS_ep_5__INTC_PRIOR_NUM\r
+ #define USBFS_EP_5_MASK USBFS_ep_5__INTC_MASK\r
+ #define USBFS_EP_5_VECT_NUM USBFS_ep_5__INTC_NUMBER\r
+\r
+ #define USBFS_EP_6_PRIOR USBFS_ep_6__INTC_PRIOR_NUM\r
+ #define USBFS_EP_6_MASK USBFS_ep_6__INTC_MASK\r
+ #define USBFS_EP_6_VECT_NUM USBFS_ep_6__INTC_NUMBER\r
+\r
+ #define USBFS_EP_7_PRIOR USBFS_ep_7__INTC_PRIOR_NUM\r
+ #define USBFS_EP_7_MASK USBFS_ep_7__INTC_MASK\r
+ #define USBFS_EP_7_VECT_NUM USBFS_ep_7__INTC_NUMBER\r
+\r
+ #define USBFS_EP_8_PRIOR USBFS_ep_8__INTC_PRIOR_NUM\r
+ #define USBFS_EP_8_MASK USBFS_ep_8__INTC_MASK\r
+ #define USBFS_EP_8_VECT_NUM USBFS_ep_8__INTC_NUMBER\r
+\r
+ /* Set ARB ISR priority 0 to be highest for all EPX ISRs. */\r
+ #define USBFS_ARB_PRIOR (0u)\r
+ #define USBFS_ARB_MASK USBFS_arb_int__INTC_MASK\r
+ #define USBFS_ARB_VECT_NUM USBFS_arb_int__INTC_NUMBER\r
+#endif /* (CY_PSOC4) */\r
+\r
+\r
+/***************************************\r
+* Endpoint 0 offsets (Table 9-2)\r
+***************************************/\r
+#define USBFS_bmRequestTypeReg USBFS_EP0_DR_BASE.epData[0u]\r
+#define USBFS_bRequestReg USBFS_EP0_DR_BASE.epData[1u]\r
+#define USBFS_wValueLoReg USBFS_EP0_DR_BASE.epData[2u]\r
+#define USBFS_wValueHiReg USBFS_EP0_DR_BASE.epData[3u]\r
+#define USBFS_wIndexLoReg USBFS_EP0_DR_BASE.epData[4u]\r
+#define USBFS_wIndexHiReg USBFS_EP0_DR_BASE.epData[5u]\r
+#define USBFS_wLengthLoReg USBFS_EP0_DR_BASE.epData[6u]\r
+#define USBFS_wLengthHiReg USBFS_EP0_DR_BASE.epData[7u]\r
+\r
+/* Compatibility defines */\r
+#define USBFS_lengthLoReg USBFS_EP0_DR_BASE.epData[6u]\r
+#define USBFS_lengthHiReg USBFS_EP0_DR_BASE.epData[7u]\r
+\r
+\r
+/***************************************\r
+* Register Constants\r
+***************************************/\r
+\r
+#define USBFS_3500MV (3500u)\r
+#if (CY_PSOC4)\r
+ #define USBFS_VDDD_MV (CYDEV_VBUS_MV)\r
+#else\r
+ #define USBFS_VDDD_MV (CYDEV_VDDD_MV)\r
+#endif /* (CY_PSOC4) */\r
+\r
+\r
+/* USBFS_USB_CLK */\r
+#define USBFS_USB_CLK_CSR_CLK_EN_POS (0u)\r
+#define USBFS_USB_CLK_CSR_CLK_EN ((uint8) ((uint8) 0x1u << USBFS_USB_CLK_CSR_CLK_EN_POS))\r
+#define USBFS_USB_CLK_ENABLE (USBFS_USB_CLK_CSR_CLK_EN)\r
+\r
+/* USBFS_CR0 */\r
+#define USBFS_CR0_DEVICE_ADDRESS_POS (0u)\r
+#define USBFS_CR0_ENABLE_POS (7u)\r
+#define USBFS_CR0_DEVICE_ADDRESS_MASK ((uint8) ((uint8) 0x7Fu << USBFS_CR0_DEVICE_ADDRESS_POS))\r
+#define USBFS_CR0_ENABLE ((uint8) ((uint8) 0x01u << USBFS_CR0_ENABLE_POS))\r
+\r
+\r
+/* USBFS_CR1 */\r
+#define USBFS_CR1_REG_ENABLE_POS (0u)\r
+#define USBFS_CR1_ENABLE_LOCK_POS (1u)\r
+#define USBFS_CR1_BUS_ACTIVITY_POS (2u)\r
+#define USBFS_CR1_TRIM_OFFSET_MSB_POS (3u)\r
+#define USBFS_CR1_REG_ENABLE ((uint8) ((uint8) 0x1u << USBFS_CR1_REG_ENABLE_POS))\r
+#define USBFS_CR1_ENABLE_LOCK ((uint8) ((uint8) 0x1u << USBFS_CR1_ENABLE_LOCK_POS))\r
+#define USBFS_CR1_BUS_ACTIVITY ((uint8) ((uint8) 0x1u << USBFS_CR1_BUS_ACTIVITY_POS))\r
+#define USBFS_CR1_TRIM_OFFSET_MSB ((uint8) ((uint8) 0x1u << USBFS_CR1_TRIM_OFFSET_MSB_POS))\r
+\r
+/* USBFS_EPX_CNT */\r
+#define USBFS_EP0_CNT_DATA_TOGGLE (0x80u)\r
+#define USBFS_EPX_CNT_DATA_TOGGLE (0x80u)\r
+#define USBFS_EPX_CNT0_MASK (0x0Fu)\r
+#define USBFS_EPX_CNTX_MSB_MASK (0x07u)\r
+#define USBFS_EPX_CNTX_ADDR_SHIFT (0x04u)\r
+#define USBFS_EPX_CNTX_ADDR_OFFSET (0x10u)\r
+#define USBFS_EPX_CNTX_CRC_COUNT (0x02u)\r
+#define USBFS_EPX_DATA_BUF_MAX (512u)\r
+\r
+/* USBFS_USBIO_CR0 */\r
+\r
+#define USBFS_USBIO_CR0_TEN (0x80u)\r
+#define USBFS_USBIO_CR0_TSE0 (0x40u)\r
+#define USBFS_USBIO_CR0_TD (0x20u)\r
+#define USBFS_USBIO_CR0_RD (0x01u)\r
+\r
+/* USBFS_USBIO_CR1 */\r
+#define USBFS_USBIO_CR1_DM0_POS (0u)\r
+#define USBFS_USBIO_CR1_DP0_POS (1u)\r
+#define USBFS_USBIO_CR1_USBPUEN_POS (2u)\r
+#define USBFS_USBIO_CR1_IOMODE_POS (5u)\r
+#define USBFS_USBIO_CR1_DM0 ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_DM0_POS))\r
+#define USBFS_USBIO_CR1_DP0 ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_DP0_POS))\r
+#define USBFS_USBIO_CR1_USBPUEN ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_USBPUEN_POS))\r
+#define USBFS_USBIO_CR1_IOMODE ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_IOMODE_POS))\r
+\r
+/* USBFS_FASTCLK_IMO_CR */\r
+#define USBFS_FASTCLK_IMO_CR_USBCLK_ON (0x40u)\r
+#define USBFS_FASTCLK_IMO_CR_XCLKEN (0x20u)\r
+#define USBFS_FASTCLK_IMO_CR_FX2ON (0x10u)\r
\r
-#define USBFS_SIE_EP2_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT0)\r
-#define USBFS_SIE_EP2_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP2_CNT0)\r
-#define USBFS_SIE_EP2_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT1)\r
-#define USBFS_SIE_EP2_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP2_CNT1)\r
-#define USBFS_SIE_EP2_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CR0)\r
-#define USBFS_SIE_EP2_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP2_CR0)\r
-\r
-#define USBFS_SIE_EP3_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT0)\r
-#define USBFS_SIE_EP3_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP3_CNT0)\r
-#define USBFS_SIE_EP3_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT1)\r
-#define USBFS_SIE_EP3_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP3_CNT1)\r
-#define USBFS_SIE_EP3_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CR0)\r
-#define USBFS_SIE_EP3_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP3_CR0)\r
-\r
-#define USBFS_SIE_EP4_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT0)\r
-#define USBFS_SIE_EP4_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP4_CNT0)\r
-#define USBFS_SIE_EP4_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT1)\r
-#define USBFS_SIE_EP4_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP4_CNT1)\r
-#define USBFS_SIE_EP4_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CR0)\r
-#define USBFS_SIE_EP4_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP4_CR0)\r
-\r
-#define USBFS_SIE_EP5_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT0)\r
-#define USBFS_SIE_EP5_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP5_CNT0)\r
-#define USBFS_SIE_EP5_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT1)\r
-#define USBFS_SIE_EP5_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP5_CNT1)\r
-#define USBFS_SIE_EP5_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CR0)\r
-#define USBFS_SIE_EP5_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP5_CR0)\r
-\r
-#define USBFS_SIE_EP6_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT0)\r
-#define USBFS_SIE_EP6_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP6_CNT0)\r
-#define USBFS_SIE_EP6_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT1)\r
-#define USBFS_SIE_EP6_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP6_CNT1)\r
-#define USBFS_SIE_EP6_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CR0)\r
-#define USBFS_SIE_EP6_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP6_CR0)\r
-\r
-#define USBFS_SIE_EP7_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT0)\r
-#define USBFS_SIE_EP7_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP7_CNT0)\r
-#define USBFS_SIE_EP7_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT1)\r
-#define USBFS_SIE_EP7_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP7_CNT1)\r
-#define USBFS_SIE_EP7_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CR0)\r
-#define USBFS_SIE_EP7_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP7_CR0)\r
-\r
-#define USBFS_SIE_EP8_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT0)\r
-#define USBFS_SIE_EP8_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP8_CNT0)\r
-#define USBFS_SIE_EP8_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT1)\r
-#define USBFS_SIE_EP8_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP8_CNT1)\r
-#define USBFS_SIE_EP8_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CR0)\r
-#define USBFS_SIE_EP8_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP8_CR0)\r
-\r
-#define USBFS_SOF0_PTR ( (reg8 *) USBFS_USB__SOF0)\r
-#define USBFS_SOF0_REG (* (reg8 *) USBFS_USB__SOF0)\r
-#define USBFS_SOF1_PTR ( (reg8 *) USBFS_USB__SOF1)\r
-#define USBFS_SOF1_REG (* (reg8 *) USBFS_USB__SOF1)\r
-\r
-#define USBFS_USB_CLK_EN_PTR ( (reg8 *) USBFS_USB__USB_CLK_EN)\r
-#define USBFS_USB_CLK_EN_REG (* (reg8 *) USBFS_USB__USB_CLK_EN)\r
-\r
-#define USBFS_USBIO_CR0_PTR ( (reg8 *) USBFS_USB__USBIO_CR0)\r
-#define USBFS_USBIO_CR0_REG (* (reg8 *) USBFS_USB__USBIO_CR0)\r
-#define USBFS_USBIO_CR1_PTR ( (reg8 *) USBFS_USB__USBIO_CR1)\r
-#define USBFS_USBIO_CR1_REG (* (reg8 *) USBFS_USB__USBIO_CR1)\r
-#if(!CY_PSOC5LP)\r
- #define USBFS_USBIO_CR2_PTR ( (reg8 *) USBFS_USB__USBIO_CR2)\r
- #define USBFS_USBIO_CR2_REG (* (reg8 *) USBFS_USB__USBIO_CR2)\r
-#endif /* CY_PSOC5LP */\r
-\r
-#define USBFS_DIE_ID CYDEV_FLSHID_CUST_TABLES_BASE\r
-\r
-#define USBFS_PM_USB_CR0_PTR ( (reg8 *) CYREG_PM_USB_CR0)\r
-#define USBFS_PM_USB_CR0_REG (* (reg8 *) CYREG_PM_USB_CR0)\r
-#define USBFS_DYN_RECONFIG_PTR ( (reg8 *) USBFS_USB__DYN_RECONFIG)\r
-#define USBFS_DYN_RECONFIG_REG (* (reg8 *) USBFS_USB__DYN_RECONFIG)\r
-\r
-#define USBFS_DM_INP_DIS_PTR ( (reg8 *) USBFS_Dm__INP_DIS)\r
-#define USBFS_DM_INP_DIS_REG (* (reg8 *) USBFS_Dm__INP_DIS)\r
-#define USBFS_DP_INP_DIS_PTR ( (reg8 *) USBFS_Dp__INP_DIS)\r
-#define USBFS_DP_INP_DIS_REG (* (reg8 *) USBFS_Dp__INP_DIS)\r
-#define USBFS_DP_INTSTAT_PTR ( (reg8 *) USBFS_Dp__INTSTAT)\r
-#define USBFS_DP_INTSTAT_REG (* (reg8 *) USBFS_Dp__INTSTAT)\r
-\r
-#if (USBFS_MON_VBUS == 1u)\r
- #if (USBFS_EXTERN_VBUS == 0u)\r
- #define USBFS_VBUS_DR_PTR ( (reg8 *) USBFS_VBUS__DR)\r
- #define USBFS_VBUS_DR_REG (* (reg8 *) USBFS_VBUS__DR)\r
- #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_VBUS__PS)\r
- #define USBFS_VBUS_PS_REG (* (reg8 *) USBFS_VBUS__PS)\r
- #define USBFS_VBUS_MASK USBFS_VBUS__MASK\r
- #else\r
- #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG )\r
- #define USBFS_VBUS_MASK (0x01u)\r
- #endif /* USBFS_EXTERN_VBUS == 0u */\r
-#endif /* USBFS_MON_VBUS */\r
-\r
-/* Renamed Registers for backward compatibility.\r
-* Should not be used in new designs.\r
+/* USBFS_ARB_EPX_CFG */\r
+#define USBFS_ARB_EPX_CFG_IN_DATA_RDY_POS (0u)\r
+#define USBFS_ARB_EPX_CFG_DMA_REQ_POS (1u)\r
+#define USBFS_ARB_EPX_CFG_CRC_BYPASS_POS (2u)\r
+#define USBFS_ARB_EPX_CFG_RESET_POS (3u)\r
+#define USBFS_ARB_EPX_CFG_IN_DATA_RDY ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_IN_DATA_RDY_POS))\r
+#define USBFS_ARB_EPX_CFG_DMA_REQ ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_DMA_REQ_POS))\r
+#define USBFS_ARB_EPX_CFG_CRC_BYPASS ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_CRC_BYPASS_POS))\r
+#define USBFS_ARB_EPX_CFG_RESET ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_RESET_POS))\r
+\r
+/* USBFS_ARB_EPX_INT / SR */\r
+#define USBFS_ARB_EPX_INT_IN_BUF_FULL_POS (0u)\r
+#define USBFS_ARB_EPX_INT_DMA_GNT_POS (1u)\r
+#define USBFS_ARB_EPX_INT_BUF_OVER_POS (2u)\r
+#define USBFS_ARB_EPX_INT_BUF_UNDER_POS (3u)\r
+#define USBFS_ARB_EPX_INT_ERR_INT_POS (4u)\r
+#define USBFS_ARB_EPX_INT_IN_BUF_FULL ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_IN_BUF_FULL_POS))\r
+#define USBFS_ARB_EPX_INT_DMA_GNT ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_DMA_GNT_POS))\r
+#define USBFS_ARB_EPX_INT_BUF_OVER ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_BUF_OVER_POS))\r
+#define USBFS_ARB_EPX_INT_BUF_UNDER ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_BUF_UNDER_POS))\r
+#define USBFS_ARB_EPX_INT_ERR_INT ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_ERR_INT_POS))\r
+\r
+#if (CY_PSOC4)\r
+#define USBFS_ARB_EPX_INT_DMA_TERMIN_POS (5u)\r
+#define USBFS_ARB_EPX_INT_DMA_TERMIN ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_DMA_TERMIN_POS))\r
+#endif /* (CY_PSOC4) */\r
+\r
+/* Common arbiter interrupt sources for all PSoC devices. */\r
+#define USBFS_ARB_EPX_INT_COMMON (USBFS_ARB_EPX_INT_IN_BUF_FULL | \\r
+ USBFS_ARB_EPX_INT_DMA_GNT | \\r
+ USBFS_ARB_EPX_INT_BUF_OVER | \\r
+ USBFS_ARB_EPX_INT_BUF_UNDER | \\r
+ USBFS_ARB_EPX_INT_ERR_INT)\r
+\r
+#if (CY_PSOC4)\r
+ #define USBFS_ARB_EPX_INT_ALL (USBFS_ARB_EPX_INT_COMMON | USBFS_ARB_EPX_INT_DMA_TERMIN)\r
+#else\r
+ #define USBFS_ARB_EPX_INT_ALL (USBFS_ARB_EPX_INT_COMMON)\r
+#endif /* (CY_PSOC4) */\r
+\r
+/* USBFS_ARB_CFG */\r
+#define USBFS_ARB_CFG_AUTO_MEM_POS (4u)\r
+#define USBFS_ARB_CFG_DMA_CFG_POS (5u)\r
+#define USBFS_ARB_CFG_CFG_CMP_POS (7u)\r
+#define USBFS_ARB_CFG_AUTO_MEM ((uint8) ((uint8) 0x1u << USBFS_ARB_CFG_AUTO_MEM_POS))\r
+#define USBFS_ARB_CFG_DMA_CFG_MASK ((uint8) ((uint8) 0x3u << USBFS_ARB_CFG_DMA_CFG_POS))\r
+#define USBFS_ARB_CFG_DMA_CFG_NONE ((uint8) ((uint8) 0x0u << USBFS_ARB_CFG_DMA_CFG_POS))\r
+#define USBFS_ARB_CFG_DMA_CFG_MANUAL ((uint8) ((uint8) 0x1u << USBFS_ARB_CFG_DMA_CFG_POS))\r
+#define USBFS_ARB_CFG_DMA_CFG_AUTO ((uint8) ((uint8) 0x2u << USBFS_ARB_CFG_DMA_CFG_POS))\r
+#define USBFS_ARB_CFG_CFG_CMP ((uint8) ((uint8) 0x1u << USBFS_ARB_CFG_CFG_CMP_POS))\r
+\r
+/* USBFS_DYN_RECONFIG */\r
+#define USBFS_DYN_RECONFIG_EP_SHIFT (1u)\r
+#define USBFS_DYN_RECONFIG_ENABLE_POS (0u)\r
+#define USBFS_DYN_RECONFIG_EPNO_POS (1u)\r
+#define USBFS_DYN_RECONFIG_RDY_STS_POS (4u)\r
+#define USBFS_DYN_RECONFIG_ENABLE ((uint8) ((uint8) 0x1u << USBFS_DYN_RECONFIG_ENABLE_POS))\r
+#define USBFS_DYN_RECONFIG_EPNO_MASK ((uint8) ((uint8) 0x7u << USBFS_DYN_RECONFIG_EPNO_POS))\r
+#define USBFS_DYN_RECONFIG_RDY_STS ((uint8) ((uint8) 0x1u << USBFS_DYN_RECONFIG_RDY_STS_POS))\r
+\r
+/* USBFS_ARB_INT */\r
+#define USBFS_ARB_INT_EP1_INTR_POS (0u) /* [0] Interrupt for USB EP1 */\r
+#define USBFS_ARB_INT_EP2_INTR_POS (1u) /* [1] Interrupt for USB EP2 */\r
+#define USBFS_ARB_INT_EP3_INTR_POS (2u) /* [2] Interrupt for USB EP3 */\r
+#define USBFS_ARB_INT_EP4_INTR_POS (3u) /* [3] Interrupt for USB EP4 */\r
+#define USBFS_ARB_INT_EP5_INTR_POS (4u) /* [4] Interrupt for USB EP5 */\r
+#define USBFS_ARB_INT_EP6_INTR_POS (5u) /* [5] Interrupt for USB EP6 */\r
+#define USBFS_ARB_INT_EP7_INTR_POS (6u) /* [6] Interrupt for USB EP7 */\r
+#define USBFS_ARB_INT_EP8_INTR_POS (7u) /* [7] Interrupt for USB EP8 */\r
+#define USBFS_ARB_INT_EP1_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP1_INTR_POS))\r
+#define USBFS_ARB_INT_EP2_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP2_INTR_POS))\r
+#define USBFS_ARB_INT_EP3_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP3_INTR_POS))\r
+#define USBFS_ARB_INT_EP4_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP4_INTR_POS))\r
+#define USBFS_ARB_INT_EP5_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP5_INTR_POS))\r
+#define USBFS_ARB_INT_EP6_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP6_INTR_POS))\r
+#define USBFS_ARB_INT_EP7_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP7_INTR_POS))\r
+#define USBFS_ARB_INT_EP8_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP8_INTR_POS))\r
+\r
+/* USBFS_SIE_INT */\r
+#define USBFS_SIE_INT_EP1_INTR_POS (0u) /* [0] Interrupt for USB EP1 */\r
+#define USBFS_SIE_INT_EP2_INTR_POS (1u) /* [1] Interrupt for USB EP2 */\r
+#define USBFS_SIE_INT_EP3_INTR_POS (2u) /* [2] Interrupt for USB EP3 */\r
+#define USBFS_SIE_INT_EP4_INTR_POS (3u) /* [3] Interrupt for USB EP4 */\r
+#define USBFS_SIE_INT_EP5_INTR_POS (4u) /* [4] Interrupt for USB EP5 */\r
+#define USBFS_SIE_INT_EP6_INTR_POS (5u) /* [5] Interrupt for USB EP6 */\r
+#define USBFS_SIE_INT_EP7_INTR_POS (6u) /* [6] Interrupt for USB EP7 */\r
+#define USBFS_SIE_INT_EP8_INTR_POS (7u) /* [7] Interrupt for USB EP8 */\r
+#define USBFS_SIE_INT_EP1_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP1_INTR_POS))\r
+#define USBFS_SIE_INT_EP2_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP2_INTR_POS))\r
+#define USBFS_SIE_INT_EP3_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP3_INTR_POS))\r
+#define USBFS_SIE_INT_EP4_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP4_INTR_POS))\r
+#define USBFS_SIE_INT_EP5_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP5_INTR_POS))\r
+#define USBFS_SIE_INT_EP6_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP6_INTR_POS))\r
+#define USBFS_SIE_INT_EP7_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP7_INTR_POS))\r
+#define USBFS_SIE_INT_EP8_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP8_INTR_POS))\r
+\r
+#if (CY_PSOC4)\r
+ /* USBFS_POWER_CTRL_REG */\r
+ #define USBFS_POWER_CTRL_VBUS_VALID_OVR_POS (0u) /* [0] */\r
+ #define USBFS_POWER_CTRL_SUSPEND_POS (2u) /* [1] */\r
+ #define USBFS_POWER_CTRL_SUSPEND_DEL_POS (3u) /* [3] */\r
+ #define USBFS_POWER_CTRL_ISOLATE_POS (4u) /* [4] */\r
+ #define USBFS_POWER_CTRL_CHDET_PWR_CTL_POS (5u) /* [5] */\r
+ #define USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN_POS (25u) /* [25] */\r
+ #define USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN_POS (26u) /* [26] */\r
+ #define USBFS_POWER_CTRL_ENABLE_RCVR_POS (27u) /* [27] */\r
+ #define USBFS_POWER_CTRL_ENABLE_DPO_POS (28u) /* [28] */\r
+ #define USBFS_POWER_CTRL_ENABLE_DMO_POS (29u) /* [29] */\r
+ #define USBFS_POWER_CTRL_ENABLE_CHGDET_POS (30u) /* [30] */\r
+ #define USBFS_POWER_CTRL_ENABLE_POS (31u) /* [31] */\r
+ #define USBFS_POWER_CTRL_VBUS_VALID_OVR_MASK ((uint32) 0x03u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS)\r
+ #define USBFS_POWER_CTRL_VBUS_VALID_OVR_0 ((uint32) 0x00u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS)\r
+ #define USBFS_POWER_CTRL_VBUS_VALID_OVR_1 ((uint32) 0x01u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS)\r
+ #define USBFS_POWER_CTRL_VBUS_VALID_OVR_GPIO ((uint32) 0x02u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS)\r
+ #define USBFS_POWER_CTRL_VBUS_VALID_OVR_PHY ((uint32) 0x03u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS)\r
+ #define USBFS_POWER_CTRL_SUSPEND ((uint32) 0x01u << USBFS_POWER_CTRL_SUSPEND_POS)\r
+ #define USBFS_POWER_CTRL_SUSPEND_DEL ((uint32) 0x01u << USBFS_POWER_CTRL_SUSPEND_DEL_POS)\r
+ #define USBFS_POWER_CTRL_ISOLATE ((uint32) 0x01u << USBFS_POWER_CTRL_ISOLATE_POS)\r
+ #define USBFS_POWER_CTRL_CHDET_PWR_CTL_MASK ((uint32) 0x03u << USBFS_POWER_CTRL_CHDET_PWR_CTL_POS)\r
+ #define USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN_POS)\r
+ #define USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN_POS)\r
+ #define USBFS_POWER_CTRL_ENABLE_RCVR ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_RCVR_POS)\r
+ #define USBFS_POWER_CTRL_ENABLE_DPO ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_DPO_POS)\r
+ #define USBFS_POWER_CTRL_ENABLE_DMO ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_DMO_POS)\r
+ #define USBFS_POWER_CTRL_ENABLE_CHGDET ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_CHGDET_POS)\r
+ #define USBFS_POWER_CTRL_ENABLE ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_POS)\r
+\r
+ /* USBFS_CHGDET_CTRL_REG */\r
+ #define USBFS_CHGDET_CTRL_COMP_DP_POS (0u) /* [0] */\r
+ #define USBFS_CHGDET_CTRL_COMP_DM_POS (1u) /* [1] */\r
+ #define USBFS_CHGDET_CTRL_COMP_EN_POS (2u) /* [2] */\r
+ #define USBFS_CHGDET_CTRL_REF_DP_POS (3u) /* [3] */\r
+ #define USBFS_CHGDET_CTRL_REF_DM_POS (4u) /* [4] */\r
+ #define USBFS_CHGDET_CTRL_REF_EN_POS (5u) /* [5] */\r
+ #define USBFS_CHGDET_CTRL_DCD_SRC_EN_POS (6u) /* [6] */\r
+ #define USBFS_CHGDET_CTRL_ADFT_CTRL_POS (12u) /* [12] */\r
+ #define USBFS_CHGDET_CTRL_COMP_OUT_POS (31u) /* [31] */\r
+ #define USBFS_CHGDET_CTRL_COMP_DP ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_DP_POS)\r
+ #define USBFS_CHGDET_CTRL_COMP_DM ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_DM_POS)\r
+ #define USBFS_CHGDET_CTRL_COMP_EN ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_EN_POS)\r
+ #define USBFS_CHGDET_CTRL_REF_DP ((uint32) 0x01u << USBFS_CHGDET_CTRL_REF_DP_POS)\r
+ #define USBFS_CHGDET_CTRL_REF_DM ((uint32) 0x01u << USBFS_CHGDET_CTRL_REF_DM_POS)\r
+ #define USBFS_CHGDET_CTRL_REF_EN ((uint32) 0x01u << USBFS_CHGDET_CTRL_REF_EN_POS)\r
+ #define USBFS_CHGDET_CTRL_DCD_SRC_EN ((uint32) 0x01u << USBFS_CHGDET_CTRL_DCD_SRC_EN_POS)\r
+ #define USBFS_CHGDET_CTRL_ADFT_CTRL_MASK ((uint32) 0x03u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS)\r
+ #define USBFS_CHGDET_CTRL_ADFT_CTRL_NORMAL ((uint32) 0x00u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS)\r
+ #define USBFS_CHGDET_CTRL_ADFT_CTRL_VBG ((uint32) 0x01u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS)\r
+ #define USBFS_CHGDET_CTRL_ADFT_CTRL_DONTUSE ((uint32) 0x02u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS)\r
+ #define USBFS_CHGDET_CTRL_ADFT_CTRL_ADFTIN ((uint32) 0x03u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS)\r
+ #define USBFS_CHGDET_CTRL_COMP_OUT ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_OUT_POS)\r
+\r
+ /* USBFS_LPM_CTRL */\r
+ #define USBFS_LPM_CTRL_LPM_EN_POS (0u)\r
+ #define USBFS_LPM_CTRL_LPM_ACK_RESP_POS (1u)\r
+ #define USBFS_LPM_CTRL_NYET_EN_POS (2u)\r
+ #define USBFS_LPM_CTRL_SUB_RESP_POS (4u)\r
+ #define USBFS_LPM_CTRL_LPM_EN ((uint32) 0x01u << USBFS_LPM_CTRL_LPM_EN_POS)\r
+ #define USBFS_LPM_CTRL_LPM_ACK_RESP ((uint32) 0x01u << USBFS_LPM_CTRL_LPM_ACK_RESP_POS)\r
+ #define USBFS_LPM_CTRL_NYET_EN ((uint32) 0x01u << USBFS_LPM_CTRL_NYET_EN_POS)\r
+ #define USBFS_LPM_CTRL_ACK_NYET_MASK ((uint32) 0x03u << USBFS_LPM_CTRL_LPM_ACK_RESP_POS)\r
+ #define USBFS_LPM_CTRL_SUB_RESP ((uint32) 0x01u << USBFS_LPM_CTRL_SUB_RESP_POS)\r
+\r
+ #define USBFS_LPM_STAT_LPM_BESL_POS (0u)\r
+ #define USBFS_LPM_STAT_LPM_REMOTE_WAKE_POS (4u)\r
+ #define USBFS_LPM_STAT_LPM_BESL_MASK ((uint32) 0x0Fu << USBFS_LPM_STAT_LPM_BESL_POS)\r
+ #define USBFS_LPM_STAT_LPM_REMOTE_WAKE ((uint32) 0x01u << USBFS_LPM_STAT_LPM_REMOTE_WAKE_POS)\r
+\r
+ /* USBFS_INTR_SIE */\r
+ #define USBFS_INTR_SIE_SOF_INTR_POS (0u) /* [0] Interrupt for USB SOF */\r
+ #define USBFS_INTR_SIE_BUS_RESET_INTR_POS (1u) /* [1] Interrupt for BUS RESET */\r
+ #define USBFS_INTR_SIE_EP0_INTR_POS (2u) /* [2] Interrupt for EP0 */\r
+ #define USBFS_INTR_SIE_LPM_INTR_POS (3u) /* [3] Interrupt for LPM */\r
+ #define USBFS_INTR_SIE_RESUME_INTR_POS (4u) /* [4] Interrupt for RESUME (not used by component) */\r
+ #define USBFS_INTR_SIE_SOF_INTR ((uint32) 0x01u << USBFS_INTR_SIE_SOF_INTR_POS)\r
+ #define USBFS_INTR_SIE_BUS_RESET_INTR ((uint32) 0x01u << USBFS_INTR_SIE_BUS_RESET_INTR_POS)\r
+ #define USBFS_INTR_SIE_EP0_INTR ((uint32) 0x01u << USBFS_INTR_SIE_EP0_INTR_POS)\r
+ #define USBFS_INTR_SIE_LPM_INTR ((uint32) 0x01u << USBFS_INTR_SIE_LPM_INTR_POS)\r
+ #define USBFS_INTR_SIE_RESUME_INTR ((uint32) 0x01u << USBFS_INTR_SIE_RESUME_INTR_POS)\r
+\r
+ /* USBFS_INTR_CAUSE_LO, MED and HI */\r
+ #define USBFS_INTR_CAUSE_SOF_INTR_POS (0u) /* [0] Interrupt status for USB SOF */\r
+ #define USBFS_INTR_CAUSE_BUS_RESET_INTR_POS (1u) /* [1] Interrupt status for USB BUS RSET */\r
+ #define USBFS_INTR_CAUSE_EP0_INTR_POS (2u) /* [2] Interrupt status for USB EP0 */\r
+ #define USBFS_INTR_CAUSE_LPM_INTR_POS (3u) /* [3] Interrupt status for USB LPM */\r
+ #define USBFS_INTR_CAUSE_RESUME_INTR_POS (4u) /* [4] Interrupt status for USB RESUME */\r
+ #define USBFS_INTR_CAUSE_ARB_INTR_POS (7u) /* [7] Interrupt status for USB ARB */\r
+ #define USBFS_INTR_CAUSE_EP1_INTR_POS (8u) /* [8] Interrupt status for USB EP1 */\r
+ #define USBFS_INTR_CAUSE_EP2_INTR_POS (9u) /* [9] Interrupt status for USB EP2 */\r
+ #define USBFS_INTR_CAUSE_EP3_INTR_POS (10u) /* [10] Interrupt status for USB EP3 */\r
+ #define USBFS_INTR_CAUSE_EP4_INTR_POS (11u) /* [11] Interrupt status for USB EP4 */\r
+ #define USBFS_INTR_CAUSE_EP5_INTR_POS (12u) /* [12] Interrupt status for USB EP5 */\r
+ #define USBFS_INTR_CAUSE_EP6_INTR_POS (13u) /* [13] Interrupt status for USB EP6 */\r
+ #define USBFS_INTR_CAUSE_EP7_INTR_POS (14u) /* [14] Interrupt status for USB EP7 */\r
+ #define USBFS_INTR_CAUSE_EP8_INTR_POS (15u) /* [15] Interrupt status for USB EP8 */\r
+ #define USBFS_INTR_CAUSE_SOF_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_SOF_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_BUS_RESET_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_BUS_RESET_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP0_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP0_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_LPM_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_LPM_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_RESUME_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_RESUME_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_ARB_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_ARB_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP1_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP1_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP2_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP2_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP3_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP3_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP4_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP4_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP5_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP5_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP6_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP6_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP7_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP7_INTR_POS)\r
+ #define USBFS_INTR_CAUSE_EP8_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP8_INTR_POS)\r
+\r
+ #define USBFS_INTR_CAUSE_CTRL_INTR_MASK (USBFS_INTR_CAUSE_SOF_INTR | \\r
+ USBFS_INTR_CAUSE_BUS_RESET_INTR | \\r
+ USBFS_INTR_CAUSE_EP0_INTR | \\r
+ USBFS_INTR_CAUSE_LPM_INTR)\r
+\r
+ #define USBFS_INTR_CAUSE_EP1_8_INTR_MASK (USBFS_INTR_CAUSE_EP1_INTR | \\r
+ USBFS_INTR_CAUSE_EP2_INTR | \\r
+ USBFS_INTR_CAUSE_EP3_INTR | \\r
+ USBFS_INTR_CAUSE_EP4_INTR | \\r
+ USBFS_INTR_CAUSE_EP5_INTR | \\r
+ USBFS_INTR_CAUSE_EP6_INTR | \\r
+ USBFS_INTR_CAUSE_EP7_INTR | \\r
+ USBFS_INTR_CAUSE_EP8_INTR)\r
+\r
+ #define USBFS_INTR_CAUSE_EP_INTR_SHIFT (USBFS_INTR_CAUSE_ARB_INTR_POS - \\r
+ (USBFS_INTR_CAUSE_LPM_INTR_POS + 1u))\r
+ #define USBFS_INTR_CAUSE_SRC_COUNT (13u)\r
+\r
+ #define USBFS_CHGDET_CTRL_PRIMARY (USBFS_CHGDET_CTRL_COMP_EN | \\r
+ USBFS_CHGDET_CTRL_COMP_DM | \\r
+ USBFS_CHGDET_CTRL_REF_EN | \\r
+ USBFS_CHGDET_CTRL_REF_DP)\r
+\r
+ #define USBFS_CHGDET_CTRL_SECONDARY (USBFS_CHGDET_CTRL_COMP_EN | \\r
+ USBFS_CHGDET_CTRL_COMP_DP | \\r
+ USBFS_CHGDET_CTRL_REF_EN | \\r
+ USBFS_CHGDET_CTRL_REF_DM)\r
+\r
+ #define USBFS_CHGDET_CTRL_DEFAULT (0x00000900u)\r
+\r
+\r
+#else /* (CY_PSOC3 || CY_PSOC5LP) */\r
+ #define USBFS_PM_ACT_EN_FSUSB USBFS_USB__PM_ACT_MSK\r
+ #define USBFS_PM_STBY_EN_FSUSB USBFS_USB__PM_STBY_MSK\r
+ #define USBFS_PM_AVAIL_EN_FSUSBIO (0x10u)\r
+\r
+ #define USBFS_PM_USB_CR0_REF_EN (0x01u)\r
+ #define USBFS_PM_USB_CR0_PD_N (0x02u)\r
+ #define USBFS_PM_USB_CR0_PD_PULLUP_N (0x04u)\r
+#endif /* (CY_PSOC4) */\r
+\r
+\r
+/***************************************\r
+* Macros Definitions\r
+***************************************/\r
+\r
+#if (CY_PSOC4)\r
+ #define USBFS_ClearSieInterruptSource(intMask) \\r
+ do{ \\r
+ USBFS_INTR_SIE_REG = (uint32) (intMask); \\r
+ }while(0)\r
+#else\r
+ #define USBFS_ClearSieInterruptSource(intMask) \\r
+ do{ /* Does nothing. */ }while(0)\r
+#endif /* (CY_PSOC4) */\r
+\r
+#define USBFS_ClearSieEpInterruptSource(intMask) \\r
+ do{ \\r
+ USBFS_SIE_EP_INT_SR_REG = (uint8) (intMask); \\r
+ }while(0)\r
+\r
+#define USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType) (((epType) == USBFS_EP_TYPE_ISOC) ? \\r
+ (USBFS_MODE_ISO_IN) : (USBFS_MODE_ACK_IN))\r
+\r
+#define USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType) (((epType) == USBFS_EP_TYPE_ISOC) ? \\r
+ (USBFS_MODE_ISO_OUT) : (USBFS_MODE_ACK_OUT))\r
+\r
+#define USBFS_GET_EP_TYPE(epNumber) (USBFS_EP[epNumber].attrib & USBFS_EP_TYPE_MASK)\r
+\r
+#define USBFS_GET_UINT16(hi, low) (((uint16) ((uint16) (hi) << 8u)) | ((uint16) (low) & 0xFFu))\r
+\r
+\r
+/***************************************\r
+* Initialization Register Settings\r
+***************************************/\r
+\r
+/* Clear device address and enable USB IP respond to USB traffic. */\r
+#define USBFS_DEFUALT_CR0 (USBFS_CR0_ENABLE)\r
+\r
+/* Arbiter configuration depends on memory management mode. */\r
+#define USBFS_DEFAULT_ARB_CFG ((USBFS_EP_MANAGEMENT_MANUAL) ? (USBFS_ARB_CFG_DMA_CFG_NONE) : \\r
+ ((USBFS_EP_MANAGEMENT_DMA_MANUAL) ? \\r
+ (USBFS_ARB_CFG_DMA_CFG_MANUAL) : \\r
+ (USBFS_ARB_CFG_AUTO_MEM | USBFS_ARB_CFG_DMA_CFG_AUTO)))\r
+\r
+/* Enable arbiter interrupt for active endpoints only */\r
+#define USBFS_DEFAULT_ARB_INT_EN \\r
+ ((uint8) ((uint8) USBFS_DMA1_ACTIVE << USBFS_ARB_INT_EP1_INTR_POS) | \\r
+ (uint8) ((uint8) USBFS_DMA2_ACTIVE << USBFS_ARB_INT_EP2_INTR_POS) | \\r
+ (uint8) ((uint8) USBFS_DMA3_ACTIVE << USBFS_ARB_INT_EP3_INTR_POS) | \\r
+ (uint8) ((uint8) USBFS_DMA4_ACTIVE << USBFS_ARB_INT_EP4_INTR_POS) | \\r
+ (uint8) ((uint8) USBFS_DMA5_ACTIVE << USBFS_ARB_INT_EP5_INTR_POS) | \\r
+ (uint8) ((uint8) USBFS_DMA6_ACTIVE << USBFS_ARB_INT_EP6_INTR_POS) | \\r
+ (uint8) ((uint8) USBFS_DMA7_ACTIVE << USBFS_ARB_INT_EP7_INTR_POS) | \\r
+ (uint8) ((uint8) USBFS_DMA8_ACTIVE << USBFS_ARB_INT_EP8_INTR_POS))\r
+\r
+/* Enable all SIE endpoints interrupts */\r
+#define USBFS_DEFAULT_SIE_EP_INT_EN (USBFS_SIE_INT_EP1_INTR | \\r
+ USBFS_SIE_INT_EP2_INTR | \\r
+ USBFS_SIE_INT_EP3_INTR | \\r
+ USBFS_SIE_INT_EP4_INTR | \\r
+ USBFS_SIE_INT_EP5_INTR | \\r
+ USBFS_SIE_INT_EP6_INTR | \\r
+ USBFS_SIE_INT_EP7_INTR | \\r
+ USBFS_SIE_INT_EP8_INTR)\r
+\r
+#define USBFS_ARB_EPX_CFG_DEFAULT (USBFS_ARB_EPX_CFG_RESET | \\r
+ USBFS_ARB_EPX_CFG_CRC_BYPASS)\r
+\r
+/* Default EP arbiter interrupt source register */\r
+#define USBFS_ARB_EPX_INT_COMMON_MASK (USBFS_ARB_EPX_INT_IN_BUF_FULL | \\r
+ USBFS_ARB_EPX_INT_BUF_OVER | \\r
+ USBFS_ARB_EPX_INT_BUF_UNDER | \\r
+ USBFS_ARB_EPX_INT_ERR_INT | \\r
+ (USBFS_EP_MANAGEMENT_DMA_MANUAL ? USBFS_ARB_EPX_INT_DMA_GNT : 0u))\r
+\r
+#define USBFS_CLEAR_REG (0u)\r
+\r
+#if (CY_PSOC4)\r
+ /* Set USB lock option when IMO is locked to USB traffic. */\r
+ #define USBFS_DEFUALT_CR1 ((0u != CySysClkImoGetUsbLock()) ? (USBFS_CR1_ENABLE_LOCK) : (0u))\r
+\r
+ /* Recommended value is increased from 3 to 10 due to suppress glitch on \r
+ * RSE0 with USB2.0 hubs (LF CLK = 32kHz equal to 350us). */\r
+ #define USBFS_DEFUALT_BUS_RST_CNT (10u)\r
+\r
+ /* Select VBUS sources as: valid, PHY of GPIO, and clears isolate bit. */\r
+ /* Application level must ensure that VBUS is valid valid to use. */\r
+ #define USBFS_DEFAULT_POWER_CTRL_VBUS (USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN | \\r
+ ((!USBFS_VBUS_MONITORING_ENABLE) ? \\r
+ (USBFS_POWER_CTRL_VBUS_VALID_OVR_1) : \\r
+ (USBFS_VBUS_POWER_PAD_ENABLE ? \\r
+ (USBFS_POWER_CTRL_VBUS_VALID_OVR_PHY) : \\r
+ (USBFS_POWER_CTRL_VBUS_VALID_OVR_GPIO))))\r
+ /* Enable USB IP. */\r
+ #define USBFS_DEFAULT_POWER_CTRL_PHY (USBFS_POWER_CTRL_SUSPEND | \\r
+ USBFS_POWER_CTRL_SUSPEND_DEL | \\r
+ USBFS_POWER_CTRL_ENABLE_RCVR | \\r
+ USBFS_POWER_CTRL_ENABLE_DPO | \\r
+ USBFS_POWER_CTRL_ENABLE_DMO | \\r
+ USBFS_POWER_CTRL_ENABLE)\r
+\r
+ /* Assign interrupt between levels lo, med, hi. */\r
+ #define USBFS_DEFAULT_INTR_LVL_SEL ((uint32) (USBFS_INTR_LVL_SEL))\r
+\r
+ /* Enable interrupt source in the INTR_SIE. The SOF is always disabled and EP0 is enabled. */\r
+ #define USBFS_DEFAULT_INTR_SIE_MASK \\r
+ ((uint32) ((uint32) USBFS_BUS_RESET_ISR_ACTIVE << USBFS_INTR_SIE_BUS_RESET_INTR_POS) | \\r
+ (uint32) ((uint32) USBFS_SOF_ISR_ACTIVE << USBFS_INTR_SIE_SOF_INTR_POS) | \\r
+ (uint32) ((uint32) USBFS_LPM_ACTIVE << USBFS_INTR_SIE_LPM_INTR_POS) | \\r
+ (uint32) ((uint32) USBFS_INTR_SIE_EP0_INTR))\r
+\r
+ /* Arbiter interrupt sources */\r
+ #define USBFS_ARB_EPX_INT_MASK (USBFS_ARB_EPX_INT_COMMON_MASK | \\r
+ (USBFS_EP_MANAGEMENT_DMA_AUTO ? USBFS_ARB_EPX_INT_DMA_TERMIN : 0u))\r
+\r
+ /* Common DMA configuration */\r
+ #define USBFS_DMA_COMMON_CFG (CYDMA_PULSE | CYDMA_ENTIRE_DESCRIPTOR | \\r
+ CYDMA_NON_PREEMPTABLE)\r
+\r
+\r
+#else\r
+ #define USBFS_ARB_EPX_INT_MASK (USBFS_ARB_EPX_INT_COMMON_MASK)\r
+\r
+ #define USBFS_DEFUALT_CR1 (USBFS_CR1_ENABLE_LOCK)\r
+\r
+ /* Recommended value is 3 for LF CLK = 100kHz equal to 100us. */\r
+ #define USBFS_DEFUALT_BUS_RST_CNT (10u)\r
+#endif /* (CY_PSOC4) */\r
+\r
+/*\r
+* \addtogroup group_deprecated\r
+* @{\r
*/\r
+\r
+/***************************************\r
+* The following code is DEPRECATED and\r
+* must not be used.\r
+***************************************/\r
+\r
+/* Renamed type definitions */\r
+#define USBFS_CODE CYCODE\r
+#define USBFS_FAR CYFAR\r
+#if defined(__C51__) || defined(__CX51__)\r
+ #define USBFS_DATA data\r
+ #define USBFS_XDATA xdata\r
+#else\r
+ #define USBFS_DATA\r
+ #define USBFS_XDATA\r
+#endif /* __C51__ */\r
+#define USBFS_NULL NULL\r
+/** @} deprecated */\r
+/* Renamed structure fields */\r
+#define wBuffOffset buffOffset\r
+#define wBufferSize bufferSize\r
+#define bStatus status\r
+#define wLength length\r
+#define wCount count\r
+\r
+/* Renamed global variable */\r
+#define CurrentTD USBFS_currentTD\r
+#define USBFS_interfaceSetting_last USBFS_interfaceSettingLast\r
+\r
+/* Renamed global constants */\r
+#define USBFS_DWR_VDDD_OPERATION (USBFS_DWR_POWER_OPERATION)\r
+\r
+/* Renamed functions */\r
+#define USBFS_bCheckActivity USBFS_CheckActivity\r
+#define USBFS_bGetConfiguration USBFS_GetConfiguration\r
+#define USBFS_bGetInterfaceSetting USBFS_GetInterfaceSetting\r
+#define USBFS_bGetEPState USBFS_GetEPState\r
+#define USBFS_wGetEPCount USBFS_GetEPCount\r
+#define USBFS_bGetEPAckState USBFS_GetEPAckState\r
+#define USBFS_bRWUEnabled USBFS_RWUEnabled\r
+#define USBFS_bVBusPresent USBFS_VBusPresent\r
+\r
+#define USBFS_bConfiguration USBFS_configuration\r
+#define USBFS_bInterfaceSetting USBFS_interfaceSetting\r
+#define USBFS_bDeviceAddress USBFS_deviceAddress\r
+#define USBFS_bDeviceStatus USBFS_deviceStatus\r
+#define USBFS_bDevice USBFS_device\r
+#define USBFS_bTransferState USBFS_transferState\r
+#define USBFS_bLastPacketSize USBFS_lastPacketSize\r
+\r
+#define USBFS_LoadEP USBFS_LoadInEP\r
+#define USBFS_LoadInISOCEP USBFS_LoadInEP\r
+#define USBFS_EnableOutISOCEP USBFS_EnableOutEP\r
+\r
+#define USBFS_SetVector CyIntSetVector\r
+#define USBFS_SetPriority CyIntSetPriority\r
+#define USBFS_EnableInt CyIntEnable\r
+\r
+/* Replace with register access. */\r
+#define USBFS_bmRequestType USBFS_EP0_DR0_PTR\r
+#define USBFS_bRequest USBFS_EP0_DR1_PTR\r
+#define USBFS_wValue USBFS_EP0_DR2_PTR\r
+#define USBFS_wValueHi USBFS_EP0_DR3_PTR\r
+#define USBFS_wValueLo USBFS_EP0_DR2_PTR\r
+#define USBFS_wIndex USBFS_EP0_DR4_PTR\r
+#define USBFS_wIndexHi USBFS_EP0_DR5_PTR\r
+#define USBFS_wIndexLo USBFS_EP0_DR4_PTR\r
+#define USBFS_length USBFS_EP0_DR6_PTR\r
+#define USBFS_lengthHi USBFS_EP0_DR7_PTR\r
+#define USBFS_lengthLo USBFS_EP0_DR6_PTR\r
+\r
+/* Rename VBUS monitoring registers. */\r
+#if (CY_PSOC3 || CY_PSOC5LP)\r
+ #if (USBFS_VBUS_MONITORING_ENABLE)\r
+ #if (USBFS_VBUS_MONITORING_INTERNAL)\r
+ #define USBFS_VBUS_DR_PTR ( (reg8 *) USBFS_VBUS__DR)\r
+ #define USBFS_VBUS_DR_REG (*(reg8 *) USBFS_VBUS__DR)\r
+ #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_VBUS__PS)\r
+ #define USBFS_VBUS_PS_REG (*(reg8 *) USBFS_VBUS__PS)\r
+ #define USBFS_VBUS_MASK USBFS_VBUS__MASK\r
+ #else\r
+ #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG)\r
+ #define USBFS_VBUS_MASK (0x01u)\r
+ #endif /* (USBFS_VBUS_MONITORING_INTERNAL) */\r
+ #endif /*(USBFS_VBUS_MONITORING_ENABLE) */\r
+ \r
+ /* Pointer DIE structure in flash (8 bytes): Y and X location, wafer, lot msb, lot lsb, \r
+ * work week, fab/year, minor. */\r
+ #define USBFS_DIE_ID CYDEV_FLSHID_CUST_TABLES_BASE\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ #if (USBFS_DMA1_ACTIVE)\r
+ #define USBFS_ep1_TD_TERMOUT_EN (USBFS_ep1__TD_TERMOUT_EN)\r
+ #else\r
+ #define USBFS_ep1_TD_TERMOUT_EN (0u)\r
+ #endif /* (USBFS_DMA1_ACTIVE) */\r
+\r
+ #if (USBFS_DMA2_ACTIVE)\r
+ #define USBFS_ep2_TD_TERMOUT_EN (USBFS_ep2__TD_TERMOUT_EN)\r
+ #else\r
+ #define USBFS_ep2_TD_TERMOUT_EN (0u)\r
+ #endif /* (USBFS_DMA2_ACTIVE) */\r
+\r
+ #if (USBFS_DMA3_ACTIVE)\r
+ #define USBFS_ep3_TD_TERMOUT_EN (USBFS_ep3__TD_TERMOUT_EN)\r
+ #else\r
+ #define USBFS_ep3_TD_TERMOUT_EN (0u)\r
+ #endif /* (USBFS_DMA3_ACTIVE) */\r
+\r
+ #if (USBFS_DMA4_ACTIVE)\r
+ #define USBFS_ep4_TD_TERMOUT_EN (USBFS_ep4__TD_TERMOUT_EN)\r
+ #else\r
+ #define USBFS_ep4_TD_TERMOUT_EN (0u)\r
+ #endif /* (USBFS_DMA4_ACTIVE) */\r
+\r
+ #if (USBFS_DMA5_ACTIVE)\r
+ #define USBFS_ep5_TD_TERMOUT_EN (USBFS_ep5__TD_TERMOUT_EN)\r
+ #else\r
+ #define USBFS_ep5_TD_TERMOUT_EN (0u)\r
+ #endif /* (USBFS_DMA5_ACTIVE) */\r
+\r
+ #if (USBFS_DMA6_ACTIVE)\r
+ #define USBFS_ep6_TD_TERMOUT_EN (USBFS_ep6__TD_TERMOUT_EN)\r
+ #else\r
+ #define USBFS_ep6_TD_TERMOUT_EN (0u)\r
+ #endif /* (USBFS_DMA6_ACTIVE) */\r
+\r
+ #if (USBFS_DMA7_ACTIVE)\r
+ #define USBFS_ep7_TD_TERMOUT_EN (USBFS_ep7__TD_TERMOUT_EN)\r
+ #else\r
+ #define USBFS_ep7_TD_TERMOUT_EN (0u)\r
+ #endif /* (USBFS_DMA7_ACTIVE) */\r
+\r
+ #if (USBFS_DMA8_ACTIVE)\r
+ #define USBFS_ep8_TD_TERMOUT_EN (USBFS_ep8__TD_TERMOUT_EN)\r
+ #else\r
+ #define USBFS_ep8_TD_TERMOUT_EN (0u)\r
+ #endif /* (USBFS_DMA8_ACTIVE) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ \r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+/* Rename USB IP registers. */\r
#define USBFS_ARB_CFG USBFS_ARB_CFG_PTR\r
\r
#define USBFS_ARB_EP1_CFG USBFS_ARB_EP1_CFG_PTR\r
#define USBFS_USBIO_CR1 USBFS_USBIO_CR1_PTR\r
#define USBFS_USBIO_CR2 USBFS_USBIO_CR2_PTR\r
\r
-#define USBFS_USB_MEM ((reg8 *) CYDEV_USB_MEM_BASE)\r
-\r
-#if(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_LEOPARD)\r
- /* PSoC3 interrupt registers*/\r
- #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_INTC_PRIOR0)\r
- #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_INTC_SET_EN0)\r
- #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_INTC_CLR_EN0)\r
- #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_INTC_VECT_MBASE)\r
-#elif(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_PANTHER)\r
- /* PSoC5 interrupt registers*/\r
- #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_NVIC_PRI_0)\r
- #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0)\r
- #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0)\r
- #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET)\r
-#endif /* CYDEV_CHIP_DIE_EXPECT */\r
-\r
-\r
-/***************************************\r
-* Interrupt vectors, masks and priorities\r
-***************************************/\r
-\r
-#define USBFS_BUS_RESET_PRIOR USBFS_bus_reset__INTC_PRIOR_NUM\r
-#define USBFS_BUS_RESET_MASK USBFS_bus_reset__INTC_MASK\r
-#define USBFS_BUS_RESET_VECT_NUM USBFS_bus_reset__INTC_NUMBER\r
-\r
-#define USBFS_SOF_PRIOR USBFS_sof_int__INTC_PRIOR_NUM\r
-#define USBFS_SOF_MASK USBFS_sof_int__INTC_MASK\r
-#define USBFS_SOF_VECT_NUM USBFS_sof_int__INTC_NUMBER\r
-\r
-#define USBFS_EP_0_PRIOR USBFS_ep_0__INTC_PRIOR_NUM\r
-#define USBFS_EP_0_MASK USBFS_ep_0__INTC_MASK\r
-#define USBFS_EP_0_VECT_NUM USBFS_ep_0__INTC_NUMBER\r
-\r
-#define USBFS_EP_1_PRIOR USBFS_ep_1__INTC_PRIOR_NUM\r
-#define USBFS_EP_1_MASK USBFS_ep_1__INTC_MASK\r
-#define USBFS_EP_1_VECT_NUM USBFS_ep_1__INTC_NUMBER\r
-\r
-#define USBFS_EP_2_PRIOR USBFS_ep_2__INTC_PRIOR_NUM\r
-#define USBFS_EP_2_MASK USBFS_ep_2__INTC_MASK\r
-#define USBFS_EP_2_VECT_NUM USBFS_ep_2__INTC_NUMBER\r
-\r
-#define USBFS_EP_3_PRIOR USBFS_ep_3__INTC_PRIOR_NUM\r
-#define USBFS_EP_3_MASK USBFS_ep_3__INTC_MASK\r
-#define USBFS_EP_3_VECT_NUM USBFS_ep_3__INTC_NUMBER\r
-\r
-#define USBFS_EP_4_PRIOR USBFS_ep_4__INTC_PRIOR_NUM\r
-#define USBFS_EP_4_MASK USBFS_ep_4__INTC_MASK\r
-#define USBFS_EP_4_VECT_NUM USBFS_ep_4__INTC_NUMBER\r
-\r
-#define USBFS_EP_5_PRIOR USBFS_ep_5__INTC_PRIOR_NUM\r
-#define USBFS_EP_5_MASK USBFS_ep_5__INTC_MASK\r
-#define USBFS_EP_5_VECT_NUM USBFS_ep_5__INTC_NUMBER\r
-\r
-#define USBFS_EP_6_PRIOR USBFS_ep_6__INTC_PRIOR_NUM\r
-#define USBFS_EP_6_MASK USBFS_ep_6__INTC_MASK\r
-#define USBFS_EP_6_VECT_NUM USBFS_ep_6__INTC_NUMBER\r
-\r
-#define USBFS_EP_7_PRIOR USBFS_ep_7__INTC_PRIOR_NUM\r
-#define USBFS_EP_7_MASK USBFS_ep_7__INTC_MASK\r
-#define USBFS_EP_7_VECT_NUM USBFS_ep_7__INTC_NUMBER\r
-\r
-#define USBFS_EP_8_PRIOR USBFS_ep_8__INTC_PRIOR_NUM\r
-#define USBFS_EP_8_MASK USBFS_ep_8__INTC_MASK\r
-#define USBFS_EP_8_VECT_NUM USBFS_ep_8__INTC_NUMBER\r
-\r
-#define USBFS_DP_INTC_PRIOR USBFS_dp_int__INTC_PRIOR_NUM\r
-#define USBFS_DP_INTC_MASK USBFS_dp_int__INTC_MASK\r
-#define USBFS_DP_INTC_VECT_NUM USBFS_dp_int__INTC_NUMBER\r
-\r
-/* ARB ISR should have higher priority from EP_X ISR, therefore it is defined to highest (0) */\r
-#define USBFS_ARB_PRIOR (0u)\r
-#define USBFS_ARB_MASK USBFS_arb_int__INTC_MASK\r
-#define USBFS_ARB_VECT_NUM USBFS_arb_int__INTC_NUMBER\r
-\r
-/***************************************\r
- * Endpoint 0 offsets (Table 9-2)\r
- **************************************/\r
-\r
-#define USBFS_bmRequestType USBFS_EP0_DR0_PTR\r
-#define USBFS_bRequest USBFS_EP0_DR1_PTR\r
-#define USBFS_wValue USBFS_EP0_DR2_PTR\r
-#define USBFS_wValueHi USBFS_EP0_DR3_PTR\r
-#define USBFS_wValueLo USBFS_EP0_DR2_PTR\r
-#define USBFS_wIndex USBFS_EP0_DR4_PTR\r
-#define USBFS_wIndexHi USBFS_EP0_DR5_PTR\r
-#define USBFS_wIndexLo USBFS_EP0_DR4_PTR\r
-#define USBFS_length USBFS_EP0_DR6_PTR\r
-#define USBFS_lengthHi USBFS_EP0_DR7_PTR\r
-#define USBFS_lengthLo USBFS_EP0_DR6_PTR\r
-\r
-\r
-/***************************************\r
-* Register Constants\r
-***************************************/\r
-#define USBFS_VDDD_MV CYDEV_VDDD_MV\r
-#define USBFS_3500MV (3500u)\r
-\r
-#define USBFS_CR1_REG_ENABLE (0x01u)\r
-#define USBFS_CR1_ENABLE_LOCK (0x02u)\r
-#define USBFS_CR1_BUS_ACTIVITY_SHIFT (0x02u)\r
-#define USBFS_CR1_BUS_ACTIVITY ((uint8)(0x01u << USBFS_CR1_BUS_ACTIVITY_SHIFT))\r
-#define USBFS_CR1_TRIM_MSB_EN (0x08u)\r
-\r
-#define USBFS_EP0_CNT_DATA_TOGGLE (0x80u)\r
-#define USBFS_EPX_CNT_DATA_TOGGLE (0x80u)\r
-#define USBFS_EPX_CNT0_MASK (0x0Fu)\r
-#define USBFS_EPX_CNTX_MSB_MASK (0x07u)\r
-#define USBFS_EPX_CNTX_ADDR_SHIFT (0x04u)\r
-#define USBFS_EPX_CNTX_ADDR_OFFSET (0x10u)\r
-#define USBFS_EPX_CNTX_CRC_COUNT (0x02u)\r
-#define USBFS_EPX_DATA_BUF_MAX (512u)\r
-\r
-#define USBFS_CR0_ENABLE (0x80u)\r
-\r
-/* A 100 KHz clock is used for BUS reset count. Recommended is to count 10 pulses */\r
-#define USBFS_BUS_RST_COUNT (0x0au)\r
-\r
-#define USBFS_USBIO_CR1_IOMODE (0x20u)\r
-#define USBFS_USBIO_CR1_USBPUEN (0x04u)\r
-#define USBFS_USBIO_CR1_DP0 (0x02u)\r
-#define USBFS_USBIO_CR1_DM0 (0x01u)\r
-\r
-#define USBFS_USBIO_CR0_TEN (0x80u)\r
-#define USBFS_USBIO_CR0_TSE0 (0x40u)\r
-#define USBFS_USBIO_CR0_TD (0x20u)\r
-#define USBFS_USBIO_CR0_RD (0x01u)\r
-\r
-#define USBFS_FASTCLK_IMO_CR_USBCLK_ON (0x40u)\r
-#define USBFS_FASTCLK_IMO_CR_XCLKEN (0x20u)\r
-#define USBFS_FASTCLK_IMO_CR_FX2ON (0x10u)\r
-\r
-#define USBFS_ARB_EPX_CFG_RESET (0x08u)\r
-#define USBFS_ARB_EPX_CFG_CRC_BYPASS (0x04u)\r
-#define USBFS_ARB_EPX_CFG_DMA_REQ (0x02u)\r
-#define USBFS_ARB_EPX_CFG_IN_DATA_RDY (0x01u)\r
-#define USBFS_ARB_EPX_CFG_DEFAULT (USBFS_ARB_EPX_CFG_RESET | \\r
- USBFS_ARB_EPX_CFG_CRC_BYPASS)\r
-\r
-#define USBFS_ARB_EPX_SR_IN_BUF_FULL (0x01u)\r
-#define USBFS_ARB_EPX_SR_DMA_GNT (0x02u)\r
-#define USBFS_ARB_EPX_SR_BUF_OVER (0x04u)\r
-#define USBFS_ARB_EPX_SR_BUF_UNDER (0x08u)\r
-\r
-#define USBFS_ARB_CFG_AUTO_MEM (0x10u)\r
-#define USBFS_ARB_CFG_MANUAL_DMA (0x20u)\r
-#define USBFS_ARB_CFG_AUTO_DMA (0x40u)\r
-#define USBFS_ARB_CFG_CFG_CPM (0x80u)\r
-\r
-#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- #define USBFS_ARB_EPX_INT_MASK (0x1Du)\r
-#else\r
- #define USBFS_ARB_EPX_INT_MASK (0x1Fu)\r
-#endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
-#define USBFS_ARB_INT_MASK (uint8)((USBFS_DMA1_REMOVE ^ 1u) | \\r
- (uint8)((USBFS_DMA2_REMOVE ^ 1u) << 1u) | \\r
- (uint8)((USBFS_DMA3_REMOVE ^ 1u) << 2u) | \\r
- (uint8)((USBFS_DMA4_REMOVE ^ 1u) << 3u) | \\r
- (uint8)((USBFS_DMA5_REMOVE ^ 1u) << 4u) | \\r
- (uint8)((USBFS_DMA6_REMOVE ^ 1u) << 5u) | \\r
- (uint8)((USBFS_DMA7_REMOVE ^ 1u) << 6u) | \\r
- (uint8)((USBFS_DMA8_REMOVE ^ 1u) << 7u) )\r
+#define USBFS_DM_INP_DIS_PTR ( (reg8 *) USBFS_Dm__INP_DIS)\r
+#define USBFS_DM_INP_DIS_REG (*(reg8 *) USBFS_Dm__INP_DIS)\r
+#define USBFS_DP_INP_DIS_PTR ( (reg8 *) USBFS_Dp__INP_DIS)\r
+#define USBFS_DP_INP_DIS_REG (*(reg8 *) USBFS_Dp__INP_DIS)\r
+#define USBFS_DP_INTSTAT_PTR ( (reg8 *) USBFS_Dp__INTSTAT)\r
+#define USBFS_DP_INTSTAT_REG (*(reg8 *) USBFS_Dp__INTSTAT)\r
+#define USBFS_DM_MASK USBFS_Dm__0__MASK\r
+#define USBFS_DP_MASK USBFS_Dp__0__MASK\r
\r
#define USBFS_SIE_EP_INT_EP1_MASK (0x01u)\r
#define USBFS_SIE_EP_INT_EP2_MASK (0x02u)\r
#define USBFS_SIE_EP_INT_EP7_MASK (0x40u)\r
#define USBFS_SIE_EP_INT_EP8_MASK (0x80u)\r
\r
-#define USBFS_PM_ACT_EN_FSUSB USBFS_USB__PM_ACT_MSK\r
-#define USBFS_PM_STBY_EN_FSUSB USBFS_USB__PM_STBY_MSK\r
-#define USBFS_PM_AVAIL_EN_FSUSBIO (0x10u)\r
+#define USBFS_ARB_EPX_SR_IN_BUF_FULL (0x01u)\r
+#define USBFS_ARB_EPX_SR_DMA_GNT (0x02u)\r
+#define USBFS_ARB_EPX_SR_BUF_OVER (0x04u)\r
+#define USBFS_ARB_EPX_SR_BUF_UNDER (0x08u)\r
+\r
+#define USBFS_ARB_EPX_INT_EN_ALL USBFS_ARB_EPX_INT_ALL\r
\r
-#define USBFS_PM_USB_CR0_REF_EN (0x01u)\r
-#define USBFS_PM_USB_CR0_PD_N (0x02u)\r
-#define USBFS_PM_USB_CR0_PD_PULLUP_N (0x04u)\r
+#define USBFS_CR1_BUS_ACTIVITY_SHIFT (0x02u)\r
\r
-#define USBFS_USB_CLK_ENABLE (0x01u)\r
+#define USBFS_BUS_RST_COUNT USBFS_DEFUALT_BUS_RST_CNT\r
\r
-#define USBFS_DM_MASK USBFS_Dm__0__MASK\r
-#define USBFS_DP_MASK USBFS_Dp__0__MASK\r
+#define USBFS_ARB_INT_MASK USBFS_DEFAULT_ARB_INT_EN\r
\r
-#define USBFS_DYN_RECONFIG_ENABLE (0x01u)\r
-#define USBFS_DYN_RECONFIG_EP_SHIFT (0x01u)\r
-#define USBFS_DYN_RECONFIG_RDY_STS (0x10u)\r
+#if (CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_LEOPARD)\r
+ /* CY_PSOC3 interrupt registers */\r
+ #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_INTC_PRIOR0)\r
+ #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_INTC_SET_EN0)\r
+ #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_INTC_CLR_EN0)\r
+ #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_INTC_VECT_MBASE)\r
+#elif (CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_PANTHER)\r
+ /* CY_PSOC5LP interrupt registers */\r
+ #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_NVIC_PRI_0)\r
+ #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0)\r
+ #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0)\r
+ #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET)\r
+#endif /* CYDEV_CHIP_DIE_EXPECT */\r
\r
\r
-#endif /* CY_USBFS_USBFS_H */\r
+#endif /* (CY_USBFS_USBFS_H) */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_Dm.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Dm_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_Write\r
*******************************************************************************/\r
-void USBFS_Dm_Write(uint8 value) \r
+void USBFS_Dm_Write(uint8 value)\r
{\r
uint8 staticBits = (USBFS_Dm_DR & (uint8)(~USBFS_Dm_MASK));\r
USBFS_Dm_DR = staticBits | ((uint8)(value << USBFS_Dm_SHIFT) & USBFS_Dm_MASK);\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Dm_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* USBFS_Dm_DM_STRONG Strong Drive \r
-* USBFS_Dm_DM_OD_HI Open Drain, Drives High \r
-* USBFS_Dm_DM_OD_LO Open Drain, Drives Low \r
-* USBFS_Dm_DM_RES_UP Resistive Pull Up \r
-* USBFS_Dm_DM_RES_DWN Resistive Pull Down \r
-* USBFS_Dm_DM_RES_UPDWN Resistive Pull Up/Down \r
-* USBFS_Dm_DM_DIG_HIZ High Impedance Digital \r
-* USBFS_Dm_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_SetDriveMode\r
*******************************************************************************/\r
-void USBFS_Dm_SetDriveMode(uint8 mode) \r
+void USBFS_Dm_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(USBFS_Dm_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Dm_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro USBFS_Dm_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_Read \r
*******************************************************************************/\r
-uint8 USBFS_Dm_Read(void) \r
+uint8 USBFS_Dm_Read(void)\r
{\r
return (USBFS_Dm_PS & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Dm_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred USBFS_Dm_Read() API because the \r
+* USBFS_Dm_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_ReadDataReg \r
*******************************************************************************/\r
-uint8 USBFS_Dm_ReadDataReg(void) \r
+uint8 USBFS_Dm_ReadDataReg(void)\r
{\r
return (USBFS_Dm_DR & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(USBFS_Dm_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: USBFS_Dm_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use USBFS_Dm_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - USBFS_Dm_0_INTR (First pin in the list)\r
+ * - USBFS_Dm_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - USBFS_Dm_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_SetInterruptMode\r
+ *******************************************************************************/\r
+ void USBFS_Dm_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & USBFS_Dm_0_INTR) != 0u) \r
+ { \r
+ USBFS_Dm_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: USBFS_Dm_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_ClearInterrupt\r
*******************************************************************************/\r
- uint8 USBFS_Dm_ClearInterrupt(void) \r
+ uint8 USBFS_Dm_ClearInterrupt(void)\r
{\r
return (USBFS_Dm_INTSTAT & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: USBFS_Dm.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "USBFS_Dm_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void USBFS_Dm_Write(uint8 value) ;\r
-void USBFS_Dm_SetDriveMode(uint8 mode) ;\r
-uint8 USBFS_Dm_ReadDataReg(void) ;\r
-uint8 USBFS_Dm_Read(void) ;\r
-uint8 USBFS_Dm_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void USBFS_Dm_Write(uint8 value);\r
+void USBFS_Dm_SetDriveMode(uint8 mode);\r
+uint8 USBFS_Dm_ReadDataReg(void);\r
+uint8 USBFS_Dm_Read(void);\r
+void USBFS_Dm_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 USBFS_Dm_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define USBFS_Dm_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define USBFS_Dm_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define USBFS_Dm_DM_RES_UP PIN_DM_RES_UP\r
-#define USBFS_Dm_DM_RES_DWN PIN_DM_RES_DWN\r
-#define USBFS_Dm_DM_OD_LO PIN_DM_OD_LO\r
-#define USBFS_Dm_DM_OD_HI PIN_DM_OD_HI\r
-#define USBFS_Dm_DM_STRONG PIN_DM_STRONG\r
-#define USBFS_Dm_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the USBFS_Dm_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define USBFS_Dm_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define USBFS_Dm_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define USBFS_Dm_DM_RES_UP PIN_DM_RES_UP\r
+ #define USBFS_Dm_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define USBFS_Dm_DM_OD_LO PIN_DM_OD_LO\r
+ #define USBFS_Dm_DM_OD_HI PIN_DM_OD_HI\r
+ #define USBFS_Dm_DM_STRONG PIN_DM_STRONG\r
+ #define USBFS_Dm_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define USBFS_Dm_MASK USBFS_Dm__MASK\r
#define USBFS_Dm_SHIFT USBFS_Dm__SHIFT\r
#define USBFS_Dm_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(USBFS_Dm__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in USBFS_Dm_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define USBFS_Dm_INTR_NONE (uint16)(0x0000u)\r
+ #define USBFS_Dm_INTR_RISING (uint16)(0x0001u)\r
+ #define USBFS_Dm_INTR_FALLING (uint16)(0x0002u)\r
+ #define USBFS_Dm_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define USBFS_Dm_INTR_MASK (0x01u) \r
+#endif /* (USBFS_Dm__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define USBFS_Dm_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_Dm__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(USBFS_Dm__INTSTAT) /* Interrupt Registers */\r
-\r
- #define USBFS_Dm_INTSTAT (* (reg8 *) USBFS_Dm__INTSTAT)\r
- #define USBFS_Dm_SNAP (* (reg8 *) USBFS_Dm__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(USBFS_Dm__SIO_CFG)\r
+ #define USBFS_Dm_SIO_HYST_EN (* (reg8 *) USBFS_Dm__SIO_HYST_EN)\r
+ #define USBFS_Dm_SIO_REG_HIFREQ (* (reg8 *) USBFS_Dm__SIO_REG_HIFREQ)\r
+ #define USBFS_Dm_SIO_CFG (* (reg8 *) USBFS_Dm__SIO_CFG)\r
+ #define USBFS_Dm_SIO_DIFF (* (reg8 *) USBFS_Dm__SIO_DIFF)\r
+#endif /* (USBFS_Dm__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(USBFS_Dm__INTSTAT)\r
+ #define USBFS_Dm_INTSTAT (* (reg8 *) USBFS_Dm__INTSTAT)\r
+ #define USBFS_Dm_SNAP (* (reg8 *) USBFS_Dm__SNAP)\r
+ \r
+ #define USBFS_Dm_0_INTTYPE_REG (* (reg8 *) USBFS_Dm__0__INTTYPE)\r
+#endif /* (USBFS_Dm__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: USBFS_Dm.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define USBFS_Dm_0 (USBFS_Dm__0__PC)\r
+#define USBFS_Dm_0 (USBFS_Dm__0__PC)\r
+#define USBFS_Dm_0_INTR ((uint16)((uint16)0x0001u << USBFS_Dm__0__SHIFT))\r
+\r
+#define USBFS_Dm_INTR_ALL ((uint16)(USBFS_Dm_0_INTR))\r
\r
#endif /* End Pins USBFS_Dm_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_Dp.c \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Dp_Write\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
+* \brief Writes the value to the physical port (data output register), masking\r
+* and shifting the bits appropriately. \r
*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This function avoids changing \r
+* other bits in the port by using the appropriate method (read-modify-write or\r
+* bit banding).\r
*\r
-* Return: \r
-* None\r
-* \r
+* <b>Note</b> This function should not be used on a hardware digital output pin \r
+* as it is driven by the hardware signal attached to it.\r
+*\r
+* \param value\r
+* Value to write to the component instance.\r
+*\r
+* \return \r
+* None \r
+*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic; the Interrupt \r
+* Service Routines (ISR) can cause corruption of this function. An ISR that \r
+* interrupts this function and performs writes to the Pins component data \r
+* register can cause corrupted port data. To avoid this issue, you should \r
+* either use the Per-Pin APIs (primary method) or disable interrupts around \r
+* this function.\r
+*\r
+* \funcusage\r
+* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_Write\r
*******************************************************************************/\r
-void USBFS_Dp_Write(uint8 value) \r
+void USBFS_Dp_Write(uint8 value)\r
{\r
uint8 staticBits = (USBFS_Dp_DR & (uint8)(~USBFS_Dp_MASK));\r
USBFS_Dp_DR = staticBits | ((uint8)(value << USBFS_Dp_SHIFT) & USBFS_Dp_MASK);\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Dp_SetDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
+* \brief Sets the drive mode for each of the Pins component's pins.\r
* \r
-* Parameters: \r
-* mode: Change the pins to one of the following drive modes.\r
-*\r
-* USBFS_Dp_DM_STRONG Strong Drive \r
-* USBFS_Dp_DM_OD_HI Open Drain, Drives High \r
-* USBFS_Dp_DM_OD_LO Open Drain, Drives Low \r
-* USBFS_Dp_DM_RES_UP Resistive Pull Up \r
-* USBFS_Dp_DM_RES_DWN Resistive Pull Down \r
-* USBFS_Dp_DM_RES_UPDWN Resistive Pull Up/Down \r
-* USBFS_Dp_DM_DIG_HIZ High Impedance Digital \r
-* USBFS_Dp_DM_ALG_HIZ High Impedance Analog \r
-*\r
-* Return: \r
+* <b>Note</b> This affects all pins in the Pins component instance. Use the\r
+* Per-Pin APIs if you wish to control individual pin's drive modes.\r
+*\r
+* \param mode\r
+* Mode for the selected signals. Valid options are documented in \r
+* \ref driveMode.\r
+*\r
+* \return\r
* None\r
*\r
+* \sideeffect\r
+* If you use read-modify-write operations that are not atomic, the ISR can\r
+* cause corruption of this function. An ISR that interrupts this function \r
+* and performs writes to the Pins component Drive Mode registers can cause \r
+* corrupted port data. To avoid this issue, you should either use the Per-Pin\r
+* APIs (primary method) or disable interrupts around this function.\r
+*\r
+* \funcusage\r
+* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_SetDriveMode\r
*******************************************************************************/\r
-void USBFS_Dp_SetDriveMode(uint8 mode) \r
+void USBFS_Dp_SetDriveMode(uint8 mode)\r
{\r
CyPins_SetPinDriveMode(USBFS_Dp_0, mode);\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Dp_Read\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
+* \brief Reads the associated physical port (pin status register) and masks \r
+* the required bits according to the width and bit position of the component\r
+* instance. \r
*\r
-* Parameters: \r
-* None\r
+* The pin's status register returns the current logic level present on the \r
+* physical pin.\r
*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro USBFS_Dp_ReadPS calls this function. \r
-* \r
+* \return \r
+* The current value for the pins in the component as a right justified number.\r
+*\r
+* \funcusage\r
+* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_Read \r
*******************************************************************************/\r
-uint8 USBFS_Dp_Read(void) \r
+uint8 USBFS_Dp_Read(void)\r
{\r
return (USBFS_Dp_PS & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Dp_ReadDataReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
+* \brief Reads the associated physical port's data output register and masks \r
+* the correct bits according to the width and bit position of the component \r
+* instance. \r
*\r
-* Parameters: \r
-* None \r
+* The data output register controls the signal applied to the physical pin in \r
+* conjunction with the drive mode parameter. This is not the same as the \r
+* preferred USBFS_Dp_Read() API because the \r
+* USBFS_Dp_ReadDataReg() reads the data register instead of the status \r
+* register. For output pins this is a useful function to determine the value \r
+* just written to the pin.\r
+*\r
+* \return \r
+* The current value of the data register masked and shifted into a right \r
+* justified number for the component instance.\r
*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
+* \funcusage\r
+* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_ReadDataReg \r
*******************************************************************************/\r
-uint8 USBFS_Dp_ReadDataReg(void) \r
+uint8 USBFS_Dp_ReadDataReg(void)\r
{\r
return (USBFS_Dp_DR & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT;\r
}\r
\r
\r
-/* If Interrupts Are Enabled for this Pins component */ \r
+/* If interrupt is connected for this Pins component */ \r
#if defined(USBFS_Dp_INTSTAT) \r
\r
+ /*******************************************************************************\r
+ * Function Name: USBFS_Dp_SetInterruptMode\r
+ ****************************************************************************//**\r
+ *\r
+ * \brief Configures the interrupt mode for each of the Pins component's\r
+ * pins. Alternatively you may set the interrupt mode for all the pins\r
+ * specified in the Pins component.\r
+ *\r
+ * <b>Note</b> The interrupt is port-wide and therefore any enabled pin\r
+ * interrupt may trigger it.\r
+ *\r
+ * \param position\r
+ * The pin position as listed in the Pins component. You may OR these to be \r
+ * able to configure the interrupt mode of multiple pins within a Pins \r
+ * component. Or you may use USBFS_Dp_INTR_ALL to configure the\r
+ * interrupt mode of all the pins in the Pins component. \r
+ * - USBFS_Dp_0_INTR (First pin in the list)\r
+ * - USBFS_Dp_1_INTR (Second pin in the list)\r
+ * - ...\r
+ * - USBFS_Dp_INTR_ALL (All pins in Pins component)\r
+ *\r
+ * \param mode\r
+ * Interrupt mode for the selected pins. Valid options are documented in\r
+ * \ref intrMode.\r
+ *\r
+ * \return \r
+ * None\r
+ * \r
+ * \sideeffect\r
+ * It is recommended that the interrupt be disabled before calling this \r
+ * function to avoid unintended interrupt requests. Note that the interrupt\r
+ * type is port wide, and therefore will trigger for any enabled pin on the \r
+ * port.\r
+ *\r
+ * \funcusage\r
+ * \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_SetInterruptMode\r
+ *******************************************************************************/\r
+ void USBFS_Dp_SetInterruptMode(uint16 position, uint16 mode)\r
+ {\r
+ if((position & USBFS_Dp_0_INTR) != 0u) \r
+ { \r
+ USBFS_Dp_0_INTTYPE_REG = (uint8)mode; \r
+ }\r
+ }\r
+ \r
+ \r
/*******************************************************************************\r
* Function Name: USBFS_Dp_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
+ ****************************************************************************//**\r
*\r
- * Parameters: \r
- * None \r
+ * \brief Clears any active interrupts attached with the component and returns \r
+ * the value of the interrupt status register allowing determination of which\r
+ * pins generated an interrupt event.\r
*\r
- * Return: \r
- * Returns the value of the interrupt status register\r
+ * \return \r
+ * The right-shifted current value of the interrupt status register. Each pin \r
+ * has one bit set if it generated an interrupt event. For example, bit 0 is \r
+ * for pin 0 and bit 1 is for pin 1 of the Pins component.\r
* \r
+ * \sideeffect\r
+ * Clears all bits of the physical port's interrupt status register, not just\r
+ * those associated with the Pins component.\r
+ *\r
+ * \funcusage\r
+ * \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_ClearInterrupt\r
*******************************************************************************/\r
- uint8 USBFS_Dp_ClearInterrupt(void) \r
+ uint8 USBFS_Dp_ClearInterrupt(void)\r
{\r
return (USBFS_Dp_INTSTAT & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT;\r
}\r
/*******************************************************************************\r
* File Name: USBFS_Dp.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains Pin function prototypes and register defines\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cypins.h"\r
#include "USBFS_Dp_aliases.h"\r
\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* APIs are not generated for P15[7:6] */\r
#if !(CY_PSOC5A &&\\r
USBFS_Dp__PORT == 15 && ((USBFS_Dp__MASK & 0xC0) != 0))\r
* Function Prototypes \r
***************************************/ \r
\r
-void USBFS_Dp_Write(uint8 value) ;\r
-void USBFS_Dp_SetDriveMode(uint8 mode) ;\r
-uint8 USBFS_Dp_ReadDataReg(void) ;\r
-uint8 USBFS_Dp_Read(void) ;\r
-uint8 USBFS_Dp_ClearInterrupt(void) ;\r
-\r
+/**\r
+* \addtogroup group_general\r
+* @{\r
+*/\r
+void USBFS_Dp_Write(uint8 value);\r
+void USBFS_Dp_SetDriveMode(uint8 mode);\r
+uint8 USBFS_Dp_ReadDataReg(void);\r
+uint8 USBFS_Dp_Read(void);\r
+void USBFS_Dp_SetInterruptMode(uint16 position, uint16 mode);\r
+uint8 USBFS_Dp_ClearInterrupt(void);\r
+/** @} general */\r
\r
/***************************************\r
* API Constants \r
***************************************/\r
-\r
-/* Drive Modes */\r
-#define USBFS_Dp_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define USBFS_Dp_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define USBFS_Dp_DM_RES_UP PIN_DM_RES_UP\r
-#define USBFS_Dp_DM_RES_DWN PIN_DM_RES_DWN\r
-#define USBFS_Dp_DM_OD_LO PIN_DM_OD_LO\r
-#define USBFS_Dp_DM_OD_HI PIN_DM_OD_HI\r
-#define USBFS_Dp_DM_STRONG PIN_DM_STRONG\r
-#define USBFS_Dp_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup driveMode Drive mode constants\r
+ * \brief Constants to be passed as "mode" parameter in the USBFS_Dp_SetDriveMode() function.\r
+ * @{\r
+ */\r
+ #define USBFS_Dp_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+ #define USBFS_Dp_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+ #define USBFS_Dp_DM_RES_UP PIN_DM_RES_UP\r
+ #define USBFS_Dp_DM_RES_DWN PIN_DM_RES_DWN\r
+ #define USBFS_Dp_DM_OD_LO PIN_DM_OD_LO\r
+ #define USBFS_Dp_DM_OD_HI PIN_DM_OD_HI\r
+ #define USBFS_Dp_DM_STRONG PIN_DM_STRONG\r
+ #define USBFS_Dp_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+ /** @} driveMode */\r
+/** @} group_constants */\r
+ \r
/* Digital Port Constants */\r
#define USBFS_Dp_MASK USBFS_Dp__MASK\r
#define USBFS_Dp_SHIFT USBFS_Dp__SHIFT\r
#define USBFS_Dp_WIDTH 1u\r
\r
+/* Interrupt constants */\r
+#if defined(USBFS_Dp__INTSTAT)\r
+/**\r
+* \addtogroup group_constants\r
+* @{\r
+*/\r
+ /** \addtogroup intrMode Interrupt constants\r
+ * \brief Constants to be passed as "mode" parameter in USBFS_Dp_SetInterruptMode() function.\r
+ * @{\r
+ */\r
+ #define USBFS_Dp_INTR_NONE (uint16)(0x0000u)\r
+ #define USBFS_Dp_INTR_RISING (uint16)(0x0001u)\r
+ #define USBFS_Dp_INTR_FALLING (uint16)(0x0002u)\r
+ #define USBFS_Dp_INTR_BOTH (uint16)(0x0003u) \r
+ /** @} intrMode */\r
+/** @} group_constants */\r
+\r
+ #define USBFS_Dp_INTR_MASK (0x01u) \r
+#endif /* (USBFS_Dp__INTSTAT) */\r
+\r
\r
/***************************************\r
* Registers \r
/* Sync Output Enable Registers */\r
#define USBFS_Dp_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_Dp__PRTDSI__SYNC_OUT) \r
\r
-\r
-#if defined(USBFS_Dp__INTSTAT) /* Interrupt Registers */\r
-\r
- #define USBFS_Dp_INTSTAT (* (reg8 *) USBFS_Dp__INTSTAT)\r
- #define USBFS_Dp_SNAP (* (reg8 *) USBFS_Dp__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
+/* SIO registers */\r
+#if defined(USBFS_Dp__SIO_CFG)\r
+ #define USBFS_Dp_SIO_HYST_EN (* (reg8 *) USBFS_Dp__SIO_HYST_EN)\r
+ #define USBFS_Dp_SIO_REG_HIFREQ (* (reg8 *) USBFS_Dp__SIO_REG_HIFREQ)\r
+ #define USBFS_Dp_SIO_CFG (* (reg8 *) USBFS_Dp__SIO_CFG)\r
+ #define USBFS_Dp_SIO_DIFF (* (reg8 *) USBFS_Dp__SIO_DIFF)\r
+#endif /* (USBFS_Dp__SIO_CFG) */\r
+\r
+/* Interrupt Registers */\r
+#if defined(USBFS_Dp__INTSTAT)\r
+ #define USBFS_Dp_INTSTAT (* (reg8 *) USBFS_Dp__INTSTAT)\r
+ #define USBFS_Dp_SNAP (* (reg8 *) USBFS_Dp__SNAP)\r
+ \r
+ #define USBFS_Dp_0_INTTYPE_REG (* (reg8 *) USBFS_Dp__0__INTTYPE)\r
+#endif /* (USBFS_Dp__INTSTAT) */\r
\r
#endif /* CY_PSOC5A... */\r
\r
/*******************************************************************************\r
* File Name: USBFS_Dp.h \r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
-* This file containts Control Register function prototypes and register defines\r
+* This file contains the Alias definitions for Per-Pin APIs in cypins.h. \r
+* Information on using these APIs can be found in the System Reference Guide.\r
*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
\r
\r
-\r
/***************************************\r
* Constants \r
***************************************/\r
-#define USBFS_Dp_0 (USBFS_Dp__0__PC)\r
+#define USBFS_Dp_0 (USBFS_Dp__0__PC)\r
+#define USBFS_Dp_0_INTR ((uint16)((uint16)0x0001u << USBFS_Dp__0__SHIFT))\r
+\r
+#define USBFS_Dp_INTR_ALL ((uint16)(USBFS_Dp_0_INTR))\r
\r
#endif /* End Pins USBFS_Dp_ALIASES_H */\r
\r
+\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: USBFS_audio.c\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_audio.c\r
+* \version 3.10\r
*\r
-* Description:\r
-* USB AUDIO Class request handler.\r
+* \brief\r
+* This file contains the USB AUDIO Class request handler.\r
*\r
* Related Document:\r
* Universal Serial Bus Device Class Definition for Audio Devices Release 1.0\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
-\r
-\r
-#if defined(USBFS_ENABLE_AUDIO_CLASS)\r
-\r
#include "USBFS_audio.h"\r
#include "USBFS_pvt.h"\r
-#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
- #include "USBFS_midi.h"\r
-#endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
\r
\r
+#if defined(USBFS_ENABLE_AUDIO_CLASS)\r
+\r
/***************************************\r
* Custom Declarations\r
***************************************/\r
\r
#if !defined(USER_SUPPLIED_AUDIO_HANDLER)\r
\r
-\r
/***************************************\r
* AUDIO Variables\r
***************************************/\r
\r
#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
+ /** Contains the current audio sample frequency. It is set by the host using a SET_CUR request to the endpoint.*/\r
volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP][USBFS_SAMPLE_FREQ_LEN];\r
+ /** Used as a flag for the user code, to inform it that the host has been sent a request \r
+ * to change the sample frequency. The sample frequency will be sent on the next OUT transaction. \r
+ * It contains the endpoint address when set. The following code is recommended for \r
+ * detecting new sample frequency in main code:\r
+ * \snippet /USBFS_sut_02.cydsn/main.c Detecting new Sample Frequency\r
+ * \r
+ * The USBFS_transferState variable is checked to make sure that the transfer completes. */\r
volatile uint8 USBFS_frequencyChanged;\r
+ /** Contains the mute configuration set by the host.*/\r
volatile uint8 USBFS_currentMute;\r
+ /** Contains the volume level set by the host.*/\r
volatile uint8 USBFS_currentVolume[USBFS_VOLUME_LEN];\r
volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_MIN_LSB,\r
USBFS_VOL_MIN_MSB};\r
\r
/*******************************************************************************\r
* Function Name: USBFS_DispatchAUDIOClassRqst\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine dispatches class requests\r
*\r
-* Parameters:\r
-* None.\r
+* \return\r
+* Results of Audio Class request handling: \r
+* - USBFS_TRUE - request was handled without errors\r
+* - USBFS_FALSE - error occurs during handling of request \r
*\r
-* Return:\r
-* requestHandled\r
-*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_currentSampleFrequency: Contains the current audio Sample\r
* Frequency. It is set by the Host using SET_CUR request to the endpoint.\r
* USBFS_frequencyChanged: This variable is used as a flag for the\r
* Sample Frequency. Sample frequency will be sent on the next OUT\r
* transaction. It is contains endpoint address when set. The following\r
* code is recommended for detecting new Sample Frequency in main code:\r
-* if((USBFS_frequencyChanged != 0) &&\r
-* (USBFS_transferState == USBFS_TRANS_STATE_IDLE))\r
-* {\r
-* USBFS_frequencyChanged = 0;\r
-* }\r
-* USBFS_transferState variable is checked to be sure that\r
-* transfer completes.\r
+* \r
+* \snippet /USBFS_sut_02.cydsn/main.c Detecting new Sample Frequency\r
+* \r
+* USBFS_transferState variable is checked to be sure that transfer\r
+* completes.\r
* USBFS_currentMute: Contains mute configuration set by Host.\r
* USBFS_currentVolume: Contains volume level set by Host.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_DispatchAUDIOClassRqst(void) \r
{\r
uint8 requestHandled = USBFS_FALSE;\r
- uint8 bmRequestType = CY_GET_REG8(USBFS_bmRequestType);\r
-\r
- #if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
- uint8 epNumber;\r
- epNumber = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED;\r
- #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
-\r
-\r
- if ((bmRequestType & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)\r
+ \r
+ uint8 RqstRcpt = (uint8)(USBFS_bmRequestTypeReg & USBFS_RQST_RCPT_MASK);\r
+#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
+ uint8 wValueHi = (uint8) USBFS_wValueHiReg;\r
+ uint8 epNumber = (uint8) USBFS_wIndexLoReg & USBFS_DIR_UNUSED;\r
+#endif /* (USBFS_ENABLE_AUDIO_STREAMING) */\r
+ \r
+ /* Check request direction: D2H or H2D. */\r
+ if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H))\r
{\r
- /* Control Read */\r
- if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)\r
+ /* Handle direction from device to host. */\r
+ \r
+ if (USBFS_RQST_RCPT_EP == RqstRcpt)\r
{\r
- /* Endpoint */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ /* Request recipient is to endpoint. */\r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_GET_CUR:\r
#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
- if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)\r
+ if (wValueHi == USBFS_SAMPLING_FREQ_CONTROL)\r
{\r
/* point Control Selector is Sampling Frequency */\r
USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;\r
USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber];\r
+ \r
requestHandled = USBFS_InitControlRead();\r
}\r
- #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
-\r
- /* `#START AUDIO_READ_REQUESTS` Place other request handler here */\r
+ #endif /* (USBFS_ENABLE_AUDIO_STREAMING) */\r
+ \r
+ /* `#START AUDIO_READ_REQUESTS` Place other request handler here */\r
- /* `#END` */\r
+ /* `#END` */\r
\r
- #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK\r
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK \r
USBFS_DispatchAUDIOClass_AUDIO_READ_REQUESTS_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK */\r
-\r
- break;\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK) */ \r
+ break;\r
+ \r
default:\r
+ /* Do not handle this request unless callback is defined. */\r
break;\r
}\r
+ \r
}\r
- else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)\r
+ else if (USBFS_RQST_RCPT_IFC == RqstRcpt)\r
{\r
- /* Interface or Entity ID */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ /* Request recipient is interface or entity ID. */\r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_GET_CUR:\r
#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
- if(CY_GET_REG8(USBFS_wValueHi) == USBFS_MUTE_CONTROL)\r
+ if (wValueHi == USBFS_MUTE_CONTROL)\r
{\r
/* `#START MUTE_CONTROL_GET_REQUEST` Place multi-channel handler here */\r
/* `#END` */\r
\r
- #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK\r
- USBFS_DispatchAUDIOClass_MUTE_CONTROL_GET_REQUEST_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK */\r
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK\r
+ USBFS_DispatchAUDIOClass_MUTE_CONTROL_GET_REQUEST_Callback();\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK) */\r
\r
/* Entity ID Control Selector is MUTE */\r
USBFS_currentTD.wCount = 1u;\r
USBFS_currentTD.pData = &USBFS_currentMute;\r
- requestHandled = USBFS_InitControlRead();\r
+ \r
+ requestHandled = USBFS_InitControlRead();\r
}\r
- else if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL)\r
+ else if (wValueHi == USBFS_VOLUME_CONTROL)\r
{\r
/* `#START VOLUME_CONTROL_GET_REQUEST` Place multi-channel handler here */\r
/* `#END` */\r
\r
- #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK\r
- USBFS_DispatchAUDIOClass_VOLUME_CONTROL_GET_REQUEST_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK */\r
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK\r
+ USBFS_DispatchAUDIOClass_VOLUME_CONTROL_GET_REQUEST_Callback();\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK) */\r
\r
/* Entity ID Control Selector is VOLUME, */\r
USBFS_currentTD.wCount = USBFS_VOLUME_LEN;\r
USBFS_currentTD.pData = USBFS_currentVolume;\r
- requestHandled = USBFS_InitControlRead();\r
+ \r
+ requestHandled = USBFS_InitControlRead();\r
}\r
else\r
{\r
/* `#END` */\r
\r
- #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK\r
- USBFS_DispatchAUDIOClass_OTHER_GET_CUR_REQUESTS_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK */\r
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK\r
+ USBFS_DispatchAUDIOClass_OTHER_GET_CUR_REQUESTS_Callback();\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK) */\r
}\r
break;\r
- case USBFS_GET_MIN: /* GET_MIN */\r
- if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL)\r
+ \r
+ case USBFS_GET_MIN:\r
+ if (wValueHi == USBFS_VOLUME_CONTROL)\r
{\r
/* Entity ID Control Selector is VOLUME, */\r
USBFS_currentTD.wCount = USBFS_VOLUME_LEN;\r
USBFS_currentTD.pData = &USBFS_minimumVolume[0];\r
- requestHandled = USBFS_InitControlRead();\r
+ \r
+ requestHandled = USBFS_InitControlRead();\r
}\r
break;\r
- case USBFS_GET_MAX: /* GET_MAX */\r
- if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL)\r
+ \r
+ case USBFS_GET_MAX:\r
+ if (wValueHi == USBFS_VOLUME_CONTROL)\r
{\r
/* Entity ID Control Selector is VOLUME, */\r
USBFS_currentTD.wCount = USBFS_VOLUME_LEN;\r
USBFS_currentTD.pData = &USBFS_maximumVolume[0];\r
- requestHandled = USBFS_InitControlRead();\r
+ \r
+ requestHandled = USBFS_InitControlRead();\r
}\r
break;\r
- case USBFS_GET_RES: /* GET_RES */\r
- if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL)\r
+ \r
+ case USBFS_GET_RES:\r
+ if (wValueHi == USBFS_VOLUME_CONTROL)\r
{\r
/* Entity ID Control Selector is VOLUME, */\r
USBFS_currentTD.wCount = USBFS_VOLUME_LEN;\r
USBFS_currentTD.pData = &USBFS_resolutionVolume[0];\r
+ \r
requestHandled = USBFS_InitControlRead();\r
}\r
break;\r
+ \r
/* The contents of the status message is reserved for future use.\r
- * For the time being, a null packet should be returned in the data stage of the\r
- * control transfer, and the received null packet should be ACKed.\r
+ * For the time being, a null packet should be returned in the data stage of the\r
+ * control transfer, and the received null packet should be ACKed.\r
*/\r
case USBFS_GET_STAT:\r
- USBFS_currentTD.wCount = 0u;\r
- requestHandled = USBFS_InitControlWrite();\r
+ USBFS_currentTD.wCount = 0u; \r
+ \r
+ requestHandled = USBFS_InitControlWrite();\r
\r
- #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
-\r
- /* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */\r
+ #endif /* (USBFS_ENABLE_AUDIO_STREAMING) */\r
+ \r
+ /* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */\r
- /* `#END` */\r
-\r
+ /* `#END` */\r
+ \r
#ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_WRITE_REQUESTS_CALLBACK\r
USBFS_DispatchAUDIOClass_AUDIO_WRITE_REQUESTS_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_WRITE_REQUESTS_CALLBACK */\r
-\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_AUDIO_WRITE_REQUESTS_CALLBACK) */\r
break;\r
+ \r
default:\r
+ /* Do not handle this request. */\r
break;\r
}\r
}\r
else\r
- { /* USBFS_RQST_RCPT_OTHER */\r
+ { \r
+ /* Do not handle other requests recipients. */\r
}\r
}\r
else\r
{\r
- /* Control Write */\r
- if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)\r
+ /* Handle direction from host to device. */\r
+ \r
+ if (USBFS_RQST_RCPT_EP == RqstRcpt)\r
{\r
- /* point */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ /* Request recipient is endpoint. */\r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_SET_CUR:\r
#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
- if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)\r
+ if (wValueHi == USBFS_SAMPLING_FREQ_CONTROL)\r
{\r
/* point Control Selector is Sampling Frequency */\r
USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;\r
USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber];\r
+ USBFS_frequencyChanged = (uint8) epNumber;\r
+ \r
requestHandled = USBFS_InitControlWrite();\r
- USBFS_frequencyChanged = epNumber;\r
}\r
- #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
+ #endif /* (USBFS_ENABLE_AUDIO_STREAMING) */\r
\r
- /* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */\r
+ /* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */\r
- /* `#END` */\r
+ /* `#END` */\r
\r
#ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_SAMPLING_FREQ_REQUESTS_CALLBACK\r
USBFS_DispatchAUDIOClass_AUDIO_SAMPLING_FREQ_REQUESTS_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_SAMPLING_FREQ_REQUESTS_CALLBACK */\r
-\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_AUDIO_SAMPLING_FREQ_REQUESTS_CALLBACK) */\r
break;\r
+ \r
default:\r
+ /* Do not handle this request. */\r
break;\r
}\r
}\r
- else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)\r
+ else if(USBFS_RQST_RCPT_IFC == RqstRcpt)\r
{\r
- /* Interface or Entity ID */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ /* Request recipient is interface or entity ID. */\r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_SET_CUR:\r
#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
- if(CY_GET_REG8(USBFS_wValueHi) == USBFS_MUTE_CONTROL)\r
+ if (wValueHi == USBFS_MUTE_CONTROL)\r
{\r
/* `#START MUTE_SET_REQUEST` Place multi-channel handler here */\r
/* `#END` */\r
\r
- #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK\r
- USBFS_DispatchAUDIOClass_MUTE_SET_REQUEST_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK */\r
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK\r
+ USBFS_DispatchAUDIOClass_MUTE_SET_REQUEST_Callback();\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK) */\r
\r
/* Entity ID Control Selector is MUTE */\r
USBFS_currentTD.wCount = 1u;\r
USBFS_currentTD.pData = &USBFS_currentMute;\r
- requestHandled = USBFS_InitControlWrite();\r
+ \r
+ requestHandled = USBFS_InitControlWrite();\r
}\r
- else if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL)\r
+ else if (wValueHi == USBFS_VOLUME_CONTROL)\r
{\r
/* `#START VOLUME_CONTROL_SET_REQUEST` Place multi-channel handler here */\r
/* `#END` */\r
\r
- #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK\r
- USBFS_DispatchAUDIOClass_VOLUME_CONTROL_SET_REQUEST_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK */\r
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK\r
+ USBFS_DispatchAUDIOClass_VOLUME_CONTROL_SET_REQUEST_Callback();\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK) */\r
\r
/* Entity ID Control Selector is VOLUME */\r
USBFS_currentTD.wCount = USBFS_VOLUME_LEN;\r
USBFS_currentTD.pData = USBFS_currentVolume;\r
- requestHandled = USBFS_InitControlWrite();\r
+ \r
+ requestHandled = USBFS_InitControlWrite();\r
}\r
else\r
{\r
/* `#END` */\r
\r
- #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK\r
- USBFS_DispatchAUDIOClass_OTHER_SET_CUR_REQUESTS_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK */\r
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK\r
+ USBFS_DispatchAUDIOClass_OTHER_SET_CUR_REQUESTS_Callback();\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK) */\r
}\r
#endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
-\r
- /* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */\r
+ \r
+ \r
+ /* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */\r
- /* `#END` */\r
-\r
+ /* `#END` */\r
+ \r
#ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_CONTROL_SEL_REQUESTS_CALLBACK\r
USBFS_DispatchAUDIOClass_AUDIO_CONTROL_SEL_REQUESTS_Callback();\r
- #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_CONTROL_SEL_REQUESTS_CALLBACK */\r
+ #endif /* (USBFS_DISPATCH_AUDIO_CLASS_AUDIO_CONTROL_SEL_REQUESTS_CALLBACK) */\r
+ break;\r
\r
- break;\r
default:\r
- break;\r
+ /* Do not handle this request. */\r
+ break;\r
}\r
}\r
else\r
{\r
- /* USBFS_RQST_RCPT_OTHER */\r
+ /* Do not handle other requests recipients. */\r
}\r
}\r
\r
- return(requestHandled);\r
+ return (requestHandled);\r
}\r
-\r
-#endif /* USER_SUPPLIED_AUDIO_HANDLER */\r
+#endif /* (USER_SUPPLIED_AUDIO_HANDLER) */\r
\r
\r
/*******************************************************************************\r
/* `#END` */\r
\r
-#endif /* USBFS_ENABLE_AUDIO_CLASS */\r
+#endif /* (USBFS_ENABLE_AUDIO_CLASS) */\r
\r
\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: USBFS_audio.h\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_audio.h\r
+* \version 3.10\r
*\r
-* Description:\r
-* Header File for the USBFS component. Contains prototypes and constant values.\r
+* \brief\r
+* This file provides function prototypes and constants for the USBFS component \r
+* Audio class.\r
*\r
* Related Document:\r
* Universal Serial Bus Device Class Definition for Audio Devices Release 1.0\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#if !defined(CY_USBFS_USBFS_audio_H)\r
#define CY_USBFS_USBFS_audio_H\r
\r
-#include "cytypes.h"\r
+#include "USBFS.h"\r
\r
\r
/***************************************\r
/***************************************\r
* External data references\r
***************************************/\r
-\r
-extern volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP]\r
- [USBFS_SAMPLE_FREQ_LEN];\r
+/**\r
+* \addtogroup group_audio\r
+* @{\r
+*/\r
+extern volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP][USBFS_SAMPLE_FREQ_LEN];\r
extern volatile uint8 USBFS_frequencyChanged;\r
extern volatile uint8 USBFS_currentMute;\r
extern volatile uint8 USBFS_currentVolume[USBFS_VOLUME_LEN];\r
+/** @} audio */\r
+\r
extern volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN];\r
extern volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN];\r
extern volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN];\r
-/*******************************************************************************\r
-* File Name: USBFS_boot.c\r
-* Version 2.80\r
-*\r
-* Description:\r
-* Boot loader API for USBFS Component.\r
+/***************************************************************************//**\r
+* \file USBFS_boot.c\r
+* \version 3.10\r
*\r
-* Note:\r
+* \brief\r
+* This file contains the Bootloader API for USBFS Component.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
+#include "USBFS_pvt.h"\r
\r
#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \\r
- (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))\r
-\r
+ (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)) \r
\r
/***************************************\r
* Bootloader Variables\r
***************************************/\r
+ \r
\r
static uint8 USBFS_started = 0u;\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_CyBtldrCommStart\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Starts the component and enables the interrupt.\r
+* This function performs all required initialization for the USBFS component, \r
+* waits on enumeration, and enables communication.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* This function starts the USB with 3V or 5V operation.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_CyBtldrCommStart(void) \r
{\r
- CyGlobalIntEnable; /* Enable Global Interrupts */\r
+ /* Enable Global Interrupts. Interrupts are mandatory for USBFS component operation. */\r
+ CyGlobalIntEnable;\r
\r
- /*Start USBFS Operation/device 0 and with 5V or 3V operation depend on Voltage Configuration in DWR */\r
- USBFS_Start(0u, USBFS_DWR_VDDD_OPERATION);\r
+ /* Start USBFS Operation: device 0 and with 5V or 3V operation depend on Voltage Configuration in DWR. */\r
+ USBFS_Start(0u, USBFS_DWR_POWER_OPERATION);\r
\r
- /* USB component started, the correct enumeration will be checked in first Read operation */\r
+ /* USB component started, the correct enumeration will be checked in the first Read operation. */\r
USBFS_started = 1u;\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_CyBtldrCommStop.\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Disable the component and disable the interrupt.\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
+* This function performs all necessary shutdown tasks required for the USBFS \r
+* component.\r
+* \r
+* \sideeffect\r
+* Calls the USBFS_Stop() function.\r
*\r
*******************************************************************************/\r
void USBFS_CyBtldrCommStop(void) \r
\r
/*******************************************************************************\r
* Function Name: USBFS_CyBtldrCommReset.\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Resets the receive and transmit communication Buffers.\r
-*\r
-* Parameters:\r
-* None\r
+****************************************************************************//**\r
*\r
-* Return:\r
-* None\r
+* This function resets receive and transmit communication buffers.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No\r
*\r
*******************************************************************************/\r
void USBFS_CyBtldrCommReset(void) \r
{\r
- USBFS_EnableOutEP(USBFS_BTLDR_OUT_EP); /* Enable the OUT endpoint */\r
+ USBFS_EnableOutEP(USBFS_BTLDR_OUT_EP); \r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_CyBtldrCommWrite.\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Allows the caller to write data to the boot loader host. The function will\r
-* handle polling to allow a block of data to be completely sent to the host\r
+* This function allows the caller to write data to the bootloader host. It \r
+* handles polling to allow a block of data to be completely sent to the host \r
* device.\r
*\r
-* Parameters:\r
-* pData: A pointer to the block of data to send to the device\r
-* size: The number of bytes to write.\r
-* count: Pointer to an unsigned short variable to write the number of\r
-* bytes actually written.\r
-* timeOut: Number of units to wait before returning because of a timeout.\r
+* \param pData A pointer to the block of data to send to the device\r
+* \param size The number of bytes to write.\r
+* \param count Pointer to an unsigned short variable to write the number of\r
+* bytes actually written.\r
+* \param timeOut Number of units to wait before returning because of a timeout.\r
*\r
-* Return:\r
-* Returns the value that best describes the problem.\r
+* \return\r
+* Returns CYRET_SUCCESS if no problem was encountered or returns the value that \r
+* best describes the problem. For more information, see the “Return Codes” \r
+* section of the System Reference Guide.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No\r
*\r
*******************************************************************************/\r
cystatus retCode;\r
uint16 timeoutMs;\r
\r
- timeoutMs = ((uint16) 10u * timeOut); /* Convert from 10mS check to number 1mS checks */\r
+ /* Convert 10mS checks into 1mS checks. */\r
+ timeoutMs = ((uint16) 10u * timeOut);\r
\r
- /* Enable IN transfer */\r
+ /* Load data into IN endpoint to be read by host. */\r
USBFS_LoadInEP(USBFS_BTLDR_IN_EP, pData, USBFS_BTLDR_SIZEOF_READ_BUFFER);\r
\r
- /* Wait for the master to read it. */\r
+ /* Wait unitl host reads data from IN endpoint. */\r
while ((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) &&\r
(0u != timeoutMs))\r
{\r
retCode = CYRET_SUCCESS;\r
}\r
\r
- return(retCode);\r
+ return (retCode);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_CyBtldrCommRead.\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Allows the caller to read data from the boot loader host. The function will\r
-* handle polling to allow a block of data to be completely received from the\r
+* This function allows the caller to read data from the bootloader host. It \r
+* handles polling to allow a block of data to be completely received from the \r
* host device.\r
*\r
-* Parameters:\r
-* pData: A pointer to the area to store the block of data received\r
-* from the device.\r
-* size: The number of bytes to read.\r
-* count: Pointer to an unsigned short variable to write the number\r
-* of bytes actually read.\r
-* timeOut: Number of units to wait before returning because of a timeOut.\r
-* Timeout is measured in 10s of ms.\r
+* \param pData A pointer to the area to store the block of data received\r
+* from the device.\r
+* \param size The number of bytes to read.\r
+* \param count Pointer to an unsigned short variable to write the number\r
+* of bytes actually read.\r
+* \param timeOut Number of units to wait before returning because of a timeOut.\r
+* Timeout is measured in 10s of ms.\r
*\r
-* Return:\r
-* Returns the value that best describes the problem.\r
+* \return\r
+* Returns CYRET_SUCCESS if no problem was encountered or returns the value that \r
+* best describes the problem. For more information, see the “Return Codes” \r
+* section of the System Reference Guide.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No\r
*\r
*******************************************************************************/\r
cystatus retCode;\r
uint16 timeoutMs;\r
\r
- timeoutMs = ((uint16) 10u * timeOut); /* Convert from 10mS check to number 1mS checks */\r
+ /* Convert 10mS checks into 1mS checks. */\r
+ timeoutMs = ((uint16) 10u * timeOut);\r
\r
if (size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)\r
{\r
size = USBFS_BTLDR_SIZEOF_WRITE_BUFFER;\r
}\r
\r
- /* Wait on enumeration in first time */\r
+ /* Wait for enumeration first time. */\r
if (0u != USBFS_started)\r
{\r
- /* Wait for Device to enumerate */\r
- while ((0u ==USBFS_GetConfiguration()) && (0u != timeoutMs))\r
+ /* Wait for device enumeration. */\r
+ while ((0u == USBFS_GetConfiguration()) && (0u != timeoutMs))\r
{\r
CyDelay(USBFS_BTLDR_WAIT_1_MS);\r
timeoutMs--;\r
}\r
\r
- /* Enable first OUT, if enumeration complete */\r
+ /* Enable OUT after enumeration. */\r
if (0u != USBFS_GetConfiguration())\r
{\r
- (void) USBFS_IsConfigurationChanged(); /* Clear configuration changes state status */\r
+ (void) USBFS_IsConfigurationChanged(); /* Clear configuration changes state status. */\r
USBFS_CyBtldrCommReset();\r
+ \r
USBFS_started = 0u;\r
}\r
}\r
- else /* Check for configuration changes, has been done by Host */\r
+ else /* Check for configuration changes, has been done by Host. */\r
{\r
- if (0u != USBFS_IsConfigurationChanged()) /* Host could send double SET_INTERFACE request or RESET */\r
+ if (0u != USBFS_IsConfigurationChanged()) /* Host could send double SET_INTERFACE request or RESET. */\r
{\r
- if (0u != USBFS_GetConfiguration()) /* Init OUT endpoints when device reconfigured */\r
+ if (0u != USBFS_GetConfiguration()) /* Init OUT endpoints when device reconfigured. */\r
{\r
USBFS_CyBtldrCommReset();\r
}\r
\r
timeoutMs = ((uint16) 10u * timeOut); /* Re-arm timeout */\r
\r
- /* Wait on next packet */\r
- while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \\r
- (0u != timeoutMs))\r
+ /* Wait unitl host writes data into OUT endpoint. */\r
+ while ((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \\r
+ (0u != timeoutMs))\r
{\r
CyDelay(USBFS_BTLDR_WAIT_1_MS);\r
timeoutMs--;\r
}\r
\r
- /* OUT EP has completed */\r
+ /* Read data from OUT endpoint if host wrote data into it. */\r
if (USBFS_GetEPState(USBFS_BTLDR_OUT_EP) == USBFS_OUT_BUFFER_FULL)\r
{\r
*count = USBFS_ReadOutEP(USBFS_BTLDR_OUT_EP, pData, size);\r
retCode = CYRET_TIMEOUT;\r
}\r
\r
- return(retCode);\r
+ return (retCode);\r
}\r
\r
-#endif /* CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */\r
+#endif /* (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) */\r
\r
\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: USBFS_cdc.c\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_cdc.c\r
+* \version 3.10\r
*\r
-* Description:\r
-* USB CDC class request handler.\r
+* \brief\r
+* This file contains the USB CDC class request handler.\r
*\r
* Related Document:\r
* Universal Serial Bus Class Definitions for Communication Devices Version 1.1\r
*\r
********************************************************************************\r
-* Copyright 2012-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2012-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
-\r
-#if defined(USBFS_ENABLE_CDC_CLASS)\r
-\r
#include "USBFS_cdc.h"\r
#include "USBFS_pvt.h"\r
\r
\r
+#if defined(USBFS_ENABLE_CDC_CLASS)\r
\r
-/***************************************\r
+/*******************************************************************************\r
* CDC Variables\r
-***************************************/\r
+*******************************************************************************/\r
\r
-volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE] =\r
+/*PUBLIC*/\r
+/** Contains the current line coding structure. The host sets it using a\r
+ * SET_LINE_CODING request and returns it to the user code using the\r
+ * USBFS_GetDTERate(), USBFS_GetCharFormat(),\r
+ * USBFS_GetParityType(), and USBFS_GetDataBits() APIs.\r
+ * It is an array of 2 elements for COM port 1 and COM port 2 for MultiCOM port\r
+ * support. In case of 1 COM port, data is in 0 element.*/\r
+volatile uint8 USBFS_linesCoding[USBFS_MAX_MULTI_COM_NUM][USBFS_LINE_CODING_SIZE] =\r
{\r
+ /*COM Port 1*/\r
+ {\r
+ 0x00u, 0xC2u, 0x01u, 0x00u, /* Data terminal rate 115200 */\r
+ 0x00u, /* 1 Stop bit */\r
+ 0x00u, /* None parity */\r
+ 0x08u /* 8 data bits */\r
+ },\r
+ /*COM Port 2*/\r
+ {\r
0x00u, 0xC2u, 0x01u, 0x00u, /* Data terminal rate 115200 */\r
0x00u, /* 1 Stop bit */\r
0x00u, /* None parity */\r
0x08u /* 8 data bits */\r
+ }\r
};\r
-volatile uint8 USBFS_lineChanged;\r
-volatile uint16 USBFS_lineControlBitmap;\r
-volatile uint8 USBFS_cdc_data_in_ep;\r
-volatile uint8 USBFS_cdc_data_out_ep;\r
+\r
+/**Used as a flag for the USBFS_IsLineChanged() API, to inform it that the\r
+ * host has been sent a request to change line coding or control bitmap. It is \r
+ * an array of 2 elements for COM port 1 and COM port 2 for MultiCOM port \r
+ * support. In case of 1 COM port, data is in 0 element.*/\r
+volatile uint8 USBFS_linesChanged[USBFS_MAX_MULTI_COM_NUM];\r
+/** Contains the current control-signal bitmap. The host sets it using a\r
+ * SET_CONTROL_LINE request and returns it to the user code using the \r
+ * USBFS_GetLineControl() API. It is an array of 2 elements for COM \r
+ * port 1 and COM port 2 for MultiCOM port support. In case of 1 COM port, data \r
+ * is in 0 element.*/\r
+volatile uint16 USBFS_linesControlBitmap[USBFS_MAX_MULTI_COM_NUM];\r
+/** Contains the 16-bit serial state value that was sent using the \r
+ * \ref USBFS_SendSerialState() API. . It is an array of 2 elements \r
+ * for COM port 1 and COM port 2 for MultiCOM port support. In case of 1 COM \r
+ * port, data is in 0 element.*/\r
+volatile uint16 USBFS_serialStateBitmap[USBFS_MAX_MULTI_COM_NUM];\r
+/** Contains the data IN endpoint number. It is initialized after a \r
+ * SET_CONFIGURATION request based on a user descriptor. It is used in CDC APIs \r
+ * to send data to the PC. It is an array of 2 elements for COM port 1 and COM \r
+ * port 2 for MultiCOM port support. In case of 1 COM port, data is in 0 element.*/\r
+volatile uint8 USBFS_cdcDataInEp[USBFS_MAX_MULTI_COM_NUM];\r
+/** Contains the data OUT endpoint number. It is initialized after a \r
+ * SET_CONFIGURATION request based on user descriptor. It is used in CDC APIs to \r
+ * receive data from the PC. It is an array of 2 elements for COM port 1 and COM \r
+ * port 2 for MultiCOM port support. In case of 1 COM port, data is in 0 element.*/\r
+volatile uint8 USBFS_cdcDataOutEp[USBFS_MAX_MULTI_COM_NUM];\r
+/** Contains the data IN endpoint number for COMMUNICATION interface. It is \r
+ * initialized after a SET_CONFIGURATION request based on a user descriptor. It \r
+ * is used in CDC APIs to send data to the PC. It is an array of 2 elements for \r
+ * COM port 1 and COM port 2 for MultiCOM port support. In case of 1 COM port, \r
+ * data is in 0 element.*/\r
+volatile uint8 USBFS_cdcCommInInterruptEp[USBFS_MAX_MULTI_COM_NUM];\r
+\r
+/*PRIVATE*/\r
+\r
+#define USBFS_CDC_IN_EP (0u)\r
+#define USBFS_CDC_OUT_EP (1u)\r
+#define USBFS_CDC_NOTE_EP (2u)\r
+\r
+#define USBFS_CDC_EP_MASK (0x01u)\r
+\r
+#define USBFS_GET_EP_COM_NUM(cdcComNums, epType) (((cdcComNums) >> (epType)) & USBFS_CDC_EP_MASK)\r
\r
\r
/***************************************\r
***************************************/\r
#if (USBFS_ENABLE_CDC_CLASS_API != 0u)\r
static uint16 USBFS_StrLen(const char8 string[]) ;\r
+ static t_USBFS_cdc_notification USBFS_serialStateNotification =\r
+ {\r
+\r
+ USBFS_SERIAL_STATE_REQUEST_TYPE, /* bRequestType */\r
+ USBFS_SERIAL_STATE, /* bNotification */\r
+ 0u, /* wValue */\r
+ 0u, /* wValueMSB */\r
+ 0u, /* wIndex */\r
+ 0u, /* wIndexMSB */\r
+ USBFS_SERIAL_STATE_LENGTH, /* wLength */\r
+ 0u, /* wLengthMSB */\r
+ 0u, /* wSerialState */\r
+ 0u, /* wSerialStateMSB */\r
+ };\r
+ static uint8 USBFS_activeCom = 0u;\r
#endif /* (USBFS_ENABLE_CDC_CLASS_API != 0u) */\r
\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_DispatchCDCClassRqst\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine dispatches CDC class requests.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled\r
*\r
-* Global variables:\r
-* USBFS_lineCoding: Contains the current line coding structure.\r
+* \globalvars\r
+* USBFS_linesCoding: Contains the current line coding structure.\r
* It is set by the Host using SET_LINE_CODING request and returned to the\r
* user code by the USBFS_GetDTERate(), USBFS_GetCharFormat(),\r
* USBFS_GetParityType(), USBFS_GetDataBits() APIs.\r
-* USBFS_lineControlBitmap: Contains the current control signal\r
+* USBFS_linesControlBitmap: Contains the current control signal\r
* bitmap. It is set by the Host using SET_CONTROL_LINE request and returned\r
* to the user code by the USBFS_GetLineControl() API.\r
-* USBFS_lineChanged: This variable is used as a flag for the\r
+* USBFS_linesChanged: This variable is used as a flag for the\r
* USBFS_IsLineChanged() API, to be aware that Host has been sent request\r
* for changing Line Coding or Control Bitmap.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_DispatchCDCClassRqst(void) \r
{\r
uint8 requestHandled = USBFS_FALSE;\r
+ uint8 comPort;\r
+\r
+ comPort = USBFS_GetInterfaceComPort((uint8)USBFS_wIndexLoReg);\r
\r
- if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)\r
- { /* Control Read */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ /* Check request direction: D2H or H2D. */\r
+ if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H))\r
+ {\r
+ /* Handle direction from device to host. */\r
+\r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_CDC_GET_LINE_CODING:\r
USBFS_currentTD.count = USBFS_LINE_CODING_SIZE;\r
- USBFS_currentTD.pData = USBFS_lineCoding;\r
+ USBFS_currentTD.pData = USBFS_linesCoding[comPort];\r
requestHandled = USBFS_InitControlRead();\r
break;\r
\r
/* `#END` */\r
\r
+ default:\r
+ /* Do not handle this request unless callback is defined. */\r
#ifdef USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK\r
- USBFS_DispatchCDCClass_CDC_READ_REQUESTS_Callback();\r
- #endif /* USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK */\r
-\r
- default: /* requestHandled is initialized as FALSE by default */\r
+ requestHandled = USBFS_DispatchCDCClass_CDC_READ_REQUESTS_Callback();\r
+ #endif /* (USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK) */\r
break;\r
}\r
}\r
- else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \\r
- USBFS_RQST_DIR_H2D)\r
- { /* Control Write */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ else\r
+ {\r
+ /* Handle direction from host to device. */\r
+\r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_CDC_SET_LINE_CODING:\r
- USBFS_currentTD.count = USBFS_LINE_CODING_SIZE;\r
- USBFS_currentTD.pData = USBFS_lineCoding;\r
- USBFS_lineChanged |= USBFS_LINE_CODING_CHANGED;\r
+ USBFS_currentTD.count = USBFS_LINE_CODING_SIZE;\r
+ USBFS_currentTD.pData = USBFS_linesCoding[comPort];\r
+ USBFS_linesChanged[comPort] |= USBFS_LINE_CODING_CHANGED;\r
+\r
requestHandled = USBFS_InitControlWrite();\r
break;\r
\r
case USBFS_CDC_SET_CONTROL_LINE_STATE:\r
- USBFS_lineControlBitmap = CY_GET_REG8(USBFS_wValueLo);\r
- USBFS_lineChanged |= USBFS_LINE_CONTROL_CHANGED;\r
+ USBFS_linesControlBitmap[comPort] = (uint8) USBFS_wValueLoReg;\r
+ USBFS_linesChanged[comPort] |= USBFS_LINE_CONTROL_CHANGED;\r
+\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
break;\r
\r
/* `#END` */\r
\r
+ default:\r
+ /* Do not handle this request unless callback is defined. */\r
#ifdef USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK\r
- USBFS_DispatchCDCClass_CDC_WRITE_REQUESTS_Callback();\r
- #endif /* USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK */\r
-\r
- default: /* requestHandled is initialized as FALSE by default */\r
+ requestHandled = USBFS_DispatchCDCClass_CDC_WRITE_REQUESTS_Callback();\r
+ #endif /* (USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK) */\r
break;\r
}\r
}\r
- else\r
- { /* requestHandled is initialized as FALSE by default */\r
- }\r
\r
return(requestHandled);\r
}\r
\r
\r
+/***************************************************************************\r
+* Function Name: USBFS_GetInterfaceComPort\r
+************************************************************************//**\r
+* \internal\r
+* Internal function which gets number of COM port by specified interface\r
+* number.\r
+*\r
+* \param uint8 interface\r
+* Interface number\r
+*\r
+* \return\r
+* COM port number (0 or 1) or error 0xFF\r
+*\r
+***************************************************************************/\r
+uint8 USBFS_GetInterfaceComPort(uint8 interface) \r
+{\r
+ uint8 comPort = 0u;\r
+ uint8 res = 0xFFu;\r
+ uint8 notEp;\r
+\r
+ while (comPort < USBFS_MAX_MULTI_COM_NUM)\r
+ {\r
+ notEp = USBFS_cdcCommInInterruptEp[comPort];\r
+\r
+ if (USBFS_EP[notEp].interface == interface)\r
+ {\r
+ res = comPort;\r
+ comPort = USBFS_MAX_MULTI_COM_NUM;\r
+ }\r
+\r
+ comPort++;\r
+ }\r
+ return (res);\r
+}\r
+\r
+\r
/***************************************\r
* Optional CDC APIs\r
***************************************/\r
#if (USBFS_ENABLE_CDC_CLASS_API != 0u)\r
+/***************************************************************************\r
+* Function Name: USBFS_CDC_Init\r
+************************************************************************//**\r
+*\r
+* This function initializes the CDC interface to be ready to receive data\r
+* from the PC. The API set active communication port to 0 in the case of \r
+* multiple communication port support.This API should be called after the \r
+* device has been started and configured using USBUART_Start() API to \r
+* initialize and start the USBFS component operation. Then call the \r
+* USBUART_GetConfiguration() API to wait until the host has enumerated and \r
+* configured the device. For example:\r
+*\r
+* \snippet /USBFS_sut_02.cydsn/main.c wait for enumeration\r
+*\r
+* \return\r
+* cystatus:\r
+* Return Value Description\r
+* USBFS_SUCCESS CDC interface was initialized correctly\r
+* USBFS_FAILURE CDC interface was not initialized\r
+*\r
+* \globalvars\r
+* USBFS_linesChanged: Initialized to zero.\r
+* USBFS_cdcDataOutEp: Used as an OUT endpoint number.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_CDC_Init(void) \r
+{\r
+ uint8 comPort;\r
+ uint8 outEp;\r
+ uint8 ret = USBFS_SUCCESS;\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_CDC_Init\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function initialize the CDC interface to be ready for the receive data\r
- * from the PC.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Global variables:\r
- * USBFS_lineChanged: Initialized to zero.\r
- * USBFS_cdc_data_out_ep: Used as an OUT endpoint number.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- void USBFS_CDC_Init(void) \r
- {\r
- USBFS_lineChanged = 0u;\r
- USBFS_EnableOutEP(USBFS_cdc_data_out_ep);\r
- }\r
-\r
+ USBFS_activeCom = 0u;\r
+ USBFS_linesChanged[USBFS_COM_PORT1] = 0u;\r
+ USBFS_linesChanged[USBFS_COM_PORT2] = 0u;\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_PutData\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function sends a specified number of bytes from the location specified\r
- * by a pointer to the PC. The USBFS_CDCIsReady() function should be\r
- * called before sending new data, to be sure that the previous data has\r
- * finished sending.\r
- * If the last sent packet is less than maximum packet size the USB transfer\r
- * of this short packet will identify the end of the segment. If the last sent\r
- * packet is exactly maximum packet size, it shall be followed by a zero-length\r
- * packet (which is a short packet) to assure the end of segment is properly\r
- * identified. To send zero-length packet, use USBFS_PutData() API\r
- * with length parameter set to zero.\r
- *\r
- * Parameters:\r
- * pData: pointer to the buffer containing data to be sent.\r
- * length: Specifies the number of bytes to send from the pData\r
- * buffer. Maximum length will be limited by the maximum packet\r
- * size for the endpoint. Data will be lost if length is greater than Max\r
- * Packet Size.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending\r
- * data.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- void USBFS_PutData(const uint8* pData, uint16 length) \r
+ for(comPort = 0u; comPort<USBFS_MAX_MULTI_COM_NUM; comPort++)\r
{\r
- /* Limits length to maximum packet size for the EP */\r
- if(length > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize)\r
+ outEp = USBFS_cdcDataOutEp[comPort];\r
+ if((0u != outEp) && (USBFS_MAX_EP > outEp))\r
{\r
- /* Caution: Data will be lost if length is greater than Max Packet Length */\r
- length = USBFS_EP[USBFS_cdc_data_in_ep].bufferSize;\r
- /* Halt CPU in debug mode */\r
- CYASSERT(0u != 0u);\r
+ USBFS_EnableOutEP(outEp);\r
}\r
- USBFS_LoadInEP(USBFS_cdc_data_in_ep, pData, length);\r
- }\r
\r
+ }\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_StrLen\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Calculates length of a null terminated string.\r
- *\r
- * Parameters:\r
- * string: pointer to the string.\r
- *\r
- * Return:\r
- * Length of the string\r
- *\r
- *******************************************************************************/\r
- static uint16 USBFS_StrLen(const char8 string[]) \r
+ /* COM Port 1 should be correct to proceed. */\r
+ if ((0u == USBFS_cdcDataInEp[USBFS_COM_PORT1]) \\r
+ || (0u == USBFS_cdcDataOutEp[USBFS_COM_PORT1]) \\r
+ || (0u == USBFS_cdcCommInInterruptEp[USBFS_COM_PORT1])\r
+ || (USBFS_cdcDataInEp[USBFS_COM_PORT1] >= USBFS_MAX_EP)\r
+ || (USBFS_cdcDataOutEp[USBFS_COM_PORT1] >= USBFS_MAX_EP)\r
+ || (USBFS_cdcCommInInterruptEp[USBFS_COM_PORT1] >= USBFS_MAX_EP))\r
{\r
- uint16 len = 0u;\r
+ ret = USBFS_FAILURE;\r
+ }\r
\r
- while (string[len] != (char8)0)\r
- {\r
- len++;\r
- }\r
+ return (ret);\r
+}\r
\r
- return (len);\r
- }\r
\r
+/*******************************************************************************\r
+* Function Name: USBFS_PutData\r
+****************************************************************************//**\r
+*\r
+* This function sends a specified number of bytes from the location specified\r
+* by a pointer to the PC. The USBFS_CDCIsReady() function should be\r
+* called before sending new data, to be sure that the previous data has\r
+* finished sending.\r
+* If the last sent packet is less than maximum packet size the USB transfer\r
+* of this short packet will identify the end of the segment. If the last sent\r
+* packet is exactly maximum packet size, it shall be followed by a zero-length\r
+* packet (which is a short packet) to assure the end of segment is properly\r
+* identified. To send zero-length packet, use USBFS_PutData() API\r
+* with length parameter set to zero.\r
+*\r
+* \param pData: pointer to the buffer containing data to be sent.\r
+* \param length: Specifies the number of bytes to send from the pData\r
+* buffer. Maximum length will be limited by the maximum packet\r
+* size for the endpoint. Data will be lost if length is greater than Max\r
+* Packet Size.\r
+*\r
+* \globalvars\r
+*\r
+* USBFS_cdcDataInEp: CDC IN endpoint number used for sending\r
+* data.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void USBFS_PutData(const uint8* pData, uint16 length) \r
+{\r
+ uint8 epNumber = USBFS_cdcDataInEp[USBFS_activeCom];\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_PutString\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function sends a null terminated string to the PC. This function will\r
- * block if there is not enough memory to place the whole string. It will block\r
- * until the entire string has been written to the transmit buffer.\r
- * The USBUART_CDCIsReady() function should be called before sending data with\r
- * a new call to USBFS_PutString(), to be sure that the previous data\r
- * has finished sending.\r
- *\r
- * Parameters:\r
- * string: pointer to the string to be sent to the PC.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending\r
- * data.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- void USBFS_PutString(const char8 string[]) \r
+ /* Limit length to maximum packet size for endpoint. */\r
+ if (length > USBFS_EP[epNumber].bufferSize)\r
{\r
- uint16 strLength;\r
- uint16 sendLength;\r
- uint16 bufIndex = 0u;\r
+ /* Caution: Data will be lost if length is greater than Max Packet Size. */\r
+ length = USBFS_EP[epNumber].bufferSize;\r
\r
- /* Get length of the null terminated string */\r
- strLength = USBFS_StrLen(string);\r
- do\r
- {\r
- /* Limits length to maximum packet size for the EP */\r
- sendLength = (strLength > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?\r
- USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : strLength;\r
- /* Enable IN transfer */\r
- USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[bufIndex], sendLength);\r
- strLength -= sendLength;\r
-\r
- /* If more data are present to send or full packet was sent */\r
- if((strLength > 0u) || (sendLength == USBFS_EP[USBFS_cdc_data_in_ep].bufferSize))\r
- {\r
- bufIndex += sendLength;\r
- /* Wait for the Host to read it. */\r
- while(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState ==\r
- USBFS_IN_BUFFER_FULL)\r
- {\r
- ;\r
- }\r
- /* If the last sent packet is exactly maximum packet size,\r
- * it shall be followed by a zero-length packet to assure the\r
- * end of segment is properly identified by the terminal.\r
- */\r
- if(strLength == 0u)\r
- {\r
- USBFS_LoadInEP(USBFS_cdc_data_in_ep, NULL, 0u);\r
- }\r
- }\r
- }while(strLength > 0u);\r
+ /* Halt CPU in debug mode */\r
+ CYASSERT(0u != 0u);\r
}\r
\r
+ USBFS_LoadInEP(epNumber, pData, length);\r
+}\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_PutChar\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Writes a single character to the PC.\r
- *\r
- * Parameters:\r
- * txDataByte: Character to be sent to the PC.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending\r
- * data.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- void USBFS_PutChar(char8 txDataByte) \r
- {\r
- uint8 dataByte;\r
- dataByte = (uint8)txDataByte;\r
\r
- USBFS_LoadInEP(USBFS_cdc_data_in_ep, &dataByte, 1u);\r
+/*******************************************************************************\r
+* Function Name: USBFS_StrLen\r
+****************************************************************************//**\r
+*\r
+* Calculates length of a null terminated string.\r
+*\r
+* \param string: pointer to the string.\r
+*\r
+* \return\r
+* Length of the string\r
+*\r
+*******************************************************************************/\r
+static uint16 USBFS_StrLen(const char8 string[]) \r
+{\r
+ uint16 len = 0u;\r
+\r
+ while (string[len] != (char8)0)\r
+ {\r
+ len++;\r
}\r
\r
+ return ((uint16) len);\r
+}\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_PutCRLF\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Sends a carriage return (0x0D) and line feed (0x0A) to the PC\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending\r
- * data.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- void USBFS_PutCRLF(void) \r
- {\r
- const uint8 CYCODE txData[] = {0x0Du, 0x0Au};\r
\r
- USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)txData, 2u);\r
- }\r
+/***************************************************************************\r
+* Function Name: USBFS_PutString\r
+************************************************************************//**\r
+*\r
+* This function sends a null terminated string to the PC. This function will\r
+* block if there is not enough memory to place the whole string. It will block\r
+* until the entire string has been written to the transmit buffer.\r
+* The USBFS_CDCIsReady() function should be called before\r
+* sending data with a new call to USBFS_PutString(), to be sure\r
+* that the previous data has finished sending. This function sends\r
+* zero-length packet automatically, if the length of the last packet, sent\r
+* by this API, is equal to Max Packet Size\r
+*\r
+* \param string: pointer to the string to be sent to the PC.\r
+*\r
+* \globalvars\r
+*\r
+* USBFS_cdcDataInEp: CDC IN endpoint number used for sending\r
+* data.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+***************************************************************************/\r
+void USBFS_PutString(const char8 string[]) \r
+{\r
+ uint16 strLength;\r
+ uint16 sendLength;\r
+ uint16 bufIndex = 0u;\r
+\r
+ uint8 epNumber = USBFS_cdcDataInEp[USBFS_activeCom];\r
\r
+ /* Get length string length (it is terminated with zero). */\r
+ strLength = USBFS_StrLen(string);\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetCount\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function returns the number of bytes that were received from the PC.\r
- * The returned length value should be passed to USBFS_GetData() as\r
- * a parameter to read all received data. If all of the received data is not\r
- * read at one time by the USBFS_GetData() API, the unread data will\r
- * be lost.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns the number of received bytes. The maximum amount of received data at\r
- * a time is limited by the maximum packet size for the endpoint.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_out_ep: CDC OUT endpoint number used.\r
- *\r
- *******************************************************************************/\r
- uint16 USBFS_GetCount(void) \r
+ do\r
{\r
- uint16 bytesCount;\r
+ /* Limit length to maximum packet size of endpoint. */\r
+ sendLength = (strLength > USBFS_EP[epNumber].bufferSize) ?\r
+ USBFS_EP[epNumber].bufferSize : strLength;\r
\r
- if (USBFS_EP[USBFS_cdc_data_out_ep].apiEpState == USBFS_OUT_BUFFER_FULL)\r
- {\r
- bytesCount = USBFS_GetEPCount(USBFS_cdc_data_out_ep);\r
- }\r
- else\r
+ /* Load IN endpoint and expose it to host. */\r
+ USBFS_LoadInEP(epNumber, (const uint8 *)&string[bufIndex], sendLength);\r
+ strLength -= sendLength;\r
+\r
+ /* If more data are present to send or full packet was sent */\r
+ if ((strLength > 0u) || (sendLength == USBFS_EP[epNumber].bufferSize))\r
{\r
- bytesCount = 0u;\r
- }\r
+ bufIndex += sendLength;\r
\r
- return(bytesCount);\r
+ /* Wait until host read data from IN endpoint buffer. */\r
+ while (USBFS_IN_BUFFER_FULL == USBFS_EP[epNumber].apiEpState)\r
+ {\r
+ }\r
+\r
+ /* If last packet is exactly maximum packet size, it shall be followed\r
+ * by a zero-length packet to assure the end of segment is properly\r
+ * identified by the terminal.\r
+ */\r
+ if (0u == strLength)\r
+ {\r
+ USBFS_LoadInEP(epNumber, NULL, 0u);\r
+ }\r
+ }\r
}\r
+ while (strLength > 0u);\r
+}\r
+\r
+\r
+/***************************************************************************\r
+* Function Name: USBFS_PutChar\r
+************************************************************************//**\r
+*\r
+* This function writes a single character to the PC at a time. This is an\r
+* inefficient way to send large amounts of data.\r
+*\r
+* \param txDataByte: Character to be sent to the PC.\r
+*\r
+* \globalvars\r
+*\r
+* USBFS_cdcDataInEp: CDC IN endpoint number used for sending\r
+* data.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+***************************************************************************/\r
+void USBFS_PutChar(char8 txDataByte) \r
+{\r
+ uint8 dataByte;\r
+ dataByte = (uint8) txDataByte;\r
+\r
+ USBFS_LoadInEP(USBFS_cdcDataInEp[USBFS_activeCom], &dataByte, 1u);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_PutCRLF\r
+****************************************************************************//**\r
+*\r
+* This function sends a carriage return (0x0D) and line feed (0x0A) to the\r
+* PC. This APIis provided to mimic API provided by our other UART components\r
+*\r
+* \globalvars\r
+*\r
+* USBFS_cdcDataInEp: CDC IN endpoint number used for sending\r
+* data.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void USBFS_PutCRLF(void) \r
+{\r
+ const uint8 CYCODE txData[] = {0x0Du, 0x0Au};\r
+\r
+ USBFS_LoadInEP(USBFS_cdcDataInEp[USBFS_activeCom], (const uint8 *)txData, 2u);\r
+}\r
+\r
\r
+/*******************************************************************************\r
+* Function Name: USBFS_GetCount\r
+****************************************************************************//**\r
+*\r
+* This function returns the number of bytes that were received from the PC.\r
+* The returned length value should be passed to USBFS_GetData() as\r
+* a parameter to read all received data. If all of the received data is not\r
+* read at one time by the USBFS_GetData() API, the unread data will\r
+* be lost.\r
+*\r
+* \return\r
+* Returns the number of received bytes. The maximum amount of received data at\r
+* a time is limited by the maximum packet size for the endpoint.\r
+*\r
+* \globalvars\r
+* USBFS_cdcDataOutEp: CDC OUT endpoint number used.\r
+*\r
+*******************************************************************************/\r
+uint16 USBFS_GetCount(void) \r
+{\r
+ uint16 bytesCount;\r
+\r
+ uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom];\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_DataIsReady\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns a nonzero value if the component received data or received\r
- * zero-length packet. The USBFS_GetAll() or\r
- * USBFS_GetData() API should be called to read data from the buffer\r
- * and re-init OUT endpoint even when zero-length packet received.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * If the OUT packet received this function returns a nonzero value.\r
- * Otherwise zero is returned.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_out_ep: CDC OUT endpoint number used.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_DataIsReady(void) \r
+ if (USBFS_OUT_BUFFER_FULL == USBFS_EP[epNumber].apiEpState)\r
+ {\r
+ bytesCount = USBFS_GetEPCount(epNumber);\r
+ }\r
+ else\r
{\r
- return(USBFS_EP[USBFS_cdc_data_out_ep].apiEpState);\r
+ bytesCount = 0u;\r
}\r
\r
+ return (bytesCount);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_DataIsReady\r
+****************************************************************************//**\r
+*\r
+* This function returns a non-zero value if the component received data or\r
+* received zero-length packet. The USBFS_GetAll() or\r
+* USBFS_GetData() API should be called to read data from the buffer\r
+* and reinitialize the OUT endpoint even when a zero-length packet is\r
+* received. These APIs will return zero value when zero-length packet is\r
+* received.\r
+*\r
+* \return\r
+* If the OUT packet is received, this function returns a non-zero value.\r
+* Otherwise, it returns zero.\r
+*\r
+* \globalvars\r
+* USBFS_cdcDataOutEp: CDC OUT endpoint number used.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_DataIsReady(void) \r
+{\r
+ return (USBFS_GetEPState(USBFS_cdcDataOutEp[USBFS_activeCom]));\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_CDCIsReady\r
+****************************************************************************//**\r
+*\r
+* This function returns a non-zero value if the component is ready to send more\r
+* data to the PC; otherwise, it returns zero. The function should be called\r
+* before sending new data when using any of the following APIs:\r
+* USBFS_PutData(),USBFS_PutString(),\r
+* USBFS_PutChar or USBFS_PutCRLF(),\r
+* to be sure that the previous data has finished sending.\r
+*\r
+* \return\r
+* If the buffer can accept new data, this function returns a non-zero value.\r
+* Otherwise, it returns zero.\r
+*\r
+* \globalvars\r
+* USBFS_cdcDataInEp: CDC IN endpoint number used.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_CDCIsReady(void) \r
+{\r
+ return (USBFS_GetEPState(USBFS_cdcDataInEp[USBFS_activeCom]));\r
+}\r
+\r
+\r
+/***************************************************************************\r
+* Function Name: USBFS_GetData\r
+************************************************************************//**\r
+*\r
+* This function gets a specified number of bytes from the input buffer and\r
+* places them in a data array specified by the passed pointer.\r
+* The USBFS_DataIsReady() API should be called first, to be sure\r
+* that data is received from the host. If all received data will not be read at\r
+* once, the unread data will be lost. The USBFS_GetData() API should\r
+* be called to get the number of bytes that were received.\r
+*\r
+* \param pData: Pointer to the data array where data will be placed.\r
+* \param Length: Number of bytes to read into the data array from the RX buffer.\r
+* Maximum length is limited by the the number of received bytes\r
+* or 64 bytes.\r
+*\r
+* \return\r
+* Number of bytes which function moves from endpoint RAM into the\r
+* data array. The function moves fewer than the requested number\r
+* of bytes if the host sends fewer bytes than requested or sends\r
+* zero-length packet.\r
+*\r
+* \globalvars\r
+* USBFS_cdcDataOutEp: CDC OUT endpoint number used.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+***************************************************************************/\r
+uint16 USBFS_GetData(uint8* pData, uint16 length) \r
+{\r
+ uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom];\r
+\r
+ /* Read data from OUT endpoint buffer. */\r
+ length = USBFS_ReadOutEP(epNumber, pData, length);\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_CDCIsReady\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function returns a nonzero value if the component is ready to send more\r
- * data to the PC; otherwise, it returns zero. The function should be called\r
- * before sending new data when using any of the following APIs:\r
- * USBFS_PutData(),USBFS_PutString(),\r
- * USBFS_PutChar or USBFS_PutCRLF(),\r
- * to be sure that the previous data has finished sending.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * If the buffer can accept new data, this function returns a nonzero value.\r
- * Otherwise, it returns zero.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_in_ep: CDC IN endpoint number used.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_CDCIsReady(void) \r
+#if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ /* Wait until DMA complete transferring data from OUT endpoint buffer. */\r
+ while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(epNumber))\r
{\r
- return(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState);\r
}\r
\r
+ /* Enable OUT endpoint to communicate with host. */\r
+ USBFS_EnableOutEP(epNumber);\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
+\r
+ return (length);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_GetAll\r
+****************************************************************************//**\r
+*\r
+* This function gets all bytes of received data from the input buffer and\r
+* places them into a specified data array. The\r
+* USBFS_DataIsReady() API should be called first, to be sure\r
+* that data is received from the host.\r
+*\r
+* \param pData: Pointer to the data array where data will be placed.\r
+*\r
+* \return\r
+* Number of bytes received. The maximum amount of the received at a time\r
+* data is 64 bytes.\r
+*\r
+* \globalvars\r
+* - \ref USBFS_cdcDataOutEp: CDC OUT endpoint number used.\r
+* - \ref USBFS_EP[].bufferSize: EP max packet size is used as a\r
+* length to read all data from the EP buffer.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+*******************************************************************************/\r
+uint16 USBFS_GetAll(uint8* pData) \r
+{\r
+ uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom];\r
+ uint16 dataLength;\r
+\r
+ /* Read data from OUT endpoint buffer. */\r
+ dataLength = USBFS_ReadOutEP(epNumber, pData, USBFS_EP[epNumber].bufferSize);\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetData\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function gets a specified number of bytes from the input buffer and\r
- * places them in a data array specified by the passed pointer.\r
- * The USBFS_DataIsReady() API should be called first, to be sure\r
- * that data is received from the host. If all received data will not be read at\r
- * once, the unread data will be lost. The USBFS_GetData() API should\r
- * be called to get the number of bytes that were received.\r
- *\r
- * Parameters:\r
- * pData: Pointer to the data array where data will be placed.\r
- * Length: Number of bytes to read into the data array from the RX buffer.\r
- * Maximum length is limited by the the number of received bytes.\r
- *\r
- * Return:\r
- * Number of bytes received.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_out_ep: CDC OUT endpoint number used.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- uint16 USBFS_GetData(uint8* pData, uint16 length) \r
+#if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ /* Wait until DMA complete transferring data from OUT endpoint buffer. */\r
+ while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(epNumber))\r
{\r
- return(USBFS_ReadOutEP(USBFS_cdc_data_out_ep, pData, length));\r
}\r
\r
+ /* Enable OUT endpoint to communicate with host. */\r
+ USBFS_EnableOutEP(epNumber);\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
+\r
+ return (dataLength);\r
+}\r
+\r
+\r
+/***************************************************************************\r
+* Function Name: USBFS_GetChar\r
+************************************************************************//**\r
+*\r
+* This function reads one byte of received data from the buffer. If more than\r
+* one byte has been received from the host, the rest of the data will be lost.\r
+*\r
+* \return\r
+* Received one character.\r
+*\r
+* \globalvars\r
+* USBFS_cdcDataOutEp: CDC OUT endpoint number used.\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+***************************************************************************/\r
+uint8 USBFS_GetChar(void) \r
+{\r
+ uint8 rxData;\r
+ uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom];\r
+\r
+ (void) USBFS_ReadOutEP(epNumber, &rxData, 1u);\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetAll\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Gets all bytes of received data from the input buffer and places it into a\r
- * specified data array. USBFS_DataIsReady() API should be called\r
- * before, to be sure that data is received from the Host.\r
- *\r
- * Parameters:\r
- * pData: Pointer to the data array where data will be placed.\r
- *\r
- * Return:\r
- * Number of bytes received.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_out_ep: CDC OUT endpoint number used.\r
- * USBFS_EP[].bufferSize: EP max packet size is used as a length\r
- * to read all data from the EP buffer.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- uint16 USBFS_GetAll(uint8* pData) \r
+#if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ /* Wait until DMA complete transferring data from OUT endpoint buffer. */\r
+ while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(epNumber))\r
{\r
- return (USBFS_ReadOutEP(USBFS_cdc_data_out_ep, pData,\r
- USBFS_EP[USBFS_cdc_data_out_ep].bufferSize));\r
}\r
\r
+ /* Enable OUT endpoint to communicate with host. */\r
+ USBFS_EnableOutEP(epNumber);\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetChar\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function reads one byte of received data from the buffer. If more than\r
- * one byte has been received from the host, the rest of the data will be lost.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Received one character.\r
- *\r
- * Global variables:\r
- * USBFS_cdc_data_out_ep: CDC OUT endpoint number used.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_GetChar(void) \r
- {\r
- uint8 rxData;\r
+ return (rxData);\r
+}\r
\r
- (void) USBFS_ReadOutEP(USBFS_cdc_data_out_ep, &rxData, 1u);\r
\r
- return(rxData);\r
- }\r
+/*******************************************************************************\r
+* Function Name: USBFS_IsLineChanged\r
+****************************************************************************//**\r
+*\r
+* This function returns clear on read status of the line. It returns not zero\r
+* value when the host sends updated coding or control information to the\r
+* device. The USBFS_GetDTERate(), USBFS_GetCharFormat()\r
+* or USBFS_GetParityType() or USBFS_GetDataBits() API\r
+* should be called to read data coding information.\r
+* The USBFS_GetLineControl() API should be called to read line\r
+* control information.\r
+*\r
+* \return\r
+* If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE requests are received, it\r
+* returns a non-zero value. Otherwise, it returns zero.\r
+* Return Value | Description\r
+* -----------------------------|--------------------------\r
+* USBUART_LINE_CODING_CHANGED | Line coding changed\r
+* USBUART_LINE_CONTROL_CHANGED | Line control changed\r
+*\r
+* \globalvars\r
+* - \ref USBFS_transferState: it is checked to be sure then OUT\r
+* data phase has been complete, and data written to the lineCoding or\r
+* Control Bitmap buffer.\r
+* - \ref USBFS_linesChanged: used as a flag to be aware that\r
+* Host has been sent request for changing Line Coding or Control Bitmap.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_IsLineChanged(void) \r
+{\r
+ uint8 state = 0u;\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_IsLineChanged\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function returns clear on read status of the line. It returns not zero\r
- * value when the host sends updated coding or control information to the\r
- * device. The USBFS_GetDTERate(), USBFS_GetCharFormat()\r
- * or USBFS_GetParityType() or USBFS_GetDataBits() API\r
- * should be called to read data coding information.\r
- * The USBFS_GetLineControl() API should be called to read line\r
- * control information.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE requests are received, it\r
- * returns a nonzero value. Otherwise, it returns zero.\r
- *\r
- * Global variables:\r
- * USBFS_transferState: it is checked to be sure then OUT data\r
- * phase has been complete, and data written to the lineCoding or Control\r
- * Bitmap buffer.\r
- * USBFS_lineChanged: used as a flag to be aware that Host has been\r
- * sent request for changing Line Coding or Control Bitmap.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_IsLineChanged(void) \r
+ /* transferState is checked to be sure then OUT data phase has been complete */\r
+ if (USBFS_transferState == USBFS_TRANS_STATE_IDLE)\r
{\r
- uint8 state = 0u;\r
-\r
- /* transferState is checked to be sure then OUT data phase has been complete */\r
- if(USBFS_transferState == USBFS_TRANS_STATE_IDLE)\r
+ if (USBFS_linesChanged[USBFS_activeCom] != 0u)\r
{\r
- if(USBFS_lineChanged != 0u)\r
- {\r
- state = USBFS_lineChanged;\r
- USBFS_lineChanged = 0u;\r
- }\r
+ state = USBFS_linesChanged[USBFS_activeCom];\r
+ USBFS_linesChanged[USBFS_activeCom] = 0u;\r
}\r
-\r
- return(state);\r
}\r
\r
+ return (state);\r
+}\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetDTERate\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns the data terminal rate set for this port in bits per second.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns a uint32 value of the data rate in bits per second.\r
- *\r
- * Global variables:\r
- * USBFS_lineCoding: First four bytes converted to uint32\r
- * depend on compiler, and returned as a data rate.\r
- *\r
- *******************************************************************************/\r
- uint32 USBFS_GetDTERate(void) \r
- {\r
- uint32 rate;\r
\r
- rate = USBFS_lineCoding[USBFS_LINE_CODING_RATE + 3u];\r
- rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE + 2u];\r
- rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE + 1u];\r
- rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE];\r
+/***************************************************************************\r
+* Function Name: USBFS_GetDTERate\r
+************************************************************************//**\r
+*\r
+* This function returns the data terminal rate set for this port in bits\r
+* per second.\r
+*\r
+* \return\r
+* Returns a uint32 value of the data rate in bits per second.\r
+*\r
+* \globalvars\r
+* USBFS_linesCoding: First four bytes converted to uint32\r
+* depend on compiler, and returned as a data rate.\r
+*\r
+*******************************************************************************/\r
+uint32 USBFS_GetDTERate(void) \r
+{\r
+ uint32 rate;\r
\r
- return(rate);\r
- }\r
+ rate = USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE + 3u];\r
+ rate = (rate << 8u) | USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE + 2u];\r
+ rate = (rate << 8u) | USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE + 1u];\r
+ rate = (rate << 8u) | USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE];\r
\r
+ return (rate);\r
+}\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetCharFormat\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns the number of stop bits.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns the number of stop bits.\r
- *\r
- * Global variables:\r
- * USBFS_lineCoding: used to get a parameter.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_GetCharFormat(void) \r
- {\r
- return(USBFS_lineCoding[USBFS_LINE_CODING_STOP_BITS]);\r
- }\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_GetCharFormat\r
+****************************************************************************//**\r
+*\r
+* Returns the number of stop bits.\r
+*\r
+* \return\r
+* Returns the number of stop bits.\r
+* Return |Value Description\r
+* ---------------------|-------------------\r
+* USBUART_1_STOPBIT | 1 stop bit\r
+* USBUART_1_5_STOPBITS | 1,5 stop bits\r
+* USBUART_2_STOPBITS | 2 stop bits\r
+*\r
+*\r
+* \globalvars\r
+* USBFS_linesCoding: used to get a parameter.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_GetCharFormat(void) \r
+{\r
+ return (USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_STOP_BITS]);\r
+}\r
\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetParityType\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns the parity type for the CDC port.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns the parity type.\r
- *\r
- * Global variables:\r
- * USBFS_lineCoding: used to get a parameter.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_GetParityType(void) \r
+/*******************************************************************************\r
+* Function Name: USBFS_GetParityType\r
+****************************************************************************//**\r
+*\r
+* This function returns the parity type for the CDC port.\r
+*\r
+* \return\r
+* Returns the parity type.\r
+* Return | Value Description\r
+* ----------------------|-------------------\r
+* USBUART_PARITY_NONE | 1 stop bit\r
+* USBUART_PARITY_ODD | 1,5 stop bits\r
+* USBUART_PARITY_EVEN | 2 stop bits\r
+* USBUART_PARITY_MARK | Mark\r
+* USBUART_PARITY_SPACE | Space\r
+*\r
+* \globalvars\r
+* USBFS_linesCoding: used to get a parameter.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_GetParityType(void) \r
+{\r
+ return (USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_PARITY]);\r
+}\r
+\r
+\r
+/***************************************************************************\r
+* Function Name: USBFS_GetDataBits\r
+************************************************************************//**\r
+*\r
+* This function returns the number of data bits for the CDC port.\r
+*\r
+* \return\r
+* Returns the number of data bits.\r
+* The number of data bits can be 5, 6, 7, 8 or 16.\r
+*\r
+* \globalvars\r
+* USBFS_linesCoding: used to get a parameter.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_GetDataBits(void) \r
+{\r
+ return (USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_DATA_BITS]);\r
+}\r
+\r
+\r
+/***************************************************************************\r
+* Function Name: USBFS_GetLineControl\r
+************************************************************************//**\r
+*\r
+* This function returns Line control bitmap that the host sends to the\r
+* device.\r
+*\r
+* \return\r
+* Returns Line control bitmap.\r
+* Return |Value Notes\r
+* -------------------------|-----------------------------------------------\r
+* USBUART_LINE_CONTROL_DTR |Indicates that a DTR signal is present. This signal corresponds to V.24 signal 108/2 and RS232 signal DTR.\r
+* USBUART_LINE_CONTROL_RTS |Carrier control for half-duplex modems. This signal corresponds to V.24 signal 105 and RS232 signal RTS.\r
+* RESERVED |The rest of the bits are reserved.\r
+*\r
+* *Note* Some terminal emulation programs do not properly handle these\r
+* control signals. They update information about DTR and RTS state only\r
+* when the RTS signal changes the state.\r
+*\r
+* \globalvars\r
+* USBFS_linesControlBitmap: used to get a parameter.\r
+*\r
+*******************************************************************************/\r
+uint16 USBFS_GetLineControl(void) \r
+{\r
+ return (USBFS_linesControlBitmap[USBFS_activeCom]);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_SendSerialState\r
+****************************************************************************//**\r
+*\r
+* Sends the serial state notification to the host using the interrupt\r
+* endpoint for the COM port selected using the API SetComPort().The\r
+* USBFS_NotificationIsReady() API must be called to check if the\r
+* Component is ready to send more serial state to the host. The API will\r
+* not send the notification data if the interrupt endpoint Max Packet Size\r
+* is less than the required 10 bytes.\r
+*\r
+* \param uint16 serialState\r
+* 16-bit value that will be sent from the device to the\r
+* host as SERIAL_STATE notification using the IN interrupt endpoint. Refer\r
+* to revision 1.2 of the CDC PSTN Subclass specification for bit field\r
+* definitions of the 16-bit serial state value.\r
+*\r
+*******************************************************************************/\r
+void USBFS_SendSerialState (uint16 serialState) \r
+{\r
+ uint8 epNumber = USBFS_cdcCommInInterruptEp[USBFS_activeCom];\r
+\r
+ if(USBFS_SERIAL_STATE_SIZE <= USBFS_EP[epNumber].bufferSize)\r
{\r
- return(USBFS_lineCoding[USBFS_LINE_CODING_PARITY]);\r
+ /* Save current SERIAL_STATE bitmap. */\r
+ USBFS_serialStateBitmap[USBFS_activeCom] = serialState;\r
+\r
+ /* Add interface number */\r
+ USBFS_serialStateNotification.wIndex = USBFS_EP[epNumber].interface;\r
+\r
+ /*Form SERIAL_STATE data*/\r
+ USBFS_serialStateNotification.wSerialState = LO8(USBFS_serialStateBitmap[USBFS_activeCom]);\r
+ USBFS_serialStateNotification.wSerialStateMSB = HI8(USBFS_serialStateBitmap[USBFS_activeCom]);\r
+\r
+ USBFS_LoadInEP(epNumber, (uint8 *) &USBFS_serialStateNotification, sizeof(USBFS_serialStateNotification));\r
}\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_GetSerialState\r
+****************************************************************************//**\r
+*\r
+* This function returns the current serial state value for the COM port\r
+* selected using the API SetComPort().\r
+*\r
+* \return\r
+* 16-bit serial state value. Refer to revision 1.2 of the CDC PSTN Subclass\r
+* specification for bit field definitions of the 16-bit serial state value.\r
+*\r
+*******************************************************************************/\r
+uint16 USBFS_GetSerialState(void) \r
+{\r
+ return USBFS_serialStateBitmap[USBFS_activeCom];\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: USBFS_NotificationIsReady\r
+****************************************************************************//**\r
+*\r
+* This function returns a non-zero value if the Component is ready to send\r
+* more notifications to the host; otherwise, it returns zero. The function\r
+* should be called before sending new notifications when using\r
+* USBFS_SendSerialState() to ensure that any previous\r
+* notification data has been already sent to the host.\r
+*\r
+* \return\r
+* If the buffer can accept new data(endpoint buffer not full), this\r
+* function returns a non-zero value. Otherwise, it returns zero.\r
+*\r
+* \globalvars\r
+* USBFS_cdcDataInEp: CDC IN endpoint number used.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_NotificationIsReady(void) \r
+{\r
+ return (USBFS_EP[USBFS_cdcCommInInterruptEp[USBFS_activeCom]].apiEpState);\r
+}\r
\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetDataBits\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns the number of data bits for the CDC port.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns the number of data bits.\r
- * The number of data bits can be 5, 6, 7, 8 or 16.\r
- *\r
- * Global variables:\r
- * USBFS_lineCoding: used to get a parameter.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_GetDataBits(void) \r
+/*******************************************************************************\r
+* Function Name: USBFS_SetComPort\r
+****************************************************************************//**\r
+*\r
+* This function allows the user to select from one of the two COM ports\r
+* they wish to address in the instance of having multiple COM ports\r
+* instantiated though the use of a composite device. Once set, all future\r
+* function calls related to the USBUART will be affected. This addressed\r
+* COM port can be changed during run time.\r
+*\r
+* \param comNumber\r
+* Contains the COM interface the user wishes to address. Value can either\r
+* be 0 or 1 since a maximum of only 2 COM ports can be supported. Note that\r
+* this COM port number is not the COM port number assigned on the PC side\r
+* for the UART communication. If a value greater than 1 is passed, the\r
+* function returns without performing any action.\r
+*\r
+*******************************************************************************/\r
+void USBFS_SetComPort(uint8 comNumber) \r
+{\r
+ if ((USBFS_activeCom != comNumber) && \\r
+ (comNumber < USBFS_MAX_MULTI_COM_NUM ))\r
{\r
- return(USBFS_lineCoding[USBFS_LINE_CODING_DATA_BITS]);\r
+ USBFS_activeCom = comNumber;\r
}\r
+}\r
+\r
\r
+/*******************************************************************************\r
+* Function Name: USBFS_GetComPort\r
+****************************************************************************//**\r
+*\r
+* This function returns the current selected COM port that the user is\r
+* currently addressing in the instance of having multiple COM ports\r
+* instantiated though the use of a composite device.\r
+*\r
+* \return\r
+* Returns the currently selected COM port. Value can either be 0 or 1 since\r
+* a maximum of only 2 COM ports can be supported. . Note that this COM port\r
+* number is not the COM port number assigned on the PC side for the UART\r
+* communication.\r
+*\r
+*******************************************************************************/\r
+uint8 USBFS_GetComPort(void) \r
+{\r
+ return (USBFS_activeCom);\r
+}\r
+\r
+\r
+#endif /* (USBFS_ENABLE_CDC_CLASS_API) */\r
\r
- /*******************************************************************************\r
- * Function Name: USBFS_GetLineControl\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns Line control bitmap.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns Line control bitmap.\r
- *\r
- * Global variables:\r
- * USBFS_lineControlBitmap: used to get a parameter.\r
- *\r
- *******************************************************************************/\r
- uint16 USBFS_GetLineControl(void) \r
+\r
+/***************************************************************************\r
+* Function Name: USBFS_Cdc_EpInit\r
+************************************************************************//**\r
+*\r
+* \internal\r
+* This routine decide type of endpoint (IN, OUT, Notification) and same to\r
+* appropriate global variables according to COM port number.\r
+* USBFS_cdcDataInEp[], USBFS_cdcCommInInterruptEp[],\r
+* USBFS_cdcDataOutEp[]\r
+*\r
+* \param pEP: Pointer to structure with current EP description.\r
+* \param epNum: EP number\r
+* \param cdcComNums: Bit array of current COM ports for CDC IN, OUT,\r
+* and notification EPs(0 - COM port 1, 1- COM port 2)\r
+*\r
+* \return\r
+* Updated cdcComNums\r
+*\r
+* \reentrant\r
+* No.\r
+*\r
+***************************************************************************/\r
+uint8 USBFS_Cdc_EpInit(const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP, uint8 epNum, uint8 cdcComNums) \r
+{\r
+ uint8 epType;\r
+\r
+ epType = pEP->attributes & USBFS_EP_TYPE_MASK;\r
+\r
+ if (0u != (pEP->addr & USBFS_DIR_IN))\r
{\r
- return(USBFS_lineControlBitmap);\r
- }\r
+ if (epType != USBFS_EP_TYPE_INT)\r
+ {\r
+ USBFS_cdcDataInEp[USBFS_GET_EP_COM_NUM(cdcComNums, USBFS_CDC_IN_EP)] = epNum;\r
+ cdcComNums |= (uint8)(USBFS_COM_PORT2 << USBFS_CDC_IN_EP);\r
+ }\r
+ else\r
+ {\r
\r
-#endif /* USBFS_ENABLE_CDC_CLASS_API*/\r
+ USBFS_cdcCommInInterruptEp[USBFS_GET_EP_COM_NUM(cdcComNums, USBFS_CDC_NOTE_EP)] = epNum;\r
+ cdcComNums |= (uint8)(USBFS_COM_PORT2 << USBFS_CDC_NOTE_EP);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (epType != USBFS_EP_TYPE_INT)\r
+ {\r
+ USBFS_cdcDataOutEp[USBFS_GET_EP_COM_NUM(cdcComNums, USBFS_CDC_OUT_EP)] = epNum;\r
+ cdcComNums |= (uint8)(USBFS_COM_PORT2 << USBFS_CDC_OUT_EP);\r
+ }\r
+ }\r
+ return (cdcComNums);\r
+}\r
\r
\r
/*******************************************************************************\r
/* `#END` */\r
\r
-#endif /* USBFS_ENABLE_CDC_CLASS*/\r
+#endif /* (USBFS_ENABLE_CDC_CLASS) */\r
\r
\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: USBFS_cdc.h\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_cdc.h\r
+* \version 3.10\r
*\r
-* Description:\r
-* Header File for the USBFS component.\r
-* Contains CDC class prototypes and constant values.\r
+* \brief\r
+* This file provides function prototypes and constants for the USBFS component \r
+* CDC class.\r
*\r
* Related Document:\r
* Universal Serial Bus Class Definitions for Communication Devices Version 1.1\r
*\r
********************************************************************************\r
-* Copyright 2012-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2012-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#if !defined(CY_USBFS_USBFS_cdc_H)\r
#define CY_USBFS_USBFS_cdc_H\r
\r
-#include "cytypes.h"\r
+#include "USBFS.h"\r
\r
\r
-/***************************************\r
+/*******************************************************************************\r
* Prototypes of the USBFS_cdc API.\r
-***************************************/\r
-\r
+*******************************************************************************/\r
+/**\r
+* \addtogroup group_cdc\r
+* @{\r
+*/\r
#if (USBFS_ENABLE_CDC_CLASS_API != 0u)\r
- void USBFS_CDC_Init(void) ;\r
+ uint8 USBFS_CDC_Init(void) ;\r
void USBFS_PutData(const uint8* pData, uint16 length) ;\r
- void USBFS_PutString(const char8 string[]) ;\r
+ void USBFS_PutString(const char8 string[]) ;\r
void USBFS_PutChar(char8 txDataByte) ;\r
- void USBFS_PutCRLF(void) ;\r
- uint16 USBFS_GetCount(void) ;\r
- uint8 USBFS_CDCIsReady(void) ;\r
- uint8 USBFS_DataIsReady(void) ;\r
- uint16 USBFS_GetData(uint8* pData, uint16 length) ;\r
- uint16 USBFS_GetAll(uint8* pData) ;\r
- uint8 USBFS_GetChar(void) ;\r
- uint8 USBFS_IsLineChanged(void) ;\r
- uint32 USBFS_GetDTERate(void) ;\r
- uint8 USBFS_GetCharFormat(void) ;\r
- uint8 USBFS_GetParityType(void) ;\r
- uint8 USBFS_GetDataBits(void) ;\r
- uint16 USBFS_GetLineControl(void) ;\r
-#endif /* USBFS_ENABLE_CDC_CLASS_API */\r
-\r
-\r
-/***************************************\r
+ void USBFS_PutCRLF(void) ;\r
+ uint16 USBFS_GetCount(void) ;\r
+ uint8 USBFS_CDCIsReady(void) ;\r
+ uint8 USBFS_DataIsReady(void) ;\r
+ uint16 USBFS_GetData(uint8* pData, uint16 length) ;\r
+ uint16 USBFS_GetAll(uint8* pData) ;\r
+ uint8 USBFS_GetChar(void) ;\r
+ uint8 USBFS_IsLineChanged(void) ;\r
+ uint32 USBFS_GetDTERate(void) ;\r
+ uint8 USBFS_GetCharFormat(void) ;\r
+ uint8 USBFS_GetParityType(void) ;\r
+ uint8 USBFS_GetDataBits(void) ;\r
+ uint16 USBFS_GetLineControl(void) ;\r
+ void USBFS_SendSerialState (uint16 serialState) ;\r
+ uint16 USBFS_GetSerialState (void) ;\r
+ void USBFS_SetComPort (uint8 comNumber) ;\r
+ uint8 USBFS_GetComPort (void) ;\r
+ uint8 USBFS_NotificationIsReady(void) ;\r
+\r
+#endif /* (USBFS_ENABLE_CDC_CLASS_API) */\r
+/** @} cdc */\r
+\r
+/*******************************************************************************\r
* Constants for USBFS_cdc API.\r
-***************************************/\r
+*******************************************************************************/\r
\r
/* CDC Class-Specific Request Codes (CDC ver 1.2 Table 19) */\r
#define USBFS_CDC_SET_LINE_CODING (0x20u)\r
#define USBFS_CDC_GET_LINE_CODING (0x21u)\r
#define USBFS_CDC_SET_CONTROL_LINE_STATE (0x22u)\r
\r
+/*PSTN Subclass Specific Notifications (CDC ver 1.2 Table 30)*/\r
+#define USBFS_SERIAL_STATE (0x20u)\r
+\r
#define USBFS_LINE_CODING_CHANGED (0x01u)\r
#define USBFS_LINE_CONTROL_CHANGED (0x02u)\r
\r
#define USBFS_LINE_CONTROL_DTR (0x01u)\r
#define USBFS_LINE_CONTROL_RTS (0x02u)\r
\r
+#define USBFS_MAX_MULTI_COM_NUM (2u) \r
+\r
+#define USBFS_COM_PORT1 (0u) \r
+#define USBFS_COM_PORT2 (1u) \r
\r
-/***************************************\r
+#define USBFS_SUCCESS (0u)\r
+#define USBFS_FAILURE (1u)\r
+\r
+#define USBFS_SERIAL_STATE_SIZE (10u)\r
+\r
+/* SerialState constants*/\r
+#define USBFS_SERIAL_STATE_REQUEST_TYPE (0xA1u)\r
+#define USBFS_SERIAL_STATE_LENGTH (0x2u)\r
+\r
+/*******************************************************************************\r
* External data references\r
-***************************************/\r
+*******************************************************************************/\r
+/**\r
+* \addtogroup group_cdc\r
+* @{\r
+*/\r
+extern volatile uint8 USBFS_linesCoding[USBFS_MAX_MULTI_COM_NUM][USBFS_LINE_CODING_SIZE];\r
+extern volatile uint8 USBFS_linesChanged[USBFS_MAX_MULTI_COM_NUM];\r
+extern volatile uint16 USBFS_linesControlBitmap[USBFS_MAX_MULTI_COM_NUM];\r
+extern volatile uint16 USBFS_serialStateBitmap[USBFS_MAX_MULTI_COM_NUM];\r
+extern volatile uint8 USBFS_cdcDataInEp[USBFS_MAX_MULTI_COM_NUM];\r
+extern volatile uint8 USBFS_cdcDataOutEp[USBFS_MAX_MULTI_COM_NUM];\r
+extern volatile uint8 USBFS_cdcCommInInterruptEp[USBFS_MAX_MULTI_COM_NUM];\r
+/** @} cdc */\r
+\r
+/*******************************************************************************\r
+* The following code is DEPRECATED and\r
+* must not be used.\r
+*******************************************************************************/\r
+\r
\r
-extern volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE];\r
-extern volatile uint8 USBFS_lineChanged;\r
-extern volatile uint16 USBFS_lineControlBitmap;\r
-extern volatile uint8 USBFS_cdc_data_in_ep;\r
-extern volatile uint8 USBFS_cdc_data_out_ep;\r
+#define USBFS_lineCoding USBFS_linesCoding[0]\r
+#define USBFS_lineChanged USBFS_linesChanged[0]\r
+#define USBFS_lineControlBitmap USBFS_linesControlBitmap[0]\r
+#define USBFS_cdc_data_in_ep USBFS_cdcDataInEp[0]\r
+#define USBFS_cdc_data_out_ep USBFS_cdcDataOutEp[0]\r
\r
-#endif /* CY_USBFS_USBFS_cdc_H */\r
+#endif /* (CY_USBFS_USBFS_cdc_H) */\r
\r
\r
/* [] END OF FILE */\r
;******************************************************************************\r
; File Name: USBFS_cdc.inf\r
-; Version 2.80\r
+; Version 3.10\r
;\r
; Description:\r
; Windows USB CDC setup file for USBUART Device.\r
;\r
;******************************************************************************\r
-; Copyright 2007-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright 2007-2016, Cypress Semiconductor Corporation. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions,\r
; disclaimers, and limitations in the end user license agreement accompanying\r
; the software package with which this file was provided.\r
\r
[DeviceList.NTx86]\r
%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_00\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_01\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_02\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_03\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_04\r
\r
[DeviceList.NTia64]\r
%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_00\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_01\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_02\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_03\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_04\r
\r
[DeviceList.NTamd64]\r
%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_00\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_01\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_02\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_03\r
+%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_04\r
\r
\r
;------------------------------------------------------------------------------\r
-/*******************************************************************************\r
-* File Name: USBFS_cls.c\r
-* Version 2.80\r
-*\r
-* Description:\r
-* USB Class request handler.\r
+/***************************************************************************//**\r
+* \file USBFS_cls.c\r
+* \version 3.10\r
*\r
-* Note:\r
+* \brief\r
+* This file contains the USB Class request handler.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
-\r
-#if(USBFS_EXTERN_CLS == USBFS_FALSE)\r
-\r
#include "USBFS_pvt.h"\r
\r
\r
+#if(USBFS_EXTERN_CLS == USBFS_FALSE)\r
\r
/***************************************\r
* User Implemented Class Driver Declarations.\r
\r
/*******************************************************************************\r
* Function Name: USBFS_DispatchClassRqst\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* This routine dispatches class specific requests depend on interface class.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_DispatchClassRqst(void) \r
{\r
- uint8 requestHandled = USBFS_FALSE;\r
- uint8 interfaceNumber = 0u;\r
+ uint8 requestHandled;\r
+ uint8 interfaceNumber;\r
\r
- switch(CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK)\r
+ /* Get interface to which request is intended. */\r
+ switch (USBFS_bmRequestTypeReg & USBFS_RQST_RCPT_MASK)\r
{\r
- case USBFS_RQST_RCPT_IFC: /* Class-specific request directed to an interface */\r
- interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); /* wIndexLo contain Interface number */\r
+ case USBFS_RQST_RCPT_IFC:\r
+ /* Class-specific request directed to interface: wIndexLoReg \r
+ * contains interface number.\r
+ */\r
+ interfaceNumber = (uint8) USBFS_wIndexLoReg;\r
break;\r
- case USBFS_RQST_RCPT_EP: /* Class-specific request directed to the endpoint */\r
- /* Find related interface to the endpoint, wIndexLo contain EP number */\r
- interfaceNumber = USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) &\r
- USBFS_DIR_UNUSED].interface;\r
+ \r
+ case USBFS_RQST_RCPT_EP:\r
+ /* Class-specific request directed to endpoint: wIndexLoReg contains \r
+ * endpoint number. Find interface related to endpoint, \r
+ */\r
+ interfaceNumber = USBFS_EP[USBFS_wIndexLoReg & USBFS_DIR_UNUSED].interface;\r
break;\r
- default: /* RequestHandled is initialized as FALSE by default */\r
+ \r
+ default:\r
+ /* Default interface is zero. */\r
+ interfaceNumber = 0u;\r
break;\r
}\r
- /* Handle Class request depend on interface type */\r
- switch(USBFS_interfaceClass[interfaceNumber])\r
+\r
+#if (defined(USBFS_ENABLE_HID_CLASS) ||\\r
+ defined(USBFS_ENABLE_AUDIO_CLASS) ||\\r
+ defined(USBFS_ENABLE_CDC_CLASS) ||\\r
+ USBFS_ENABLE_MSC_CLASS)\r
+\r
+ /* Handle class request depends on interface type. */\r
+ switch (USBFS_interfaceClass[interfaceNumber])\r
{\r
+ #if defined(USBFS_ENABLE_HID_CLASS)\r
case USBFS_CLASS_HID:\r
- #if defined(USBFS_ENABLE_HID_CLASS)\r
- requestHandled = USBFS_DispatchHIDClassRqst();\r
- #endif /* USBFS_ENABLE_HID_CLASS */\r
+ requestHandled = USBFS_DispatchHIDClassRqst();\r
break;\r
+ #endif /* (USBFS_ENABLE_HID_CLASS) */\r
+ \r
+ #if defined(USBFS_ENABLE_AUDIO_CLASS)\r
case USBFS_CLASS_AUDIO:\r
- #if defined(USBFS_ENABLE_AUDIO_CLASS)\r
- requestHandled = USBFS_DispatchAUDIOClassRqst();\r
- #endif /* USBFS_CLASS_AUDIO */\r
+ requestHandled = USBFS_DispatchAUDIOClassRqst();\r
break;\r
+ #endif /* (USBFS_CLASS_AUDIO) */\r
+ \r
+ #if defined(USBFS_ENABLE_CDC_CLASS)\r
case USBFS_CLASS_CDC:\r
- #if defined(USBFS_ENABLE_CDC_CLASS)\r
- requestHandled = USBFS_DispatchCDCClassRqst();\r
- #endif /* USBFS_ENABLE_CDC_CLASS */\r
+ requestHandled = USBFS_DispatchCDCClassRqst();\r
break;\r
- default: /* requestHandled is initialized as FALSE by default */\r
+ #endif /* (USBFS_ENABLE_CDC_CLASS) */\r
+ \r
+ #if (USBFS_ENABLE_MSC_CLASS)\r
+ case USBFS_CLASS_MSD:\r
+ #if (USBFS_HANDLE_MSC_REQUESTS)\r
+ /* MSC requests are handled by the component. */\r
+ requestHandled = USBFS_DispatchMSCClassRqst();\r
+ #elif defined(USBFS_DISPATCH_MSC_CLASS_RQST_CALLBACK)\r
+ /* MSC requests are handled by user defined callbcak. */\r
+ requestHandled = USBFS_DispatchMSCClassRqst_Callback();\r
+ #else\r
+ /* MSC requests are not handled. */\r
+ requestHandled = USBFS_FALSE;\r
+ #endif /* (USBFS_HANDLE_MSC_REQUESTS) */\r
+ break;\r
+ #endif /* (USBFS_ENABLE_MSC_CLASS) */\r
+ \r
+ default:\r
+ /* Request is not handled: unknown class request type. */\r
+ requestHandled = USBFS_FALSE;\r
break;\r
}\r
+#else /*No class is defined*/\r
+ if (0u != interfaceNumber)\r
+ {\r
+ /* Suppress warning message */\r
+ }\r
+ requestHandled = USBFS_FALSE;\r
+#endif /*HID or AUDIO or MSC or CDC class enabled*/\r
\r
/* `#START USER_DEFINED_CLASS_CODE` Place your Class request here */\r
/* `#END` */\r
\r
- #ifdef USBFS_DISPATCH_CLASS_RQST_CALLBACK\r
- USBFS_DispatchClassRqst_Callback();\r
- #endif /* USBFS_DISPATCH_CLASS_RQST_CALLBACK */\r
+#ifdef USBFS_DISPATCH_CLASS_RQST_CALLBACK\r
+ if (USBFS_FALSE == requestHandled)\r
+ {\r
+ requestHandled = USBFS_DispatchClassRqst_Callback(interfaceNumber);\r
+ }\r
+#endif /* (USBFS_DISPATCH_CLASS_RQST_CALLBACK) */\r
\r
- return(requestHandled);\r
+ return (requestHandled);\r
}\r
\r
\r
--- /dev/null
+/***************************************************************************//**
+* \file USBFS_cydmac.h
+* \version 3.10
+*
+* \brief
+* This file provides macros implemenation of DMA_P4 functions.
+*
+********************************************************************************
+* \copyright
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_USBFS_USBFS_cydmac_H)
+#define CY_USBFS_USBFS_cydmac_H
+
+#include "USBFS_pvt.h"
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaSetConfiguration
+****************************************************************************//**
+*
+* Sets configuration information for the specified descriptor.
+*
+* \param ch: DMA ch modified by this function.
+* \param descr: Descriptor (0 or 1) modified by this function.
+* \param cfg: Descriptor control register.
+*
+* \sideeffect
+* The status register associated with the specified descriptor is reset to
+* zero after this function call. This function should not be called while
+* the descriptor is active. This can be checked by calling CyDmaGetStatus().
+*
+*******************************************************************************/
+#define USBFS_CyDmaSetConfiguration(ch, descr, cfg) \
+ do{ \
+ CYDMA_DESCR_BASE.descriptor[ch][descr].ctl = (cfg); \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaSetInterruptMask
+****************************************************************************//**
+*
+* Enables the DMA channel interrupt.
+*
+* \param ch: Channel used by this function.
+*
+*
+*******************************************************************************/
+#define USBFS_CyDmaSetInterruptMask(ch) \
+ do{ \
+ CYDMA_INTR_MASK_REG |= ((uint32)(1UL << (ch))); \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name:USBFS_CyDmaSetDescriptor0Next
+****************************************************************************//**
+*
+* Sets the descriptor 0 that should be run the next time the channel is
+* triggered.
+*
+* \param channel: Channel used by this function.
+*
+*
+*******************************************************************************/
+#define USBFS_CyDmaSetDescriptor0Next(ch) \
+ do{ \
+ CYDMA_CH_CTL_BASE.ctl[(ch)] &= (uint32) ~CYDMA_DESCRIPTOR; \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaSetNumDataElements
+****************************************************************************//**
+*
+* Sets the number of data elements to transfer for specified descriptor.
+*
+* \param ch: Channel used by this function.
+* \param descr: Descriptor (0 or 1) modified by this function.
+* \param numEl: Total number of data elements this descriptor transfers - 1u.
+* Valid ranges are 0 to 65535.
+*
+*
+* \sideeffect
+* This function should not be called when the specified descriptor is active
+* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus().
+*
+*******************************************************************************/
+#define USBFS_CyDmaSetNumDataElements(ch, descr, numEl) \
+ do{ \
+ CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].ctl = \
+ ((CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].ctl & (uint32) ~CYDMA_DATA_NR) | ((uint32) (numEl))); \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaGetSrcAddress
+****************************************************************************//**
+*
+* Returns the source address for the specified descriptor.
+*
+* \param ch: Channel used by this function.
+* \param descr: Specifies descriptor (0 or 1) used by this function.
+*
+* \return
+* Source address written to specified descriptor.
+*
+*******************************************************************************/
+#define USBFS_CyDmaGetSrcAddress(ch, descr) CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].src
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaSetSrcAddress
+****************************************************************************//**
+*
+* Configures the source address for the specified descriptor.
+*
+* \param ch: Channel used by this function.
+* \param descr: Descriptor (0 or 1) modified by this function.
+* \param srcAddress: Address of DMA transfer source.
+*
+*
+* \sideeffect
+* This function should not be called when the specified descriptor is active
+* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus().
+*
+*******************************************************************************/
+#define USBFS_CyDmaSetSrcAddress(ch, descr, srcAddress) \
+ do{ \
+ CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].src = (srcAddress); \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaGetDstAddress
+****************************************************************************//**
+*
+* Returns the destination address for the specified descriptor, set by
+* CyDmaSetDstAddress().
+*
+* \param ch: Channel used by this function.
+* \param descr: Specifies descriptor (0 or 1) used by this function.
+*
+* \return
+* Destination address written to specified descriptor.
+*
+*******************************************************************************/
+#define USBFS_CyDmaGetDstAddress(ch, descr) CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].dst
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaSetDstAddress
+****************************************************************************//**
+*
+* Configures the destination address for the specified descriptor.
+*
+* \param ch: Channel used by this function.
+* \param descr: Descriptor (0 or 1) modified by this function.
+* \param dstAddress: Address of DMA transfer destination.
+*
+*
+* \sideeffect
+* This function should not be called when the specified descriptor is active
+* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus().
+*
+*******************************************************************************/
+#define USBFS_CyDmaSetDstAddress(ch, descr, dstAddress) \
+ do{ \
+ CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].dst = (dstAddress); \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaValidateDescriptor
+****************************************************************************//**
+*
+* Validates the specified descriptor after it has been invalidated.
+*
+* \param ch: Channel used by this function.
+* \param descr: Descriptor (0 or 1) modified by this function.
+*
+*
+* \sideeffect
+* The status register associated with the specified descriptor is reset to
+* zero after this function call.
+* This function should not be called when the specified descriptor is active
+* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus().
+*
+*******************************************************************************/
+#define USBFS_CyDmaValidateDescriptor(ch, descr) \
+ do{ \
+ CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].status = CYDMA_VALID; \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaChEnable
+****************************************************************************//**
+*
+* Enables the DMA ch.
+*
+* \param ch: Channel used by this function.
+*
+*
+* \sideeffect
+* If this function is called before DMA is completely configured the operation
+* of the DMA is undefined and could result in system data corruption.
+*
+*******************************************************************************/
+#define USBFS_CyDmaChEnable(ch) \
+ do{ \
+ CYDMA_CH_CTL_BASE.ctl[(ch)] |= CYDMA_ENABLED; \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: CyDmaChDisable
+****************************************************************************//**
+*
+* Disables the DMA ch.
+*
+* \param ch: Channel used by this function.
+*
+*
+* \sideeffect
+* If this function is called during a DMA transfer the transfer is aborted.
+*
+*******************************************************************************/
+#define USBFS_CyDmaChDisable(ch) \
+ do{ \
+ CYDMA_CH_CTL_BASE.ctl[(ch)] &= (uint32) ~CYDMA_ENABLED; \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaTriggerIn
+****************************************************************************//**
+*
+* Triggers the DMA channel to execute a transfer. The tr_in signal is
+* triggered.
+*
+* \param trSel: trigger to be activated.
+*
+*
+*******************************************************************************/
+#define USBFS_DMA_USB_REQ_TR_OUT (0xC0020100U)
+#define USBFS_CyDmaTriggerIn(trSel) \
+ do{ \
+ CYDMA_TR_CTL_REG = USBFS_DMA_USB_REQ_TR_OUT | (uint32)(trSel); \
+ }while(0)
+
+
+/*******************************************************************************
+* Function Name: USBFS_CyDmaTriggerOut
+****************************************************************************//**
+*
+* Triggers the DMA channel to generate a transfer completion signal without
+* actual transfer executed. The tr_out signal is triggered.
+*
+* \param trSel: trigger to be activated.
+*
+*
+*******************************************************************************/
+#define USBFS_DMA_USB_BURST_END_TR_OUT (0xC0020300U)
+#define USBFS_CyDmaTriggerOut(trSel) \
+ do{ \
+ CYDMA_TR_CTL_REG = USBFS_DMA_USB_BURST_END_TR_OUT | (uint32)(trSel); \
+ }while(0)
+
+
+#endif /* (CY_USBFS_USBFS_cydmac_H) */
+
+
+/* [] END OF FILE */
-/*******************************************************************************\r
-* File Name: USBFS_descr.c\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_descr.c\r
+* \version 3.10\r
*\r
-* Description:\r
-* USB descriptors and storage.\r
-*\r
-* Note:\r
+* \brief\r
+* This file contains the USB descriptors and storage.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
#include "USBFS_pvt.h"\r
\r
\r
* Device Dispatch Table -- Points to the Device Descriptor and each of\r
* and Configuration Tables for this Device \r
*********************************************************************/\r
-const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[2u] = {\r
+const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[3u] = {\r
{0x01u, &USBFS_DEVICE0_DESCR},\r
+ {0x00u, NULL},\r
{0x01u, &USBFS_DEVICE0_CONFIGURATION0_TABLE}\r
};\r
/*********************************************************************\r
-/*******************************************************************************\r
-* File Name: USBFS_drv.c\r
-* Version 2.80\r
-*\r
-* Description:\r
-* Endpoint 0 Driver for the USBFS Component.\r
+/***************************************************************************//**\r
+* \file USBFS_drv.c\r
+* \version 3.10\r
*\r
-* Note:\r
+* \brief\r
+* This file contains the Endpoint 0 Driver for the USBFS Component. \r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
#include "USBFS_pvt.h"\r
\r
\r
***************************************/\r
\r
volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP];\r
+\r
+/** Contains the current configuration number, which is set by the host using a \r
+ * SET_CONFIGURATION request. This variable is initialized to zero in \r
+ * USBFS_InitComponent() API and can be read by the USBFS_GetConfiguration() \r
+ * API.*/\r
volatile uint8 USBFS_configuration;\r
+\r
+/** Contains the current interface number.*/\r
volatile uint8 USBFS_interfaceNumber;\r
+\r
+/** This variable is set to one after SET_CONFIGURATION and SET_INTERFACE \r
+ *requests. It can be read by the USBFS_IsConfigurationChanged() API */\r
volatile uint8 USBFS_configurationChanged;\r
+\r
+/** Contains the current device address.*/\r
volatile uint8 USBFS_deviceAddress;\r
+\r
+/** This is a two-bit variable that contains power status in the bit 0 \r
+ * (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote wakeup \r
+ * status (DEVICE_STATUS_REMOTE_WAKEUP) in the bit 1. This variable is \r
+ * initialized to zero in USBFS_InitComponent() API, configured by the \r
+ * USBFS_SetPowerStatus() API. The remote wakeup status cannot be set using the \r
+ * API SetPowerStatus(). */\r
volatile uint8 USBFS_deviceStatus;\r
+\r
volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER];\r
volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER];\r
volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER];\r
+\r
+/** Contains the started device number. This variable is set by the \r
+ * USBFS_Start() or USBFS_InitComponent() APIs.*/\r
volatile uint8 USBFS_device;\r
+\r
+/** Initialized class array for each interface. It is used for handling Class \r
+ * specific requests depend on interface class. Different classes in multiple \r
+ * alternate settings are not supported.*/\r
const uint8 CYCODE *USBFS_interfaceClass;\r
\r
\r
* Local data allocation\r
***************************************/\r
\r
-volatile uint8 USBFS_ep0Toggle;\r
-volatile uint8 USBFS_lastPacketSize;\r
-volatile uint8 USBFS_transferState;\r
+volatile uint8 USBFS_ep0Toggle;\r
+volatile uint8 USBFS_lastPacketSize;\r
+\r
+/** This variable is used by the communication functions to handle the current \r
+* transfer state.\r
+* Initialized to TRANS_STATE_IDLE in the USBFS_InitComponent() API and after a \r
+* complete transfer in the status stage.\r
+* Changed to the TRANS_STATE_CONTROL_READ or TRANS_STATE_CONTROL_WRITE in setup \r
+* transaction depending on the request type.\r
+*/\r
+volatile uint8 USBFS_transferState;\r
volatile T_USBFS_TD USBFS_currentTD;\r
-volatile uint8 USBFS_ep0Mode;\r
-volatile uint8 USBFS_ep0Count;\r
+volatile uint8 USBFS_ep0Mode;\r
+volatile uint8 USBFS_ep0Count;\r
volatile uint16 USBFS_transferByteCount;\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ep_0_Interrupt\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This Interrupt Service Routine handles Endpoint 0 (Control Pipe) traffic.\r
* It dispatches setup requests and handles the data and status stages.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_0_ISR)\r
{\r
- uint8 bRegTemp;\r
+ uint8 tempReg;\r
uint8 modifyReg;\r
\r
- #ifdef USBFS_EP_0_ISR_ENTRY_CALLBACK\r
- USBFS_EP_0_ISR_EntryCallback();\r
- #endif /* USBFS_EP_0_ISR_ENTRY_CALLBACK */\r
+#ifdef USBFS_EP_0_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_0_ISR_EntryCallback();\r
+#endif /* (USBFS_EP_0_ISR_ENTRY_CALLBACK) */\r
\r
- bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR);\r
- if ((bRegTemp & USBFS_MODE_ACKD) != 0u)\r
+ tempReg = USBFS_EP0_CR_REG;\r
+ if ((tempReg & USBFS_MODE_ACKD) != 0u)\r
{\r
modifyReg = 1u;\r
- if ((bRegTemp & USBFS_MODE_SETUP_RCVD) != 0u)\r
+ if ((tempReg & USBFS_MODE_SETUP_RCVD) != 0u)\r
{\r
- if((bRegTemp & USBFS_MODE_MASK) != USBFS_MODE_NAK_IN_OUT)\r
+ if ((tempReg & USBFS_MODE_MASK) != USBFS_MODE_NAK_IN_OUT)\r
{\r
- modifyReg = 0u; /* When mode not NAK_IN_OUT => invalid setup */\r
+ /* Mode not equal to NAK_IN_OUT: invalid setup */\r
+ modifyReg = 0u;\r
}\r
else\r
{\r
USBFS_HandleSetup();\r
- if((USBFS_ep0Mode & USBFS_MODE_SETUP_RCVD) != 0u)\r
+ \r
+ if ((USBFS_ep0Mode & USBFS_MODE_SETUP_RCVD) != 0u)\r
{\r
- modifyReg = 0u; /* if SETUP bit set -> exit without modifying the mode */\r
+ /* SETUP bit set: exit without mode modificaiton */\r
+ modifyReg = 0u;\r
}\r
-\r
}\r
}\r
- else if ((bRegTemp & USBFS_MODE_IN_RCVD) != 0u)\r
+ else if ((tempReg & USBFS_MODE_IN_RCVD) != 0u)\r
{\r
USBFS_HandleIN();\r
}\r
- else if ((bRegTemp & USBFS_MODE_OUT_RCVD) != 0u)\r
+ else if ((tempReg & USBFS_MODE_OUT_RCVD) != 0u)\r
{\r
USBFS_HandleOUT();\r
}\r
{\r
modifyReg = 0u;\r
}\r
- if(modifyReg != 0u)\r
+ \r
+ /* Modify the EP0_CR register */\r
+ if (modifyReg != 0u)\r
{\r
- bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */\r
- if((bRegTemp & USBFS_MODE_SETUP_RCVD) == 0u) /* Check if SETUP bit is not set, otherwise exit */\r
+ \r
+ tempReg = USBFS_EP0_CR_REG;\r
+ \r
+ /* Make sure that SETUP bit is cleared before modification */\r
+ if ((tempReg & USBFS_MODE_SETUP_RCVD) == 0u)\r
{\r
- /* Update the count register */\r
- bRegTemp = USBFS_ep0Toggle | USBFS_ep0Count;\r
- CY_SET_REG8(USBFS_EP0_CNT_PTR, bRegTemp);\r
- if(bRegTemp == CY_GET_REG8(USBFS_EP0_CNT_PTR)) /* continue if writing was successful */\r
+ /* Update count register */\r
+ tempReg = (uint8) USBFS_ep0Toggle | USBFS_ep0Count;\r
+ USBFS_EP0_CNT_REG = tempReg;\r
+ \r
+ /* Make sure that previous write operaiton was successful */\r
+ if (tempReg == USBFS_EP0_CNT_REG)\r
{\r
+ /* Repeat until next successful write operation */\r
do\r
{\r
- modifyReg = USBFS_ep0Mode; /* Init temporary variable */\r
- /* Unlock registers */\r
- bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_SETUP_RCVD;\r
- if(bRegTemp == 0u) /* Check if SETUP bit is not set */\r
+ /* Init temporary variable */\r
+ modifyReg = USBFS_ep0Mode;\r
+ \r
+ /* Unlock register */\r
+ tempReg = (uint8) (USBFS_EP0_CR_REG & USBFS_MODE_SETUP_RCVD);\r
+ \r
+ /* Check if SETUP bit is not set */\r
+ if (0u == tempReg)\r
{\r
/* Set the Mode Register */\r
- CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_ep0Mode);\r
+ USBFS_EP0_CR_REG = USBFS_ep0Mode;\r
+ \r
/* Writing check */\r
- modifyReg = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_MASK;\r
+ modifyReg = USBFS_EP0_CR_REG & USBFS_MODE_MASK;\r
}\r
- }while(modifyReg != USBFS_ep0Mode); /* Repeat if writing was not successful */\r
+ }\r
+ while (modifyReg != USBFS_ep0Mode);\r
}\r
}\r
}\r
}\r
- #ifdef USBFS_EP_0_ISR_EXIT_CALLBACK\r
- USBFS_EP_0_ISR_ExitCallback();\r
- #endif /* USBFS_EP_0_ISR_EXIT_CALLBACK */\r
+\r
+ USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_EP0_INTR);\r
+ \r
+#ifdef USBFS_EP_0_ISR_EXIT_CALLBACK\r
+ USBFS_EP_0_ISR_ExitCallback();\r
+#endif /* (USBFS_EP_0_ISR_EXIT_CALLBACK) */\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_HandleSetup\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This Routine dispatches requests for the four USB request types\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_HandleSetup(void) \r
{\r
uint8 requestHandled;\r
-\r
- requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */\r
- CY_SET_REG8(USBFS_EP0_CR_PTR, requestHandled); /* clear setup bit */\r
- requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* reread register */\r
- if((requestHandled & USBFS_MODE_SETUP_RCVD) != 0u)\r
+ \r
+ /* Clear register lock by SIE (read register) and clear setup bit \r
+ * (write any value in register).\r
+ */\r
+ requestHandled = (uint8) USBFS_EP0_CR_REG;\r
+ USBFS_EP0_CR_REG = (uint8) requestHandled;\r
+ requestHandled = (uint8) USBFS_EP0_CR_REG;\r
+\r
+ if ((requestHandled & USBFS_MODE_SETUP_RCVD) != 0u)\r
{\r
- USBFS_ep0Mode = requestHandled; /* if SETUP bit set -> exit without modifying the mode */\r
+ /* SETUP bit is set: exit without mode modification. */\r
+ USBFS_ep0Mode = requestHandled;\r
}\r
else\r
{\r
/* In case the previous transfer did not complete, close it out */\r
USBFS_UpdateStatusBlock(USBFS_XFER_PREMATURE);\r
\r
- switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_TYPE_MASK)\r
+ /* Check request type. */\r
+ switch (USBFS_bmRequestTypeReg & USBFS_RQST_TYPE_MASK)\r
{\r
case USBFS_RQST_TYPE_STD:\r
requestHandled = USBFS_HandleStandardRqst();\r
break;\r
+ \r
case USBFS_RQST_TYPE_CLS:\r
requestHandled = USBFS_DispatchClassRqst();\r
break;\r
+ \r
case USBFS_RQST_TYPE_VND:\r
requestHandled = USBFS_HandleVendorRqst();\r
break;\r
+ \r
default:\r
requestHandled = USBFS_FALSE;\r
break;\r
}\r
+ \r
+ /* If request is not recognized. Stall endpoint 0 IN and OUT. */\r
if (requestHandled == USBFS_FALSE)\r
{\r
USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT;\r
\r
/*******************************************************************************\r
* Function Name: USBFS_HandleIN\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine handles EP0 IN transfers.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
{\r
case USBFS_TRANS_STATE_IDLE:\r
break;\r
+ \r
case USBFS_TRANS_STATE_CONTROL_READ:\r
USBFS_ControlReadDataStage();\r
break;\r
+ \r
case USBFS_TRANS_STATE_CONTROL_WRITE:\r
USBFS_ControlWriteStatusStage();\r
break;\r
+ \r
case USBFS_TRANS_STATE_NO_DATA_CONTROL:\r
USBFS_NoDataControlStatusStage();\r
break;\r
+ \r
default: /* there are no more states */\r
break;\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_HandleOUT\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine handles EP0 OUT transfers.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
{\r
case USBFS_TRANS_STATE_IDLE:\r
break;\r
+ \r
case USBFS_TRANS_STATE_CONTROL_READ:\r
USBFS_ControlReadStatusStage();\r
break;\r
+ \r
case USBFS_TRANS_STATE_CONTROL_WRITE:\r
USBFS_ControlWriteDataStage();\r
break;\r
+ \r
case USBFS_TRANS_STATE_NO_DATA_CONTROL:\r
/* Update the completion block */\r
USBFS_UpdateStatusBlock(USBFS_XFER_ERROR);\r
+ \r
/* We expect no more data, so stall INs and OUTs */\r
USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT;\r
break;\r
- default: /* There are no more states */\r
+ \r
+ default: \r
+ /* There are no more states */\r
break;\r
}\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_LoadEP0\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* This routine loads the EP0 data registers for OUT transfers. It uses the\r
+* This routine loads the EP0 data registers for OUT transfers. It uses the\r
* currentTD (previously initialized by the _InitControlWrite function and\r
* updated for each OUT transfer, and the bLastPacketSize) to determine how\r
* many uint8s to transfer on the current OUT.\r
* of the control endpoint size (8) or remaining number of uint8s for the\r
* transaction.\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_transferByteCount - Update the transfer byte count from the\r
* last transaction.\r
* USBFS_ep0Count - counts the data loaded to the SIE memory in\r
* USBFS_ep0Mode - prepare for mode register content.\r
* USBFS_transferState - set to TRANS_STATE_CONTROL_READ\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
\r
/* Update the transfer byte count from the last transaction */\r
USBFS_transferByteCount += USBFS_lastPacketSize;\r
+\r
/* Now load the next transaction */\r
while ((USBFS_currentTD.count > 0u) && (ep0Count < 8u))\r
{\r
- CY_SET_REG8((reg8 *)(USBFS_EP0_DR0_IND + ep0Count), *USBFS_currentTD.pData);\r
+ USBFS_EP0_DR_BASE.epData[ep0Count] = (uint8) *USBFS_currentTD.pData;\r
USBFS_currentTD.pData = &USBFS_currentTD.pData[1u];\r
ep0Count++;\r
USBFS_currentTD.count--;\r
}\r
- /* Support zero-length packet*/\r
- if( (USBFS_lastPacketSize == 8u) || (ep0Count > 0u) )\r
+\r
+ /* Support zero-length packet */\r
+ if ((USBFS_lastPacketSize == 8u) || (ep0Count > 0u))\r
{\r
/* Update the data toggle */\r
USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE;\r
}\r
\r
/* Save the packet size for next time */\r
- USBFS_lastPacketSize = ep0Count;\r
- USBFS_ep0Count = ep0Count;\r
+ USBFS_ep0Count = (uint8) ep0Count;\r
+ USBFS_lastPacketSize = (uint8) ep0Count;\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_InitControlRead\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Initialize a control read transaction, usable to send data to the host.\r
+* Initialize a control read transaction. It is used to send data to the host.\r
* The following global variables should be initialized before this function\r
* called. To send zero length packet use InitZeroLengthControlTransfer\r
* function.\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
+* \return\r
* requestHandled state.\r
*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_currentTD.count - counts of data to be sent.\r
* USBFS_currentTD.pData - data pointer.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_InitControlRead(void) \r
{\r
uint16 xferCount;\r
- if(USBFS_currentTD.count == 0u)\r
+\r
+ if (USBFS_currentTD.count == 0u)\r
{\r
(void) USBFS_InitZeroLengthControlTransfer();\r
}\r
{\r
/* Set up the state machine */\r
USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ;\r
+ \r
/* Set the toggle, it gets updated in LoadEP */\r
USBFS_ep0Toggle = 0u;\r
+ \r
/* Initialize the Status Block */\r
USBFS_InitializeStatusBlock();\r
- xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo)));\r
+ \r
+ xferCount = ((uint16)((uint16) USBFS_lengthHiReg << 8u) | ((uint16) USBFS_lengthLoReg));\r
\r
if (USBFS_currentTD.count > xferCount)\r
{\r
USBFS_currentTD.count = xferCount;\r
}\r
+ \r
USBFS_LoadEP0();\r
}\r
\r
- return(USBFS_TRUE);\r
+ return (USBFS_TRUE);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_InitZeroLengthControlTransfer\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Initialize a zero length data IN transfer.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled state.\r
*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE\r
* USBFS_ep0Mode - prepare for mode register content.\r
* USBFS_transferState - set to TRANS_STATE_CONTROL_READ\r
* USBFS_ep0Count - cleared, means the zero-length packet.\r
* USBFS_lastPacketSize - cleared.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
{\r
/* Update the state */\r
USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ;\r
+ \r
/* Set the data toggle */\r
USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE;\r
+ \r
/* Set the Mode Register */\r
USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT;\r
+ \r
/* Save the packet size for next time */\r
USBFS_lastPacketSize = 0u;\r
+ \r
USBFS_ep0Count = 0u;\r
\r
- return(USBFS_TRUE);\r
+ return (USBFS_TRUE);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ControlReadDataStage\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Handle the Data Stage of a control read transfer.\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ControlReadStatusStage\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Handle the Status Stage of a control read transfer.\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_USBFS_transferByteCount - updated with last packet size.\r
* USBFS_transferState - set to TRANS_STATE_IDLE.\r
* USBFS_ep0Mode - set to MODE_STALL_IN_OUT.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
{\r
/* Update the transfer byte count */\r
USBFS_transferByteCount += USBFS_lastPacketSize;\r
+ \r
/* Go Idle */\r
USBFS_transferState = USBFS_TRANS_STATE_IDLE;\r
+ \r
/* Update the completion block */\r
USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK);\r
+ \r
/* We expect no more data, so stall INs and OUTs */\r
- USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT;\r
+ USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT;\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_InitControlWrite\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Initialize a control write transaction\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled state.\r
*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_USBFS_transferState - set to TRANS_STATE_CONTROL_WRITE\r
* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE\r
* USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
\r
/* Set up the state machine */\r
USBFS_transferState = USBFS_TRANS_STATE_CONTROL_WRITE;\r
+ \r
/* This might not be necessary */\r
USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE;\r
+ \r
/* Initialize the Status Block */\r
USBFS_InitializeStatusBlock();\r
\r
- xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo)));\r
+ xferCount = ((uint16)((uint16) USBFS_lengthHiReg << 8u) | ((uint16) USBFS_lengthLoReg));\r
\r
if (USBFS_currentTD.count > xferCount)\r
{\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ControlWriteDataStage\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Handle the Data Stage of a control write transfer\r
* 1. Get the data (We assume the destination was validated previously)\r
* 2. Update the count and data toggle\r
* 3. Update the mode register for the next transaction\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_transferByteCount - Update the transfer byte count from the\r
* last transaction.\r
* USBFS_ep0Count - counts the data loaded from the SIE memory\r
* USBFS_ep0Toggle - inverted\r
* USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 ep0Count;\r
uint8 regIndex = 0u;\r
\r
- ep0Count = (CY_GET_REG8(USBFS_EP0_CNT_PTR) & USBFS_EPX_CNT0_MASK) -\r
- USBFS_EPX_CNTX_CRC_COUNT;\r
+ ep0Count = (USBFS_EP0_CNT_REG & USBFS_EPX_CNT0_MASK) - USBFS_EPX_CNTX_CRC_COUNT;\r
\r
- USBFS_transferByteCount += ep0Count;\r
+ USBFS_transferByteCount += (uint8)ep0Count;\r
\r
while ((USBFS_currentTD.count > 0u) && (ep0Count > 0u))\r
{\r
- *USBFS_currentTD.pData = CY_GET_REG8((reg8 *)(USBFS_EP0_DR0_IND + regIndex));\r
+ *USBFS_currentTD.pData = (uint8) USBFS_EP0_DR_BASE.epData[regIndex];\r
USBFS_currentTD.pData = &USBFS_currentTD.pData[1u];\r
regIndex++;\r
ep0Count--;\r
USBFS_currentTD.count--;\r
}\r
- USBFS_ep0Count = ep0Count;\r
+ \r
+ USBFS_ep0Count = (uint8)ep0Count;\r
+ \r
/* Update the data toggle */\r
USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE;\r
+ \r
/* Expect Data or Status Stage */\r
USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN;\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ControlWriteStatusStage\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Handle the Status Stage of a control write transfer\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_transferState - set to TRANS_STATE_IDLE.\r
* USBFS_USBFS_ep0Mode - set to MODE_STALL_IN_OUT.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
{\r
/* Go Idle */\r
USBFS_transferState = USBFS_TRANS_STATE_IDLE;\r
- /* Update the completion block */\r
+ \r
+ /* Update the completion block */ \r
USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK);\r
+ \r
/* We expect no more data, so stall INs and OUTs */\r
USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT;\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_InitNoDataControlTransfer\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Initialize a no data control transfer\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled state.\r
*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_transferState - set to TRANS_STATE_NO_DATA_CONTROL.\r
* USBFS_ep0Mode - set to MODE_STATUS_IN_ONLY.\r
* USBFS_ep0Count - cleared.\r
* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_InitNoDataControlTransfer(void) \r
{\r
USBFS_transferState = USBFS_TRANS_STATE_NO_DATA_CONTROL;\r
- USBFS_ep0Mode = USBFS_MODE_STATUS_IN_ONLY;\r
- USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE;\r
- USBFS_ep0Count = 0u;\r
+ USBFS_ep0Mode = USBFS_MODE_STATUS_IN_ONLY;\r
+ USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE;\r
+ USBFS_ep0Count = 0u;\r
\r
- return(USBFS_TRUE);\r
+ return (USBFS_TRUE);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_NoDataControlStatusStage\r
-********************************************************************************\r
-* Summary:\r
+****************************************************************************//**\r
* Handle the Status Stage of a no data control transfer.\r
*\r
* SET_ADDRESS is special, since we need to receive the status stage with\r
* the old address.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_transferState - set to TRANS_STATE_IDLE.\r
* USBFS_ep0Mode - set to MODE_STALL_IN_OUT.\r
* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE\r
* USBFS_deviceAddress - used to set new address and cleared\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_NoDataControlStatusStage(void) \r
{\r
- /* Change the USB address register if we got a SET_ADDRESS. */\r
- if (USBFS_deviceAddress != 0u)\r
+ if (0u != USBFS_deviceAddress)\r
{\r
- CY_SET_REG8(USBFS_CR0_PTR, USBFS_deviceAddress | USBFS_CR0_ENABLE);\r
+ /* Update device address if we got new address. */\r
+ USBFS_CR0_REG = (uint8) USBFS_deviceAddress | USBFS_CR0_ENABLE;\r
USBFS_deviceAddress = 0u;\r
}\r
- /* Go Idle */\r
+\r
USBFS_transferState = USBFS_TRANS_STATE_IDLE;\r
- /* Update the completion block */\r
+ \r
+ /* Update the completion block. */\r
USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK);\r
- /* We expect no more data, so stall INs and OUTs */\r
+ \r
+ /* Stall IN and OUT, no more data is expected. */\r
USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT;\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_UpdateStatusBlock\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Update the Completion Status Block for a Request. The block is updated\r
* with the completion code the USBFS_transferByteCount. The\r
* StatusBlock Pointer is set to NULL.\r
*\r
-* Parameters:\r
* completionCode - status.\r
*\r
-* Return:\r
-* None.\r
*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_currentTD.pStatusBlock->status - updated by the\r
* completionCode parameter.\r
* USBFS_currentTD.pStatusBlock->length - updated.\r
* USBFS_currentTD.pStatusBlock - cleared.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: USBFS_InitializeStatusBlock\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Initialize the Completion Status Block for a Request. The completion\r
* code is set to USB_XFER_IDLE.\r
*\r
* Also, initializes USBFS_transferByteCount. Save some space,\r
* this is the only consumer.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_currentTD.pStatusBlock->status - set to XFER_IDLE.\r
* USBFS_currentTD.pStatusBlock->length - cleared.\r
* USBFS_transferByteCount - cleared.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_InitializeStatusBlock(void) \r
{\r
USBFS_transferByteCount = 0u;\r
- if(USBFS_currentTD.pStatusBlock != NULL)\r
+ \r
+ if (USBFS_currentTD.pStatusBlock != NULL)\r
{\r
USBFS_currentTD.pStatusBlock->status = USBFS_XFER_IDLE;\r
USBFS_currentTD.pStatusBlock->length = 0u;\r
-/*******************************************************************************\r
-* File Name: USBFS_episr.c\r
-* Version 2.80\r
-*\r
-* Description:\r
-* Data endpoint Interrupt Service Routines\r
+/***************************************************************************//**\r
+* \file USBFS_episr.c\r
+* \version 3.10\r
*\r
-* Note:\r
+* \brief\r
+* This file contains the Data endpoint Interrupt Service Routines.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
#include "USBFS_pvt.h"\r
+#include "USBFS_cydmac.h"\r
\r
-#if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u))\r
- #include "USBFS_midi.h"\r
-#endif /* (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)) */\r
-#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- #include "USBFS_EP8_DMA_Done_SR.h"\r
- #include "USBFS_EP17_DMA_Done_SR.h"\r
-#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
\r
\r
/***************************************\r
/* `#END` */\r
\r
\r
-#if(USBFS_EP1_ISR_REMOVE == 0u)\r
-\r
-\r
+#if (USBFS_EP1_ISR_ACTIVE)\r
/******************************************************************************\r
* Function Name: USBFS_EP_1_ISR\r
- *******************************************************************************\r
+ ***************************************************************************//**\r
*\r
- * Summary:\r
* Endpoint 1 Interrupt Service Routine\r
*\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
******************************************************************************/\r
CY_ISR(USBFS_EP_1_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
\r
- #ifdef USBFS_EP_1_ISR_ENTRY_CALLBACK\r
- USBFS_EP_1_ISR_EntryCallback();\r
- #endif /* USBFS_EP_1_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_EP_1_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_1_ISR_EntryCallback();\r
+ #endif /* (USBFS_EP_1_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START EP1_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
-\r
- CY_GET_REG8(USBFS_SIE_EP1_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_EP[USBFS_EP1].attrib & USBFS_EP_TYPE_MASK) !=\r
- USBFS_EP_TYPE_ISOC)\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
{\r
- USBFS_EP[USBFS_EP1].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ uint8 intEn = EA;\r
+ CyGlobalIntEnable; /* Enable nested interrupts. */\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ \r
+ USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP1_INTR);\r
+ \r
+ /* Notifies user that transfer IN or OUT transfer is completed.\r
+ * IN endpoint: endpoint buffer can be reloaded, Host is read data.\r
+ * OUT endpoint: data is ready to be read from endpoint buffer. \r
+ */\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (0u != (USBFS_EP[USBFS_EP1].addr & USBFS_DIR_IN))\r
+ #endif /* (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ {\r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP1].epCr0;\r
+ \r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(USBFS_EP1) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[USBFS_EP1].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+\r
+ /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify\r
+ * user that DMA has completed copying data from OUT endpoint which is not completely true.\r
+ * Because last chunk of data is being copied.\r
+ * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast.\r
+ * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN).\r
+ */\r
+ USBFS_EP[USBFS_EP1].apiEpState = USBFS_EVENT_PENDING;\r
}\r
- USBFS_EP[USBFS_EP1].apiEpState = USBFS_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) &\r
- (uint8)~USBFS_SIE_EP_INT_EP1_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_midi_out_ep == USBFS_EP1)\r
+ #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO))\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ if (USBFS_midi_out_ep == USBFS_EP1)\r
{\r
- USBFS_MIDI_OUT_EP_Service();\r
+ USBFS_MIDI_OUT_Service();\r
}\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */\r
+ \r
/* `#START EP1_END_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- #ifdef USBFS_EP_1_ISR_EXIT_CALLBACK\r
- USBFS_EP_1_ISR_ExitCallback();\r
- #endif /* USBFS_EP_1_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_EP_1_ISR_EXIT_CALLBACK\r
+ USBFS_EP_1_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_1_ISR_EXIT_CALLBACK) */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ \r
+ EA = intEn; /* Restore nested interrupt configuration. */\r
+ }\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
}\r
\r
-#endif /* USBFS_EP1_ISR_REMOVE */\r
-\r
+#endif /* (USBFS_EP1_ISR_ACTIVE) */\r
\r
-#if(USBFS_EP2_ISR_REMOVE == 0u)\r
\r
+#if (USBFS_EP2_ISR_ACTIVE)\r
/*******************************************************************************\r
* Function Name: USBFS_EP_2_ISR\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Endpoint 2 Interrupt Service Routine\r
- *\r
- * Parameters:\r
- * None.\r
+ ****************************************************************************//**\r
*\r
- * Return:\r
- * None.\r
+ * Endpoint 2 Interrupt Service Routine.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_2_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
-\r
- #ifdef USBFS_EP_2_ISR_ENTRY_CALLBACK\r
- USBFS_EP_2_ISR_EntryCallback();\r
- #endif /* USBFS_EP_2_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_EP_2_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_2_ISR_EntryCallback();\r
+ #endif /* (USBFS_EP_2_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START EP2_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
-\r
- CY_GET_REG8(USBFS_SIE_EP2_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_EP[USBFS_EP2].attrib & USBFS_EP_TYPE_MASK) !=\r
- USBFS_EP_TYPE_ISOC)\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
{\r
- USBFS_EP[USBFS_EP2].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ uint8 intEn = EA;\r
+ CyGlobalIntEnable; /* Enable nested interrupts. */\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
+\r
+ USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP2_INTR);\r
+\r
+ /* Notifies user that transfer IN or OUT transfer is completed.\r
+ * IN endpoint: endpoint buffer can be reloaded, Host is read data.\r
+ * OUT endpoint: data is ready to be read from endpoint buffer. \r
+ */\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (0u != (USBFS_EP[USBFS_EP2].addr & USBFS_DIR_IN))\r
+ #endif /* (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ { \r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP2].epCr0;\r
+ \r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(USBFS_EP2) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[USBFS_EP2].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+\r
+ /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify\r
+ * user that DMA has completed copying data from OUT endpoint which is not completely true.\r
+ * Because last chunk of data is being copied.\r
+ * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast.\r
+ * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN).\r
+ */\r
+ USBFS_EP[USBFS_EP2].apiEpState = USBFS_EVENT_PENDING;\r
}\r
- USBFS_EP[USBFS_EP2].apiEpState = USBFS_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_SIE_EP_INT_EP2_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_midi_out_ep == USBFS_EP2)\r
+ #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO))\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ if (USBFS_midi_out_ep == USBFS_EP2)\r
{\r
- USBFS_MIDI_OUT_EP_Service();\r
+ USBFS_MIDI_OUT_Service();\r
}\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ \r
+ \r
/* `#START EP2_END_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- #ifdef USBFS_EP_2_ISR_EXIT_CALLBACK\r
- USBFS_EP_2_ISR_ExitCallback();\r
- #endif /* USBFS_EP_2_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_EP_2_ISR_EXIT_CALLBACK\r
+ USBFS_EP_2_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_2_ISR_EXIT_CALLBACK) */\r
+\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
+ EA = intEn; /* Restore nested interrupt configuration. */\r
+ }\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
}\r
-\r
-#endif /* USBFS_EP2_ISR_REMOVE */\r
+#endif /* (USBFS_EP2_ISR_ACTIVE) */\r
\r
\r
-#if(USBFS_EP3_ISR_REMOVE == 0u)\r
-\r
+#if (USBFS_EP3_ISR_ACTIVE)\r
/*******************************************************************************\r
* Function Name: USBFS_EP_3_ISR\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Endpoint 3 Interrupt Service Routine\r
+ ****************************************************************************//**\r
*\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
+ * Endpoint 3 Interrupt Service Routine.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_3_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
-\r
- #ifdef USBFS_EP_3_ISR_ENTRY_CALLBACK\r
- USBFS_EP_3_ISR_EntryCallback();\r
- #endif /* USBFS_EP_3_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_EP_3_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_3_ISR_EntryCallback();\r
+ #endif /* (USBFS_EP_3_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START EP3_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
- CY_GET_REG8(USBFS_SIE_EP3_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_EP[USBFS_EP3].attrib & USBFS_EP_TYPE_MASK) !=\r
- USBFS_EP_TYPE_ISOC)\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
{\r
- USBFS_EP[USBFS_EP3].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ uint8 intEn = EA;\r
+ CyGlobalIntEnable; /* Enable nested interrupts. */\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
+\r
+ USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP3_INTR); \r
+\r
+ /* Notifies user that transfer IN or OUT transfer is completed.\r
+ * IN endpoint: endpoint buffer can be reloaded, Host is read data.\r
+ * OUT endpoint: data is ready to be read from endpoint buffer. \r
+ */\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (0u != (USBFS_EP[USBFS_EP3].addr & USBFS_DIR_IN))\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ { \r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP3].epCr0;\r
+\r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(USBFS_EP3) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[USBFS_EP3].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+\r
+ /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify\r
+ * user that DMA has completed copying data from OUT endpoint which is not completely true.\r
+ * Because last chunk of data is being copied.\r
+ * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast.\r
+ * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN).\r
+ */\r
+ USBFS_EP[USBFS_EP3].apiEpState = USBFS_EVENT_PENDING;\r
}\r
- USBFS_EP[USBFS_EP3].apiEpState = USBFS_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_SIE_EP_INT_EP3_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_midi_out_ep == USBFS_EP3)\r
+ #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO))\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ if (USBFS_midi_out_ep == USBFS_EP3)\r
{\r
- USBFS_MIDI_OUT_EP_Service();\r
+ USBFS_MIDI_OUT_Service();\r
}\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ \r
\r
/* `#START EP3_END_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- #ifdef USBFS_EP_3_ISR_EXIT_CALLBACK\r
- USBFS_EP_3_ISR_ExitCallback();\r
- #endif /* USBFS_EP_3_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_EP_3_ISR_EXIT_CALLBACK\r
+ USBFS_EP_3_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_3_ISR_EXIT_CALLBACK) */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ \r
+ EA = intEn; /* Restore nested interrupt configuration. */\r
+ }\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
}\r
-\r
-#endif /* USBFS_EP3_ISR_REMOVE */\r
+#endif /* (USBFS_EP3_ISR_ACTIVE) */\r
\r
\r
-#if(USBFS_EP4_ISR_REMOVE == 0u)\r
-\r
+#if (USBFS_EP4_ISR_ACTIVE)\r
/*******************************************************************************\r
* Function Name: USBFS_EP_4_ISR\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Endpoint 4 Interrupt Service Routine\r
+ ****************************************************************************//**\r
*\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
+ * Endpoint 4 Interrupt Service Routine.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_4_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
- #ifdef USBFS_EP_4_ISR_ENTRY_CALLBACK\r
- USBFS_EP_4_ISR_EntryCallback();\r
- #endif /* USBFS_EP_4_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_EP_4_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_4_ISR_EntryCallback();\r
+ #endif /* (USBFS_EP_4_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START EP4_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ {\r
+ uint8 intEn = EA;\r
+ CyGlobalIntEnable; /* Enable nested interrupts. */\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
\r
- CY_GET_REG8(USBFS_SIE_EP4_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_EP[USBFS_EP4].attrib & USBFS_EP_TYPE_MASK) !=\r
- USBFS_EP_TYPE_ISOC)\r
+ USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP4_INTR);\r
+ \r
+ /* Notifies user that transfer IN or OUT transfer is completed.\r
+ * IN endpoint: endpoint buffer can be reloaded, Host is read data.\r
+ * OUT endpoint: data is ready to read from endpoint buffer. \r
+ */\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (0u != (USBFS_EP[USBFS_EP4].addr & USBFS_DIR_IN))\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
{\r
- USBFS_EP[USBFS_EP4].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP4].epCr0;\r
+\r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(USBFS_EP4) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[USBFS_EP4].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+\r
+ /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify\r
+ * user that DMA has completed copying data from OUT endpoint which is not completely true.\r
+ * Because last chunk of data is being copied.\r
+ * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast.\r
+ * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN).\r
+ */\r
+ USBFS_EP[USBFS_EP4].apiEpState = USBFS_EVENT_PENDING;\r
}\r
- USBFS_EP[USBFS_EP4].apiEpState = USBFS_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_SIE_EP_INT_EP4_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT)\r
+ #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO))\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP4)\r
{\r
- USBFS_MIDI_OUT_EP_Service();\r
+ USBFS_MIDI_OUT_Service();\r
}\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ \r
\r
/* `#START EP4_END_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- #ifdef USBFS_EP_4_ISR_EXIT_CALLBACK\r
- USBFS_EP_4_ISR_ExitCallback();\r
- #endif /* USBFS_EP_4_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_EP_4_ISR_EXIT_CALLBACK\r
+ USBFS_EP_4_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_4_ISR_EXIT_CALLBACK) */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ \r
+ EA = intEn; /* Restore nested interrupt configuration. */\r
+ }\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
}\r
+#endif /* (USBFS_EP4_ISR_ACTIVE) */\r
\r
-#endif /* USBFS_EP4_ISR_REMOVE */\r
-\r
-\r
-#if(USBFS_EP5_ISR_REMOVE == 0u)\r
\r
+#if (USBFS_EP5_ISR_ACTIVE)\r
/*******************************************************************************\r
* Function Name: USBFS_EP_5_ISR\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Endpoint 5 Interrupt Service Routine\r
*\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_5_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
- #ifdef USBFS_EP_5_ISR_ENTRY_CALLBACK\r
- USBFS_EP_5_ISR_EntryCallback();\r
- #endif /* USBFS_EP_5_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_EP_5_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_5_ISR_EntryCallback();\r
+ #endif /* (USBFS_EP_5_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START EP5_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
- CY_GET_REG8(USBFS_SIE_EP5_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_EP[USBFS_EP5].attrib & USBFS_EP_TYPE_MASK) !=\r
- USBFS_EP_TYPE_ISOC)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
{\r
- USBFS_EP[USBFS_EP5].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ uint8 intEn = EA;\r
+ CyGlobalIntEnable; /* Enable nested interrupts. */\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
+\r
+ USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP5_INTR);\r
+ \r
+ /* Notifies user that transfer IN or OUT transfer is completed.\r
+ * IN endpoint: endpoint buffer can be reloaded, Host is read data.\r
+ * OUT endpoint: data is ready to read from endpoint buffer. \r
+ */\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (0u != (USBFS_EP[USBFS_EP5].addr & USBFS_DIR_IN))\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ { \r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP5].epCr0;\r
+\r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(USBFS_EP5) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[USBFS_EP5].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+\r
+ /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify\r
+ * user that DMA has completed copying data from OUT endpoint which is not completely true.\r
+ * Because last chunk of data is being copied.\r
+ * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast.\r
+ * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN).\r
+ */\r
+ USBFS_EP[USBFS_EP5].apiEpState = USBFS_EVENT_PENDING;\r
}\r
- USBFS_EP[USBFS_EP5].apiEpState = USBFS_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_SIE_EP_INT_EP5_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_midi_out_ep == USBFS_EP5)\r
+ #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) \r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ if (USBFS_midi_out_ep == USBFS_EP5)\r
{\r
- USBFS_MIDI_OUT_EP_Service();\r
+ USBFS_MIDI_OUT_Service();\r
}\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */\r
\r
/* `#START EP5_END_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- #ifdef USBFS_EP_5_ISR_EXIT_CALLBACK\r
- USBFS_EP_5_ISR_ExitCallback();\r
- #endif /* USBFS_EP_5_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_EP_5_ISR_EXIT_CALLBACK\r
+ USBFS_EP_5_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_5_ISR_EXIT_CALLBACK) */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ \r
+ EA = intEn; /* Restore nested interrupt configuration. */\r
+ }\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
}\r
-#endif /* USBFS_EP5_ISR_REMOVE */\r
+#endif /* (USBFS_EP5_ISR_ACTIVE) */\r
\r
\r
-#if(USBFS_EP6_ISR_REMOVE == 0u)\r
-\r
+#if (USBFS_EP6_ISR_ACTIVE)\r
/*******************************************************************************\r
* Function Name: USBFS_EP_6_ISR\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Endpoint 6 Interrupt Service Routine\r
+ ****************************************************************************//**\r
*\r
- * Parameters:\r
- * None.\r
+ * Endpoint 6 Interrupt Service Routine.\r
*\r
- * Return:\r
- * None.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_6_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
- #ifdef USBFS_EP_6_ISR_ENTRY_CALLBACK\r
- USBFS_EP_6_ISR_EntryCallback();\r
- #endif /* USBFS_EP_6_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_EP_6_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_6_ISR_EntryCallback();\r
+ #endif /* (USBFS_EP_6_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START EP6_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ {\r
+ uint8 intEn = EA;\r
+ CyGlobalIntEnable; /* Enable nested interrupts. */\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
\r
- CY_GET_REG8(USBFS_SIE_EP6_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_EP[USBFS_EP6].attrib & USBFS_EP_TYPE_MASK) !=\r
- USBFS_EP_TYPE_ISOC)\r
+ USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP6_INTR);\r
+ \r
+ /* Notifies user that transfer IN or OUT transfer is completed.\r
+ * IN endpoint: endpoint buffer can be reloaded, Host is read data.\r
+ * OUT endpoint: data is ready to read from endpoint buffer. \r
+ */\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (0u != (USBFS_EP[USBFS_EP6].addr & USBFS_DIR_IN))\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
{\r
- USBFS_EP[USBFS_EP6].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP6].epCr0;\r
+\r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(USBFS_EP6) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[USBFS_EP6].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+ \r
+ /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify\r
+ * user that DMA has completed copying data from OUT endpoint which is not completely true.\r
+ * Because last chunk of data is being copied.\r
+ * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast.\r
+ * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN).\r
+ */\r
+ USBFS_EP[USBFS_EP6].apiEpState = USBFS_EVENT_PENDING;\r
}\r
- USBFS_EP[USBFS_EP6].apiEpState = USBFS_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_SIE_EP_INT_EP6_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_midi_out_ep == USBFS_EP6)\r
+ #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO))\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ if (USBFS_midi_out_ep == USBFS_EP6)\r
{\r
- USBFS_MIDI_OUT_EP_Service();\r
+ USBFS_MIDI_OUT_Service();\r
}\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */\r
\r
/* `#START EP6_END_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- #ifdef USBFS_EP_6_ISR_EXIT_CALLBACK\r
- USBFS_EP_6_ISR_ExitCallback();\r
- #endif /* USBFS_EP_6_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_EP_6_ISR_EXIT_CALLBACK\r
+ USBFS_EP_6_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_6_ISR_EXIT_CALLBACK) */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ \r
+ EA = intEn; /* Restore nested interrupt configuration. */\r
+ }\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
}\r
-\r
-#endif /* USBFS_EP6_ISR_REMOVE */\r
+#endif /* (USBFS_EP6_ISR_ACTIVE) */\r
\r
\r
-#if(USBFS_EP7_ISR_REMOVE == 0u)\r
-\r
+#if (USBFS_EP7_ISR_ACTIVE)\r
/*******************************************************************************\r
* Function Name: USBFS_EP_7_ISR\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Endpoint 7 Interrupt Service Routine\r
+ ****************************************************************************//**\r
*\r
- * Parameters:\r
- * None.\r
+ * Endpoint 7 Interrupt Service Routine.\r
*\r
- * Return:\r
- * None.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_7_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
- #ifdef USBFS_EP_7_ISR_ENTRY_CALLBACK\r
- USBFS_EP_7_ISR_EntryCallback();\r
- #endif /* USBFS_EP_7_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_EP_7_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_7_ISR_EntryCallback();\r
+ #endif /* (USBFS_EP_7_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START EP7_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
- CY_GET_REG8(USBFS_SIE_EP7_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_EP[USBFS_EP7].attrib & USBFS_EP_TYPE_MASK) !=\r
- USBFS_EP_TYPE_ISOC)\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
{\r
- USBFS_EP[USBFS_EP7].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ uint8 intEn = EA;\r
+ CyGlobalIntEnable; /* Enable nested interrupts. */\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ \r
+ USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP7_INTR);\r
+ \r
+ /* Notifies user that transfer IN or OUT transfer is completed.\r
+ * IN endpoint: endpoint buffer can be reloaded, Host is read data.\r
+ * OUT endpoint: data is ready to read from endpoint buffer. \r
+ */\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (0u != (USBFS_EP[USBFS_EP7].addr & USBFS_DIR_IN))\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ { \r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP7].epCr0;\r
+\r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(USBFS_EP7) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[USBFS_EP7].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+ \r
+ /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify\r
+ * user that DMA has completed copying data from OUT endpoint which is not completely true.\r
+ * Because last chunk of data is being copied.\r
+ * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast.\r
+ * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN).\r
+ */\r
+ USBFS_EP[USBFS_EP7].apiEpState = USBFS_EVENT_PENDING;\r
}\r
- USBFS_EP[USBFS_EP7].apiEpState = USBFS_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_SIE_EP_INT_EP7_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT)\r
+\r
+ #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO))\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP7)\r
{\r
- USBFS_MIDI_OUT_EP_Service();\r
+ USBFS_MIDI_OUT_Service();\r
}\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */\r
\r
/* `#START EP7_END_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- #ifdef USBFS_EP_7_ISR_EXIT_CALLBACK\r
- USBFS_EP_7_ISR_ExitCallback();\r
- #endif /* USBFS_EP_7_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_EP_7_ISR_EXIT_CALLBACK\r
+ USBFS_EP_7_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_7_ISR_EXIT_CALLBACK) */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ \r
+ EA = intEn; /* Restore nested interrupt configuration. */\r
+ }\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
}\r
+#endif /* (USBFS_EP7_ISR_ACTIVE) */\r
\r
-#endif /* USBFS_EP7_ISR_REMOVE */\r
-\r
-\r
-#if(USBFS_EP8_ISR_REMOVE == 0u)\r
\r
+#if (USBFS_EP8_ISR_ACTIVE)\r
/*******************************************************************************\r
* Function Name: USBFS_EP_8_ISR\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Endpoint 8 Interrupt Service Routine\r
*\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_8_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
-\r
- #ifdef USBFS_EP_8_ISR_ENTRY_CALLBACK\r
- USBFS_EP_8_ISR_EntryCallback();\r
- #endif /* USBFS_EP_8_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_EP_8_ISR_ENTRY_CALLBACK\r
+ USBFS_EP_8_ISR_EntryCallback();\r
+ #endif /* (USBFS_EP_8_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START EP8_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ {\r
+ uint8 intEn = EA;\r
+ CyGlobalIntEnable; /* Enable nested interrupts. */\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
\r
- CY_GET_REG8(USBFS_SIE_EP8_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_EP[USBFS_EP8].attrib & USBFS_EP_TYPE_MASK) !=\r
- USBFS_EP_TYPE_ISOC)\r
+ USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP8_INTR);\r
+ \r
+ /* Notifies user that transfer IN or OUT transfer is completed.\r
+ * IN endpoint: endpoint buffer can be reloaded, Host is read data.\r
+ * OUT endpoint: data is ready to read from endpoint buffer. \r
+ */\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ if (0u != (USBFS_EP[USBFS_EP8].addr & USBFS_DIR_IN))\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
{\r
- USBFS_EP[USBFS_EP8].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP8].epCr0;\r
+\r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(USBFS_EP8) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[USBFS_EP8].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+\r
+ /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify\r
+ * user that DMA has completed copying data from OUT endpoint which is not completely true.\r
+ * Because last chunk of data is being copied.\r
+ * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast.\r
+ * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN).\r
+ */\r
+ USBFS_EP[USBFS_EP8].apiEpState = USBFS_EVENT_PENDING;\r
}\r
- USBFS_EP[USBFS_EP8].apiEpState = USBFS_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_SIE_EP_INT_EP8_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_midi_out_ep == USBFS_EP8)\r
+ #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO))\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ if (USBFS_midi_out_ep == USBFS_EP8)\r
{\r
- USBFS_MIDI_OUT_EP_Service();\r
+ USBFS_MIDI_OUT_Service();\r
}\r
- #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */\r
\r
/* `#START EP8_END_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- #ifdef USBFS_EP_8_ISR_EXIT_CALLBACK\r
- USBFS_EP_8_ISR_ExitCallback();\r
- #endif /* USBFS_EP_8_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_EP_8_ISR_EXIT_CALLBACK\r
+ USBFS_EP_8_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_8_ISR_EXIT_CALLBACK) */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
- USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ \r
+ EA = intEn; /* Restore nested interrupt configuration. */\r
+ }\r
+ #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */\r
}\r
+#endif /* (USBFS_EP8_ISR_ACTIVE) */\r
\r
-#endif /* USBFS_EP8_ISR_REMOVE */\r
\r
+#if (USBFS_SOF_ISR_ACTIVE)\r
+ /*******************************************************************************\r
+ * Function Name: USBFS_SOF_ISR\r
+ ****************************************************************************//**\r
+ *\r
+ * Start of Frame Interrupt Service Routine.\r
+ *\r
+ *\r
+ *******************************************************************************/\r
+ CY_ISR(USBFS_SOF_ISR)\r
+ {\r
+ #ifdef USBFS_SOF_ISR_ENTRY_CALLBACK\r
+ USBFS_SOF_ISR_EntryCallback();\r
+ #endif /* (USBFS_SOF_ISR_ENTRY_CALLBACK) */\r
\r
-/*******************************************************************************\r
-* Function Name: USBFS_SOF_ISR\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Start of Frame Interrupt Service Routine\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-*******************************************************************************/\r
-CY_ISR(USBFS_SOF_ISR)\r
-{\r
- #ifdef USBFS_SOF_ISR_INTERRUPT_CALLBACK\r
- USBFS_SOF_ISR_InterruptCallback();\r
- #endif /* USBFS_SOF_ISR_INTERRUPT_CALLBACK */\r
-\r
- /* `#START SOF_USER_CODE` Place your code here */\r
+ /* `#START SOF_USER_CODE` Place your code here */\r
- /* `#END` */\r
-}\r
+ /* `#END` */\r
+\r
+ USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_SOF_INTR);\r
+\r
+ #ifdef USBFS_SOF_ISR_EXIT_CALLBACK\r
+ USBFS_SOF_ISR_ExitCallback();\r
+ #endif /* (USBFS_SOF_ISR_EXIT_CALLBACK) */\r
+ }\r
+#endif /* (USBFS_SOF_ISR_ACTIVE) */\r
\r
\r
+#if (USBFS_BUS_RESET_ISR_ACTIVE)\r
/*******************************************************************************\r
* Function Name: USBFS_BUS_RESET_ISR\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* USB Bus Reset Interrupt Service Routine. Calls _Start with the same\r
* parameters as the last USER call to _Start\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
*\r
*******************************************************************************/\r
CY_ISR(USBFS_BUS_RESET_ISR)\r
{\r
- #ifdef USBFS_BUS_RESET_ISR_ENTRY_CALLBACK\r
- USBFS_BUS_RESET_ISR_EntryCallback();\r
- #endif /* USBFS_BUS_RESET_ISR_ENTRY_CALLBACK */\r
+#ifdef USBFS_BUS_RESET_ISR_ENTRY_CALLBACK\r
+ USBFS_BUS_RESET_ISR_EntryCallback();\r
+#endif /* (USBFS_BUS_RESET_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START BUS_RESET_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
+ USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_BUS_RESET_INTR);\r
+\r
USBFS_ReInitComponent();\r
\r
- #ifdef USBFS_BUS_RESET_ISR_EXIT_CALLBACK\r
- USBFS_BUS_RESET_ISR_ExitCallback();\r
- #endif /* USBFS_BUS_RESET_ISR_EXIT_CALLBACK */ \r
+#ifdef USBFS_BUS_RESET_ISR_EXIT_CALLBACK\r
+ USBFS_BUS_RESET_ISR_ExitCallback();\r
+#endif /* (USBFS_BUS_RESET_ISR_EXIT_CALLBACK) */\r
}\r
+#endif /* (USBFS_BUS_RESET_ISR_ACTIVE) */\r
\r
\r
-#if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))\r
+#if (USBFS_LPM_ACTIVE)\r
+/***************************************************************************\r
+* Function Name: USBFS_INTR_LPM_ISR\r
+************************************************************************//**\r
+*\r
+* Interrupt Service Routine for LPM of the interrupt sources.\r
+*\r
+*\r
+***************************************************************************/\r
+CY_ISR(USBFS_LPM_ISR)\r
+{\r
+#ifdef USBFS_LPM_ISR_ENTRY_CALLBACK\r
+ USBFS_LPM_ISR_EntryCallback();\r
+#endif /* (USBFS_LPM_ISR_ENTRY_CALLBACK) */\r
\r
+ /* `#START LPM_BEGIN_USER_CODE` Place your code here */\r
\r
- /*******************************************************************************\r
+ /* `#END` */\r
+\r
+ USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_LPM_INTR);\r
+\r
+ /* `#START LPM_END_USER_CODE` Place your code here */\r
+\r
+ /* `#END` */\r
+\r
+#ifdef USBFS_LPM_ISR_EXIT_CALLBACK\r
+ USBFS_LPM_ISR_ExitCallback();\r
+#endif /* (USBFS_LPM_ISR_EXIT_CALLBACK) */\r
+}\r
+#endif /* (USBFS_LPM_ACTIVE) */\r
+\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE)\r
+ /***************************************************************************\r
* Function Name: USBFS_ARB_ISR\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Arbiter Interrupt Service Routine\r
+ ************************************************************************//**\r
*\r
- * Parameters:\r
- * None.\r
+ * Arbiter Interrupt Service Routine.\r
*\r
- * Return:\r
- * None.\r
*\r
- * Side effect:\r
- * Search for EP8 int_status will be much slower than search for EP1 int_status.\r
- *\r
- *******************************************************************************/\r
+ ***************************************************************************/\r
CY_ISR(USBFS_ARB_ISR)\r
{\r
- uint8 int_status;\r
- uint8 ep_status;\r
+ uint8 arbIntrStatus;\r
+ uint8 epStatus;\r
uint8 ep = USBFS_EP1;\r
- uint8 ptr = 0u;\r
\r
- #ifdef USBFS_ARB_ISR_ENTRY_CALLBACK\r
- USBFS_ARB_ISR_EntryCallback();\r
- #endif /* USBFS_ARB_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_ARB_ISR_ENTRY_CALLBACK\r
+ USBFS_ARB_ISR_EntryCallback();\r
+ #endif /* (USBFS_ARB_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START ARB_BEGIN_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- int_status = USBFS_ARB_INT_SR_REG; /* read Arbiter Status Register */\r
- USBFS_ARB_INT_SR_REG = int_status; /* Clear Serviced Interrupts */\r
+ /* Get pending ARB interrupt sources. */\r
+ arbIntrStatus = USBFS_ARB_INT_SR_REG;\r
\r
- while(int_status != 0u)\r
+ while (0u != arbIntrStatus)\r
{\r
- if((int_status & 1u) != 0u) /* If EpX interrupt present */\r
- { /* read Endpoint Status Register */\r
- ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr));\r
- /* If In Buffer Full */\r
- if((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) != 0u)\r
+ /* Check which EP is interrupt source. */\r
+ if (0u != (arbIntrStatus & 0x01u))\r
+ {\r
+ /* Get endpoint enable interrupt sources. */\r
+ epStatus = (USBFS_ARB_EP_BASE.arbEp[ep].epSr & USBFS_ARB_EP_BASE.arbEp[ep].epIntEn);\r
+\r
+ /* Handle IN endpoint buffer full event: happens only once when endpoint buffer is loaded. */\r
+ if (0u != (epStatus & USBFS_ARB_EPX_INT_IN_BUF_FULL))\r
{\r
- if((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u)\r
+ if (0u != (USBFS_EP[ep].addr & USBFS_DIR_IN))\r
{\r
- /* Clear Data ready status */\r
- *(reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) &=\r
- (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
- #if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- /* Setup common area DMA with rest of the data */\r
+ /* Clear data ready status. */\r
+ USBFS_ARB_EP_BASE.arbEp[ep].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+\r
+ #if (CY_PSOC3 || CY_PSOC5LP)\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ /* Set up common area DMA with rest of data. */\r
if(USBFS_inLength[ep] > USBFS_DMA_BYTES_PER_BURST)\r
{\r
USBFS_LoadNextInEP(ep, 0u);\r
{\r
USBFS_inBufFull[ep] = 1u;\r
}\r
- #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
- /* Write the Mode register */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), USBFS_EP[ep].epMode);\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN)\r
- if(ep == USBFS_midi_in_ep)\r
- { /* Clear MIDI input pointer */\r
- USBFS_midiInPointer = 0u;\r
- }\r
- #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+ /* Arm IN endpoint. */\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_EP[ep].epMode;\r
+\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN)\r
+ if (ep == USBFS_midi_in_ep)\r
+ {\r
+ /* Clear MIDI input pointer. */\r
+ USBFS_midiInPointer = 0u;\r
+ }\r
+ #endif /* (USBFS_ENABLE_MIDI_STREAMING) */\r
}\r
}\r
- /* (re)arm Out EP only for mode2 */\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- /* If DMA Grant */\r
- if((ep_status & USBFS_ARB_EPX_SR_DMA_GNT) != 0u)\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ /* Handle DMA completion event for OUT endpoints. */\r
+ if (0u != (epStatus & USBFS_ARB_EPX_SR_DMA_GNT))\r
+ {\r
+ if (0u == (USBFS_EP[ep].addr & USBFS_DIR_IN))\r
{\r
- if((USBFS_EP[ep].addr & USBFS_DIR_IN) == 0u)\r
- {\r
- USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING;\r
- /* Write the Mode register */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr),\r
- USBFS_EP[ep].epMode);\r
- }\r
+ /* Notify user that data has been copied from endpoint buffer. */\r
+ USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING;\r
+\r
+ /* DMA done coping data: OUT endpoint has to be re-armed by user. */\r
+ }\r
+ }\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
+\r
+ #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Handle DMA completion event for OUT endpoints. */\r
+ if (0u != (epStatus & USBFS_ARB_EPX_INT_DMA_TERMIN))\r
+ {\r
+ uint32 channelNum = USBFS_DmaChan[ep];\r
+\r
+ /* Restore burst counter for endpoint. */\r
+ USBFS_DmaEpBurstCnt[ep] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCntBackup[ep]);\r
+\r
+ /* Disable DMA channel to restore descriptor configuration. The on-going transfer is aborted. */\r
+ USBFS_CyDmaChDisable(channelNum);\r
+\r
+ /* Generate DMA tr_out signal to notify USB IP that DMA is done. This signal is not generated\r
+ * when transfer was aborted (it occurs when host writes less bytes than buffer size).\r
+ */\r
+ USBFS_CyDmaTriggerOut(USBFS_DmaBurstEndOut[ep]);\r
+\r
+ /* Restore destination address for output endpoint. */\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[ep]));\r
+ USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[ep] +\r
+ USBFS_DMA_BYTES_PER_BURST));\r
+\r
+ /* Restore number of data elements to transfer which was adjusted for last burst. */\r
+ if (0u != (USBFS_DmaEpLastBurstEl[ep] & USBFS_DMA_DESCR_REVERT))\r
+ {\r
+ USBFS_CyDmaSetNumDataElements(channelNum, (USBFS_DmaEpLastBurstEl[ep] >> USBFS_DMA_DESCR_SHIFT),\r
+ USBFS_DMA_GET_MAX_ELEM_PER_BURST(USBFS_DmaEpLastBurstEl[ep]));\r
}\r
- #endif /* USBFS_EP_MM */\r
+\r
+ /* Validate descriptor 0 and 1 (also reset current state). Command to start with descriptor 0. */\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0);\r
+ if (USBFS_DmaEpBurstCntBackup[ep] > 1u)\r
+ {\r
+ USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1);\r
+ }\r
+ USBFS_CyDmaSetDescriptor0Next(channelNum);\r
+\r
+ /* Enable DMA channel: configuration complete. */\r
+ USBFS_CyDmaChEnable(channelNum);\r
+ \r
+ \r
+ /* Read CR0 register to clear SIE lock. */\r
+ (void) USBFS_SIE_EP_BASE.sieEp[ep].epCr0;\r
+ \r
+ /* Toggle all endpoint types except ISOC. */\r
+ if (USBFS_GET_EP_TYPE(ep) != USBFS_EP_TYPE_ISOC)\r
+ {\r
+ USBFS_EP[ep].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE;\r
+ }\r
+ \r
+ /* Notify user that data has been copied from endpoint buffer. */\r
+ USBFS_EP[ep].apiEpState = USBFS_EVENT_PENDING;\r
+ \r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
+ !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ if (USBFS_midi_out_ep == ep)\r
+ {\r
+ USBFS_MIDI_OUT_Service();\r
+ }\r
+ #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */\r
+ }\r
+ #endif /* (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+\r
\r
/* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */\r
/* `#END` */\r
\r
- #ifdef USBFS_ARB_ISR_CALLBACK\r
- USBFS_ARB_ISR_Callback();\r
- #endif /* USBFS_ARB_ISR_CALLBACK */\r
+ #ifdef USBFS_ARB_ISR_CALLBACK\r
+ USBFS_ARB_ISR_Callback(ep, epStatus);\r
+ #endif /* (USBFS_ARB_ISR_CALLBACK) */\r
\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr), ep_status); /* Clear Serviced events */\r
+ /* Clear serviced endpoint interrupt sources. */\r
+ USBFS_ARB_EP_BASE.arbEp[ep].epSr = epStatus;\r
}\r
- ptr += USBFS_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */\r
- ep++;\r
- int_status >>= 1u;\r
+\r
+ ++ep;\r
+ arbIntrStatus >>= 1u;\r
}\r
\r
/* `#START ARB_END_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- #ifdef USBFS_ARB_ISR_EXIT_CALLBACK\r
- USBFS_ARB_ISR_ExitCallback();\r
- #endif /* USBFS_ARB_ISR_EXIT_CALLBACK */\r
+ #ifdef USBFS_ARB_ISR_EXIT_CALLBACK\r
+ USBFS_ARB_ISR_ExitCallback();\r
+ #endif /* (USBFS_ARB_ISR_EXIT_CALLBACK) */\r
}\r
\r
-#endif /* USBFS_EP_MM */\r
+#endif /* (USBFS_ARB_ISR_ACTIVE && USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+#if (CY_PSOC4)\r
\r
-#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
/******************************************************************************\r
- * Function Name: USBFS_EP_DMA_DONE_ISR\r
- *******************************************************************************\r
- *\r
- * Summary:\r
- * Endpoint 1 DMA Done Interrupt Service Routine\r
- *\r
- * Parameters:\r
- * None.\r
+ * Function Name: USBFS_EPxDmaDone\r
+ ***************************************************************************//**\r
*\r
- * Return:\r
- * None.\r
+ * \internal\r
+ * Endpoint DMA Done Interrupt Service Routine basic function .\r
+ * \r
+ * \param dmaCh\r
+ * number of DMA channel\r
+ * \r
+ * \param ep\r
+ * number of USB end point\r
+ * \r
+ * \param dmaDone\r
+ * transfer completion flag\r
+ * \r
+ * \return\r
+ * updated transfer completion flag\r
*\r
******************************************************************************/\r
- CY_ISR(USBFS_EP_DMA_DONE_ISR)\r
+ CY_INLINE static void USBFS_EPxDmaDone(uint8 dmaCh, uint8 ep)\r
{\r
- uint8 int8Status;\r
- uint8 int17Status;\r
- uint8 ep_status;\r
- uint8 ep = USBFS_EP1;\r
- uint8 ptr = 0u;\r
+ uint32 nextAddr;\r
+\r
+ /* Manage data elements which remain to transfer. */\r
+ if (0u != USBFS_DmaEpBurstCnt[ep])\r
+ {\r
+ if(USBFS_DmaEpBurstCnt[ep] <= 2u)\r
+ {\r
+ /* Adjust length of last burst. */\r
+ USBFS_CyDmaSetNumDataElements(dmaCh,\r
+ ((uint32) USBFS_DmaEpLastBurstEl[ep] >> USBFS_DMA_DESCR_SHIFT),\r
+ ((uint32) USBFS_DmaEpLastBurstEl[ep] & USBFS_DMA_BURST_BYTES_MASK));\r
+ }\r
+ \r
+\r
+ /* Advance source for input endpoint or destination for output endpoint. */\r
+ if (0u != (USBFS_EP[ep].addr & USBFS_DIR_IN))\r
+ {\r
+ /* Change source for descriptor 0. */\r
+ nextAddr = (uint32) USBFS_CyDmaGetSrcAddress(dmaCh, USBFS_DMA_DESCR0);\r
+ nextAddr += (2u * USBFS_DMA_BYTES_PER_BURST);\r
+ USBFS_CyDmaSetSrcAddress(dmaCh, USBFS_DMA_DESCR0, (void *) nextAddr);\r
+\r
+ /* Change source for descriptor 1. */\r
+ nextAddr += USBFS_DMA_BYTES_PER_BURST;\r
+ USBFS_CyDmaSetSrcAddress(dmaCh, USBFS_DMA_DESCR1, (void *) nextAddr);\r
+ }\r
+ else\r
+ {\r
+ /* Change destination for descriptor 0. */\r
+ nextAddr = (uint32) USBFS_CyDmaGetDstAddress(dmaCh, USBFS_DMA_DESCR0);\r
+ nextAddr += (2u * USBFS_DMA_BYTES_PER_BURST);\r
+ USBFS_CyDmaSetDstAddress(dmaCh, USBFS_DMA_DESCR0, (void *) nextAddr);\r
+\r
+ /* Change destination for descriptor 1. */\r
+ nextAddr += USBFS_DMA_BYTES_PER_BURST;\r
+ USBFS_CyDmaSetDstAddress(dmaCh, USBFS_DMA_DESCR1, (void *) nextAddr);\r
+ }\r
+\r
+ /* Enable DMA to execute transfer as it was disabled because there were no valid descriptor. */\r
+ USBFS_CyDmaValidateDescriptor(dmaCh, USBFS_DMA_DESCR0);\r
+ \r
+ --USBFS_DmaEpBurstCnt[ep];\r
+ if (0u != USBFS_DmaEpBurstCnt[ep])\r
+ {\r
+ USBFS_CyDmaValidateDescriptor(dmaCh, USBFS_DMA_DESCR1);\r
+ --USBFS_DmaEpBurstCnt[ep];\r
+ }\r
+ \r
+ USBFS_CyDmaChEnable (dmaCh);\r
+ USBFS_CyDmaTriggerIn(USBFS_DmaReqOut[ep]);\r
+ }\r
+ else\r
+ {\r
+ /* No data to transfer. False DMA trig. Ignore. */\r
+ }\r
+\r
+ }\r
+\r
+ #if (USBFS_DMA1_ACTIVE)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP1_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * Endpoint 1 DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ void USBFS_EP1_DMA_DONE_ISR(void)\r
+ {\r
+\r
+ USBFS_EPxDmaDone((uint8)USBFS_EP1_DMA_CH,\r
+ USBFS_EP1);\r
+ \r
+ }\r
+ #endif /* (USBFS_DMA1_ACTIVE) */\r
+\r
+\r
+ #if (USBFS_DMA2_ACTIVE)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP2_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * Endpoint 2 DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ void USBFS_EP2_DMA_DONE_ISR(void)\r
+ {\r
+\r
+ USBFS_EPxDmaDone((uint8)USBFS_EP2_DMA_CH,\r
+ USBFS_EP2);\r
+ }\r
+ #endif /* (USBFS_DMA2_ACTIVE) */\r
+\r
+\r
+ #if (USBFS_DMA3_ACTIVE)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP3_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * Endpoint 3 DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ void USBFS_EP3_DMA_DONE_ISR(void)\r
+ {\r
+\r
+ USBFS_EPxDmaDone((uint8)USBFS_EP3_DMA_CH,\r
+ USBFS_EP3);\r
+ }\r
+ #endif /* (USBFS_DMA3_ACTIVE) */\r
+\r
+\r
+ #if (USBFS_DMA4_ACTIVE)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP4_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * Endpoint 4 DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ void USBFS_EP4_DMA_DONE_ISR(void)\r
+ {\r
+\r
+ USBFS_EPxDmaDone((uint8)USBFS_EP4_DMA_CH,\r
+ USBFS_EP4);\r
+ }\r
+ #endif /* (USBFS_DMA4_ACTIVE) */\r
+\r
+\r
+ #if (USBFS_DMA5_ACTIVE)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP5_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * Endpoint 5 DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ void USBFS_EP5_DMA_DONE_ISR(void)\r
+ {\r
+\r
+ USBFS_EPxDmaDone((uint8)USBFS_EP5_DMA_CH,\r
+ USBFS_EP5);\r
+ }\r
+ #endif /* (USBFS_DMA5_ACTIVE) */\r
+\r
+\r
+ #if (USBFS_DMA6_ACTIVE)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP6_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * Endpoint 6 DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ void USBFS_EP6_DMA_DONE_ISR(void)\r
+ {\r
+\r
+ USBFS_EPxDmaDone((uint8)USBFS_EP6_DMA_CH,\r
+ USBFS_EP6);\r
+ }\r
+ #endif /* (USBFS_DMA6_ACTIVE) */\r
+\r
+\r
+ #if (USBFS_DMA7_ACTIVE)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP7_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * Endpoint 7 DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ void USBFS_EP7_DMA_DONE_ISR(void)\r
+ {\r
+\r
+ USBFS_EPxDmaDone((uint8)USBFS_EP7_DMA_CH,\r
+ USBFS_EP7);\r
+ }\r
+ #endif /* (USBFS_DMA7_ACTIVE) */\r
+\r
+\r
+ #if (USBFS_DMA8_ACTIVE)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP8_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * Endpoint 8 DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ void USBFS_EP8_DMA_DONE_ISR(void)\r
+ {\r
+\r
+ USBFS_EPxDmaDone((uint8)USBFS_EP8_DMA_CH,\r
+ USBFS_EP8);\r
+ }\r
+ #endif /* (USBFS_DMA8_ACTIVE) */\r
+\r
+\r
+#else\r
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP_DMA_DONE_ISR\r
+ ***************************************************************************//**\r
+ *\r
+ * DMA Done Interrupt Service Routine.\r
+ *\r
+ *\r
+ ******************************************************************************/\r
+ CY_ISR(USBFS_EP_DMA_DONE_ISR)\r
+ {\r
+ uint8 int8Status;\r
+ uint8 int17Status;\r
+ uint8 ep_status;\r
+ uint8 ep = USBFS_EP1;\r
\r
#ifdef USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK\r
USBFS_EP_DMA_DONE_ISR_EntryCallback();\r
- #endif /* USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK */\r
+ #endif /* (USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK) */\r
\r
- /* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */\r
+ /* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */\r
- /* `#END` */\r
+ /* `#END` */\r
\r
- /* Read clear on read status register with the EP source of interrupt */\r
- int17Status = USBFS_EP17_DMA_Done_SR_Read() & USBFS_EP17_SR_MASK;\r
- int8Status = USBFS_EP8_DMA_Done_SR_Read() & USBFS_EP8_SR_MASK;\r
+ /* Read clear on read status register with EP source of interrupt. */\r
+ int17Status = USBFS_EP17_DMA_Done_SR_Read() & USBFS_EP17_SR_MASK;\r
+ int8Status = USBFS_EP8_DMA_Done_SR_Read() & USBFS_EP8_SR_MASK;\r
\r
- while(int8Status != 0u)\r
- {\r
- while(int17Status != 0u)\r
+ while (int8Status != 0u)\r
{\r
- if((int17Status & 1u) != 0u) /* If EpX interrupt present */\r
+ while (int17Status != 0u)\r
{\r
- /* Read Endpoint Status Register */\r
- ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr));\r
- if( ((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) == 0u) &&\r
- (USBFS_inBufFull[ep] == 0u))\r
+ if ((int17Status & 1u) != 0u) /* If EpX interrupt present. */\r
{\r
- /* `#START EP_DMA_DONE_USER_CODE` Place your code here */\r
+ /* Read Endpoint Status Register. */\r
+ ep_status = USBFS_ARB_EP_BASE.arbEp[ep].epSr;\r
+\r
+ if ((0u == (ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL)) &&\r
+ (0u ==USBFS_inBufFull[ep]))\r
+ {\r
+ /* `#START EP_DMA_DONE_USER_CODE` Place your code here */\r
- /* `#END` */\r
+ /* `#END` */\r
\r
#ifdef USBFS_EP_DMA_DONE_ISR_CALLBACK\r
USBFS_EP_DMA_DONE_ISR_Callback();\r
- #endif /* USBFS_EP_DMA_DONE_ISR_CALLBACK */\r
-\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ptr), 0x00u);\r
- /* repeat 2 last bytes to prefetch endpoint area */\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ptr),\r
- USBFS_DMA_BYTES_PER_BURST * ep - USBFS_DMA_BYTES_REPEAT);\r
- USBFS_LoadNextInEP(ep, 1);\r
- /* Set Data ready status, This will generate DMA request */\r
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+ #endif /* (USBFS_EP_DMA_DONE_ISR_CALLBACK) */\r
+\r
+ /* Transfer again 2 last bytes into pre-fetch endpoint area. */\r
+ USBFS_ARB_EP_BASE.arbEp[ep].rwWaMsb = 0u;\r
+ USBFS_ARB_EP_BASE.arbEp[ep].rwWa = (USBFS_DMA_BYTES_PER_BURST * ep) - USBFS_DMA_BYTES_REPEAT;\r
+ USBFS_LoadNextInEP(ep, 1u);\r
+\r
+ /* Set Data ready status to generate DMA request. */\r
+ USBFS_ARB_EP_BASE.arbEp[ep].epCfg |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+ }\r
}\r
+\r
+ ep++;\r
+ int17Status >>= 1u;\r
+ }\r
+\r
+ int8Status >>= 1u;\r
+\r
+ if (int8Status != 0u)\r
+ {\r
+ /* Prepare pointer for EP8. */\r
+ ep = USBFS_EP8;\r
+ int17Status = int8Status & 0x01u;\r
}\r
- ptr += USBFS_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */\r
- ep++;\r
- int17Status >>= 1u;\r
}\r
- int8Status >>= 1u;\r
- if(int8Status != 0u)\r
+\r
+ /* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */\r
+
+ /* `#END` */\r
+\r
+ #ifdef USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK\r
+ USBFS_EP_DMA_DONE_ISR_ExitCallback();\r
+ #endif /* (USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK) */\r
+ }\r
+ #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+#endif /* (CY_PSOC4) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+\r
+\r
+#if (CY_PSOC4)\r
+ /***************************************************************************\r
+ * Function Name: USBFS_IntrHandler\r
+ ************************************************************************//**\r
+ *\r
+ * Interrupt handler for Hi/Mid/Low ISRs.\r
+ *\r
+ * regCause - The cause register of interrupt. One of the three variants:\r
+ * USBFS_INTR_CAUSE_LO_REG - Low interrupts.\r
+ * USBFS_INTR_CAUSE_MED_REG - Med interrupts.\r
+ * USBFS_INTR_CAUSE_HI_REG - - High interrupts.\r
+ *\r
+ *\r
+ ***************************************************************************/\r
+ CY_INLINE static void USBFS_IntrHandler(uint32 intrCause)\r
+ {\r
+ /* Array of pointers to component interrupt handlers. */\r
+ static const cyisraddress USBFS_isrCallbacks[] =\r
+ {\r
+\r
+ };\r
+\r
+ uint32 cbIdx = 0u;\r
+\r
+ /* Check arbiter interrupt source first. */\r
+ if (0u != (intrCause & USBFS_INTR_CAUSE_ARB_INTR))\r
+ {\r
+ USBFS_isrCallbacks[USBFS_ARB_EP_INTR_NUM]();\r
+ }\r
+\r
+ /* Check all other interrupt sources (except arbiter and resume). */\r
+ intrCause = (intrCause & USBFS_INTR_CAUSE_CTRL_INTR_MASK) |\r
+ ((intrCause & USBFS_INTR_CAUSE_EP1_8_INTR_MASK) >>\r
+ USBFS_INTR_CAUSE_EP_INTR_SHIFT);\r
+\r
+ /* Call interrupt handlers for active interrupt sources. */\r
+ while (0u != intrCause)\r
+ {\r
+ if (0u != (intrCause & 0x1u))\r
{\r
- /* Prepare pointer for EP8 */\r
- ptr = ((USBFS_EP8 - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
- ep = USBFS_EP8;\r
- int17Status = int8Status & 0x01u;\r
+ USBFS_isrCallbacks[cbIdx]();\r
}\r
+\r
+ intrCause >>= 1u;\r
+ ++cbIdx;\r
}\r
+ }\r
\r
- /* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */\r
-
- /* `#END` */\r
\r
- #ifdef USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK\r
- USBFS_EP_DMA_DONE_ISR_ExitCallback();\r
- #endif /* USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK */\r
+ /***************************************************************************\r
+ * Function Name: USBFS_INTR_HI_ISR\r
+ ************************************************************************//**\r
+ *\r
+ * Interrupt Service Routine for the high group of the interrupt sources.\r
+ *\r
+ *\r
+ ***************************************************************************/\r
+ CY_ISR(USBFS_INTR_HI_ISR)\r
+ {\r
+ USBFS_IntrHandler(USBFS_INTR_CAUSE_HI_REG);\r
+ }\r
+\r
+ /***************************************************************************\r
+ * Function Name: USBFS_INTR_MED_ISR\r
+ ************************************************************************//**\r
+ *\r
+ * Interrupt Service Routine for the medium group of the interrupt sources.\r
+ *\r
+ *\r
+ ***************************************************************************/\r
+ CY_ISR(USBFS_INTR_MED_ISR)\r
+ {\r
+ USBFS_IntrHandler(USBFS_INTR_CAUSE_MED_REG);\r
+ }\r
+\r
+ /***************************************************************************\r
+ * Function Name: USBFS_INTR_LO_ISR\r
+ ************************************************************************//**\r
+ *\r
+ * Interrupt Service Routine for the low group of the interrupt sources.\r
+ *\r
+ *\r
+ ***************************************************************************/\r
+ CY_ISR(USBFS_INTR_LO_ISR)\r
+ {\r
+ USBFS_IntrHandler(USBFS_INTR_CAUSE_LO_REG);\r
}\r
-#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+#endif /* (CY_PSOC4) */\r
\r
\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: USBFS_hid.c\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_hid.c\r
+* \version 3.10\r
*\r
-* Description:\r
-* USB HID Class request handler.\r
+* \brief\r
+* This file contains the USB HID Class request handler. \r
*\r
* Related Document:\r
* Device Class Definition for Human Interface Devices (HID) Version 1.11\r
*\r
-* Note:\r
-*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
-\r
-#if defined(USBFS_ENABLE_HID_CLASS)\r
-\r
-#include "USBFS_pvt.h"\r
#include "USBFS_hid.h"\r
+#include "USBFS_pvt.h"\r
+\r
\r
\r
+#if defined(USBFS_ENABLE_HID_CLASS)\r
\r
/***************************************\r
* HID Variables\r
***************************************/\r
-\r
-volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER]; /* HID device protocol status */\r
-volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER]; /* HID device idle reload value */\r
+/** This variable is initialized in the USBFS_InitComponent() API to the \r
+ * PROTOCOL_REPORT value. It is controlled by the host using the \r
+ * HID_SET_PROTOCOL request. The value is returned to the user code by the \r
+ * USBFS_GetProtocol() API.*/\r
+volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER];\r
+\r
+/** This variable controls the HID report rate. It is controlled by the host \r
+ * using the HID_SET_IDLE request and used by the USBFS_UpdateHIDTimer() API to \r
+ * reload timer.*/\r
+volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER];\r
+\r
+/** This variable contains the timer counter, which is decremented and reloaded \r
+ * by the USBFS_UpdateHIDTimer() API.*/\r
volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER]; /* HID device idle rate value */\r
\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_UpdateHIDTimer\r
-********************************************************************************\r
+****************************************************************************//**\r
+*\r
+* This function updates the HID Report idle timer and returns the status and \r
+* reloads the timer if it expires.\r
*\r
-* Summary:\r
-* Updates the HID report timer and reloads it if expired\r
+* \param interface Contains the interface number.\r
*\r
-* Parameters:\r
-* interface: Interface Number.\r
+* \return\r
+* Returns the state of the HID timer. Symbolic names and their associated values are given here:\r
+* Return Value |Notes\r
+* ---------------------------|------------------------------------------------\r
+* USBFS_IDLE_TIMER_EXPIRED | The timer expired.\r
+* USBFS_IDLE_TIMER_RUNNING | The timer is running.\r
+* USBFS_IDLE_TIMER_IDEFINITE | The report is sent when data or state changes.\r
*\r
-* Return:\r
-* status.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
}\r
}\r
\r
- return(stat);\r
+ return((uint8)stat);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_GetProtocol\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* Returns the selected protocol value to the application\r
+* This function returns the HID protocol value for the selected interface.\r
*\r
-* Parameters:\r
-* interface: Interface Number.\r
+* \param interface: Contains the interface number.\r
*\r
-* Return:\r
-* Interface protocol.\r
+* \return\r
+* Returns the protocol value. \r
*\r
*******************************************************************************/\r
uint8 USBFS_GetProtocol(uint8 interface) \r
\r
/*******************************************************************************\r
* Function Name: USBFS_DispatchHIDClassRqst\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine dispatches class requests\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* requestHandled\r
+* \return\r
+* Results of HID Class request handling: \r
+* - USBFS_TRUE - request was handled without errors\r
+* - USBFS_FALSE - error occurs during handling of request \r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_DispatchHIDClassRqst(void) \r
{\r
uint8 requestHandled = USBFS_FALSE;\r
- uint8 interfaceNumber;\r
\r
- interfaceNumber = CY_GET_REG8(USBFS_wIndexLo);\r
- if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)\r
- { /* Control Read */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ uint8 interfaceNumber = (uint8) USBFS_wIndexLoReg;\r
+ \r
+ /* Check request direction: D2H or H2D. */\r
+ if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H))\r
+ {\r
+ /* Handle direction from device to host. */\r
+ \r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_GET_DESCRIPTOR:\r
- if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_CLASS)\r
+ if (USBFS_wValueHiReg == USBFS_DESCR_HID_CLASS)\r
{\r
USBFS_FindHidClassDecriptor();\r
if (USBFS_currentTD.count != 0u)\r
requestHandled = USBFS_InitControlRead();\r
}\r
}\r
- else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_REPORT)\r
+ else if (USBFS_wValueHiReg == USBFS_DESCR_HID_REPORT)\r
{\r
USBFS_FindReportDescriptor();\r
if (USBFS_currentTD.count != 0u)\r
}\r
}\r
else\r
- { /* requestHandled is initialezed as FALSE by default */\r
+ { \r
+ /* Do not handle this request. */\r
}\r
break;\r
+ \r
case USBFS_HID_GET_REPORT:\r
USBFS_FindReport();\r
if (USBFS_currentTD.count != 0u)\r
\r
case USBFS_HID_GET_IDLE:\r
/* This function does not support multiple reports per interface*/\r
- /* Validate interfaceNumber and Report ID (should be 0) */\r
- if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) &&\r
- (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */\r
+ /* Validate interfaceNumber and Report ID (should be 0): Do not support Idle per Report ID */\r
+ if ((interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && (USBFS_wValueLoReg == 0u)) \r
{\r
USBFS_currentTD.count = 1u;\r
USBFS_currentTD.pData = &USBFS_hidIdleRate[interfaceNumber];\r
requestHandled = USBFS_InitControlRead();\r
}\r
break;\r
+ \r
case USBFS_HID_GET_PROTOCOL:\r
/* Validate interfaceNumber */\r
if( interfaceNumber < USBFS_MAX_INTERFACES_NUMBER)\r
requestHandled = USBFS_InitControlRead();\r
}\r
break;\r
+ \r
default: /* requestHandled is initialized as FALSE by default */\r
break;\r
}\r
}\r
- else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) ==\r
- USBFS_RQST_DIR_H2D)\r
- { /* Control Write */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ else\r
+ { \r
+ /* Handle direction from host to device. */\r
+ \r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_HID_SET_REPORT:\r
USBFS_FindReport();\r
requestHandled = USBFS_InitControlWrite();\r
}\r
break;\r
+ \r
case USBFS_HID_SET_IDLE:\r
/* This function does not support multiple reports per interface */\r
- /* Validate interfaceNumber and Report ID (should be 0) */\r
- if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) &&\r
- (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */\r
+ /* Validate interfaceNumber and Report ID (should be 0): Do not support Idle per Report ID */\r
+ if ((interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && (USBFS_wValueLoReg == 0u))\r
{\r
- USBFS_hidIdleRate[interfaceNumber] = CY_GET_REG8(USBFS_wValueHi);\r
+ USBFS_hidIdleRate[interfaceNumber] = (uint8)USBFS_wValueHiReg;\r
/* With regards to HID spec: "7.2.4 Set_Idle Request"\r
* Latency. If the current period has gone past the\r
* newly proscribed time duration, then a report\r
\r
case USBFS_HID_SET_PROTOCOL:\r
/* Validate interfaceNumber and protocol (must be 0 or 1) */\r
- if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) &&\r
- (CY_GET_REG8(USBFS_wValueLo) <= 1u) )\r
+ if ((interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && (USBFS_wValueLoReg <= 1u))\r
{\r
- USBFS_hidProtocol[interfaceNumber] = CY_GET_REG8(USBFS_wValueLo);\r
+ USBFS_hidProtocol[interfaceNumber] = (uint8)USBFS_wValueLoReg;\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
}\r
break;\r
- default: /* requestHandled is initialized as FALSE by default */\r
+ \r
+ default: \r
+ /* Unknown class request is not handled. */\r
break;\r
}\r
}\r
- else\r
- { /* requestHandled is initialized as FALSE by default */\r
- }\r
\r
- return(requestHandled);\r
+ return (requestHandled);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USB_FindHidClassDescriptor\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine find Hid Class Descriptor pointer based on the Interface number\r
* and Alternate setting then loads the currentTD structure with the address of\r
* the buffer and the size.\r
* The HID Class Descriptor resides inside the config descriptor.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* currentTD\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 interfaceN;\r
\r
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);\r
- interfaceN = CY_GET_REG8(USBFS_wIndexLo);\r
+ \r
+ interfaceN = (uint8) USBFS_wIndexLoReg;\r
/* Third entry in the LUT starts the Interface Table pointers */\r
/* Now use the request interface number*/\r
pTmp = &pTmp[interfaceN + 2u];\r
+ \r
/* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */\r
pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list;\r
+ \r
/* Now use Alternate setting number */\r
pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]];\r
+ \r
/* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */\r
pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list;\r
+ \r
/* Fifth entry in the LUT points to Hid Class Descriptor in Configuration Descriptor */\r
pTmp = &pTmp[4u];\r
pDescr = (volatile uint8 *)pTmp->p_list;\r
+ \r
/* The first byte contains the descriptor length */\r
USBFS_currentTD.count = *pDescr;\r
USBFS_currentTD.pData = pDescr;\r
\r
/*******************************************************************************\r
* Function Name: USB_FindReportDescriptor\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine find Hid Report Descriptor pointer based on the Interface\r
* number, then loads the currentTD structure with the address of the buffer\r
* and the size.\r
* Hid Report Descriptor is located after IN/OUT/FEATURE reports.\r
*\r
-* Parameters:\r
-* void\r
-*\r
-* Return:\r
+* \return\r
* currentTD\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 interfaceN;\r
\r
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);\r
- interfaceN = CY_GET_REG8(USBFS_wIndexLo);\r
+ interfaceN = (uint8) USBFS_wIndexLoReg;\r
+ \r
/* Third entry in the LUT starts the Interface Table pointers */\r
/* Now use the request interface number */\r
pTmp = &pTmp[interfaceN + 2u];\r
+ \r
/* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */\r
pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list;\r
+ \r
/* Now use Alternate setting number */\r
pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]];\r
+ \r
/* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */\r
pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list;\r
+ \r
/* Fourth entry in the LUT starts the Hid Report Descriptor */\r
pTmp = &pTmp[3u];\r
pDescr = (volatile uint8 *)pTmp->p_list;\r
+ \r
/* The 1st and 2nd bytes of descriptor contain its length. LSB is 1st. */\r
- USBFS_currentTD.count = (((uint16)pDescr[1u] << 8u) | pDescr[0u]);\r
+ USBFS_currentTD.count = ((uint16)((uint16) pDescr[1u] << 8u) | pDescr[0u]);\r
USBFS_currentTD.pData = &pDescr[2u];\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_FindReport\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine sets up a transfer based on the Interface number, Report Type\r
* and Report ID, then loads the currentTD structure with the address of the\r
* buffer and the size. The caller has to decide if it is a control read or\r
* control write.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* currentTD\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
{\r
const T_USBFS_LUT CYCODE *pTmp;\r
T_USBFS_TD *pTD;\r
- uint8 interfaceN;\r
uint8 reportType;\r
-\r
+ uint8 interfaceN;\r
+ \r
/* `#START HID_FINDREPORT` Place custom handling here */\r
/* `#END` */\r
\r
- #ifdef USBFS_FIND_REPORT_CALLBACK\r
- USBFS_FindReport_Callback();\r
- #endif /* USBFS_FIND_REPORT_CALLBACK */\r
+#ifdef USBFS_FIND_REPORT_CALLBACK\r
+ USBFS_FindReport_Callback();\r
+#endif /* (USBFS_FIND_REPORT_CALLBACK) */\r
\r
USBFS_currentTD.count = 0u; /* Init not supported condition */\r
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);\r
- reportType = CY_GET_REG8(USBFS_wValueHi);\r
- interfaceN = CY_GET_REG8(USBFS_wIndexLo);\r
- /* Third entry in the LUT COnfiguration Table starts the Interface Table pointers */\r
+ reportType = (uint8) USBFS_wValueHiReg;\r
+ interfaceN = (uint8) USBFS_wIndexLoReg;\r
+ \r
+ /* Third entry in the LUT Configuration Table starts the Interface Table pointers */\r
/* Now use the request interface number */\r
pTmp = &pTmp[interfaceN + 2u];\r
- /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE*/\r
+ \r
+ /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */\r
pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list;\r
- if(interfaceN < USBFS_MAX_INTERFACES_NUMBER)\r
+ if (interfaceN < USBFS_MAX_INTERFACES_NUMBER)\r
{\r
/* Now use Alternate setting number */\r
pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]];\r
+ \r
/* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */\r
pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list;\r
+ \r
/* Validate reportType to comply with "7.2.1 Get_Report Request" */\r
- if((reportType >= USBFS_HID_GET_REPORT_INPUT) &&\r
- (reportType <= USBFS_HID_GET_REPORT_FEATURE))\r
+ if ((reportType >= USBFS_HID_GET_REPORT_INPUT) &&\r
+ (reportType <= USBFS_HID_GET_REPORT_FEATURE))\r
{\r
/* Get the entry proper TD (IN, OUT or Feature Report Table)*/\r
pTmp = &pTmp[reportType - 1u];\r
- reportType = CY_GET_REG8(USBFS_wValueLo); /* Get reportID */\r
+ \r
+ /* Get reportID */\r
+ reportType = (uint8) USBFS_wValueLoReg;\r
+ \r
/* Validate table support by the HID descriptor, compare table count with reportID */\r
- if(pTmp->c >= reportType)\r
+ if (pTmp->c >= reportType)\r
{\r
pTD = (T_USBFS_TD *) pTmp->p_list;\r
pTD = &pTD[reportType]; /* select entry depend on report ID*/\r
-/*******************************************************************************\r
-* File Name: USBFS_hid.h\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_hid.h\r
+* \version 3.10\r
*\r
-* Description:\r
-* Header File for the USBFS component. Contains prototypes and constant values.\r
+* \brief\r
+* This file provides function prototypes and constants for the USBFS component \r
+* HID class.\r
*\r
* Related Document:\r
* Device Class Definition for Human Interface Devices (HID) Version 1.11\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#if !defined(CY_USBFS_USBFS_hid_H)\r
#define CY_USBFS_USBFS_hid_H\r
\r
-#include "cytypes.h"\r
-\r
+#include "USBFS.h"\r
\r
/***************************************\r
* Prototypes of the USBFS_hid API.\r
***************************************/\r
-\r
+/**\r
+* \addtogroup group_hid\r
+* @{\r
+*/\r
uint8 USBFS_UpdateHIDTimer(uint8 interface) ;\r
-uint8 USBFS_GetProtocol(uint8 interface) ;\r
-\r
+uint8 USBFS_GetProtocol(uint8 interface) ;\r
+/** @} hid */\r
\r
/***************************************\r
*Renamed Functions for backward compatible\r
***************************************/\r
\r
-#define USBFS_bGetProtocol USBFS_GetProtocol\r
+#define USBFS_bGetProtocol USBFS_GetProtocol\r
\r
\r
/***************************************\r
-/*******************************************************************************\r
-* File Name: USBFS_midi.c\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_midi.c\r
+* \version 3.10\r
*\r
-* Description:\r
+* \brief\r
* MIDI Streaming request handler.\r
* This file contains routines for sending and receiving MIDI\r
* messages, and handles running status in both directions.\r
* MIDI 1.0 Detailed Specification Document Version 4.2\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
-\r
-#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
-\r
#include "USBFS_midi.h"\r
#include "USBFS_pvt.h"\r
\r
\r
+#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
\r
/***************************************\r
* MIDI Constants\r
* Global variables\r
***************************************/\r
\r
+\r
#if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
#if (USBFS_MIDI_IN_BUFF_SIZE >= 256)\r
+ /** Input endpoint buffer pointer. This pointer is used as an index for the\r
+ * USBMIDI_midiInBuffer to write data. It is cleared to zero by the\r
+ * USBMIDI_MIDI_EP_Init() function.*/\r
volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */\r
#else\r
volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */\r
#endif /* (USBFS_MIDI_IN_BUFF_SIZE >= 256) */\r
- volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */\r
+ /** Contains the midi IN endpoint number, It is initialized after a\r
+ * SET_CONFIGURATION request based on a user descriptor. It is used in MIDI\r
+ * APIs to send data to the host.*/\r
+ volatile uint8 USBFS_midi_in_ep;\r
+ /** Input endpoint buffer with a length equal to MIDI IN EP Max Packet Size.\r
+ * This buffer is used to save and combine the data received from the UARTs,\r
+ * generated internally by USBMIDI_PutUsbMidiIn() function messages, or both.\r
+ * The USBMIDI_MIDI_IN_Service() function transfers the data from this buffer to the host.*/\r
uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */\r
#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
\r
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
+ /** Contains the midi OUT endpoint number. It is initialized after a\r
+ * SET_CONFIGURATION request based on a user descriptor. It is used in\r
+ * MIDI APIs to receive data from the host.*/\r
volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */\r
+ /** Output endpoint buffer with a length equal to MIDI OUT EP Max Packet Size.\r
+ * This buffer is used by the USBMIDI_MIDI_OUT_EP_Service() function to save\r
+ * the data received from the host. The received data is then parsed. The\r
+ * parsed data is transferred to the UARTs buffer and also used for internal\r
+ * processing by the USBMIDI_callbackLocalMidiEvent() function.*/\r
uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */\r
#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
+\r
static USBFS_MIDI_RX_STATUS USBFS_MIDI1_Event; /* MIDI RX status structure */\r
static volatile uint8 USBFS_MIDI1_TxRunStat; /* MIDI Output running status */\r
+ /** The USBFS supports a maximum of two external Jacks. The two flag variables\r
+ * are used to represent the status of two external Jacks. These optional variables\r
+ * are allocated when External Mode is enabled. The following flags help to\r
+ * detect and generate responses for SysEx messages. The USBMIDI_MIDI2_InqFlags\r
+ * is optional and is not available when only one external Jack is configured.\r
+ * Flag | Description\r
+ * ------------------------------|---------------------------------------\r
+ * USBMIDI_INQ_SYSEX_FLAG | Non-real-time SysEx message received.\r
+ * USBMIDI_INQ_IDENTITY_REQ_FLAG | Identity Request received. You should clear this bit when an Identity Reply message is generated.\r
+ * SysEX messages are intended for local device and shouldn't go out on the\r
+ * external MIDI jack, this flag indicates when a MIDI SysEx OUT message is\r
+ * in progress for the application */\r
volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
static USBFS_MIDI_RX_STATUS USBFS_MIDI2_Event; /* MIDI RX status structure */\r
static volatile uint8 USBFS_MIDI2_TxRunStat; /* MIDI Output running status */\r
+ /** See description of \ref USBFS_MIDI1_InqFlags*/\r
volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */\r
#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
/* `#END` */\r
\r
\r
-/***************************************\r
-* Optional MIDI APIs\r
-***************************************/\r
#if (USBFS_ENABLE_MIDI_API != 0u)\r
-\r
-\r
/*******************************************************************************\r
-* Function Name: USBFS_MIDI_EP_Init\r
-********************************************************************************\r
+* Function Name: USBFS_MIDI_Init\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function initializes the MIDI interface and UART(s) to be ready to\r
* receive data from the PC and MIDI ports.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
+* \globalvars\r
*\r
-* Global variables:\r
-* USBFS_midiInBuffer: This buffer is used for saving and combining\r
+* \ref USBFS_midiInBuffer: This buffer is used for saving and combining\r
* the received data from UART(s) and(or) generated internally by\r
* PutUsbMidiIn() function messages. USBFS_MIDI_IN_EP_Service()\r
* function transfers the data from this buffer to the PC.\r
-* USBFS_midiOutBuffer: This buffer is used by the\r
-* USBFS_MIDI_OUT_EP_Service() function for saving the received\r
+*\r
+* \ref USBFS_midiOutBuffer: This buffer is used by the\r
+* USBFS_MIDI_OUT_Service() function for saving the received\r
* from the PC data, then the data are parsed and transferred to UART(s)\r
* buffer and to the internal processing by the\r
-* USBFS_callbackLocalMidiEvent function.\r
-* USBFS_midi_out_ep: Used as an OUT endpoint number.\r
-* USBFS_midi_in_ep: Used as an IN endpoint number.\r
-* USBFS_midiInPointer: Initialized to zero.\r
*\r
-* Reentrant:\r
+* \ref USBFS_callbackLocalMidiEvent function.\r
+*\r
+* \ref USBFS_midi_out_ep: Used as an OUT endpoint number.\r
+*\r
+* \ref USBFS_midi_in_ep: Used as an IN endpoint number.\r
+*\r
+* \ref USBFS_midiInPointer: Initialized to zero.\r
+*\r
+* \sideeffect\r
+* The priority of the UART RX ISR should be higher than UART TX ISR. To do\r
+* that this function changes the priority of the UARTs TX and RX interrupts.\r
+*\r
+* \reentrant\r
* No\r
*\r
*******************************************************************************/\r
-void USBFS_MIDI_EP_Init(void) \r
+void USBFS_MIDI_Init(void) \r
{\r
+#if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
+ USBFS_midiInPointer = 0u;\r
+#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
#if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
- USBFS_midiInPointer = 0u;\r
- #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
-\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- #if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
- /* Init DMA configurations for IN EP*/\r
- USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer,\r
- USBFS_MIDI_IN_BUFF_SIZE);\r
-\r
- #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
- #if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
- /* Init DMA configurations for OUT EP*/\r
- (void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer,\r
- USBFS_MIDI_OUT_BUFF_SIZE);\r
- #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
- #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */\r
+ /* Provide buffer for IN endpoint. */\r
+ USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer,\r
+ USBFS_MIDI_IN_BUFF_SIZE);\r
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
\r
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
- USBFS_EnableOutEP(USBFS_midi_out_ep);\r
+ /* Provide buffer for OUT endpoint. */\r
+ (void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer,\r
+ USBFS_MIDI_OUT_BUFF_SIZE);\r
#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+\r
+#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
+ USBFS_EnableOutEP(USBFS_midi_out_ep);\r
+#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
\r
/* Initialize the MIDI port(s) */\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
- USBFS_MIDI_Init();\r
- #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
+#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
+ USBFS_MIDI_InitInterface();\r
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
}\r
\r
-#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
-\r
\r
+#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
/*******************************************************************************\r
- * Function Name: USBFS_MIDI_OUT_EP_Service\r
- ********************************************************************************\r
+ * Function Name: USBFS_MIDI_OUT_Service\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
- * Services the USB MIDI OUT endpoints.\r
- * This function is called from OUT EP ISR. It transfers the received from PC\r
- * data to the external MIDI port(UART TX buffer) and calls the\r
- * USBFS_callbackLocalMidiEvent() function to internal process\r
- * of the MIDI data.\r
- * This function is blocked by UART, if not enough space is available in UART\r
- * TX buffer. Therefore it is recommended to use large UART TX buffer size.\r
+ * This function services the traffic from the USBMIDI OUT endpoint and\r
+ * sends the data to the MIDI output ports (TX UARTs). It is blocked by the\r
+ * UART when not enough space is available in the UART TX buffer.\r
+ * This function is automatically called from OUT EP ISR in DMA with\r
+ * Automatic Memory Management mode. In Manual and DMA with Manual EP\r
+ * Management modes you must call it from the main foreground task.\r
*\r
- * Parameters:\r
- * None\r
+ * \globalvars\r
*\r
- * Return:\r
- * None\r
+ * \ref USBFS_midiOutBuffer: Used as temporary buffer between USB\r
+ * internal memory and UART TX buffer.\r
*\r
- * Global variables:\r
- * USBFS_midiOutBuffer: Used as temporary buffer between USB internal\r
- * memory and UART TX buffer.\r
- * USBFS_midi_out_ep: Used as an OUT endpoint number.\r
+ * \ref USBFS_midi_out_ep: Used as an OUT endpoint number.\r
*\r
- * Reentrant:\r
+ * \reentrant\r
* No\r
*\r
*******************************************************************************/\r
- void USBFS_MIDI_OUT_EP_Service(void) \r
+ void USBFS_MIDI_OUT_Service(void) \r
{\r
- #if USBFS_MIDI_OUT_BUFF_SIZE >= 256\r
- uint16 outLength;\r
- uint16 outPointer;\r
- #else\r
- uint8 outLength;\r
- uint8 outPointer;\r
- #endif /* USBFS_MIDI_OUT_BUFF_SIZE >=256 */\r
-\r
- uint8 dmaState = 0u;\r
+ #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256)\r
+ uint16 outLength;\r
+ uint16 outPointer;\r
+ #else\r
+ uint8 outLength;\r
+ uint8 outPointer;\r
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */\r
\r
- /* Service the USB MIDI output endpoint */\r
- if (USBFS_GetEPState(USBFS_midi_out_ep) == USBFS_OUT_BUFFER_FULL)\r
+ /* Service the USB MIDI output endpoint. */\r
+ if (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(USBFS_midi_out_ep))\r
{\r
- #if(USBFS_MIDI_OUT_BUFF_SIZE >= 256)\r
- outLength = USBFS_GetEPCount(USBFS_midi_out_ep);\r
+ #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256)\r
+ outLength = USBFS_GetEPCount(USBFS_midi_out_ep);\r
+ #else\r
+ outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep);\r
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */\r
+\r
+ #if (!USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256)\r
+ outLength = USBFS_ReadOutEP(USBFS_midi_out_ep,\r
+ USBFS_midiOutBuffer, outLength);\r
#else\r
- outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep);\r
+ outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep,\r
+ USBFS_midiOutBuffer, (uint16) outLength);\r
#endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */\r
\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256)\r
- outLength = USBFS_ReadOutEP(USBFS_midi_out_ep,\r
- USBFS_midiOutBuffer, outLength);\r
- #else\r
- outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep,\r
- USBFS_midiOutBuffer, (uint16)outLength);\r
- #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */\r
-\r
- #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
- do /* wait for DMA transfer complete */\r
- {\r
- (void) CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);\r
- }\r
- while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);\r
- #endif /* (USBFS_EP_MM == USBFS__EP_DMAMANUAL) */\r
-\r
- #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */\r
+ #if (USBFS_EP_MANAGEMENT_DMA_MANUAL)\r
+ /* Wait until DMA complete transferring data from OUT endpoint buffer. */\r
+ while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(USBFS_midi_out_ep))\r
+ {\r
+ }\r
\r
- if(dmaState != 0u)\r
- {\r
- /* Suppress compiler warning */\r
- }\r
+ /* Enable OUT endpoint for communication with host. */\r
+ USBFS_EnableOutEP(USBFS_midi_out_ep);\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */\r
+ #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
\r
if (outLength >= USBFS_EVENT_LENGTH)\r
{\r
outPointer = 0u;\r
while (outPointer < outLength)\r
{\r
- /* In some OS OUT packet could be appended by nulls which could be skipped */\r
+ /* In some OS OUT packet could be appended by nulls which could be skipped. */\r
if (USBFS_midiOutBuffer[outPointer] == 0u)\r
{\r
break;\r
}\r
- /* Route USB MIDI to the External connection */\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
- if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) ==\r
- USBFS_MIDI_CABLE_00)\r
- {\r
- USBFS_MIDI1_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]);\r
- }\r
- else if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) ==\r
- USBFS_MIDI_CABLE_01)\r
- {\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]);\r
- #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
- }\r
- else\r
- {\r
- /* `#START CUSTOM_MIDI_OUT_EP_SERV` Place your code here */\r
+\r
+ /* Route USB MIDI to the External connection */\r
+ #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
+ if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) ==\r
+ USBFS_MIDI_CABLE_00)\r
+ {\r
+ USBFS_MIDI1_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]);\r
+ }\r
+ else if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) ==\r
+ USBFS_MIDI_CABLE_01)\r
+ {\r
+ #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
+ USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]);\r
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
+ }\r
+ else\r
+ {\r
+ /* `#START CUSTOM_MIDI_OUT_EP_SERV` Place your code here */\r
- /* `#END` */\r
+ /* `#END` */\r
\r
- #ifdef USBFS_MIDI_OUT_EP_SERVICE_CALLBACK\r
- USBFS_MIDI_OUT_EP_Service_Callback();\r
- #endif /* USBFS_MIDI_OUT_EP_SERVICE_CALLBACK */\r
- }\r
- #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
+ #ifdef USBFS_MIDI_OUT_EP_SERVICE_CALLBACK\r
+ USBFS_MIDI_OUT_EP_Service_Callback();\r
+ #endif /* USBFS_MIDI_OUT_EP_SERVICE_CALLBACK */\r
+ }\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
/* Process any local MIDI output functions */\r
- USBFS_callbackLocalMidiEvent(\r
- USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK,\r
- &USBFS_midiOutBuffer[outPointer + USBFS_EVENT_BYTE1]);\r
+ USBFS_callbackLocalMidiEvent(USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK,\r
+ &USBFS_midiOutBuffer[outPointer + USBFS_EVENT_BYTE1]);\r
outPointer += USBFS_EVENT_LENGTH;\r
}\r
}\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- /* Enable Out EP*/\r
- USBFS_EnableOutEP(USBFS_midi_out_ep);\r
- #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Enable OUT endpoint for communiation. */\r
+ USBFS_EnableOutEP(USBFS_midi_out_ep);\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
}\r
}\r
+#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
\r
-#endif /* #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
\r
#if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
-\r
-\r
/*******************************************************************************\r
* Function Name: USBFS_MIDI_IN_EP_Service\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Services the USB MIDI IN endpoint. Non-blocking.\r
* Checks that previous packet was processed by HOST, otherwise service the\r
* input endpoint on the subsequent call. It is called from the\r
* USBFS_MIDI_IN_Service() and from the\r
* USBFS_PutUsbMidiIn() function.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Global variables:\r
+ * \globalvars\r
* USBFS_midi_in_ep: Used as an IN endpoint number.\r
* USBFS_midiInBuffer: Function loads the data from this buffer to\r
* the USB IN endpoint.\r
* USBFS_midiInPointer: Cleared to zero when data are sent.\r
*\r
- * Reentrant:\r
+ * \reentrant\r
* No\r
*\r
*******************************************************************************/\r
{\r
if(USBFS_GetEPState(USBFS_midi_in_ep) == USBFS_EVENT_PENDING)\r
{\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer,\r
- (uint16)USBFS_midiInPointer);\r
- #else /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
- /* rearm IN EP */\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
USBFS_LoadInEP(USBFS_midi_in_ep, NULL, (uint16)USBFS_midiInPointer);\r
- #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */\r
+ #else\r
+ USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer,\r
+ (uint16) USBFS_midiInPointer);\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
\r
/* Clear the midiInPointer. For DMA mode, clear this pointer in the ARB ISR when data are moved by DMA */\r
- #if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
+ #if (USBFS_EP_MANAGEMENT_MANUAL)\r
USBFS_midiInPointer = 0u;\r
- #endif /* (USBFS_EP_MM == USBFS__EP_MANUAL) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */\r
}\r
}\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_MIDI_IN_Service\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
- * Services the traffic from the MIDI input ports (RX UART) and prepare data\r
- * in USB MIDI IN endpoint buffer.\r
+ * This function services the traffic from the MIDI input ports (RX UART)\r
+ * and prepare data in USB MIDI IN endpoint buffer.\r
* Calls the USBFS_MIDI_IN_EP_Service() function to sent the\r
* data from buffer to PC. Non-blocking. Should be called from main foreground\r
* task.\r
* This function is not protected from the reentrant calls. When it is required\r
* to use this function in UART RX ISR to guaranty low latency, care should be\r
* taken to protect from reentrant calls.\r
+ * In PSoC 3, if this function is called from an ISR, you must declare this\r
+ * function as re-entrant so that different variable storage space is\r
+ * created by the compiler. This is automatically taken care for PSoC 4 and\r
+ * PSoC 5LP devices by the compiler.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
+ * \globalvars\r
*\r
- * Global variables:\r
* USBFS_midiInPointer: Cleared to zero when data are sent.\r
*\r
- * Reentrant:\r
+ * \reentrant\r
* No\r
*\r
*******************************************************************************/\r
/* Service the MIDI UART inputs until either both receivers have no more\r
* events or until the input endpoint buffer fills up.\r
*/\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
+ #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
uint8 m1 = 0u;\r
uint8 m2 = 0u;\r
+\r
+ if (0u == USBFS_midiInPointer)\r
+ {\r
do\r
{\r
- if (USBFS_midiInPointer <=\r
- (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
+ if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
{\r
/* Check MIDI1 input port for a complete event */\r
m1 = USBFS_MIDI1_GetEvent();\r
if (m1 != 0u)\r
{\r
USBFS_PrepareInBuffer(m1, (uint8 *)&USBFS_MIDI1_Event.msgBuff[0],\r
- USBFS_MIDI1_Event.size, USBFS_MIDI_CABLE_00);\r
+ USBFS_MIDI1_Event.size, USBFS_MIDI_CABLE_00);\r
}\r
}\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- if (USBFS_midiInPointer <=\r
- (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
+ if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
{\r
/* Check MIDI2 input port for a complete event */\r
m2 = USBFS_MIDI2_GetEvent();\r
if (m2 != 0u)\r
{\r
USBFS_PrepareInBuffer(m2, (uint8 *)&USBFS_MIDI2_Event.msgBuff[0],\r
- USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01);\r
+ USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01);\r
}\r
}\r
#endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
-\r
- }while( (USBFS_midiInPointer <=\r
- (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) &&\r
- ((m1 != 0u) || (m2 != 0u)) );\r
- #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
+ }\r
+ while((USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) &&\r
+ ((m1 != 0u) || (m2 != 0u)));\r
+ }\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
/* Service the USB MIDI input endpoint */\r
USBFS_MIDI_IN_EP_Service();\r
}\r
\r
\r
- /*******************************************************************************\r
+ /***************************************************************************\r
* Function Name: USBFS_PutUsbMidiIn\r
- ********************************************************************************\r
+ ************************************************************************//**\r
*\r
- * Summary:\r
- * Puts one MIDI messages into the USB MIDI In endpoint buffer. These are\r
- * MIDI input messages to the host. This function is only used if the device\r
- * has internal MIDI input functionality. USBMIDI_MIDI_IN_Service() function\r
- * should additionally be called to send the message from local buffer to\r
- * IN endpoint.\r
+ * This function puts one MIDI message into the USB MIDI In endpoint buffer.\r
+ * This is a MIDI input message to the host. This function is used only if\r
+ * the device has internal MIDI input functionality.\r
+ * The USBFS_MIDI_IN_Service() function should also be called to\r
+ * send the message from local buffer to the IN endpoint.\r
*\r
- * Parameters:\r
- * ic: 0 = No message (should never happen)\r
- * 1 - 3 = Complete MIDI message in midiMsg\r
- * 3 - IN EP LENGTH = Complete SySEx message(without EOSEX byte) in\r
- * midiMsg. The length is limited by the max BULK EP size(64)\r
- * MIDI_SYSEX = Start or continuation of SysEx message\r
- * (put event bytes in midiMsg buffer)\r
- * MIDI_EOSEX = End of SysEx message\r
- * (put event bytes in midiMsg buffer)\r
- * MIDI_TUNEREQ = Tune Request message (single byte system common msg)\r
- * 0xf8 - 0xff = Single byte real-time message\r
- * midiMsg: pointer to MIDI message.\r
- * cable: cable number.\r
+ * \param ic: The length of the MIDI message or command is described on the\r
+ * following table.\r
+ * Value | Description\r
+ * ---------------|---------------------------------------------------------\r
+ * 0 | No message (should never happen)\r
+ * 1 - 3 | Complete MIDI message in midiMsg\r
+ * 3 IN EP LENGTH | Complete SySEx message(without EOSEX byte) in midiMsg. The length is limited by the max BULK EP size(64)\r
+ * MIDI_SYSEX | Start or continuation of SysEx message (put event bytes in midiMsg buffer)\r
+ * MIDI_EOSEX | End of SysEx message (put event bytes in midiMsg buffer)\r
+ * MIDI_TUNEREQ | Tune Request message (single byte system common msg)\r
+ * 0xF8 - 0xFF | Single byte real-time message\r
*\r
- * Return:\r
- * USBFS_TRUE if error.\r
- * USBFS_FALSE if success.\r
+ * \param midiMsg: pointer to MIDI message.\r
+ * \param cable: cable number.\r
*\r
- * Global variables:\r
- * USBFS_midi_in_ep: MIDI IN endpoint number used for sending data.\r
- * USBFS_midiInPointer: Checked this variable to see if there is\r
- * enough free space in the IN endpoint buffer. If buffer is full, initiate\r
- * sending to PC.\r
+ * \return\r
+ * Return Value | Description\r
+ * ----------------------|-----------------------------------------\r
+ * USBFS_TRUE | Host is not ready to receive this message\r
+ * USBFS_FALSE | Success transfer\r
*\r
- * Reentrant:\r
+ * \globalvars\r
+ *\r
+ * \ref USBFS_midi_in_ep: MIDI IN endpoint number used for\r
+ * sending data.\r
+ *\r
+ * \ref USBFS_midiInPointer: Checked this variable to see if\r
+ * there is enough free space in the IN endpoint buffer. If buffer is\r
+ * full, initiate sending to PC.\r
+ *\r
+ * \reentrant\r
* No\r
*\r
- *******************************************************************************/\r
+ ***************************************************************************/\r
uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable)\r
\r
{\r
uint8 msgIndex;\r
\r
/* Protect PrepareInBuffer() function from concurrent calls */\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
- MIDI1_UART_DisableRxInt();\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- MIDI2_UART_DisableRxInt();\r
- #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
- #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
+ #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
+ MIDI1_UART_DisableRxInt();\r
+ #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
+ MIDI2_UART_DisableRxInt();\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
if (USBFS_midiInPointer >\r
(USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
{\r
USBFS_MIDI_IN_EP_Service();\r
}\r
+\r
if (USBFS_midiInPointer <=\r
(USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
{\r
USBFS_PrepareInBuffer(ic, midiMsg, ic, cable);\r
}\r
else\r
- { /* Only SysEx message is greater than 4 bytes */\r
+ {\r
+ /* Only SysEx message is greater than 4 bytes */\r
msgIndex = 0u;\r
+\r
do\r
{\r
USBFS_PrepareInBuffer(USBFS_MIDI_SYSEX, &midiMsg[msgIndex],\r
USBFS_EVENT_BYTE3, cable);\r
+\r
ic -= USBFS_EVENT_BYTE3;\r
msgIndex += USBFS_EVENT_BYTE3;\r
+\r
if (USBFS_midiInPointer >\r
(USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
{\r
USBFS_MIDI_IN_EP_Service();\r
- if(USBFS_midiInPointer >\r
- (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
+\r
+ if (USBFS_midiInPointer >\r
+ (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
{\r
/* Error condition. HOST is not ready to receive this packet. */\r
retError = USBFS_TRUE;\r
}\r
}\r
}\r
- while(ic > USBFS_EVENT_BYTE3);\r
+ while (ic > USBFS_EVENT_BYTE3);\r
\r
- if(retError == USBFS_FALSE)\r
+ if (retError == USBFS_FALSE)\r
{\r
USBFS_PrepareInBuffer(USBFS_MIDI_EOSEX, midiMsg, ic, cable);\r
}\r
retError = USBFS_TRUE;\r
}\r
\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
- MIDI1_UART_EnableRxInt();\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- MIDI2_UART_EnableRxInt();\r
- #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
- #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
+ #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
+ MIDI1_UART_EnableRxInt();\r
+ #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
+ MIDI2_UART_EnableRxInt();\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
return (retError);\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_PrepareInBuffer\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Builds a USB MIDI event in the input endpoint buffer at the current pointer.\r
* Puts one MIDI message into the USB MIDI In endpoint buffer.\r
*\r
- * Parameters:\r
- * ic: 0 = No message (should never happen)\r
+ * \param ic: 0 = No message (should never happen)\r
* 1 - 3 = Complete MIDI message at pMdat[0]\r
* MIDI_SYSEX = Start or continuation of SysEx message\r
* (put eventLen bytes in buffer)\r
* MIDI_TUNEREQ = Tune Request message (single byte system common msg)\r
* 0xf8 - 0xff = Single byte real-time message\r
*\r
- * srcBuff: pointer to MIDI data\r
- * eventLen: number of bytes in MIDI event\r
- * cable: MIDI source port number\r
- *\r
- * Return:\r
- * None\r
+ * \param srcBuff: pointer to MIDI data\r
+ * \param eventLen: number of bytes in MIDI event\r
+ * \param cable: MIDI source port number\r
*\r
- * Global variables:\r
+ * \globalvars\r
* USBFS_midiInBuffer: This buffer is used for saving and combine the\r
* received from UART(s) and(or) generated internally by\r
* USBFS_PutUsbMidiIn() function messages.\r
* USBFS_midiInPointer: Used as an index for midiInBuffer to\r
* write data.\r
*\r
- * Reentrant:\r
+ * \reentrant\r
* No\r
*\r
*******************************************************************************/\r
}\r
}\r
\r
-#endif /* #if (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
+#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
\r
\r
/* The implementation for external serial input and output connections\r
* to route USB MIDI data to and from those connections.\r
*/\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
-\r
-\r
/*******************************************************************************\r
- * Function Name: USBFS_MIDI_Init\r
- ********************************************************************************\r
+ * Function Name: USBFS_MIDI_InitInterface\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Initializes MIDI variables and starts the UART(s) hardware block(s).\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Side Effects:\r
+ * \sideeffect\r
* Change the priority of the UART(s) TX interrupts to be higher than the\r
* default EP ISR priority.\r
*\r
- * Global variables:\r
+ * \globalvars\r
* USBFS_MIDI_Event: initialized to zero.\r
* USBFS_MIDI_TxRunStat: initialized to zero.\r
*\r
*******************************************************************************/\r
- void USBFS_MIDI_Init(void) \r
+ void USBFS_MIDI_InitInterface(void) \r
{\r
- USBFS_MIDI1_Event.length = 0u;\r
- USBFS_MIDI1_Event.count = 0u;\r
- USBFS_MIDI1_Event.size = 0u;\r
+ USBFS_MIDI1_Event.length = 0u;\r
+ USBFS_MIDI1_Event.count = 0u;\r
+ USBFS_MIDI1_Event.size = 0u;\r
USBFS_MIDI1_Event.runstat = 0u;\r
- USBFS_MIDI1_TxRunStat = 0u;\r
- USBFS_MIDI1_InqFlags = 0u;\r
+ USBFS_MIDI1_TxRunStat = 0u;\r
+ USBFS_MIDI1_InqFlags = 0u;\r
+\r
/* Start UART block */\r
MIDI1_UART_Start();\r
+\r
/* Change the priority of the UART TX and RX interrupt */\r
CyIntSetPriority(MIDI1_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM);\r
CyIntSetPriority(MIDI1_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM);\r
\r
- #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- USBFS_MIDI2_Event.length = 0u;\r
- USBFS_MIDI2_Event.count = 0u;\r
- USBFS_MIDI2_Event.size = 0u;\r
- USBFS_MIDI2_Event.runstat = 0u;\r
- USBFS_MIDI2_TxRunStat = 0u;\r
- USBFS_MIDI2_InqFlags = 0u;\r
- /* Start second UART block */\r
- MIDI2_UART_Start();\r
- /* Change the priority of the UART TX interrupt */\r
- CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM);\r
- CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM);\r
- #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/\r
+ #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
+ USBFS_MIDI2_Event.length = 0u;\r
+ USBFS_MIDI2_Event.count = 0u;\r
+ USBFS_MIDI2_Event.size = 0u;\r
+ USBFS_MIDI2_Event.runstat = 0u;\r
+ USBFS_MIDI2_TxRunStat = 0u;\r
+ USBFS_MIDI2_InqFlags = 0u;\r
+\r
+ /* Start second UART block */\r
+ MIDI2_UART_Start();\r
+\r
+ /* Change the priority of the UART TX interrupt */\r
+ CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM);\r
+ CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM);\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
\r
/* `#START MIDI_INIT_CUSTOM` Init other extended UARTs here */\r
/* `#END` */\r
\r
- #ifdef USBFS_MIDI_INIT_CALLBACK\r
- USBFS_MIDI_Init_Callback();\r
- #endif /* USBFS_MIDI_INIT_CALLBACK */\r
+ #ifdef USBFS_MIDI_INIT_CALLBACK\r
+ USBFS_MIDI_Init_Callback();\r
+ #endif /* (USBFS_MIDI_INIT_CALLBACK) */\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ProcessMidiIn\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Processes one byte of incoming MIDI data.\r
*\r
- * Parameters:\r
* mData = current MIDI input data byte\r
* *rxStat = pointer to a MIDI_RX_STATUS structure\r
*\r
- * Return:\r
+ * \return\r
* 0, if no complete message\r
* 1 - 4, if message complete\r
* MIDI_SYSEX, if start or continuation of system exclusive\r
break;\r
case USBFS_MIDI_PROGRAM_CHANGE:\r
case USBFS_MIDI_CHANNEL_PRESSURE:\r
- rxStat->size =rxStat->count;\r
+ rxStat->size = rxStat->count;\r
rxStat->count = 0u;\r
midiReturn = rxStat->size;\r
break;\r
\r
/*******************************************************************************\r
* Function Name: USBFS_MIDI1_GetEvent\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Checks for incoming MIDI data, calls the MIDI event builder if so.\r
* Returns either empty or with a complete event.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
+ * \return\r
* 0, if no complete message\r
* 1 - 4, if message complete\r
* MIDI_SYSEX, if start or continuation of system exclusive\r
* MIDI_EOSEX, if end of system exclusive\r
* 0xf8 - 0xff, if single byte real time message\r
*\r
- * Global variables:\r
+ * \globalvars\r
* USBFS_MIDI1_Event: RX status structure used to parse received\r
* data.\r
*\r
/* Read buffer loop condition to the local variable */\r
rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect;\r
\r
- if ( (MIDI1_UART_rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u) )\r
+ if ((MIDI1_UART_rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u))\r
{\r
/* Protect variables that could change on interrupt by disabling Rx interrupt.*/\r
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
#endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+\r
rxBufferRead = MIDI1_UART_rxBufferRead;\r
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
rxBufferWrite = MIDI1_UART_rxBufferWrite;\r
rxData = MIDI1_UART_rxBuffer[rxBufferRead];\r
/* Increment pointer with a wrap */\r
rxBufferRead++;\r
- if(rxBufferRead >= MIDI1_UART_RXBUFFERSIZE)\r
+ if (rxBufferRead >= MIDI1_UART_RXBUFFERSIZE)\r
{\r
rxBufferRead = 0u;\r
}\r
+\r
/* If loop condition was set - update real read buffer pointer\r
* to avoid overflow status\r
*/\r
- if(rxBufferLoopDetect != 0u )\r
+ if (rxBufferLoopDetect != 0u )\r
{\r
MIDI1_UART_rxBufferLoopDetect = 0u;\r
- #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
+ CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
+ #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+\r
MIDI1_UART_rxBufferRead = rxBufferRead;\r
- #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntEnable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
+ CyIntEnable(MIDI1_UART_RX_VECT_NUM);\r
+ #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */\r
}\r
\r
msgRtn = USBFS_ProcessMidiIn(rxData,\r
/* Finally, update the real output pointer, then return with\r
* an indication as to whether there's a complete message in the buffer.\r
*/\r
- #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
- MIDI1_UART_rxBufferRead = rxBufferRead;\r
- #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntEnable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+ #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
+ CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+\r
+ MIDI1_UART_rxBufferRead = rxBufferRead;\r
+ #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
+ CyIntEnable(MIDI1_UART_RX_VECT_NUM);\r
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
}\r
\r
return (msgRtn);\r
\r
/*******************************************************************************\r
* Function Name: USBFS_MIDI1_ProcessUsbOut\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Process a USB MIDI output event.\r
* Puts data into the MIDI TX output buffer.\r
*\r
- * Parameters:\r
- * *epBuf: pointer on MIDI event.\r
+ * \param *epBuf: pointer on MIDI event.\r
*\r
- * Return:\r
- * None\r
- *\r
- * Global variables:\r
+ * \globalvars\r
* USBFS_MIDI1_TxRunStat: This variable used to save the MIDI\r
* status byte and skip to send the repeated status byte in subsequent event.\r
* USBFS_MIDI1_InqFlags: The following flags are set when SysEx\r
/* `#END` */\r
\r
- #ifdef USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK\r
- USBFS_MIDI1_ProcessUsbOut_EntryCallback();\r
- #endif /* USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK */\r
+ #ifdef USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK\r
+ USBFS_MIDI1_ProcessUsbOut_EntryCallback();\r
+ #endif /* (USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK) */\r
\r
cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK;\r
- if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1))\r
+\r
+ if ((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1))\r
{\r
len = USBFS_MIDI_SIZE[cmd];\r
i = USBFS_EVENT_BYTE1;\r
/* Universal System Exclusive message parsing */\r
- if(cmd == USBFS_SYSEX)\r
+ if (cmd == USBFS_SYSEX)\r
{\r
- if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) &&\r
- (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME))\r
- { /* Non-Real Time SySEx starts */\r
+ if ((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) &&\r
+ (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME))\r
+ {\r
+ /* Non-Real Time SySEx starts */\r
USBFS_MIDI1_InqFlags |= USBFS_INQ_SYSEX_FLAG;\r
}\r
else\r
USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG;\r
}\r
}\r
- else if(cmd == USBFS_SYSEX_ENDS_WITH1)\r
+ else if (cmd == USBFS_SYSEX_ENDS_WITH1)\r
{\r
USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG;\r
}\r
- else if(cmd == USBFS_SYSEX_ENDS_WITH2)\r
+ else if (cmd == USBFS_SYSEX_ENDS_WITH2)\r
{\r
USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG;\r
}\r
- else if(cmd == USBFS_SYSEX_ENDS_WITH3)\r
+ else if (cmd == USBFS_SYSEX_ENDS_WITH3)\r
{\r
/* Identify Request support */\r
- if((USBFS_MIDI1_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u)\r
+ if ((USBFS_MIDI1_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u)\r
{\r
USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG;\r
- if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) &&\r
- (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ))\r
- { /* Set the flag about received the Identity Request.\r
+ if ((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) &&\r
+ (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ))\r
+ {\r
+ /* Set the flag about received the Identity Request.\r
* The Identity Reply message may be send by user code.\r
*/\r
USBFS_MIDI1_InqFlags |= USBFS_INQ_IDENTITY_REQ_FLAG;\r
else /* Do nothing for other command */\r
{\r
}\r
+\r
/* Running Status for Voice and Mode messages only. */\r
- if((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE))\r
+ if ((cmd >= USBFS_NOTE_OFF) && (cmd <= USBFS_PITCH_BEND_CHANGE))\r
{\r
- if(USBFS_MIDI1_TxRunStat == epBuf[USBFS_EVENT_BYTE1])\r
- { /* Skip the repeated Status byte */\r
+ if (USBFS_MIDI1_TxRunStat == epBuf[USBFS_EVENT_BYTE1])\r
+ {\r
+ /* Skip the repeated Status byte */\r
i++;\r
}\r
else\r
- { /* Save Status byte for next event */\r
+ {\r
+ /* Save Status byte for next event */\r
USBFS_MIDI1_TxRunStat = epBuf[USBFS_EVENT_BYTE1];\r
}\r
}\r
else\r
- { /* Clear Running Status */\r
+ {\r
+ /* Clear Running Status */\r
USBFS_MIDI1_TxRunStat = 0u;\r
}\r
+\r
/* Puts data into the MIDI TX output buffer.*/\r
do\r
{\r
MIDI1_UART_PutChar(epBuf[i]);\r
i++;\r
- } while (i <= len);\r
+ }\r
+ while (i <= len);\r
}\r
\r
/* User code is required at the end of the procedure */\r
/* `#END` */\r
\r
- #ifdef USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK\r
- USBFS_MIDI1_ProcessUsbOut_ExitCallback();\r
- #endif /* USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK */\r
+ #ifdef USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK\r
+ USBFS_MIDI1_ProcessUsbOut_ExitCallback();\r
+ #endif /* (USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK) */\r
}\r
\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
-\r
-\r
/*******************************************************************************\r
* Function Name: USBFS_MIDI2_GetEvent\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Checks for incoming MIDI data, calls the MIDI event builder if so.\r
* Returns either empty or with a complete event.\r
*\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
+ * \return\r
* 0, if no complete message\r
* 1 - 4, if message complete\r
* MIDI_SYSEX, if start or continuation of system exclusive\r
* MIDI_EOSEX, if end of system exclusive\r
* 0xf8 - 0xff, if single byte real time message\r
*\r
- * Global variables:\r
+ * \globalvars\r
* USBFS_MIDI2_Event: RX status structure used to parse received\r
* data.\r
*\r
{\r
uint8 msgRtn = 0u;\r
uint8 rxData;\r
+\r
#if (MIDI2_UART_RXBUFFERSIZE >= 256u)\r
uint16 rxBufferRead;\r
#if (CY_PSOC3) /* This local variable required only for PSOC3 and large buffer */\r
{\r
rxBufferRead = 0u;\r
}\r
+\r
/* If loop condition was set - update real read buffer pointer\r
* to avoid overflow status\r
*/\r
- if(rxBufferLoopDetect != 0u )\r
+ if (rxBufferLoopDetect != 0u)\r
{\r
MIDI2_UART_rxBufferLoopDetect = 0u;\r
- #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntDisable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+ #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
+ CyIntDisable(MIDI2_UART_RX_VECT_NUM);\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+\r
MIDI2_UART_rxBufferRead = rxBufferRead;\r
- #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntEnable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+ #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
+ CyIntEnable(MIDI2_UART_RX_VECT_NUM);\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
}\r
\r
msgRtn = USBFS_ProcessMidiIn(rxData,\r
/* Finally, update the real output pointer, then return with\r
* an indication as to whether there's a complete message in the buffer.\r
*/\r
- #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntDisable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+ #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
+ CyIntDisable(MIDI2_UART_RX_VECT_NUM);\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+\r
MIDI2_UART_rxBufferRead = rxBufferRead;\r
- #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntEnable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
+ #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
+ CyIntEnable(MIDI2_UART_RX_VECT_NUM);\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
}\r
\r
return (msgRtn);\r
\r
/*******************************************************************************\r
* Function Name: USBFS_MIDI2_ProcessUsbOut\r
- ********************************************************************************\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* Process a USB MIDI output event.\r
* Puts data into the MIDI TX output buffer.\r
*\r
- * Parameters:\r
- * *epBuf: pointer on MIDI event.\r
- *\r
- * Return:\r
- * None\r
+ * \param *epBuf: pointer on MIDI event.\r
*\r
- * Global variables:\r
+ * \globalvars\r
* USBFS_MIDI2_TxRunStat: This variable used to save the MIDI\r
* status byte and skip to send the repeated status byte in subsequent event.\r
* USBFS_MIDI2_InqFlags: The following flags are set when SysEx\r
/* `#END` */\r
\r
- #ifdef USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK\r
- USBFS_MIDI2_ProcessUsbOut_EntryCallback();\r
- #endif /* USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK */\r
+ #ifdef USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK\r
+ USBFS_MIDI2_ProcessUsbOut_EntryCallback();\r
+ #endif /* (USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK) */\r
\r
cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK;\r
- if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1))\r
+\r
+ if ((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1))\r
{\r
len = USBFS_MIDI_SIZE[cmd];\r
i = USBFS_EVENT_BYTE1;\r
+\r
/* Universal System Exclusive message parsing */\r
if(cmd == USBFS_SYSEX)\r
{\r
if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) &&\r
(epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME))\r
- { /* SySEx starts */\r
+ {\r
+ /* SySEx starts */\r
USBFS_MIDI2_InqFlags |= USBFS_INQ_SYSEX_FLAG;\r
}\r
else\r
else if(cmd == USBFS_SYSEX_ENDS_WITH3)\r
{\r
/* Identify Request support */\r
- if((USBFS_MIDI2_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u)\r
+ if ((USBFS_MIDI2_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u)\r
{\r
USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG;\r
+\r
if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) &&\r
(epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ))\r
{ /* Set the flag about received the Identity Request.\r
else /* Do nothing for other command */\r
{\r
}\r
+\r
/* Running Status for Voice and Mode messages only. */\r
- if((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE))\r
+ if ((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE))\r
{\r
- if(USBFS_MIDI2_TxRunStat == epBuf[USBFS_EVENT_BYTE1])\r
+ if (USBFS_MIDI2_TxRunStat == epBuf[USBFS_EVENT_BYTE1])\r
{ /* Skip the repeated Status byte */\r
i++;\r
}\r
{ /* Clear Running Status */\r
USBFS_MIDI2_TxRunStat = 0u;\r
}\r
+\r
/* Puts data into the MIDI TX output buffer.*/\r
do\r
{\r
MIDI2_UART_PutChar(epBuf[i]);\r
i++;\r
- } while (i <= len);\r
+ }\r
+ while (i <= len);\r
}\r
\r
/* User code is required at the end of the procedure */\r
/* `#END` */\r
\r
- #ifdef USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK\r
- USBFS_MIDI2_ProcessUsbOut_ExitCallback();\r
- #endif /* USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK */\r
+ #ifdef USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK\r
+ USBFS_MIDI2_ProcessUsbOut_ExitCallback();\r
+ #endif /* (USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK) */\r
}\r
#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
/* `#END` */\r
\r
-#endif /* defined(USBFS_ENABLE_MIDI_STREAMING) */\r
+#endif /* defined(USBFS_ENABLE_MIDI_STREAMING) */\r
\r
\r
/* [] END OF FILE */\r
-/*******************************************************************************\r
-* File Name: USBFS_midi.h\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file USBFS_midi.h\r
+* \version 3.10\r
*\r
-* Description:\r
-* Header File for the USBFS MIDI module.\r
-* Contains prototypes and constant values.\r
+* \brief\r
+* This file provides function prototypes and constants for the USBFS component \r
+* MIDI class support.\r
*\r
* Related Document:\r
* Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0\r
* MIDI 1.0 Detailed Specification Document Version 4.2\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#if !defined(CY_USBFS_USBFS_midi_H)\r
#define CY_USBFS_USBFS_midi_H\r
\r
-#include "cytypes.h"\r
#include "USBFS.h"\r
\r
+/***************************************\r
+* Initial Parameter Constants\r
+***************************************/\r
+\r
+#define USBFS_ENABLE_MIDI_API (0u != (1u))\r
+#define USBFS_MIDI_EXT_MODE (0u)\r
+\r
+\r
+/* Number of external interfaces (UARTs). */\r
+#define USBFS_ONE_EXT_INTRF (0x01u)\r
+#define USBFS_TWO_EXT_INTRF (0x02u)\r
+ \r
+#define USBFS_ISR_SERVICE_MIDI_OUT \\r
+ ((USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_OUT_BUFF_SIZE > 0) && \\r
+ (USBFS_EP_MANAGEMENT_DMA_AUTO))\r
+\r
+#define USBFS_ISR_SERVICE_MIDI_IN \\r
+ ((USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0))\r
+\r
+\r
+/***************************************\r
+* External References\r
+***************************************/\r
+\r
+#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
+ #include "MIDI1_UART.h"\r
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
+\r
+#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
+ #include "MIDI2_UART.h"\r
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+\r
\r
/***************************************\r
* Data Structure Definition\r
***************************************/\r
\r
/* The following structure is used to hold status information for\r
- building and parsing incoming MIDI messages. */\r
+* building and parsing incoming MIDI messages. \r
+*/\r
typedef struct\r
{\r
uint8 length; /* expected length */\r
uint8 count; /* current byte count */\r
uint8 size; /* complete size */\r
uint8 runstat; /* running status */\r
- uint8 msgBuff[4]; /* message buffer */\r
+ uint8 msgBuff[4u]; /* message buffer */\r
} USBFS_MIDI_RX_STATUS;\r
\r
\r
/***************************************\r
-* MIDI Constants.\r
+* Function Prototypes\r
***************************************/\r
+/**\r
+* \addtogroup group_midi\r
+* @{\r
+*/\r
+#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)\r
+ void USBFS_MIDI_Init(void) ;\r
+\r
+ #if (USBFS_MIDI_IN_BUFF_SIZE > 0u)\r
+ void USBFS_MIDI_IN_Service(void) ;\r
+ uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable) ;\r
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0u) */\r
+\r
+ #if (USBFS_MIDI_OUT_BUFF_SIZE > 0u)\r
+ void USBFS_MIDI_OUT_Service(void) ;\r
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0u) */\r
+#endif /* (USBFS_ENABLE_MIDI_API != 0u) */\r
+\r
+\r
+/*******************************************************************************\r
+* Callback Function Prototypes\r
+*******************************************************************************/\r
\r
-#define USBFS_ONE_EXT_INTRF (0x01u)\r
-#define USBFS_TWO_EXT_INTRF (0x02u)\r
+/*******************************************************************************\r
+* Function Name: USBFS_callbackLocalMidiEvent\r
+****************************************************************************//**\r
+*\r
+* This is a callback function that locally processes data received from the PC \r
+* in main.c. You should implement this function if you want to use it. It is \r
+* called from the USB output processing routine for each MIDI output event \r
+* processed (decoded) from the output endpoint buffer. \r
+*\r
+* \param cable: Cable number\r
+* \r
+* \param midiMsg: Pointer to the 3-byte MIDI message\r
+*\r
+*\r
+***************************************************************************/\r
+void USBFS_callbackLocalMidiEvent(uint8 cable, uint8 *midiMsg)\r
+ ;\r
+/** @} midi */\r
+ \r
+/***************************************\r
+* MIDI Constants.\r
+***************************************/\r
\r
/* Flag definitions for use with MIDI device inquiry */\r
#define USBFS_INQ_SYSEX_FLAG (0x01u)\r
/* MIDI Universal System Exclusive defines */\r
#define USBFS_MIDI_SYSEX_NON_REAL_TIME (0x7Eu)\r
#define USBFS_MIDI_SYSEX_REALTIME (0x7Fu)\r
+\r
/* ID of target device */\r
#define USBFS_MIDI_SYSEX_ID_ALL (0x7Fu)\r
+\r
/* Sub-ID#1*/\r
#define USBFS_MIDI_SYSEX_GEN_INFORMATION (0x06u)\r
#define USBFS_MIDI_SYSEX_GEN_MESSAGE (0x09u)\r
+\r
/* Sub-ID#2*/\r
#define USBFS_MIDI_SYSEX_IDENTITY_REQ (0x01u)\r
#define USBFS_MIDI_SYSEX_IDENTITY_REPLY (0x02u)\r
#define USBFS_MIDI_SYSEX_SYSTEM_ON (0x01u)\r
#define USBFS_MIDI_SYSEX_SYSTEM_OFF (0x02u)\r
\r
-#define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x04u)\r
-#define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x02u)\r
-\r
-#define USBFS_ISR_SERVICE_MIDI_OUT \\r
- ( (USBFS_ENABLE_MIDI_API != 0u) && \\r
- (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO))\r
-#define USBFS_ISR_SERVICE_MIDI_IN \\r
- ( (USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0) )\r
-\r
-\r
-/***************************************\r
-* External function references\r
-***************************************/\r
-\r
-void USBFS_callbackLocalMidiEvent(uint8 cable, uint8 *midiMsg)\r
- ;\r
-\r
-\r
-/***************************************\r
-* External references\r
-***************************************/\r
-\r
-#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
- #include "MIDI1_UART.h"\r
-#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
-#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- #include "MIDI2_UART.h"\r
-#endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
-#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- #include <CyDmac.h>\r
-#endif /* USBFS_EP_MM */\r
+/* UART TX and RX interrupt priority. */\r
+#if (CY_PSOC4)\r
+ #define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x01u)\r
+ #define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x02u)\r
+#else\r
+ #define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x02u)\r
+ #define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x04u)\r
+#endif /* (CYPSOC4) */\r
\r
\r
/***************************************\r
-* Private function prototypes\r
+* Private Function Prototypes\r
***************************************/\r
\r
void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint8 cable)\r
- ;\r
+ ;\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
- void USBFS_MIDI_Init(void) ;\r
+ void USBFS_MIDI_InitInterface(void) ;\r
uint8 USBFS_ProcessMidiIn(uint8 mData, USBFS_MIDI_RX_STATUS *rxStat)\r
;\r
- uint8 USBFS_MIDI1_GetEvent(void) ;\r
- void USBFS_MIDI1_ProcessUsbOut(const uint8 epBuf[])\r
- ;\r
+ uint8 USBFS_MIDI1_GetEvent(void) ;\r
+ void USBFS_MIDI1_ProcessUsbOut(const uint8 epBuf[])\r
+ ;\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- uint8 USBFS_MIDI2_GetEvent(void) ;\r
- void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[])\r
- ;\r
- #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
-#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ uint8 USBFS_MIDI2_GetEvent(void) ;\r
+ void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[])\r
+ ;\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
\r
/***************************************\r
-* External data references\r
+* Vars with External Linkage\r
***************************************/\r
\r
#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
\r
#if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
#if (USBFS_MIDI_IN_BUFF_SIZE >= 256)\r
+/**\r
+* \addtogroup group_midi\r
+* @{\r
+*/ \r
extern volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */\r
+/** @} midi*/\r
#else\r
extern volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */\r
- #endif /* USBFS_MIDI_IN_BUFF_SIZE >=256 */\r
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE >=256) */\r
+/**\r
+* \addtogroup group_midi\r
+* @{\r
+*/ \r
extern volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */\r
extern uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */\r
-#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */\r
+#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
\r
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
extern volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */\r
extern uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */\r
-#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */\r
+#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
- extern volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */\r
+ extern volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */\r
+ \r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- extern volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */\r
- #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
-#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ extern volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
+/** @} midi */\r
+#endif /* (USBFS_ENABLE_MIDI_STREAMING) */\r
+\r
\r
-#endif /* USBFS_ENABLE_MIDI_STREAMING */\r
+/***************************************\r
+* The following code is DEPRECATED and\r
+* must not be used.\r
+***************************************/\r
\r
+#define USBFS_MIDI_EP_Init USBFS_MIDI_Init\r
+#define USBFS_MIDI_OUT_EP_Service USBFS_MIDI_OUT_Service\r
\r
-#endif /* CY_USBFS_USBFS_midi_H */\r
+#endif /* (CY_USBFS_USBFS_midi_H) */\r
\r
\r
/* [] END OF FILE */\r
--- /dev/null
+/***************************************************************************//**
+* \file USBFS_cdc.c
+* \version 3.10
+*
+* \brief
+* This file contains the USB MSC Class request handler and global API for MSC
+* class.
+*
+* Related Document:
+* Universal Serial Bus Class Definitions for Communication Devices Version 1.1
+*
+********************************************************************************
+* \copyright
+* Copyright 2012-2016, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "USBFS_msc.h"
+#include "USBFS_pvt.h"
+
+
+#if (USBFS_HANDLE_MSC_REQUESTS)
+
+/***************************************
+* Internal variables
+***************************************/
+
+static uint8 USBFS_lunCount = USBFS_MSC_LUN_NUMBER;
+
+
+/*******************************************************************************
+* Function Name: USBFS_DispatchMSCClassRqst
+****************************************************************************//**
+*
+* \internal
+* This routine dispatches MSC class requests.
+*
+* \return
+* Status of request processing: handled or not handled.
+*
+* \globalvars
+* USBFS_lunCount - stores number of LUN (logical units).
+*
+* \reentrant
+* No.
+*
+*******************************************************************************/
+uint8 USBFS_DispatchMSCClassRqst(void)
+{
+ uint8 requestHandled = USBFS_FALSE;
+
+ /* Get request data. */
+ uint16 value = USBFS_GET_UINT16(USBFS_wValueHiReg, USBFS_wValueLoReg);
+ uint16 dataLength = USBFS_GET_UINT16(USBFS_wLengthHiReg, USBFS_wLengthLoReg);
+
+ /* Check request direction: D2H or H2D. */
+ if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H))
+ {
+ /* Handle direction from device to host. */
+
+ if (USBFS_MSC_GET_MAX_LUN == USBFS_bRequestReg)
+ {
+ /* Check request fields. */
+ if ((value == USBFS_MSC_GET_MAX_LUN_WVALUE) &&
+ (dataLength == USBFS_MSC_GET_MAX_LUN_WLENGTH))
+ {
+ /* Reply to Get Max LUN request: setup control read. */
+ USBFS_currentTD.pData = &USBFS_lunCount;
+ USBFS_currentTD.count = USBFS_MSC_GET_MAX_LUN_WLENGTH;
+
+ requestHandled = USBFS_InitControlRead();
+ }
+ }
+ }
+ else
+ {
+ /* Handle direction from host to device. */
+
+ if (USBFS_MSC_RESET == USBFS_bRequestReg)
+ {
+ /* Check request fields. */
+ if ((value == USBFS_MSC_RESET_WVALUE) &&
+ (dataLength == USBFS_MSC_RESET_WLENGTH))
+ {
+ /* Handle to Bulk-Only Reset request: no data control transfer. */
+ USBFS_currentTD.count = USBFS_MSC_RESET_WLENGTH;
+
+ #ifdef USBFS_DISPATCH_MSC_CLASS_MSC_RESET_RQST_CALLBACK
+ USBFS_DispatchMSCClass_MSC_RESET_RQST_Callback();
+ #endif /* (USBFS_DISPATCH_MSC_CLASS_MSC_RESET_RQST_CALLBACK) */
+
+ requestHandled = USBFS_InitNoDataControlTransfer();
+ }
+ }
+ }
+
+ return (requestHandled);
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_MSC_SetLunCount
+****************************************************************************//**
+*
+* This function sets the number of logical units supported in the application.
+* The default number of logical units is set in the component customizer.
+*
+* \param lunCount: Count of the logical units. Valid range is between 1 and 16.
+*
+*
+* \globalvars
+* USBFS_lunCount - stores number of LUN (logical units).
+*
+* \reentrant
+* No.
+*
+*******************************************************************************/
+void USBFS_MSC_SetLunCount(uint8 lunCount)
+{
+ USBFS_lunCount = (lunCount - 1u);
+}
+
+
+/*******************************************************************************
+* Function Name: USBFS_MSC_GetLunCount
+****************************************************************************//**
+*
+* This function returns the number of logical units.
+*
+* \return
+* Number of the logical units.
+*
+* \globalvars
+* USBFS_lunCount - stores number of LUN (logical units).
+*
+* \reentrant
+* No.
+*
+*******************************************************************************/
+uint8 USBFS_MSC_GetLunCount(void)
+{
+ return (USBFS_lunCount + 1u);
+}
+
+#endif /* (USBFS_HANDLE_MSC_REQUESTS) */
+
+
+/* [] END OF FILE */
--- /dev/null
+/***************************************************************************//**
+* \file USBFS_msc.h
+* \version 3.10
+*
+* \brief
+* This file provides function prototypes and constants for the USBFS component
+* MSC class support.
+*
+* Related Document:
+* Device Class Definition for Mass Storage (MSC) Version TDB
+*
+********************************************************************************
+* \copyright
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_USBFS_USBFS_msc_H)
+#define CY_USBFS_USBFS_msc_H
+
+#include "USBFS.h"
+
+/***************************************
+* Initial Parameter Constants
+***************************************/
+
+#define USBFS_HANDLE_MSC_REQUESTS (0u != (1u))
+#define USBFS_MSC_LUN_NUMBER (1u - 1u)
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+/**
+* \addtogroup group_msc
+* @{
+*/
+#if (USBFS_HANDLE_MSC_REQUESTS)
+ void USBFS_MSC_SetLunCount(uint8 lunCount) ;
+ uint8 USBFS_MSC_GetLunCount(void) ;
+#endif /* (USBFS_HANDLE_MSC_REQUESTS) */
+/** @} msc */
+
+/***************************************
+* Constants
+***************************************/
+
+/* MSC Class-Specific requests */
+#define USBFS_MSC_RESET (0xFFu)
+#define USBFS_MSC_GET_MAX_LUN (0xFEu)
+
+/* MSC Class-Specific requests constant fields. */
+#define USBFS_MSC_RESET_WVALUE (0u)
+#define USBFS_MSC_RESET_WLENGTH (0u)
+
+#define USBFS_MSC_GET_MAX_LUN_WVALUE (0u)
+#define USBFS_MSC_GET_MAX_LUN_WLENGTH (1u)
+
+#endif /* CY_USBFS_USBFS_msc_H */
+
+
+/* [] END OF FILE */
-/*******************************************************************************\r
-* File Name: USBFS_pm.c\r
-* Version 2.80\r
-*\r
-* Description:\r
-* This file provides Suspend/Resume APIs functionality.\r
+/***************************************************************************//**\r
+* \file USBFS_pm.c\r
+* \version 3.10\r
*\r
-* Note:\r
+* \brief\r
+* This file provides Suspend/Resume APIs implementation.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "project.h"\r
-#include "USBFS.h"\r
#include "USBFS_pvt.h"\r
-\r
+#include "USBFS_Dp.h"\r
\r
\r
/***************************************\r
\r
static USBFS_BACKUP_STRUCT USBFS_backup;\r
\r
-\r
-#if(USBFS_DP_ISR_REMOVE == 0u)\r
-\r
+#if (USBFS_DP_ISR_ACTIVE)\r
/*******************************************************************************\r
- * Function Name: USBFS_DP_Interrupt\r
- ********************************************************************************\r
+ * Function Name: USBFS_DP_ISR\r
+ ****************************************************************************//**\r
*\r
- * Summary:\r
* This Interrupt Service Routine handles DP pin changes for wake-up from\r
* the sleep mode.\r
*\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
*******************************************************************************/\r
CY_ISR(USBFS_DP_ISR)\r
{\r
- #ifdef USBFS_DP_ISR_ENTRY_CALLBACK\r
- USBFS_DP_ISR_EntryCallback();\r
- #endif /* USBFS_DP_ISR_ENTRY_CALLBACK */\r
+ #ifdef USBFS_DP_ISR_ENTRY_CALLBACK\r
+ USBFS_DP_ISR_EntryCallback();\r
+ #endif /* (USBFS_DP_ISR_ENTRY_CALLBACK) */\r
\r
/* `#START DP_USER_CODE` Place your code here */\r
/* `#END` */\r
\r
- /* Clears active interrupt */\r
- CY_GET_REG8(USBFS_DP_INTSTAT_PTR);\r
-\r
- #ifdef USBFS_DP_ISR_EXIT_CALLBACK\r
- USBFS_DP_ISR_ExitCallback();\r
- #endif /* USBFS_DP_ISR_EXIT_CALLBACK */\r
+ (void) USBFS_Dp_ClearInterrupt();\r
+ \r
+ #ifdef USBFS_DP_ISR_EXIT_CALLBACK\r
+ USBFS_DP_ISR_ExitCallback();\r
+ #endif /* (USBFS_DP_ISR_EXIT_CALLBACK) */\r
}\r
-\r
-#endif /* (USBFS_DP_ISR_REMOVE == 0u) */\r
+#endif /* (USBFS_DP_ISR_ACTIVE) */\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_SaveConfig\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Saves the current user configuration.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_SaveConfig(void) \r
{\r
-\r
+ /* Empty function added for the compatibility purpose. */\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_RestoreConfig\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Restores the current user configuration.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_RestoreConfig(void) \r
{\r
- if(USBFS_configuration != 0u)\r
+ if (USBFS_configuration != 0u)\r
{\r
USBFS_ConfigReg();\r
+ USBFS_EpStateInit();\r
}\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Suspend\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This function disables the USBFS block and prepares for power down mode.\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None.\r
+* This function prepares the USBFS component to enter low power mode. The \r
+* interrupt on falling edge on Dp pin is configured to wakeup device when the \r
+* host drives resume condition. The pull-up is enabled on the Dp line while \r
+* device is in low power mode. The supported low power modes are Deep Sleep \r
+* (PSoC 4200L) and Sleep (PSoC 3/ PSoC 5LP).\r
+* \r
+* *Note* For PSoC 4200L devices, this function should not be called before \r
+* entering Sleep.\r
+* \r
+* *Note* After enter low power mode, the data which is left in the IN or OUT \r
+* endpoint buffers is not restored after wakeup and lost. Therefore it should \r
+* be stored in the SRAM for OUT endpoint or read by the host for IN endpoint \r
+* before enter low power mode.\r
*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_backup.enable: modified.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_Suspend(void) \r
{\r
uint8 enableInterrupts;\r
+\r
enableInterrupts = CyEnterCriticalSection();\r
\r
- if((CY_GET_REG8(USBFS_CR0_PTR) & USBFS_CR0_ENABLE) != 0u)\r
- { /* USB block is enabled */\r
+ if (0u != (USBFS_CR0_REG & USBFS_CR0_ENABLE))\r
+ {\r
+ /* USB block is enabled. */\r
USBFS_backup.enableState = 1u;\r
\r
- #if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #if (USBFS_EP_MANAGEMENT_DMA)\r
+ USBFS_Stop_DMA(USBFS_MAX_EP);\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+ #if (CY_PSOC4)\r
+ /* Suspend enter sequence. */\r
+ USBFS_POWER_CTRL_REG |= (USBFS_POWER_CTRL_SUSPEND |\r
+ USBFS_POWER_CTRL_SUSPEND_DEL);\r
+\r
+ /* Store state of USB regulator and disable it. */\r
+ USBFS_backup.mode = (uint8) (USBFS_CR1_REG & USBFS_CR1_REG_ENABLE);\r
+ USBFS_CR1_REG &= (uint32) ~USBFS_CR1_REG_ENABLE;\r
+ \r
+ /* Store SIE interrupt sources. Valid bits are 0 - 4. */\r
+ USBFS_backup.intrSeiMask = (uint8) USBFS_INTR_SIE_MASK_REG;\r
\r
- /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */\r
- USBFS_USBIO_CR0_REG &= (uint8)~USBFS_USBIO_CR0_TEN;\r
- CyDelayUs(0u); /*~50ns delay */\r
+ #else\r
+ /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled. */\r
+ USBFS_USBIO_CR0_REG &= (uint8) ~USBFS_USBIO_CR0_TEN;\r
+ CyDelayUs(USBFS_WAIT_REG_STABILITY_50NS); /*~50ns delay. */\r
\r
/* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) and pd_pullup_hv(Inverted) high. */\r
- USBFS_PM_USB_CR0_REG &=\r
- (uint8)~(USBFS_PM_USB_CR0_PD_N | USBFS_PM_USB_CR0_PD_PULLUP_N);\r
+ USBFS_PM_USB_CR0_REG &= (uint8) ~(USBFS_PM_USB_CR0_PD_N |\r
+ USBFS_PM_USB_CR0_PD_PULLUP_N);\r
\r
- /* Disable the SIE */\r
- USBFS_CR0_REG &= (uint8)~USBFS_CR0_ENABLE;\r
+ /* Disable the SIE. */\r
+ USBFS_CR0_REG &= (uint8) ~USBFS_CR0_ENABLE;\r
\r
- CyDelayUs(0u); /* ~50ns delay */\r
- /* Store mode and Disable VRegulator*/\r
- USBFS_backup.mode = USBFS_CR1_REG & USBFS_CR1_REG_ENABLE;\r
- USBFS_CR1_REG &= (uint8)~USBFS_CR1_REG_ENABLE;\r
+ CyDelayUs(USBFS_WAIT_REG_STABILITY_50NS); /* ~50ns delay. */\r
+ /* Store mode and disable VRegulator. */\r
+ USBFS_backup.mode = (uint8) (USBFS_CR1_REG & USBFS_CR1_REG_ENABLE);\r
+ USBFS_CR1_REG &= (uint8) ~USBFS_CR1_REG_ENABLE;\r
+\r
+ CyDelayUs(USBFS_WAIT_REG_STABILITY_1US); /* min 0.5us delay required. */\r
\r
- CyDelayUs(1u); /* 0.5 us min delay */\r
/* Disable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/\r
- USBFS_PM_USB_CR0_REG &= (uint8)~USBFS_PM_USB_CR0_REF_EN;\r
+ USBFS_PM_USB_CR0_REG &= (uint8) ~USBFS_PM_USB_CR0_REF_EN;\r
\r
- /* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pullup*/\r
+ /* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pull-up. */\r
USBFS_USBIO_CR1_REG |= USBFS_USBIO_CR1_IOMODE;\r
\r
- /* Disable USB in ACT PM */\r
- USBFS_PM_ACT_CFG_REG &= (uint8)~USBFS_PM_ACT_EN_FSUSB;\r
- /* Disable USB block for Standby Power Mode */\r
- USBFS_PM_STBY_CFG_REG &= (uint8)~USBFS_PM_STBY_EN_FSUSB;\r
- CyDelayUs(1u); /* min 0.5us delay required */\r
+ /* Disable USBFS block. */\r
+ /* Clear power active and standby mode templates: disable USB block. */\r
+ USBFS_PM_ACT_CFG_REG &= (uint8) ~USBFS_PM_ACT_EN_FSUSB;\r
+ USBFS_PM_STBY_CFG_REG &= (uint8) ~USBFS_PM_STBY_EN_FSUSB;\r
\r
+ CyDelayUs(USBFS_WAIT_REG_STABILITY_1US); /* min 0.5us delay required. */\r
+ #endif /* (CY_PSOC4) */\r
}\r
else\r
{\r
\r
CyExitCriticalSection(enableInterrupts);\r
\r
- /* Set the DP Interrupt for wake-up from sleep mode. */\r
- #if(USBFS_DP_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR);\r
- CyIntSetPriority(USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIOR);\r
- CyIntClearPending(USBFS_DP_INTC_VECT_NUM);\r
- CyIntEnable(USBFS_DP_INTC_VECT_NUM);\r
- #endif /* (USBFS_DP_ISR_REMOVE == 0u) */\r
+#if (USBFS_DP_ISR_ACTIVE)\r
+ /* Clear active mode Dp interrupt source history. */\r
+ (void) USBFS_Dp_ClearInterrupt();\r
+ CyIntClearPending(USBFS_DP_INTC_VECT_NUM);\r
+\r
+ CyIntEnable (USBFS_DP_INTC_VECT_NUM);\r
+#endif /* (USBFS_DP_ISR_ACTIVE). */\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Resume\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This function enables the USBFS block after power down mode.\r
+****************************************************************************//**\r
*\r
-* Parameters:\r
-* None.\r
+* This function prepares the USBFS component for active mode operation after \r
+* exit low power mode. It restores the component active mode configuration such \r
+* as device address assigned previously by the host, endpoints buffer and disables \r
+* interrupt on Dp pin.\r
+* The supported low power modes are Deep Sleep (PSoC 4200L) and Sleep \r
+* (PSoC 3/ PSoC 5LP).\r
+* \r
+* *Note* For PSoC 4200L devices, this function should not be called after \r
+* exiting Sleep.\r
+* \r
+* *Note* To resume communication with the host, the data endpoints must be \r
+* managed: the OUT endpoints must be enabled and IN endpoints must be loaded \r
+* with data. For DMA with Automatic Buffer Management, all endpoints buffers \r
+* must be initialized again before making them available to the host.\r
*\r
-* Return:\r
-* None.\r
*\r
-* Global variables:\r
+* \globalvars\r
* USBFS_backup - checked.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_Resume(void) \r
{\r
uint8 enableInterrupts;\r
+\r
enableInterrupts = CyEnterCriticalSection();\r
\r
- if(USBFS_backup.enableState != 0u)\r
+ if (0u != USBFS_backup.enableState)\r
{\r
- #if(USBFS_DP_ISR_REMOVE == 0u)\r
- CyIntDisable(USBFS_DP_INTC_VECT_NUM);\r
- #endif /* USBFS_DP_ISR_REMOVE */\r
+ #if (USBFS_DP_ISR_ACTIVE)\r
+ CyIntDisable(USBFS_DP_INTC_VECT_NUM);\r
+ #endif /* (USBFS_DP_ISR_ACTIVE) */\r
+\r
+ #if (CY_PSOC4)\r
+ /* Enable clock to USB IP. */\r
+ USBFS_USB_CLK_EN_REG |= USBFS_USB_CLK_CSR_CLK_EN;\r
+\r
+ /* Restore arbiter configuration for DMA transfers. */\r
+ #if (USBFS_EP_MANAGEMENT_DMA)\r
+ #if (USBFS_ARB_ISR_ACTIVE)\r
+ /* Enable ARB EP interrupt sources. */\r
+ USBFS_ARB_INT_EN_REG = USBFS_DEFAULT_ARB_INT_EN;\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+ /* Configure arbiter for Manual or Auto DMA operation and clear \r
+ * configuration completion. \r
+ */\r
+ USBFS_ARB_CFG_REG = USBFS_DEFAULT_ARB_CFG;\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+ /* Restore level (hi, lo, med) for each interrupt source. */\r
+ USBFS_INTR_LVL_SEL_REG = USBFS_DEFAULT_INTR_LVL_SEL;\r
+ \r
+ /* Store SIE interrupt sources. */\r
+ USBFS_INTR_SIE_MASK_REG = (uint32) USBFS_backup.intrSeiMask;\r
+\r
+ /* Set EP0.CR: ACK Setup, NAK IN/OUT. */\r
+ USBFS_EP0_CR_REG = USBFS_MODE_NAK_IN_OUT;\r
+\r
+ /* Restore data EP1-8 configuration. */\r
+ USBFS_RestoreConfig();\r
\r
- /* Enable USB block */\r
- USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB;\r
- /* Enable USB block for Standby Power Mode */\r
+ /* Restore state of USB regulator and wait until it supples stable power. */\r
+ USBFS_CR1_REG |= USBFS_backup.mode;\r
+ CyDelayUs(USBFS_WAIT_VREF_STABILITY);\r
+\r
+ /* Suspend exit sequence. */\r
+ USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND;\r
+ CyDelayUs(USBFS_WAIT_SUSPEND_DEL_DISABLE);\r
+ USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND_DEL;\r
+\r
+ #else\r
+ /* Set power active and standby mode templates: enable USB block. */\r
+ USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB;\r
USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB;\r
- /* Enable core clock */\r
+\r
+ /* Enable core clock. */\r
USBFS_USB_CLK_EN_REG |= USBFS_USB_CLK_ENABLE;\r
\r
/* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/\r
USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN;\r
- /* The reference will be available ~40us after power restored */\r
- CyDelayUs(40u);\r
- /* Return VRegulator*/\r
+\r
+ /* The reference is available ~40us after power restored. */\r
+ CyDelayUs(USBFS_WAIT_VREF_RESTORE);\r
+ /* Restore state of USB regulator and wait until it supples stable power. */\r
USBFS_CR1_REG |= USBFS_backup.mode;\r
- CyDelayUs(0u); /*~50ns delay */\r
- /* Enable USBIO */\r
+ CyDelayUs(USBFS_WAIT_VREF_STABILITY); /*~50ns delay. */\r
+\r
+ /* Enable USBIO. */\r
USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N;\r
- CyDelayUs(2u);\r
- /* Set the USBIO pull-up enable */\r
+ CyDelayUs(USBFS_WAIT_PD_PULLUP_N_ENABLE);\r
+ /* Set the USBIO pull-up enable. */\r
USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N;\r
\r
- /* Re-init Arbiter configuration for DMA transfers */\r
- #if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- /* Usb arb interrupt enable */\r
- USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;\r
- #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
- USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- /*Set cfg cmplt this rises DMA request when the full configuration is done */\r
- USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
-\r
- /* STALL_IN_OUT */\r
- CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);\r
- /* Enable the SIE with a last address */\r
+ /* Restore arbiter configuration for DMA transfers. */\r
+ #if (USBFS_EP_MANAGEMENT_DMA)\r
+ #if (USBFS_ARB_ISR_ACTIVE)\r
+ /* Enable ARB EP interrupt sources. */\r
+ USBFS_ARB_INT_EN_REG = USBFS_DEFAULT_ARB_INT_EN;\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+ /* Configure arbiter for Manual or Auto DMA operation and clear \r
+ * configuration completion. \r
+ */\r
+ USBFS_ARB_CFG_REG = USBFS_DEFAULT_ARB_CFG;\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+ /* Set EP0.CR: ACK Setup, STALL IN/OUT. */\r
+ USBFS_EP0_CR_REG = USBFS_MODE_STALL_IN_OUT;\r
+\r
+ /* Enable the USB IP to respond to USB traffic with the last address. */\r
USBFS_CR0_REG |= USBFS_CR0_ENABLE;\r
- CyDelayCycles(1u);\r
- /* Finally, Enable d+ pullup and select iomode to USB mode*/\r
- CY_SET_REG8(USBFS_USBIO_CR1_PTR, USBFS_USBIO_CR1_USBPUEN);\r
+ CyDelayCycles(USBFS_WAIT_CR0_REG_STABILITY);\r
+\r
+ /* Enable D+ pull-up and keep USB control on IO. */\r
+ USBFS_USBIO_CR1_REG = USBFS_USBIO_CR1_USBPUEN;\r
\r
- /* Restore USB register settings */\r
+ /* Restore data EP1-8 configuration. */\r
USBFS_RestoreConfig();\r
+ #endif /* (CY_PSOC4) */\r
}\r
\r
CyExitCriticalSection(enableInterrupts);\r
-/*******************************************************************************\r
-* File Name: .h\r
-* Version 2.80\r
+/***************************************************************************//**\r
+* \file .h\r
+* \version 3.10\r
*\r
-* Description:\r
-* This private file provides constants and parameter values for the\r
-* USBFS Component.\r
-* Please do not use this file or its content in your project.\r
-*\r
-* Note:\r
+* \brief\r
+* This file provides private function prototypes and constants for the \r
+* USBFS component. It is not intended to be used in the user project.\r
*\r
********************************************************************************\r
-* Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2013-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#if !defined(CY_USBFS_USBFS_pvt_H)\r
#define CY_USBFS_USBFS_pvt_H\r
\r
+#include "USBFS.h"\r
+ \r
+#ifdef USBFS_ENABLE_AUDIO_CLASS\r
+ #include "USBFS_audio.h"\r
+#endif /* USBFS_ENABLE_AUDIO_CLASS */\r
+\r
+#ifdef USBFS_ENABLE_CDC_CLASS\r
+ #include "USBFS_cdc.h"\r
+#endif /* USBFS_ENABLE_CDC_CLASS */\r
+\r
+#if (USBFS_ENABLE_MIDI_CLASS)\r
+ #include "USBFS_midi.h"\r
+#endif /* (USBFS_ENABLE_MIDI_CLASS) */\r
+\r
+#if (USBFS_ENABLE_MSC_CLASS)\r
+ #include "USBFS_msc.h"\r
+#endif /* (USBFS_ENABLE_MSC_CLASS) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+ #if (CY_PSOC4)\r
+ #include <CyDMA.h>\r
+ #else\r
+ #include <CyDmac.h>\r
+ #if ((USBFS_EP_MANAGEMENT_DMA_AUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ #include "USBFS_EP_DMA_Done_isr.h"\r
+ #include "USBFS_EP8_DMA_Done_SR.h"\r
+ #include "USBFS_EP17_DMA_Done_SR.h"\r
+ #endif /* ((USBFS_EP_MANAGEMENT_DMA_AUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+ #endif /* (CY_PSOC4) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+#if (USBFS_DMA1_ACTIVE)\r
+ #include "USBFS_ep1_dma.h"\r
+ #define USBFS_EP1_DMA_CH (USBFS_ep1_dma_CHANNEL)\r
+#endif /* (USBFS_DMA1_ACTIVE) */\r
+\r
+#if (USBFS_DMA2_ACTIVE)\r
+ #include "USBFS_ep2_dma.h"\r
+ #define USBFS_EP2_DMA_CH (USBFS_ep2_dma_CHANNEL)\r
+#endif /* (USBFS_DMA2_ACTIVE) */\r
+\r
+#if (USBFS_DMA3_ACTIVE)\r
+ #include "USBFS_ep3_dma.h"\r
+ #define USBFS_EP3_DMA_CH (USBFS_ep3_dma_CHANNEL)\r
+#endif /* (USBFS_DMA3_ACTIVE) */\r
+\r
+#if (USBFS_DMA4_ACTIVE)\r
+ #include "USBFS_ep4_dma.h"\r
+ #define USBFS_EP4_DMA_CH (USBFS_ep4_dma_CHANNEL)\r
+#endif /* (USBFS_DMA4_ACTIVE) */\r
+\r
+#if (USBFS_DMA5_ACTIVE)\r
+ #include "USBFS_ep5_dma.h"\r
+ #define USBFS_EP5_DMA_CH (USBFS_ep5_dma_CHANNEL)\r
+#endif /* (USBFS_DMA5_ACTIVE) */\r
+\r
+#if (USBFS_DMA6_ACTIVE)\r
+ #include "USBFS_ep6_dma.h"\r
+ #define USBFS_EP6_DMA_CH (USBFS_ep6_dma_CHANNEL)\r
+#endif /* (USBFS_DMA6_ACTIVE) */\r
+\r
+#if (USBFS_DMA7_ACTIVE)\r
+ #include "USBFS_ep7_dma.h"\r
+ #define USBFS_EP7_DMA_CH (USBFS_ep7_dma_CHANNEL)\r
+#endif /* (USBFS_DMA7_ACTIVE) */\r
+\r
+#if (USBFS_DMA8_ACTIVE)\r
+ #include "USBFS_ep8_dma.h"\r
+ #define USBFS_EP8_DMA_CH (USBFS_ep8_dma_CHANNEL)\r
+#endif /* (USBFS_DMA8_ACTIVE) */\r
+\r
\r
/***************************************\r
* Private Variables\r
***************************************/\r
\r
-/* Generated external references for descriptors*/\r
+/* Generated external references for descriptors. */\r
extern const uint8 CYCODE USBFS_DEVICE0_DESCR[18u];\r
extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[73u];\r
extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE[1u];\r
extern const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[4u];\r
extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[2u];\r
extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[5u];\r
-extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[2u];\r
+extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[3u];\r
extern const T_USBFS_LUT CYCODE USBFS_TABLE[1u];\r
extern const uint8 CYCODE USBFS_SN_STRING_DESCRIPTOR[10];\r
extern const uint8 CYCODE USBFS_STRING_DESCRIPTORS[45u];\r
extern const uint8 CYCODE USBFS_MSOS_CONFIGURATION_DESCR[USBFS_MSOS_CONF_DESCR_LENGTH];\r
#if defined(USBFS_ENABLE_IDSN_STRING)\r
extern uint8 USBFS_idSerialNumberStringDescriptor[USBFS_IDSN_DESCR_LENGTH];\r
-#endif /* USBFS_ENABLE_IDSN_STRING */\r
+#endif /* (USBFS_ENABLE_IDSN_STRING) */\r
\r
extern volatile uint8 USBFS_interfaceNumber;\r
extern volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER];\r
-extern volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER];\r
+extern volatile uint8 USBFS_interfaceSettingLast[USBFS_MAX_INTERFACES_NUMBER];\r
extern volatile uint8 USBFS_deviceAddress;\r
extern volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER];\r
extern const uint8 CYCODE *USBFS_interfaceClass;\r
extern volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP];\r
extern volatile T_USBFS_TD USBFS_currentTD;\r
\r
-#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- extern uint8 USBFS_DmaChan[USBFS_MAX_EP];\r
- extern uint8 USBFS_DmaTd[USBFS_MAX_EP];\r
-#endif /* USBFS_EP_MM */\r
-#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- extern uint8 USBFS_DmaNextTd[USBFS_MAX_EP];\r
- extern const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP];\r
- extern volatile uint16 USBFS_inLength[USBFS_MAX_EP];\r
- extern const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];\r
- extern volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];\r
-#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
+ #if (CY_PSOC4)\r
+ extern const uint8 USBFS_DmaChan[USBFS_MAX_EP];\r
+ #else\r
+ extern uint8 USBFS_DmaChan[USBFS_MAX_EP];\r
+ extern uint8 USBFS_DmaTd [USBFS_MAX_EP];\r
+ #endif /* (CY_PSOC4) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+#if (CY_PSOC4)\r
+ extern uint8 USBFS_DmaEpBurstCnt [USBFS_MAX_EP];\r
+ extern uint8 USBFS_DmaEpLastBurstEl[USBFS_MAX_EP];\r
+\r
+ extern uint8 USBFS_DmaEpBurstCntBackup [USBFS_MAX_EP];\r
+ extern uint32 USBFS_DmaEpBufferAddrBackup[USBFS_MAX_EP];\r
+ \r
+ extern const uint8 USBFS_DmaReqOut [USBFS_MAX_EP]; \r
+ extern const uint8 USBFS_DmaBurstEndOut[USBFS_MAX_EP];\r
+#else\r
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ extern uint8 USBFS_DmaNextTd[USBFS_MAX_EP];\r
+ extern volatile uint16 USBFS_inLength [USBFS_MAX_EP];\r
+ extern volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];\r
+ extern const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP];\r
+ extern const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];\r
+ #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+#endif /* CY_PSOC4 */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
\r
extern volatile uint8 USBFS_ep0Toggle;\r
extern volatile uint8 USBFS_lastPacketSize;\r
/***************************************\r
* Private Function Prototypes\r
***************************************/\r
-void USBFS_ReInitComponent(void) ;\r
-void USBFS_HandleSetup(void) ;\r
-void USBFS_HandleIN(void) ;\r
-void USBFS_HandleOUT(void) ;\r
-void USBFS_LoadEP0(void) ;\r
-uint8 USBFS_InitControlRead(void) ;\r
-uint8 USBFS_InitControlWrite(void) ;\r
-void USBFS_ControlReadDataStage(void) ;\r
-void USBFS_ControlReadStatusStage(void) ;\r
-void USBFS_ControlReadPrematureStatus(void)\r
- ;\r
-uint8 USBFS_InitControlWrite(void) ;\r
-uint8 USBFS_InitZeroLengthControlTransfer(void)\r
- ;\r
-void USBFS_ControlWriteDataStage(void) ;\r
-void USBFS_ControlWriteStatusStage(void) ;\r
-void USBFS_ControlWritePrematureStatus(void)\r
- ;\r
-uint8 USBFS_InitNoDataControlTransfer(void) ;\r
-void USBFS_NoDataControlStatusStage(void) ;\r
-void USBFS_InitializeStatusBlock(void) ;\r
+void USBFS_ReInitComponent(void) ;\r
+void USBFS_HandleSetup(void) ;\r
+void USBFS_HandleIN(void) ;\r
+void USBFS_HandleOUT(void) ;\r
+void USBFS_LoadEP0(void) ;\r
+uint8 USBFS_InitControlRead(void) ;\r
+uint8 USBFS_InitControlWrite(void) ;\r
+void USBFS_ControlReadDataStage(void) ;\r
+void USBFS_ControlReadStatusStage(void) ;\r
+void USBFS_ControlReadPrematureStatus(void) ;\r
+uint8 USBFS_InitControlWrite(void) ;\r
+uint8 USBFS_InitZeroLengthControlTransfer(void) ;\r
+void USBFS_ControlWriteDataStage(void) ;\r
+void USBFS_ControlWriteStatusStage(void) ;\r
+void USBFS_ControlWritePrematureStatus(void);\r
+uint8 USBFS_InitNoDataControlTransfer(void) ;\r
+void USBFS_NoDataControlStatusStage(void) ;\r
+void USBFS_InitializeStatusBlock(void) ;\r
void USBFS_UpdateStatusBlock(uint8 completionCode) ;\r
-uint8 USBFS_DispatchClassRqst(void) ;\r
+uint8 USBFS_DispatchClassRqst(void) ;\r
\r
void USBFS_Config(uint8 clearAltSetting) ;\r
-void USBFS_ConfigAltChanged(void) ;\r
-void USBFS_ConfigReg(void) ;\r
-\r
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)\r
- ;\r
-const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void)\r
- ;\r
-const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void)\r
- ;\r
-uint8 USBFS_ClearEndpointHalt(void) ;\r
-uint8 USBFS_SetEndpointHalt(void) ;\r
-uint8 USBFS_ValidateAlternateSetting(void) ;\r
-\r
-void USBFS_SaveConfig(void) ;\r
-void USBFS_RestoreConfig(void) ;\r
-\r
-#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) ;\r
-#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+void USBFS_ConfigAltChanged(void) ;\r
+void USBFS_ConfigReg(void) ;\r
+void USBFS_EpStateInit(void) ;\r
+\r
+\r
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex);\r
+const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) ;\r
+#if (USBFS_BOS_ENABLE)\r
+ const T_USBFS_LUT CYCODE *USBFS_GetBOSPtr(void) ;\r
+#endif /* (USBFS_BOS_ENABLE) */\r
+const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) ;uint8 USBFS_ClearEndpointHalt(void) ;\r
+uint8 USBFS_SetEndpointHalt(void) ;\r
+uint8 USBFS_ValidateAlternateSetting(void) ;\r
+\r
+void USBFS_SaveConfig(void) ;\r
+void USBFS_RestoreConfig(void) ;\r
+\r
+#if (CY_PSOC3 || CY_PSOC5LP)\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) ;\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
\r
#if defined(USBFS_ENABLE_IDSN_STRING)\r
- void USBFS_ReadDieID(uint8 descr[]) ;\r
+ void USBFS_ReadDieID(uint8 descr[]) ;\r
#endif /* USBFS_ENABLE_IDSN_STRING */\r
\r
#if defined(USBFS_ENABLE_HID_CLASS)\r
- uint8 USBFS_DispatchHIDClassRqst(void);\r
-#endif /* USBFS_ENABLE_HID_CLASS */\r
+ uint8 USBFS_DispatchHIDClassRqst(void) ;\r
+#endif /* (USBFS_ENABLE_HID_CLASS) */\r
+\r
#if defined(USBFS_ENABLE_AUDIO_CLASS)\r
- uint8 USBFS_DispatchAUDIOClassRqst(void);\r
-#endif /* USBFS_ENABLE_HID_CLASS */\r
+ uint8 USBFS_DispatchAUDIOClassRqst(void) ;\r
+#endif /* (USBFS_ENABLE_AUDIO_CLASS) */\r
+\r
#if defined(USBFS_ENABLE_CDC_CLASS)\r
- uint8 USBFS_DispatchCDCClassRqst(void);\r
-#endif /* USBFS_ENABLE_CDC_CLASS */\r
+ uint8 USBFS_DispatchCDCClassRqst(void) ;\r
+#endif /* (USBFS_ENABLE_CDC_CLASS) */\r
+\r
+#if (USBFS_ENABLE_MSC_CLASS)\r
+ #if (USBFS_HANDLE_MSC_REQUESTS)\r
+ uint8 USBFS_DispatchMSCClassRqst(void) ;\r
+ #endif /* (USBFS_HANDLE_MSC_REQUESTS) */\r
+#endif /* (USBFS_ENABLE_MSC_CLASS */\r
\r
CY_ISR_PROTO(USBFS_EP_0_ISR);\r
-#if(USBFS_EP1_ISR_REMOVE == 0u)\r
+CY_ISR_PROTO(USBFS_BUS_RESET_ISR);\r
+\r
+#if (USBFS_SOF_ISR_ACTIVE)\r
+ CY_ISR_PROTO(USBFS_SOF_ISR);\r
+#endif /* (USBFS_SOF_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP1_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_EP_1_ISR);\r
-#endif /* USBFS_EP1_ISR_REMOVE */\r
-#if(USBFS_EP2_ISR_REMOVE == 0u)\r
+#endif /* (USBFS_EP1_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP2_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_EP_2_ISR);\r
-#endif /* USBFS_EP2_ISR_REMOVE */\r
-#if(USBFS_EP3_ISR_REMOVE == 0u)\r
+#endif /* (USBFS_EP2_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP3_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_EP_3_ISR);\r
-#endif /* USBFS_EP3_ISR_REMOVE */\r
-#if(USBFS_EP4_ISR_REMOVE == 0u)\r
+#endif /* (USBFS_EP3_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP4_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_EP_4_ISR);\r
-#endif /* USBFS_EP4_ISR_REMOVE */\r
-#if(USBFS_EP5_ISR_REMOVE == 0u)\r
+#endif /* (USBFS_EP4_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP5_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_EP_5_ISR);\r
-#endif /* USBFS_EP5_ISR_REMOVE */\r
-#if(USBFS_EP6_ISR_REMOVE == 0u)\r
+#endif /* (USBFS_EP5_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP6_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_EP_6_ISR);\r
-#endif /* USBFS_EP6_ISR_REMOVE */\r
-#if(USBFS_EP7_ISR_REMOVE == 0u)\r
+#endif /* (USBFS_EP6_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP7_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_EP_7_ISR);\r
-#endif /* USBFS_EP7_ISR_REMOVE */\r
-#if(USBFS_EP8_ISR_REMOVE == 0u)\r
+#endif /* (USBFS_EP7_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP8_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_EP_8_ISR);\r
-#endif /* USBFS_EP8_ISR_REMOVE */\r
-CY_ISR_PROTO(USBFS_BUS_RESET_ISR);\r
-#if(USBFS_SOF_ISR_REMOVE == 0u)\r
- CY_ISR_PROTO(USBFS_SOF_ISR);\r
-#endif /* USBFS_SOF_ISR_REMOVE */\r
-#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
+#endif /* (USBFS_EP8_ISR_ACTIVE) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA)\r
CY_ISR_PROTO(USBFS_ARB_ISR);\r
-#endif /* USBFS_EP_MM */\r
-#if(USBFS_DP_ISR_REMOVE == 0u)\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+\r
+#if (USBFS_DP_ISR_ACTIVE)\r
CY_ISR_PROTO(USBFS_DP_ISR);\r
-#endif /* USBFS_DP_ISR_REMOVE */\r
-#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
- CY_ISR_PROTO(USBFS_EP_DMA_DONE_ISR);\r
-#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+#endif /* (USBFS_DP_ISR_ACTIVE) */\r
+\r
+#if (CY_PSOC4)\r
+ CY_ISR_PROTO(USBFS_INTR_HI_ISR);\r
+ CY_ISR_PROTO(USBFS_INTR_MED_ISR);\r
+ CY_ISR_PROTO(USBFS_INTR_LO_ISR);\r
+ #if (USBFS_LPM_ACTIVE)\r
+ CY_ISR_PROTO(USBFS_LPM_ISR);\r
+ #endif /* (USBFS_LPM_ACTIVE) */\r
+#endif /* (CY_PSOC4) */\r
+\r
+#if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+#if (CY_PSOC4)\r
+ #if (USBFS_DMA1_ACTIVE)\r
+ void USBFS_EP1_DMA_DONE_ISR(void);\r
+ #endif /* (USBFS_DMA1_ACTIVE) */\r
+\r
+ #if (USBFS_DMA2_ACTIVE)\r
+ void USBFS_EP2_DMA_DONE_ISR(void);\r
+ #endif /* (USBFS_DMA2_ACTIVE) */\r
+\r
+ #if (USBFS_DMA3_ACTIVE)\r
+ void USBFS_EP3_DMA_DONE_ISR(void);\r
+ #endif /* (USBFS_DMA3_ACTIVE) */\r
+\r
+ #if (USBFS_DMA4_ACTIVE)\r
+ void USBFS_EP4_DMA_DONE_ISR(void);\r
+ #endif /* (USBFS_DMA4_ACTIVE) */\r
+\r
+ #if (USBFS_DMA5_ACTIVE)\r
+ void USBFS_EP5_DMA_DONE_ISR(void);\r
+ #endif /* (USBFS_DMA5_ACTIVE) */\r
+\r
+ #if (USBFS_DMA6_ACTIVE)\r
+ void USBFS_EP6_DMA_DONE_ISR(void);\r
+ #endif /* (USBFS_DMA6_ACTIVE) */\r
+\r
+ #if (USBFS_DMA7_ACTIVE)\r
+ void USBFS_EP7_DMA_DONE_ISR(void);\r
+ #endif /* (USBFS_DMA7_ACTIVE) */\r
+\r
+ #if (USBFS_DMA8_ACTIVE)\r
+ void USBFS_EP8_DMA_DONE_ISR(void);\r
+ #endif /* (USBFS_DMA8_ACTIVE) */\r
+\r
+#else\r
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ CY_ISR_PROTO(USBFS_EP_DMA_DONE_ISR);\r
+ #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+#endif /* (CY_PSOC4) */\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+\r
\r
/***************************************\r
-* Request Handlers\r
+* Request Handlers\r
***************************************/\r
\r
uint8 USBFS_HandleStandardRqst(void) ;\r
-uint8 USBFS_DispatchClassRqst(void) ;\r
-uint8 USBFS_HandleVendorRqst(void) ;\r
+uint8 USBFS_DispatchClassRqst(void) ;\r
+uint8 USBFS_HandleVendorRqst(void) ;\r
\r
\r
/***************************************\r
***************************************/\r
\r
#if defined(USBFS_ENABLE_HID_CLASS)\r
- void USBFS_FindReport(void) ;\r
- void USBFS_FindReportDescriptor(void) ;\r
+ void USBFS_FindReport(void) ;\r
+ void USBFS_FindReportDescriptor(void) ;\r
void USBFS_FindHidClassDecriptor(void) ;\r
#endif /* USBFS_ENABLE_HID_CLASS */\r
\r
***************************************/\r
\r
#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
- void USBFS_MIDI_IN_EP_Service(void) ;\r
-#endif /* USBFS_ENABLE_MIDI_STREAMING */\r
+ void USBFS_MIDI_IN_EP_Service(void) ;\r
+#endif /* (USBFS_ENABLE_MIDI_STREAMING) */\r
+\r
+\r
+/***************************************\r
+* CDC Internal references\r
+***************************************/\r
+\r
+#if defined(USBFS_ENABLE_CDC_CLASS)\r
+\r
+ typedef struct\r
+ {\r
+ uint8 bRequestType;\r
+ uint8 bNotification;\r
+ uint8 wValue;\r
+ uint8 wValueMSB;\r
+ uint8 wIndex;\r
+ uint8 wIndexMSB;\r
+ uint8 wLength;\r
+ uint8 wLengthMSB;\r
+ uint8 wSerialState;\r
+ uint8 wSerialStateMSB;\r
+ } t_USBFS_cdc_notification;\r
+\r
+ uint8 USBFS_GetInterfaceComPort(uint8 interface) ;\r
+ uint8 USBFS_Cdc_EpInit( const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP, uint8 epNum, uint8 cdcComNums) ;\r
+\r
+ extern volatile uint8 USBFS_cdc_dataInEpList[USBFS_MAX_MULTI_COM_NUM];\r
+ extern volatile uint8 USBFS_cdc_dataOutEpList[USBFS_MAX_MULTI_COM_NUM];\r
+ extern volatile uint8 USBFS_cdc_commInEpList[USBFS_MAX_MULTI_COM_NUM];\r
+#endif /* (USBFS_ENABLE_CDC_CLASS) */\r
\r
\r
#endif /* CY_USBFS_USBFS_pvt_H */\r
-/*******************************************************************************\r
-* File Name: USBFS_std.c\r
-* Version 2.80\r
-*\r
-* Description:\r
-* USB Standard request handler.\r
+/***************************************************************************//**\r
+* \file USBFS_std.c\r
+* \version 3.10\r
*\r
-* Note:\r
+* \brief\r
+* This file contains the USB Standard request handler.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
-#include "USBFS_cdc.h"\r
#include "USBFS_pvt.h"\r
-#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
- #include "USBFS_midi.h"\r
-#endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
-\r
\r
/***************************************\r
* Static data allocation\r
***************************************/\r
\r
#if defined(USBFS_ENABLE_FWSN_STRING)\r
- static volatile uint8 *USBFS_fwSerialNumberStringDescriptor;\r
- static volatile uint8 USBFS_snStringConfirm = USBFS_FALSE;\r
-#endif /* USBFS_ENABLE_FWSN_STRING */\r
+ static volatile uint8* USBFS_fwSerialNumberStringDescriptor;\r
+ static volatile uint8 USBFS_snStringConfirm = USBFS_FALSE;\r
+#endif /* (USBFS_ENABLE_FWSN_STRING) */\r
\r
#if defined(USBFS_ENABLE_FWSN_STRING)\r
-\r
- /*******************************************************************************\r
+ /***************************************************************************\r
* Function Name: USBFS_SerialNumString\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Application firmware may supply the source of the USB device descriptors\r
- * serial number string during runtime.\r
+ ************************************************************************//**\r
*\r
- * Parameters:\r
- * snString: pointer to string.\r
+ * This function is available only when the User Call Back option in the \r
+ * Serial Number String descriptor properties is selected. Application \r
+ * firmware can provide the source of the USB device serial number string \r
+ * descriptor during run time. The default string is used if the application \r
+ * firmware does not use this function or sets the wrong string descriptor.\r
*\r
- * Return:\r
- * None.\r
+ * \param snString: Pointer to the user-defined string descriptor. The \r
+ * string descriptor should meet the Universal Serial Bus Specification \r
+ * revision 2.0 chapter 9.6.7\r
+ * Offset|Size|Value|Description\r
+ * ------|----|------|---------------------------------\r
+ * 0 |1 |N |Size of this descriptor in bytes\r
+ * 1 |1 |0x03 |STRING Descriptor Type\r
+ * 2 |N-2 |Number|UNICODE encoded string\r
+ * \r
+ * *For example:* uint8 snString[16]={0x0E,0x03,'F',0,'W',0,'S',0,'N',0,'0',0,'1',0};\r
*\r
- * Reentrant:\r
+ * \reentrant\r
* No.\r
*\r
- *******************************************************************************/\r
+ ***************************************************************************/\r
void USBFS_SerialNumString(uint8 snString[]) \r
{\r
USBFS_snStringConfirm = USBFS_FALSE;\r
- if(snString != NULL)\r
+ \r
+ if (snString != NULL)\r
{\r
/* Check descriptor validation */\r
- if( (snString[0u] > 1u ) && (snString[1u] == USBFS_DESCR_STRING) )\r
+ if ((snString[0u] > 1u) && (snString[1u] == USBFS_DESCR_STRING))\r
{\r
USBFS_fwSerialNumberStringDescriptor = snString;\r
USBFS_snStringConfirm = USBFS_TRUE;\r
}\r
}\r
}\r
-\r
#endif /* USBFS_ENABLE_FWSN_STRING */\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_HandleStandardRqst\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This Routine dispatches standard requests\r
*\r
-* Parameters:\r
-* None.\r
*\r
-* Return:\r
+* \return\r
* TRUE if request handled.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 requestHandled = USBFS_FALSE;\r
uint8 interfaceNumber;\r
uint8 configurationN;\r
- #if defined(USBFS_ENABLE_STRINGS)\r
- volatile uint8 *pStr = 0u;\r
- #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS)\r
- uint8 nStr;\r
- uint8 descrLength;\r
- #endif /* USBFS_ENABLE_DESCRIPTOR_STRINGS */\r
- #endif /* USBFS_ENABLE_STRINGS */\r
+ uint8 bmRequestType = USBFS_bmRequestTypeReg;\r
+\r
+#if defined(USBFS_ENABLE_STRINGS)\r
+ volatile uint8 *pStr = 0u;\r
+ #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS)\r
+ uint8 nStr;\r
+ uint8 descrLength;\r
+ #endif /* (USBFS_ENABLE_DESCRIPTOR_STRINGS) */\r
+#endif /* (USBFS_ENABLE_STRINGS) */\r
+ \r
static volatile uint8 USBFS_tBuffer[USBFS_STATUS_LENGTH_MAX];\r
const T_USBFS_LUT CYCODE *pTmp;\r
+\r
USBFS_currentTD.count = 0u;\r
\r
- if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)\r
+ if (USBFS_RQST_DIR_D2H == (bmRequestType & USBFS_RQST_DIR_MASK))\r
{\r
/* Control Read */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_GET_DESCRIPTOR:\r
- if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_DEVICE)\r
+ if (USBFS_DESCR_DEVICE ==USBFS_wValueHiReg)\r
{\r
pTmp = USBFS_GetDeviceTablePtr();\r
USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;\r
USBFS_currentTD.count = USBFS_DEVICE_DESCR_LENGTH;\r
+ \r
requestHandled = USBFS_InitControlRead();\r
}\r
- else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_CONFIG)\r
+ else if (USBFS_DESCR_CONFIG == USBFS_wValueHiReg)\r
{\r
- pTmp = USBFS_GetConfigTablePtr(CY_GET_REG8(USBFS_wValueLo));\r
- if( pTmp != NULL ) /* Verify that requested descriptor exists */\r
+ pTmp = USBFS_GetConfigTablePtr((uint8) USBFS_wValueLoReg);\r
+ \r
+ /* Verify that requested descriptor exists */\r
+ if (pTmp != NULL)\r
{\r
USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;\r
- USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \\r
- USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \\r
- (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];\r
+ USBFS_currentTD.count = (uint16)((uint16)(USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \\r
+ (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];\r
requestHandled = USBFS_InitControlRead();\r
}\r
}\r
- #if defined(USBFS_ENABLE_STRINGS)\r
- else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_STRING)\r
+ \r
+ #if(USBFS_BOS_ENABLE)\r
+ else if (USBFS_DESCR_BOS == USBFS_wValueHiReg)\r
{\r
- /* Descriptor Strings*/\r
- #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS)\r
- nStr = 0u;\r
- pStr = (volatile uint8 *)&USBFS_STRING_DESCRIPTORS[0u];\r
- while ( (CY_GET_REG8(USBFS_wValueLo) > nStr) && (*pStr != 0u) )\r
- {\r
- /* Read descriptor length from 1st byte */\r
- descrLength = *pStr;\r
- /* Move to next string descriptor */\r
- pStr = &pStr[descrLength];\r
- nStr++;\r
- }\r
- #endif /* USBFS_ENABLE_DESCRIPTOR_STRINGS */\r
- /* Microsoft OS String*/\r
- #if defined(USBFS_ENABLE_MSOS_STRING)\r
- if( CY_GET_REG8(USBFS_wValueLo) == USBFS_STRING_MSOS )\r
+ pTmp = USBFS_GetBOSPtr();\r
+ \r
+ /* Verify that requested descriptor exists */\r
+ if (pTmp != NULL)\r
+ {\r
+ USBFS_currentTD.pData = (volatile uint8 *)pTmp;\r
+ USBFS_currentTD.count = ((uint16)((uint16)(USBFS_currentTD.pData)[USBFS_BOS_DESCR_TOTAL_LENGTH_HI] << 8u)) | \\r
+ (USBFS_currentTD.pData)[USBFS_BOS_DESCR_TOTAL_LENGTH_LOW];\r
+ requestHandled = USBFS_InitControlRead();\r
+ }\r
+ }\r
+ #endif /*(USBFS_BOS_ENABLE)*/\r
+ \r
+ #if defined(USBFS_ENABLE_STRINGS)\r
+ else if (USBFS_DESCR_STRING == USBFS_wValueHiReg)\r
+ {\r
+ /* Descriptor Strings */\r
+ #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS)\r
+ nStr = 0u;\r
+ pStr = (volatile uint8 *) &USBFS_STRING_DESCRIPTORS[0u];\r
+ \r
+ while ((USBFS_wValueLoReg > nStr) && (*pStr != 0u))\r
+ {\r
+ /* Read descriptor length from 1st byte */\r
+ descrLength = *pStr;\r
+ /* Move to next string descriptor */\r
+ pStr = &pStr[descrLength];\r
+ nStr++;\r
+ }\r
+ #endif /* (USBFS_ENABLE_DESCRIPTOR_STRINGS) */\r
+ \r
+ /* Microsoft OS String */\r
+ #if defined(USBFS_ENABLE_MSOS_STRING)\r
+ if (USBFS_STRING_MSOS == USBFS_wValueLoReg)\r
+ {\r
+ pStr = (volatile uint8 *)& USBFS_MSOS_DESCRIPTOR[0u];\r
+ }\r
+ #endif /* (USBFS_ENABLE_MSOS_STRING) */\r
+ \r
+ /* SN string */\r
+ #if defined(USBFS_ENABLE_SN_STRING)\r
+ if ((USBFS_wValueLoReg != 0u) && \r
+ (USBFS_wValueLoReg == USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]))\r
+ {\r
+ #if defined(USBFS_ENABLE_IDSN_STRING)\r
+ /* Read DIE ID and generate string descriptor in RAM */\r
+ USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor);\r
+ pStr = USBFS_idSerialNumberStringDescriptor;\r
+ #elif defined(USBFS_ENABLE_FWSN_STRING)\r
+ \r
+ if(USBFS_snStringConfirm != USBFS_FALSE)\r
{\r
- pStr = (volatile uint8 *)&USBFS_MSOS_DESCRIPTOR[0u];\r
+ pStr = USBFS_fwSerialNumberStringDescriptor;\r
}\r
- #endif /* USBFS_ENABLE_MSOS_STRING*/\r
- /* SN string */\r
- #if defined(USBFS_ENABLE_SN_STRING)\r
- if( (CY_GET_REG8(USBFS_wValueLo) != 0u) &&\r
- (CY_GET_REG8(USBFS_wValueLo) ==\r
- USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]) )\r
+ else\r
{\r
-\r
- #if defined(USBFS_ENABLE_IDSN_STRING)\r
- /* Read DIE ID and generate string descriptor in RAM */\r
- USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor);\r
- pStr = USBFS_idSerialNumberStringDescriptor;\r
- #elif defined(USBFS_ENABLE_FWSN_STRING)\r
- if(USBFS_snStringConfirm != USBFS_FALSE)\r
- {\r
- pStr = USBFS_fwSerialNumberStringDescriptor;\r
- }\r
- else\r
- {\r
- pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];\r
- }\r
- #else\r
- pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];\r
- #endif /* defined(USBFS_ENABLE_IDSN_STRING) */\r
+ pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];\r
}\r
- #endif /* USBFS_ENABLE_SN_STRING */\r
+ #else\r
+ pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];\r
+ #endif /* (USBFS_ENABLE_IDSN_STRING) */\r
+ }\r
+ #endif /* (USBFS_ENABLE_SN_STRING) */\r
+ \r
if (*pStr != 0u)\r
{\r
USBFS_currentTD.count = *pStr;\r
requestHandled = USBFS_InitControlRead();\r
}\r
}\r
- #endif /* USBFS_ENABLE_STRINGS */\r
+ #endif /* USBFS_ENABLE_STRINGS */\r
else\r
{\r
requestHandled = USBFS_DispatchClassRqst();\r
}\r
break;\r
+ \r
case USBFS_GET_STATUS:\r
- switch ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK))\r
+ switch (bmRequestType & USBFS_RQST_RCPT_MASK)\r
{\r
case USBFS_RQST_RCPT_EP:\r
USBFS_currentTD.count = USBFS_EP_STATUS_LENGTH;\r
- USBFS_tBuffer[0u] = USBFS_EP[ \\r
- CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].hwEpState;\r
- USBFS_tBuffer[1u] = 0u;\r
+ USBFS_tBuffer[0u] = USBFS_EP[USBFS_wIndexLoReg & USBFS_DIR_UNUSED].hwEpState;\r
+ USBFS_tBuffer[1u] = 0u;\r
USBFS_currentTD.pData = &USBFS_tBuffer[0u];\r
+ \r
requestHandled = USBFS_InitControlRead();\r
break;\r
case USBFS_RQST_RCPT_DEV:\r
USBFS_currentTD.count = USBFS_DEVICE_STATUS_LENGTH;\r
- USBFS_tBuffer[0u] = USBFS_deviceStatus;\r
- USBFS_tBuffer[1u] = 0u;\r
+ USBFS_tBuffer[0u] = USBFS_deviceStatus;\r
+ USBFS_tBuffer[1u] = 0u;\r
USBFS_currentTD.pData = &USBFS_tBuffer[0u];\r
+ \r
requestHandled = USBFS_InitControlRead();\r
break;\r
default: /* requestHandled is initialized as FALSE by default */\r
break;\r
}\r
break;\r
+ \r
case USBFS_GET_CONFIGURATION:\r
USBFS_currentTD.count = 1u;\r
- USBFS_currentTD.pData = (volatile uint8 *)&USBFS_configuration;\r
+ USBFS_currentTD.pData = (volatile uint8 *) &USBFS_configuration;\r
requestHandled = USBFS_InitControlRead();\r
break;\r
+ \r
case USBFS_GET_INTERFACE:\r
USBFS_currentTD.count = 1u;\r
- USBFS_currentTD.pData = (volatile uint8 *)&USBFS_interfaceSetting[ \\r
- CY_GET_REG8(USBFS_wIndexLo)];\r
+ USBFS_currentTD.pData = (volatile uint8 *) &USBFS_interfaceSetting[USBFS_wIndexLoReg];\r
requestHandled = USBFS_InitControlRead();\r
break;\r
+ \r
default: /* requestHandled is initialized as FALSE by default */\r
break;\r
}\r
}\r
- else {\r
+ else\r
+ {\r
/* Control Write */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_SET_ADDRESS:\r
- USBFS_deviceAddress = CY_GET_REG8(USBFS_wValueLo);\r
+ /* Store address to be set in USBFS_NoDataControlStatusStage(). */\r
+ USBFS_deviceAddress = (uint8) USBFS_wValueLoReg;\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
break;\r
+ \r
case USBFS_SET_CONFIGURATION:\r
- configurationN = CY_GET_REG8(USBFS_wValueLo);\r
+ configurationN = USBFS_wValueLoReg;\r
+ \r
+ /* Verify that configuration descriptor exists */\r
if(configurationN > 0u)\r
- { /* Verify that configuration descriptor exists */\r
- pTmp = USBFS_GetConfigTablePtr(configurationN - 1u);\r
+ {\r
+ pTmp = USBFS_GetConfigTablePtr((uint8) configurationN - 1u);\r
}\r
+ \r
/* Responds with a Request Error when configuration number is invalid */\r
if (((configurationN > 0u) && (pTmp != NULL)) || (configurationN == 0u))\r
{\r
/* Set new configuration if it has been changed */\r
if(configurationN != USBFS_configuration)\r
{\r
- USBFS_configuration = configurationN;\r
+ USBFS_configuration = (uint8) configurationN;\r
USBFS_configurationChanged = USBFS_TRUE;\r
USBFS_Config(USBFS_TRUE);\r
}\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
}\r
break;\r
+ \r
case USBFS_SET_INTERFACE:\r
- if (USBFS_ValidateAlternateSetting() != 0u)\r
+ if (0u != USBFS_ValidateAlternateSetting())\r
{\r
- interfaceNumber = CY_GET_REG8(USBFS_wIndexLo);\r
- USBFS_interfaceNumber = interfaceNumber;\r
- USBFS_configurationChanged = USBFS_TRUE;\r
- #if ((USBFS_EP_MA == USBFS__MA_DYNAMIC) && \\r
- (USBFS_EP_MM == USBFS__EP_MANUAL) )\r
+ /* Get interface number from the request. */\r
+ interfaceNumber = USBFS_wIndexLoReg;\r
+ USBFS_interfaceNumber = (uint8) USBFS_wIndexLoReg;\r
+ \r
+ /* Check if alternate settings is changed for interface. */\r
+ if (USBFS_interfaceSettingLast[interfaceNumber] != USBFS_interfaceSetting[interfaceNumber])\r
+ {\r
+ USBFS_configurationChanged = USBFS_TRUE;\r
+ \r
+ /* Change alternate setting for the endpoints. */\r
+ #if (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC)\r
USBFS_Config(USBFS_FALSE);\r
#else\r
USBFS_ConfigAltChanged();\r
- #endif /* (USBFS_EP_MA == USBFS__MA_DYNAMIC) */\r
- /* Update handled Alt setting changes status */\r
- USBFS_interfaceSetting_last[interfaceNumber] =\r
- USBFS_interfaceSetting[interfaceNumber];\r
+ #endif /* (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC) */\r
+ }\r
+ \r
requestHandled = USBFS_InitNoDataControlTransfer();\r
}\r
break;\r
+ \r
case USBFS_CLEAR_FEATURE:\r
- switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK)\r
+ switch (bmRequestType & USBFS_RQST_RCPT_MASK)\r
{\r
case USBFS_RQST_RCPT_EP:\r
- if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT)\r
+ if (USBFS_wValueLoReg == USBFS_ENDPOINT_HALT)\r
{\r
requestHandled = USBFS_ClearEndpointHalt();\r
}\r
break;\r
case USBFS_RQST_RCPT_DEV:\r
/* Clear device REMOTE_WAKEUP */\r
- if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP)\r
+ if (USBFS_wValueLoReg == USBFS_DEVICE_REMOTE_WAKEUP)\r
{\r
USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_REMOTE_WAKEUP;\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
break;\r
case USBFS_RQST_RCPT_IFC:\r
/* Validate interfaceNumber */\r
- if (CY_GET_REG8(USBFS_wIndexLo) < USBFS_MAX_INTERFACES_NUMBER)\r
+ if (USBFS_wIndexLoReg < USBFS_MAX_INTERFACES_NUMBER)\r
{\r
- USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &=\r
- (uint8)~(CY_GET_REG8(USBFS_wValueLo));\r
+ USBFS_interfaceStatus[USBFS_wIndexLoReg] &= (uint8) ~USBFS_wValueLoReg;\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
}\r
break;\r
break;\r
}\r
break;\r
+ \r
case USBFS_SET_FEATURE:\r
- switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK)\r
+ switch (bmRequestType & USBFS_RQST_RCPT_MASK)\r
{\r
case USBFS_RQST_RCPT_EP:\r
- if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT)\r
+ if (USBFS_wValueLoReg == USBFS_ENDPOINT_HALT)\r
{\r
requestHandled = USBFS_SetEndpointHalt();\r
}\r
break;\r
+ \r
case USBFS_RQST_RCPT_DEV:\r
/* Set device REMOTE_WAKEUP */\r
- if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP)\r
+ if (USBFS_wValueLoReg == USBFS_DEVICE_REMOTE_WAKEUP)\r
{\r
USBFS_deviceStatus |= USBFS_DEVICE_STATUS_REMOTE_WAKEUP;\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
}\r
break;\r
+ \r
case USBFS_RQST_RCPT_IFC:\r
/* Validate interfaceNumber */\r
- if (CY_GET_REG8(USBFS_wIndexLo) < USBFS_MAX_INTERFACES_NUMBER)\r
+ if (USBFS_wIndexLoReg < USBFS_MAX_INTERFACES_NUMBER)\r
{\r
- USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &=\r
- (uint8)~(CY_GET_REG8(USBFS_wValueLo));\r
+ USBFS_interfaceStatus[USBFS_wIndexLoReg] &= (uint8) ~USBFS_wValueLoReg;\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
}\r
break;\r
+ \r
default: /* requestHandled is initialized as FALSE by default */\r
break;\r
}\r
break;\r
+ \r
default: /* requestHandled is initialized as FALSE by default */\r
break;\r
}\r
}\r
- return(requestHandled);\r
+ \r
+ return (requestHandled);\r
}\r
\r
\r
#if defined(USBFS_ENABLE_IDSN_STRING)\r
-\r
/***************************************************************************\r
* Function Name: USBFS_ReadDieID\r
- ****************************************************************************\r
+ ************************************************************************//**\r
*\r
- * Summary:\r
* This routine read Die ID and generate Serial Number string descriptor.\r
*\r
- * Parameters:\r
- * descr: pointer on string descriptor.\r
+ * \param descr: pointer on string descriptor. This string size has to be equal or\r
+ * greater than USBFS_IDSN_DESCR_LENGTH.\r
*\r
- * Return:\r
- * None.\r
*\r
- * Reentrant:\r
+ * \reentrant\r
* No.\r
*\r
***************************************************************************/\r
void USBFS_ReadDieID(uint8 descr[]) \r
{\r
+ const char8 CYCODE hex[] = "0123456789ABCDEF";\r
uint8 i;\r
uint8 j = 0u;\r
- uint8 value;\r
- const char8 CYCODE hex[16u] = "0123456789ABCDEF";\r
+ uint8 uniqueId[8u];\r
\r
- /* Check descriptor validation */\r
- if( descr != NULL)\r
+ if (NULL != descr)\r
{\r
+ /* Initialize descriptor header. */\r
descr[0u] = USBFS_IDSN_DESCR_LENGTH;\r
descr[1u] = USBFS_DESCR_STRING;\r
+ \r
+ /* Unique ID size is 8 bytes. */\r
+ CyGetUniqueId((uint32 *) uniqueId);\r
\r
- /* fill descriptor */\r
- for(i = 2u; i < USBFS_IDSN_DESCR_LENGTH; i += 4u)\r
+ /* Fill descriptor with unique device ID. */\r
+ for (i = 2u; i < USBFS_IDSN_DESCR_LENGTH; i += 4u)\r
{\r
- value = CY_GET_XTND_REG8((void CYFAR *)(USBFS_DIE_ID + j));\r
- j++;\r
- descr[i] = (uint8)hex[value >> 4u];\r
- descr[i + 2u] = (uint8)hex[value & 0x0Fu];\r
+ descr[i] = (uint8) hex[(uniqueId[j] >> 4u)];\r
+ descr[i + 1u] = 0u;\r
+ descr[i + 2u] = (uint8) hex[(uniqueId[j] & 0x0Fu)];\r
+ descr[i + 3u] = 0u;\r
+ ++j;\r
}\r
}\r
}\r
-\r
-#endif /* USBFS_ENABLE_IDSN_STRING */\r
+#endif /* (USBFS_ENABLE_IDSN_STRING) */\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ConfigReg\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine configures hardware registers from the variables.\r
* It is called from USBFS_Config() function and from RestoreConfig\r
* after Wakeup.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
*******************************************************************************/\r
void USBFS_ConfigReg(void) \r
{\r
uint8 ep;\r
- uint8 i;\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- uint8 epType = 0u;\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
\r
- /* Set the endpoint buffer addresses */\r
- ep = USBFS_EP1;\r
- for (i = 0u; i < 0x80u; i+= 0x10u)\r
- {\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_DEFAULT);\r
- #if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- /* Enable all Arbiter EP Interrupts : err, buf under, buf over, dma gnt(mode2 only), in buf full */\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_INT_EN_IND + i), USBFS_ARB_EPX_INT_MASK);\r
- #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
+#if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ uint8 epType = 0u;\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
\r
- if(USBFS_EP[ep].epMode != USBFS_MODE_DISABLE)\r
+ /* Go thought all endpoints and set hardware configuration */\r
+ for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ++ep)\r
+ {\r
+ USBFS_ARB_EP_BASE.arbEp[ep].epCfg = USBFS_ARB_EPX_CFG_DEFAULT;\r
+ \r
+ #if (USBFS_EP_MANAGEMENT_DMA)\r
+ /* Enable arbiter endpoint interrupt sources */\r
+ USBFS_ARB_EP_BASE.arbEp[ep].epIntEn = USBFS_ARB_EPX_INT_MASK;\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA) */\r
+ \r
+ if (USBFS_EP[ep].epMode != USBFS_MODE_DISABLE)\r
{\r
- if((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u )\r
+ if (0u != (USBFS_EP[ep].addr & USBFS_DIR_IN))\r
{\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_IN);\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_IN;\r
+ \r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO && CY_PSOC4)\r
+ /* Clear DMA_TERMIN for IN endpoint. */\r
+ USBFS_ARB_EP_BASE.arbEp[ep].epIntEn &= (uint32) ~USBFS_ARB_EPX_INT_DMA_TERMIN;\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && CY_PSOC4) */\r
}\r
else\r
{\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_OUT);\r
- /* Prepare EP type mask for automatic memory allocation */\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- epType |= (uint8)(0x01u << (ep - USBFS_EP1));\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_OUT;\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* (CY_PSOC4): DMA_TERMIN for OUT endpoint is set above. */\r
+ \r
+ /* Prepare endpoint type mask. */\r
+ epType |= (uint8) (0x01u << (ep - USBFS_EP1));\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
}\r
}\r
else\r
{\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_STALL_DATA_EP);\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_STALL_DATA_EP;\r
}\r
+ \r
+ #if (!USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ #if (CY_PSOC4)\r
+ USBFS_ARB_EP16_BASE.arbEp[ep].rwRa16 = (uint32) USBFS_EP[ep].buffOffset;\r
+ USBFS_ARB_EP16_BASE.arbEp[ep].rwWa16 = (uint32) USBFS_EP[ep].buffOffset;\r
+ #else\r
+ USBFS_ARB_EP_BASE.arbEp[ep].rwRa = LO8(USBFS_EP[ep].buffOffset);\r
+ USBFS_ARB_EP_BASE.arbEp[ep].rwRaMsb = HI8(USBFS_EP[ep].buffOffset);\r
+ USBFS_ARB_EP_BASE.arbEp[ep].rwWa = LO8(USBFS_EP[ep].buffOffset);\r
+ USBFS_ARB_EP_BASE.arbEp[ep].rwWaMsb = HI8(USBFS_EP[ep].buffOffset);\r
+ #endif /* (CY_PSOC4) */\r
+ #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+ }\r
\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + i), USBFS_EP[ep].bufferSize >> 8u);\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + i), USBFS_EP[ep].bufferSize & 0xFFu);\r
+#if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* BUF_SIZE depend on DMA_THRESS value:0x55-32 bytes 0x44-16 bytes 0x33-8 bytes 0x22-4 bytes 0x11-2 bytes */\r
+ USBFS_BUF_SIZE_REG = USBFS_DMA_BUF_SIZE;\r
+\r
+ /* Configure DMA burst threshold */\r
+#if (CY_PSOC4)\r
+ USBFS_DMA_THRES16_REG = USBFS_DMA_BYTES_PER_BURST;\r
+#else\r
+ USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST;\r
+ USBFS_DMA_THRES_MSB_REG = 0u;\r
+#endif /* (CY_PSOC4) */\r
+ USBFS_EP_ACTIVE_REG = USBFS_DEFAULT_ARB_INT_EN;\r
+ USBFS_EP_TYPE_REG = epType;\r
+ \r
+ /* Cfg_cmp bit set to 1 once configuration is complete. */\r
+ /* Lock arbiter configtuation */\r
+ USBFS_ARB_CFG_REG |= (uint8) USBFS_ARB_CFG_CFG_CMP;\r
+ /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */\r
+ USBFS_ARB_CFG_REG &= (uint8) ~USBFS_ARB_CFG_CFG_CMP;\r
+\r
+#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
+\r
+ /* Enable interrupt SIE interurpt source from EP0-EP1 */\r
+ USBFS_SIE_EP_INT_EN_REG = (uint8) USBFS_DEFAULT_SIE_EP_INT_EN;\r
+}\r
\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu);\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu);\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);\r
- #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
\r
- ep++;\r
- }\r
+/*******************************************************************************\r
+* Function Name: USBFS_EpStateInit\r
+****************************************************************************//**\r
+*\r
+* This routine initialize state of Data end points based of its type: \r
+* IN - USBFS_IN_BUFFER_EMPTY (USBFS_EVENT_PENDING)\r
+* OUT - USBFS_OUT_BUFFER_EMPTY (USBFS_NO_EVENT_PENDING)\r
+*\r
+*******************************************************************************/\r
+void USBFS_EpStateInit(void) \r
+{\r
+ uint8 i;\r
\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- /* BUF_SIZE depend on DMA_THRESS value: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */\r
- USBFS_BUF_SIZE_REG = USBFS_DMA_BUF_SIZE;\r
- USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST; /* DMA burst threshold */\r
- USBFS_DMA_THRES_MSB_REG = 0u;\r
- USBFS_EP_ACTIVE_REG = USBFS_ARB_INT_MASK;\r
- USBFS_EP_TYPE_REG = epType;\r
- /* Cfg_cmp bit set to 1 once configuration is complete. */\r
- USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM |\r
- USBFS_ARB_CFG_CFG_CPM;\r
- /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */\r
- USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
-\r
- CY_SET_REG8(USBFS_SIE_EP_INT_EN_PTR, 0xFFu);\r
+ for (i = USBFS_EP1; i < USBFS_MAX_EP; i++)\r
+ { \r
+ if (0u != (USBFS_EP[i].addr & USBFS_DIR_IN))\r
+ {\r
+ /* IN Endpoint */\r
+ USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING;\r
+ }\r
+ else\r
+ {\r
+ /* OUT Endpoint */\r
+ USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING;\r
+ }\r
+ }\r
+ \r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_Config\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine configures endpoints for the entire configuration by scanning\r
* the configuration descriptor.\r
*\r
-* Parameters:\r
-* clearAltSetting: It configures the bAlternateSetting 0 for each interface.\r
-*\r
-* Return:\r
-* None.\r
+* \param clearAltSetting: It configures the bAlternateSetting 0 for each interface.\r
*\r
* USBFS_interfaceClass - Initialized class array for each interface.\r
* It is used for handling Class specific requests depend on interface class.\r
* Different classes in multiple Alternate settings does not supported.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_Config(uint8 clearAltSetting) \r
{\r
uint8 ep;\r
- uint8 cur_ep;\r
+ uint8 curEp;\r
uint8 i;\r
uint8 epType;\r
const uint8 *pDescr;\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
+ \r
+ #if (!USBFS_EP_MANAGEMENT_DMA_AUTO)\r
uint16 buffCount = 0u;\r
- #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
\r
const T_USBFS_LUT CYCODE *pTmp;\r
const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP;\r
\r
- /* Clear all of the endpoints */\r
- for (ep = 0u; ep < USBFS_MAX_EP; ep++)\r
+ /* Clear endpoints settings */\r
+ for (ep = 0u; ep < USBFS_MAX_EP; ++ep)\r
{\r
- USBFS_EP[ep].attrib = 0u;\r
- USBFS_EP[ep].hwEpState = 0u;\r
- USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING;\r
- USBFS_EP[ep].epToggle = 0u;\r
- USBFS_EP[ep].epMode = USBFS_MODE_DISABLE;\r
+ USBFS_EP[ep].attrib = 0u;\r
+ USBFS_EP[ep].hwEpState = 0u;\r
+ USBFS_EP[ep].epToggle = 0u;\r
USBFS_EP[ep].bufferSize = 0u;\r
- USBFS_EP[ep].interface = 0u;\r
-\r
+ USBFS_EP[ep].interface = 0u;\r
+ USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING;\r
+ USBFS_EP[ep].epMode = USBFS_MODE_DISABLE; \r
}\r
\r
- /* Clear Alternate settings for all interfaces */\r
- if(clearAltSetting != 0u)\r
+ /* Clear Alternate settings for all interfaces. */\r
+ if (0u != clearAltSetting)\r
{\r
- for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++)\r
+ for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; ++i)\r
{\r
- USBFS_interfaceSetting[i] = 0x00u;\r
- USBFS_interfaceSetting_last[i] = 0x00u;\r
+ USBFS_interfaceSetting[i] = 0u;\r
+ USBFS_interfaceSettingLast[i] = 0u;\r
}\r
}\r
\r
/* Init Endpoints and Device Status if configured */\r
- if(USBFS_configuration > 0u)\r
+ if (USBFS_configuration > 0u)\r
{\r
+ #if defined(USBFS_ENABLE_CDC_CLASS)\r
+ uint8 cdcComNums = 0u;\r
+ #endif /* (USBFS_ENABLE_CDC_CLASS) */ \r
+\r
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);\r
+ \r
/* Set Power status for current configuration */\r
pDescr = (const uint8 *)pTmp->p_list;\r
- if((pDescr[USBFS_CONFIG_DESCR_ATTRIB] & USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED) != 0u)\r
+ if ((pDescr[USBFS_CONFIG_DESCR_ATTRIB] & USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED) != 0u)\r
{\r
- USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED;\r
+ USBFS_deviceStatus |= (uint8) USBFS_DEVICE_STATUS_SELF_POWERED;\r
}\r
else\r
{\r
- USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_SELF_POWERED;\r
+ USBFS_deviceStatus &= (uint8) ~USBFS_DEVICE_STATUS_SELF_POWERED;\r
}\r
+ \r
/* Move to next element */\r
pTmp = &pTmp[1u];\r
ep = pTmp->c; /* For this table, c is the number of endpoints configurations */\r
\r
- #if ((USBFS_EP_MA == USBFS__MA_DYNAMIC) && \\r
- (USBFS_EP_MM == USBFS__EP_MANUAL) )\r
+ #if (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC)\r
/* Configure for dynamic EP memory allocation */\r
/* p_list points the endpoint setting table. */\r
pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list;\r
+ \r
for (i = 0u; i < ep; i++)\r
- {\r
+ { \r
/* Compare current Alternate setting with EP Alt */\r
- if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)\r
- {\r
- cur_ep = pEP->addr & USBFS_DIR_UNUSED;\r
+ if (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)\r
+ { \r
+ curEp = pEP->addr & USBFS_DIR_UNUSED;\r
epType = pEP->attributes & USBFS_EP_TYPE_MASK;\r
- if (pEP->addr & USBFS_DIR_IN)\r
+ \r
+ USBFS_EP[curEp].addr = pEP->addr;\r
+ USBFS_EP[curEp].attrib = pEP->attributes;\r
+ USBFS_EP[curEp].bufferSize = pEP->bufferSize;\r
+\r
+ if (0u != (pEP->addr & USBFS_DIR_IN))\r
{\r
/* IN Endpoint */\r
- USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;\r
- USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
- USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;\r
- #if defined(USBFS_ENABLE_CDC_CLASS)\r
- if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||\r
- (pEP->bMisc == USBFS_CLASS_CDC)) &&\r
- (epType != USBFS_EP_TYPE_INT))\r
- {\r
- USBFS_cdc_data_in_ep = cur_ep;\r
- }\r
- #endif /* USBFS_ENABLE_CDC_CLASS*/\r
- #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
- (USBFS_MIDI_IN_BUFF_SIZE > 0) )\r
- if((pEP->bMisc == USBFS_CLASS_AUDIO) &&\r
- (epType == USBFS_EP_TYPE_BULK))\r
- {\r
- USBFS_midi_in_ep = cur_ep;\r
- }\r
- #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
+ USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType);\r
+ USBFS_EP[curEp].apiEpState = USBFS_EVENT_PENDING;\r
+ \r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_IN_BUFF_SIZE > 0))\r
+ if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK))\r
+ {\r
+ USBFS_midi_in_ep = curEp;\r
+ }\r
+ #endif /* (USBFS_ENABLE_MIDI_STREAMING) */\r
}\r
else\r
{\r
/* OUT Endpoint */\r
- USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;\r
- USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
- USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;\r
- #if defined(USBFS_ENABLE_CDC_CLASS)\r
- if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||\r
- (pEP->bMisc == USBFS_CLASS_CDC)) &&\r
- (epType != USBFS_EP_TYPE_INT))\r
- {\r
- USBFS_cdc_data_out_ep = cur_ep;\r
- }\r
- #endif /* USBFS_ENABLE_CDC_CLASS*/\r
- #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
- (USBFS_MIDI_OUT_BUFF_SIZE > 0) )\r
- if((pEP->bMisc == USBFS_CLASS_AUDIO) &&\r
- (epType == USBFS_EP_TYPE_BULK))\r
- {\r
- USBFS_midi_out_ep = cur_ep;\r
- }\r
- #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
+ USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType);\r
+ USBFS_EP[curEp].apiEpState = USBFS_NO_EVENT_PENDING;\r
+ \r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_OUT_BUFF_SIZE > 0))\r
+ if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK))\r
+ {\r
+ USBFS_midi_out_ep = curEp;\r
+ }\r
+ #endif /* (USBFS_ENABLE_MIDI_STREAMING) */\r
+ }\r
+\r
+ #if(defined (USBFS_ENABLE_CDC_CLASS))\r
+ if((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||(pEP->bMisc == USBFS_CLASS_CDC))\r
+ {\r
+ cdcComNums = USBFS_Cdc_EpInit(pEP, curEp, cdcComNums);\r
}\r
- USBFS_EP[cur_ep].bufferSize = pEP->bufferSize;\r
- USBFS_EP[cur_ep].addr = pEP->addr;\r
- USBFS_EP[cur_ep].attrib = pEP->attributes;\r
+ #endif /* (USBFS_ENABLE_CDC_CLASS) */\r
}\r
+ \r
pEP = &pEP[1u];\r
}\r
- #else /* Configure for static EP memory allocation */\r
- for (i = USBFS_EP1; i < USBFS_MAX_EP; i++)\r
+ \r
+ #else\r
+ for (i = USBFS_EP1; i < USBFS_MAX_EP; ++i)\r
{\r
/* p_list points the endpoint setting table. */\r
pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list;\r
/* Find max length for each EP and select it (length could be different in different Alt settings) */\r
/* but other settings should be correct with regards to Interface alt Setting */\r
- for (cur_ep = 0u; cur_ep < ep; cur_ep++)\r
+ \r
+ for (curEp = 0u; curEp < ep; ++curEp)\r
{\r
- /* EP count is equal to EP # in table and we found larger EP length than have before*/\r
- if(i == (pEP->addr & USBFS_DIR_UNUSED))\r
+ if (i == (pEP->addr & USBFS_DIR_UNUSED))\r
{\r
- if(USBFS_EP[i].bufferSize < pEP->bufferSize)\r
+ /* Compare endpoint buffers size with current size to find greater. */\r
+ if (USBFS_EP[i].bufferSize < pEP->bufferSize)\r
{\r
USBFS_EP[i].bufferSize = pEP->bufferSize;\r
}\r
- /* Compare current Alternate setting with EP Alt*/\r
- if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)\r
- {\r
+ \r
+ /* Compare current Alternate setting with EP Alt */\r
+ if (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)\r
+ { \r
+ USBFS_EP[i].addr = pEP->addr;\r
+ USBFS_EP[i].attrib = pEP->attributes;\r
+ \r
epType = pEP->attributes & USBFS_EP_TYPE_MASK;\r
- if ((pEP->addr & USBFS_DIR_IN) != 0u)\r
+ \r
+ if (0u != (pEP->addr & USBFS_DIR_IN))\r
{\r
/* IN Endpoint */\r
+ USBFS_EP[i].epMode = USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType);\r
USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING;\r
- USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
- USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;\r
- /* Find and initialize CDC IN endpoint number */\r
- #if defined(USBFS_ENABLE_CDC_CLASS)\r
- if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||\r
- (pEP->bMisc == USBFS_CLASS_CDC)) &&\r
- (epType != USBFS_EP_TYPE_INT))\r
- {\r
- USBFS_cdc_data_in_ep = i;\r
- }\r
- #endif /* USBFS_ENABLE_CDC_CLASS*/\r
- #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
- (USBFS_MIDI_IN_BUFF_SIZE > 0) )\r
- if((pEP->bMisc == USBFS_CLASS_AUDIO) &&\r
- (epType == USBFS_EP_TYPE_BULK))\r
- {\r
- USBFS_midi_in_ep = i;\r
- }\r
- #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
+ \r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_IN_BUFF_SIZE > 0))\r
+ if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK))\r
+ {\r
+ USBFS_midi_in_ep = i;\r
+ }\r
+ #endif /* (USBFS_ENABLE_MIDI_STREAMING) */\r
}\r
else\r
{\r
/* OUT Endpoint */\r
+ USBFS_EP[i].epMode = USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType);\r
USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING;\r
- USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
- USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;\r
- /* Find and initialize CDC IN endpoint number */\r
- #if defined(USBFS_ENABLE_CDC_CLASS)\r
- if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||\r
- (pEP->bMisc == USBFS_CLASS_CDC)) &&\r
- (epType != USBFS_EP_TYPE_INT))\r
- {\r
- USBFS_cdc_data_out_ep = i;\r
- }\r
- #endif /* USBFS_ENABLE_CDC_CLASS*/\r
- #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
- (USBFS_MIDI_OUT_BUFF_SIZE > 0) )\r
- if((pEP->bMisc == USBFS_CLASS_AUDIO) &&\r
- (epType == USBFS_EP_TYPE_BULK))\r
- {\r
- USBFS_midi_out_ep = i;\r
- }\r
- #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
+ \r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_OUT_BUFF_SIZE > 0))\r
+ if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK))\r
+ {\r
+ USBFS_midi_out_ep = i;\r
+ }\r
+ #endif /* (USBFS_ENABLE_MIDI_STREAMING) */\r
}\r
- USBFS_EP[i].addr = pEP->addr;\r
- USBFS_EP[i].attrib = pEP->attributes;\r
\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- break; /* use first EP setting in Auto memory managment */\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #if (defined(USBFS_ENABLE_CDC_CLASS))\r
+ if((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||(pEP->bMisc == USBFS_CLASS_CDC))\r
+ {\r
+ cdcComNums = USBFS_Cdc_EpInit(pEP, i, cdcComNums);\r
+ }\r
+ #endif /* (USBFS_ENABLE_CDC_CLASS) */\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ break; /* Use first EP setting in Auto memory management */\r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
}\r
}\r
+ \r
pEP = &pEP[1u];\r
}\r
}\r
- #endif /* (USBFS_EP_MA == USBFS__MA_DYNAMIC) */\r
+ #endif /* (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC) */\r
\r
/* Init class array for each interface and interface number for each EP.\r
* It is used for handling Class specific requests directed to either an\r
pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list;\r
for (i = 0u; i < ep; i++)\r
{\r
- /* Configure interface number for each EP*/\r
+ /* Configure interface number for each EP */\r
USBFS_EP[pEP->addr & USBFS_DIR_UNUSED].interface = pEP->interface;\r
pEP = &pEP[1u];\r
}\r
- /* Init pointer on interface class table*/\r
+ \r
+ /* Init pointer on interface class table */\r
USBFS_interfaceClass = USBFS_GetInterfaceClassTablePtr();\r
- /* Set the endpoint buffer addresses */\r
-\r
- #if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ep++)\r
- {\r
- USBFS_EP[ep].buffOffset = buffCount;\r
- buffCount += USBFS_EP[ep].bufferSize;\r
- }\r
- #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ \r
+ /* Set the endpoint buffer addresses */\r
+ #if (!USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ buffCount = 0u;\r
+ for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ++ep)\r
+ {\r
+ USBFS_EP[ep].buffOffset = buffCount; \r
+ buffCount += USBFS_EP[ep].bufferSize;\r
+ \r
+ #if (USBFS_GEN_16BITS_EP_ACCESS)\r
+ /* Align EP buffers to be event size to access 16-bits DR register. */\r
+ buffCount += (0u != (buffCount & 0x01u)) ? 1u : 0u;\r
+ #endif /* (USBFS_GEN_16BITS_EP_ACCESS) */ \r
+ }\r
+ #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
\r
/* Configure hardware registers */\r
USBFS_ConfigReg();\r
- } /* USBFS_configuration > 0 */\r
+ }\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ConfigAltChanged\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine update configuration for the required endpoints only.\r
* It is called after SET_INTERFACE request when Static memory allocation used.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
void USBFS_ConfigAltChanged(void) \r
{\r
uint8 ep;\r
- uint8 cur_ep;\r
- uint8 i;\r
+ uint8 curEp;\r
uint8 epType;\r
- uint8 ri;\r
+ uint8 i;\r
+ uint8 interfaceNum;\r
\r
const T_USBFS_LUT CYCODE *pTmp;\r
const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP;\r
\r
-\r
/* Init Endpoints and Device Status if configured */\r
- if(USBFS_configuration > 0u)\r
+ if (USBFS_configuration > 0u)\r
{\r
+ /* Get number of endpoints configurations (ep). */\r
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);\r
pTmp = &pTmp[1u];\r
- ep = pTmp->c; /* For this table, c is the number of endpoints configurations */\r
+ ep = pTmp->c;\r
\r
- /* Do not touch EP which doesn't need reconfiguration */\r
- /* When Alt setting changed, the only required endpoints need to be reconfigured */\r
- /* p_list points the endpoint setting table. */\r
+ /* Get pointer to endpoints setting table (pEP). */\r
pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list;\r
+ \r
+ /* Look through all possible endpoint configurations. Find endpoints \r
+ * which belong to current interface and alternate settings for \r
+ * re-configuration.\r
+ */\r
+ interfaceNum = USBFS_interfaceNumber;\r
for (i = 0u; i < ep; i++)\r
{\r
- /*If Alt setting changed and new is same with EP Alt */\r
- if((USBFS_interfaceSetting[pEP->interface] !=\r
- USBFS_interfaceSetting_last[pEP->interface] ) &&\r
- (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) &&\r
- (pEP->interface == CY_GET_REG8(USBFS_wIndexLo)))\r
+ /* Find endpoints which belong to current interface and alternate settings. */\r
+ if ((interfaceNum == pEP->interface) && \r
+ (USBFS_interfaceSetting[interfaceNum] == pEP->altSetting))\r
{\r
- cur_ep = pEP->addr & USBFS_DIR_UNUSED;\r
- ri = ((cur_ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
- epType = pEP->attributes & USBFS_EP_TYPE_MASK;\r
- if ((pEP->addr & USBFS_DIR_IN) != 0u)\r
+ curEp = ((uint8) pEP->addr & USBFS_DIR_UNUSED);\r
+ epType = ((uint8) pEP->attributes & USBFS_EP_TYPE_MASK);\r
+ \r
+ /* Change the SIE mode for the selected EP to NAK ALL */\r
+ USBFS_EP[curEp].epToggle = 0u;\r
+ USBFS_EP[curEp].addr = pEP->addr;\r
+ USBFS_EP[curEp].attrib = pEP->attributes;\r
+ USBFS_EP[curEp].bufferSize = pEP->bufferSize;\r
+\r
+ if (0u != (pEP->addr & USBFS_DIR_IN))\r
{\r
/* IN Endpoint */\r
- USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;\r
- USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
- USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;\r
+ USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType);\r
+ USBFS_EP[curEp].apiEpState = USBFS_EVENT_PENDING;\r
}\r
else\r
{\r
/* OUT Endpoint */\r
- USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;\r
- USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
- USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;\r
+ USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType);\r
+ USBFS_EP[curEp].apiEpState = USBFS_NO_EVENT_PENDING;\r
}\r
- /* Change the SIE mode for the selected EP to NAK ALL */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN_OUT);\r
- USBFS_EP[cur_ep].bufferSize = pEP->bufferSize;\r
- USBFS_EP[cur_ep].addr = pEP->addr;\r
- USBFS_EP[cur_ep].attrib = pEP->attributes;\r
-\r
- /* Clear the data toggle */\r
- USBFS_EP[cur_ep].epToggle = 0u;\r
-\r
- /* Dynamic reconfiguration for mode 3 transfer */\r
- #if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- /* In_data_rdy for selected EP should be set to 0 */\r
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
-\r
- /* write the EP number for which reconfiguration is required */\r
- USBFS_DYN_RECONFIG_REG = (cur_ep - USBFS_EP1) <<\r
- USBFS_DYN_RECONFIG_EP_SHIFT;\r
- /* Set the dyn_config_en bit in dynamic reconfiguration register */\r
+ \r
+ /* Make SIE to NAK any endpoint requests */\r
+ USBFS_SIE_EP_BASE.sieEp[curEp].epCr0 = USBFS_MODE_NAK_IN_OUT;\r
+\r
+ #if (USBFS_EP_MANAGEMENT_DMA_AUTO)\r
+ /* Clear IN data ready. */\r
+ USBFS_ARB_EP_BASE.arbEp[curEp].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+\r
+ /* Select endpoint number of reconfiguration */\r
+ USBFS_DYN_RECONFIG_REG = (uint8) ((curEp - 1u) << USBFS_DYN_RECONFIG_EP_SHIFT);\r
+ \r
+ /* Request for dynamic re-configuration of endpoint. */\r
USBFS_DYN_RECONFIG_REG |= USBFS_DYN_RECONFIG_ENABLE;\r
- /* wait for the dyn_config_rdy bit to set by the block,\r
- * this bit will be set to 1 when block is ready for reconfiguration.\r
- */\r
- while((USBFS_DYN_RECONFIG_REG & USBFS_DYN_RECONFIG_RDY_STS) == 0u)\r
+ \r
+ /* Wait until block is ready for re-configuration */\r
+ while (0u == (USBFS_DYN_RECONFIG_REG & USBFS_DYN_RECONFIG_RDY_STS))\r
{\r
- ;\r
}\r
- /* Once dyn_config_rdy bit is set, FW can change the EP configuration. */\r
+ \r
+ /* Once DYN_RECONFIG_RDY_STS bit is set, FW can change the EP configuration. */\r
/* Change EP Type with new direction */\r
- if((pEP->addr & USBFS_DIR_IN) == 0u)\r
+ if (0u != (pEP->addr & USBFS_DIR_IN))\r
{\r
- USBFS_EP_TYPE_REG |= (uint8)(0x01u << (cur_ep - USBFS_EP1));\r
+ /* Set endpoint type: 0 - IN and 1 - OUT. */\r
+ USBFS_EP_TYPE_REG &= (uint8) ~(uint8)((uint8) 0x01u << (curEp - 1u));\r
+ \r
+ #if (CY_PSOC4)\r
+ /* Clear DMA_TERMIN for IN endpoint */\r
+ USBFS_ARB_EP_BASE.arbEp[curEp].epIntEn &= (uint32) ~USBFS_ARB_EPX_INT_DMA_TERMIN;\r
+ #endif /* (CY_PSOC4) */\r
}\r
else\r
{\r
- USBFS_EP_TYPE_REG &= (uint8)~(uint8)(0x01u << (cur_ep - USBFS_EP1));\r
+ /* Set endpoint type: 0 - IN and 1- OUT. */\r
+ USBFS_EP_TYPE_REG |= (uint8) ((uint8) 0x01u << (curEp - 1u));\r
+ \r
+ #if (CY_PSOC4)\r
+ /* Set DMA_TERMIN for OUT endpoint */\r
+ USBFS_ARB_EP_BASE.arbEp[curEp].epIntEn |= (uint32) USBFS_ARB_EPX_INT_DMA_TERMIN;\r
+ #endif /* (CY_PSOC4) */\r
}\r
- /* dynamic reconfiguration enable bit cleared, pointers and control/status\r
- * signals for the selected EP is cleared/re-initialized on negative edge\r
- * of dynamic reconfiguration enable bit).\r
+ \r
+ /* Complete dynamic re-configuration: all endpoint related status and signals \r
+ * are set into the default state.\r
*/\r
- USBFS_DYN_RECONFIG_REG &= (uint8)~USBFS_DYN_RECONFIG_ENABLE;\r
- /* The main loop has to re-enable DMA and OUT endpoint*/\r
+ USBFS_DYN_RECONFIG_REG &= (uint8) ~USBFS_DYN_RECONFIG_ENABLE;\r
+\r
#else\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri),\r
- USBFS_EP[cur_ep].bufferSize >> 8u);\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri),\r
- USBFS_EP[cur_ep].bufferSize & 0xFFu);\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + ri),\r
- USBFS_EP[cur_ep].buffOffset & 0xFFu);\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + ri),\r
- USBFS_EP[cur_ep].buffOffset >> 8u);\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ri),\r
- USBFS_EP[cur_ep].buffOffset & 0xFFu);\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ri),\r
- USBFS_EP[cur_ep].buffOffset >> 8u);\r
- #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ USBFS_SIE_EP_BASE.sieEp[curEp].epCnt0 = HI8(USBFS_EP[curEp].bufferSize);\r
+ USBFS_SIE_EP_BASE.sieEp[curEp].epCnt1 = LO8(USBFS_EP[curEp].bufferSize);\r
+ \r
+ #if (CY_PSOC4)\r
+ USBFS_ARB_EP16_BASE.arbEp[curEp].rwRa16 = (uint32) USBFS_EP[curEp].buffOffset;\r
+ USBFS_ARB_EP16_BASE.arbEp[curEp].rwWa16 = (uint32) USBFS_EP[curEp].buffOffset;\r
+ #else\r
+ USBFS_ARB_EP_BASE.arbEp[curEp].rwRa = LO8(USBFS_EP[curEp].buffOffset);\r
+ USBFS_ARB_EP_BASE.arbEp[curEp].rwRaMsb = HI8(USBFS_EP[curEp].buffOffset);\r
+ USBFS_ARB_EP_BASE.arbEp[curEp].rwWa = LO8(USBFS_EP[curEp].buffOffset);\r
+ USBFS_ARB_EP_BASE.arbEp[curEp].rwWaMsb = HI8(USBFS_EP[curEp].buffOffset);\r
+ #endif /* (CY_PSOC4) */ \r
+ #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */\r
}\r
- /* Get next EP element */\r
- pEP = &pEP[1u];\r
+ \r
+ pEP = &pEP[1u]; /* Get next EP element */\r
}\r
- } /* USBFS_configuration > 0 */\r
+ \r
+ /* The main loop has to re-enable DMA and OUT endpoint */\r
+ }\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_GetConfigTablePtr\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine returns a pointer a configuration table entry\r
*\r
-* Parameters:\r
-* confIndex: Configuration Index\r
+* \param confIndex: Configuration Index\r
*\r
-* Return:\r
-* Device Descriptor pointer or NULL when descriptor isn't exists.\r
+* \return\r
+* Device Descriptor pointer or NULL when descriptor does not exist.\r
*\r
*******************************************************************************/\r
const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)\r
pTmp = (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list;\r
\r
/* The first entry points to the Device Descriptor,\r
+ * the second entry point to the BOS Descriptor\r
* the rest configuration entries.\r
* Set pointer to the first Configuration Descriptor\r
*/\r
- pTmp = &pTmp[1u];\r
+ pTmp = &pTmp[2u];\r
/* For this table, c is the number of configuration descriptors */\r
if(confIndex >= pTmp->c) /* Verify that required configuration descriptor exists */\r
{\r
pTmp = (const T_USBFS_LUT CYCODE *) pTmp[confIndex].p_list;\r
}\r
\r
- return( pTmp );\r
+ return (pTmp);\r
}\r
\r
\r
+#if (USBFS_BOS_ENABLE)\r
+ /*******************************************************************************\r
+ * Function Name: USBFS_GetBOSPtr\r
+ ****************************************************************************//**\r
+ *\r
+ * This routine returns a pointer a BOS table entry\r
+ *\r
+ * \r
+ *\r
+ * \return\r
+ * BOS Descriptor pointer or NULL when descriptor does not exist.\r
+ *\r
+ *******************************************************************************/\r
+ const T_USBFS_LUT CYCODE *USBFS_GetBOSPtr(void)\r
+ \r
+ {\r
+ /* Device Table */\r
+ const T_USBFS_LUT CYCODE *pTmp;\r
+\r
+ pTmp = (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list;\r
+\r
+ /* The first entry points to the Device Descriptor,\r
+ * the second entry points to the BOS Descriptor\r
+ */\r
+ pTmp = &pTmp[1u];\r
+ pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list;\r
+ return (pTmp);\r
+ }\r
+#endif /* (USBFS_BOS_ENABLE) */\r
+\r
+\r
/*******************************************************************************\r
* Function Name: USBFS_GetDeviceTablePtr\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine returns a pointer to the Device table\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* Device Table pointer\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: USB_GetInterfaceClassTablePtr\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine returns Interface Class table pointer, which contains\r
* the relation between interface number and interface class.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* Interface Class table pointer.\r
*\r
*******************************************************************************/\r
uint8 currentInterfacesNum;\r
\r
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);\r
- if( pTmp != NULL )\r
+ if (pTmp != NULL)\r
{\r
currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];\r
/* Third entry in the LUT starts the Interface Table pointers */\r
pInterfaceClass = (const uint8 CYCODE *) NULL;\r
}\r
\r
- return( pInterfaceClass );\r
+ return (pInterfaceClass);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_TerminateEP\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function terminates the specified USBFS endpoint.\r
* This function should be used before endpoint reconfiguration.\r
*\r
-* Parameters:\r
-* Endpoint number.\r
+* \param ep Contains the data endpoint number.\r
*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
+* \sideeffect\r
+* \r
+* The device responds with a NAK for any transactions on the selected endpoint.\r
+* \r
*******************************************************************************/\r
-void USBFS_TerminateEP(uint8 ep) \r
+void USBFS_TerminateEP(uint8 epNumber) \r
{\r
- uint8 ri;\r
-\r
- ep &= USBFS_DIR_UNUSED;\r
- ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
+ /* Get endpoint number */\r
+ epNumber &= USBFS_DIR_UNUSED;\r
\r
- if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP))\r
+ if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
/* Set the endpoint Halt */\r
- USBFS_EP[ep].hwEpState |= (USBFS_ENDPOINT_STATUS_HALT);\r
+ USBFS_EP[epNumber].hwEpState |= USBFS_ENDPOINT_STATUS_HALT;\r
\r
/* Clear the data toggle */\r
- USBFS_EP[ep].epToggle = 0u;\r
- USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_ALLOWED;\r
+ USBFS_EP[epNumber].epToggle = 0u;\r
+ USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_ALLOWED;\r
\r
- if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u)\r
- {\r
+ if ((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u)\r
+ { \r
/* IN Endpoint */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN);\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_MODE_NAK_IN;\r
}\r
else\r
{\r
/* OUT Endpoint */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT);\r
+ USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_MODE_NAK_OUT;\r
}\r
}\r
}\r
\r
/*******************************************************************************\r
* Function Name: USBFS_SetEndpointHalt\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine handles set endpoint halt.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_SetEndpointHalt(void) \r
{\r
- uint8 ep;\r
- uint8 ri;\r
uint8 requestHandled = USBFS_FALSE;\r
-\r
+ uint8 ep;\r
+ \r
/* Set endpoint halt */\r
- ep = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED;\r
- ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
+ ep = USBFS_wIndexLoReg & USBFS_DIR_UNUSED;\r
\r
if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP))\r
{\r
if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u)\r
{\r
/* IN Endpoint */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_STALL_DATA_EP |\r
- USBFS_MODE_ACK_IN);\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = (USBFS_MODE_STALL_DATA_EP | \r
+ USBFS_MODE_ACK_IN);\r
}\r
else\r
{\r
/* OUT Endpoint */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_STALL_DATA_EP |\r
- USBFS_MODE_ACK_OUT);\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = (USBFS_MODE_STALL_DATA_EP | \r
+ USBFS_MODE_ACK_OUT);\r
}\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
}\r
\r
- return(requestHandled);\r
+ return (requestHandled);\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ClearEndpointHalt\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine handles clear endpoint halt.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_ClearEndpointHalt(void) \r
{\r
- uint8 ep;\r
- uint8 ri;\r
uint8 requestHandled = USBFS_FALSE;\r
+ uint8 ep;\r
\r
/* Clear endpoint halt */\r
- ep = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED;\r
- ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
+ ep = USBFS_wIndexLoReg & USBFS_DIR_UNUSED;\r
\r
if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP))\r
{\r
/* Clear the endpoint Halt */\r
- USBFS_EP[ep].hwEpState &= (uint8)~(USBFS_ENDPOINT_STATUS_HALT);\r
+ USBFS_EP[ep].hwEpState &= (uint8) ~USBFS_ENDPOINT_STATUS_HALT;\r
\r
/* Clear the data toggle */\r
USBFS_EP[ep].epToggle = 0u;\r
+ \r
/* Clear toggle bit for already armed packet */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), CY_GET_REG8(\r
- (reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) & (uint8)~USBFS_EPX_CNT_DATA_TOGGLE);\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCnt0 = (uint8) ~(uint8)USBFS_EPX_CNT_DATA_TOGGLE;\r
+ \r
/* Return API State as it was defined before */\r
- USBFS_EP[ep].apiEpState &= (uint8)~USBFS_NO_EVENT_ALLOWED;\r
+ USBFS_EP[ep].apiEpState &= (uint8) ~USBFS_NO_EVENT_ALLOWED;\r
\r
if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u)\r
{\r
/* IN Endpoint */\r
if(USBFS_EP[ep].apiEpState == USBFS_IN_BUFFER_EMPTY)\r
- { /* Wait for next packet from application */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN);\r
+ { \r
+ /* Wait for next packet from application */\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_IN;\r
}\r
else /* Continue armed transfer */\r
{\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_ACK_IN);\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_ACK_IN;\r
}\r
}\r
else\r
{\r
/* OUT Endpoint */\r
- if(USBFS_EP[ep].apiEpState == USBFS_OUT_BUFFER_FULL)\r
- { /* Allow application to read full buffer */\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT);\r
+ if (USBFS_EP[ep].apiEpState == USBFS_OUT_BUFFER_FULL)\r
+ { \r
+ /* Allow application to read full buffer */\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_OUT;\r
}\r
else /* Mark endpoint as empty, so it will be reloaded */\r
{\r
- CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_ACK_OUT);\r
+ USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_ACK_OUT;\r
}\r
}\r
+ \r
requestHandled = USBFS_InitNoDataControlTransfer();\r
}\r
\r
\r
/*******************************************************************************\r
* Function Name: USBFS_ValidateAlternateSetting\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Validates (and records) a SET INTERFACE request.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
uint8 USBFS_ValidateAlternateSetting(void) \r
{\r
- uint8 requestHandled = USBFS_TRUE;\r
+ uint8 requestHandled = USBFS_FALSE;\r
+ \r
uint8 interfaceNum;\r
+ uint8 curInterfacesNum;\r
const T_USBFS_LUT CYCODE *pTmp;\r
- uint8 currentInterfacesNum;\r
-\r
- interfaceNum = CY_GET_REG8(USBFS_wIndexLo);\r
- /* Validate interface setting, stall if invalid. */\r
+ \r
+ /* Get interface number from the request. */\r
+ interfaceNum = (uint8) USBFS_wIndexLoReg;\r
+ \r
+ /* Get number of interfaces for current configuration. */\r
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);\r
- currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];\r
+ curInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];\r
\r
- if((interfaceNum >= currentInterfacesNum) || (interfaceNum >= USBFS_MAX_INTERFACES_NUMBER))\r
- { /* Wrong interface number */\r
- requestHandled = USBFS_FALSE;\r
- }\r
- else\r
+ /* Validate that interface number is within range. */\r
+ if ((interfaceNum <= curInterfacesNum) || (interfaceNum <= USBFS_MAX_INTERFACES_NUMBER))\r
{\r
- /* Save current Alt setting to find out the difference in Config() function */\r
- USBFS_interfaceSetting_last[interfaceNum] = USBFS_interfaceSetting[interfaceNum];\r
- USBFS_interfaceSetting[interfaceNum] = CY_GET_REG8(USBFS_wValueLo);\r
+ /* Save current and new alternate settings (come with request) to make \r
+ * desicion about following endpoint re-configuration.\r
+ */\r
+ USBFS_interfaceSettingLast[interfaceNum] = USBFS_interfaceSetting[interfaceNum];\r
+ USBFS_interfaceSetting[interfaceNum] = (uint8) USBFS_wValueLoReg;\r
+ \r
+ requestHandled = USBFS_TRUE;\r
}\r
\r
return (requestHandled);\r
-/*******************************************************************************\r
-* File Name: USBFS_vnd.c\r
-* Version 2.80\r
-*\r
-* Description:\r
-* USB vendor request handler.\r
+/***************************************************************************//**\r
+* \file USBFS_vnd.c\r
+* \version 3.10\r
*\r
-* Note:\r
+* \brief\r
+* This file contains the USB vendor request handler.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#include "USBFS.h"\r
#include "USBFS_pvt.h"\r
\r
\r
#if(USBFS_EXTERN_VND == USBFS_FALSE)\r
\r
-\r
/***************************************\r
* Vendor Specific Declarations\r
***************************************/\r
\r
/*******************************************************************************\r
* Function Name: USBFS_HandleVendorRqst\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This routine provide users with a method to implement vendor specific\r
* requests.\r
*\r
* must set the variable "requestHandled" to TRUE, indicating that the\r
* request has been handled.\r
*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
+* \return\r
* requestHandled.\r
*\r
-* Reentrant:\r
+* \reentrant\r
* No.\r
*\r
*******************************************************************************/\r
{\r
uint8 requestHandled = USBFS_FALSE;\r
\r
- if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)\r
+ /* Check request direction: D2H or H2D. */\r
+ if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H))\r
{\r
- /* Control Read */\r
- switch (CY_GET_REG8(USBFS_bRequest))\r
+ /* Handle direction from device to host. */\r
+ \r
+ switch (USBFS_bRequestReg)\r
{\r
case USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR:\r
- #if defined(USBFS_ENABLE_MSOS_STRING)\r
- USBFS_currentTD.pData = (volatile uint8 *)&USBFS_MSOS_CONFIGURATION_DESCR[0u];\r
- USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u];\r
- requestHandled = USBFS_InitControlRead();\r
- #endif /* USBFS_ENABLE_MSOS_STRING */\r
+ #if defined(USBFS_ENABLE_MSOS_STRING)\r
+ USBFS_currentTD.pData = (volatile uint8 *) &USBFS_MSOS_CONFIGURATION_DESCR[0u];\r
+ USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u];\r
+ requestHandled = USBFS_InitControlRead();\r
+ #endif /* (USBFS_ENABLE_MSOS_STRING) */\r
break;\r
+ \r
default:\r
break;\r
}\r
/* `#END` */\r
\r
- #ifdef USBFS_HANDLE_VENDOR_RQST_CALLBACK\r
- USBFS_HandleVendorRqst_Callback();\r
- #endif /* USBFS_HANDLE_VENDOR_RQST_CALLBACK */\r
+#ifdef USBFS_HANDLE_VENDOR_RQST_CALLBACK\r
+ if (USBFS_FALSE == requestHandled)\r
+ {\r
+ requestHandled = USBFS_HandleVendorRqst_Callback();\r
+ }\r
+#endif /* (USBFS_HANDLE_VENDOR_RQST_CALLBACK) */\r
\r
- return(requestHandled);\r
+ return (requestHandled);\r
}\r
\r
\r
/* `#END` */\r
\r
+\r
#endif /* USBFS_EXTERN_VND */\r
\r
\r
SEARCH_DIR(.)\r
GROUP(-lgcc -lc -lnosys)\r
\r
+/* Code sharing support */\r
+INCLUDE cycodeshareexport.ld\r
+INCLUDE cycodeshareimport.ld\r
+\r
\r
MEMORY\r
{\r
- rom (rx) : ORIGIN = 0x0, LENGTH = 131072\r
- ram (rwx) : ORIGIN = 0x20000000 - (32768 / 2), LENGTH = 32768\r
+ rom (rx) : ORIGIN = 0x0, LENGTH = 131072\r
+ ram (rwx) : ORIGIN = 0x20000000 - (32768 / 2), LENGTH = 32768\r
}\r
\r
\r
-CY_APPL_ORIGIN = 0; \r
+CY_APPL_ORIGIN = 0;\r
CY_FLASH_ROW_SIZE = 256;\r
CY_ECC_ROW_SIZE = 32;\r
CY_EE_IN_BTLDR = 0x00;\r
CY_APPL_NUM = 1;\r
CY_APPL_MAX = 1;\r
CY_METADATA_SIZE = 64;\r
+CY_APPL_LOADABLE = 1;\r
+CY_CHECKSUM_EXCLUDE_SIZE = ALIGN(0, CY_FLASH_ROW_SIZE);\r
\r
\r
/* These force the linker to search for particular symbols from\r
\r
SECTIONS\r
{\r
- /* The bootloader location */\r
- .cybootloader 0x0 : { KEEP(*(.cybootloader)) } >rom\r
-\r
- /* Calculate where the loadables should start */\r
- appl1_start = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : ALIGN(CY_FLASH_ROW_SIZE);\r
- appl2_start = appl1_start + ALIGN((LENGTH(rom) - appl1_start - 2 * CY_FLASH_ROW_SIZE) / 2, CY_FLASH_ROW_SIZE);\r
- appl_start = (CY_APPL_NUM == 1) ? appl1_start : appl2_start;\r
- ecc_offset = (appl_start / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE;\r
- ee_offset = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0;\r
- ee_size = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE;\r
- PROVIDE(CY_ECC_OFFSET = ecc_offset);\r
- \r
- .text appl_start :\r
- {\r
- CREATE_OBJECT_SYMBOLS\r
- PROVIDE(__cy_interrupt_vector = RomVectors);\r
-\r
- *(.romvectors)\r
-\r
- /* Make sure we pulled in an interrupt vector. */\r
- ASSERT (. != __cy_interrupt_vector, "No interrupt vector");\r
-\r
- ASSERT (CY_APPL_ORIGIN ? (SIZEOF(.cybootloader) <= CY_APPL_ORIGIN) : 1, "Wrong image location");\r
-\r
- PROVIDE(__cy_reset = Reset);\r
- *(.text.Reset)\r
- /* Make sure we pulled in some reset code. */\r
- ASSERT (. != __cy_reset, "No reset code");\r
-\r
- /* Place DMA initialization before text to ensure it gets placed in first 64K of flash */\r
- *(.dma_init)\r
- ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");\r
- \r
- *(.text .text.* .gnu.linkonce.t.*)\r
- *(.plt)\r
- *(.gnu.warning)\r
- *(.glue_7t) *(.glue_7) *(.vfp11_veneer)\r
- \r
- KEEP(*(.bootloader)) /* necessary for bootloader's, but doesn't impact non-bootloaders */\r
-\r
- *(.ARM.extab* .gnu.linkonce.armextab.*)\r
- *(.gcc_except_table)\r
- } >rom\r
- .eh_frame_hdr : ALIGN (4)\r
- {\r
- KEEP (*(.eh_frame_hdr))\r
- } >rom\r
- .eh_frame : ALIGN (4)\r
- {\r
- KEEP (*(.eh_frame))\r
- } >rom\r
- /* .ARM.exidx is sorted, so has to go in its own output section. */\r
- PROVIDE_HIDDEN (__exidx_start = .);\r
- .ARM.exidx :\r
- {\r
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
- } >rom\r
- __exidx_end = .;\r
- .rodata : ALIGN (4)\r
- {\r
- *(.rodata .rodata.* .gnu.linkonce.r.*)\r
-\r
- . = ALIGN(4);\r
- KEEP(*(.init))\r
-\r
- . = ALIGN(4);\r
- __preinit_array_start = .;\r
- KEEP (*(.preinit_array))\r
- __preinit_array_end = .;\r
-\r
- . = ALIGN(4);\r
- __init_array_start = .;\r
- KEEP (*(SORT(.init_array.*)))\r
- KEEP (*(.init_array))\r
- __init_array_end = .;\r
-\r
- . = ALIGN(4);\r
- KEEP(*(.fini))\r
-\r
- . = ALIGN(4);\r
- __fini_array_start = .;\r
- KEEP (*(.fini_array))\r
- KEEP (*(SORT(.fini_array.*)))\r
- __fini_array_end = .;\r
-\r
- . = ALIGN(0x4);\r
- KEEP (*crtbegin.o(.ctors))\r
- KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r
- KEEP (*(SORT(.ctors.*)))\r
- KEEP (*crtend.o(.ctors))\r
-\r
- . = ALIGN(0x4);\r
- KEEP (*crtbegin.o(.dtors))\r
- KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r
- KEEP (*(SORT(.dtors.*)))\r
- KEEP (*crtend.o(.dtors))\r
-\r
- . = ALIGN(4);\r
- __cy_regions = .;\r
- LONG (__cy_region_init_ram)\r
- LONG (__cy_region_start_data)\r
- LONG (__cy_region_init_size_ram)\r
- LONG (__cy_region_zero_size_ram)\r
- __cy_regions_end = .;\r
-\r
- . = ALIGN (8);\r
- _etext = .;\r
- } >rom\r
+ /* The bootloader location */\r
+ .cybootloader 0x0 : { KEEP(*(.cybootloader)) } >rom\r
+\r
+ /* Calculate where the loadables should start */\r
+ appl1_start = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : ALIGN(CY_FLASH_ROW_SIZE);\r
+ appl2_start = appl1_start + ALIGN((LENGTH(rom) - appl1_start - 2 * CY_FLASH_ROW_SIZE) / 2, CY_FLASH_ROW_SIZE);\r
+ appl_start = (CY_APPL_NUM == 1) ? appl1_start : appl2_start;\r
+ ecc_offset = (appl_start / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE;\r
+ ee_offset = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0;\r
+ ee_size = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE;\r
+ PROVIDE(CY_ECC_OFFSET = ecc_offset);\r
+\r
+ .text appl_start :\r
+ {\r
+ CREATE_OBJECT_SYMBOLS\r
+ PROVIDE(__cy_interrupt_vector = RomVectors);\r
+\r
+ *(.romvectors)\r
+\r
+ /* Make sure we pulled in an interrupt vector. */\r
+ ASSERT (. != __cy_interrupt_vector, "No interrupt vector");\r
+\r
+ ASSERT (CY_APPL_ORIGIN ? (SIZEOF(.cybootloader) <= CY_APPL_ORIGIN) : 1, "Wrong image location");\r
+\r
+ PROVIDE(__cy_reset = Reset);\r
+ *(.text.Reset)\r
+ /* Make sure we pulled in some reset code. */\r
+ ASSERT (. != __cy_reset, "No reset code");\r
\r
- .ramvectors (NOLOAD) : ALIGN(8)\r
- {\r
- __cy_region_start_ram = .;\r
- KEEP(*(.ramvectors))\r
- }\r
-\r
- .noinit (NOLOAD) : ALIGN(8)\r
- {\r
- KEEP(*(.noinit))\r
- }\r
-\r
- .data : ALIGN(8)\r
- {\r
- __cy_region_start_data = .;\r
-\r
- KEEP(*(.jcr))\r
- *(.got.plt) *(.got)\r
- *(.shdata)\r
- *(.data .data.* .gnu.linkonce.d.*)\r
- . = ALIGN (8);\r
- *(.ram)\r
- _edata = .;\r
- } >ram AT>rom\r
- .bss : ALIGN(8)\r
- {\r
- PROVIDE(__bss_start__ = .);\r
- *(.shbss)\r
- *(.bss .bss.* .gnu.linkonce.b.*)\r
- *(COMMON)\r
- . = ALIGN (8);\r
- *(.ram.b)\r
- _end = .;\r
- __end = .;\r
- } >ram AT>rom\r
- PROVIDE(end = .);\r
- PROVIDE(__bss_end__ = .);\r
- \r
- __cy_region_init_ram = LOADADDR (.data);\r
- __cy_region_init_size_ram = _edata - ADDR (.data);\r
- __cy_region_zero_size_ram = _end - _edata;\r
- \r
- /* The .stack and .heap sections don't contain any symbols. \r
- * They are only used for linker to calculate RAM utilization.\r
- */\r
- .heap (NOLOAD) :\r
- {\r
- . = _end;\r
- . += 0x0400;\r
- __cy_heap_limit = .;\r
- } >ram\r
-\r
- .stack (__cy_stack - 0x1000) (NOLOAD) :\r
- {\r
- __cy_stack_limit = .;\r
- . += 0x1000;\r
- } >ram\r
- \r
- /* Check if data + heap + stack exceeds RAM limit */\r
- ASSERT(__cy_stack_limit >= __cy_heap_limit, "region RAM overflowed with stack")\r
-\r
- .cyloadermeta ((appl_start == 0) ? (LENGTH(rom) - CY_METADATA_SIZE) : 0xF0000000) :\r
- {\r
- KEEP(*(.cyloadermeta))\r
- } :NONE\r
-\r
- .cyloadablemeta (LENGTH(rom) - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) :\r
- {\r
- KEEP(*(.cyloadablemeta))\r
+ /* Place DMA initialization before text to ensure it gets placed in first 64K of flash */\r
+ *(.dma_init)\r
+ ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");\r
+\r
+ *(.text .text.* .gnu.linkonce.t.*)\r
+ *(.plt)\r
+ *(.gnu.warning)\r
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)\r
+\r
+ KEEP(*(.bootloader)) /* necessary for bootloader's, but doesn't impact non-bootloaders */\r
+\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+ *(.gcc_except_table)\r
} >rom\r
\r
- .cyconfigecc (0x80000000 + ecc_offset) : \r
- {\r
- KEEP(*(.cyconfigecc))\r
- } :NONE \r
-\r
- .cycustnvl 0x90000000 : { KEEP(*(.cycustnvl)) } :NONE \r
- .cywolatch 0x90100000 : { KEEP(*(.cywolatch)) } :NONE \r
-\r
- .cyeeprom (0x90200000 + ee_offset) : \r
- {\r
- KEEP(*(.cyeeprom))\r
- ASSERT(. <= (0x90200000 + ee_offset + ee_size), ".cyeeprom data will not fit in EEPROM");\r
- } :NONE \r
-\r
- .cyflashprotect 0x90400000 : { KEEP(*(.cyflashprotect)) } :NONE \r
- .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE \r
-\r
- .stab 0 (NOLOAD) : { *(.stab) }\r
- .stabstr 0 (NOLOAD) : { *(.stabstr) }\r
- /* DWARF debug sections.\r
- * Symbols in the DWARF debugging sections are relative to the beginning\r
- * of the section so we begin them at 0.\r
- */\r
- /* DWARF 1 */\r
- .debug 0 : { *(.debug) }\r
- .line 0 : { *(.line) }\r
- /* GNU DWARF 1 extensions */\r
- .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
- .debug_sfnames 0 : { *(.debug_sfnames) }\r
- /* DWARF 1.1 and DWARF 2 */\r
- .debug_aranges 0 : { *(.debug_aranges) }\r
- .debug_pubnames 0 : { *(.debug_pubnames) }\r
- /* DWARF 2 */\r
- .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
- .debug_abbrev 0 : { *(.debug_abbrev) }\r
- .debug_line 0 : { *(.debug_line) }\r
- .debug_frame 0 : { *(.debug_frame) }\r
- .debug_str 0 : { *(.debug_str) }\r
- .debug_loc 0 : { *(.debug_loc) }\r
- .debug_macinfo 0 : { *(.debug_macinfo) }\r
- /* DWARF 2.1 */\r
- .debug_ranges 0 : { *(.debug_ranges) }\r
- /* SGI/MIPS DWARF 2 extensions */\r
- .debug_weaknames 0 : { *(.debug_weaknames) }\r
- .debug_funcnames 0 : { *(.debug_funcnames) }\r
- .debug_typenames 0 : { *(.debug_typenames) }\r
- .debug_varnames 0 : { *(.debug_varnames) }\r
-\r
- .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\r
- .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }\r
- /DISCARD/ : { *(.note.GNU-stack) }\r
+\r
+ .eh_frame_hdr : ALIGN (4)\r
+ {\r
+ KEEP (*(.eh_frame_hdr))\r
+ } >rom\r
+\r
+\r
+ .eh_frame : ALIGN (4)\r
+ {\r
+ KEEP (*(.eh_frame))\r
+ } >rom\r
+\r
+\r
+ /* .ARM.exidx is sorted, so has to go in its own output section. */\r
+ PROVIDE_HIDDEN (__exidx_start = .);\r
+ .ARM.exidx :\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } >rom\r
+ __exidx_end = .;\r
+\r
+\r
+ .rodata : ALIGN (4)\r
+ {\r
+ *(.rodata .rodata.* .gnu.linkonce.r.*)\r
+\r
+ . = ALIGN(4);\r
+ KEEP(*(.init))\r
+\r
+ . = ALIGN(4);\r
+ __preinit_array_start = .;\r
+ KEEP (*(.preinit_array))\r
+ __preinit_array_end = .;\r
+\r
+ . = ALIGN(4);\r
+ __init_array_start = .;\r
+ KEEP (*(SORT(.init_array.*)))\r
+ KEEP (*(.init_array))\r
+ __init_array_end = .;\r
+\r
+ . = ALIGN(4);\r
+ KEEP(*(.fini))\r
+\r
+ . = ALIGN(4);\r
+ __fini_array_start = .;\r
+ KEEP (*(.fini_array))\r
+ KEEP (*(SORT(.fini_array.*)))\r
+ __fini_array_end = .;\r
+\r
+ . = ALIGN(0x4);\r
+ KEEP (*crtbegin.o(.ctors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r
+ KEEP (*(SORT(.ctors.*)))\r
+ KEEP (*crtend.o(.ctors))\r
+\r
+ . = ALIGN(0x4);\r
+ KEEP (*crtbegin.o(.dtors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r
+ KEEP (*(SORT(.dtors.*)))\r
+ KEEP (*crtend.o(.dtors))\r
+\r
+ . = ALIGN(4);\r
+ __cy_regions = .;\r
+ LONG (__cy_region_init_ram)\r
+ LONG (__cy_region_start_data)\r
+ LONG (__cy_region_init_size_ram)\r
+ LONG (__cy_region_zero_size_ram)\r
+ __cy_regions_end = .;\r
+\r
+ . = ALIGN (8);\r
+ _etext = .;\r
+ } >rom\r
+\r
+\r
+ /***************************************************************************\r
+ * Checksum Exclude Section for non-bootloadable projects. See below.\r
+ ***************************************************************************/\r
+ \r
+\r
+\r
+ .ramvectors (NOLOAD) : ALIGN(8)\r
+ {\r
+ __cy_region_start_ram = .;\r
+ KEEP(*(.ramvectors))\r
+ }\r
+\r
+\r
+ .noinit (NOLOAD) : ALIGN(8)\r
+ {\r
+ KEEP(*(.noinit))\r
+ }\r
+\r
+\r
+ .data : ALIGN(8)\r
+ {\r
+ __cy_region_start_data = .;\r
+\r
+ KEEP(*(.jcr))\r
+ *(.got.plt) *(.got)\r
+ *(.shdata)\r
+ *(.data .data.* .gnu.linkonce.d.*)\r
+ . = ALIGN (8);\r
+ *(.ram)\r
+ _edata = .;\r
+ } >ram AT>rom\r
+\r
+\r
+ .bss : ALIGN(8)\r
+ {\r
+ PROVIDE(__bss_start__ = .);\r
+ *(.shbss)\r
+ *(.bss .bss.* .gnu.linkonce.b.*)\r
+ *(COMMON)\r
+ . = ALIGN (8);\r
+ *(.ram.b)\r
+ _end = .;\r
+ __end = .;\r
+ } >ram AT>rom\r
+\r
+\r
+ PROVIDE(end = .);\r
+ PROVIDE(__bss_end__ = .);\r
+\r
+ __cy_region_init_ram = LOADADDR (.data);\r
+ __cy_region_init_size_ram = _edata - ADDR (.data);\r
+ __cy_region_zero_size_ram = _end - _edata;\r
+\r
+ /* The .stack and .heap sections don't contain any symbols.\r
+ * They are only used for linker to calculate RAM utilization.\r
+ */\r
+ .heap (NOLOAD) :\r
+ {\r
+ . = _end;\r
+ . += 0x0400;\r
+ __cy_heap_limit = .;\r
+ } >ram\r
+\r
+ .stack (__cy_stack - 0x1000) (NOLOAD) :\r
+ {\r
+ __cy_stack_limit = .;\r
+ . += 0x1000;\r
+ } >ram\r
+\r
+ /* Check if data + heap + stack exceeds RAM limit */\r
+ ASSERT(__cy_stack_limit >= __cy_heap_limit, "region RAM overflowed with stack")\r
+\r
+\r
+ /***************************************************************************\r
+ * Checksum Exclude Section\r
+ ***************************************************************************\r
+ *\r
+ * For the normal and bootloader projects this section is placed at any\r
+ * place. For the Bootloadable applications, it is placed at the specific\r
+ * address.\r
+ *\r
+ * Case # 1. Bootloadable application\r
+ *\r
+ * _______________________________\r
+ * | Metadata (BTLDBL) |\r
+ * |-------------------------------|\r
+ * | Checksum Exclude (BTLDBL) |\r
+ * |-------------------------------|\r
+ * | |\r
+ * | |\r
+ * | |\r
+ * |-------------------------------|\r
+ * | |\r
+ * | |\r
+ * | |\r
+ * | BTLDBL |\r
+ * | |\r
+ * | |\r
+ * | |\r
+ * |-------------------------------|\r
+ * | |\r
+ * | BTLDR |\r
+ * |_______________________________|\r
+ *\r
+ *\r
+ * Case # 2. Bootloadable application for Dual-Application Bootloader\r
+ *\r
+ * _______________________________\r
+ * | Metadata (BTLDBL # 1) |\r
+ * |-------------------------------|\r
+ * | Metadata (BTLDBL # 2) |\r
+ * |-------------------------------|\r
+ * | Checksum Exclude (BTLDBL # 2) |\r
+ * |-------------------------------|\r
+ * | |\r
+ * | |\r
+ * | |\r
+ * |-------------------------------|\r
+ * | |\r
+ * | BTLDBL # 2 |\r
+ * |_______________________________|____BTLDBL # 2 Start address___\r
+ * | Checksum Exclude (BTLDBL # 1) |\r
+ * |-------------------------------|\r
+ * | |\r
+ * | |\r
+ * | |\r
+ * |-------------------------------|\r
+ * | |\r
+ * | BTLDBL # 1 |\r
+ * | |\r
+ * |-------------------------------|\r
+ * | BTLDR |\r
+ * |_______________________________|\r
+ */\r
+ .cy_checksum_exclude ((LENGTH(rom) - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE): { KEEP(*(.cy_checksum_exclude)) }\r
+\r
+\r
+ /* Bootloadable applications only: verify that size of the data in the section is within the specified limit. */\r
+ cy_checksum_exclude_size = (CY_APPL_LOADABLE == 1) ? SIZEOF(.cy_checksum_exclude) : 0;\r
+ ASSERT(cy_checksum_exclude_size <= CY_CHECKSUM_EXCLUDE_SIZE, "CY_BOOT: Section .cy_checksum_exclude size exceedes specified limit.")\r
+\r
+\r
+ .cyloadermeta ((appl_start == 0) ? (LENGTH(rom) - CY_METADATA_SIZE) : 0xF0000000) :\r
+ {\r
+ KEEP(*(.cyloadermeta))\r
+ } :NONE\r
+\r
+ .cyloadablemeta (LENGTH(rom) - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) :\r
+ {\r
+ KEEP(*(.cyloadablemeta))\r
+ } >rom\r
+\r
+\r
+ .cyconfigecc (0x80000000 + ecc_offset) :\r
+ {\r
+ KEEP(*(.cyconfigecc))\r
+ } :NONE\r
+\r
+ .cycustnvl 0x90000000 : { KEEP(*(.cycustnvl)) } :NONE\r
+ .cywolatch 0x90100000 : { KEEP(*(.cywolatch)) } :NONE\r
+\r
+ .cyeeprom (0x90200000 + ee_offset) :\r
+ {\r
+ KEEP(*(.cyeeprom))\r
+ ASSERT(. <= (0x90200000 + ee_offset + ee_size), ".cyeeprom data will not fit in EEPROM");\r
+ } :NONE\r
+\r
+ .cyflashprotect 0x90400000 : { KEEP(*(.cyflashprotect)) } :NONE\r
+ .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE\r
+\r
+ .stab 0 (NOLOAD) : { *(.stab) }\r
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }\r
+ /* DWARF debug sections.\r
+ * Symbols in the DWARF debugging sections are relative to the beginning\r
+ * of the section so we begin them at 0.\r
+ */\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+ /* DWARF 2.1 */\r
+ .debug_ranges 0 : { *(.debug_ranges) }\r
+ /* SGI/MIPS DWARF 2 extensions */\r
+ .debug_weaknames 0 : { *(.debug_weaknames) }\r
+ .debug_funcnames 0 : { *(.debug_funcnames) }\r
+ .debug_typenames 0 : { *(.debug_typenames) }\r
+ .debug_varnames 0 : { *(.debug_varnames) }\r
+\r
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\r
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }\r
+ /DISCARD/ : { *(.note.GNU-stack) }\r
}\r
\r
--- /dev/null
+/**************************************************************************//**
+ * @file cmsis_armcc.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+ \return xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+ register uint32_t __regBasePriMax __ASM("basepri_max");
+ __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0U);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+#define __ISB() do {\
+ __schedule_barrier();\
+ __isb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+ __schedule_barrier();\
+ __dsb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+ __schedule_barrier();\
+ __dmb(0xF);\
+ __schedule_barrier();\
+ } while (0U)
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+#endif
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+#define __ROR __ror
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __breakpoint(value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+ #define __RBIT __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+ return(result);
+}
+#endif
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+#else
+ #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+#else
+ #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+#else
+ #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXB(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXH(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+ #define __STREXW(value, ptr) __strex(value, ptr)
+#else
+ #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
+#endif
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX __clrex
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+ rrx r0, r0
+ bx lr
+}
+#endif
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRBT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRHT(value, ptr) __strt(value, ptr)
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+#define __STRT(value, ptr) __strt(value, ptr)
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
+
+#define __SADD8 __sadd8
+#define __QADD8 __qadd8
+#define __SHADD8 __shadd8
+#define __UADD8 __uadd8
+#define __UQADD8 __uqadd8
+#define __UHADD8 __uhadd8
+#define __SSUB8 __ssub8
+#define __QSUB8 __qsub8
+#define __SHSUB8 __shsub8
+#define __USUB8 __usub8
+#define __UQSUB8 __uqsub8
+#define __UHSUB8 __uhsub8
+#define __SADD16 __sadd16
+#define __QADD16 __qadd16
+#define __SHADD16 __shadd16
+#define __UADD16 __uadd16
+#define __UQADD16 __uqadd16
+#define __UHADD16 __uhadd16
+#define __SSUB16 __ssub16
+#define __QSUB16 __qsub16
+#define __SHSUB16 __shsub16
+#define __USUB16 __usub16
+#define __UQSUB16 __uqsub16
+#define __UHSUB16 __uhsub16
+#define __SASX __sasx
+#define __QASX __qasx
+#define __SHASX __shasx
+#define __UASX __uasx
+#define __UQASX __uqasx
+#define __UHASX __uhasx
+#define __SSAX __ssax
+#define __QSAX __qsax
+#define __SHSAX __shsax
+#define __USAX __usax
+#define __UQSAX __uqsax
+#define __UHSAX __uhsax
+#define __USAD8 __usad8
+#define __USADA8 __usada8
+#define __SSAT16 __ssat16
+#define __USAT16 __usat16
+#define __UXTB16 __uxtb16
+#define __UXTAB16 __uxtab16
+#define __SXTB16 __sxtb16
+#define __SXTAB16 __sxtab16
+#define __SMUAD __smuad
+#define __SMUADX __smuadx
+#define __SMLAD __smlad
+#define __SMLADX __smladx
+#define __SMLALD __smlald
+#define __SMLALDX __smlaldx
+#define __SMUSD __smusd
+#define __SMUSDX __smusdx
+#define __SMLSD __smlsd
+#define __SMLSDX __smlsdx
+#define __SMLSLD __smlsld
+#define __SMLSLDX __smlsldx
+#define __SEL __sel
+#define __QADD __qadd
+#define __QSUB __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
+ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
+
+#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
+ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
+
+#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+ ((int64_t)(ARG3) << 32U) ) >> 32U))
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
--- /dev/null
+/**************************************************************************//**
+ * @file cmsis_gcc.h
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+#endif
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+/**
+ \brief Enable IRQ Interrupts
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+ \brief Disable IRQ Interrupts
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+ \brief Get Control Register
+ \details Returns the content of the Control Register.
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Control Register
+ \details Writes the given value to the Control Register.
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+/**
+ \brief Get IPSR Register
+ \details Returns the content of the IPSR Register.
+ \return IPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get APSR Register
+ \details Returns the content of the APSR Register.
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get xPSR Register
+ \details Returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Get Process Stack Pointer
+ \details Returns the current value of the Process Stack Pointer (PSP).
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Process Stack Pointer
+ \details Assigns the given value to the Process Stack Pointer (PSP).
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
+}
+
+
+/**
+ \brief Get Main Stack Pointer
+ \details Returns the current value of the Main Stack Pointer (MSP).
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Main Stack Pointer
+ \details Assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
+}
+
+
+/**
+ \brief Get Priority Mask
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Priority Mask
+ \details Assigns the given value to the Priority Mask Register.
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (__CORTEX_M >= 0x03U)
+
+/**
+ \brief Enable FIQ
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+ \brief Disable FIQ
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+ \brief Get Base Priority
+ \details Returns the current value of the Base Priority register.
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Base Priority
+ \details Assigns the given value to the Base Priority register.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+ \brief Set Base Priority with condition
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+ or the new value increases the BASEPRI priority level.
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
+{
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
+}
+
+
+/**
+ \brief Get Fault Mask
+ \details Returns the current value of the Fault Mask register.
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/**
+ \brief Set Fault Mask
+ \details Assigns the given value to the Fault Mask register.
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+#endif /* (__CORTEX_M >= 0x03U) */
+
+
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
+
+/**
+ \brief Get FPSCR
+ \details Returns the current value of the Floating Point Status/Control register.
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ uint32_t result;
+
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ __ASM volatile ("");
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/**
+ \brief Set FPSCR
+ \details Assigns the given value to the Floating Point Status/Control register.
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
+ /* Empty asm statement works as a scheduling barrier */
+ __ASM volatile ("");
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
+ __ASM volatile ("");
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
+
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+ \brief No Operation
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/**
+ \brief Wait For Interrupt
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/**
+ \brief Wait For Event
+ \details Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/**
+ \brief Send Event
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/**
+ \brief Instruction Synchronization Barrier
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or memory,
+ after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+ __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Synchronization Barrier
+ \details Acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+ \brief Data Memory Barrier
+ \details Ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+ \brief Reverse byte order (32 bit)
+ \details Reverses the byte order in integer value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+ return __builtin_bswap32(value);
+#else
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Reverse byte order (16 bit)
+ \details Reverses the byte order in two unsigned short values.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief Reverse byte order in signed short value
+ \details Reverses the byte order in a signed short value with sign extension to integer.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ return (short)__builtin_bswap16(value);
+#else
+ int32_t result;
+
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+#endif
+}
+
+
+/**
+ \brief Rotate Right in unsigned value (32 bit)
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+ \param [in] value Value to rotate
+ \param [in] value Number of Bits to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+ return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+ \brief Breakpoint
+ \details Causes the processor to enter Debug state.
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+ \param [in] value is ignored by the processor.
+ If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value) __ASM volatile ("bkpt "#value)
+
+
+/**
+ \brief Reverse bit order of value
+ \details Reverses the bit order of the given value.
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
+
+ result = value; /* r will be reversed bits of v; first get LSB of v */
+ for (value >>= 1U; value; value >>= 1U)
+ {
+ result <<= 1U;
+ result |= value & 1U;
+ s--;
+ }
+ result <<= s; /* shift when v's highest bits are zero */
+#endif
+ return(result);
+}
+
+
+/**
+ \brief Count leading zeros
+ \details Counts the number of leading zeros of a data value.
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __builtin_clz
+
+
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
+
+/**
+ \brief LDR Exclusive (8 bit)
+ \details Executes a exclusive LDR instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (16 bit)
+ \details Executes a exclusive LDR instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDR Exclusive (32 bit)
+ \details Executes a exclusive LDR instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (8 bit)
+ \details Executes a exclusive STR instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (16 bit)
+ \details Executes a exclusive STR instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+ return(result);
+}
+
+
+/**
+ \brief STR Exclusive (32 bit)
+ \details Executes a exclusive STR instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+ return(result);
+}
+
+
+/**
+ \brief Remove the exclusive lock
+ \details Removes the exclusive lock which is created by LDREX.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex" ::: "memory");
+}
+
+
+/**
+ \brief Signed Saturate
+ \details Saturates a signed value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Unsigned Saturate
+ \details Saturates an unsigned value.
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/**
+ \brief Rotate Right with Extend (32 bit)
+ \details Moves each bit of a bitstring right by one bit.
+ The carry input is shifted in at the left end of the bitstring.
+ \param [in] value Value to rotate
+ \return Rotated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+ return(result);
+}
+
+
+/**
+ \brief LDRT Unprivileged (8 bit)
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint8_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (16 bit)
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
+{
+ uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+ accepted by assembler. So has to use following less efficient pattern.
+ */
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+ return ((uint16_t) result); /* Add explicit type cast here */
+}
+
+
+/**
+ \brief LDRT Unprivileged (32 bit)
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
+ return(result);
+}
+
+
+/**
+ \brief STRT Unprivileged (8 bit)
+ \details Executes a Unprivileged STRT instruction for 8 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
+{
+ __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (16 bit)
+ \details Executes a Unprivileged STRT instruction for 16 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
+{
+ __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+ \brief STRT Unprivileged (32 bit)
+ \details Executes a Unprivileged STRT instruction for 32 bit values.
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
+{
+ __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
+}
+
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+ Access to dedicated SIMD instructions
+ @{
+*/
+
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({ \
+ int32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+ uint32_t result;
+
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+ union llreg_u{
+ uint32_t w32[2];
+ uint64_t w64;
+ } llr;
+ llr.w64 = acc;
+
+#ifndef __ARMEB__ /* Little endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else /* Big endian */
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+ return(llr.w64);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
+{
+ uint32_t result;
+
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
+{
+ int32_t result;
+
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+ return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+ if (ARG3 == 0) \
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
+ else \
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
+ __RES; \
+ })
+
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x04) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#if defined ( __GNUC__ )
+#pragma GCC diagnostic pop
+#endif
+
+#endif /* __CMSIS_GCC_H */
/**************************************************************************//**\r
* @file core_cm3.h\r
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
- * @version V3.20\r
- * @date 25. February 2013\r
- *\r
- * @note\r
- *\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
******************************************************************************/\r
-/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
\r
All rights reserved.\r
Redistribution and use in source and binary forms, with or without\r
---------------------------------------------------------------------------*/\r
\r
\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
#endif\r
\r
+#ifndef __CORE_CM3_H_GENERIC\r
+#define __CORE_CM3_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
#ifdef __cplusplus\r
extern "C" {\r
#endif\r
\r
-#ifndef __CORE_CM3_H_GENERIC\r
-#define __CORE_CM3_H_GENERIC\r
-\r
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
CMSIS violates the following MISRA-C:2004 rules:\r
\r
\li Required Rule 8.5, object/function definition in header file.<br>\r
/*******************************************************************************\r
* CMSIS definitions\r
******************************************************************************/\r
-/** \ingroup Cortex_M3\r
+/**\r
+ \ingroup Cortex_M3\r
@{\r
*/\r
\r
/* CMSIS CM3 definitions */\r
-#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \\r
- __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
\r
-#define __CORTEX_M (0x03) /*!< Cortex-M Core */\r
+#define __CORTEX_M (0x03U) /*!< Cortex-M Core */\r
\r
\r
#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
#define __STATIC_INLINE static __inline\r
\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
#define __STATIC_INLINE static inline\r
\r
#elif defined ( __TMS470__ )\r
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
#define __STATIC_INLINE static inline\r
\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
#define __STATIC_INLINE static inline\r
\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+#elif defined ( __CSMC__ )\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r
#define __STATIC_INLINE static inline\r
\r
+#else\r
+ #error Unknown compiler\r
#endif\r
\r
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ This core does not support an FPU at all\r
*/\r
-#define __FPU_USED 0\r
+#define __FPU_USED 0U\r
\r
#if defined ( __CC_ARM )\r
#if defined __TARGET_FPU_VFP\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
#endif\r
\r
#elif defined ( __ICCARM__ )\r
#if defined __ARMVFP__\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
#endif\r
\r
#elif defined ( __TMS470__ )\r
- #if defined __TI__VFP_SUPPORT____\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
- #endif\r
-\r
-#elif defined ( __GNUC__ )\r
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
#endif\r
\r
#elif defined ( __TASKING__ )\r
#if defined __FPU_VFP__\r
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
#endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
#endif\r
\r
-#include <stdint.h> /* standard types definitions */\r
-#include <core_cmInstr.h> /* Core Instruction Access */\r
-#include <core_cmFunc.h> /* Core Function Access */\r
+#include "core_cmInstr.h" /* Core Instruction Access */\r
+#include "core_cmFunc.h" /* Core Function Access */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
\r
#endif /* __CORE_CM3_H_GENERIC */\r
\r
#ifndef __CORE_CM3_H_DEPENDANT\r
#define __CORE_CM3_H_DEPENDANT\r
\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
/* check device defines and use defaults */\r
#if defined __CHECK_DEVICE_DEFINES\r
#ifndef __CM3_REV\r
- #define __CM3_REV 0x0200\r
+ #define __CM3_REV 0x0200U\r
#warning "__CM3_REV not defined in device header file; using default!"\r
#endif\r
\r
#ifndef __MPU_PRESENT\r
- #define __MPU_PRESENT 0\r
+ #define __MPU_PRESENT 0U\r
#warning "__MPU_PRESENT not defined in device header file; using default!"\r
#endif\r
\r
#ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 4\r
+ #define __NVIC_PRIO_BITS 4U\r
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
#endif\r
\r
#ifndef __Vendor_SysTickConfig\r
- #define __Vendor_SysTickConfig 0\r
+ #define __Vendor_SysTickConfig 0U\r
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
#endif\r
#endif\r
\li for automatic generation of peripheral register debug information.\r
*/\r
#ifdef __cplusplus\r
- #define __I volatile /*!< Defines 'read only' permissions */\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
#else\r
- #define __I volatile const /*!< Defines 'read only' permissions */\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
#endif\r
-#define __O volatile /*!< Defines 'write only' permissions */\r
-#define __IO volatile /*!< Defines 'read / write' permissions */\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
\r
/*@} end of group Cortex_M3 */\r
\r
- Core Debug Register\r
- Core MPU Register\r
******************************************************************************/\r
-/** \defgroup CMSIS_core_register Defines and Type Definitions\r
- \brief Type definitions and defines for Cortex-M processor based devices.\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
*/\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CORE Status and Control Registers\r
- \brief Core Register type definitions.\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
@{\r
*/\r
\r
-/** \brief Union type to access the Application Program Status Register (APSR).\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
*/\r
typedef union\r
{\r
struct\r
{\r
-#if (__CORTEX_M != 0x04)\r
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
-#else\r
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
-#endif\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
} APSR_Type;\r
\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
\r
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
*/\r
typedef union\r
{\r
struct\r
{\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
} IPSR_Type;\r
\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
\r
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
*/\r
typedef union\r
{\r
struct\r
{\r
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
-#if (__CORTEX_M != 0x04)\r
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
-#else\r
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
-#endif\r
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
} xPSR_Type;\r
\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
\r
-/** \brief Union type to access the Control Registers (CONTROL).\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
*/\r
typedef union\r
{\r
struct\r
{\r
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
- } b; /*!< Structure used for bit access */\r
- uint32_t w; /*!< Type used for word access */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
} CONTROL_Type;\r
\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
/*@} end of group CMSIS_CORE */\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
- \brief Type definitions for the NVIC Registers\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
@{\r
*/\r
\r
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
*/\r
typedef struct\r
{\r
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24];\r
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24];\r
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24];\r
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24];\r
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
- uint32_t RESERVED4[56];\r
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644];\r
- __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
} NVIC_Type;\r
\r
/* Software Triggered Interrupt Register Definitions */\r
-#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
\r
/*@} end of group CMSIS_NVIC */\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCB System Control Block (SCB)\r
- \brief Type definitions for the System Control Block Registers\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
@{\r
*/\r
\r
-/** \brief Structure type to access the System Control Block (SCB).\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
*/\r
typedef struct\r
{\r
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
- __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
- __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
- __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
- __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
- __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
- __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
- __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
- __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
- __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
- uint32_t RESERVED0[5];\r
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5U];\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
} SCB_Type;\r
\r
/* SCB CPUID Register Definitions */\r
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
\r
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
\r
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
\r
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
\r
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
\r
/* SCB Interrupt Control State Register Definitions */\r
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
\r
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
\r
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
\r
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
\r
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
\r
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
\r
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
\r
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
\r
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
\r
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
\r
/* SCB Vector Table Offset Register Definitions */\r
-#if (__CM3_REV < 0x0201) /* core r2p1 */\r
-#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#if (__CM3_REV < 0x0201U) /* core r2p1 */\r
+#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */\r
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
\r
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
#else\r
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
#endif\r
\r
/* SCB Application Interrupt and Reset Control Register Definitions */\r
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
\r
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
\r
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
\r
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
\r
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
\r
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
\r
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
\r
/* SCB System Control Register Definitions */\r
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
\r
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
\r
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
\r
/* SCB Configuration Control Register Definitions */\r
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
\r
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
\r
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
\r
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
\r
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
\r
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
\r
/* SCB System Handler Control and State Register Definitions */\r
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
\r
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
\r
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
\r
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
\r
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
\r
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
\r
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
\r
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
\r
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
\r
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
\r
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
\r
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
\r
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
\r
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
\r
-/* SCB Configurable Fault Status Registers Definitions */\r
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
\r
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
\r
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
\r
-/* SCB Hard Fault Status Registers Definitions */\r
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
\r
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
\r
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
\r
/* SCB Debug Fault Status Register Definitions */\r
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
\r
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
\r
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
\r
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
\r
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
\r
/*@} end of group CMSIS_SCB */\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
- \brief Type definitions for the System Control and ID Register not in the SCB\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
@{\r
*/\r
\r
-/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
*/\r
typedef struct\r
{\r
- uint32_t RESERVED0[1];\r
- __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
- __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U))\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
#else\r
- uint32_t RESERVED1[1];\r
+ uint32_t RESERVED1[1U];\r
#endif\r
} SCnSCB_Type;\r
\r
/* Interrupt Controller Type Register Definitions */\r
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
\r
/* Auxiliary Control Register Definitions */\r
\r
-#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
\r
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */\r
#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
\r
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
\r
/*@} end of group CMSIS_SCnotSCB */\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
- \brief Type definitions for the System Timer Registers.\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
@{\r
*/\r
\r
-/** \brief Structure type to access the System Timer (SysTick).\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
*/\r
typedef struct\r
{\r
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
} SysTick_Type;\r
\r
/* SysTick Control / Status Register Definitions */\r
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
\r
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
\r
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
\r
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
\r
/* SysTick Reload Register Definitions */\r
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
\r
/* SysTick Current Register Definitions */\r
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
\r
/* SysTick Calibration Register Definitions */\r
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
\r
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
\r
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
\r
/*@} end of group CMSIS_SysTick */\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
@{\r
*/\r
\r
-/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
*/\r
typedef struct\r
{\r
- __O union\r
+ __OM union\r
{\r
- __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
- __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
- __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
- } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864];\r
- __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
- uint32_t RESERVED1[15];\r
- __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15];\r
- __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
- uint32_t RESERVED3[29];\r
- __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
- __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
- __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43];\r
- __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
- __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
- uint32_t RESERVED5[6];\r
- __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
- __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
- __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
- __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
- __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
- __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
- __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
- __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
- __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
- __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
- __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
- __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
} ITM_Type;\r
\r
/* ITM Trace Privilege Register Definitions */\r
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
\r
/* ITM Trace Control Register Definitions */\r
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
\r
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
\r
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
\r
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
\r
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
\r
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
\r
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
\r
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
\r
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
\r
/* ITM Integration Write Register Definitions */\r
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
\r
/* ITM Integration Read Register Definitions */\r
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
\r
/* ITM Integration Mode Control Register Definitions */\r
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
\r
/* ITM Lock Status Register Definitions */\r
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
\r
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
\r
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
\r
/*@}*/ /* end of group CMSIS_ITM */\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
- \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
@{\r
*/\r
\r
-/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
*/\r
typedef struct\r
{\r
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
- __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
- __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
- __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
- __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
- __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
- __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
- __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
- __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
- __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
- __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
- uint32_t RESERVED0[1];\r
- __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
- __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
- __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
- uint32_t RESERVED1[1];\r
- __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
- __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
- __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
- uint32_t RESERVED2[1];\r
- __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
- __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
- __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
} DWT_Type;\r
\r
/* DWT Control Register Definitions */\r
-#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
\r
-#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
\r
-#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
\r
-#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
\r
-#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
\r
-#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
\r
-#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
\r
-#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
\r
-#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
\r
-#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
\r
-#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
\r
-#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
\r
-#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
\r
-#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
\r
-#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
\r
-#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
\r
-#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
\r
-#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
\r
/* DWT CPI Count Register Definitions */\r
-#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
\r
/* DWT Exception Overhead Count Register Definitions */\r
-#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
\r
/* DWT Sleep Count Register Definitions */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
\r
/* DWT LSU Count Register Definitions */\r
-#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
\r
/* DWT Folded-instruction Count Register Definitions */\r
-#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
\r
/* DWT Comparator Mask Register Definitions */\r
-#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
\r
/* DWT Comparator Function Register Definitions */\r
-#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
\r
-#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
\r
-#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
\r
-#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
\r
-#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
\r
-#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
\r
-#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
\r
-#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
\r
-#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
\r
/*@}*/ /* end of group CMSIS_DWT */\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
- \brief Type definitions for the Trace Port Interface (TPI)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
@{\r
*/\r
\r
-/** \brief Structure type to access the Trace Port Interface Register (TPI).\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
*/\r
typedef struct\r
{\r
- __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
- __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
- uint32_t RESERVED0[2];\r
- __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
- uint32_t RESERVED1[55];\r
- __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
- uint32_t RESERVED2[131];\r
- __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
- __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
- __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
- uint32_t RESERVED3[759];\r
- __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
- __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
- __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
- uint32_t RESERVED4[1];\r
- __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
- __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
- __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
- uint32_t RESERVED5[39];\r
- __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
- __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
- uint32_t RESERVED7[8];\r
- __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
- __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
} TPI_Type;\r
\r
/* TPI Asynchronous Clock Prescaler Register Definitions */\r
-#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
\r
/* TPI Selected Pin Protocol Register Definitions */\r
-#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
\r
/* TPI Formatter and Flush Status Register Definitions */\r
-#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
\r
-#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
\r
-#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
\r
-#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
\r
/* TPI Formatter and Flush Control Register Definitions */\r
-#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
\r
-#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
\r
/* TPI TRIGGER Register Definitions */\r
-#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
\r
/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
-#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
\r
-#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
\r
-#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
\r
-#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
\r
-#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
\r
-#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
\r
-#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
\r
/* TPI ITATBCTR2 Register Definitions */\r
-#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
\r
/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
-#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
\r
-#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
\r
-#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
\r
-#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
\r
-#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
\r
-#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
\r
-#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
\r
/* TPI ITATBCTR0 Register Definitions */\r
-#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
\r
/* TPI Integration Mode Control Register Definitions */\r
-#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
\r
/* TPI DEVID Register Definitions */\r
-#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
\r
-#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
\r
-#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
\r
-#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
\r
-#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
\r
-#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
\r
/* TPI DEVTYPE Register Definitions */\r
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
-\r
-#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
\r
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
/*@}*/ /* end of group CMSIS_TPI */\r
\r
\r
-#if (__MPU_PRESENT == 1)\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
- \brief Type definitions for the Memory Protection Unit (MPU)\r
+#if (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
@{\r
*/\r
\r
-/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
*/\r
typedef struct\r
{\r
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
- __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
- __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
- __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
} MPU_Type;\r
\r
-/* MPU Type Register */\r
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
\r
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
\r
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
\r
-/* MPU Control Register */\r
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
\r
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
\r
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
\r
-/* MPU Region Number Register */\r
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
\r
-/* MPU Region Base Address Register */\r
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
\r
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
\r
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
\r
-/* MPU Region Attribute and Size Register */\r
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
\r
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
\r
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
\r
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
\r
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
\r
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
\r
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
\r
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
\r
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
\r
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
\r
/*@} end of group CMSIS_MPU */\r
#endif\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
- \brief Type definitions for the Core Debug Registers\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
@{\r
*/\r
\r
-/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
*/\r
typedef struct\r
{\r
- __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
- __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
- __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
- __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
} CoreDebug_Type;\r
\r
-/* Debug Halting Control and Status Register */\r
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
\r
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
\r
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
\r
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
\r
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
\r
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
\r
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
\r
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
\r
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
\r
-/* Debug Core Register Selector Register */\r
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
\r
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
\r
-/* Debug Exception and Monitor Control Register */\r
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
\r
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
\r
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
\r
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
\r
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
\r
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
\r
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
\r
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
\r
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
\r
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
\r
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
\r
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
\r
/*@} end of group CMSIS_CoreDebug */\r
\r
\r
-/** \ingroup CMSIS_core_register\r
- \defgroup CMSIS_core_base Core Definitions\r
- \brief Definitions for base addresses, unions, and structures.\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
@{\r
*/\r
\r
/* Memory mapping of Cortex-M3 Hardware */\r
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
\r
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if (__MPU_PRESENT == 1)\r
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
#endif\r
\r
/*@} */\r
- Core Debug Functions\r
- Core Register Access Functions\r
******************************************************************************/\r
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
*/\r
\r
\r
\r
/* ########################## NVIC functions #################################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
- \brief Functions that manage interrupts and exceptions via the NVIC.\r
- @{\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
*/\r
\r
-/** \brief Set Priority Grouping\r
-\r
- The function sets the priority grouping field using the required unlock sequence.\r
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
- Only values from 0..7 are used.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
-\r
- \param [in] PriorityGroup Priority grouping field.\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
*/\r
__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
{\r
uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
\r
reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
- reg_value = (reg_value |\r
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
SCB->AIRCR = reg_value;\r
}\r
\r
\r
-/** \brief Get Priority Grouping\r
-\r
- The function reads the priority grouping field from the NVIC Interrupt Controller.\r
-\r
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
{\r
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
}\r
\r
\r
-/** \brief Enable External Interrupt\r
-\r
- The function enables a device-specific interrupt in the NVIC interrupt controller.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
+/**\r
+ \brief Enable External Interrupt\r
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
*/\r
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
-/** \brief Disable External Interrupt\r
-\r
- The function disables a device-specific interrupt in the NVIC interrupt controller.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
+/**\r
+ \brief Disable External Interrupt\r
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
*/\r
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
-/** \brief Get Pending Interrupt\r
-\r
- The function reads the pending register in the NVIC and returns the pending bit\r
- for the specified interrupt.\r
-\r
- \param [in] IRQn Interrupt number.\r
-\r
- \return 0 Interrupt status is not pending.\r
- \return 1 Interrupt status is pending.\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
}\r
\r
\r
-/** \brief Set Pending Interrupt\r
-\r
- The function sets the pending bit of an external interrupt.\r
-\r
- \param [in] IRQn Interrupt number. Value cannot be negative.\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of an external interrupt.\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
*/\r
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
-/** \brief Clear Pending Interrupt\r
-\r
- The function clears the pending bit of an external interrupt.\r
-\r
- \param [in] IRQn External interrupt number. Value cannot be negative.\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of an external interrupt.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
*/\r
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
}\r
\r
\r
-/** \brief Get Active Interrupt\r
-\r
- The function reads the active register in NVIC and returns the active bit.\r
-\r
- \param [in] IRQn Interrupt number.\r
-\r
- \return 0 Interrupt status is not active.\r
- \return 1 Interrupt status is active.\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in NVIC and returns the active bit.\r
+ \param [in] IRQn Interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
}\r
\r
\r
-/** \brief Set Interrupt Priority\r
-\r
- The function sets the priority of an interrupt.\r
-\r
- \note The priority cannot be set for every core interrupt.\r
-\r
- \param [in] IRQn Interrupt number.\r
- \param [in] priority Priority to set.\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of an interrupt.\r
+ \note The priority cannot be set for every core interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
*/\r
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
{\r
- if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
- else {\r
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+ if ((int32_t)(IRQn) < 0)\r
+ {\r
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
}\r
\r
\r
-/** \brief Get Interrupt Priority\r
-\r
- The function reads the priority of an interrupt. The interrupt\r
- number can be positive to specify an external (device specific)\r
- interrupt, or negative to specify an internal (core) interrupt.\r
-\r
-\r
- \param [in] IRQn Interrupt number.\r
- \return Interrupt Priority. Value is aligned automatically to the implemented\r
- priority bits of the microcontroller.\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of an interrupt.\r
+ The interrupt number can be positive to specify an external (device specific) interrupt,\r
+ or negative to specify an internal (core) interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
*/\r
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
{\r
\r
- if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
- else {\r
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+ if ((int32_t)(IRQn) < 0)\r
+ {\r
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
}\r
\r
\r
-/** \brief Encode Priority\r
-\r
- The function encodes the priority for an interrupt with the given priority group,\r
- preemptive priority value, and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.\r
-\r
- \param [in] PriorityGroup Used priority group.\r
- \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
- \param [in] SubPriority Subpriority value (starting from 0).\r
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
*/\r
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
uint32_t PreemptPriorityBits;\r
uint32_t SubPriorityBits;\r
\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
\r
return (\r
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
);\r
}\r
\r
\r
-/** \brief Decode Priority\r
-\r
- The function decodes an interrupt priority value with a given priority group to\r
- preemptive priority value and subpriority value.\r
- In case of a conflict between priority grouping and available\r
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
-\r
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
- \param [in] PriorityGroup Used priority group.\r
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
- \param [out] pSubPriority Subpriority value (starting from 0).\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
*/\r
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
{\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
uint32_t PreemptPriorityBits;\r
uint32_t SubPriorityBits;\r
\r
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
\r
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
}\r
\r
\r
-/** \brief System Reset\r
-\r
- The function initiates a system reset request to reset the MCU.\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
*/\r
__STATIC_INLINE void NVIC_SystemReset(void)\r
{\r
- __DSB(); /* Ensure all outstanding memory accesses included\r
- buffered write are completed before reset */\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */\r
- while(1); /* wait until reset */\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
}\r
\r
/*@} end of CMSIS_Core_NVICFunctions */\r
\r
\r
/* ################################## SysTick function ############################################ */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
- \brief Functions that configure the System.\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
@{\r
*/\r
\r
-#if (__Vendor_SysTickConfig == 0)\r
-\r
-/** \brief System Tick Configuration\r
-\r
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
- Counter is in free running mode to generate periodic interrupts.\r
-\r
- \param [in] ticks Number of ticks between two interrupts.\r
-\r
- \return 0 Function succeeded.\r
- \return 1 Function failed.\r
-\r
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
- must contain a vendor-specific implementation of this function.\r
+#if (__Vendor_SysTickConfig == 0U)\r
\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
*/\r
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
{\r
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
\r
- SysTick->LOAD = ticks - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
SysTick_CTRL_TICKINT_Msk |\r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
}\r
\r
#endif\r
\r
\r
/* ##################################### Debug In/Output function ########################################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_core_DebugFunctions ITM Functions\r
- \brief Functions that access the ITM debug interface.\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
@{\r
*/\r
\r
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
-\r
-\r
-/** \brief ITM Send Character\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
\r
- The function transmits a character via the ITM channel 0, and\r
- \li Just returns when no debugger is connected that has booked the output.\r
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
\r
- \param [in] ch Character to transmit.\r
-\r
- \returns Character to transmit.\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
*/\r
__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
{\r
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
{\r
- while (ITM->PORT[0].u32 == 0);\r
- ITM->PORT[0].u8 = (uint8_t) ch;\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
}\r
return (ch);\r
}\r
\r
\r
-/** \brief ITM Receive Character\r
-\r
- The function inputs a character via the external variable \ref ITM_RxBuffer.\r
-\r
- \return Received character.\r
- \return -1 No character pending.\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
*/\r
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
int32_t ch = -1; /* no character available */\r
\r
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
ch = ITM_RxBuffer;\r
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
}\r
}\r
\r
\r
-/** \brief ITM Check Character\r
-\r
- The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
-\r
- \return 0 No character available.\r
- \return 1 Character available.\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
*/\r
-__STATIC_INLINE int32_t ITM_CheckChar (void) {\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
\r
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
- return (0); /* no character available */\r
- } else {\r
- return (1); /* character available */\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
}\r
}\r
\r
/*@} end of CMSIS_core_DebugFunctions */\r
\r
-#endif /* __CORE_CM3_H_DEPENDANT */\r
\r
-#endif /* __CMSIS_GENERIC */\r
+\r
\r
#ifdef __cplusplus\r
}\r
#endif\r
+\r
+#endif /* __CORE_CM3_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
/*******************************************************************************\r
-* File Name: core_cm3_psoc5.h\r
-* Version 4.20\r
+* \file core_cm3_psoc5.h\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides important type information for the PSoC5. This includes types\r
-* necessary for core_cm3.h.\r
+* \brief Provides important type information for the PSoC5. This includes types\r
+* necessary for core_cm3.h.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the\r
-* System Reference Guide provided with PSoC Creator.\r
+* \note Documentation of the API's in this file is located in the\r
+* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
/**************************************************************************//**\r
* @file core_cmFunc.h\r
* @brief CMSIS Cortex-M Core Function Access Header File\r
- * @version V3.20\r
- * @date 25. February 2013\r
- *\r
- * @note\r
- *\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
******************************************************************************/\r
-/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
\r
All rights reserved.\r
Redistribution and use in source and binary forms, with or without\r
---------------------------------------------------------------------------*/\r
\r
\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
#ifndef __CORE_CMFUNC_H\r
#define __CORE_CMFUNC_H\r
\r
/** \ingroup CMSIS_Core_FunctionInterface\r
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
@{\r
- */\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#if (__ARMCC_VERSION < 400677)\r
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
-#endif\r
-\r
-/* intrinsic void __enable_irq(); */\r
-/* intrinsic void __disable_irq(); */\r
-\r
-/** \brief Get Control Register\r
-\r
- This function returns the content of the Control Register.\r
-\r
- \return Control Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_CONTROL(void)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- return(__regControl);\r
-}\r
-\r
-\r
-/** \brief Set Control Register\r
-\r
- This function writes the given value to the Control Register.\r
-\r
- \param [in] control Control Register value to set\r
- */\r
-__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- __regControl = control;\r
-}\r
-\r
-\r
-/** \brief Get IPSR Register\r
-\r
- This function returns the content of the IPSR Register.\r
-\r
- \return IPSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_IPSR(void)\r
-{\r
- register uint32_t __regIPSR __ASM("ipsr");\r
- return(__regIPSR);\r
-}\r
-\r
-\r
-/** \brief Get APSR Register\r
-\r
- This function returns the content of the APSR Register.\r
-\r
- \return APSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_APSR(void)\r
-{\r
- register uint32_t __regAPSR __ASM("apsr");\r
- return(__regAPSR);\r
-}\r
-\r
-\r
-/** \brief Get xPSR Register\r
-\r
- This function returns the content of the xPSR Register.\r
-\r
- \return xPSR Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_xPSR(void)\r
-{\r
- register uint32_t __regXPSR __ASM("xpsr");\r
- return(__regXPSR);\r
-}\r
-\r
-\r
-/** \brief Get Process Stack Pointer\r
-\r
- This function returns the current value of the Process Stack Pointer (PSP).\r
-\r
- \return PSP Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_PSP(void)\r
-{\r
- register uint32_t __regProcessStackPointer __ASM("psp");\r
- return(__regProcessStackPointer);\r
-}\r
-\r
-\r
-/** \brief Set Process Stack Pointer\r
-\r
- This function assigns the given value to the Process Stack Pointer (PSP).\r
-\r
- \param [in] topOfProcStack Process Stack Pointer value to set\r
- */\r
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- register uint32_t __regProcessStackPointer __ASM("psp");\r
- __regProcessStackPointer = topOfProcStack;\r
-}\r
-\r
-\r
-/** \brief Get Main Stack Pointer\r
-\r
- This function returns the current value of the Main Stack Pointer (MSP).\r
-\r
- \return MSP Register value\r
- */\r
-__STATIC_INLINE uint32_t __get_MSP(void)\r
-{\r
- register uint32_t __regMainStackPointer __ASM("msp");\r
- return(__regMainStackPointer);\r
-}\r
-\r
-\r
-/** \brief Set Main Stack Pointer\r
-\r
- This function assigns the given value to the Main Stack Pointer (MSP).\r
-\r
- \param [in] topOfMainStack Main Stack Pointer value to set\r
- */\r
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- register uint32_t __regMainStackPointer __ASM("msp");\r
- __regMainStackPointer = topOfMainStack;\r
-}\r
-\r
-\r
-/** \brief Get Priority Mask\r
-\r
- This function returns the current state of the priority mask bit from the Priority Mask Register.\r
-\r
- \return Priority Mask value\r
- */\r
-__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- return(__regPriMask);\r
-}\r
-\r
-\r
-/** \brief Set Priority Mask\r
+*/\r
\r
- This function assigns the given value to the Priority Mask Register.\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
\r
- \param [in] priMask Priority Mask\r
- */\r
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- __regPriMask = (priMask);\r
-}\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
\r
-#if (__CORTEX_M >= 0x03)\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
\r
-/** \brief Enable FIQ\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
\r
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-#define __enable_fault_irq __enable_fiq\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
\r
-\r
-/** \brief Disable FIQ\r
-\r
- This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-#define __disable_fault_irq __disable_fiq\r
-\r
-\r
-/** \brief Get Base Priority\r
-\r
- This function returns the current value of the Base Priority register.\r
-\r
- \return Base Priority register value\r
- */\r
-__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- return(__regBasePri);\r
-}\r
-\r
-\r
-/** \brief Set Base Priority\r
-\r
- This function assigns the given value to the Base Priority register.\r
-\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- __regBasePri = (basePri & 0xff);\r
-}\r
-\r
-\r
-/** \brief Get Fault Mask\r
-\r
- This function returns the current value of the Fault Mask register.\r
-\r
- \return Fault Mask register value\r
- */\r
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- return(__regFaultMask);\r
-}\r
-\r
-\r
-/** \brief Set Fault Mask\r
-\r
- This function assigns the given value to the Fault Mask register.\r
-\r
- \param [in] faultMask Fault Mask value to set\r
- */\r
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- __regFaultMask = (faultMask & (uint32_t)1);\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-#if (__CORTEX_M == 0x04)\r
-\r
-/** \brief Get FPSCR\r
-\r
- This function returns the current value of the Floating Point Status/Control register.\r
-\r
- \return Floating Point Status/Control register value\r
- */\r
-__STATIC_INLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- register uint32_t __regfpscr __ASM("fpscr");\r
- return(__regfpscr);\r
-#else\r
- return(0);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Set FPSCR\r
-\r
- This function assigns the given value to the Floating Point Status/Control register.\r
-\r
- \param [in] fpscr Floating Point Status/Control value to set\r
- */\r
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- register uint32_t __regfpscr __ASM("fpscr");\r
- __regfpscr = (fpscr);\r
-#endif\r
-}\r
-\r
-#endif /* (__CORTEX_M == 0x04) */\r
-\r
-\r
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#include <cmsis_iar.h>\r
-\r
-\r
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
-/* TI CCS specific functions */\r
-\r
-#include <cmsis_ccs.h>\r
-\r
-\r
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-/** \brief Enable IRQ Interrupts\r
-\r
- This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
-{\r
- __ASM volatile ("cpsie i" : : : "memory");\r
-}\r
-\r
-\r
-/** \brief Disable IRQ Interrupts\r
-\r
- This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
-{\r
- __ASM volatile ("cpsid i" : : : "memory");\r
-}\r
-\r
-\r
-/** \brief Get Control Register\r
-\r
- This function returns the content of the Control Register.\r
-\r
- \return Control Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, control" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Control Register\r
-\r
- This function writes the given value to the Control Register.\r
-\r
- \param [in] control Control Register value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
-}\r
-\r
-\r
-/** \brief Get IPSR Register\r
-\r
- This function returns the content of the IPSR Register.\r
-\r
- \return IPSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Get APSR Register\r
-\r
- This function returns the content of the APSR Register.\r
-\r
- \return APSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Get xPSR Register\r
-\r
- This function returns the content of the xPSR Register.\r
-\r
- \return xPSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Get Process Stack Pointer\r
-\r
- This function returns the current value of the Process Stack Pointer (PSP).\r
-\r
- \return PSP Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Process Stack Pointer\r
-\r
- This function assigns the given value to the Process Stack Pointer (PSP).\r
-\r
- \param [in] topOfProcStack Process Stack Pointer value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");\r
-}\r
-\r
-\r
-/** \brief Get Main Stack Pointer\r
-\r
- This function returns the current value of the Main Stack Pointer (MSP).\r
-\r
- \return MSP Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Main Stack Pointer\r
-\r
- This function assigns the given value to the Main Stack Pointer (MSP).\r
-\r
- \param [in] topOfMainStack Main Stack Pointer value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");\r
-}\r
-\r
-\r
-/** \brief Get Priority Mask\r
-\r
- This function returns the current state of the priority mask bit from the Priority Mask Register.\r
-\r
- \return Priority Mask value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Priority Mask\r
-\r
- This function assigns the given value to the Priority Mask Register.\r
-\r
- \param [in] priMask Priority Mask\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
-}\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Enable FIQ\r
-\r
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsie f" : : : "memory");\r
-}\r
-\r
-\r
-/** \brief Disable FIQ\r
-\r
- This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsid f" : : : "memory");\r
-}\r
-\r
-\r
-/** \brief Get Base Priority\r
-\r
- This function returns the current value of the Base Priority register.\r
-\r
- \return Base Priority register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Base Priority\r
-\r
- This function assigns the given value to the Base Priority register.\r
-\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
-}\r
-\r
-\r
-/** \brief Get Fault Mask\r
-\r
- This function returns the current value of the Fault Mask register.\r
-\r
- \return Fault Mask register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Set Fault Mask\r
-\r
- This function assigns the given value to the Fault Mask register.\r
-\r
- \param [in] faultMask Fault Mask value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-#if (__CORTEX_M == 0x04)\r
-\r
-/** \brief Get FPSCR\r
-\r
- This function returns the current value of the Floating Point Status/Control register.\r
-\r
- \return Floating Point Status/Control register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- uint32_t result;\r
-\r
- /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("");\r
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
- __ASM volatile ("");\r
- return(result);\r
-#else\r
- return(0);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Set FPSCR\r
-\r
- This function assigns the given value to the Floating Point Status/Control register.\r
-\r
- \param [in] fpscr Floating Point Status/Control value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
- /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("");\r
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
- __ASM volatile ("");\r
-#endif\r
-}\r
-\r
-#endif /* (__CORTEX_M == 0x04) */\r
-\r
-\r
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
\r
#endif\r
\r
/*@} end of CMSIS_Core_RegAccFunctions */\r
\r
-\r
#endif /* __CORE_CMFUNC_H */\r
/**************************************************************************//**\r
* @file core_cmInstr.h\r
* @brief CMSIS Cortex-M Core Instruction Access Header File\r
- * @version V3.20\r
- * @date 05. March 2013\r
- *\r
- * @note\r
- *\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
******************************************************************************/\r
-/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
\r
All rights reserved.\r
Redistribution and use in source and binary forms, with or without\r
---------------------------------------------------------------------------*/\r
\r
\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
#ifndef __CORE_CMINSTR_H\r
#define __CORE_CMINSTR_H\r
\r
@{\r
*/\r
\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-#if (__ARMCC_VERSION < 400677)\r
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
-#endif\r
-\r
-\r
-/** \brief No Operation\r
-\r
- No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-#define __NOP __nop\r
-\r
-\r
-/** \brief Wait For Interrupt\r
-\r
- Wait For Interrupt is a hint instruction that suspends execution\r
- until one of a number of events occurs.\r
- */\r
-#define __WFI __wfi\r
-\r
-\r
-/** \brief Wait For Event\r
-\r
- Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-#define __WFE __wfe\r
-\r
-\r
-/** \brief Send Event\r
-\r
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-#define __SEV __sev\r
-\r
-\r
-/** \brief Instruction Synchronization Barrier\r
-\r
- Instruction Synchronization Barrier flushes the pipeline in the processor,\r
- so that all instructions following the ISB are fetched from cache or\r
- memory, after the instruction has been completed.\r
- */\r
-#define __ISB() __isb(0xF)\r
-\r
-\r
-/** \brief Data Synchronization Barrier\r
-\r
- This function acts as a special kind of Data Memory Barrier.\r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-#define __DSB() __dsb(0xF)\r
-\r
-\r
-/** \brief Data Memory Barrier\r
-\r
- This function ensures the apparent order of the explicit memory operations before\r
- and after the instruction, without ensuring their completion.\r
- */\r
-#define __DMB() __dmb(0xF)\r
-\r
-\r
-/** \brief Reverse byte order (32 bit)\r
-\r
- This function reverses the byte order in integer value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#define __REV __rev\r
-\r
-\r
-/** \brief Reverse byte order (16 bit)\r
-\r
- This function reverses the byte order in two unsigned short values.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
-{\r
- rev16 r0, r0\r
- bx lr\r
-}\r
-#endif\r
-\r
-/** \brief Reverse byte order in signed short value\r
-\r
- This function reverses the byte order in a signed short value with sign extension to integer.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#ifndef __NO_EMBEDDED_ASM\r
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
-{\r
- revsh r0, r0\r
- bx lr\r
-}\r
-#endif\r
-\r
-\r
-/** \brief Rotate Right in unsigned value (32 bit)\r
-\r
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
-\r
- \param [in] value Value to rotate\r
- \param [in] value Number of Bits to rotate\r
- \return Rotated value\r
- */\r
-#define __ROR __ror\r
-\r
-\r
-/** \brief Breakpoint\r
-\r
- This function causes the processor to enter Debug state.\r
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
-\r
- \param [in] value is ignored by the processor.\r
- If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value) __breakpoint(value)\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Reverse bit order of value\r
-\r
- This function reverses the bit order of the given value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-#define __RBIT __rbit\r
-\r
-\r
-/** \brief LDR Exclusive (8 bit)\r
-\r
- This function performs a exclusive LDR command for 8 bit value.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
-\r
-\r
-/** \brief LDR Exclusive (16 bit)\r
-\r
- This function performs a exclusive LDR command for 16 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
-\r
-\r
-/** \brief LDR Exclusive (32 bit)\r
-\r
- This function performs a exclusive LDR command for 32 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
-\r
-\r
-/** \brief STR Exclusive (8 bit)\r
-\r
- This function performs a exclusive STR command for 8 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXB(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief STR Exclusive (16 bit)\r
-\r
- This function performs a exclusive STR command for 16 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXH(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief STR Exclusive (32 bit)\r
-\r
- This function performs a exclusive STR command for 32 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-#define __STREXW(value, ptr) __strex(value, ptr)\r
-\r
-\r
-/** \brief Remove the exclusive lock\r
-\r
- This function removes the exclusive lock which is created by LDREX.\r
-\r
- */\r
-#define __CLREX __clrex\r
-\r
-\r
-/** \brief Signed Saturate\r
-\r
- This function saturates a signed value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-#define __SSAT __ssat\r
-\r
-\r
-/** \brief Unsigned Saturate\r
-\r
- This function saturates an unsigned value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT __usat\r
-\r
-\r
-/** \brief Count leading zeros\r
-\r
- This function counts the number of leading zeros of a data value.\r
-\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-#define __CLZ __clz\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-\r
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#include <cmsis_iar.h>\r
-\r
-\r
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
-/* TI CCS specific functions */\r
-\r
-#include <cmsis_ccs.h>\r
-\r
-\r
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-/* Define macros for porting to both thumb1 and thumb2.\r
- * For thumb1, use low register (r0-r7), specified by constrant "l"\r
- * Otherwise, use general registers, specified by constrant "r" */\r
-#if defined (__thumb__) && !defined (__thumb2__)\r
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
-#else\r
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
-#endif\r
-\r
-/** \brief No Operation\r
-\r
- No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)\r
-{\r
- __ASM volatile ("nop");\r
-}\r
-\r
-\r
-/** \brief Wait For Interrupt\r
-\r
- Wait For Interrupt is a hint instruction that suspends execution\r
- until one of a number of events occurs.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)\r
-{\r
- __ASM volatile ("wfi");\r
-}\r
-\r
-\r
-/** \brief Wait For Event\r
-\r
- Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)\r
-{\r
- __ASM volatile ("wfe");\r
-}\r
-\r
-\r
-/** \brief Send Event\r
-\r
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)\r
-{\r
- __ASM volatile ("sev");\r
-}\r
-\r
-\r
-/** \brief Instruction Synchronization Barrier\r
-\r
- Instruction Synchronization Barrier flushes the pipeline in the processor,\r
- so that all instructions following the ISB are fetched from cache or\r
- memory, after the instruction has been completed.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)\r
-{\r
- __ASM volatile ("isb");\r
-}\r
-\r
-\r
-/** \brief Data Synchronization Barrier\r
-\r
- This function acts as a special kind of Data Memory Barrier.\r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)\r
-{\r
- __ASM volatile ("dsb");\r
-}\r
-\r
-\r
-/** \brief Data Memory Barrier\r
-\r
- This function ensures the apparent order of the explicit memory operations before\r
- and after the instruction, without ensuring their completion.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)\r
-{\r
- __ASM volatile ("dmb");\r
-}\r
-\r
-\r
-/** \brief Reverse byte order (32 bit)\r
-\r
- This function reverses the byte order in integer value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
- return __builtin_bswap32(value);\r
-#else\r
- uint32_t result;\r
-\r
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Reverse byte order (16 bit)\r
-\r
- This function reverses the byte order in two unsigned short values.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Reverse byte order in signed short value\r
-\r
- This function reverses the byte order in a signed short value with sign extension to integer.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- return (short)__builtin_bswap16(value);\r
-#else\r
- uint32_t result;\r
-\r
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-#endif\r
-}\r
-\r
-\r
-/** \brief Rotate Right in unsigned value (32 bit)\r
-\r
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
-\r
- \param [in] value Value to rotate\r
- \param [in] value Number of Bits to rotate\r
- \return Rotated value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
-{\r
- return (op1 >> op2) | (op1 << (32 - op2));\r
-}\r
-\r
-\r
-/** \brief Breakpoint\r
-\r
- This function causes the processor to enter Debug state.\r
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
-\r
- \param [in] value is ignored by the processor.\r
- If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
-\r
-\r
-#if (__CORTEX_M >= 0x03)\r
-\r
-/** \brief Reverse bit order of value\r
-\r
- This function reverses the bit order of the given value.\r
-\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (8 bit)\r
-\r
- This function performs a exclusive LDR command for 8 bit value.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (16 bit)\r
-\r
- This function performs a exclusive LDR command for 16 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief LDR Exclusive (32 bit)\r
-\r
- This function performs a exclusive LDR command for 32 bit values.\r
-\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (8 bit)\r
-\r
- This function performs a exclusive STR command for 8 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (16 bit)\r
-\r
- This function performs a exclusive STR command for 16 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief STR Exclusive (32 bit)\r
-\r
- This function performs a exclusive STR command for 32 bit values.\r
-\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/** \brief Remove the exclusive lock\r
-\r
- This function removes the exclusive lock which is created by LDREX.\r
-\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)\r
-{\r
- __ASM volatile ("clrex" ::: "memory");\r
-}\r
-\r
-\r
-/** \brief Signed Saturate\r
-\r
- This function saturates a signed value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-#define __SSAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/** \brief Unsigned Saturate\r
-\r
- This function saturates an unsigned value.\r
-\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/** \brief Count leading zeros\r
-\r
- This function counts the number of leading zeros of a data value.\r
-\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03) */\r
-\r
-\r
-\r
-\r
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all intrinsics,\r
- * Including the CMSIS ones.\r
- */\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
\r
#endif\r
\r
-/*******************************************************************************\r
-* File Name: cyPm.c\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file cyPm.c\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides an API for the power management.\r
+* \brief Provides an API for the power management.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the\r
+* \note Documentation of the API's in this file is located in the\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#include "cyPm.h"\r
\r
\r
+\r
/*******************************************************************\r
* Place your includes, defines, and code here. Do not use the merge\r
* region below unless any component datasheet suggests doing so.\r
\r
/*******************************************************************************\r
* Function Name: CyPmSaveClocks\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This function is called in preparation for entering sleep or hibernate low\r
* power modes. Saves all the states of the clocking system that do not persist\r
* during sleep/hibernate or that need to be altered in preparation for\r
* must be set manually to another source before using the\r
* CyPmSaveClocks()/CyPmRestoreClocks() functions.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* All peripheral clocks are going to be off after this API method call.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyPmRestoreClocks\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Restores any state that was preserved by the last call to CyPmSaveClocks().\r
* The Flash wait state setting is also restored.\r
*\r
* The 130 ms is given for the megahertz crystal to stabilize. Its readiness is\r
* not verified after a hold-off timeout.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyPmRestoreClocks(void) \r
{\r
/* `#START_MHZ_ECO_TIMEOUT` */\r
/* `#END` */\r
+\r
+ #ifdef CY_BOOT_CY_PM_RESTORE_CLOCKS_ECO_TIMEOUT_CALLBACK\r
+ CyBoot_CyPmRestoreClocks_EcoTimeout_Callback();\r
+ #endif /* CY_BOOT_CY_PM_RESTORE_CLOCKS_ECO_TIMEOUT_CALLBACK */\r
}\r
} /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */\r
\r
\r
- /* Temprorary set maximum flash wait cycles */\r
+ /* Temporary set maximum flash wait cycles */\r
CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES);\r
\r
/* XTAL and DSI clocks are ready to be source for Master clock. */\r
/* `#START_PLL_TIMEOUT` */\r
/* `#END` */\r
+\r
+ #ifdef CY_BOOT_CY_PM_RESTORE_CLOCKS_PLL_TIMEOUT_CALLBACK\r
+ CyBoot_CyPmRestoreClocks_PllTimeout_Callback();\r
+ #endif /* CY_BOOT_CY_PM_RESTORE_CLOCKS_PLL_TIMEOUT_CALLBACK */\r
}\r
} /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */\r
\r
\r
/*******************************************************************************\r
* Function Name: CyPmAltAct\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Puts the part into the Alternate Active (Standby) state. The Alternate Active\r
* state can allow for any of the capabilities of the device to be active, but\r
* the operation of this function is dependent on the CPU being disabled during\r
* PM_ALT_ACT_SRC_NONE) is called and PICU interrupt occurs, the CPU will be\r
* started while device remains in Alternate Active mode.\r
*\r
-* Parameters:\r
-* wakeupTime: Specifies a timer wakeup source and the frequency of that\r
+* \param wakeupTime: Specifies a timer wakeup source and the frequency of that\r
* source. For PSoC 5LP this parameter is ignored.\r
*\r
* Define Time\r
* PM_ALT_ACT_TIME_NONE None\r
-* PM_ALT_ACT_TIME_ONE_PPS One PPS: 1 second\r
-* PM_ALT_ACT_TIME_CTW_2MS CTW: 2 ms\r
-* PM_ALT_ACT_TIME_CTW_4MS CTW: 4 ms\r
-* PM_ALT_ACT_TIME_CTW_8MS CTW: 8 ms\r
-* PM_ALT_ACT_TIME_CTW_16MS CTW: 16 ms\r
-* PM_ALT_ACT_TIME_CTW_32MS CTW: 32 ms\r
-* PM_ALT_ACT_TIME_CTW_64MS CTW: 64 ms\r
-* PM_ALT_ACT_TIME_CTW_128MS CTW: 128 ms\r
-* PM_ALT_ACT_TIME_CTW_256MS CTW: 256 ms\r
-* PM_ALT_ACT_TIME_CTW_512MS CTW: 512 ms\r
-* PM_ALT_ACT_TIME_CTW_1024MS CTW: 1024 ms\r
-* PM_ALT_ACT_TIME_CTW_2048MS CTW: 2048 ms\r
-* PM_ALT_ACT_TIME_CTW_4096MS CTW: 4096 ms\r
+* \param PM_ALT_ACT_TIME_ONE_PPS One PPS: 1 second\r
+* \param PM_ALT_ACT_TIME_CTW_2MS CTW: 2 ms\r
+* \param PM_ALT_ACT_TIME_CTW_4MS CTW: 4 ms\r
+* \param PM_ALT_ACT_TIME_CTW_8MS CTW: 8 ms\r
+* \param PM_ALT_ACT_TIME_CTW_16MS CTW: 16 ms\r
+* \param PM_ALT_ACT_TIME_CTW_32MS CTW: 32 ms\r
+* \param PM_ALT_ACT_TIME_CTW_64MS CTW: 64 ms\r
+* \param PM_ALT_ACT_TIME_CTW_128MS CTW: 128 ms\r
+* \param PM_ALT_ACT_TIME_CTW_256MS CTW: 256 ms\r
+* \param PM_ALT_ACT_TIME_CTW_512MS CTW: 512 ms\r
+* \param PM_ALT_ACT_TIME_CTW_1024MS CTW: 1024 ms\r
+* \param PM_ALT_ACT_TIME_CTW_2048MS CTW: 2048 ms\r
+* \param PM_ALT_ACT_TIME_CTW_4096MS CTW: 4096 ms\r
* PM_ALT_ACT_TIME_FTW(1-256)* FTW: 10us to 2.56 ms\r
*\r
-* *Note: PM_ALT_ACT_TIME_FTW() is a macro that takes an argument that\r
+* \param *Note: PM_ALT_ACT_TIME_FTW() is a macro that takes an argument that\r
* specifies how many increments of 10 us to delay.\r
For PSoC 3 silicon the valid range of values is 1 to 256.\r
*\r
-* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if\r
-* a wakeupTime has been specified, the associated timer will be\r
-* included as a wakeup source.\r
+* \param wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if\r
+* a wakeupTime has been specified, the associated timer will\r
+* be included as a wakeup source.\r
*\r
* Define Source\r
* PM_ALT_ACT_SRC_NONE None\r
* PM_ALT_ACT_SRC_ONE_PPS One PPS**\r
* PM_ALT_ACT_SRC_LCD LCD\r
*\r
-* *Note : FTW and HVI/LVI wakeup signals are in the same mask bit.\r
-* **Note: CTW and One PPS wakeup signals are in the same mask bit.\r
+* \param *Note : FTW and HVI/LVI wakeup signals are in the same mask bit.\r
+* \param **Note: CTW and One PPS wakeup signals are in the same mask bit.\r
*\r
* When specifying a Comparator as the wakeupSource, an instance specific define\r
* that will track with the specific comparator that the instance\r
-* is placed into should be used. As an example, for a Comparator instance named MyComp the\r
-* value to OR into the mask is: MyComp_ctComp__CMP_MASK.\r
+* is placed into should be used. As an example, for a Comparator instance named\r
+* \param MyComp the value to OR into the mask is: MyComp_ctComp__CMP_MASK.\r
*\r
* When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus()\r
* function must be called upon wakeup with a corresponding parameter. Please\r
* refer to the CyPmReadStatus() API in the System Reference Guide for more\r
* information.\r
*\r
-* Return:\r
-* None\r
-*\r
* Reentrant:\r
* No\r
*\r
-* Side Effects:\r
+* \sideeffect\r
* If a wakeupTime other than NONE is specified, then upon exit the state of the\r
* specified timer will be left as specified by wakeupTime with the timer\r
* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is\r
\r
/*******************************************************************************\r
* Function Name: CyPmSleep\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Puts the part into the Sleep state.\r
*\r
* Note Before calling this function, you must manually configure the power\r
* intervals and RTC for 1PPS interval. The component must be configured to\r
* generate interrupt.\r
*\r
-* Parameters:\r
-* wakeupTime: Specifies a timer wakeup source and the frequency of that\r
+* \param wakeupTime: Specifies a timer wakeup source and the frequency of that\r
* source. For PSoC 5LP, this parameter is ignored.\r
*\r
* Define Time\r
* PM_SLEEP_TIME_NONE None\r
-* PM_SLEEP_TIME_ONE_PPS One PPS: 1 second\r
-* PM_SLEEP_TIME_CTW_2MS CTW: 2 ms\r
-* PM_SLEEP_TIME_CTW_4MS CTW: 4 ms\r
-* PM_SLEEP_TIME_CTW_8MS CTW: 8 ms\r
-* PM_SLEEP_TIME_CTW_16MS CTW: 16 ms\r
-* PM_SLEEP_TIME_CTW_32MS CTW: 32 ms\r
-* PM_SLEEP_TIME_CTW_64MS CTW: 64 ms\r
-* PM_SLEEP_TIME_CTW_128MS CTW: 128 ms\r
-* PM_SLEEP_TIME_CTW_256MS CTW: 256 ms\r
-* PM_SLEEP_TIME_CTW_512MS CTW: 512 ms\r
-* PM_SLEEP_TIME_CTW_1024MS CTW: 1024 ms\r
-* PM_SLEEP_TIME_CTW_2048MS CTW: 2048 ms\r
-* PM_SLEEP_TIME_CTW_4096MS CTW: 4096 ms\r
-*\r
-* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if\r
+* \param PM_SLEEP_TIME_ONE_PPS One PPS: 1 second\r
+* \param PM_SLEEP_TIME_CTW_2MS CTW: 2 ms\r
+* \param PM_SLEEP_TIME_CTW_4MS CTW: 4 ms\r
+* \param PM_SLEEP_TIME_CTW_8MS CTW: 8 ms\r
+* \param PM_SLEEP_TIME_CTW_16MS CTW: 16 ms\r
+* \param PM_SLEEP_TIME_CTW_32MS CTW: 32 ms\r
+* \param PM_SLEEP_TIME_CTW_64MS CTW: 64 ms\r
+* \param PM_SLEEP_TIME_CTW_128MS CTW: 128 ms\r
+* \param PM_SLEEP_TIME_CTW_256MS CTW: 256 ms\r
+* \param PM_SLEEP_TIME_CTW_512MS CTW: 512 ms\r
+* \param PM_SLEEP_TIME_CTW_1024MS CTW: 1024 ms\r
+* \param PM_SLEEP_TIME_CTW_2048MS CTW: 2048 ms\r
+* \param PM_SLEEP_TIME_CTW_4096MS CTW: 4096 ms\r
+*\r
+* \param wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if\r
* a wakeupTime has been specified the associated timer will be\r
* included as a wakeup source.\r
*\r
* PM_SLEEP_SRC_ONE_PPS One PPS*\r
* PM_SLEEP_SRC_LCD LCD\r
*\r
-* *Note: CTW and One PPS wakeup signals are in the same mask bit.\r
+* \param *Note: CTW and One PPS wakeup signals are in the same mask bit.\r
*\r
* When specifying a Comparator as the wakeupSource an instance specific define\r
* should be used that will track with the specific comparator that the instance\r
* is placed into. As an example for a Comparator instance named MyComp the\r
-* value to OR into the mask is: MyComp_ctComp__CMP_MASK.\r
+* \param value to OR into the mask is: MyComp_ctComp__CMP_MASK.\r
*\r
* When CTW or One PPS is used as a wakeup source, the CyPmReadStatus()\r
* function must be called upon wakeup with corresponding parameter. Please\r
* refer to the CyPmReadStatus() API in the System Reference Guide for more\r
* information.\r
*\r
-* Return:\r
-* None\r
-*\r
* Reentrant:\r
* No\r
*\r
/* `#END` */\r
\r
+ #ifdef CY_BOOT_CY_PM_SLEEP_BEFORE_SLEEP_CALLBACK\r
+ CyBoot_CyPmSleep_BeforeSleep_Callback();\r
+ #endif /* CY_BOOT_CY_PM_SLEEP_BEFORE_SLEEP_CALLBACK */\r
\r
/* Last moment IMO frequency change */\r
if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK))\r
/* `#END` */\r
\r
+ #ifdef CY_BOOT_CY_PM_SLEEP_AFTER_SLEEP_CALLBACK\r
+ CyBoot_CyPmSleep_AfterSleep_Callback();\r
+ #endif /* CY_BOOT_CY_PM_SLEEP_AFTER_SLEEP_CALLBACK */\r
\r
/* Restore hardware configuration */\r
CyPmHibSlpRestore();\r
\r
/*******************************************************************************\r
* Function Name: CyPmHibernate\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Puts the part into the Hibernate state.\r
*\r
-* PSoC 3 and PSoC 5LP:\r
* Before switching to Hibernate, the current status of the PICU wakeup source\r
* bit is saved and then set. This configures the device to wake up from the\r
* PICU. Make sure you have at least one pin configured to generate PICU\r
* option. Once the wakeup occurs, the PICU wakeup source bit is restored and\r
* the PSoC returns to the Active state.\r
*\r
-* Parameters:\r
-* None\r
+* Reentrant:\r
+* No\r
+*\r
+* \sideeffect\r
+* Applications must wait 20 us before re-entering hibernate or sleep after\r
+* waking up from hibernate. The 20 us allows the sleep regulator time to\r
+* stabilize before the next hibernate / sleep event occurs. The 20 us\r
+* requirement begins when the device wakes up. There is no hardware check that\r
+* this requirement is met. The specified delay should be done on ISR entry.\r
*\r
-* Return:\r
-* None\r
+* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin\r
+* is instance name of the Pins component) function must be called to clear the\r
+* latched pin events to allow the proper Hibernate mode entry and to enable\r
+* detection of future events.\r
+*\r
+* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to\r
+* measure Hibernate/Sleep regulator settling time after a reset. The holdoff\r
+* delay is measured using the rising edges of the 1 kHz ILO.\r
+*\r
+*******************************************************************************/\r
+void CyPmHibernate(void) \r
+{\r
+ CyPmHibernateEx(CY_PM_HIB_SRC_PICU);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmHibernateEx\r
+****************************************************************************//**\r
+*\r
+* Puts the part into the Hibernate state.\r
+*\r
+* The following wake up sources can be configured: PICU interrupt, Comparator0,\r
+* Comparator1, Comparator2, and Comparator3 output.\r
+*\r
+* Before switching to Hibernate, the current status of the PICU wakeup source\r
+* bit is saved and then set.\r
+*\r
+* If using PICU as the wake up source, make sure you have at least one pin\r
+* configured to generate a PICU interrupt. For pin Px.y, the register\r
+* "PICU_INTTYPE_PICUx_INTTYPEy" controls the PICU behavior. In the TRM, this\r
+* register is "PICU[0..15]_INTTYPE[0..7]." In the Pins component datasheet,\r
+* this register is referred to as the IRQ option. Once the wakeup occurs, the\r
+* PICU wakeup source bit is restored and the PSoC returns to the Active state.\r
+*\r
+* If using a comparator as the wake up source, make sure you call this function\r
+* with the 'wakeupSource' parameter set to the appropriate comparator. The part\r
+* is configured for the requested wakeup source by setting the corresponding\r
+* bits in PM_WAKEUP_CFG1 register.\r
+*\r
+* Function call CyPmHibernateEx(CY_PM_HIB_SRC_PICU) will act in the same way as\r
+* CyPmHibernate().\r
+*\r
+* \param wakeupSource:\r
+* Parameter Value Description\r
+* CY_PM_HIB_SRC_PICU PICU interrupt is set as the wake up source.\r
+* CY_PM_HIB_SRC_COMPARATOR0 Comparator 0 is set as the wake up source.\r
+* CY_PM_HIB_SRC_COMPARATOR1 Comparator 1 is set as the wake up source.\r
+* CY_PM_HIB_SRC_COMPARATOR2 Comparator 2 is set as the wake up source.\r
+* CY_PM_HIB_SRC_COMPARATOR3 Comparator 3 is set as the wake up source.\r
*\r
* Reentrant:\r
* No\r
*\r
-* Side Effects:\r
+* \sideeffect\r
* Applications must wait 20 us before re-entering hibernate or sleep after\r
* waking up from hibernate. The 20 us allows the sleep regulator time to\r
* stabilize before the next hibernate / sleep event occurs. The 20 us\r
* requirement begins when the device wakes up. There is no hardware check that\r
* this requirement is met. The specified delay should be done on ISR entry.\r
*\r
-* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is\r
-* instance name of the Pins component) function must be called to clear the\r
+* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin\r
+* is instance name of the Pins component) function must be called to clear the\r
* latched pin events to allow the proper Hibernate mode entry and to enable\r
* detection of future events.\r
*\r
* delay is measured using the rising edges of the 1 kHz ILO.\r
*\r
*******************************************************************************/\r
-void CyPmHibernate(void) \r
+void CyPmHibernateEx(uint16 wakeupSource) \r
{\r
uint8 interruptState;\r
\r
CyPmHibSaveSet();\r
\r
\r
+ /* Save and set new wake up configuration */\r
+\r
/* Save and enable only wakeup on PICU */\r
cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG;\r
- CY_PM_WAKEUP_CFG0_REG = CY_PM_WAKEUP_PICU;\r
+ CY_PM_WAKEUP_CFG0_REG = ((uint8) (wakeupSource >> 4u) & CY_PM_WAKEUP_PICU);\r
\r
+ /* Comparators */\r
cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG;\r
- CY_PM_WAKEUP_CFG1_REG = 0x00u;\r
+ CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK);\r
\r
cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG;\r
CY_PM_WAKEUP_CFG2_REG = 0x00u;\r
\r
/*******************************************************************************\r
* Function Name: CyPmReadStatus\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Manages the Power Manager Interrupt Status Register. This register has the\r
* interrupt status for the one pulse per second, central timewheel and fast\r
* timewheel timers. This hardware register clears on read. To allow for only\r
* Note You must call this function within 1 ms (1 clock cycle of the ILO)\r
* after a CTW event has occurred.\r
*\r
-* Parameters:\r
-* mask: Bits in the shadow register to clear.\r
+* \param mask: Bits in the shadow register to clear.\r
*\r
* Define Source\r
* CY_PM_FTW_INT Fast Timewheel\r
* CY_PM_CTW_INT Central Timewheel\r
* CY_PM_ONEPPS_INT One Pulse Per Second\r
*\r
-* Return:\r
+* \return\r
* Status. Same bits values as the mask parameter.\r
*\r
*******************************************************************************/\r
\r
/* Save value of register, copy it and clear desired bit */\r
interruptStatus |= CY_PM_INT_SR_REG;\r
- tmpStatus = interruptStatus;\r
+ tmpStatus = interruptStatus & (CY_PM_FTW_INT | CY_PM_CTW_INT | CY_PM_ONEPPS_INT);\r
interruptStatus &= ((uint8)(~mask));\r
\r
/* Exit critical section */\r
\r
/*******************************************************************************\r
* Function Name: CyPmHibSaveSet\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Prepare device for proper Hibernate low power mode entry:\r
* - Disables I2C backup regulator\r
* - Saves ILO power down mode state and enable it\r
* - Save LVI/HVI configuration and disable them - CyPmHviLviSaveDisable()\r
* - CyPmHibSlpSaveSet() function is called\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
* Reentrant:\r
* No\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyPmHibRestore\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Restores the device for the proper Hibernate mode exit:\r
* - Restores LVI/HVI configuration - calsl CyPmHviLviRestore()\r
* - CyPmHibSlpSaveRestore() function is called\r
* - Restores the state of 1 kHz and 100 kHz ILO and disables them\r
* - Restores the sleep regulator settings\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
static void CyPmHibRestore(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyPmCtwSetInterval\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Performs the CTW configuration:\r
* - Disables the CTW interrupt\r
* - Enables 1 kHz ILO\r
* - Sets a new CTW interval\r
*\r
-* Parameters:\r
-* ctwInterval: the CTW interval to be set.\r
+* \param ctwInterval: the CTW interval to be set.\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* Enables ILO 1 KHz clock and leaves it enabled.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyPmOppsSet\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Performs 1PPS configuration:\r
* - Starts 32 KHz XTAL\r
* - Disables 1PPS interrupts\r
* - Enables 1PPS\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
void CyPmOppsSet(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyPmFtwSetInterval\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Performs the FTW configuration:\r
* - Disables the FTW interrupt\r
* - Enables 100 kHz ILO\r
* - Sets a new FTW interval.\r
*\r
-* Parameters:\r
-* ftwInterval - FTW counter interval.\r
+* \param ftwInterval The FTW counter interval.\r
*\r
-* Return:\r
-* None\r
-*\r
-* Side Effects:\r
+* \sideeffect\r
* Enables the ILO 100 KHz clock and leaves it enabled.\r
*\r
*******************************************************************************/\r
\r
/*******************************************************************************\r
* Function Name: CyPmHibSlpSaveSet\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* This API is used for preparing the device for the Sleep and Hibernate low power\r
-* modes entry:\r
+* This API is used for preparing the device for the Sleep and Hibernate low\r
+* power modes entry:\r
* - Saves the COMP, VIDAC, DSM, and SAR routing connections (PSoC 5)\r
* - Saves the SC/CT routing connections (PSoC 3/5/5LP)\r
* - Disables the Serial Wire Viewer (SWV) (PSoC 3)\r
* - Saves the boost reference selection and sets it to internal\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
* Reentrant:\r
* No\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyPmHibSlpRestore\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
-* This API is used for restoring the device configurations after wakeup from the Sleep\r
-* and Hibernate low power modes:\r
+* This API is used for restoring the device configurations after wakeup from\r
+* the Sleep and Hibernate low power modes:\r
* - Restores the SC/CT routing connections\r
* - Restores the enable state of the Serial Wire Viewer (SWV) (PSoC 3)\r
* - Restores the boost reference selection\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
static void CyPmHibSlpRestore(void) \r
{\r
\r
/*******************************************************************************\r
* Function Name: CyPmHviLviSaveDisable\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Saves analog and digital LVI and HVI configuration and disables them.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
* Reentrant:\r
* No\r
*\r
\r
/*******************************************************************************\r
* Function Name: CyPmHviLviRestore\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Restores the analog and digital LVI and HVI configuration.\r
*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
* Reentrant:\r
* No\r
*\r
-/*******************************************************************************\r
-* File Name: cyPm.h\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file cyPm.h\r
+* \version 5.50\r
*\r
-* Description:\r
-* Provides the function definitions for the power management API.\r
+* \brief Provides the function definitions for the power management API.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the\r
+* \note Documentation of the API's in this file is located in the\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) ;\r
void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) ;\r
void CyPmHibernate(void) ;\r
+void CyPmHibernateEx(uint16 wakeupSource) ;\r
\r
uint8 CyPmReadStatus(uint8 mask) ;\r
\r
#define PM_SLEEP_SRC_ONE_PPS (0x0800u)\r
#define PM_SLEEP_SRC_LCD (0x1000u)\r
\r
+/* Wake up sources for Hibernate mode */\r
+#define CY_PM_HIB_SRC_PICU (0x0040u)\r
+#define CY_PM_HIB_SRC_COMPARATOR0 (0x0001u)\r
+#define CY_PM_HIB_SRC_COMPARATOR1 (0x0002u)\r
+#define CY_PM_HIB_SRC_COMPARATOR2 (0x0004u)\r
+#define CY_PM_HIB_SRC_COMPARATOR3 (0x0008u)\r
+\r
/* Wake up sources for Alternate Active mode */\r
#define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u)\r
#define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u)\r
#if defined(__ARMCC_VERSION) /* Instristic for Keil compilers */\r
#define CY_PM_WFI __wfi()\r
#else /* ASM for GCC & IAR */\r
- #define CY_PM_WFI asm volatile ("WFI \n")\r
+ #define CY_PM_WFI __asm volatile ("WFI \n")\r
#endif /* (__ARMCC_VERSION) */\r
\r
#else\r
/*******************************************************************************\r
* File Name: cydevice.h\r
* OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator 3.3\r
+* PSoC Creator 4.0 Update 1\r
*\r
* Description:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: cydevice_trm.h\r
* \r
-* PSoC Creator 3.3\r
+* PSoC Creator 4.0 Update 1\r
*\r
* Description:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: cydevicegnu.inc\r
* OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator 3.3\r
+* PSoC Creator 4.0 Update 1\r
*\r
* Description:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: cydevicegnu_trm.inc\r
* \r
-* PSoC Creator 3.3\r
+* PSoC Creator 4.0 Update 1\r
*\r
* Description:\r
* This file provides all of the address values for the entire PSoC device.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
;\r
; File Name: cydeviceiar.inc\r
; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator 3.3\r
+; PSoC Creator 4.0 Update 1\r
;\r
; Description:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
;\r
; File Name: cydeviceiar_trm.inc\r
; \r
-; PSoC Creator 3.3\r
+; PSoC Creator 4.0 Update 1\r
;\r
; Description:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
;\r
; File Name: cydevicerv.inc\r
; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator 3.3\r
+; PSoC Creator 4.0 Update 1\r
;\r
; Description:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
;\r
; File Name: cydevicerv_trm.inc\r
; \r
-; PSoC Creator 3.3\r
+; PSoC Creator 4.0 Update 1\r
;\r
; Description:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+; Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions, \r
; disclaimers, and limitations in the end user license agreement accompanying \r
; the software package with which this file was provided.\r
#define LED1__0__MASK 0x02u\r
#define LED1__0__PC CYREG_PRT0_PC1\r
#define LED1__0__PORT 0u\r
-#define LED1__0__SHIFT 1\r
+#define LED1__0__SHIFT 1u\r
#define LED1__AG CYREG_PRT0_AG\r
#define LED1__AMUX CYREG_PRT0_AMUX\r
#define LED1__BIE CYREG_PRT0_BIE\r
#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define LED1__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define LED1__PS CYREG_PRT0_PS\r
-#define LED1__SHIFT 1\r
+#define LED1__SHIFT 1u\r
#define LED1__SLW CYREG_PRT0_SLW\r
\r
/* SD_CD */\r
#define SD_CD__0__MASK 0x20u\r
#define SD_CD__0__PC CYREG_PRT3_PC5\r
#define SD_CD__0__PORT 3u\r
-#define SD_CD__0__SHIFT 5\r
+#define SD_CD__0__SHIFT 5u\r
#define SD_CD__AG CYREG_PRT3_AG\r
#define SD_CD__AMUX CYREG_PRT3_AMUX\r
#define SD_CD__BIE CYREG_PRT3_BIE\r
#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
#define SD_CD__PS CYREG_PRT3_PS\r
-#define SD_CD__SHIFT 5\r
+#define SD_CD__SHIFT 5u\r
#define SD_CD__SLW CYREG_PRT3_SLW\r
\r
/* SD_CS */\r
#define SD_CS__0__MASK 0x10u\r
#define SD_CS__0__PC CYREG_PRT3_PC4\r
#define SD_CS__0__PORT 3u\r
-#define SD_CS__0__SHIFT 4\r
+#define SD_CS__0__SHIFT 4u\r
#define SD_CS__AG CYREG_PRT3_AG\r
#define SD_CS__AMUX CYREG_PRT3_AMUX\r
#define SD_CS__BIE CYREG_PRT3_BIE\r
#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
#define SD_CS__PS CYREG_PRT3_PS\r
-#define SD_CS__SHIFT 4\r
+#define SD_CS__SHIFT 4u\r
#define SD_CS__SLW CYREG_PRT3_SLW\r
\r
/* USBFS_arb_int */\r
#define USBFS_Dm__0__MASK 0x80u\r
#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1\r
#define USBFS_Dm__0__PORT 15u\r
-#define USBFS_Dm__0__SHIFT 7\r
+#define USBFS_Dm__0__SHIFT 7u\r
#define USBFS_Dm__AG CYREG_PRT15_AG\r
#define USBFS_Dm__AMUX CYREG_PRT15_AMUX\r
#define USBFS_Dm__BIE CYREG_PRT15_BIE\r
#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
#define USBFS_Dm__PS CYREG_PRT15_PS\r
-#define USBFS_Dm__SHIFT 7\r
+#define USBFS_Dm__SHIFT 7u\r
#define USBFS_Dm__SLW CYREG_PRT15_SLW\r
\r
/* USBFS_Dp */\r
#define USBFS_Dp__0__MASK 0x40u\r
#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0\r
#define USBFS_Dp__0__PORT 15u\r
-#define USBFS_Dp__0__SHIFT 6\r
+#define USBFS_Dp__0__SHIFT 6u\r
#define USBFS_Dp__AG CYREG_PRT15_AG\r
#define USBFS_Dp__AMUX CYREG_PRT15_AMUX\r
#define USBFS_Dp__BIE CYREG_PRT15_BIE\r
#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
#define USBFS_Dp__PS CYREG_PRT15_PS\r
-#define USBFS_Dp__SHIFT 6\r
+#define USBFS_Dp__SHIFT 6u\r
#define USBFS_Dp__SLW CYREG_PRT15_SLW\r
#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15\r
\r
#define EXTLED__0__MASK 0x01u\r
#define EXTLED__0__PC CYREG_PRT0_PC0\r
#define EXTLED__0__PORT 0u\r
-#define EXTLED__0__SHIFT 0\r
+#define EXTLED__0__SHIFT 0u\r
#define EXTLED__AG CYREG_PRT0_AG\r
#define EXTLED__AMUX CYREG_PRT0_AMUX\r
#define EXTLED__BIE CYREG_PRT0_BIE\r
#define EXTLED__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define EXTLED__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define EXTLED__PS CYREG_PRT0_PS\r
-#define EXTLED__SHIFT 0\r
+#define EXTLED__SHIFT 0u\r
#define EXTLED__SLW CYREG_PRT0_SLW\r
\r
/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB08_MSK\r
-#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB08_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB04_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB04_ST\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1\r
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0\r
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__2__POS 2\r
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
-#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB06_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB06_ST\r
\r
/* SD_SCK */\r
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2\r
#define SD_SCK__0__MASK 0x04u\r
#define SD_SCK__0__PC CYREG_PRT3_PC2\r
#define SD_SCK__0__PORT 3u\r
-#define SD_SCK__0__SHIFT 2\r
+#define SD_SCK__0__SHIFT 2u\r
#define SD_SCK__AG CYREG_PRT3_AG\r
#define SD_SCK__AMUX CYREG_PRT3_AMUX\r
#define SD_SCK__BIE CYREG_PRT3_BIE\r
#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
#define SD_SCK__PS CYREG_PRT3_PS\r
-#define SD_SCK__SHIFT 2\r
+#define SD_SCK__SHIFT 2u\r
#define SD_SCK__SLW CYREG_PRT3_SLW\r
\r
/* SCSI_In */\r
#define SCSI_In__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In__0__PS CYREG_PRT2_PS\r
-#define SCSI_In__0__SHIFT 1\r
+#define SCSI_In__0__SHIFT 1u\r
#define SCSI_In__0__SLW CYREG_PRT2_SLW\r
#define SCSI_In__1__AG CYREG_PRT4_AG\r
#define SCSI_In__1__AMUX CYREG_PRT4_AMUX\r
#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_In__1__PS CYREG_PRT4_PS\r
-#define SCSI_In__1__SHIFT 6\r
+#define SCSI_In__1__SHIFT 6u\r
#define SCSI_In__1__SLW CYREG_PRT4_SLW\r
#define SCSI_In__2__AG CYREG_PRT4_AG\r
#define SCSI_In__2__AMUX CYREG_PRT4_AMUX\r
#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_In__2__PS CYREG_PRT4_PS\r
-#define SCSI_In__2__SHIFT 2\r
+#define SCSI_In__2__SHIFT 2u\r
#define SCSI_In__2__SLW CYREG_PRT4_SLW\r
#define SCSI_In__3__AG CYREG_PRT0_AG\r
#define SCSI_In__3__AMUX CYREG_PRT0_AMUX\r
#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_In__3__PS CYREG_PRT0_PS\r
-#define SCSI_In__3__SHIFT 5\r
+#define SCSI_In__3__SHIFT 5u\r
#define SCSI_In__3__SLW CYREG_PRT0_SLW\r
#define SCSI_In__4__AG CYREG_PRT0_AG\r
#define SCSI_In__4__AMUX CYREG_PRT0_AMUX\r
#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_In__4__PS CYREG_PRT0_PS\r
-#define SCSI_In__4__SHIFT 4\r
+#define SCSI_In__4__SHIFT 4u\r
#define SCSI_In__4__SLW CYREG_PRT0_SLW\r
#define SCSI_In__CD__AG CYREG_PRT4_AG\r
#define SCSI_In__CD__AMUX CYREG_PRT4_AMUX\r
#define SCSI_In__CD__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_In__CD__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_In__CD__PS CYREG_PRT4_PS\r
-#define SCSI_In__CD__SHIFT 2\r
+#define SCSI_In__CD__SHIFT 2u\r
#define SCSI_In__CD__SLW CYREG_PRT4_SLW\r
#define SCSI_In__DBP__AG CYREG_PRT2_AG\r
#define SCSI_In__DBP__AMUX CYREG_PRT2_AMUX\r
#define SCSI_In__DBP__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In__DBP__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In__DBP__PS CYREG_PRT2_PS\r
-#define SCSI_In__DBP__SHIFT 1\r
+#define SCSI_In__DBP__SHIFT 1u\r
#define SCSI_In__DBP__SLW CYREG_PRT2_SLW\r
#define SCSI_In__IO__AG CYREG_PRT0_AG\r
#define SCSI_In__IO__AMUX CYREG_PRT0_AMUX\r
#define SCSI_In__IO__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_In__IO__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_In__IO__PS CYREG_PRT0_PS\r
-#define SCSI_In__IO__SHIFT 4\r
+#define SCSI_In__IO__SHIFT 4u\r
#define SCSI_In__IO__SLW CYREG_PRT0_SLW\r
#define SCSI_In__MSG__AG CYREG_PRT4_AG\r
#define SCSI_In__MSG__AMUX CYREG_PRT4_AMUX\r
#define SCSI_In__MSG__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_In__MSG__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_In__MSG__PS CYREG_PRT4_PS\r
-#define SCSI_In__MSG__SHIFT 6\r
+#define SCSI_In__MSG__SHIFT 6u\r
#define SCSI_In__MSG__SLW CYREG_PRT4_SLW\r
#define SCSI_In__REQ__AG CYREG_PRT0_AG\r
#define SCSI_In__REQ__AMUX CYREG_PRT0_AMUX\r
#define SCSI_In__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_In__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_In__REQ__PS CYREG_PRT0_PS\r
-#define SCSI_In__REQ__SHIFT 5\r
+#define SCSI_In__REQ__SHIFT 5u\r
#define SCSI_In__REQ__SLW CYREG_PRT0_SLW\r
\r
/* SCSI_In_DBx */\r
#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_In_DBx__0__PS CYREG_PRT5_PS\r
-#define SCSI_In_DBx__0__SHIFT 3\r
+#define SCSI_In_DBx__0__SHIFT 3u\r
#define SCSI_In_DBx__0__SLW CYREG_PRT5_SLW\r
#define SCSI_In_DBx__1__AG CYREG_PRT5_AG\r
#define SCSI_In_DBx__1__AMUX CYREG_PRT5_AMUX\r
#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_In_DBx__1__PS CYREG_PRT5_PS\r
-#define SCSI_In_DBx__1__SHIFT 2\r
+#define SCSI_In_DBx__1__SHIFT 2u\r
#define SCSI_In_DBx__1__SLW CYREG_PRT5_SLW\r
#define SCSI_In_DBx__2__AG CYREG_PRT6_AG\r
#define SCSI_In_DBx__2__AMUX CYREG_PRT6_AMUX\r
#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_In_DBx__2__PS CYREG_PRT6_PS\r
-#define SCSI_In_DBx__2__SHIFT 7\r
+#define SCSI_In_DBx__2__SHIFT 7u\r
#define SCSI_In_DBx__2__SLW CYREG_PRT6_SLW\r
#define SCSI_In_DBx__3__AG CYREG_PRT6_AG\r
#define SCSI_In_DBx__3__AMUX CYREG_PRT6_AMUX\r
#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_In_DBx__3__PS CYREG_PRT6_PS\r
-#define SCSI_In_DBx__3__SHIFT 6\r
+#define SCSI_In_DBx__3__SHIFT 6u\r
#define SCSI_In_DBx__3__SLW CYREG_PRT6_SLW\r
#define SCSI_In_DBx__4__AG CYREG_PRT12_AG\r
#define SCSI_In_DBx__4__BIE CYREG_PRT12_BIE\r
#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
#define SCSI_In_DBx__4__PS CYREG_PRT12_PS\r
-#define SCSI_In_DBx__4__SHIFT 5\r
+#define SCSI_In_DBx__4__SHIFT 5u\r
#define SCSI_In_DBx__4__SIO_CFG CYREG_PRT12_SIO_CFG\r
#define SCSI_In_DBx__4__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
#define SCSI_In_DBx__4__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
#define SCSI_In_DBx__5__PS CYREG_PRT12_PS\r
-#define SCSI_In_DBx__5__SHIFT 4\r
+#define SCSI_In_DBx__5__SHIFT 4u\r
#define SCSI_In_DBx__5__SIO_CFG CYREG_PRT12_SIO_CFG\r
#define SCSI_In_DBx__5__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
#define SCSI_In_DBx__5__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__6__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__6__SHIFT 5\r
+#define SCSI_In_DBx__6__SHIFT 5u\r
#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW\r
#define SCSI_In_DBx__7__AG CYREG_PRT2_AG\r
#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX\r
#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__7__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__7__SHIFT 4\r
+#define SCSI_In_DBx__7__SHIFT 4u\r
#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW\r
#define SCSI_In_DBx__DB0__AG CYREG_PRT5_AG\r
#define SCSI_In_DBx__DB0__AMUX CYREG_PRT5_AMUX\r
#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_In_DBx__DB0__PS CYREG_PRT5_PS\r
-#define SCSI_In_DBx__DB0__SHIFT 3\r
+#define SCSI_In_DBx__DB0__SHIFT 3u\r
#define SCSI_In_DBx__DB0__SLW CYREG_PRT5_SLW\r
#define SCSI_In_DBx__DB1__AG CYREG_PRT5_AG\r
#define SCSI_In_DBx__DB1__AMUX CYREG_PRT5_AMUX\r
#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_In_DBx__DB1__PS CYREG_PRT5_PS\r
-#define SCSI_In_DBx__DB1__SHIFT 2\r
+#define SCSI_In_DBx__DB1__SHIFT 2u\r
#define SCSI_In_DBx__DB1__SLW CYREG_PRT5_SLW\r
#define SCSI_In_DBx__DB2__AG CYREG_PRT6_AG\r
#define SCSI_In_DBx__DB2__AMUX CYREG_PRT6_AMUX\r
#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_In_DBx__DB2__PS CYREG_PRT6_PS\r
-#define SCSI_In_DBx__DB2__SHIFT 7\r
+#define SCSI_In_DBx__DB2__SHIFT 7u\r
#define SCSI_In_DBx__DB2__SLW CYREG_PRT6_SLW\r
#define SCSI_In_DBx__DB3__AG CYREG_PRT6_AG\r
#define SCSI_In_DBx__DB3__AMUX CYREG_PRT6_AMUX\r
#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_In_DBx__DB3__PS CYREG_PRT6_PS\r
-#define SCSI_In_DBx__DB3__SHIFT 6\r
+#define SCSI_In_DBx__DB3__SHIFT 6u\r
#define SCSI_In_DBx__DB3__SLW CYREG_PRT6_SLW\r
#define SCSI_In_DBx__DB4__AG CYREG_PRT12_AG\r
#define SCSI_In_DBx__DB4__BIE CYREG_PRT12_BIE\r
#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
#define SCSI_In_DBx__DB4__PS CYREG_PRT12_PS\r
-#define SCSI_In_DBx__DB4__SHIFT 5\r
+#define SCSI_In_DBx__DB4__SHIFT 5u\r
#define SCSI_In_DBx__DB4__SIO_CFG CYREG_PRT12_SIO_CFG\r
#define SCSI_In_DBx__DB4__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
#define SCSI_In_DBx__DB4__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
#define SCSI_In_DBx__DB5__PS CYREG_PRT12_PS\r
-#define SCSI_In_DBx__DB5__SHIFT 4\r
+#define SCSI_In_DBx__DB5__SHIFT 4u\r
#define SCSI_In_DBx__DB5__SIO_CFG CYREG_PRT12_SIO_CFG\r
#define SCSI_In_DBx__DB5__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
#define SCSI_In_DBx__DB5__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB6__SHIFT 5\r
+#define SCSI_In_DBx__DB6__SHIFT 5u\r
#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW\r
#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG\r
#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX\r
#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB7__SHIFT 4\r
+#define SCSI_In_DBx__DB7__SHIFT 4u\r
#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW\r
\r
/* SD_MISO */\r
#define SD_MISO__0__MASK 0x02u\r
#define SD_MISO__0__PC CYREG_PRT3_PC1\r
#define SD_MISO__0__PORT 3u\r
-#define SD_MISO__0__SHIFT 1\r
+#define SD_MISO__0__SHIFT 1u\r
#define SD_MISO__AG CYREG_PRT3_AG\r
#define SD_MISO__AMUX CYREG_PRT3_AMUX\r
#define SD_MISO__BIE CYREG_PRT3_BIE\r
#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
#define SD_MISO__PS CYREG_PRT3_PS\r
-#define SD_MISO__SHIFT 1\r
+#define SD_MISO__SHIFT 1u\r
#define SD_MISO__SLW CYREG_PRT3_SLW\r
\r
/* SD_MOSI */\r
#define SD_MOSI__0__MASK 0x08u\r
#define SD_MOSI__0__PC CYREG_PRT3_PC3\r
#define SD_MOSI__0__PORT 3u\r
-#define SD_MOSI__0__SHIFT 3\r
+#define SD_MOSI__0__SHIFT 3u\r
#define SD_MOSI__AG CYREG_PRT3_AG\r
#define SD_MOSI__AMUX CYREG_PRT3_AMUX\r
#define SD_MOSI__BIE CYREG_PRT3_BIE\r
#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
#define SD_MOSI__PS CYREG_PRT3_PS\r
-#define SD_MOSI__SHIFT 3\r
+#define SD_MOSI__SHIFT 3u\r
#define SD_MOSI__SLW CYREG_PRT3_SLW\r
\r
/* SCSI_CLK */\r
#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
#define SCSI_Out__0__PS CYREG_PRT15_PS\r
-#define SCSI_Out__0__SHIFT 5\r
+#define SCSI_Out__0__SHIFT 5u\r
#define SCSI_Out__0__SLW CYREG_PRT15_SLW\r
#define SCSI_Out__1__AG CYREG_PRT15_AG\r
#define SCSI_Out__1__AMUX CYREG_PRT15_AMUX\r
#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
#define SCSI_Out__1__PS CYREG_PRT15_PS\r
-#define SCSI_Out__1__SHIFT 4\r
+#define SCSI_Out__1__SHIFT 4u\r
#define SCSI_Out__1__SLW CYREG_PRT15_SLW\r
#define SCSI_Out__2__AG CYREG_PRT6_AG\r
#define SCSI_Out__2__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Out__2__PS CYREG_PRT6_PS\r
-#define SCSI_Out__2__SHIFT 1\r
+#define SCSI_Out__2__SHIFT 1u\r
#define SCSI_Out__2__SLW CYREG_PRT6_SLW\r
#define SCSI_Out__3__AG CYREG_PRT6_AG\r
#define SCSI_Out__3__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Out__3__PS CYREG_PRT6_PS\r
-#define SCSI_Out__3__SHIFT 0\r
+#define SCSI_Out__3__SHIFT 0u\r
#define SCSI_Out__3__SLW CYREG_PRT6_SLW\r
#define SCSI_Out__4__AG CYREG_PRT4_AG\r
#define SCSI_Out__4__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Out__4__PS CYREG_PRT4_PS\r
-#define SCSI_Out__4__SHIFT 5\r
+#define SCSI_Out__4__SHIFT 5u\r
#define SCSI_Out__4__SLW CYREG_PRT4_SLW\r
#define SCSI_Out__5__AG CYREG_PRT4_AG\r
#define SCSI_Out__5__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Out__5__PS CYREG_PRT4_PS\r
-#define SCSI_Out__5__SHIFT 4\r
+#define SCSI_Out__5__SHIFT 4u\r
#define SCSI_Out__5__SLW CYREG_PRT4_SLW\r
#define SCSI_Out__6__AG CYREG_PRT0_AG\r
#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__6__PS CYREG_PRT0_PS\r
-#define SCSI_Out__6__SHIFT 7\r
+#define SCSI_Out__6__SHIFT 7u\r
#define SCSI_Out__6__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__7__AG CYREG_PRT0_AG\r
#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__7__PS CYREG_PRT0_PS\r
-#define SCSI_Out__7__SHIFT 6\r
+#define SCSI_Out__7__SHIFT 6u\r
#define SCSI_Out__7__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__8__AG CYREG_PRT0_AG\r
#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__8__PS CYREG_PRT0_PS\r
-#define SCSI_Out__8__SHIFT 3\r
+#define SCSI_Out__8__SHIFT 3u\r
#define SCSI_Out__8__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__9__AG CYREG_PRT0_AG\r
#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__9__PS CYREG_PRT0_PS\r
-#define SCSI_Out__9__SHIFT 2\r
+#define SCSI_Out__9__SHIFT 2u\r
#define SCSI_Out__9__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__ACK__AG CYREG_PRT6_AG\r
#define SCSI_Out__ACK__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Out__ACK__PS CYREG_PRT6_PS\r
-#define SCSI_Out__ACK__SHIFT 0\r
+#define SCSI_Out__ACK__SHIFT 0u\r
#define SCSI_Out__ACK__SLW CYREG_PRT6_SLW\r
#define SCSI_Out__ATN__AG CYREG_PRT15_AG\r
#define SCSI_Out__ATN__AMUX CYREG_PRT15_AMUX\r
#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
#define SCSI_Out__ATN__PS CYREG_PRT15_PS\r
-#define SCSI_Out__ATN__SHIFT 4\r
+#define SCSI_Out__ATN__SHIFT 4u\r
#define SCSI_Out__ATN__SLW CYREG_PRT15_SLW\r
#define SCSI_Out__BSY__AG CYREG_PRT6_AG\r
#define SCSI_Out__BSY__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Out__BSY__PS CYREG_PRT6_PS\r
-#define SCSI_Out__BSY__SHIFT 1\r
+#define SCSI_Out__BSY__SHIFT 1u\r
#define SCSI_Out__BSY__SLW CYREG_PRT6_SLW\r
#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG\r
#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS\r
-#define SCSI_Out__CD_raw__SHIFT 6\r
+#define SCSI_Out__CD_raw__SHIFT 6u\r
#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__DBP_raw__AG CYREG_PRT15_AG\r
#define SCSI_Out__DBP_raw__AMUX CYREG_PRT15_AMUX\r
#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
#define SCSI_Out__DBP_raw__PS CYREG_PRT15_PS\r
-#define SCSI_Out__DBP_raw__SHIFT 5\r
+#define SCSI_Out__DBP_raw__SHIFT 5u\r
#define SCSI_Out__DBP_raw__SLW CYREG_PRT15_SLW\r
#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG\r
#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS\r
-#define SCSI_Out__IO_raw__SHIFT 2\r
+#define SCSI_Out__IO_raw__SHIFT 2u\r
#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__MSG_raw__AG CYREG_PRT4_AG\r
#define SCSI_Out__MSG_raw__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Out__MSG_raw__PS CYREG_PRT4_PS\r
-#define SCSI_Out__MSG_raw__SHIFT 4\r
+#define SCSI_Out__MSG_raw__SHIFT 4u\r
#define SCSI_Out__MSG_raw__SLW CYREG_PRT4_SLW\r
#define SCSI_Out__REQ__AG CYREG_PRT0_AG\r
#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__REQ__PS CYREG_PRT0_PS\r
-#define SCSI_Out__REQ__SHIFT 3\r
+#define SCSI_Out__REQ__SHIFT 3u\r
#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW\r
#define SCSI_Out__RST__AG CYREG_PRT4_AG\r
#define SCSI_Out__RST__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Out__RST__PS CYREG_PRT4_PS\r
-#define SCSI_Out__RST__SHIFT 5\r
+#define SCSI_Out__RST__SHIFT 5u\r
#define SCSI_Out__RST__SLW CYREG_PRT4_SLW\r
#define SCSI_Out__SEL__AG CYREG_PRT0_AG\r
#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX\r
#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out__SEL__PS CYREG_PRT0_PS\r
-#define SCSI_Out__SEL__SHIFT 7\r
+#define SCSI_Out__SEL__SHIFT 7u\r
#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW\r
\r
/* SCSI_Out_Bits */\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
\r
/* SCSI_Out_Ctl */\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK\r
\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG\r
#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_Out_DBx__0__PS CYREG_PRT5_PS\r
-#define SCSI_Out_DBx__0__SHIFT 1\r
+#define SCSI_Out_DBx__0__SHIFT 1u\r
#define SCSI_Out_DBx__0__SLW CYREG_PRT5_SLW\r
#define SCSI_Out_DBx__1__AG CYREG_PRT5_AG\r
#define SCSI_Out_DBx__1__AMUX CYREG_PRT5_AMUX\r
#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_Out_DBx__1__PS CYREG_PRT5_PS\r
-#define SCSI_Out_DBx__1__SHIFT 0\r
+#define SCSI_Out_DBx__1__SHIFT 0u\r
#define SCSI_Out_DBx__1__SLW CYREG_PRT5_SLW\r
#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG\r
#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__2__SHIFT 5\r
+#define SCSI_Out_DBx__2__SHIFT 5u\r
#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW\r
#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG\r
#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__3__SHIFT 4\r
+#define SCSI_Out_DBx__3__SHIFT 4u\r
#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW\r
#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG\r
#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX\r
#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS\r
-#define SCSI_Out_DBx__4__SHIFT 7\r
+#define SCSI_Out_DBx__4__SHIFT 7u\r
#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW\r
#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG\r
#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX\r
#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS\r
-#define SCSI_Out_DBx__5__SHIFT 6\r
+#define SCSI_Out_DBx__5__SHIFT 6u\r
#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW\r
#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG\r
#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX\r
#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS\r
-#define SCSI_Out_DBx__6__SHIFT 3\r
+#define SCSI_Out_DBx__6__SHIFT 3u\r
#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW\r
#define SCSI_Out_DBx__7__AG CYREG_PRT2_AG\r
#define SCSI_Out_DBx__7__AMUX CYREG_PRT2_AMUX\r
#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_Out_DBx__7__PS CYREG_PRT2_PS\r
-#define SCSI_Out_DBx__7__SHIFT 2\r
+#define SCSI_Out_DBx__7__SHIFT 2u\r
#define SCSI_Out_DBx__7__SLW CYREG_PRT2_SLW\r
#define SCSI_Out_DBx__DB0__AG CYREG_PRT5_AG\r
#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT5_AMUX\r
#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_Out_DBx__DB0__PS CYREG_PRT5_PS\r
-#define SCSI_Out_DBx__DB0__SHIFT 1\r
+#define SCSI_Out_DBx__DB0__SHIFT 1u\r
#define SCSI_Out_DBx__DB0__SLW CYREG_PRT5_SLW\r
#define SCSI_Out_DBx__DB1__AG CYREG_PRT5_AG\r
#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT5_AMUX\r
#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_Out_DBx__DB1__PS CYREG_PRT5_PS\r
-#define SCSI_Out_DBx__DB1__SHIFT 0\r
+#define SCSI_Out_DBx__DB1__SHIFT 0u\r
#define SCSI_Out_DBx__DB1__SLW CYREG_PRT5_SLW\r
#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG\r
#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB2__SHIFT 5\r
+#define SCSI_Out_DBx__DB2__SHIFT 5u\r
#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW\r
#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG\r
#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB3__SHIFT 4\r
+#define SCSI_Out_DBx__DB3__SHIFT 4u\r
#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW\r
#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG\r
#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX\r
#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS\r
-#define SCSI_Out_DBx__DB4__SHIFT 7\r
+#define SCSI_Out_DBx__DB4__SHIFT 7u\r
#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW\r
#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG\r
#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX\r
#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS\r
-#define SCSI_Out_DBx__DB5__SHIFT 6\r
+#define SCSI_Out_DBx__DB5__SHIFT 6u\r
#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW\r
#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG\r
#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX\r
#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS\r
-#define SCSI_Out_DBx__DB6__SHIFT 3\r
+#define SCSI_Out_DBx__DB6__SHIFT 3u\r
#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW\r
#define SCSI_Out_DBx__DB7__AG CYREG_PRT2_AG\r
#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT2_AMUX\r
#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_Out_DBx__DB7__PS CYREG_PRT2_PS\r
-#define SCSI_Out_DBx__DB7__SHIFT 2\r
+#define SCSI_Out_DBx__DB7__SHIFT 2u\r
#define SCSI_Out_DBx__DB7__SLW CYREG_PRT2_SLW\r
\r
/* SD_RX_DMA */\r
#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_Noise__0__PS CYREG_PRT2_PS\r
-#define SCSI_Noise__0__SHIFT 0\r
+#define SCSI_Noise__0__SHIFT 0u\r
#define SCSI_Noise__0__SLW CYREG_PRT2_SLW\r
#define SCSI_Noise__1__AG CYREG_PRT6_AG\r
#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Noise__1__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__1__SHIFT 3\r
+#define SCSI_Noise__1__SHIFT 3u\r
#define SCSI_Noise__1__SLW CYREG_PRT6_SLW\r
#define SCSI_Noise__2__AG CYREG_PRT4_AG\r
#define SCSI_Noise__2__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Noise__2__PS CYREG_PRT4_PS\r
-#define SCSI_Noise__2__SHIFT 3\r
+#define SCSI_Noise__2__SHIFT 3u\r
#define SCSI_Noise__2__SLW CYREG_PRT4_SLW\r
#define SCSI_Noise__3__AG CYREG_PRT4_AG\r
#define SCSI_Noise__3__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Noise__3__PS CYREG_PRT4_PS\r
-#define SCSI_Noise__3__SHIFT 7\r
+#define SCSI_Noise__3__SHIFT 7u\r
#define SCSI_Noise__3__SLW CYREG_PRT4_SLW\r
#define SCSI_Noise__4__AG CYREG_PRT6_AG\r
#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Noise__4__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__4__SHIFT 2\r
+#define SCSI_Noise__4__SHIFT 2u\r
#define SCSI_Noise__4__SLW CYREG_PRT6_SLW\r
#define SCSI_Noise__ACK__AG CYREG_PRT6_AG\r
#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Noise__ACK__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__ACK__SHIFT 2\r
+#define SCSI_Noise__ACK__SHIFT 2u\r
#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW\r
#define SCSI_Noise__ATN__AG CYREG_PRT2_AG\r
#define SCSI_Noise__ATN__AMUX CYREG_PRT2_AMUX\r
#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_Noise__ATN__PS CYREG_PRT2_PS\r
-#define SCSI_Noise__ATN__SHIFT 0\r
+#define SCSI_Noise__ATN__SHIFT 0u\r
#define SCSI_Noise__ATN__SLW CYREG_PRT2_SLW\r
#define SCSI_Noise__BSY__AG CYREG_PRT6_AG\r
#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX\r
#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_Noise__BSY__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__BSY__SHIFT 3\r
+#define SCSI_Noise__BSY__SHIFT 3u\r
#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW\r
#define SCSI_Noise__RST__AG CYREG_PRT4_AG\r
#define SCSI_Noise__RST__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Noise__RST__PS CYREG_PRT4_PS\r
-#define SCSI_Noise__RST__SHIFT 7\r
+#define SCSI_Noise__RST__SHIFT 7u\r
#define SCSI_Noise__RST__SLW CYREG_PRT4_SLW\r
#define SCSI_Noise__SEL__AG CYREG_PRT4_AG\r
#define SCSI_Noise__SEL__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
#define SCSI_Noise__SEL__PS CYREG_PRT4_PS\r
-#define SCSI_Noise__SEL__SHIFT 3\r
+#define SCSI_Noise__SEL__SHIFT 3u\r
#define SCSI_Noise__SEL__SLW CYREG_PRT4_SLW\r
\r
/* scsiTarget */\r
#define scsiTarget_StatusReg__0__POS 0\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__2__POS 2\r
#define scsiTarget_StatusReg__3__MASK 0x08u\r
#define scsiTarget_StatusReg__4__MASK 0x10u\r
#define scsiTarget_StatusReg__4__POS 4\r
#define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST\r
\r
/* Debug_Timer_Interrupt */\r
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST\r
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST\r
\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK\r
\r
/* SCSI_Parity_Error */\r
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B1_UDB05_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B1_UDB05_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB03_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB03_ST\r
\r
/* Miscellaneous */\r
#define BCLK__BUS_CLK__HZ 50000000U\r
#define BCLK__BUS_CLK__KHZ 50000U\r
#define BCLK__BUS_CLK__MHZ 50U\r
#define CY_PROJECT_NAME "SCSI2SD"\r
-#define CY_VERSION "PSoC Creator 3.3"\r
+#define CY_VERSION "PSoC Creator 4.0 Update 1"\r
#define CYDEV_CHIP_DIE_LEOPARD 1u\r
-#define CYDEV_CHIP_DIE_PANTHER 18u\r
-#define CYDEV_CHIP_DIE_PSOC4A 10u\r
-#define CYDEV_CHIP_DIE_PSOC5LP 17u\r
+#define CYDEV_CHIP_DIE_PSOC4A 12u\r
+#define CYDEV_CHIP_DIE_PSOC5LP 19u\r
+#define CYDEV_CHIP_DIE_PSOC5TM 20u\r
#define CYDEV_CHIP_DIE_TMA4 2u\r
#define CYDEV_CHIP_DIE_UNKNOWN 0u\r
+#define CYDEV_CHIP_FAMILY_FM0P 4u\r
+#define CYDEV_CHIP_FAMILY_FM3 5u\r
+#define CYDEV_CHIP_FAMILY_FM4 6u\r
#define CYDEV_CHIP_FAMILY_PSOC3 1u\r
#define CYDEV_CHIP_FAMILY_PSOC4 2u\r
#define CYDEV_CHIP_FAMILY_PSOC5 3u\r
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5\r
#define CYDEV_CHIP_JTAG_ID 0x2E133069u\r
#define CYDEV_CHIP_MEMBER_3A 1u\r
-#define CYDEV_CHIP_MEMBER_4A 10u\r
-#define CYDEV_CHIP_MEMBER_4C 15u\r
-#define CYDEV_CHIP_MEMBER_4D 6u\r
+#define CYDEV_CHIP_MEMBER_4A 12u\r
+#define CYDEV_CHIP_MEMBER_4C 18u\r
+#define CYDEV_CHIP_MEMBER_4D 8u\r
#define CYDEV_CHIP_MEMBER_4E 4u\r
-#define CYDEV_CHIP_MEMBER_4F 11u\r
+#define CYDEV_CHIP_MEMBER_4F 13u\r
#define CYDEV_CHIP_MEMBER_4G 2u\r
-#define CYDEV_CHIP_MEMBER_4H 9u\r
-#define CYDEV_CHIP_MEMBER_4I 14u\r
-#define CYDEV_CHIP_MEMBER_4J 7u\r
-#define CYDEV_CHIP_MEMBER_4K 8u\r
-#define CYDEV_CHIP_MEMBER_4L 13u\r
-#define CYDEV_CHIP_MEMBER_4M 12u\r
-#define CYDEV_CHIP_MEMBER_4N 5u\r
+#define CYDEV_CHIP_MEMBER_4H 11u\r
+#define CYDEV_CHIP_MEMBER_4I 17u\r
+#define CYDEV_CHIP_MEMBER_4J 9u\r
+#define CYDEV_CHIP_MEMBER_4K 10u\r
+#define CYDEV_CHIP_MEMBER_4L 16u\r
+#define CYDEV_CHIP_MEMBER_4M 15u\r
+#define CYDEV_CHIP_MEMBER_4N 6u\r
+#define CYDEV_CHIP_MEMBER_4O 5u\r
+#define CYDEV_CHIP_MEMBER_4P 14u\r
+#define CYDEV_CHIP_MEMBER_4Q 7u\r
#define CYDEV_CHIP_MEMBER_4U 3u\r
-#define CYDEV_CHIP_MEMBER_5A 17u\r
-#define CYDEV_CHIP_MEMBER_5B 16u\r
+#define CYDEV_CHIP_MEMBER_5A 20u\r
+#define CYDEV_CHIP_MEMBER_5B 19u\r
+#define CYDEV_CHIP_MEMBER_FM3 24u\r
+#define CYDEV_CHIP_MEMBER_FM4 25u\r
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 21u\r
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 22u\r
+#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 23u\r
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u\r
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B\r
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED\r
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u\r
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u\r
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u\r
-#define CYDEV_CHIP_REV_PANTHER_ES0 0u\r
-#define CYDEV_CHIP_REV_PANTHER_ES1 1u\r
-#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u\r
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u\r
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u\r
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u\r
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u\r
+#define CYDEV_CHIP_REV_PSOC5TM_ES0 0u\r
+#define CYDEV_CHIP_REV_PSOC5TM_ES1 1u\r
+#define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1u\r
#define CYDEV_CHIP_REV_TMA4_ES 17u\r
#define CYDEV_CHIP_REV_TMA4_ES2 33u\r
#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u\r
#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_5A_ES0 0u\r
#define CYDEV_CHIP_REVISION_5A_ES1 1u\r
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u\r
#define CYDEV_CHIP_REVISION_5B_ES0 0u\r
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION\r
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED\r
#define CYDEV_CONFIG_FASTBOOT_ENABLED 1\r
/*******************************************************************************\r
* File Name: cyfitter_cfg.c\r
* \r
-* PSoC Creator 3.3\r
+* PSoC Creator 4.0 Update 1\r
*\r
* Description:\r
* This file contains device initialization code.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#define CYPACKED_ATTR __attribute__ ((packed))\r
#define CYALIGNED __attribute__ ((aligned))\r
#define CY_CFG_UNUSED __attribute__ ((unused))\r
- #define CY_CFG_SECTION __attribute__ ((section(".psocinit")))\r
+ #ifndef CY_CFG_SECTION\r
+ #define CY_CFG_SECTION __attribute__ ((section(".psocinit")))\r
+ #endif\r
\r
#if defined(__ARMCC_VERSION)\r
#define CY_CFG_MEMORY_BARRIER() __memory_changed()\r
\r
\r
\r
+\r
/* Clock startup error codes */\r
#define CYCLOCKSTART_NO_ERROR 0u\r
#define CYCLOCKSTART_XTAL_ERROR 1u\r
#define CYCLOCKSTART_32KHZ_ERROR 2u\r
#define CYCLOCKSTART_PLL_ERROR 3u\r
\r
+\r
#ifdef CY_NEED_CYCLOCKSTARTUPERROR\r
/*******************************************************************************\r
* Function Name: CyClockStartupError\r
/* To remove the compiler warning if errorCode not used. */\r
errorCode = errorCode;\r
\r
+ /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */\r
+ /* we will end up here to allow the customer to implement something to */\r
+ /* deal with the clock condition. */\r
+\r
+#ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK\r
+ CY_CFG_Clock_Startup_ErrorCallback();\r
+#else\r
+ /* If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */\r
/* `#START CyClockStartupError` */\r
\r
/* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */\r
/* If nothing else, stop here since the clocks have not started */\r
/* correctly. */\r
while(1) {}\r
+#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ \r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 41u\r
+#define CY_CFG_BASE_ADDR_COUNT 42u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
\r
/* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */\r
static const uint8 CYCODE BS_IOPINS0_8_VAL[] = {\r
- 0x00u, 0x00u, 0x00u, 0x30u, 0x30u, 0x00u, 0x20u, 0x00u, 0xC0u, 0x00u};\r
+ 0x40u, 0x00u, 0x00u, 0x30u, 0x30u, 0x00u, 0x20u, 0x00u, 0xC0u, 0x00u};\r
+\r
+ /* IOPINS0_1 Address: CYREG_PRT1_DM0 Size (bytes): 8 */\r
+ static const uint8 CYCODE BS_IOPINS0_1_VAL[] = {\r
+ 0x00u, 0x0Bu, 0x0Bu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
\r
/* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */\r
static const uint8 CYCODE BS_IOPINS0_2_VAL[] = {\r
0x4000520Eu, /* Base address: 0x40005200 Count: 14 */\r
0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
- 0x40010050u, /* Base address: 0x40010000 Count: 80 */\r
- 0x40010146u, /* Base address: 0x40010100 Count: 70 */\r
- 0x4001025Cu, /* Base address: 0x40010200 Count: 92 */\r
- 0x4001035Du, /* Base address: 0x40010300 Count: 93 */\r
- 0x4001044Eu, /* Base address: 0x40010400 Count: 78 */\r
- 0x40010558u, /* Base address: 0x40010500 Count: 88 */\r
- 0x40010646u, /* Base address: 0x40010600 Count: 70 */\r
- 0x4001074Eu, /* Base address: 0x40010700 Count: 78 */\r
- 0x40010851u, /* Base address: 0x40010800 Count: 81 */\r
- 0x4001095Au, /* Base address: 0x40010900 Count: 90 */\r
- 0x40010A4Au, /* Base address: 0x40010A00 Count: 74 */\r
- 0x40010B57u, /* Base address: 0x40010B00 Count: 87 */\r
- 0x40010C53u, /* Base address: 0x40010C00 Count: 83 */\r
- 0x40010D51u, /* Base address: 0x40010D00 Count: 81 */\r
- 0x40010E4Cu, /* Base address: 0x40010E00 Count: 76 */\r
- 0x40010F3Du, /* Base address: 0x40010F00 Count: 61 */\r
- 0x40011410u, /* Base address: 0x40011400 Count: 16 */\r
- 0x40011548u, /* Base address: 0x40011500 Count: 72 */\r
- 0x40011650u, /* Base address: 0x40011600 Count: 80 */\r
- 0x4001174Eu, /* Base address: 0x40011700 Count: 78 */\r
- 0x40011912u, /* Base address: 0x40011900 Count: 18 */\r
- 0x40011B06u, /* Base address: 0x40011B00 Count: 6 */\r
+ 0x40010046u, /* Base address: 0x40010000 Count: 70 */\r
+ 0x4001013Eu, /* Base address: 0x40010100 Count: 62 */\r
+ 0x40010253u, /* Base address: 0x40010200 Count: 83 */\r
+ 0x40010354u, /* Base address: 0x40010300 Count: 84 */\r
+ 0x4001044Cu, /* Base address: 0x40010400 Count: 76 */\r
+ 0x4001055Du, /* Base address: 0x40010500 Count: 93 */\r
+ 0x40010648u, /* Base address: 0x40010600 Count: 72 */\r
+ 0x4001075Cu, /* Base address: 0x40010700 Count: 92 */\r
+ 0x40010845u, /* Base address: 0x40010800 Count: 69 */\r
+ 0x40010957u, /* Base address: 0x40010900 Count: 87 */\r
+ 0x40010A51u, /* Base address: 0x40010A00 Count: 81 */\r
+ 0x40010B5Eu, /* Base address: 0x40010B00 Count: 94 */\r
+ 0x40010C40u, /* Base address: 0x40010C00 Count: 64 */\r
+ 0x40010D5Du, /* Base address: 0x40010D00 Count: 93 */\r
+ 0x40010E52u, /* Base address: 0x40010E00 Count: 82 */\r
+ 0x40010F3Eu, /* Base address: 0x40010F00 Count: 62 */\r
+ 0x40011460u, /* Base address: 0x40011400 Count: 96 */\r
+ 0x40011543u, /* Base address: 0x40011500 Count: 67 */\r
+ 0x40011651u, /* Base address: 0x40011600 Count: 81 */\r
+ 0x40011752u, /* Base address: 0x40011700 Count: 82 */\r
+ 0x40011804u, /* Base address: 0x40011800 Count: 4 */\r
+ 0x40011911u, /* Base address: 0x40011900 Count: 17 */\r
+ 0x40011B02u, /* Base address: 0x40011B00 Count: 2 */\r
0x4001401Au, /* Base address: 0x40014000 Count: 26 */\r
- 0x4001411Bu, /* Base address: 0x40014100 Count: 27 */\r
- 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */\r
- 0x40014308u, /* Base address: 0x40014300 Count: 8 */\r
- 0x4001440Fu, /* Base address: 0x40014400 Count: 15 */\r
- 0x4001451Fu, /* Base address: 0x40014500 Count: 31 */\r
- 0x40014610u, /* Base address: 0x40014600 Count: 16 */\r
- 0x4001470Eu, /* Base address: 0x40014700 Count: 14 */\r
- 0x40014806u, /* Base address: 0x40014800 Count: 6 */\r
- 0x40014909u, /* Base address: 0x40014900 Count: 9 */\r
- 0x40014C09u, /* Base address: 0x40014C00 Count: 9 */\r
- 0x40014D09u, /* Base address: 0x40014D00 Count: 9 */\r
+ 0x40014116u, /* Base address: 0x40014100 Count: 22 */\r
+ 0x40014211u, /* Base address: 0x40014200 Count: 17 */\r
+ 0x40014309u, /* Base address: 0x40014300 Count: 9 */\r
+ 0x4001440Du, /* Base address: 0x40014400 Count: 13 */\r
+ 0x4001451Cu, /* Base address: 0x40014500 Count: 28 */\r
+ 0x4001460Du, /* Base address: 0x40014600 Count: 13 */\r
+ 0x40014710u, /* Base address: 0x40014700 Count: 16 */\r
+ 0x40014807u, /* Base address: 0x40014800 Count: 7 */\r
+ 0x4001490Cu, /* Base address: 0x40014900 Count: 12 */\r
+ 0x40014C06u, /* Base address: 0x40014C00 Count: 6 */\r
+ 0x40014D0Bu, /* Base address: 0x40014D00 Count: 11 */\r
0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
- {0x0Au, 0x1Bu},\r
- {0x00u, 0x48u},\r
- {0x01u, 0x0Cu},\r
+ {0x0Au, 0x36u},\r
+ {0x00u, 0x41u},\r
+ {0x01u, 0x48u},\r
{0x04u, 0x31u},\r
- {0x10u, 0x4Cu},\r
+ {0x10u, 0xC8u},\r
{0x11u, 0x84u},\r
- {0x18u, 0x08u},\r
+ {0x18u, 0x04u},\r
{0x1Cu, 0x30u},\r
{0x20u, 0x10u},\r
+ {0x21u, 0x10u},\r
{0x24u, 0x44u},\r
{0x29u, 0x01u},\r
- {0x30u, 0x20u},\r
- {0x31u, 0x30u},\r
+ {0x31u, 0x10u},\r
{0x78u, 0x20u},\r
{0x7Cu, 0x40u},\r
{0x20u, 0x01u},\r
- {0x84u, 0x0Fu},\r
- {0x04u, 0x0Fu},\r
- {0x06u, 0xF0u},\r
- {0x09u, 0x03u},\r
- {0x0Bu, 0x04u},\r
- {0x0Du, 0x04u},\r
- {0x0Eu, 0xFFu},\r
- {0x0Fu, 0x03u},\r
- {0x10u, 0x69u},\r
- {0x11u, 0x05u},\r
- {0x12u, 0x96u},\r
- {0x13u, 0x02u},\r
- {0x14u, 0xFFu},\r
- {0x15u, 0x01u},\r
- {0x17u, 0x06u},\r
- {0x1Au, 0xFFu},\r
- {0x1Eu, 0xFFu},\r
- {0x20u, 0xFFu},\r
- {0x24u, 0x33u},\r
- {0x26u, 0xCCu},\r
- {0x28u, 0x55u},\r
- {0x2Au, 0xAAu},\r
- {0x31u, 0x07u},\r
+ {0x86u, 0x0Fu},\r
+ {0x05u, 0x04u},\r
+ {0x06u, 0xFFu},\r
+ {0x07u, 0x08u},\r
+ {0x08u, 0x50u},\r
+ {0x0Au, 0xA0u},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Cu, 0x0Fu},\r
+ {0x0Eu, 0xF0u},\r
+ {0x10u, 0x06u},\r
+ {0x12u, 0x09u},\r
+ {0x14u, 0x05u},\r
+ {0x16u, 0x0Au},\r
+ {0x17u, 0x07u},\r
+ {0x18u, 0x60u},\r
+ {0x1Au, 0x90u},\r
+ {0x1Cu, 0x03u},\r
+ {0x1Eu, 0x0Cu},\r
+ {0x20u, 0x30u},\r
+ {0x22u, 0xC0u},\r
+ {0x26u, 0xFFu},\r
+ {0x29u, 0x09u},\r
+ {0x2Bu, 0x02u},\r
+ {0x2Cu, 0xFFu},\r
+ {0x2Du, 0x0Au},\r
+ {0x2Fu, 0x05u},\r
{0x32u, 0xFFu},\r
- {0x3Au, 0x08u},\r
- {0x3Bu, 0x02u},\r
- {0x40u, 0x26u},\r
- {0x41u, 0x03u},\r
- {0x42u, 0x50u},\r
- {0x45u, 0xECu},\r
- {0x46u, 0xD2u},\r
- {0x47u, 0x0Fu},\r
+ {0x33u, 0x0Fu},\r
+ {0x3Eu, 0x04u},\r
+ {0x40u, 0x35u},\r
+ {0x41u, 0x06u},\r
+ {0x42u, 0x20u},\r
+ {0x45u, 0xF2u},\r
+ {0x46u, 0xDCu},\r
+ {0x47u, 0x0Eu},\r
{0x48u, 0x1Fu},\r
{0x49u, 0xFFu},\r
{0x4Au, 0xFFu},\r
{0x59u, 0x04u},\r
{0x5Au, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x01u},\r
+ {0x5Cu, 0x10u},\r
{0x5Du, 0x01u},\r
{0x5Fu, 0x01u},\r
{0x60u, 0x08u},\r
{0x68u, 0x40u},\r
{0x69u, 0x40u},\r
{0x6Eu, 0x08u},\r
- {0x84u, 0x03u},\r
- {0x85u, 0x03u},\r
- {0x86u, 0x14u},\r
- {0x87u, 0x1Cu},\r
- {0x89u, 0x09u},\r
- {0x8Bu, 0x12u},\r
- {0x8Cu, 0x04u},\r
- {0x91u, 0x04u},\r
- {0x94u, 0x18u},\r
- {0x96u, 0x03u},\r
- {0x99u, 0x08u},\r
- {0x9Au, 0x01u},\r
- {0x9Bu, 0x17u},\r
- {0x9Eu, 0x1Fu},\r
- {0x9Fu, 0x07u},\r
- {0xA2u, 0x08u},\r
- {0xA3u, 0x01u},\r
- {0xA4u, 0x01u},\r
- {0xA5u, 0x02u},\r
- {0xA6u, 0x0Eu},\r
- {0xA8u, 0x02u},\r
- {0xADu, 0x0Bu},\r
- {0xAFu, 0x14u},\r
- {0xB3u, 0x1Fu},\r
- {0xB4u, 0x1Fu},\r
+ {0x85u, 0x04u},\r
+ {0x87u, 0x03u},\r
+ {0x89u, 0x0Bu},\r
+ {0x8Bu, 0x04u},\r
+ {0x95u, 0x09u},\r
+ {0x97u, 0x06u},\r
+ {0x99u, 0x0Du},\r
+ {0x9Bu, 0x02u},\r
+ {0xB1u, 0x08u},\r
+ {0xB3u, 0x07u},\r
{0xBBu, 0x08u},\r
- {0xD8u, 0x04u},\r
+ {0xBFu, 0x01u},\r
+ {0xD6u, 0x08u},\r
{0xD9u, 0x04u},\r
- {0xDCu, 0x11u},\r
+ {0xDBu, 0x04u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x08u},\r
- {0x03u, 0x02u},\r
- {0x04u, 0x04u},\r
- {0x07u, 0x02u},\r
- {0x08u, 0xA1u},\r
- {0x0Bu, 0x11u},\r
- {0x0Eu, 0x08u},\r
- {0x0Fu, 0x11u},\r
- {0x10u, 0x14u},\r
- {0x13u, 0x02u},\r
- {0x15u, 0x28u},\r
- {0x16u, 0x40u},\r
- {0x19u, 0x08u},\r
- {0x1Au, 0x10u},\r
- {0x1Cu, 0x04u},\r
- {0x23u, 0x40u},\r
+ {0x00u, 0x08u},\r
+ {0x01u, 0x40u},\r
+ {0x03u, 0x04u},\r
+ {0x08u, 0x80u},\r
+ {0x09u, 0x0Au},\r
+ {0x0Bu, 0x04u},\r
+ {0x10u, 0x80u},\r
+ {0x11u, 0x84u},\r
+ {0x13u, 0x30u},\r
+ {0x1Bu, 0x04u},\r
+ {0x21u, 0x08u},\r
+ {0x24u, 0x80u},\r
{0x25u, 0x04u},\r
- {0x29u, 0x20u},\r
- {0x2Bu, 0x08u},\r
- {0x2Cu, 0xA0u},\r
- {0x2Fu, 0x02u},\r
- {0x32u, 0x0Au},\r
- {0x34u, 0xA0u},\r
- {0x37u, 0x02u},\r
- {0x3Au, 0x20u},\r
- {0x3Bu, 0x40u},\r
+ {0x27u, 0x20u},\r
+ {0x29u, 0xA0u},\r
+ {0x31u, 0x08u},\r
+ {0x33u, 0x08u},\r
+ {0x35u, 0x04u},\r
+ {0x36u, 0x20u},\r
+ {0x39u, 0x18u},\r
+ {0x3Cu, 0x10u},\r
{0x3Du, 0x08u},\r
- {0x3Fu, 0x10u},\r
- {0x40u, 0x24u},\r
+ {0x40u, 0x04u},\r
{0x41u, 0x04u},\r
- {0x48u, 0x05u},\r
- {0x4Au, 0x90u},\r
- {0x4Bu, 0x10u},\r
- {0x50u, 0xA0u},\r
- {0x51u, 0x10u},\r
- {0x52u, 0x40u},\r
- {0x53u, 0x08u},\r
- {0x58u, 0x08u},\r
- {0x59u, 0x50u},\r
- {0x5Au, 0x01u},\r
+ {0x49u, 0xAAu},\r
+ {0x4Au, 0x04u},\r
+ {0x52u, 0x44u},\r
+ {0x53u, 0x20u},\r
+ {0x5Au, 0x58u},\r
+ {0x5Bu, 0x02u},\r
+ {0x5Cu, 0x40u},\r
{0x60u, 0x02u},\r
- {0x61u, 0x24u},\r
- {0x62u, 0x01u},\r
- {0x68u, 0x10u},\r
- {0x69u, 0x80u},\r
- {0x6Au, 0x20u},\r
- {0x6Bu, 0x40u},\r
- {0x70u, 0x58u},\r
- {0x72u, 0x80u},\r
- {0x81u, 0x40u},\r
- {0x83u, 0x40u},\r
- {0x84u, 0x14u},\r
- {0x8Au, 0x80u},\r
- {0x8Cu, 0x40u},\r
- {0x8Du, 0x04u},\r
- {0x8Eu, 0x10u},\r
- {0xC0u, 0xA5u},\r
- {0xC2u, 0xEFu},\r
- {0xC4u, 0x7Eu},\r
- {0xCAu, 0xD0u},\r
- {0xCCu, 0xB3u},\r
- {0xCEu, 0x6Cu},\r
+ {0x62u, 0x1Au},\r
+ {0x64u, 0x01u},\r
+ {0x68u, 0x60u},\r
+ {0x69u, 0x10u},\r
+ {0x6Au, 0x80u},\r
+ {0x70u, 0x08u},\r
+ {0x72u, 0x0Au},\r
+ {0x73u, 0x40u},\r
+ {0x80u, 0x02u},\r
+ {0x81u, 0x02u},\r
+ {0x83u, 0x04u},\r
+ {0x85u, 0x43u},\r
+ {0x88u, 0x40u},\r
+ {0x89u, 0x08u},\r
+ {0x8Au, 0x04u},\r
+ {0x8Bu, 0x02u},\r
+ {0x8Eu, 0x05u},\r
+ {0xC0u, 0x07u},\r
+ {0xC2u, 0x0Fu},\r
+ {0xC4u, 0x0Du},\r
+ {0xCAu, 0x0Cu},\r
+ {0xCCu, 0x62u},\r
+ {0xCEu, 0x66u},\r
{0xD0u, 0x06u},\r
{0xD2u, 0x0Cu},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x0Fu},\r
- {0xE0u, 0x01u},\r
- {0xE2u, 0x0Au},\r
- {0xE4u, 0x09u},\r
- {0xE6u, 0x42u},\r
- {0x00u, 0x0Fu},\r
- {0x02u, 0xF0u},\r
- {0x05u, 0x20u},\r
- {0x06u, 0xFFu},\r
- {0x07u, 0x4Fu},\r
- {0x09u, 0x05u},\r
- {0x0Bu, 0x0Au},\r
- {0x0Du, 0x06u},\r
- {0x0Fu, 0x09u},\r
- {0x13u, 0x70u},\r
- {0x15u, 0x0Fu},\r
- {0x16u, 0xFFu},\r
- {0x18u, 0x55u},\r
- {0x19u, 0x10u},\r
- {0x1Au, 0xAAu},\r
- {0x1Bu, 0x2Fu},\r
- {0x1Du, 0x03u},\r
- {0x1Eu, 0xFFu},\r
- {0x1Fu, 0x0Cu},\r
- {0x20u, 0xFFu},\r
- {0x24u, 0xFFu},\r
- {0x28u, 0x69u},\r
- {0x2Au, 0x96u},\r
- {0x2Cu, 0x33u},\r
- {0x2Du, 0x40u},\r
- {0x2Eu, 0xCCu},\r
- {0x2Fu, 0x1Fu},\r
- {0x30u, 0xFFu},\r
- {0x31u, 0x7Fu},\r
+ {0xD6u, 0x1Fu},\r
+ {0xD8u, 0x1Fu},\r
+ {0xE2u, 0x4Bu},\r
+ {0xE4u, 0x08u},\r
+ {0xE6u, 0x51u},\r
+ {0x03u, 0x80u},\r
+ {0x05u, 0x04u},\r
+ {0x07u, 0x08u},\r
+ {0x08u, 0x04u},\r
+ {0x0Au, 0x02u},\r
+ {0x0Bu, 0x02u},\r
+ {0x0Fu, 0x70u},\r
+ {0x10u, 0x02u},\r
+ {0x11u, 0x08u},\r
+ {0x12u, 0x04u},\r
+ {0x13u, 0x05u},\r
+ {0x14u, 0x04u},\r
+ {0x15u, 0x90u},\r
+ {0x16u, 0x02u},\r
+ {0x17u, 0x20u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x08u},\r
+ {0x1Au, 0x0Au},\r
+ {0x1Bu, 0x04u},\r
+ {0x1Du, 0xA0u},\r
+ {0x1Fu, 0x50u},\r
+ {0x20u, 0x04u},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0x03u},\r
+ {0x23u, 0x04u},\r
+ {0x29u, 0x40u},\r
+ {0x2Bu, 0x80u},\r
+ {0x2Du, 0x08u},\r
+ {0x2Fu, 0x04u},\r
+ {0x30u, 0x06u},\r
+ {0x31u, 0x01u},\r
+ {0x32u, 0x08u},\r
+ {0x33u, 0x0Cu},\r
+ {0x34u, 0x01u},\r
+ {0x35u, 0x02u},\r
+ {0x37u, 0xF0u},\r
{0x3Au, 0x02u},\r
+ {0x3Bu, 0x08u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x20u},\r
- {0x81u, 0x40u},\r
- {0x82u, 0x40u},\r
- {0x83u, 0x80u},\r
- {0x84u, 0x01u},\r
- {0x85u, 0x10u},\r
+ {0x82u, 0x17u},\r
+ {0x84u, 0x49u},\r
{0x86u, 0x02u},\r
- {0x87u, 0x20u},\r
- {0x88u, 0x08u},\r
- {0x8Au, 0x10u},\r
- {0x8Cu, 0x44u},\r
- {0x8Du, 0x02u},\r
- {0x8Eu, 0x3Bu},\r
- {0x8Fu, 0xF0u},\r
+ {0x8Cu, 0x4Au},\r
+ {0x8Du, 0x0Du},\r
+ {0x8Eu, 0x05u},\r
+ {0x8Fu, 0x32u},\r
{0x90u, 0x44u},\r
- {0x92u, 0x3Bu},\r
- {0x94u, 0x1Fu},\r
- {0x95u, 0x05u},\r
- {0x96u, 0x20u},\r
- {0x97u, 0xF8u},\r
- {0x98u, 0x01u},\r
- {0x9Au, 0x02u},\r
- {0x9Bu, 0x01u},\r
- {0x9Du, 0xF0u},\r
- {0x9Eu, 0x3Bu},\r
- {0x9Fu, 0x08u},\r
- {0xA0u, 0x1Bu},\r
- {0xA1u, 0x40u},\r
+ {0x91u, 0x20u},\r
+ {0x92u, 0x08u},\r
+ {0x93u, 0x10u},\r
+ {0x96u, 0x80u},\r
+ {0x9Au, 0x08u},\r
+ {0x9Du, 0x04u},\r
+ {0x9Eu, 0x20u},\r
+ {0x9Fu, 0x09u},\r
+ {0xA0u, 0x10u},\r
+ {0xA1u, 0x08u},\r
{0xA2u, 0x20u},\r
- {0xA3u, 0x80u},\r
- {0xA4u, 0x08u},\r
- {0xA5u, 0xF4u},\r
- {0xA6u, 0x10u},\r
- {0xA7u, 0x08u},\r
- {0xA9u, 0x01u},\r
- {0xAAu, 0x04u},\r
- {0xABu, 0xF8u},\r
+ {0xA3u, 0x04u},\r
+ {0xAAu, 0x40u},\r
{0xADu, 0x10u},\r
- {0xAFu, 0x20u},\r
- {0xB0u, 0x60u},\r
- {0xB2u, 0x18u},\r
- {0xB3u, 0x0Fu},\r
- {0xB4u, 0x03u},\r
- {0xB5u, 0x30u},\r
- {0xB6u, 0x04u},\r
- {0xB7u, 0xC0u},\r
- {0xB9u, 0x08u},\r
- {0xBAu, 0x2Au},\r
- {0xBBu, 0xA0u},\r
- {0xBEu, 0x40u},\r
+ {0xAFu, 0x22u},\r
+ {0xB0u, 0x0Fu},\r
+ {0xB1u, 0x03u},\r
+ {0xB2u, 0x30u},\r
+ {0xB4u, 0x80u},\r
+ {0xB5u, 0x3Cu},\r
+ {0xB6u, 0x40u},\r
+ {0xBEu, 0x44u},\r
+ {0xBFu, 0x11u},\r
+ {0xD4u, 0x01u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
+ {0xDCu, 0x01u},\r
+ {0xDDu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x02u},\r
- {0x02u, 0x20u},\r
- {0x03u, 0x0Au},\r
- {0x04u, 0x04u},\r
- {0x05u, 0x01u},\r
+ {0x01u, 0x8Au},\r
+ {0x07u, 0x04u},\r
+ {0x08u, 0x08u},\r
+ {0x0Au, 0x06u},\r
+ {0x0Bu, 0x80u},\r
+ {0x0Du, 0x22u},\r
+ {0x0Eu, 0x20u},\r
+ {0x10u, 0x04u},\r
+ {0x13u, 0x02u},\r
+ {0x16u, 0x80u},\r
+ {0x19u, 0x22u},\r
+ {0x1Au, 0x20u},\r
+ {0x1Bu, 0x80u},\r
+ {0x1Cu, 0x20u},\r
+ {0x1Du, 0x22u},\r
+ {0x1Eu, 0x20u},\r
+ {0x20u, 0x08u},\r
+ {0x21u, 0x01u},\r
+ {0x23u, 0x08u},\r
+ {0x25u, 0x44u},\r
+ {0x26u, 0x81u},\r
+ {0x27u, 0x24u},\r
+ {0x29u, 0x02u},\r
+ {0x2Bu, 0x02u},\r
+ {0x2Eu, 0x01u},\r
+ {0x2Fu, 0x05u},\r
+ {0x32u, 0x83u},\r
+ {0x34u, 0x11u},\r
+ {0x35u, 0x88u},\r
+ {0x36u, 0x04u},\r
+ {0x39u, 0x48u},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Cu, 0x20u},\r
+ {0x3Du, 0x88u},\r
+ {0x3Eu, 0x02u},\r
+ {0x59u, 0x40u},\r
+ {0x5Cu, 0x80u},\r
+ {0x5Eu, 0x03u},\r
+ {0x66u, 0x80u},\r
+ {0x69u, 0x40u},\r
+ {0x6Bu, 0x02u},\r
+ {0x6Du, 0x14u},\r
+ {0x6Fu, 0x01u},\r
+ {0x80u, 0x80u},\r
+ {0x85u, 0x01u},\r
+ {0x88u, 0x04u},\r
+ {0x8Au, 0x40u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Eu, 0x04u},\r
+ {0x8Fu, 0x02u},\r
+ {0x90u, 0x80u},\r
+ {0x91u, 0x01u},\r
+ {0x92u, 0x84u},\r
+ {0x93u, 0x50u},\r
+ {0x94u, 0x14u},\r
+ {0x95u, 0x4Cu},\r
+ {0x96u, 0x78u},\r
+ {0x98u, 0x01u},\r
+ {0x9Au, 0x4Eu},\r
+ {0x9Du, 0x84u},\r
+ {0x9Eu, 0x11u},\r
+ {0xA0u, 0x28u},\r
+ {0xA3u, 0x2Cu},\r
+ {0xA4u, 0x84u},\r
+ {0xA6u, 0x2Cu},\r
+ {0xA8u, 0x80u},\r
+ {0xAAu, 0x10u},\r
+ {0xADu, 0x82u},\r
+ {0xB3u, 0x24u},\r
+ {0xB4u, 0x40u},\r
+ {0xB6u, 0x02u},\r
+ {0xC0u, 0x4Du},\r
+ {0xC2u, 0x7Fu},\r
+ {0xC4u, 0x1Au},\r
+ {0xCAu, 0xB9u},\r
+ {0xCCu, 0xF9u},\r
+ {0xCEu, 0xF8u},\r
+ {0xD6u, 0x18u},\r
+ {0xD8u, 0x10u},\r
+ {0xE4u, 0x02u},\r
+ {0xE8u, 0x08u},\r
+ {0xEAu, 0x02u},\r
+ {0xECu, 0x04u},\r
+ {0xEEu, 0x01u},\r
+ {0x00u, 0xE0u},\r
+ {0x01u, 0x01u},\r
{0x06u, 0x10u},\r
- {0x07u, 0x40u},\r
- {0x08u, 0x80u},\r
- {0x09u, 0x04u},\r
- {0x0Au, 0x04u},\r
- {0x0Bu, 0x81u},\r
+ {0x0Cu, 0xCAu},\r
{0x0Du, 0x04u},\r
- {0x0Fu, 0x09u},\r
- {0x10u, 0x04u},\r
- {0x13u, 0x1Au},\r
- {0x14u, 0x12u},\r
- {0x15u, 0x04u},\r
- {0x16u, 0x08u},\r
- {0x17u, 0x02u},\r
- {0x18u, 0x01u},\r
- {0x19u, 0x14u},\r
- {0x1Au, 0x04u},\r
- {0x1Bu, 0x09u},\r
- {0x1Du, 0x01u},\r
- {0x21u, 0xA4u},\r
- {0x22u, 0x04u},\r
- {0x23u, 0x24u},\r
- {0x26u, 0x01u},\r
+ {0x0Eu, 0x15u},\r
+ {0x10u, 0x40u},\r
+ {0x11u, 0x02u},\r
+ {0x12u, 0x80u},\r
+ {0x14u, 0x40u},\r
+ {0x15u, 0x01u},\r
+ {0x16u, 0x80u},\r
+ {0x18u, 0x0Bu},\r
+ {0x1Au, 0xF4u},\r
+ {0x1Eu, 0xFFu},\r
+ {0x20u, 0x06u},\r
+ {0x21u, 0x01u},\r
+ {0x24u, 0x01u},\r
{0x28u, 0x11u},\r
- {0x2Au, 0x12u},\r
- {0x2Fu, 0x02u},\r
- {0x30u, 0x20u},\r
- {0x32u, 0x44u},\r
- {0x36u, 0x05u},\r
- {0x37u, 0x60u},\r
- {0x3Au, 0x41u},\r
- {0x3Bu, 0x04u},\r
- {0x3Cu, 0x0Au},\r
- {0x3Du, 0x0Cu},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x82u},\r
- {0x44u, 0x80u},\r
- {0x45u, 0x80u},\r
- {0x46u, 0x41u},\r
- {0x58u, 0x44u},\r
- {0x59u, 0x20u},\r
- {0x5Bu, 0x01u},\r
- {0x5Eu, 0x60u},\r
- {0x5Fu, 0x10u},\r
- {0x60u, 0x01u},\r
- {0x64u, 0x01u},\r
- {0x82u, 0x0Au},\r
- {0x87u, 0x08u},\r
- {0x89u, 0x08u},\r
- {0x8Au, 0x01u},\r
- {0x8Eu, 0x40u},\r
- {0x90u, 0x24u},\r
- {0x91u, 0x20u},\r
- {0x92u, 0x10u},\r
- {0x93u, 0x40u},\r
- {0x95u, 0x08u},\r
- {0x98u, 0x40u},\r
- {0x99u, 0x20u},\r
- {0x9Cu, 0x89u},\r
- {0x9Du, 0x54u},\r
- {0x9Eu, 0x21u},\r
- {0x9Fu, 0x02u},\r
- {0xA0u, 0x18u},\r
- {0xA2u, 0x10u},\r
- {0xA3u, 0x40u},\r
- {0xA4u, 0x05u},\r
- {0xA5u, 0x20u},\r
- {0xA6u, 0x0Eu},\r
- {0xA7u, 0x02u},\r
- {0xABu, 0x40u},\r
- {0xACu, 0x04u},\r
- {0xAEu, 0x01u},\r
- {0xB0u, 0x42u},\r
- {0xB2u, 0x80u},\r
- {0xB7u, 0x08u},\r
- {0xC0u, 0x3Fu},\r
- {0xC2u, 0xEFu},\r
- {0xC4u, 0xFEu},\r
- {0xCAu, 0x1Fu},\r
- {0xCCu, 0xFEu},\r
- {0xCEu, 0x7Bu},\r
- {0xD6u, 0x1Fu},\r
- {0xD8u, 0x18u},\r
- {0xE2u, 0x08u},\r
- {0xE6u, 0x2Fu},\r
- {0xEAu, 0x9Cu},\r
- {0xECu, 0x02u},\r
- {0xEEu, 0x80u},\r
- {0x00u, 0x10u},\r
- {0x02u, 0x20u},\r
- {0x04u, 0x08u},\r
- {0x05u, 0x09u},\r
- {0x06u, 0x04u},\r
- {0x07u, 0x02u},\r
- {0x08u, 0x04u},\r
- {0x0Au, 0x08u},\r
- {0x0Bu, 0x08u},\r
- {0x0Cu, 0x08u},\r
- {0x0Eu, 0x04u},\r
- {0x10u, 0x08u},\r
- {0x11u, 0x10u},\r
- {0x12u, 0x06u},\r
- {0x13u, 0x20u},\r
- {0x16u, 0x10u},\r
- {0x1Bu, 0x07u},\r
- {0x1Du, 0x04u},\r
- {0x1Fu, 0x08u},\r
- {0x20u, 0x08u},\r
- {0x22u, 0x05u},\r
- {0x27u, 0x10u},\r
- {0x29u, 0x0Au},\r
- {0x2Au, 0x20u},\r
- {0x2Bu, 0x05u},\r
- {0x2Fu, 0x20u},\r
- {0x30u, 0x01u},\r
- {0x32u, 0x0Cu},\r
- {0x34u, 0x02u},\r
- {0x35u, 0x0Fu},\r
- {0x36u, 0x30u},\r
- {0x37u, 0x30u},\r
+ {0x29u, 0x01u},\r
+ {0x2Au, 0xECu},\r
+ {0x31u, 0x02u},\r
+ {0x32u, 0xC0u},\r
+ {0x33u, 0x04u},\r
+ {0x35u, 0x01u},\r
+ {0x36u, 0x3Fu},\r
+ {0x39u, 0x20u},\r
{0x3Au, 0x08u},\r
- {0x3Eu, 0x40u},\r
- {0x3Fu, 0x40u},\r
- {0x56u, 0x08u},\r
+ {0x3Fu, 0x10u},\r
+ {0x54u, 0x40u},\r
+ {0x56u, 0x04u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
- {0x5Du, 0x90u},\r
+ {0x5Cu, 0x91u},\r
{0x5Fu, 0x01u},\r
- {0x85u, 0x02u},\r
- {0x86u, 0x82u},\r
- {0x87u, 0x05u},\r
- {0x88u, 0x11u},\r
- {0x89u, 0x02u},\r
- {0x8Au, 0x02u},\r
- {0x8Bu, 0x09u},\r
- {0x8Du, 0x02u},\r
- {0x8Fu, 0x01u},\r
- {0x90u, 0x48u},\r
+ {0x81u, 0x01u},\r
+ {0x85u, 0x01u},\r
+ {0x88u, 0x08u},\r
+ {0x89u, 0x08u},\r
+ {0x8Au, 0x06u},\r
+ {0x8Bu, 0x21u},\r
+ {0x8Du, 0x01u},\r
{0x91u, 0x01u},\r
- {0x92u, 0x03u},\r
- {0x93u, 0x02u},\r
- {0x96u, 0x7Cu},\r
- {0x9Au, 0x01u},\r
- {0xA4u, 0x04u},\r
- {0xA6u, 0x23u},\r
- {0xA8u, 0x70u},\r
- {0xADu, 0x02u},\r
- {0xAFu, 0x11u},\r
- {0xB1u, 0x04u},\r
- {0xB2u, 0x0Fu},\r
- {0xB3u, 0x08u},\r
- {0xB4u, 0x80u},\r
- {0xB5u, 0x10u},\r
- {0xB6u, 0x70u},\r
- {0xB7u, 0x03u},\r
- {0xBBu, 0x80u},\r
- {0xBEu, 0x40u},\r
+ {0x94u, 0x08u},\r
+ {0x95u, 0x07u},\r
+ {0x96u, 0x04u},\r
+ {0x97u, 0x18u},\r
+ {0x99u, 0x22u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Du, 0x04u},\r
+ {0x9Eu, 0x04u},\r
+ {0xA0u, 0x08u},\r
+ {0xA1u, 0x40u},\r
+ {0xA2u, 0x05u},\r
+ {0xA5u, 0x01u},\r
+ {0xA9u, 0x10u},\r
+ {0xACu, 0x04u},\r
+ {0xADu, 0x40u},\r
+ {0xAEu, 0x08u},\r
+ {0xB1u, 0x3Fu},\r
+ {0xB2u, 0x02u},\r
+ {0xB4u, 0x01u},\r
+ {0xB6u, 0x0Cu},\r
+ {0xB7u, 0x40u},\r
+ {0xB9u, 0x82u},\r
+ {0xBAu, 0x80u},\r
+ {0xBFu, 0x01u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x10u},\r
+ {0xDCu, 0x01u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x04u},\r
- {0x02u, 0x40u},\r
- {0x03u, 0x0Eu},\r
- {0x06u, 0x10u},\r
- {0x07u, 0x08u},\r
- {0x0Au, 0x60u},\r
- {0x0Du, 0x02u},\r
- {0x0Eu, 0x14u},\r
- {0x12u, 0x84u},\r
- {0x16u, 0x20u},\r
- {0x17u, 0x10u},\r
- {0x18u, 0x04u},\r
- {0x19u, 0x04u},\r
- {0x1Au, 0x48u},\r
- {0x1Bu, 0x48u},\r
- {0x1Cu, 0x02u},\r
- {0x1Eu, 0x14u},\r
- {0x20u, 0x01u},\r
- {0x22u, 0x50u},\r
- {0x23u, 0x02u},\r
- {0x24u, 0x42u},\r
- {0x25u, 0x14u},\r
- {0x27u, 0x01u},\r
- {0x29u, 0x14u},\r
- {0x2Bu, 0x01u},\r
- {0x2Fu, 0x01u},\r
- {0x30u, 0x82u},\r
- {0x32u, 0x10u},\r
- {0x36u, 0x08u},\r
- {0x37u, 0x09u},\r
- {0x38u, 0x20u},\r
- {0x39u, 0x08u},\r
- {0x3Cu, 0x40u},\r
- {0x3Du, 0x28u},\r
- {0x44u, 0x80u},\r
- {0x47u, 0x01u},\r
- {0x49u, 0x80u},\r
- {0x4Au, 0x01u},\r
- {0x58u, 0x10u},\r
- {0x5Bu, 0x40u},\r
- {0x5Du, 0x40u},\r
- {0x62u, 0xA0u},\r
- {0x63u, 0x0Au},\r
- {0x67u, 0x02u},\r
- {0x68u, 0x02u},\r
- {0x6Cu, 0x24u},\r
- {0x6Du, 0x80u},\r
- {0x6Eu, 0x08u},\r
- {0x83u, 0x44u},\r
- {0x84u, 0x08u},\r
- {0x85u, 0x40u},\r
- {0x88u, 0x10u},\r
- {0x8Bu, 0x01u},\r
- {0x8Cu, 0x41u},\r
- {0x8Du, 0x01u},\r
- {0x8Fu, 0x40u},\r
- {0x90u, 0x20u},\r
- {0x91u, 0x28u},\r
- {0x93u, 0xC0u},\r
- {0x96u, 0x82u},\r
- {0x9Cu, 0x8Au},\r
- {0x9Du, 0x40u},\r
- {0x9Eu, 0x20u},\r
- {0x9Fu, 0x02u},\r
- {0xA0u, 0x98u},\r
- {0xA2u, 0x11u},\r
- {0xA4u, 0x24u},\r
- {0xA5u, 0x08u},\r
- {0xA6u, 0x2Eu},\r
- {0xA7u, 0x04u},\r
- {0xA8u, 0x84u},\r
- {0xAAu, 0x04u},\r
- {0xABu, 0x02u},\r
- {0xB1u, 0x14u},\r
- {0xB3u, 0x41u},\r
- {0xC0u, 0x6Fu},\r
- {0xC2u, 0x7Cu},\r
- {0xC4u, 0x6Au},\r
- {0xCAu, 0x1Eu},\r
- {0xCCu, 0x8Du},\r
- {0xCEu, 0x76u},\r
- {0xD6u, 0x1Cu},\r
- {0xD8u, 0x1Cu},\r
- {0xE0u, 0x01u},\r
- {0xE2u, 0x04u},\r
- {0xE6u, 0x09u},\r
- {0xE8u, 0x04u},\r
- {0xECu, 0x04u},\r
- {0x00u, 0xE0u},\r
- {0x08u, 0xCAu},\r
- {0x0Au, 0x15u},\r
- {0x0Cu, 0x40u},\r
- {0x0Eu, 0x80u},\r
- {0x11u, 0x01u},\r
- {0x14u, 0x06u},\r
- {0x18u, 0x01u},\r
- {0x1Cu, 0x11u},\r
- {0x1Eu, 0xECu},\r
- {0x22u, 0xFFu},\r
- {0x24u, 0x0Bu},\r
- {0x26u, 0xF4u},\r
- {0x2Au, 0x10u},\r
- {0x2Cu, 0x40u},\r
- {0x2Eu, 0x80u},\r
- {0x33u, 0x01u},\r
- {0x34u, 0x3Fu},\r
- {0x36u, 0xC0u},\r
- {0x38u, 0x08u},\r
- {0x3Au, 0x80u},\r
+ {0x00u, 0x02u},\r
+ {0x01u, 0x80u},\r
+ {0x03u, 0x20u},\r
+ {0x05u, 0x10u},\r
+ {0x08u, 0x42u},\r
+ {0x0Au, 0x10u},\r
+ {0x0Bu, 0x04u},\r
+ {0x0Eu, 0x21u},\r
+ {0x11u, 0x14u},\r
+ {0x12u, 0x40u},\r
+ {0x15u, 0x80u},\r
+ {0x16u, 0x82u},\r
+ {0x19u, 0x80u},\r
+ {0x1Au, 0x10u},\r
+ {0x1Du, 0x10u},\r
+ {0x1Eu, 0x20u},\r
+ {0x1Fu, 0x40u},\r
+ {0x20u, 0x20u},\r
+ {0x21u, 0x11u},\r
+ {0x26u, 0x40u},\r
+ {0x27u, 0x40u},\r
+ {0x2Bu, 0x44u},\r
+ {0x2Eu, 0x40u},\r
+ {0x2Fu, 0x98u},\r
+ {0x31u, 0x0Au},\r
+ {0x33u, 0xC0u},\r
+ {0x35u, 0x04u},\r
+ {0x36u, 0x60u},\r
+ {0x37u, 0x01u},\r
+ {0x39u, 0x81u},\r
+ {0x3Bu, 0x80u},\r
+ {0x3Cu, 0x90u},\r
+ {0x3Du, 0x02u},\r
{0x3Eu, 0x04u},\r
- {0x56u, 0x08u},\r
+ {0x44u, 0x40u},\r
+ {0x45u, 0x02u},\r
+ {0x5Au, 0x02u},\r
+ {0x5Bu, 0x02u},\r
+ {0x5Du, 0x40u},\r
+ {0x5Eu, 0x08u},\r
+ {0x5Fu, 0x04u},\r
+ {0x61u, 0x20u},\r
+ {0x62u, 0x89u},\r
+ {0x66u, 0x80u},\r
+ {0x7Du, 0x10u},\r
+ {0x7Fu, 0x04u},\r
+ {0x80u, 0x80u},\r
+ {0x81u, 0x0Au},\r
+ {0x84u, 0x01u},\r
+ {0x88u, 0x90u},\r
+ {0x89u, 0x02u},\r
+ {0x8Du, 0x80u},\r
+ {0x8Eu, 0x06u},\r
+ {0x90u, 0x80u},\r
+ {0x91u, 0x05u},\r
+ {0x92u, 0x80u},\r
+ {0x93u, 0x58u},\r
+ {0x94u, 0x14u},\r
+ {0x96u, 0x18u},\r
+ {0x97u, 0x02u},\r
+ {0x9Au, 0x4Cu},\r
+ {0x9Bu, 0x2Au},\r
+ {0x9Cu, 0x10u},\r
+ {0x9Du, 0xC4u},\r
+ {0x9Eu, 0x11u},\r
+ {0xA0u, 0x28u},\r
+ {0xA1u, 0x02u},\r
+ {0xA2u, 0x01u},\r
+ {0xA3u, 0x24u},\r
+ {0xA4u, 0x80u},\r
+ {0xA6u, 0x24u},\r
+ {0xA8u, 0x08u},\r
+ {0xAAu, 0x42u},\r
+ {0xADu, 0x14u},\r
+ {0xAEu, 0x08u},\r
+ {0xB1u, 0x04u},\r
+ {0xB3u, 0x41u},\r
+ {0xB5u, 0x20u},\r
+ {0xB7u, 0x80u},\r
+ {0xC0u, 0x4Du},\r
+ {0xC2u, 0xAFu},\r
+ {0xC4u, 0x9Eu},\r
+ {0xCAu, 0xF5u},\r
+ {0xCCu, 0xF3u},\r
+ {0xCEu, 0xF9u},\r
+ {0xD6u, 0x10u},\r
+ {0xD8u, 0x1Fu},\r
+ {0xE2u, 0x17u},\r
+ {0xE4u, 0x04u},\r
+ {0xE6u, 0x88u},\r
+ {0xEAu, 0x0Du},\r
+ {0xECu, 0x02u},\r
+ {0xEEu, 0x24u},\r
+ {0x00u, 0x07u},\r
+ {0x03u, 0x18u},\r
+ {0x04u, 0x01u},\r
+ {0x07u, 0x01u},\r
+ {0x09u, 0x10u},\r
+ {0x0Au, 0x02u},\r
+ {0x0Bu, 0x20u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Fu, 0x10u},\r
+ {0x13u, 0x40u},\r
+ {0x16u, 0x10u},\r
+ {0x19u, 0x25u},\r
+ {0x1Bu, 0x18u},\r
+ {0x1Eu, 0x08u},\r
+ {0x24u, 0x04u},\r
+ {0x29u, 0x21u},\r
+ {0x2Au, 0x07u},\r
+ {0x2Bu, 0x18u},\r
+ {0x2Du, 0x04u},\r
+ {0x2Fu, 0x18u},\r
+ {0x30u, 0x08u},\r
+ {0x33u, 0x0Fu},\r
+ {0x34u, 0x07u},\r
+ {0x35u, 0x30u},\r
+ {0x36u, 0x10u},\r
+ {0x37u, 0x40u},\r
+ {0x39u, 0x08u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Eu, 0x10u},\r
+ {0x54u, 0x09u},\r
+ {0x56u, 0x04u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x91u},\r
- {0x5Du, 0x90u},\r
+ {0x5Cu, 0x11u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x05u},\r
- {0x82u, 0x0Au},\r
- {0x85u, 0x50u},\r
- {0x87u, 0xA0u},\r
- {0x88u, 0x06u},\r
- {0x8Au, 0x09u},\r
- {0x8Cu, 0x30u},\r
- {0x8Du, 0x30u},\r
- {0x8Eu, 0xC0u},\r
- {0x8Fu, 0xC0u},\r
- {0x90u, 0x03u},\r
- {0x92u, 0x0Cu},\r
- {0x94u, 0x50u},\r
- {0x96u, 0xA0u},\r
- {0x99u, 0x06u},\r
- {0x9Au, 0xFFu},\r
- {0x9Bu, 0x09u},\r
- {0x9Du, 0x03u},\r
- {0x9Eu, 0xFFu},\r
- {0x9Fu, 0x0Cu},\r
- {0xA0u, 0x0Fu},\r
- {0xA2u, 0xF0u},\r
- {0xA5u, 0x60u},\r
- {0xA7u, 0x90u},\r
- {0xA8u, 0xFFu},\r
- {0xA9u, 0x05u},\r
- {0xABu, 0x0Au},\r
- {0xACu, 0x60u},\r
- {0xADu, 0x0Fu},\r
- {0xAEu, 0x90u},\r
- {0xAFu, 0xF0u},\r
- {0xB0u, 0xFFu},\r
- {0xB5u, 0xFFu},\r
- {0xBEu, 0x01u},\r
- {0xBFu, 0x10u},\r
- {0xD4u, 0x09u},\r
- {0xD6u, 0x04u},\r
+ {0x82u, 0x47u},\r
+ {0x84u, 0x09u},\r
+ {0x85u, 0x44u},\r
+ {0x86u, 0x02u},\r
+ {0x87u, 0x88u},\r
+ {0x8Bu, 0x07u},\r
+ {0x8Cu, 0x0Au},\r
+ {0x8Eu, 0x05u},\r
+ {0x8Fu, 0x70u},\r
+ {0x92u, 0x20u},\r
+ {0x96u, 0x10u},\r
+ {0x97u, 0x08u},\r
+ {0x98u, 0x04u},\r
+ {0x99u, 0x99u},\r
+ {0x9Au, 0x08u},\r
+ {0x9Bu, 0x22u},\r
+ {0x9Cu, 0x50u},\r
+ {0x9Eu, 0xA0u},\r
+ {0xA2u, 0x80u},\r
+ {0xA6u, 0x08u},\r
+ {0xA7u, 0x80u},\r
+ {0xADu, 0xAAu},\r
+ {0xAFu, 0x55u},\r
+ {0xB0u, 0x0Fu},\r
+ {0xB2u, 0x30u},\r
+ {0xB4u, 0xC0u},\r
+ {0xB5u, 0x0Fu},\r
+ {0xB7u, 0xF0u},\r
+ {0xBEu, 0x14u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDCu, 0x11u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x80u},\r
- {0x03u, 0x84u},\r
- {0x04u, 0x01u},\r
- {0x05u, 0x50u},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0x10u},\r
- {0x0Bu, 0x06u},\r
- {0x0Cu, 0x80u},\r
- {0x0Eu, 0x28u},\r
- {0x10u, 0x02u},\r
- {0x12u, 0x40u},\r
- {0x13u, 0x10u},\r
- {0x14u, 0x02u},\r
- {0x15u, 0x28u},\r
- {0x17u, 0x01u},\r
- {0x18u, 0x80u},\r
+ {0x01u, 0x82u},\r
+ {0x03u, 0x10u},\r
+ {0x04u, 0x10u},\r
+ {0x05u, 0x04u},\r
+ {0x06u, 0x40u},\r
+ {0x08u, 0x01u},\r
+ {0x0Au, 0x22u},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Du, 0x80u},\r
+ {0x0Eu, 0x20u},\r
+ {0x10u, 0xA0u},\r
+ {0x14u, 0x04u},\r
+ {0x17u, 0x08u},\r
+ {0x19u, 0x1Au},\r
{0x1Cu, 0x08u},\r
- {0x1Du, 0x50u},\r
- {0x1Fu, 0x08u},\r
- {0x23u, 0x04u},\r
- {0x25u, 0x08u},\r
- {0x29u, 0x20u},\r
- {0x2Au, 0x4Cu},\r
- {0x32u, 0x50u},\r
- {0x37u, 0x01u},\r
- {0x38u, 0x0Cu},\r
- {0x3Au, 0x80u},\r
- {0x58u, 0xA0u},\r
- {0x59u, 0x05u},\r
- {0x5Du, 0x40u},\r
- {0x62u, 0x80u},\r
- {0x63u, 0x80u},\r
- {0x64u, 0x02u},\r
- {0x68u, 0x02u},\r
- {0x69u, 0x10u},\r
- {0x6Au, 0x16u},\r
- {0x70u, 0x04u},\r
- {0x72u, 0x8Au},\r
- {0x81u, 0x20u},\r
+ {0x1Eu, 0x01u},\r
+ {0x1Fu, 0x01u},\r
+ {0x21u, 0x50u},\r
+ {0x24u, 0x04u},\r
+ {0x25u, 0x90u},\r
+ {0x26u, 0x04u},\r
+ {0x27u, 0x10u},\r
+ {0x29u, 0x80u},\r
+ {0x2Au, 0x08u},\r
+ {0x2Du, 0x80u},\r
+ {0x2Fu, 0x04u},\r
+ {0x30u, 0x08u},\r
+ {0x33u, 0x10u},\r
+ {0x36u, 0x01u},\r
+ {0x37u, 0x10u},\r
+ {0x39u, 0xA0u},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Cu, 0x02u},\r
+ {0x3Du, 0x24u},\r
+ {0x3Eu, 0x80u},\r
+ {0x41u, 0x02u},\r
+ {0x42u, 0x80u},\r
+ {0x58u, 0x40u},\r
+ {0x5Cu, 0x40u},\r
+ {0x5Du, 0x20u},\r
+ {0x5Fu, 0x06u},\r
+ {0x60u, 0x02u},\r
+ {0x66u, 0x02u},\r
+ {0x67u, 0x01u},\r
{0x82u, 0x02u},\r
- {0x87u, 0x80u},\r
- {0x89u, 0x10u},\r
- {0x8Bu, 0x14u},\r
- {0x8Du, 0x10u},\r
- {0x90u, 0x01u},\r
- {0x91u, 0x28u},\r
- {0x92u, 0x28u},\r
- {0x93u, 0xC0u},\r
- {0x94u, 0x80u},\r
- {0x96u, 0x02u},\r
+ {0x83u, 0x20u},\r
+ {0x85u, 0x29u},\r
+ {0x88u, 0x02u},\r
+ {0x8Au, 0x14u},\r
+ {0x8Du, 0x18u},\r
+ {0x90u, 0x80u},\r
+ {0x91u, 0x04u},\r
+ {0x92u, 0x82u},\r
+ {0x93u, 0x58u},\r
+ {0x94u, 0x14u},\r
+ {0x96u, 0x4Du},\r
+ {0x97u, 0x22u},\r
+ {0x98u, 0x81u},\r
{0x99u, 0x80u},\r
- {0x9Bu, 0x01u},\r
+ {0x9Au, 0x08u},\r
+ {0x9Bu, 0x20u},\r
{0x9Cu, 0x12u},\r
- {0x9Du, 0x50u},\r
- {0x9Eu, 0xF4u},\r
- {0x9Fu, 0x10u},\r
- {0xA0u, 0x89u},\r
- {0xA1u, 0x01u},\r
- {0xA2u, 0x14u},\r
- {0xA4u, 0x04u},\r
- {0xA5u, 0x0Au},\r
- {0xA6u, 0x0Au},\r
- {0xA7u, 0x02u},\r
- {0xA8u, 0x04u},\r
+ {0x9Du, 0x46u},\r
+ {0x9Eu, 0x10u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA0u, 0xA9u},\r
+ {0xA1u, 0x02u},\r
+ {0xA2u, 0x51u},\r
+ {0xA4u, 0x40u},\r
+ {0xA5u, 0x21u},\r
+ {0xA6u, 0xACu},\r
+ {0xA7u, 0x08u},\r
{0xA9u, 0x40u},\r
- {0xAEu, 0x80u},\r
- {0xB4u, 0x01u},\r
- {0xC0u, 0xDBu},\r
- {0xC2u, 0xEFu},\r
- {0xC4u, 0xFBu},\r
- {0xCAu, 0x0Eu},\r
- {0xCCu, 0x8Cu},\r
- {0xCEu, 0x0Au},\r
- {0xD6u, 0x1Fu},\r
- {0xD8u, 0x19u},\r
- {0xE4u, 0x05u},\r
- {0xE6u, 0x08u},\r
- {0xE8u, 0x02u},\r
- {0x00u, 0x0Fu},\r
- {0x01u, 0x80u},\r
- {0x02u, 0xF0u},\r
- {0x03u, 0x50u},\r
- {0x04u, 0x30u},\r
- {0x05u, 0x04u},\r
- {0x06u, 0xC0u},\r
- {0x07u, 0x08u},\r
- {0x08u, 0x09u},\r
- {0x09u, 0x80u},\r
- {0x0Au, 0x06u},\r
- {0x0Bu, 0x40u},\r
- {0x0Cu, 0x03u},\r
- {0x0Eu, 0x0Cu},\r
- {0x0Fu, 0x07u},\r
- {0x11u, 0x80u},\r
- {0x12u, 0xFFu},\r
- {0x13u, 0x60u},\r
- {0x14u, 0x50u},\r
- {0x15u, 0x80u},\r
- {0x16u, 0xA0u},\r
- {0x17u, 0x40u},\r
- {0x19u, 0x40u},\r
+ {0xABu, 0x42u},\r
+ {0xACu, 0x01u},\r
+ {0xADu, 0x11u},\r
+ {0xAFu, 0x08u},\r
+ {0xB2u, 0x40u},\r
+ {0xC0u, 0x7Du},\r
+ {0xC2u, 0xAFu},\r
+ {0xC4u, 0x6Cu},\r
+ {0xCAu, 0x3Au},\r
+ {0xCCu, 0xA6u},\r
+ {0xCEu, 0xFEu},\r
+ {0xD6u, 0xF8u},\r
+ {0xD8u, 0x98u},\r
+ {0xE0u, 0x01u},\r
+ {0xE4u, 0x08u},\r
+ {0xE8u, 0x0Au},\r
+ {0xEAu, 0x04u},\r
+ {0xECu, 0x01u},\r
+ {0xEEu, 0x08u},\r
+ {0x01u, 0x3Fu},\r
+ {0x02u, 0xFFu},\r
+ {0x04u, 0x33u},\r
+ {0x05u, 0x01u},\r
+ {0x06u, 0xCCu},\r
+ {0x07u, 0x02u},\r
+ {0x09u, 0x04u},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Eu, 0xFFu},\r
+ {0x0Fu, 0x3Fu},\r
+ {0x10u, 0x0Fu},\r
+ {0x11u, 0x10u},\r
+ {0x12u, 0xF0u},\r
+ {0x13u, 0x20u},\r
+ {0x14u, 0x69u},\r
+ {0x15u, 0x10u},\r
+ {0x16u, 0x96u},\r
+ {0x17u, 0x20u},\r
+ {0x19u, 0x01u},\r
{0x1Au, 0xFFu},\r
- {0x1Bu, 0x80u},\r
- {0x1Cu, 0x90u},\r
- {0x1Eu, 0x60u},\r
- {0x20u, 0x05u},\r
- {0x21u, 0x0Au},\r
- {0x22u, 0x0Au},\r
- {0x23u, 0x05u},\r
- {0x26u, 0xFFu},\r
- {0x27u, 0x08u},\r
- {0x2Du, 0x09u},\r
- {0x2Fu, 0x02u},\r
- {0x31u, 0x0Fu},\r
- {0x33u, 0xC0u},\r
- {0x35u, 0x20u},\r
- {0x36u, 0xFFu},\r
- {0x37u, 0x10u},\r
- {0x3Bu, 0x08u},\r
- {0x3Eu, 0x40u},\r
- {0x54u, 0x40u},\r
- {0x56u, 0x04u},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Cu, 0xFFu},\r
+ {0x20u, 0x55u},\r
+ {0x21u, 0x3Fu},\r
+ {0x22u, 0xAAu},\r
+ {0x27u, 0x3Fu},\r
+ {0x29u, 0x04u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Cu, 0xFFu},\r
+ {0x2Fu, 0x3Fu},\r
+ {0x30u, 0xFFu},\r
+ {0x33u, 0x03u},\r
+ {0x35u, 0x0Cu},\r
+ {0x37u, 0x30u},\r
+ {0x3Au, 0x02u},\r
+ {0x3Bu, 0xA8u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x10u},\r
+ {0x5Cu, 0x11u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x02u},\r
- {0x82u, 0x01u},\r
- {0x84u, 0x01u},\r
- {0x86u, 0x02u},\r
- {0x8Bu, 0x04u},\r
- {0x8Du, 0x12u},\r
- {0x8Fu, 0x24u},\r
- {0x93u, 0x01u},\r
- {0x94u, 0x02u},\r
- {0x96u, 0x01u},\r
- {0x97u, 0x08u},\r
- {0x9Cu, 0x02u},\r
- {0x9Eu, 0x01u},\r
- {0xA3u, 0x10u},\r
+ {0x80u, 0x96u},\r
+ {0x82u, 0x69u},\r
+ {0x88u, 0x0Fu},\r
+ {0x8Au, 0xF0u},\r
+ {0x8Cu, 0xFFu},\r
+ {0x90u, 0xFFu},\r
+ {0x93u, 0x02u},\r
+ {0x94u, 0x33u},\r
+ {0x96u, 0xCCu},\r
+ {0x97u, 0x01u},\r
+ {0x9Au, 0xFFu},\r
+ {0x9Eu, 0xFFu},\r
+ {0xA0u, 0x55u},\r
+ {0xA2u, 0xAAu},\r
+ {0xA5u, 0x01u},\r
{0xA7u, 0x02u},\r
- {0xA8u, 0x02u},\r
- {0xAAu, 0x01u},\r
- {0xABu, 0x20u},\r
- {0xB1u, 0x08u},\r
- {0xB3u, 0x01u},\r
- {0xB4u, 0x03u},\r
- {0xB5u, 0x30u},\r
- {0xB7u, 0x06u},\r
+ {0xAEu, 0xFFu},\r
+ {0xB4u, 0xFFu},\r
+ {0xB7u, 0x03u},\r
{0xBAu, 0x20u},\r
- {0xBFu, 0x50u},\r
+ {0xBFu, 0x40u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
+ {0xDCu, 0x01u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x04u},\r
+ {0x00u, 0x40u},\r
+ {0x01u, 0x20u},\r
{0x02u, 0x80u},\r
- {0x04u, 0x12u},\r
- {0x05u, 0x40u},\r
- {0x06u, 0x14u},\r
- {0x09u, 0x08u},\r
- {0x0Au, 0x02u},\r
- {0x0Cu, 0x84u},\r
- {0x0Du, 0x02u},\r
- {0x0Eu, 0x20u},\r
- {0x0Fu, 0x08u},\r
- {0x13u, 0x10u},\r
- {0x14u, 0x40u},\r
+ {0x04u, 0x06u},\r
+ {0x06u, 0x02u},\r
+ {0x08u, 0x1Au},\r
+ {0x09u, 0x40u},\r
+ {0x0Au, 0x41u},\r
+ {0x0Bu, 0x80u},\r
+ {0x0Cu, 0x10u},\r
+ {0x0Eu, 0x80u},\r
+ {0x0Fu, 0x12u},\r
+ {0x11u, 0x40u},\r
+ {0x12u, 0x40u},\r
+ {0x14u, 0x02u},\r
{0x15u, 0x02u},\r
- {0x17u, 0x08u},\r
- {0x18u, 0x04u},\r
- {0x1Fu, 0x80u},\r
- {0x21u, 0x40u},\r
- {0x22u, 0x11u},\r
- {0x23u, 0x10u},\r
- {0x24u, 0x40u},\r
- {0x25u, 0x10u},\r
- {0x26u, 0x21u},\r
+ {0x19u, 0x20u},\r
+ {0x1Eu, 0x80u},\r
+ {0x1Fu, 0x02u},\r
+ {0x22u, 0x40u},\r
+ {0x24u, 0x20u},\r
+ {0x26u, 0x10u},\r
{0x27u, 0x11u},\r
- {0x28u, 0x44u},\r
{0x29u, 0x04u},\r
- {0x2Cu, 0x20u},\r
- {0x2Eu, 0x02u},\r
- {0x2Fu, 0x02u},\r
- {0x31u, 0x08u},\r
- {0x32u, 0x01u},\r
- {0x34u, 0x20u},\r
- {0x37u, 0x15u},\r
- {0x38u, 0x20u},\r
- {0x39u, 0x40u},\r
- {0x3Cu, 0x40u},\r
- {0x3Du, 0x28u},\r
- {0x3Fu, 0x02u},\r
- {0x58u, 0x80u},\r
- {0x63u, 0x02u},\r
- {0x66u, 0x28u},\r
- {0x67u, 0x82u},\r
- {0x6Cu, 0x03u},\r
- {0x6Du, 0x40u},\r
- {0x81u, 0x04u},\r
- {0x83u, 0x20u},\r
- {0x84u, 0x40u},\r
- {0x89u, 0x02u},\r
+ {0x2Cu, 0x10u},\r
+ {0x2Du, 0x40u},\r
+ {0x2Fu, 0x44u},\r
+ {0x30u, 0x0Au},\r
+ {0x36u, 0x08u},\r
+ {0x37u, 0x11u},\r
+ {0x3Cu, 0x04u},\r
+ {0x3Du, 0x80u},\r
+ {0x3Fu, 0x12u},\r
+ {0x44u, 0x90u},\r
+ {0x45u, 0x48u},\r
+ {0x46u, 0x02u},\r
+ {0x47u, 0x02u},\r
+ {0x59u, 0x08u},\r
+ {0x5Au, 0x20u},\r
+ {0x5Bu, 0x40u},\r
+ {0x5Cu, 0x80u},\r
+ {0x5Eu, 0x19u},\r
+ {0x60u, 0x04u},\r
+ {0x62u, 0x80u},\r
+ {0x63u, 0x10u},\r
+ {0x67u, 0x02u},\r
+ {0x82u, 0x10u},\r
+ {0x83u, 0x21u},\r
+ {0x89u, 0x01u},\r
{0x8Au, 0x10u},\r
- {0x8Bu, 0x08u},\r
- {0x8Du, 0x08u},\r
- {0x8Eu, 0x02u},\r
- {0x90u, 0x10u},\r
- {0x91u, 0x02u},\r
- {0x92u, 0x08u},\r
- {0x95u, 0x80u},\r
- {0x96u, 0x40u},\r
- {0x97u, 0x80u},\r
- {0x99u, 0x40u},\r
- {0x9Bu, 0x0Cu},\r
- {0x9Cu, 0x26u},\r
- {0x9Du, 0x08u},\r
- {0x9Eu, 0x12u},\r
- {0xA0u, 0x20u},\r
- {0xA1u, 0x0Cu},\r
- {0xA2u, 0x80u},\r
- {0xA3u, 0x02u},\r
- {0xA4u, 0x82u},\r
- {0xA5u, 0x02u},\r
- {0xA6u, 0x20u},\r
- {0xA7u, 0xA0u},\r
- {0xA9u, 0x40u},\r
- {0xAAu, 0x04u},\r
- {0xAEu, 0x01u},\r
- {0xAFu, 0x04u},\r
- {0xB6u, 0x40u},\r
- {0xB7u, 0x20u},\r
- {0xC0u, 0xFCu},\r
- {0xC2u, 0xF5u},\r
- {0xC4u, 0x32u},\r
- {0xCAu, 0xD7u},\r
+ {0x8Bu, 0x05u},\r
+ {0x8Cu, 0x08u},\r
+ {0x8Eu, 0x40u},\r
+ {0x90u, 0x40u},\r
+ {0x92u, 0x40u},\r
+ {0x94u, 0xA0u},\r
+ {0x98u, 0x08u},\r
+ {0x99u, 0x04u},\r
+ {0x9Au, 0x40u},\r
+ {0x9Bu, 0x02u},\r
+ {0x9Cu, 0x01u},\r
+ {0xA0u, 0x02u},\r
+ {0xA1u, 0x48u},\r
+ {0xA2u, 0x0Cu},\r
+ {0xA3u, 0x21u},\r
+ {0xA4u, 0x28u},\r
+ {0xA6u, 0x02u},\r
+ {0xA9u, 0x04u},\r
+ {0xABu, 0x0Au},\r
+ {0xACu, 0x94u},\r
+ {0xAFu, 0x01u},\r
+ {0xB3u, 0x08u},\r
+ {0xC0u, 0xBBu},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0x99u},\r
+ {0xCAu, 0xF2u},\r
{0xCCu, 0xE3u},\r
- {0xCEu, 0xFCu},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0xF8u},\r
- {0xE0u, 0xC0u},\r
- {0xE4u, 0x20u},\r
- {0xE6u, 0x80u},\r
- {0xE8u, 0x01u},\r
- {0xECu, 0x16u},\r
- {0x04u, 0x0Au},\r
- {0x06u, 0x05u},\r
- {0x07u, 0x02u},\r
- {0x0Au, 0x17u},\r
- {0x0Cu, 0x09u},\r
- {0x0Eu, 0x02u},\r
- {0x11u, 0x01u},\r
- {0x13u, 0x02u},\r
- {0x14u, 0x04u},\r
- {0x16u, 0x08u},\r
- {0x1Au, 0x08u},\r
- {0x1Fu, 0x04u},\r
- {0x22u, 0x20u},\r
- {0x2Cu, 0x10u},\r
- {0x2Eu, 0x20u},\r
- {0x2Fu, 0x01u},\r
- {0x31u, 0x03u},\r
- {0x32u, 0x0Fu},\r
- {0x33u, 0x04u},\r
- {0x34u, 0x30u},\r
- {0x3Eu, 0x10u},\r
+ {0xCEu, 0xF0u},\r
+ {0xD6u, 0xFEu},\r
+ {0xD8u, 0x1Eu},\r
+ {0xE0u, 0x60u},\r
+ {0xE2u, 0x80u},\r
+ {0xE4u, 0x18u},\r
+ {0xE6u, 0x20u},\r
+ {0xE8u, 0x02u},\r
+ {0xECu, 0x80u},\r
+ {0xEEu, 0x02u},\r
+ {0x00u, 0x04u},\r
+ {0x02u, 0x08u},\r
+ {0x04u, 0x01u},\r
+ {0x06u, 0x06u},\r
+ {0x09u, 0x50u},\r
+ {0x0Bu, 0xA0u},\r
+ {0x0Du, 0x06u},\r
+ {0x0Fu, 0x09u},\r
+ {0x10u, 0x02u},\r
+ {0x11u, 0x30u},\r
+ {0x12u, 0x01u},\r
+ {0x13u, 0xC0u},\r
+ {0x14u, 0x02u},\r
+ {0x15u, 0x03u},\r
+ {0x16u, 0x01u},\r
+ {0x17u, 0x0Cu},\r
+ {0x18u, 0x02u},\r
+ {0x19u, 0x05u},\r
+ {0x1Au, 0x01u},\r
+ {0x1Bu, 0x0Au},\r
+ {0x1Cu, 0x02u},\r
+ {0x1Eu, 0x09u},\r
+ {0x25u, 0x0Fu},\r
+ {0x27u, 0xF0u},\r
+ {0x29u, 0x60u},\r
+ {0x2Bu, 0x90u},\r
+ {0x30u, 0x0Cu},\r
+ {0x31u, 0xFFu},\r
+ {0x34u, 0x03u},\r
+ {0x3Au, 0x20u},\r
+ {0x3Eu, 0x01u},\r
{0x3Fu, 0x01u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
+ {0x5Cu, 0x01u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x82u, 0x80u},\r
+ {0x80u, 0x05u},\r
+ {0x82u, 0x0Au},\r
{0x84u, 0x0Fu},\r
- {0x85u, 0x10u},\r
- {0x87u, 0x20u},\r
- {0x88u, 0x04u},\r
- {0x89u, 0x01u},\r
- {0x8Au, 0x08u},\r
- {0x8Cu, 0xAFu},\r
- {0x8Eu, 0x50u},\r
- {0x8Fu, 0x1Cu},\r
- {0x90u, 0x40u},\r
- {0x91u, 0x01u},\r
- {0x92u, 0x8Fu},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x28u},\r
- {0x96u, 0x08u},\r
- {0x97u, 0x14u},\r
- {0x98u, 0x01u},\r
- {0x9Au, 0x02u},\r
- {0x9Bu, 0x02u},\r
- {0x9Eu, 0x70u},\r
- {0xA0u, 0x90u},\r
- {0xA1u, 0x01u},\r
- {0xA2u, 0x2Fu},\r
- {0xA7u, 0x20u},\r
- {0xA8u, 0x01u},\r
- {0xA9u, 0x01u},\r
- {0xAAu, 0x02u},\r
- {0xADu, 0x24u},\r
- {0xAEu, 0x0Fu},\r
- {0xAFu, 0x08u},\r
- {0xB1u, 0x3Cu},\r
- {0xB2u, 0x0Cu},\r
- {0xB3u, 0x01u},\r
- {0xB4u, 0x03u},\r
- {0xB5u, 0x02u},\r
- {0xB6u, 0xF0u},\r
- {0xB9u, 0x08u},\r
- {0xBAu, 0x28u},\r
- {0xBFu, 0x04u},\r
+ {0x85u, 0x30u},\r
+ {0x86u, 0xF0u},\r
+ {0x87u, 0xC0u},\r
+ {0x89u, 0x50u},\r
+ {0x8Bu, 0xA0u},\r
+ {0x8Cu, 0x30u},\r
+ {0x8Eu, 0xC0u},\r
+ {0x8Fu, 0xFFu},\r
+ {0x90u, 0x06u},\r
+ {0x91u, 0x90u},\r
+ {0x92u, 0x09u},\r
+ {0x93u, 0x60u},\r
+ {0x94u, 0x50u},\r
+ {0x96u, 0xA0u},\r
+ {0x97u, 0xFFu},\r
+ {0x99u, 0x03u},\r
+ {0x9Au, 0xFFu},\r
+ {0x9Bu, 0x0Cu},\r
+ {0x9Cu, 0xFFu},\r
+ {0x9Du, 0x05u},\r
+ {0x9Fu, 0x0Au},\r
+ {0xA0u, 0x60u},\r
+ {0xA2u, 0x90u},\r
+ {0xA4u, 0x03u},\r
+ {0xA6u, 0x0Cu},\r
+ {0xA7u, 0xFFu},\r
+ {0xA9u, 0x0Fu},\r
+ {0xABu, 0xF0u},\r
+ {0xADu, 0x09u},\r
+ {0xAEu, 0xFFu},\r
+ {0xAFu, 0x06u},\r
+ {0xB0u, 0xFFu},\r
+ {0xB1u, 0xFFu},\r
+ {0xBEu, 0x01u},\r
+ {0xBFu, 0x01u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x10u},\r
- {0x01u, 0x08u},\r
- {0x03u, 0x02u},\r
- {0x05u, 0x10u},\r
- {0x06u, 0x42u},\r
- {0x07u, 0x20u},\r
- {0x09u, 0x14u},\r
- {0x0Du, 0x20u},\r
- {0x0Eu, 0x22u},\r
- {0x0Fu, 0x80u},\r
- {0x10u, 0x82u},\r
- {0x14u, 0x01u},\r
- {0x15u, 0x01u},\r
- {0x16u, 0x04u},\r
- {0x18u, 0x10u},\r
- {0x1Au, 0x08u},\r
- {0x1Cu, 0x02u},\r
- {0x1Du, 0x60u},\r
- {0x1Eu, 0x22u},\r
- {0x1Fu, 0x04u},\r
- {0x21u, 0x08u},\r
- {0x22u, 0x01u},\r
- {0x24u, 0x40u},\r
- {0x26u, 0x04u},\r
- {0x27u, 0x04u},\r
- {0x28u, 0x02u},\r
- {0x2Eu, 0x08u},\r
- {0x2Fu, 0x8Au},\r
- {0x30u, 0x02u},\r
- {0x32u, 0x80u},\r
- {0x35u, 0x09u},\r
- {0x36u, 0x20u},\r
- {0x3Bu, 0x04u},\r
- {0x3Cu, 0x40u},\r
- {0x3Du, 0x08u},\r
- {0x3Eu, 0x10u},\r
- {0x5Au, 0x80u},\r
- {0x5Cu, 0x24u},\r
+ {0x00u, 0x06u},\r
+ {0x05u, 0x04u},\r
+ {0x06u, 0x01u},\r
+ {0x07u, 0x40u},\r
+ {0x08u, 0x02u},\r
+ {0x09u, 0xA0u},\r
+ {0x0Au, 0x20u},\r
+ {0x0Cu, 0x81u},\r
+ {0x0Eu, 0x04u},\r
+ {0x0Fu, 0x10u},\r
+ {0x14u, 0x20u},\r
+ {0x15u, 0x40u},\r
+ {0x17u, 0x01u},\r
+ {0x18u, 0x44u},\r
+ {0x1Au, 0x80u},\r
+ {0x1Bu, 0x21u},\r
+ {0x1Fu, 0x02u},\r
+ {0x20u, 0x80u},\r
+ {0x25u, 0x02u},\r
+ {0x29u, 0x24u},\r
+ {0x2Cu, 0x01u},\r
+ {0x2Eu, 0x04u},\r
+ {0x2Fu, 0x18u},\r
+ {0x30u, 0x2Au},\r
+ {0x34u, 0x24u},\r
+ {0x36u, 0x60u},\r
+ {0x37u, 0x41u},\r
+ {0x38u, 0x80u},\r
+ {0x3Au, 0x10u},\r
+ {0x3Bu, 0x80u},\r
+ {0x3Cu, 0x80u},\r
+ {0x3Du, 0x6Cu},\r
+ {0x3Fu, 0x10u},\r
+ {0x58u, 0x90u},\r
+ {0x5Bu, 0x04u},\r
{0x5Du, 0x02u},\r
- {0x5Eu, 0x40u},\r
- {0x62u, 0x80u},\r
- {0x67u, 0x01u},\r
- {0x83u, 0x01u},\r
- {0x87u, 0x04u},\r
- {0x88u, 0x01u},\r
- {0x8Au, 0x40u},\r
- {0x8Du, 0x02u},\r
- {0x8Eu, 0x11u},\r
- {0x90u, 0x04u},\r
- {0x91u, 0x03u},\r
- {0x94u, 0x50u},\r
+ {0x5Eu, 0x20u},\r
+ {0x5Fu, 0x88u},\r
+ {0x60u, 0x08u},\r
+ {0x61u, 0x40u},\r
+ {0x62u, 0x48u},\r
+ {0x63u, 0x20u},\r
+ {0x67u, 0x02u},\r
+ {0x68u, 0x01u},\r
+ {0x80u, 0x20u},\r
+ {0x81u, 0x06u},\r
+ {0x82u, 0x01u},\r
+ {0x84u, 0x90u},\r
+ {0x87u, 0x01u},\r
+ {0x89u, 0x40u},\r
+ {0x8Au, 0x01u},\r
+ {0x8Du, 0x01u},\r
+ {0x8Eu, 0x44u},\r
+ {0x8Fu, 0x80u},\r
+ {0x91u, 0x04u},\r
+ {0x92u, 0x22u},\r
+ {0x93u, 0x22u},\r
+ {0x94u, 0x20u},\r
+ {0x96u, 0x80u},\r
{0x97u, 0x80u},\r
- {0x99u, 0x11u},\r
- {0x9Au, 0x0Cu},\r
- {0x9Bu, 0x08u},\r
- {0x9Cu, 0x04u},\r
- {0x9Du, 0x4Au},\r
- {0x9Eu, 0x10u},\r
- {0x9Fu, 0x20u},\r
- {0xA0u, 0x20u},\r
- {0xA1u, 0x14u},\r
- {0xA3u, 0x4Au},\r
- {0xA4u, 0x83u},\r
- {0xA5u, 0x22u},\r
- {0xA7u, 0x20u},\r
- {0xA9u, 0x04u},\r
+ {0x98u, 0x02u},\r
+ {0x99u, 0x22u},\r
+ {0x9Au, 0x10u},\r
+ {0x9Bu, 0x07u},\r
+ {0x9Cu, 0x0Du},\r
+ {0x9Du, 0x41u},\r
+ {0xA0u, 0x12u},\r
+ {0xA1u, 0xB8u},\r
+ {0xA2u, 0x50u},\r
+ {0xA4u, 0x40u},\r
+ {0xA5u, 0x40u},\r
+ {0xA6u, 0x22u},\r
+ {0xA7u, 0x19u},\r
+ {0xA8u, 0x50u},\r
{0xAAu, 0x10u},\r
- {0xABu, 0x44u},\r
- {0xADu, 0x80u},\r
- {0xB1u, 0x01u},\r
+ {0xACu, 0x20u},\r
+ {0xAFu, 0x18u},\r
{0xB2u, 0x08u},\r
- {0xB3u, 0x02u},\r
- {0xB6u, 0x40u},\r
- {0xC0u, 0xF7u},\r
- {0xC2u, 0xF6u},\r
- {0xC4u, 0xD9u},\r
- {0xCAu, 0xF8u},\r
- {0xCCu, 0xE9u},\r
- {0xCEu, 0x72u},\r
- {0xD6u, 0xF8u},\r
- {0xD8u, 0x18u},\r
- {0xE0u, 0x40u},\r
- {0xE2u, 0x14u},\r
- {0xE4u, 0xF0u},\r
- {0xE6u, 0x01u},\r
- {0xEAu, 0x08u},\r
- {0xECu, 0x80u},\r
- {0x03u, 0x03u},\r
- {0x04u, 0x30u},\r
- {0x06u, 0xC0u},\r
- {0x07u, 0x03u},\r
- {0x08u, 0x06u},\r
- {0x09u, 0x04u},\r
- {0x0Au, 0x09u},\r
+ {0xB4u, 0x02u},\r
+ {0xB7u, 0x01u},\r
+ {0xC0u, 0xBCu},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0xB0u},\r
+ {0xCAu, 0x76u},\r
+ {0xCCu, 0xF7u},\r
+ {0xCEu, 0x7Cu},\r
+ {0xD6u, 0xFEu},\r
+ {0xD8u, 0x1Eu},\r
+ {0xE0u, 0x48u},\r
+ {0xE2u, 0x30u},\r
+ {0xE4u, 0x70u},\r
+ {0xE6u, 0x0Au},\r
+ {0xE8u, 0x50u},\r
+ {0xEEu, 0x88u},\r
+ {0x01u, 0x64u},\r
+ {0x06u, 0x02u},\r
+ {0x08u, 0x01u},\r
+ {0x0Au, 0x02u},\r
{0x0Bu, 0x08u},\r
- {0x0Cu, 0x03u},\r
- {0x0Du, 0x08u},\r
- {0x0Eu, 0x0Cu},\r
- {0x0Fu, 0x04u},\r
- {0x10u, 0xFFu},\r
- {0x11u, 0x01u},\r
- {0x13u, 0x02u},\r
- {0x14u, 0x50u},\r
- {0x15u, 0x03u},\r
- {0x16u, 0xA0u},\r
+ {0x0Fu, 0x7Fu},\r
+ {0x11u, 0x78u},\r
+ {0x12u, 0x01u},\r
+ {0x13u, 0x03u},\r
+ {0x15u, 0x20u},\r
+ {0x17u, 0x40u},\r
{0x19u, 0x03u},\r
- {0x1Au, 0xFFu},\r
- {0x1Cu, 0x60u},\r
- {0x1Du, 0x20u},\r
- {0x1Eu, 0x90u},\r
- {0x1Fu, 0x10u},\r
- {0x20u, 0x05u},\r
- {0x22u, 0x0Au},\r
- {0x23u, 0x03u},\r
- {0x25u, 0x10u},\r
- {0x26u, 0xFFu},\r
- {0x27u, 0x20u},\r
- {0x29u, 0x01u},\r
- {0x2Bu, 0x02u},\r
- {0x2Cu, 0x0Fu},\r
- {0x2Du, 0x0Cu},\r
- {0x2Eu, 0xF0u},\r
- {0x2Fu, 0x30u},\r
- {0x30u, 0xFFu},\r
- {0x35u, 0x3Cu},\r
- {0x37u, 0x03u},\r
- {0x3Bu, 0x80u},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x10u},\r
- {0x56u, 0x08u},\r
+ {0x1Bu, 0x74u},\r
+ {0x21u, 0x02u},\r
+ {0x27u, 0x01u},\r
+ {0x29u, 0x20u},\r
+ {0x2Bu, 0x40u},\r
+ {0x2Du, 0x01u},\r
+ {0x2Fu, 0x6Eu},\r
+ {0x32u, 0x03u},\r
+ {0x33u, 0x1Fu},\r
+ {0x35u, 0x60u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Eu, 0x04u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
{0x5Cu, 0x10u},\r
- {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x03u},\r
- {0x82u, 0x0Cu},\r
- {0x84u, 0x30u},\r
- {0x85u, 0x01u},\r
- {0x86u, 0xC0u},\r
+ {0x83u, 0xFFu},\r
+ {0x85u, 0x33u},\r
+ {0x86u, 0x02u},\r
+ {0x87u, 0xCCu},\r
{0x88u, 0x09u},\r
- {0x8Au, 0x06u},\r
- {0x8Fu, 0x02u},\r
- {0x90u, 0xFFu},\r
- {0x91u, 0x02u},\r
- {0x93u, 0x04u},\r
- {0x96u, 0xFFu},\r
- {0x9Cu, 0x05u},\r
- {0x9Eu, 0x0Au},\r
- {0xA0u, 0x90u},\r
- {0xA2u, 0x60u},\r
- {0xA4u, 0xFFu},\r
- {0xA8u, 0x50u},\r
- {0xAAu, 0xA0u},\r
- {0xABu, 0x04u},\r
- {0xACu, 0x0Fu},\r
- {0xAEu, 0xF0u},\r
- {0xB2u, 0xFFu},\r
- {0xB3u, 0x06u},\r
- {0xB5u, 0x01u},\r
- {0xBEu, 0x04u},\r
- {0xBFu, 0x04u},\r
+ {0x8Au, 0x12u},\r
+ {0x8Du, 0x55u},\r
+ {0x8Eu, 0x20u},\r
+ {0x8Fu, 0xAAu},\r
+ {0x91u, 0x0Fu},\r
+ {0x92u, 0x08u},\r
+ {0x93u, 0xF0u},\r
+ {0x97u, 0xFFu},\r
+ {0x9Au, 0x04u},\r
+ {0x9Fu, 0xFFu},\r
+ {0xA1u, 0xFFu},\r
+ {0xA5u, 0x69u},\r
+ {0xA6u, 0x10u},\r
+ {0xA7u, 0x96u},\r
+ {0xADu, 0xFFu},\r
+ {0xAEu, 0x01u},\r
+ {0xB0u, 0x04u},\r
+ {0xB1u, 0xFFu},\r
+ {0xB2u, 0x18u},\r
+ {0xB4u, 0x20u},\r
+ {0xB6u, 0x03u},\r
+ {0xBBu, 0x02u},\r
+ {0xBEu, 0x44u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x90u},\r
+ {0xDCu, 0x11u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x12u},\r
+ {0x00u, 0x50u},\r
{0x02u, 0x10u},\r
- {0x04u, 0x10u},\r
- {0x05u, 0x40u},\r
- {0x06u, 0x10u},\r
- {0x09u, 0x02u},\r
- {0x0Au, 0x22u},\r
- {0x0Cu, 0x84u},\r
- {0x0Du, 0x02u},\r
- {0x0Fu, 0x08u},\r
- {0x10u, 0x86u},\r
- {0x13u, 0x08u},\r
- {0x14u, 0x01u},\r
- {0x15u, 0x02u},\r
- {0x17u, 0x08u},\r
- {0x1Bu, 0x08u},\r
- {0x1Du, 0x01u},\r
- {0x20u, 0x20u},\r
- {0x21u, 0x10u},\r
- {0x27u, 0x0Au},\r
- {0x29u, 0x20u},\r
- {0x2Cu, 0x03u},\r
- {0x2Du, 0x02u},\r
+ {0x03u, 0x08u},\r
+ {0x04u, 0x18u},\r
+ {0x08u, 0x40u},\r
+ {0x09u, 0x40u},\r
+ {0x0Bu, 0x84u},\r
+ {0x0Eu, 0x80u},\r
+ {0x10u, 0x20u},\r
+ {0x12u, 0x02u},\r
+ {0x18u, 0x40u},\r
+ {0x19u, 0x14u},\r
+ {0x1Au, 0x01u},\r
+ {0x1Cu, 0x20u},\r
+ {0x22u, 0x01u},\r
+ {0x25u, 0x08u},\r
+ {0x26u, 0x08u},\r
+ {0x27u, 0x18u},\r
+ {0x28u, 0x08u},\r
+ {0x29u, 0x01u},\r
+ {0x2Au, 0x20u},\r
+ {0x2Bu, 0x11u},\r
+ {0x2Du, 0x42u},\r
{0x2Eu, 0x20u},\r
- {0x2Fu, 0x20u},\r
- {0x30u, 0x02u},\r
- {0x35u, 0x08u},\r
- {0x36u, 0x40u},\r
- {0x37u, 0x22u},\r
- {0x38u, 0x44u},\r
- {0x39u, 0x08u},\r
- {0x3Cu, 0x40u},\r
- {0x3Du, 0x19u},\r
- {0x58u, 0x20u},\r
- {0x5Au, 0x40u},\r
- {0x5Du, 0x80u},\r
- {0x61u, 0x10u},\r
- {0x62u, 0xE0u},\r
- {0x67u, 0x02u},\r
- {0x78u, 0x08u},\r
- {0x7Bu, 0x20u},\r
- {0x82u, 0x20u},\r
- {0x83u, 0x01u},\r
- {0x86u, 0x40u},\r
- {0x88u, 0x30u},\r
- {0x89u, 0x20u},\r
- {0x8Au, 0x40u},\r
- {0x91u, 0x1Au},\r
- {0x92u, 0x02u},\r
- {0x95u, 0x21u},\r
- {0x97u, 0x82u},\r
- {0x9Au, 0x2Cu},\r
- {0x9Cu, 0x09u},\r
- {0x9Du, 0x02u},\r
- {0x9Eu, 0x10u},\r
- {0x9Fu, 0x22u},\r
- {0xA0u, 0x20u},\r
- {0xA1u, 0x10u},\r
- {0xA4u, 0x01u},\r
- {0xA5u, 0x20u},\r
- {0xA6u, 0x88u},\r
- {0xA7u, 0x40u},\r
- {0xAAu, 0x10u},\r
- {0xABu, 0x10u},\r
- {0xADu, 0xA0u},\r
- {0xAFu, 0x09u},\r
- {0xB3u, 0x42u},\r
- {0xB7u, 0x08u},\r
- {0xC0u, 0xEEu},\r
- {0xC2u, 0xFDu},\r
- {0xC4u, 0xBFu},\r
- {0xCAu, 0xF4u},\r
- {0xCCu, 0xF1u},\r
- {0xCEu, 0xFAu},\r
- {0xD6u, 0x1Cu},\r
- {0xD8u, 0x1Cu},\r
- {0xE0u, 0x20u},\r
- {0xE6u, 0x4Au},\r
- {0xEAu, 0x21u},\r
- {0xECu, 0x08u},\r
- {0xEEu, 0x80u},\r
- {0x01u, 0x02u},\r
- {0x02u, 0x04u},\r
- {0x03u, 0x01u},\r
- {0x05u, 0x01u},\r
+ {0x2Fu, 0x90u},\r
+ {0x30u, 0x40u},\r
+ {0x31u, 0x08u},\r
+ {0x32u, 0x01u},\r
+ {0x35u, 0x01u},\r
+ {0x37u, 0x18u},\r
+ {0x38u, 0x04u},\r
+ {0x3Au, 0x42u},\r
+ {0x3Du, 0x90u},\r
+ {0x3Eu, 0x80u},\r
+ {0x3Fu, 0x02u},\r
+ {0x58u, 0xA0u},\r
+ {0x61u, 0x80u},\r
+ {0x62u, 0x80u},\r
+ {0x63u, 0x04u},\r
+ {0x6Cu, 0x44u},\r
+ {0x6Du, 0x24u},\r
+ {0x6Fu, 0x01u},\r
+ {0x74u, 0x22u},\r
+ {0x75u, 0x20u},\r
+ {0x76u, 0x11u},\r
+ {0x81u, 0x04u},\r
+ {0x83u, 0x04u},\r
+ {0x8Au, 0x41u},\r
+ {0x8Cu, 0x80u},\r
+ {0x8Du, 0x40u},\r
+ {0x8Eu, 0x03u},\r
+ {0x90u, 0x04u},\r
+ {0x91u, 0x10u},\r
+ {0x92u, 0x20u},\r
+ {0x94u, 0x40u},\r
+ {0x95u, 0x44u},\r
+ {0x96u, 0x80u},\r
+ {0x97u, 0x24u},\r
+ {0x9Au, 0x40u},\r
+ {0x9Bu, 0x02u},\r
+ {0x9Cu, 0x07u},\r
+ {0x9Du, 0x50u},\r
+ {0x9Eu, 0x82u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA1u, 0x20u},\r
+ {0xA2u, 0x10u},\r
+ {0xA3u, 0x80u},\r
+ {0xA4u, 0x40u},\r
+ {0xA5u, 0x18u},\r
+ {0xA6u, 0xE0u},\r
+ {0xA7u, 0x09u},\r
+ {0xAAu, 0x60u},\r
+ {0xACu, 0x11u},\r
+ {0xAEu, 0x08u},\r
+ {0xB0u, 0x20u},\r
+ {0xB3u, 0x81u},\r
+ {0xB5u, 0x02u},\r
+ {0xC0u, 0x67u},\r
+ {0xC2u, 0x1Au},\r
+ {0xC4u, 0x05u},\r
+ {0xCAu, 0xFBu},\r
+ {0xCCu, 0xEBu},\r
+ {0xCEu, 0xBBu},\r
+ {0xD6u, 0x0Cu},\r
+ {0xD8u, 0x0Cu},\r
+ {0xE0u, 0x60u},\r
+ {0xE2u, 0x01u},\r
+ {0xE4u, 0x03u},\r
+ {0xE6u, 0x40u},\r
+ {0xE8u, 0x80u},\r
+ {0xEAu, 0x44u},\r
+ {0xECu, 0x04u},\r
+ {0xEEu, 0x32u},\r
+ {0x00u, 0x01u},\r
+ {0x02u, 0x02u},\r
+ {0x04u, 0x08u},\r
+ {0x05u, 0x04u},\r
+ {0x06u, 0x10u},\r
{0x07u, 0x02u},\r
- {0x09u, 0x02u},\r
- {0x0Bu, 0x01u},\r
- {0x0Du, 0x02u},\r
- {0x0Fu, 0x01u},\r
- {0x10u, 0x04u},\r
- {0x12u, 0x08u},\r
- {0x13u, 0x1Cu},\r
- {0x15u, 0x24u},\r
- {0x17u, 0x08u},\r
+ {0x08u, 0x1Bu},\r
+ {0x0Du, 0x04u},\r
+ {0x0Eu, 0x1Bu},\r
+ {0x0Fu, 0x02u},\r
+ {0x10u, 0x1Bu},\r
+ {0x15u, 0x04u},\r
+ {0x16u, 0x1Bu},\r
+ {0x17u, 0x02u},\r
+ {0x18u, 0x01u},\r
+ {0x19u, 0x04u},\r
{0x1Au, 0x02u},\r
- {0x1Bu, 0x20u},\r
- {0x1Du, 0x28u},\r
- {0x1Eu, 0x01u},\r
- {0x1Fu, 0x14u},\r
- {0x21u, 0x10u},\r
- {0x22u, 0x10u},\r
- {0x23u, 0x20u},\r
- {0x26u, 0x08u},\r
- {0x29u, 0x02u},\r
- {0x2Bu, 0x01u},\r
- {0x30u, 0x0Cu},\r
- {0x31u, 0x3Cu},\r
- {0x32u, 0x02u},\r
- {0x33u, 0x03u},\r
- {0x34u, 0x01u},\r
- {0x36u, 0x10u},\r
- {0x3Bu, 0x08u},\r
- {0x3Eu, 0x01u},\r
+ {0x1Bu, 0x03u},\r
+ {0x1Cu, 0x08u},\r
+ {0x1Du, 0x02u},\r
+ {0x1Eu, 0x10u},\r
+ {0x1Fu, 0x04u},\r
+ {0x22u, 0x04u},\r
+ {0x2Eu, 0x1Bu},\r
+ {0x2Fu, 0x08u},\r
+ {0x32u, 0x04u},\r
+ {0x33u, 0x01u},\r
+ {0x34u, 0x03u},\r
+ {0x35u, 0x08u},\r
+ {0x36u, 0x18u},\r
+ {0x37u, 0x06u},\r
+ {0x3Au, 0xA0u},\r
+ {0x3Bu, 0x80u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x96u},\r
- {0x83u, 0x69u},\r
- {0x85u, 0x0Fu},\r
- {0x87u, 0xF0u},\r
- {0x8Fu, 0xFFu},\r
- {0x90u, 0x10u},\r
- {0x92u, 0x20u},\r
- {0x96u, 0x20u},\r
- {0x97u, 0xFFu},\r
- {0x99u, 0xFFu},\r
- {0x9Au, 0x1Du},\r
- {0x9Cu, 0x28u},\r
- {0x9Du, 0x33u},\r
- {0x9Eu, 0x14u},\r
- {0x9Fu, 0xCCu},\r
- {0xA0u, 0x24u},\r
- {0xA2u, 0x08u},\r
- {0xA3u, 0xFFu},\r
- {0xA9u, 0xFFu},\r
- {0xAAu, 0x02u},\r
- {0xACu, 0x01u},\r
- {0xADu, 0x55u},\r
- {0xAEu, 0x02u},\r
- {0xAFu, 0xAAu},\r
+ {0x82u, 0x1Fu},\r
+ {0x84u, 0x27u},\r
+ {0x85u, 0x30u},\r
+ {0x86u, 0x48u},\r
+ {0x87u, 0xC0u},\r
+ {0x89u, 0x50u},\r
+ {0x8Bu, 0xA0u},\r
+ {0x8Cu, 0x01u},\r
+ {0x8Du, 0xFFu},\r
+ {0x8Eu, 0x02u},\r
+ {0x90u, 0x01u},\r
+ {0x91u, 0x90u},\r
+ {0x92u, 0x02u},\r
+ {0x93u, 0x60u},\r
+ {0x94u, 0x2Cu},\r
+ {0x95u, 0xFFu},\r
+ {0x96u, 0x53u},\r
+ {0x98u, 0x0Cu},\r
+ {0x99u, 0x03u},\r
+ {0x9Au, 0x70u},\r
+ {0x9Bu, 0x0Cu},\r
+ {0x9Cu, 0x13u},\r
+ {0x9Du, 0x05u},\r
+ {0x9Fu, 0x0Au},\r
+ {0xA2u, 0x04u},\r
+ {0xA4u, 0x08u},\r
+ {0xA7u, 0xFFu},\r
+ {0xA9u, 0x0Fu},\r
+ {0xABu, 0xF0u},\r
+ {0xACu, 0x20u},\r
+ {0xADu, 0x09u},\r
+ {0xAEu, 0x5Fu},\r
+ {0xAFu, 0x06u},\r
{0xB0u, 0x03u},\r
- {0xB3u, 0xFFu},\r
- {0xB4u, 0x3Cu},\r
- {0xBBu, 0x08u},\r
- {0xBEu, 0x01u},\r
- {0xD6u, 0x08u},\r
+ {0xB4u, 0x7Cu},\r
+ {0xB5u, 0xFFu},\r
+ {0xBAu, 0x22u},\r
+ {0xBFu, 0x10u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
- {0xDDu, 0x90u},\r
+ {0xDCu, 0x01u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x02u},\r
- {0x08u, 0x01u},\r
- {0x0Au, 0x05u},\r
- {0x0Du, 0x88u},\r
+ {0x00u, 0x04u},\r
+ {0x01u, 0x80u},\r
+ {0x02u, 0x48u},\r
+ {0x04u, 0x08u},\r
+ {0x05u, 0x40u},\r
+ {0x06u, 0x80u},\r
+ {0x09u, 0x08u},\r
+ {0x0Au, 0x86u},\r
+ {0x0Du, 0x0Au},\r
{0x0Eu, 0x08u},\r
- {0x0Fu, 0x80u},\r
- {0x12u, 0x50u},\r
- {0x14u, 0x09u},\r
- {0x15u, 0x01u},\r
- {0x18u, 0x22u},\r
- {0x19u, 0x20u},\r
- {0x1Au, 0x05u},\r
- {0x1Bu, 0x01u},\r
- {0x1Du, 0x01u},\r
+ {0x0Fu, 0x02u},\r
+ {0x11u, 0x40u},\r
+ {0x12u, 0x80u},\r
+ {0x14u, 0x60u},\r
+ {0x16u, 0x02u},\r
+ {0x1Au, 0x26u},\r
+ {0x1Bu, 0x10u},\r
+ {0x1Du, 0x02u},\r
{0x1Eu, 0x08u},\r
- {0x21u, 0x05u},\r
- {0x22u, 0x01u},\r
- {0x25u, 0x04u},\r
- {0x27u, 0x10u},\r
- {0x29u, 0x20u},\r
- {0x2Bu, 0x40u},\r
- {0x2Du, 0x02u},\r
- {0x2Fu, 0x09u},\r
- {0x31u, 0x80u},\r
- {0x32u, 0x09u},\r
- {0x33u, 0x20u},\r
- {0x36u, 0x88u},\r
- {0x37u, 0x20u},\r
- {0x38u, 0x22u},\r
- {0x39u, 0x08u},\r
- {0x3Au, 0x40u},\r
- {0x3Du, 0x08u},\r
- {0x3Fu, 0x81u},\r
- {0x59u, 0x40u},\r
- {0x5Du, 0x80u},\r
- {0x5Eu, 0x10u},\r
- {0x5Fu, 0x08u},\r
+ {0x21u, 0xA0u},\r
+ {0x22u, 0x04u},\r
+ {0x23u, 0x02u},\r
+ {0x27u, 0x08u},\r
+ {0x28u, 0x02u},\r
+ {0x2Cu, 0x01u},\r
+ {0x2Fu, 0x18u},\r
+ {0x31u, 0x90u},\r
+ {0x32u, 0x04u},\r
+ {0x34u, 0x04u},\r
+ {0x36u, 0x60u},\r
+ {0x37u, 0x01u},\r
+ {0x38u, 0x40u},\r
+ {0x3Bu, 0x04u},\r
+ {0x3Cu, 0x80u},\r
+ {0x3Du, 0x24u},\r
+ {0x4Cu, 0x04u},\r
+ {0x4Eu, 0x08u},\r
+ {0x58u, 0x10u},\r
+ {0x5Au, 0x40u},\r
+ {0x60u, 0x04u},\r
{0x62u, 0x40u},\r
- {0x66u, 0x24u},\r
- {0x67u, 0x21u},\r
- {0x79u, 0x10u},\r
- {0x7Au, 0x04u},\r
- {0x81u, 0x90u},\r
- {0x82u, 0x08u},\r
- {0x85u, 0x50u},\r
- {0x86u, 0x20u},\r
- {0x87u, 0x10u},\r
- {0x88u, 0x20u},\r
- {0x8Du, 0x09u},\r
- {0x8Fu, 0x20u},\r
- {0xC0u, 0x08u},\r
- {0xC2u, 0xFBu},\r
- {0xC4u, 0xDCu},\r
- {0xCAu, 0xB5u},\r
- {0xCCu, 0x7Fu},\r
- {0xCEu, 0xDFu},\r
- {0xD6u, 0x78u},\r
- {0xD8u, 0x78u},\r
- {0xE0u, 0x40u},\r
- {0xE2u, 0x04u},\r
- {0xE4u, 0x30u},\r
- {0x85u, 0x01u},\r
- {0x87u, 0x1Au},\r
- {0x91u, 0x32u},\r
- {0x93u, 0x01u},\r
- {0x99u, 0x06u},\r
- {0x9Fu, 0x08u},\r
- {0xA5u, 0x01u},\r
- {0xA7u, 0x2Cu},\r
- {0xB5u, 0x07u},\r
- {0xB7u, 0x38u},\r
- {0xB9u, 0x20u},\r
- {0xD4u, 0x01u},\r
+ {0x65u, 0x80u},\r
+ {0x66u, 0x80u},\r
+ {0x81u, 0x10u},\r
+ {0x83u, 0x10u},\r
+ {0x84u, 0x40u},\r
+ {0x86u, 0x10u},\r
+ {0x87u, 0x08u},\r
+ {0x88u, 0x40u},\r
+ {0x89u, 0x10u},\r
+ {0x8Au, 0x01u},\r
+ {0x8Eu, 0x04u},\r
+ {0xC0u, 0xBFu},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0xB9u},\r
+ {0xCAu, 0x78u},\r
+ {0xCCu, 0xFEu},\r
+ {0xCEu, 0x7Au},\r
+ {0xD6u, 0x0Cu},\r
+ {0xD8u, 0x0Cu},\r
+ {0xE0u, 0x80u},\r
+ {0xE2u, 0x60u},\r
+ {0x00u, 0x06u},\r
+ {0x04u, 0x02u},\r
+ {0x05u, 0x08u},\r
+ {0x06u, 0x01u},\r
+ {0x07u, 0x03u},\r
+ {0x08u, 0x01u},\r
+ {0x09u, 0x04u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Bu, 0x03u},\r
+ {0x0Fu, 0x12u},\r
+ {0x10u, 0x01u},\r
+ {0x12u, 0x02u},\r
+ {0x17u, 0x0Cu},\r
+ {0x1Fu, 0x01u},\r
+ {0x25u, 0x01u},\r
+ {0x27u, 0x02u},\r
+ {0x33u, 0x0Fu},\r
+ {0x36u, 0x07u},\r
+ {0x37u, 0x10u},\r
+ {0x38u, 0x80u},\r
+ {0x40u, 0x32u},\r
+ {0x41u, 0x05u},\r
+ {0x42u, 0x10u},\r
+ {0x44u, 0x04u},\r
+ {0x45u, 0xDEu},\r
+ {0x46u, 0xFBu},\r
+ {0x47u, 0xCBu},\r
+ {0x48u, 0x3Fu},\r
+ {0x49u, 0xFFu},\r
+ {0x4Au, 0xFFu},\r
+ {0x4Bu, 0xFFu},\r
+ {0x4Cu, 0x22u},\r
+ {0x4Eu, 0xF0u},\r
+ {0x4Fu, 0x08u},\r
+ {0x50u, 0x04u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Au, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x62u, 0xC0u},\r
+ {0x64u, 0x40u},\r
+ {0x65u, 0x01u},\r
+ {0x66u, 0x10u},\r
+ {0x67u, 0x11u},\r
+ {0x68u, 0xC0u},\r
+ {0x69u, 0x01u},\r
+ {0x6Bu, 0x11u},\r
+ {0x6Cu, 0x40u},\r
+ {0x6Du, 0x01u},\r
+ {0x6Eu, 0x40u},\r
+ {0x6Fu, 0x01u},\r
+ {0x80u, 0x1Cu},\r
+ {0x83u, 0x01u},\r
+ {0x84u, 0x30u},\r
+ {0x85u, 0x1Bu},\r
+ {0x86u, 0x0Fu},\r
+ {0x88u, 0x21u},\r
+ {0x89u, 0x04u},\r
+ {0x8Au, 0x1Eu},\r
+ {0x8Bu, 0xA8u},\r
+ {0x8Cu, 0x0Cu},\r
+ {0x8Du, 0x1Bu},\r
+ {0x8Eu, 0x10u},\r
+ {0x93u, 0x20u},\r
+ {0x94u, 0x11u},\r
+ {0x95u, 0x02u},\r
+ {0x96u, 0x22u},\r
+ {0x97u, 0x64u},\r
+ {0x98u, 0x14u},\r
+ {0x99u, 0xC4u},\r
+ {0x9Au, 0x08u},\r
+ {0x9Bu, 0x10u},\r
+ {0x9Cu, 0x1Cu},\r
+ {0x9Du, 0x04u},\r
+ {0x9Fu, 0x1Au},\r
+ {0xA0u, 0x08u},\r
+ {0xA1u, 0x1Bu},\r
+ {0xA4u, 0x10u},\r
+ {0xA6u, 0x0Cu},\r
+ {0xA8u, 0x24u},\r
+ {0xA9u, 0x1Bu},\r
+ {0xAAu, 0x10u},\r
+ {0xADu, 0x1Au},\r
+ {0xAFu, 0x01u},\r
+ {0xB1u, 0x1Eu},\r
+ {0xB2u, 0x0Fu},\r
+ {0xB3u, 0x01u},\r
+ {0xB4u, 0x30u},\r
+ {0xB6u, 0x0Fu},\r
+ {0xB7u, 0xE0u},\r
+ {0xBAu, 0x20u},\r
+ {0xBBu, 0x02u},\r
+ {0xBFu, 0x04u},\r
+ {0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDDu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x41u},\r
- {0x03u, 0x24u},\r
- {0x09u, 0x06u},\r
- {0x0Bu, 0x04u},\r
- {0x11u, 0x10u},\r
- {0x12u, 0x12u},\r
- {0x13u, 0x01u},\r
- {0x19u, 0x09u},\r
- {0x1Au, 0x40u},\r
- {0x21u, 0x04u},\r
- {0x26u, 0xA0u},\r
- {0x28u, 0x01u},\r
- {0x2Au, 0x12u},\r
- {0x2Bu, 0x20u},\r
- {0x2Fu, 0x20u},\r
- {0x32u, 0x12u},\r
- {0x33u, 0x04u},\r
- {0x36u, 0xA2u},\r
- {0x37u, 0x10u},\r
- {0x38u, 0x20u},\r
- {0x39u, 0x45u},\r
- {0x3Du, 0x08u},\r
- {0x41u, 0x08u},\r
- {0x42u, 0x41u},\r
- {0x43u, 0x20u},\r
- {0x49u, 0x06u},\r
- {0x4Au, 0x02u},\r
- {0x52u, 0x51u},\r
- {0x53u, 0x01u},\r
- {0x5Du, 0x80u},\r
- {0x63u, 0x40u},\r
- {0x68u, 0x20u},\r
- {0x69u, 0x55u},\r
- {0x6Au, 0xA4u},\r
- {0x70u, 0x40u},\r
- {0x72u, 0x02u},\r
- {0x73u, 0x01u},\r
- {0x85u, 0x02u},\r
- {0x86u, 0x05u},\r
- {0x88u, 0x10u},\r
- {0x8Au, 0xC0u},\r
- {0x90u, 0x20u},\r
- {0x93u, 0x44u},\r
- {0x94u, 0x80u},\r
- {0x95u, 0x59u},\r
- {0x96u, 0x80u},\r
- {0x97u, 0x03u},\r
- {0x98u, 0x01u},\r
- {0x99u, 0x80u},\r
- {0x9Bu, 0x04u},\r
- {0x9Cu, 0x10u},\r
- {0x9Du, 0x0Fu},\r
- {0x9Eu, 0x11u},\r
- {0x9Fu, 0x10u},\r
- {0xA1u, 0x0Cu},\r
- {0xA2u, 0x02u},\r
- {0xA3u, 0x20u},\r
- {0xA4u, 0x20u},\r
- {0xACu, 0x20u},\r
- {0xADu, 0x40u},\r
- {0xB4u, 0x10u},\r
- {0xC0u, 0x0Fu},\r
- {0xC2u, 0x0Eu},\r
- {0xC4u, 0x0Fu},\r
- {0xCAu, 0x4Fu},\r
- {0xCCu, 0xB7u},\r
- {0xCEu, 0x4Fu},\r
+ {0x00u, 0x15u},\r
+ {0x02u, 0x40u},\r
+ {0x04u, 0x14u},\r
+ {0x06u, 0x80u},\r
+ {0x07u, 0x01u},\r
+ {0x0Bu, 0x80u},\r
+ {0x0Eu, 0x25u},\r
+ {0x14u, 0x08u},\r
+ {0x15u, 0x02u},\r
+ {0x17u, 0x04u},\r
+ {0x18u, 0x01u},\r
+ {0x1Cu, 0x02u},\r
+ {0x1Du, 0x14u},\r
+ {0x1Eu, 0x20u},\r
+ {0x1Fu, 0x50u},\r
+ {0x22u, 0x44u},\r
+ {0x26u, 0x08u},\r
+ {0x27u, 0x42u},\r
+ {0x28u, 0x08u},\r
+ {0x29u, 0x14u},\r
+ {0x2Du, 0x40u},\r
+ {0x2Eu, 0x11u},\r
+ {0x30u, 0x04u},\r
+ {0x32u, 0x44u},\r
+ {0x35u, 0x04u},\r
+ {0x36u, 0x20u},\r
+ {0x37u, 0x42u},\r
+ {0x38u, 0x94u},\r
+ {0x3Cu, 0x90u},\r
+ {0x3Eu, 0x84u},\r
+ {0x3Fu, 0x01u},\r
+ {0x40u, 0x94u},\r
+ {0x41u, 0x80u},\r
+ {0x48u, 0x01u},\r
+ {0x4Au, 0x80u},\r
+ {0x4Bu, 0x05u},\r
+ {0x50u, 0x40u},\r
+ {0x51u, 0x21u},\r
+ {0x53u, 0x09u},\r
+ {0x80u, 0x80u},\r
+ {0x87u, 0x02u},\r
+ {0x88u, 0x40u},\r
+ {0x90u, 0x14u},\r
+ {0x91u, 0x40u},\r
+ {0x92u, 0x15u},\r
+ {0x94u, 0x80u},\r
+ {0x95u, 0x02u},\r
+ {0x97u, 0x26u},\r
+ {0x9Bu, 0x05u},\r
+ {0x9Cu, 0x44u},\r
+ {0x9Du, 0x14u},\r
+ {0x9Eu, 0x40u},\r
+ {0xA0u, 0x40u},\r
+ {0xA1u, 0x80u},\r
+ {0xA2u, 0x20u},\r
+ {0xA5u, 0x20u},\r
+ {0xA6u, 0x88u},\r
+ {0xA7u, 0x08u},\r
+ {0xACu, 0x04u},\r
+ {0xC0u, 0xFEu},\r
+ {0xC2u, 0xE8u},\r
+ {0xC4u, 0x70u},\r
+ {0xCAu, 0xB2u},\r
+ {0xCCu, 0xFAu},\r
+ {0xCEu, 0xFEu},\r
{0xD0u, 0x0Fu},\r
{0xD2u, 0x08u},\r
- {0xD6u, 0x10u},\r
- {0xD8u, 0x01u},\r
- {0xE2u, 0x80u},\r
- {0x01u, 0x6Cu},\r
- {0x04u, 0x92u},\r
- {0x05u, 0x71u},\r
- {0x06u, 0x64u},\r
- {0x07u, 0x82u},\r
- {0x08u, 0x71u},\r
- {0x0Au, 0x82u},\r
- {0x0Cu, 0x40u},\r
- {0x0Du, 0x2Cu},\r
- {0x0Fu, 0x40u},\r
- {0x10u, 0x12u},\r
- {0x11u, 0xC0u},\r
- {0x12u, 0xE8u},\r
- {0x13u, 0x2Fu},\r
- {0x14u, 0x02u},\r
- {0x15u, 0xA4u},\r
- {0x16u, 0x0Du},\r
- {0x17u, 0x40u},\r
- {0x18u, 0x2Du},\r
- {0x19u, 0x91u},\r
- {0x1Au, 0x40u},\r
- {0x1Bu, 0x4Eu},\r
- {0x1Cu, 0x6Du},\r
- {0x20u, 0x6Du},\r
- {0x21u, 0x6Cu},\r
- {0x24u, 0x20u},\r
- {0x25u, 0x64u},\r
- {0x27u, 0x08u},\r
- {0x28u, 0x0Du},\r
- {0x29u, 0x40u},\r
- {0x2Au, 0x60u},\r
- {0x2Bu, 0x2Cu},\r
- {0x2Cu, 0x6Du},\r
- {0x2Du, 0x08u},\r
- {0x2Fu, 0x10u},\r
- {0x31u, 0x31u},\r
- {0x32u, 0x0Fu},\r
+ {0x00u, 0xC0u},\r
+ {0x01u, 0xC6u},\r
+ {0x02u, 0x02u},\r
+ {0x04u, 0x1Fu},\r
+ {0x05u, 0xC2u},\r
+ {0x06u, 0x20u},\r
+ {0x07u, 0x04u},\r
+ {0x08u, 0x80u},\r
+ {0x09u, 0x39u},\r
+ {0x0Bu, 0x06u},\r
+ {0x0Du, 0xC6u},\r
+ {0x0Eu, 0x9Fu},\r
+ {0x11u, 0x46u},\r
+ {0x12u, 0x60u},\r
+ {0x13u, 0x80u},\r
+ {0x14u, 0x7Fu},\r
+ {0x15u, 0x77u},\r
+ {0x16u, 0x80u},\r
+ {0x17u, 0x08u},\r
+ {0x18u, 0xC0u},\r
+ {0x19u, 0x01u},\r
+ {0x1Au, 0x04u},\r
+ {0x1Bu, 0x5Eu},\r
+ {0x1Cu, 0xC0u},\r
+ {0x1Eu, 0x01u},\r
+ {0x20u, 0x90u},\r
+ {0x22u, 0x40u},\r
+ {0x24u, 0xC0u},\r
+ {0x25u, 0x42u},\r
+ {0x26u, 0x08u},\r
+ {0x29u, 0x80u},\r
+ {0x2Au, 0xFFu},\r
+ {0x2Bu, 0x46u},\r
+ {0x2Du, 0x04u},\r
+ {0x2Fu, 0x20u},\r
+ {0x30u, 0xFFu},\r
+ {0x31u, 0x08u},\r
{0x33u, 0x0Fu},\r
- {0x34u, 0xF0u},\r
- {0x35u, 0xC0u},\r
- {0x38u, 0x20u},\r
- {0x3Au, 0x08u},\r
- {0x3Bu, 0x23u},\r
+ {0x35u, 0x70u},\r
+ {0x37u, 0x80u},\r
+ {0x39u, 0x08u},\r
+ {0x3Bu, 0x30u},\r
+ {0x3Eu, 0x01u},\r
+ {0x3Fu, 0x41u},\r
+ {0x56u, 0x02u},\r
+ {0x57u, 0x28u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x04u},\r
- {0x84u, 0x0Au},\r
- {0x85u, 0x01u},\r
- {0x86u, 0x05u},\r
- {0x89u, 0x04u},\r
- {0x8Au, 0x07u},\r
- {0x8Du, 0x04u},\r
- {0x90u, 0x09u},\r
- {0x91u, 0x02u},\r
- {0x92u, 0x02u},\r
- {0x93u, 0x08u},\r
- {0x95u, 0x02u},\r
- {0x97u, 0x08u},\r
- {0x99u, 0x04u},\r
- {0x9Au, 0x10u},\r
- {0x9Fu, 0x04u},\r
- {0xA0u, 0x04u},\r
- {0xA2u, 0x08u},\r
- {0xA3u, 0x04u},\r
- {0xA5u, 0x01u},\r
- {0xA9u, 0x0Au},\r
- {0xAAu, 0x08u},\r
- {0xB0u, 0x10u},\r
- {0xB1u, 0x08u},\r
- {0xB3u, 0x04u},\r
- {0xB4u, 0x0Fu},\r
- {0xB5u, 0x01u},\r
- {0xB7u, 0x02u},\r
- {0xB9u, 0x20u},\r
- {0xBFu, 0x45u},\r
+ {0x82u, 0x70u},\r
+ {0x84u, 0x10u},\r
+ {0x85u, 0x44u},\r
+ {0x86u, 0x2Fu},\r
+ {0x87u, 0x88u},\r
+ {0x8Bu, 0x07u},\r
+ {0x8Cu, 0x20u},\r
+ {0x8Eu, 0x4Fu},\r
+ {0x8Fu, 0x80u},\r
+ {0x90u, 0x06u},\r
+ {0x92u, 0x09u},\r
+ {0x94u, 0x03u},\r
+ {0x96u, 0x0Cu},\r
+ {0x97u, 0x70u},\r
+ {0x98u, 0x40u},\r
+ {0x99u, 0x99u},\r
+ {0x9Au, 0x1Fu},\r
+ {0x9Bu, 0x22u},\r
+ {0x9Cu, 0x05u},\r
+ {0x9Eu, 0x0Au},\r
+ {0x9Fu, 0x08u},\r
+ {0xA4u, 0x0Fu},\r
+ {0xADu, 0xAAu},\r
+ {0xAFu, 0x55u},\r
+ {0xB3u, 0xF0u},\r
+ {0xB5u, 0x0Fu},\r
+ {0xB6u, 0x7Fu},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDCu, 0x01u},\r
+ {0xDCu, 0x11u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x08u},\r
- {0x01u, 0x20u},\r
- {0x04u, 0x24u},\r
- {0x05u, 0x40u},\r
- {0x06u, 0x01u},\r
- {0x0Au, 0x08u},\r
- {0x0Bu, 0x80u},\r
- {0x0Cu, 0x20u},\r
- {0x0Du, 0x02u},\r
- {0x0Eu, 0x20u},\r
- {0x0Fu, 0x01u},\r
- {0x10u, 0x88u},\r
- {0x15u, 0x51u},\r
- {0x17u, 0x04u},\r
- {0x19u, 0x20u},\r
- {0x1Bu, 0x02u},\r
- {0x1Cu, 0x04u},\r
- {0x1Du, 0x10u},\r
- {0x1Eu, 0x20u},\r
- {0x1Fu, 0x20u},\r
- {0x20u, 0x10u},\r
- {0x21u, 0x01u},\r
- {0x22u, 0x80u},\r
- {0x23u, 0x04u},\r
- {0x24u, 0x20u},\r
- {0x25u, 0x0Eu},\r
- {0x26u, 0x0Au},\r
- {0x27u, 0x04u},\r
- {0x29u, 0x1Au},\r
- {0x2Au, 0x22u},\r
- {0x2Cu, 0x20u},\r
- {0x2Du, 0x11u},\r
- {0x2Fu, 0x01u},\r
- {0x30u, 0x20u},\r
+ {0x01u, 0x80u},\r
+ {0x03u, 0x90u},\r
+ {0x04u, 0x80u},\r
+ {0x05u, 0x14u},\r
+ {0x07u, 0x40u},\r
+ {0x08u, 0x82u},\r
+ {0x09u, 0x04u},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Cu, 0x80u},\r
+ {0x0Eu, 0xA4u},\r
+ {0x11u, 0x04u},\r
+ {0x17u, 0x25u},\r
+ {0x19u, 0x40u},\r
+ {0x1Bu, 0x80u},\r
+ {0x1Eu, 0x40u},\r
+ {0x21u, 0x18u},\r
+ {0x22u, 0x10u},\r
+ {0x24u, 0x54u},\r
+ {0x25u, 0x80u},\r
+ {0x26u, 0x30u},\r
+ {0x27u, 0x2Au},\r
+ {0x29u, 0x80u},\r
+ {0x2Eu, 0x10u},\r
+ {0x2Fu, 0x11u},\r
{0x31u, 0x08u},\r
- {0x32u, 0x42u},\r
- {0x35u, 0x10u},\r
- {0x36u, 0x02u},\r
- {0x37u, 0x04u},\r
- {0x38u, 0x80u},\r
- {0x39u, 0x19u},\r
- {0x3Du, 0x48u},\r
- {0x3Fu, 0x01u},\r
- {0x40u, 0x80u},\r
- {0x41u, 0x01u},\r
- {0x84u, 0x01u},\r
- {0x87u, 0x04u},\r
- {0x8Eu, 0x02u},\r
- {0x92u, 0x08u},\r
- {0x93u, 0xC0u},\r
+ {0x32u, 0x40u},\r
+ {0x33u, 0x10u},\r
+ {0x35u, 0x04u},\r
+ {0x36u, 0x20u},\r
+ {0x37u, 0x01u},\r
+ {0x39u, 0x20u},\r
+ {0x3Bu, 0x48u},\r
+ {0x3Cu, 0x90u},\r
+ {0x3Eu, 0x05u},\r
+ {0x67u, 0x10u},\r
+ {0x6Du, 0x42u},\r
+ {0x6Eu, 0x15u},\r
+ {0x6Fu, 0x45u},\r
+ {0x74u, 0xC0u},\r
+ {0x80u, 0x02u},\r
+ {0x89u, 0x10u},\r
+ {0x91u, 0x04u},\r
+ {0x92u, 0x80u},\r
+ {0x93u, 0x58u},\r
+ {0x94u, 0x50u},\r
+ {0x95u, 0x02u},\r
+ {0x96u, 0x64u},\r
+ {0x97u, 0x24u},\r
+ {0x98u, 0x80u},\r
{0x99u, 0x80u},\r
- {0x9Cu, 0xB0u},\r
- {0x9Du, 0x25u},\r
- {0x9Eu, 0x30u},\r
- {0x9Fu, 0x10u},\r
- {0xA0u, 0x8Cu},\r
- {0xA5u, 0x02u},\r
- {0xA6u, 0x8Au},\r
- {0xA7u, 0x02u},\r
- {0xA8u, 0x04u},\r
+ {0x9Bu, 0x10u},\r
+ {0x9Cu, 0x44u},\r
+ {0x9Du, 0x44u},\r
+ {0x9Eu, 0x40u},\r
+ {0x9Fu, 0x0Bu},\r
+ {0xA0u, 0x04u},\r
+ {0xA1u, 0x04u},\r
+ {0xA2u, 0x40u},\r
+ {0xA4u, 0x40u},\r
+ {0xA5u, 0x29u},\r
+ {0xA6u, 0xA8u},\r
+ {0xA7u, 0x08u},\r
+ {0xA9u, 0x40u},\r
{0xAAu, 0x04u},\r
- {0xABu, 0x0Du},\r
- {0xAEu, 0x40u},\r
- {0xB0u, 0x43u},\r
- {0xB2u, 0x04u},\r
- {0xB5u, 0x40u},\r
- {0xB6u, 0x40u},\r
- {0xB7u, 0x40u},\r
- {0xC0u, 0xE6u},\r
- {0xC2u, 0xFAu},\r
- {0xC4u, 0xFAu},\r
- {0xCAu, 0xF7u},\r
- {0xCCu, 0xEFu},\r
- {0xCEu, 0xDFu},\r
- {0xE8u, 0x04u},\r
- {0xEAu, 0x89u},\r
+ {0xACu, 0x10u},\r
+ {0xADu, 0x80u},\r
+ {0xB1u, 0x10u},\r
+ {0xB4u, 0x40u},\r
+ {0xB5u, 0x04u},\r
+ {0xB7u, 0x01u},\r
+ {0xC0u, 0xFDu},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0x74u},\r
+ {0xCAu, 0x78u},\r
+ {0xCCu, 0xEEu},\r
+ {0xCEu, 0xFEu},\r
+ {0xD8u, 0x40u},\r
+ {0xE2u, 0x08u},\r
+ {0xE6u, 0x01u},\r
+ {0xE8u, 0x01u},\r
+ {0xEAu, 0x22u},\r
{0xECu, 0x04u},\r
+ {0x39u, 0x20u},\r
+ {0x3Fu, 0x10u},\r
+ {0x59u, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x27u, 0x08u},\r
+ {0x81u, 0x20u},\r
+ {0x87u, 0x08u},\r
+ {0x88u, 0x01u},\r
+ {0x96u, 0x20u},\r
+ {0x99u, 0x20u},\r
+ {0x9Cu, 0x01u},\r
+ {0xA8u, 0x41u},\r
+ {0xA9u, 0x40u},\r
+ {0xADu, 0x08u},\r
+ {0xB0u, 0x20u},\r
+ {0xB2u, 0x02u},\r
+ {0xB7u, 0x42u},\r
+ {0xE4u, 0x20u},\r
+ {0xEAu, 0x22u},\r
+ {0xECu, 0x20u},\r
{0xEEu, 0x48u},\r
- {0x82u, 0x10u},\r
- {0x8Fu, 0x01u},\r
- {0x92u, 0x20u},\r
- {0x97u, 0x02u},\r
- {0x9Eu, 0x28u},\r
- {0xA8u, 0x90u},\r
- {0xAAu, 0x04u},\r
- {0xABu, 0x04u},\r
- {0xACu, 0x02u},\r
- {0xB0u, 0x80u},\r
- {0xB2u, 0x14u},\r
- {0xB4u, 0x06u},\r
- {0xB6u, 0x41u},\r
- {0xE0u, 0x40u},\r
- {0xE4u, 0x04u},\r
- {0xEAu, 0x50u},\r
- {0xECu, 0xA0u},\r
- {0xEEu, 0x09u},\r
- {0x8Au, 0x20u},\r
- {0x9Eu, 0x20u},\r
- {0xB6u, 0x08u},\r
- {0xE2u, 0x20u},\r
- {0xE4u, 0x80u},\r
- {0xE8u, 0x10u},\r
- {0x05u, 0x40u},\r
- {0x0Eu, 0x08u},\r
- {0x13u, 0x20u},\r
+ {0xB6u, 0x10u},\r
+ {0xE2u, 0x80u},\r
+ {0x04u, 0x40u},\r
+ {0x0Eu, 0x02u},\r
+ {0x10u, 0x04u},\r
{0x16u, 0x80u},\r
- {0x17u, 0x40u},\r
- {0x30u, 0x08u},\r
- {0x36u, 0x80u},\r
- {0x37u, 0x01u},\r
+ {0x17u, 0x20u},\r
+ {0x32u, 0x01u},\r
+ {0x36u, 0x88u},\r
+ {0x38u, 0x01u},\r
{0x3Au, 0x80u},\r
- {0x3Bu, 0x08u},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x20u},\r
- {0x41u, 0x20u},\r
- {0x5Eu, 0x04u},\r
- {0x85u, 0x40u},\r
- {0x87u, 0x01u},\r
- {0x8Eu, 0x40u},\r
+ {0x3Cu, 0x04u},\r
+ {0x3Du, 0x40u},\r
+ {0x40u, 0x08u},\r
+ {0x44u, 0x04u},\r
+ {0x45u, 0x20u},\r
+ {0x66u, 0x10u},\r
+ {0x81u, 0x40u},\r
+ {0x8Cu, 0x05u},\r
+ {0x8Fu, 0x01u},\r
{0xC0u, 0x80u},\r
{0xC2u, 0x80u},\r
{0xC4u, 0xE0u},\r
{0xCCu, 0xE0u},\r
{0xCEu, 0xF0u},\r
{0xD0u, 0x10u},\r
- {0xD6u, 0x80u},\r
- {0xE2u, 0x40u},\r
- {0xE4u, 0x10u},\r
- {0x30u, 0x22u},\r
- {0x34u, 0x08u},\r
- {0x37u, 0x40u},\r
+ {0xD8u, 0x80u},\r
+ {0xE6u, 0x20u},\r
+ {0x31u, 0x20u},\r
+ {0x33u, 0x01u},\r
+ {0x34u, 0x02u},\r
+ {0x37u, 0x20u},\r
{0x3Bu, 0x40u},\r
- {0x50u, 0x01u},\r
- {0x5Cu, 0x02u},\r
- {0x5Eu, 0x40u},\r
- {0x68u, 0x20u},\r
- {0x6Bu, 0x20u},\r
- {0x84u, 0x08u},\r
- {0x87u, 0x40u},\r
- {0x88u, 0x08u},\r
- {0x92u, 0x40u},\r
- {0x96u, 0x04u},\r
- {0x9Bu, 0x60u},\r
- {0xA2u, 0x04u},\r
- {0xA4u, 0x08u},\r
- {0xA5u, 0x20u},\r
- {0xA6u, 0x80u},\r
- {0xB2u, 0x01u},\r
- {0xB3u, 0x04u},\r
- {0xB7u, 0x10u},\r
+ {0x53u, 0x11u},\r
+ {0x67u, 0x08u},\r
+ {0x82u, 0x01u},\r
+ {0x90u, 0x40u},\r
+ {0x93u, 0x02u},\r
+ {0x96u, 0x02u},\r
+ {0x9Bu, 0x20u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Eu, 0x10u},\r
+ {0xA1u, 0x20u},\r
+ {0xA2u, 0x01u},\r
+ {0xA6u, 0x88u},\r
{0xCCu, 0xF0u},\r
{0xCEu, 0x10u},\r
- {0xD4u, 0x80u},\r
- {0xD6u, 0xA0u},\r
- {0xE6u, 0x50u},\r
+ {0xD4u, 0xA0u},\r
+ {0xD8u, 0x80u},\r
+ {0xE4u, 0x80u},\r
{0x12u, 0x80u},\r
{0x33u, 0x80u},\r
- {0x80u, 0x02u},\r
- {0x86u, 0x04u},\r
- {0x96u, 0x04u},\r
- {0x9Cu, 0x02u},\r
- {0xA2u, 0x04u},\r
- {0xA4u, 0x02u},\r
- {0xA5u, 0x20u},\r
- {0xA6u, 0x80u},\r
- {0xA8u, 0x01u},\r
+ {0x87u, 0x80u},\r
+ {0x8Au, 0x08u},\r
+ {0x8Cu, 0x02u},\r
+ {0x90u, 0x40u},\r
+ {0x96u, 0x02u},\r
+ {0x97u, 0x40u},\r
+ {0x9Cu, 0x0Au},\r
+ {0x9Fu, 0x01u},\r
+ {0xA6u, 0x88u},\r
+ {0xAFu, 0x14u},\r
+ {0xB2u, 0x10u},\r
{0xC4u, 0x10u},\r
{0xCCu, 0x10u},\r
- {0xE2u, 0x60u},\r
- {0xEEu, 0x20u},\r
- {0x63u, 0x20u},\r
- {0xA5u, 0x20u},\r
- {0xA7u, 0x80u},\r
- {0xA8u, 0x02u},\r
- {0xAAu, 0x04u},\r
- {0xD8u, 0x40u},\r
+ {0xE6u, 0x10u},\r
+ {0xEEu, 0x50u},\r
+ {0x80u, 0x08u},\r
+ {0x97u, 0x40u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA8u, 0x40u},\r
+ {0xAEu, 0x01u},\r
+ {0xE6u, 0x20u},\r
{0xECu, 0x20u},\r
- {0xEEu, 0x80u},\r
- {0x03u, 0x08u},\r
- {0x04u, 0x10u},\r
- {0x09u, 0x20u},\r
+ {0xEEu, 0x40u},\r
+ {0x00u, 0x10u},\r
+ {0x04u, 0x40u},\r
+ {0x08u, 0x80u},\r
{0x0Fu, 0x02u},\r
- {0x10u, 0x80u},\r
- {0x16u, 0x80u},\r
- {0x62u, 0x08u},\r
- {0x66u, 0x02u},\r
- {0x81u, 0x01u},\r
- {0x8Eu, 0x01u},\r
+ {0x13u, 0x01u},\r
+ {0x16u, 0x20u},\r
+ {0x62u, 0x80u},\r
+ {0x63u, 0x08u},\r
{0xC0u, 0x03u},\r
{0xC2u, 0x03u},\r
{0xC4u, 0x0Cu},\r
- {0xD8u, 0x03u},\r
- {0xE4u, 0x02u},\r
- {0x03u, 0x40u},\r
- {0x05u, 0x01u},\r
- {0x0Bu, 0x10u},\r
- {0x0Fu, 0x80u},\r
- {0x55u, 0x10u},\r
- {0x5Eu, 0x80u},\r
- {0x62u, 0x01u},\r
- {0x65u, 0x80u},\r
- {0x84u, 0x80u},\r
- {0x86u, 0x10u},\r
- {0x8Au, 0x08u},\r
- {0x8Bu, 0x01u},\r
- {0x8Cu, 0x80u},\r
+ {0xD6u, 0x02u},\r
+ {0xD8u, 0x02u},\r
+ {0x03u, 0x20u},\r
+ {0x04u, 0x08u},\r
+ {0x0Bu, 0x40u},\r
+ {0x0Eu, 0x80u},\r
+ {0x56u, 0x40u},\r
+ {0x5Bu, 0x40u},\r
+ {0x5Fu, 0x02u},\r
+ {0x66u, 0x08u},\r
+ {0x83u, 0x03u},\r
+ {0x86u, 0x08u},\r
+ {0x8Au, 0x40u},\r
+ {0x8Cu, 0x10u},\r
{0x90u, 0x10u},\r
- {0x9Au, 0x01u},\r
- {0x9Du, 0x01u},\r
- {0xA0u, 0x80u},\r
- {0xA3u, 0x09u},\r
- {0xA6u, 0x08u},\r
- {0xAAu, 0x80u},\r
- {0xAEu, 0x02u},\r
- {0xB5u, 0x20u},\r
+ {0x93u, 0x01u},\r
+ {0xA3u, 0x01u},\r
+ {0xA6u, 0x80u},\r
+ {0xAAu, 0x20u},\r
+ {0xABu, 0x04u},\r
+ {0xACu, 0x80u},\r
+ {0xB4u, 0x40u},\r
{0xC0u, 0x0Cu},\r
{0xC2u, 0x0Cu},\r
- {0xD4u, 0x02u},\r
- {0xD6u, 0x05u},\r
- {0xD8u, 0x02u},\r
- {0xE2u, 0x01u},\r
+ {0xD4u, 0x03u},\r
+ {0xD6u, 0x01u},\r
+ {0xD8u, 0x01u},\r
+ {0xE2u, 0x08u},\r
{0xE4u, 0x01u},\r
- {0xE6u, 0x02u},\r
- {0xEEu, 0x02u},\r
- {0x57u, 0x04u},\r
- {0x82u, 0x40u},\r
- {0x83u, 0x08u},\r
- {0x8Du, 0x80u},\r
- {0x90u, 0x10u},\r
- {0x9Bu, 0x40u},\r
- {0x9Cu, 0x80u},\r
- {0x9Du, 0x80u},\r
- {0xA3u, 0x08u},\r
- {0xA5u, 0x10u},\r
- {0xA6u, 0x50u},\r
- {0xAFu, 0x10u},\r
- {0xB7u, 0x40u},\r
+ {0xEAu, 0x02u},\r
+ {0x56u, 0x80u},\r
+ {0x84u, 0x40u},\r
+ {0x87u, 0x42u},\r
+ {0x8Fu, 0x10u},\r
+ {0x90u, 0x08u},\r
+ {0x93u, 0x40u},\r
+ {0x9Fu, 0x40u},\r
+ {0xA2u, 0x40u},\r
+ {0xA3u, 0x01u},\r
+ {0xA6u, 0x80u},\r
+ {0xAFu, 0x20u},\r
{0xD4u, 0x02u},\r
- {0xE4u, 0x02u},\r
- {0xEEu, 0x02u},\r
+ {0xE2u, 0x08u},\r
{0x08u, 0x80u},\r
- {0x0Au, 0x40u},\r
- {0x0Eu, 0x20u},\r
- {0x0Fu, 0x02u},\r
- {0x90u, 0x10u},\r
- {0x96u, 0x40u},\r
- {0x9Cu, 0x80u},\r
- {0xA6u, 0x10u},\r
- {0xA9u, 0x10u},\r
- {0xABu, 0x04u},\r
- {0xAEu, 0x40u},\r
- {0xB7u, 0x40u},\r
+ {0x09u, 0x08u},\r
+ {0x0Cu, 0x40u},\r
+ {0x0Fu, 0x20u},\r
+ {0x87u, 0x80u},\r
+ {0x8Eu, 0x80u},\r
+ {0x8Fu, 0x40u},\r
+ {0x90u, 0x08u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Fu, 0x40u},\r
+ {0xA3u, 0x03u},\r
+ {0xA6u, 0x80u},\r
+ {0xA7u, 0x10u},\r
+ {0xAEu, 0xC0u},\r
{0xC2u, 0x0Fu},\r
- {0xEAu, 0x08u},\r
- {0xA3u, 0x20u},\r
- {0xABu, 0x10u},\r
- {0xAFu, 0x80u},\r
- {0xB3u, 0x20u},\r
- {0xB5u, 0x20u},\r
- {0xEEu, 0x90u},\r
- {0x06u, 0x40u},\r
- {0x53u, 0x04u},\r
- {0x57u, 0x20u},\r
- {0x86u, 0x40u},\r
- {0x8Bu, 0x04u},\r
- {0xA3u, 0x20u},\r
+ {0xE0u, 0x0Au},\r
+ {0x67u, 0x80u},\r
+ {0x87u, 0x40u},\r
+ {0xAFu, 0x01u},\r
+ {0xB3u, 0x40u},\r
+ {0xD8u, 0x80u},\r
+ {0xE2u, 0x10u},\r
+ {0xEAu, 0x40u},\r
+ {0x05u, 0x04u},\r
+ {0x51u, 0x80u},\r
+ {0x57u, 0x08u},\r
+ {0x81u, 0x04u},\r
+ {0x87u, 0x08u},\r
+ {0xA1u, 0x80u},\r
+ {0xADu, 0x80u},\r
{0xC0u, 0x20u},\r
{0xD4u, 0x60u},\r
- {0xE0u, 0x10u},\r
- {0x83u, 0x01u},\r
- {0x93u, 0x08u},\r
- {0x9Eu, 0x02u},\r
- {0xA8u, 0x10u},\r
+ {0xE4u, 0x80u},\r
+ {0xE6u, 0x40u},\r
+ {0xEEu, 0x40u},\r
+ {0xA3u, 0x82u},\r
+ {0xADu, 0x08u},\r
{0xAFu, 0x01u},\r
- {0xB3u, 0x04u},\r
- {0xB6u, 0x02u},\r
- {0xE8u, 0x01u},\r
- {0xEAu, 0x02u},\r
- {0x03u, 0x08u},\r
- {0x06u, 0x02u},\r
- {0x53u, 0x05u},\r
- {0x8Bu, 0x08u},\r
- {0x93u, 0x0Au},\r
- {0x9Eu, 0x02u},\r
+ {0xB0u, 0x80u},\r
+ {0xB4u, 0x04u},\r
+ {0xEAu, 0x0Cu},\r
+ {0x01u, 0x10u},\r
+ {0x04u, 0x40u},\r
+ {0x53u, 0x82u},\r
+ {0x89u, 0x10u},\r
+ {0x94u, 0x40u},\r
+ {0xA3u, 0x82u},\r
+ {0xB4u, 0x40u},\r
{0xC0u, 0x03u},\r
{0xD4u, 0x05u},\r
- {0xE2u, 0x04u},\r
+ {0xE2u, 0x01u},\r
+ {0xEAu, 0x02u},\r
{0x10u, 0x03u},\r
{0x1Au, 0x03u},\r
{0x00u, 0xFDu},\r
static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
/* address, size */\r
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
- {(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
{(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},\r
};\r
\r
- /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */\r
- static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {\r
- 0x41u, 0xC0u, 0x00u, 0x02u, 0x08u, 0xC0u, 0x21u, 0x04u, 0x01u, 0x1Fu, 0x00u, 0x20u, 0x01u, 0x90u, 0x40u, 0x40u, \r
- 0x41u, 0x7Fu, 0x00u, 0x80u, 0x07u, 0x80u, 0x18u, 0x00u, 0x04u, 0xC0u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, \r
- 0x41u, 0xC0u, 0x00u, 0x01u, 0x10u, 0x00u, 0x00u, 0xFFu, 0x40u, 0x00u, 0x00u, 0x9Fu, 0x22u, 0x00u, 0x08u, 0x60u, \r
- 0x40u, 0x00u, 0x3Fu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x05u, 0x04u, \r
- 0x25u, 0x03u, 0x40u, 0x00u, 0x01u, 0xDEu, 0xBFu, 0xC0u, 0x2Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x2Cu, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, \r
- 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
-\r
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u};\r
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u},\r
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},\r
};\r
\r
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DM0), (const void CYCODE *)(BS_IOPINS0_7_VAL), 8u);\r
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DM0 + 0x00000009u), (const void CYCODE *)(BS_IOPINS1_7_VAL), 5u);\r
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u);\r
+ CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT1_DM0), (const void CYCODE *)(BS_IOPINS0_1_VAL), 8u);\r
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u);\r
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DR), (const void CYCODE *)(BS_IOPINS0_3_VAL), 10u);\r
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u);\r
/*******************************************************************************\r
* File Name: cyfitter_cfg.h\r
* \r
-* PSoC Creator 3.3\r
+* PSoC Creator 4.0 Update 1\r
*\r
* Description:\r
* This file provides basic startup and mux configration settings\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
.set EXTLED__SLW, CYREG_PRT0_SLW\r
\r
/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB08_MSK\r
-.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB08_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB04_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB04_ST\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1\r
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0\r
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
.set SDCard_BSPIM_TxStsReg__2__POS, 2\r
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08\r
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
-.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB06_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB06_ST\r
\r
/* SD_SCK */\r
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK\r
\r
/* SCSI_Out_Ctl */\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK\r
\r
/* SCSI_Out_DBx */\r
.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG\r
.set scsiTarget_StatusReg__0__POS, 0\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__2__POS, 2\r
.set scsiTarget_StatusReg__3__MASK, 0x08\r
.set scsiTarget_StatusReg__4__MASK, 0x10\r
.set scsiTarget_StatusReg__4__POS, 4\r
.set scsiTarget_StatusReg__MASK, 0x1F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST\r
\r
/* Debug_Timer_Interrupt */\r
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST\r
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST\r
\r
/* SCSI_CTL_PHASE */\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK\r
\r
/* SCSI_Parity_Error */\r
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B1_UDB05_MSK\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B1_UDB05_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB03_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB03_ST\r
\r
/* Miscellaneous */\r
.set BCLK__BUS_CLK__HZ, 50000000\r
.set BCLK__BUS_CLK__KHZ, 50000\r
.set BCLK__BUS_CLK__MHZ, 50\r
.set CYDEV_CHIP_DIE_LEOPARD, 1\r
-.set CYDEV_CHIP_DIE_PANTHER, 18\r
-.set CYDEV_CHIP_DIE_PSOC4A, 10\r
-.set CYDEV_CHIP_DIE_PSOC5LP, 17\r
+.set CYDEV_CHIP_DIE_PSOC4A, 12\r
+.set CYDEV_CHIP_DIE_PSOC5LP, 19\r
+.set CYDEV_CHIP_DIE_PSOC5TM, 20\r
.set CYDEV_CHIP_DIE_TMA4, 2\r
.set CYDEV_CHIP_DIE_UNKNOWN, 0\r
+.set CYDEV_CHIP_FAMILY_FM0P, 4\r
+.set CYDEV_CHIP_FAMILY_FM3, 5\r
+.set CYDEV_CHIP_FAMILY_FM4, 6\r
.set CYDEV_CHIP_FAMILY_PSOC3, 1\r
.set CYDEV_CHIP_FAMILY_PSOC4, 2\r
.set CYDEV_CHIP_FAMILY_PSOC5, 3\r
.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5\r
.set CYDEV_CHIP_JTAG_ID, 0x2E133069\r
.set CYDEV_CHIP_MEMBER_3A, 1\r
-.set CYDEV_CHIP_MEMBER_4A, 10\r
-.set CYDEV_CHIP_MEMBER_4C, 15\r
-.set CYDEV_CHIP_MEMBER_4D, 6\r
+.set CYDEV_CHIP_MEMBER_4A, 12\r
+.set CYDEV_CHIP_MEMBER_4C, 18\r
+.set CYDEV_CHIP_MEMBER_4D, 8\r
.set CYDEV_CHIP_MEMBER_4E, 4\r
-.set CYDEV_CHIP_MEMBER_4F, 11\r
+.set CYDEV_CHIP_MEMBER_4F, 13\r
.set CYDEV_CHIP_MEMBER_4G, 2\r
-.set CYDEV_CHIP_MEMBER_4H, 9\r
-.set CYDEV_CHIP_MEMBER_4I, 14\r
-.set CYDEV_CHIP_MEMBER_4J, 7\r
-.set CYDEV_CHIP_MEMBER_4K, 8\r
-.set CYDEV_CHIP_MEMBER_4L, 13\r
-.set CYDEV_CHIP_MEMBER_4M, 12\r
-.set CYDEV_CHIP_MEMBER_4N, 5\r
+.set CYDEV_CHIP_MEMBER_4H, 11\r
+.set CYDEV_CHIP_MEMBER_4I, 17\r
+.set CYDEV_CHIP_MEMBER_4J, 9\r
+.set CYDEV_CHIP_MEMBER_4K, 10\r
+.set CYDEV_CHIP_MEMBER_4L, 16\r
+.set CYDEV_CHIP_MEMBER_4M, 15\r
+.set CYDEV_CHIP_MEMBER_4N, 6\r
+.set CYDEV_CHIP_MEMBER_4O, 5\r
+.set CYDEV_CHIP_MEMBER_4P, 14\r
+.set CYDEV_CHIP_MEMBER_4Q, 7\r
.set CYDEV_CHIP_MEMBER_4U, 3\r
-.set CYDEV_CHIP_MEMBER_5A, 17\r
-.set CYDEV_CHIP_MEMBER_5B, 16\r
+.set CYDEV_CHIP_MEMBER_5A, 20\r
+.set CYDEV_CHIP_MEMBER_5B, 19\r
+.set CYDEV_CHIP_MEMBER_FM3, 24\r
+.set CYDEV_CHIP_MEMBER_FM4, 25\r
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 21\r
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 22\r
+.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 23\r
.set CYDEV_CHIP_MEMBER_UNKNOWN, 0\r
.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B\r
.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED\r
.set CYDEV_CHIP_REV_LEOPARD_ES2, 1\r
.set CYDEV_CHIP_REV_LEOPARD_ES3, 3\r
.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3\r
-.set CYDEV_CHIP_REV_PANTHER_ES0, 0\r
-.set CYDEV_CHIP_REV_PANTHER_ES1, 1\r
-.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1\r
.set CYDEV_CHIP_REV_PSOC4A_ES0, 17\r
.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17\r
.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0\r
.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0\r
+.set CYDEV_CHIP_REV_PSOC5TM_ES0, 0\r
+.set CYDEV_CHIP_REV_PSOC5TM_ES1, 1\r
+.set CYDEV_CHIP_REV_PSOC5TM_PRODUCTION, 1\r
.set CYDEV_CHIP_REV_TMA4_ES, 17\r
.set CYDEV_CHIP_REV_TMA4_ES2, 33\r
.set CYDEV_CHIP_REV_TMA4_PRODUCTION, 17\r
.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_4N_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_5A_ES0, 0\r
.set CYDEV_CHIP_REVISION_5A_ES1, 1\r
.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1\r
.set CYDEV_CHIP_REVISION_5B_ES0, 0\r
.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION\r
.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED\r
.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1\r
EXTLED__SLW EQU CYREG_PRT0_SLW\r
\r
/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
-SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
\r
/* SD_SCK */\r
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
\r
/* SCSI_Out_Ctl */\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
\r
/* SCSI_Out_DBx */\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
\r
/* Debug_Timer_Interrupt */\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
\r
/* SCSI_CTL_PHASE */\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
\r
/* SCSI_Parity_Error */\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB05_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB05_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB03_MSK\r
+SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB03_ST\r
\r
/* Miscellaneous */\r
BCLK__BUS_CLK__HZ EQU 50000000\r
BCLK__BUS_CLK__KHZ EQU 50000\r
BCLK__BUS_CLK__MHZ EQU 50\r
CYDEV_CHIP_DIE_LEOPARD EQU 1\r
-CYDEV_CHIP_DIE_PANTHER EQU 18\r
-CYDEV_CHIP_DIE_PSOC4A EQU 10\r
-CYDEV_CHIP_DIE_PSOC5LP EQU 17\r
+CYDEV_CHIP_DIE_PSOC4A EQU 12\r
+CYDEV_CHIP_DIE_PSOC5LP EQU 19\r
+CYDEV_CHIP_DIE_PSOC5TM EQU 20\r
CYDEV_CHIP_DIE_TMA4 EQU 2\r
CYDEV_CHIP_DIE_UNKNOWN EQU 0\r
+CYDEV_CHIP_FAMILY_FM0P EQU 4\r
+CYDEV_CHIP_FAMILY_FM3 EQU 5\r
+CYDEV_CHIP_FAMILY_FM4 EQU 6\r
CYDEV_CHIP_FAMILY_PSOC3 EQU 1\r
CYDEV_CHIP_FAMILY_PSOC4 EQU 2\r
CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
CYDEV_CHIP_JTAG_ID EQU 0x2E133069\r
CYDEV_CHIP_MEMBER_3A EQU 1\r
-CYDEV_CHIP_MEMBER_4A EQU 10\r
-CYDEV_CHIP_MEMBER_4C EQU 15\r
-CYDEV_CHIP_MEMBER_4D EQU 6\r
+CYDEV_CHIP_MEMBER_4A EQU 12\r
+CYDEV_CHIP_MEMBER_4C EQU 18\r
+CYDEV_CHIP_MEMBER_4D EQU 8\r
CYDEV_CHIP_MEMBER_4E EQU 4\r
-CYDEV_CHIP_MEMBER_4F EQU 11\r
+CYDEV_CHIP_MEMBER_4F EQU 13\r
CYDEV_CHIP_MEMBER_4G EQU 2\r
-CYDEV_CHIP_MEMBER_4H EQU 9\r
-CYDEV_CHIP_MEMBER_4I EQU 14\r
-CYDEV_CHIP_MEMBER_4J EQU 7\r
-CYDEV_CHIP_MEMBER_4K EQU 8\r
-CYDEV_CHIP_MEMBER_4L EQU 13\r
-CYDEV_CHIP_MEMBER_4M EQU 12\r
-CYDEV_CHIP_MEMBER_4N EQU 5\r
+CYDEV_CHIP_MEMBER_4H EQU 11\r
+CYDEV_CHIP_MEMBER_4I EQU 17\r
+CYDEV_CHIP_MEMBER_4J EQU 9\r
+CYDEV_CHIP_MEMBER_4K EQU 10\r
+CYDEV_CHIP_MEMBER_4L EQU 16\r
+CYDEV_CHIP_MEMBER_4M EQU 15\r
+CYDEV_CHIP_MEMBER_4N EQU 6\r
+CYDEV_CHIP_MEMBER_4O EQU 5\r
+CYDEV_CHIP_MEMBER_4P EQU 14\r
+CYDEV_CHIP_MEMBER_4Q EQU 7\r
CYDEV_CHIP_MEMBER_4U EQU 3\r
-CYDEV_CHIP_MEMBER_5A EQU 17\r
-CYDEV_CHIP_MEMBER_5B EQU 16\r
+CYDEV_CHIP_MEMBER_5A EQU 20\r
+CYDEV_CHIP_MEMBER_5B EQU 19\r
+CYDEV_CHIP_MEMBER_FM3 EQU 24\r
+CYDEV_CHIP_MEMBER_FM4 EQU 25\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23\r
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED\r
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1\r
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3\r
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3\r
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0\r
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1\r
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1\r
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17\r
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17\r
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0\r
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0\r
+CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0\r
+CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1\r
+CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1\r
CYDEV_CHIP_REV_TMA4_ES EQU 17\r
CYDEV_CHIP_REV_TMA4_ES2 EQU 33\r
CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17\r
CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
CYDEV_CHIP_REVISION_5B_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION\r
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED\r
CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1\r
EXTLED__SLW EQU CYREG_PRT0_SLW\r
\r
; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
-SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
\r
; SD_SCK\r
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
\r
; SCSI_Out_Ctl\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
\r
; SCSI_Out_DBx\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
\r
; Debug_Timer_Interrupt\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
\r
; SCSI_CTL_PHASE\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
\r
; SCSI_Glitch_Ctl\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
\r
; SCSI_Parity_Error\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB05_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB05_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB03_MSK\r
+SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB03_ST\r
\r
; Miscellaneous\r
BCLK__BUS_CLK__HZ EQU 50000000\r
BCLK__BUS_CLK__KHZ EQU 50000\r
BCLK__BUS_CLK__MHZ EQU 50\r
CYDEV_CHIP_DIE_LEOPARD EQU 1\r
-CYDEV_CHIP_DIE_PANTHER EQU 18\r
-CYDEV_CHIP_DIE_PSOC4A EQU 10\r
-CYDEV_CHIP_DIE_PSOC5LP EQU 17\r
+CYDEV_CHIP_DIE_PSOC4A EQU 12\r
+CYDEV_CHIP_DIE_PSOC5LP EQU 19\r
+CYDEV_CHIP_DIE_PSOC5TM EQU 20\r
CYDEV_CHIP_DIE_TMA4 EQU 2\r
CYDEV_CHIP_DIE_UNKNOWN EQU 0\r
+CYDEV_CHIP_FAMILY_FM0P EQU 4\r
+CYDEV_CHIP_FAMILY_FM3 EQU 5\r
+CYDEV_CHIP_FAMILY_FM4 EQU 6\r
CYDEV_CHIP_FAMILY_PSOC3 EQU 1\r
CYDEV_CHIP_FAMILY_PSOC4 EQU 2\r
CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
CYDEV_CHIP_JTAG_ID EQU 0x2E133069\r
CYDEV_CHIP_MEMBER_3A EQU 1\r
-CYDEV_CHIP_MEMBER_4A EQU 10\r
-CYDEV_CHIP_MEMBER_4C EQU 15\r
-CYDEV_CHIP_MEMBER_4D EQU 6\r
+CYDEV_CHIP_MEMBER_4A EQU 12\r
+CYDEV_CHIP_MEMBER_4C EQU 18\r
+CYDEV_CHIP_MEMBER_4D EQU 8\r
CYDEV_CHIP_MEMBER_4E EQU 4\r
-CYDEV_CHIP_MEMBER_4F EQU 11\r
+CYDEV_CHIP_MEMBER_4F EQU 13\r
CYDEV_CHIP_MEMBER_4G EQU 2\r
-CYDEV_CHIP_MEMBER_4H EQU 9\r
-CYDEV_CHIP_MEMBER_4I EQU 14\r
-CYDEV_CHIP_MEMBER_4J EQU 7\r
-CYDEV_CHIP_MEMBER_4K EQU 8\r
-CYDEV_CHIP_MEMBER_4L EQU 13\r
-CYDEV_CHIP_MEMBER_4M EQU 12\r
-CYDEV_CHIP_MEMBER_4N EQU 5\r
+CYDEV_CHIP_MEMBER_4H EQU 11\r
+CYDEV_CHIP_MEMBER_4I EQU 17\r
+CYDEV_CHIP_MEMBER_4J EQU 9\r
+CYDEV_CHIP_MEMBER_4K EQU 10\r
+CYDEV_CHIP_MEMBER_4L EQU 16\r
+CYDEV_CHIP_MEMBER_4M EQU 15\r
+CYDEV_CHIP_MEMBER_4N EQU 6\r
+CYDEV_CHIP_MEMBER_4O EQU 5\r
+CYDEV_CHIP_MEMBER_4P EQU 14\r
+CYDEV_CHIP_MEMBER_4Q EQU 7\r
CYDEV_CHIP_MEMBER_4U EQU 3\r
-CYDEV_CHIP_MEMBER_5A EQU 17\r
-CYDEV_CHIP_MEMBER_5B EQU 16\r
+CYDEV_CHIP_MEMBER_5A EQU 20\r
+CYDEV_CHIP_MEMBER_5B EQU 19\r
+CYDEV_CHIP_MEMBER_FM3 EQU 24\r
+CYDEV_CHIP_MEMBER_FM4 EQU 25\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 21\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 22\r
+CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 23\r
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED\r
CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1\r
CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3\r
CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3\r
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0\r
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1\r
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1\r
CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17\r
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17\r
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0\r
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0\r
+CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0\r
+CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1\r
+CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1\r
CYDEV_CHIP_REV_TMA4_ES EQU 17\r
CYDEV_CHIP_REV_TMA4_ES2 EQU 33\r
CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17\r
CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
CYDEV_CHIP_REVISION_5B_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION\r
CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED\r
CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1\r
/*******************************************************************************\r
* File Name: cymetadata.c\r
* \r
-* PSoC Creator 3.3\r
+* PSoC Creator 4.0 Update 1\r
*\r
* Description:\r
* This file defines all extra memory spaces that need to be included.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
\r
\r
#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
-__attribute__ ((__section__(".cyloadablemeta"), used))\r
+#ifndef CY_LOADABLE_META_SECTION\r
+#define CY_LOADABLE_META_SECTION __attribute__ ((__section__(".cyloadablemeta"), used))\r
+#endif\r
+CY_LOADABLE_META_SECTION\r
#elif defined(__ICCARM__)\r
#pragma location=".cyloadablemeta"\r
#else\r
const uint8 cy_meta_loadable[] = {\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x60u, 0x04u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x71u, 0x04u,\r
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
};\r
\r
#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
-__attribute__ ((__section__(".cyconfigecc"), used))\r
+#ifndef CY_CONFIG_ECC_SECTION\r
+#define CY_CONFIG_ECC_SECTION __attribute__ ((__section__(".cyconfigecc"), used))\r
+#endif\r
+CY_CONFIG_ECC_SECTION\r
#elif defined(__ICCARM__)\r
#pragma location=".cyconfigecc"\r
#else\r
-/*******************************************************************************\r
-* File Name: cypins.h\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file cypins.h\r
+* \version 5.50\r
*\r
-* Description:\r
-* This file contains the function prototypes and constants used for a port/pin\r
-* in access and control.\r
+* \brief This file contains the function prototypes and constants used for a\r
+* port/pin in access and control.\r
*\r
-* Note:\r
-* Documentation of the API's in this file is located in the\r
-* System Reference Guide provided with PSoC Creator.\r
+* \note Documentation of the API's in this file is located in the\r
+* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
/*******************************************************************************\r
* Macro Name: CyPins_ReadPin\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Reads the current value on the pin (pin state, PS).\r
*\r
-* Parameters:\r
-* pinPC: Port pin configuration register (uint16).\r
+* \param pinPC: Port pin configuration register (uint16).\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
-* in the form:\r
+* \param in the form:\r
* CYREG_PRTx_PCy\r
*\r
* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
*\r
-* Return:\r
+* \return\r
* Pin state\r
* 0: Logic low value\r
* Non-0: Logic high value\r
\r
/*******************************************************************************\r
* Macro Name: CyPins_SetPin\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Set the output value for the pin (data register, DR) to a logic high.\r
*\r
* Note that this only has an effect for pins configured as software pins that\r
* interrupt is disabled or within critical section (all interrupts are\r
* disabled).\r
*\r
-* Parameters:\r
-* pinPC: Port pin configuration register (uint16).\r
+* \param pinPC: Port pin configuration register (uint16).\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
-* in the form:\r
+* \param in the form:\r
* CYREG_PRTx_PCy\r
*\r
* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
#define CyPins_SetPin(pinPC) ( *(reg8 *)(pinPC) |= CY_PINS_PC_DATAOUT)\r
\r
\r
/*******************************************************************************\r
* Macro Name: CyPins_ClearPin\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* This macro sets the state of the specified pin to 0.\r
*\r
* The macro operation is not atomic. It is not guaranteed that shared register\r
* interrupt is disabled or within critical section (all interrupts are\r
* disabled).\r
*\r
-* Parameters:\r
-* pinPC: address of a Pin Configuration register.\r
+* \param pinPC: address of a Pin Configuration register.\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
-* in the form:\r
+* \param in the form:\r
* CYREG_PRTx_PCy\r
*\r
* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
#define CyPins_ClearPin(pinPC) ( *(reg8 *)(pinPC) &= ((uint8)(~CY_PINS_PC_DATAOUT)))\r
\r
\r
/*******************************************************************************\r
* Macro Name: CyPins_SetPinDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Sets the drive mode for the pin (DM).\r
*\r
* The macro operation is not atomic. It is not guaranteed that shared register\r
* interrupt is disabled or within critical section (all interrupts are\r
* disabled).\r
*\r
-* Parameters:\r
-* pinPC: Port pin configuration register (uint16)\r
+* \param pinPC: Port pin configuration register (uint16)\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
-* in the form:\r
+* \param in the form:\r
* CYREG_PRTx_PCy\r
*\r
* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
*\r
-* mode: Desired drive mode\r
+* \param mode: Desired drive mode\r
*\r
* Define Source\r
* PIN_DM_ALG_HIZ Analog HiZ\r
* PIN_DM_STRONG Strong CMOS Output\r
* PIN_DM_RES_UPDWN Resistive pull up/down\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
#define CyPins_SetPinDriveMode(pinPC, mode) \\r
( *(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & ((uint8)(~CY_PINS_PC_DRIVE_MODE_MASK))) | \\r
\r
/*******************************************************************************\r
* Macro Name: CyPins_ReadPinDriveMode\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Reads the drive mode for the pin (DM).\r
*\r
-* Parameters:\r
-* pinPC: Port pin configuration register (uint16)\r
+* \param pinPC: Port pin configuration register (uint16)\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
-* in the form:\r
+* \param in the form:\r
* CYREG_PRTx_PCy\r
*\r
* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
*\r
*\r
-* Return:\r
+* \return\r
* mode: The current drive mode for the pin\r
*\r
* Define Source\r
\r
/*******************************************************************************\r
* Macro Name: CyPins_FastSlew\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Set the slew rate for the pin to fast the edge rate.\r
* Note that this only applies for pins in strong output drive modes,\r
* not to resistive drive modes.\r
* interrupt is disabled or within critical section (all interrupts are\r
* disabled).\r
*\r
-* Parameters:\r
-* pinPC: address of a Pin Configuration register.\r
+* \param pinPC: address of a Pin Configuration register.\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
-* in the form:\r
+* \param in the form:\r
* CYREG_PRTx_PCy\r
*\r
* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
*\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
#define CyPins_FastSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & CY_PINS_PC_PIN_FASTSLEW))\r
\r
\r
/*******************************************************************************\r
* Macro Name: CyPins_SlowSlew\r
-********************************************************************************\r
+****************************************************************************//**\r
*\r
-* Summary:\r
* Set the slew rate for the pin to slow the edge rate.\r
* Note that this only applies for pins in strong output drive modes,\r
* not to resistive drive modes.\r
* interrupt is disabled or within critical section (all interrupts are\r
* disabled).\r
*\r
-* Parameters:\r
-* pinPC: address of a Pin Configuration register.\r
+* \param pinPC: address of a Pin Configuration register.\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
-* in the form:\r
+* \param in the form:\r
* CYREG_PRTx_PCy\r
*\r
* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
*\r
-* Return:\r
-* None\r
-*\r
*******************************************************************************/\r
#define CyPins_SlowSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) | CY_PINS_PC_PIN_SLOWSLEW))\r
\r
-/*******************************************************************************\r
-* FILENAME: cytypes.h\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file cytypes.h\r
+* \version 5.50\r
*\r
-* Description:\r
-* CyTypes provides register access macros and approved types for use in\r
-* firmware.\r
+* \brief CyTypes provides register access macros and approved types for use in\r
+* firmware.\r
*\r
-* Note:\r
-* Due to endiannesses of the hardware and some compilers, the register\r
-* access macros for big endian compilers use some library calls to arrange\r
-* data the correct way.\r
+* \note Due to endiannesses of the hardware and some compilers, the register\r
+* access macros for big endian compilers use some library calls to arrange\r
+* data the correct way.\r
*\r
-* Register Access macros and functions perform their operations on an\r
-* input of the type pointer to void. The arguments passed to it should be\r
-* pointers to the type associated with the register size.\r
-* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value)\r
+* Register Access macros and functions perform their operations on an\r
+* input of the type pointer to void. The arguments passed to it should be\r
+* pointers to the type associated with the register size.\r
+* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value)\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#define CY_PSOC4_4200BL (0u != 0u)\r
#endif /* CYDEV_CHIP_MEMBER_4F */\r
\r
+#ifdef CYDEV_CHIP_MEMBER_4M\r
+ #define CY_PSOC4_4100M (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4M)\r
+ #define CY_PSOC4_4200M (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4M)\r
+#else\r
+ #define CY_PSOC4_4100M (0u != 0u)\r
+ #define CY_PSOC4_4200M (0u != 0u)\r
+#endif /* CYDEV_CHIP_MEMBER_4M */\r
+\r
+#ifdef CYDEV_CHIP_MEMBER_4H\r
+ #define CY_PSOC4_4200D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4H)\r
+#else\r
+ #define CY_PSOC4_4200D (0u != 0u)\r
+#endif /* CYDEV_CHIP_MEMBER_4H */\r
+\r
+#ifdef CYDEV_CHIP_MEMBER_4L\r
+ #define CY_PSOC4_4200L (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4L)\r
+#else\r
+ #define CY_PSOC4_4200L (0u != 0u)\r
+#endif /* CYDEV_CHIP_MEMBER_4L */\r
+\r
+#ifdef CYDEV_CHIP_MEMBER_4U\r
+ #define CY_PSOC4_4000U (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4U)\r
+#else\r
+ #define CY_PSOC4_4000U (0u != 0u)\r
+#endif /* CYDEV_CHIP_MEMBER_4U */\r
+\r
+#ifdef CYDEV_CHIP_MEMBER_4J\r
+ #define CY_PSOC4_4000S (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4J)\r
+#else\r
+ #define CY_PSOC4_4000S (0u != 0u)\r
+#endif /* CYDEV_CHIP_MEMBER_4J */\r
+\r
+#ifdef CYDEV_CHIP_MEMBER_4K\r
+ #define CY_PSOC4_4100S (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4K)\r
+#else\r
+ #define CY_PSOC4_4100S (0u != 0u)\r
+#endif /* CYDEV_CHIP_MEMBER_4K */\r
+\r
+\r
+#define CY_IP_HOBTO_DEVICE (!(0 == 1))\r
+\r
\r
/*******************************************************************************\r
* IP blocks\r
#if (CY_PSOC4)\r
\r
/* Using SRSSv2 or SRS-Lite */\r
- #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
- #define CY_IP_SRSSV2 (0u == 0u)\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #define CY_IP_SRSSV2 (0 != 0)\r
#define CY_IP_SRSSLT (!CY_IP_SRSSV2)\r
#else\r
- #define CY_IP_SRSSV2 (0u != 0u)\r
+ #define CY_IP_SRSSV2 (0 == 0)\r
#define CY_IP_SRSSLT (!CY_IP_SRSSV2)\r
- #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #define CY_IP_CPUSSV3 (0 == 1)\r
+ #define CY_IP_CPUSSV2 (0 == 1)\r
+ #define CY_IP_CPUSS (0 == 1)\r
+ #else\r
+ #define CY_IP_CPUSSV3 (0 != 0)\r
+ #define CY_IP_CPUSSV2 (0 != 0)\r
+ #define CY_IP_CPUSS (0 == 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+ /* CM0 present or CM0+ present (1=CM0, 0=CM0+) */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_IP_CPUSS_CM0 (0 == 0)\r
+ #else /* CY_IP_CPUSSV3 */\r
+ #define CY_IP_CPUSS_CM0 (-1 == 1)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
+ #define CY_IP_CPUSS_CM0PLUS (!CY_IP_CPUSS_CM0)\r
+ #else\r
+ #define CY_IP_CPUSS_CM0 (0 == 0)\r
+ #define CY_IP_CPUSS_CM0PLUS (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
\r
- #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
- #define CY_IP_CPUSSV2 (0u != 0u)\r
- #define CY_IP_CPUSS (0u == 0u)\r
+\r
+ /* Flash memory present or not (1=Flash present, 0=Flash not present) */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #define CY_IP_CPUSS_FLASHC_PRESENT (0 == 0)\r
#else\r
- #define CY_IP_CPUSSV2 (0u != 0u)\r
- #define CY_IP_CPUSS (!CY_IP_CPUSSV2)\r
- #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+ #define CY_IP_CPUSS_FLASHC_PRESENT (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
\r
/* Product uses FLASH-Lite or regular FLASH */\r
- #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
- #define CY_IP_FMLT (0u != 0u) /* FLASH-Lite */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_IP_FM (-1 == 0)\r
+ #define CY_IP_FMLT (-1 == 1)\r
+ #define CY_IP_FS (-1 == 2)\r
+ #define CY_IP_FSLT (-1 == 3)\r
+ #else /* CY_IP_CPUSSV3 */\r
+ #define CY_IP_FM (-1 == 0)\r
+ #define CY_IP_FMLT (-1 == 1)\r
+ #define CY_IP_FS (-1 == 2)\r
+ #define CY_IP_FSLT (-1 == 3)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
+ #else\r
#define CY_IP_FM (!CY_IP_FMLT) /* Regular FLASH */\r
+ #define CY_IP_FMLT (0 != 0) /* FLASH-Lite */\r
+ #define CY_IP_FS (0 != 0) /* FS */\r
+ #define CY_IP_FSLT (0 != 0) /* FSLT */\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+\r
+ /* Enable simultaneous execution/programming in multi-macro devices */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_IP_FLASH_PARALLEL_PGM_EN (-1 == 1)\r
+ #else /* CY_IP_CPUSSV3 */\r
+ #define CY_IP_FLASH_PARALLEL_PGM_EN (-1 == 1)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
#else\r
- #define CY_IP_FMLT (-1u != 0u)\r
- #define CY_IP_FM (!CY_IP_FMLT)\r
- #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+ #define CY_IP_FLASH_PARALLEL_PGM_EN (0u != 0u)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+\r
+ /* Number of Flash macros used in the device (0, 1 or 2) */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_IP_FLASH_MACROS (-1u)\r
+ #else /* CY_IP_CPUSSV3 */\r
+ #define CY_IP_FLASH_MACROS (-1u)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
+ #else\r
+ #define CY_IP_FLASH_MACROS (1u)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
\r
/* Number of interrupt request inputs to CM0 */\r
- #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_IP_INT_NR (-1u)\r
+ #else /* CY_IP_CPUSSV3 */\r
+ #define CY_IP_INT_NR (-1u)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
+ #else\r
#define CY_IP_INT_NR (32u)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+\r
+ /* Presence of the BLESS IP block */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #define CY_IP_BLESS (0 != 0)\r
#else\r
- #define CY_IP_INT_NR (-1u)\r
- #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+ #define CY_IP_BLESS (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
\r
- /* Number of Flash macros used in the device (0, 1 or 2) */\r
- #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
- #define CY_IP_FLASH_MACROS (1u)\r
+\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #define CY_IP_USBDEV (0 != 0)\r
#else\r
- #define CY_IP_FLASH_MACROS (-1u)\r
- #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+ #define CY_IP_USBDEV (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
\r
\r
- /* Number of Flash macros used in the device (0, 1 or 2) */\r
- #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
- #define CY_IP_BLESS (0u != 0u)\r
+ /***************************************************************************\r
+ * Devices with the SPCIF_SYNCHRONOUS parameter set to one will not use\r
+ * the 36MHz Oscillator for Flash operation. Instead, flash write function\r
+ * ensures that the charge pump clock and the higher frequency clock (HFCLK)\r
+ * are set to the IMO at 48MHz prior to writing the flash.\r
+ ***************************************************************************/\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_IP_SPCIF_SYNCHRONOUS (-1 == 1)\r
+ #else /* CY_IP_CPUSSV3 */\r
+ #define CY_IP_SPCIF_SYNCHRONOUS (-1 == 1)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
#else\r
- #define CY_IP_BLESS (0u != 0u)\r
- #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+ #define CY_IP_SPCIF_SYNCHRONOUS (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
\r
/* Watch Crystal Oscillator (WCO) is present (32kHz) */\r
- #if (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200)\r
- #define CY_IP_WCO (0u != 0u)\r
- #elif CY_IP_BLESS || defined (CYIPBLOCK_s8swco_VERSION)\r
- #define CY_IP_WCO (0u == 0u)\r
- #elif (CY_IP_SRSSV2)\r
- #define CY_IP_WCO (-1u)\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_BLESS)\r
+ #define CY_IP_WCO_BLESS (0 == 0)\r
+ #define CY_IP_WCO_WCO (0 != 0)\r
+ #define CY_IP_WCO_SRSSV2 (0 != 0)\r
+ #else\r
+ #define CY_IP_WCO_BLESS (0 != 0)\r
+ #define CY_IP_WCO_WCO (0 == 1)\r
+ #define CY_IP_WCO_SRSSV2 (-1 == 1)\r
+ #endif /* (CY_IP_BLESS) */\r
#else\r
- #define CY_IP_WCO (0u != 0u)\r
- #endif /* (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+ #define CY_IP_WCO_BLESS (0 != 0)\r
+ #define CY_IP_WCO_WCO (0 != 0)\r
+ #define CY_IP_WCO_SRSSV2 (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+ #define CY_IP_WCO (CY_IP_WCO_BLESS || CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2)\r
+\r
+\r
+ /* PLL is present */\r
+ #if (CY_IP_HOBTO_DEVICE && CY_IP_SRSSV2)\r
+ #define CY_IP_PLL ((-1 != 0) || \\r
+ (-1 != 0))\r
+\r
+ #define CY_IP_PLL_NR (-1u + \\r
+ -1u)\r
+ #else\r
+ #define CY_IP_PLL (0 != 0)\r
+ #define CY_IP_PLL_NR (0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE && CY_IP_SRSSV2) */\r
+\r
+\r
+ /* External Crystal Oscillator is present (high frequency) */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_BLESS)\r
+ #define CY_IP_ECO_BLESS (0 == 0)\r
+ #define CY_IP_ECO_SRSSV2 (0 != 0)\r
+ #else\r
+ #define CY_IP_ECO_BLESS (0 != 0)\r
+ #define CY_IP_ECO_SRSSV2 (-1 == 1)\r
+ #endif /* (CY_IP_BLESS) */\r
+ #else\r
+ #define CY_IP_ECO_BLESS (0 != 0)\r
+ #define CY_IP_ECO_SRSSV2 (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+ #define CY_IP_ECO (CY_IP_ECO_BLESS || CY_IP_ECO_SRSSV2)\r
+\r
+\r
+ /* Clock Source clk_lf implemented in SysTick Counter. When 0, not implemented, 1=implemented */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_SYSTICK_LFCLK_SOURCE (-1 != 0)\r
+ #else /* CY_IP_CPUSSV3 */\r
+ #define CY_SYSTICK_LFCLK_SOURCE (-1 != 0)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
+ #else\r
+ #define CY_SYSTICK_LFCLK_SOURCE (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+\r
+ /* Flash Macro 0 has extra rows */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #ifdef CYREG_SFLASH_MACRO_0_FREE_SFLASH0\r
+ #define CY_SFLASH_XTRA_ROWS (0 == 0)\r
+ #else\r
+ #define CY_SFLASH_XTRA_ROWS (0 != 0)\r
+ #endif /* CYREG_SFLASH_MACRO_0_FREE_SFLASH0 */\r
+\r
+ #else\r
+ #define CY_SFLASH_XTRA_ROWS (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+\r
+ #if (CY_IP_USBDEV)\r
+ #define CY_IP_IMO_TRIMMABLE_BY_USB (0 == 0)\r
+ #else\r
+ #define CY_IP_IMO_TRIMMABLE_BY_USB (0 != 0)\r
+ #endif /* (CY_IP_USBDEV) */\r
+\r
+\r
+ #if (CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2)\r
+ #define CY_IP_IMO_TRIMMABLE_BY_WCO (0 == 0)\r
+ #else\r
+ #define CY_IP_IMO_TRIMMABLE_BY_WCO (0 != 0)\r
+ #endif /* (CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2) */\r
+\r
+\r
+ /* DW/DMA Controller present (0=No, 1=Yes) */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_IP_DMAC_PRESENT (-1 == 1)\r
+ #else\r
+ #define CY_IP_DMAC_PRESENT (-1 == 1)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
+ #else\r
+ #define CY_IP_DMAC_PRESENT (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #define CY_IP_PASS (0 == 1)\r
+ #else\r
+ #define CY_IP_PASS (0 != 0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+\r
+\r
+ /* Number of external slave ports on System Interconnect */\r
+ #if (CY_IP_HOBTO_DEVICE)\r
+ #if (CY_IP_CPUSSV2)\r
+ #define CY_IP_SL_NR (-1)\r
+ #else\r
+ #define CY_IP_SL_NR (-1)\r
+ #endif /* (CY_IP_CPUSSV2) */\r
+ #else\r
+ #define CY_IP_SL_NR (0)\r
+ #endif /* (CY_IP_HOBTO_DEVICE) */\r
+\r
+#else\r
+\r
+ #if (CY_PSOC3)\r
+ #define CY_SYSTICK_LFCLK_SOURCE (0 != 0)\r
+ #else /* PSoC 5LP */\r
+ #define CY_SYSTICK_LFCLK_SOURCE (0 == 0)\r
+ #endif /* (CY_PSOC3) */\r
\r
#endif /* (CY_PSOC4) */\r
\r
* (defined(CY_BOOT_VERSION) && CY_BOOT_VERSION >= CY_BOOT_4_20)\r
*******************************************************************************/\r
#define CY_BOOT_4_20 (420u)\r
-#define CY_BOOT_VERSION (CY_BOOT_4_20)\r
+#define CY_BOOT_5_0 (500u)\r
+#define CY_BOOT_5_10 (510u)\r
+#define CY_BOOT_5_20 (520u)\r
+#define CY_BOOT_5_30 (530u)\r
+#define CY_BOOT_5_40 (540u)\r
+#define CY_BOOT_VERSION (CY_BOOT_5_40)\r
\r
\r
/*******************************************************************************\r
#endif /* (CY_PSOC3) */\r
\r
\r
-/*******************************************************************************\r
-* Register Access\r
-*******************************************************************************/\r
-#if(CY_PSOC3)\r
+#define CY_M_PI (3.14159265358979323846264338327)\r
+\r
+\r
+/**\r
+* \addtogroup group_register_access\r
+A library of macros provides read and write access to the registers of the device. These macros are used with the\r
+defined values made available in the generated cydevice_trm.h and cyfitter.h files. Access to registers should be made\r
+using these macros and not the functions that are used to implement the macros. This allows for device independent code\r
+generation.\r
+\r
+The PSoC 4 processor architecture use little endian ordering.\r
+\r
+SRAM and Flash storage in all architectures is done using the endianness of the architecture and compilers. However,\r
+the registers in all these chips are laid out in little endian order. These macros allow register accesses to match this\r
+little endian ordering. If you perform operations on multi-byte registers without using these macros, you must consider\r
+the byte ordering of the specific architecture. Examples include usage of DMA to transfer between memory and registers,\r
+as well as function calls that are passed an array of bytes in memory.\r
+\r
+The PSoC 4 requires these accesses to be aligned to the width of the transaction.\r
+\r
+The PSoC 4 requires peripheral register accesses to match the hardware register size. Otherwise, the peripheral might\r
+ignore the transfer and Hard Fault exception will be generated.\r
+\r
+*/\r
\r
+/** @} group_register_access */\r
\r
+\r
+/**\r
+* \addtogroup group_register_access_macros Register Access\r
+* \ingroup group_register_access\r
+* @{\r
+*/\r
+\r
+#if(CY_PSOC3)\r
/*******************************************************************************\r
- * KEIL for the 8051 is a big endian compiler This causes problems as the on chip\r
- * registers are little endian. Byte swapping for two and four byte registers is\r
- * implemented in the functions below. This will require conditional compilation\r
- * of function prototypes in the code.\r
+ * Macro Name: CY_GET_REG8(addr)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the 8-bit value from the specified register.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Read value.\r
+ *\r
*******************************************************************************/\r
+ #define CY_GET_REG8(addr) (*((const reg8 *)(addr)))\r
\r
- /* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */\r
\r
- #define CY_GET_REG8(addr) (*((const reg8 *)(addr)))\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_REG8(addr, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Writes the 8-bit value to the specified register.\r
+ *\r
+ * \param reg Register address.\r
+ * \param value Value to write.\r
+ *\r
+ *******************************************************************************/\r
#define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value))\r
\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_REG16(addr)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the 16-bit value from the specified register. This macro implements the\r
+ * byte swapping required for proper operation.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Read value.\r
+ *\r
+ *******************************************************************************/\r
#define CY_GET_REG16(addr) cyread16_nodpx ((const volatile void far *)(const reg16 *)(addr))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_REG16(addr, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Writes the 16-bit value to the specified register. This macro implements the\r
+ * byte swapping required for proper operation.\r
+ *\r
+ * \param reg Register address.\r
+ * \param value Value to write.\r
+ *\r
+ *******************************************************************************/\r
#define CY_SET_REG16(addr, value) cywrite16_nodpx((volatile void far *)(reg16 *)(addr), value)\r
\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_REG24(addr)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the 24-bit value from the specified register. This macro implements the\r
+ * byte swapping required for proper operation.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Read value.\r
+ *\r
+ *******************************************************************************/\r
#define CY_GET_REG24(addr) cyread24_nodpx ((const volatile void far *)(const reg32 *)(addr))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_REG24(addr, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Writes the 24-bit value to the specified register. This macro implements the\r
+ * byte swapping required for proper operation.\r
+ *\r
+ * \param reg Register address.\r
+ * \param value Value to write.\r
+ *\r
+ *******************************************************************************/\r
#define CY_SET_REG24(addr, value) cywrite24_nodpx((volatile void far *)(reg32 *)(addr),value)\r
\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_REG32(addr)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the 32-bit value from the specified register. This macro implements the\r
+ * byte swapping required for proper operation.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Read value.\r
+ *\r
+ *******************************************************************************/\r
#define CY_GET_REG32(addr) cyread32_nodpx ((const volatile void far *)(const reg32 *)(addr))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_REG32(addr, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Writes the 32-bit value to the specified register. This macro implements the\r
+ * byte swapping required for proper operation.\r
+ *\r
+ * \param reg Register address.\r
+ * \param value Value to write.\r
+ *\r
+ *******************************************************************************/\r
#define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value)\r
\r
- /* Access 8, 16, 24 and 32-bit registers, ABOVE THE FIRST 64K OF XDATA */\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_XTND_REG8(addr)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the 8-bit value from the specified register.\r
+ * Identical to \ref CY_GET_REG8 for PSoC 4.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Read value.\r
+ *\r
+ *******************************************************************************/\r
#define CY_GET_XTND_REG8(addr) cyread8((const volatile void far *)(addr))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_XTND_REG8(addr, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Writes the 8-bit value to the specified register.\r
+ * Identical to \ref CY_SET_REG8 for PSoC 4.\r
+ *\r
+ * \param reg Register address.\r
+ * \param value Value to write.\r
+ *\r
+ *******************************************************************************/\r
#define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value)\r
\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_XTND_REG16(addr)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the 16-bit value from the specified register. This macro implements the\r
+ * byte swapping required for proper operation. Identical to \ref CY_GET_REG16\r
+ * for PSoC 4.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Read value.\r
+ *\r
+ *******************************************************************************/\r
#define CY_GET_XTND_REG16(addr) cyread16((const volatile void far *)(addr))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_XTND_REG16(addr, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Writes the 16-bit value to the specified register. This macro implements the\r
+ * byte swapping required for proper operation. Identical to \ref CY_SET_REG16\r
+ * for PSoC 4.\r
+ *\r
+ * \param reg Register address.\r
+ * \param value Value to write.\r
+ *\r
+ *******************************************************************************/\r
#define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value)\r
\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_XTND_REG24(addr)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the 24-bit value from the specified register. This macro implements the\r
+ * byte swapping required for proper operation. Identical to \ref CY_GET_REG24\r
+ * for PSoC 4.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Read value.\r
+ *\r
+ *******************************************************************************/\r
#define CY_GET_XTND_REG24(addr) cyread24((const volatile void far *)(addr))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_XTND_REG24(addr, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Writes the 24-bit value to the specified register. This macro implements the\r
+ * byte swapping required for proper operation. Identical to \ref CY_SET_REG24\r
+ * for PSoC 4.\r
+ *\r
+ * \param reg Register address.\r
+ * \param value Value to write.\r
+ *\r
+ *******************************************************************************/\r
#define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value)\r
\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_XTND_REG32(addr)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the 32-bit value from the specified register. This macro implements the\r
+ * byte swapping required for proper operation. Identical to \ref CY_GET_REG32\r
+ * for PSoC 4.\r
+ *\r
+ * \param reg Register address.\r
+ *\r
+ * \return Read value.\r
+ *\r
+ *******************************************************************************/\r
#define CY_GET_XTND_REG32(addr) cyread32((const volatile void far *)(addr))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_XTND_REG32(addr, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Writes the 32-bit value to the specified register. This macro implements the\r
+ * byte swapping required for proper operation. Identical to \ref CY_SET_REG32\r
+ * for PSoC 4.\r
+ *\r
+ * \param reg Register address.\r
+ * \param value Value to write.\r
+ *\r
+ *******************************************************************************/\r
#define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value)\r
\r
#else\r
\r
- /* 8, 16, 24 and 32-bit register access macros */\r
#define CY_GET_REG8(addr) (*((const reg8 *)(addr)))\r
#define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value))\r
\r
#define CY_GET_REG32(addr) (*((const reg32 *)(addr)))\r
#define CY_SET_REG32(addr, value) (*((reg32 *)(addr)) = (uint32)(value))\r
\r
-\r
/* To allow code to be 8051-ARM agnostic. */\r
#define CY_GET_XTND_REG8(addr) CY_GET_REG8(addr)\r
#define CY_SET_XTND_REG8(addr, value) CY_SET_REG8(addr, value)\r
#define CY_SET_XTND_REG32(addr, value) CY_SET_REG32(addr, value)\r
\r
#endif /* (CY_PSOC3) */\r
+/** @} group_register_access_macros */\r
+\r
+\r
+/**\r
+* \addtogroup group_register_access_bits Bit Manipulation\r
+* \ingroup group_register_access\r
+* @{\r
+*/\r
+\r
+#if(CY_PSOC4)\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_FIELD_MASK(regSize, bitFieldName)\r
+ ****************************************************************************//**\r
+ *\r
+ * Returns the bit field mask for the specified register size and bit field\r
+ * name.\r
+ *\r
+ * \param regSize Size of the register in bits.\r
+ * \param bitFieldName Fully qualified name of the bit field. The biFieldName\r
+ * is automatically appended with __OFFSET and __SIZE by the macro for usage.\r
+ *\r
+ * \return Returns the bit mask.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_GET_FIELD_MASK(regSize, bitFieldName) \\r
+ ((((uint ## regSize) 0xFFFFFFFFu << ((uint32)(regSize) - bitFieldName ## __SIZE - bitFieldName ## __OFFSET)) >>\\r
+ ((uint32)(regSize) - bitFieldName ## __SIZE)) << bitFieldName ## __OFFSET)\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_REG8_FIELD(registerName, bitFieldName)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the specified bit field value from the specified 8-bit register.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register will remain uncorrupted during simultaneous read-modify-write\r
+ * operation performed by two threads (main and interrupt threads). To\r
+ * guarantee data integrity in such cases, the macro should be invoked while\r
+ * the specific interrupt is disabled or within a critical section (all\r
+ * interrupts are disabled).\r
+ *\r
+ * Using this macro on 32-bit and 16-bit width registers will generate a\r
+ * hard fault exception. Examples of 8-bit registers are the UDB registers.\r
+ *\r
+ * \param registerName: The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName: fully qualified name of the bit field. The biFieldName is\r
+ * automatically appended with __OFFSET and __SIZE by the macro for usage.\r
+ *\r
+ * For fully qualified names of the register and bit fields and the possible\r
+ * values the field can take, please, refer to a respective PSoC family\r
+ * register TRM.\r
+ *\r
+ * \return Zero if the specified bit field is zero, and a non-zero value,\r
+ * otherwise. The return value is of type uint32.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_GET_REG8_FIELD(registerName, bitFieldName) \\r
+ ((CY_GET_REG8((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFu << bitFieldName ## __SIZE)))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_REG8_FIELD(registerName, bitFieldName, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Sets the specified bit field value of the specified 8-bit register to the\r
+ * required value.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write\r
+ * operation performed by two threads (main and interrupt threads). To\r
+ * guarantee data integrity in such cases, the macro should be invoked while\r
+ * the specific interrupt is disabled or within a critical section (all\r
+ * interrupts are disabled).\r
+ *\r
+ * Using this macro on the 32-bit and 16-bit width registers, generates a\r
+ * hard fault exception. Examples of 8-bit registers are the UDB registers.\r
+ *\r
+ * \param registerName The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName fully qualified name of the bit field. The biFieldName is\r
+ * automatically appended with __OFFSET and __SIZE by the macro for usage.\r
+ * \param value The value that the field must be configured for.\r
+ *\r
+ * For fully qualified names of the register and bit fields and the possible\r
+ * values the field can take, please, refer to a respective PSoC family\r
+ * register TRM.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_SET_REG8_FIELD(registerName, bitFieldName, value) \\r
+ CY_SET_REG8((registerName), \\r
+ ((CY_GET_REG8((registerName)) & ~CY_GET_FIELD_MASK(8, bitFieldName)) | \\r
+ (((uint8)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(8, bitFieldName))))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_CLEAR_REG8_FIELD(registerName, bitFieldName)\r
+ ****************************************************************************//**\r
+ *\r
+ * Clears the specified bit field of the specified 8-bit register.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write\r
+ * operation performed by two threads (main and interrupt threads). To\r
+ * guarantee data integrity in such cases, the macro should be invoked while\r
+ * the specific interrupt is disabled or within a critical section (all\r
+ * interrupts are disabled).\r
+ *\r
+ * Using this macro on the 32-bit and 16-bit width registers generates a\r
+ * hard fault exception. Examples of 8-bit registers are the UDB registers.\r
+ *\r
+ * \param registerName The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName fully qualified name of the bit field. The biFieldName is\r
+ * automatically appended with __OFFSET and __SIZE by the macro for usage.\r
+ *\r
+ * For fully qualified names of the register and bit fields and the\r
+ * possible values the field can take, please, refer to a respective PSoC\r
+ * family register TRM.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_CLEAR_REG8_FIELD(registerName, bitFieldName) \\r
+ (CY_SET_REG8((registerName), (CY_GET_REG8((registerName)) & ~CY_GET_FIELD_MASK(8, bitFieldName))))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_REG16_FIELD(registerName, bitFieldName)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the specified bit field value from the specified 16-bit register.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write\r
+ * operation performed by two threads (main and interrupt threads). To\r
+ * guarantee data integrity in such cases, the macro should be invoked while\r
+ * the specific interrupt is disabled or within a critical section (all\r
+ * interrupts are disabled).\r
+ *\r
+ * Using this macro on the 32-bit and 16-bit width registers generates a\r
+ * hardfault exception. Examples of 8-bit registers are the UDB registers.\r
+ *\r
+ * \param registerName The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName fully qualified name of the bit field. The biFieldName is\r
+ * automatically appended with __OFFSET and __SIZE by the macro for usage.\r
+ *\r
+ * For fully qualified names of the register and bit fields and the\r
+ * possible values the field can take, please, refer to a respective PSoC\r
+ * family register TRM.\r
+ *\r
+ * \return Zero if the specified bit field is zero, and a non-zero value,\r
+ * otherwise. The return value is of type uint32.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_GET_REG16_FIELD(registerName, bitFieldName) \\r
+ ((CY_GET_REG16((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFFFu << bitFieldName ## __SIZE)))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_REG16_FIELD(registerName, bitFieldName, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Sets the specified bit field value of the specified 16-bit register to the\r
+ * required value.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write operation\r
+ * performed by two threads (main and interrupt threads). To guarantee data\r
+ * integrity in such cases, the macro should be invoked while the specific\r
+ * interrupt is disabled or within a critical section (all interrupts are\r
+ * disabled).\r
+ *\r
+ * Using this macro on the 32-bit and 16-bit width registers generates a hard\r
+ * fault exception. Examples of 8-bit registers are the UDB registers.\r
+ *\r
+ * \param registerNam The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName: fully qualified name of the bit field. The biFieldName is\r
+ * automatically appended with __OFFSET and __SIZE by the macro for usage.\r
+ * \param value The value that the field must be configured for.\r
+ *\r
+ * For fully qualified names of the register and bit fields and the possible\r
+ * values the field can take, please, refer to a respective PSoC family\r
+ * register TRM.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_SET_REG16_FIELD(registerName, bitFieldName, value) \\r
+ CY_SET_REG16((registerName), \\r
+ ((CY_GET_REG16((registerName)) & ~CY_GET_FIELD_MASK(16, bitFieldName)) | \\r
+ (((uint16)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(16, bitFieldName))))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_CLEAR_REG16_FIELD(registerName, bitFieldName)\r
+ ****************************************************************************//**\r
+ *\r
+ * Clears the specified bit field of the specified 16-bit register.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write operation\r
+ * performed by two threads (main and interrupt threads). To guarantee data\r
+ * integrity in such cases, the macro should be invoked while the specific\r
+ * interrupt is disabled or within a critical section (all interrupts are\r
+ * disabled).\r
+ *\r
+ * Using this macro on the 32-bit and 16-bit width registers generates a hard\r
+ * fault exception. Examples of 8-bit registers are the UDB registers.\r
+ *\r
+ * \param registerName: The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName: fully qualified name of the bit field. The biFieldName is\r
+ * automatically appended with __OFFSET and __SIZE by the macro for usage.\r
+ *\r
+ * For fully qualified names of the register and bit fields and the possible\r
+ * values the field can take, please, refer to a respective PSoC family register\r
+ * TRM.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_CLEAR_REG16_FIELD(registerName, bitFieldName)\\r
+ (CY_SET_REG16((registerName), (CY_GET_REG16((registerName)) & ~CY_GET_FIELD_MASK(16, bitFieldName))))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_REG32_FIELD(registerName, bitFieldName)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the specified bit field value from the specified 32-bit register.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write operation\r
+ * performed by two threads (main and interrupt threads). To guarantee data\r
+ * integrity in such cases, the macro should be invoked while the specific\r
+ * interrupt is disabled or within a critical section (all interrupts are\r
+ * disabled).\r
+ *\r
+ * Using this macro on the 16-bit and 8-bit width registers generates a hard\r
+ * fault exception.\r
+ *\r
+ * \param registerName The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName The Fully qualified name of the bit field. The\r
+ * biFieldName is automatically appended with __OFFSET and __SIZE by the macro\r
+ * for usage.\r
+ *\r
+ * For fully qualified names of the register and bit fields, please, refer to\r
+ * a respective PSoC family register TRM.\r
+ *\r
+ * \return Zero if the specified bit field is zero, and a non-zero value, otherwise.\r
+ * The return value is of type uint32.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_GET_REG32_FIELD(registerName, bitFieldName) \\r
+ ((CY_GET_REG32((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFFFFFFFu << bitFieldName ## __SIZE)))\r
+\r
\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_REG32_FIELD(registerName, bitFieldName, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Sets the specified bit field value of the specified 32-bit register to the\r
+ * required value.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write operation\r
+ * performed by two threads (main and interrupt threads). To guarantee data\r
+ * integrity in such cases, the macro should be invoked while the specific\r
+ * interrupt is disabled or within a critical section (all interrupts are\r
+ * disabled).\r
+ *\r
+ * Using this macro on the 16-bit and 8-bit width registers generates a hard\r
+ * fault exception.\r
+ *\r
+ * \param registerName The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName The fully qualified name of the bit field. The\r
+ * biFieldName is automatically appended with __OFFSET and __SIZE by the macro\r
+ * for usage.\r
+ * \param value The value that the field must be configured for.\r
+ *\r
+ * For fully qualified names of the register and bit fields and the possible\r
+ * values the field can take, please, refer to a respective PSoC family register\r
+ * TRM.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_SET_REG32_FIELD(registerName, bitFieldName, value) \\r
+ CY_SET_REG32((registerName), \\r
+ ((CY_GET_REG32((registerName)) & ~CY_GET_FIELD_MASK(32, bitFieldName)) | \\r
+ (((uint32)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(32, bitFieldName))))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_CLEAR_REG32_FIELD(registerName, bitFieldName)\r
+ ****************************************************************************//**\r
+ *\r
+ * Clears the specified bit field of the specified 32-bit register.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write operation\r
+ * performed by two threads (main and interrupt threads). To guarantee data\r
+ * integrity in such cases, the macro should be invoked while the specific\r
+ * interrupt is disabled or within a critical section (all interrupts are\r
+ * disabled).\r
+ *\r
+ * Using this macro on the 16-bit and 8-bit width registers generates a hard\r
+ * fault exception.\r
+ *\r
+ * \param registerName The fully qualified name of the PSoC 4 device register.\r
+ * \param bitFieldName The fully qualified name of the bit field. The\r
+ * biFieldName is automatically appended with __OFFSET and __SIZE by the macro\r
+ * for usage.\r
+ *\r
+ * For fully qualified names of the register and bit fields and the possible\r
+ * values the field can take, please, refer to a respective PSoC family register\r
+ * TRM.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_CLEAR_REG32_FIELD(registerName, bitFieldName) \\r
+ (CY_SET_REG32((registerName), (CY_GET_REG32((registerName)) & ~CY_GET_FIELD_MASK(32, bitFieldName))))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_GET_FIELD(regValue, bitFieldName)\r
+ ****************************************************************************//**\r
+ *\r
+ * Reads the specified bit field value from the given 32-bit value.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write operation\r
+ * performed by two threads (main and interrupt threads). To guarantee data\r
+ * integrity in such cases, the macro should be invoked while the specific\r
+ * interrupt is disabled or within a critical section (all interrupts are\r
+ * disabled).\r
+ *\r
+ * This macro has to be used in conjunction with \ref CY_GET_REG32 for atomic\r
+ * reads.\r
+ *\r
+ * \param regValue The value as read by \ref CY_GET_REG32.\r
+ * \param bitFieldName The fully qualified name of the bit field. The\r
+ * biFieldName is automatically appended with __OFFSET and __SIZE by the macro\r
+ * for usage.\r
+ *\r
+ * For fully qualified names of the bit field and the possible values the field\r
+ * can take, please, refer to a respective PSoC family register TRM.\r
+ *\r
+ * \return Zero if the specified bit field is zero, and a non-zero value,\r
+ * otherwise. The return value is of type uint32.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_GET_FIELD(regValue, bitFieldName) \\r
+ (((regValue) >> bitFieldName ## __OFFSET) & (~(0xFFFFFFFFu << bitFieldName ## __SIZE)))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CY_SET_FIELD(regValue, bitFieldName, value)\r
+ ****************************************************************************//**\r
+ *\r
+ * Sets the specified bit field value within a given 32-bit value.\r
+ *\r
+ * The macro operation is not atomic. It is not guaranteed that the shared\r
+ * register remains uncorrupted during simultaneous read-modify-write operation\r
+ * performed by two threads (main and interrupt threads). To guarantee data\r
+ * integrity in such cases, the macro should be invoked while the specific\r
+ * interrupt is disabled or within a critical section (all interrupts are\r
+ * disabled).\r
+ *\r
+ * This macro has to be used in conjunction with \ref CY_GET_REG32 for atomic\r
+ * reads and \ref CY_SET_REG32 for atomic writes.\r
+ *\r
+ * \param regValue The value as read by \ref CY_GET_REG32.\r
+ * \param bitFieldName The fully qualified name of the bit field. The\r
+ * biFieldName is automatically appended with __OFFSET and __SIZE by the macro\r
+ * for usage.\r
+ * \param value The value that the field must be configured for.\r
+ *\r
+ * For fully qualified names of the bit field and the possible values the field\r
+ * can take, please, refer to the respective PSoC family register TRM.\r
+ *\r
+ *******************************************************************************/\r
+ #define CY_SET_FIELD(regValue, bitFieldName, value) \\r
+ ((regValue) = \\r
+ ((((uint32)(value) & (~(0xFFFFFFu << bitFieldName ## __SIZE))) << bitFieldName ## __OFFSET)) | \\r
+ ((uint32)(regValue) & (((~(0xFFu << bitFieldName ## __SIZE))) << bitFieldName ## __OFFSET)))\r
+\r
+#endif /* (CY_PSOC4) */\r
+\r
+/** @} group_register_access_bits */\r
\r
\r
/*******************************************************************************\r
\r
/* Swap the byte ordering of 32 bit value */\r
#define CYSWAP_ENDIAN32(x) \\r
- ((uint32)(((x) >> 24) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24)))\r
+ ((uint32)((((x) >> 24) & 0x000000FFu) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24)))\r
\r
/* Swap the byte ordering of 16 bit value */\r
-#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | ((x) >> 8)))\r
+#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | (((x) >> 8) & 0x00FFu)))\r
\r
\r
/*******************************************************************************\r
\r
\r
/*******************************************************************************\r
-* The following code is OBSOLETE and must not be used starting from cy_boot 3.10\r
+* The following code is OBSOLETE and must not be used starting from cy_boot 5.10\r
*\r
* If the obsoleted macro definitions intended for use in the application use the\r
* following scheme, redefine your own versions of these definitions:\r
* used in the application and their modification might lead to unexpected\r
* consequences.\r
*******************************************************************************/\r
+#define CY_IP_S8FS CY_IP_FS\r
+\r
+\r
+/*******************************************************************************\r
+* The following code is OBSOLETE and must not be used starting from cy_boot 3.10\r
+*******************************************************************************/\r
#define CY_UDB_V0 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)\r
#define CY_UDB_V1 (!CY_UDB_V0)\r
#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)\r
-/*******************************************************************************\r
-* FILENAME: cyutils.c\r
-* Version 4.20\r
+/***************************************************************************//**\r
+* \file cyutils.c\r
+* \version 5.50\r
*\r
-* Description:\r
-* CyUtils provides a function to handle 24-bit value writes.\r
+* \brief Provides a function to handle 24-bit value writes.\r
*\r
********************************************************************************\r
-* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
+* \copyright\r
+* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
/***************************************************************************\r
* Function Name: CySetReg24\r
- ****************************************************************************\r
+ ************************************************************************//**\r
*\r
- * Summary:\r
- * Writes a 24-bit value to the specified register.\r
+ * Writes a 24-bit value to the specified register.\r
*\r
- * Parameters:\r
- * addr : the address where data must be written.\r
- * value: the data that must be written.\r
- *\r
- * Return:\r
- * None\r
+ * \param add The address where data must be written.\r
+ * \param value The data that must be written.\r
*\r
* Reentrant:\r
* No\r
\r
/***************************************************************************\r
* Function Name: CyGetReg24\r
- ****************************************************************************\r
+ ************************************************************************//**\r
*\r
- * Summary:\r
* Reads the 24-bit value from the specified register.\r
*\r
- * Parameters:\r
- * addr : the address where data must be read.\r
- *\r
- * Return:\r
- * None\r
+ * \param addr : the address where data must be read.\r
*\r
* Reentrant:\r
* No\r
/*******************************************************************************\r
* File Name: project.h\r
* \r
-* PSoC Creator 3.3\r
+* PSoC Creator 4.0 Update 1\r
*\r
* Description:\r
* It contains references to all generated header files and should not be modified.\r
* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.\r
+* Copyright (c) 2007-2016 Cypress Semiconductor. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
#include "USBFS_hid.h"\r
#include "USBFS_midi.h"\r
#include "USBFS_pvt.h"\r
+#include "USBFS_cydmac.h"\r
+#include "USBFS_msc.h"\r
#include "Bootloadable_1.h"\r
#include "SCSI_Out_Bits.h"\r
#include "SCSI_Out_Ctl.h"\r
#include "USBFS_Dp_aliases.h"\r
#include "USBFS_Dp.h"\r
#include "core_cm3_psoc5.h"\r
-#include "core_cm3.h"\r
#include "CyDmac.h"\r
#include "CyFlash.h"\r
#include "CyLib.h"\r
#include "cyPm.h"\r
#include "CySpc.h"\r
#include "cytypes.h"\r
-#include "core_cmFunc.h"\r
-#include "core_cmInstr.h"\r
\r
/*[]*/\r
\r
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006565" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_MASK_REG" address="0x40006585" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006595" bitWidth="8" desc="" hidden="false">\r
- <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006463" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x40006483" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006493" bitWidth="8" desc="" hidden="false">\r
+ <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
</field>\r
- <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">\r
+ <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt" hidden="false">\r
<value name="ENABLED" value="1" desc="Interrupt enabled" />\r
<value name="DISABLED" value="0" desc="Interrupt disabled" />\r
</field>\r
- <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">\r
+ <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level" hidden="false">\r
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
</field>\r
- <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">\r
+ <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level" hidden="false">\r
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
</field>\r
- <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">\r
+ <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear" hidden="false">\r
<value name="ENABLED" value="1" desc="Clear FIFO state" />\r
<value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
</field>\r
- <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">\r
+ <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear" hidden="false">\r
<value name="ENABLED" value="1" desc="Clear FIFO state" />\r
<value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
</field>\r
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Filtered_STATUS_REG" address="0x4000646B" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Filtered_MASK_REG" address="0x4000648B" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649B" bitWidth="8" desc="" hidden="false">\r
- <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
+ <register name="SCSI_Filtered_STATUS_REG" address="0x40006468" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Filtered_MASK_REG" address="0x40006488" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006498" bitWidth="8" desc="" hidden="false">\r
+ <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
</field>\r
- <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">\r
+ <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt" hidden="false">\r
<value name="ENABLED" value="1" desc="Interrupt enabled" />\r
<value name="DISABLED" value="0" desc="Interrupt disabled" />\r
</field>\r
- <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">\r
+ <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level" hidden="false">\r
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
</field>\r
- <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">\r
+ <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level" hidden="false">\r
<value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
<value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
</field>\r
- <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">\r
+ <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear" hidden="false">\r
<value name="ENABLED" value="1" desc="Clear FIFO state" />\r
<value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
</field>\r
- <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">\r
+ <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear" hidden="false">\r
<value name="ENABLED" value="1" desc="Clear FIFO state" />\r
<value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
</field>\r
<block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG" hidden="false">\r
- <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />\r
+ <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." hidden="false" />\r
</register>\r
<register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0" hidden="false">\r
- <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />\r
- <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">\r
+ <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." hidden="false" />\r
+ <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)" hidden="false">\r
<value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />\r
<value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />\r
</field>\r
- <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />\r
- <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />\r
- <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />\r
- <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">\r
+ <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." hidden="false" />\r
+ <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." hidden="false" />\r
+ <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" hidden="false" />\r
+ <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively." hidden="false">\r
<value name="Timer" value="0" desc="CMP and TC are output." />\r
<value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />\r
</field>\r
- <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />\r
+ <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" hidden="false" />\r
</register>\r
<register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1" hidden="false">\r
- <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />\r
- <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">\r
+ <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" hidden="false" />\r
+ <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled." hidden="false">\r
<value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />\r
<value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />\r
</field>\r
- <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />\r
- <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />\r
- <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />\r
- <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />\r
+ <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." hidden="false" />\r
+ <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." hidden="false" />\r
+ <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." hidden="false" />\r
+ <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." hidden="false" />\r
</register>\r
<register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2" hidden="false">\r
- <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">\r
+ <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ" hidden="false">\r
<value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />\r
<value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />\r
<value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />\r
<value name="Irq" value="11" desc="Timer runs until IRQ." />\r
</field>\r
- <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />\r
- <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />\r
- <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">\r
+ <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." hidden="false" />\r
+ <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" hidden="false" />\r
+ <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations" hidden="false">\r
<value name="Equal" value="0" desc="Compare Equal " />\r
<value name="Less than" value="1" desc="Compare Less Than " />\r
<value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />\r
<value name="Greater" value="11" desc="Compare Greater Than ." />\r
<value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />\r
</field>\r
- <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />\r
+ <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." hidden="false" />\r
</register>\r
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />\r
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />\r
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true" hidden="false">\r
- <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="ZeroTerminal_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="ZeroTerminal_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0" hidden="false">\r
- <field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />\r
- <field name="fsusbio_pd_n" from="1" to="1" access="RW" resetVal="" desc="" />\r
- <field name="fsusbio_pd_pullup_n" from="2" to="2" access="RW" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_PM_ACT_CFG" address="0x400043A5" bitWidth="8" desc="Active Power Mode Configuration Register" hidden="false" />\r
- <register name="USBFS_PM_STBY_CFG" address="0x400043B5" bitWidth="8" desc="Standby Power Mode Configuration Register" hidden="false" />\r
- <register name="USBFS_PRT.PS" address="0x400051F1" bitWidth="8" desc="Port Pin State Register" hidden="false">\r
- <field name="PinState_DP" from="6" to="6" access="R" resetVal="" desc="" />\r
- <field name="PinState_DM" from="7" to="7" access="R" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_PRT_DM0" address="0x400051F2" bitWidth="8" desc="Port Drive Mode Register" hidden="false">\r
- <field name="DriveMode_DP" from="6" to="6" access="RW" resetVal="" desc="" />\r
- <field name="DriveMode_DM" from="7" to="7" access="RW" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_PRT_DM1" address="0x400051F3" bitWidth="8" desc="Port Drive Mode Register" hidden="false">\r
- <field name="PullUp_en_DP" from="6" to="6" access="RW" resetVal="" desc="" />\r
- <field name="PullUp_en_DM" from="7" to="7" access="RW" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_PRT.INP_DIS" address="0x400051F8" bitWidth="8" desc="Input buffer disable override" hidden="false">\r
- <field name="seinput_dis_dp" from="6" to="6" access="RW" resetVal="" desc="" />\r
- <field name="seinput_dis_dm" from="7" to="7" access="RW" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_EP0_DR0" address="0x40006000" bitWidth="8" desc="bmRequestType" hidden="false" />\r
- <register name="USBFS_EP0_DR1" address="0x40006001" bitWidth="8" desc="bRequest" hidden="false" />\r
- <register name="USBFS_EP0_DR2" address="0x40006002" bitWidth="8" desc="wValueLo" hidden="false" />\r
- <register name="USBFS_EP0_DR3" address="0x40006003" bitWidth="8" desc="wValueHi" hidden="false" />\r
- <register name="USBFS_EP0_DR4" address="0x40006004" bitWidth="8" desc="wIndexLo" hidden="false" />\r
- <register name="USBFS_EP0_DR5" address="0x40006005" bitWidth="8" desc="wIndexHi" hidden="false" />\r
- <register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" hidden="false" />\r
- <register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" hidden="false" />\r
- <register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0" hidden="false">\r
- <field name="device_address" from="6" to="0" access="R" resetVal="" desc="" />\r
- <field name="usb_enable" from="7" to="7" access="RW" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1" hidden="false">\r
- <field name="reg_enable" from="0" to="0" access="RW" resetVal="" desc="" />\r
- <field name="enable_lock" from="1" to="1" access="RW" resetVal="" desc="" />\r
- <field name="bus_activity" from="2" to="2" access="RW" resetVal="" desc="" />\r
- <field name="trim_offset_msb" from="3" to="3" access="RW" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_SIE_EP1_CR0" address="0x4000600E" bitWidth="8" desc="The Endpoint1 Control Register" hidden="false" />\r
- <register name="USBFS_USBIO_CR0" address="0x40006010" bitWidth="8" desc="USBIO Control Register 0" hidden="false">\r
- <field name="rd" from="0" to="0" access="R" resetVal="" desc="" />\r
- <field name="td" from="5" to="5" access="RW" resetVal="" desc="" />\r
- <field name="tse0" from="6" to="6" access="RW" resetVal="" desc="" />\r
- <field name="ten" from="7" to="7" access="RW" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_USBIO_CR1" address="0x40006012" bitWidth="8" desc="USBIO Control Register 1" hidden="false">\r
- <field name="dmo" from="0" to="0" access="R" resetVal="" desc="" />\r
- <field name="dpo" from="1" to="1" access="R" resetVal="" desc="" />\r
- <field name="usbpuen" from="2" to="2" access="RW" resetVal="" desc="" />\r
- <field name="iomode" from="5" to="5" access="RW" resetVal="" desc="" />\r
- </register>\r
- <register name="USBFS_SIE_EP2_CR0" address="0x4000601E" bitWidth="8" desc="The Endpoint2 Control Register" hidden="false" />\r
- <register name="USBFS_SIE_EP3_CR0" address="0x4000602E" bitWidth="8" desc="The Endpoint3 Control Register" hidden="false" />\r
- <register name="USBFS_SIE_EP4_CR0" address="0x4000603E" bitWidth="8" desc="The Endpoint4 Control Register" hidden="false" />\r
- <register name="USBFS_SIE_EP5_CR0" address="0x4000604E" bitWidth="8" desc="The Endpoint5 Control Register" hidden="false" />\r
- <register name="USBFS_SIE_EP6_CR0" address="0x4000605E" bitWidth="8" desc="The Endpoint6 Control Register" hidden="false" />\r
- <register name="USBFS_SIE_EP7_CR0" address="0x4000606E" bitWidth="8" desc="The Endpoint7 Control Register" hidden="false" />\r
- <register name="USBFS_SIE_EP8_CR0" address="0x4000607E" bitWidth="8" desc="The Endpoint8 Control Register" hidden="false" />\r
- <register name="USBFS_BUF_SIZE" address="0x4000608C" bitWidth="8" desc="Dedicated Endpoint Buffer Size Register" hidden="false" />\r
- <register name="USBFS_EP_ACTIVE" address="0x4000608E" bitWidth="8" desc="Endpoint Active Indication Register" hidden="false" />\r
- <register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" hidden="false" />\r
- <register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" hidden="false" />\r
+ <block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <register name="POWER_CTRL" address="0x40006008" bitWidth="32" desc="Power Control Register" hidden="true">\r
+ <field name="VBUS_VALID_OVR" from="1" to="0" access="RW" resetVal="" desc="Overrides the value received from the GPIO input buffer connected to VBUS" hidden="false">\r
+ <value name="FORCE_VALID_0" value="00" desc="Force vbus_valid = 0." />\r
+ <value name="FORCE_VALID_1" value="01" desc="Force vbus_valid = 1." />\r
+ <value name="GPIO_VALID" value="10" desc="Use vbus_valid signal from GPIO input." />\r
+ <value name="PHY_VALID" value="11" desc="Use vbus_valid signal from PHY detector." />\r
+ </field>\r
+ <field name="SUSPEND" from="2" to="2" access="RW" resetVal="" desc="Put PHY into Suspend mode. If the PHY is enabled, this bit MUST be set before entering a low power mode (DeepSleep/Hibernate)." hidden="false" />\r
+ <field name="SUSPEND_DEL" from="3" to="3" access="RW" resetVal="" desc="Delayed version of SUSPEND. Always set SUSPEND and SUSPEND_DEL together in a single register write. When taking PHY out of suspend mode, first clear SUSPEND, then clear SUSPEND_DEL at least 2us later." hidden="false" />\r
+ <field name="ISOLATE" from="4" to="4" access="RW" resetVal="" desc="Isolates the PHY outputs. Clear this bit at least 2us after vbus is known to be valid (vbus_valid=1). Isolation will be forced when vbus_valid goes low (see VBUS_VALID_OVR)." hidden="false" />\r
+ <field name="CHDET_PWR_CTL" from="6" to="5" access="RW" resetVal="" desc="Power programmability for bandgap voltage buffer in the charger detect block. See s8bg_vrefbuf public cell for more information. Default '0' is low power mode." hidden="false" />\r
+ <field name="ENABLE_DM_PULLDOWN" from="26" to="26" access="RW" resetVal="" desc="Enables the ~15k pull down on the DM, default off. The 15k pull down is needed for Data Contact Detection (DCD)." hidden="false" />\r
+ <field name="ENABLE_VBUS_PULLDOWN" from="26" to="26" access="RW" resetVal="" desc="Enables the weak pull down on the VBUS, default on, to prevent floating node crow bar currents." hidden="false" />\r
+ <field name="ENABLE_RCVR" from="27" to="27" access="RW" resetVal="" desc="Enables the differential USB receiver." hidden="false" />\r
+ <field name="ENABLE_DPO" from="28" to="28" access="RW" resetVal="" desc="Enables the single ended receiver on D+." hidden="false" />\r
+ <field name="ENABLE_DMO" from="29" to="29" access="RW" resetVal="" desc="Enables the signle ended receiver on D-." hidden="false" />\r
+ <field name="ENABLE_CHGDET" from="30" to="30" access="RW" resetVal="" desc="Enables the charger detection circuitry. After USB has connected, this circuitry can be disabled to save power." hidden="false" />\r
+ <field name="ENABLE" from="31" to="31" access="RW" resetVal="" desc="Mast enable of PHY and Charger Detector. Nothing will work until this bit is set." hidden="false" />\r
+ </register>\r
+ <register name="CR0" address="0x40006008" bitWidth="8" desc="USB Control 0 Register" hidden="false">\r
+ <field name="DEVICE_ADDRESS" from="6" to="0" access="R" resetVal="" desc="These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware." hidden="false" />\r
+ <field name="USB_ENABLE" from="7" to="7" access="RW" resetVal="" desc="This bit enables the device to respond to USB traffic." hidden="false">\r
+ <value name="Disabled" value="0" desc="Block responds to USB traffic." />\r
+ <value name="Enabled" value="1" desc="Block does not respond to USB traffic." />\r
+ </field>\r
+ </register>\r
+ <register name="INTR_CAUSE_HIGH" address="0x40006008" bitWidth="32" desc="High priority interrupt Cause register" hidden="true">\r
+ <field name="SOF_INTR" from="0" to="0" access="RW" resetVal="" desc="USB SOF Interrupt." hidden="false" />\r
+ <field name="BUS_RESET_INTR" from="1" to="1" access="RW" resetVal="" desc="BUS RESET Interrupt." hidden="false" />\r
+ <field name="EP0_INTR" from="2" to="2" access="RW" resetVal="" desc="EP0 Interrupt." hidden="false" />\r
+ <field name="LPM_INTR" from="3" to="3" access="RW" resetVal="" desc="LPM Interrupt." hidden="false" />\r
+ <field name="RESUME_INTR" from="4" to="4" access="RW" resetVal="" desc="Resume Interrupt." hidden="false" />\r
+ <field name="ARB_EP_INTR" from="7" to="7" access="RW" resetVal="" desc="Arbiter Endpoint Interrupt." hidden="false" />\r
+ <field name="EP1_INTR" from="8" to="8" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP2_INTR" from="9" to="9" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP3_INTR" from="10" to="10" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP4_INTR" from="11" to="11" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP5_INTR" from="12" to="12" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP6_INTR" from="13" to="13" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP7_INTR" from="14" to="14" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP8_INTR" from="15" to="15" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ </register>\r
+ <register name="LPM_STAT" address="0x40006008" bitWidth="32" desc="LPM Status register" hidden="true">\r
+ <field name="LPM_BESL" from="3" to="0" access="RW" resetVal="" desc="Best Effort Service Latency. This value should match either the Baseline (DeepSleep) or Deep (Hibernate) BESL in the BOS descriptor." hidden="false" />\r
+ <field name="LPM_REMOTEWAKE" from="4" to="4" access="RW" resetVal="" desc="LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request." hidden="false">\r
+ <value name="Prohibited" value="0" desc="Device is prohibited from initiating a remote wake." />\r
+ <value name="Allowed" value="1" desc="Device is allow to wake the host." />\r
+ </field>\r
+ </register>\r
+ <register name="INTR_LVL_SEL" address="0x40006008" bitWidth="32" desc="Select interrupt level for each interrupt source" hidden="true">\r
+ <field name="SOF_LVL_SEL" from="1" to="0" access="RW" resetVal="" desc="USB SOF Interrupt level select." hidden="false" />\r
+ <field name="BUS_RESET_LVL_SEL" from="3" to="2" access="RW" resetVal="" desc="BUS RESET Interrupt level select." hidden="false" />\r
+ <field name="EP0_LVL_SEL" from="5" to="4" access="RW" resetVal="" desc="EP0 Interrupt level select." hidden="false" />\r
+ <field name="LPM_LVL_SEL" from="7" to="6" access="RW" resetVal="" desc="LPM Interrupt level select." hidden="false" />\r
+ <field name="RESUME_LVL_SEL" from="9" to="8" access="RW" resetVal="" desc="Resume Interrupt level select." hidden="false" />\r
+ <field name="ARB_EP_LVL_SEL" from="15" to="14" access="RW" resetVal="" desc="Arbiter Endpoint Interrupt level select." hidden="false" />\r
+ <field name="EP1_LVL_SEL" from="17" to="16" access="RW" resetVal="" desc="EP1 Interrupt level select." hidden="false" />\r
+ <field name="EP2_LVL_SEL" from="19" to="18" access="RW" resetVal="" desc="EP2 Interrupt level select." hidden="false" />\r
+ <field name="EP3_LVL_SEL" from="21" to="20" access="RW" resetVal="" desc="EP3 Interrupt level select." hidden="false" />\r
+ <field name="EP4_LVL_SEL" from="23" to="22" access="RW" resetVal="" desc="EP4 Interrupt level select." hidden="false" />\r
+ <field name="EP5_LVL_SEL" from="25" to="24" access="RW" resetVal="" desc="EP5 Interrupt level select." hidden="false" />\r
+ <field name="EP6_LVL_SEL" from="27" to="26" access="RW" resetVal="" desc="EP6 Interrupt level select." hidden="false" />\r
+ <field name="EP7_LVL_SEL" from="29" to="28" access="RW" resetVal="" desc="EP7 Interrupt level select." hidden="false" />\r
+ <field name="EP8_LVL_SEL" from="31" to="30" access="RW" resetVal="" desc="EP8 Interrupt level select." hidden="false" />\r
+ </register>\r
+ <register name="CHGDET_CTRL" address="0x40006008" bitWidth="32" desc="Charger Detection Control Register" hidden="true">\r
+ <field name="COMP_DP" from="0" to="0" access="RW" resetVal="" desc="Connect the primary/secondary detection comparator and current sink to D+." hidden="false" />\r
+ <field name="COMP_DM" from="1" to="1" access="RW" resetVal="" desc="Connect the primary/secondary detection comparator and current sink to D-." hidden="false" />\r
+ <field name="COMP_EN" from="2" to="2" access="RW" resetVal="" desc="Enable the primary/secondary detection comparator and current sink. This bit can be written concurrently with COMP_DP/COMP_DM. Note that REF_EN must also be 1 for the comparator to work (because it receives a reference from it)." hidden="false" />\r
+ <field name="REF_DP" from="3" to="3" access="RW" resetVal="" desc="Connect the primary/secondary detection reference driver to D+." hidden="false" />\r
+ <field name="REF_DM" from="4" to="4" access="RW" resetVal="" desc="Connect the primary/secondary detection reference driver to D-." hidden="false" />\r
+ <field name="REF_EN" from="5" to="5" access="RW" resetVal="" desc="Enable the primary/secondary reference driver. This bit can be written concurrently with REF_DP/REF_DM." hidden="false" />\r
+ <field name="DCD_SRC_EN" from="6" to="6" access="RW" resetVal="" desc="Enable the Data Contact Detect current source on D+." hidden="false" />\r
+ <field name="ADFT_CTRL" from="13" to="12" access="RW" resetVal="" desc="ADFT option to bring out buffered version of voltage reference input or adft intput to ADFT output (adft_out)." hidden="false">\r
+ <value name="ADFT_NORMAL" value="00" desc="Normal operating mode, reference buffer used to generate internal references. adft_out pulled low." />\r
+ <value name="ADFT_VBG" value="01" desc="Use reference buffer to bring out voltage reference input (vbg) onto adft_out." />\r
+ <value name="ADFT_DONTUSE" value="10" desc="Illegal - do not use." />\r
+ <value name="ADFT_ADFTIN" value="11" desc="Use reference buffer to bring out buffered version of system level adft input (adft_in) onto adft_out." />\r
+ </field>\r
+ <field name="COMP_OUT" from="31" to="31" access="RW" resetVal="" desc="Output of the primary/secondary detection comparator. This output is not filtered or debounced and must be polled in software." hidden="false" />\r
+ </register>\r
+ <register name="LPM_CTRL" address="0x40006008" bitWidth="32" desc="LPM Control Register" hidden="true">\r
+ <field name="LPM_EN" from="0" to="0" access="RW" resetVal="" desc="LPM enable." hidden="false">\r
+ <value name="Disable" value="0" desc="LPM token will not get a response (backward compatibility mode)." />\r
+ <value name="Enable" value="1" desc="LPM token will get a handshake response (ACK, STALL, NYET or NAK). A STALL will be sent if the bLinkState is not 0001b. A NYET, NAK or ACK response will be sent depending on the NYET_EN and LPM_ACK_RESP bits below." />\r
+ </field>\r
+ <field name="LPM_ACK_RESP" from="1" to="1" access="RW" resetVal="" desc="LPM ACK response enable (if LPM_EN=1), to allow firmware to refuse a low power request." hidden="false">\r
+ <value name="NYET_NACK" value="0" desc="A LPM token will get a NYET or NAK (depending on NYET_EN bit below) response and the device will NOT go to a low power mode." />\r
+ <value name="ACK" value="1" desc="A LPM token will get an ACK response and the device will go to the requested low power mode." />\r
+ </field>\r
+ <field name="NYET_EN" from="2" to="2" access="RW" resetVal="" desc="Allow firmware to choose which response to use for an LPM token (LPM_EN=1) when the device is NOT ready to go to the requested low power mode (LPM_ACK_RESP=0)." hidden="false">\r
+ <value name="NYET" value="0" desc="A LPM token will get an NAK response (indicating a CRC error), the host is expected to repeat the LPM token." />\r
+ <value name="NACK" value="1" desc="A LPM token will get a NYET response." />\r
+ </field>\r
+ <field name="SUB_RESP" from="4" to="4" access="RW" resetVal="" desc="Enable a STALL response for all undefined SubPIDs, i.e. other than LPM (0011b). If not enabled then there will be no response (Error) for the undefined SubPIDs." hidden="false" />\r
+ </register>\r
+ <register name="INTR_SIE_MASK" address="0x40006008" bitWidth="32" desc="USB SOF, BUS RESET and EP0 Interrupt Mask" hidden="true">\r
+ <field name="SOF_INTR" from="0" to="0" access="RW" resetVal="" desc="USB SOF Interrupt." hidden="false" />\r
+ <field name="BUS_RESET_INTR" from="1" to="1" access="RW" resetVal="" desc="BUS RESET Interrupt." hidden="false" />\r
+ <field name="EP0_INTR" from="2" to="2" access="RW" resetVal="" desc="EP0 Interrupt." hidden="false" />\r
+ <field name="LPM_INTR" from="3" to="3" access="RW" resetVal="" desc="LPM Interrupt." hidden="false" />\r
+ <field name="RESUME_INTR" from="4" to="4" access="RW" resetVal="" desc="Resume Interrupt." hidden="false" />\r
+ </register>\r
+ <register name="INTR_CAUSE_LO" address="0x40006008" bitWidth="32" desc="Low priority interrupt Cause register" hidden="true">\r
+ <field name="SOF_INTR" from="0" to="0" access="RW" resetVal="" desc="USB SOF Interrupt." hidden="false" />\r
+ <field name="BUS_RESET_INTR" from="1" to="1" access="RW" resetVal="" desc="BUS RESET Interrupt." hidden="false" />\r
+ <field name="EP0_INTR" from="2" to="2" access="RW" resetVal="" desc="EP0 Interrupt." hidden="false" />\r
+ <field name="LPM_INTR" from="3" to="3" access="RW" resetVal="" desc="LPM Interrupt." hidden="false" />\r
+ <field name="RESUME_INTR" from="4" to="4" access="RW" resetVal="" desc="Resume Interrupt." hidden="false" />\r
+ <field name="ARB_EP_INTR" from="7" to="7" access="RW" resetVal="" desc="Arbiter Endpoint Interrupt." hidden="false" />\r
+ <field name="EP1_INTR" from="8" to="8" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP2_INTR" from="9" to="9" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP3_INTR" from="10" to="10" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP4_INTR" from="11" to="11" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP5_INTR" from="12" to="12" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP6_INTR" from="13" to="13" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP7_INTR" from="14" to="14" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP8_INTR" from="15" to="15" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ </register>\r
+ <register name="INTR_CAUSE_MED" address="0x40006008" bitWidth="32" desc="Medium priority interrupt Cause register" hidden="true">\r
+ <field name="SOF_INTR" from="0" to="0" access="RW" resetVal="" desc="USB SOF Interrupt." hidden="false" />\r
+ <field name="BUS_RESET_INTR" from="1" to="1" access="RW" resetVal="" desc="BUS RESET Interrupt." hidden="false" />\r
+ <field name="EP0_INTR" from="2" to="2" access="RW" resetVal="" desc="EP0 Interrupt." hidden="false" />\r
+ <field name="LPM_INTR" from="3" to="3" access="RW" resetVal="" desc="LPM Interrupt." hidden="false" />\r
+ <field name="RESUME_INTR" from="4" to="4" access="RW" resetVal="" desc="Resume Interrupt." hidden="false" />\r
+ <field name="ARB_EP_INTR" from="7" to="7" access="RW" resetVal="" desc="Arbiter Endpoint Interrupt." hidden="false" />\r
+ <field name="EP1_INTR" from="8" to="8" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP2_INTR" from="9" to="9" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP3_INTR" from="10" to="10" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP4_INTR" from="11" to="11" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP5_INTR" from="12" to="12" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP6_INTR" from="13" to="13" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP7_INTR" from="14" to="14" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ <field name="EP8_INTR" from="15" to="15" access="RW" resetVal="" desc="EP1 Interrupt." hidden="false" />\r
+ </register>\r
+ <register name="`INTR_SIE" address="0x40006008" bitWidth="32" desc="USB SOF, BUS RESET and EP0 Interrupt Status" hidden="true">\r
+ <field name="SOF_INTR" from="0" to="0" access="RW" resetVal="" desc="USB SOF Interrupt." hidden="false" />\r
+ <field name="BUS_RESET_INTR" from="1" to="1" access="RW" resetVal="" desc="BUS RESET Interrupt." hidden="false" />\r
+ <field name="EP0_INTR" from="2" to="2" access="RW" resetVal="" desc="EP0 Interrupt." hidden="false" />\r
+ <field name="LPM_INTR" from="3" to="3" access="RW" resetVal="" desc="LPM Interrupt." hidden="false" />\r
+ <field name="RESUME_INTR" from="4" to="4" access="RW" resetVal="" desc="Resume Interrupt." hidden="false" />\r
+ </register>\r
+ <register name="CR1" address="0x40006009" bitWidth="8" desc="USB Control 1 Register" hidden="false">\r
+ <field name="REG_ENABLE" from="0" to="0" access="R" resetVal="" desc="This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply." hidden="false">\r
+ <value name="Disabled" value="0" desc="Regulator for 5V is disabled." />\r
+ <value name="Enabled" value="1" desc="Regulator for 5V is enabled." />\r
+ </field>\r
+ <field name="ENABLE_LOCK" from="1" to="1" access="RW" resetVal="" desc="This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation." hidden="false" />\r
+ <field name="BUS_ACTIVITY" from="2" to="2" access="RW" resetVal="" desc="The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High value until firmware clears it." hidden="false" />\r
+ <field name="TRIM_OFFSET_MSB" from="3" to="3" access="RW" resetVal="" desc="This bit enables trim bit[7]." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP_INT_EN" address="0x4000600A" bitWidth="8" desc="USB SIE Data Endpoints Interrupt Enable Register" hidden="false">\r
+ <field name="EP1_INTR_EN" from="0" to="0" access="RW" resetVal="" desc="Enables interrupt for EP1." hidden="false" />\r
+ <field name="EP2_INTR_EN" from="1" to="1" access="RW" resetVal="" desc="Enables interrupt for EP2." hidden="false" />\r
+ <field name="EP3_INTR_EN" from="2" to="2" access="RW" resetVal="" desc="Enables interrupt for EP3." hidden="false" />\r
+ <field name="EP4_INTR_EN" from="3" to="3" access="RW" resetVal="" desc="Enables interrupt for EP4." hidden="false" />\r
+ <field name="EP5_INTR_EN" from="4" to="4" access="RW" resetVal="" desc="Enables interrupt for EP5." hidden="false" />\r
+ <field name="EP6_INTR_EN" from="5" to="5" access="RW" resetVal="" desc="Enables interrupt for EP6." hidden="false" />\r
+ <field name="EP7_INTR_EN" from="6" to="6" access="RW" resetVal="" desc="Enables interrupt for EP7." hidden="false" />\r
+ <field name="EP8_INTR_EN" from="7" to="7" access="RW" resetVal="" desc="Enables interrupt for EP8." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP_INT_SR" address="0x4000600B" bitWidth="8" desc="SIE Data Endpoint Interrupt Status Register" hidden="false">\r
+ <field name="EP1_INTR" from="0" to="0" access="RW" resetVal="" desc="Interrupt status for EP1." hidden="false" />\r
+ <field name="EP2_INTR" from="1" to="1" access="RW" resetVal="" desc="Interrupt status for EP2." hidden="false" />\r
+ <field name="EP3_INTR" from="2" to="2" access="RW" resetVal="" desc="Interrupt status for EP3." hidden="false" />\r
+ <field name="EP4_INTR" from="3" to="3" access="RW" resetVal="" desc="Interrupt status for EP4." hidden="false" />\r
+ <field name="EP5_INTR" from="4" to="4" access="RW" resetVal="" desc="Interrupt status for EP5." hidden="false" />\r
+ <field name="EP6_INTR" from="5" to="5" access="RW" resetVal="" desc="Interrupt status for EP6." hidden="false" />\r
+ <field name="EP7_INTR" from="6" to="6" access="RW" resetVal="" desc="Interrupt status for EP7." hidden="false" />\r
+ <field name="EP8_INTR" from="7" to="7" access="RW" resetVal="" desc="Interrupt status for EP8." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP1_CNT0" address="0x4000600C" bitWidth="8" desc="SIE Endpoint 1 Count0 Register" hidden="false">\r
+ <field name="DATA_COUNT_MSB" from="2" to="0" access="RW" resetVal="" desc="These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="DATA_ERROR - 0, DATA_VALID - 1." hidden="false" />\r
+ <field name="DATA_TOGGLE" from="7" to="7" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP1_CNT1" address="0x4000600D" bitWidth="8" desc="SIE Endpoint 1 Count1 Register" hidden="false">\r
+ <field name="DATA_COUNT" from="7" to="0" access="RW" resetVal="" desc="These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP1_CR0" address="0x4000600E" bitWidth="8" desc="SIE Endpoint 1 Control Register" hidden="false">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="USBIO_CR0" address="0x40006010" bitWidth="8" desc="USBIO Control 0 Register" hidden="false">\r
+ <field name="RD" from="0" to="0" access="R" resetVal="" desc="Received Data. This read only bit gives the state of the USB differential receiver." hidden="false">\r
+ <value name="DIFF_LOW" value="0" desc="D+ less than D- (K state), or D+=D-=0 (SE0)." />\r
+ <value name="DIFF_HIGH" value="1" desc="D+ greater than D- (J state)." />\r
+ </field>\r
+ <field name="TD" from="5" to="5" access="RW" resetVal="" desc="Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1." hidden="false">\r
+ <value name="DIFF_K" value="0" desc="Force USB K state (D+ is low D- is high)." />\r
+ <value name="DIFF_J" value="1" desc="Force USB J state (D+ is high D- is low)." />\r
+ </field>\r
+ <field name="TSE0" from="6" to="6" access="RW" resetVal="" desc="Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0." hidden="false" />\r
+ <field name="TEN" from="7" to="7" access="RW" resetVal="" desc="USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually transmitting is to force a resume state on the bus." hidden="false" />\r
+ </register>\r
+ <register name="USBIO_CR1" address="0x40006012" bitWidth="8" desc="USBIO Control 1 Register" hidden="false">\r
+ <field name="DMO" from="0" to="0" access="R" resetVal="" desc="This read only bit gives the state of the D- pin." hidden="false" />\r
+ <field name="DPO" from="1" to="1" access="R" resetVal="" desc="This read only bit gives the state of the D+ pin." hidden="false" />\r
+ <field name="USBPUEN" from="2" to="2" access="RW" resetVal="" desc="This bit enables the connection of the internal 1.5 k pull up resistor on the D+ pin." hidden="false" />\r
+ <field name="IOMODE" from="5" to="5" access="RW" resetVal="" desc="This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins." hidden="false">\r
+ <value name="Bit-banged" value="0" desc="Bit-banged mode for Dm and Dp." />\r
+ <value name="USB" value="1" desc="USB block controls Dm and Dp." />\r
+ </field>\r
+ </register>\r
+ <register name="DYN_RECONFIG" address="0x40006014" bitWidth="8" desc="USB Dynamic reconfiguration Register" hidden="true">\r
+ <field name="DYN_CONFIG_EN" from="0" to="0" access="RW" resetVal="" desc="This bit is used to enable the dynamic re-configuration for the selected EP. If set to 1, indicates the reconfiguration required for selected EP. Use 0 for EP1, 1 for EP2, etc." hidden="false" />\r
+ <field name="DYN_RECONFIG_EPNO" from="3" to="1" access="RW" resetVal="" desc="These bits indicates the EP number for which reconfiguration is required when dyn_config_en bit is set to 1." hidden="false" />\r
+ <field name="DYN_RECONFIG_RDY_STS" from="4" to="4" access="R" resetVal="" desc="This bit indicates the ready status for the dynamic reconfiguration, when set to 1, indicates the block is ready for reconfiguration." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP2_CNT0" address="0x4000601C" bitWidth="8" desc="SIE Endpoint 1 Count0 Register" hidden="false">\r
+ <field name="DATA_COUNT_MSB" from="2" to="0" access="RW" resetVal="" desc="These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="DATA_ERROR - 0, DATA_VALID - 1." hidden="false" />\r
+ <field name="DATA_TOGGLE" from="7" to="7" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP2_CNT1" address="0x4000601D" bitWidth="8" desc="SIE Endpoint 1 Count1 Register" hidden="false">\r
+ <field name="DATA_COUNT" from="7" to="0" access="RW" resetVal="" desc="These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP2_CR0" address="0x4000601E" bitWidth="8" desc="SIE Endpoint 1 Control Register" hidden="false">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="EP0_CR" address="0x40006028" bitWidth="8" desc="Endpoint0 control Register" hidden="false">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="EP0_CNT" address="0x40006029" bitWidth="8" desc="Endpoint0 control Register" hidden="false">\r
+ <field name="BYTE_COUNT" from="3" to="0" access="RW" resetVal="" desc="These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings." hidden="false">\r
+ <value name="DATA_ERROR" value="0" desc="No ACK'd transactions since bit was last cleared." />\r
+ <value name="DATA_VALID" value="1" desc="Indicates a transaction ended with an ACK." />\r
+ </field>\r
+ <field name="DATA_TOGGLE" from="5" to="5" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP3_CNT0" address="0x4000602C" bitWidth="8" desc="SIE Endpoint 1 Count0 Register" hidden="false">\r
+ <field name="DATA_COUNT_MSB" from="2" to="0" access="RW" resetVal="" desc="These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="DATA_ERROR - 0, DATA_VALID - 1." hidden="false" />\r
+ <field name="DATA_TOGGLE" from="7" to="7" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP3_CNT1" address="0x4000602D" bitWidth="8" desc="SIE Endpoint 1 Count1 Register" hidden="false">\r
+ <field name="DATA_COUNT" from="7" to="0" access="RW" resetVal="" desc="These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP3_CR0" address="0x4000602E" bitWidth="8" desc="SIE Endpoint 1 Control Register" hidden="false">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP4_CNT0" address="0x4000603C" bitWidth="8" desc="SIE Endpoint 1 Count0 Register" hidden="false">\r
+ <field name="DATA_COUNT_MSB" from="2" to="0" access="RW" resetVal="" desc="These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="DATA_ERROR - 0, DATA_VALID - 1." hidden="false" />\r
+ <field name="DATA_TOGGLE" from="7" to="7" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP4_CNT1" address="0x4000603D" bitWidth="8" desc="SIE Endpoint 1 Count1 Register" hidden="false">\r
+ <field name="DATA_COUNT" from="7" to="0" access="RW" resetVal="" desc="These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP4_CR0" address="0x4000603E" bitWidth="8" desc="SIE Endpoint 1 Control Register" hidden="false">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP5_CNT0" address="0x4000604C" bitWidth="8" desc="SIE Endpoint 1 Count0 Register" hidden="true">\r
+ <field name="DATA_COUNT_MSB" from="2" to="0" access="RW" resetVal="" desc="These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="DATA_ERROR - 0, DATA_VALID - 1." hidden="false" />\r
+ <field name="DATA_TOGGLE" from="7" to="7" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP5_CNT1" address="0x4000604D" bitWidth="8" desc="SIE Endpoint 1 Count1 Register" hidden="true">\r
+ <field name="DATA_COUNT" from="7" to="0" access="RW" resetVal="" desc="These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP5_CR0" address="0x4000604E" bitWidth="8" desc="SIE Endpoint 1 Control Register" hidden="true">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP6_CNT0" address="0x4000605C" bitWidth="8" desc="SIE Endpoint 1 Count0 Register" hidden="true">\r
+ <field name="DATA_COUNT_MSB" from="2" to="0" access="RW" resetVal="" desc="These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="DATA_ERROR - 0, DATA_VALID - 1." hidden="false" />\r
+ <field name="DATA_TOGGLE" from="7" to="7" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP6_CNT1" address="0x4000605D" bitWidth="8" desc="SIE Endpoint 1 Count1 Register" hidden="true">\r
+ <field name="DATA_COUNT" from="7" to="0" access="RW" resetVal="" desc="These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP6_CR0" address="0x4000605E" bitWidth="8" desc="SIE Endpoint 1 Control Register" hidden="true">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP7_CNT0" address="0x4000606C" bitWidth="8" desc="SIE Endpoint 1 Count0 Register" hidden="true">\r
+ <field name="DATA_COUNT_MSB" from="2" to="0" access="RW" resetVal="" desc="These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="DATA_ERROR - 0, DATA_VALID - 1." hidden="false" />\r
+ <field name="DATA_TOGGLE" from="7" to="7" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP7_CNT1" address="0x4000606D" bitWidth="8" desc="SIE Endpoint 1 Count1 Register" hidden="true">\r
+ <field name="DATA_COUNT" from="7" to="0" access="RW" resetVal="" desc="These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP7_CR0" address="0x4000606E" bitWidth="8" desc="SIE Endpoint 1 Control Register" hidden="true">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP8_CNT0" address="0x4000607C" bitWidth="8" desc="SIE Endpoint 1 Count0 Register" hidden="true">\r
+ <field name="DATA_COUNT_MSB" from="2" to="0" access="RW" resetVal="" desc="These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information." hidden="false" />\r
+ <field name="DATA_VALID" from="4" to="4" access="RW" resetVal="" desc="DATA_ERROR - 0, DATA_VALID - 1." hidden="false" />\r
+ <field name="DATA_TOGGLE" from="7" to="7" access="RW" resetVal="" desc="This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP8_CNT1" address="0x4000607D" bitWidth="8" desc="SIE Endpoint 1 Count1 Register" hidden="true">\r
+ <field name="DATA_COUNT" from="7" to="0" access="RW" resetVal="" desc="These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction." hidden="false" />\r
+ </register>\r
+ <register name="SIE_EP8_CR0" address="0x4000607E" bitWidth="8" desc="SIE Endpoint 1 Control Register" hidden="true">\r
+ <field name="MODE" from="3" to="0" access="RW" resetVal="" desc="The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint." hidden="false">\r
+ <value name="DISABLE" value="0000" desc="Ignore all USB traffic to this endpoint." />\r
+ <value name="NAK_INOUT" value="0001" desc="SETUP: Accept, IN: NAK, OUT: NAK." />\r
+ <value name="STATUS_OUT_ONLY" value="0010" desc="SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others." />\r
+ <value name="STALL_INOUT" value="0011" desc="SETUP: Accept, IN: STALL, OUT: STALL." />\r
+ <value name="ISO_OUT" value="0101" desc="SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token." />\r
+ <value name="STATUS_IN_ONLY" value="0110" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Stall." />\r
+ <value name="ISO_IN" value="0111" desc="SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore." />\r
+ <value name="NAK_OUT" value="1000" desc="SETUP: Ignore, IN: Ignore, OUT: NAK." />\r
+ <value name="ACK_OUT" value="1001" desc="SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token." />\r
+ <value name="ACK_OUT_STATUS_IN" value="1011" desc="SETUP: Accept, IN: Respond with 0B data, OUT: Accept data." />\r
+ <value name="NAK_IN" value="1100" desc="SETUP: Ignore, IN: NAK, OUT: Ignore." />\r
+ <value name="ACK_IN" value="1101" desc="SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore" />\r
+ <value name="ACK_IN STATUS OUT" value="1111" desc="SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others." />\r
+ </field>\r
+ <field name="ACKED_TXN" from="4" to="4" access="RW" resetVal="" desc="ACKED_NO - 0, ACKED_YES - 1." hidden="false" />\r
+ <field name="NAK_INT_EN" from="5" to="5" access="RW" resetVal="" desc="When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK." hidden="false" />\r
+ <field name="ERR_IN_TXN" from="6" to="6" access="RW" resetVal="" desc="The Error in transaction bit is set whenever an error is detected." hidden="false" />\r
+ <field name="STALL" from="7" to="7" access="RW" resetVal="" desc="When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes." hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP1_CFG" address="0x40006080" bitWidth="8" desc="Arbiter Endpoint 1 Configuration Register" hidden="false">\r
+ <field name="IN_DATA_RDY" from="0" to="0" access="RW" resetVal="" desc="Indication that Endpoint Packet Data is Ready in Main memory" hidden="false" />\r
+ <field name="DMA_REQ" from="1" to="1" access="RW" resetVal="" desc="Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." hidden="false" />\r
+ <field name="CRC_BYPASS" from="2" to="2" access="RW" resetVal="" desc="CRC_NORMAL - 0, CRC_BYPASS - 1" hidden="false" />\r
+ <field name="RESET_PTR" from="3" to="3" access="RW" resetVal="" desc="RESET_KRYPTON - 0, RESET_NORMAL - 1" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP1_INT_EN" address="0x40006081" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Enable Register" hidden="false">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP1_INT_SR" address="0x40006082" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Status Register" hidden="false">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW1_WA" address="0x40006084" bitWidth="8" desc="Arbiter Endpoint 1 Write Address LSB Register" hidden="false">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for EP." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW1_WA_MSB" address="0x40006085" bitWidth="8" desc="Arbiter Endpoint 1 Write Address MSB Register" hidden="false">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW1_RA" address="0x40006086" bitWidth="8" desc="Arbiter Endpoint 1 Read Address LSB Register" hidden="false">\r
+ <field name="RA8" from="7" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW1_RA_MSB" address="0x40006087" bitWidth="8" desc="Arbiter Endpoint 1 Read Address MSB Register" hidden="false">\r
+ <field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="BUF_SIZE" address="0x4000608C" bitWidth="8" desc="Dedicated Endpoint Buffer Size Register" hidden="true">\r
+ <field name="IN_BUF" from="3" to="0" access="RW" resetVal="" desc="Buffer size for IN Endpoints: 1 - 2 bytes, 2 - 4 bytes; 9 - 512 bytes." hidden="false" />\r
+ <field name="OUT_BUF" from="7" to="4" access="RW" resetVal="" desc="Buffer size for OUT Endpoints: 1 - 2 bytes, 2 - 4 bytes; 9 - 512 bytes." hidden="false" />\r
+ </register>\r
+ <register name="EP_ACTIVE" address="0x4000608E" bitWidth="8" desc="Endpoint Active Indication Register" hidden="true">\r
+ <field name="EP1_ACT" from="0" to="0" access="R" resetVal="" desc="Indicates that EP1 is currently active" hidden="false" />\r
+ <field name="EP2_ACT" from="1" to="1" access="R" resetVal="" desc="Indicates that EP2 is currently active" hidden="false" />\r
+ <field name="EP3_ACT" from="2" to="2" access="R" resetVal="" desc="Indicates that EP3 is currently active" hidden="false" />\r
+ <field name="EP4_ACT" from="3" to="3" access="R" resetVal="" desc="Indicates that EP4 is currently active" hidden="false" />\r
+ <field name="EP5_ACT" from="4" to="4" access="R" resetVal="" desc="Indicates that EP5 is currently active" hidden="false" />\r
+ <field name="EP6_ACT" from="5" to="5" access="R" resetVal="" desc="Indicates that EP6 is currently active6" hidden="false" />\r
+ <field name="EP7_ACT" from="6" to="6" access="R" resetVal="" desc="Indicates that EP7 is currently active" hidden="false" />\r
+ <field name="EP8_ACT" from="7" to="7" access="R" resetVal="" desc="Indicates that EP8 is currently active" hidden="false" />\r
+ </register>\r
+ <register name="EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" hidden="true">\r
+ <field name="EP1_TYP" from="0" to="0" access="RW" resetVal="" desc="Endpoint Type Indication." hidden="false">\r
+ <value name="EP_IN" value="0" desc="IN outpoint." />\r
+ <value name="EP_OUT" value="1" desc="OUT outpoint." />\r
+ </field>\r
+ <field name="EP2_TYP" from="1" to="1" access="RW" resetVal="" desc="Endpoint Type Indication." hidden="false">\r
+ <value name="EP_IN" value="0" desc="IN outpoint." />\r
+ <value name="EP_OUT" value="1" desc="OUT outpoint." />\r
+ </field>\r
+ <field name="EP3_TYP" from="2" to="2" access="RW" resetVal="" desc="Endpoint Type Indication." hidden="false">\r
+ <value name="EP_IN" value="0" desc="IN outpoint." />\r
+ <value name="EP_OUT" value="1" desc="OUT outpoint." />\r
+ </field>\r
+ <field name="EP4_TYP" from="3" to="3" access="RW" resetVal="" desc="Endpoint Type Indication." hidden="false">\r
+ <value name="EP_IN" value="0" desc="IN outpoint." />\r
+ <value name="EP_OUT" value="1" desc="OUT outpoint." />\r
+ </field>\r
+ <field name="EP5_TYP" from="4" to="4" access="RW" resetVal="" desc="Endpoint Type Indication." hidden="false">\r
+ <value name="EP_IN" value="0" desc="IN outpoint." />\r
+ <value name="EP_OUT" value="1" desc="OUT outpoint." />\r
+ </field>\r
+ <field name="EP6_TYP" from="5" to="5" access="RW" resetVal="" desc="Endpoint Type Indication." hidden="false">\r
+ <value name="EP_IN" value="0" desc="IN outpoint." />\r
+ <value name="EP_OUT" value="1" desc="OUT outpoint." />\r
+ </field>\r
+ <field name="EP7_TYP" from="6" to="6" access="RW" resetVal="" desc="Endpoint Type Indication." hidden="false">\r
+ <value name="EP_IN" value="0" desc="IN outpoint." />\r
+ <value name="EP_OUT" value="1" desc="OUT outpoint." />\r
+ </field>\r
+ <field name="EP8_TYP" from="7" to="7" access="RW" resetVal="" desc="Endpoint Type Indication." hidden="false">\r
+ <value name="EP_IN" value="0" desc="IN outpoint." />\r
+ <value name="EP_OUT" value="1" desc="OUT outpoint." />\r
+ </field>\r
+ </register>\r
+ <register name="ARB_EP2_CFG" address="0x40006090" bitWidth="8" desc="Arbiter Endpoint 1 Configuration Register" hidden="false">\r
+ <field name="IN_DATA_RDY" from="0" to="0" access="RW" resetVal="" desc="Indication that Endpoint Packet Data is Ready in Main memory" hidden="false" />\r
+ <field name="DMA_REQ" from="1" to="1" access="RW" resetVal="" desc="Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." hidden="false" />\r
+ <field name="CRC_BYPASS" from="2" to="2" access="RW" resetVal="" desc="CRC_NORMAL - 0, CRC_BYPASS - 1" hidden="false" />\r
+ <field name="RESET_PTR" from="3" to="3" access="RW" resetVal="" desc="RESET_KRYPTON - 0, RESET_NORMAL - 1" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP2_INT_EN" address="0x40006091" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Enable Register" hidden="false">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP2_INT_SR" address="0x40006092" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Status Register" hidden="false">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW2_WA" address="0x40006094" bitWidth="8" desc="Arbiter Endpoint 1 Write Address LSB Register" hidden="false">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for EP." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW2_WA_MSB" address="0x40006095" bitWidth="8" desc="Arbiter Endpoint 1 Write Address MSB Register" hidden="false">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW2_RA" address="0x40006096" bitWidth="8" desc="Arbiter Endpoint 1 Read Address LSB Register" hidden="false">\r
+ <field name="RA8" from="7" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW2_RA_MSB" address="0x40006097" bitWidth="8" desc="Arbiter Endpoint 1 Read Address MSB Register" hidden="false">\r
+ <field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_CFG" address="0x4000609C" bitWidth="8" desc="Arbiter configuration register" hidden="false">\r
+ <field name="AUTO_MEM" from="4" to="4" access="RW" resetVal="" desc="Enables Auto Memory Configuration. Manual memory configuration by default." hidden="false" />\r
+ <field name="DMA_CFG" from="6" to="5" access="RW" resetVal="" desc="DMA Access Configuration." hidden="false">\r
+ <value name="DMA_NONE" value="00" desc="No DMA." />\r
+ <value name="DMA_MANUAL" value="01" desc="Manual DMA." />\r
+ <value name="DMA_AUTO" value="10" desc="Auto DMA." />\r
+ </field>\r
+ <field name="CFG_CMP" from="7" to="7" access="RW" resetVal="" desc="Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required." hidden="false" />\r
+ </register>\r
+ <register name="USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Control 0 Register" hidden="false">\r
+ <field name="CSR_CLK_EN" from="7" to="7" access="RW" resetVal="" desc="Clock Enable for Core Logic clocked by AHB bus clock." hidden="false">\r
+ <value name="Disabled" value="0" desc="Disables clock to UBS block." />\r
+ <value name="Enabled" value="1" desc="Enables clock to UBS block." />\r
+ </field>\r
+ </register>\r
+ <register name="ARB_INT_EN" address="0x4000609E" bitWidth="8" desc="Arbiter Interrupt Enable Register" hidden="false">\r
+ <field name="EP1_INTR_EN" from="0" to="0" access="RW" resetVal="" desc="Enables interrupt for EP1." hidden="false" />\r
+ <field name="EP2_INTR_EN" from="1" to="1" access="RW" resetVal="" desc="Enables interrupt for EP2." hidden="false" />\r
+ <field name="EP3_INTR_EN" from="2" to="2" access="RW" resetVal="" desc="Enables interrupt for EP3." hidden="false" />\r
+ <field name="EP4_INTR_EN" from="3" to="3" access="RW" resetVal="" desc="Enables interrupt for EP4." hidden="false" />\r
+ <field name="EP5_INTR_EN" from="4" to="4" access="RW" resetVal="" desc="Enables interrupt for EP5." hidden="false" />\r
+ <field name="EP6_INTR_EN" from="5" to="5" access="RW" resetVal="" desc="Enables interrupt for EP6." hidden="false" />\r
+ <field name="EP7_INTR_EN" from="6" to="6" access="RW" resetVal="" desc="Enables interrupt for EP7." hidden="false" />\r
+ <field name="EP8_INTR_EN" from="7" to="7" access="RW" resetVal="" desc="Enables interrupt for EP8." hidden="false" />\r
+ </register>\r
+ <register name="ARB_INT_SR" address="0x4000609F" bitWidth="8" desc="Arbiter Interrupt Status" hidden="false">\r
+ <field name="EP1_INTR" from="0" to="0" access="R" resetVal="" desc="Interrupt status for EP1." hidden="false" />\r
+ <field name="EP2_INTR" from="1" to="1" access="R" resetVal="" desc="Interrupt status for EP2." hidden="false" />\r
+ <field name="EP3_INTR" from="2" to="2" access="R" resetVal="" desc="Interrupt status for EP3." hidden="false" />\r
+ <field name="EP4_INTR" from="3" to="3" access="R" resetVal="" desc="Interrupt status for EP4." hidden="false" />\r
+ <field name="EP5_INTR" from="4" to="4" access="R" resetVal="" desc="Interrupt status for EP5." hidden="false" />\r
+ <field name="EP6_INTR" from="5" to="5" access="R" resetVal="" desc="Interrupt status for EP6." hidden="false" />\r
+ <field name="EP7_INTR" from="6" to="6" access="R" resetVal="" desc="Interrupt status for EP7." hidden="false" />\r
+ <field name="EP8_INTR" from="7" to="7" access="R" resetVal="" desc="Interrupt status for EP8." hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP3_CFG" address="0x400060A0" bitWidth="8" desc="Arbiter Endpoint 1 Configuration Register" hidden="false">\r
+ <field name="IN_DATA_RDY" from="0" to="0" access="RW" resetVal="" desc="Indication that Endpoint Packet Data is Ready in Main memory" hidden="false" />\r
+ <field name="DMA_REQ" from="1" to="1" access="RW" resetVal="" desc="Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." hidden="false" />\r
+ <field name="CRC_BYPASS" from="2" to="2" access="RW" resetVal="" desc="CRC_NORMAL - 0, CRC_BYPASS - 1" hidden="false" />\r
+ <field name="RESET_PTR" from="3" to="3" access="RW" resetVal="" desc="RESET_KRYPTON - 0, RESET_NORMAL - 1" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP3_INT_EN" address="0x400060A1" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Enable Register" hidden="false">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP3_INT_SR" address="0x400060A2" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Status Register" hidden="false">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW3_WA" address="0x400060A4" bitWidth="8" desc="Arbiter Endpoint 1 Write Address LSB Register" hidden="false">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for EP." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW3_WA_MSB" address="0x400060A5" bitWidth="8" desc="Arbiter Endpoint 1 Write Address MSB Register" hidden="false">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW3_RA" address="0x400060A6" bitWidth="8" desc="Arbiter Endpoint 1 Read Address LSB Register" hidden="false">\r
+ <field name="RA8" from="7" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW3_RA_MSB" address="0x400060A7" bitWidth="8" desc="Arbiter Endpoint 1 Read Address MSB Register" hidden="false">\r
+ <field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="CWA" address="0x400060AC" bitWidth="8" desc="Common Area Write Address LSB Register" hidden="true">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for Common Area." hidden="false" />\r
+ </register>\r
+ <register name="CWA_MSB" address="0x400060AD" bitWidth="8" desc="Common Area Write Address LSB Register" hidden="true">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for Common Area MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP4_CFG" address="0x400060B0" bitWidth="8" desc="Arbiter Endpoint 1 Configuration Register" hidden="false">\r
+ <field name="IN_DATA_RDY" from="0" to="0" access="RW" resetVal="" desc="Indication that Endpoint Packet Data is Ready in Main memory" hidden="false" />\r
+ <field name="DMA_REQ" from="1" to="1" access="RW" resetVal="" desc="Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." hidden="false" />\r
+ <field name="CRC_BYPASS" from="2" to="2" access="RW" resetVal="" desc="CRC_NORMAL - 0, CRC_BYPASS - 1" hidden="false" />\r
+ <field name="RESET_PTR" from="3" to="3" access="RW" resetVal="" desc="RESET_KRYPTON - 0, RESET_NORMAL - 1" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP4_INT_EN" address="0x400060B1" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Enable Register" hidden="false">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP4_INT_SR" address="0x400060B2" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Status Register" hidden="false">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW4_WA" address="0x400060B4" bitWidth="8" desc="Arbiter Endpoint 1 Write Address LSB Register" hidden="false">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for EP." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW4_WA_MSB" address="0x400060B5" bitWidth="8" desc="Arbiter Endpoint 1 Write Address MSB Register" hidden="false">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW4_RA" address="0x400060B6" bitWidth="8" desc="Arbiter Endpoint 1 Read Address LSB Register" hidden="false">\r
+ <field name="RA8" from="7" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW4_RA_MSB" address="0x400060B7" bitWidth="8" desc="Arbiter Endpoint 1 Read Address MSB Register" hidden="false">\r
+ <field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="DMA_THRES" address="0x400060BC" bitWidth="8" desc="DMA Burst / Threshold Configuration LSB Register" hidden="true">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="DMA Threshold count." hidden="false" />\r
+ </register>\r
+ <register name="DMA_THRES_MSB" address="0x400060BD" bitWidth="8" desc="DMA Burst / Threshold Configuration LSB Register" hidden="true">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="DMA Threshold count MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP5_CFG" address="0x400060C0" bitWidth="8" desc="Arbiter Endpoint 1 Configuration Register" hidden="true">\r
+ <field name="IN_DATA_RDY" from="0" to="0" access="RW" resetVal="" desc="Indication that Endpoint Packet Data is Ready in Main memory" hidden="false" />\r
+ <field name="DMA_REQ" from="1" to="1" access="RW" resetVal="" desc="Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." hidden="false" />\r
+ <field name="CRC_BYPASS" from="2" to="2" access="RW" resetVal="" desc="CRC_NORMAL - 0, CRC_BYPASS - 1" hidden="false" />\r
+ <field name="RESET_PTR" from="3" to="3" access="RW" resetVal="" desc="RESET_KRYPTON - 0, RESET_NORMAL - 1" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP5_INT_EN" address="0x400060C1" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Enable Register" hidden="true">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP5_INT_SR" address="0x400060C2" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Status Register" hidden="true">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW5_WA" address="0x400060C4" bitWidth="8" desc="Arbiter Endpoint 1 Write Address LSB Register" hidden="true">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for EP." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW5_WA_MSB" address="0x400060C5" bitWidth="8" desc="Arbiter Endpoint 1 Write Address MSB Register" hidden="true">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW5_RA" address="0x400060C6" bitWidth="8" desc="Arbiter Endpoint 1 Read Address LSB Register" hidden="true">\r
+ <field name="RA8" from="7" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW5_RA_MSB" address="0x400060C7" bitWidth="8" desc="Arbiter Endpoint 1 Read Address MSB Register" hidden="true">\r
+ <field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="BUS_RST_CNT" address="0x400060CC" bitWidth="8" desc="Bus Reset Count Register" hidden="true">\r
+ <field name="BUS_RST_CNT" from="3" to="0" access="RW" resetVal="" desc="Bus Reset Count Length. Bus Reset Count register ; For USB bus reset length; The value in this register determines the no. of pulses of the low freq. clock which will be counted to determine if an SE0 condition has been held for long enough to declare a USB Bus reset condition. In krypton, 3 pulses of a 32 KHz clock were counted to declare a usb bus reset condition. In leopard, a 100 KHz clock is used. Recommended is to count 10 pulses of this clock to remain equivalent to Krypton." hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP6_CFG" address="0x400060D0" bitWidth="8" desc="Arbiter Endpoint 1 Configuration Register" hidden="true">\r
+ <field name="IN_DATA_RDY" from="0" to="0" access="RW" resetVal="" desc="Indication that Endpoint Packet Data is Ready in Main memory" hidden="false" />\r
+ <field name="DMA_REQ" from="1" to="1" access="RW" resetVal="" desc="Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." hidden="false" />\r
+ <field name="CRC_BYPASS" from="2" to="2" access="RW" resetVal="" desc="CRC_NORMAL - 0, CRC_BYPASS - 1" hidden="false" />\r
+ <field name="RESET_PTR" from="3" to="3" access="RW" resetVal="" desc="RESET_KRYPTON - 0, RESET_NORMAL - 1" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP6_INT_EN" address="0x400060D1" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Enable Register" hidden="true">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP6_INT_SR" address="0x400060D2" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Status Register" hidden="true">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW6_WA" address="0x400060D4" bitWidth="8" desc="Arbiter Endpoint 1 Write Address LSB Register" hidden="true">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for EP." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW6_WA_MSB" address="0x400060D5" bitWidth="8" desc="Arbiter Endpoint 1 Write Address MSB Register" hidden="true">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW6_RA" address="0x400060D6" bitWidth="8" desc="Arbiter Endpoint 1 Read Address LSB Register" hidden="true">\r
+ <field name="RA8" from="7" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW6_RA_MSB" address="0x400060D7" bitWidth="8" desc="Arbiter Endpoint 1 Read Address MSB Register" hidden="true">\r
+ <field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP7_CFG" address="0x400060E0" bitWidth="8" desc="Arbiter Endpoint 1 Configuration Register" hidden="true">\r
+ <field name="IN_DATA_RDY" from="0" to="0" access="RW" resetVal="" desc="Indication that Endpoint Packet Data is Ready in Main memory" hidden="false" />\r
+ <field name="DMA_REQ" from="1" to="1" access="RW" resetVal="" desc="Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." hidden="false" />\r
+ <field name="CRC_BYPASS" from="2" to="2" access="RW" resetVal="" desc="CRC_NORMAL - 0, CRC_BYPASS - 1" hidden="false" />\r
+ <field name="RESET_PTR" from="3" to="3" access="RW" resetVal="" desc="RESET_KRYPTON - 0, RESET_NORMAL - 1" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP7_INT_EN" address="0x400060E1" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Enable Register" hidden="true">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP7_INT_SR" address="0x400060E2" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Status Register" hidden="true">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW7_WA" address="0x400060E4" bitWidth="8" desc="Arbiter Endpoint 1 Write Address LSB Register" hidden="true">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for EP." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW7_WA_MSB" address="0x400060E5" bitWidth="8" desc="Arbiter Endpoint 1 Write Address MSB Register" hidden="true">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW7_RA" address="0x400060E6" bitWidth="8" desc="Arbiter Endpoint 1 Read Address LSB Register" hidden="true">\r
+ <field name="RA8" from="7" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW7_RA_MSB" address="0x400060E7" bitWidth="8" desc="Arbiter Endpoint 1 Read Address MSB Register" hidden="true">\r
+ <field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP8_CFG" address="0x400060F0" bitWidth="8" desc="Arbiter Endpoint 1 Configuration Register" hidden="true">\r
+ <field name="IN_DATA_RDY" from="0" to="0" access="RW" resetVal="" desc="Indication that Endpoint Packet Data is Ready in Main memory" hidden="false" />\r
+ <field name="DMA_REQ" from="1" to="1" access="RW" resetVal="" desc="Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated." hidden="false" />\r
+ <field name="CRC_BYPASS" from="2" to="2" access="RW" resetVal="" desc="CRC_NORMAL - 0, CRC_BYPASS - 1" hidden="false" />\r
+ <field name="RESET_PTR" from="3" to="3" access="RW" resetVal="" desc="RESET_KRYPTON - 0, RESET_NORMAL - 1" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP8_INT_EN" address="0x400060F1" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Enable Register" hidden="true">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_EP8_INT_SR" address="0x400060F2" bitWidth="8" desc="Arbiter Endpoint 1 Interrupt Status Register" hidden="true">\r
+ <field name="IN_BUF_FULL_EN" from="0" to="0" access="RW" resetVal="" desc="IN Endpoint Local Buffer Full" hidden="false" />\r
+ <field name="DMA_GNT_EN" from="1" to="1" access="RW" resetVal="" desc="Endpoint DMA Grant" hidden="false" />\r
+ <field name="BUF_OVER_EN" from="2" to="2" access="RW" resetVal="" desc="Endpoint Buffer Overflow" hidden="false" />\r
+ <field name="BUF_UNDER_EN" from="3" to="3" access="RW" resetVal="" desc="Endpoint Buffer Underflow" hidden="false" />\r
+ <field name="ERR_INT_EN" from="4" to="4" access="RW" resetVal="" desc="Endpoint Error in Transaction Interrupt" hidden="false" />\r
+ <field name="DMA_TERMIN_EN" from="5" to="5" access="RW" resetVal="" desc="Endpoint DMA Terminated Enable" hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW8_WA" address="0x400060F4" bitWidth="8" desc="Arbiter Endpoint 1 Write Address LSB Register" hidden="true">\r
+ <field name="WA8" from="7" to="0" access="RW" resetVal="" desc="Write Address for EP." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW8_WA_MSB" address="0x400060F5" bitWidth="8" desc="Arbiter Endpoint 1 Write Address MSB Register" hidden="true">\r
+ <field name="WA9" from="0" to="0" access="RW" resetVal="" desc="Write Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW8_RA" address="0x400060F6" bitWidth="8" desc="Arbiter Endpoint 1 Read Address LSB Register" hidden="true">\r
+ <field name="RA8" from="7" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
+ <register name="ARB_RW8_RA_MSB" address="0x400060F7" bitWidth="8" desc="Arbiter Endpoint 1 Read Address MSB Register" hidden="true">\r
+ <field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />\r
+ </register>\r
</block>\r
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006477" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
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<Hidden v="False" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
-<build_action v="NONE" />\r
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</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
</dependencies>\r
<project_current_platform v="c9323d49-d323-40b8-9b59-cc008d68a989" />\r
<project_current_processor v="CortexM3" />\r
<last_selected_tab v="Cypress" />\r
-<WriteAppVersionLastSavedWith v="3.3.0.410" />\r
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+<project_id v="6e1f5cbb-a0ca-4f55-a1fa-7b20c5be3a3e" />\r
+<GenerateDescriptionFiles v="False" />\r
+</CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>\r
</CyGuid_60697ce6-dce2-4816-8680-4de0635742eb>\r
<top_block v="TopDesign" />\r
<selected_device v="CY8C5267AXI-LP051" />\r
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+<pdl_path v="" />\r
+<include_paths />\r
+<CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtComponentMgrSerialize" version="4" xml_contents_version="1">\r
<library_deps>\r
<library_dep persistent="${CyRoot}\psoc\content\default\CyAnnotationLibrary\CyAnnotationLibrary.cylib\CyAnnotationLibrary.cyprj" />\r
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<boot_component v="cy_boot_v4_20" />\r
-<current_generation v="3" /><BootloaderTag hexFile="" elfFile="" /></CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>\r
+<current_generation v="3" />\r
+</CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>\r
</CyXmlSerializer>
\ No newline at end of file
<peripheral>\r
<name>SCSI_Parity_Error</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006565</baseAddress>\r
+ <baseAddress>0x40006463</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_Filtered</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000646B</baseAddress>\r
+ <baseAddress>0x40006468</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_Glitch_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006474</baseAddress>\r
+ <baseAddress>0x4000647A</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_CTL_PHASE</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006475</baseAddress>\r
+ <baseAddress>0x40006472</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
</addressBlock>\r
<registers>\r
<register>\r
- <name>USBFS_PM_USB_CR0</name>\r
- <description>USB Power Mode Control Register 0</description>\r
- <addressOffset>0x40004394</addressOffset>\r
+ <name>CR0</name>\r
+ <description>USB Control 0 Register</description>\r
+ <addressOffset>0x40006008</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DEVICE_ADDRESS</name>\r
+ <description>These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware.</description>\r
+ <lsb>0</lsb>\r
+ <msb>6</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>USB_ENABLE</name>\r
+ <description>This bit enables the device to respond to USB traffic.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Disabled</name>\r
+ <description>Block responds to USB traffic.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Enabled</name>\r
+ <description>Block does not respond to USB traffic.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>CR1</name>\r
+ <description>USB Control 1 Register</description>\r
+ <addressOffset>0x40006009</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>REG_ENABLE</name>\r
+ <description>This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-only</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Disabled</name>\r
+ <description>Regulator for 5V is disabled.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Enabled</name>\r
+ <description>Regulator for 5V is enabled.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>ENABLE_LOCK</name>\r
+ <description>This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUS_ACTIVITY</name>\r
+ <description>The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High value until firmware clears it.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>TRIM_OFFSET_MSB</name>\r
+ <description>This bit enables trim bit[7].</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP_INT_EN</name>\r
+ <description>USB SIE Data Endpoints Interrupt Enable Register</description>\r
+ <addressOffset>0x4000600A</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>EP1_INTR_EN</name>\r
+ <description>Enables interrupt for EP1.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP2_INTR_EN</name>\r
+ <description>Enables interrupt for EP2.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP3_INTR_EN</name>\r
+ <description>Enables interrupt for EP3.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP4_INTR_EN</name>\r
+ <description>Enables interrupt for EP4.</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP5_INTR_EN</name>\r
+ <description>Enables interrupt for EP5.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP6_INTR_EN</name>\r
+ <description>Enables interrupt for EP6.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP7_INTR_EN</name>\r
+ <description>Enables interrupt for EP7.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP8_INTR_EN</name>\r
+ <description>Enables interrupt for EP8.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP_INT_SR</name>\r
+ <description>SIE Data Endpoint Interrupt Status Register</description>\r
+ <addressOffset>0x4000600B</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>EP1_INTR</name>\r
+ <description>Interrupt status for EP1.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP2_INTR</name>\r
+ <description>Interrupt status for EP2.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP3_INTR</name>\r
+ <description>Interrupt status for EP3.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP4_INTR</name>\r
+ <description>Interrupt status for EP4.</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP5_INTR</name>\r
+ <description>Interrupt status for EP5.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP6_INTR</name>\r
+ <description>Interrupt status for EP6.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP7_INTR</name>\r
+ <description>Interrupt status for EP7.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP8_INTR</name>\r
+ <description>Interrupt status for EP8.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP1_CNT0</name>\r
+ <description>SIE Endpoint 1 Count0 Register</description>\r
+ <addressOffset>0x4000600C</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DATA_COUNT_MSB</name>\r
+ <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>\r
+ <lsb>0</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_VALID</name>\r
+ <description>DATA_ERROR - 0, DATA_VALID - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_TOGGLE</name>\r
+ <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP1_CNT1</name>\r
+ <description>SIE Endpoint 1 Count1 Register</description>\r
+ <addressOffset>0x4000600D</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DATA_COUNT</name>\r
+ <description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP1_CR0</name>\r
+ <description>SIE Endpoint 1 Control Register</description>\r
+ <addressOffset>0x4000600E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>MODE</name>\r
+ <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>\r
+ <lsb>0</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DISABLE</name>\r
+ <description>Ignore all USB traffic to this endpoint.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_INOUT</name>\r
+ <description>SETUP: Accept, IN: NAK, OUT: NAK.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_OUT_ONLY</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STALL_INOUT</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: STALL.</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>\r
+ <value>5</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_IN_ONLY</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Stall.</description>\r
+ <value>6</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_IN</name>\r
+ <description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>\r
+ <value>7</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>\r
+ <value>8</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>\r
+ <value>9</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT_STATUS_IN</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Accept data.</description>\r
+ <value>11</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_IN</name>\r
+ <description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>\r
+ <value>12</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN</name>\r
+ <description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>\r
+ <value>13</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN_STATUS_OUT</name>\r
+ <description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>15</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>ACKED_TXN</name>\r
+ <description>ACKED_NO - 0, ACKED_YES - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>NAK_INT_EN</name>\r
+ <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_IN_TXN</name>\r
+ <description>The Error in transaction bit is set whenever an error is detected.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>STALL</name>\r
+ <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>USBIO_CR0</name>\r
+ <description>USBIO Control 0 Register</description>\r
+ <addressOffset>0x40006010</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>RD</name>\r
+ <description>Received Data. This read only bit gives the state of the USB differential receiver.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-only</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DIFF_LOW</name>\r
+ <description>D+ less than D- (K state), or D+=D-=0 (SE0).</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DIFF_HIGH</name>\r
+ <description>D+ greater than D- (J state).</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>TD</name>\r
+ <description>Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DIFF_K</name>\r
+ <description>Force USB K state (D+ is low D- is high).</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DIFF_J</name>\r
+ <description>Force USB J state (D+ is high D- is low).</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>TSE0</name>\r
+ <description>Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>TEN</name>\r
+ <description>USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually transmitting is to force a resume state on the bus.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>USBIO_CR1</name>\r
+ <description>USBIO Control 1 Register</description>\r
+ <addressOffset>0x40006012</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DMO</name>\r
+ <description>This read only bit gives the state of the D- pin.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>DPO</name>\r
+ <description>This read only bit gives the state of the D+ pin.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>USBPUEN</name>\r
+ <description>This bit enables the connection of the internal 1.5 k pull up resistor on the D+ pin.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>IOMODE</name>\r
+ <description>This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Bit_banged</name>\r
+ <description>Bit-banged mode for Dm and Dp.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>USB</name>\r
+ <description>USB block controls Dm and Dp.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP2_CNT0</name>\r
+ <description>SIE Endpoint 1 Count0 Register</description>\r
+ <addressOffset>0x4000601C</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DATA_COUNT_MSB</name>\r
+ <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>\r
+ <lsb>0</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_VALID</name>\r
+ <description>DATA_ERROR - 0, DATA_VALID - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_TOGGLE</name>\r
+ <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP2_CNT1</name>\r
+ <description>SIE Endpoint 1 Count1 Register</description>\r
+ <addressOffset>0x4000601D</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DATA_COUNT</name>\r
+ <description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP2_CR0</name>\r
+ <description>SIE Endpoint 1 Control Register</description>\r
+ <addressOffset>0x4000601E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>MODE</name>\r
+ <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>\r
+ <lsb>0</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DISABLE</name>\r
+ <description>Ignore all USB traffic to this endpoint.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_INOUT</name>\r
+ <description>SETUP: Accept, IN: NAK, OUT: NAK.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_OUT_ONLY</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STALL_INOUT</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: STALL.</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>\r
+ <value>5</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_IN_ONLY</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Stall.</description>\r
+ <value>6</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_IN</name>\r
+ <description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>\r
+ <value>7</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>\r
+ <value>8</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>\r
+ <value>9</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT_STATUS_IN</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Accept data.</description>\r
+ <value>11</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_IN</name>\r
+ <description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>\r
+ <value>12</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN</name>\r
+ <description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>\r
+ <value>13</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN_STATUS_OUT</name>\r
+ <description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>15</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>ACKED_TXN</name>\r
+ <description>ACKED_NO - 0, ACKED_YES - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>NAK_INT_EN</name>\r
+ <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_IN_TXN</name>\r
+ <description>The Error in transaction bit is set whenever an error is detected.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>STALL</name>\r
+ <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>EP0_CR</name>\r
+ <description>Endpoint0 control Register</description>\r
+ <addressOffset>0x40006028</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>MODE</name>\r
+ <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>\r
+ <lsb>0</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DISABLE</name>\r
+ <description>Ignore all USB traffic to this endpoint.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_INOUT</name>\r
+ <description>SETUP: Accept, IN: NAK, OUT: NAK.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_OUT_ONLY</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STALL_INOUT</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: STALL.</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>\r
+ <value>5</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_IN_ONLY</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Stall.</description>\r
+ <value>6</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_IN</name>\r
+ <description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>\r
+ <value>7</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>\r
+ <value>8</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>\r
+ <value>9</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT_STATUS_IN</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Accept data.</description>\r
+ <value>11</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_IN</name>\r
+ <description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>\r
+ <value>12</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN</name>\r
+ <description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>\r
+ <value>13</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN_STATUS_OUT</name>\r
+ <description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>15</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>ACKED_TXN</name>\r
+ <description>ACKED_NO - 0, ACKED_YES - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>NAK_INT_EN</name>\r
+ <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_IN_TXN</name>\r
+ <description>The Error in transaction bit is set whenever an error is detected.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>STALL</name>\r
+ <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>EP0_CNT</name>\r
+ <description>Endpoint0 control Register</description>\r
+ <addressOffset>0x40006029</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>BYTE_COUNT</name>\r
+ <description>These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10.</description>\r
+ <lsb>0</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_VALID</name>\r
+ <description>This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DATA_ERROR</name>\r
+ <description>No ACK'd transactions since bit was last cleared.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DATA_VALID</name>\r
+ <description>Indicates a transaction ended with an ACK.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>DATA_TOGGLE</name>\r
+ <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP3_CNT0</name>\r
+ <description>SIE Endpoint 1 Count0 Register</description>\r
+ <addressOffset>0x4000602C</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DATA_COUNT_MSB</name>\r
+ <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>\r
+ <lsb>0</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_VALID</name>\r
+ <description>DATA_ERROR - 0, DATA_VALID - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_TOGGLE</name>\r
+ <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP3_CNT1</name>\r
+ <description>SIE Endpoint 1 Count1 Register</description>\r
+ <addressOffset>0x4000602D</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DATA_COUNT</name>\r
+ <description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP3_CR0</name>\r
+ <description>SIE Endpoint 1 Control Register</description>\r
+ <addressOffset>0x4000602E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>MODE</name>\r
+ <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>\r
+ <lsb>0</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DISABLE</name>\r
+ <description>Ignore all USB traffic to this endpoint.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_INOUT</name>\r
+ <description>SETUP: Accept, IN: NAK, OUT: NAK.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_OUT_ONLY</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STALL_INOUT</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: STALL.</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>\r
+ <value>5</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_IN_ONLY</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Stall.</description>\r
+ <value>6</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_IN</name>\r
+ <description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>\r
+ <value>7</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>\r
+ <value>8</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>\r
+ <value>9</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT_STATUS_IN</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Accept data.</description>\r
+ <value>11</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_IN</name>\r
+ <description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>\r
+ <value>12</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN</name>\r
+ <description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>\r
+ <value>13</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN_STATUS_OUT</name>\r
+ <description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>15</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>ACKED_TXN</name>\r
+ <description>ACKED_NO - 0, ACKED_YES - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>NAK_INT_EN</name>\r
+ <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_IN_TXN</name>\r
+ <description>The Error in transaction bit is set whenever an error is detected.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>STALL</name>\r
+ <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP4_CNT0</name>\r
+ <description>SIE Endpoint 1 Count0 Register</description>\r
+ <addressOffset>0x4000603C</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DATA_COUNT_MSB</name>\r
+ <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>\r
+ <lsb>0</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_VALID</name>\r
+ <description>DATA_ERROR - 0, DATA_VALID - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DATA_TOGGLE</name>\r
+ <description>This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP4_CNT1</name>\r
+ <description>SIE Endpoint 1 Count1 Register</description>\r
+ <addressOffset>0x4000603D</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>DATA_COUNT</name>\r
+ <description>These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SIE_EP4_CR0</name>\r
+ <description>SIE Endpoint 1 Control Register</description>\r
+ <addressOffset>0x4000603E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>MODE</name>\r
+ <description>The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint.</description>\r
+ <lsb>0</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DISABLE</name>\r
+ <description>Ignore all USB traffic to this endpoint.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_INOUT</name>\r
+ <description>SETUP: Accept, IN: NAK, OUT: NAK.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_OUT_ONLY</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STALL_INOUT</name>\r
+ <description>SETUP: Accept, IN: STALL, OUT: STALL.</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token.</description>\r
+ <value>5</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>STATUS_IN_ONLY</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Stall.</description>\r
+ <value>6</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ISO_IN</name>\r
+ <description>SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore.</description>\r
+ <value>7</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: NAK.</description>\r
+ <value>8</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT</name>\r
+ <description>SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token.</description>\r
+ <value>9</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_OUT_STATUS_IN</name>\r
+ <description>SETUP: Accept, IN: Respond with 0B data, OUT: Accept data.</description>\r
+ <value>11</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>NAK_IN</name>\r
+ <description>SETUP: Ignore, IN: NAK, OUT: Ignore.</description>\r
+ <value>12</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN</name>\r
+ <description>SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore</description>\r
+ <value>13</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>ACK_IN_STATUS_OUT</name>\r
+ <description>SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others.</description>\r
+ <value>15</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>ACKED_TXN</name>\r
+ <description>ACKED_NO - 0, ACKED_YES - 1.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>NAK_INT_EN</name>\r
+ <description>When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_IN_TXN</name>\r
+ <description>The Error in transaction bit is set whenever an error is detected.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>STALL</name>\r
+ <description>When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_EP1_CFG</name>\r
+ <description>Arbiter Endpoint 1 Configuration Register</description>\r
+ <addressOffset>0x40006080</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>IN_DATA_RDY</name>\r
+ <description>Indication that Endpoint Packet Data is Ready in Main memory</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_REQ</name>\r
+ <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>CRC_BYPASS</name>\r
+ <description>CRC_NORMAL - 0, CRC_BYPASS - 1</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>RESET_PTR</name>\r
+ <description>RESET_KRYPTON - 0, RESET_NORMAL - 1</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_EP1_INT_EN</name>\r
+ <description>Arbiter Endpoint 1 Interrupt Enable Register</description>\r
+ <addressOffset>0x40006081</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>IN_BUF_FULL_EN</name>\r
+ <description>IN Endpoint Local Buffer Full</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_GNT_EN</name>\r
+ <description>Endpoint DMA Grant</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_OVER_EN</name>\r
+ <description>Endpoint Buffer Overflow</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_UNDER_EN</name>\r
+ <description>Endpoint Buffer Underflow</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_INT_EN</name>\r
+ <description>Endpoint Error in Transaction Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_TERMIN_EN</name>\r
+ <description>Endpoint DMA Terminated Enable</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_EP1_INT_SR</name>\r
+ <description>Arbiter Endpoint 1 Interrupt Status Register</description>\r
+ <addressOffset>0x40006082</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>IN_BUF_FULL_EN</name>\r
+ <description>IN Endpoint Local Buffer Full</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_GNT_EN</name>\r
+ <description>Endpoint DMA Grant</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_OVER_EN</name>\r
+ <description>Endpoint Buffer Overflow</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_UNDER_EN</name>\r
+ <description>Endpoint Buffer Underflow</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_INT_EN</name>\r
+ <description>Endpoint Error in Transaction Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_TERMIN_EN</name>\r
+ <description>Endpoint DMA Terminated Enable</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_RW1_WA</name>\r
+ <description>Arbiter Endpoint 1 Write Address LSB Register</description>\r
+ <addressOffset>0x40006084</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>WA8</name>\r
+ <description>Write Address for EP.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_RW1_WA_MSB</name>\r
+ <description>Arbiter Endpoint 1 Write Address MSB Register</description>\r
+ <addressOffset>0x40006085</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>WA9</name>\r
+ <description>Write Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_RW1_RA</name>\r
+ <description>Arbiter Endpoint 1 Read Address LSB Register</description>\r
+ <addressOffset>0x40006086</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>RA8</name>\r
+ <description>Read Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_RW1_RA_MSB</name>\r
+ <description>Arbiter Endpoint 1 Read Address MSB Register</description>\r
+ <addressOffset>0x40006087</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>RA9</name>\r
+ <description>Read Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_EP2_CFG</name>\r
+ <description>Arbiter Endpoint 1 Configuration Register</description>\r
+ <addressOffset>0x40006090</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>IN_DATA_RDY</name>\r
+ <description>Indication that Endpoint Packet Data is Ready in Main memory</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_REQ</name>\r
+ <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>CRC_BYPASS</name>\r
+ <description>CRC_NORMAL - 0, CRC_BYPASS - 1</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>RESET_PTR</name>\r
+ <description>RESET_KRYPTON - 0, RESET_NORMAL - 1</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_EP2_INT_EN</name>\r
+ <description>Arbiter Endpoint 1 Interrupt Enable Register</description>\r
+ <addressOffset>0x40006091</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>IN_BUF_FULL_EN</name>\r
+ <description>IN Endpoint Local Buffer Full</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_GNT_EN</name>\r
+ <description>Endpoint DMA Grant</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_OVER_EN</name>\r
+ <description>Endpoint Buffer Overflow</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_UNDER_EN</name>\r
+ <description>Endpoint Buffer Underflow</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_INT_EN</name>\r
+ <description>Endpoint Error in Transaction Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_TERMIN_EN</name>\r
+ <description>Endpoint DMA Terminated Enable</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_EP2_INT_SR</name>\r
+ <description>Arbiter Endpoint 1 Interrupt Status Register</description>\r
+ <addressOffset>0x40006092</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>fsusbio_ref_en</name>\r
- <description>No description available</description>\r
+ <name>IN_BUF_FULL_EN</name>\r
+ <description>IN Endpoint Local Buffer Full</description>\r
<lsb>0</lsb>\r
<msb>0</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>fsusbio_pd_n</name>\r
- <description>No description available</description>\r
+ <name>DMA_GNT_EN</name>\r
+ <description>Endpoint DMA Grant</description>\r
<lsb>1</lsb>\r
<msb>1</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>fsusbio_pd_pullup_n</name>\r
- <description>No description available</description>\r
+ <name>BUF_OVER_EN</name>\r
+ <description>Endpoint Buffer Overflow</description>\r
<lsb>2</lsb>\r
<msb>2</msb>\r
<access>read-write</access>\r
</field>\r
+ <field>\r
+ <name>BUF_UNDER_EN</name>\r
+ <description>Endpoint Buffer Underflow</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_INT_EN</name>\r
+ <description>Endpoint Error in Transaction Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_TERMIN_EN</name>\r
+ <description>Endpoint DMA Terminated Enable</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_RW2_WA</name>\r
+ <description>Arbiter Endpoint 1 Write Address LSB Register</description>\r
+ <addressOffset>0x40006094</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>WA8</name>\r
+ <description>Write Address for EP.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_RW2_WA_MSB</name>\r
+ <description>Arbiter Endpoint 1 Write Address MSB Register</description>\r
+ <addressOffset>0x40006095</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>WA9</name>\r
+ <description>Write Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_RW2_RA</name>\r
+ <description>Arbiter Endpoint 1 Read Address LSB Register</description>\r
+ <addressOffset>0x40006096</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>RA8</name>\r
+ <description>Read Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_RW2_RA_MSB</name>\r
+ <description>Arbiter Endpoint 1 Read Address MSB Register</description>\r
+ <addressOffset>0x40006097</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>RA9</name>\r
+ <description>Read Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>ARB_CFG</name>\r
+ <description>Arbiter configuration register</description>\r
+ <addressOffset>0x4000609C</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>AUTO_MEM</name>\r
+ <description>Enables Auto Memory Configuration. Manual memory configuration by default.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_CFG</name>\r
+ <description>DMA Access Configuration.</description>\r
+ <lsb>5</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>DMA_NONE</name>\r
+ <description>No DMA.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DMA_MANUAL</name>\r
+ <description>Manual DMA.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DMA_AUTO</name>\r
+ <description>Auto DMA.</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>CFG_CMP</name>\r
+ <description>Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_PM_ACT_CFG</name>\r
- <description>Active Power Mode Configuration Register</description>\r
- <addressOffset>0x400043A5</addressOffset>\r
+ <name>USB_CLK_EN</name>\r
+ <description>USB Control 0 Register</description>\r
+ <addressOffset>0x4000609D</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>CSR_CLK_EN</name>\r
+ <description>Clock Enable for Core Logic clocked by AHB bus clock.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Disabled</name>\r
+ <description>Disables clock to UBS block.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Enabled</name>\r
+ <description>Enables clock to UBS block.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_PM_STBY_CFG</name>\r
- <description>Standby Power Mode Configuration Register</description>\r
- <addressOffset>0x400043B5</addressOffset>\r
+ <name>ARB_INT_EN</name>\r
+ <description>Arbiter Interrupt Enable Register</description>\r
+ <addressOffset>0x4000609E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>EP1_INTR_EN</name>\r
+ <description>Enables interrupt for EP1.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP2_INTR_EN</name>\r
+ <description>Enables interrupt for EP2.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP3_INTR_EN</name>\r
+ <description>Enables interrupt for EP3.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP4_INTR_EN</name>\r
+ <description>Enables interrupt for EP4.</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP5_INTR_EN</name>\r
+ <description>Enables interrupt for EP5.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP6_INTR_EN</name>\r
+ <description>Enables interrupt for EP6.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP7_INTR_EN</name>\r
+ <description>Enables interrupt for EP7.</description>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>EP8_INTR_EN</name>\r
+ <description>Enables interrupt for EP8.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_PRT_PS</name>\r
- <description>Port Pin State Register</description>\r
- <addressOffset>0x400051F1</addressOffset>\r
+ <name>ARB_INT_SR</name>\r
+ <description>Arbiter Interrupt Status</description>\r
+ <addressOffset>0x4000609F</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>PinState_DP</name>\r
- <description>No description available</description>\r
+ <name>EP1_INTR</name>\r
+ <description>Interrupt status for EP1.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>EP2_INTR</name>\r
+ <description>Interrupt status for EP2.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>EP3_INTR</name>\r
+ <description>Interrupt status for EP3.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>EP4_INTR</name>\r
+ <description>Interrupt status for EP4.</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>EP5_INTR</name>\r
+ <description>Interrupt status for EP5.</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>EP6_INTR</name>\r
+ <description>Interrupt status for EP6.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>EP7_INTR</name>\r
+ <description>Interrupt status for EP7.</description>\r
<lsb>6</lsb>\r
<msb>6</msb>\r
<access>read-only</access>\r
</field>\r
<field>\r
- <name>PinState_DM</name>\r
- <description>No description available</description>\r
+ <name>EP8_INTR</name>\r
+ <description>Interrupt status for EP8.</description>\r
<lsb>7</lsb>\r
<msb>7</msb>\r
<access>read-only</access>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_PRT_DM0</name>\r
- <description>Port Drive Mode Register</description>\r
- <addressOffset>0x400051F2</addressOffset>\r
+ <name>ARB_EP3_CFG</name>\r
+ <description>Arbiter Endpoint 1 Configuration Register</description>\r
+ <addressOffset>0x400060A0</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>DriveMode_DP</name>\r
- <description>No description available</description>\r
- <lsb>6</lsb>\r
- <msb>6</msb>\r
+ <name>IN_DATA_RDY</name>\r
+ <description>Indication that Endpoint Packet Data is Ready in Main memory</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>DriveMode_DM</name>\r
- <description>No description available</description>\r
- <lsb>7</lsb>\r
- <msb>7</msb>\r
+ <name>DMA_REQ</name>\r
+ <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>CRC_BYPASS</name>\r
+ <description>CRC_NORMAL - 0, CRC_BYPASS - 1</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>RESET_PTR</name>\r
+ <description>RESET_KRYPTON - 0, RESET_NORMAL - 1</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_PRT_DM1</name>\r
- <description>Port Drive Mode Register</description>\r
- <addressOffset>0x400051F3</addressOffset>\r
+ <name>ARB_EP3_INT_EN</name>\r
+ <description>Arbiter Endpoint 1 Interrupt Enable Register</description>\r
+ <addressOffset>0x400060A1</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>PullUp_en_DP</name>\r
- <description>No description available</description>\r
- <lsb>6</lsb>\r
- <msb>6</msb>\r
+ <name>IN_BUF_FULL_EN</name>\r
+ <description>IN Endpoint Local Buffer Full</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>PullUp_en_DM</name>\r
- <description>No description available</description>\r
- <lsb>7</lsb>\r
- <msb>7</msb>\r
+ <name>DMA_GNT_EN</name>\r
+ <description>Endpoint DMA Grant</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_OVER_EN</name>\r
+ <description>Endpoint Buffer Overflow</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_UNDER_EN</name>\r
+ <description>Endpoint Buffer Underflow</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_INT_EN</name>\r
+ <description>Endpoint Error in Transaction Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_TERMIN_EN</name>\r
+ <description>Endpoint DMA Terminated Enable</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_PRT_INP_DIS</name>\r
- <description>Input buffer disable override</description>\r
- <addressOffset>0x400051F8</addressOffset>\r
+ <name>ARB_EP3_INT_SR</name>\r
+ <description>Arbiter Endpoint 1 Interrupt Status Register</description>\r
+ <addressOffset>0x400060A2</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>seinput_dis_dp</name>\r
- <description>No description available</description>\r
- <lsb>6</lsb>\r
- <msb>6</msb>\r
+ <name>IN_BUF_FULL_EN</name>\r
+ <description>IN Endpoint Local Buffer Full</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>seinput_dis_dm</name>\r
- <description>No description available</description>\r
- <lsb>7</lsb>\r
- <msb>7</msb>\r
+ <name>DMA_GNT_EN</name>\r
+ <description>Endpoint DMA Grant</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_OVER_EN</name>\r
+ <description>Endpoint Buffer Overflow</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUF_UNDER_EN</name>\r
+ <description>Endpoint Buffer Underflow</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_INT_EN</name>\r
+ <description>Endpoint Error in Transaction Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_TERMIN_EN</name>\r
+ <description>Endpoint DMA Terminated Enable</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_EP0_DR0</name>\r
- <description>bmRequestType</description>\r
- <addressOffset>0x40006000</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_EP0_DR1</name>\r
- <description>bRequest</description>\r
- <addressOffset>0x40006001</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_EP0_DR2</name>\r
- <description>wValueLo</description>\r
- <addressOffset>0x40006002</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_EP0_DR3</name>\r
- <description>wValueHi</description>\r
- <addressOffset>0x40006003</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_EP0_DR4</name>\r
- <description>wIndexLo</description>\r
- <addressOffset>0x40006004</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_EP0_DR5</name>\r
- <description>wIndexHi</description>\r
- <addressOffset>0x40006005</addressOffset>\r
+ <name>ARB_RW3_WA</name>\r
+ <description>Arbiter Endpoint 1 Write Address LSB Register</description>\r
+ <addressOffset>0x400060A4</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>WA8</name>\r
+ <description>Write Address for EP.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_EP0_DR6</name>\r
- <description>lengthLo</description>\r
- <addressOffset>0x40006006</addressOffset>\r
+ <name>ARB_RW3_WA_MSB</name>\r
+ <description>Arbiter Endpoint 1 Write Address MSB Register</description>\r
+ <addressOffset>0x400060A5</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>WA9</name>\r
+ <description>Write Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_EP0_DR7</name>\r
- <description>lengthHi</description>\r
- <addressOffset>0x40006007</addressOffset>\r
+ <name>ARB_RW3_RA</name>\r
+ <description>Arbiter Endpoint 1 Read Address LSB Register</description>\r
+ <addressOffset>0x400060A6</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>RA8</name>\r
+ <description>Read Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_CR0</name>\r
- <description>USB Control Register 0</description>\r
- <addressOffset>0x40006008</addressOffset>\r
+ <name>ARB_RW3_RA_MSB</name>\r
+ <description>Arbiter Endpoint 1 Read Address MSB Register</description>\r
+ <addressOffset>0x400060A7</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>device_address</name>\r
- <description>No description available</description>\r
+ <name>RA9</name>\r
+ <description>Read Address for EP MSB.</description>\r
<lsb>0</lsb>\r
- <msb>6</msb>\r
- <access>read-only</access>\r
- </field>\r
- <field>\r
- <name>usb_enable</name>\r
- <description>No description available</description>\r
- <lsb>7</lsb>\r
- <msb>7</msb>\r
+ <msb>0</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_CR1</name>\r
- <description>USB Control Register 1</description>\r
- <addressOffset>0x40006009</addressOffset>\r
+ <name>ARB_EP4_CFG</name>\r
+ <description>Arbiter Endpoint 1 Configuration Register</description>\r
+ <addressOffset>0x400060B0</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>reg_enable</name>\r
- <description>No description available</description>\r
+ <name>IN_DATA_RDY</name>\r
+ <description>Indication that Endpoint Packet Data is Ready in Main memory</description>\r
<lsb>0</lsb>\r
<msb>0</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>enable_lock</name>\r
- <description>No description available</description>\r
+ <name>DMA_REQ</name>\r
+ <description>Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated.</description>\r
<lsb>1</lsb>\r
<msb>1</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>bus_activity</name>\r
- <description>No description available</description>\r
+ <name>CRC_BYPASS</name>\r
+ <description>CRC_NORMAL - 0, CRC_BYPASS - 1</description>\r
<lsb>2</lsb>\r
<msb>2</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>trim_offset_msb</name>\r
- <description>No description available</description>\r
+ <name>RESET_PTR</name>\r
+ <description>RESET_KRYPTON - 0, RESET_NORMAL - 1</description>\r
<lsb>3</lsb>\r
<msb>3</msb>\r
<access>read-write</access>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_SIE_EP1_CR0</name>\r
- <description>The Endpoint1 Control Register</description>\r
- <addressOffset>0x4000600E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_USBIO_CR0</name>\r
- <description>USBIO Control Register 0</description>\r
- <addressOffset>0x40006010</addressOffset>\r
+ <name>ARB_EP4_INT_EN</name>\r
+ <description>Arbiter Endpoint 1 Interrupt Enable Register</description>\r
+ <addressOffset>0x400060B1</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>rd</name>\r
- <description>No description available</description>\r
+ <name>IN_BUF_FULL_EN</name>\r
+ <description>IN Endpoint Local Buffer Full</description>\r
<lsb>0</lsb>\r
<msb>0</msb>\r
- <access>read-only</access>\r
+ <access>read-write</access>\r
</field>\r
<field>\r
- <name>td</name>\r
- <description>No description available</description>\r
- <lsb>5</lsb>\r
- <msb>5</msb>\r
+ <name>DMA_GNT_EN</name>\r
+ <description>Endpoint DMA Grant</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>tse0</name>\r
- <description>No description available</description>\r
- <lsb>6</lsb>\r
- <msb>6</msb>\r
+ <name>BUF_OVER_EN</name>\r
+ <description>Endpoint Buffer Overflow</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>ten</name>\r
- <description>No description available</description>\r
- <lsb>7</lsb>\r
- <msb>7</msb>\r
+ <name>BUF_UNDER_EN</name>\r
+ <description>Endpoint Buffer Underflow</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_INT_EN</name>\r
+ <description>Endpoint Error in Transaction Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_TERMIN_EN</name>\r
+ <description>Endpoint DMA Terminated Enable</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_USBIO_CR1</name>\r
- <description>USBIO Control Register 1</description>\r
- <addressOffset>0x40006012</addressOffset>\r
+ <name>ARB_EP4_INT_SR</name>\r
+ <description>Arbiter Endpoint 1 Interrupt Status Register</description>\r
+ <addressOffset>0x400060B2</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>dmo</name>\r
- <description>No description available</description>\r
+ <name>IN_BUF_FULL_EN</name>\r
+ <description>IN Endpoint Local Buffer Full</description>\r
<lsb>0</lsb>\r
<msb>0</msb>\r
- <access>read-only</access>\r
+ <access>read-write</access>\r
</field>\r
<field>\r
- <name>dpo</name>\r
- <description>No description available</description>\r
+ <name>DMA_GNT_EN</name>\r
+ <description>Endpoint DMA Grant</description>\r
<lsb>1</lsb>\r
<msb>1</msb>\r
- <access>read-only</access>\r
+ <access>read-write</access>\r
</field>\r
<field>\r
- <name>usbpuen</name>\r
- <description>No description available</description>\r
+ <name>BUF_OVER_EN</name>\r
+ <description>Endpoint Buffer Overflow</description>\r
<lsb>2</lsb>\r
<msb>2</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>iomode</name>\r
- <description>No description available</description>\r
+ <name>BUF_UNDER_EN</name>\r
+ <description>Endpoint Buffer Underflow</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ERR_INT_EN</name>\r
+ <description>Endpoint Error in Transaction Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DMA_TERMIN_EN</name>\r
+ <description>Endpoint DMA Terminated Enable</description>\r
<lsb>5</lsb>\r
<msb>5</msb>\r
<access>read-write</access>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_SIE_EP2_CR0</name>\r
- <description>The Endpoint2 Control Register</description>\r
- <addressOffset>0x4000601E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_SIE_EP3_CR0</name>\r
- <description>The Endpoint3 Control Register</description>\r
- <addressOffset>0x4000602E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_SIE_EP4_CR0</name>\r
- <description>The Endpoint4 Control Register</description>\r
- <addressOffset>0x4000603E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_SIE_EP5_CR0</name>\r
- <description>The Endpoint5 Control Register</description>\r
- <addressOffset>0x4000604E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_SIE_EP6_CR0</name>\r
- <description>The Endpoint6 Control Register</description>\r
- <addressOffset>0x4000605E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_SIE_EP7_CR0</name>\r
- <description>The Endpoint7 Control Register</description>\r
- <addressOffset>0x4000606E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_SIE_EP8_CR0</name>\r
- <description>The Endpoint8 Control Register</description>\r
- <addressOffset>0x4000607E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_BUF_SIZE</name>\r
- <description>Dedicated Endpoint Buffer Size Register</description>\r
- <addressOffset>0x4000608C</addressOffset>\r
+ <name>ARB_RW4_WA</name>\r
+ <description>Arbiter Endpoint 1 Write Address LSB Register</description>\r
+ <addressOffset>0x400060B4</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>WA8</name>\r
+ <description>Write Address for EP.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_EP_ACTIVE</name>\r
- <description>Endpoint Active Indication Register</description>\r
- <addressOffset>0x4000608E</addressOffset>\r
+ <name>ARB_RW4_WA_MSB</name>\r
+ <description>Arbiter Endpoint 1 Write Address MSB Register</description>\r
+ <addressOffset>0x400060B5</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>WA9</name>\r
+ <description>Write Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_EP_TYPE</name>\r
- <description>Endpoint Type (IN/OUT) Indication</description>\r
- <addressOffset>0x4000608F</addressOffset>\r
+ <name>ARB_RW4_RA</name>\r
+ <description>Arbiter Endpoint 1 Read Address LSB Register</description>\r
+ <addressOffset>0x400060B6</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>RA8</name>\r
+ <description>Read Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_USB_CLK_EN</name>\r
- <description>USB Block Clock Enable Register</description>\r
- <addressOffset>0x4000609D</addressOffset>\r
+ <name>ARB_RW4_RA_MSB</name>\r
+ <description>Arbiter Endpoint 1 Read Address MSB Register</description>\r
+ <addressOffset>0x400060B7</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>RA9</name>\r
+ <description>Read Address for EP MSB.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
</registers>\r
</peripheral>\r
<peripheral>\r
<name>SCSI_Out_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006478</baseAddress>\r
+ <baseAddress>0x40006473</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_Out_Bits</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006477</baseAddress>\r
+ <baseAddress>0x4000647C</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
projects / SCSI2SD.git / commitdiff