Fix for scsi2sd-util crashes on exit.
USB Interface (firmware updates and config)
USB 2.0 micro-B
Power
- 5V via standard molex drive connector.
+ 5V via standard molex drive connector
+ USB or self-powered using the SCSI host termination power. (v5 only)
Dimensions
- 10cm x 10cm x 1.5cm
- Mounting holes to suit standard 2.5" - 3.5" drive bracket.
+ 10cm x 5cm x 1.5cm (v5)
+ 10cm x 10cm x 1.5cm (v3, v4)
Performance
Device-type modifier: 0x4c
Applix 1616
IMS MM/1
+ NeXTcube + NeXTSTEP 3.3
+ NeXTStation
+ Modified geometry settings are required to avoid "cylinder group too large" errors while formatting.
+ (To simulate Quantum Fireball 1050S)
+ 512 bytesPerSector
+ 139 sectorsPerTrack
+ 4 tracksPerCylinder
+ 4135 cylinder per volume
+ 1 spare sector per cylinder
+ 2051459 usable sectors on volume
+
Samplers
\r
#include <string.h>\r
\r
-static const uint16_t FIRMWARE_VERSION = 0x0424;\r
+static const uint16_t FIRMWARE_VERSION = 0x0430;\r
\r
// 1 flash row\r
static const uint8_t DEFAULT_CONFIG[256] =\r
uint64 fromByteAddr =\r
scsiByteAddress(\r
scsiDev.target->liveCfg.bytesPerSector,\r
+ scsiDev.target->cfg->headsPerCylinder,\r
+ scsiDev.target->cfg->sectorsPerTrack,\r
suppliedFmt,\r
&scsiDev.data[6]);\r
\r
scsiSaveByteAddress(\r
scsiDev.target->liveCfg.bytesPerSector,\r
+ scsiDev.target->cfg->headsPerCylinder,\r
+ scsiDev.target->cfg->sectorsPerTrack,\r
translateFmt,\r
fromByteAddr,\r
&scsiDev.data[6]);\r
\r
// Standard mapping according to ECMA-107 and ISO/IEC 9293:1994\r
// Sector always starts at 1. There is no 0 sector.\r
-uint64 CHS2LBA(uint32 c, uint8 h, uint32 s)\r
+uint64_t CHS2LBA(\r
+ uint32_t c,\r
+ uint8_t h,\r
+ uint32_t s,\r
+ uint16_t headsPerCylinder,\r
+ uint16_t sectorsPerTrack)\r
{\r
return (\r
- (((uint64)c) * SCSI_HEADS_PER_CYLINDER + h) *\r
- (uint64) SCSI_SECTORS_PER_TRACK\r
+ (((uint64_t)c) * headsPerCylinder + h) *\r
+ (uint64_t) sectorsPerTrack\r
) + (s - 1);\r
}\r
\r
\r
-void LBA2CHS(uint32 lba, uint32* c, uint8* h, uint32* s)\r
+void LBA2CHS(\r
+ uint32_t lba,\r
+ uint32_t* c,\r
+ uint8_t* h,\r
+ uint32_t* s,\r
+ uint16_t headsPerCylinder,\r
+ uint16_t sectorsPerTrack)\r
{\r
- *c = lba / (SCSI_SECTORS_PER_TRACK * SCSI_HEADS_PER_CYLINDER);\r
- *h = (lba / SCSI_SECTORS_PER_TRACK) % SCSI_HEADS_PER_CYLINDER;\r
- *s = (lba % SCSI_SECTORS_PER_TRACK) + 1;\r
+ *c = lba / (((uint32_t) sectorsPerTrack) * headsPerCylinder);\r
+ *h = (lba / sectorsPerTrack) % headsPerCylinder;\r
+ *s = (lba % sectorsPerTrack) + 1;\r
}\r
\r
-uint64 scsiByteAddress(\r
+uint64_t scsiByteAddress(\r
uint16_t bytesPerSector,\r
+ uint16_t headsPerCylinder,\r
+ uint16_t sectorsPerTrack,\r
int format,\r
- const uint8* addr)\r
+ const uint8_t* addr)\r
{\r
- uint64 result;\r
+ uint64_t result;\r
switch (format)\r
{\r
case ADDRESS_BLOCK:\r
{\r
- uint32 lba =\r
- (((uint32) addr[0]) << 24) +\r
- (((uint32) addr[1]) << 16) +\r
- (((uint32) addr[2]) << 8) +\r
+ uint32_t lba =\r
+ (((uint32_t) addr[0]) << 24) +\r
+ (((uint32_t) addr[1]) << 16) +\r
+ (((uint32_t) addr[2]) << 8) +\r
addr[3];\r
\r
result = (uint64_t) bytesPerSector * lba;\r
\r
case ADDRESS_PHYSICAL_BYTE:\r
{\r
- uint32 cyl =\r
- (((uint32) addr[0]) << 16) +\r
- (((uint32) addr[1]) << 8) +\r
+ uint32_t cyl =\r
+ (((uint32_t) addr[0]) << 16) +\r
+ (((uint32_t) addr[1]) << 8) +\r
addr[2];\r
\r
- uint8 head = addr[3];\r
+ uint8_t head = addr[3];\r
\r
- uint32 bytes =\r
- (((uint32) addr[4]) << 24) +\r
- (((uint32) addr[5]) << 16) +\r
- (((uint32) addr[6]) << 8) +\r
+ uint32_t bytes =\r
+ (((uint32_t) addr[4]) << 24) +\r
+ (((uint32_t) addr[5]) << 16) +\r
+ (((uint32_t) addr[6]) << 8) +\r
addr[7];\r
\r
- result = CHS2LBA(cyl, head, 1) * (uint64_t) bytesPerSector + bytes;\r
+ result = CHS2LBA(cyl, head, 1, headsPerCylinder, sectorsPerTrack) *\r
+ (uint64_t) bytesPerSector + bytes;\r
} break;\r
\r
case ADDRESS_PHYSICAL_SECTOR:\r
{\r
uint32 cyl =\r
- (((uint32) addr[0]) << 16) +\r
- (((uint32) addr[1]) << 8) +\r
+ (((uint32_t) addr[0]) << 16) +\r
+ (((uint32_t) addr[1]) << 8) +\r
addr[2];\r
\r
uint8 head = scsiDev.data[3];\r
\r
uint32 sector =\r
- (((uint32) addr[4]) << 24) +\r
- (((uint32) addr[5]) << 16) +\r
- (((uint32) addr[6]) << 8) +\r
+ (((uint32_t) addr[4]) << 24) +\r
+ (((uint32_t) addr[5]) << 16) +\r
+ (((uint32_t) addr[6]) << 8) +\r
addr[7];\r
\r
- result = CHS2LBA(cyl, head, sector) * (uint64_t) bytesPerSector;\r
+ result = CHS2LBA(cyl, head, sector, headsPerCylinder, sectorsPerTrack) * (uint64_t) bytesPerSector;\r
} break;\r
\r
default:\r
\r
void scsiSaveByteAddress(\r
uint16_t bytesPerSector,\r
+ uint16_t headsPerCylinder,\r
+ uint16_t sectorsPerTrack,\r
int format,\r
- uint64 byteAddr,\r
- uint8* buf)\r
+ uint64_t byteAddr,\r
+ uint8_t* buf)\r
{\r
- uint32 lba = byteAddr / bytesPerSector;\r
- uint32 byteOffset = byteAddr % bytesPerSector;\r
+ uint32_t lba = byteAddr / bytesPerSector;\r
+ uint32_t byteOffset = byteAddr % bytesPerSector;\r
\r
switch (format)\r
{\r
\r
case ADDRESS_PHYSICAL_BYTE:\r
{\r
- uint32 cyl;\r
- uint8 head;\r
- uint32 sector;\r
- uint32 bytes;\r
+ uint32_t cyl;\r
+ uint8_t head;\r
+ uint32_t sector;\r
+ uint32_t bytes;\r
\r
- LBA2CHS(lba, &cyl, &head, §or);\r
+ LBA2CHS(lba, &cyl, &head, §or, headsPerCylinder, sectorsPerTrack);\r
\r
bytes = sector * bytesPerSector + byteOffset;\r
\r
\r
case ADDRESS_PHYSICAL_SECTOR:\r
{\r
- uint32 cyl;\r
- uint8 head;\r
- uint32 sector;\r
+ uint32_t cyl;\r
+ uint8_t head;\r
+ uint32_t sector;\r
\r
- LBA2CHS(lba, &cyl, &head, §or);\r
+ LBA2CHS(lba, &cyl, &head, §or, headsPerCylinder, sectorsPerTrack);\r
\r
buf[0] = cyl >> 16;\r
buf[1] = cyl >> 8;\r
#include "config.h"
#include "sd.h"
-// Max allowed by legacy IBM-PC Bios (6 bits)
-#define SCSI_SECTORS_PER_TRACK 63
-
-// MS-DOS up to 7.10 will crash on 256 heads.
-#define SCSI_HEADS_PER_CYLINDER 255
-
typedef enum
{
ADDRESS_BLOCK = 0,
uint16_t bytesPerSector,
uint32_t scsiSector);
-uint64 CHS2LBA(uint32 c, uint8 h, uint32 s);
-void LBA2CHS(uint32 lba, uint32* c, uint8* h, uint32* s);
+uint64_t CHS2LBA(
+ uint32_t c,
+ uint8_t h,
+ uint32_t s,
+ uint16_t headsPerCylinder,
+ uint16_t sectorsPerTrack);
+void LBA2CHS(
+ uint32_t lba,
+ uint32_t* c,
+ uint8_t* h,
+ uint32_t* s,
+ uint16_t headsPerCylinder,
+ uint16_t sectorsPerTrack);
// Convert an address in the given SCSI_ADDRESS_FORMAT to
// a linear byte address.
// addr must be >= 8 bytes.
-uint64 scsiByteAddress(
- uint16_t bytesPerSector, int format, const uint8* addr);
+uint64_t scsiByteAddress(
+ uint16_t bytesPerSector,
+ uint16_t headsPerCylinder,
+ uint16_t sectorsPerTrack,
+ int format,
+ const uint8_t* addr);
void scsiSaveByteAddress(
- uint16_t bytesPerSector, int format, uint64 byteAddr, uint8* buf);
+ uint16_t bytesPerSector,
+ uint16_t headsPerCylinder,
+ uint16_t sectorsPerTrack,
+ int format,
+ uint64_t byteAddr,
+ uint8_t* buf);
#endif
0x00, 0x00, // No alternate sectors\r
0x00, 0x00, // No alternate tracks\r
0x00, 0x00, // No alternate tracks per lun\r
-0x00, SCSI_SECTORS_PER_TRACK, // Sectors per track\r
+0x00, 0x00, // Sectors per track, configurable\r
0xFF, 0xFF, // Data bytes per physical sector. Configurable.\r
0x00, 0x01, // Interleave\r
0x00, 0x00, // Track skew factor\r
0x04, // Page code\r
0x16, // Page length\r
0xFF, 0xFF, 0xFF, // Number of cylinders\r
-SCSI_HEADS_PER_CYLINDER, // Number of heads\r
+0x00, // Number of heads (replaced by configured value)\r
0xFF, 0xFF, 0xFF, // Starting cylinder-write precompensation\r
0xFF, 0xFF, 0xFF, // Starting cylinder-reduced write current\r
0x00, 0x1, // Drive step rate (units of 100ns)\r
0x04, // Page code\r
0x12, // Page length\r
0xFF, 0xFF, 0xFF, // Number of cylinders\r
-SCSI_HEADS_PER_CYLINDER, // Number of heads\r
+0x00, // Number of heads (replaced by configured value)\r
0xFF, 0xFF, 0xFF, // Starting cylinder-write precompensation\r
0xFF, 0xFF, 0xFF, // Starting cylinder-reduced write current\r
0x00, 0x1, // Drive step rate (units of 100ns)\r
pageIn(pc, idx, FormatDevicePage, sizeof(FormatDevicePage));\r
if (pc != 0x01)\r
{\r
+ uint16_t sectorsPerTrack = scsiDev.target->cfg->sectorsPerTrack;\r
+ scsiDev.data[idx+10] = sectorsPerTrack >> 8;\r
+ scsiDev.data[idx+11] = sectorsPerTrack & 0xFF;\r
+\r
// Fill out the configured bytes-per-sector\r
uint32_t bytesPerSector = scsiDev.target->liveCfg.bytesPerSector;\r
scsiDev.data[idx+12] = bytesPerSector >> 8;\r
scsiDev.target->cfg->scsiSectors),\r
&cyl,\r
&head,\r
- §or);\r
+ §or,\r
+ scsiDev.target->cfg->headsPerCylinder,\r
+ scsiDev.target->cfg->sectorsPerTrack);\r
\r
scsiDev.data[idx+2] = cyl >> 16;\r
scsiDev.data[idx+3] = cyl >> 8;\r
\r
memcpy(&scsiDev.data[idx+6], &scsiDev.data[idx+2], 3);\r
memcpy(&scsiDev.data[idx+9], &scsiDev.data[idx+2], 3);\r
+\r
+ scsiDev.data[idx+5] = scsiDev.target->cfg->headsPerCylinder;\r
}\r
\r
if ((scsiDev.compatMode >= COMPAT_SCSI2))\r
/* USBFS_ep_1 */\r
#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_1__INTC_MASK 0x40u\r
-#define USBFS_ep_1__INTC_NUMBER 6u\r
+#define USBFS_ep_1__INTC_MASK 0x80u\r
+#define USBFS_ep_1__INTC_NUMBER 7u\r
#define USBFS_ep_1__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6\r
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7\r
#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_2 */\r
#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_2__INTC_MASK 0x80u\r
-#define USBFS_ep_2__INTC_NUMBER 7u\r
+#define USBFS_ep_2__INTC_MASK 0x100u\r
+#define USBFS_ep_2__INTC_NUMBER 8u\r
#define USBFS_ep_2__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7\r
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8\r
#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_3 */\r
#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_3__INTC_MASK 0x100u\r
-#define USBFS_ep_3__INTC_NUMBER 8u\r
+#define USBFS_ep_3__INTC_MASK 0x200u\r
+#define USBFS_ep_3__INTC_NUMBER 9u\r
#define USBFS_ep_3__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8\r
+#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9\r
#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_4 */\r
#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_4__INTC_MASK 0x200u\r
-#define USBFS_ep_4__INTC_NUMBER 9u\r
+#define USBFS_ep_4__INTC_MASK 0x400u\r
+#define USBFS_ep_4__INTC_NUMBER 10u\r
#define USBFS_ep_4__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_9\r
+#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10\r
#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1\r
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0\r
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__2__POS 2\r
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB05_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB05_ST\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
\r
/* SD_SCK */\r
#define SD_SCK__0__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL\r
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK\r
\r
/* SCSI_Out_Ctl */\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
/* SD_RX_DMA_COMPLETE */\r
#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u\r
-#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u\r
+#define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u\r
+#define SD_RX_DMA_COMPLETE__INTC_NUMBER 5u\r
#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5\r
#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* SD_TX_DMA_COMPLETE */\r
#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u\r
-#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u\r
+#define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u\r
+#define SD_TX_DMA_COMPLETE__INTC_NUMBER 6u\r
#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5\r
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6\r
#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* SCSI_TX_DMA_COMPLETE */\r
#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u\r
#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
+/* SCSI_SEL_ISR */\r
+#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_SEL_ISR__INTC_MASK 0x08u\r
+#define SCSI_SEL_ISR__INTC_NUMBER 3u\r
+#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u\r
+#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
+#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
/* SCSI_Filtered */\r
#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u\r
#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST\r
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB13_MSK\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB13_ST\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK\r
+#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST\r
\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
/* SCSI_Parity_Error */\r
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST\r
\r
/* Miscellaneous */\r
#define BCLK__BUS_CLK__HZ 50000000U\r
#define CYDEV_ECC_ENABLE 0\r
#define CYDEV_HEAP_SIZE 0x0400\r
#define CYDEV_INSTRUCT_CACHE_ENABLED 1\r
-#define CYDEV_INTR_RISING 0x0000003Eu\r
+#define CYDEV_INTR_RISING 0x0000007Eu\r
#define CYDEV_PROJ_TYPE 2\r
#define CYDEV_PROJ_TYPE_BOOTLOADER 1\r
#define CYDEV_PROJ_TYPE_LOADABLE 2\r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 41u\r
+#define CY_CFG_BASE_ADDR_COUNT 40u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
0x4000520Cu, /* Base address: 0x40005200 Count: 12 */\r
0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
- 0x4001003Eu, /* Base address: 0x40010000 Count: 62 */\r
- 0x40010137u, /* Base address: 0x40010100 Count: 55 */\r
- 0x40010246u, /* Base address: 0x40010200 Count: 70 */\r
- 0x40010350u, /* Base address: 0x40010300 Count: 80 */\r
- 0x4001044Eu, /* Base address: 0x40010400 Count: 78 */\r
- 0x4001054Eu, /* Base address: 0x40010500 Count: 78 */\r
- 0x40010654u, /* Base address: 0x40010600 Count: 84 */\r
- 0x40010750u, /* Base address: 0x40010700 Count: 80 */\r
- 0x40010851u, /* Base address: 0x40010800 Count: 81 */\r
- 0x40010958u, /* Base address: 0x40010900 Count: 88 */\r
- 0x40010A46u, /* Base address: 0x40010A00 Count: 70 */\r
- 0x40010B4Eu, /* Base address: 0x40010B00 Count: 78 */\r
- 0x40010C46u, /* Base address: 0x40010C00 Count: 70 */\r
- 0x40010D4Au, /* Base address: 0x40010D00 Count: 74 */\r
- 0x40010F06u, /* Base address: 0x40010F00 Count: 6 */\r
- 0x4001145Fu, /* Base address: 0x40011400 Count: 95 */\r
- 0x40011558u, /* Base address: 0x40011500 Count: 88 */\r
- 0x4001164Eu, /* Base address: 0x40011600 Count: 78 */\r
- 0x40011750u, /* Base address: 0x40011700 Count: 80 */\r
- 0x40011804u, /* Base address: 0x40011800 Count: 4 */\r
- 0x40011913u, /* Base address: 0x40011900 Count: 19 */\r
- 0x40011B0Cu, /* Base address: 0x40011B00 Count: 12 */\r
+ 0x40010036u, /* Base address: 0x40010000 Count: 54 */\r
+ 0x4001013Du, /* Base address: 0x40010100 Count: 61 */\r
+ 0x40010243u, /* Base address: 0x40010200 Count: 67 */\r
+ 0x40010358u, /* Base address: 0x40010300 Count: 88 */\r
+ 0x40010448u, /* Base address: 0x40010400 Count: 72 */\r
+ 0x40010555u, /* Base address: 0x40010500 Count: 85 */\r
+ 0x4001064Cu, /* Base address: 0x40010600 Count: 76 */\r
+ 0x40010746u, /* Base address: 0x40010700 Count: 70 */\r
+ 0x4001083Fu, /* Base address: 0x40010800 Count: 63 */\r
+ 0x40010948u, /* Base address: 0x40010900 Count: 72 */\r
+ 0x40010A4Du, /* Base address: 0x40010A00 Count: 77 */\r
+ 0x40010B4Au, /* Base address: 0x40010B00 Count: 74 */\r
+ 0x40010C42u, /* Base address: 0x40010C00 Count: 66 */\r
+ 0x40010D4Cu, /* Base address: 0x40010D00 Count: 76 */\r
+ 0x40010E4Cu, /* Base address: 0x40010E00 Count: 76 */\r
+ 0x40010F3Bu, /* Base address: 0x40010F00 Count: 59 */\r
+ 0x4001142Cu, /* Base address: 0x40011400 Count: 44 */\r
+ 0x40011550u, /* Base address: 0x40011500 Count: 80 */\r
+ 0x4001163Eu, /* Base address: 0x40011600 Count: 62 */\r
+ 0x4001173Fu, /* Base address: 0x40011700 Count: 63 */\r
+ 0x40011904u, /* Base address: 0x40011900 Count: 4 */\r
+ 0x40011B02u, /* Base address: 0x40011B00 Count: 2 */\r
0x4001401Bu, /* Base address: 0x40014000 Count: 27 */\r
- 0x4001411Eu, /* Base address: 0x40014100 Count: 30 */\r
- 0x4001420Bu, /* Base address: 0x40014200 Count: 11 */\r
- 0x4001430Cu, /* Base address: 0x40014300 Count: 12 */\r
- 0x4001440Du, /* Base address: 0x40014400 Count: 13 */\r
- 0x40014518u, /* Base address: 0x40014500 Count: 24 */\r
- 0x40014611u, /* Base address: 0x40014600 Count: 17 */\r
- 0x40014711u, /* Base address: 0x40014700 Count: 17 */\r
- 0x4001480Cu, /* Base address: 0x40014800 Count: 12 */\r
- 0x4001490Fu, /* Base address: 0x40014900 Count: 15 */\r
- 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */\r
- 0x40014D06u, /* Base address: 0x40014D00 Count: 6 */\r
+ 0x4001411Bu, /* Base address: 0x40014100 Count: 27 */\r
+ 0x40014211u, /* Base address: 0x40014200 Count: 17 */\r
+ 0x4001430Du, /* Base address: 0x40014300 Count: 13 */\r
+ 0x40014411u, /* Base address: 0x40014400 Count: 17 */\r
+ 0x40014517u, /* Base address: 0x40014500 Count: 23 */\r
+ 0x40014608u, /* Base address: 0x40014600 Count: 8 */\r
+ 0x4001470Du, /* Base address: 0x40014700 Count: 13 */\r
+ 0x40014806u, /* Base address: 0x40014800 Count: 6 */\r
+ 0x40014908u, /* Base address: 0x40014900 Count: 8 */\r
+ 0x40014D04u, /* Base address: 0x40014D00 Count: 4 */\r
0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
- {0x0Au, 0x36u},\r
- {0x00u, 0x04u},\r
- {0x01u, 0x11u},\r
- {0x18u, 0x0Cu},\r
+ {0x0Au, 0x4Bu},\r
+ {0x00u, 0x11u},\r
+ {0x01u, 0x02u},\r
+ {0x18u, 0x08u},\r
{0x19u, 0x04u},\r
{0x1Cu, 0x71u},\r
- {0x20u, 0x60u},\r
- {0x21u, 0xC0u},\r
+ {0x20u, 0xA0u},\r
+ {0x21u, 0x68u},\r
{0x2Cu, 0x0Eu},\r
- {0x30u, 0x05u},\r
+ {0x30u, 0x0Au},\r
{0x31u, 0x0Cu},\r
{0x34u, 0x80u},\r
{0x7Cu, 0x40u},\r
{0x20u, 0x02u},\r
- {0x86u, 0x0Fu},\r
- {0x02u, 0x07u},\r
- {0x06u, 0x70u},\r
- {0x08u, 0xAAu},\r
- {0x0Au, 0x55u},\r
- {0x0Eu, 0x08u},\r
- {0x11u, 0x01u},\r
- {0x15u, 0x08u},\r
- {0x20u, 0x44u},\r
- {0x22u, 0x88u},\r
- {0x26u, 0x80u},\r
- {0x28u, 0x99u},\r
- {0x29u, 0x02u},\r
- {0x2Au, 0x22u},\r
- {0x2Du, 0x04u},\r
- {0x30u, 0x0Fu},\r
- {0x31u, 0x04u},\r
- {0x33u, 0x02u},\r
- {0x34u, 0xF0u},\r
- {0x35u, 0x08u},\r
- {0x37u, 0x01u},\r
+ {0x84u, 0x0Fu},\r
+ {0x00u, 0x80u},\r
+ {0x04u, 0x10u},\r
+ {0x0Cu, 0x02u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Eu, 0x28u},\r
+ {0x10u, 0x01u},\r
+ {0x14u, 0x32u},\r
+ {0x15u, 0x04u},\r
+ {0x16u, 0x44u},\r
+ {0x1Au, 0x04u},\r
+ {0x1Du, 0x08u},\r
+ {0x24u, 0x4Cu},\r
+ {0x26u, 0x32u},\r
+ {0x29u, 0x01u},\r
+ {0x2Eu, 0x7Eu},\r
+ {0x30u, 0x0Eu},\r
+ {0x31u, 0x08u},\r
+ {0x32u, 0x70u},\r
+ {0x33u, 0x04u},\r
+ {0x34u, 0x01u},\r
+ {0x35u, 0x01u},\r
+ {0x36u, 0x80u},\r
+ {0x37u, 0x02u},\r
+ {0x3Eu, 0x50u},\r
{0x3Fu, 0x55u},\r
- {0x40u, 0x56u},\r
- {0x41u, 0x02u},\r
- {0x42u, 0x30u},\r
+ {0x40u, 0x42u},\r
+ {0x41u, 0x03u},\r
+ {0x42u, 0x50u},\r
{0x45u, 0xF2u},\r
{0x46u, 0xCDu},\r
{0x47u, 0x0Eu},\r
{0x68u, 0x40u},\r
{0x69u, 0x40u},\r
{0x6Eu, 0x08u},\r
- {0x85u, 0x08u},\r
- {0x8Bu, 0x3Fu},\r
- {0x8Du, 0x40u},\r
- {0x91u, 0x01u},\r
- {0x93u, 0x14u},\r
- {0x95u, 0x19u},\r
- {0x97u, 0x22u},\r
- {0x99u, 0x26u},\r
- {0x9Bu, 0x19u},\r
- {0xABu, 0x02u},\r
- {0xB1u, 0x07u},\r
- {0xB3u, 0x40u},\r
- {0xB5u, 0x38u},\r
- {0xBFu, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDCu, 0x10u},\r
+ {0x88u, 0x01u},\r
+ {0xB6u, 0x01u},\r
+ {0xBEu, 0x40u},\r
+ {0xD8u, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x80u},\r
- {0x01u, 0x22u},\r
- {0x03u, 0x20u},\r
- {0x11u, 0x22u},\r
- {0x13u, 0x04u},\r
- {0x19u, 0x02u},\r
- {0x1Bu, 0x20u},\r
+ {0x00u, 0x41u},\r
+ {0x03u, 0x10u},\r
+ {0x05u, 0x10u},\r
+ {0x0Au, 0x10u},\r
+ {0x0Bu, 0x44u},\r
+ {0x11u, 0x40u},\r
+ {0x12u, 0x20u},\r
+ {0x18u, 0x40u},\r
+ {0x19u, 0x48u},\r
+ {0x1Au, 0x10u},\r
+ {0x1Bu, 0x12u},\r
+ {0x1Du, 0x80u},\r
{0x20u, 0x04u},\r
- {0x21u, 0x80u},\r
- {0x22u, 0x05u},\r
- {0x25u, 0x31u},\r
- {0x26u, 0x01u},\r
- {0x27u, 0x58u},\r
- {0x28u, 0x02u},\r
- {0x2Au, 0x08u},\r
- {0x2Bu, 0x24u},\r
- {0x2Fu, 0x04u},\r
- {0x31u, 0x06u},\r
- {0x35u, 0x20u},\r
- {0x36u, 0x01u},\r
- {0x37u, 0x08u},\r
- {0x3Du, 0x04u},\r
- {0x3Eu, 0x90u},\r
- {0x41u, 0x30u},\r
- {0x43u, 0x08u},\r
- {0x49u, 0x10u},\r
- {0x4Au, 0x01u},\r
- {0x4Bu, 0x0Au},\r
- {0x50u, 0x08u},\r
- {0x52u, 0x90u},\r
- {0x5Au, 0x8Au},\r
- {0x5Bu, 0x10u},\r
- {0x60u, 0x54u},\r
- {0x61u, 0x80u},\r
- {0x68u, 0x40u},\r
- {0x69u, 0x50u},\r
- {0x6Au, 0x04u},\r
- {0x70u, 0x02u},\r
- {0x72u, 0x20u},\r
- {0x73u, 0x06u},\r
- {0x83u, 0x01u},\r
- {0x85u, 0x10u},\r
- {0x8Cu, 0x08u},\r
- {0xC0u, 0x0Fu},\r
- {0xC4u, 0x0Eu},\r
- {0xCAu, 0x2Cu},\r
- {0xCCu, 0xE3u},\r
- {0xCEu, 0x70u},\r
- {0xD0u, 0x06u},\r
- {0xD2u, 0x0Cu},\r
+ {0x21u, 0x02u},\r
+ {0x23u, 0x22u},\r
+ {0x2Bu, 0x04u},\r
+ {0x31u, 0x04u},\r
+ {0x32u, 0x80u},\r
+ {0x3Au, 0x40u},\r
+ {0x41u, 0x10u},\r
+ {0x42u, 0x10u},\r
+ {0x43u, 0x02u},\r
+ {0x48u, 0x01u},\r
+ {0x49u, 0x02u},\r
+ {0x4Bu, 0x04u},\r
+ {0x50u, 0x10u},\r
+ {0x52u, 0x04u},\r
+ {0x53u, 0x80u},\r
+ {0x59u, 0x40u},\r
+ {0x5Au, 0x08u},\r
+ {0x5Bu, 0x22u},\r
+ {0x60u, 0x04u},\r
+ {0x61u, 0x82u},\r
+ {0x63u, 0x20u},\r
+ {0x68u, 0x90u},\r
+ {0x69u, 0x10u},\r
+ {0x6Au, 0x80u},\r
+ {0x70u, 0x60u},\r
+ {0x72u, 0x40u},\r
+ {0x73u, 0x10u},\r
+ {0x81u, 0x02u},\r
+ {0x83u, 0x10u},\r
+ {0x85u, 0x40u},\r
+ {0x88u, 0x40u},\r
+ {0x89u, 0x08u},\r
+ {0x8Cu, 0x40u},\r
+ {0x8Eu, 0x10u},\r
+ {0xC0u, 0x4Du},\r
+ {0xC2u, 0x0Eu},\r
+ {0xC4u, 0x05u},\r
+ {0xCAu, 0x04u},\r
+ {0xCCu, 0x0Au},\r
+ {0xCEu, 0x08u},\r
+ {0xD0u, 0x07u},\r
+ {0xD2u, 0x08u},\r
{0xD6u, 0x0Fu},\r
{0xD8u, 0x0Fu},\r
- {0xE2u, 0x01u},\r
- {0xE4u, 0x0Cu},\r
- {0xE6u, 0x10u},\r
- {0x00u, 0x08u},\r
- {0x01u, 0x47u},\r
- {0x02u, 0x04u},\r
- {0x03u, 0x88u},\r
- {0x07u, 0x80u},\r
- {0x09u, 0x95u},\r
- {0x0Bu, 0x2Au},\r
- {0x11u, 0x03u},\r
- {0x13u, 0x0Cu},\r
- {0x14u, 0x04u},\r
- {0x16u, 0x08u},\r
- {0x17u, 0x70u},\r
- {0x18u, 0x08u},\r
- {0x19u, 0xA6u},\r
- {0x1Au, 0x14u},\r
- {0x1Bu, 0x59u},\r
- {0x1Cu, 0x08u},\r
- {0x1Eu, 0x05u},\r
- {0x23u, 0x03u},\r
- {0x25u, 0x01u},\r
- {0x2Bu, 0x02u},\r
- {0x2Cu, 0x08u},\r
- {0x2Eu, 0x06u},\r
- {0x30u, 0x01u},\r
- {0x31u, 0x0Fu},\r
- {0x32u, 0x0Cu},\r
- {0x34u, 0x02u},\r
- {0x35u, 0xF0u},\r
- {0x36u, 0x10u},\r
- {0x3Au, 0x08u},\r
- {0x3Bu, 0x02u},\r
+ {0xE0u, 0x06u},\r
+ {0xE2u, 0x10u},\r
+ {0xE4u, 0x04u},\r
+ {0xE6u, 0x20u},\r
+ {0x09u, 0x05u},\r
+ {0x0Bu, 0x0Au},\r
+ {0x0Du, 0x0Fu},\r
+ {0x0Eu, 0x01u},\r
+ {0x0Fu, 0xF0u},\r
+ {0x10u, 0x01u},\r
+ {0x12u, 0x02u},\r
+ {0x15u, 0x60u},\r
+ {0x17u, 0x90u},\r
+ {0x19u, 0x30u},\r
+ {0x1Bu, 0xC0u},\r
+ {0x1Du, 0x06u},\r
+ {0x1Fu, 0x09u},\r
+ {0x21u, 0x03u},\r
+ {0x23u, 0x0Cu},\r
+ {0x25u, 0x50u},\r
+ {0x26u, 0x02u},\r
+ {0x27u, 0xA0u},\r
+ {0x30u, 0x03u},\r
+ {0x37u, 0xFFu},\r
+ {0x3Eu, 0x01u},\r
+ {0x3Fu, 0x40u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x19u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x02u},\r
- {0x84u, 0x03u},\r
- {0x88u, 0x10u},\r
- {0x8Au, 0x60u},\r
- {0x8Cu, 0x18u},\r
- {0x8Eu, 0x03u},\r
- {0x90u, 0x20u},\r
- {0x92u, 0x5Cu},\r
- {0x96u, 0x1Fu},\r
- {0x98u, 0x3Fu},\r
- {0x9Au, 0x40u},\r
- {0xA0u, 0x80u},\r
- {0xA5u, 0x01u},\r
- {0xA6u, 0x01u},\r
- {0xA8u, 0x27u},\r
- {0xA9u, 0x02u},\r
- {0xAAu, 0x50u},\r
- {0xB0u, 0x80u},\r
- {0xB1u, 0x02u},\r
- {0xB2u, 0x70u},\r
- {0xB3u, 0x01u},\r
- {0xB4u, 0x0Fu},\r
- {0xBAu, 0x08u},\r
- {0xBEu, 0x01u},\r
- {0xBFu, 0x05u},\r
+ {0x83u, 0x1Fu},\r
+ {0x85u, 0x3Fu},\r
+ {0x86u, 0x70u},\r
+ {0x87u, 0x40u},\r
+ {0x89u, 0x03u},\r
+ {0x8Cu, 0x44u},\r
+ {0x8Du, 0x20u},\r
+ {0x8Eu, 0x88u},\r
+ {0x8Fu, 0x5Cu},\r
+ {0x94u, 0x99u},\r
+ {0x95u, 0x18u},\r
+ {0x96u, 0x22u},\r
+ {0x97u, 0x03u},\r
+ {0x98u, 0xAAu},\r
+ {0x9Au, 0x55u},\r
+ {0x9Bu, 0x01u},\r
+ {0x9Du, 0x10u},\r
+ {0x9Eu, 0x07u},\r
+ {0x9Fu, 0x60u},\r
+ {0xA1u, 0x02u},\r
+ {0xA5u, 0x27u},\r
+ {0xA6u, 0x08u},\r
+ {0xA7u, 0x50u},\r
+ {0xA9u, 0x80u},\r
+ {0xAAu, 0x80u},\r
+ {0xB3u, 0x80u},\r
+ {0xB4u, 0xF0u},\r
+ {0xB5u, 0x0Fu},\r
+ {0xB6u, 0x0Fu},\r
+ {0xB7u, 0x70u},\r
+ {0xBBu, 0x80u},\r
+ {0xBFu, 0x04u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x01u},\r
+ {0xDCu, 0x11u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x81u},\r
- {0x02u, 0x90u},\r
- {0x03u, 0x18u},\r
- {0x05u, 0x01u},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0x18u},\r
- {0x0Eu, 0x2Au},\r
- {0x11u, 0x24u},\r
- {0x12u, 0x40u},\r
- {0x16u, 0x02u},\r
- {0x19u, 0x30u},\r
- {0x1Au, 0x88u},\r
- {0x1Bu, 0x08u},\r
- {0x1Du, 0x01u},\r
- {0x1Eu, 0x3Au},\r
- {0x20u, 0x50u},\r
- {0x26u, 0x02u},\r
- {0x27u, 0x04u},\r
- {0x28u, 0x28u},\r
- {0x2Du, 0x04u},\r
- {0x2Fu, 0x84u},\r
- {0x35u, 0x20u},\r
- {0x36u, 0x02u},\r
+ {0x00u, 0x40u},\r
+ {0x03u, 0x20u},\r
+ {0x05u, 0x40u},\r
+ {0x09u, 0x20u},\r
+ {0x0Au, 0x12u},\r
+ {0x0Cu, 0x02u},\r
+ {0x0Fu, 0x80u},\r
+ {0x10u, 0x20u},\r
+ {0x13u, 0x10u},\r
+ {0x17u, 0x04u},\r
+ {0x19u, 0x40u},\r
+ {0x1Au, 0x02u},\r
+ {0x1Bu, 0x30u},\r
+ {0x1Cu, 0x80u},\r
+ {0x20u, 0x06u},\r
+ {0x21u, 0xB0u},\r
+ {0x22u, 0x24u},\r
+ {0x23u, 0x08u},\r
+ {0x25u, 0x40u},\r
+ {0x28u, 0x08u},\r
+ {0x29u, 0x08u},\r
+ {0x2Bu, 0x80u},\r
+ {0x2Du, 0x01u},\r
+ {0x2Eu, 0x04u},\r
+ {0x31u, 0x80u},\r
+ {0x32u, 0x08u},\r
+ {0x33u, 0x10u},\r
+ {0x34u, 0x10u},\r
+ {0x35u, 0x40u},\r
{0x37u, 0x04u},\r
- {0x3Du, 0x22u},\r
- {0x3Eu, 0x04u},\r
- {0x45u, 0x04u},\r
- {0x47u, 0x04u},\r
- {0x58u, 0x90u},\r
- {0x5Au, 0x02u},\r
- {0x5Bu, 0x08u},\r
- {0x5Fu, 0x80u},\r
- {0x60u, 0x02u},\r
- {0x61u, 0x06u},\r
- {0x62u, 0x05u},\r
- {0x63u, 0x08u},\r
- {0x66u, 0x80u},\r
- {0x6Du, 0x14u},\r
- {0x6Fu, 0x22u},\r
- {0x83u, 0x08u},\r
- {0x84u, 0x90u},\r
- {0x86u, 0x10u},\r
- {0x87u, 0x80u},\r
- {0x88u, 0x10u},\r
- {0x89u, 0x10u},\r
- {0x8Au, 0x02u},\r
- {0x8Du, 0x40u},\r
- {0x8Fu, 0x02u},\r
- {0x91u, 0x60u},\r
- {0x92u, 0x04u},\r
- {0x93u, 0x08u},\r
- {0x94u, 0x50u},\r
- {0x95u, 0x04u},\r
- {0x96u, 0x90u},\r
- {0x99u, 0x02u},\r
- {0x9Au, 0x38u},\r
- {0x9Bu, 0x42u},\r
- {0x9Cu, 0x02u},\r
- {0x9Du, 0x34u},\r
- {0x9Eu, 0x80u},\r
- {0xA0u, 0x02u},\r
- {0xA1u, 0x11u},\r
- {0xA2u, 0x80u},\r
- {0xA5u, 0x02u},\r
- {0xA7u, 0x0Cu},\r
- {0xA9u, 0x10u},\r
- {0xB6u, 0x01u},\r
- {0xC0u, 0x1Fu},\r
- {0xC2u, 0xEEu},\r
- {0xC4u, 0x8Eu},\r
- {0xCAu, 0xE6u},\r
- {0xCCu, 0xE0u},\r
- {0xCEu, 0xE0u},\r
- {0xD6u, 0x1Fu},\r
- {0xD8u, 0x1Fu},\r
- {0xE2u, 0xC4u},\r
+ {0x38u, 0x64u},\r
+ {0x3Au, 0x02u},\r
+ {0x3Fu, 0xA0u},\r
+ {0x58u, 0x66u},\r
+ {0x5Du, 0x80u},\r
+ {0x5Fu, 0x20u},\r
+ {0x61u, 0x04u},\r
+ {0x62u, 0x80u},\r
+ {0x63u, 0x48u},\r
+ {0x65u, 0x30u},\r
+ {0x66u, 0x40u},\r
+ {0x67u, 0x02u},\r
+ {0x6Du, 0x28u},\r
+ {0x6Eu, 0x80u},\r
+ {0x6Fu, 0x10u},\r
+ {0x80u, 0x30u},\r
+ {0x85u, 0x80u},\r
+ {0x86u, 0x40u},\r
+ {0x87u, 0xA0u},\r
+ {0x88u, 0x42u},\r
+ {0x8Au, 0x0Au},\r
+ {0x8Du, 0x04u},\r
+ {0x90u, 0x60u},\r
+ {0x91u, 0x10u},\r
+ {0x92u, 0xF0u},\r
+ {0x93u, 0x14u},\r
+ {0x94u, 0x01u},\r
+ {0x95u, 0x60u},\r
+ {0x96u, 0x08u},\r
+ {0x97u, 0x40u},\r
+ {0x99u, 0x08u},\r
+ {0x9Du, 0x14u},\r
+ {0x9Eu, 0x40u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA0u, 0xA0u},\r
+ {0xA3u, 0x82u},\r
+ {0xA4u, 0x45u},\r
+ {0xA5u, 0x40u},\r
+ {0xA6u, 0xA0u},\r
+ {0xA7u, 0x04u},\r
+ {0xAAu, 0x04u},\r
+ {0xACu, 0x14u},\r
+ {0xADu, 0x10u},\r
+ {0xB7u, 0x02u},\r
+ {0xC0u, 0x85u},\r
+ {0xC2u, 0x17u},\r
+ {0xC4u, 0x26u},\r
+ {0xCAu, 0xC7u},\r
+ {0xCCu, 0x7Eu},\r
+ {0xCEu, 0x3Fu},\r
+ {0xD6u, 0x3Fu},\r
+ {0xD8u, 0x3Fu},\r
+ {0xE0u, 0x04u},\r
+ {0xE2u, 0x0Au},\r
{0xE4u, 0x08u},\r
- {0xE6u, 0xE2u},\r
- {0xE8u, 0x01u},\r
- {0xEEu, 0x02u},\r
- {0x02u, 0xFFu},\r
- {0x04u, 0x0Fu},\r
- {0x05u, 0x0Fu},\r
- {0x06u, 0xF0u},\r
- {0x08u, 0x69u},\r
- {0x09u, 0x90u},\r
- {0x0Au, 0x96u},\r
- {0x0Bu, 0x2Fu},\r
- {0x0Cu, 0xFFu},\r
- {0x10u, 0x33u},\r
- {0x12u, 0xCCu},\r
- {0x13u, 0x70u},\r
- {0x15u, 0x03u},\r
- {0x16u, 0xFFu},\r
- {0x17u, 0x0Cu},\r
- {0x18u, 0xFFu},\r
- {0x1Bu, 0x80u},\r
- {0x1Du, 0xC0u},\r
- {0x1Fu, 0x1Fu},\r
- {0x21u, 0x06u},\r
- {0x23u, 0x09u},\r
- {0x25u, 0x05u},\r
- {0x27u, 0x0Au},\r
- {0x29u, 0xA0u},\r
- {0x2Au, 0xFFu},\r
- {0x2Bu, 0x4Fu},\r
- {0x2Cu, 0x55u},\r
- {0x2Eu, 0xAAu},\r
- {0x2Fu, 0x80u},\r
- {0x31u, 0x7Fu},\r
- {0x32u, 0xFFu},\r
- {0x35u, 0x80u},\r
- {0x3Au, 0x08u},\r
+ {0xE6u, 0x24u},\r
+ {0xE8u, 0x0Bu},\r
+ {0xEEu, 0x01u},\r
+ {0x02u, 0x07u},\r
+ {0x07u, 0x10u},\r
+ {0x09u, 0x0Au},\r
+ {0x0Bu, 0x05u},\r
+ {0x0Cu, 0x44u},\r
+ {0x0Du, 0x04u},\r
+ {0x0Eu, 0x88u},\r
+ {0x0Fu, 0x08u},\r
+ {0x11u, 0x10u},\r
+ {0x13u, 0x20u},\r
+ {0x14u, 0x99u},\r
+ {0x16u, 0x22u},\r
+ {0x17u, 0x07u},\r
+ {0x1Eu, 0x70u},\r
+ {0x1Fu, 0x08u},\r
+ {0x22u, 0x80u},\r
+ {0x23u, 0x20u},\r
+ {0x24u, 0xAAu},\r
+ {0x25u, 0x09u},\r
+ {0x26u, 0x55u},\r
+ {0x27u, 0x02u},\r
+ {0x2Au, 0x08u},\r
+ {0x30u, 0x0Fu},\r
+ {0x33u, 0x0Fu},\r
+ {0x35u, 0x30u},\r
+ {0x36u, 0xF0u},\r
{0x3Fu, 0x10u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x83u, 0x7Cu},\r
- {0x84u, 0x40u},\r
- {0x85u, 0x48u},\r
- {0x86u, 0x80u},\r
- {0x87u, 0x03u},\r
- {0x88u, 0x20u},\r
- {0x8Au, 0x18u},\r
- {0x92u, 0x01u},\r
- {0x93u, 0x01u},\r
- {0x94u, 0x18u},\r
- {0x95u, 0x70u},\r
- {0x96u, 0x25u},\r
- {0x98u, 0x2Eu},\r
- {0x99u, 0x04u},\r
- {0x9Au, 0x10u},\r
- {0x9Bu, 0x23u},\r
- {0x9Du, 0x11u},\r
- {0x9Fu, 0x02u},\r
- {0xA0u, 0x08u},\r
- {0xA2u, 0x33u},\r
- {0xA6u, 0x80u},\r
- {0xAAu, 0x40u},\r
- {0xAFu, 0x02u},\r
- {0xB0u, 0x07u},\r
- {0xB1u, 0x0Fu},\r
- {0xB2u, 0xC0u},\r
- {0xB3u, 0x70u},\r
- {0xB4u, 0x38u},\r
- {0xBAu, 0x20u},\r
- {0xBEu, 0x04u},\r
- {0xBFu, 0x04u},\r
- {0xD4u, 0x01u},\r
+ {0x84u, 0x10u},\r
+ {0x85u, 0x69u},\r
+ {0x86u, 0x20u},\r
+ {0x87u, 0x96u},\r
+ {0x88u, 0x06u},\r
+ {0x8Au, 0x09u},\r
+ {0x8Bu, 0xFFu},\r
+ {0x8Cu, 0x07u},\r
+ {0x8Eu, 0x08u},\r
+ {0x8Fu, 0xFFu},\r
+ {0x90u, 0x03u},\r
+ {0x91u, 0x0Fu},\r
+ {0x92u, 0x0Cu},\r
+ {0x93u, 0xF0u},\r
+ {0x94u, 0x05u},\r
+ {0x95u, 0xFFu},\r
+ {0x96u, 0x0Au},\r
+ {0x99u, 0xFFu},\r
+ {0x9Au, 0x02u},\r
+ {0xA2u, 0x10u},\r
+ {0xA3u, 0xFFu},\r
+ {0xA6u, 0x20u},\r
+ {0xA8u, 0x01u},\r
+ {0xA9u, 0x55u},\r
+ {0xABu, 0xAAu},\r
+ {0xADu, 0x33u},\r
+ {0xAEu, 0x03u},\r
+ {0xAFu, 0xCCu},\r
+ {0xB0u, 0x0Fu},\r
+ {0xB4u, 0x30u},\r
+ {0xB7u, 0xFFu},\r
+ {0xBAu, 0x02u},\r
+ {0xBBu, 0x80u},\r
+ {0xBEu, 0x10u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDDu, 0x10u},\r
+ {0xDCu, 0x11u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x88u},\r
- {0x02u, 0x04u},\r
- {0x03u, 0x40u},\r
- {0x04u, 0x08u},\r
- {0x05u, 0x10u},\r
- {0x08u, 0x02u},\r
- {0x0Au, 0x18u},\r
- {0x0Eu, 0x64u},\r
- {0x11u, 0x20u},\r
- {0x12u, 0x01u},\r
- {0x14u, 0x50u},\r
- {0x15u, 0x02u},\r
- {0x16u, 0x08u},\r
- {0x19u, 0x08u},\r
- {0x1Cu, 0x20u},\r
- {0x1Du, 0x10u},\r
- {0x1Eu, 0x40u},\r
- {0x1Fu, 0x10u},\r
+ {0x00u, 0x40u},\r
+ {0x01u, 0x02u},\r
+ {0x04u, 0x40u},\r
+ {0x06u, 0x20u},\r
+ {0x07u, 0x08u},\r
+ {0x0Au, 0x12u},\r
+ {0x0Eu, 0x90u},\r
+ {0x0Fu, 0x04u},\r
+ {0x10u, 0x80u},\r
+ {0x11u, 0x10u},\r
+ {0x13u, 0x08u},\r
+ {0x14u, 0x10u},\r
+ {0x15u, 0x01u},\r
+ {0x16u, 0x12u},\r
+ {0x17u, 0x10u},\r
+ {0x19u, 0x02u},\r
+ {0x1Au, 0x02u},\r
+ {0x1Du, 0x20u},\r
+ {0x1Eu, 0x80u},\r
{0x20u, 0x08u},\r
- {0x21u, 0x02u},\r
- {0x23u, 0x80u},\r
- {0x25u, 0x09u},\r
- {0x29u, 0xA8u},\r
+ {0x21u, 0x08u},\r
+ {0x27u, 0x01u},\r
+ {0x29u, 0x08u},\r
{0x2Bu, 0x40u},\r
+ {0x2Du, 0x20u},\r
+ {0x2Eu, 0x02u},\r
{0x2Fu, 0x01u},\r
- {0x31u, 0x02u},\r
- {0x32u, 0x08u},\r
- {0x33u, 0x50u},\r
- {0x34u, 0x40u},\r
- {0x35u, 0x01u},\r
- {0x36u, 0x10u},\r
- {0x37u, 0x04u},\r
- {0x39u, 0x24u},\r
- {0x3Du, 0x02u},\r
- {0x3Eu, 0x04u},\r
- {0x4Cu, 0x0Cu},\r
- {0x58u, 0x80u},\r
- {0x59u, 0x04u},\r
- {0x5Bu, 0x20u},\r
- {0x5Fu, 0x80u},\r
- {0x60u, 0x38u},\r
- {0x62u, 0x40u},\r
- {0x63u, 0x02u},\r
- {0x80u, 0x10u},\r
- {0x88u, 0x04u},\r
- {0x8Eu, 0x0Au},\r
- {0x8Fu, 0x40u},\r
- {0x91u, 0xE4u},\r
- {0x92u, 0x18u},\r
- {0x98u, 0x02u},\r
- {0x99u, 0x22u},\r
- {0x9Au, 0xADu},\r
- {0x9Bu, 0x52u},\r
- {0x9Cu, 0x28u},\r
- {0x9Du, 0x80u},\r
- {0x9Eu, 0x42u},\r
- {0xA0u, 0x02u},\r
- {0xA1u, 0x14u},\r
- {0xA3u, 0x24u},\r
- {0xA4u, 0x10u},\r
- {0xABu, 0x80u},\r
- {0xADu, 0x01u},\r
- {0xAEu, 0x11u},\r
- {0xAFu, 0x20u},\r
- {0xB1u, 0x20u},\r
- {0xC0u, 0x6Fu},\r
- {0xC2u, 0x7Eu},\r
- {0xC4u, 0x73u},\r
- {0xCAu, 0x1Fu},\r
- {0xCCu, 0xFFu},\r
- {0xCEu, 0xC6u},\r
- {0xD6u, 0x1Eu},\r
- {0xD8u, 0x0Eu},\r
- {0xE4u, 0x01u},\r
- {0xE6u, 0x10u},\r
- {0xE8u, 0x0Au},\r
- {0xEAu, 0x01u},\r
- {0xEEu, 0x02u},\r
- {0x00u, 0x04u},\r
- {0x01u, 0x33u},\r
- {0x02u, 0x20u},\r
- {0x03u, 0xCCu},\r
- {0x04u, 0x42u},\r
- {0x05u, 0x69u},\r
- {0x07u, 0x96u},\r
- {0x08u, 0x01u},\r
- {0x0Au, 0x5Eu},\r
- {0x0Bu, 0xFFu},\r
- {0x10u, 0x77u},\r
- {0x12u, 0x08u},\r
- {0x14u, 0x39u},\r
- {0x15u, 0xFFu},\r
- {0x16u, 0x06u},\r
- {0x19u, 0x0Fu},\r
- {0x1Bu, 0xF0u},\r
- {0x1Cu, 0x46u},\r
- {0x1Fu, 0xFFu},\r
- {0x20u, 0x46u},\r
- {0x25u, 0xFFu},\r
- {0x26u, 0x46u},\r
- {0x28u, 0x42u},\r
- {0x2Au, 0x04u},\r
- {0x2Bu, 0xFFu},\r
- {0x2Cu, 0x46u},\r
- {0x2Du, 0x55u},\r
- {0x2Fu, 0xAAu},\r
- {0x30u, 0x08u},\r
- {0x32u, 0x0Fu},\r
- {0x33u, 0xFFu},\r
+ {0x30u, 0x02u},\r
+ {0x31u, 0x08u},\r
+ {0x32u, 0x40u},\r
+ {0x36u, 0x28u},\r
+ {0x37u, 0x01u},\r
+ {0x38u, 0x48u},\r
+ {0x39u, 0x20u},\r
+ {0x3Cu, 0x40u},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x08u},\r
+ {0x5Bu, 0xA0u},\r
+ {0x60u, 0x09u},\r
+ {0x68u, 0x02u},\r
+ {0x80u, 0x01u},\r
+ {0x83u, 0x10u},\r
+ {0x85u, 0x02u},\r
+ {0x89u, 0x10u},\r
+ {0x8Au, 0x40u},\r
+ {0x8Cu, 0x24u},\r
+ {0x8Du, 0x10u},\r
+ {0x8Eu, 0x02u},\r
+ {0x90u, 0x40u},\r
+ {0x91u, 0x30u},\r
+ {0x92u, 0xF0u},\r
+ {0x93u, 0x46u},\r
+ {0x94u, 0x01u},\r
+ {0x95u, 0x01u},\r
+ {0x99u, 0x28u},\r
+ {0x9Bu, 0x98u},\r
+ {0x9Cu, 0x18u},\r
+ {0x9Fu, 0x04u},\r
+ {0xA0u, 0x80u},\r
+ {0xA1u, 0x04u},\r
+ {0xA2u, 0xA8u},\r
+ {0xA3u, 0x06u},\r
+ {0xA4u, 0x06u},\r
+ {0xA6u, 0x02u},\r
+ {0xABu, 0xB0u},\r
+ {0xACu, 0x04u},\r
+ {0xB2u, 0x04u},\r
+ {0xB3u, 0x08u},\r
+ {0xB5u, 0x50u},\r
+ {0xB6u, 0x02u},\r
+ {0xC0u, 0xE9u},\r
+ {0xC2u, 0x75u},\r
+ {0xC4u, 0xFEu},\r
+ {0xCAu, 0xB3u},\r
+ {0xCCu, 0xEBu},\r
+ {0xCEu, 0x7Eu},\r
+ {0xD6u, 0x0Cu},\r
+ {0xD8u, 0x0Cu},\r
+ {0xE0u, 0x05u},\r
+ {0xE2u, 0x20u},\r
+ {0xE4u, 0x08u},\r
+ {0xE6u, 0x80u},\r
+ {0xEAu, 0x09u},\r
+ {0xECu, 0x04u},\r
+ {0xEEu, 0x10u},\r
+ {0x00u, 0x0Du},\r
+ {0x04u, 0x01u},\r
+ {0x05u, 0x0Fu},\r
+ {0x06u, 0x32u},\r
+ {0x08u, 0x62u},\r
+ {0x09u, 0x03u},\r
+ {0x0Au, 0x08u},\r
+ {0x0Bu, 0x0Cu},\r
+ {0x10u, 0x02u},\r
+ {0x11u, 0x05u},\r
+ {0x12u, 0x0Du},\r
+ {0x13u, 0x0Au},\r
+ {0x14u, 0x0Du},\r
+ {0x15u, 0x20u},\r
+ {0x17u, 0x4Fu},\r
+ {0x1Au, 0x10u},\r
+ {0x1Cu, 0x02u},\r
+ {0x1Eu, 0x54u},\r
+ {0x1Fu, 0x70u},\r
+ {0x20u, 0x0Du},\r
+ {0x24u, 0x0Du},\r
+ {0x25u, 0x06u},\r
+ {0x27u, 0x09u},\r
+ {0x29u, 0x10u},\r
+ {0x2Bu, 0x2Fu},\r
+ {0x2Cu, 0x0Du},\r
+ {0x2Du, 0x40u},\r
+ {0x2Fu, 0x1Fu},\r
+ {0x30u, 0x0Fu},\r
+ {0x31u, 0x7Fu},\r
{0x34u, 0x70u},\r
- {0x38u, 0x08u},\r
- {0x3Au, 0x30u},\r
- {0x3Bu, 0x08u},\r
- {0x3Eu, 0x01u},\r
+ {0x3Au, 0x02u},\r
+ {0x54u, 0x01u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
{0x5Cu, 0x10u},\r
+ {0x5Du, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0xFFu},\r
- {0x86u, 0xFFu},\r
- {0x87u, 0xFFu},\r
- {0x88u, 0x50u},\r
- {0x8Au, 0xA0u},\r
- {0x8Bu, 0xFFu},\r
- {0x8Cu, 0x09u},\r
- {0x8Du, 0x05u},\r
- {0x8Eu, 0x06u},\r
- {0x8Fu, 0x0Au},\r
- {0x90u, 0x05u},\r
- {0x92u, 0x0Au},\r
- {0x94u, 0x90u},\r
- {0x95u, 0x0Fu},\r
- {0x96u, 0x60u},\r
- {0x97u, 0xF0u},\r
- {0x9Bu, 0xFFu},\r
- {0x9Cu, 0x03u},\r
- {0x9Du, 0x30u},\r
- {0x9Eu, 0x0Cu},\r
- {0x9Fu, 0xC0u},\r
- {0xA0u, 0x30u},\r
- {0xA1u, 0x03u},\r
- {0xA2u, 0xC0u},\r
- {0xA3u, 0x0Cu},\r
+ {0x80u, 0x96u},\r
+ {0x82u, 0x69u},\r
+ {0x85u, 0x02u},\r
+ {0x87u, 0x11u},\r
+ {0x88u, 0x0Fu},\r
+ {0x8Au, 0xF0u},\r
+ {0x8Du, 0x01u},\r
+ {0x8Eu, 0xFFu},\r
+ {0x8Fu, 0x02u},\r
+ {0x90u, 0x55u},\r
+ {0x92u, 0xAAu},\r
+ {0x95u, 0x02u},\r
+ {0x96u, 0xFFu},\r
+ {0x97u, 0x05u},\r
+ {0x99u, 0x02u},\r
+ {0x9Au, 0xFFu},\r
+ {0x9Bu, 0x09u},\r
+ {0x9Cu, 0x33u},\r
+ {0x9Du, 0x02u},\r
+ {0x9Eu, 0xCCu},\r
+ {0x9Fu, 0x01u},\r
{0xA4u, 0xFFu},\r
- {0xA5u, 0x50u},\r
- {0xA7u, 0xA0u},\r
- {0xA8u, 0x0Fu},\r
- {0xA9u, 0x90u},\r
- {0xAAu, 0xF0u},\r
- {0xABu, 0x60u},\r
- {0xADu, 0x09u},\r
- {0xAFu, 0x06u},\r
- {0xB0u, 0xFFu},\r
- {0xB1u, 0xFFu},\r
- {0xBEu, 0x01u},\r
- {0xBFu, 0x01u},\r
- {0xD4u, 0x40u},\r
- {0xD6u, 0x04u},\r
+ {0xA8u, 0xFFu},\r
+ {0xB1u, 0x03u},\r
+ {0xB3u, 0x08u},\r
+ {0xB4u, 0xFFu},\r
+ {0xB5u, 0x10u},\r
+ {0xB7u, 0x04u},\r
+ {0xBAu, 0x20u},\r
+ {0xBBu, 0x02u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDCu, 0x91u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x01u},\r
- {0x03u, 0x2Au},\r
- {0x04u, 0x04u},\r
+ {0x01u, 0x20u},\r
+ {0x02u, 0x80u},\r
+ {0x03u, 0x02u},\r
+ {0x04u, 0x08u},\r
{0x05u, 0x10u},\r
- {0x06u, 0x40u},\r
- {0x08u, 0x44u},\r
- {0x0Bu, 0x80u},\r
- {0x0Du, 0x03u},\r
- {0x0Eu, 0x21u},\r
- {0x10u, 0x88u},\r
- {0x11u, 0x04u},\r
+ {0x07u, 0x40u},\r
+ {0x08u, 0x20u},\r
+ {0x0Au, 0x10u},\r
+ {0x0Bu, 0x41u},\r
+ {0x0Cu, 0x08u},\r
+ {0x0Eu, 0x8Au},\r
+ {0x12u, 0x08u},\r
+ {0x13u, 0x08u},\r
+ {0x15u, 0x06u},\r
{0x16u, 0x02u},\r
- {0x17u, 0x15u},\r
- {0x18u, 0x80u},\r
- {0x1Du, 0x10u},\r
- {0x1Eu, 0x64u},\r
- {0x1Fu, 0x04u},\r
- {0x23u, 0x80u},\r
- {0x26u, 0x08u},\r
- {0x27u, 0x20u},\r
- {0x28u, 0x44u},\r
- {0x29u, 0x04u},\r
- {0x2Bu, 0x42u},\r
- {0x2Du, 0x08u},\r
- {0x2Eu, 0x90u},\r
- {0x30u, 0x88u},\r
- {0x33u, 0x20u},\r
- {0x37u, 0x68u},\r
- {0x39u, 0x84u},\r
- {0x3Bu, 0x90u},\r
- {0x3Du, 0x20u},\r
- {0x3Fu, 0x0Au},\r
- {0x59u, 0x08u},\r
- {0x5Au, 0x08u},\r
- {0x60u, 0x02u},\r
- {0x61u, 0x28u},\r
- {0x62u, 0x01u},\r
- {0x80u, 0x40u},\r
- {0x81u, 0x04u},\r
+ {0x19u, 0x20u},\r
+ {0x1Bu, 0x20u},\r
+ {0x1Eu, 0x88u},\r
+ {0x20u, 0x40u},\r
+ {0x21u, 0x28u},\r
+ {0x22u, 0x40u},\r
+ {0x27u, 0x80u},\r
+ {0x2Eu, 0x10u},\r
+ {0x2Fu, 0x22u},\r
+ {0x31u, 0x28u},\r
+ {0x32u, 0x40u},\r
+ {0x37u, 0x89u},\r
+ {0x38u, 0x44u},\r
+ {0x39u, 0x80u},\r
+ {0x3Du, 0x28u},\r
+ {0x58u, 0x80u},\r
+ {0x5Au, 0x20u},\r
+ {0x5Fu, 0x80u},\r
+ {0x60u, 0x04u},\r
+ {0x63u, 0x01u},\r
{0x83u, 0x40u},\r
- {0x89u, 0x04u},\r
- {0x8Bu, 0x80u},\r
- {0x8Cu, 0x80u},\r
- {0x8Du, 0x10u},\r
- {0x91u, 0xE0u},\r
- {0x92u, 0x18u},\r
- {0x93u, 0x20u},\r
- {0x95u, 0x02u},\r
- {0x96u, 0x04u},\r
- {0x97u, 0x02u},\r
- {0x98u, 0x04u},\r
- {0x99u, 0x02u},\r
- {0x9Au, 0xA0u},\r
- {0x9Bu, 0x4Au},\r
- {0x9Du, 0x01u},\r
- {0xA0u, 0x02u},\r
+ {0x8Au, 0x11u},\r
+ {0x8Fu, 0x04u},\r
+ {0x92u, 0x72u},\r
+ {0x93u, 0x40u},\r
+ {0x95u, 0x01u},\r
+ {0x98u, 0xA0u},\r
+ {0x99u, 0x08u},\r
+ {0x9Bu, 0x09u},\r
+ {0x9Eu, 0x10u},\r
+ {0x9Fu, 0x04u},\r
{0xA1u, 0x14u},\r
- {0xA3u, 0x25u},\r
- {0xA4u, 0x08u},\r
- {0xA6u, 0x18u},\r
- {0xA9u, 0x80u},\r
- {0xABu, 0x28u},\r
+ {0xA2u, 0x88u},\r
+ {0xA3u, 0x02u},\r
+ {0xA6u, 0x02u},\r
+ {0xA7u, 0x40u},\r
+ {0xA8u, 0x02u},\r
+ {0xAAu, 0x20u},\r
+ {0xABu, 0x20u},\r
{0xACu, 0x80u},\r
- {0xB0u, 0x14u},\r
- {0xB1u, 0x08u},\r
+ {0xB1u, 0x28u},\r
{0xB4u, 0x08u},\r
- {0xB5u, 0x04u},\r
- {0xB6u, 0x40u},\r
- {0xB7u, 0x04u},\r
- {0xC0u, 0x7Fu},\r
- {0xC2u, 0xBDu},\r
- {0xC4u, 0xFEu},\r
- {0xCAu, 0x7Fu},\r
- {0xCCu, 0x7Eu},\r
- {0xCEu, 0xEEu},\r
- {0xD8u, 0x0Fu},\r
- {0xE0u, 0x05u},\r
- {0xE2u, 0x0Au},\r
- {0xEAu, 0x05u},\r
- {0xEEu, 0x62u},\r
- {0x00u, 0x0Fu},\r
- {0x02u, 0xF0u},\r
- {0x03u, 0xFFu},\r
- {0x04u, 0x50u},\r
- {0x05u, 0x30u},\r
- {0x06u, 0xA0u},\r
- {0x07u, 0xC0u},\r
- {0x0Du, 0x06u},\r
- {0x0Eu, 0xFFu},\r
- {0x0Fu, 0x09u},\r
- {0x10u, 0x06u},\r
- {0x12u, 0x09u},\r
- {0x14u, 0x05u},\r
- {0x15u, 0x03u},\r
- {0x16u, 0x0Au},\r
- {0x17u, 0x0Cu},\r
- {0x18u, 0x30u},\r
- {0x19u, 0x05u},\r
- {0x1Au, 0xC0u},\r
- {0x1Bu, 0x0Au},\r
- {0x1Cu, 0x60u},\r
- {0x1Eu, 0x90u},\r
- {0x1Fu, 0xFFu},\r
- {0x20u, 0xFFu},\r
- {0x21u, 0x60u},\r
- {0x23u, 0x90u},\r
- {0x24u, 0x03u},\r
- {0x25u, 0x50u},\r
- {0x26u, 0x0Cu},\r
- {0x27u, 0xA0u},\r
- {0x29u, 0xFFu},\r
- {0x2Au, 0xFFu},\r
- {0x2Du, 0x0Fu},\r
- {0x2Fu, 0xF0u},\r
- {0x32u, 0xFFu},\r
- {0x33u, 0xFFu},\r
- {0x3Eu, 0x04u},\r
- {0x3Fu, 0x04u},\r
+ {0xC0u, 0x7Bu},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0xB6u},\r
+ {0xCAu, 0x70u},\r
+ {0xCCu, 0xDEu},\r
+ {0xCEu, 0x6Au},\r
+ {0xD6u, 0x1Cu},\r
+ {0xD8u, 0x0Cu},\r
+ {0xE2u, 0x44u},\r
+ {0xE6u, 0xCAu},\r
+ {0xE8u, 0x04u},\r
+ {0xEAu, 0x01u},\r
+ {0xEEu, 0x86u},\r
+ {0x00u, 0x01u},\r
+ {0x01u, 0x02u},\r
+ {0x02u, 0x02u},\r
+ {0x03u, 0x01u},\r
+ {0x08u, 0x02u},\r
+ {0x0Au, 0x01u},\r
+ {0x0Cu, 0x04u},\r
+ {0x0Eu, 0x08u},\r
+ {0x15u, 0x02u},\r
+ {0x16u, 0x20u},\r
+ {0x17u, 0x01u},\r
+ {0x19u, 0x02u},\r
+ {0x1Au, 0x10u},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Du, 0x01u},\r
+ {0x1Eu, 0x40u},\r
+ {0x1Fu, 0x02u},\r
+ {0x20u, 0x08u},\r
+ {0x22u, 0x04u},\r
+ {0x28u, 0x03u},\r
+ {0x2Au, 0x0Cu},\r
+ {0x2Du, 0x02u},\r
+ {0x2Fu, 0x01u},\r
+ {0x30u, 0x10u},\r
+ {0x32u, 0x40u},\r
+ {0x34u, 0x20u},\r
+ {0x36u, 0x0Fu},\r
+ {0x37u, 0x03u},\r
+ {0x3Bu, 0x80u},\r
+ {0x3Eu, 0x40u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
+ {0x5Cu, 0x99u},\r
{0x5Fu, 0x01u},\r
- {0x82u, 0x20u},\r
- {0x83u, 0x02u},\r
- {0x84u, 0x08u},\r
- {0x86u, 0x04u},\r
- {0x88u, 0x04u},\r
- {0x89u, 0x04u},\r
- {0x8Au, 0x08u},\r
- {0x8Cu, 0x08u},\r
- {0x8Eu, 0x04u},\r
- {0x91u, 0x04u},\r
- {0x94u, 0x08u},\r
- {0x95u, 0x01u},\r
- {0x96u, 0x14u},\r
- {0x99u, 0x04u},\r
- {0x9Cu, 0x08u},\r
- {0x9Eu, 0x04u},\r
- {0xA5u, 0x04u},\r
- {0xA6u, 0x01u},\r
- {0xAAu, 0x02u},\r
- {0xACu, 0x01u},\r
- {0xAEu, 0x02u},\r
- {0xB0u, 0x10u},\r
- {0xB1u, 0x01u},\r
- {0xB2u, 0x0Cu},\r
- {0xB3u, 0x02u},\r
- {0xB4u, 0x20u},\r
+ {0x87u, 0x10u},\r
+ {0x89u, 0x02u},\r
+ {0x8Bu, 0x01u},\r
+ {0x8Du, 0x02u},\r
+ {0x8Fu, 0x01u},\r
+ {0x91u, 0x01u},\r
+ {0x93u, 0x02u},\r
+ {0x95u, 0x10u},\r
+ {0x97u, 0x20u},\r
+ {0x9Du, 0x04u},\r
+ {0xA3u, 0x20u},\r
+ {0xA5u, 0x08u},\r
+ {0xA9u, 0x02u},\r
+ {0xABu, 0x01u},\r
+ {0xADu, 0x02u},\r
+ {0xAFu, 0x01u},\r
+ {0xB1u, 0x03u},\r
+ {0xB3u, 0x08u},\r
{0xB5u, 0x04u},\r
- {0xB6u, 0x03u},\r
- {0xB9u, 0x20u},\r
- {0xBAu, 0x08u},\r
- {0xBEu, 0x40u},\r
- {0xBFu, 0x10u},\r
+ {0xB7u, 0x30u},\r
+ {0xBBu, 0x02u},\r
+ {0xBFu, 0x40u},\r
{0xD6u, 0x08u},\r
- {0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x99u},\r
+ {0xDCu, 0x90u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x41u},\r
- {0x03u, 0x28u},\r
- {0x04u, 0x0Au},\r
- {0x06u, 0x02u},\r
- {0x07u, 0x20u},\r
- {0x09u, 0x08u},\r
- {0x0Bu, 0x01u},\r
- {0x0Eu, 0x21u},\r
- {0x0Fu, 0x88u},\r
- {0x10u, 0x10u},\r
- {0x11u, 0x80u},\r
- {0x13u, 0x20u},\r
- {0x14u, 0x40u},\r
- {0x15u, 0x10u},\r
- {0x17u, 0x08u},\r
- {0x18u, 0x40u},\r
- {0x19u, 0x40u},\r
- {0x1Au, 0x84u},\r
- {0x1Bu, 0x08u},\r
- {0x1Du, 0x04u},\r
- {0x21u, 0x28u},\r
- {0x22u, 0x01u},\r
- {0x27u, 0x10u},\r
- {0x29u, 0x04u},\r
- {0x2Du, 0x30u},\r
- {0x2Eu, 0x09u},\r
- {0x2Fu, 0x42u},\r
- {0x32u, 0x06u},\r
- {0x33u, 0x10u},\r
- {0x34u, 0x50u},\r
- {0x35u, 0x80u},\r
- {0x36u, 0x18u},\r
- {0x37u, 0x08u},\r
- {0x39u, 0x20u},\r
- {0x3Bu, 0x01u},\r
- {0x3Du, 0x08u},\r
- {0x3Eu, 0x02u},\r
- {0x3Fu, 0x88u},\r
- {0x58u, 0x20u},\r
- {0x5Bu, 0x40u},\r
- {0x62u, 0x10u},\r
- {0x63u, 0x01u},\r
- {0x6Cu, 0x01u},\r
- {0x6Du, 0x80u},\r
- {0x6Fu, 0x02u},\r
- {0x81u, 0x01u},\r
- {0x82u, 0x0Au},\r
- {0x83u, 0x40u},\r
- {0x85u, 0x20u},\r
- {0x88u, 0x04u},\r
- {0x89u, 0x30u},\r
- {0x8Cu, 0x10u},\r
- {0x8Du, 0x0Cu},\r
- {0x90u, 0x29u},\r
- {0x92u, 0x08u},\r
- {0x93u, 0x80u},\r
- {0x94u, 0x02u},\r
- {0x96u, 0x86u},\r
- {0x9Cu, 0x0Cu},\r
- {0x9Du, 0x49u},\r
- {0x9Eu, 0x10u},\r
- {0x9Fu, 0x04u},\r
- {0xA0u, 0x45u},\r
- {0xA2u, 0x10u},\r
- {0xA3u, 0xA0u},\r
- {0xA6u, 0x04u},\r
- {0xA7u, 0x4Au},\r
- {0xAAu, 0x40u},\r
- {0xB0u, 0x22u},\r
- {0xB2u, 0x08u},\r
- {0xB3u, 0x40u},\r
- {0xB5u, 0x02u},\r
- {0xB6u, 0x02u},\r
- {0xC0u, 0xBFu},\r
- {0xC2u, 0xF5u},\r
- {0xC4u, 0x77u},\r
- {0xCAu, 0xF2u},\r
- {0xCCu, 0x77u},\r
- {0xCEu, 0xD5u},\r
- {0xD6u, 0x0Cu},\r
- {0xD8u, 0x0Cu},\r
- {0xE0u, 0x40u},\r
- {0xE2u, 0x22u},\r
- {0xE4u, 0x20u},\r
- {0xE6u, 0x41u},\r
- {0xE8u, 0x40u},\r
- {0xEAu, 0x31u},\r
- {0xEEu, 0x92u},\r
- {0x00u, 0x02u},\r
- {0x02u, 0x01u},\r
- {0x0Cu, 0x01u},\r
- {0x0Eu, 0x02u},\r
- {0x11u, 0x06u},\r
- {0x12u, 0x10u},\r
- {0x14u, 0x02u},\r
+ {0x05u, 0x01u},\r
+ {0x06u, 0x09u},\r
+ {0x0Eu, 0x28u},\r
+ {0x0Fu, 0x02u},\r
+ {0x14u, 0x04u},\r
{0x15u, 0x01u},\r
- {0x16u, 0x05u},\r
- {0x17u, 0x02u},\r
- {0x18u, 0x02u},\r
- {0x1Au, 0x01u},\r
- {0x25u, 0x02u},\r
- {0x27u, 0x01u},\r
+ {0x1Du, 0x40u},\r
+ {0x1Eu, 0x28u},\r
+ {0x1Fu, 0x01u},\r
+ {0x21u, 0x42u},\r
+ {0x22u, 0x04u},\r
+ {0x23u, 0x48u},\r
+ {0x25u, 0x80u},\r
+ {0x26u, 0x80u},\r
{0x28u, 0x02u},\r
- {0x29u, 0x01u},\r
- {0x2Au, 0x09u},\r
- {0x2Bu, 0x04u},\r
- {0x30u, 0x03u},\r
- {0x31u, 0x07u},\r
+ {0x29u, 0x10u},\r
+ {0x2Bu, 0xA0u},\r
+ {0x2Fu, 0x01u},\r
+ {0x30u, 0x04u},\r
+ {0x31u, 0x82u},\r
{0x32u, 0x08u},\r
- {0x34u, 0x10u},\r
- {0x36u, 0x04u},\r
- {0x39u, 0x02u},\r
- {0x3Au, 0x02u},\r
+ {0x36u, 0x94u},\r
+ {0x38u, 0x90u},\r
+ {0x3Au, 0x08u},\r
+ {0x3Fu, 0x02u},\r
+ {0x58u, 0x80u},\r
+ {0x5Du, 0x06u},\r
+ {0x5Fu, 0x60u},\r
+ {0x63u, 0x02u},\r
+ {0x65u, 0x80u},\r
+ {0x6Cu, 0x16u},\r
+ {0x6Du, 0x41u},\r
+ {0x6Fu, 0x80u},\r
+ {0x74u, 0x80u},\r
+ {0x76u, 0x95u},\r
+ {0x80u, 0x80u},\r
+ {0x86u, 0x04u},\r
+ {0x8Au, 0x88u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Eu, 0x04u},\r
+ {0x90u, 0x90u},\r
+ {0x94u, 0x28u},\r
+ {0x95u, 0xC0u},\r
+ {0x98u, 0x02u},\r
+ {0x99u, 0x91u},\r
+ {0x9Du, 0x40u},\r
+ {0x9Eu, 0x10u},\r
+ {0xA2u, 0x08u},\r
+ {0xA3u, 0x20u},\r
+ {0xA4u, 0x02u},\r
+ {0xA8u, 0x80u},\r
+ {0xAAu, 0x08u},\r
+ {0xABu, 0x01u},\r
+ {0xB0u, 0x40u},\r
+ {0xB1u, 0x10u},\r
+ {0xB2u, 0x80u},\r
+ {0xB7u, 0x80u},\r
+ {0xC0u, 0xD0u},\r
+ {0xC2u, 0xE0u},\r
+ {0xC4u, 0x50u},\r
+ {0xCAu, 0x1Fu},\r
+ {0xCCu, 0x7Bu},\r
+ {0xCEu, 0x8Eu},\r
+ {0xD6u, 0xF8u},\r
+ {0xD8u, 0x18u},\r
+ {0xE0u, 0x20u},\r
+ {0xE2u, 0x40u},\r
+ {0xE6u, 0xF2u},\r
+ {0xE8u, 0x40u},\r
+ {0xEAu, 0x01u},\r
+ {0xECu, 0x20u},\r
+ {0xEEu, 0x02u},\r
+ {0x03u, 0xFFu},\r
+ {0x05u, 0x50u},\r
+ {0x07u, 0xA0u},\r
+ {0x09u, 0x30u},\r
+ {0x0Bu, 0xC0u},\r
+ {0x0Du, 0x06u},\r
+ {0x0Eu, 0x01u},\r
+ {0x0Fu, 0x09u},\r
+ {0x11u, 0x60u},\r
+ {0x12u, 0x04u},\r
+ {0x13u, 0x90u},\r
+ {0x17u, 0xFFu},\r
+ {0x19u, 0x03u},\r
+ {0x1Au, 0x08u},\r
+ {0x1Bu, 0x0Cu},\r
+ {0x1Du, 0x0Fu},\r
+ {0x1Eu, 0x10u},\r
+ {0x1Fu, 0xF0u},\r
+ {0x20u, 0x01u},\r
+ {0x21u, 0x05u},\r
+ {0x22u, 0x02u},\r
+ {0x23u, 0x0Au},\r
+ {0x2Du, 0xFFu},\r
+ {0x2Eu, 0x02u},\r
+ {0x30u, 0x10u},\r
+ {0x32u, 0x08u},\r
+ {0x34u, 0x04u},\r
+ {0x35u, 0xFFu},\r
+ {0x36u, 0x03u},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x10u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Cu, 0x09u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x0Fu},\r
- {0x82u, 0xF0u},\r
- {0x84u, 0x06u},\r
+ {0x84u, 0x50u},\r
{0x85u, 0xFFu},\r
- {0x86u, 0x09u},\r
- {0x88u, 0x60u},\r
- {0x89u, 0x55u},\r
- {0x8Au, 0x90u},\r
- {0x8Bu, 0xAAu},\r
+ {0x86u, 0xA0u},\r
+ {0x88u, 0x30u},\r
+ {0x89u, 0x33u},\r
+ {0x8Au, 0xC0u},\r
+ {0x8Bu, 0xCCu},\r
+ {0x8Cu, 0xFFu},\r
+ {0x8Fu, 0xFFu},\r
+ {0x90u, 0x90u},\r
+ {0x91u, 0x0Fu},\r
+ {0x92u, 0x60u},\r
+ {0x93u, 0xF0u},\r
{0x94u, 0x05u},\r
- {0x95u, 0x0Fu},\r
{0x96u, 0x0Au},\r
- {0x97u, 0xF0u},\r
- {0x98u, 0x03u},\r
- {0x9Au, 0x0Cu},\r
- {0x9Bu, 0xFFu},\r
- {0x9Du, 0x33u},\r
- {0x9Fu, 0xCCu},\r
- {0xA1u, 0x96u},\r
- {0xA3u, 0x69u},\r
+ {0x97u, 0xFFu},\r
+ {0x99u, 0x55u},\r
+ {0x9Bu, 0xAAu},\r
+ {0x9Cu, 0x0Fu},\r
+ {0x9Du, 0xFFu},\r
+ {0x9Eu, 0xF0u},\r
+ {0xA0u, 0x09u},\r
+ {0xA1u, 0x69u},\r
+ {0xA2u, 0x06u},\r
+ {0xA3u, 0x96u},\r
+ {0xA4u, 0x03u},\r
+ {0xA6u, 0x0Cu},\r
{0xA7u, 0xFFu},\r
- {0xA8u, 0x50u},\r
- {0xAAu, 0xA0u},\r
- {0xABu, 0xFFu},\r
- {0xACu, 0x30u},\r
- {0xADu, 0xFFu},\r
- {0xAEu, 0xC0u},\r
- {0xB3u, 0xFFu},\r
- {0xB4u, 0xFFu},\r
- {0xBBu, 0x08u},\r
- {0xBEu, 0x10u},\r
- {0xD6u, 0x08u},\r
+ {0xA8u, 0xFFu},\r
+ {0xAEu, 0xFFu},\r
+ {0xB1u, 0xFFu},\r
+ {0xB6u, 0xFFu},\r
+ {0xB8u, 0x02u},\r
+ {0xBBu, 0x02u},\r
+ {0xBEu, 0x41u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
{0xDCu, 0x10u},\r
- {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x41u},\r
- {0x04u, 0x02u},\r
- {0x05u, 0x04u},\r
+ {0x00u, 0x80u},\r
+ {0x04u, 0x28u},\r
+ {0x05u, 0x41u},\r
+ {0x07u, 0x40u},\r
+ {0x09u, 0x80u},\r
+ {0x0Au, 0x44u},\r
+ {0x0Cu, 0x82u},\r
+ {0x0Eu, 0x20u},\r
+ {0x10u, 0x80u},\r
+ {0x11u, 0x40u},\r
+ {0x14u, 0x14u},\r
+ {0x16u, 0x81u},\r
+ {0x18u, 0x92u},\r
+ {0x19u, 0x10u},\r
+ {0x1Au, 0x44u},\r
+ {0x1Fu, 0x41u},\r
+ {0x22u, 0x20u},\r
+ {0x26u, 0x02u},\r
+ {0x29u, 0x40u},\r
+ {0x2Au, 0x02u},\r
+ {0x2Fu, 0xA0u},\r
+ {0x30u, 0x9Eu},\r
+ {0x31u, 0x20u},\r
+ {0x34u, 0x08u},\r
+ {0x35u, 0xA0u},\r
+ {0x36u, 0x02u},\r
+ {0x38u, 0x28u},\r
+ {0x3Au, 0x81u},\r
+ {0x3Du, 0x20u},\r
+ {0x3Fu, 0x84u},\r
+ {0x58u, 0x80u},\r
+ {0x60u, 0x02u},\r
+ {0x61u, 0x80u},\r
+ {0x81u, 0x10u},\r
+ {0x82u, 0x01u},\r
+ {0x84u, 0x80u},\r
+ {0x86u, 0x12u},\r
+ {0x8Bu, 0x04u},\r
+ {0x8Cu, 0x40u},\r
+ {0x8Eu, 0x02u},\r
+ {0x8Fu, 0x60u},\r
+ {0x90u, 0x40u},\r
+ {0x94u, 0x2Au},\r
+ {0x95u, 0xE0u},\r
+ {0x97u, 0x80u},\r
+ {0x98u, 0x08u},\r
+ {0x99u, 0xA0u},\r
+ {0x9Bu, 0x40u},\r
+ {0x9Du, 0x40u},\r
+ {0x9Eu, 0x10u},\r
+ {0xA0u, 0x08u},\r
+ {0xA1u, 0x20u},\r
+ {0xA3u, 0x40u},\r
+ {0xA4u, 0x80u},\r
+ {0xA6u, 0x30u},\r
+ {0xABu, 0x04u},\r
+ {0xB2u, 0x10u},\r
+ {0xB3u, 0x02u},\r
+ {0xB4u, 0x40u},\r
+ {0xB6u, 0x80u},\r
+ {0xC0u, 0xE1u},\r
+ {0xC2u, 0xBBu},\r
+ {0xC4u, 0xF9u},\r
+ {0xCAu, 0xC9u},\r
+ {0xCCu, 0xFFu},\r
+ {0xCEu, 0x7Fu},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x08u},\r
+ {0xE2u, 0x50u},\r
+ {0xE4u, 0x20u},\r
+ {0xE6u, 0x92u},\r
+ {0xEAu, 0x49u},\r
+ {0xECu, 0x80u},\r
+ {0xEEu, 0x20u},\r
+ {0x02u, 0x02u},\r
{0x06u, 0x08u},\r
- {0x0Au, 0xA4u},\r
- {0x0Cu, 0x04u},\r
- {0x0Eu, 0x08u},\r
- {0x12u, 0x04u},\r
- {0x17u, 0x50u},\r
- {0x18u, 0x41u},\r
- {0x1Au, 0x60u},\r
- {0x1Bu, 0x20u},\r
- {0x1Cu, 0x08u},\r
- {0x21u, 0x02u},\r
- {0x26u, 0x08u},\r
- {0x28u, 0x08u},\r
- {0x29u, 0x08u},\r
- {0x2Cu, 0x20u},\r
- {0x2Du, 0x10u},\r
- {0x2Eu, 0x42u},\r
- {0x31u, 0x02u},\r
- {0x33u, 0x04u},\r
- {0x35u, 0x20u},\r
- {0x36u, 0x88u},\r
- {0x38u, 0x40u},\r
- {0x3Au, 0x40u},\r
- {0x3Du, 0x04u},\r
- {0x3Fu, 0x20u},\r
- {0x58u, 0x60u},\r
- {0x5Bu, 0x08u},\r
- {0x5Eu, 0x80u},\r
- {0x62u, 0x84u},\r
- {0x63u, 0x08u},\r
- {0x67u, 0x02u},\r
- {0x6Cu, 0x16u},\r
- {0x6Fu, 0x80u},\r
- {0x74u, 0x41u},\r
- {0x76u, 0x08u},\r
- {0x77u, 0x50u},\r
- {0x83u, 0x10u},\r
- {0x85u, 0x40u},\r
- {0x87u, 0x08u},\r
- {0x88u, 0x02u},\r
- {0x8Du, 0x04u},\r
- {0x8Eu, 0x08u},\r
- {0x8Fu, 0x01u},\r
- {0x91u, 0x14u},\r
- {0x92u, 0x08u},\r
- {0x94u, 0x20u},\r
- {0x96u, 0x02u},\r
- {0x98u, 0x40u},\r
- {0x99u, 0x20u},\r
- {0x9Cu, 0x06u},\r
- {0x9Du, 0x01u},\r
- {0x9Eu, 0x50u},\r
- {0x9Fu, 0x10u},\r
- {0xA0u, 0x20u},\r
- {0xA2u, 0x50u},\r
- {0xA4u, 0x02u},\r
- {0xA7u, 0x4Eu},\r
- {0xAEu, 0x05u},\r
- {0xB0u, 0x40u},\r
- {0xB1u, 0x04u},\r
- {0xC0u, 0x79u},\r
- {0xC2u, 0x6Eu},\r
- {0xC4u, 0xC2u},\r
- {0xCAu, 0xF6u},\r
- {0xCCu, 0x73u},\r
- {0xCEu, 0x60u},\r
- {0xD6u, 0x1Eu},\r
- {0xD8u, 0x1Eu},\r
- {0xE0u, 0x30u},\r
- {0xE2u, 0x48u},\r
- {0xE4u, 0x08u},\r
- {0xE6u, 0x50u},\r
- {0xE8u, 0x20u},\r
- {0xEAu, 0x01u},\r
- {0xEEu, 0x02u},\r
- {0x02u, 0x01u},\r
- {0x05u, 0x0Au},\r
- {0x07u, 0x05u},\r
- {0x0Au, 0x02u},\r
- {0x0Bu, 0x07u},\r
- {0x17u, 0x10u},\r
- {0x1Bu, 0x20u},\r
- {0x1Cu, 0x01u},\r
- {0x1Eu, 0x02u},\r
- {0x23u, 0x08u},\r
- {0x25u, 0x09u},\r
- {0x27u, 0x02u},\r
- {0x29u, 0x04u},\r
- {0x2Bu, 0x08u},\r
- {0x2Du, 0x10u},\r
- {0x2Eu, 0x04u},\r
- {0x2Fu, 0x20u},\r
- {0x31u, 0x30u},\r
- {0x32u, 0x03u},\r
- {0x35u, 0x0Fu},\r
- {0x36u, 0x04u},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Du, 0x04u},\r
+ {0x0Fu, 0x08u},\r
+ {0x15u, 0x09u},\r
+ {0x17u, 0x02u},\r
+ {0x1Au, 0x04u},\r
+ {0x1Eu, 0x01u},\r
+ {0x1Fu, 0x07u},\r
+ {0x20u, 0x04u},\r
+ {0x22u, 0x08u},\r
+ {0x2Du, 0x0Au},\r
+ {0x2Fu, 0x05u},\r
+ {0x30u, 0x01u},\r
+ {0x31u, 0x0Fu},\r
+ {0x32u, 0x0Cu},\r
+ {0x34u, 0x02u},\r
{0x3Eu, 0x04u},\r
- {0x3Fu, 0x01u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
{0x5Fu, 0x01u},\r
{0x80u, 0x01u},\r
{0x82u, 0x02u},\r
- {0x83u, 0x10u},\r
- {0x85u, 0x01u},\r
- {0x87u, 0x02u},\r
- {0x8Cu, 0x02u},\r
- {0x8Du, 0x02u},\r
- {0x8Eu, 0x01u},\r
- {0x8Fu, 0x01u},\r
- {0x92u, 0x08u},\r
- {0x93u, 0x08u},\r
+ {0x84u, 0x08u},\r
+ {0x86u, 0x04u},\r
+ {0x8Bu, 0x02u},\r
+ {0x8Cu, 0x08u},\r
+ {0x8Eu, 0x04u},\r
+ {0x90u, 0x02u},\r
+ {0x92u, 0x01u},\r
{0x94u, 0x02u},\r
{0x96u, 0x01u},\r
- {0x99u, 0x02u},\r
+ {0x97u, 0x08u},\r
{0x9Bu, 0x01u},\r
- {0x9Du, 0x02u},\r
- {0x9Fu, 0x01u},\r
- {0xA3u, 0x04u},\r
+ {0x9Cu, 0x04u},\r
+ {0x9Du, 0x01u},\r
+ {0x9Eu, 0x08u},\r
+ {0x9Fu, 0x02u},\r
+ {0xA0u, 0x08u},\r
+ {0xA2u, 0x04u},\r
{0xA4u, 0x02u},\r
- {0xA6u, 0x11u},\r
+ {0xA6u, 0x01u},\r
+ {0xA7u, 0x10u},\r
{0xA8u, 0x02u},\r
- {0xA9u, 0x02u},\r
- {0xAAu, 0x05u},\r
- {0xABu, 0x21u},\r
- {0xADu, 0x04u},\r
- {0xAFu, 0x08u},\r
+ {0xAAu, 0x01u},\r
+ {0xABu, 0x04u},\r
+ {0xACu, 0x08u},\r
+ {0xAEu, 0x04u},\r
{0xB0u, 0x03u},\r
- {0xB1u, 0x0Cu},\r
- {0xB2u, 0x04u},\r
+ {0xB1u, 0x04u},\r
{0xB3u, 0x10u},\r
- {0xB4u, 0x08u},\r
- {0xB5u, 0x03u},\r
- {0xB6u, 0x10u},\r
- {0xB7u, 0x20u},\r
- {0xBAu, 0x02u},\r
- {0xBBu, 0x20u},\r
- {0xBFu, 0x01u},\r
+ {0xB5u, 0x08u},\r
+ {0xB6u, 0x0Cu},\r
+ {0xB7u, 0x03u},\r
+ {0xBAu, 0x82u},\r
+ {0xBFu, 0x40u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
{0xDCu, 0x99u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x82u},\r
- {0x04u, 0x20u},\r
+ {0x00u, 0x88u},\r
+ {0x02u, 0x80u},\r
{0x05u, 0x01u},\r
- {0x0Au, 0x10u},\r
- {0x0Bu, 0x80u},\r
- {0x0Fu, 0x02u},\r
- {0x12u, 0x18u},\r
- {0x15u, 0x80u},\r
- {0x18u, 0x02u},\r
- {0x19u, 0x92u},\r
- {0x1Au, 0x10u},\r
- {0x1Du, 0x04u},\r
- {0x1Fu, 0x40u},\r
- {0x20u, 0x80u},\r
- {0x21u, 0x40u},\r
- {0x22u, 0x58u},\r
- {0x23u, 0x04u},\r
- {0x24u, 0x80u},\r
- {0x25u, 0x10u},\r
- {0x26u, 0x10u},\r
- {0x2Bu, 0x47u},\r
- {0x2Cu, 0x20u},\r
- {0x2Du, 0x20u},\r
- {0x2Fu, 0x82u},\r
- {0x30u, 0x02u},\r
- {0x31u, 0x10u},\r
- {0x32u, 0x40u},\r
- {0x34u, 0x04u},\r
- {0x37u, 0x10u},\r
- {0x38u, 0x02u},\r
- {0x3Bu, 0x84u},\r
- {0x3Du, 0x24u},\r
- {0x58u, 0x09u},\r
- {0x5Au, 0x20u},\r
- {0x5Bu, 0x40u},\r
- {0x5Cu, 0x20u},\r
- {0x5Eu, 0x05u},\r
+ {0x06u, 0x10u},\r
+ {0x08u, 0x02u},\r
+ {0x0Au, 0x22u},\r
+ {0x0Fu, 0x0Au},\r
+ {0x12u, 0x4Au},\r
+ {0x13u, 0x04u},\r
+ {0x14u, 0x40u},\r
+ {0x18u, 0x40u},\r
+ {0x19u, 0x80u},\r
+ {0x1Au, 0x03u},\r
+ {0x1Cu, 0x88u},\r
+ {0x1Du, 0x15u},\r
+ {0x22u, 0x0Au},\r
+ {0x23u, 0x06u},\r
+ {0x27u, 0x40u},\r
+ {0x28u, 0x10u},\r
+ {0x29u, 0x10u},\r
+ {0x2Fu, 0x02u},\r
+ {0x30u, 0xC0u},\r
+ {0x31u, 0x20u},\r
+ {0x32u, 0x08u},\r
+ {0x34u, 0x08u},\r
+ {0x37u, 0x40u},\r
+ {0x38u, 0x20u},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x80u},\r
+ {0x58u, 0x10u},\r
+ {0x5Au, 0x60u},\r
+ {0x5Cu, 0x24u},\r
+ {0x5Du, 0x02u},\r
{0x5Fu, 0x80u},\r
{0x62u, 0x40u},\r
- {0x64u, 0x02u},\r
- {0x78u, 0x01u},\r
- {0x7Au, 0x80u},\r
- {0x80u, 0x08u},\r
- {0x81u, 0x02u},\r
- {0x83u, 0x48u},\r
- {0x85u, 0x10u},\r
- {0x86u, 0x84u},\r
- {0x88u, 0x40u},\r
- {0x8Du, 0x10u},\r
- {0x94u, 0x80u},\r
- {0x96u, 0x02u},\r
- {0x98u, 0x20u},\r
- {0x99u, 0x20u},\r
+ {0x63u, 0x02u},\r
+ {0x64u, 0x01u},\r
+ {0x80u, 0x04u},\r
+ {0x81u, 0x40u},\r
+ {0x85u, 0x02u},\r
+ {0x8Au, 0x01u},\r
+ {0x8Cu, 0x01u},\r
+ {0x8Du, 0x20u},\r
+ {0x92u, 0x70u},\r
+ {0x94u, 0x2Cu},\r
+ {0x95u, 0x60u},\r
+ {0x97u, 0x80u},\r
+ {0x98u, 0x2Bu},\r
{0x9Bu, 0x80u},\r
- {0x9Du, 0x04u},\r
- {0xA0u, 0x20u},\r
- {0xA2u, 0x40u},\r
- {0xA3u, 0x80u},\r
- {0xA8u, 0x20u},\r
- {0xA9u, 0x04u},\r
- {0xAEu, 0x01u},\r
- {0xB5u, 0x20u},\r
- {0xC0u, 0x59u},\r
- {0xC2u, 0x8Cu},\r
- {0xC4u, 0x86u},\r
- {0xCAu, 0xFDu},\r
- {0xCCu, 0x6Du},\r
- {0xCEu, 0x6Bu},\r
- {0xD6u, 0xFFu},\r
+ {0x9Du, 0xC4u},\r
+ {0x9Fu, 0x02u},\r
+ {0xA0u, 0x08u},\r
+ {0xA1u, 0x20u},\r
+ {0xA3u, 0x40u},\r
+ {0xA4u, 0x80u},\r
+ {0xA6u, 0x30u},\r
+ {0xA8u, 0x10u},\r
+ {0xAAu, 0x40u},\r
+ {0xABu, 0x80u},\r
+ {0xACu, 0x20u},\r
+ {0xADu, 0x01u},\r
+ {0xB6u, 0x60u},\r
+ {0xB7u, 0x40u},\r
+ {0xC0u, 0x3Du},\r
+ {0xC2u, 0xCDu},\r
+ {0xC4u, 0x1Fu},\r
+ {0xCAu, 0x16u},\r
+ {0xCCu, 0x5Eu},\r
+ {0xCEu, 0x34u},\r
+ {0xD6u, 0xF8u},\r
{0xD8u, 0x18u},\r
- {0xE2u, 0x64u},\r
- {0xE6u, 0x92u},\r
- {0xE8u, 0x10u},\r
- {0xECu, 0x01u},\r
- {0x80u, 0x60u},\r
- {0x86u, 0x40u},\r
- {0x87u, 0x80u},\r
- {0x8Fu, 0x80u},\r
- {0xE4u, 0x10u},\r
- {0xE6u, 0x02u},\r
- {0x09u, 0x04u},\r
- {0x0Bu, 0x88u},\r
- {0x15u, 0x53u},\r
- {0x16u, 0x01u},\r
- {0x17u, 0xACu},\r
- {0x1Eu, 0x02u},\r
- {0x21u, 0x02u},\r
- {0x23u, 0x11u},\r
- {0x25u, 0x01u},\r
- {0x27u, 0x42u},\r
- {0x28u, 0x01u},\r
- {0x29u, 0x08u},\r
- {0x2Au, 0x02u},\r
- {0x2Bu, 0x24u},\r
- {0x30u, 0x03u},\r
- {0x31u, 0xC0u},\r
- {0x33u, 0x0Fu},\r
- {0x35u, 0x30u},\r
+ {0xE0u, 0x11u},\r
+ {0xE2u, 0xAAu},\r
+ {0xE6u, 0x84u},\r
+ {0xEAu, 0x04u},\r
+ {0xECu, 0x40u},\r
+ {0x07u, 0x02u},\r
+ {0x08u, 0x30u},\r
+ {0x0Au, 0xC0u},\r
+ {0x0Cu, 0x60u},\r
+ {0x0Eu, 0x90u},\r
+ {0x10u, 0xFFu},\r
+ {0x14u, 0x05u},\r
+ {0x16u, 0x0Au},\r
+ {0x17u, 0x01u},\r
+ {0x18u, 0x03u},\r
+ {0x1Au, 0x0Cu},\r
+ {0x1Du, 0x01u},\r
+ {0x1Eu, 0xFFu},\r
+ {0x1Fu, 0x02u},\r
+ {0x20u, 0x0Fu},\r
+ {0x22u, 0xF0u},\r
+ {0x24u, 0x50u},\r
+ {0x26u, 0xA0u},\r
+ {0x28u, 0x06u},\r
+ {0x2Au, 0x09u},\r
+ {0x2Eu, 0xFFu},\r
+ {0x2Fu, 0x04u},\r
+ {0x30u, 0xFFu},\r
+ {0x33u, 0x03u},\r
+ {0x35u, 0x04u},\r
{0x3Eu, 0x01u},\r
- {0x3Fu, 0x15u},\r
- {0x40u, 0x36u},\r
- {0x41u, 0x04u},\r
- {0x42u, 0x50u},\r
- {0x44u, 0x01u},\r
- {0x45u, 0xBEu},\r
- {0x46u, 0xFCu},\r
- {0x47u, 0x0Du},\r
- {0x48u, 0x1Fu},\r
- {0x49u, 0xFFu},\r
- {0x4Au, 0xFFu},\r
- {0x4Bu, 0xFFu},\r
- {0x4Cu, 0x22u},\r
- {0x4Eu, 0xF0u},\r
- {0x4Fu, 0x08u},\r
- {0x50u, 0x04u},\r
+ {0x3Fu, 0x04u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Au, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x90u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x62u, 0xC0u},\r
- {0x64u, 0x40u},\r
- {0x65u, 0x01u},\r
- {0x66u, 0x10u},\r
- {0x67u, 0x11u},\r
- {0x68u, 0xC0u},\r
- {0x69u, 0x01u},\r
- {0x6Bu, 0x11u},\r
- {0x6Cu, 0x40u},\r
- {0x6Du, 0x01u},\r
- {0x6Eu, 0x40u},\r
- {0x6Fu, 0x01u},\r
- {0x80u, 0x40u},\r
- {0x81u, 0x0Du},\r
- {0x84u, 0x01u},\r
- {0x88u, 0x22u},\r
- {0x89u, 0x0Du},\r
- {0x8Au, 0x08u},\r
- {0x8Cu, 0x01u},\r
- {0x90u, 0x07u},\r
- {0x91u, 0x0Du},\r
- {0x92u, 0x18u},\r
- {0x94u, 0x08u},\r
- {0x95u, 0x0Du},\r
- {0x96u, 0x21u},\r
- {0x98u, 0x04u},\r
- {0x99u, 0x12u},\r
- {0x9Bu, 0x08u},\r
- {0x9Cu, 0x10u},\r
- {0x9Du, 0x02u},\r
- {0x9Eu, 0x80u},\r
- {0x9Fu, 0x0Du},\r
- {0xA0u, 0x01u},\r
- {0xA1u, 0x0Du},\r
- {0xA4u, 0x40u},\r
- {0xA8u, 0x01u},\r
- {0xA9u, 0x12u},\r
- {0xABu, 0x04u},\r
- {0xACu, 0x01u},\r
- {0xADu, 0x11u},\r
- {0xAFu, 0x02u},\r
- {0xB0u, 0x80u},\r
- {0xB1u, 0x0Fu},\r
- {0xB4u, 0x40u},\r
- {0xB6u, 0x3Fu},\r
- {0xB7u, 0x10u},\r
- {0xB8u, 0xA0u},\r
- {0xBBu, 0x02u},\r
- {0xBEu, 0x40u},\r
+ {0x83u, 0x10u},\r
+ {0x84u, 0x50u},\r
+ {0x86u, 0xA0u},\r
+ {0x87u, 0x20u},\r
+ {0x88u, 0x30u},\r
+ {0x8Au, 0xC0u},\r
+ {0x8Bu, 0x0Eu},\r
+ {0x8Du, 0x01u},\r
+ {0x8Eu, 0xFFu},\r
+ {0x94u, 0x05u},\r
+ {0x95u, 0x32u},\r
+ {0x96u, 0x0Au},\r
+ {0x97u, 0x04u},\r
+ {0x98u, 0x03u},\r
+ {0x99u, 0x01u},\r
+ {0x9Au, 0x0Cu},\r
+ {0x9Cu, 0x0Fu},\r
+ {0x9Du, 0x01u},\r
+ {0x9Eu, 0xF0u},\r
+ {0xA1u, 0x01u},\r
+ {0xA2u, 0xFFu},\r
+ {0xA5u, 0x34u},\r
+ {0xA6u, 0xFFu},\r
+ {0xA7u, 0x0Au},\r
+ {0xA8u, 0x09u},\r
+ {0xA9u, 0x28u},\r
+ {0xAAu, 0x06u},\r
+ {0xABu, 0x10u},\r
+ {0xACu, 0x90u},\r
+ {0xAEu, 0x60u},\r
+ {0xAFu, 0x20u},\r
+ {0xB0u, 0xFFu},\r
+ {0xB3u, 0x01u},\r
+ {0xB5u, 0x1Eu},\r
+ {0xB7u, 0x20u},\r
+ {0xB9u, 0x08u},\r
+ {0xBEu, 0x01u},\r
+ {0xBFu, 0x44u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDCu, 0x10u},\r
+ {0xDFu, 0x01u},\r
+ {0x01u, 0x40u},\r
+ {0x02u, 0x04u},\r
+ {0x04u, 0x28u},\r
+ {0x05u, 0x40u},\r
+ {0x06u, 0x14u},\r
+ {0x09u, 0x1Au},\r
+ {0x0Bu, 0x02u},\r
+ {0x0Cu, 0x80u},\r
+ {0x0Du, 0x28u},\r
+ {0x0Eu, 0x20u},\r
+ {0x10u, 0x86u},\r
+ {0x12u, 0x10u},\r
+ {0x14u, 0x04u},\r
+ {0x15u, 0x60u},\r
+ {0x17u, 0x09u},\r
+ {0x18u, 0x40u},\r
+ {0x1Eu, 0x80u},\r
+ {0x22u, 0x10u},\r
+ {0x23u, 0x20u},\r
+ {0x24u, 0x10u},\r
+ {0x25u, 0x30u},\r
+ {0x26u, 0x80u},\r
+ {0x28u, 0x02u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Du, 0x80u},\r
+ {0x2Eu, 0x20u},\r
+ {0x2Fu, 0x40u},\r
+ {0x30u, 0x80u},\r
+ {0x31u, 0x08u},\r
+ {0x34u, 0x08u},\r
+ {0x36u, 0x60u},\r
+ {0x38u, 0x08u},\r
+ {0x3Cu, 0x44u},\r
+ {0x3Du, 0x21u},\r
+ {0x5Au, 0x80u},\r
+ {0x60u, 0x02u},\r
+ {0x65u, 0x40u},\r
+ {0x67u, 0x02u},\r
+ {0x78u, 0x01u},\r
+ {0x7Au, 0x80u},\r
+ {0x80u, 0x22u},\r
+ {0x83u, 0x2Au},\r
+ {0x84u, 0x08u},\r
+ {0x85u, 0x02u},\r
+ {0x87u, 0x01u},\r
+ {0x88u, 0x08u},\r
+ {0x8Du, 0x04u},\r
+ {0x8Eu, 0x10u},\r
+ {0xC0u, 0xE3u},\r
+ {0xC2u, 0xEFu},\r
+ {0xC4u, 0xFFu},\r
+ {0xCAu, 0xF8u},\r
+ {0xCCu, 0x7Au},\r
+ {0xCEu, 0xF2u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x08u},\r
+ {0xE0u, 0x81u},\r
+ {0xE2u, 0x50u},\r
+ {0xE4u, 0x11u},\r
+ {0x81u, 0x5Cu},\r
+ {0x84u, 0x14u},\r
+ {0x85u, 0x24u},\r
+ {0x87u, 0x10u},\r
+ {0x88u, 0x3Fu},\r
+ {0x89u, 0x50u},\r
+ {0x8Au, 0x40u},\r
+ {0x8Bu, 0x0Cu},\r
+ {0x8Cu, 0x34u},\r
+ {0x90u, 0x34u},\r
+ {0x91u, 0x21u},\r
+ {0x93u, 0x1Eu},\r
+ {0x94u, 0x20u},\r
+ {0x95u, 0x11u},\r
+ {0x96u, 0x02u},\r
+ {0x97u, 0x22u},\r
+ {0x98u, 0x08u},\r
+ {0x99u, 0x30u},\r
+ {0x9Au, 0x75u},\r
+ {0x9Bu, 0x0Fu},\r
+ {0x9Cu, 0x4Bu},\r
+ {0x9Eu, 0x30u},\r
+ {0xA0u, 0x34u},\r
+ {0xA1u, 0x5Cu},\r
+ {0xA5u, 0x54u},\r
+ {0xA6u, 0x34u},\r
+ {0xA7u, 0x08u},\r
+ {0xA8u, 0x14u},\r
+ {0xA9u, 0x08u},\r
+ {0xAAu, 0x20u},\r
+ {0xADu, 0x0Cu},\r
+ {0xAFu, 0x50u},\r
+ {0xB3u, 0x30u},\r
+ {0xB4u, 0x07u},\r
+ {0xB5u, 0x0Fu},\r
+ {0xB6u, 0x78u},\r
+ {0xB7u, 0x40u},\r
+ {0xB8u, 0x80u},\r
+ {0xBAu, 0x30u},\r
+ {0xBBu, 0x08u},\r
{0xBFu, 0x40u},\r
- {0xD4u, 0x09u},\r
- {0xD6u, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x04u, 0x05u},\r
- {0x05u, 0x10u},\r
- {0x07u, 0x01u},\r
- {0x08u, 0x40u},\r
- {0x0Au, 0x20u},\r
- {0x0Du, 0x06u},\r
- {0x0Eu, 0x24u},\r
- {0x0Fu, 0x01u},\r
- {0x10u, 0x08u},\r
+ {0x00u, 0x04u},\r
+ {0x01u, 0x01u},\r
+ {0x03u, 0x06u},\r
+ {0x06u, 0x02u},\r
+ {0x07u, 0x14u},\r
+ {0x09u, 0x20u},\r
+ {0x0Bu, 0xA2u},\r
+ {0x0Cu, 0x02u},\r
+ {0x0Du, 0x08u},\r
+ {0x0Eu, 0x06u},\r
+ {0x10u, 0x82u},\r
+ {0x11u, 0x04u},\r
+ {0x12u, 0x08u},\r
{0x15u, 0x01u},\r
- {0x16u, 0x02u},\r
- {0x17u, 0x18u},\r
- {0x1Bu, 0x01u},\r
- {0x1Cu, 0x01u},\r
- {0x1Du, 0x01u},\r
- {0x1Eu, 0x04u},\r
- {0x1Fu, 0x20u},\r
- {0x20u, 0x08u},\r
- {0x22u, 0x02u},\r
- {0x23u, 0x10u},\r
- {0x27u, 0x42u},\r
- {0x28u, 0x08u},\r
- {0x29u, 0x0Au},\r
- {0x2Du, 0x01u},\r
- {0x2Fu, 0x06u},\r
- {0x30u, 0x08u},\r
+ {0x17u, 0x28u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x80u},\r
+ {0x1Bu, 0x03u},\r
+ {0x1Du, 0x10u},\r
+ {0x1Eu, 0x06u},\r
+ {0x1Fu, 0x70u},\r
+ {0x21u, 0x20u},\r
+ {0x24u, 0x29u},\r
+ {0x25u, 0x04u},\r
+ {0x26u, 0x08u},\r
+ {0x27u, 0x15u},\r
+ {0x29u, 0x01u},\r
+ {0x2Bu, 0x21u},\r
+ {0x2Cu, 0x02u},\r
+ {0x2Du, 0x05u},\r
+ {0x2Fu, 0x04u},\r
+ {0x30u, 0x82u},\r
+ {0x32u, 0x10u},\r
+ {0x33u, 0x04u},\r
{0x35u, 0x10u},\r
- {0x36u, 0x04u},\r
- {0x37u, 0x41u},\r
- {0x3Au, 0x10u},\r
+ {0x36u, 0x01u},\r
+ {0x37u, 0x04u},\r
+ {0x38u, 0x20u},\r
+ {0x39u, 0x05u},\r
+ {0x3Bu, 0x80u},\r
+ {0x3Du, 0x08u},\r
{0x3Eu, 0x12u},\r
- {0x41u, 0x06u},\r
- {0x42u, 0x01u},\r
- {0x43u, 0x02u},\r
- {0x48u, 0x01u},\r
- {0x49u, 0x10u},\r
- {0x4Bu, 0x07u},\r
- {0x50u, 0x44u},\r
- {0x51u, 0x20u},\r
- {0x52u, 0x40u},\r
- {0x58u, 0x02u},\r
- {0x5Bu, 0x02u},\r
- {0x5Eu, 0x42u},\r
- {0x5Fu, 0x24u},\r
- {0x64u, 0x02u},\r
- {0x66u, 0x01u},\r
- {0x80u, 0x40u},\r
- {0x82u, 0x01u},\r
- {0x83u, 0x20u},\r
- {0x84u, 0x04u},\r
- {0x86u, 0x01u},\r
- {0x88u, 0x08u},\r
- {0x8Au, 0x10u},\r
- {0x8Eu, 0x02u},\r
- {0x90u, 0x04u},\r
- {0x91u, 0x01u},\r
- {0x92u, 0x70u},\r
- {0x93u, 0x08u},\r
+ {0x40u, 0x01u},\r
+ {0x43u, 0x24u},\r
+ {0x49u, 0x05u},\r
+ {0x4Au, 0x05u},\r
+ {0x4Bu, 0x02u},\r
+ {0x51u, 0x08u},\r
+ {0x52u, 0x50u},\r
+ {0x53u, 0x04u},\r
+ {0x60u, 0x20u},\r
+ {0x61u, 0x0Au},\r
+ {0x68u, 0x0Au},\r
+ {0x69u, 0x05u},\r
+ {0x6Au, 0x30u},\r
+ {0x6Bu, 0x68u},\r
+ {0x70u, 0x80u},\r
+ {0x72u, 0x02u},\r
+ {0x8Eu, 0x04u},\r
{0x94u, 0x08u},\r
- {0x97u, 0x12u},\r
- {0x98u, 0x40u},\r
- {0x99u, 0x1Au},\r
- {0x9Au, 0x02u},\r
- {0x9Bu, 0x19u},\r
- {0x9Du, 0x01u},\r
- {0x9Eu, 0x40u},\r
- {0xA0u, 0x09u},\r
+ {0x95u, 0x04u},\r
+ {0x96u, 0x10u},\r
+ {0x97u, 0x82u},\r
+ {0x9Cu, 0x20u},\r
+ {0x9Du, 0x94u},\r
+ {0x9Eu, 0x52u},\r
+ {0x9Fu, 0x45u},\r
{0xA1u, 0x02u},\r
- {0xA2u, 0x15u},\r
- {0xA5u, 0x20u},\r
- {0xA7u, 0x21u},\r
- {0xAAu, 0x10u},\r
- {0xB0u, 0x40u},\r
- {0xB4u, 0x02u},\r
- {0xB5u, 0x04u},\r
- {0xC0u, 0xF0u},\r
- {0xC2u, 0xF5u},\r
- {0xC4u, 0xF2u},\r
- {0xCAu, 0xB7u},\r
- {0xCCu, 0xF2u},\r
- {0xCEu, 0xA4u},\r
- {0xD0u, 0x0Bu},\r
+ {0xA4u, 0x0Au},\r
+ {0xA6u, 0x01u},\r
+ {0xC0u, 0xEFu},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0x7Fu},\r
+ {0xCAu, 0xFBu},\r
+ {0xCCu, 0xEFu},\r
+ {0xCEu, 0xEFu},\r
+ {0xD0u, 0x0Eu},\r
{0xD2u, 0x0Cu},\r
- {0xD6u, 0xF0u},\r
- {0xD8u, 0x90u},\r
- {0xE4u, 0x02u},\r
- {0xE6u, 0x10u},\r
- {0xECu, 0x04u},\r
- {0x00u, 0x10u},\r
- {0x01u, 0xC0u},\r
- {0x03u, 0x02u},\r
- {0x05u, 0x80u},\r
- {0x06u, 0x01u},\r
- {0x08u, 0xC0u},\r
- {0x09u, 0xC0u},\r
- {0x0Au, 0x1Eu},\r
- {0x0Bu, 0x08u},\r
- {0x0Cu, 0x18u},\r
- {0x0Du, 0x1Fu},\r
- {0x0Eu, 0x61u},\r
- {0x0Fu, 0x20u},\r
- {0x10u, 0x42u},\r
- {0x11u, 0x90u},\r
- {0x12u, 0x84u},\r
- {0x13u, 0x40u},\r
- {0x14u, 0x82u},\r
- {0x15u, 0xC0u},\r
- {0x16u, 0x5Cu},\r
- {0x17u, 0x04u},\r
- {0x18u, 0x88u},\r
- {0x19u, 0x7Fu},\r
- {0x1Au, 0x40u},\r
- {0x1Bu, 0x80u},\r
- {0x1Du, 0xC0u},\r
- {0x1Fu, 0x01u},\r
- {0x20u, 0x79u},\r
- {0x24u, 0x61u},\r
- {0x26u, 0x18u},\r
- {0x27u, 0x60u},\r
- {0x28u, 0x69u},\r
- {0x2Au, 0x10u},\r
- {0x2Bu, 0xFFu},\r
- {0x2Cu, 0x79u},\r
- {0x2Fu, 0x9Fu},\r
- {0x30u, 0x1Eu},\r
- {0x32u, 0x01u},\r
- {0x34u, 0xC0u},\r
- {0x35u, 0xFFu},\r
- {0x36u, 0x20u},\r
- {0x3Au, 0x20u},\r
- {0x3Eu, 0x44u},\r
- {0x3Fu, 0x10u},\r
- {0x56u, 0x02u},\r
- {0x57u, 0x28u},\r
+ {0xD8u, 0x01u},\r
+ {0xE0u, 0x40u},\r
+ {0x00u, 0x08u},\r
+ {0x03u, 0x01u},\r
+ {0x04u, 0x01u},\r
+ {0x07u, 0x0Cu},\r
+ {0x08u, 0x04u},\r
+ {0x09u, 0x60u},\r
+ {0x11u, 0x14u},\r
+ {0x12u, 0x08u},\r
+ {0x13u, 0x43u},\r
+ {0x14u, 0x08u},\r
+ {0x15u, 0x11u},\r
+ {0x17u, 0x22u},\r
+ {0x18u, 0x07u},\r
+ {0x19u, 0x28u},\r
+ {0x1Bu, 0x13u},\r
+ {0x1Eu, 0x02u},\r
+ {0x22u, 0x08u},\r
+ {0x24u, 0x08u},\r
+ {0x2Au, 0x07u},\r
+ {0x2Cu, 0x08u},\r
+ {0x2Fu, 0x82u},\r
+ {0x30u, 0x07u},\r
+ {0x33u, 0x0Fu},\r
+ {0x34u, 0x08u},\r
+ {0x35u, 0x70u},\r
+ {0x37u, 0x80u},\r
+ {0x39u, 0x20u},\r
+ {0x3Eu, 0x11u},\r
+ {0x54u, 0x40u},\r
+ {0x56u, 0x04u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x44u},\r
- {0x82u, 0x88u},\r
- {0x86u, 0x70u},\r
- {0x87u, 0x07u},\r
- {0x89u, 0x99u},\r
- {0x8Bu, 0x22u},\r
- {0x92u, 0x07u},\r
- {0x93u, 0x80u},\r
- {0x95u, 0xAAu},\r
- {0x97u, 0x55u},\r
- {0x98u, 0xAAu},\r
- {0x9Au, 0x55u},\r
- {0x9Bu, 0x70u},\r
- {0x9Du, 0x44u},\r
- {0x9Fu, 0x88u},\r
- {0xA2u, 0x80u},\r
- {0xA8u, 0x99u},\r
- {0xAAu, 0x22u},\r
- {0xABu, 0x08u},\r
- {0xAEu, 0x08u},\r
+ {0x82u, 0x07u},\r
+ {0x84u, 0x09u},\r
+ {0x85u, 0x09u},\r
+ {0x86u, 0x02u},\r
+ {0x87u, 0x06u},\r
+ {0x8Cu, 0x04u},\r
+ {0x8Du, 0x0Bu},\r
+ {0x8Eu, 0x08u},\r
+ {0x8Fu, 0x04u},\r
+ {0x91u, 0x04u},\r
+ {0x92u, 0x08u},\r
+ {0x93u, 0x03u},\r
+ {0xA4u, 0x0Au},\r
+ {0xA6u, 0x05u},\r
+ {0xA9u, 0x0Du},\r
+ {0xABu, 0x02u},\r
{0xB0u, 0x0Fu},\r
- {0xB2u, 0xF0u},\r
- {0xB3u, 0x0Fu},\r
- {0xB5u, 0xF0u},\r
+ {0xB1u, 0x07u},\r
+ {0xB7u, 0x08u},\r
+ {0xBBu, 0x02u},\r
+ {0xBFu, 0x40u},\r
+ {0xD4u, 0x09u},\r
+ {0xD6u, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDCu, 0x11u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x01u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x08u},\r
- {0x03u, 0x40u},\r
+ {0x01u, 0x0Bu},\r
+ {0x03u, 0x02u},\r
{0x04u, 0x08u},\r
- {0x05u, 0x14u},\r
- {0x06u, 0x40u},\r
- {0x07u, 0x01u},\r
- {0x0Au, 0x88u},\r
- {0x0Du, 0x02u},\r
- {0x0Eu, 0x24u},\r
- {0x11u, 0x60u},\r
- {0x13u, 0x02u},\r
- {0x15u, 0x01u},\r
- {0x16u, 0x02u},\r
- {0x17u, 0x14u},\r
- {0x19u, 0x08u},\r
- {0x1Au, 0x80u},\r
- {0x1Bu, 0x02u},\r
- {0x1Cu, 0x86u},\r
- {0x1Du, 0x0Au},\r
- {0x1Eu, 0x06u},\r
- {0x21u, 0x04u},\r
- {0x22u, 0x10u},\r
- {0x27u, 0x08u},\r
- {0x2Au, 0x20u},\r
- {0x2Fu, 0x25u},\r
- {0x30u, 0x02u},\r
- {0x32u, 0x14u},\r
- {0x33u, 0x40u},\r
- {0x35u, 0x90u},\r
- {0x36u, 0x04u},\r
- {0x37u, 0x01u},\r
- {0x39u, 0x28u},\r
- {0x3Cu, 0x84u},\r
- {0x3Du, 0x01u},\r
- {0x3Eu, 0x10u},\r
+ {0x05u, 0x10u},\r
+ {0x07u, 0x40u},\r
+ {0x0Au, 0x40u},\r
+ {0x0Cu, 0x02u},\r
+ {0x0Du, 0x21u},\r
+ {0x0Eu, 0x12u},\r
+ {0x13u, 0x08u},\r
+ {0x15u, 0x04u},\r
+ {0x16u, 0x42u},\r
+ {0x17u, 0x20u},\r
+ {0x19u, 0x02u},\r
+ {0x1Du, 0x01u},\r
+ {0x1Fu, 0x10u},\r
+ {0x21u, 0x02u},\r
+ {0x23u, 0x01u},\r
+ {0x24u, 0x01u},\r
+ {0x25u, 0x34u},\r
+ {0x27u, 0x20u},\r
+ {0x29u, 0x10u},\r
+ {0x2Fu, 0x01u},\r
+ {0x31u, 0x02u},\r
+ {0x35u, 0x10u},\r
+ {0x36u, 0x01u},\r
+ {0x37u, 0x04u},\r
+ {0x38u, 0x08u},\r
+ {0x3Bu, 0x80u},\r
+ {0x3Cu, 0x01u},\r
+ {0x3Du, 0x28u},\r
+ {0x58u, 0x20u},\r
+ {0x59u, 0x84u},\r
+ {0x5Bu, 0x01u},\r
+ {0x62u, 0x02u},\r
+ {0x63u, 0x01u},\r
+ {0x66u, 0x51u},\r
{0x67u, 0x20u},\r
- {0x6Du, 0x01u},\r
- {0x6Eu, 0x19u},\r
- {0x6Fu, 0x15u},\r
- {0x75u, 0x80u},\r
- {0x76u, 0x02u},\r
- {0x87u, 0x01u},\r
- {0x89u, 0x04u},\r
- {0x8Du, 0x02u},\r
- {0x91u, 0x60u},\r
- {0x92u, 0x48u},\r
- {0x93u, 0x28u},\r
- {0x94u, 0x04u},\r
- {0x96u, 0x01u},\r
- {0x97u, 0x12u},\r
- {0x99u, 0x12u},\r
- {0x9Au, 0x20u},\r
- {0x9Bu, 0x42u},\r
- {0x9Cu, 0x02u},\r
- {0x9Du, 0x01u},\r
- {0x9Eu, 0x42u},\r
- {0x9Fu, 0x15u},\r
- {0xA0u, 0x0Au},\r
- {0xA1u, 0x10u},\r
- {0xA2u, 0x10u},\r
- {0xA5u, 0x2Au},\r
- {0xA7u, 0x02u},\r
- {0xA9u, 0x04u},\r
- {0xABu, 0x0Au},\r
- {0xADu, 0x01u},\r
- {0xAFu, 0x30u},\r
- {0xB0u, 0x08u},\r
- {0xB2u, 0x10u},\r
- {0xB6u, 0x01u},\r
- {0xC0u, 0xFCu},\r
- {0xC2u, 0x7Au},\r
- {0xC4u, 0xFBu},\r
- {0xCAu, 0x74u},\r
- {0xCCu, 0xFFu},\r
- {0xCEu, 0xF6u},\r
- {0xD8u, 0x40u},\r
- {0xE2u, 0x08u},\r
- {0xE8u, 0x0Cu},\r
- {0xECu, 0x08u},\r
- {0xEEu, 0x41u},\r
- {0x38u, 0x80u},\r
- {0x3Eu, 0x40u},\r
- {0x58u, 0x04u},\r
- {0x5Fu, 0x01u},\r
- {0x1Fu, 0x40u},\r
- {0x87u, 0x40u},\r
- {0x88u, 0x04u},\r
- {0x8Fu, 0x04u},\r
- {0x9Cu, 0x24u},\r
- {0x9Fu, 0x04u},\r
- {0xA0u, 0x41u},\r
- {0xA3u, 0x80u},\r
- {0xA6u, 0x04u},\r
- {0xA8u, 0x04u},\r
- {0xAAu, 0x08u},\r
- {0xABu, 0x40u},\r
- {0xADu, 0x80u},\r
- {0xAEu, 0x02u},\r
- {0xB0u, 0x08u},\r
- {0xB1u, 0x40u},\r
- {0xE4u, 0x90u},\r
- {0xE8u, 0x80u},\r
- {0xEEu, 0x20u},\r
- {0x88u, 0x40u},\r
- {0x8Bu, 0x80u},\r
- {0x8Cu, 0x20u},\r
- {0x9Cu, 0x20u},\r
- {0xA0u, 0x40u},\r
- {0xA3u, 0x80u},\r
+ {0x81u, 0x01u},\r
+ {0x92u, 0x40u},\r
+ {0x94u, 0x08u},\r
+ {0x95u, 0x07u},\r
+ {0x99u, 0x08u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Du, 0x10u},\r
+ {0x9Eu, 0x03u},\r
+ {0x9Fu, 0x40u},\r
+ {0xA3u, 0x02u},\r
+ {0xA4u, 0x08u},\r
+ {0xA6u, 0x03u},\r
+ {0xA9u, 0x40u},\r
{0xAAu, 0x04u},\r
- {0xB0u, 0x01u},\r
- {0xE2u, 0x80u},\r
- {0xE4u, 0x02u},\r
- {0xE6u, 0x20u},\r
- {0xEAu, 0x80u},\r
- {0x13u, 0x40u},\r
- {0x17u, 0x48u},\r
- {0x33u, 0x08u},\r
- {0x36u, 0x20u},\r
+ {0xB6u, 0x01u},\r
+ {0xC0u, 0x7Du},\r
+ {0xC2u, 0xF8u},\r
+ {0xC4u, 0xF4u},\r
+ {0xCAu, 0x14u},\r
+ {0xCCu, 0xE1u},\r
+ {0xCEu, 0xEAu},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0xF9u},\r
+ {0xE8u, 0x01u},\r
+ {0xEEu, 0x40u},\r
+ {0x9Cu, 0x80u},\r
+ {0xABu, 0x20u},\r
+ {0xB1u, 0x86u},\r
+ {0xB3u, 0x20u},\r
+ {0x88u, 0x80u},\r
+ {0x9Cu, 0x80u},\r
+ {0x12u, 0x08u},\r
+ {0x16u, 0x80u},\r
+ {0x17u, 0x20u},\r
+ {0x32u, 0x04u},\r
+ {0x36u, 0x80u},\r
{0x37u, 0x08u},\r
{0x38u, 0x01u},\r
- {0x3Bu, 0x40u},\r
+ {0x3Au, 0x80u},\r
{0x3Cu, 0x04u},\r
{0x3Du, 0x40u},\r
- {0x43u, 0x10u},\r
- {0x52u, 0x40u},\r
- {0x59u, 0x08u},\r
- {0x5Fu, 0x01u},\r
- {0x61u, 0x02u},\r
- {0x67u, 0x10u},\r
+ {0x41u, 0x10u},\r
+ {0x5Au, 0x01u},\r
+ {0x5Bu, 0x40u},\r
+ {0x5Cu, 0x02u},\r
+ {0x62u, 0x02u},\r
+ {0x65u, 0x04u},\r
{0x81u, 0x40u},\r
- {0x83u, 0x01u},\r
- {0x8Cu, 0x01u},\r
+ {0x8Au, 0x02u},\r
+ {0x8Du, 0x04u},\r
{0xC4u, 0xE0u},\r
{0xCCu, 0xE0u},\r
{0xCEu, 0xF0u},\r
{0xD0u, 0x10u},\r
- {0xD4u, 0x20u},\r
+ {0xD4u, 0x80u},\r
{0xD6u, 0xC0u},\r
{0xD8u, 0xC0u},\r
- {0xE2u, 0x80u},\r
{0xE6u, 0x20u},\r
- {0x31u, 0x08u},\r
- {0x33u, 0x40u},\r
- {0x35u, 0x80u},\r
- {0x37u, 0x04u},\r
- {0x39u, 0x40u},\r
- {0x50u, 0x08u},\r
- {0x57u, 0x80u},\r
- {0x58u, 0x20u},\r
- {0x62u, 0x01u},\r
- {0x87u, 0x10u},\r
- {0x88u, 0x08u},\r
- {0x89u, 0x80u},\r
- {0x8Bu, 0x80u},\r
- {0x8Du, 0x40u},\r
- {0x8Eu, 0x01u},\r
+ {0x33u, 0x18u},\r
+ {0x36u, 0x08u},\r
+ {0x37u, 0x20u},\r
+ {0x38u, 0x20u},\r
+ {0x51u, 0x08u},\r
+ {0x56u, 0x20u},\r
+ {0x58u, 0x10u},\r
+ {0x5Cu, 0x02u},\r
+ {0x84u, 0x02u},\r
+ {0x89u, 0x10u},\r
{0x94u, 0x04u},\r
- {0x97u, 0x10u},\r
- {0x9Bu, 0x40u},\r
- {0x9Du, 0x08u},\r
- {0x9Eu, 0x40u},\r
- {0x9Fu, 0x10u},\r
- {0xA5u, 0x02u},\r
- {0xA6u, 0x20u},\r
- {0xAFu, 0x08u},\r
+ {0x95u, 0x20u},\r
+ {0x96u, 0x09u},\r
+ {0x9Bu, 0x30u},\r
+ {0x9Fu, 0x08u},\r
+ {0xA6u, 0x80u},\r
+ {0xA8u, 0x01u},\r
+ {0xAAu, 0x08u},\r
+ {0xABu, 0x50u},\r
+ {0xACu, 0x02u},\r
{0xCCu, 0xF0u},\r
{0xCEu, 0x10u},\r
{0xD4u, 0xE0u},\r
- {0xD8u, 0x40u},\r
- {0xE2u, 0x10u},\r
- {0xEEu, 0x40u},\r
- {0x12u, 0x20u},\r
- {0x8Fu, 0x04u},\r
- {0x94u, 0x04u},\r
- {0x9Du, 0x08u},\r
- {0x9Eu, 0x40u},\r
- {0x9Fu, 0x14u},\r
- {0xA5u, 0x0Au},\r
- {0xA6u, 0x20u},\r
- {0xACu, 0x20u},\r
+ {0xD6u, 0x80u},\r
+ {0xE6u, 0x40u},\r
+ {0xEAu, 0x80u},\r
+ {0xEEu, 0xC0u},\r
+ {0x12u, 0x80u},\r
+ {0x32u, 0x10u},\r
+ {0x58u, 0x08u},\r
+ {0x88u, 0x10u},\r
+ {0x8Au, 0x08u},\r
+ {0x94u, 0x24u},\r
+ {0x96u, 0x09u},\r
+ {0x9Cu, 0x10u},\r
+ {0x9Fu, 0x08u},\r
+ {0xA6u, 0x88u},\r
+ {0xA7u, 0x08u},\r
+ {0xAAu, 0x20u},\r
+ {0xB5u, 0x08u},\r
{0xC4u, 0x10u},\r
- {0xEEu, 0x10u},\r
- {0x85u, 0x08u},\r
- {0x86u, 0x40u},\r
- {0x94u, 0x04u},\r
- {0x9Au, 0x80u},\r
- {0x9Du, 0x08u},\r
- {0x9Eu, 0x40u},\r
- {0x9Fu, 0x10u},\r
- {0xA0u, 0x02u},\r
- {0xA5u, 0x0Au},\r
- {0xB2u, 0x80u},\r
- {0xB4u, 0x02u},\r
- {0xE2u, 0x50u},\r
- {0x08u, 0x18u},\r
- {0x0Fu, 0x10u},\r
- {0x13u, 0x02u},\r
- {0x14u, 0x80u},\r
- {0x50u, 0x04u},\r
+ {0xCCu, 0x10u},\r
+ {0xD6u, 0x40u},\r
+ {0xEAu, 0x20u},\r
+ {0x86u, 0x04u},\r
+ {0x87u, 0x08u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Cu, 0x10u},\r
+ {0x8Eu, 0x10u},\r
+ {0x94u, 0x24u},\r
+ {0x96u, 0x28u},\r
+ {0x9Fu, 0x08u},\r
+ {0xA7u, 0x08u},\r
+ {0xA8u, 0x08u},\r
+ {0xB2u, 0x01u},\r
+ {0xE6u, 0x50u},\r
+ {0xEEu, 0x20u},\r
+ {0x09u, 0x80u},\r
+ {0x0Au, 0x20u},\r
+ {0x0Cu, 0x02u},\r
+ {0x10u, 0x20u},\r
+ {0x15u, 0x04u},\r
+ {0x50u, 0x08u},\r
{0x52u, 0x02u},\r
- {0x56u, 0x08u},\r
- {0x5Du, 0x10u},\r
- {0x84u, 0x10u},\r
+ {0x57u, 0x08u},\r
+ {0x5Cu, 0x40u},\r
+ {0x82u, 0x02u},\r
+ {0x83u, 0x08u},\r
+ {0x8Eu, 0x10u},\r
{0xC2u, 0x0Eu},\r
{0xC4u, 0x0Cu},\r
{0xD4u, 0x07u},\r
{0xD6u, 0x04u},\r
- {0x00u, 0x10u},\r
- {0x03u, 0x80u},\r
- {0x04u, 0x20u},\r
- {0x06u, 0x80u},\r
- {0x08u, 0x12u},\r
- {0x0Cu, 0x20u},\r
- {0x0Du, 0x01u},\r
- {0x80u, 0x10u},\r
- {0x85u, 0x01u},\r
- {0x88u, 0x14u},\r
- {0x8Au, 0x02u},\r
- {0x8Eu, 0x04u},\r
- {0x93u, 0x10u},\r
- {0x95u, 0x10u},\r
- {0x98u, 0x88u},\r
- {0x9Bu, 0x02u},\r
- {0x9Eu, 0x08u},\r
- {0xA6u, 0x02u},\r
- {0xA8u, 0x04u},\r
+ {0xE2u, 0x02u},\r
+ {0x00u, 0x08u},\r
+ {0x03u, 0x08u},\r
+ {0x05u, 0x02u},\r
+ {0x06u, 0x02u},\r
+ {0x09u, 0x12u},\r
+ {0x0Du, 0x24u},\r
+ {0x80u, 0x08u},\r
+ {0x82u, 0x02u},\r
+ {0x85u, 0x06u},\r
+ {0x89u, 0x02u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Cu, 0x40u},\r
+ {0x91u, 0x04u},\r
+ {0x94u, 0x40u},\r
+ {0xA0u, 0x20u},\r
+ {0xA4u, 0x08u},\r
+ {0xA8u, 0x02u},\r
+ {0xB5u, 0x80u},\r
{0xC0u, 0x0Fu},\r
{0xC2u, 0x0Fu},\r
- {0xE2u, 0x06u},\r
- {0xE4u, 0x04u},\r
- {0xE6u, 0x01u},\r
- {0x85u, 0x10u},\r
- {0x87u, 0x10u},\r
- {0x8Fu, 0x01u},\r
- {0x90u, 0x10u},\r
- {0x93u, 0x10u},\r
- {0x95u, 0x10u},\r
- {0x98u, 0x88u},\r
- {0x9Au, 0x80u},\r
- {0x9Bu, 0x02u},\r
- {0x9Cu, 0x04u},\r
- {0x9Eu, 0x08u},\r
- {0xA6u, 0x04u},\r
+ {0xE0u, 0x02u},\r
+ {0xE2u, 0x05u},\r
+ {0xEAu, 0x08u},\r
+ {0x85u, 0x04u},\r
+ {0x88u, 0x02u},\r
+ {0x91u, 0x04u},\r
+ {0xA0u, 0x04u},\r
+ {0xA1u, 0x10u},\r
{0xA8u, 0x20u},\r
- {0xACu, 0x02u},\r
- {0xB3u, 0x80u},\r
- {0xE6u, 0x08u},\r
- {0xEAu, 0x01u},\r
- {0x08u, 0x04u},\r
- {0x0Bu, 0x01u},\r
- {0x0Cu, 0x08u},\r
+ {0xADu, 0x20u},\r
+ {0xE6u, 0x01u},\r
+ {0x09u, 0x20u},\r
+ {0x0Bu, 0x20u},\r
+ {0x0Cu, 0x02u},\r
{0x0Eu, 0x08u},\r
- {0x80u, 0x80u},\r
- {0x84u, 0x08u},\r
- {0x97u, 0x01u},\r
- {0x98u, 0x80u},\r
- {0x9Cu, 0x04u},\r
- {0x9Eu, 0x08u},\r
- {0xA6u, 0x04u},\r
- {0xAAu, 0x80u},\r
- {0xAFu, 0x02u},\r
- {0xB0u, 0x08u},\r
- {0xB4u, 0x10u},\r
+ {0x87u, 0x10u},\r
+ {0x8Du, 0x20u},\r
+ {0x8Eu, 0x04u},\r
+ {0xA4u, 0x02u},\r
+ {0xA9u, 0x10u},\r
+ {0xACu, 0x04u},\r
{0xC2u, 0x0Fu},\r
- {0xEAu, 0x09u},\r
- {0x67u, 0x80u},\r
- {0x85u, 0x08u},\r
- {0x87u, 0x40u},\r
- {0x9Au, 0x80u},\r
- {0x9Du, 0x08u},\r
- {0x9Fu, 0x10u},\r
- {0xA0u, 0x02u},\r
- {0xA5u, 0x02u},\r
+ {0xE2u, 0x02u},\r
+ {0xE6u, 0x02u},\r
+ {0x83u, 0x40u},\r
+ {0x98u, 0x20u},\r
+ {0xA8u, 0x20u},\r
{0xB4u, 0x04u},\r
- {0xD8u, 0x80u},\r
- {0xE2u, 0x10u},\r
- {0xE6u, 0x10u},\r
- {0x06u, 0x40u},\r
- {0x54u, 0x02u},\r
- {0x56u, 0x80u},\r
- {0x83u, 0x10u},\r
- {0x86u, 0x40u},\r
- {0x8Du, 0x02u},\r
- {0x9Au, 0x80u},\r
- {0x9Fu, 0x10u},\r
- {0xA0u, 0x02u},\r
- {0xA5u, 0x02u},\r
- {0xC0u, 0x20u},\r
- {0xD4u, 0x40u},\r
- {0xD6u, 0x20u},\r
- {0xE0u, 0x10u},\r
{0xE2u, 0x20u},\r
- {0x9Eu, 0x08u},\r
- {0x01u, 0x02u},\r
- {0x86u, 0x08u},\r
- {0x8Du, 0x02u},\r
- {0x9Eu, 0x08u},\r
+ {0xEEu, 0x20u},\r
+ {0x04u, 0x02u},\r
+ {0x57u, 0x40u},\r
+ {0x58u, 0x20u},\r
+ {0x8Cu, 0x01u},\r
+ {0x98u, 0x20u},\r
+ {0xA3u, 0x40u},\r
+ {0xC0u, 0x20u},\r
+ {0xD4u, 0xC0u},\r
+ {0x01u, 0x04u},\r
+ {0x89u, 0x04u},\r
{0xC0u, 0x08u},\r
- {0xE2u, 0x02u},\r
+ {0xE2u, 0x04u},\r
{0x10u, 0x03u},\r
{0x1Au, 0x03u},\r
{0x00u, 0xFDu},\r
- {0x01u, 0xAFu},\r
- {0x02u, 0x0Au},\r
+ {0x01u, 0xBFu},\r
+ {0x02u, 0x2Au},\r
{0x10u, 0x55u},\r
};\r
\r
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
{(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
{(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},\r
};\r
\r
+ /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */\r
+ static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {\r
+ 0x01u, 0xC0u, 0x00u, 0x02u, 0x40u, 0xC0u, 0x00u, 0x04u, 0x07u, 0x80u, 0x18u, 0x00u, 0x04u, 0x00u, 0x00u, 0xFFu, \r
+ 0x08u, 0x90u, 0x21u, 0x40u, 0x22u, 0x1Fu, 0x08u, 0x20u, 0x40u, 0xC0u, 0x00u, 0x08u, 0x10u, 0xC0u, 0x00u, 0x01u, \r
+ 0x01u, 0x00u, 0x00u, 0x9Fu, 0x01u, 0x7Fu, 0x00u, 0x80u, 0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x60u, \r
+ 0x40u, 0x00u, 0x00u, 0x00u, 0x3Fu, 0xFFu, 0x08u, 0x00u, 0x22u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x10u, \r
+ 0x52u, 0x03u, 0x10u, 0x00u, 0x06u, 0xBEu, 0xFDu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x2Cu, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, \r
+ 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
+\r
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u};\r
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u},\r
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},\r
};\r
\r
/* USBFS_ep_1 */\r
.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_1__INTC_MASK, 0x40\r
-.set USBFS_ep_1__INTC_NUMBER, 6\r
+.set USBFS_ep_1__INTC_MASK, 0x80\r
+.set USBFS_ep_1__INTC_NUMBER, 7\r
.set USBFS_ep_1__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_6\r
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7\r
.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_2 */\r
.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_2__INTC_MASK, 0x80\r
-.set USBFS_ep_2__INTC_NUMBER, 7\r
+.set USBFS_ep_2__INTC_MASK, 0x100\r
+.set USBFS_ep_2__INTC_NUMBER, 8\r
.set USBFS_ep_2__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_7\r
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8\r
.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_3 */\r
.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_3__INTC_MASK, 0x100\r
-.set USBFS_ep_3__INTC_NUMBER, 8\r
+.set USBFS_ep_3__INTC_MASK, 0x200\r
+.set USBFS_ep_3__INTC_NUMBER, 9\r
.set USBFS_ep_3__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_8\r
+.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9\r
.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_4 */\r
.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_4__INTC_MASK, 0x200\r
-.set USBFS_ep_4__INTC_NUMBER, 9\r
+.set USBFS_ep_4__INTC_MASK, 0x400\r
+.set USBFS_ep_4__INTC_NUMBER, 10\r
.set USBFS_ep_4__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_9\r
+.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10\r
.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1\r
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0\r
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
.set SDCard_BSPIM_TxStsReg__2__POS, 2\r
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08\r
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB05_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB05_ST\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
\r
/* SD_SCK */\r
.set SD_SCK__0__MASK, 0x04\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL\r
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK\r
\r
/* SCSI_Out_Ctl */\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Out_DBx */\r
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
/* SD_RX_DMA_COMPLETE */\r
.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x10\r
-.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 4\r
+.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20\r
+.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 5\r
.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5\r
.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* SD_TX_DMA_COMPLETE */\r
.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x20\r
-.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 5\r
+.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40\r
+.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 6\r
.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5\r
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6\r
.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* SCSI_TX_DMA_COMPLETE */\r
.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x08\r
-.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 3\r
+.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10\r
+.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4\r
.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
+/* SCSI_SEL_ISR */\r
+.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_SEL_ISR__INTC_MASK, 0x08\r
+.set SCSI_SEL_ISR__INTC_NUMBER, 3\r
+.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7\r
+.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
+.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
/* SCSI_Filtered */\r
.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01\r
.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST\r
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB13_MSK\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB13_ST\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK\r
+.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST\r
\r
/* SCSI_CTL_PHASE */\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
/* SCSI_Parity_Error */\r
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST\r
\r
/* Miscellaneous */\r
.set BCLK__BUS_CLK__HZ, 50000000\r
.set CYDEV_ECC_ENABLE, 0\r
.set CYDEV_HEAP_SIZE, 0x0400\r
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1\r
-.set CYDEV_INTR_RISING, 0x0000003E\r
+.set CYDEV_INTR_RISING, 0x0000007E\r
.set CYDEV_PROJ_TYPE, 2\r
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1\r
.set CYDEV_PROJ_TYPE_LOADABLE, 2\r
/* USBFS_ep_1 */\r
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x40\r
-USBFS_ep_1__INTC_NUMBER EQU 6\r
+USBFS_ep_1__INTC_MASK EQU 0x80\r
+USBFS_ep_1__INTC_NUMBER EQU 7\r
USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_2 */\r
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x80\r
-USBFS_ep_2__INTC_NUMBER EQU 7\r
+USBFS_ep_2__INTC_MASK EQU 0x100\r
+USBFS_ep_2__INTC_NUMBER EQU 8\r
USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_3 */\r
USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_3__INTC_MASK EQU 0x100\r
-USBFS_ep_3__INTC_NUMBER EQU 8\r
+USBFS_ep_3__INTC_MASK EQU 0x200\r
+USBFS_ep_3__INTC_NUMBER EQU 9\r
USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_4 */\r
USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_4__INTC_MASK EQU 0x200\r
-USBFS_ep_4__INTC_NUMBER EQU 9\r
+USBFS_ep_4__INTC_MASK EQU 0x400\r
+USBFS_ep_4__INTC_NUMBER EQU 10\r
USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10\r
USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
\r
/* SD_SCK */\r
SD_SCK__0__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
\r
/* SCSI_Out_Ctl */\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Out_DBx */\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
/* SD_RX_DMA_COMPLETE */\r
SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* SD_TX_DMA_COMPLETE */\r
SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40\r
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6\r
SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* SCSI_TX_DMA_COMPLETE */\r
SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08\r
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3\r
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
+/* SCSI_SEL_ISR */\r
+SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_SEL_ISR__INTC_MASK EQU 0x08\r
+SCSI_SEL_ISR__INTC_NUMBER EQU 3\r
+SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
/* SCSI_Filtered */\r
SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
\r
/* SCSI_CTL_PHASE */\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
/* SCSI_Parity_Error */\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
\r
/* Miscellaneous */\r
BCLK__BUS_CLK__HZ EQU 50000000\r
CYDEV_ECC_ENABLE EQU 0\r
CYDEV_HEAP_SIZE EQU 0x0400\r
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x0000003E\r
+CYDEV_INTR_RISING EQU 0x0000007E\r
CYDEV_PROJ_TYPE EQU 2\r
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
; USBFS_ep_1\r
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x40\r
-USBFS_ep_1__INTC_NUMBER EQU 6\r
+USBFS_ep_1__INTC_MASK EQU 0x80\r
+USBFS_ep_1__INTC_NUMBER EQU 7\r
USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; USBFS_ep_2\r
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x80\r
-USBFS_ep_2__INTC_NUMBER EQU 7\r
+USBFS_ep_2__INTC_MASK EQU 0x100\r
+USBFS_ep_2__INTC_NUMBER EQU 8\r
USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; USBFS_ep_3\r
USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_3__INTC_MASK EQU 0x100\r
-USBFS_ep_3__INTC_NUMBER EQU 8\r
+USBFS_ep_3__INTC_MASK EQU 0x200\r
+USBFS_ep_3__INTC_NUMBER EQU 9\r
USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; USBFS_ep_4\r
USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_4__INTC_MASK EQU 0x200\r
-USBFS_ep_4__INTC_NUMBER EQU 9\r
+USBFS_ep_4__INTC_MASK EQU 0x400\r
+USBFS_ep_4__INTC_NUMBER EQU 10\r
USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10\r
USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
\r
; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
\r
; SD_SCK\r
SD_SCK__0__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
\r
; SCSI_Out_Ctl\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
\r
; SCSI_Out_DBx\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
; SD_RX_DMA_COMPLETE\r
SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; SD_TX_DMA_COMPLETE\r
SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40\r
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6\r
SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; SCSI_TX_DMA_COMPLETE\r
SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08\r
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3\r
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
+; SCSI_SEL_ISR\r
+SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_SEL_ISR__INTC_MASK EQU 0x08\r
+SCSI_SEL_ISR__INTC_NUMBER EQU 3\r
+SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
; SCSI_Filtered\r
SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
\r
; SCSI_CTL_PHASE\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
; SCSI_Parity_Error\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
\r
; Miscellaneous\r
BCLK__BUS_CLK__HZ EQU 50000000\r
CYDEV_ECC_ENABLE EQU 0\r
CYDEV_HEAP_SIZE EQU 0x0400\r
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x0000003E\r
+CYDEV_INTR_RISING EQU 0x0000007E\r
CYDEV_PROJ_TYPE EQU 2\r
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
#include <SCSI_RX_DMA_COMPLETE.h>\r
#include <SCSI_Parity_Error.h>\r
#include <SCSI_Filtered.h>\r
+#include <SCSI_SEL_ISR.h>\r
#include <USBFS_Dm_aliases.h>\r
#include <USBFS_Dm.h>\r
#include <USBFS_Dp_aliases.h>\r
<?xml version="1.0" encoding="utf-8"?>\r
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
- <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />\r
- </block>\r
- <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" />\r
- </block>\r
+ <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />\r
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />\r
</block>\r
- <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" />\r
+ </block>\r
+ <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Filtered_STATUS_REG" address="0x4000646D" bitWidth="8" desc="" />\r
- <register name="SCSI_Filtered_MASK_REG" address="0x4000648D" bitWidth="8" desc="" />\r
- <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649D" bitWidth="8" desc="">\r
+ <register name="SCSI_Filtered_STATUS_REG" address="0x40006468" bitWidth="8" desc="" />\r
+ <register name="SCSI_Filtered_MASK_REG" address="0x40006488" bitWidth="8" desc="" />\r
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006498" bitWidth="8" desc="">\r
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
</register>\r
</block>\r
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006465" bitWidth="8" desc="" />\r
- <register name="SCSI_Parity_Error_MASK_REG" address="0x40006485" bitWidth="8" desc="" />\r
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="">\r
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006466" bitWidth="8" desc="" />\r
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x40006486" bitWidth="8" desc="" />\r
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006496" bitWidth="8" desc="">\r
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
</field>\r
</register>\r
</block>\r
- <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" />\r
+ </block>\r
+ <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />\r
</block>\r
- <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
</block>\r
+ <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">\r
<block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />\r
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />\r
</block>\r
- <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
</blockRegMap>
\ No newline at end of file
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
<filters />\r
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_SEL_ISR" persistent="">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
+<dependencies>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_SEL_ISR.c" persistent=".\Generated_Source\PSoC5\SCSI_SEL_ISR.c">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="ARM_C_FILE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_SEL_ISR.h" persistent=".\Generated_Source\PSoC5\SCSI_SEL_ISR.h">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="NONE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
+</dependencies>\r
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
+<filters />\r
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
</dependencies>\r
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@Command Line@Command Line" v="" />\r
</name>\r
</platform>\r
+<platform>\r
+<name v="e9305a93-d091-4da5-bdc7-2813049dcdbf">\r
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Assembly@Command Line@Command Line" v="-s+ -M<> -w+ -r -DNDEBUG --fpu None" />\r
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@C/C++@Command Line@Command Line" v="-D NDEBUG --debug --endian=little -e --fpu=None --no_wrap_diagnostics" />\r
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Linker@Command Line@Command Line" v="--semihosting --entry __iar_program_start --vfe" />\r
+</name>\r
+</platform>\r
</platforms>\r
<project_current_platform v="c9323d49-d323-40b8-9b59-cc008d68a989" />\r
<project_current_processor v="CortexM3" />\r
<addressUnitBits>8</addressUnitBits>\r
<width>32</width>\r
<peripherals>\r
- <peripheral>\r
- <name>SCSI_Out_Bits</name>\r
- <description>No description available</description>\r
- <baseAddress>0x4000647B</baseAddress>\r
- <addressBlock>\r
- <offset>0</offset>\r
- <size>0x0</size>\r
- <usage>registers</usage>\r
- </addressBlock>\r
- <registers>\r
- <register>\r
- <name>SCSI_Out_Bits_CONTROL_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- </registers>\r
- </peripheral>\r
- <peripheral>\r
- <name>SCSI_Out_Ctl</name>\r
- <description>No description available</description>\r
- <baseAddress>0x40006478</baseAddress>\r
- <addressBlock>\r
- <offset>0</offset>\r
- <size>0x0</size>\r
- <usage>registers</usage>\r
- </addressBlock>\r
- <registers>\r
- <register>\r
- <name>SCSI_Out_Ctl_CONTROL_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- </registers>\r
- </peripheral>\r
<peripheral>\r
<name>Debug_Timer</name>\r
<description>No description available</description>\r
</register>\r
</registers>\r
</peripheral>\r
+ <peripheral>\r
+ <name>SCSI_Out_Ctl</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x40006474</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x0</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_Out_Ctl_CONTROL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
<peripheral>\r
<name>SCSI_Filtered</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000646D</baseAddress>\r
+ <baseAddress>0x40006468</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_Parity_Error</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006465</baseAddress>\r
+ <baseAddress>0x40006466</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
</register>\r
</registers>\r
</peripheral>\r
+ <peripheral>\r
+ <name>SCSI_Out_Bits</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x40006478</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x0</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_Out_Bits_CONTROL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
<peripheral>\r
<name>SCSI_CTL_PHASE</name>\r
<description>No description available</description>\r
const uint8 cy_meta_loadable[] = {
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x24u, 0x04u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x30u, 0x04u,
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
if (!myInitialConfig)
{
+/* This doesn't work properly, and causes crashes.
wxCommandEvent loadEvent(wxEVT_NULL, ID_BtnLoad);
GetEventHandler()->AddPendingEvent(loadEvent);
+*/
}
}
projects / SCSI2SD.git / commitdiff