--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_CMD_TIMER.c
+* Version 2.50
+*
+* Description:
+* The Timer component consists of a 8, 16, 24 or 32-bit timer with
+* a selectable period between 2 and 2^Width - 1. The timer may free run
+* or be used as a capture timer as well. The capture can be initiated
+* by a positive or negative edge signal as well as via software.
+* A trigger input can be programmed to enable the timer on rising edge
+* falling edge, either edge or continous run.
+* Interrupts may be generated due to a terminal count condition
+* or a capture event.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+
+#include "SCSI_CMD_TIMER.h"
+
+uint8 SCSI_CMD_TIMER_initVar = 0u;
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_Init
+********************************************************************************
+*
+* Summary:
+* Initialize to the schematic state
+*
+* Parameters:
+* void
+*
+* Return:
+* void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_Init(void)
+{
+ #if(!SCSI_CMD_TIMER_UsingFixedFunction)
+ /* Interrupt State Backup for Critical Region*/
+ uint8 SCSI_CMD_TIMER_interruptState;
+ #endif /* Interrupt state back up for Fixed Function only */
+
+ #if (SCSI_CMD_TIMER_UsingFixedFunction)
+ /* Clear all bits but the enable bit (if it's already set) for Timer operation */
+ SCSI_CMD_TIMER_CONTROL &= SCSI_CMD_TIMER_CTRL_ENABLE;
+
+ /* Clear the mode bits for continuous run mode */
+ #if (CY_PSOC5A)
+ SCSI_CMD_TIMER_CONTROL2 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_MODE_MASK));
+ #endif /* Clear bits in CONTROL2 only in PSOC5A */
+
+ #if (CY_PSOC3 || CY_PSOC5LP)
+ SCSI_CMD_TIMER_CONTROL3 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_MODE_MASK));
+ #endif /* CONTROL3 register exists only in PSoC3 OR PSoC5LP */
+
+ /* Check if One Shot mode is enabled i.e. RunMode !=0*/
+ #if (SCSI_CMD_TIMER_RunModeUsed != 0x0u)
+ /* Set 3rd bit of Control register to enable one shot mode */
+ SCSI_CMD_TIMER_CONTROL |= 0x04u;
+ #endif /* One Shot enabled only when RunModeUsed is not Continuous*/
+
+ #if (SCSI_CMD_TIMER_RunModeUsed == 2)
+ #if (CY_PSOC5A)
+ /* Set last 2 bits of control2 register if one shot(halt on
+ interrupt) is enabled*/
+ SCSI_CMD_TIMER_CONTROL2 |= 0x03u;
+ #endif /* Set One-Shot Halt on Interrupt bit in CONTROL2 for PSoC5A */
+
+ #if (CY_PSOC3 || CY_PSOC5LP)
+ /* Set last 2 bits of control3 register if one shot(halt on
+ interrupt) is enabled*/
+ SCSI_CMD_TIMER_CONTROL3 |= 0x03u;
+ #endif /* Set One-Shot Halt on Interrupt bit in CONTROL3 for PSoC3 or PSoC5LP */
+
+ #endif /* Remove section if One Shot Halt on Interrupt is not enabled */
+
+ #if (SCSI_CMD_TIMER_UsingHWEnable != 0)
+ #if (CY_PSOC5A)
+ /* Set the default Run Mode of the Timer to Continuous */
+ SCSI_CMD_TIMER_CONTROL2 |= SCSI_CMD_TIMER_CTRL_MODE_PULSEWIDTH;
+ #endif /* Set Continuous Run Mode in CONTROL2 for PSoC5A */
+
+ #if (CY_PSOC3 || CY_PSOC5LP)
+ /* Clear and Set ROD and COD bits of CFG2 register */
+ SCSI_CMD_TIMER_CONTROL3 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_RCOD_MASK));
+ SCSI_CMD_TIMER_CONTROL3 |= SCSI_CMD_TIMER_CTRL_RCOD;
+
+ /* Clear and Enable the HW enable bit in CFG2 register */
+ SCSI_CMD_TIMER_CONTROL3 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_ENBL_MASK));
+ SCSI_CMD_TIMER_CONTROL3 |= SCSI_CMD_TIMER_CTRL_ENBL;
+
+ /* Set the default Run Mode of the Timer to Continuous */
+ SCSI_CMD_TIMER_CONTROL3 |= SCSI_CMD_TIMER_CTRL_MODE_CONTINUOUS;
+ #endif /* Set Continuous Run Mode in CONTROL3 for PSoC3ES3 or PSoC5A */
+
+ #endif /* Configure Run Mode with hardware enable */
+
+ /* Clear and Set SYNCTC and SYNCCMP bits of RT1 register */
+ SCSI_CMD_TIMER_RT1 &= ((uint8)(~SCSI_CMD_TIMER_RT1_MASK));
+ SCSI_CMD_TIMER_RT1 |= SCSI_CMD_TIMER_SYNC;
+
+ /*Enable DSI Sync all all inputs of the Timer*/
+ SCSI_CMD_TIMER_RT1 &= ((uint8)(~SCSI_CMD_TIMER_SYNCDSI_MASK));
+ SCSI_CMD_TIMER_RT1 |= SCSI_CMD_TIMER_SYNCDSI_EN;
+
+ /* Set the IRQ to use the status register interrupts */
+ SCSI_CMD_TIMER_CONTROL2 |= SCSI_CMD_TIMER_CTRL2_IRQ_SEL;
+ #endif /* Configuring registers of fixed function implementation */
+
+ /* Set Initial values from Configuration */
+ SCSI_CMD_TIMER_WritePeriod(SCSI_CMD_TIMER_INIT_PERIOD);
+ SCSI_CMD_TIMER_WriteCounter(SCSI_CMD_TIMER_INIT_PERIOD);
+
+ #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)/* Capture counter is enabled */
+ SCSI_CMD_TIMER_CAPTURE_COUNT_CTRL |= SCSI_CMD_TIMER_CNTR_ENABLE;
+ SCSI_CMD_TIMER_SetCaptureCount(SCSI_CMD_TIMER_INIT_CAPTURE_COUNT);
+ #endif /* Configure capture counter value */
+
+ #if (!SCSI_CMD_TIMER_UsingFixedFunction)
+ #if (SCSI_CMD_TIMER_SoftwareCaptureMode)
+ SCSI_CMD_TIMER_SetCaptureMode(SCSI_CMD_TIMER_INIT_CAPTURE_MODE);
+ #endif /* Set Capture Mode for UDB implementation if capture mode is software controlled */
+
+ #if (SCSI_CMD_TIMER_SoftwareTriggerMode)
+ if (0u == (SCSI_CMD_TIMER_CONTROL & SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE))
+ {
+ SCSI_CMD_TIMER_SetTriggerMode(SCSI_CMD_TIMER_INIT_TRIGGER_MODE);
+ }
+ #endif /* Set trigger mode for UDB Implementation if trigger mode is software controlled */
+
+ /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
+ /* Enter Critical Region*/
+ SCSI_CMD_TIMER_interruptState = CyEnterCriticalSection();
+
+ /* Use the interrupt output of the status register for IRQ output */
+ SCSI_CMD_TIMER_STATUS_AUX_CTRL |= SCSI_CMD_TIMER_STATUS_ACTL_INT_EN_MASK;
+
+ /* Exit Critical Region*/
+ CyExitCriticalSection(SCSI_CMD_TIMER_interruptState);
+
+ #if (SCSI_CMD_TIMER_EnableTriggerMode)
+ SCSI_CMD_TIMER_EnableTrigger();
+ #endif /* Set Trigger enable bit for UDB implementation in the control register*/
+
+ #if (SCSI_CMD_TIMER_InterruptOnCaptureCount)
+ #if (!SCSI_CMD_TIMER_ControlRegRemoved)
+ SCSI_CMD_TIMER_SetInterruptCount(SCSI_CMD_TIMER_INIT_INT_CAPTURE_COUNT);
+ #endif /* Set interrupt count in control register if control register is not removed */
+ #endif /*Set interrupt count in UDB implementation if interrupt count feature is checked.*/
+
+ SCSI_CMD_TIMER_ClearFIFO();
+ #endif /* Configure additional features of UDB implementation */
+
+ SCSI_CMD_TIMER_SetInterruptMode(SCSI_CMD_TIMER_INIT_INTERRUPT_MODE);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_Enable
+********************************************************************************
+*
+* Summary:
+* Enable the Timer
+*
+* Parameters:
+* void
+*
+* Return:
+* void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_Enable(void)
+{
+ /* Globally Enable the Fixed Function Block chosen */
+ #if (SCSI_CMD_TIMER_UsingFixedFunction)
+ SCSI_CMD_TIMER_GLOBAL_ENABLE |= SCSI_CMD_TIMER_BLOCK_EN_MASK;
+ SCSI_CMD_TIMER_GLOBAL_STBY_ENABLE |= SCSI_CMD_TIMER_BLOCK_STBY_EN_MASK;
+ #endif /* Set Enable bit for enabling Fixed function timer*/
+
+ /* Remove assignment if control register is removed */
+ #if (!SCSI_CMD_TIMER_ControlRegRemoved || SCSI_CMD_TIMER_UsingFixedFunction)
+ SCSI_CMD_TIMER_CONTROL |= SCSI_CMD_TIMER_CTRL_ENABLE;
+ #endif /* Remove assignment if control register is removed */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_Start
+********************************************************************************
+*
+* Summary:
+* The start function initializes the timer with the default values, the
+* enables the timerto begin counting. It does not enable interrupts,
+* the EnableInt command should be called if interrupt generation is required.
+*
+* Parameters:
+* void
+*
+* Return:
+* void
+*
+* Global variables:
+* SCSI_CMD_TIMER_initVar: Is modified when this function is called for the
+* first time. Is used to ensure that initialization happens only once.
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_Start(void)
+{
+ if(SCSI_CMD_TIMER_initVar == 0u)
+ {
+ SCSI_CMD_TIMER_Init();
+
+ SCSI_CMD_TIMER_initVar = 1u; /* Clear this bit for Initialization */
+ }
+
+ /* Enable the Timer */
+ SCSI_CMD_TIMER_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_Stop
+********************************************************************************
+*
+* Summary:
+* The stop function halts the timer, but does not change any modes or disable
+* interrupts.
+*
+* Parameters:
+* void
+*
+* Return:
+* void
+*
+* Side Effects: If the Enable mode is set to Hardware only then this function
+* has no effect on the operation of the timer.
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_Stop(void)
+{
+ /* Disable Timer */
+ #if(!SCSI_CMD_TIMER_ControlRegRemoved || SCSI_CMD_TIMER_UsingFixedFunction)
+ SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_ENABLE));
+ #endif /* Remove assignment if control register is removed */
+
+ /* Globally disable the Fixed Function Block chosen */
+ #if (SCSI_CMD_TIMER_UsingFixedFunction)
+ SCSI_CMD_TIMER_GLOBAL_ENABLE &= ((uint8)(~SCSI_CMD_TIMER_BLOCK_EN_MASK));
+ SCSI_CMD_TIMER_GLOBAL_STBY_ENABLE &= ((uint8)(~SCSI_CMD_TIMER_BLOCK_STBY_EN_MASK));
+ #endif /* Disable global enable for the Timer Fixed function block to stop the Timer*/
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_SetInterruptMode
+********************************************************************************
+*
+* Summary:
+* This function selects which of the interrupt inputs may cause an interrupt.
+* The twosources are caputure and terminal. One, both or neither may
+* be selected.
+*
+* Parameters:
+* interruptMode: This parameter is used to enable interrups on either/or
+* terminal count or capture.
+*
+* Return:
+* void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_SetInterruptMode(uint8 interruptMode)
+{
+ SCSI_CMD_TIMER_STATUS_MASK = interruptMode;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_SoftwareCapture
+********************************************************************************
+*
+* Summary:
+* This function forces a capture independent of the capture signal.
+*
+* Parameters:
+* void
+*
+* Return:
+* void
+*
+* Side Effects:
+* An existing hardware capture could be overwritten.
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_SoftwareCapture(void)
+{
+ /* Generate a software capture by reading the counter register */
+ (void)SCSI_CMD_TIMER_COUNTER_LSB;
+ /* Capture Data is now in the FIFO */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ReadStatusRegister
+********************************************************************************
+*
+* Summary:
+* Reads the status register and returns it's state. This function should use
+* defined types for the bit-field information as the bits in this register may
+* be permuteable.
+*
+* Parameters:
+* void
+*
+* Return:
+* The contents of the status register
+*
+* Side Effects:
+* Status register bits may be clear on read.
+*
+*******************************************************************************/
+uint8 SCSI_CMD_TIMER_ReadStatusRegister(void)
+{
+ return (SCSI_CMD_TIMER_STATUS);
+}
+
+
+#if (!SCSI_CMD_TIMER_ControlRegRemoved) /* Remove API if control register is removed */
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ReadControlRegister
+********************************************************************************
+*
+* Summary:
+* Reads the control register and returns it's value.
+*
+* Parameters:
+* void
+*
+* Return:
+* The contents of the control register
+*
+*******************************************************************************/
+uint8 SCSI_CMD_TIMER_ReadControlRegister(void)
+{
+ return ((uint8)SCSI_CMD_TIMER_CONTROL);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_WriteControlRegister
+********************************************************************************
+*
+* Summary:
+* Sets the bit-field of the control register.
+*
+* Parameters:
+* control: The contents of the control register
+*
+* Return:
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_WriteControlRegister(uint8 control)
+{
+ SCSI_CMD_TIMER_CONTROL = control;
+}
+#endif /* Remove API if control register is removed */
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ReadPeriod
+********************************************************************************
+*
+* Summary:
+* This function returns the current value of the Period.
+*
+* Parameters:
+* void
+*
+* Return:
+* The present value of the counter.
+*
+*******************************************************************************/
+uint16 SCSI_CMD_TIMER_ReadPeriod(void)
+{
+ #if(SCSI_CMD_TIMER_UsingFixedFunction)
+ return ((uint16)CY_GET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR));
+ #else
+ return (CY_GET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR));
+ #endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_WritePeriod
+********************************************************************************
+*
+* Summary:
+* This function is used to change the period of the counter. The new period
+* will be loaded the next time terminal count is detected.
+*
+* Parameters:
+* period: This value may be between 1 and (2^Resolution)-1. A value of 0 will
+* result in the counter remaining at zero.
+*
+* Return:
+* void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_WritePeriod(uint16 period)
+{
+ #if(SCSI_CMD_TIMER_UsingFixedFunction)
+ uint16 period_temp = (uint16)period;
+ CY_SET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR, period_temp);
+ #else
+ CY_SET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR, period);
+ #endif /*Write Period value with appropriate resolution suffix depending on UDB or fixed function implementation */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ReadCapture
+********************************************************************************
+*
+* Summary:
+* This function returns the last value captured.
+*
+* Parameters:
+* void
+*
+* Return:
+* Present Capture value.
+*
+*******************************************************************************/
+uint16 SCSI_CMD_TIMER_ReadCapture(void)
+{
+ #if(SCSI_CMD_TIMER_UsingFixedFunction)
+ return ((uint16)CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR));
+ #else
+ return (CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR));
+ #endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_WriteCounter
+********************************************************************************
+*
+* Summary:
+* This funtion is used to set the counter to a specific value
+*
+* Parameters:
+* counter: New counter value.
+*
+* Return:
+* void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_WriteCounter(uint16 counter) \
+
+{
+ #if(SCSI_CMD_TIMER_UsingFixedFunction)
+ /* This functionality is removed until a FixedFunction HW update to
+ * allow this register to be written
+ */
+ CY_SET_REG16(SCSI_CMD_TIMER_COUNTER_LSB_PTR, (uint16)counter);
+
+ #else
+ CY_SET_REG16(SCSI_CMD_TIMER_COUNTER_LSB_PTR, counter);
+ #endif /* Set Write Counter only for the UDB implementation (Write Counter not available in fixed function Timer */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ReadCounter
+********************************************************************************
+*
+* Summary:
+* This function returns the current counter value.
+*
+* Parameters:
+* void
+*
+* Return:
+* Present compare value.
+*
+*******************************************************************************/
+uint16 SCSI_CMD_TIMER_ReadCounter(void)
+{
+
+ /* Force capture by reading Accumulator */
+ /* Must first do a software capture to be able to read the counter */
+ /* It is up to the user code to make sure there isn't already captured data in the FIFO */
+ (void)SCSI_CMD_TIMER_COUNTER_LSB;
+
+ /* Read the data from the FIFO (or capture register for Fixed Function)*/
+ #if(SCSI_CMD_TIMER_UsingFixedFunction)
+ return ((uint16)CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR));
+ #else
+ return (CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR));
+ #endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */
+}
+
+
+#if(!SCSI_CMD_TIMER_UsingFixedFunction) /* UDB Specific Functions */
+
+/*******************************************************************************
+ * The functions below this point are only available using the UDB
+ * implementation. If a feature is selected, then the API is enabled.
+ ******************************************************************************/
+
+
+#if (SCSI_CMD_TIMER_SoftwareCaptureMode)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_SetCaptureMode
+********************************************************************************
+*
+* Summary:
+* This function sets the capture mode to either rising or falling edge.
+*
+* Parameters:
+* captureMode: This parameter sets the capture mode of the UDB capture feature
+* The parameter values are defined using the
+* #define SCSI_CMD_TIMER__B_TIMER__CM_NONE 0
+#define SCSI_CMD_TIMER__B_TIMER__CM_RISINGEDGE 1
+#define SCSI_CMD_TIMER__B_TIMER__CM_FALLINGEDGE 2
+#define SCSI_CMD_TIMER__B_TIMER__CM_EITHEREDGE 3
+#define SCSI_CMD_TIMER__B_TIMER__CM_SOFTWARE 4
+ identifiers
+* The following are the possible values of the parameter
+* SCSI_CMD_TIMER__B_TIMER__CM_NONE - Set Capture mode to None
+* SCSI_CMD_TIMER__B_TIMER__CM_RISINGEDGE - Rising edge of Capture input
+* SCSI_CMD_TIMER__B_TIMER__CM_FALLINGEDGE - Falling edge of Capture input
+* SCSI_CMD_TIMER__B_TIMER__CM_EITHEREDGE - Either edge of Capture input
+*
+* Return:
+* void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_SetCaptureMode(uint8 captureMode)
+{
+ /* This must only set to two bits of the control register associated */
+ captureMode = ((uint8)((uint8)captureMode << SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT));
+ captureMode &= (SCSI_CMD_TIMER_CTRL_CAP_MODE_MASK);
+
+ /* Clear the Current Setting */
+ SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_CAP_MODE_MASK));
+
+ /* Write The New Setting */
+ SCSI_CMD_TIMER_CONTROL |= captureMode;
+}
+#endif /* Remove API if Capture Mode is not Software Controlled */
+
+
+#if (SCSI_CMD_TIMER_SoftwareTriggerMode)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_SetTriggerMode
+********************************************************************************
+*
+* Summary:
+* This function sets the trigger input mode
+*
+* Parameters:
+* triggerMode: Pass one of the pre-defined Trigger Modes (except Software)
+ #define SCSI_CMD_TIMER__B_TIMER__TM_NONE 0x00u
+ #define SCSI_CMD_TIMER__B_TIMER__TM_RISINGEDGE 0x04u
+ #define SCSI_CMD_TIMER__B_TIMER__TM_FALLINGEDGE 0x08u
+ #define SCSI_CMD_TIMER__B_TIMER__TM_EITHEREDGE 0x0Cu
+ #define SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE 0x10u
+*
+* Return:
+* void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_SetTriggerMode(uint8 triggerMode)
+{
+ /* This must only set to two bits of the control register associated */
+ triggerMode &= SCSI_CMD_TIMER_CTRL_TRIG_MODE_MASK;
+
+ /* Clear the Current Setting */
+ SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_TRIG_MODE_MASK));
+
+ /* Write The New Setting */
+ SCSI_CMD_TIMER_CONTROL |= (triggerMode | SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE);
+
+}
+#endif /* Remove API if Trigger Mode is not Software Controlled */
+
+#if (SCSI_CMD_TIMER_EnableTriggerMode)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_EnableTrigger
+********************************************************************************
+*
+* Summary:
+* Sets the control bit enabling Hardware Trigger mode
+*
+* Parameters:
+* void
+*
+* Return:
+* void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_EnableTrigger(void)
+{
+ #if (!SCSI_CMD_TIMER_ControlRegRemoved) /* Remove assignment if control register is removed */
+ SCSI_CMD_TIMER_CONTROL |= SCSI_CMD_TIMER_CTRL_TRIG_EN;
+ #endif /* Remove code section if control register is not used */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_DisableTrigger
+********************************************************************************
+*
+* Summary:
+* Clears the control bit enabling Hardware Trigger mode
+*
+* Parameters:
+* void
+*
+* Return:
+* void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_DisableTrigger(void)
+{
+ #if (!SCSI_CMD_TIMER_ControlRegRemoved) /* Remove assignment if control register is removed */
+ SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_TRIG_EN));
+ #endif /* Remove code section if control register is not used */
+}
+#endif /* Remove API is Trigger Mode is set to None */
+
+
+#if(SCSI_CMD_TIMER_InterruptOnCaptureCount)
+#if (!SCSI_CMD_TIMER_ControlRegRemoved) /* Remove API if control register is removed */
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_SetInterruptCount
+********************************************************************************
+*
+* Summary:
+* This function sets the capture count before an interrupt is triggered.
+*
+* Parameters:
+* interruptCount: A value between 0 and 3 is valid. If the value is 0, then
+* an interrupt will occur each time a capture occurs.
+* A value of 1 to 3 will cause the interrupt
+* to delay by the same number of captures.
+*
+* Return:
+* void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_SetInterruptCount(uint8 interruptCount)
+{
+ /* This must only set to two bits of the control register associated */
+ interruptCount &= SCSI_CMD_TIMER_CTRL_INTCNT_MASK;
+
+ /* Clear the Current Setting */
+ SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_INTCNT_MASK));
+ /* Write The New Setting */
+ SCSI_CMD_TIMER_CONTROL |= interruptCount;
+}
+#endif /* Remove API if control register is removed */
+#endif /* SCSI_CMD_TIMER_InterruptOnCaptureCount */
+
+
+#if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_SetCaptureCount
+********************************************************************************
+*
+* Summary:
+* This function sets the capture count
+*
+* Parameters:
+* captureCount: A value between 2 and 127 inclusive is valid. A value of 1
+* to 127 will cause the interrupt to delay by the same number of
+* captures.
+*
+* Return:
+* void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_SetCaptureCount(uint8 captureCount)
+{
+ SCSI_CMD_TIMER_CAP_COUNT = captureCount;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ReadCaptureCount
+********************************************************************************
+*
+* Summary:
+* This function reads the capture count setting
+*
+* Parameters:
+* void
+*
+* Return:
+* Returns the Capture Count Setting
+*
+*******************************************************************************/
+uint8 SCSI_CMD_TIMER_ReadCaptureCount(void)
+{
+ return ((uint8)SCSI_CMD_TIMER_CAP_COUNT);
+}
+#endif /* SCSI_CMD_TIMER_UsingHWCaptureCounter */
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ClearFIFO
+********************************************************************************
+*
+* Summary:
+* This function clears all capture data from the capture FIFO
+*
+* Parameters:
+* void
+*
+* Return:
+* void
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ClearFIFO(void)
+{
+ while(0u != (SCSI_CMD_TIMER_ReadStatusRegister() & SCSI_CMD_TIMER_STATUS_FIFONEMP))
+ {
+ (void)SCSI_CMD_TIMER_ReadCapture();
+ }
+}
+
+#endif /* UDB Specific Functions */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_CMD_TIMER.h
+* Version 2.50
+*
+* Description:
+* Contains the function prototypes and constants available to the timer
+* user module.
+*
+* Note:
+* None
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+
+#if !defined(CY_Timer_v2_30_SCSI_CMD_TIMER_H)
+#define CY_Timer_v2_30_SCSI_CMD_TIMER_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */
+
+extern uint8 SCSI_CMD_TIMER_initVar;
+
+/* Check to see if required defines such as CY_PSOC5LP are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5LP)
+ #error Component Timer_v2_50 requires cy_boot v3.0 or later
+#endif /* (CY_ PSOC5LP) */
+
+
+/**************************************
+* Parameter Defaults
+**************************************/
+
+#define SCSI_CMD_TIMER_Resolution 16u
+#define SCSI_CMD_TIMER_UsingFixedFunction 1u
+#define SCSI_CMD_TIMER_UsingHWCaptureCounter 0u
+#define SCSI_CMD_TIMER_SoftwareCaptureMode 0u
+#define SCSI_CMD_TIMER_SoftwareTriggerMode 0u
+#define SCSI_CMD_TIMER_UsingHWEnable 0u
+#define SCSI_CMD_TIMER_EnableTriggerMode 0u
+#define SCSI_CMD_TIMER_InterruptOnCaptureCount 0u
+#define SCSI_CMD_TIMER_RunModeUsed 1u
+#define SCSI_CMD_TIMER_ControlRegRemoved 0u
+
+
+/***************************************
+* Type defines
+***************************************/
+
+
+/**************************************************************************
+ * Sleep Wakeup Backup structure for Timer Component
+ *************************************************************************/
+typedef struct
+{
+ uint8 TimerEnableState;
+ #if(!SCSI_CMD_TIMER_UsingFixedFunction)
+ #if (CY_UDB_V0)
+ uint16 TimerUdb; /* Timer internal counter value */
+ uint16 TimerPeriod; /* Timer Period value */
+ uint8 InterruptMaskValue; /* Timer Compare Value */
+ #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
+ uint8 TimerCaptureCounter; /* Timer Capture Counter Value */
+ #endif /* variable declaration for backing up Capture Counter value*/
+ #endif /* variables for non retention registers in CY_UDB_V0 */
+
+ #if (CY_UDB_V1)
+ uint16 TimerUdb;
+ uint8 InterruptMaskValue;
+ #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
+ uint8 TimerCaptureCounter;
+ #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */
+ #endif /* (CY_UDB_V1) */
+
+ #if (!SCSI_CMD_TIMER_ControlRegRemoved)
+ uint8 TimerControlRegister;
+ #endif /* variable declaration for backing up enable state of the Timer */
+ #endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */
+}SCSI_CMD_TIMER_backupStruct;
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+void SCSI_CMD_TIMER_Start(void) ;
+void SCSI_CMD_TIMER_Stop(void) ;
+
+void SCSI_CMD_TIMER_SetInterruptMode(uint8 interruptMode) ;
+uint8 SCSI_CMD_TIMER_ReadStatusRegister(void) ;
+/* Deprecated function. Do not use this in future. Retained for backward compatibility */
+#define SCSI_CMD_TIMER_GetInterruptSource() SCSI_CMD_TIMER_ReadStatusRegister()
+
+#if(!SCSI_CMD_TIMER_ControlRegRemoved)
+ uint8 SCSI_CMD_TIMER_ReadControlRegister(void) ;
+ void SCSI_CMD_TIMER_WriteControlRegister(uint8 control) \
+ ;
+#endif /* (!SCSI_CMD_TIMER_ControlRegRemoved) */
+
+uint16 SCSI_CMD_TIMER_ReadPeriod(void) ;
+void SCSI_CMD_TIMER_WritePeriod(uint16 period) \
+ ;
+uint16 SCSI_CMD_TIMER_ReadCounter(void) ;
+void SCSI_CMD_TIMER_WriteCounter(uint16 counter) \
+ ;
+uint16 SCSI_CMD_TIMER_ReadCapture(void) ;
+void SCSI_CMD_TIMER_SoftwareCapture(void) ;
+
+
+#if(!SCSI_CMD_TIMER_UsingFixedFunction) /* UDB Prototypes */
+ #if (SCSI_CMD_TIMER_SoftwareCaptureMode)
+ void SCSI_CMD_TIMER_SetCaptureMode(uint8 captureMode) ;
+ #endif /* (!SCSI_CMD_TIMER_UsingFixedFunction) */
+
+ #if (SCSI_CMD_TIMER_SoftwareTriggerMode)
+ void SCSI_CMD_TIMER_SetTriggerMode(uint8 triggerMode) ;
+ #endif /* (SCSI_CMD_TIMER_SoftwareTriggerMode) */
+ #if (SCSI_CMD_TIMER_EnableTriggerMode)
+ void SCSI_CMD_TIMER_EnableTrigger(void) ;
+ void SCSI_CMD_TIMER_DisableTrigger(void) ;
+ #endif /* (SCSI_CMD_TIMER_EnableTriggerMode) */
+
+ #if(SCSI_CMD_TIMER_InterruptOnCaptureCount)
+ #if(!SCSI_CMD_TIMER_ControlRegRemoved)
+ void SCSI_CMD_TIMER_SetInterruptCount(uint8 interruptCount) \
+ ;
+ #endif /* (!SCSI_CMD_TIMER_ControlRegRemoved) */
+ #endif /* (SCSI_CMD_TIMER_InterruptOnCaptureCount) */
+
+ #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
+ void SCSI_CMD_TIMER_SetCaptureCount(uint8 captureCount) \
+ ;
+ uint8 SCSI_CMD_TIMER_ReadCaptureCount(void) ;
+ #endif /* (SCSI_CMD_TIMER_UsingHWCaptureCounter) */
+
+ void SCSI_CMD_TIMER_ClearFIFO(void) ;
+#endif /* UDB Prototypes */
+
+/* Sleep Retention APIs */
+void SCSI_CMD_TIMER_Init(void) ;
+void SCSI_CMD_TIMER_Enable(void) ;
+void SCSI_CMD_TIMER_SaveConfig(void) ;
+void SCSI_CMD_TIMER_RestoreConfig(void) ;
+void SCSI_CMD_TIMER_Sleep(void) ;
+void SCSI_CMD_TIMER_Wakeup(void) ;
+
+
+/***************************************
+* Enumerated Types and Parameters
+***************************************/
+
+/* Enumerated Type B_Timer__CaptureModes, Used in Capture Mode */
+#define SCSI_CMD_TIMER__B_TIMER__CM_NONE 0
+#define SCSI_CMD_TIMER__B_TIMER__CM_RISINGEDGE 1
+#define SCSI_CMD_TIMER__B_TIMER__CM_FALLINGEDGE 2
+#define SCSI_CMD_TIMER__B_TIMER__CM_EITHEREDGE 3
+#define SCSI_CMD_TIMER__B_TIMER__CM_SOFTWARE 4
+
+
+
+/* Enumerated Type B_Timer__TriggerModes, Used in Trigger Mode */
+#define SCSI_CMD_TIMER__B_TIMER__TM_NONE 0x00u
+#define SCSI_CMD_TIMER__B_TIMER__TM_RISINGEDGE 0x04u
+#define SCSI_CMD_TIMER__B_TIMER__TM_FALLINGEDGE 0x08u
+#define SCSI_CMD_TIMER__B_TIMER__TM_EITHEREDGE 0x0Cu
+#define SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE 0x10u
+
+
+/***************************************
+* Initialial Parameter Constants
+***************************************/
+
+#define SCSI_CMD_TIMER_INIT_PERIOD 1199u
+#define SCSI_CMD_TIMER_INIT_CAPTURE_MODE ((uint8)((uint8)0u << SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT))
+#define SCSI_CMD_TIMER_INIT_TRIGGER_MODE ((uint8)((uint8)0u << SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT))
+#if (SCSI_CMD_TIMER_UsingFixedFunction)
+ #define SCSI_CMD_TIMER_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT)) | \
+ ((uint8)((uint8)0 << SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT)))
+#else
+ #define SCSI_CMD_TIMER_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT)) | \
+ ((uint8)((uint8)0 << SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT)) | \
+ ((uint8)((uint8)0 << SCSI_CMD_TIMER_STATUS_FIFOFULL_INT_MASK_SHIFT)))
+#endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */
+#define SCSI_CMD_TIMER_INIT_CAPTURE_COUNT (2u)
+#define SCSI_CMD_TIMER_INIT_INT_CAPTURE_COUNT ((uint8)((uint8)(1u - 1u) << SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT))
+
+
+/***************************************
+* Registers
+***************************************/
+
+#if (SCSI_CMD_TIMER_UsingFixedFunction) /* Implementation Specific Registers and Register Constants */
+
+
+ /***************************************
+ * Fixed Function Registers
+ ***************************************/
+
+ #define SCSI_CMD_TIMER_STATUS (*(reg8 *) SCSI_CMD_TIMER_TimerHW__SR0 )
+ /* In Fixed Function Block Status and Mask are the same register */
+ #define SCSI_CMD_TIMER_STATUS_MASK (*(reg8 *) SCSI_CMD_TIMER_TimerHW__SR0 )
+ #define SCSI_CMD_TIMER_CONTROL (*(reg8 *) SCSI_CMD_TIMER_TimerHW__CFG0)
+ #define SCSI_CMD_TIMER_CONTROL2 (*(reg8 *) SCSI_CMD_TIMER_TimerHW__CFG1)
+ #define SCSI_CMD_TIMER_CONTROL2_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerHW__CFG1)
+ #define SCSI_CMD_TIMER_RT1 (*(reg8 *) SCSI_CMD_TIMER_TimerHW__RT1)
+ #define SCSI_CMD_TIMER_RT1_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerHW__RT1)
+
+ #if (CY_PSOC3 || CY_PSOC5LP)
+ #define SCSI_CMD_TIMER_CONTROL3 (*(reg8 *) SCSI_CMD_TIMER_TimerHW__CFG2)
+ #define SCSI_CMD_TIMER_CONTROL3_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerHW__CFG2)
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */
+ #define SCSI_CMD_TIMER_GLOBAL_ENABLE (*(reg8 *) SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG)
+ #define SCSI_CMD_TIMER_GLOBAL_STBY_ENABLE (*(reg8 *) SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG)
+
+ #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerHW__CAP0 )
+ #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerHW__CAP0 )
+ #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerHW__PER0 )
+ #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerHW__PER0 )
+ #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerHW__CNT_CMP0 )
+ #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerHW__CNT_CMP0 )
+
+
+ /***************************************
+ * Register Constants
+ ***************************************/
+
+ /* Fixed Function Block Chosen */
+ #define SCSI_CMD_TIMER_BLOCK_EN_MASK SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK
+ #define SCSI_CMD_TIMER_BLOCK_STBY_EN_MASK SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK
+
+ /* Control Register Bit Locations */
+ /* Interrupt Count - Not valid for Fixed Function Block */
+ #define SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT 0x00u
+ /* Trigger Polarity - Not valid for Fixed Function Block */
+ #define SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT 0x00u
+ /* Trigger Enable - Not valid for Fixed Function Block */
+ #define SCSI_CMD_TIMER_CTRL_TRIG_EN_SHIFT 0x00u
+ /* Capture Polarity - Not valid for Fixed Function Block */
+ #define SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT 0x00u
+ /* Timer Enable - As defined in Register Map, part of TMRX_CFG0 register */
+ #define SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT 0x00u
+
+ /* Control Register Bit Masks */
+ #define SCSI_CMD_TIMER_CTRL_ENABLE ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT))
+
+ /* Control2 Register Bit Masks */
+ /* As defined in Register Map, Part of the TMRX_CFG1 register */
+ #define SCSI_CMD_TIMER_CTRL2_IRQ_SEL_SHIFT 0x00u
+ #define SCSI_CMD_TIMER_CTRL2_IRQ_SEL ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL2_IRQ_SEL_SHIFT))
+
+ #if (CY_PSOC5A)
+ /* Use CFG1 Mode bits to set run mode */
+ /* As defined by Verilog Implementation */
+ #define SCSI_CMD_TIMER_CTRL_MODE_SHIFT 0x01u
+ #define SCSI_CMD_TIMER_CTRL_MODE_MASK ((uint8)((uint8)0x07u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT))
+ #endif /* (CY_PSOC5A) */
+ #if (CY_PSOC3 || CY_PSOC5LP)
+ /* Control3 Register Bit Locations */
+ #define SCSI_CMD_TIMER_CTRL_RCOD_SHIFT 0x02u
+ #define SCSI_CMD_TIMER_CTRL_ENBL_SHIFT 0x00u
+ #define SCSI_CMD_TIMER_CTRL_MODE_SHIFT 0x00u
+
+ /* Control3 Register Bit Masks */
+ #define SCSI_CMD_TIMER_CTRL_RCOD_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_RCOD_SHIFT)) /* ROD and COD bit masks */
+ #define SCSI_CMD_TIMER_CTRL_ENBL_MASK ((uint8)((uint8)0x80u << SCSI_CMD_TIMER_CTRL_ENBL_SHIFT)) /* HW_EN bit mask */
+ #define SCSI_CMD_TIMER_CTRL_MODE_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT)) /* Run mode bit mask */
+
+ #define SCSI_CMD_TIMER_CTRL_RCOD ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_RCOD_SHIFT))
+ #define SCSI_CMD_TIMER_CTRL_ENBL ((uint8)((uint8)0x80u << SCSI_CMD_TIMER_CTRL_ENBL_SHIFT))
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+ /*RT1 Synch Constants: Applicable for PSoC3 and PSoC5LP */
+ #define SCSI_CMD_TIMER_RT1_SHIFT 0x04u
+ /* Sync TC and CMP bit masks */
+ #define SCSI_CMD_TIMER_RT1_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_RT1_SHIFT))
+ #define SCSI_CMD_TIMER_SYNC ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_RT1_SHIFT))
+ #define SCSI_CMD_TIMER_SYNCDSI_SHIFT 0x00u
+ /* Sync all DSI inputs with Mask */
+ #define SCSI_CMD_TIMER_SYNCDSI_MASK ((uint8)((uint8)0x0Fu << SCSI_CMD_TIMER_SYNCDSI_SHIFT))
+ /* Sync all DSI inputs */
+ #define SCSI_CMD_TIMER_SYNCDSI_EN ((uint8)((uint8)0x0Fu << SCSI_CMD_TIMER_SYNCDSI_SHIFT))
+
+ #define SCSI_CMD_TIMER_CTRL_MODE_PULSEWIDTH ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT))
+ #define SCSI_CMD_TIMER_CTRL_MODE_PERIOD ((uint8)((uint8)0x02u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT))
+ #define SCSI_CMD_TIMER_CTRL_MODE_CONTINUOUS ((uint8)((uint8)0x00u << SCSI_CMD_TIMER_CTRL_MODE_SHIFT))
+
+ /* Status Register Bit Locations */
+ /* As defined in Register Map, part of TMRX_SR0 register */
+ #define SCSI_CMD_TIMER_STATUS_TC_SHIFT 0x07u
+ /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
+ #define SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT 0x06u
+ /* As defined in Register Map, part of TMRX_SR0 register */
+ #define SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT (SCSI_CMD_TIMER_STATUS_TC_SHIFT - 0x04u)
+ /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
+ #define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT (SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT - 0x04u)
+
+ /* Status Register Bit Masks */
+ #define SCSI_CMD_TIMER_STATUS_TC ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_SHIFT))
+ #define SCSI_CMD_TIMER_STATUS_CAPTURE ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT))
+ /* Interrupt Enable Bit-Mask for interrupt on TC */
+ #define SCSI_CMD_TIMER_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT))
+ /* Interrupt Enable Bit-Mask for interrupt on Capture */
+ #define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT))
+
+#else /* UDB Registers and Register Constants */
+
+
+ /***************************************
+ * UDB Registers
+ ***************************************/
+
+ #define SCSI_CMD_TIMER_STATUS (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_rstSts_stsreg__STATUS_REG )
+ #define SCSI_CMD_TIMER_STATUS_MASK (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_rstSts_stsreg__MASK_REG)
+ #define SCSI_CMD_TIMER_STATUS_AUX_CTRL (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG)
+ #define SCSI_CMD_TIMER_CONTROL (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG )
+
+ #if(SCSI_CMD_TIMER_Resolution <= 8u) /* 8-bit Timer */
+ #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
+ #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
+ #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
+ #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
+ #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
+ #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg8 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
+ #elif(SCSI_CMD_TIMER_Resolution <= 16u) /* 8-bit Timer */
+ #if(CY_PSOC3) /* 8-bit addres space */
+ #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
+ #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
+ #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
+ #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
+ #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
+ #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
+ #else /* 16-bit address space */
+ #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
+ #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
+ #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
+ #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
+ #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
+ #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg16 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
+ #endif /* CY_PSOC3 */
+ #elif(SCSI_CMD_TIMER_Resolution <= 24u)/* 24-bit Timer */
+ #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
+ #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
+ #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
+ #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
+ #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
+ #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
+ #else /* 32-bit Timer */
+ #if(CY_PSOC3 || CY_PSOC5) /* 8-bit address space */
+ #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
+ #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__F0_REG )
+ #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
+ #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__D0_REG )
+ #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
+ #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__A0_REG )
+ #else /* 32-bit address space */
+ #define SCSI_CMD_TIMER_CAPTURE_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
+ #define SCSI_CMD_TIMER_CAPTURE_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
+ #define SCSI_CMD_TIMER_PERIOD_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
+ #define SCSI_CMD_TIMER_PERIOD_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
+ #define SCSI_CMD_TIMER_COUNTER_LSB (* (reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
+ #define SCSI_CMD_TIMER_COUNTER_LSB_PTR ((reg32 *) SCSI_CMD_TIMER_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
+ #endif /* CY_PSOC3 || CY_PSOC5 */
+ #endif
+
+ #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
+ #define SCSI_CMD_TIMER_CAP_COUNT (*(reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__PERIOD_REG )
+ #define SCSI_CMD_TIMER_CAP_COUNT_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__PERIOD_REG )
+ #define SCSI_CMD_TIMER_CAPTURE_COUNT_CTRL (*(reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
+ #define SCSI_CMD_TIMER_CAPTURE_COUNT_CTRL_PTR ( (reg8 *) SCSI_CMD_TIMER_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
+ #endif /* (SCSI_CMD_TIMER_UsingHWCaptureCounter) */
+
+
+ /***************************************
+ * Register Constants
+ ***************************************/
+
+ /* Control Register Bit Locations */
+ #define SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT 0x00u /* As defined by Verilog Implementation */
+ #define SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT 0x02u /* As defined by Verilog Implementation */
+ #define SCSI_CMD_TIMER_CTRL_TRIG_EN_SHIFT 0x04u /* As defined by Verilog Implementation */
+ #define SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT 0x05u /* As defined by Verilog Implementation */
+ #define SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT 0x07u /* As defined by Verilog Implementation */
+
+ /* Control Register Bit Masks */
+ #define SCSI_CMD_TIMER_CTRL_INTCNT_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_INTCNT_SHIFT))
+ #define SCSI_CMD_TIMER_CTRL_TRIG_MODE_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_TRIG_MODE_SHIFT))
+ #define SCSI_CMD_TIMER_CTRL_TRIG_EN ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_TRIG_EN_SHIFT))
+ #define SCSI_CMD_TIMER_CTRL_CAP_MODE_MASK ((uint8)((uint8)0x03u << SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT))
+ #define SCSI_CMD_TIMER_CTRL_ENABLE ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_CTRL_ENABLE_SHIFT))
+
+ /* Bit Counter (7-bit) Control Register Bit Definitions */
+ /* As defined by the Register map for the AUX Control Register */
+ #define SCSI_CMD_TIMER_CNTR_ENABLE 0x20u
+
+ /* Status Register Bit Locations */
+ #define SCSI_CMD_TIMER_STATUS_TC_SHIFT 0x00u /* As defined by Verilog Implementation */
+ #define SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT 0x01u /* As defined by Verilog Implementation */
+ #define SCSI_CMD_TIMER_STATUS_TC_INT_MASK_SHIFT SCSI_CMD_TIMER_STATUS_TC_SHIFT
+ #define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK_SHIFT SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT
+ #define SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT 0x02u /* As defined by Verilog Implementation */
+ #define SCSI_CMD_TIMER_STATUS_FIFONEMP_SHIFT 0x03u /* As defined by Verilog Implementation */
+ #define SCSI_CMD_TIMER_STATUS_FIFOFULL_INT_MASK_SHIFT SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT
+
+ /* Status Register Bit Masks */
+ /* Sticky TC Event Bit-Mask */
+ #define SCSI_CMD_TIMER_STATUS_TC ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_SHIFT))
+ /* Sticky Capture Event Bit-Mask */
+ #define SCSI_CMD_TIMER_STATUS_CAPTURE ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT))
+ /* Interrupt Enable Bit-Mask */
+ #define SCSI_CMD_TIMER_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_TC_SHIFT))
+ /* Interrupt Enable Bit-Mask */
+ #define SCSI_CMD_TIMER_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_CAPTURE_SHIFT))
+ /* NOT-Sticky FIFO Full Bit-Mask */
+ #define SCSI_CMD_TIMER_STATUS_FIFOFULL ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT))
+ /* NOT-Sticky FIFO Not Empty Bit-Mask */
+ #define SCSI_CMD_TIMER_STATUS_FIFONEMP ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_FIFONEMP_SHIFT))
+ /* Interrupt Enable Bit-Mask */
+ #define SCSI_CMD_TIMER_STATUS_FIFOFULL_INT_MASK ((uint8)((uint8)0x01u << SCSI_CMD_TIMER_STATUS_FIFOFULL_SHIFT))
+
+ #define SCSI_CMD_TIMER_STATUS_ACTL_INT_EN 0x10u /* As defined for the ACTL Register */
+
+ /* Datapath Auxillary Control Register definitions */
+ #define SCSI_CMD_TIMER_AUX_CTRL_FIFO0_CLR 0x01u /* As defined by Register map */
+ #define SCSI_CMD_TIMER_AUX_CTRL_FIFO1_CLR 0x02u /* As defined by Register map */
+ #define SCSI_CMD_TIMER_AUX_CTRL_FIFO0_LVL 0x04u /* As defined by Register map */
+ #define SCSI_CMD_TIMER_AUX_CTRL_FIFO1_LVL 0x08u /* As defined by Register map */
+ #define SCSI_CMD_TIMER_STATUS_ACTL_INT_EN_MASK 0x10u /* As defined for the ACTL Register */
+
+#endif /* Implementation Specific Registers and Register Constants */
+
+#endif /* CY_Timer_v2_30_SCSI_CMD_TIMER_H */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_CMD_TIMER_ISR.c
+* Version 1.70
+*
+* Description:
+* API for controlling the state of an interrupt.
+*
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <SCSI_CMD_TIMER_ISR.h>
+
+#if !defined(SCSI_CMD_TIMER_ISR__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Place your includes, defines and code here
+********************************************************************************/
+/* `#START SCSI_CMD_TIMER_ISR_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE 16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_Start
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_Start(void)
+{
+ /* For all we know the interrupt is active. */
+ SCSI_CMD_TIMER_ISR_Disable();
+
+ /* Set the ISR to point to the SCSI_CMD_TIMER_ISR Interrupt. */
+ SCSI_CMD_TIMER_ISR_SetVector(&SCSI_CMD_TIMER_ISR_Interrupt);
+
+ /* Set the priority. */
+ SCSI_CMD_TIMER_ISR_SetPriority((uint8)SCSI_CMD_TIMER_ISR_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SCSI_CMD_TIMER_ISR_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_StartEx
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_StartEx(cyisraddress address)
+{
+ /* For all we know the interrupt is active. */
+ SCSI_CMD_TIMER_ISR_Disable();
+
+ /* Set the ISR to point to the SCSI_CMD_TIMER_ISR Interrupt. */
+ SCSI_CMD_TIMER_ISR_SetVector(address);
+
+ /* Set the priority. */
+ SCSI_CMD_TIMER_ISR_SetPriority((uint8)SCSI_CMD_TIMER_ISR_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ SCSI_CMD_TIMER_ISR_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_Stop
+********************************************************************************
+*
+* Summary:
+* Disables and removes the interrupt.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_Stop(void)
+{
+ /* Disable this interrupt. */
+ SCSI_CMD_TIMER_ISR_Disable();
+
+ /* Set the ISR to point to the passive one. */
+ SCSI_CMD_TIMER_ISR_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_Interrupt
+********************************************************************************
+*
+* Summary:
+* The default Interrupt Service Routine for SCSI_CMD_TIMER_ISR.
+*
+* Add custom code between the coments to keep the next version of this file
+* from over writting your code.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+CY_ISR(SCSI_CMD_TIMER_ISR_Interrupt)
+{
+ /* Place your Interrupt code here. */
+ /* `#START SCSI_CMD_TIMER_ISR_Interrupt` */
+
+ /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_SetVector
+********************************************************************************
+*
+* Summary:
+* Change the ISR vector for the Interrupt. Note calling SCSI_CMD_TIMER_ISR_Start
+* will override any effect this method would have had. To set the vector
+* before the component has been started use SCSI_CMD_TIMER_ISR_StartEx instead.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_SetVector(cyisraddress address)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_CMD_TIMER_ISR__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_GetVector
+********************************************************************************
+*
+* Summary:
+* Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress SCSI_CMD_TIMER_ISR_GetVector(void)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_CMD_TIMER_ISR__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_SetPriority
+********************************************************************************
+*
+* Summary:
+* Sets the Priority of the Interrupt. Note calling SCSI_CMD_TIMER_ISR_Start
+* or SCSI_CMD_TIMER_ISR_StartEx will override any effect this method
+* would have had. This method should only be called after
+* SCSI_CMD_TIMER_ISR_Start or SCSI_CMD_TIMER_ISR_StartEx has been called. To set
+* the initial priority for the component use the cydwr file in the tool.
+*
+* Parameters:
+* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_SetPriority(uint8 priority)
+{
+ *SCSI_CMD_TIMER_ISR_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_GetPriority
+********************************************************************************
+*
+* Summary:
+* Gets the Priority of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+*******************************************************************************/
+uint8 SCSI_CMD_TIMER_ISR_GetPriority(void)
+{
+ uint8 priority;
+
+
+ priority = *SCSI_CMD_TIMER_ISR_INTC_PRIOR >> 5;
+
+ return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_Enable
+********************************************************************************
+*
+* Summary:
+* Enables the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_Enable(void)
+{
+ /* Enable the general interrupt. */
+ *SCSI_CMD_TIMER_ISR_INTC_SET_EN = SCSI_CMD_TIMER_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_GetState
+********************************************************************************
+*
+* Summary:
+* Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* 1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 SCSI_CMD_TIMER_ISR_GetState(void)
+{
+ /* Get the state of the general interrupt. */
+ return ((*SCSI_CMD_TIMER_ISR_INTC_SET_EN & (uint32)SCSI_CMD_TIMER_ISR__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_Disable
+********************************************************************************
+*
+* Summary:
+* Disables the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_Disable(void)
+{
+ /* Disable the general interrupt. */
+ *SCSI_CMD_TIMER_ISR_INTC_CLR_EN = SCSI_CMD_TIMER_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_SetPending
+********************************************************************************
+*
+* Summary:
+* Causes the Interrupt to enter the pending state, a software method of
+* generating the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_SetPending(void)
+{
+ *SCSI_CMD_TIMER_ISR_INTC_SET_PD = SCSI_CMD_TIMER_ISR__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_ISR_ClearPending
+********************************************************************************
+*
+* Summary:
+* Clears a pending interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_ISR_ClearPending(void)
+{
+ *SCSI_CMD_TIMER_ISR_INTC_CLR_PD = SCSI_CMD_TIMER_ISR__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_CMD_TIMER_ISR.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_SCSI_CMD_TIMER_ISR_H)
+#define CY_ISR_SCSI_CMD_TIMER_ISR_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void SCSI_CMD_TIMER_ISR_Start(void);
+void SCSI_CMD_TIMER_ISR_StartEx(cyisraddress address);
+void SCSI_CMD_TIMER_ISR_Stop(void);
+
+CY_ISR_PROTO(SCSI_CMD_TIMER_ISR_Interrupt);
+
+void SCSI_CMD_TIMER_ISR_SetVector(cyisraddress address);
+cyisraddress SCSI_CMD_TIMER_ISR_GetVector(void);
+
+void SCSI_CMD_TIMER_ISR_SetPriority(uint8 priority);
+uint8 SCSI_CMD_TIMER_ISR_GetPriority(void);
+
+void SCSI_CMD_TIMER_ISR_Enable(void);
+uint8 SCSI_CMD_TIMER_ISR_GetState(void);
+void SCSI_CMD_TIMER_ISR_Disable(void);
+
+void SCSI_CMD_TIMER_ISR_SetPending(void);
+void SCSI_CMD_TIMER_ISR_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_CMD_TIMER_ISR ISR. */
+#define SCSI_CMD_TIMER_ISR_INTC_VECTOR ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_VECT)
+
+/* Address of the SCSI_CMD_TIMER_ISR ISR priority. */
+#define SCSI_CMD_TIMER_ISR_INTC_PRIOR ((reg8 *) SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG)
+
+/* Priority of the SCSI_CMD_TIMER_ISR interrupt. */
+#define SCSI_CMD_TIMER_ISR_INTC_PRIOR_NUMBER SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_CMD_TIMER_ISR interrupt. */
+#define SCSI_CMD_TIMER_ISR_INTC_SET_EN ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_CMD_TIMER_ISR interrupt. */
+#define SCSI_CMD_TIMER_ISR_INTC_CLR_EN ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the SCSI_CMD_TIMER_ISR interrupt state to pending. */
+#define SCSI_CMD_TIMER_ISR_INTC_SET_PD ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the SCSI_CMD_TIMER_ISR interrupt. */
+#define SCSI_CMD_TIMER_ISR_INTC_CLR_PD ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_SCSI_CMD_TIMER_ISR_H */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_CMD_TIMER_PM.c
+* Version 2.50
+*
+* Description:
+* This file provides the power management source code to API for the
+* Timer.
+*
+* Note:
+* None
+*
+*******************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+
+#include "SCSI_CMD_TIMER.h"
+static SCSI_CMD_TIMER_backupStruct SCSI_CMD_TIMER_backup;
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_SaveConfig
+********************************************************************************
+*
+* Summary:
+* Save the current user configuration
+*
+* Parameters:
+* void
+*
+* Return:
+* void
+*
+* Global variables:
+* SCSI_CMD_TIMER_backup: Variables of this global structure are modified to
+* store the values of non retention configuration registers when Sleep() API is
+* called.
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_SaveConfig(void)
+{
+ #if (!SCSI_CMD_TIMER_UsingFixedFunction)
+ /* Backup the UDB non-rentention registers for CY_UDB_V0 */
+ #if (CY_UDB_V0)
+ SCSI_CMD_TIMER_backup.TimerUdb = SCSI_CMD_TIMER_ReadCounter();
+ SCSI_CMD_TIMER_backup.TimerPeriod = SCSI_CMD_TIMER_ReadPeriod();
+ SCSI_CMD_TIMER_backup.InterruptMaskValue = SCSI_CMD_TIMER_STATUS_MASK;
+ #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
+ SCSI_CMD_TIMER_backup.TimerCaptureCounter = SCSI_CMD_TIMER_ReadCaptureCount();
+ #endif /* Backup the UDB non-rentention register capture counter for CY_UDB_V0 */
+ #endif /* Backup the UDB non-rentention registers for CY_UDB_V0 */
+
+ #if (CY_UDB_V1)
+ SCSI_CMD_TIMER_backup.TimerUdb = SCSI_CMD_TIMER_ReadCounter();
+ SCSI_CMD_TIMER_backup.InterruptMaskValue = SCSI_CMD_TIMER_STATUS_MASK;
+ #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
+ SCSI_CMD_TIMER_backup.TimerCaptureCounter = SCSI_CMD_TIMER_ReadCaptureCount();
+ #endif /* Back Up capture counter register */
+ #endif /* Backup non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
+
+ #if(!SCSI_CMD_TIMER_ControlRegRemoved)
+ SCSI_CMD_TIMER_backup.TimerControlRegister = SCSI_CMD_TIMER_ReadControlRegister();
+ #endif /* Backup the enable state of the Timer component */
+ #endif /* Backup non retention registers in UDB implementation. All fixed function registers are retention */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_RestoreConfig
+********************************************************************************
+*
+* Summary:
+* Restores the current user configuration.
+*
+* Parameters:
+* void
+*
+* Return:
+* void
+*
+* Global variables:
+* SCSI_CMD_TIMER_backup: Variables of this global structure are used to
+* restore the values of non retention registers on wakeup from sleep mode.
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_RestoreConfig(void)
+{
+ #if (!SCSI_CMD_TIMER_UsingFixedFunction)
+ /* Restore the UDB non-rentention registers for CY_UDB_V0 */
+ #if (CY_UDB_V0)
+ /* Interrupt State Backup for Critical Region*/
+ uint8 SCSI_CMD_TIMER_interruptState;
+
+ SCSI_CMD_TIMER_WriteCounter(SCSI_CMD_TIMER_backup.TimerUdb);
+ SCSI_CMD_TIMER_WritePeriod(SCSI_CMD_TIMER_backup.TimerPeriod);
+ /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
+ /* Enter Critical Region*/
+ SCSI_CMD_TIMER_interruptState = CyEnterCriticalSection();
+ /* Use the interrupt output of the status register for IRQ output */
+ SCSI_CMD_TIMER_STATUS_AUX_CTRL |= SCSI_CMD_TIMER_STATUS_ACTL_INT_EN_MASK;
+ /* Exit Critical Region*/
+ CyExitCriticalSection(SCSI_CMD_TIMER_interruptState);
+ SCSI_CMD_TIMER_STATUS_MASK =SCSI_CMD_TIMER_backup.InterruptMaskValue;
+ #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
+ SCSI_CMD_TIMER_SetCaptureCount(SCSI_CMD_TIMER_backup.TimerCaptureCounter);
+ #endif /* Restore the UDB non-rentention register capture counter for CY_UDB_V0 */
+ #endif /* Restore the UDB non-rentention registers for CY_UDB_V0 */
+
+ #if (CY_UDB_V1)
+ SCSI_CMD_TIMER_WriteCounter(SCSI_CMD_TIMER_backup.TimerUdb);
+ SCSI_CMD_TIMER_STATUS_MASK =SCSI_CMD_TIMER_backup.InterruptMaskValue;
+ #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
+ SCSI_CMD_TIMER_SetCaptureCount(SCSI_CMD_TIMER_backup.TimerCaptureCounter);
+ #endif /* Restore Capture counter register*/
+ #endif /* Restore up non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
+
+ #if(!SCSI_CMD_TIMER_ControlRegRemoved)
+ SCSI_CMD_TIMER_WriteControlRegister(SCSI_CMD_TIMER_backup.TimerControlRegister);
+ #endif /* Restore the enable state of the Timer component */
+ #endif /* Restore non retention registers in the UDB implementation only */
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_Sleep
+********************************************************************************
+*
+* Summary:
+* Stop and Save the user configuration
+*
+* Parameters:
+* void
+*
+* Return:
+* void
+*
+* Global variables:
+* SCSI_CMD_TIMER_backup.TimerEnableState: Is modified depending on the
+* enable state of the block before entering sleep mode.
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_Sleep(void)
+{
+ #if(!SCSI_CMD_TIMER_ControlRegRemoved)
+ /* Save Counter's enable state */
+ if(SCSI_CMD_TIMER_CTRL_ENABLE == (SCSI_CMD_TIMER_CONTROL & SCSI_CMD_TIMER_CTRL_ENABLE))
+ {
+ /* Timer is enabled */
+ SCSI_CMD_TIMER_backup.TimerEnableState = 1u;
+ }
+ else
+ {
+ /* Timer is disabled */
+ SCSI_CMD_TIMER_backup.TimerEnableState = 0u;
+ }
+ #endif /* Back up enable state from the Timer control register */
+ SCSI_CMD_TIMER_Stop();
+ SCSI_CMD_TIMER_SaveConfig();
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CMD_TIMER_Wakeup
+********************************************************************************
+*
+* Summary:
+* Restores and enables the user configuration
+*
+* Parameters:
+* void
+*
+* Return:
+* void
+*
+* Global variables:
+* SCSI_CMD_TIMER_backup.enableState: Is used to restore the enable state of
+* block on wakeup from sleep mode.
+*
+*******************************************************************************/
+void SCSI_CMD_TIMER_Wakeup(void)
+{
+ SCSI_CMD_TIMER_RestoreConfig();
+ #if(!SCSI_CMD_TIMER_ControlRegRemoved)
+ if(SCSI_CMD_TIMER_backup.TimerEnableState == 1u)
+ { /* Enable Timer's operation */
+ SCSI_CMD_TIMER_Enable();
+ } /* Do nothing if Timer was disabled before */
+ #endif /* Remove this code section if Control register is removed */
+}
+
+
+/* [] END OF FILE */
#include <cydevice.h>\r
#include <cydevice_trm.h>\r
\r
+/* SCSI_CMD_TIMER_TimerHW */\r
+#define SCSI_CMD_TIMER_TimerHW__CAP0 CYREG_TMR0_CAP0\r
+#define SCSI_CMD_TIMER_TimerHW__CAP1 CYREG_TMR0_CAP1\r
+#define SCSI_CMD_TIMER_TimerHW__CFG0 CYREG_TMR0_CFG0\r
+#define SCSI_CMD_TIMER_TimerHW__CFG1 CYREG_TMR0_CFG1\r
+#define SCSI_CMD_TIMER_TimerHW__CFG2 CYREG_TMR0_CFG2\r
+#define SCSI_CMD_TIMER_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0\r
+#define SCSI_CMD_TIMER_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1\r
+#define SCSI_CMD_TIMER_TimerHW__PER0 CYREG_TMR0_PER0\r
+#define SCSI_CMD_TIMER_TimerHW__PER1 CYREG_TMR0_PER1\r
+#define SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3\r
+#define SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK 0x01u\r
+#define SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3\r
+#define SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK 0x01u\r
+#define SCSI_CMD_TIMER_TimerHW__RT0 CYREG_TMR0_RT0\r
+#define SCSI_CMD_TIMER_TimerHW__RT1 CYREG_TMR0_RT1\r
+#define SCSI_CMD_TIMER_TimerHW__SR0 CYREG_TMR0_SR0\r
+\r
+/* SCSI_CMD_TIMER_ISR */\r
+#define SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_CMD_TIMER_ISR__INTC_MASK 0x01u\r
+#define SCSI_CMD_TIMER_ISR__INTC_NUMBER 0u\r
+#define SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM 7u\r
+#define SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
+#define SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
/* USBFS_bus_reset */\r
#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK\r
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB05_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB05_ST\r
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0\r
/* SCSI_CTL_IO */\r
#define SCSI_CTL_IO_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_IO_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL\r
#define SCSI_CTL_IO_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
-#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
\r
/* SCSI_In_DBx */\r
#define SCSI_In_DBx__0__AG CYREG_PRT12_AG\r
/* scsiTarget */\r
#define scsiTarget_StatusReg__0__MASK 0x01u\r
#define scsiTarget_StatusReg__0__POS 0\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__3__MASK 0x08u\r
#define scsiTarget_StatusReg__3__POS 3\r
#define scsiTarget_StatusReg__MASK 0x0Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB14_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB14_ST\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST\r
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB13_MSK\r
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB13_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB13_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB13_ST\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL\r
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK\r
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK\r
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB13_CTL\r
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL\r
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB13_CTL\r
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL\r
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB13_MSK\r
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB13_14_A0\r
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB13_14_A1\r
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB13_14_D0\r
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB13_14_D1\r
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB13_14_F0\r
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB13_14_F1\r
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB13_A0_A1\r
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB13_A0\r
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB13_A1\r
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB13_D0_D1\r
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB13_D0\r
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB13_D1\r
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB13_F0_F1\r
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB13_F0\r
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB13_F1\r
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK\r
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK\r
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB03_ST\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB03_CTL\r
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB03_CTL\r
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB03_MSK\r
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB03_04_A0\r
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB03_04_A1\r
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB03_04_D0\r
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB03_04_D1\r
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB03_04_F0\r
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB03_04_F1\r
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB03_A0_A1\r
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB03_A0\r
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB03_A1\r
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB03_D0_D1\r
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB03_D0\r
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB03_D1\r
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB03_F0_F1\r
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB03_F0\r
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB03_F1\r
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
\r
/* SD_Clk_Ctl */\r
#define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
/* USBFS_ep_1 */\r
#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_1__INTC_MASK 0x01u\r
-#define USBFS_ep_1__INTC_NUMBER 0u\r
+#define USBFS_ep_1__INTC_MASK 0x02u\r
+#define USBFS_ep_1__INTC_NUMBER 1u\r
#define USBFS_ep_1__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_2 */\r
#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_2__INTC_MASK 0x02u\r
-#define USBFS_ep_2__INTC_NUMBER 1u\r
+#define USBFS_ep_2__INTC_MASK 0x04u\r
+#define USBFS_ep_2__INTC_NUMBER 2u\r
#define USBFS_ep_2__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
#define CYDEV_ECC_ENABLE 0\r
#define CYDEV_HEAP_SIZE 0x1000\r
#define CYDEV_INSTRUCT_CACHE_ENABLED 1\r
-#define CYDEV_INTR_RISING 0x00000000u\r
+#define CYDEV_INTR_RISING 0x00000001u\r
#define CYDEV_PROJ_TYPE 2\r
#define CYDEV_PROJ_TYPE_BOOTLOADER 1\r
#define CYDEV_PROJ_TYPE_LOADABLE 2\r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 33u\r
+#define CY_CFG_BASE_ADDR_COUNT 35u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
{\r
static const uint32 CYCODE cy_cfg_addr_table[] = {\r
0x40004502u, /* Base address: 0x40004500 Count: 2 */\r
+ 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
0x4000520Au, /* Base address: 0x40005200 Count: 10 */\r
0x40006402u, /* Base address: 0x40006400 Count: 2 */\r
- 0x40010101u, /* Base address: 0x40010100 Count: 1 */\r
- 0x40010308u, /* Base address: 0x40010300 Count: 8 */\r
- 0x40010442u, /* Base address: 0x40010400 Count: 66 */\r
- 0x4001053Cu, /* Base address: 0x40010500 Count: 60 */\r
- 0x40010604u, /* Base address: 0x40010600 Count: 4 */\r
- 0x40010747u, /* Base address: 0x40010700 Count: 71 */\r
- 0x40010908u, /* Base address: 0x40010900 Count: 8 */\r
- 0x40010A44u, /* Base address: 0x40010A00 Count: 68 */\r
- 0x40010B40u, /* Base address: 0x40010B00 Count: 64 */\r
- 0x40010C35u, /* Base address: 0x40010C00 Count: 53 */\r
- 0x40010D49u, /* Base address: 0x40010D00 Count: 73 */\r
- 0x40010E43u, /* Base address: 0x40010E00 Count: 67 */\r
- 0x40010F2Fu, /* Base address: 0x40010F00 Count: 47 */\r
+ 0x40010046u, /* Base address: 0x40010000 Count: 70 */\r
+ 0x40010136u, /* Base address: 0x40010100 Count: 54 */\r
+ 0x4001023Eu, /* Base address: 0x40010200 Count: 62 */\r
+ 0x4001035Bu, /* Base address: 0x40010300 Count: 91 */\r
+ 0x40010447u, /* Base address: 0x40010400 Count: 71 */\r
+ 0x40010546u, /* Base address: 0x40010500 Count: 70 */\r
+ 0x4001060Bu, /* Base address: 0x40010600 Count: 11 */\r
+ 0x4001074Au, /* Base address: 0x40010700 Count: 74 */\r
+ 0x40010906u, /* Base address: 0x40010900 Count: 6 */\r
+ 0x40010A04u, /* Base address: 0x40010A00 Count: 4 */\r
+ 0x40010B10u, /* Base address: 0x40010B00 Count: 16 */\r
+ 0x40010C36u, /* Base address: 0x40010C00 Count: 54 */\r
+ 0x40010D36u, /* Base address: 0x40010D00 Count: 54 */\r
+ 0x40010F04u, /* Base address: 0x40010F00 Count: 4 */\r
0x40011504u, /* Base address: 0x40011500 Count: 4 */\r
- 0x40011648u, /* Base address: 0x40011600 Count: 72 */\r
- 0x40011740u, /* Base address: 0x40011700 Count: 64 */\r
- 0x40011904u, /* Base address: 0x40011900 Count: 4 */\r
- 0x4001400Bu, /* Base address: 0x40014000 Count: 11 */\r
- 0x4001410Fu, /* Base address: 0x40014100 Count: 15 */\r
- 0x40014207u, /* Base address: 0x40014200 Count: 7 */\r
- 0x40014303u, /* Base address: 0x40014300 Count: 3 */\r
- 0x4001440Cu, /* Base address: 0x40014400 Count: 12 */\r
- 0x40014516u, /* Base address: 0x40014500 Count: 22 */\r
- 0x40014608u, /* Base address: 0x40014600 Count: 8 */\r
- 0x40014708u, /* Base address: 0x40014700 Count: 8 */\r
- 0x4001480Au, /* Base address: 0x40014800 Count: 10 */\r
- 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */\r
- 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */\r
+ 0x4001164Bu, /* Base address: 0x40011600 Count: 75 */\r
+ 0x40011749u, /* Base address: 0x40011700 Count: 73 */\r
+ 0x40011902u, /* Base address: 0x40011900 Count: 2 */\r
+ 0x4001400Du, /* Base address: 0x40014000 Count: 13 */\r
+ 0x4001410Eu, /* Base address: 0x40014100 Count: 14 */\r
+ 0x4001420Cu, /* Base address: 0x40014200 Count: 12 */\r
+ 0x4001430Du, /* Base address: 0x40014300 Count: 13 */\r
+ 0x40014410u, /* Base address: 0x40014400 Count: 16 */\r
+ 0x40014515u, /* Base address: 0x40014500 Count: 21 */\r
+ 0x40014603u, /* Base address: 0x40014600 Count: 3 */\r
+ 0x40014703u, /* Base address: 0x40014700 Count: 3 */\r
+ 0x4001480Eu, /* Base address: 0x40014800 Count: 14 */\r
+ 0x4001490Au, /* Base address: 0x40014900 Count: 10 */\r
+ 0x40014C02u, /* Base address: 0x40014C00 Count: 2 */\r
0x40015006u, /* Base address: 0x40015000 Count: 6 */\r
0x40015101u, /* Base address: 0x40015100 Count: 1 */\r
};\r
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
{0x36u, 0x02u},\r
{0x7Eu, 0x02u},\r
- {0x00u, 0x01u},\r
+ {0x01u, 0x80u},\r
+ {0x0Au, 0x4Bu},\r
+ {0x00u, 0x02u},\r
{0x01u, 0x03u},\r
- {0x18u, 0x04u},\r
+ {0x18u, 0x08u},\r
{0x19u, 0x0Cu},\r
{0x1Cu, 0x61u},\r
- {0x20u, 0x98u},\r
- {0x21u, 0x38u},\r
- {0x30u, 0x03u},\r
- {0x31u, 0x05u},\r
+ {0x20u, 0xC0u},\r
+ {0x21u, 0x90u},\r
+ {0x30u, 0x0Au},\r
+ {0x31u, 0x09u},\r
{0x7Cu, 0x40u},\r
- {0x3Du, 0x03u},\r
+ {0x33u, 0x03u},\r
{0x86u, 0x0Fu},\r
- {0xE2u, 0x80u},\r
- {0x81u, 0x40u},\r
- {0x85u, 0x04u},\r
- {0xA0u, 0x04u},\r
- {0xACu, 0x04u},\r
- {0xE2u, 0x08u},\r
- {0xE6u, 0x25u},\r
- {0xEAu, 0x01u},\r
- {0xEEu, 0x02u},\r
- {0x07u, 0x04u},\r
- {0x0Bu, 0x04u},\r
- {0x0Du, 0x04u},\r
- {0x0Fu, 0x02u},\r
+ {0x03u, 0x04u},\r
+ {0x06u, 0x10u},\r
+ {0x07u, 0x44u},\r
+ {0x0Bu, 0x40u},\r
+ {0x0Du, 0x44u},\r
+ {0x0Eu, 0x0Cu},\r
+ {0x0Fu, 0x22u},\r
+ {0x12u, 0x01u},\r
{0x13u, 0x03u},\r
- {0x19u, 0x04u},\r
- {0x1Bu, 0x01u},\r
+ {0x16u, 0x10u},\r
+ {0x18u, 0x10u},\r
+ {0x1Au, 0x04u},\r
+ {0x1Cu, 0x01u},\r
+ {0x1Eu, 0x02u},\r
+ {0x1Fu, 0x30u},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0x02u},\r
+ {0x24u, 0x20u},\r
+ {0x29u, 0x44u},\r
+ {0x2Bu, 0x11u},\r
+ {0x2Cu, 0x10u},\r
+ {0x2Eu, 0x08u},\r
+ {0x30u, 0x1Cu},\r
{0x31u, 0x07u},\r
- {0x56u, 0x08u},\r
- {0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Cu, 0x90u},\r
- {0x5Du, 0x90u},\r
- {0x5Fu, 0x01u},\r
- {0x80u, 0xD6u},\r
- {0x81u, 0x2Cu},\r
- {0x84u, 0x17u},\r
- {0x86u, 0x28u},\r
- {0x88u, 0xD2u},\r
- {0x89u, 0x31u},\r
- {0x8Au, 0x04u},\r
- {0x8Bu, 0x42u},\r
- {0x8Cu, 0xD6u},\r
- {0x8Du, 0x2Cu},\r
- {0x91u, 0xC0u},\r
- {0x94u, 0x29u},\r
- {0x96u, 0x46u},\r
- {0x97u, 0x2Cu},\r
- {0x98u, 0x20u},\r
- {0x99u, 0x40u},\r
- {0x9Au, 0xD0u},\r
- {0x9Bu, 0x2Fu},\r
- {0x9Cu, 0x04u},\r
- {0x9Du, 0x24u},\r
- {0xA0u, 0xD6u},\r
- {0xA1u, 0x08u},\r
- {0xA3u, 0x10u},\r
- {0xA4u, 0xD0u},\r
- {0xA5u, 0x24u},\r
- {0xA6u, 0x06u},\r
- {0xA7u, 0x08u},\r
- {0xA8u, 0x21u},\r
- {0xA9u, 0x11u},\r
- {0xAAu, 0x8Eu},\r
- {0xABu, 0x8Eu},\r
- {0xACu, 0x02u},\r
- {0xADu, 0x2Cu},\r
- {0xB0u, 0x01u},\r
- {0xB1u, 0xC1u},\r
- {0xB2u, 0x0Fu},\r
- {0xB3u, 0x31u},\r
- {0xB4u, 0xF0u},\r
- {0xB5u, 0x0Fu},\r
- {0xB6u, 0x08u},\r
- {0xB8u, 0x08u},\r
- {0xB9u, 0x02u},\r
- {0xBAu, 0x20u},\r
- {0xBBu, 0x0Cu},\r
- {0xBEu, 0x41u},\r
- {0xD4u, 0x09u},\r
- {0xD8u, 0x0Bu},\r
- {0xD9u, 0x0Bu},\r
- {0xDBu, 0x0Bu},\r
- {0xDCu, 0x99u},\r
- {0xDDu, 0x90u},\r
- {0xDFu, 0x01u},\r
- {0x04u, 0x29u},\r
- {0x06u, 0x02u},\r
- {0x0Eu, 0x28u},\r
- {0x0Fu, 0x02u},\r
- {0x17u, 0x65u},\r
- {0x1Cu, 0x10u},\r
- {0x1Du, 0x48u},\r
- {0x1Eu, 0x28u},\r
- {0x1Fu, 0x09u},\r
- {0x21u, 0x02u},\r
- {0x23u, 0x40u},\r
- {0x24u, 0x08u},\r
- {0x25u, 0x10u},\r
- {0x26u, 0x02u},\r
- {0x27u, 0x38u},\r
- {0x29u, 0xC0u},\r
- {0x2Du, 0x02u},\r
- {0x2Fu, 0x2Au},\r
- {0x31u, 0x02u},\r
- {0x32u, 0x10u},\r
- {0x34u, 0x01u},\r
- {0x36u, 0x02u},\r
- {0x37u, 0x54u},\r
- {0x39u, 0x48u},\r
- {0x3Au, 0x10u},\r
- {0x3Cu, 0x81u},\r
- {0x3Du, 0x20u},\r
- {0x3Eu, 0x01u},\r
- {0x58u, 0x80u},\r
- {0x5Du, 0x98u},\r
- {0x5Eu, 0x02u},\r
- {0x60u, 0x02u},\r
- {0x62u, 0x80u},\r
- {0x65u, 0x08u},\r
- {0x66u, 0x04u},\r
- {0x67u, 0x02u},\r
- {0x7Eu, 0x80u},\r
- {0x89u, 0x02u},\r
- {0x8Cu, 0x20u},\r
- {0x91u, 0x48u},\r
- {0x92u, 0x20u},\r
- {0x9Au, 0x10u},\r
- {0xA0u, 0x04u},\r
- {0xA4u, 0x10u},\r
- {0xAEu, 0x10u},\r
- {0xB0u, 0x10u},\r
- {0xB6u, 0x10u},\r
- {0xC0u, 0xF0u},\r
- {0xC2u, 0xE0u},\r
- {0xC4u, 0xF0u},\r
- {0xCAu, 0xF0u},\r
- {0xCCu, 0xF5u},\r
- {0xCEu, 0xBEu},\r
- {0xD6u, 0xF8u},\r
- {0xD8u, 0x18u},\r
- {0xDEu, 0x80u},\r
- {0xE2u, 0x40u},\r
- {0xE6u, 0x20u},\r
- {0xEAu, 0x02u},\r
- {0xEEu, 0x08u},\r
- {0xD4u, 0x40u},\r
- {0xDBu, 0x0Bu},\r
- {0xDDu, 0x90u},\r
- {0xDFu, 0x01u},\r
- {0x04u, 0x20u},\r
- {0x06u, 0x02u},\r
- {0x07u, 0x60u},\r
- {0x0Eu, 0xA1u},\r
- {0x0Fu, 0x04u},\r
- {0x15u, 0x14u},\r
- {0x17u, 0x09u},\r
- {0x1Fu, 0x08u},\r
- {0x25u, 0x40u},\r
- {0x26u, 0x40u},\r
- {0x27u, 0x80u},\r
- {0x2Cu, 0x80u},\r
- {0x2Fu, 0x2Au},\r
- {0x36u, 0x02u},\r
- {0x37u, 0xA8u},\r
- {0x3Cu, 0x10u},\r
- {0x3Du, 0x80u},\r
- {0x3Eu, 0x01u},\r
+ {0x32u, 0x03u},\r
+ {0x33u, 0x08u},\r
+ {0x36u, 0x20u},\r
+ {0x37u, 0x70u},\r
+ {0x3Eu, 0x44u},\r
{0x3Fu, 0x04u},\r
- {0x45u, 0x88u},\r
- {0x46u, 0x40u},\r
- {0x47u, 0x20u},\r
- {0x4Cu, 0x04u},\r
- {0x4Du, 0x0Au},\r
- {0x4Fu, 0x06u},\r
- {0x55u, 0x20u},\r
- {0x56u, 0x84u},\r
- {0x61u, 0x20u},\r
- {0x62u, 0x08u},\r
- {0x63u, 0x01u},\r
- {0x65u, 0x80u},\r
- {0x6Cu, 0x10u},\r
- {0x6Du, 0x11u},\r
- {0x6Eu, 0x09u},\r
- {0x6Fu, 0x27u},\r
- {0x74u, 0xC0u},\r
- {0x76u, 0x02u},\r
- {0x78u, 0x02u},\r
- {0x7Eu, 0x80u},\r
- {0x81u, 0x48u},\r
- {0x90u, 0x18u},\r
- {0x92u, 0x80u},\r
- {0x93u, 0x40u},\r
- {0x94u, 0x20u},\r
- {0x96u, 0x01u},\r
- {0x98u, 0x23u},\r
- {0x9Bu, 0x38u},\r
- {0x9Du, 0x02u},\r
- {0x9Eu, 0x06u},\r
- {0x9Fu, 0x45u},\r
- {0xA0u, 0x04u},\r
- {0xA1u, 0x08u},\r
- {0xA2u, 0x90u},\r
- {0xA4u, 0x50u},\r
- {0xA6u, 0x01u},\r
- {0xA7u, 0x23u},\r
- {0xAAu, 0x40u},\r
- {0xACu, 0x80u},\r
- {0xB1u, 0x12u},\r
- {0xC0u, 0xF0u},\r
- {0xC2u, 0xF0u},\r
- {0xC4u, 0x70u},\r
- {0xCAu, 0xF0u},\r
- {0xCCu, 0xF0u},\r
- {0xCEu, 0xF0u},\r
- {0xD0u, 0xF0u},\r
- {0xD2u, 0x20u},\r
- {0xD8u, 0x1Eu},\r
- {0xDEu, 0x81u},\r
- {0xE8u, 0x40u},\r
- {0xEEu, 0x03u},\r
- {0x9Cu, 0x04u},\r
- {0xA7u, 0x40u},\r
- {0xAEu, 0x11u},\r
- {0xB0u, 0x80u},\r
- {0xB6u, 0x10u},\r
- {0xE8u, 0x40u},\r
- {0xEAu, 0x02u},\r
- {0xEEu, 0x01u},\r
- {0x04u, 0x24u},\r
- {0x06u, 0x12u},\r
- {0x07u, 0x03u},\r
- {0x0Au, 0x24u},\r
- {0x0Bu, 0x04u},\r
- {0x0Eu, 0x03u},\r
- {0x10u, 0x40u},\r
- {0x12u, 0x80u},\r
- {0x13u, 0x20u},\r
- {0x16u, 0x80u},\r
- {0x1Au, 0x18u},\r
- {0x1Bu, 0x24u},\r
- {0x1Fu, 0x18u},\r
- {0x21u, 0x40u},\r
- {0x22u, 0x20u},\r
- {0x25u, 0x24u},\r
- {0x26u, 0x04u},\r
- {0x27u, 0x12u},\r
- {0x29u, 0x80u},\r
- {0x2Au, 0x40u},\r
- {0x2Cu, 0x24u},\r
- {0x2Du, 0x24u},\r
- {0x2Eu, 0x09u},\r
- {0x2Fu, 0x09u},\r
- {0x30u, 0x07u},\r
- {0x31u, 0x80u},\r
- {0x33u, 0x40u},\r
- {0x34u, 0x38u},\r
- {0x35u, 0x07u},\r
- {0x36u, 0xC0u},\r
- {0x37u, 0x38u},\r
- {0x3Eu, 0x40u},\r
- {0x3Fu, 0x05u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
{0x5Cu, 0x99u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x85u, 0x33u},\r
- {0x86u, 0xFFu},\r
- {0x87u, 0xCCu},\r
- {0x89u, 0xFFu},\r
- {0x8Du, 0x0Fu},\r
- {0x8Eu, 0xFFu},\r
- {0x8Fu, 0xF0u},\r
- {0x90u, 0x96u},\r
- {0x92u, 0x69u},\r
+ {0x81u, 0x33u},\r
+ {0x82u, 0x02u},\r
+ {0x83u, 0xCCu},\r
+ {0x85u, 0x55u},\r
+ {0x86u, 0x20u},\r
+ {0x87u, 0xAAu},\r
+ {0x88u, 0x20u},\r
+ {0x89u, 0x96u},\r
+ {0x8Au, 0x08u},\r
+ {0x8Bu, 0x69u},\r
+ {0x8Fu, 0xFFu},\r
+ {0x90u, 0x20u},\r
+ {0x92u, 0x10u},\r
{0x93u, 0xFFu},\r
- {0x94u, 0xFFu},\r
- {0x98u, 0x33u},\r
- {0x9Au, 0xCCu},\r
- {0x9Du, 0x96u},\r
- {0x9Fu, 0x69u},\r
- {0xA0u, 0x55u},\r
- {0xA1u, 0x55u},\r
- {0xA2u, 0xAAu},\r
- {0xA3u, 0xAAu},\r
- {0xA7u, 0xFFu},\r
- {0xACu, 0x0Fu},\r
- {0xAEu, 0xF0u},\r
- {0xB2u, 0xFFu},\r
- {0xB3u, 0xFFu},\r
+ {0x95u, 0xFFu},\r
+ {0x96u, 0x20u},\r
+ {0x9Au, 0x18u},\r
+ {0x9Eu, 0x07u},\r
+ {0xA0u, 0x07u},\r
+ {0xA4u, 0x01u},\r
+ {0xA5u, 0x0Fu},\r
+ {0xA7u, 0xF0u},\r
+ {0xA8u, 0x04u},\r
+ {0xB2u, 0x07u},\r
+ {0xB4u, 0x38u},\r
+ {0xB7u, 0xFFu},\r
{0xBEu, 0x04u},\r
- {0xBFu, 0x04u},\r
+ {0xBFu, 0x40u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDCu, 0x09u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x50u},\r
- {0x03u, 0x20u},\r
- {0x05u, 0x04u},\r
- {0x06u, 0x20u},\r
- {0x07u, 0x01u},\r
- {0x0Au, 0x64u},\r
- {0x0Eu, 0x80u},\r
- {0x0Fu, 0xA4u},\r
- {0x10u, 0xA5u},\r
- {0x13u, 0x40u},\r
- {0x14u, 0x40u},\r
- {0x15u, 0x40u},\r
+ {0x00u, 0x40u},\r
+ {0x03u, 0x10u},\r
+ {0x05u, 0x10u},\r
+ {0x06u, 0x80u},\r
+ {0x07u, 0x20u},\r
+ {0x09u, 0x08u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Bu, 0x82u},\r
+ {0x0Du, 0x24u},\r
+ {0x0Eu, 0x01u},\r
+ {0x0Fu, 0x40u},\r
+ {0x10u, 0x40u},\r
+ {0x13u, 0x48u},\r
+ {0x14u, 0x90u},\r
+ {0x16u, 0x04u},\r
{0x18u, 0x40u},\r
- {0x1Au, 0x06u},\r
- {0x1Bu, 0x10u},\r
- {0x1Fu, 0x04u},\r
- {0x22u, 0x46u},\r
- {0x23u, 0x04u},\r
- {0x25u, 0x08u},\r
- {0x28u, 0x81u},\r
- {0x2Au, 0x10u},\r
- {0x2Bu, 0x20u},\r
- {0x2Cu, 0x40u},\r
- {0x2Eu, 0x04u},\r
- {0x30u, 0x42u},\r
- {0x31u, 0x20u},\r
- {0x32u, 0x40u},\r
- {0x36u, 0x40u},\r
- {0x37u, 0x01u},\r
- {0x39u, 0x10u},\r
- {0x3Bu, 0x04u},\r
- {0x3Du, 0x40u},\r
- {0x3Eu, 0x20u},\r
- {0x3Fu, 0x04u},\r
- {0x6Au, 0x40u},\r
- {0x6Fu, 0x01u},\r
- {0x8Cu, 0x40u},\r
- {0x90u, 0x10u},\r
- {0x91u, 0x50u},\r
- {0x93u, 0x40u},\r
- {0x96u, 0x08u},\r
- {0x97u, 0x0Cu},\r
- {0x99u, 0x04u},\r
- {0x9Cu, 0x40u},\r
- {0x9Fu, 0x01u},\r
- {0xA0u, 0xA2u},\r
- {0xA1u, 0x20u},\r
- {0xA3u, 0x20u},\r
- {0xA5u, 0x08u},\r
- {0xA6u, 0x02u},\r
- {0xA7u, 0x50u},\r
- {0xADu, 0x50u},\r
- {0xB2u, 0xC0u},\r
- {0xB3u, 0x08u},\r
- {0xB4u, 0x42u},\r
- {0xC0u, 0xA7u},\r
- {0xC2u, 0x7Eu},\r
- {0xC4u, 0x9Fu},\r
- {0xCAu, 0xCFu},\r
- {0xCCu, 0x9Du},\r
- {0xCEu, 0x76u},\r
- {0xE2u, 0x40u},\r
- {0xEAu, 0x40u},\r
- {0xECu, 0x80u},\r
- {0x80u, 0x10u},\r
- {0x84u, 0x0Eu},\r
+ {0x19u, 0x84u},\r
+ {0x1Du, 0x20u},\r
+ {0x1Fu, 0x14u},\r
+ {0x20u, 0x02u},\r
+ {0x21u, 0xC0u},\r
+ {0x22u, 0x03u},\r
+ {0x23u, 0x10u},\r
+ {0x25u, 0x40u},\r
+ {0x29u, 0x10u},\r
+ {0x2Au, 0x01u},\r
+ {0x2Fu, 0x20u},\r
+ {0x31u, 0x80u},\r
+ {0x32u, 0x01u},\r
+ {0x36u, 0x06u},\r
+ {0x39u, 0x18u},\r
+ {0x3Au, 0x02u},\r
+ {0x3Bu, 0x40u},\r
+ {0x3Cu, 0x02u},\r
+ {0x3Du, 0x60u},\r
+ {0x3Fu, 0x0Cu},\r
+ {0x5Bu, 0x40u},\r
+ {0x60u, 0x02u},\r
+ {0x6Du, 0x40u},\r
+ {0x80u, 0x40u},\r
+ {0x81u, 0x80u},\r
+ {0x83u, 0x20u},\r
+ {0x86u, 0x01u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Eu, 0x01u},\r
+ {0xC0u, 0x75u},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0x7Du},\r
+ {0xCAu, 0x45u},\r
+ {0xCCu, 0xC9u},\r
+ {0xCEu, 0xFFu},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x08u},\r
+ {0xE4u, 0x05u},\r
+ {0x01u, 0x03u},\r
+ {0x03u, 0x0Cu},\r
+ {0x25u, 0x05u},\r
+ {0x27u, 0x0Au},\r
+ {0x29u, 0x06u},\r
+ {0x2Bu, 0x09u},\r
+ {0x35u, 0x0Fu},\r
+ {0x3Fu, 0x10u},\r
+ {0x59u, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x85u, 0x10u},\r
+ {0x87u, 0x2Du},\r
{0x89u, 0x01u},\r
- {0x8Au, 0x0Eu},\r
- {0x8Bu, 0x92u},\r
- {0x8Cu, 0x04u},\r
- {0x8Du, 0x19u},\r
- {0x8Fu, 0xA4u},\r
- {0x90u, 0x0Cu},\r
- {0x91u, 0x08u},\r
- {0x92u, 0x01u},\r
- {0x94u, 0x02u},\r
- {0x96u, 0x04u},\r
- {0x97u, 0x3Fu},\r
- {0x9Au, 0x0Bu},\r
- {0xA4u, 0x04u},\r
- {0xA7u, 0x04u},\r
- {0xA9u, 0x26u},\r
- {0xABu, 0x99u},\r
- {0xADu, 0x40u},\r
- {0xB0u, 0x10u},\r
- {0xB1u, 0x38u},\r
- {0xB3u, 0x40u},\r
- {0xB4u, 0x0Eu},\r
- {0xB5u, 0x07u},\r
- {0xB6u, 0x01u},\r
- {0xB7u, 0x80u},\r
+ {0x8Bu, 0x02u},\r
+ {0x8Cu, 0x01u},\r
+ {0x8Du, 0x67u},\r
+ {0x8Fu, 0x18u},\r
+ {0x90u, 0x04u},\r
+ {0x92u, 0x03u},\r
+ {0x96u, 0x12u},\r
+ {0x98u, 0x03u},\r
+ {0x9Au, 0x14u},\r
+ {0x9Fu, 0x40u},\r
+ {0xA1u, 0x02u},\r
+ {0xA4u, 0x08u},\r
+ {0xA5u, 0x02u},\r
+ {0xA9u, 0x16u},\r
+ {0xAAu, 0x07u},\r
+ {0xABu, 0x48u},\r
+ {0xAFu, 0x77u},\r
+ {0xB0u, 0x08u},\r
+ {0xB1u, 0x07u},\r
+ {0xB3u, 0x70u},\r
+ {0xB4u, 0x07u},\r
+ {0xB5u, 0x08u},\r
+ {0xB6u, 0x10u},\r
{0xBEu, 0x41u},\r
- {0xBFu, 0x44u},\r
- {0xC0u, 0x26u},\r
- {0xC1u, 0x04u},\r
- {0xC2u, 0x50u},\r
- {0xC5u, 0xD2u},\r
- {0xC6u, 0xCEu},\r
- {0xC7u, 0x0Fu},\r
+ {0xBFu, 0x10u},\r
+ {0xC0u, 0x34u},\r
+ {0xC1u, 0x02u},\r
+ {0xC2u, 0x60u},\r
+ {0xC5u, 0xCDu},\r
+ {0xC6u, 0xF2u},\r
+ {0xC7u, 0x0Eu},\r
{0xC8u, 0x1Fu},\r
{0xC9u, 0xFFu},\r
{0xCAu, 0xFFu},\r
{0xE8u, 0x40u},\r
{0xE9u, 0x40u},\r
{0xEEu, 0x08u},\r
- {0x00u, 0x80u},\r
- {0x02u, 0x80u},\r
- {0x03u, 0x28u},\r
- {0x04u, 0x08u},\r
- {0x07u, 0x10u},\r
- {0x09u, 0x20u},\r
- {0x0Bu, 0x60u},\r
- {0x12u, 0x10u},\r
+ {0x01u, 0x40u},\r
+ {0x03u, 0x01u},\r
+ {0x09u, 0x08u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Bu, 0x40u},\r
+ {0x12u, 0x08u},\r
{0x13u, 0x08u},\r
- {0x19u, 0x52u},\r
- {0x1Bu, 0x20u},\r
- {0x20u, 0x42u},\r
- {0x21u, 0x31u},\r
- {0x22u, 0x08u},\r
+ {0x18u, 0x40u},\r
+ {0x19u, 0x10u},\r
+ {0x1Au, 0x0Cu},\r
+ {0x1Bu, 0x40u},\r
+ {0x20u, 0x28u},\r
+ {0x21u, 0x0Du},\r
{0x23u, 0x40u},\r
- {0x28u, 0x02u},\r
- {0x29u, 0x18u},\r
- {0x33u, 0x09u},\r
- {0x38u, 0x50u},\r
- {0x39u, 0x20u},\r
- {0x40u, 0x40u},\r
- {0x41u, 0x10u},\r
- {0x48u, 0x41u},\r
- {0x49u, 0x19u},\r
- {0x50u, 0x04u},\r
- {0x52u, 0x10u},\r
+ {0x24u, 0x08u},\r
+ {0x25u, 0x10u},\r
+ {0x27u, 0x04u},\r
+ {0x29u, 0x1Au},\r
+ {0x2Bu, 0x02u},\r
+ {0x2Du, 0x20u},\r
+ {0x2Fu, 0x10u},\r
+ {0x33u, 0x80u},\r
+ {0x38u, 0x20u},\r
+ {0x39u, 0x08u},\r
+ {0x3Bu, 0x40u},\r
+ {0x3Fu, 0x01u},\r
+ {0x41u, 0x05u},\r
+ {0x42u, 0x04u},\r
+ {0x48u, 0x84u},\r
+ {0x49u, 0x0Au},\r
+ {0x50u, 0x08u},\r
+ {0x52u, 0x20u},\r
{0x53u, 0x80u},\r
- {0x59u, 0x02u},\r
- {0x5Au, 0xA8u},\r
- {0x60u, 0x04u},\r
- {0x62u, 0x4Au},\r
- {0x68u, 0x82u},\r
- {0x69u, 0x14u},\r
- {0x70u, 0x20u},\r
- {0x72u, 0x80u},\r
- {0x73u, 0x12u},\r
- {0x81u, 0x10u},\r
- {0x84u, 0x01u},\r
- {0x87u, 0x10u},\r
- {0x8Bu, 0x11u},\r
- {0x90u, 0x04u},\r
- {0x91u, 0x40u},\r
- {0x92u, 0xA0u},\r
- {0x95u, 0x26u},\r
- {0x97u, 0x4Cu},\r
- {0x99u, 0x04u},\r
- {0x9Cu, 0x41u},\r
- {0x9Du, 0x11u},\r
- {0x9Eu, 0x80u},\r
- {0x9Fu, 0x1Bu},\r
- {0xA5u, 0x28u},\r
- {0xA7u, 0xF0u},\r
- {0xA8u, 0x40u},\r
- {0xAAu, 0x10u},\r
- {0xACu, 0x40u},\r
- {0xAEu, 0x01u},\r
- {0xAFu, 0x04u},\r
- {0xB2u, 0x02u},\r
- {0xB7u, 0x10u},\r
- {0xC0u, 0x0Fu},\r
+ {0x58u, 0x24u},\r
+ {0x59u, 0x80u},\r
+ {0x5Bu, 0x02u},\r
+ {0x60u, 0x48u},\r
+ {0x61u, 0x80u},\r
+ {0x63u, 0x10u},\r
+ {0x68u, 0x02u},\r
+ {0x69u, 0x10u},\r
+ {0x6Bu, 0x50u},\r
+ {0x71u, 0x01u},\r
+ {0x72u, 0x02u},\r
+ {0x73u, 0x24u},\r
+ {0x80u, 0x06u},\r
+ {0x81u, 0x40u},\r
+ {0x83u, 0x01u},\r
+ {0x85u, 0x09u},\r
+ {0x86u, 0x04u},\r
+ {0x87u, 0x08u},\r
+ {0x89u, 0x04u},\r
+ {0x8Au, 0x01u},\r
+ {0x8Eu, 0x28u},\r
+ {0x8Fu, 0x02u},\r
+ {0x90u, 0x20u},\r
+ {0x91u, 0xC0u},\r
+ {0x92u, 0x02u},\r
+ {0x93u, 0x38u},\r
+ {0x95u, 0x18u},\r
+ {0x96u, 0x05u},\r
+ {0x97u, 0xC0u},\r
+ {0x98u, 0x02u},\r
+ {0x99u, 0x80u},\r
+ {0x9Cu, 0xD0u},\r
+ {0x9Du, 0x10u},\r
+ {0x9Eu, 0x86u},\r
+ {0x9Fu, 0x30u},\r
+ {0xA1u, 0x40u},\r
+ {0xA3u, 0x24u},\r
+ {0xA5u, 0x18u},\r
+ {0xA6u, 0x04u},\r
+ {0xA8u, 0x10u},\r
+ {0xB3u, 0x04u},\r
+ {0xB5u, 0x24u},\r
+ {0xB7u, 0x41u},\r
+ {0xC0u, 0x01u},\r
{0xC2u, 0x0Eu},\r
- {0xC4u, 0x04u},\r
- {0xCAu, 0x0Eu},\r
- {0xCCu, 0x03u},\r
- {0xCEu, 0x0Cu},\r
- {0xD0u, 0x05u},\r
- {0xD2u, 0x0Cu},\r
+ {0xC4u, 0x06u},\r
+ {0xCAu, 0x6Fu},\r
+ {0xCCu, 0x08u},\r
+ {0xCEu, 0x8Eu},\r
+ {0xD0u, 0x07u},\r
+ {0xD2u, 0x04u},\r
{0xD6u, 0x0Fu},\r
{0xD8u, 0x0Fu},\r
- {0xE2u, 0x02u},\r
- {0xE6u, 0x21u},\r
- {0xE8u, 0x02u},\r
- {0xECu, 0x0Cu},\r
- {0x01u, 0x04u},\r
- {0x03u, 0x01u},\r
- {0x04u, 0x24u},\r
- {0x05u, 0x10u},\r
- {0x06u, 0x12u},\r
- {0x0Bu, 0x04u},\r
- {0x0Eu, 0x18u},\r
- {0x0Fu, 0x04u},\r
- {0x10u, 0x40u},\r
+ {0xE0u, 0x06u},\r
+ {0xE2u, 0x08u},\r
+ {0xE4u, 0x0Fu},\r
+ {0xEAu, 0x04u},\r
+ {0xEEu, 0x40u},\r
+ {0x00u, 0x08u},\r
+ {0x05u, 0xFFu},\r
+ {0x06u, 0x03u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Du, 0x33u},\r
+ {0x0Fu, 0xCCu},\r
+ {0x10u, 0x04u},\r
+ {0x12u, 0x02u},\r
+ {0x13u, 0xFFu},\r
+ {0x15u, 0x96u},\r
+ {0x17u, 0x69u},\r
+ {0x18u, 0x04u},\r
+ {0x1Au, 0x01u},\r
+ {0x20u, 0x08u},\r
+ {0x25u, 0x0Fu},\r
+ {0x26u, 0x04u},\r
+ {0x27u, 0xF0u},\r
+ {0x28u, 0x08u},\r
+ {0x29u, 0x55u},\r
+ {0x2Bu, 0xAAu},\r
+ {0x2Cu, 0x08u},\r
+ {0x2Fu, 0xFFu},\r
+ {0x30u, 0x08u},\r
+ {0x33u, 0xFFu},\r
+ {0x34u, 0x07u},\r
+ {0x38u, 0x02u},\r
+ {0x3Eu, 0x01u},\r
+ {0x3Fu, 0x04u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Cu, 0x09u},\r
+ {0x5Fu, 0x01u},\r
+ {0x81u, 0x02u},\r
+ {0x83u, 0x0Du},\r
+ {0x84u, 0x04u},\r
+ {0x86u, 0x03u},\r
+ {0x87u, 0x10u},\r
+ {0x88u, 0x08u},\r
+ {0x89u, 0x02u},\r
+ {0x8Au, 0x03u},\r
+ {0x8Bu, 0x54u},\r
+ {0x8Du, 0x8Du},\r
+ {0x91u, 0x8Du},\r
+ {0x94u, 0x01u},\r
+ {0x95u, 0x62u},\r
+ {0x96u, 0x02u},\r
+ {0x97u, 0x08u},\r
+ {0x99u, 0x01u},\r
+ {0x9Au, 0x01u},\r
+ {0x9Bu, 0x32u},\r
+ {0x9Eu, 0x0Cu},\r
+ {0xA3u, 0x80u},\r
+ {0xA5u, 0x8Du},\r
+ {0xA9u, 0x8Du},\r
+ {0xADu, 0x0Du},\r
+ {0xAEu, 0x12u},\r
+ {0xAFu, 0x80u},\r
+ {0xB1u, 0x0Fu},\r
+ {0xB3u, 0x70u},\r
+ {0xB4u, 0x10u},\r
+ {0xB5u, 0x80u},\r
+ {0xB6u, 0x0Fu},\r
+ {0xBBu, 0x02u},\r
+ {0xBFu, 0x10u},\r
+ {0xD4u, 0x40u},\r
+ {0xD8u, 0x0Bu},\r
+ {0xD9u, 0x0Bu},\r
+ {0xDBu, 0x0Bu},\r
+ {0xDCu, 0x99u},\r
+ {0xDDu, 0x90u},\r
+ {0xDFu, 0x01u},\r
+ {0x00u, 0x24u},\r
+ {0x02u, 0x40u},\r
+ {0x04u, 0x28u},\r
+ {0x06u, 0x04u},\r
+ {0x0Au, 0x08u},\r
+ {0x0Bu, 0x40u},\r
+ {0x0Eu, 0x25u},\r
+ {0x10u, 0x80u},\r
+ {0x11u, 0x80u},\r
+ {0x13u, 0x24u},\r
+ {0x16u, 0x02u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x20u},\r
+ {0x1Au, 0x80u},\r
+ {0x1Eu, 0x05u},\r
+ {0x23u, 0x20u},\r
+ {0x25u, 0x25u},\r
+ {0x2Bu, 0x25u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Du, 0x02u},\r
+ {0x2Eu, 0x10u},\r
+ {0x2Fu, 0x02u},\r
+ {0x33u, 0x05u},\r
+ {0x34u, 0x10u},\r
+ {0x36u, 0x19u},\r
+ {0x39u, 0x84u},\r
+ {0x3Cu, 0x80u},\r
+ {0x3Du, 0x2Au},\r
+ {0x45u, 0x20u},\r
+ {0x46u, 0x08u},\r
+ {0x66u, 0x28u},\r
+ {0x67u, 0x01u},\r
+ {0x7Cu, 0x02u},\r
+ {0x80u, 0x80u},\r
+ {0x8Du, 0x04u},\r
+ {0x91u, 0x8Cu},\r
+ {0x92u, 0x08u},\r
+ {0x93u, 0x4Cu},\r
+ {0x96u, 0x01u},\r
+ {0x97u, 0x80u},\r
+ {0x98u, 0x02u},\r
+ {0x99u, 0x11u},\r
+ {0x9Bu, 0x45u},\r
+ {0x9Cu, 0xD0u},\r
+ {0x9Du, 0x20u},\r
+ {0x9Eu, 0x84u},\r
+ {0xA0u, 0x10u},\r
+ {0xA1u, 0x40u},\r
+ {0xA3u, 0x24u},\r
+ {0xA6u, 0x04u},\r
+ {0xA8u, 0x80u},\r
+ {0xACu, 0x0Cu},\r
+ {0xADu, 0x80u},\r
+ {0xB1u, 0x04u},\r
+ {0xB3u, 0x02u},\r
+ {0xB4u, 0x28u},\r
+ {0xB7u, 0x40u},\r
+ {0xC0u, 0x6Eu},\r
+ {0xC2u, 0xEAu},\r
+ {0xC4u, 0x8Fu},\r
+ {0xCAu, 0xFEu},\r
+ {0xCCu, 0xE3u},\r
+ {0xCEu, 0xFAu},\r
+ {0xD8u, 0x70u},\r
+ {0xDEu, 0x80u},\r
+ {0xE2u, 0x04u},\r
+ {0xE6u, 0x40u},\r
+ {0xE8u, 0x04u},\r
+ {0xEAu, 0x08u},\r
+ {0xEEu, 0x4Au},\r
+ {0x82u, 0x04u},\r
+ {0x8Au, 0x04u},\r
+ {0x8Eu, 0x03u},\r
+ {0x98u, 0x04u},\r
+ {0x9Au, 0x01u},\r
+ {0xACu, 0x04u},\r
+ {0xAEu, 0x02u},\r
+ {0xB0u, 0x07u},\r
+ {0xD8u, 0x04u},\r
+ {0xDCu, 0x09u},\r
+ {0xDFu, 0x01u},\r
+ {0x00u, 0x60u},\r
+ {0x03u, 0x40u},\r
+ {0x04u, 0x29u},\r
+ {0x06u, 0x02u},\r
+ {0x0Au, 0x08u},\r
+ {0x0Du, 0x20u},\r
+ {0x0Eu, 0x62u},\r
+ {0x13u, 0x40u},\r
+ {0x17u, 0x15u},\r
+ {0x18u, 0x40u},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Eu, 0x01u},\r
+ {0x24u, 0x2Eu},\r
+ {0x25u, 0x10u},\r
+ {0x26u, 0x08u},\r
+ {0x27u, 0x02u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Eu, 0x10u},\r
+ {0x36u, 0x59u},\r
+ {0x39u, 0x04u},\r
+ {0x3Au, 0x08u},\r
+ {0x3Cu, 0x81u},\r
+ {0x3Du, 0x20u},\r
+ {0x3Fu, 0x08u},\r
+ {0x45u, 0x1Au},\r
+ {0x4Cu, 0x01u},\r
+ {0x4Du, 0x02u},\r
+ {0x4Eu, 0x08u},\r
+ {0x4Fu, 0x09u},\r
+ {0x56u, 0x2Au},\r
+ {0x65u, 0x20u},\r
+ {0x6Cu, 0x20u},\r
+ {0x6Du, 0x03u},\r
+ {0x6Eu, 0xD2u},\r
+ {0x6Fu, 0x16u},\r
+ {0x74u, 0x40u},\r
+ {0x77u, 0x01u},\r
+ {0x7Cu, 0x02u},\r
+ {0x81u, 0x02u},\r
+ {0x8Cu, 0x40u},\r
+ {0x8Eu, 0x04u},\r
+ {0x91u, 0x08u},\r
+ {0x92u, 0x08u},\r
+ {0x93u, 0x48u},\r
+ {0x94u, 0x28u},\r
+ {0x96u, 0x10u},\r
+ {0x97u, 0x01u},\r
+ {0x98u, 0x02u},\r
+ {0x99u, 0x11u},\r
+ {0x9Bu, 0x40u},\r
+ {0x9Cu, 0xC0u},\r
+ {0x9Du, 0x02u},\r
+ {0x9Eu, 0x22u},\r
+ {0xA0u, 0x10u},\r
+ {0xA4u, 0x60u},\r
+ {0xA5u, 0x10u},\r
+ {0xA6u, 0x1Du},\r
+ {0xA7u, 0x03u},\r
+ {0xA9u, 0x10u},\r
+ {0xAAu, 0xC0u},\r
+ {0xAFu, 0x40u},\r
+ {0xB2u, 0x40u},\r
+ {0xB4u, 0x04u},\r
+ {0xC0u, 0xFBu},\r
+ {0xC2u, 0xF2u},\r
+ {0xC4u, 0x71u},\r
+ {0xCAu, 0x60u},\r
+ {0xCCu, 0xF0u},\r
+ {0xCEu, 0xF0u},\r
+ {0xD0u, 0xE0u},\r
+ {0xD2u, 0x30u},\r
+ {0xD8u, 0x20u},\r
+ {0xDEu, 0x80u},\r
+ {0xEEu, 0x42u},\r
+ {0x8Du, 0x40u},\r
+ {0x95u, 0x40u},\r
+ {0xAFu, 0x08u},\r
+ {0xB3u, 0x40u},\r
+ {0xE0u, 0x40u},\r
+ {0xEEu, 0x80u},\r
+ {0x38u, 0x08u},\r
+ {0x3Eu, 0x04u},\r
+ {0x58u, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x1Bu, 0x08u},\r
+ {0x80u, 0x10u},\r
+ {0x90u, 0x20u},\r
+ {0x93u, 0x80u},\r
+ {0x95u, 0x40u},\r
+ {0xA8u, 0x20u},\r
+ {0xABu, 0x08u},\r
+ {0xACu, 0x05u},\r
+ {0xADu, 0x04u},\r
+ {0xB0u, 0x04u},\r
+ {0xB2u, 0x20u},\r
+ {0xB4u, 0x40u},\r
+ {0xB7u, 0x90u},\r
+ {0xEAu, 0x60u},\r
+ {0xECu, 0x90u},\r
+ {0xEEu, 0x04u},\r
+ {0x04u, 0x0Fu},\r
+ {0x05u, 0x04u},\r
+ {0x06u, 0xF0u},\r
+ {0x07u, 0x02u},\r
+ {0x0Cu, 0x55u},\r
+ {0x0Du, 0x04u},\r
+ {0x0Eu, 0xAAu},\r
+ {0x0Fu, 0x01u},\r
+ {0x10u, 0x33u},\r
+ {0x12u, 0xCCu},\r
{0x13u, 0x03u},\r
- {0x15u, 0x10u},\r
- {0x16u, 0x03u},\r
- {0x19u, 0x04u},\r
- {0x1Au, 0x24u},\r
- {0x1Bu, 0x02u},\r
- {0x1Du, 0x10u},\r
- {0x21u, 0x20u},\r
- {0x22u, 0x04u},\r
- {0x26u, 0x20u},\r
- {0x29u, 0x08u},\r
- {0x2Cu, 0x24u},\r
- {0x2Du, 0x10u},\r
- {0x2Eu, 0x09u},\r
- {0x30u, 0x38u},\r
- {0x31u, 0x07u},\r
- {0x32u, 0x07u},\r
- {0x33u, 0x10u},\r
- {0x34u, 0x40u},\r
+ {0x17u, 0x04u},\r
+ {0x19u, 0x08u},\r
+ {0x1Au, 0xFFu},\r
+ {0x1Cu, 0x69u},\r
+ {0x1Eu, 0x96u},\r
+ {0x20u, 0xFFu},\r
+ {0x2Bu, 0x04u},\r
+ {0x2Cu, 0xFFu},\r
{0x35u, 0x08u},\r
- {0x37u, 0x20u},\r
- {0x39u, 0x08u},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x54u},\r
+ {0x36u, 0xFFu},\r
+ {0x37u, 0x07u},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x10u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x99u},\r
+ {0x5Cu, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x85u, 0x33u},\r
- {0x86u, 0xFFu},\r
- {0x87u, 0xCCu},\r
- {0x89u, 0xFFu},\r
- {0x8Du, 0x0Fu},\r
- {0x8Eu, 0xFFu},\r
- {0x8Fu, 0xF0u},\r
- {0x90u, 0x69u},\r
- {0x92u, 0x96u},\r
- {0x93u, 0xFFu},\r
- {0x96u, 0xFFu},\r
- {0x98u, 0x33u},\r
- {0x9Au, 0xCCu},\r
- {0x9Du, 0x69u},\r
- {0x9Fu, 0x96u},\r
- {0xA0u, 0x55u},\r
- {0xA1u, 0x55u},\r
- {0xA2u, 0xAAu},\r
- {0xA3u, 0xAAu},\r
- {0xA9u, 0xFFu},\r
- {0xACu, 0x0Fu},\r
- {0xAEu, 0xF0u},\r
- {0xB0u, 0xFFu},\r
- {0xB7u, 0xFFu},\r
- {0xBEu, 0x01u},\r
- {0xBFu, 0x40u},\r
+ {0x84u, 0x0Fu},\r
+ {0x86u, 0xF0u},\r
+ {0x88u, 0x69u},\r
+ {0x89u, 0x02u},\r
+ {0x8Au, 0x96u},\r
+ {0x8Cu, 0x55u},\r
+ {0x8Eu, 0xAAu},\r
+ {0x90u, 0x33u},\r
+ {0x92u, 0xCCu},\r
+ {0x95u, 0x01u},\r
+ {0x9Eu, 0xFFu},\r
+ {0xA1u, 0x04u},\r
+ {0xA2u, 0xFFu},\r
+ {0xA5u, 0x08u},\r
+ {0xAEu, 0xFFu},\r
+ {0xB1u, 0x04u},\r
+ {0xB2u, 0xFFu},\r
+ {0xB3u, 0x01u},\r
+ {0xB5u, 0x02u},\r
+ {0xB7u, 0x08u},\r
+ {0xBEu, 0x04u},\r
+ {0xBFu, 0x55u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x40u},\r
- {0x01u, 0x40u},\r
- {0x03u, 0x20u},\r
- {0x05u, 0x04u},\r
+ {0x01u, 0x08u},\r
+ {0x03u, 0x09u},\r
+ {0x05u, 0x08u},\r
{0x07u, 0x01u},\r
- {0x08u, 0x01u},\r
- {0x09u, 0x20u},\r
- {0x0Au, 0x10u},\r
- {0x0Cu, 0x08u},\r
- {0x0Eu, 0x80u},\r
- {0x0Fu, 0xA4u},\r
- {0x11u, 0x04u},\r
- {0x13u, 0x42u},\r
- {0x14u, 0x40u},\r
+ {0x08u, 0x81u},\r
+ {0x0Au, 0x80u},\r
+ {0x0Cu, 0x01u},\r
+ {0x0Eu, 0x0Au},\r
+ {0x11u, 0x40u},\r
+ {0x12u, 0x80u},\r
+ {0x14u, 0x80u},\r
{0x15u, 0x40u},\r
- {0x18u, 0x44u},\r
- {0x19u, 0x04u},\r
- {0x1Au, 0x10u},\r
- {0x1Fu, 0x02u},\r
- {0x22u, 0x55u},\r
- {0x26u, 0x80u},\r
- {0x2Au, 0x22u},\r
- {0x2Bu, 0x02u},\r
- {0x2Cu, 0x48u},\r
- {0x31u, 0x18u},\r
- {0x32u, 0x81u},\r
- {0x36u, 0x40u},\r
- {0x37u, 0x01u},\r
- {0x39u, 0x22u},\r
- {0x3Au, 0x80u},\r
- {0x3Bu, 0x08u},\r
- {0x3Cu, 0x40u},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x04u},\r
- {0x43u, 0xC0u},\r
- {0x59u, 0x01u},\r
- {0x5Bu, 0x58u},\r
- {0x86u, 0x20u},\r
- {0x8Au, 0x04u},\r
- {0xC0u, 0xA5u},\r
- {0xC2u, 0x7Eu},\r
- {0xC4u, 0x9Du},\r
- {0xCAu, 0xADu},\r
- {0xCCu, 0x9Fu},\r
- {0xCEu, 0x7Fu},\r
- {0xD6u, 0x0Fu},\r
- {0xE2u, 0x88u},\r
- {0x80u, 0x01u},\r
- {0x90u, 0x02u},\r
- {0xB2u, 0x01u},\r
- {0xEAu, 0x20u},\r
- {0x01u, 0x05u},\r
- {0x02u, 0x01u},\r
- {0x05u, 0x09u},\r
- {0x06u, 0x0Cu},\r
- {0x07u, 0x02u},\r
- {0x08u, 0x01u},\r
- {0x0Au, 0x02u},\r
- {0x0Bu, 0x38u},\r
- {0x0Eu, 0x10u},\r
- {0x0Fu, 0x04u},\r
- {0x13u, 0x05u},\r
- {0x14u, 0x04u},\r
- {0x15u, 0x05u},\r
- {0x16u, 0x03u},\r
- {0x18u, 0x10u},\r
- {0x19u, 0x23u},\r
+ {0x18u, 0x20u},\r
+ {0x1Fu, 0x40u},\r
+ {0x20u, 0x4Au},\r
+ {0x21u, 0x04u},\r
+ {0x26u, 0x20u},\r
+ {0x27u, 0x03u},\r
+ {0x28u, 0x20u},\r
+ {0x2Bu, 0x80u},\r
+ {0x2Cu, 0x04u},\r
+ {0x33u, 0x04u},\r
+ {0x36u, 0x08u},\r
+ {0x37u, 0x12u},\r
+ {0x3Au, 0x20u},\r
+ {0x3Du, 0x84u},\r
+ {0x5Du, 0x22u},\r
+ {0x5Fu, 0x88u},\r
+ {0x6Cu, 0x01u},\r
+ {0x82u, 0x8Du},\r
+ {0x83u, 0x0Cu},\r
+ {0x85u, 0x46u},\r
+ {0x88u, 0x80u},\r
+ {0x8Au, 0x20u},\r
+ {0x8Bu, 0x80u},\r
+ {0x8Du, 0x60u},\r
+ {0x92u, 0x80u},\r
+ {0x94u, 0x02u},\r
+ {0x99u, 0x08u},\r
+ {0x9Fu, 0x01u},\r
+ {0xB3u, 0x01u},\r
+ {0xB4u, 0x01u},\r
+ {0xC0u, 0xA7u},\r
+ {0xC2u, 0xD9u},\r
+ {0xC4u, 0x99u},\r
+ {0xCAu, 0x23u},\r
+ {0xCCu, 0xE2u},\r
+ {0xCEu, 0x54u},\r
+ {0xD6u, 0xF0u},\r
+ {0xE0u, 0x30u},\r
+ {0xE2u, 0x09u},\r
+ {0xE6u, 0x40u},\r
+ {0xEAu, 0x44u},\r
+ {0xEEu, 0x20u},\r
+ {0x81u, 0x08u},\r
+ {0x82u, 0x40u},\r
+ {0xE4u, 0x05u},\r
+ {0xE6u, 0xC0u},\r
+ {0x87u, 0x04u},\r
+ {0x93u, 0x08u},\r
+ {0xA8u, 0x20u},\r
+ {0xABu, 0x04u},\r
+ {0x00u, 0x2Cu},\r
+ {0x01u, 0x01u},\r
+ {0x04u, 0xC1u},\r
+ {0x06u, 0x2Eu},\r
+ {0x08u, 0x60u},\r
+ {0x09u, 0x48u},\r
+ {0x0Au, 0x8Fu},\r
+ {0x0Bu, 0x21u},\r
+ {0x0Cu, 0x44u},\r
+ {0x0Du, 0x01u},\r
+ {0x0Eu, 0x20u},\r
+ {0x10u, 0x0Cu},\r
+ {0x12u, 0x20u},\r
+ {0x14u, 0x21u},\r
+ {0x15u, 0x62u},\r
+ {0x16u, 0xC2u},\r
+ {0x17u, 0x08u},\r
+ {0x18u, 0x08u},\r
+ {0x19u, 0x01u},\r
{0x1Cu, 0x10u},\r
- {0x1Du, 0x02u},\r
- {0x1Fu, 0x01u},\r
- {0x20u, 0x10u},\r
- {0x21u, 0x05u},\r
- {0x24u, 0x10u},\r
- {0x25u, 0x05u},\r
- {0x28u, 0x08u},\r
- {0x29u, 0x02u},\r
- {0x2Au, 0x03u},\r
- {0x2Bu, 0x11u},\r
- {0x2Du, 0x38u},\r
- {0x2Eu, 0x22u},\r
- {0x30u, 0x20u},\r
- {0x31u, 0x03u},\r
+ {0x1Du, 0x01u},\r
+ {0x20u, 0x2Cu},\r
+ {0x21u, 0x10u},\r
+ {0x24u, 0x20u},\r
+ {0x25u, 0x04u},\r
+ {0x26u, 0x0Cu},\r
+ {0x28u, 0x24u},\r
+ {0x29u, 0x47u},\r
+ {0x2Au, 0x08u},\r
+ {0x2Bu, 0x18u},\r
+ {0x2Cu, 0x10u},\r
+ {0x2Du, 0x01u},\r
+ {0x30u, 0x80u},\r
+ {0x31u, 0x3Fu},\r
{0x32u, 0x0Fu},\r
- {0x33u, 0x04u},\r
- {0x36u, 0x10u},\r
- {0x37u, 0x38u},\r
- {0x3Bu, 0x02u},\r
- {0x3Eu, 0x40u},\r
- {0x3Fu, 0x44u},\r
+ {0x34u, 0x10u},\r
+ {0x36u, 0x60u},\r
+ {0x37u, 0x40u},\r
+ {0x38u, 0x20u},\r
+ {0x39u, 0x02u},\r
+ {0x3Au, 0x80u},\r
+ {0x3Eu, 0x01u},\r
+ {0x3Fu, 0x41u},\r
+ {0x54u, 0x09u},\r
{0x58u, 0x0Bu},\r
- {0x59u, 0x0Bu},\r
- {0x5Cu, 0x99u},\r
+ {0x59u, 0x04u},\r
+ {0x5Bu, 0x0Bu},\r
+ {0x5Cu, 0x09u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x18u},\r
- {0x86u, 0x60u},\r
- {0x87u, 0x06u},\r
- {0x8Cu, 0x04u},\r
- {0x8Eu, 0x03u},\r
- {0x93u, 0x02u},\r
- {0x94u, 0x03u},\r
- {0x96u, 0x04u},\r
- {0x97u, 0x0Au},\r
- {0x98u, 0x30u},\r
- {0x99u, 0x0Cu},\r
- {0x9Au, 0x48u},\r
- {0x9Du, 0x01u},\r
- {0xA4u, 0x01u},\r
- {0xA6u, 0x06u},\r
- {0xA8u, 0x05u},\r
- {0xAAu, 0x02u},\r
- {0xACu, 0x28u},\r
- {0xAEu, 0x50u},\r
- {0xB1u, 0x0Eu},\r
- {0xB3u, 0x01u},\r
- {0xB4u, 0x78u},\r
+ {0x84u, 0x19u},\r
+ {0x86u, 0x24u},\r
+ {0x87u, 0x04u},\r
+ {0x8Du, 0x04u},\r
+ {0x8Fu, 0x02u},\r
+ {0x93u, 0x03u},\r
+ {0x94u, 0x09u},\r
+ {0x96u, 0x32u},\r
+ {0x98u, 0x20u},\r
+ {0x9Au, 0x18u},\r
+ {0x9Cu, 0x06u},\r
+ {0xA3u, 0x04u},\r
+ {0xA8u, 0x2Au},\r
+ {0xA9u, 0x04u},\r
+ {0xAAu, 0x11u},\r
+ {0xABu, 0x01u},\r
+ {0xB1u, 0x07u},\r
+ {0xB4u, 0x38u},\r
{0xB6u, 0x07u},\r
- {0xBAu, 0x80u},\r
- {0xBEu, 0x10u},\r
- {0xBFu, 0x04u},\r
+ {0xB8u, 0x80u},\r
+ {0xBAu, 0x20u},\r
{0xD8u, 0x0Bu},\r
- {0xD9u, 0x0Bu},\r
+ {0xD9u, 0x04u},\r
{0xDCu, 0x99u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x08u},\r
- {0x01u, 0x80u},\r
- {0x05u, 0x05u},\r
- {0x06u, 0x20u},\r
- {0x07u, 0x09u},\r
- {0x08u, 0x20u},\r
+ {0x00u, 0x04u},\r
+ {0x04u, 0x28u},\r
+ {0x05u, 0x40u},\r
+ {0x06u, 0x80u},\r
+ {0x08u, 0x80u},\r
{0x09u, 0x08u},\r
- {0x0Cu, 0x80u},\r
- {0x0Eu, 0x28u},\r
- {0x11u, 0x04u},\r
- {0x13u, 0x60u},\r
- {0x15u, 0x41u},\r
- {0x17u, 0x14u},\r
- {0x18u, 0x04u},\r
- {0x19u, 0x80u},\r
- {0x1Du, 0x85u},\r
- {0x1Eu, 0x02u},\r
- {0x20u, 0x20u},\r
- {0x22u, 0x01u},\r
+ {0x0Au, 0x06u},\r
+ {0x0Eu, 0xA1u},\r
+ {0x0Fu, 0x08u},\r
+ {0x12u, 0x08u},\r
+ {0x15u, 0x01u},\r
+ {0x17u, 0x94u},\r
+ {0x19u, 0x20u},\r
+ {0x1Au, 0x06u},\r
+ {0x1Cu, 0x01u},\r
+ {0x1Du, 0x68u},\r
+ {0x1Eu, 0x60u},\r
+ {0x1Fu, 0x28u},\r
+ {0x21u, 0x02u},\r
{0x24u, 0x02u},\r
- {0x26u, 0x0Au},\r
- {0x27u, 0x40u},\r
- {0x2Cu, 0x81u},\r
- {0x2Fu, 0x28u},\r
- {0x31u, 0x08u},\r
- {0x32u, 0x41u},\r
- {0x33u, 0x18u},\r
- {0x37u, 0x65u},\r
- {0x38u, 0x08u},\r
- {0x3Du, 0x05u},\r
- {0x3Eu, 0xA0u},\r
+ {0x27u, 0x80u},\r
+ {0x29u, 0x11u},\r
+ {0x2Eu, 0x02u},\r
+ {0x2Fu, 0x2Au},\r
+ {0x31u, 0x02u},\r
+ {0x35u, 0x40u},\r
+ {0x36u, 0x08u},\r
+ {0x37u, 0x10u},\r
+ {0x39u, 0x08u},\r
+ {0x3Bu, 0x40u},\r
+ {0x3Cu, 0x80u},\r
+ {0x3Du, 0x22u},\r
+ {0x3Eu, 0x80u},\r
+ {0x4Cu, 0x01u},\r
+ {0x4Du, 0x80u},\r
+ {0x5Cu, 0x20u},\r
+ {0x5Du, 0x04u},\r
+ {0x5Eu, 0x40u},\r
+ {0x5Fu, 0x02u},\r
+ {0x65u, 0x80u},\r
{0x78u, 0x02u},\r
- {0x7Eu, 0x80u},\r
- {0x90u, 0x08u},\r
- {0x91u, 0x45u},\r
- {0x92u, 0x80u},\r
- {0x93u, 0x40u},\r
- {0x94u, 0x04u},\r
- {0x98u, 0x23u},\r
- {0x9Au, 0x80u},\r
- {0x9Bu, 0x3Du},\r
- {0x9Du, 0x80u},\r
- {0x9Fu, 0x40u},\r
- {0xA0u, 0x84u},\r
- {0xA1u, 0x08u},\r
- {0xA2u, 0x94u},\r
- {0xA3u, 0x20u},\r
- {0xA4u, 0x10u},\r
- {0xA5u, 0x80u},\r
- {0xA6u, 0x0Bu},\r
- {0xA8u, 0x04u},\r
- {0xAEu, 0x40u},\r
- {0xB6u, 0x80u},\r
- {0xB7u, 0x01u},\r
- {0xC0u, 0xF5u},\r
- {0xC2u, 0xE6u},\r
- {0xC4u, 0xF7u},\r
- {0xCAu, 0xF0u},\r
- {0xCCu, 0xFFu},\r
- {0xCEu, 0xF2u},\r
+ {0x7Cu, 0x02u},\r
+ {0x89u, 0x02u},\r
+ {0x90u, 0x2Cu},\r
+ {0x91u, 0x0Du},\r
+ {0x92u, 0x01u},\r
+ {0x93u, 0x48u},\r
+ {0x94u, 0x01u},\r
+ {0x98u, 0x02u},\r
+ {0x99u, 0x11u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Bu, 0x16u},\r
+ {0x9Cu, 0x80u},\r
+ {0x9Du, 0x20u},\r
+ {0xA0u, 0x40u},\r
+ {0xA1u, 0x11u},\r
+ {0xA2u, 0x48u},\r
+ {0xA3u, 0x06u},\r
+ {0xA5u, 0x28u},\r
+ {0xA6u, 0x10u},\r
+ {0xACu, 0x40u},\r
+ {0xC0u, 0xF4u},\r
+ {0xC2u, 0xF7u},\r
+ {0xC4u, 0xF2u},\r
+ {0xCAu, 0xF5u},\r
+ {0xCCu, 0x71u},\r
+ {0xCEu, 0xBAu},\r
+ {0xD6u, 0xF0u},\r
+ {0xD8u, 0x10u},\r
{0xDEu, 0x81u},\r
- {0xE8u, 0x04u},\r
- {0xECu, 0x80u},\r
+ {0xE6u, 0x20u},\r
+ {0xEAu, 0x02u},\r
{0xEEu, 0x02u},\r
- {0xABu, 0x40u},\r
- {0xB0u, 0x04u},\r
- {0xECu, 0x80u},\r
+ {0xEAu, 0x02u},\r
{0xEEu, 0x02u},\r
- {0x33u, 0x40u},\r
+ {0x30u, 0x20u},\r
+ {0x33u, 0x01u},\r
{0x36u, 0x40u},\r
- {0x58u, 0x08u},\r
- {0x5Cu, 0x01u},\r
- {0x5Du, 0x10u},\r
+ {0x53u, 0x08u},\r
+ {0x5Bu, 0x08u},\r
{0x61u, 0x08u},\r
- {0x64u, 0x10u},\r
- {0x89u, 0x10u},\r
- {0xCCu, 0x30u},\r
- {0xD6u, 0xE0u},\r
+ {0x65u, 0xA0u},\r
+ {0x85u, 0x20u},\r
+ {0xCCu, 0x70u},\r
+ {0xD4u, 0x20u},\r
+ {0xD6u, 0xC0u},\r
{0xD8u, 0xC0u},\r
- {0x59u, 0x40u},\r
- {0x5Fu, 0x20u},\r
- {0x83u, 0x40u},\r
- {0x8Bu, 0x20u},\r
- {0x9Cu, 0x08u},\r
- {0x9Fu, 0x40u},\r
+ {0xE6u, 0x40u},\r
+ {0x59u, 0x10u},\r
+ {0x5Eu, 0x40u},\r
+ {0x81u, 0x18u},\r
+ {0x9Du, 0x80u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA4u, 0x20u},\r
{0xA5u, 0x08u},\r
{0xA6u, 0x40u},\r
- {0xA8u, 0x01u},\r
- {0xACu, 0x10u},\r
+ {0xA7u, 0x08u},\r
+ {0xB7u, 0x08u},\r
{0xD4u, 0x80u},\r
{0xD6u, 0x20u},\r
- {0xE6u, 0x80u},\r
- {0xEAu, 0x80u},\r
- {0xEEu, 0x40u},\r
- {0x89u, 0x08u},\r
- {0x8Cu, 0x08u},\r
- {0x9Cu, 0x08u},\r
+ {0xE0u, 0x80u},\r
+ {0xE6u, 0x20u},\r
+ {0x10u, 0x20u},\r
+ {0x58u, 0x02u},\r
+ {0x8Fu, 0x02u},\r
+ {0x9Du, 0x80u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA4u, 0x20u},\r
{0xA5u, 0x08u},\r
{0xA6u, 0x40u},\r
- {0xADu, 0x40u},\r
- {0xEEu, 0x10u},\r
- {0x94u, 0x02u},\r
+ {0xA7u, 0x08u},\r
+ {0xB6u, 0x40u},\r
+ {0xC4u, 0x10u},\r
+ {0xD6u, 0x40u},\r
+ {0x80u, 0x01u},\r
+ {0x97u, 0x10u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA3u, 0x02u},\r
+ {0xA5u, 0x08u},\r
{0xA6u, 0x40u},\r
- {0xB4u, 0x01u},\r
- {0x08u, 0x80u},\r
- {0x0Fu, 0x40u},\r
- {0x12u, 0x80u},\r
- {0x53u, 0x04u},\r
- {0x57u, 0x80u},\r
- {0x5Bu, 0x20u},\r
- {0x5Cu, 0x10u},\r
- {0x84u, 0x80u},\r
+ {0xABu, 0x08u},\r
+ {0xACu, 0x02u},\r
+ {0xAFu, 0x10u},\r
+ {0xB5u, 0x80u},\r
+ {0xE0u, 0x80u},\r
+ {0xE8u, 0x10u},\r
+ {0xEEu, 0xC0u},\r
+ {0x09u, 0x20u},\r
+ {0x0Fu, 0x80u},\r
+ {0x13u, 0x08u},\r
+ {0x52u, 0x20u},\r
+ {0x53u, 0x01u},\r
+ {0x57u, 0x20u},\r
+ {0x5Fu, 0x80u},\r
+ {0x82u, 0x20u},\r
+ {0x83u, 0x20u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Eu, 0x01u},\r
{0xC2u, 0x06u},\r
{0xC4u, 0x08u},\r
{0xD4u, 0x07u},\r
{0xD6u, 0x04u},\r
- {0x01u, 0x20u},\r
- {0x06u, 0x80u},\r
- {0x07u, 0x01u},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0x02u},\r
- {0x0Cu, 0x80u},\r
- {0x0Eu, 0x20u},\r
- {0x82u, 0x40u},\r
- {0x87u, 0x01u},\r
- {0x8Bu, 0x40u},\r
- {0x93u, 0x40u},\r
- {0x98u, 0x80u},\r
- {0xA4u, 0x80u},\r
- {0xABu, 0x80u},\r
- {0xAFu, 0x24u},\r
- {0xB2u, 0x80u},\r
- {0xB4u, 0x10u},\r
+ {0xE6u, 0x03u},\r
+ {0x02u, 0x01u},\r
+ {0x04u, 0x40u},\r
+ {0x06u, 0x20u},\r
+ {0x0Bu, 0x11u},\r
+ {0x0Fu, 0x82u},\r
+ {0x83u, 0x01u},\r
+ {0x86u, 0x20u},\r
+ {0x8Bu, 0x11u},\r
+ {0x8Du, 0x20u},\r
+ {0x8Fu, 0x01u},\r
+ {0x97u, 0x02u},\r
+ {0x9Eu, 0x01u},\r
+ {0xA1u, 0x20u},\r
+ {0xABu, 0x40u},\r
+ {0xB3u, 0x80u},\r
{0xC0u, 0x07u},\r
{0xC2u, 0x0Fu},\r
- {0xE2u, 0x04u},\r
- {0xE8u, 0x08u},\r
- {0xEAu, 0x01u},\r
- {0x92u, 0x02u},\r
- {0x96u, 0x80u},\r
- {0x9Au, 0x80u},\r
- {0xA1u, 0x01u},\r
- {0xB0u, 0x80u},\r
- {0xB2u, 0x10u},\r
- {0xB5u, 0x20u},\r
- {0xEAu, 0x0Du},\r
- {0x0Au, 0x80u},\r
- {0x0Fu, 0x40u},\r
- {0x96u, 0x80u},\r
- {0xA9u, 0x01u},\r
- {0xAEu, 0x80u},\r
- {0xB2u, 0x01u},\r
+ {0xE0u, 0x02u},\r
+ {0xE2u, 0x01u},\r
+ {0xE6u, 0x03u},\r
+ {0xECu, 0x04u},\r
+ {0xA8u, 0x40u},\r
+ {0xB7u, 0x40u},\r
+ {0xEEu, 0x02u},\r
+ {0x0Bu, 0x40u},\r
+ {0x0Du, 0x08u},\r
{0xC2u, 0x0Cu},\r
- {0xEAu, 0x04u},\r
- {0x22u, 0x08u},\r
- {0x24u, 0x02u},\r
- {0x94u, 0x02u},\r
- {0x9Eu, 0x20u},\r
- {0xA6u, 0x08u},\r
- {0xAEu, 0x60u},\r
- {0xB2u, 0x08u},\r
+ {0x23u, 0x10u},\r
+ {0x26u, 0x10u},\r
+ {0x89u, 0x08u},\r
+ {0x94u, 0x01u},\r
+ {0x97u, 0x10u},\r
+ {0xA3u, 0x02u},\r
+ {0xA5u, 0x08u},\r
+ {0xA6u, 0x10u},\r
+ {0xAEu, 0x50u},\r
+ {0xAFu, 0x01u},\r
{0xC8u, 0x60u},\r
- {0xE8u, 0x10u},\r
+ {0xEAu, 0x40u},\r
+ {0xECu, 0x10u},\r
{0xEEu, 0x40u},\r
- {0x06u, 0x20u},\r
- {0x53u, 0x01u},\r
- {0x5Du, 0x20u},\r
- {0x83u, 0x01u},\r
- {0x99u, 0x20u},\r
- {0x9Eu, 0x20u},\r
- {0xB1u, 0x20u},\r
+ {0x04u, 0x01u},\r
+ {0x53u, 0x02u},\r
+ {0x57u, 0x01u},\r
+ {0x87u, 0x01u},\r
+ {0x94u, 0x01u},\r
+ {0xA3u, 0x02u},\r
{0xC0u, 0x20u},\r
{0xD4u, 0x80u},\r
{0xD6u, 0x20u},\r
- {0xE6u, 0x20u},\r
+ {0xE6u, 0x10u},\r
+ {0xADu, 0x08u},\r
{0xAFu, 0x40u},\r
{0x01u, 0x01u},\r
+ {0x09u, 0x01u},\r
{0x0Bu, 0x01u},\r
- {0x0Du, 0x01u},\r
{0x0Fu, 0x01u},\r
{0x11u, 0x01u},\r
{0x1Bu, 0x01u},\r
- {0x00u, 0x0Au},\r
+ {0x00u, 0x2Bu},\r
};\r
\r
\r
\r
static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
/* address, size */\r
+ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
{(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1536u},\r
{(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), 2432u},\r
\r
/* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */\r
static const uint8 CYCODE BS_UDB_1_2_1_CONFIG_VAL[] = {\r
- 0x80u, 0x01u, 0x00u, 0x00u, 0x7Fu, 0x10u, 0x80u, 0x00u, 0xC0u, 0x08u, 0x04u, 0x21u, 0xC0u, 0x04u, 0x01u, 0x00u, \r
- 0x00u, 0x01u, 0x60u, 0x00u, 0x00u, 0x07u, 0xFFu, 0x18u, 0x00u, 0x22u, 0x9Fu, 0x08u, 0xC0u, 0x40u, 0x02u, 0x00u, \r
- 0x90u, 0x01u, 0x40u, 0x00u, 0x1Fu, 0x01u, 0x20u, 0x00u, 0xC0u, 0x40u, 0x08u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, \r
- 0x00u, 0x3Fu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x82u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x01u, \r
- 0x32u, 0x06u, 0x10u, 0x00u, 0x04u, 0xCBu, 0xFDu, 0x0Eu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u, \r
+ 0x80u, 0x42u, 0x00u, 0x00u, 0x00u, 0x04u, 0xFFu, 0x20u, 0x7Fu, 0x39u, 0x80u, 0x06u, 0x00u, 0xC6u, 0x9Fu, 0x00u, \r
+ 0x90u, 0xC6u, 0x40u, 0x00u, 0x1Fu, 0x01u, 0x20u, 0x5Eu, 0x00u, 0x77u, 0x60u, 0x08u, 0xC0u, 0x46u, 0x02u, 0x80u, \r
+ 0xC0u, 0x00u, 0x01u, 0x00u, 0xC0u, 0xC2u, 0x08u, 0x04u, 0xC0u, 0x80u, 0x04u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, \r
+ 0x00u, 0x00u, 0x00u, 0x70u, 0x00u, 0x0Fu, 0xFFu, 0x80u, 0x00u, 0x20u, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x40u, 0x40u, \r
+ 0x26u, 0x03u, 0x50u, 0x00u, 0x04u, 0xDCu, 0xF0u, 0xBEu, 0x3Bu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u, \r
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
\r
.include "cydevicegnu.inc"\r
.include "cydevicegnu_trm.inc"\r
\r
+/* SCSI_CMD_TIMER_TimerHW */\r
+.set SCSI_CMD_TIMER_TimerHW__CAP0, CYREG_TMR0_CAP0\r
+.set SCSI_CMD_TIMER_TimerHW__CAP1, CYREG_TMR0_CAP1\r
+.set SCSI_CMD_TIMER_TimerHW__CFG0, CYREG_TMR0_CFG0\r
+.set SCSI_CMD_TIMER_TimerHW__CFG1, CYREG_TMR0_CFG1\r
+.set SCSI_CMD_TIMER_TimerHW__CFG2, CYREG_TMR0_CFG2\r
+.set SCSI_CMD_TIMER_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0\r
+.set SCSI_CMD_TIMER_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1\r
+.set SCSI_CMD_TIMER_TimerHW__PER0, CYREG_TMR0_PER0\r
+.set SCSI_CMD_TIMER_TimerHW__PER1, CYREG_TMR0_PER1\r
+.set SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3\r
+.set SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK, 0x01\r
+.set SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3\r
+.set SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK, 0x01\r
+.set SCSI_CMD_TIMER_TimerHW__RT0, CYREG_TMR0_RT0\r
+.set SCSI_CMD_TIMER_TimerHW__RT1, CYREG_TMR0_RT1\r
+.set SCSI_CMD_TIMER_TimerHW__SR0, CYREG_TMR0_SR0\r
+\r
+/* SCSI_CMD_TIMER_ISR */\r
+.set SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_CMD_TIMER_ISR__INTC_MASK, 0x01\r
+.set SCSI_CMD_TIMER_ISR__INTC_NUMBER, 0\r
+.set SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM, 7\r
+.set SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
/* USBFS_bus_reset */\r
.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK\r
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB05_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB05_ST\r
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0\r
/* SCSI_CTL_IO */\r
.set SCSI_CTL_IO_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_CTL_IO_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL\r
.set SCSI_CTL_IO_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK\r
-.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
\r
/* SCSI_In_DBx */\r
.set SCSI_In_DBx__0__AG, CYREG_PRT12_AG\r
/* scsiTarget */\r
.set scsiTarget_StatusReg__0__MASK, 0x01\r
.set scsiTarget_StatusReg__0__POS, 0\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__3__MASK, 0x08\r
.set scsiTarget_StatusReg__3__POS, 3\r
.set scsiTarget_StatusReg__MASK, 0x0F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB14_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB14_ST\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST\r
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB13_MSK\r
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB13_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB13_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB13_ST\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL\r
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK\r
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK\r
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB13_CTL\r
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL\r
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB13_CTL\r
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL\r
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB13_MSK\r
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB13_14_A0\r
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB13_14_A1\r
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB13_14_D0\r
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB13_14_D1\r
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB13_14_F0\r
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB13_14_F1\r
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB13_A0_A1\r
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB13_A0\r
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB13_A1\r
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB13_D0_D1\r
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB13_D0\r
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB13_D1\r
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB13_F0_F1\r
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB13_F0\r
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB13_F1\r
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK\r
+.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK\r
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB03_ST\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB03_CTL\r
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB03_CTL\r
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB03_MSK\r
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB03_04_A0\r
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB03_04_A1\r
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB03_04_D0\r
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB03_04_D1\r
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB03_04_F0\r
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB03_04_F1\r
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB03_A0_A1\r
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB03_A0\r
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB03_A1\r
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB03_D0_D1\r
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB03_D0\r
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB03_D1\r
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB03_F0_F1\r
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB03_F0\r
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB03_F1\r
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
\r
/* SD_Clk_Ctl */\r
.set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
/* USBFS_ep_1 */\r
.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_1__INTC_MASK, 0x01\r
-.set USBFS_ep_1__INTC_NUMBER, 0\r
+.set USBFS_ep_1__INTC_MASK, 0x02\r
+.set USBFS_ep_1__INTC_NUMBER, 1\r
.set USBFS_ep_1__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_2 */\r
.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_2__INTC_MASK, 0x02\r
-.set USBFS_ep_2__INTC_NUMBER, 1\r
+.set USBFS_ep_2__INTC_MASK, 0x04\r
+.set USBFS_ep_2__INTC_NUMBER, 2\r
.set USBFS_ep_2__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
.set CYDEV_ECC_ENABLE, 0\r
.set CYDEV_HEAP_SIZE, 0x1000\r
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1\r
-.set CYDEV_INTR_RISING, 0x00000000\r
+.set CYDEV_INTR_RISING, 0x00000001\r
.set CYDEV_PROJ_TYPE, 2\r
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1\r
.set CYDEV_PROJ_TYPE_LOADABLE, 2\r
INCLUDE cydeviceiar.inc\r
INCLUDE cydeviceiar_trm.inc\r
\r
+/* SCSI_CMD_TIMER_TimerHW */\r
+SCSI_CMD_TIMER_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
+SCSI_CMD_TIMER_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
+SCSI_CMD_TIMER_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
+SCSI_CMD_TIMER_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
+SCSI_CMD_TIMER_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
+SCSI_CMD_TIMER_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
+SCSI_CMD_TIMER_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
+SCSI_CMD_TIMER_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
+SCSI_CMD_TIMER_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
+SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
+SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK EQU 0x01\r
+SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
+SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK EQU 0x01\r
+SCSI_CMD_TIMER_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
+SCSI_CMD_TIMER_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
+SCSI_CMD_TIMER_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
+\r
+/* SCSI_CMD_TIMER_ISR */\r
+SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_CMD_TIMER_ISR__INTC_MASK EQU 0x01\r
+SCSI_CMD_TIMER_ISR__INTC_NUMBER EQU 0\r
+SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
/* USBFS_bus_reset */\r
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
/* SCSI_CTL_IO */\r
SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
\r
/* SCSI_In_DBx */\r
SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
/* scsiTarget */\r
scsiTarget_StatusReg__0__MASK EQU 0x01\r
scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__3__POS EQU 3\r
scsiTarget_StatusReg__MASK EQU 0x0F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
\r
/* SD_Clk_Ctl */\r
SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
/* USBFS_ep_1 */\r
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x01\r
-USBFS_ep_1__INTC_NUMBER EQU 0\r
+USBFS_ep_1__INTC_MASK EQU 0x02\r
+USBFS_ep_1__INTC_NUMBER EQU 1\r
USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_2 */\r
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x02\r
-USBFS_ep_2__INTC_NUMBER EQU 1\r
+USBFS_ep_2__INTC_MASK EQU 0x04\r
+USBFS_ep_2__INTC_NUMBER EQU 2\r
USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
CYDEV_ECC_ENABLE EQU 0\r
CYDEV_HEAP_SIZE EQU 0x1000\r
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x00000000\r
+CYDEV_INTR_RISING EQU 0x00000001\r
CYDEV_PROJ_TYPE EQU 2\r
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
GET cydevicerv.inc\r
GET cydevicerv_trm.inc\r
\r
+; SCSI_CMD_TIMER_TimerHW\r
+SCSI_CMD_TIMER_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
+SCSI_CMD_TIMER_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
+SCSI_CMD_TIMER_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
+SCSI_CMD_TIMER_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
+SCSI_CMD_TIMER_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
+SCSI_CMD_TIMER_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
+SCSI_CMD_TIMER_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
+SCSI_CMD_TIMER_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
+SCSI_CMD_TIMER_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
+SCSI_CMD_TIMER_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
+SCSI_CMD_TIMER_TimerHW__PM_ACT_MSK EQU 0x01\r
+SCSI_CMD_TIMER_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
+SCSI_CMD_TIMER_TimerHW__PM_STBY_MSK EQU 0x01\r
+SCSI_CMD_TIMER_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
+SCSI_CMD_TIMER_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
+SCSI_CMD_TIMER_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
+\r
+; SCSI_CMD_TIMER_ISR\r
+SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_CMD_TIMER_ISR__INTC_MASK EQU 0x01\r
+SCSI_CMD_TIMER_ISR__INTC_NUMBER EQU 0\r
+SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
; USBFS_bus_reset\r
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
; SCSI_CTL_IO\r
SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
-SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
\r
; SCSI_In_DBx\r
SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
; scsiTarget\r
scsiTarget_StatusReg__0__MASK EQU 0x01\r
scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__3__POS EQU 3\r
scsiTarget_StatusReg__MASK EQU 0x0F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
\r
; SD_Clk_Ctl\r
SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
\r
; USBFS_ep_0\r
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
; USBFS_ep_1\r
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x01\r
-USBFS_ep_1__INTC_NUMBER EQU 0\r
+USBFS_ep_1__INTC_MASK EQU 0x02\r
+USBFS_ep_1__INTC_NUMBER EQU 1\r
USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; USBFS_ep_2\r
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x02\r
-USBFS_ep_2__INTC_NUMBER EQU 1\r
+USBFS_ep_2__INTC_MASK EQU 0x04\r
+USBFS_ep_2__INTC_NUMBER EQU 2\r
USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
CYDEV_ECC_ENABLE EQU 0\r
CYDEV_HEAP_SIZE EQU 0x1000\r
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x00000000\r
+CYDEV_INTR_RISING EQU 0x00000001\r
CYDEV_PROJ_TYPE EQU 2\r
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
#include <USBFS_midi.h>\r
#include <USBFS_pvt.h>\r
#include <Bootloadable_1.h>\r
+#include <SCSI_CMD_TIMER.h>\r
+#include <SCSI_CMD_TIMER_ISR.h>\r
#include <USBFS_Dm_aliases.h>\r
#include <USBFS_Dm.h>\r
#include <USBFS_Dp_aliases.h>\r
<?xml version="1.0" encoding="utf-8"?>\r
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
- <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ </block>\r
+ <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_CMD_TIMER_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_CMD_TIMER" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <register name="SCSI_CMD_TIMER_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">\r
+ <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />\r
+ </register>\r
+ <register name="SCSI_CMD_TIMER_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">\r
+ <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />\r
+ <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">\r
+ <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />\r
+ <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />\r
+ </field>\r
+ <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />\r
+ <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />\r
+ <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />\r
+ <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">\r
+ <value name="Timer" value="0" desc="CMP and TC are output." />\r
+ <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />\r
+ </field>\r
+ <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />\r
+ </register>\r
+ <register name="SCSI_CMD_TIMER_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">\r
+ <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />\r
+ <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">\r
+ <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />\r
+ <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />\r
+ </field>\r
+ <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />\r
+ <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />\r
+ <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />\r
+ <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />\r
+ </register>\r
+ <register name="SCSI_CMD_TIMER_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">\r
+ <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">\r
+ <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />\r
+ <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />\r
+ <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />\r
+ <value name="Irq" value="11" desc="Timer runs until IRQ." />\r
+ </field>\r
+ <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />\r
+ <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />\r
+ <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">\r
+ <value name="Equal" value="0" desc="Compare Equal " />\r
+ <value name="Less than" value="1" desc="Compare Less Than " />\r
+ <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />\r
+ <value name="Greater" value="11" desc="Compare Greater Than ." />\r
+ <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />\r
+ </field>\r
+ <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />\r
+ </register>\r
+ <register name="SCSI_CMD_TIMER_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />\r
+ <register name="SCSI_CMD_TIMER_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />\r
+ </block>\r
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">\r
<block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />\r
</block>\r
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- </block>\r
- <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_Init_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SD_Clk_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" />\r
+ <register name="SD_Clk_Ctl_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />\r
</block>\r
- <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_CTL_IO" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_CTL_IO_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />\r
+ <register name="SCSI_CTL_IO_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />\r
</block>\r
+ <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
</blockRegMap>
\ No newline at end of file
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
<filters />\r
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CMD_TIMER" persistent="">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
+<dependencies>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CMD_TIMER.c" persistent=".\Generated_Source\PSoC5\SCSI_CMD_TIMER.c">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="ARM_C_FILE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
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<addressUnitBits>8</addressUnitBits>\r
<width>32</width>\r
<peripherals>\r
+ <peripheral>\r
+ <name>SCSI_CMD_TIMER</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x400043A3</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0xB64</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_CMD_TIMER_GLOBAL_ENABLE</name>\r
+ <description>PM.ACT.CFG</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>en_timer</name>\r
+ <description>Enable timer/counters.</description>\r
+ <lsb>0</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SCSI_CMD_TIMER_CONTROL</name>\r
+ <description>TMRx.CFG0</description>\r
+ <addressOffset>0xB5D</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>EN</name>\r
+ <description>Enables timer/comparator.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>MODE</name>\r
+ <description>Mode. (0 = Timer; 1 = Comparator)</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Timer</name>\r
+ <description>Timer mode. CNT/CMP register holds timer count value.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Comparator</name>\r
+ <description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>ONESHOT</name>\r
+ <description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>CMP_BUFF</name>\r
+ <description>Buffer compare register. Compare register updates only on timer terminal count.</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>INV</name>\r
+ <description>Invert sense of TIMEREN signal</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DB</name>\r
+ <description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Timer</name>\r
+ <description>CMP and TC are output.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Deadband</name>\r
+ <description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>DEADBAND_PERIOD</name>\r
+ <description>Deadband Period</description>\r
+ <lsb>6</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SCSI_CMD_TIMER_CONTROL2</name>\r
+ <description>TMRx.CFG1</description>\r
+ <addressOffset>0xB5E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>IRQ_SEL</name>\r
+ <description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>FTC</name>\r
+ <description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Disable_FTC</name>\r
+ <description>Disable the single cycle pulse, which signifies the timer is starting.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Enable_FTC</name>\r
+ <description>Enable the single cycle pulse, which signifies the timer is starting.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>DCOR</name>\r
+ <description>Disable Clear on Read (DCOR) of Status Register SR0.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DBMODE</name>\r
+ <description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>CLK_BUS_EN_SEL</name>\r
+ <description>Digital Global Clock selection.</description>\r
+ <lsb>4</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUS_CLK_SEL</name>\r
+ <description>Bus Clock selection.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SCSI_CMD_TIMER_CONTROL3_</name>\r
+ <description>TMRx.CFG2</description>\r
+ <addressOffset>0xB5F</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>TMR_CFG</name>\r
+ <description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>\r
+ <lsb>0</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Continuous</name>\r
+ <description>Timer runs while EN bit of CFG0 register is set to '1'.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Pulsewidth</name>\r
+ <description>Timer runs from positive to negative edge of TIMEREN.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Period</name>\r
+ <description>Timer runs from positive to positive edge of TIMEREN.</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Irq</name>\r
+ <description>Timer runs until IRQ.</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>COD</name>\r
+ <description>Clear On Disable (COD). Clears or gates outputs to zero.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ROD</name>\r
+ <description>Reset On Disable (ROD). Resets internal state of output logic</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>CMP_CFG</name>\r
+ <description>Comparator configurations</description>\r
+ <lsb>4</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Equal</name>\r
+ <description>Compare Equal </description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Less_than</name>\r
+ <description>Compare Less Than </description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Less_than_or_equal</name>\r
+ <description>Compare Less Than or Equal .</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Greater</name>\r
+ <description>Compare Greater Than .</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Greater_than_or_equal</name>\r
+ <description>Compare Greater Than or Equal </description>\r
+ <value>4</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>HW_EN</name>\r
+ <description>When set Timer Enable controls counting.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>SCSI_CMD_TIMER_PERIOD</name>\r
+ <description>TMRx.PER0 - Assigned Period</description>\r
+ <addressOffset>0xB61</addressOffset>\r
+ <size>16</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>SCSI_CMD_TIMER_COUNTER</name>\r
+ <description>TMRx.CNT_CMP0 - Current Down Counter Value</description>\r
+ <addressOffset>0xB63</addressOffset>\r
+ <size>16</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
<peripheral>\r
<name>USBFS</name>\r
<description>USBFS</description>\r
<peripheral>\r
<name>SD_Clk_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000647A</baseAddress>\r
+ <baseAddress>0x4000647C</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x1</size>\r
<peripheral>\r
<name>SCSI_CTL_IO</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000647B</baseAddress>\r
+ <baseAddress>0x40006471</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x1</size>\r
\r
static void doReserveRelease(void);\r
\r
+static uint8_t CmdTimerComplete = 0;\r
+CY_ISR(CommandTimerISR)\r
+{\r
+ CmdTimerComplete = 1;\r
+}\r
+\r
static void enter_BusFree()\r
{\r
- // TODO MPC3000 testing.\r
+ // Spin until the 10us timer has stopped.\r
+ // Required for Akai MPC3000, and possibly other broken controllers.\r
// 1,2us: Cannot see SCSI device.\r
// 5us: Can see SCSI device, format fails\r
// 10us: Format succeeds.\r
// 25us: Format fails.\r
- CyDelayUs(10);\r
-\r
-\r
-\r
-\r
+ while (!CmdTimerComplete) {}\r
+ SCSI_CMD_TIMER_Stop();\r
+ \r
SCSI_ClearPin(SCSI_Out_BSY);\r
// We now have a Bus Clear Delay of 800ns to release remaining signals.\r
SCSI_ClearPin(SCSI_Out_MSG);\r
scsiDev.sense.code = NO_SENSE;\r
scsiDev.sense.asc = NO_ADDITIONAL_SENSE_INFORMATION;\r
scsiDiskReset();\r
+ \r
+ SCSI_CMD_TIMER_Stop();\r
\r
// Sleep to allow the bus to settle down a bit.\r
// We must be ready again within the "Reset to selection time" of\r
// for our BSY response, which is actually a very generous 250ms)\r
SCSI_SetPin(SCSI_Out_BSY);\r
ledOn();\r
+ \r
+ // Used in enter_BusFree() to ensure each command takes at least 10us.\r
+ // as required by some old SCSI controllers (MPC3000).\r
+ CmdTimerComplete = 0;\r
+ SCSI_CMD_TIMER_Enable();\r
\r
#ifdef MM_DEBUG\r
scsiDev.selCount++;\r
\r
void scsiInit()\r
{\r
+ SCSI_CMD_TIMER_Init(); // config but don't start the timeout counter\r
+ SCSI_CMD_TIMER_ISR_StartEx(CommandTimerISR); // setup timer interrupt sub-routine\r
+ \r
scsiDev.scsiIdMask = 1 << (config->scsiId);\r
\r
scsiDev.atnFlag = 0;\r
// Set this to true to log SCSI commands and status information via
// USB HID packets. The can be captured and viewed in wireshark.
// For windows users, capture using USBPcap http://desowin.org/usbpcap/
-#define MM_DEBUG 0
+#define MM_DEBUG 1
#include "geometry.h"
#include "sense.h"
projects / SCSI2SD.git / commitdiff