201408XX 3.6
- Fix handling requests for LUNs other than 0 from SCSI-2 hosts.
- - Handle glitches of the ACK line to improve stability and operate with
+ - Handle glitches of the scsi signals to improve stability and operate with
multiple devices on the SCSI bus.
- Re-add parity checking. This can be disabled using scsi2sd-config if
required.
debugBuffer[14] = scsiDev.lastStatus;\r
debugBuffer[15] = scsiDev.lastSense;\r
debugBuffer[16] = scsiDev.phase;\r
- debugBuffer[17] = SCSI_ReadPin(SCSI_In_BSY);\r
- debugBuffer[18] = SCSI_ReadPin(SCSI_In_SEL);\r
- debugBuffer[19] = SCSI_ReadPin(SCSI_ATN_INT);\r
- debugBuffer[20] = SCSI_ReadPin(SCSI_RST_INT);\r
+ debugBuffer[17] = SCSI_ReadFilt(SCSI_Filt_BSY);\r
+ debugBuffer[18] = SCSI_ReadFilt(SCSI_Filt_SEL);\r
+ debugBuffer[19] = SCSI_ReadFilt(SCSI_Filt_ATN);\r
+ debugBuffer[20] = SCSI_ReadFilt(SCSI_Filt_RST);\r
debugBuffer[21] = scsiDev.rstCount;\r
debugBuffer[22] = scsiDev.selCount;\r
debugBuffer[23] = scsiDev.msgCount;\r
\r
static void process_SelectionPhase()\r
{\r
- int sel = SCSI_ReadPin(SCSI_In_SEL);\r
- int bsy = SCSI_ReadPin(SCSI_In_BSY);\r
+ int sel = SCSI_ReadFilt(SCSI_Filt_SEL);\r
+ int bsy = SCSI_ReadFilt(SCSI_Filt_BSY);\r
\r
// Only read these pins AFTER SEL and BSY - we don't want to catch them\r
// during a transition period.\r
// Do we enter MESSAGE OUT immediately ? SCSI 1 and 2 standards says\r
// move to MESSAGE OUT if ATN is true before we assert BSY.\r
// The initiator should assert ATN with SEL.\r
- scsiDev.atnFlag = SCSI_ReadPin(SCSI_ATN_INT);\r
+ scsiDev.atnFlag = SCSI_ReadFilt(SCSI_Filt_ATN);\r
\r
// Unit attention breaks many older SCSI hosts. Disable it completely for\r
// SCSI-1 (and older) hosts, regardless of our configured setting.\r
// Wait until the end of the selection phase.\r
while (!scsiDev.resetFlag)\r
{\r
- if (!SCSI_ReadPin(SCSI_In_SEL))\r
+ if (!SCSI_ReadFilt(SCSI_Filt_SEL))\r
{\r
break;\r
}\r
// Skip the remaining message bytes, and then start the MESSAGE_OUT\r
// phase again from the start. The initiator will re-send the\r
// same set of messages.\r
- while (SCSI_ReadPin(SCSI_ATN_INT) && !scsiDev.resetFlag)\r
+ while (SCSI_ReadFilt(SCSI_Filt_ATN) && !scsiDev.resetFlag)\r
{\r
scsiReadByte();\r
}\r
}\r
\r
// Re-check the ATN flag in case it stays asserted.\r
- scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
+ scsiDev.atnFlag |= SCSI_ReadFilt(SCSI_Filt_ATN);\r
}\r
\r
void scsiPoll(void)\r
if (scsiDev.resetFlag)\r
{\r
scsiReset();\r
- if ((scsiDev.resetFlag = SCSI_ReadPin(SCSI_RST_INT)))\r
+ if ((scsiDev.resetFlag = SCSI_ReadFilt(SCSI_Filt_RST)))\r
{\r
// Still in reset phase. Do not try and process any commands.\r
return;\r
switch (scsiDev.phase)\r
{\r
case BUS_FREE:\r
- if (SCSI_ReadPin(SCSI_In_BSY))\r
+ if (SCSI_ReadFilt(SCSI_Filt_BSY))\r
{\r
scsiDev.phase = BUS_BUSY;\r
}\r
// one initiator in the chain. Support this by moving\r
// straight to selection if SEL is asserted.\r
// ie. the initiator won't assert BSY and it's own ID before moving to selection.\r
- else if (SCSI_ReadPin(SCSI_In_SEL))\r
+ else if (SCSI_ReadFilt(SCSI_Filt_SEL))\r
{\r
enter_SelectionPhase();\r
}\r
case BUS_BUSY:\r
// Someone is using the bus. Perhaps they are trying to\r
// select us.\r
- if (SCSI_ReadPin(SCSI_In_SEL))\r
+ if (SCSI_ReadFilt(SCSI_Filt_SEL))\r
{\r
enter_SelectionPhase();\r
}\r
- else if (!SCSI_ReadPin(SCSI_In_BSY))\r
+ else if (!SCSI_ReadFilt(SCSI_Filt_BSY))\r
{\r
scsiDev.phase = BUS_FREE;\r
}\r
break;\r
\r
case DATA_IN:\r
- scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
+ scsiDev.atnFlag |= SCSI_ReadFilt(SCSI_Filt_ATN);\r
if (scsiDev.atnFlag)\r
{\r
process_MessageOut();\r
break;\r
\r
case DATA_OUT:\r
- scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
+ scsiDev.atnFlag |= SCSI_ReadFilt(SCSI_Filt_ATN);\r
if (scsiDev.atnFlag)\r
{\r
process_MessageOut();\r
break;\r
\r
case STATUS:\r
- scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
+ scsiDev.atnFlag |= SCSI_ReadFilt(SCSI_Filt_ATN);\r
if (scsiDev.atnFlag)\r
{\r
process_MessageOut();\r
break;\r
\r
case MESSAGE_IN:\r
- scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
+ scsiDev.atnFlag |= SCSI_ReadFilt(SCSI_Filt_ATN);\r
if (scsiDev.atnFlag)\r
{\r
process_MessageOut();\r
CY_ISR(scsiResetISR)\r
{\r
scsiDev.resetFlag = 1;\r
- SCSI_RST_ClearInterrupt();\r
}\r
\r
uint8_t\r
scsiPhyInitDMA();\r
\r
SCSI_RST_ISR_StartEx(scsiResetISR);\r
-\r
- // Interrupts may have already been directed to the (empty)\r
- // standard ISR generated by PSoC Creator.\r
- SCSI_RST_ClearInterrupt();\r
}\r
#define SCSI_ReadPin(pin) \
(CyPins_ReadPin((pin)) == 0)
+// These signals go through a glitch filter - we do not access the pin
+// directly
+enum FilteredInputs
+{
+ SCSI_Filt_ATN = 0x01,
+ SCSI_Filt_BSY = 0x02,
+ SCSI_Filt_SEL = 0x04,
+ SCSI_Filt_RST = 0x08,
+ SCSI_Filt_ACK = 0x10
+};
+#define SCSI_ReadFilt(filt) \
+ ((SCSI_Filtered_Read() & (filt)) == 0)
+
// Contains the odd-parity flag for a given 8-bit value.
extern const uint8_t Lookup_OddParity[256];
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Filtered.c
+* Version 1.80
+*
+* Description:
+* This file contains API to enable firmware to read the value of a Status
+* Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Filtered.h"
+
+#if !defined(SCSI_Filtered_sts_sts_reg__REMOVED) /* Check for removal by optimization */
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_Read
+********************************************************************************
+*
+* Summary:
+* Reads the current value assigned to the Status Register.
+*
+* Parameters:
+* None.
+*
+* Return:
+* The current value in the Status Register.
+*
+*******************************************************************************/
+uint8 SCSI_Filtered_Read(void)
+{
+ return SCSI_Filtered_Status;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_InterruptEnable
+********************************************************************************
+*
+* Summary:
+* Enables the Status Register interrupt.
+*
+* Parameters:
+* None.
+*
+* Return:
+* None.
+*
+*******************************************************************************/
+void SCSI_Filtered_InterruptEnable(void)
+{
+ uint8 interruptState;
+ interruptState = CyEnterCriticalSection();
+ SCSI_Filtered_Status_Aux_Ctrl |= SCSI_Filtered_STATUS_INTR_ENBL;
+ CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_InterruptDisable
+********************************************************************************
+*
+* Summary:
+* Disables the Status Register interrupt.
+*
+* Parameters:
+* None.
+*
+* Return:
+* None.
+*
+*******************************************************************************/
+void SCSI_Filtered_InterruptDisable(void)
+{
+ uint8 interruptState;
+ interruptState = CyEnterCriticalSection();
+ SCSI_Filtered_Status_Aux_Ctrl &= (uint8)(~SCSI_Filtered_STATUS_INTR_ENBL);
+ CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_WriteMask
+********************************************************************************
+*
+* Summary:
+* Writes the current mask value assigned to the Status Register.
+*
+* Parameters:
+* mask: Value to write into the mask register.
+*
+* Return:
+* None.
+*
+*******************************************************************************/
+void SCSI_Filtered_WriteMask(uint8 mask)
+{
+ #if(SCSI_Filtered_INPUTS < 8u)
+ mask &= (uint8)((((uint8)1u) << SCSI_Filtered_INPUTS) - 1u);
+ #endif /* End SCSI_Filtered_INPUTS < 8u */
+ SCSI_Filtered_Status_Mask = mask;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_ReadMask
+********************************************************************************
+*
+* Summary:
+* Reads the current interrupt mask assigned to the Status Register.
+*
+* Parameters:
+* None.
+*
+* Return:
+* The value of the interrupt mask of the Status Register.
+*
+*******************************************************************************/
+uint8 SCSI_Filtered_ReadMask(void)
+{
+ return SCSI_Filtered_Status_Mask;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Filtered.h
+* Version 1.80
+*
+* Description:
+* This file containts Status Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_STATUS_REG_SCSI_Filtered_H) /* CY_STATUS_REG_SCSI_Filtered_H */
+#define CY_STATUS_REG_SCSI_Filtered_H
+
+#include "cytypes.h"
+#include "CyLib.h"
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+uint8 SCSI_Filtered_Read(void) ;
+void SCSI_Filtered_InterruptEnable(void) ;
+void SCSI_Filtered_InterruptDisable(void) ;
+void SCSI_Filtered_WriteMask(uint8 mask) ;
+uint8 SCSI_Filtered_ReadMask(void) ;
+
+
+/***************************************
+* API Constants
+***************************************/
+
+#define SCSI_Filtered_STATUS_INTR_ENBL 0x10u
+
+
+/***************************************
+* Parameter Constants
+***************************************/
+
+/* Status Register Inputs */
+#define SCSI_Filtered_INPUTS 5
+
+
+/***************************************
+* Registers
+***************************************/
+
+/* Status Register */
+#define SCSI_Filtered_Status (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG )
+#define SCSI_Filtered_Status_PTR ( (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG )
+#define SCSI_Filtered_Status_Mask (* (reg8 *) SCSI_Filtered_sts_sts_reg__MASK_REG )
+#define SCSI_Filtered_Status_Aux_Ctrl (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG )
+
+#endif /* End CY_STATUS_REG_SCSI_Filtered_H */
+
+
+/* [] END OF FILE */
#define SCSI_In_2 SCSI_In__2__PC\r
#define SCSI_In_3 SCSI_In__3__PC\r
#define SCSI_In_4 SCSI_In__4__PC\r
-#define SCSI_In_5 SCSI_In__5__PC\r
-#define SCSI_In_6 SCSI_In__6__PC\r
-#define SCSI_In_7 SCSI_In__7__PC\r
\r
#define SCSI_In_DBP SCSI_In__DBP__PC\r
-#define SCSI_In_BSY SCSI_In__BSY__PC\r
-#define SCSI_In_ACK SCSI_In__ACK__PC\r
#define SCSI_In_MSG SCSI_In__MSG__PC\r
-#define SCSI_In_SEL SCSI_In__SEL__PC\r
#define SCSI_In_CD SCSI_In__CD__PC\r
#define SCSI_In_REQ SCSI_In__REQ__PC\r
#define SCSI_In_IO SCSI_In__IO__PC\r
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Noise.h
+* Version 1.90
+*
+* Description:
+* This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SCSI_Noise_ALIASES_H) /* Pins SCSI_Noise_ALIASES_H */
+#define CY_PINS_SCSI_Noise_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+* Constants
+***************************************/
+#define SCSI_Noise_0 SCSI_Noise__0__PC
+#define SCSI_Noise_1 SCSI_Noise__1__PC
+#define SCSI_Noise_2 SCSI_Noise__2__PC
+#define SCSI_Noise_3 SCSI_Noise__3__PC
+#define SCSI_Noise_4 SCSI_Noise__4__PC
+
+#define SCSI_Noise_ATN SCSI_Noise__ATN__PC
+#define SCSI_Noise_BSY SCSI_Noise__BSY__PC
+#define SCSI_Noise_SEL SCSI_Noise__SEL__PC
+#define SCSI_Noise_RST SCSI_Noise__RST__PC
+#define SCSI_Noise_ACK SCSI_Noise__ACK__PC
+
+#endif /* End Pins SCSI_Noise_ALIASES_H */
+
+/* [] END OF FILE */
/* SCSI_TX_DMA_COMPLETE */\r
#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x04u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 2u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u\r
#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* SD_RX_DMA_COMPLETE */\r
#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SD_RX_DMA_COMPLETE__INTC_MASK 0x08u\r
-#define SD_RX_DMA_COMPLETE__INTC_NUMBER 3u\r
+#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u\r
+#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u\r
#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* SD_TX_DMA_COMPLETE */\r
#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SD_TX_DMA_COMPLETE__INTC_MASK 0x10u\r
-#define SD_TX_DMA_COMPLETE__INTC_NUMBER 4u\r
+#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u\r
+#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u\r
#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5\r
#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* SCSI_Parity_Error */\r
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB10_11_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB10_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB10_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB07_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB07_ST\r
\r
/* USBFS_bus_reset */\r
#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+\r
+/* SCSI_Filtered */\r
+#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u\r
+#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST\r
+#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
+#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
+#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
+#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
+#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
+#define SCSI_Filtered_sts_sts_reg__3__POS 3\r
+#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
+#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
+#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB00_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB00_ST\r
\r
/* SCSI_Out_Bits */\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
\r
/* USBFS_arb_int */\r
#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
/* SCSI_Out_Ctl */\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
/* SCSI_RST_ISR */\r
#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_RST_ISR__INTC_MASK 0x400u\r
-#define SCSI_RST_ISR__INTC_NUMBER 10u\r
+#define SCSI_RST_ISR__INTC_MASK 0x04u\r
+#define SCSI_RST_ISR__INTC_NUMBER 2u\r
#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u\r
-#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_10\r
+#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB05_ST\r
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB06_07_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB06_07_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB06_07_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB06_07_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB06_07_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB06_07_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB06_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB06_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB06_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB06_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB06_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB06_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB06_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB06_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB06_F1\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB06_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB06_ST\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB05_06_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB05_06_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB05_06_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB05_06_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB05_06_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB05_06_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB05_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB05_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB05_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB05_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB05_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB05_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB05_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB05_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB05_F1\r
\r
/* USBFS_dp_int */\r
#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
#define timer_clock__PM_STBY_MSK 0x04u\r
\r
+/* SCSI_Noise */\r
+#define SCSI_Noise__0__AG CYREG_PRT12_AG\r
+#define SCSI_Noise__0__BIE CYREG_PRT12_BIE\r
+#define SCSI_Noise__0__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_Noise__0__BYP CYREG_PRT12_BYP\r
+#define SCSI_Noise__0__DM0 CYREG_PRT12_DM0\r
+#define SCSI_Noise__0__DM1 CYREG_PRT12_DM1\r
+#define SCSI_Noise__0__DM2 CYREG_PRT12_DM2\r
+#define SCSI_Noise__0__DR CYREG_PRT12_DR\r
+#define SCSI_Noise__0__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_Noise__0__MASK 0x20u\r
+#define SCSI_Noise__0__PC CYREG_PRT12_PC5\r
+#define SCSI_Noise__0__PORT 12u\r
+#define SCSI_Noise__0__PRT CYREG_PRT12_PRT\r
+#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_Noise__0__PS CYREG_PRT12_PS\r
+#define SCSI_Noise__0__SHIFT 5\r
+#define SCSI_Noise__0__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_Noise__0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_Noise__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_Noise__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_Noise__0__SLW CYREG_PRT12_SLW\r
+#define SCSI_Noise__1__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__1__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__1__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__1__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__1__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__1__MASK 0x10u\r
+#define SCSI_Noise__1__PC CYREG_PRT6_PC4\r
+#define SCSI_Noise__1__PORT 6u\r
+#define SCSI_Noise__1__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__1__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__1__SHIFT 4\r
+#define SCSI_Noise__1__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__2__AG CYREG_PRT5_AG\r
+#define SCSI_Noise__2__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_Noise__2__BIE CYREG_PRT5_BIE\r
+#define SCSI_Noise__2__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_Noise__2__BYP CYREG_PRT5_BYP\r
+#define SCSI_Noise__2__CTL CYREG_PRT5_CTL\r
+#define SCSI_Noise__2__DM0 CYREG_PRT5_DM0\r
+#define SCSI_Noise__2__DM1 CYREG_PRT5_DM1\r
+#define SCSI_Noise__2__DM2 CYREG_PRT5_DM2\r
+#define SCSI_Noise__2__DR CYREG_PRT5_DR\r
+#define SCSI_Noise__2__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_Noise__2__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_Noise__2__MASK 0x01u\r
+#define SCSI_Noise__2__PC CYREG_PRT5_PC0\r
+#define SCSI_Noise__2__PORT 5u\r
+#define SCSI_Noise__2__PRT CYREG_PRT5_PRT\r
+#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_Noise__2__PS CYREG_PRT5_PS\r
+#define SCSI_Noise__2__SHIFT 0\r
+#define SCSI_Noise__2__SLW CYREG_PRT5_SLW\r
+#define SCSI_Noise__3__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__3__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__3__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__3__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__3__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__3__MASK 0x40u\r
+#define SCSI_Noise__3__PC CYREG_PRT6_PC6\r
+#define SCSI_Noise__3__PORT 6u\r
+#define SCSI_Noise__3__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__3__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__3__SHIFT 6\r
+#define SCSI_Noise__3__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__4__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__4__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__4__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__4__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__4__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__4__MASK 0x20u\r
+#define SCSI_Noise__4__PC CYREG_PRT6_PC5\r
+#define SCSI_Noise__4__PORT 6u\r
+#define SCSI_Noise__4__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__4__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__4__SHIFT 5\r
+#define SCSI_Noise__4__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__ACK__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__ACK__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__ACK__MASK 0x20u\r
+#define SCSI_Noise__ACK__PC CYREG_PRT6_PC5\r
+#define SCSI_Noise__ACK__PORT 6u\r
+#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__ACK__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__ACK__SHIFT 5\r
+#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__ATN__AG CYREG_PRT12_AG\r
+#define SCSI_Noise__ATN__BIE CYREG_PRT12_BIE\r
+#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_Noise__ATN__BYP CYREG_PRT12_BYP\r
+#define SCSI_Noise__ATN__DM0 CYREG_PRT12_DM0\r
+#define SCSI_Noise__ATN__DM1 CYREG_PRT12_DM1\r
+#define SCSI_Noise__ATN__DM2 CYREG_PRT12_DM2\r
+#define SCSI_Noise__ATN__DR CYREG_PRT12_DR\r
+#define SCSI_Noise__ATN__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_Noise__ATN__MASK 0x20u\r
+#define SCSI_Noise__ATN__PC CYREG_PRT12_PC5\r
+#define SCSI_Noise__ATN__PORT 12u\r
+#define SCSI_Noise__ATN__PRT CYREG_PRT12_PRT\r
+#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_Noise__ATN__PS CYREG_PRT12_PS\r
+#define SCSI_Noise__ATN__SHIFT 5\r
+#define SCSI_Noise__ATN__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_Noise__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_Noise__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_Noise__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_Noise__ATN__SLW CYREG_PRT12_SLW\r
+#define SCSI_Noise__BSY__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__BSY__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__BSY__MASK 0x10u\r
+#define SCSI_Noise__BSY__PC CYREG_PRT6_PC4\r
+#define SCSI_Noise__BSY__PORT 6u\r
+#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__BSY__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__BSY__SHIFT 4\r
+#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__RST__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__RST__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__RST__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__RST__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__RST__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__RST__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__RST__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__RST__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__RST__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__RST__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__RST__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__RST__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__RST__MASK 0x40u\r
+#define SCSI_Noise__RST__PC CYREG_PRT6_PC6\r
+#define SCSI_Noise__RST__PORT 6u\r
+#define SCSI_Noise__RST__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__RST__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__RST__SHIFT 6\r
+#define SCSI_Noise__RST__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__SEL__AG CYREG_PRT5_AG\r
+#define SCSI_Noise__SEL__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_Noise__SEL__BIE CYREG_PRT5_BIE\r
+#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_Noise__SEL__BYP CYREG_PRT5_BYP\r
+#define SCSI_Noise__SEL__CTL CYREG_PRT5_CTL\r
+#define SCSI_Noise__SEL__DM0 CYREG_PRT5_DM0\r
+#define SCSI_Noise__SEL__DM1 CYREG_PRT5_DM1\r
+#define SCSI_Noise__SEL__DM2 CYREG_PRT5_DM2\r
+#define SCSI_Noise__SEL__DR CYREG_PRT5_DR\r
+#define SCSI_Noise__SEL__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_Noise__SEL__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_Noise__SEL__MASK 0x01u\r
+#define SCSI_Noise__SEL__PC CYREG_PRT5_PC0\r
+#define SCSI_Noise__SEL__PORT 5u\r
+#define SCSI_Noise__SEL__PRT CYREG_PRT5_PRT\r
+#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_Noise__SEL__PS CYREG_PRT5_PS\r
+#define SCSI_Noise__SEL__SHIFT 0\r
+#define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW\r
+\r
/* scsiTarget */\r
#define scsiTarget_StatusReg__0__MASK 0x01u\r
#define scsiTarget_StatusReg__0__POS 0\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__4__MASK 0x10u\r
#define scsiTarget_StatusReg__4__POS 4\r
#define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK\r
-#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
-#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL\r
-#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB04_MSK\r
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB04_ST\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB04_CTL\r
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB04_CTL\r
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB04_MSK\r
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB04_05_A0\r
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB04_05_A1\r
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB04_05_D0\r
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB04_05_D1\r
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB04_05_F0\r
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB04_05_F1\r
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB04_A0_A1\r
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB04_A0\r
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB04_A1\r
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB04_D0_D1\r
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB04_D0\r
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB04_D1\r
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB04_F0_F1\r
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB04_F0\r
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB04_F1\r
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK\r
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB12_MSK\r
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB12_ST\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB12_CTL\r
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB12_CTL\r
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB12_MSK\r
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB12_13_A0\r
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB12_13_A1\r
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB12_13_D0\r
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB12_13_D1\r
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB12_13_F0\r
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB12_13_F1\r
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB12_A0_A1\r
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB12_A0\r
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB12_A1\r
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB12_D0_D1\r
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB12_D0\r
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB12_D1\r
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB12_F0_F1\r
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB12_F0\r
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB12_F1\r
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
/* USBFS_ep_1 */\r
#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_1__INTC_MASK 0x20u\r
-#define USBFS_ep_1__INTC_NUMBER 5u\r
+#define USBFS_ep_1__INTC_MASK 0x40u\r
+#define USBFS_ep_1__INTC_NUMBER 6u\r
#define USBFS_ep_1__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_5\r
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6\r
#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_2 */\r
#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_2__INTC_MASK 0x40u\r
-#define USBFS_ep_2__INTC_NUMBER 6u\r
+#define USBFS_ep_2__INTC_MASK 0x80u\r
+#define USBFS_ep_2__INTC_NUMBER 7u\r
#define USBFS_ep_2__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_6\r
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7\r
#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_3 */\r
#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_3__INTC_MASK 0x80u\r
-#define USBFS_ep_3__INTC_NUMBER 7u\r
+#define USBFS_ep_3__INTC_MASK 0x100u\r
+#define USBFS_ep_3__INTC_NUMBER 8u\r
#define USBFS_ep_3__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_7\r
+#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8\r
#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_4 */\r
#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_4__INTC_MASK 0x100u\r
-#define USBFS_ep_4__INTC_NUMBER 8u\r
+#define USBFS_ep_4__INTC_MASK 0x200u\r
+#define USBFS_ep_4__INTC_NUMBER 9u\r
#define USBFS_ep_4__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_8\r
+#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_9\r
#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN\r
\r
-/* SCSI_ATN */\r
-#define SCSI_ATN__0__MASK 0x20u\r
-#define SCSI_ATN__0__PC CYREG_PRT12_PC5\r
-#define SCSI_ATN__0__PORT 12u\r
-#define SCSI_ATN__0__SHIFT 5\r
-#define SCSI_ATN__AG CYREG_PRT12_AG\r
-#define SCSI_ATN__BIE CYREG_PRT12_BIE\r
-#define SCSI_ATN__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_ATN__BYP CYREG_PRT12_BYP\r
-#define SCSI_ATN__DM0 CYREG_PRT12_DM0\r
-#define SCSI_ATN__DM1 CYREG_PRT12_DM1\r
-#define SCSI_ATN__DM2 CYREG_PRT12_DM2\r
-#define SCSI_ATN__DR CYREG_PRT12_DR\r
-#define SCSI_ATN__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_ATN__INT__MASK 0x20u\r
-#define SCSI_ATN__INT__PC CYREG_PRT12_PC5\r
-#define SCSI_ATN__INT__PORT 12u\r
-#define SCSI_ATN__INT__SHIFT 5\r
-#define SCSI_ATN__MASK 0x20u\r
-#define SCSI_ATN__PORT 12u\r
-#define SCSI_ATN__PRT CYREG_PRT12_PRT\r
-#define SCSI_ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_ATN__PS CYREG_PRT12_PS\r
-#define SCSI_ATN__SHIFT 5\r
-#define SCSI_ATN__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_ATN__SLW CYREG_PRT12_SLW\r
-\r
/* SCSI_CLK */\r
#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0\r
#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1\r
#define SCSI_Out__SEL__SHIFT 3\r
#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW\r
\r
-/* SCSI_RST */\r
-#define SCSI_RST__0__MASK 0x40u\r
-#define SCSI_RST__0__PC CYREG_PRT6_PC6\r
-#define SCSI_RST__0__PORT 6u\r
-#define SCSI_RST__0__SHIFT 6\r
-#define SCSI_RST__AG CYREG_PRT6_AG\r
-#define SCSI_RST__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_RST__BIE CYREG_PRT6_BIE\r
-#define SCSI_RST__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_RST__BYP CYREG_PRT6_BYP\r
-#define SCSI_RST__CTL CYREG_PRT6_CTL\r
-#define SCSI_RST__DM0 CYREG_PRT6_DM0\r
-#define SCSI_RST__DM1 CYREG_PRT6_DM1\r
-#define SCSI_RST__DM2 CYREG_PRT6_DM2\r
-#define SCSI_RST__DR CYREG_PRT6_DR\r
-#define SCSI_RST__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_RST__INTSTAT CYREG_PICU6_INTSTAT\r
-#define SCSI_RST__INT__MASK 0x40u\r
-#define SCSI_RST__INT__PC CYREG_PRT6_PC6\r
-#define SCSI_RST__INT__PORT 6u\r
-#define SCSI_RST__INT__SHIFT 6\r
-#define SCSI_RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_RST__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_RST__MASK 0x40u\r
-#define SCSI_RST__PORT 6u\r
-#define SCSI_RST__PRT CYREG_PRT6_PRT\r
-#define SCSI_RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_RST__PS CYREG_PRT6_PS\r
-#define SCSI_RST__SHIFT 6\r
-#define SCSI_RST__SLW CYREG_PRT6_SLW\r
-#define SCSI_RST__SNAP CYREG_PICU6_SNAP\r
-\r
/* USBFS_Dm */\r
#define USBFS_Dm__0__MASK 0x80u\r
#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1\r
#define SCSI_In__1__INP_DIS CYREG_PRT6_INP_DIS\r
#define SCSI_In__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
#define SCSI_In__1__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__1__MASK 0x10u\r
-#define SCSI_In__1__PC CYREG_PRT6_PC4\r
+#define SCSI_In__1__MASK 0x80u\r
+#define SCSI_In__1__PC CYREG_PRT6_PC7\r
#define SCSI_In__1__PORT 6u\r
#define SCSI_In__1__PRT CYREG_PRT6_PRT\r
#define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_In__1__PS CYREG_PRT6_PS\r
-#define SCSI_In__1__SHIFT 4\r
+#define SCSI_In__1__SHIFT 7\r
#define SCSI_In__1__SLW CYREG_PRT6_SLW\r
-#define SCSI_In__2__AG CYREG_PRT6_AG\r
-#define SCSI_In__2__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In__2__BIE CYREG_PRT6_BIE\r
-#define SCSI_In__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In__2__BYP CYREG_PRT6_BYP\r
-#define SCSI_In__2__CTL CYREG_PRT6_CTL\r
-#define SCSI_In__2__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In__2__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In__2__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In__2__DR CYREG_PRT6_DR\r
-#define SCSI_In__2__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In__2__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__2__MASK 0x20u\r
-#define SCSI_In__2__PC CYREG_PRT6_PC5\r
-#define SCSI_In__2__PORT 6u\r
-#define SCSI_In__2__PRT CYREG_PRT6_PRT\r
-#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In__2__PS CYREG_PRT6_PS\r
-#define SCSI_In__2__SHIFT 5\r
-#define SCSI_In__2__SLW CYREG_PRT6_SLW\r
-#define SCSI_In__3__AG CYREG_PRT6_AG\r
-#define SCSI_In__3__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In__3__BIE CYREG_PRT6_BIE\r
-#define SCSI_In__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In__3__BYP CYREG_PRT6_BYP\r
-#define SCSI_In__3__CTL CYREG_PRT6_CTL\r
-#define SCSI_In__3__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In__3__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In__3__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In__3__DR CYREG_PRT6_DR\r
-#define SCSI_In__3__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In__3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__3__MASK 0x80u\r
-#define SCSI_In__3__PC CYREG_PRT6_PC7\r
-#define SCSI_In__3__PORT 6u\r
-#define SCSI_In__3__PRT CYREG_PRT6_PRT\r
-#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In__3__PS CYREG_PRT6_PS\r
-#define SCSI_In__3__SHIFT 7\r
-#define SCSI_In__3__SLW CYREG_PRT6_SLW\r
+#define SCSI_In__2__AG CYREG_PRT5_AG\r
+#define SCSI_In__2__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__2__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__2__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__2__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__2__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__2__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__2__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__2__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__2__DR CYREG_PRT5_DR\r
+#define SCSI_In__2__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__2__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__2__MASK 0x02u\r
+#define SCSI_In__2__PC CYREG_PRT5_PC1\r
+#define SCSI_In__2__PORT 5u\r
+#define SCSI_In__2__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__2__PS CYREG_PRT5_PS\r
+#define SCSI_In__2__SHIFT 1\r
+#define SCSI_In__2__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__3__AG CYREG_PRT5_AG\r
+#define SCSI_In__3__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__3__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__3__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__3__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__3__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__3__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__3__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__3__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__3__DR CYREG_PRT5_DR\r
+#define SCSI_In__3__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__3__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__3__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__3__MASK 0x04u\r
+#define SCSI_In__3__PC CYREG_PRT5_PC2\r
+#define SCSI_In__3__PORT 5u\r
+#define SCSI_In__3__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__3__PS CYREG_PRT5_PS\r
+#define SCSI_In__3__SHIFT 2\r
+#define SCSI_In__3__SLW CYREG_PRT5_SLW\r
#define SCSI_In__4__AG CYREG_PRT5_AG\r
#define SCSI_In__4__AMUX CYREG_PRT5_AMUX\r
#define SCSI_In__4__BIE CYREG_PRT5_BIE\r
#define SCSI_In__4__INP_DIS CYREG_PRT5_INP_DIS\r
#define SCSI_In__4__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
#define SCSI_In__4__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__4__MASK 0x01u\r
-#define SCSI_In__4__PC CYREG_PRT5_PC0\r
+#define SCSI_In__4__MASK 0x08u\r
+#define SCSI_In__4__PC CYREG_PRT5_PC3\r
#define SCSI_In__4__PORT 5u\r
#define SCSI_In__4__PRT CYREG_PRT5_PRT\r
#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_In__4__PS CYREG_PRT5_PS\r
-#define SCSI_In__4__SHIFT 0\r
+#define SCSI_In__4__SHIFT 3\r
#define SCSI_In__4__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__5__AG CYREG_PRT5_AG\r
-#define SCSI_In__5__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__5__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__5__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__5__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__5__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__5__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__5__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__5__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__5__DR CYREG_PRT5_DR\r
-#define SCSI_In__5__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__5__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__5__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__5__MASK 0x02u\r
-#define SCSI_In__5__PC CYREG_PRT5_PC1\r
-#define SCSI_In__5__PORT 5u\r
-#define SCSI_In__5__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__5__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__5__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__5__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__5__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__5__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__5__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__5__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__5__PS CYREG_PRT5_PS\r
-#define SCSI_In__5__SHIFT 1\r
-#define SCSI_In__5__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__6__AG CYREG_PRT5_AG\r
-#define SCSI_In__6__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__6__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__6__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__6__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__6__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__6__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__6__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__6__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__6__DR CYREG_PRT5_DR\r
-#define SCSI_In__6__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__6__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__6__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__6__MASK 0x04u\r
-#define SCSI_In__6__PC CYREG_PRT5_PC2\r
-#define SCSI_In__6__PORT 5u\r
-#define SCSI_In__6__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__6__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__6__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__6__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__6__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__6__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__6__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__6__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__6__PS CYREG_PRT5_PS\r
-#define SCSI_In__6__SHIFT 2\r
-#define SCSI_In__6__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__7__AG CYREG_PRT5_AG\r
-#define SCSI_In__7__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__7__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__7__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__7__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__7__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__7__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__7__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__7__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__7__DR CYREG_PRT5_DR\r
-#define SCSI_In__7__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__7__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__7__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__7__MASK 0x08u\r
-#define SCSI_In__7__PC CYREG_PRT5_PC3\r
-#define SCSI_In__7__PORT 5u\r
-#define SCSI_In__7__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__7__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__7__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__7__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__7__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__7__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__7__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__7__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__7__PS CYREG_PRT5_PS\r
-#define SCSI_In__7__SHIFT 3\r
-#define SCSI_In__7__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__ACK__AG CYREG_PRT6_AG\r
-#define SCSI_In__ACK__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In__ACK__BIE CYREG_PRT6_BIE\r
-#define SCSI_In__ACK__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In__ACK__BYP CYREG_PRT6_BYP\r
-#define SCSI_In__ACK__CTL CYREG_PRT6_CTL\r
-#define SCSI_In__ACK__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In__ACK__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In__ACK__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In__ACK__DR CYREG_PRT6_DR\r
-#define SCSI_In__ACK__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In__ACK__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__ACK__MASK 0x20u\r
-#define SCSI_In__ACK__PC CYREG_PRT6_PC5\r
-#define SCSI_In__ACK__PORT 6u\r
-#define SCSI_In__ACK__PRT CYREG_PRT6_PRT\r
-#define SCSI_In__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In__ACK__PS CYREG_PRT6_PS\r
-#define SCSI_In__ACK__SHIFT 5\r
-#define SCSI_In__ACK__SLW CYREG_PRT6_SLW\r
-#define SCSI_In__BSY__AG CYREG_PRT6_AG\r
-#define SCSI_In__BSY__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In__BSY__BIE CYREG_PRT6_BIE\r
-#define SCSI_In__BSY__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In__BSY__BYP CYREG_PRT6_BYP\r
-#define SCSI_In__BSY__CTL CYREG_PRT6_CTL\r
-#define SCSI_In__BSY__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In__BSY__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In__BSY__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In__BSY__DR CYREG_PRT6_DR\r
-#define SCSI_In__BSY__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In__BSY__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__BSY__MASK 0x10u\r
-#define SCSI_In__BSY__PC CYREG_PRT6_PC4\r
-#define SCSI_In__BSY__PORT 6u\r
-#define SCSI_In__BSY__PRT CYREG_PRT6_PRT\r
-#define SCSI_In__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In__BSY__PS CYREG_PRT6_PS\r
-#define SCSI_In__BSY__SHIFT 4\r
-#define SCSI_In__BSY__SLW CYREG_PRT6_SLW\r
#define SCSI_In__CD__AG CYREG_PRT5_AG\r
#define SCSI_In__CD__AMUX CYREG_PRT5_AMUX\r
#define SCSI_In__CD__BIE CYREG_PRT5_BIE\r
#define SCSI_In__REQ__PS CYREG_PRT5_PS\r
#define SCSI_In__REQ__SHIFT 2\r
#define SCSI_In__REQ__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__SEL__AG CYREG_PRT5_AG\r
-#define SCSI_In__SEL__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__SEL__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__SEL__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__SEL__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__SEL__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__SEL__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__SEL__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__SEL__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__SEL__DR CYREG_PRT5_DR\r
-#define SCSI_In__SEL__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__SEL__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__SEL__MASK 0x01u\r
-#define SCSI_In__SEL__PC CYREG_PRT5_PC0\r
-#define SCSI_In__SEL__PORT 5u\r
-#define SCSI_In__SEL__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__SEL__PS CYREG_PRT5_PS\r
-#define SCSI_In__SEL__SHIFT 0\r
-#define SCSI_In__SEL__SLW CYREG_PRT5_SLW\r
\r
/* SD_DAT1 */\r
#define SD_DAT1__0__MASK 0x01u\r
#define CYDEV_ECC_ENABLE 0\r
#define CYDEV_HEAP_SIZE 0x0400\r
#define CYDEV_INSTRUCT_CACHE_ENABLED 1\r
-#define CYDEV_INTR_RISING 0x0000001Eu\r
+#define CYDEV_INTR_RISING 0x0000003Eu\r
#define CYDEV_PROJ_TYPE 2\r
#define CYDEV_PROJ_TYPE_BOOTLOADER 1\r
#define CYDEV_PROJ_TYPE_LOADABLE 2\r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 37u\r
+#define CY_CFG_BASE_ADDR_COUNT 41u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
\r
{\r
static const uint32 CYCODE cy_cfg_addr_table[] = {\r
- 0x40004502u, /* Base address: 0x40004500 Count: 2 */\r
+ 0x40004501u, /* Base address: 0x40004500 Count: 1 */\r
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
- 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */\r
- 0x40006402u, /* Base address: 0x40006400 Count: 2 */\r
- 0x4001004Au, /* Base address: 0x40010000 Count: 74 */\r
- 0x40010137u, /* Base address: 0x40010100 Count: 55 */\r
- 0x4001024Au, /* Base address: 0x40010200 Count: 74 */\r
- 0x4001035Cu, /* Base address: 0x40010300 Count: 92 */\r
- 0x4001043Au, /* Base address: 0x40010400 Count: 58 */\r
- 0x4001055Cu, /* Base address: 0x40010500 Count: 92 */\r
- 0x4001064Eu, /* Base address: 0x40010600 Count: 78 */\r
- 0x40010757u, /* Base address: 0x40010700 Count: 87 */\r
- 0x4001091Au, /* Base address: 0x40010900 Count: 26 */\r
- 0x40010A3Bu, /* Base address: 0x40010A00 Count: 59 */\r
- 0x40010B51u, /* Base address: 0x40010B00 Count: 81 */\r
- 0x40010D23u, /* Base address: 0x40010D00 Count: 35 */\r
- 0x40010E49u, /* Base address: 0x40010E00 Count: 73 */\r
- 0x40010F35u, /* Base address: 0x40010F00 Count: 53 */\r
- 0x4001145Bu, /* Base address: 0x40011400 Count: 91 */\r
- 0x40011543u, /* Base address: 0x40011500 Count: 67 */\r
- 0x4001161Eu, /* Base address: 0x40011600 Count: 30 */\r
- 0x40011750u, /* Base address: 0x40011700 Count: 80 */\r
- 0x4001190Du, /* Base address: 0x40011900 Count: 13 */\r
- 0x40011B03u, /* Base address: 0x40011B00 Count: 3 */\r
- 0x4001401Bu, /* Base address: 0x40014000 Count: 27 */\r
- 0x40014119u, /* Base address: 0x40014100 Count: 25 */\r
- 0x4001420Cu, /* Base address: 0x40014200 Count: 12 */\r
- 0x4001430Eu, /* Base address: 0x40014300 Count: 14 */\r
- 0x4001440Eu, /* Base address: 0x40014400 Count: 14 */\r
+ 0x4000520Bu, /* Base address: 0x40005200 Count: 11 */\r
+ 0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
+ 0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
+ 0x40010047u, /* Base address: 0x40010000 Count: 71 */\r
+ 0x4001013Fu, /* Base address: 0x40010100 Count: 63 */\r
+ 0x40010249u, /* Base address: 0x40010200 Count: 73 */\r
+ 0x40010354u, /* Base address: 0x40010300 Count: 84 */\r
+ 0x40010453u, /* Base address: 0x40010400 Count: 83 */\r
+ 0x4001054Fu, /* Base address: 0x40010500 Count: 79 */\r
+ 0x40010651u, /* Base address: 0x40010600 Count: 81 */\r
+ 0x40010747u, /* Base address: 0x40010700 Count: 71 */\r
+ 0x4001090Bu, /* Base address: 0x40010900 Count: 11 */\r
+ 0x40010A4Au, /* Base address: 0x40010A00 Count: 74 */\r
+ 0x40010B4Au, /* Base address: 0x40010B00 Count: 74 */\r
+ 0x40010C39u, /* Base address: 0x40010C00 Count: 57 */\r
+ 0x40010D5Cu, /* Base address: 0x40010D00 Count: 92 */\r
+ 0x40010E44u, /* Base address: 0x40010E00 Count: 68 */\r
+ 0x40010F3Bu, /* Base address: 0x40010F00 Count: 59 */\r
+ 0x40011465u, /* Base address: 0x40011400 Count: 101 */\r
+ 0x4001154Fu, /* Base address: 0x40011500 Count: 79 */\r
+ 0x40011650u, /* Base address: 0x40011600 Count: 80 */\r
+ 0x40011744u, /* Base address: 0x40011700 Count: 68 */\r
+ 0x40011804u, /* Base address: 0x40011800 Count: 4 */\r
+ 0x40011907u, /* Base address: 0x40011900 Count: 7 */\r
+ 0x40011B09u, /* Base address: 0x40011B00 Count: 9 */\r
+ 0x40014018u, /* Base address: 0x40014000 Count: 24 */\r
+ 0x4001411Du, /* Base address: 0x40014100 Count: 29 */\r
+ 0x40014210u, /* Base address: 0x40014200 Count: 16 */\r
+ 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */\r
+ 0x40014411u, /* Base address: 0x40014400 Count: 17 */\r
0x40014514u, /* Base address: 0x40014500 Count: 20 */\r
- 0x40014609u, /* Base address: 0x40014600 Count: 9 */\r
+ 0x4001460Du, /* Base address: 0x40014600 Count: 13 */\r
0x4001470Cu, /* Base address: 0x40014700 Count: 12 */\r
- 0x40014805u, /* Base address: 0x40014800 Count: 5 */\r
- 0x4001490Fu, /* Base address: 0x40014900 Count: 15 */\r
- 0x40014C04u, /* Base address: 0x40014C00 Count: 4 */\r
- 0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
+ 0x40014809u, /* Base address: 0x40014800 Count: 9 */\r
+ 0x40014910u, /* Base address: 0x40014900 Count: 16 */\r
+ 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */\r
+ 0x40014D04u, /* Base address: 0x40014D00 Count: 4 */\r
+ 0x40015004u, /* Base address: 0x40015000 Count: 4 */\r
0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
\r
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
- {0x36u, 0x02u},\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
- {0x0Au, 0x27u},\r
- {0x00u, 0x04u},\r
- {0x01u, 0x11u},\r
- {0x18u, 0x04u},\r
+ {0x0Au, 0x36u},\r
+ {0x00u, 0x12u},\r
+ {0x01u, 0x04u},\r
+ {0x18u, 0x08u},\r
{0x1Cu, 0x61u},\r
- {0x20u, 0x68u},\r
- {0x21u, 0xC0u},\r
- {0x2Cu, 0x0Fu},\r
- {0x30u, 0x09u},\r
- {0x31u, 0x0Au},\r
- {0x34u, 0x90u},\r
- {0x64u, 0x20u},\r
+ {0x20u, 0x50u},\r
+ {0x21u, 0x90u},\r
+ {0x2Cu, 0x0Eu},\r
+ {0x30u, 0x0Au},\r
+ {0x31u, 0x09u},\r
+ {0x34u, 0x80u},\r
{0x7Cu, 0x40u},\r
- {0x24u, 0x02u},\r
+ {0x2Cu, 0x02u},\r
{0x86u, 0x0Fu},\r
- {0x03u, 0x80u},\r
- {0x06u, 0x80u},\r
+ {0x02u, 0x10u},\r
+ {0x03u, 0x08u},\r
+ {0x04u, 0x01u},\r
+ {0x06u, 0x02u},\r
{0x07u, 0x07u},\r
- {0x09u, 0x44u},\r
- {0x0Bu, 0x88u},\r
- {0x0Eu, 0x07u},\r
- {0x10u, 0xAAu},\r
- {0x11u, 0xAAu},\r
- {0x12u, 0x55u},\r
- {0x13u, 0x55u},\r
- {0x14u, 0x99u},\r
+ {0x0Bu, 0x70u},\r
+ {0x0Cu, 0x02u},\r
+ {0x0Du, 0x44u},\r
+ {0x0Eu, 0x01u},\r
+ {0x0Fu, 0x88u},\r
+ {0x14u, 0x02u},\r
{0x15u, 0x99u},\r
- {0x16u, 0x22u},\r
+ {0x16u, 0x05u},\r
{0x17u, 0x22u},\r
- {0x1Au, 0x70u},\r
- {0x1Bu, 0x70u},\r
- {0x27u, 0x08u},\r
- {0x28u, 0x44u},\r
- {0x2Au, 0x88u},\r
- {0x2Eu, 0x08u},\r
- {0x30u, 0x0Fu},\r
+ {0x18u, 0x02u},\r
+ {0x1Au, 0x09u},\r
+ {0x1Cu, 0x10u},\r
+ {0x1Du, 0xAAu},\r
+ {0x1Eu, 0x20u},\r
+ {0x1Fu, 0x55u},\r
+ {0x26u, 0x20u},\r
+ {0x28u, 0x02u},\r
+ {0x2Au, 0x01u},\r
+ {0x2Bu, 0x80u},\r
+ {0x30u, 0x04u},\r
+ {0x32u, 0x08u},\r
{0x33u, 0x0Fu},\r
- {0x34u, 0xF0u},\r
+ {0x34u, 0x03u},\r
{0x35u, 0xF0u},\r
- {0x56u, 0x08u},\r
+ {0x36u, 0x30u},\r
+ {0x3Au, 0x20u},\r
+ {0x3Eu, 0x40u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
- {0x5Du, 0x90u},\r
+ {0x5Cu, 0x19u},\r
{0x5Fu, 0x01u},\r
- {0x82u, 0x20u},\r
- {0x84u, 0x02u},\r
- {0x85u, 0x08u},\r
- {0x86u, 0x0Du},\r
- {0x88u, 0x02u},\r
- {0x8Au, 0x04u},\r
- {0x8Bu, 0x19u},\r
- {0x8Cu, 0x0Du},\r
- {0x8Du, 0x33u},\r
- {0x8Fu, 0x4Cu},\r
- {0x90u, 0x10u},\r
- {0x91u, 0x18u},\r
- {0x92u, 0x20u},\r
- {0x93u, 0x60u},\r
- {0x94u, 0x0Du},\r
- {0x99u, 0x2Au},\r
- {0x9Au, 0x10u},\r
- {0x9Bu, 0x55u},\r
- {0x9Cu, 0x0Du},\r
- {0x9Du, 0x01u},\r
- {0x9Fu, 0x06u},\r
- {0xA0u, 0x02u},\r
- {0xA2u, 0x08u},\r
- {0xA3u, 0x10u},\r
- {0xA4u, 0x0Du},\r
- {0xA5u, 0x3Au},\r
- {0xA7u, 0x45u},\r
- {0xA8u, 0x01u},\r
- {0xAAu, 0x02u},\r
- {0xABu, 0x01u},\r
- {0xACu, 0x0Du},\r
- {0xB1u, 0x07u},\r
- {0xB2u, 0x0Fu},\r
- {0xB6u, 0x30u},\r
- {0xB7u, 0x78u},\r
- {0xBAu, 0x08u},\r
- {0xBBu, 0x82u},\r
- {0xBEu, 0x40u},\r
+ {0x81u, 0x02u},\r
+ {0x83u, 0x01u},\r
+ {0x87u, 0x04u},\r
+ {0x8Du, 0x02u},\r
+ {0x8Fu, 0x01u},\r
+ {0x91u, 0x01u},\r
+ {0x92u, 0x02u},\r
+ {0x93u, 0x02u},\r
+ {0x9Au, 0x04u},\r
+ {0x9Cu, 0x04u},\r
+ {0x9Du, 0x02u},\r
+ {0x9Eu, 0x08u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA2u, 0x01u},\r
+ {0xA5u, 0x02u},\r
+ {0xA7u, 0x11u},\r
+ {0xAAu, 0x08u},\r
+ {0xAFu, 0x08u},\r
+ {0xB0u, 0x01u},\r
+ {0xB1u, 0x10u},\r
+ {0xB2u, 0x0Cu},\r
+ {0xB3u, 0x04u},\r
+ {0xB4u, 0x02u},\r
+ {0xB5u, 0x08u},\r
+ {0xB7u, 0x03u},\r
+ {0xBBu, 0x80u},\r
+ {0xBEu, 0x04u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x99u},\r
+ {0xDDu, 0x90u},\r
+ {0xDFu, 0x01u},\r
+ {0x00u, 0x04u},\r
+ {0x01u, 0x01u},\r
+ {0x03u, 0x02u},\r
+ {0x08u, 0x10u},\r
+ {0x0Au, 0x22u},\r
+ {0x0Bu, 0x01u},\r
+ {0x0Du, 0x10u},\r
+ {0x0Eu, 0x80u},\r
+ {0x0Fu, 0x01u},\r
+ {0x11u, 0x24u},\r
+ {0x16u, 0x88u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x10u},\r
+ {0x1Au, 0x21u},\r
+ {0x1Bu, 0x12u},\r
+ {0x1Cu, 0x20u},\r
+ {0x1Eu, 0x80u},\r
+ {0x1Fu, 0x10u},\r
+ {0x20u, 0x08u},\r
+ {0x21u, 0x14u},\r
+ {0x22u, 0x08u},\r
+ {0x24u, 0x02u},\r
+ {0x25u, 0x91u},\r
+ {0x27u, 0x12u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Fu, 0x12u},\r
+ {0x30u, 0x80u},\r
+ {0x31u, 0x04u},\r
+ {0x36u, 0x40u},\r
+ {0x37u, 0x02u},\r
+ {0x38u, 0x80u},\r
+ {0x39u, 0x28u},\r
+ {0x3Bu, 0x02u},\r
+ {0x3Du, 0x02u},\r
+ {0x3Eu, 0x80u},\r
+ {0x3Fu, 0x04u},\r
+ {0x58u, 0x40u},\r
+ {0x5Au, 0x18u},\r
+ {0x5Bu, 0x02u},\r
+ {0x5Cu, 0x80u},\r
+ {0x5Du, 0x20u},\r
+ {0x62u, 0x80u},\r
+ {0x66u, 0xA0u},\r
+ {0x67u, 0x04u},\r
+ {0x80u, 0x80u},\r
+ {0x81u, 0x90u},\r
+ {0x82u, 0x80u},\r
+ {0x84u, 0x10u},\r
+ {0x88u, 0x10u},\r
+ {0x89u, 0x20u},\r
+ {0x8Au, 0x02u},\r
+ {0x8Du, 0x40u},\r
+ {0xC0u, 0x0Du},\r
+ {0xC2u, 0xD7u},\r
+ {0xC4u, 0x56u},\r
+ {0xCAu, 0x54u},\r
+ {0xCCu, 0x9Au},\r
+ {0xCEu, 0xDFu},\r
+ {0xD6u, 0x3Fu},\r
+ {0xD8u, 0x38u},\r
+ {0xE2u, 0x04u},\r
+ {0xE4u, 0x05u},\r
+ {0xE6u, 0xA2u},\r
+ {0x01u, 0x02u},\r
+ {0x02u, 0x10u},\r
+ {0x03u, 0x01u},\r
+ {0x04u, 0x05u},\r
+ {0x05u, 0x02u},\r
+ {0x06u, 0x02u},\r
+ {0x07u, 0x05u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Fu, 0x09u},\r
+ {0x10u, 0x04u},\r
+ {0x11u, 0x01u},\r
+ {0x12u, 0x03u},\r
+ {0x13u, 0x02u},\r
+ {0x14u, 0x01u},\r
+ {0x16u, 0x06u},\r
+ {0x19u, 0x02u},\r
+ {0x1Bu, 0x11u},\r
+ {0x1Eu, 0x08u},\r
+ {0x28u, 0x03u},\r
+ {0x2Au, 0x04u},\r
+ {0x2Cu, 0x08u},\r
+ {0x2Eu, 0x10u},\r
+ {0x30u, 0x07u},\r
+ {0x31u, 0x04u},\r
+ {0x33u, 0x10u},\r
+ {0x34u, 0x18u},\r
+ {0x35u, 0x08u},\r
+ {0x36u, 0x07u},\r
+ {0x37u, 0x03u},\r
+ {0x3Au, 0x82u},\r
+ {0x3Bu, 0x80u},\r
+ {0x3Eu, 0x10u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x90u},\r
+ {0x5Fu, 0x01u},\r
+ {0x80u, 0x05u},\r
+ {0x82u, 0x0Au},\r
+ {0x83u, 0xFFu},\r
+ {0x84u, 0x06u},\r
+ {0x86u, 0x09u},\r
+ {0x89u, 0x55u},\r
+ {0x8Bu, 0xAAu},\r
+ {0x90u, 0x0Fu},\r
+ {0x92u, 0xF0u},\r
+ {0x97u, 0xFFu},\r
+ {0x98u, 0x60u},\r
+ {0x99u, 0x0Fu},\r
+ {0x9Au, 0x90u},\r
+ {0x9Bu, 0xF0u},\r
+ {0x9Cu, 0x03u},\r
+ {0x9Du, 0xFFu},\r
+ {0x9Eu, 0x0Cu},\r
+ {0xA1u, 0x69u},\r
+ {0xA3u, 0x96u},\r
+ {0xA7u, 0xFFu},\r
+ {0xA8u, 0x50u},\r
+ {0xA9u, 0xFFu},\r
+ {0xAAu, 0xA0u},\r
+ {0xACu, 0x30u},\r
+ {0xADu, 0x33u},\r
+ {0xAEu, 0xC0u},\r
+ {0xAFu, 0xCCu},\r
+ {0xB2u, 0xFFu},\r
+ {0xB5u, 0xFFu},\r
+ {0xBBu, 0x20u},\r
+ {0xBEu, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
{0xDCu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x48u},\r
- {0x05u, 0x56u},\r
- {0x09u, 0x0Au},\r
- {0x0Au, 0x04u},\r
- {0x0Du, 0x20u},\r
- {0x0Eu, 0x11u},\r
- {0x0Fu, 0x40u},\r
- {0x11u, 0x50u},\r
- {0x15u, 0x24u},\r
- {0x16u, 0x02u},\r
- {0x17u, 0x01u},\r
- {0x18u, 0x40u},\r
- {0x1Au, 0x0Cu},\r
- {0x1Bu, 0x01u},\r
- {0x1Cu, 0x02u},\r
- {0x1Du, 0x04u},\r
- {0x21u, 0x24u},\r
- {0x27u, 0x42u},\r
- {0x2Au, 0x08u},\r
- {0x2Fu, 0x54u},\r
- {0x31u, 0x2Au},\r
- {0x36u, 0x10u},\r
- {0x37u, 0x42u},\r
+ {0x00u, 0x08u},\r
+ {0x03u, 0x80u},\r
+ {0x04u, 0x04u},\r
+ {0x06u, 0x80u},\r
+ {0x08u, 0x01u},\r
+ {0x0Au, 0x01u},\r
+ {0x0Bu, 0x04u},\r
+ {0x0Eu, 0xA1u},\r
+ {0x0Fu, 0x02u},\r
+ {0x10u, 0x40u},\r
+ {0x13u, 0x52u},\r
+ {0x14u, 0x01u},\r
+ {0x17u, 0x20u},\r
+ {0x18u, 0x10u},\r
+ {0x1Eu, 0x80u},\r
+ {0x1Fu, 0x60u},\r
+ {0x21u, 0x20u},\r
+ {0x25u, 0x05u},\r
+ {0x26u, 0x20u},\r
+ {0x27u, 0x02u},\r
+ {0x29u, 0x90u},\r
+ {0x2Au, 0x06u},\r
+ {0x30u, 0x81u},\r
+ {0x31u, 0x24u},\r
+ {0x32u, 0x01u},\r
+ {0x36u, 0x20u},\r
+ {0x37u, 0x02u},\r
{0x38u, 0x02u},\r
- {0x39u, 0x18u},\r
- {0x3Bu, 0x24u},\r
- {0x3Du, 0x08u},\r
- {0x3Eu, 0x40u},\r
- {0x3Fu, 0x20u},\r
- {0x59u, 0x80u},\r
- {0x5Bu, 0x20u},\r
- {0x60u, 0x04u},\r
+ {0x39u, 0x20u},\r
+ {0x3Cu, 0x40u},\r
+ {0x3Du, 0x0Au},\r
+ {0x44u, 0x10u},\r
+ {0x45u, 0x08u},\r
+ {0x58u, 0x10u},\r
+ {0x59u, 0x01u},\r
+ {0x5Au, 0x40u},\r
+ {0x5Bu, 0x08u},\r
{0x62u, 0x80u},\r
- {0x63u, 0x08u},\r
- {0x6Cu, 0x02u},\r
- {0x6Du, 0x08u},\r
- {0x6Fu, 0x18u},\r
- {0x83u, 0x18u},\r
- {0x84u, 0x50u},\r
- {0x88u, 0x01u},\r
- {0x89u, 0x04u},\r
- {0x8Au, 0x04u},\r
- {0x8Bu, 0x02u},\r
- {0x8Fu, 0x04u},\r
- {0xC0u, 0xF5u},\r
- {0xC2u, 0xFEu},\r
- {0xC4u, 0xF3u},\r
- {0xCAu, 0xE2u},\r
- {0xCCu, 0xB7u},\r
- {0xCEu, 0x77u},\r
- {0xD6u, 0x0Cu},\r
- {0xD8u, 0x0Cu},\r
+ {0x69u, 0x55u},\r
+ {0x6Cu, 0x10u},\r
+ {0x6Du, 0xA0u},\r
+ {0x71u, 0x80u},\r
+ {0x72u, 0x88u},\r
+ {0x73u, 0x54u},\r
+ {0x80u, 0x10u},\r
+ {0x81u, 0x10u},\r
+ {0x85u, 0x80u},\r
+ {0x89u, 0x40u},\r
+ {0x8Bu, 0x10u},\r
+ {0x8Cu, 0xC0u},\r
+ {0x8Fu, 0x0Au},\r
+ {0x90u, 0x02u},\r
+ {0x92u, 0x40u},\r
+ {0x94u, 0x80u},\r
+ {0x95u, 0x44u},\r
+ {0x96u, 0x1Au},\r
+ {0x97u, 0x02u},\r
+ {0x99u, 0x10u},\r
+ {0x9Au, 0x22u},\r
+ {0x9Bu, 0x10u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Du, 0x04u},\r
+ {0x9Eu, 0x08u},\r
+ {0xA0u, 0x04u},\r
+ {0xA2u, 0x08u},\r
+ {0xA3u, 0x10u},\r
+ {0xA7u, 0x08u},\r
+ {0xACu, 0x80u},\r
+ {0xAEu, 0x01u},\r
+ {0xB1u, 0x01u},\r
+ {0xB6u, 0x40u},\r
+ {0xC0u, 0x3Cu},\r
+ {0xC2u, 0xBBu},\r
+ {0xC4u, 0xC3u},\r
+ {0xCAu, 0x0Fu},\r
+ {0xCCu, 0xAEu},\r
+ {0xCEu, 0xD5u},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x08u},\r
{0xE0u, 0x04u},\r
- {0xE2u, 0xA0u},\r
- {0xE6u, 0x02u},\r
- {0x01u, 0x60u},\r
- {0x04u, 0x06u},\r
- {0x06u, 0x01u},\r
- {0x08u, 0x04u},\r
- {0x09u, 0x04u},\r
- {0x0Bu, 0x03u},\r
- {0x10u, 0x1Fu},\r
- {0x11u, 0x2Du},\r
- {0x13u, 0x12u},\r
- {0x16u, 0x1Eu},\r
- {0x18u, 0x01u},\r
- {0x19u, 0x1Bu},\r
- {0x1Au, 0x18u},\r
- {0x1Bu, 0x44u},\r
- {0x24u, 0x07u},\r
- {0x26u, 0x08u},\r
- {0x29u, 0x19u},\r
- {0x2Au, 0x02u},\r
- {0x2Bu, 0x26u},\r
- {0x2Cu, 0x17u},\r
- {0x30u, 0x1Eu},\r
- {0x31u, 0x70u},\r
- {0x33u, 0x07u},\r
- {0x34u, 0x01u},\r
- {0x35u, 0x08u},\r
- {0x39u, 0x02u},\r
- {0x3Bu, 0x08u},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x10u},\r
+ {0xE2u, 0x08u},\r
+ {0xE6u, 0x28u},\r
+ {0xE8u, 0x08u},\r
+ {0xEEu, 0x42u},\r
+ {0x04u, 0x30u},\r
+ {0x06u, 0xC0u},\r
+ {0x07u, 0x80u},\r
+ {0x08u, 0xFFu},\r
+ {0x09u, 0x0Fu},\r
+ {0x0Cu, 0x05u},\r
+ {0x0Du, 0xC0u},\r
+ {0x0Eu, 0x0Au},\r
+ {0x0Fu, 0x1Fu},\r
+ {0x10u, 0x03u},\r
+ {0x12u, 0x0Cu},\r
+ {0x13u, 0x70u},\r
+ {0x15u, 0x90u},\r
+ {0x16u, 0xFFu},\r
+ {0x17u, 0x2Fu},\r
+ {0x18u, 0xFFu},\r
+ {0x19u, 0x05u},\r
+ {0x1Bu, 0x0Au},\r
+ {0x1Cu, 0x0Fu},\r
+ {0x1Eu, 0xF0u},\r
+ {0x20u, 0x09u},\r
+ {0x21u, 0x03u},\r
+ {0x22u, 0x06u},\r
+ {0x23u, 0x0Cu},\r
+ {0x27u, 0x80u},\r
+ {0x28u, 0x50u},\r
+ {0x29u, 0x06u},\r
+ {0x2Au, 0xA0u},\r
+ {0x2Bu, 0x09u},\r
+ {0x2Cu, 0x90u},\r
+ {0x2Du, 0xA0u},\r
+ {0x2Eu, 0x60u},\r
+ {0x2Fu, 0x4Fu},\r
+ {0x31u, 0x7Fu},\r
+ {0x36u, 0xFFu},\r
+ {0x37u, 0x80u},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x40u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x01u},\r
+ {0x5Cu, 0x10u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x40u},\r
- {0x81u, 0x02u},\r
- {0x85u, 0x01u},\r
- {0x8Au, 0x07u},\r
- {0x8Du, 0x04u},\r
- {0x8Eu, 0x20u},\r
- {0x8Fu, 0x08u},\r
- {0x90u, 0x0Au},\r
- {0x92u, 0x05u},\r
- {0x94u, 0x09u},\r
+ {0x82u, 0x70u},\r
+ {0x84u, 0x02u},\r
+ {0x85u, 0xC8u},\r
+ {0x86u, 0x05u},\r
+ {0x87u, 0x03u},\r
+ {0x88u, 0x40u},\r
+ {0x8Cu, 0x70u},\r
+ {0x8Fu, 0x0Cu},\r
+ {0x93u, 0x01u},\r
+ {0x94u, 0x01u},\r
{0x96u, 0x02u},\r
- {0x97u, 0x04u},\r
- {0x98u, 0x04u},\r
- {0x99u, 0x02u},\r
- {0x9Au, 0x08u},\r
- {0xA1u, 0x02u},\r
- {0xA2u, 0x08u},\r
- {0xA6u, 0x10u},\r
- {0xABu, 0x08u},\r
+ {0x97u, 0x20u},\r
+ {0x98u, 0x02u},\r
+ {0x99u, 0x04u},\r
+ {0x9Au, 0x09u},\r
+ {0x9Bu, 0xA3u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Eu, 0x01u},\r
+ {0xA4u, 0x02u},\r
+ {0xA6u, 0x01u},\r
+ {0xA9u, 0x01u},\r
+ {0xAAu, 0x20u},\r
+ {0xABu, 0x62u},\r
{0xACu, 0x10u},\r
- {0xADu, 0x02u},\r
- {0xAEu, 0x20u},\r
- {0xB0u, 0x30u},\r
- {0xB1u, 0x02u},\r
- {0xB2u, 0x0Fu},\r
- {0xB3u, 0x01u},\r
- {0xB4u, 0x40u},\r
- {0xB7u, 0x0Cu},\r
- {0xB9u, 0x02u},\r
- {0xBEu, 0x11u},\r
- {0xBFu, 0x45u},\r
- {0xD6u, 0x08u},\r
+ {0xAFu, 0x12u},\r
+ {0xB0u, 0x70u},\r
+ {0xB1u, 0x10u},\r
+ {0xB2u, 0x03u},\r
+ {0xB4u, 0x04u},\r
+ {0xB5u, 0xE0u},\r
+ {0xB6u, 0x08u},\r
+ {0xB7u, 0x0Fu},\r
+ {0xBAu, 0x08u},\r
+ {0xBEu, 0x01u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x01u},\r
- {0xDDu, 0x90u},\r
+ {0xDCu, 0x09u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x20u},\r
- {0x02u, 0x82u},\r
- {0x03u, 0x08u},\r
- {0x04u, 0x20u},\r
- {0x05u, 0x08u},\r
- {0x09u, 0x0Au},\r
- {0x0Au, 0x04u},\r
- {0x0Eu, 0x44u},\r
- {0x0Fu, 0x20u},\r
- {0x11u, 0x01u},\r
- {0x13u, 0x44u},\r
- {0x14u, 0x21u},\r
- {0x17u, 0x10u},\r
- {0x19u, 0x20u},\r
- {0x1Au, 0x80u},\r
- {0x1Bu, 0x08u},\r
- {0x1Du, 0x02u},\r
- {0x1Eu, 0x40u},\r
- {0x1Fu, 0x20u},\r
- {0x20u, 0x12u},\r
- {0x22u, 0x01u},\r
- {0x24u, 0x80u},\r
- {0x25u, 0x01u},\r
- {0x27u, 0x28u},\r
- {0x28u, 0x04u},\r
- {0x29u, 0x01u},\r
- {0x2Bu, 0x02u},\r
- {0x2Eu, 0x20u},\r
- {0x32u, 0x28u},\r
- {0x35u, 0x10u},\r
- {0x37u, 0x01u},\r
- {0x38u, 0x04u},\r
- {0x39u, 0x22u},\r
- {0x3Au, 0x20u},\r
- {0x3Bu, 0x40u},\r
- {0x3Du, 0x02u},\r
- {0x3Fu, 0x10u},\r
- {0x45u, 0x40u},\r
- {0x46u, 0x02u},\r
- {0x58u, 0x98u},\r
- {0x5Cu, 0x40u},\r
- {0x5Fu, 0x30u},\r
- {0x60u, 0x02u},\r
- {0x62u, 0x14u},\r
- {0x66u, 0x80u},\r
- {0x80u, 0x02u},\r
- {0x81u, 0x02u},\r
- {0x82u, 0x40u},\r
- {0x84u, 0x01u},\r
- {0x85u, 0x80u},\r
- {0x88u, 0x04u},\r
- {0x8Au, 0x01u},\r
- {0x8Bu, 0x20u},\r
- {0x8Cu, 0x0Au},\r
- {0x90u, 0x04u},\r
- {0x92u, 0x08u},\r
- {0x93u, 0x04u},\r
- {0x94u, 0x02u},\r
- {0x95u, 0x64u},\r
- {0x96u, 0x51u},\r
- {0x97u, 0xE8u},\r
- {0x98u, 0x10u},\r
- {0x99u, 0x01u},\r
- {0x9Bu, 0x50u},\r
- {0x9Cu, 0x40u},\r
- {0x9Du, 0xD2u},\r
- {0x9Eu, 0x0Au},\r
- {0x9Fu, 0x01u},\r
- {0xA0u, 0x02u},\r
- {0xA1u, 0x04u},\r
- {0xA2u, 0x80u},\r
- {0xA3u, 0x11u},\r
- {0xA4u, 0x04u},\r
- {0xA5u, 0x0Au},\r
- {0xA6u, 0x10u},\r
- {0xABu, 0x10u},\r
+ {0x00u, 0x90u},\r
+ {0x01u, 0x04u},\r
+ {0x05u, 0x80u},\r
+ {0x06u, 0x88u},\r
+ {0x07u, 0x10u},\r
+ {0x09u, 0x01u},\r
+ {0x0Au, 0x06u},\r
+ {0x0Bu, 0x20u},\r
+ {0x0Eu, 0x1Au},\r
+ {0x11u, 0x50u},\r
+ {0x12u, 0x40u},\r
+ {0x16u, 0x22u},\r
+ {0x17u, 0x20u},\r
+ {0x1Bu, 0x40u},\r
+ {0x1Du, 0x01u},\r
+ {0x1Eu, 0x1Au},\r
+ {0x21u, 0x02u},\r
+ {0x22u, 0x80u},\r
+ {0x23u, 0x80u},\r
+ {0x25u, 0x40u},\r
+ {0x26u, 0x02u},\r
+ {0x27u, 0x08u},\r
+ {0x28u, 0x88u},\r
+ {0x2Bu, 0x12u},\r
+ {0x2Cu, 0x02u},\r
+ {0x2Fu, 0x04u},\r
+ {0x31u, 0x26u},\r
+ {0x36u, 0x02u},\r
+ {0x37u, 0x28u},\r
+ {0x38u, 0xA0u},\r
+ {0x39u, 0x08u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Cu, 0x04u},\r
+ {0x3Du, 0x80u},\r
+ {0x3Eu, 0x88u},\r
+ {0x58u, 0x40u},\r
+ {0x63u, 0x01u},\r
+ {0x87u, 0x01u},\r
+ {0x88u, 0x80u},\r
+ {0x89u, 0x10u},\r
+ {0x8Au, 0x02u},\r
+ {0x8Bu, 0x04u},\r
+ {0x8Fu, 0x08u},\r
+ {0x90u, 0xB2u},\r
+ {0x91u, 0x5Du},\r
+ {0x93u, 0x80u},\r
+ {0x94u, 0x04u},\r
+ {0x95u, 0x20u},\r
+ {0x96u, 0x1Au},\r
+ {0x99u, 0x04u},\r
+ {0x9Au, 0x20u},\r
+ {0x9Bu, 0x10u},\r
+ {0x9Fu, 0x20u},\r
+ {0xA1u, 0xA0u},\r
+ {0xA2u, 0x08u},\r
+ {0xA3u, 0x12u},\r
+ {0xA6u, 0x90u},\r
+ {0xA7u, 0x01u},\r
+ {0xA9u, 0x05u},\r
+ {0xABu, 0x01u},\r
+ {0xADu, 0x08u},\r
{0xAFu, 0x20u},\r
- {0xB1u, 0x20u},\r
+ {0xB1u, 0x04u},\r
+ {0xB3u, 0x08u},\r
{0xB4u, 0x40u},\r
- {0xB5u, 0x01u},\r
- {0xC0u, 0x6Bu},\r
- {0xC2u, 0x7Eu},\r
- {0xC4u, 0xEDu},\r
- {0xCAu, 0x2Du},\r
- {0xCCu, 0xA6u},\r
- {0xCEu, 0xABu},\r
- {0xD6u, 0x1Eu},\r
- {0xD8u, 0x1Eu},\r
- {0xE0u, 0x01u},\r
- {0xE2u, 0x28u},\r
- {0xEAu, 0x02u},\r
- {0xEEu, 0x01u},\r
- {0x00u, 0x02u},\r
+ {0xB6u, 0x04u},\r
+ {0xB7u, 0x80u},\r
+ {0xC0u, 0xF7u},\r
+ {0xC2u, 0xEFu},\r
+ {0xC4u, 0xEBu},\r
+ {0xCAu, 0x3Fu},\r
+ {0xCCu, 0xE7u},\r
+ {0xCEu, 0x5Eu},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x08u},\r
+ {0xE2u, 0x18u},\r
+ {0xE6u, 0x48u},\r
+ {0xEAu, 0x06u},\r
+ {0xEEu, 0x05u},\r
+ {0x01u, 0x0Du},\r
+ {0x04u, 0x7Fu},\r
+ {0x05u, 0x02u},\r
+ {0x06u, 0x80u},\r
+ {0x07u, 0x08u},\r
{0x09u, 0x01u},\r
- {0x14u, 0x01u},\r
- {0x28u, 0x04u},\r
- {0x2Du, 0x02u},\r
- {0x30u, 0x02u},\r
- {0x31u, 0x01u},\r
- {0x34u, 0x04u},\r
- {0x36u, 0x01u},\r
- {0x37u, 0x02u},\r
- {0x3Eu, 0x51u},\r
- {0x3Fu, 0x41u},\r
- {0x40u, 0x24u},\r
- {0x41u, 0x03u},\r
- {0x42u, 0x10u},\r
- {0x45u, 0xFCu},\r
- {0x46u, 0xD2u},\r
- {0x47u, 0x0Eu},\r
- {0x48u, 0x1Fu},\r
- {0x49u, 0xFFu},\r
- {0x4Au, 0xFFu},\r
- {0x4Bu, 0xFFu},\r
- {0x4Fu, 0x2Cu},\r
- {0x56u, 0x01u},\r
+ {0x0Au, 0xFFu},\r
+ {0x0Bu, 0x02u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Eu, 0x9Fu},\r
+ {0x0Fu, 0x0Du},\r
+ {0x10u, 0x80u},\r
+ {0x11u, 0x0Du},\r
+ {0x14u, 0xC0u},\r
+ {0x15u, 0x10u},\r
+ {0x16u, 0x08u},\r
+ {0x18u, 0xC0u},\r
+ {0x19u, 0x02u},\r
+ {0x1Au, 0x04u},\r
+ {0x1Bu, 0x04u},\r
+ {0x1Cu, 0xC0u},\r
+ {0x1Du, 0x10u},\r
+ {0x1Eu, 0x02u},\r
+ {0x20u, 0x90u},\r
+ {0x21u, 0x0Du},\r
+ {0x22u, 0x40u},\r
+ {0x25u, 0x0Du},\r
+ {0x26u, 0x60u},\r
+ {0x28u, 0x1Fu},\r
+ {0x29u, 0x0Du},\r
+ {0x2Au, 0x20u},\r
+ {0x2Cu, 0xC0u},\r
+ {0x2Eu, 0x01u},\r
+ {0x35u, 0x10u},\r
+ {0x36u, 0xFFu},\r
+ {0x37u, 0x0Fu},\r
+ {0x39u, 0x20u},\r
+ {0x3Bu, 0x80u},\r
+ {0x3Eu, 0x40u},\r
+ {0x54u, 0x09u},\r
+ {0x56u, 0x04u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Au, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Du, 0x01u},\r
{0x5Fu, 0x01u},\r
- {0x62u, 0xC0u},\r
- {0x66u, 0x80u},\r
- {0x68u, 0x40u},\r
- {0x69u, 0x40u},\r
- {0x6Eu, 0x08u},\r
- {0x84u, 0x0Bu},\r
- {0x86u, 0x14u},\r
- {0x8Du, 0x01u},\r
- {0x90u, 0x34u},\r
- {0x92u, 0x0Bu},\r
- {0x96u, 0x3Fu},\r
- {0x98u, 0x08u},\r
- {0x9Au, 0x22u},\r
- {0x9Eu, 0x10u},\r
- {0xA8u, 0x01u},\r
- {0xAFu, 0x02u},\r
- {0xB2u, 0x07u},\r
- {0xB3u, 0x02u},\r
- {0xB4u, 0x38u},\r
- {0xB5u, 0x01u},\r
- {0xBFu, 0x10u},\r
- {0xD4u, 0x09u},\r
- {0xD6u, 0x04u},\r
+ {0x80u, 0x20u},\r
+ {0x81u, 0x02u},\r
+ {0x82u, 0x90u},\r
+ {0x83u, 0x11u},\r
+ {0x88u, 0x4Du},\r
+ {0x8Au, 0xB2u},\r
+ {0x8Du, 0x02u},\r
+ {0x8Fu, 0x01u},\r
+ {0x94u, 0x08u},\r
+ {0x95u, 0x01u},\r
+ {0x96u, 0x44u},\r
+ {0x97u, 0x02u},\r
+ {0x99u, 0x02u},\r
+ {0x9Bu, 0x09u},\r
+ {0x9Cu, 0x10u},\r
+ {0x9Du, 0x02u},\r
+ {0x9Eu, 0x22u},\r
+ {0x9Fu, 0x05u},\r
+ {0xA8u, 0x04u},\r
+ {0xAAu, 0x09u},\r
+ {0xB0u, 0xC0u},\r
+ {0xB1u, 0x04u},\r
+ {0xB2u, 0x03u},\r
+ {0xB3u, 0x03u},\r
+ {0xB4u, 0x3Cu},\r
+ {0xB5u, 0x10u},\r
+ {0xB7u, 0x08u},\r
+ {0xBBu, 0x08u},\r
+ {0xBEu, 0x15u},\r
+ {0xD4u, 0x01u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x01u},\r
+ {0xDCu, 0x90u},\r
+ {0xDDu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x02u, 0x40u},\r
- {0x05u, 0x04u},\r
- {0x08u, 0x08u},\r
- {0x0Du, 0x42u},\r
- {0x0Eu, 0x04u},\r
- {0x0Fu, 0x20u},\r
- {0x12u, 0x04u},\r
- {0x17u, 0x10u},\r
- {0x18u, 0x04u},\r
- {0x19u, 0x01u},\r
- {0x1Bu, 0x40u},\r
- {0x1Du, 0x0Cu},\r
- {0x1Eu, 0x24u},\r
- {0x1Fu, 0x30u},\r
- {0x23u, 0x81u},\r
- {0x27u, 0x24u},\r
- {0x28u, 0x06u},\r
- {0x2Au, 0x10u},\r
- {0x2Cu, 0x02u},\r
- {0x3Au, 0x10u},\r
- {0x3Eu, 0x80u},\r
- {0x41u, 0x0Au},\r
- {0x42u, 0x04u},\r
- {0x43u, 0x40u},\r
- {0x49u, 0x08u},\r
- {0x4Bu, 0x02u},\r
- {0x50u, 0x10u},\r
- {0x51u, 0x40u},\r
- {0x52u, 0x08u},\r
- {0x53u, 0x40u},\r
- {0x59u, 0x21u},\r
- {0x5Bu, 0x84u},\r
+ {0x01u, 0x01u},\r
+ {0x03u, 0x08u},\r
+ {0x04u, 0xA4u},\r
+ {0x09u, 0x84u},\r
+ {0x0Cu, 0x10u},\r
+ {0x0Eu, 0x99u},\r
+ {0x12u, 0x08u},\r
+ {0x16u, 0x06u},\r
+ {0x17u, 0x05u},\r
+ {0x19u, 0x08u},\r
+ {0x1Au, 0x04u},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Du, 0x40u},\r
+ {0x21u, 0x28u},\r
+ {0x22u, 0x84u},\r
+ {0x23u, 0x40u},\r
+ {0x25u, 0x40u},\r
+ {0x27u, 0x04u},\r
+ {0x2Cu, 0x10u},\r
+ {0x2Eu, 0x12u},\r
+ {0x31u, 0x28u},\r
+ {0x32u, 0x80u},\r
+ {0x35u, 0x40u},\r
+ {0x37u, 0x29u},\r
+ {0x3Bu, 0x41u},\r
+ {0x3Cu, 0x04u},\r
+ {0x3Du, 0x80u},\r
+ {0x3Eu, 0x21u},\r
+ {0x5Bu, 0x80u},\r
{0x5Cu, 0x40u},\r
- {0x5Du, 0x10u},\r
+ {0x5Du, 0x20u},\r
{0x5Eu, 0x02u},\r
{0x5Fu, 0x04u},\r
- {0x60u, 0x14u},\r
- {0x63u, 0x81u},\r
- {0x64u, 0x40u},\r
- {0x65u, 0x80u},\r
- {0x68u, 0x04u},\r
- {0x69u, 0x49u},\r
- {0x70u, 0x09u},\r
- {0x72u, 0x0Au},\r
- {0x83u, 0x01u},\r
- {0x86u, 0x08u},\r
- {0x88u, 0x20u},\r
- {0x8Au, 0x04u},\r
- {0x8Bu, 0x04u},\r
- {0x8Cu, 0x98u},\r
- {0x90u, 0x90u},\r
+ {0x66u, 0x01u},\r
+ {0x67u, 0x02u},\r
+ {0x82u, 0x01u},\r
+ {0x8Au, 0x01u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Du, 0x01u},\r
+ {0x90u, 0x12u},\r
+ {0x91u, 0x55u},\r
+ {0x93u, 0xA1u},\r
+ {0x94u, 0x04u},\r
+ {0x96u, 0x0Eu},\r
+ {0x97u, 0x08u},\r
+ {0x99u, 0x01u},\r
+ {0x9Bu, 0x80u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Du, 0x80u},\r
+ {0x9Eu, 0x40u},\r
+ {0x9Fu, 0x20u},\r
+ {0xA1u, 0x84u},\r
+ {0xA2u, 0x08u},\r
+ {0xA3u, 0x40u},\r
+ {0xA4u, 0x42u},\r
+ {0xA5u, 0x01u},\r
+ {0xA6u, 0x10u},\r
+ {0xA9u, 0x04u},\r
+ {0xB1u, 0x10u},\r
+ {0xB4u, 0x08u},\r
+ {0xC0u, 0xEAu},\r
+ {0xC2u, 0xF5u},\r
+ {0xC4u, 0xF2u},\r
+ {0xCAu, 0xE0u},\r
+ {0xCCu, 0xFEu},\r
+ {0xCEu, 0xF9u},\r
+ {0xD6u, 0xF8u},\r
+ {0xD8u, 0x90u},\r
+ {0xE2u, 0x08u},\r
+ {0xE6u, 0x48u},\r
+ {0xEAu, 0x04u},\r
+ {0x91u, 0x40u},\r
{0x92u, 0x08u},\r
- {0x93u, 0x10u},\r
- {0x94u, 0x22u},\r
- {0x95u, 0x67u},\r
- {0x96u, 0x15u},\r
- {0x97u, 0xE8u},\r
- {0x98u, 0x02u},\r
- {0x99u, 0x20u},\r
- {0x9Au, 0x94u},\r
- {0x9Bu, 0x58u},\r
- {0x9Cu, 0x60u},\r
- {0x9Du, 0x58u},\r
- {0x9Eu, 0x08u},\r
- {0x9Fu, 0x01u},\r
- {0xA0u, 0x10u},\r
- {0xA1u, 0x06u},\r
- {0xA2u, 0x80u},\r
- {0xA3u, 0x11u},\r
- {0xA4u, 0x04u},\r
- {0xA5u, 0x48u},\r
- {0xA6u, 0x30u},\r
- {0xA7u, 0x02u},\r
- {0xA8u, 0x40u},\r
- {0xAAu, 0x02u},\r
- {0xACu, 0x01u},\r
- {0xADu, 0x0Au},\r
- {0xAEu, 0x08u},\r
- {0xB0u, 0x80u},\r
- {0xB6u, 0x04u},\r
- {0xC0u, 0x28u},\r
- {0xC2u, 0xF4u},\r
- {0xC4u, 0x42u},\r
- {0xCAu, 0x18u},\r
- {0xCEu, 0x14u},\r
- {0xD0u, 0x0Fu},\r
- {0xD6u, 0xFFu},\r
- {0xD8u, 0x9Fu},\r
- {0xE0u, 0x08u},\r
- {0xE4u, 0x04u},\r
- {0xEAu, 0x09u},\r
- {0xEEu, 0x0Cu},\r
- {0x08u, 0x14u},\r
- {0x0Au, 0x43u},\r
- {0x0Bu, 0xFFu},\r
- {0x0Cu, 0xE0u},\r
- {0x0Du, 0x69u},\r
- {0x0Fu, 0x96u},\r
- {0x11u, 0x0Fu},\r
- {0x12u, 0x02u},\r
- {0x13u, 0xF0u},\r
- {0x15u, 0x33u},\r
- {0x17u, 0xCCu},\r
- {0x18u, 0x21u},\r
- {0x1Au, 0x12u},\r
- {0x1Bu, 0xFFu},\r
- {0x1Du, 0x55u},\r
- {0x1Eu, 0xECu},\r
- {0x1Fu, 0xAAu},\r
- {0x20u, 0x88u},\r
+ {0x93u, 0x80u},\r
+ {0xA1u, 0x40u},\r
+ {0xABu, 0x10u},\r
+ {0xB1u, 0x88u},\r
+ {0xB4u, 0x81u},\r
+ {0xE2u, 0x08u},\r
+ {0xE6u, 0x08u},\r
+ {0xE8u, 0x80u},\r
+ {0xEAu, 0x40u},\r
+ {0x00u, 0xFFu},\r
+ {0x01u, 0x55u},\r
+ {0x03u, 0xAAu},\r
+ {0x09u, 0xFFu},\r
+ {0x0Au, 0xFFu},\r
+ {0x0Du, 0x0Fu},\r
+ {0x0Eu, 0xFFu},\r
+ {0x0Fu, 0xF0u},\r
+ {0x10u, 0x33u},\r
+ {0x12u, 0xCCu},\r
+ {0x13u, 0xFFu},\r
+ {0x17u, 0xFFu},\r
+ {0x18u, 0x55u},\r
+ {0x19u, 0x69u},\r
+ {0x1Au, 0xAAu},\r
+ {0x1Bu, 0x96u},\r
+ {0x1Cu, 0x0Fu},\r
+ {0x1Eu, 0xF0u},\r
+ {0x1Fu, 0xFFu},\r
{0x21u, 0xFFu},\r
- {0x22u, 0x13u},\r
- {0x27u, 0xFFu},\r
- {0x2Au, 0x01u},\r
- {0x2Bu, 0xFFu},\r
- {0x30u, 0x10u},\r
+ {0x22u, 0xFFu},\r
+ {0x24u, 0xFFu},\r
+ {0x2Cu, 0x96u},\r
+ {0x2Du, 0x33u},\r
+ {0x2Eu, 0x69u},\r
+ {0x2Fu, 0xCCu},\r
{0x31u, 0xFFu},\r
- {0x34u, 0xE0u},\r
- {0x36u, 0x0Fu},\r
+ {0x36u, 0xFFu},\r
+ {0x3Au, 0x80u},\r
{0x3Bu, 0x02u},\r
- {0x3Eu, 0x11u},\r
- {0x56u, 0x02u},\r
- {0x57u, 0x28u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x10u},\r
+ {0x5Cu, 0x11u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x40u},\r
- {0x85u, 0x03u},\r
- {0x86u, 0x1Fu},\r
- {0x87u, 0x0Cu},\r
- {0x89u, 0x50u},\r
- {0x8Au, 0x70u},\r
- {0x8Bu, 0xA0u},\r
- {0x8Cu, 0x03u},\r
- {0x8Du, 0x0Fu},\r
- {0x8Eu, 0x0Cu},\r
- {0x8Fu, 0xF0u},\r
- {0x90u, 0x20u},\r
- {0x92u, 0x4Fu},\r
- {0x94u, 0x10u},\r
- {0x95u, 0x05u},\r
- {0x96u, 0x2Fu},\r
- {0x97u, 0x0Au},\r
- {0x98u, 0x05u},\r
- {0x9Au, 0x0Au},\r
- {0x9Bu, 0xFFu},\r
- {0x9Fu, 0xFFu},\r
- {0xA1u, 0x60u},\r
- {0xA3u, 0x90u},\r
- {0xA4u, 0x0Fu},\r
- {0xA5u, 0xFFu},\r
- {0xA9u, 0x30u},\r
- {0xABu, 0xC0u},\r
- {0xACu, 0x06u},\r
- {0xADu, 0x06u},\r
- {0xAEu, 0x09u},\r
- {0xAFu, 0x09u},\r
- {0xB4u, 0x7Fu},\r
- {0xB5u, 0xFFu},\r
- {0xB9u, 0x80u},\r
- {0xBFu, 0x50u},\r
+ {0x82u, 0x08u},\r
+ {0x83u, 0x80u},\r
+ {0x85u, 0xAAu},\r
+ {0x86u, 0x80u},\r
+ {0x87u, 0x55u},\r
+ {0x88u, 0x0Au},\r
+ {0x8Au, 0x05u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Eu, 0x07u},\r
+ {0x8Fu, 0x07u},\r
+ {0x91u, 0x44u},\r
+ {0x92u, 0x40u},\r
+ {0x93u, 0x88u},\r
+ {0x95u, 0x99u},\r
+ {0x96u, 0x20u},\r
+ {0x97u, 0x22u},\r
+ {0x9Au, 0x10u},\r
+ {0x9Bu, 0x70u},\r
+ {0x9Cu, 0x04u},\r
+ {0x9Eu, 0x08u},\r
+ {0xA0u, 0x50u},\r
+ {0xA2u, 0xA0u},\r
+ {0xA4u, 0x09u},\r
+ {0xA6u, 0x02u},\r
+ {0xB0u, 0xC0u},\r
+ {0xB2u, 0x30u},\r
+ {0xB3u, 0xF0u},\r
+ {0xB6u, 0x0Fu},\r
+ {0xB7u, 0x0Fu},\r
+ {0xBEu, 0x05u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x01u},\r
+ {0xDCu, 0x11u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x20u},\r
{0x02u, 0x02u},\r
- {0x03u, 0x20u},\r
- {0x04u, 0x80u},\r
- {0x05u, 0x10u},\r
- {0x08u, 0x10u},\r
- {0x09u, 0x0Au},\r
- {0x0Bu, 0x80u},\r
- {0x0Cu, 0x02u},\r
- {0x0Du, 0x90u},\r
- {0x11u, 0x08u},\r
- {0x12u, 0x01u},\r
- {0x17u, 0x21u},\r
- {0x19u, 0x20u},\r
- {0x1Cu, 0x48u},\r
- {0x1Du, 0x80u},\r
- {0x21u, 0x40u},\r
- {0x22u, 0x20u},\r
- {0x26u, 0x02u},\r
- {0x28u, 0x40u},\r
- {0x29u, 0x02u},\r
- {0x2Au, 0x08u},\r
- {0x2Bu, 0x05u},\r
- {0x2Fu, 0x64u},\r
- {0x32u, 0x44u},\r
- {0x33u, 0x10u},\r
- {0x34u, 0x04u},\r
- {0x36u, 0x92u},\r
- {0x38u, 0x04u},\r
- {0x3Bu, 0x60u},\r
- {0x3Eu, 0x80u},\r
- {0x3Fu, 0x20u},\r
- {0x58u, 0xA0u},\r
- {0x60u, 0x08u},\r
- {0x62u, 0x40u},\r
- {0x67u, 0x10u},\r
- {0x6Du, 0xC4u},\r
- {0x6Eu, 0x15u},\r
- {0x75u, 0xC0u},\r
- {0x80u, 0x20u},\r
- {0x82u, 0x08u},\r
- {0x84u, 0x04u},\r
- {0x8Au, 0x40u},\r
- {0x8Bu, 0x40u},\r
- {0x8Cu, 0x08u},\r
- {0x8Du, 0x40u},\r
- {0x90u, 0x80u},\r
- {0x91u, 0x08u},\r
- {0x92u, 0x08u},\r
- {0x93u, 0x18u},\r
- {0x94u, 0x40u},\r
- {0x95u, 0x36u},\r
- {0x96u, 0x11u},\r
- {0x97u, 0x44u},\r
- {0x98u, 0x94u},\r
- {0x9Au, 0x83u},\r
- {0x9Bu, 0x30u},\r
- {0x9Cu, 0x08u},\r
- {0x9Du, 0x50u},\r
- {0x9Eu, 0x40u},\r
- {0x9Fu, 0x01u},\r
- {0xA0u, 0x10u},\r
- {0xA1u, 0x0Eu},\r
- {0xA2u, 0x90u},\r
- {0xA3u, 0x31u},\r
- {0xA4u, 0x02u},\r
- {0xA5u, 0x40u},\r
- {0xA6u, 0x21u},\r
- {0xA7u, 0x02u},\r
- {0xA9u, 0x08u},\r
- {0xAAu, 0x01u},\r
- {0xADu, 0x80u},\r
- {0xAFu, 0x08u},\r
- {0xB0u, 0x10u},\r
- {0xB5u, 0x08u},\r
- {0xC0u, 0xC7u},\r
- {0xC2u, 0xDEu},\r
- {0xC4u, 0x55u},\r
- {0xCAu, 0xEFu},\r
- {0xCCu, 0xFEu},\r
- {0xCEu, 0x3Eu},\r
- {0xD6u, 0x0Cu},\r
- {0xD8u, 0x4Cu},\r
- {0xE2u, 0x02u},\r
- {0xE6u, 0x1Du},\r
- {0xEAu, 0x06u},\r
- {0xECu, 0x04u},\r
- {0x81u, 0x80u},\r
- {0x8Bu, 0x0Au},\r
- {0x8Fu, 0x80u},\r
- {0x90u, 0x02u},\r
- {0x92u, 0x01u},\r
- {0x9Bu, 0x02u},\r
- {0x9Fu, 0x48u},\r
- {0xA0u, 0x80u},\r
- {0xA1u, 0x80u},\r
- {0xA2u, 0x04u},\r
- {0xA3u, 0x08u},\r
- {0xA4u, 0x10u},\r
- {0xA6u, 0x20u},\r
- {0xA7u, 0x80u},\r
- {0xA8u, 0x08u},\r
- {0xABu, 0x10u},\r
- {0xADu, 0x21u},\r
- {0xB3u, 0x10u},\r
- {0xB4u, 0x08u},\r
- {0xB5u, 0x02u},\r
- {0xE0u, 0x40u},\r
- {0xE2u, 0x22u},\r
- {0xE4u, 0x80u},\r
- {0xE6u, 0x0Cu},\r
- {0xEAu, 0x22u},\r
- {0xECu, 0x10u},\r
- {0x00u, 0x06u},\r
- {0x0Bu, 0x02u},\r
- {0x0Cu, 0x04u},\r
- {0x0Eu, 0x03u},\r
+ {0x03u, 0x84u},\r
+ {0x05u, 0x48u},\r
+ {0x07u, 0x48u},\r
+ {0x08u, 0x02u},\r
+ {0x09u, 0x10u},\r
+ {0x0Au, 0x01u},\r
+ {0x0Du, 0x04u},\r
+ {0x0Eu, 0x0Au},\r
+ {0x0Fu, 0x80u},\r
+ {0x10u, 0x01u},\r
{0x11u, 0x02u},\r
- {0x13u, 0x04u},\r
- {0x14u, 0x06u},\r
+ {0x13u, 0x08u},\r
+ {0x17u, 0x05u},\r
{0x18u, 0x02u},\r
- {0x1Au, 0x04u},\r
- {0x1Bu, 0x04u},\r
- {0x23u, 0x01u},\r
+ {0x1Au, 0x01u},\r
+ {0x1Du, 0x40u},\r
+ {0x1Fu, 0x0Au},\r
+ {0x23u, 0x40u},\r
+ {0x25u, 0x40u},\r
+ {0x27u, 0x10u},\r
+ {0x2Bu, 0x81u},\r
+ {0x31u, 0x20u},\r
+ {0x32u, 0x42u},\r
+ {0x33u, 0x04u},\r
+ {0x36u, 0x03u},\r
+ {0x37u, 0x14u},\r
+ {0x3Au, 0x10u},\r
+ {0x3Bu, 0x41u},\r
+ {0x3Du, 0x89u},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x80u},\r
+ {0x59u, 0xA0u},\r
+ {0x5Cu, 0x80u},\r
+ {0x60u, 0x02u},\r
+ {0x61u, 0x10u},\r
+ {0x63u, 0x04u},\r
+ {0x64u, 0x01u},\r
+ {0x66u, 0x80u},\r
+ {0x6Cu, 0x02u},\r
+ {0x6Du, 0x40u},\r
+ {0x6Fu, 0x01u},\r
+ {0x85u, 0x60u},\r
+ {0x8Bu, 0x44u},\r
+ {0x8Fu, 0x0Au},\r
+ {0x91u, 0x09u},\r
+ {0x92u, 0x98u},\r
+ {0x93u, 0x81u},\r
+ {0x9Au, 0x10u},\r
+ {0x9Bu, 0x4Cu},\r
+ {0x9Du, 0x10u},\r
+ {0x9Eu, 0x80u},\r
+ {0xA1u, 0x35u},\r
+ {0xA2u, 0x06u},\r
+ {0xA3u, 0x81u},\r
+ {0xA4u, 0x02u},\r
+ {0xA8u, 0x04u},\r
+ {0xAAu, 0x03u},\r
+ {0xACu, 0x08u},\r
+ {0xADu, 0x80u},\r
+ {0xB0u, 0x80u},\r
+ {0xB6u, 0x46u},\r
+ {0xC0u, 0xFBu},\r
+ {0xC2u, 0xFBu},\r
+ {0xC4u, 0x3Du},\r
+ {0xCAu, 0x09u},\r
+ {0xCCu, 0xEFu},\r
+ {0xCEu, 0xFDu},\r
+ {0xD6u, 0x1Cu},\r
+ {0xD8u, 0x1Cu},\r
+ {0xE2u, 0x38u},\r
+ {0xE6u, 0x22u},\r
+ {0xEAu, 0x48u},\r
+ {0xEEu, 0x90u},\r
+ {0x00u, 0x01u},\r
+ {0x03u, 0xE7u},\r
+ {0x05u, 0x20u},\r
+ {0x09u, 0x08u},\r
+ {0x11u, 0x01u},\r
+ {0x13u, 0x44u},\r
+ {0x15u, 0x61u},\r
+ {0x17u, 0x82u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x10u},\r
+ {0x20u, 0x02u},\r
+ {0x27u, 0x02u},\r
+ {0x28u, 0x08u},\r
+ {0x29u, 0x86u},\r
+ {0x2Bu, 0x61u},\r
{0x30u, 0x01u},\r
- {0x31u, 0x06u},\r
- {0x33u, 0x01u},\r
- {0x34u, 0x06u},\r
- {0x3Au, 0x20u},\r
- {0x3Fu, 0x01u},\r
- {0x54u, 0x01u},\r
+ {0x31u, 0x07u},\r
+ {0x32u, 0x08u},\r
+ {0x33u, 0x08u},\r
+ {0x34u, 0x04u},\r
+ {0x35u, 0xE0u},\r
+ {0x36u, 0x02u},\r
+ {0x37u, 0x10u},\r
+ {0x3Eu, 0x55u},\r
+ {0x3Fu, 0x44u},\r
+ {0x40u, 0x53u},\r
+ {0x41u, 0x06u},\r
+ {0x42u, 0x40u},\r
+ {0x45u, 0xC2u},\r
+ {0x46u, 0x0Eu},\r
+ {0x47u, 0xDFu},\r
+ {0x48u, 0x37u},\r
+ {0x49u, 0xFFu},\r
+ {0x4Au, 0xFFu},\r
+ {0x4Bu, 0xFFu},\r
+ {0x4Fu, 0x2Cu},\r
+ {0x56u, 0x01u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
+ {0x5Au, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
- {0x5Du, 0x10u},\r
+ {0x5Cu, 0x10u},\r
+ {0x5Du, 0x01u},\r
{0x5Fu, 0x01u},\r
- {0x82u, 0xFFu},\r
- {0x84u, 0x0Fu},\r
- {0x86u, 0xF0u},\r
- {0x87u, 0xFFu},\r
- {0x88u, 0x33u},\r
- {0x89u, 0xFFu},\r
- {0x8Au, 0xCCu},\r
- {0x92u, 0xFFu},\r
- {0x93u, 0xFFu},\r
- {0x94u, 0x55u},\r
- {0x95u, 0x0Fu},\r
- {0x96u, 0xAAu},\r
- {0x97u, 0xF0u},\r
- {0x9Au, 0xFFu},\r
- {0x9Cu, 0xFFu},\r
- {0x9Du, 0x33u},\r
- {0x9Fu, 0xCCu},\r
- {0xA1u, 0x96u},\r
- {0xA3u, 0x69u},\r
- {0xA4u, 0x69u},\r
- {0xA6u, 0x96u},\r
- {0xA7u, 0xFFu},\r
- {0xABu, 0xFFu},\r
- {0xADu, 0x55u},\r
- {0xAEu, 0xFFu},\r
- {0xAFu, 0xAAu},\r
- {0xB3u, 0xFFu},\r
- {0xB4u, 0xFFu},\r
- {0xBAu, 0x20u},\r
- {0xBBu, 0x08u},\r
- {0xD8u, 0x04u},\r
+ {0x62u, 0xC0u},\r
+ {0x66u, 0x80u},\r
+ {0x68u, 0x40u},\r
+ {0x69u, 0x40u},\r
+ {0x6Eu, 0x08u},\r
+ {0xADu, 0x01u},\r
+ {0xB1u, 0x01u},\r
+ {0xBFu, 0x01u},\r
+ {0xD6u, 0x08u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x60u},\r
- {0x01u, 0x12u},\r
- {0x04u, 0x04u},\r
- {0x07u, 0x88u},\r
- {0x09u, 0x08u},\r
- {0x0Au, 0x08u},\r
- {0x0Du, 0x42u},\r
- {0x0Eu, 0x04u},\r
- {0x0Fu, 0x20u},\r
- {0x14u, 0x02u},\r
- {0x17u, 0x04u},\r
- {0x19u, 0x03u},\r
- {0x1Au, 0x0Cu},\r
- {0x1Cu, 0x04u},\r
- {0x1Fu, 0x10u},\r
- {0x21u, 0x08u},\r
+ {0x06u, 0x80u},\r
+ {0x0Du, 0x20u},\r
+ {0x14u, 0x08u},\r
+ {0x16u, 0x40u},\r
+ {0x1Cu, 0x01u},\r
+ {0x1Du, 0x01u},\r
+ {0x1Eu, 0x04u},\r
+ {0x1Fu, 0x04u},\r
{0x23u, 0x40u},\r
- {0x26u, 0x08u},\r
- {0x27u, 0x10u},\r
- {0x29u, 0x01u},\r
- {0x2Cu, 0x08u},\r
- {0x2Eu, 0x04u},\r
- {0x2Fu, 0x81u},\r
- {0x30u, 0x20u},\r
- {0x32u, 0x01u},\r
- {0x34u, 0x02u},\r
- {0x36u, 0x88u},\r
- {0x39u, 0x10u},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x04u},\r
- {0x5Au, 0x02u},\r
- {0x5Bu, 0x42u},\r
- {0x5Cu, 0x28u},\r
- {0x5Du, 0x81u},\r
- {0x65u, 0x40u},\r
- {0x6Cu, 0x21u},\r
- {0x6Eu, 0x89u},\r
- {0x6Fu, 0x08u},\r
- {0x74u, 0x81u},\r
- {0x76u, 0x24u},\r
- {0x80u, 0x20u},\r
- {0x85u, 0x80u},\r
- {0x8Au, 0x04u},\r
- {0x8Bu, 0x84u},\r
- {0x8Cu, 0x01u},\r
- {0x8Du, 0x20u},\r
- {0x90u, 0x40u},\r
- {0x91u, 0x80u},\r
- {0x92u, 0x10u},\r
- {0x93u, 0x02u},\r
- {0x94u, 0x01u},\r
- {0x97u, 0x44u},\r
- {0x98u, 0x02u},\r
- {0x99u, 0x40u},\r
- {0x9Bu, 0x06u},\r
- {0x9Eu, 0x24u},\r
- {0xA1u, 0x80u},\r
- {0xA2u, 0x80u},\r
- {0xA3u, 0x10u},\r
- {0xA4u, 0x11u},\r
- {0xA5u, 0x02u},\r
- {0xA6u, 0x64u},\r
- {0xA7u, 0x08u},\r
- {0xAAu, 0x04u},\r
- {0xACu, 0x01u},\r
- {0xAEu, 0x03u},\r
- {0xB0u, 0x40u},\r
- {0xB7u, 0x04u},\r
- {0xC0u, 0x79u},\r
- {0xC2u, 0xF6u},\r
- {0xC4u, 0xA0u},\r
- {0xCAu, 0xF1u},\r
- {0xCCu, 0xD5u},\r
- {0xCEu, 0x64u},\r
- {0xD6u, 0xF8u},\r
- {0xD8u, 0x10u},\r
- {0xE2u, 0x90u},\r
- {0xE4u, 0x70u},\r
- {0xEAu, 0x20u},\r
- {0xECu, 0x10u},\r
- {0xEEu, 0x04u},\r
- {0x81u, 0x40u},\r
- {0x82u, 0x12u},\r
- {0x87u, 0x40u},\r
- {0x89u, 0x40u},\r
- {0x8Au, 0x20u},\r
- {0x8Fu, 0x10u},\r
- {0x90u, 0x40u},\r
- {0x92u, 0x01u},\r
- {0x93u, 0x02u},\r
- {0x94u, 0x01u},\r
- {0x97u, 0x04u},\r
- {0x98u, 0x02u},\r
- {0x9Bu, 0x02u},\r
- {0x9Cu, 0x40u},\r
- {0x9Eu, 0x26u},\r
- {0xA1u, 0x80u},\r
- {0xA2u, 0x80u},\r
- {0xA4u, 0x10u},\r
- {0xA5u, 0x02u},\r
- {0xA6u, 0x66u},\r
- {0xA7u, 0x08u},\r
- {0xA8u, 0x02u},\r
- {0xAEu, 0x04u},\r
+ {0x24u, 0x08u},\r
+ {0x25u, 0x88u},\r
+ {0x26u, 0x12u},\r
+ {0x27u, 0x04u},\r
+ {0x2Bu, 0x01u},\r
+ {0x2Du, 0x04u},\r
+ {0x2Eu, 0x20u},\r
+ {0x31u, 0xCCu},\r
+ {0x35u, 0x10u},\r
+ {0x36u, 0x02u},\r
+ {0x37u, 0x04u},\r
+ {0x3Cu, 0x04u},\r
+ {0x3Du, 0x22u},\r
+ {0x3Fu, 0x20u},\r
+ {0x45u, 0x06u},\r
+ {0x46u, 0x30u},\r
+ {0x47u, 0x08u},\r
+ {0x4Cu, 0x84u},\r
+ {0x4Du, 0x04u},\r
+ {0x4Eu, 0x82u},\r
+ {0x54u, 0x08u},\r
+ {0x56u, 0x01u},\r
+ {0x57u, 0x42u},\r
+ {0x58u, 0x20u},\r
+ {0x59u, 0x80u},\r
+ {0x5Cu, 0x01u},\r
+ {0x5Du, 0x20u},\r
+ {0x5Eu, 0x04u},\r
+ {0x5Fu, 0x40u},\r
+ {0x60u, 0x02u},\r
+ {0x63u, 0x09u},\r
+ {0x65u, 0x45u},\r
+ {0x67u, 0x08u},\r
+ {0x6Cu, 0x10u},\r
+ {0x6Du, 0x41u},\r
+ {0x6Eu, 0x10u},\r
+ {0x75u, 0x08u},\r
+ {0x76u, 0x0Au},\r
+ {0x77u, 0x40u},\r
+ {0x80u, 0x04u},\r
+ {0x86u, 0x40u},\r
+ {0x89u, 0x04u},\r
+ {0x8Eu, 0x08u},\r
+ {0x8Fu, 0x0Cu},\r
+ {0x92u, 0x88u},\r
+ {0x93u, 0x80u},\r
+ {0x94u, 0x2Cu},\r
+ {0x95u, 0x44u},\r
+ {0x96u, 0x40u},\r
+ {0x98u, 0x28u},\r
+ {0x99u, 0x20u},\r
+ {0x9Au, 0x40u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Du, 0x08u},\r
+ {0xA1u, 0x23u},\r
+ {0xA2u, 0x04u},\r
+ {0xA3u, 0x91u},\r
+ {0xA4u, 0x02u},\r
+ {0xA6u, 0x92u},\r
+ {0xA7u, 0x42u},\r
+ {0xA9u, 0x01u},\r
+ {0xAAu, 0x10u},\r
+ {0xB0u, 0xA0u},\r
{0xB2u, 0x04u},\r
- {0xB3u, 0x08u},\r
- {0xB4u, 0x90u},\r
- {0xB7u, 0x04u},\r
- {0xE0u, 0x90u},\r
- {0xE2u, 0x48u},\r
- {0xE4u, 0x02u},\r
- {0xE6u, 0x80u},\r
- {0xE8u, 0x40u},\r
- {0xEAu, 0x02u},\r
- {0xECu, 0x88u},\r
- {0xEEu, 0x40u},\r
- {0x02u, 0x08u},\r
- {0x05u, 0x01u},\r
- {0x06u, 0x10u},\r
- {0x0Cu, 0x0Au},\r
- {0x0Du, 0x02u},\r
- {0x0Eu, 0x05u},\r
- {0x0Fu, 0x04u},\r
- {0x10u, 0x09u},\r
- {0x12u, 0x02u},\r
- {0x17u, 0x04u},\r
- {0x18u, 0x04u},\r
- {0x1Au, 0x08u},\r
- {0x1Bu, 0x02u},\r
- {0x1Eu, 0x07u},\r
- {0x20u, 0x20u},\r
- {0x22u, 0x40u},\r
- {0x26u, 0x20u},\r
- {0x2Eu, 0x40u},\r
- {0x30u, 0x10u},\r
- {0x33u, 0x06u},\r
- {0x34u, 0x60u},\r
- {0x35u, 0x01u},\r
- {0x36u, 0x0Fu},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x04u},\r
+ {0xB3u, 0x40u},\r
+ {0xB7u, 0x40u},\r
+ {0xC0u, 0x10u},\r
+ {0xC2u, 0x40u},\r
+ {0xC4u, 0x50u},\r
+ {0xCAu, 0x68u},\r
+ {0xCCu, 0xE0u},\r
+ {0xCEu, 0xE0u},\r
+ {0xD0u, 0xC0u},\r
+ {0xD2u, 0x30u},\r
+ {0xD6u, 0xFCu},\r
+ {0xD8u, 0xFCu},\r
+ {0xE2u, 0x50u},\r
+ {0xE4u, 0x80u},\r
+ {0xE6u, 0x48u},\r
+ {0xE8u, 0x0Cu},\r
+ {0xEAu, 0x01u},\r
+ {0xEEu, 0xC2u},\r
+ {0x01u, 0x01u},\r
+ {0x02u, 0x04u},\r
+ {0x03u, 0x06u},\r
+ {0x05u, 0x4Au},\r
+ {0x07u, 0x15u},\r
+ {0x0Fu, 0x40u},\r
+ {0x10u, 0x01u},\r
+ {0x11u, 0x22u},\r
+ {0x13u, 0x45u},\r
+ {0x17u, 0x38u},\r
+ {0x19u, 0x53u},\r
+ {0x1Au, 0x02u},\r
+ {0x1Bu, 0x2Cu},\r
+ {0x21u, 0x01u},\r
+ {0x27u, 0x01u},\r
+ {0x2Cu, 0x02u},\r
+ {0x2Eu, 0x04u},\r
+ {0x30u, 0x06u},\r
+ {0x31u, 0x07u},\r
+ {0x33u, 0x78u},\r
+ {0x34u, 0x01u},\r
+ {0x3Bu, 0x02u},\r
+ {0x3Eu, 0x11u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
+ {0x5Cu, 0x10u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x50u},\r
- {0x85u, 0x09u},\r
- {0x86u, 0xA0u},\r
- {0x87u, 0x06u},\r
- {0x88u, 0x60u},\r
- {0x89u, 0x03u},\r
- {0x8Au, 0x90u},\r
- {0x8Bu, 0x0Cu},\r
- {0x8Cu, 0x0Fu},\r
- {0x8Eu, 0xF0u},\r
- {0x8Fu, 0xFFu},\r
- {0x91u, 0x0Fu},\r
- {0x93u, 0xF0u},\r
- {0x95u, 0x30u},\r
- {0x97u, 0xC0u},\r
- {0x9Bu, 0xFFu},\r
- {0x9Cu, 0x05u},\r
- {0x9Du, 0x90u},\r
- {0x9Eu, 0x0Au},\r
- {0x9Fu, 0x60u},\r
- {0xA3u, 0xFFu},\r
- {0xA4u, 0x03u},\r
- {0xA5u, 0x05u},\r
- {0xA6u, 0x0Cu},\r
- {0xA7u, 0x0Au},\r
- {0xA8u, 0x06u},\r
- {0xA9u, 0x50u},\r
- {0xAAu, 0x09u},\r
- {0xABu, 0xA0u},\r
- {0xACu, 0x30u},\r
- {0xAEu, 0xC0u},\r
- {0xB3u, 0xFFu},\r
- {0xB6u, 0xFFu},\r
- {0xBEu, 0x40u},\r
- {0xBFu, 0x04u},\r
+ {0x82u, 0x07u},\r
+ {0x83u, 0x3Fu},\r
+ {0x85u, 0x10u},\r
+ {0x86u, 0x80u},\r
+ {0x87u, 0x01u},\r
+ {0x8Au, 0x08u},\r
+ {0x8Du, 0x30u},\r
+ {0x8Fu, 0xC0u},\r
+ {0x91u, 0x70u},\r
+ {0x93u, 0x8Cu},\r
+ {0x94u, 0x99u},\r
+ {0x95u, 0x6Fu},\r
+ {0x96u, 0x22u},\r
+ {0x97u, 0x90u},\r
+ {0x99u, 0x57u},\r
+ {0x9Au, 0x70u},\r
+ {0x9Bu, 0xA0u},\r
+ {0x9Cu, 0x44u},\r
+ {0x9Du, 0x03u},\r
+ {0x9Eu, 0x88u},\r
+ {0xA1u, 0x08u},\r
+ {0xA3u, 0x03u},\r
+ {0xA4u, 0xAAu},\r
+ {0xA6u, 0x55u},\r
+ {0xA7u, 0x20u},\r
+ {0xADu, 0x02u},\r
+ {0xB4u, 0xF0u},\r
+ {0xB5u, 0x0Fu},\r
+ {0xB6u, 0x0Fu},\r
+ {0xB7u, 0xF0u},\r
+ {0xBBu, 0x80u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDCu, 0x11u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x09u},\r
- {0x02u, 0x02u},\r
- {0x06u, 0x24u},\r
- {0x07u, 0x02u},\r
- {0x09u, 0x02u},\r
- {0x0Au, 0x01u},\r
- {0x0Bu, 0x04u},\r
- {0x0Eu, 0x01u},\r
- {0x11u, 0x04u},\r
- {0x13u, 0x82u},\r
- {0x14u, 0x04u},\r
- {0x16u, 0x02u},\r
+ {0x01u, 0x02u},\r
+ {0x04u, 0x21u},\r
+ {0x05u, 0x08u},\r
+ {0x08u, 0x02u},\r
+ {0x0Au, 0x08u},\r
+ {0x0Eu, 0x2Au},\r
+ {0x10u, 0x02u},\r
{0x17u, 0x08u},\r
- {0x18u, 0x40u},\r
- {0x1Au, 0x05u},\r
- {0x1Du, 0x80u},\r
- {0x1Fu, 0x80u},\r
- {0x20u, 0x08u},\r
+ {0x19u, 0x21u},\r
+ {0x1Cu, 0x01u},\r
+ {0x1Eu, 0x08u},\r
+ {0x1Fu, 0x40u},\r
+ {0x21u, 0x0Bu},\r
{0x22u, 0x04u},\r
- {0x24u, 0x20u},\r
- {0x2Cu, 0x20u},\r
- {0x2Fu, 0x88u},\r
- {0x30u, 0x20u},\r
- {0x33u, 0x08u},\r
- {0x36u, 0x64u},\r
- {0x37u, 0x82u},\r
- {0x38u, 0x04u},\r
- {0x39u, 0x40u},\r
- {0x3Cu, 0x20u},\r
- {0x3Du, 0x04u},\r
- {0x3Fu, 0x88u},\r
- {0x58u, 0x40u},\r
- {0x5Bu, 0x10u},\r
- {0x5Cu, 0x80u},\r
- {0x60u, 0x04u},\r
- {0x62u, 0x80u},\r
- {0x64u, 0x02u},\r
- {0x69u, 0x40u},\r
- {0x6Bu, 0x02u},\r
- {0x83u, 0x40u},\r
- {0x88u, 0x24u},\r
- {0x8Fu, 0x11u},\r
- {0xC0u, 0xEDu},\r
- {0xC2u, 0x8Bu},\r
- {0xC4u, 0xEDu},\r
- {0xCAu, 0xE0u},\r
- {0xCCu, 0xF6u},\r
- {0xCEu, 0x7Au},\r
- {0xD6u, 0x1Cu},\r
- {0xD8u, 0x1Cu},\r
+ {0x25u, 0x40u},\r
+ {0x26u, 0x20u},\r
+ {0x27u, 0x08u},\r
+ {0x2Au, 0x08u},\r
+ {0x2Bu, 0x80u},\r
+ {0x2Du, 0x04u},\r
+ {0x2Fu, 0x82u},\r
+ {0x31u, 0x08u},\r
+ {0x32u, 0x22u},\r
+ {0x36u, 0x93u},\r
+ {0x37u, 0x08u},\r
+ {0x38u, 0x08u},\r
+ {0x39u, 0x42u},\r
+ {0x3Cu, 0x04u},\r
+ {0x3Du, 0x82u},\r
+ {0x58u, 0x80u},\r
+ {0x5Au, 0x10u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Eu, 0x44u},\r
+ {0x5Fu, 0x10u},\r
+ {0x61u, 0x20u},\r
+ {0x63u, 0x22u},\r
+ {0x64u, 0x08u},\r
+ {0x66u, 0x40u},\r
+ {0x67u, 0x20u},\r
+ {0x81u, 0x01u},\r
+ {0x82u, 0x48u},\r
+ {0x83u, 0x88u},\r
+ {0x87u, 0x10u},\r
+ {0x88u, 0x08u},\r
+ {0x89u, 0x40u},\r
+ {0x8Bu, 0x10u},\r
+ {0x8Du, 0x02u},\r
+ {0x8Fu, 0x04u},\r
+ {0xC0u, 0x78u},\r
+ {0xC2u, 0xEAu},\r
+ {0xC4u, 0x21u},\r
+ {0xCAu, 0xD3u},\r
+ {0xCCu, 0xF7u},\r
+ {0xCEu, 0xDBu},\r
+ {0xD6u, 0x7Eu},\r
+ {0xD8u, 0x7Eu},\r
{0xE0u, 0x40u},\r
- {0xE4u, 0xA0u},\r
- {0xE6u, 0x02u},\r
+ {0xE2u, 0xA0u},\r
+ {0xE6u, 0x20u},\r
{0x00u, 0x09u},\r
{0x02u, 0x06u},\r
- {0x04u, 0x03u},\r
- {0x05u, 0x03u},\r
- {0x06u, 0x0Cu},\r
- {0x07u, 0x0Cu},\r
- {0x08u, 0x05u},\r
+ {0x04u, 0x30u},\r
+ {0x05u, 0x30u},\r
+ {0x06u, 0xC0u},\r
+ {0x07u, 0xC0u},\r
{0x09u, 0x50u},\r
- {0x0Au, 0x0Au},\r
+ {0x0Au, 0xFFu},\r
{0x0Bu, 0xA0u},\r
- {0x0Du, 0x0Fu},\r
- {0x0Fu, 0xF0u},\r
- {0x10u, 0x0Fu},\r
- {0x12u, 0xF0u},\r
- {0x15u, 0x05u},\r
+ {0x0Cu, 0x05u},\r
+ {0x0Du, 0x06u},\r
+ {0x0Eu, 0x0Au},\r
+ {0x0Fu, 0x09u},\r
+ {0x11u, 0x0Fu},\r
+ {0x13u, 0xF0u},\r
{0x16u, 0xFFu},\r
- {0x17u, 0x0Au},\r
- {0x18u, 0xFFu},\r
+ {0x1Au, 0xFFu},\r
{0x1Bu, 0xFFu},\r
- {0x1Cu, 0x90u},\r
- {0x1Du, 0xFFu},\r
- {0x1Eu, 0x60u},\r
- {0x20u, 0xFFu},\r
- {0x21u, 0x60u},\r
- {0x23u, 0x90u},\r
- {0x24u, 0x50u},\r
- {0x26u, 0xA0u},\r
- {0x27u, 0xFFu},\r
- {0x28u, 0x30u},\r
- {0x29u, 0x30u},\r
- {0x2Au, 0xC0u},\r
- {0x2Bu, 0xC0u},\r
- {0x2Du, 0x06u},\r
- {0x2Fu, 0x09u},\r
+ {0x1Cu, 0x0Fu},\r
+ {0x1Du, 0x03u},\r
+ {0x1Eu, 0xF0u},\r
+ {0x1Fu, 0x0Cu},\r
+ {0x20u, 0x03u},\r
+ {0x21u, 0x05u},\r
+ {0x22u, 0x0Cu},\r
+ {0x23u, 0x0Au},\r
+ {0x25u, 0xFFu},\r
+ {0x28u, 0x50u},\r
+ {0x2Au, 0xA0u},\r
+ {0x2Bu, 0xFFu},\r
+ {0x2Cu, 0x90u},\r
+ {0x2Du, 0x60u},\r
+ {0x2Eu, 0x60u},\r
+ {0x2Fu, 0x90u},\r
{0x30u, 0xFFu},\r
{0x31u, 0xFFu},\r
{0x3Eu, 0x01u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x22u},\r
- {0x82u, 0x10u},\r
- {0x83u, 0x9Fu},\r
- {0x84u, 0x17u},\r
- {0x85u, 0xC0u},\r
- {0x86u, 0x28u},\r
- {0x87u, 0x04u},\r
- {0x88u, 0x29u},\r
- {0x89u, 0xC0u},\r
- {0x8Au, 0x16u},\r
- {0x8Bu, 0x08u},\r
- {0x8Cu, 0x16u},\r
- {0x8Du, 0x80u},\r
- {0x90u, 0x04u},\r
- {0x91u, 0x7Fu},\r
- {0x93u, 0x80u},\r
- {0x94u, 0x40u},\r
- {0x97u, 0x60u},\r
- {0x98u, 0x12u},\r
- {0x99u, 0x1Fu},\r
- {0x9Au, 0x04u},\r
- {0x9Bu, 0x20u},\r
- {0x9Cu, 0x16u},\r
- {0x9Du, 0xC0u},\r
- {0x9Fu, 0x01u},\r
- {0xA0u, 0x31u},\r
- {0xA1u, 0xC0u},\r
- {0xA2u, 0x0Eu},\r
- {0xA3u, 0x02u},\r
- {0xA4u, 0x40u},\r
- {0xA7u, 0xFFu},\r
- {0xA8u, 0x10u},\r
- {0xAAu, 0x06u},\r
- {0xACu, 0x06u},\r
- {0xADu, 0x90u},\r
- {0xAEu, 0x10u},\r
- {0xAFu, 0x40u},\r
- {0xB0u, 0x30u},\r
- {0xB2u, 0x40u},\r
- {0xB4u, 0x0Fu},\r
- {0xB5u, 0xFFu},\r
- {0xB8u, 0x28u},\r
- {0xBAu, 0x02u},\r
+ {0x80u, 0x01u},\r
+ {0x81u, 0x68u},\r
+ {0x85u, 0x12u},\r
+ {0x87u, 0xE1u},\r
+ {0x89u, 0x08u},\r
+ {0x8Bu, 0x60u},\r
+ {0x8Fu, 0x08u},\r
+ {0x91u, 0x60u},\r
+ {0x93u, 0x08u},\r
+ {0x95u, 0x28u},\r
+ {0x97u, 0x40u},\r
+ {0x99u, 0x91u},\r
+ {0x9Bu, 0x64u},\r
+ {0x9Du, 0x06u},\r
+ {0xA1u, 0x68u},\r
+ {0xA5u, 0x40u},\r
+ {0xA9u, 0x71u},\r
+ {0xABu, 0x82u},\r
+ {0xADu, 0x20u},\r
+ {0xB1u, 0x07u},\r
+ {0xB3u, 0xF0u},\r
+ {0xB5u, 0x08u},\r
+ {0xB6u, 0x01u},\r
+ {0xB9u, 0x0Au},\r
{0xBFu, 0x10u},\r
+ {0xC0u, 0x62u},\r
+ {0xC1u, 0x03u},\r
+ {0xC2u, 0x10u},\r
+ {0xC4u, 0x04u},\r
+ {0xC5u, 0xBEu},\r
+ {0xC6u, 0xFDu},\r
+ {0xC7u, 0xBCu},\r
+ {0xC8u, 0x3Fu},\r
+ {0xC9u, 0xFFu},\r
+ {0xCAu, 0xFFu},\r
+ {0xCBu, 0xFFu},\r
+ {0xCCu, 0x22u},\r
+ {0xCEu, 0xF0u},\r
+ {0xCFu, 0x08u},\r
+ {0xD0u, 0x04u},\r
{0xD4u, 0x40u},\r
{0xD6u, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDAu, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDCu, 0x09u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x04u},\r
- {0x02u, 0x48u},\r
- {0x05u, 0x91u},\r
- {0x07u, 0x20u},\r
- {0x08u, 0x50u},\r
- {0x0Au, 0x20u},\r
- {0x0Bu, 0x40u},\r
- {0x0Eu, 0x25u},\r
- {0x0Fu, 0x80u},\r
- {0x10u, 0x84u},\r
- {0x12u, 0x10u},\r
- {0x15u, 0x50u},\r
- {0x17u, 0x09u},\r
- {0x1Bu, 0x02u},\r
- {0x1Du, 0x15u},\r
- {0x1Eu, 0x40u},\r
- {0x1Fu, 0x20u},\r
- {0x21u, 0x01u},\r
- {0x27u, 0x08u},\r
- {0x28u, 0x54u},\r
- {0x2Au, 0x48u},\r
- {0x2Bu, 0x05u},\r
- {0x2Du, 0x40u},\r
- {0x2Eu, 0x01u},\r
- {0x2Fu, 0x20u},\r
+ {0xE2u, 0xC0u},\r
+ {0xE4u, 0x40u},\r
+ {0xE5u, 0x01u},\r
+ {0xE6u, 0x10u},\r
+ {0xE7u, 0x11u},\r
+ {0xE8u, 0xC0u},\r
+ {0xE9u, 0x01u},\r
+ {0xEBu, 0x11u},\r
+ {0xECu, 0x40u},\r
+ {0xEDu, 0x01u},\r
+ {0xEEu, 0x40u},\r
+ {0xEFu, 0x01u},\r
+ {0x00u, 0x92u},\r
+ {0x01u, 0x04u},\r
+ {0x02u, 0x41u},\r
+ {0x03u, 0x08u},\r
+ {0x04u, 0x02u},\r
+ {0x08u, 0x10u},\r
+ {0x0Au, 0x26u},\r
+ {0x0Bu, 0x22u},\r
+ {0x10u, 0x81u},\r
+ {0x11u, 0x50u},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Fu, 0x40u},\r
+ {0x21u, 0x02u},\r
+ {0x24u, 0x20u},\r
+ {0x26u, 0x18u},\r
+ {0x27u, 0x60u},\r
+ {0x28u, 0x11u},\r
+ {0x2Au, 0x01u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Eu, 0x4Au},\r
+ {0x2Fu, 0x04u},\r
{0x30u, 0x80u},\r
- {0x32u, 0x5Cu},\r
- {0x33u, 0x10u},\r
- {0x35u, 0x84u},\r
- {0x37u, 0x21u},\r
- {0x38u, 0x04u},\r
- {0x3Au, 0x10u},\r
- {0x3Bu, 0x60u},\r
- {0x3Du, 0x12u},\r
- {0x3Eu, 0x54u},\r
- {0x64u, 0xA0u},\r
- {0x66u, 0x20u},\r
- {0x67u, 0x01u},\r
- {0x84u, 0x80u},\r
- {0x8Eu, 0x04u},\r
- {0x90u, 0x04u},\r
- {0x91u, 0x40u},\r
- {0x92u, 0x9Du},\r
- {0x93u, 0x61u},\r
- {0x95u, 0x02u},\r
- {0x98u, 0x60u},\r
- {0x99u, 0x80u},\r
- {0x9Au, 0x28u},\r
- {0x9Bu, 0x31u},\r
- {0x9Du, 0x15u},\r
- {0xA1u, 0x01u},\r
- {0xA2u, 0x14u},\r
- {0xA3u, 0x45u},\r
- {0xA7u, 0x02u},\r
- {0xA8u, 0x05u},\r
- {0xAAu, 0x01u},\r
- {0xB1u, 0x30u},\r
- {0xB2u, 0x80u},\r
- {0xC0u, 0xFEu},\r
- {0xC2u, 0xFFu},\r
- {0xC4u, 0xFEu},\r
- {0xCAu, 0xDFu},\r
- {0xCCu, 0xFEu},\r
+ {0x32u, 0x11u},\r
+ {0x35u, 0x80u},\r
+ {0x36u, 0x04u},\r
+ {0x37u, 0x61u},\r
+ {0x39u, 0x14u},\r
+ {0x3Au, 0x40u},\r
+ {0x3Cu, 0x04u},\r
+ {0x3Eu, 0x91u},\r
+ {0x44u, 0x80u},\r
+ {0x45u, 0xA8u},\r
+ {0x4Cu, 0x40u},\r
+ {0x4Eu, 0x08u},\r
+ {0x4Fu, 0x04u},\r
+ {0x54u, 0x02u},\r
+ {0x56u, 0x98u},\r
+ {0x5Eu, 0x20u},\r
+ {0x5Fu, 0x10u},\r
+ {0x66u, 0x90u},\r
+ {0x67u, 0x50u},\r
+ {0x80u, 0x80u},\r
+ {0x84u, 0x40u},\r
+ {0x87u, 0x40u},\r
+ {0x88u, 0xC0u},\r
+ {0x8Bu, 0x40u},\r
+ {0x8Fu, 0x01u},\r
+ {0x90u, 0x16u},\r
+ {0x91u, 0x54u},\r
+ {0x92u, 0x55u},\r
+ {0x93u, 0x28u},\r
+ {0x94u, 0xA0u},\r
+ {0x96u, 0x02u},\r
+ {0x97u, 0x04u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Bu, 0x01u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Du, 0x80u},\r
+ {0x9Eu, 0x08u},\r
+ {0x9Fu, 0x20u},\r
+ {0xA0u, 0x01u},\r
+ {0xA1u, 0xA8u},\r
+ {0xA2u, 0x04u},\r
+ {0xA4u, 0xC2u},\r
+ {0xA5u, 0x02u},\r
+ {0xA7u, 0x01u},\r
+ {0xAAu, 0x10u},\r
+ {0xACu, 0x01u},\r
+ {0xC0u, 0x1Fu},\r
+ {0xC2u, 0x07u},\r
+ {0xC4u, 0x0Bu},\r
+ {0xCAu, 0xFFu},\r
+ {0xCCu, 0xFDu},\r
{0xCEu, 0xFEu},\r
+ {0xD0u, 0xF0u},\r
+ {0xD2u, 0x20u},\r
{0xD8u, 0xF0u},\r
- {0xE2u, 0x40u},\r
- {0xEAu, 0x04u},\r
- {0x80u, 0x08u},\r
- {0x82u, 0x84u},\r
- {0x87u, 0x80u},\r
- {0x88u, 0x02u},\r
- {0x8Au, 0x41u},\r
- {0x8Bu, 0x07u},\r
- {0x8Cu, 0x04u},\r
- {0x8Eu, 0x28u},\r
- {0x90u, 0x53u},\r
- {0x91u, 0xAAu},\r
- {0x92u, 0xACu},\r
- {0x93u, 0x55u},\r
- {0x94u, 0x01u},\r
- {0x95u, 0x99u},\r
- {0x96u, 0x12u},\r
- {0x97u, 0x22u},\r
- {0x9Bu, 0x70u},\r
- {0xA3u, 0x08u},\r
- {0xA5u, 0x44u},\r
- {0xA7u, 0x88u},\r
- {0xB0u, 0x0Fu},\r
- {0xB3u, 0x0Fu},\r
- {0xB4u, 0xC0u},\r
- {0xB5u, 0xF0u},\r
- {0xB6u, 0x30u},\r
- {0xBEu, 0x51u},\r
+ {0xE2u, 0x22u},\r
+ {0xEEu, 0x08u},\r
+ {0x01u, 0x41u},\r
+ {0x04u, 0x91u},\r
+ {0x05u, 0x41u},\r
+ {0x06u, 0x0Eu},\r
+ {0x08u, 0x08u},\r
+ {0x09u, 0x40u},\r
+ {0x0Au, 0x10u},\r
+ {0x0Cu, 0x6Cu},\r
+ {0x10u, 0x24u},\r
+ {0x11u, 0x01u},\r
+ {0x13u, 0x40u},\r
+ {0x14u, 0x40u},\r
+ {0x15u, 0x04u},\r
+ {0x16u, 0x2Cu},\r
+ {0x18u, 0x80u},\r
+ {0x19u, 0x88u},\r
+ {0x1Au, 0x2Fu},\r
+ {0x1Bu, 0x61u},\r
+ {0x1Cu, 0x6Cu},\r
+ {0x1Du, 0x81u},\r
+ {0x1Fu, 0x40u},\r
+ {0x20u, 0x2Cu},\r
+ {0x21u, 0x41u},\r
+ {0x22u, 0x40u},\r
+ {0x24u, 0xB1u},\r
+ {0x25u, 0xE2u},\r
+ {0x26u, 0x02u},\r
+ {0x27u, 0x08u},\r
+ {0x28u, 0x64u},\r
+ {0x29u, 0x47u},\r
+ {0x2Au, 0x08u},\r
+ {0x2Bu, 0x98u},\r
+ {0x2Du, 0x10u},\r
+ {0x30u, 0x80u},\r
+ {0x31u, 0x08u},\r
+ {0x32u, 0x0Fu},\r
+ {0x34u, 0x31u},\r
+ {0x35u, 0x3Fu},\r
+ {0x36u, 0x40u},\r
+ {0x37u, 0xC0u},\r
+ {0x39u, 0x20u},\r
+ {0x3Au, 0x30u},\r
+ {0x3Bu, 0x80u},\r
+ {0x3Eu, 0x41u},\r
+ {0x3Fu, 0x11u},\r
+ {0x56u, 0x02u},\r
+ {0x57u, 0x2Cu},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x80u, 0x06u},\r
+ {0x82u, 0x09u},\r
+ {0x84u, 0x30u},\r
+ {0x86u, 0xC0u},\r
+ {0x88u, 0xFFu},\r
+ {0x8Cu, 0x05u},\r
+ {0x8Eu, 0x0Au},\r
+ {0x91u, 0x01u},\r
+ {0x96u, 0xFFu},\r
+ {0x9Au, 0xFFu},\r
+ {0x9Cu, 0x0Fu},\r
+ {0x9Eu, 0xF0u},\r
+ {0xA0u, 0x03u},\r
+ {0xA1u, 0x01u},\r
+ {0xA2u, 0x0Cu},\r
+ {0xA5u, 0x01u},\r
+ {0xA8u, 0x50u},\r
+ {0xAAu, 0xA0u},\r
+ {0xACu, 0x60u},\r
+ {0xADu, 0x01u},\r
+ {0xAEu, 0x90u},\r
+ {0xB4u, 0xFFu},\r
+ {0xB5u, 0x01u},\r
+ {0xB9u, 0x20u},\r
+ {0xBEu, 0x10u},\r
+ {0xBFu, 0x10u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDCu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x20u},\r
- {0x01u, 0x01u},\r
- {0x02u, 0x01u},\r
- {0x05u, 0x95u},\r
- {0x07u, 0x08u},\r
- {0x08u, 0x20u},\r
- {0x09u, 0x10u},\r
- {0x0Bu, 0x50u},\r
- {0x0Cu, 0x02u},\r
- {0x0Eu, 0x09u},\r
- {0x15u, 0x64u},\r
- {0x17u, 0x21u},\r
- {0x18u, 0x02u},\r
- {0x19u, 0x20u},\r
- {0x1Au, 0x80u},\r
- {0x1Eu, 0x28u},\r
- {0x20u, 0x04u},\r
- {0x21u, 0x20u},\r
- {0x23u, 0x10u},\r
- {0x24u, 0x01u},\r
- {0x25u, 0x10u},\r
- {0x26u, 0x03u},\r
- {0x27u, 0x21u},\r
- {0x2Au, 0x02u},\r
- {0x2Bu, 0x20u},\r
- {0x2Eu, 0x85u},\r
- {0x31u, 0x2Au},\r
- {0x35u, 0x81u},\r
- {0x37u, 0x28u},\r
- {0x39u, 0x08u},\r
+ {0x00u, 0x92u},\r
+ {0x01u, 0x04u},\r
+ {0x02u, 0x40u},\r
+ {0x05u, 0x20u},\r
+ {0x06u, 0x0Au},\r
+ {0x07u, 0x20u},\r
+ {0x0Au, 0x06u},\r
+ {0x0Bu, 0x20u},\r
+ {0x0Du, 0x20u},\r
+ {0x0Eu, 0x91u},\r
+ {0x10u, 0x80u},\r
+ {0x11u, 0x52u},\r
+ {0x16u, 0x20u},\r
+ {0x17u, 0x11u},\r
+ {0x1Bu, 0x10u},\r
+ {0x1Cu, 0x04u},\r
+ {0x1Du, 0xA8u},\r
+ {0x1Eu, 0x22u},\r
+ {0x1Fu, 0x25u},\r
+ {0x22u, 0x10u},\r
+ {0x24u, 0x40u},\r
+ {0x26u, 0x40u},\r
+ {0x27u, 0x08u},\r
+ {0x2Bu, 0x51u},\r
+ {0x2Cu, 0x02u},\r
+ {0x2Eu, 0x22u},\r
+ {0x2Fu, 0x24u},\r
+ {0x31u, 0x02u},\r
+ {0x36u, 0x40u},\r
+ {0x37u, 0x25u},\r
+ {0x3Au, 0x04u},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Du, 0x08u},\r
+ {0x3Eu, 0x11u},\r
+ {0x5Eu, 0xC0u},\r
+ {0x67u, 0x80u},\r
+ {0x6Du, 0x08u},\r
+ {0x6Eu, 0x19u},\r
+ {0x6Fu, 0x11u},\r
+ {0x76u, 0x02u},\r
+ {0x90u, 0x12u},\r
+ {0x91u, 0x54u},\r
+ {0x92u, 0x04u},\r
+ {0x93u, 0xA0u},\r
+ {0x94u, 0xE4u},\r
+ {0x96u, 0x13u},\r
+ {0x97u, 0x0Eu},\r
+ {0x9Bu, 0x04u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Du, 0xA0u},\r
+ {0x9Eu, 0x66u},\r
+ {0x9Fu, 0x29u},\r
+ {0xA3u, 0x40u},\r
+ {0xA4u, 0x42u},\r
+ {0xA5u, 0x01u},\r
+ {0xA6u, 0x55u},\r
+ {0xAFu, 0x02u},\r
+ {0xB5u, 0x08u},\r
+ {0xC0u, 0xEFu},\r
+ {0xC2u, 0xF7u},\r
+ {0xC4u, 0x7Bu},\r
+ {0xCAu, 0xFBu},\r
+ {0xCCu, 0xF1u},\r
+ {0xCEu, 0xE0u},\r
+ {0xD8u, 0x80u},\r
+ {0xE2u, 0x08u},\r
+ {0xE8u, 0x08u},\r
+ {0xEAu, 0x40u},\r
+ {0x39u, 0x20u},\r
+ {0x3Fu, 0x10u},\r
+ {0x59u, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x27u, 0x08u},\r
+ {0x87u, 0x08u},\r
+ {0x91u, 0x40u},\r
+ {0x92u, 0x08u},\r
+ {0x93u, 0x80u},\r
+ {0xA1u, 0x40u},\r
+ {0xE8u, 0x08u},\r
+ {0x85u, 0x40u},\r
+ {0x8Bu, 0x40u},\r
+ {0x8Du, 0x40u},\r
+ {0x91u, 0x40u},\r
+ {0x93u, 0x80u},\r
+ {0xA1u, 0x40u},\r
+ {0xAEu, 0x04u},\r
+ {0xE2u, 0xC0u},\r
+ {0xE6u, 0x80u},\r
+ {0x13u, 0x10u},\r
+ {0x17u, 0x48u},\r
+ {0x33u, 0x02u},\r
+ {0x36u, 0x80u},\r
+ {0x37u, 0x08u},\r
+ {0x3Au, 0x01u},\r
{0x3Bu, 0x10u},\r
- {0x3Cu, 0x01u},\r
- {0x3Du, 0x48u},\r
- {0x3Eu, 0x10u},\r
- {0x47u, 0x29u},\r
- {0x4Cu, 0x04u},\r
- {0x4Eu, 0x02u},\r
- {0x4Fu, 0x05u},\r
- {0x54u, 0x02u},\r
- {0x55u, 0x05u},\r
- {0x56u, 0xA0u},\r
- {0x57u, 0x40u},\r
- {0x7Au, 0x80u},\r
- {0x7Bu, 0x40u},\r
- {0x89u, 0x20u},\r
- {0x8Eu, 0x40u},\r
- {0x91u, 0x4Du},\r
- {0x92u, 0x1Du},\r
- {0x93u, 0x60u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x32u},\r
- {0x96u, 0x80u},\r
- {0x97u, 0x04u},\r
- {0x98u, 0x40u},\r
- {0x99u, 0x80u},\r
- {0x9Au, 0x0Au},\r
- {0x9Bu, 0x10u},\r
- {0x9Du, 0x10u},\r
- {0x9Fu, 0x01u},\r
- {0xA0u, 0x10u},\r
- {0xA1u, 0x0Au},\r
- {0xA3u, 0x25u},\r
- {0xA4u, 0x02u},\r
- {0xA6u, 0x01u},\r
- {0xA7u, 0x02u},\r
- {0xA9u, 0x02u},\r
- {0xADu, 0x01u},\r
- {0xB3u, 0x10u},\r
- {0xB5u, 0x20u},\r
- {0xB7u, 0x04u},\r
- {0xC0u, 0xFBu},\r
- {0xC2u, 0xDCu},\r
- {0xC4u, 0xF0u},\r
- {0xCAu, 0xD3u},\r
- {0xCCu, 0xF7u},\r
- {0xCEu, 0xF6u},\r
- {0xD0u, 0xE0u},\r
- {0xD2u, 0x30u},\r
- {0xEAu, 0x08u},\r
- {0xEEu, 0x06u},\r
- {0x8Eu, 0x20u},\r
- {0xA0u, 0x80u},\r
- {0xA4u, 0x10u},\r
- {0xA6u, 0x20u},\r
- {0xA8u, 0x01u},\r
- {0xAEu, 0x01u},\r
- {0xB3u, 0x08u},\r
- {0xB6u, 0x04u},\r
- {0xB7u, 0x40u},\r
- {0xE0u, 0x30u},\r
- {0xE8u, 0x10u},\r
- {0xEAu, 0x60u},\r
- {0xEEu, 0x02u},\r
- {0xA8u, 0x80u},\r
- {0xB0u, 0x10u},\r
- {0xECu, 0x80u},\r
- {0x12u, 0x08u},\r
- {0x15u, 0x80u},\r
- {0x17u, 0x04u},\r
- {0x33u, 0x04u},\r
- {0x36u, 0x28u},\r
- {0x39u, 0x88u},\r
- {0x3Du, 0x44u},\r
- {0x43u, 0x80u},\r
- {0x56u, 0x08u},\r
- {0x5Au, 0x08u},\r
- {0x5Cu, 0x08u},\r
+ {0x3Cu, 0x80u},\r
+ {0x3Eu, 0x08u},\r
+ {0x43u, 0x10u},\r
+ {0x53u, 0x20u},\r
+ {0x59u, 0x04u},\r
{0x61u, 0x10u},\r
- {0x65u, 0x04u},\r
- {0x81u, 0x80u},\r
- {0x83u, 0x10u},\r
- {0x87u, 0x80u},\r
- {0x89u, 0x80u},\r
- {0x8Au, 0x04u},\r
+ {0x66u, 0x40u},\r
+ {0x67u, 0x08u},\r
+ {0x89u, 0x08u},\r
+ {0x8Au, 0x40u},\r
{0xC4u, 0xE0u},\r
{0xCCu, 0xE0u},\r
{0xCEu, 0xF0u},\r
{0xD0u, 0x10u},\r
- {0xD4u, 0x40u},\r
+ {0xD4u, 0x20u},\r
{0xD6u, 0xC0u},\r
{0xD8u, 0xC0u},\r
- {0xE2u, 0x20u},\r
- {0xE6u, 0x90u},\r
- {0x30u, 0x20u},\r
{0x32u, 0x04u},\r
- {0x34u, 0x01u},\r
- {0x36u, 0x40u},\r
- {0x51u, 0x80u},\r
- {0x57u, 0x10u},\r
- {0x59u, 0x80u},\r
- {0x62u, 0x08u},\r
- {0x81u, 0x04u},\r
- {0x82u, 0x08u},\r
+ {0x33u, 0x40u},\r
+ {0x34u, 0x08u},\r
+ {0x35u, 0x80u},\r
+ {0x3Au, 0x40u},\r
+ {0x50u, 0x80u},\r
+ {0x52u, 0x02u},\r
+ {0x55u, 0x08u},\r
+ {0x66u, 0x80u},\r
+ {0x80u, 0x80u},\r
+ {0x82u, 0x02u},\r
{0x84u, 0x08u},\r
- {0x8Au, 0x08u},\r
- {0x95u, 0x4Cu},\r
- {0x99u, 0x80u},\r
- {0x9Cu, 0x08u},\r
+ {0x8Au, 0x80u},\r
+ {0x97u, 0x08u},\r
+ {0x9Bu, 0x40u},\r
{0x9Du, 0x14u},\r
{0x9Eu, 0x08u},\r
- {0xA1u, 0x80u},\r
- {0xA3u, 0x10u},\r
- {0xA6u, 0x20u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA1u, 0x08u},\r
+ {0xA4u, 0x40u},\r
+ {0xA6u, 0x80u},\r
+ {0xA7u, 0x22u},\r
+ {0xB6u, 0x01u},\r
{0xCCu, 0xF0u},\r
+ {0xCEu, 0x10u},\r
{0xD4u, 0xE0u},\r
- {0xD8u, 0x40u},\r
- {0xE2u, 0x20u},\r
- {0xE6u, 0x90u},\r
- {0x12u, 0x20u},\r
- {0x81u, 0x40u},\r
- {0x85u, 0x04u},\r
- {0x95u, 0x4Cu},\r
+ {0xD6u, 0x80u},\r
+ {0xE2u, 0xA0u},\r
+ {0xE6u, 0x10u},\r
+ {0x12u, 0x80u},\r
+ {0x85u, 0x80u},\r
+ {0x8Cu, 0x80u},\r
+ {0x8Du, 0x04u},\r
{0x96u, 0x08u},\r
- {0x9Cu, 0x01u},\r
- {0x9Du, 0x10u},\r
- {0xA4u, 0x20u},\r
- {0xA6u, 0x60u},\r
+ {0x9Du, 0x94u},\r
+ {0x9Eu, 0x48u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA6u, 0x80u},\r
+ {0xA7u, 0x22u},\r
+ {0xACu, 0x40u},\r
+ {0xAFu, 0x04u},\r
{0xC4u, 0x10u},\r
{0xE2u, 0x10u},\r
- {0xE6u, 0x20u},\r
- {0x73u, 0x01u},\r
- {0x84u, 0x20u},\r
- {0x86u, 0x24u},\r
- {0x8Fu, 0x01u},\r
- {0x95u, 0x04u},\r
+ {0xEAu, 0x40u},\r
+ {0xEEu, 0x10u},\r
+ {0x83u, 0x10u},\r
+ {0x86u, 0x44u},\r
+ {0x8Fu, 0x40u},\r
{0x96u, 0x08u},\r
{0x9Du, 0x10u},\r
- {0xA4u, 0x20u},\r
- {0xA6u, 0x40u},\r
- {0xACu, 0x01u},\r
- {0xDCu, 0x20u},\r
- {0xE2u, 0x40u},\r
- {0xE6u, 0x50u},\r
- {0xEAu, 0x40u},\r
- {0x09u, 0x80u},\r
- {0x0Fu, 0x80u},\r
+ {0x9Eu, 0x48u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA0u, 0x80u},\r
+ {0xA7u, 0x22u},\r
+ {0xE2u, 0x30u},\r
+ {0xE6u, 0x10u},\r
+ {0x08u, 0x80u},\r
+ {0x0Bu, 0x20u},\r
+ {0x0Cu, 0x01u},\r
{0x10u, 0x10u},\r
- {0x53u, 0x80u},\r
- {0x54u, 0x04u},\r
- {0x59u, 0x20u},\r
- {0x5Fu, 0x80u},\r
- {0x84u, 0x10u},\r
- {0x8Fu, 0x40u},\r
- {0xC2u, 0x06u},\r
- {0xC4u, 0x08u},\r
+ {0x14u, 0x40u},\r
+ {0x50u, 0x10u},\r
+ {0x53u, 0x02u},\r
+ {0x54u, 0x02u},\r
+ {0x56u, 0x20u},\r
+ {0x8Bu, 0x18u},\r
+ {0x8Eu, 0x04u},\r
+ {0xC2u, 0x0Eu},\r
+ {0xC4u, 0x0Cu},\r
{0xD4u, 0x07u},\r
{0xD6u, 0x04u},\r
- {0xE6u, 0x02u},\r
- {0x00u, 0x02u},\r
- {0x03u, 0x01u},\r
- {0x04u, 0x42u},\r
- {0x0Bu, 0x22u},\r
- {0x0Eu, 0x01u},\r
- {0x0Fu, 0x20u},\r
- {0x85u, 0x20u},\r
- {0x86u, 0x01u},\r
- {0x8Cu, 0x40u},\r
- {0x9Du, 0x20u},\r
- {0x9Fu, 0x01u},\r
- {0xA4u, 0x04u},\r
- {0xAFu, 0x81u},\r
- {0xB3u, 0x80u},\r
- {0xB5u, 0x80u},\r
+ {0xE2u, 0x04u},\r
+ {0xE6u, 0x09u},\r
+ {0x01u, 0x01u},\r
+ {0x02u, 0x04u},\r
+ {0x07u, 0x48u},\r
+ {0x0Bu, 0x41u},\r
+ {0x0Cu, 0x82u},\r
+ {0x87u, 0x04u},\r
+ {0x94u, 0x20u},\r
+ {0x97u, 0x01u},\r
+ {0x9Eu, 0x04u},\r
+ {0x9Fu, 0x08u},\r
+ {0xA7u, 0x02u},\r
+ {0xA8u, 0x02u},\r
+ {0xABu, 0x01u},\r
+ {0xACu, 0x80u},\r
+ {0xAEu, 0x20u},\r
+ {0xB0u, 0x51u},\r
{0xC0u, 0x0Fu},\r
{0xC2u, 0x0Fu},\r
- {0xE2u, 0x02u},\r
- {0xEAu, 0x08u},\r
- {0xECu, 0x04u},\r
- {0x8Fu, 0x10u},\r
- {0x90u, 0x02u},\r
- {0xA3u, 0x10u},\r
- {0xA4u, 0x04u},\r
- {0xABu, 0x01u},\r
- {0xB0u, 0x01u},\r
- {0xB3u, 0x10u},\r
- {0xE2u, 0x08u},\r
{0xEAu, 0x05u},\r
- {0x09u, 0x02u},\r
+ {0xEEu, 0x04u},\r
+ {0x84u, 0x04u},\r
+ {0x87u, 0x40u},\r
+ {0x8Cu, 0x10u},\r
+ {0x91u, 0x01u},\r
+ {0x93u, 0x40u},\r
+ {0x94u, 0x20u},\r
+ {0x97u, 0x08u},\r
+ {0x9Bu, 0x40u},\r
+ {0xA7u, 0x02u},\r
+ {0xACu, 0x80u},\r
+ {0xB4u, 0x02u},\r
+ {0xE4u, 0x02u},\r
+ {0xEEu, 0x02u},\r
+ {0x08u, 0x04u},\r
{0x0Bu, 0x08u},\r
- {0x0Eu, 0x04u},\r
- {0x0Fu, 0x40u},\r
- {0x80u, 0x01u},\r
- {0x85u, 0x02u},\r
- {0x87u, 0x04u},\r
- {0x90u, 0x02u},\r
- {0x96u, 0x04u},\r
- {0xA4u, 0x04u},\r
- {0xAEu, 0x04u},\r
+ {0x0Eu, 0x21u},\r
+ {0x86u, 0x11u},\r
+ {0x97u, 0x08u},\r
+ {0x9Cu, 0x04u},\r
+ {0xA7u, 0x02u},\r
+ {0xB1u, 0x01u},\r
+ {0xB7u, 0x40u},\r
{0xC2u, 0x0Fu},\r
- {0x95u, 0x04u},\r
- {0x9Du, 0x10u},\r
- {0xA2u, 0x20u},\r
- {0xAEu, 0x40u},\r
- {0xEEu, 0x40u},\r
+ {0xEAu, 0x08u},\r
+ {0xEEu, 0x01u},\r
+ {0x67u, 0x80u},\r
+ {0x87u, 0x40u},\r
+ {0x9Eu, 0x08u},\r
+ {0xA0u, 0x80u},\r
+ {0xA3u, 0x40u},\r
+ {0xA7u, 0x22u},\r
+ {0xB5u, 0x10u},\r
+ {0xD8u, 0x80u},\r
+ {0xE2u, 0x10u},\r
{0x07u, 0x40u},\r
- {0x52u, 0x20u},\r
- {0x57u, 0x80u},\r
- {0x85u, 0x04u},\r
- {0x8Fu, 0x80u},\r
- {0x95u, 0x04u},\r
- {0x9Fu, 0x40u},\r
- {0xA2u, 0x20u},\r
- {0xA9u, 0x10u},\r
- {0xABu, 0x40u},\r
+ {0x50u, 0x80u},\r
+ {0x57u, 0x40u},\r
+ {0x83u, 0x40u},\r
+ {0x87u, 0x02u},\r
+ {0x8Au, 0x08u},\r
+ {0x9Eu, 0x08u},\r
+ {0xA0u, 0x80u},\r
+ {0xA3u, 0x40u},\r
+ {0xA7u, 0x02u},\r
+ {0xABu, 0x20u},\r
{0xC0u, 0x20u},\r
{0xD4u, 0x60u},\r
- {0xE6u, 0x40u},\r
- {0xECu, 0x80u},\r
+ {0xE2u, 0x10u},\r
+ {0xE4u, 0x80u},\r
{0xEEu, 0x20u},\r
- {0x88u, 0x04u},\r
- {0xA4u, 0x04u},\r
- {0xAFu, 0x40u},\r
- {0xE0u, 0x04u},\r
- {0x10u, 0x03u},\r
- {0x1Au, 0x03u},\r
+ {0xAFu, 0x02u},\r
+ {0x01u, 0x02u},\r
+ {0x89u, 0x02u},\r
+ {0xC0u, 0x08u},\r
+ {0xE2u, 0x01u},\r
+ {0x10u, 0x01u},\r
+ {0x11u, 0x01u},\r
+ {0x1Au, 0x01u},\r
+ {0x1Bu, 0x01u},\r
{0x00u, 0xFDu},\r
- {0x01u, 0xABu},\r
- {0x02u, 0x02u},\r
+ {0x01u, 0xAFu},\r
+ {0x02u, 0x0Au},\r
{0x10u, 0x55u},\r
};\r
\r
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
{(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 512u},\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P3_U1_BASE), 1408u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
{(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},\r
};\r
\r
- /* UDB_1_1_1_CONFIG Address: CYDEV_UCFG_B1_P3_U0_BASE Size (bytes): 128 */\r
- static const uint8 CYCODE BS_UDB_1_1_1_CONFIG_VAL[] = {\r
- 0x01u, 0x00u, 0x00u, 0x75u, 0x04u, 0x00u, 0x00u, 0x08u, 0x08u, 0x88u, 0x61u, 0x64u, 0x01u, 0x64u, 0x00u, 0x88u, \r
- 0x10u, 0x24u, 0x00u, 0x00u, 0x00u, 0x03u, 0x00u, 0x70u, 0x00u, 0x07u, 0x40u, 0x10u, 0x01u, 0xECu, 0x00u, 0x00u, \r
- 0xA2u, 0xECu, 0x08u, 0x00u, 0x01u, 0xACu, 0x00u, 0x40u, 0x07u, 0x00u, 0xD8u, 0x00u, 0x01u, 0x40u, 0x00u, 0x02u, \r
- 0x00u, 0x80u, 0x3Fu, 0x71u, 0xE0u, 0x08u, 0x00u, 0x07u, 0x08u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x00u, 0x04u, 0x11u, \r
- 0x34u, 0x02u, 0x50u, 0x00u, 0x06u, 0xDEu, 0xFCu, 0xBDu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, \r
- 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
-\r
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x00u, 0x02u, 0x01u};\r
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P3_U0_BASE), BS_UDB_1_1_1_CONFIG_VAL, 128u},\r
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},\r
};\r
\r
/* SCSI_TX_DMA_COMPLETE */\r
.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x04\r
-.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 2\r
+.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x08\r
+.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 3\r
.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* SD_RX_DMA_COMPLETE */\r
.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x08\r
-.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 3\r
+.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x10\r
+.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 4\r
.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* SD_TX_DMA_COMPLETE */\r
.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x10\r
-.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 4\r
+.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x20\r
+.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 5\r
.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5\r
.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* SCSI_Parity_Error */\r
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB10_11_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB10_MSK\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB10_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB07_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB07_ST\r
\r
/* USBFS_bus_reset */\r
.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
/* SCSI_CTL_PHASE */\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+\r
+/* SCSI_Filtered */\r
+.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01\r
+.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST\r
+.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
+.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
+.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
+.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
+.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
+.set SCSI_Filtered_sts_sts_reg__3__POS, 3\r
+.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
+.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
+.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB00_MSK\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB00_ST\r
\r
/* SCSI_Out_Bits */\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
\r
/* USBFS_arb_int */\r
.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
/* SCSI_Out_Ctl */\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
\r
/* SCSI_Out_DBx */\r
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
/* SCSI_RST_ISR */\r
.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_RST_ISR__INTC_MASK, 0x400\r
-.set SCSI_RST_ISR__INTC_NUMBER, 10\r
+.set SCSI_RST_ISR__INTC_MASK, 0x04\r
+.set SCSI_RST_ISR__INTC_NUMBER, 2\r
.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7\r
-.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_10\r
+.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB05_ST\r
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB06_07_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB06_07_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB06_07_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB06_07_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB06_07_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB06_07_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB06_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB06_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB06_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB06_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB06_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB06_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB06_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB06_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB06_F1\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB06_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB06_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB05_06_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB05_06_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB05_06_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB05_06_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB05_06_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB05_06_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB05_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB05_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB05_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB05_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB05_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB05_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB05_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB05_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB05_F1\r
\r
/* USBFS_dp_int */\r
.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
.set timer_clock__PM_STBY_MSK, 0x04\r
\r
+/* SCSI_Noise */\r
+.set SCSI_Noise__0__AG, CYREG_PRT12_AG\r
+.set SCSI_Noise__0__BIE, CYREG_PRT12_BIE\r
+.set SCSI_Noise__0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_Noise__0__BYP, CYREG_PRT12_BYP\r
+.set SCSI_Noise__0__DM0, CYREG_PRT12_DM0\r
+.set SCSI_Noise__0__DM1, CYREG_PRT12_DM1\r
+.set SCSI_Noise__0__DM2, CYREG_PRT12_DM2\r
+.set SCSI_Noise__0__DR, CYREG_PRT12_DR\r
+.set SCSI_Noise__0__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_Noise__0__MASK, 0x20\r
+.set SCSI_Noise__0__PC, CYREG_PRT12_PC5\r
+.set SCSI_Noise__0__PORT, 12\r
+.set SCSI_Noise__0__PRT, CYREG_PRT12_PRT\r
+.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_Noise__0__PS, CYREG_PRT12_PS\r
+.set SCSI_Noise__0__SHIFT, 5\r
+.set SCSI_Noise__0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_Noise__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_Noise__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_Noise__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_Noise__0__SLW, CYREG_PRT12_SLW\r
+.set SCSI_Noise__1__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__1__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__1__MASK, 0x10\r
+.set SCSI_Noise__1__PC, CYREG_PRT6_PC4\r
+.set SCSI_Noise__1__PORT, 6\r
+.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__1__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__1__SHIFT, 4\r
+.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__2__AG, CYREG_PRT5_AG\r
+.set SCSI_Noise__2__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_Noise__2__BIE, CYREG_PRT5_BIE\r
+.set SCSI_Noise__2__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_Noise__2__BYP, CYREG_PRT5_BYP\r
+.set SCSI_Noise__2__CTL, CYREG_PRT5_CTL\r
+.set SCSI_Noise__2__DM0, CYREG_PRT5_DM0\r
+.set SCSI_Noise__2__DM1, CYREG_PRT5_DM1\r
+.set SCSI_Noise__2__DM2, CYREG_PRT5_DM2\r
+.set SCSI_Noise__2__DR, CYREG_PRT5_DR\r
+.set SCSI_Noise__2__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_Noise__2__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_Noise__2__MASK, 0x01\r
+.set SCSI_Noise__2__PC, CYREG_PRT5_PC0\r
+.set SCSI_Noise__2__PORT, 5\r
+.set SCSI_Noise__2__PRT, CYREG_PRT5_PRT\r
+.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_Noise__2__PS, CYREG_PRT5_PS\r
+.set SCSI_Noise__2__SHIFT, 0\r
+.set SCSI_Noise__2__SLW, CYREG_PRT5_SLW\r
+.set SCSI_Noise__3__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__3__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__3__MASK, 0x40\r
+.set SCSI_Noise__3__PC, CYREG_PRT6_PC6\r
+.set SCSI_Noise__3__PORT, 6\r
+.set SCSI_Noise__3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__3__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__3__SHIFT, 6\r
+.set SCSI_Noise__3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__4__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__4__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__4__MASK, 0x20\r
+.set SCSI_Noise__4__PC, CYREG_PRT6_PC5\r
+.set SCSI_Noise__4__PORT, 6\r
+.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__4__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__4__SHIFT, 5\r
+.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__ACK__MASK, 0x20\r
+.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC5\r
+.set SCSI_Noise__ACK__PORT, 6\r
+.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__ACK__SHIFT, 5\r
+.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__ATN__AG, CYREG_PRT12_AG\r
+.set SCSI_Noise__ATN__BIE, CYREG_PRT12_BIE\r
+.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_Noise__ATN__BYP, CYREG_PRT12_BYP\r
+.set SCSI_Noise__ATN__DM0, CYREG_PRT12_DM0\r
+.set SCSI_Noise__ATN__DM1, CYREG_PRT12_DM1\r
+.set SCSI_Noise__ATN__DM2, CYREG_PRT12_DM2\r
+.set SCSI_Noise__ATN__DR, CYREG_PRT12_DR\r
+.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_Noise__ATN__MASK, 0x20\r
+.set SCSI_Noise__ATN__PC, CYREG_PRT12_PC5\r
+.set SCSI_Noise__ATN__PORT, 12\r
+.set SCSI_Noise__ATN__PRT, CYREG_PRT12_PRT\r
+.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_Noise__ATN__PS, CYREG_PRT12_PS\r
+.set SCSI_Noise__ATN__SHIFT, 5\r
+.set SCSI_Noise__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_Noise__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_Noise__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_Noise__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_Noise__ATN__SLW, CYREG_PRT12_SLW\r
+.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__BSY__MASK, 0x10\r
+.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC4\r
+.set SCSI_Noise__BSY__PORT, 6\r
+.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__BSY__SHIFT, 4\r
+.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__RST__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__RST__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__RST__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__RST__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__RST__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__RST__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__RST__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__RST__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__RST__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__RST__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__RST__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__RST__MASK, 0x40\r
+.set SCSI_Noise__RST__PC, CYREG_PRT6_PC6\r
+.set SCSI_Noise__RST__PORT, 6\r
+.set SCSI_Noise__RST__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__RST__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__RST__SHIFT, 6\r
+.set SCSI_Noise__RST__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__SEL__AG, CYREG_PRT5_AG\r
+.set SCSI_Noise__SEL__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_Noise__SEL__BIE, CYREG_PRT5_BIE\r
+.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_Noise__SEL__BYP, CYREG_PRT5_BYP\r
+.set SCSI_Noise__SEL__CTL, CYREG_PRT5_CTL\r
+.set SCSI_Noise__SEL__DM0, CYREG_PRT5_DM0\r
+.set SCSI_Noise__SEL__DM1, CYREG_PRT5_DM1\r
+.set SCSI_Noise__SEL__DM2, CYREG_PRT5_DM2\r
+.set SCSI_Noise__SEL__DR, CYREG_PRT5_DR\r
+.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_Noise__SEL__MASK, 0x01\r
+.set SCSI_Noise__SEL__PC, CYREG_PRT5_PC0\r
+.set SCSI_Noise__SEL__PORT, 5\r
+.set SCSI_Noise__SEL__PRT, CYREG_PRT5_PRT\r
+.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_Noise__SEL__PS, CYREG_PRT5_PS\r
+.set SCSI_Noise__SEL__SHIFT, 0\r
+.set SCSI_Noise__SEL__SLW, CYREG_PRT5_SLW\r
+\r
/* scsiTarget */\r
.set scsiTarget_StatusReg__0__MASK, 0x01\r
.set scsiTarget_StatusReg__0__POS, 0\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__4__MASK, 0x10\r
.set scsiTarget_StatusReg__4__POS, 4\r
.set scsiTarget_StatusReg__MASK, 0x1F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK\r
-.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
-.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
-.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL\r
-.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB04_MSK\r
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB04_ST\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB04_CTL\r
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB04_CTL\r
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB04_MSK\r
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB04_05_A0\r
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB04_05_A1\r
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB04_05_D0\r
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB04_05_D1\r
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB04_05_F0\r
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB04_05_F1\r
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB04_A0_A1\r
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB04_A0\r
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB04_A1\r
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB04_D0_D1\r
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB04_D0\r
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB04_D1\r
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB04_F0_F1\r
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB04_F0\r
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB04_F1\r
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK\r
+.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST\r
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB12_MSK\r
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB12_ST\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB12_CTL\r
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB12_CTL\r
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB12_MSK\r
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB12_13_A0\r
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB12_13_A1\r
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB12_13_D0\r
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB12_13_D1\r
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB12_13_F0\r
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB12_13_F1\r
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB12_A0_A1\r
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB12_A0\r
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB12_A1\r
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB12_D0_D1\r
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB12_D0\r
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB12_D1\r
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB12_F0_F1\r
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB12_F0\r
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB12_F1\r
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
/* USBFS_ep_1 */\r
.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_1__INTC_MASK, 0x20\r
-.set USBFS_ep_1__INTC_NUMBER, 5\r
+.set USBFS_ep_1__INTC_MASK, 0x40\r
+.set USBFS_ep_1__INTC_NUMBER, 6\r
.set USBFS_ep_1__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_5\r
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_6\r
.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_2 */\r
.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_2__INTC_MASK, 0x40\r
-.set USBFS_ep_2__INTC_NUMBER, 6\r
+.set USBFS_ep_2__INTC_MASK, 0x80\r
+.set USBFS_ep_2__INTC_NUMBER, 7\r
.set USBFS_ep_2__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_6\r
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_7\r
.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_3 */\r
.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_3__INTC_MASK, 0x80\r
-.set USBFS_ep_3__INTC_NUMBER, 7\r
+.set USBFS_ep_3__INTC_MASK, 0x100\r
+.set USBFS_ep_3__INTC_NUMBER, 8\r
.set USBFS_ep_3__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_7\r
+.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_8\r
.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_4 */\r
.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_4__INTC_MASK, 0x100\r
-.set USBFS_ep_4__INTC_NUMBER, 8\r
+.set USBFS_ep_4__INTC_MASK, 0x200\r
+.set USBFS_ep_4__INTC_NUMBER, 9\r
.set USBFS_ep_4__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_8\r
+.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_9\r
.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1\r
.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN\r
\r
-/* SCSI_ATN */\r
-.set SCSI_ATN__0__MASK, 0x20\r
-.set SCSI_ATN__0__PC, CYREG_PRT12_PC5\r
-.set SCSI_ATN__0__PORT, 12\r
-.set SCSI_ATN__0__SHIFT, 5\r
-.set SCSI_ATN__AG, CYREG_PRT12_AG\r
-.set SCSI_ATN__BIE, CYREG_PRT12_BIE\r
-.set SCSI_ATN__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set SCSI_ATN__BYP, CYREG_PRT12_BYP\r
-.set SCSI_ATN__DM0, CYREG_PRT12_DM0\r
-.set SCSI_ATN__DM1, CYREG_PRT12_DM1\r
-.set SCSI_ATN__DM2, CYREG_PRT12_DM2\r
-.set SCSI_ATN__DR, CYREG_PRT12_DR\r
-.set SCSI_ATN__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_ATN__INT__MASK, 0x20\r
-.set SCSI_ATN__INT__PC, CYREG_PRT12_PC5\r
-.set SCSI_ATN__INT__PORT, 12\r
-.set SCSI_ATN__INT__SHIFT, 5\r
-.set SCSI_ATN__MASK, 0x20\r
-.set SCSI_ATN__PORT, 12\r
-.set SCSI_ATN__PRT, CYREG_PRT12_PRT\r
-.set SCSI_ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set SCSI_ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set SCSI_ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set SCSI_ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set SCSI_ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set SCSI_ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set SCSI_ATN__PS, CYREG_PRT12_PS\r
-.set SCSI_ATN__SHIFT, 5\r
-.set SCSI_ATN__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set SCSI_ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set SCSI_ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set SCSI_ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set SCSI_ATN__SLW, CYREG_PRT12_SLW\r
-\r
/* SCSI_CLK */\r
.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0\r
.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1\r
.set SCSI_Out__SEL__SHIFT, 3\r
.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW\r
\r
-/* SCSI_RST */\r
-.set SCSI_RST__0__MASK, 0x40\r
-.set SCSI_RST__0__PC, CYREG_PRT6_PC6\r
-.set SCSI_RST__0__PORT, 6\r
-.set SCSI_RST__0__SHIFT, 6\r
-.set SCSI_RST__AG, CYREG_PRT6_AG\r
-.set SCSI_RST__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_RST__BIE, CYREG_PRT6_BIE\r
-.set SCSI_RST__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_RST__BYP, CYREG_PRT6_BYP\r
-.set SCSI_RST__CTL, CYREG_PRT6_CTL\r
-.set SCSI_RST__DM0, CYREG_PRT6_DM0\r
-.set SCSI_RST__DM1, CYREG_PRT6_DM1\r
-.set SCSI_RST__DM2, CYREG_PRT6_DM2\r
-.set SCSI_RST__DR, CYREG_PRT6_DR\r
-.set SCSI_RST__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_RST__INTSTAT, CYREG_PICU6_INTSTAT\r
-.set SCSI_RST__INT__MASK, 0x40\r
-.set SCSI_RST__INT__PC, CYREG_PRT6_PC6\r
-.set SCSI_RST__INT__PORT, 6\r
-.set SCSI_RST__INT__SHIFT, 6\r
-.set SCSI_RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_RST__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_RST__MASK, 0x40\r
-.set SCSI_RST__PORT, 6\r
-.set SCSI_RST__PRT, CYREG_PRT6_PRT\r
-.set SCSI_RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_RST__PS, CYREG_PRT6_PS\r
-.set SCSI_RST__SHIFT, 6\r
-.set SCSI_RST__SLW, CYREG_PRT6_SLW\r
-.set SCSI_RST__SNAP, CYREG_PICU6_SNAP\r
-\r
/* USBFS_Dm */\r
.set USBFS_Dm__0__MASK, 0x80\r
.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1\r
.set SCSI_In__1__INP_DIS, CYREG_PRT6_INP_DIS\r
.set SCSI_In__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
.set SCSI_In__1__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In__1__MASK, 0x10\r
-.set SCSI_In__1__PC, CYREG_PRT6_PC4\r
+.set SCSI_In__1__MASK, 0x80\r
+.set SCSI_In__1__PC, CYREG_PRT6_PC7\r
.set SCSI_In__1__PORT, 6\r
.set SCSI_In__1__PRT, CYREG_PRT6_PRT\r
.set SCSI_In__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
.set SCSI_In__1__PS, CYREG_PRT6_PS\r
-.set SCSI_In__1__SHIFT, 4\r
+.set SCSI_In__1__SHIFT, 7\r
.set SCSI_In__1__SLW, CYREG_PRT6_SLW\r
-.set SCSI_In__2__AG, CYREG_PRT6_AG\r
-.set SCSI_In__2__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_In__2__BIE, CYREG_PRT6_BIE\r
-.set SCSI_In__2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_In__2__BYP, CYREG_PRT6_BYP\r
-.set SCSI_In__2__CTL, CYREG_PRT6_CTL\r
-.set SCSI_In__2__DM0, CYREG_PRT6_DM0\r
-.set SCSI_In__2__DM1, CYREG_PRT6_DM1\r
-.set SCSI_In__2__DM2, CYREG_PRT6_DM2\r
-.set SCSI_In__2__DR, CYREG_PRT6_DR\r
-.set SCSI_In__2__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_In__2__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In__2__MASK, 0x20\r
-.set SCSI_In__2__PC, CYREG_PRT6_PC5\r
-.set SCSI_In__2__PORT, 6\r
-.set SCSI_In__2__PRT, CYREG_PRT6_PRT\r
-.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_In__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_In__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_In__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_In__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_In__2__PS, CYREG_PRT6_PS\r
-.set SCSI_In__2__SHIFT, 5\r
-.set SCSI_In__2__SLW, CYREG_PRT6_SLW\r
-.set SCSI_In__3__AG, CYREG_PRT6_AG\r
-.set SCSI_In__3__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_In__3__BIE, CYREG_PRT6_BIE\r
-.set SCSI_In__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_In__3__BYP, CYREG_PRT6_BYP\r
-.set SCSI_In__3__CTL, CYREG_PRT6_CTL\r
-.set SCSI_In__3__DM0, CYREG_PRT6_DM0\r
-.set SCSI_In__3__DM1, CYREG_PRT6_DM1\r
-.set SCSI_In__3__DM2, CYREG_PRT6_DM2\r
-.set SCSI_In__3__DR, CYREG_PRT6_DR\r
-.set SCSI_In__3__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_In__3__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In__3__MASK, 0x80\r
-.set SCSI_In__3__PC, CYREG_PRT6_PC7\r
-.set SCSI_In__3__PORT, 6\r
-.set SCSI_In__3__PRT, CYREG_PRT6_PRT\r
-.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_In__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_In__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_In__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_In__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_In__3__PS, CYREG_PRT6_PS\r
-.set SCSI_In__3__SHIFT, 7\r
-.set SCSI_In__3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In__2__AG, CYREG_PRT5_AG\r
+.set SCSI_In__2__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__2__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__2__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__2__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__2__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__2__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__2__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__2__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__2__DR, CYREG_PRT5_DR\r
+.set SCSI_In__2__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__2__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__2__MASK, 0x02\r
+.set SCSI_In__2__PC, CYREG_PRT5_PC1\r
+.set SCSI_In__2__PORT, 5\r
+.set SCSI_In__2__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__2__PS, CYREG_PRT5_PS\r
+.set SCSI_In__2__SHIFT, 1\r
+.set SCSI_In__2__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__3__AG, CYREG_PRT5_AG\r
+.set SCSI_In__3__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__3__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__3__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__3__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__3__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__3__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__3__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__3__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__3__DR, CYREG_PRT5_DR\r
+.set SCSI_In__3__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__3__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__3__MASK, 0x04\r
+.set SCSI_In__3__PC, CYREG_PRT5_PC2\r
+.set SCSI_In__3__PORT, 5\r
+.set SCSI_In__3__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__3__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__3__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__3__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__3__PS, CYREG_PRT5_PS\r
+.set SCSI_In__3__SHIFT, 2\r
+.set SCSI_In__3__SLW, CYREG_PRT5_SLW\r
.set SCSI_In__4__AG, CYREG_PRT5_AG\r
.set SCSI_In__4__AMUX, CYREG_PRT5_AMUX\r
.set SCSI_In__4__BIE, CYREG_PRT5_BIE\r
.set SCSI_In__4__INP_DIS, CYREG_PRT5_INP_DIS\r
.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
.set SCSI_In__4__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__4__MASK, 0x01\r
-.set SCSI_In__4__PC, CYREG_PRT5_PC0\r
+.set SCSI_In__4__MASK, 0x08\r
+.set SCSI_In__4__PC, CYREG_PRT5_PC3\r
.set SCSI_In__4__PORT, 5\r
.set SCSI_In__4__PRT, CYREG_PRT5_PRT\r
.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
.set SCSI_In__4__PS, CYREG_PRT5_PS\r
-.set SCSI_In__4__SHIFT, 0\r
+.set SCSI_In__4__SHIFT, 3\r
.set SCSI_In__4__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__5__AG, CYREG_PRT5_AG\r
-.set SCSI_In__5__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__5__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__5__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__5__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__5__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__5__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__5__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__5__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__5__DR, CYREG_PRT5_DR\r
-.set SCSI_In__5__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__5__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__5__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__5__MASK, 0x02\r
-.set SCSI_In__5__PC, CYREG_PRT5_PC1\r
-.set SCSI_In__5__PORT, 5\r
-.set SCSI_In__5__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__5__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__5__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__5__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__5__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__5__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__5__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__5__PS, CYREG_PRT5_PS\r
-.set SCSI_In__5__SHIFT, 1\r
-.set SCSI_In__5__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__6__AG, CYREG_PRT5_AG\r
-.set SCSI_In__6__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__6__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__6__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__6__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__6__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__6__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__6__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__6__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__6__DR, CYREG_PRT5_DR\r
-.set SCSI_In__6__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__6__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__6__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__6__MASK, 0x04\r
-.set SCSI_In__6__PC, CYREG_PRT5_PC2\r
-.set SCSI_In__6__PORT, 5\r
-.set SCSI_In__6__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__6__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__6__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__6__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__6__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__6__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__6__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__6__PS, CYREG_PRT5_PS\r
-.set SCSI_In__6__SHIFT, 2\r
-.set SCSI_In__6__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__7__AG, CYREG_PRT5_AG\r
-.set SCSI_In__7__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__7__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__7__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__7__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__7__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__7__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__7__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__7__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__7__DR, CYREG_PRT5_DR\r
-.set SCSI_In__7__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__7__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__7__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__7__MASK, 0x08\r
-.set SCSI_In__7__PC, CYREG_PRT5_PC3\r
-.set SCSI_In__7__PORT, 5\r
-.set SCSI_In__7__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__7__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__7__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__7__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__7__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__7__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__7__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__7__PS, CYREG_PRT5_PS\r
-.set SCSI_In__7__SHIFT, 3\r
-.set SCSI_In__7__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__ACK__AG, CYREG_PRT6_AG\r
-.set SCSI_In__ACK__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_In__ACK__BIE, CYREG_PRT6_BIE\r
-.set SCSI_In__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_In__ACK__BYP, CYREG_PRT6_BYP\r
-.set SCSI_In__ACK__CTL, CYREG_PRT6_CTL\r
-.set SCSI_In__ACK__DM0, CYREG_PRT6_DM0\r
-.set SCSI_In__ACK__DM1, CYREG_PRT6_DM1\r
-.set SCSI_In__ACK__DM2, CYREG_PRT6_DM2\r
-.set SCSI_In__ACK__DR, CYREG_PRT6_DR\r
-.set SCSI_In__ACK__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_In__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_In__ACK__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In__ACK__MASK, 0x20\r
-.set SCSI_In__ACK__PC, CYREG_PRT6_PC5\r
-.set SCSI_In__ACK__PORT, 6\r
-.set SCSI_In__ACK__PRT, CYREG_PRT6_PRT\r
-.set SCSI_In__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_In__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_In__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_In__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_In__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_In__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_In__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_In__ACK__PS, CYREG_PRT6_PS\r
-.set SCSI_In__ACK__SHIFT, 5\r
-.set SCSI_In__ACK__SLW, CYREG_PRT6_SLW\r
-.set SCSI_In__BSY__AG, CYREG_PRT6_AG\r
-.set SCSI_In__BSY__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_In__BSY__BIE, CYREG_PRT6_BIE\r
-.set SCSI_In__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_In__BSY__BYP, CYREG_PRT6_BYP\r
-.set SCSI_In__BSY__CTL, CYREG_PRT6_CTL\r
-.set SCSI_In__BSY__DM0, CYREG_PRT6_DM0\r
-.set SCSI_In__BSY__DM1, CYREG_PRT6_DM1\r
-.set SCSI_In__BSY__DM2, CYREG_PRT6_DM2\r
-.set SCSI_In__BSY__DR, CYREG_PRT6_DR\r
-.set SCSI_In__BSY__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_In__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_In__BSY__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In__BSY__MASK, 0x10\r
-.set SCSI_In__BSY__PC, CYREG_PRT6_PC4\r
-.set SCSI_In__BSY__PORT, 6\r
-.set SCSI_In__BSY__PRT, CYREG_PRT6_PRT\r
-.set SCSI_In__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_In__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_In__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_In__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_In__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_In__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_In__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_In__BSY__PS, CYREG_PRT6_PS\r
-.set SCSI_In__BSY__SHIFT, 4\r
-.set SCSI_In__BSY__SLW, CYREG_PRT6_SLW\r
.set SCSI_In__CD__AG, CYREG_PRT5_AG\r
.set SCSI_In__CD__AMUX, CYREG_PRT5_AMUX\r
.set SCSI_In__CD__BIE, CYREG_PRT5_BIE\r
.set SCSI_In__REQ__PS, CYREG_PRT5_PS\r
.set SCSI_In__REQ__SHIFT, 2\r
.set SCSI_In__REQ__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__SEL__AG, CYREG_PRT5_AG\r
-.set SCSI_In__SEL__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__SEL__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__SEL__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__SEL__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__SEL__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__SEL__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__SEL__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__SEL__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__SEL__DR, CYREG_PRT5_DR\r
-.set SCSI_In__SEL__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__SEL__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__SEL__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__SEL__MASK, 0x01\r
-.set SCSI_In__SEL__PC, CYREG_PRT5_PC0\r
-.set SCSI_In__SEL__PORT, 5\r
-.set SCSI_In__SEL__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__SEL__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__SEL__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__SEL__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__SEL__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__SEL__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__SEL__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__SEL__PS, CYREG_PRT5_PS\r
-.set SCSI_In__SEL__SHIFT, 0\r
-.set SCSI_In__SEL__SLW, CYREG_PRT5_SLW\r
\r
/* SD_DAT1 */\r
.set SD_DAT1__0__MASK, 0x01\r
.set CYDEV_ECC_ENABLE, 0\r
.set CYDEV_HEAP_SIZE, 0x0400\r
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1\r
-.set CYDEV_INTR_RISING, 0x0000001E\r
+.set CYDEV_INTR_RISING, 0x0000003E\r
.set CYDEV_PROJ_TYPE, 2\r
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1\r
.set CYDEV_PROJ_TYPE_LOADABLE, 2\r
/* SCSI_TX_DMA_COMPLETE */\r
SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x04\r
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 2\r
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08\r
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3\r
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* SD_RX_DMA_COMPLETE */\r
SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x08\r
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 3\r
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* SD_TX_DMA_COMPLETE */\r
SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* SCSI_Parity_Error */\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
\r
/* USBFS_bus_reset */\r
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
/* SCSI_CTL_PHASE */\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+\r
+/* SCSI_Filtered */\r
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST\r
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB00_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB00_ST\r
\r
/* SCSI_Out_Bits */\r
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
\r
/* USBFS_arb_int */\r
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
/* SCSI_Out_Ctl */\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
\r
/* SCSI_Out_DBx */\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
/* SCSI_RST_ISR */\r
SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RST_ISR__INTC_MASK EQU 0x400\r
-SCSI_RST_ISR__INTC_NUMBER EQU 10\r
+SCSI_RST_ISR__INTC_MASK EQU 0x04\r
+SCSI_RST_ISR__INTC_NUMBER EQU 2\r
SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10\r
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB05_06_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB05_06_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB05_06_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB05_06_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB05_06_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB05_06_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB05_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB05_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB05_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB05_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB05_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB05_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB05_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB05_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB05_F1\r
\r
/* USBFS_dp_int */\r
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
timer_clock__PM_STBY_MSK EQU 0x04\r
\r
+/* SCSI_Noise */\r
+SCSI_Noise__0__AG EQU CYREG_PRT12_AG\r
+SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_Noise__0__DR EQU CYREG_PRT12_DR\r
+SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_Noise__0__MASK EQU 0x20\r
+SCSI_Noise__0__PC EQU CYREG_PRT12_PC5\r
+SCSI_Noise__0__PORT EQU 12\r
+SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_Noise__0__PS EQU CYREG_PRT12_PS\r
+SCSI_Noise__0__SHIFT EQU 5\r
+SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_Noise__1__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__1__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__1__MASK EQU 0x10\r
+SCSI_Noise__1__PC EQU CYREG_PRT6_PC4\r
+SCSI_Noise__1__PORT EQU 6\r
+SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__1__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__1__SHIFT EQU 4\r
+SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__2__AG EQU CYREG_PRT5_AG\r
+SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Noise__2__DR EQU CYREG_PRT5_DR\r
+SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Noise__2__MASK EQU 0x01\r
+SCSI_Noise__2__PC EQU CYREG_PRT5_PC0\r
+SCSI_Noise__2__PORT EQU 5\r
+SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Noise__2__PS EQU CYREG_PRT5_PS\r
+SCSI_Noise__2__SHIFT EQU 0\r
+SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW\r
+SCSI_Noise__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__3__MASK EQU 0x40\r
+SCSI_Noise__3__PC EQU CYREG_PRT6_PC6\r
+SCSI_Noise__3__PORT EQU 6\r
+SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__3__SHIFT EQU 6\r
+SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__4__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__4__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__4__MASK EQU 0x20\r
+SCSI_Noise__4__PC EQU CYREG_PRT6_PC5\r
+SCSI_Noise__4__PORT EQU 6\r
+SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__4__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__4__SHIFT EQU 5\r
+SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__ACK__MASK EQU 0x20\r
+SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5\r
+SCSI_Noise__ACK__PORT EQU 6\r
+SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__ACK__SHIFT EQU 5\r
+SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG\r
+SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE\r
+SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP\r
+SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR\r
+SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_Noise__ATN__MASK EQU 0x20\r
+SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5\r
+SCSI_Noise__ATN__PORT EQU 12\r
+SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT\r
+SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS\r
+SCSI_Noise__ATN__SHIFT EQU 5\r
+SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW\r
+SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__BSY__MASK EQU 0x10\r
+SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4\r
+SCSI_Noise__BSY__PORT EQU 6\r
+SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__BSY__SHIFT EQU 4\r
+SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__RST__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__RST__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__RST__MASK EQU 0x40\r
+SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6\r
+SCSI_Noise__RST__PORT EQU 6\r
+SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__RST__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__RST__SHIFT EQU 6\r
+SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG\r
+SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR\r
+SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Noise__SEL__MASK EQU 0x01\r
+SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0\r
+SCSI_Noise__SEL__PORT EQU 5\r
+SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS\r
+SCSI_Noise__SEL__SHIFT EQU 0\r
+SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW\r
+\r
/* scsiTarget */\r
scsiTarget_StatusReg__0__MASK EQU 0x01\r
scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL\r
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB04_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB04_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB04_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB04_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB04_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB04_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB04_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB04_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK\r
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB12_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB12_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB12_13_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB12_13_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB12_13_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB12_13_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB12_13_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB12_13_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB12_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB12_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB12_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB12_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB12_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB12_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB12_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB12_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB12_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
/* USBFS_ep_1 */\r
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x20\r
-USBFS_ep_1__INTC_NUMBER EQU 5\r
+USBFS_ep_1__INTC_MASK EQU 0x40\r
+USBFS_ep_1__INTC_NUMBER EQU 6\r
USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_2 */\r
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x40\r
-USBFS_ep_2__INTC_NUMBER EQU 6\r
+USBFS_ep_2__INTC_MASK EQU 0x80\r
+USBFS_ep_2__INTC_NUMBER EQU 7\r
USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_3 */\r
USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_3__INTC_MASK EQU 0x80\r
-USBFS_ep_3__INTC_NUMBER EQU 7\r
+USBFS_ep_3__INTC_MASK EQU 0x100\r
+USBFS_ep_3__INTC_NUMBER EQU 8\r
USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_4 */\r
USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_4__INTC_MASK EQU 0x100\r
-USBFS_ep_4__INTC_NUMBER EQU 8\r
+USBFS_ep_4__INTC_MASK EQU 0x200\r
+USBFS_ep_4__INTC_NUMBER EQU 9\r
USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
\r
-/* SCSI_ATN */\r
-SCSI_ATN__0__MASK EQU 0x20\r
-SCSI_ATN__0__PC EQU CYREG_PRT12_PC5\r
-SCSI_ATN__0__PORT EQU 12\r
-SCSI_ATN__0__SHIFT EQU 5\r
-SCSI_ATN__AG EQU CYREG_PRT12_AG\r
-SCSI_ATN__BIE EQU CYREG_PRT12_BIE\r
-SCSI_ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_ATN__BYP EQU CYREG_PRT12_BYP\r
-SCSI_ATN__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_ATN__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_ATN__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_ATN__DR EQU CYREG_PRT12_DR\r
-SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_ATN__INT__MASK EQU 0x20\r
-SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5\r
-SCSI_ATN__INT__PORT EQU 12\r
-SCSI_ATN__INT__SHIFT EQU 5\r
-SCSI_ATN__MASK EQU 0x20\r
-SCSI_ATN__PORT EQU 12\r
-SCSI_ATN__PRT EQU CYREG_PRT12_PRT\r
-SCSI_ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_ATN__PS EQU CYREG_PRT12_PS\r
-SCSI_ATN__SHIFT EQU 5\r
-SCSI_ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_ATN__SLW EQU CYREG_PRT12_SLW\r
-\r
/* SCSI_CLK */\r
SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
SCSI_Out__SEL__SHIFT EQU 3\r
SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
\r
-/* SCSI_RST */\r
-SCSI_RST__0__MASK EQU 0x40\r
-SCSI_RST__0__PC EQU CYREG_PRT6_PC6\r
-SCSI_RST__0__PORT EQU 6\r
-SCSI_RST__0__SHIFT EQU 6\r
-SCSI_RST__AG EQU CYREG_PRT6_AG\r
-SCSI_RST__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_RST__BIE EQU CYREG_PRT6_BIE\r
-SCSI_RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_RST__BYP EQU CYREG_PRT6_BYP\r
-SCSI_RST__CTL EQU CYREG_PRT6_CTL\r
-SCSI_RST__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_RST__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_RST__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_RST__DR EQU CYREG_PRT6_DR\r
-SCSI_RST__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_RST__INTSTAT EQU CYREG_PICU6_INTSTAT\r
-SCSI_RST__INT__MASK EQU 0x40\r
-SCSI_RST__INT__PC EQU CYREG_PRT6_PC6\r
-SCSI_RST__INT__PORT EQU 6\r
-SCSI_RST__INT__SHIFT EQU 6\r
-SCSI_RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_RST__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_RST__MASK EQU 0x40\r
-SCSI_RST__PORT EQU 6\r
-SCSI_RST__PRT EQU CYREG_PRT6_PRT\r
-SCSI_RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_RST__PS EQU CYREG_PRT6_PS\r
-SCSI_RST__SHIFT EQU 6\r
-SCSI_RST__SLW EQU CYREG_PRT6_SLW\r
-SCSI_RST__SNAP EQU CYREG_PICU6_SNAP\r
-\r
/* USBFS_Dm */\r
USBFS_Dm__0__MASK EQU 0x80\r
USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__1__MASK EQU 0x10\r
-SCSI_In__1__PC EQU CYREG_PRT6_PC4\r
+SCSI_In__1__MASK EQU 0x80\r
+SCSI_In__1__PC EQU CYREG_PRT6_PC7\r
SCSI_In__1__PORT EQU 6\r
SCSI_In__1__PRT EQU CYREG_PRT6_PRT\r
SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
SCSI_In__1__PS EQU CYREG_PRT6_PS\r
-SCSI_In__1__SHIFT EQU 4\r
+SCSI_In__1__SHIFT EQU 7\r
SCSI_In__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In__2__AG EQU CYREG_PRT6_AG\r
-SCSI_In__2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__2__DR EQU CYREG_PRT6_DR\r
-SCSI_In__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__2__MASK EQU 0x20\r
-SCSI_In__2__PC EQU CYREG_PRT6_PC5\r
-SCSI_In__2__PORT EQU 6\r
-SCSI_In__2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__2__PS EQU CYREG_PRT6_PS\r
-SCSI_In__2__SHIFT EQU 5\r
-SCSI_In__2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In__3__AG EQU CYREG_PRT6_AG\r
-SCSI_In__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__3__DR EQU CYREG_PRT6_DR\r
-SCSI_In__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__3__MASK EQU 0x80\r
-SCSI_In__3__PC EQU CYREG_PRT6_PC7\r
-SCSI_In__3__PORT EQU 6\r
-SCSI_In__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__3__PS EQU CYREG_PRT6_PS\r
-SCSI_In__3__SHIFT EQU 7\r
-SCSI_In__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__2__AG EQU CYREG_PRT5_AG\r
+SCSI_In__2__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__2__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__2__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__2__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__2__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__2__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__2__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__2__DR EQU CYREG_PRT5_DR\r
+SCSI_In__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__2__MASK EQU 0x02\r
+SCSI_In__2__PC EQU CYREG_PRT5_PC1\r
+SCSI_In__2__PORT EQU 5\r
+SCSI_In__2__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__2__PS EQU CYREG_PRT5_PS\r
+SCSI_In__2__SHIFT EQU 1\r
+SCSI_In__2__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__3__AG EQU CYREG_PRT5_AG\r
+SCSI_In__3__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__3__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__3__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__3__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__3__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__3__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__3__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__3__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__3__DR EQU CYREG_PRT5_DR\r
+SCSI_In__3__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__3__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__3__MASK EQU 0x04\r
+SCSI_In__3__PC EQU CYREG_PRT5_PC2\r
+SCSI_In__3__PORT EQU 5\r
+SCSI_In__3__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__3__PS EQU CYREG_PRT5_PS\r
+SCSI_In__3__SHIFT EQU 2\r
+SCSI_In__3__SLW EQU CYREG_PRT5_SLW\r
SCSI_In__4__AG EQU CYREG_PRT5_AG\r
SCSI_In__4__AMUX EQU CYREG_PRT5_AMUX\r
SCSI_In__4__BIE EQU CYREG_PRT5_BIE\r
SCSI_In__4__INP_DIS EQU CYREG_PRT5_INP_DIS\r
SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
SCSI_In__4__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__4__MASK EQU 0x01\r
-SCSI_In__4__PC EQU CYREG_PRT5_PC0\r
+SCSI_In__4__MASK EQU 0x08\r
+SCSI_In__4__PC EQU CYREG_PRT5_PC3\r
SCSI_In__4__PORT EQU 5\r
SCSI_In__4__PRT EQU CYREG_PRT5_PRT\r
SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
SCSI_In__4__PS EQU CYREG_PRT5_PS\r
-SCSI_In__4__SHIFT EQU 0\r
+SCSI_In__4__SHIFT EQU 3\r
SCSI_In__4__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__5__AG EQU CYREG_PRT5_AG\r
-SCSI_In__5__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__5__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__5__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__5__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__5__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__5__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__5__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__5__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__5__DR EQU CYREG_PRT5_DR\r
-SCSI_In__5__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__5__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__5__MASK EQU 0x02\r
-SCSI_In__5__PC EQU CYREG_PRT5_PC1\r
-SCSI_In__5__PORT EQU 5\r
-SCSI_In__5__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__5__PS EQU CYREG_PRT5_PS\r
-SCSI_In__5__SHIFT EQU 1\r
-SCSI_In__5__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__6__AG EQU CYREG_PRT5_AG\r
-SCSI_In__6__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__6__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__6__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__6__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__6__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__6__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__6__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__6__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__6__DR EQU CYREG_PRT5_DR\r
-SCSI_In__6__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__6__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__6__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__6__MASK EQU 0x04\r
-SCSI_In__6__PC EQU CYREG_PRT5_PC2\r
-SCSI_In__6__PORT EQU 5\r
-SCSI_In__6__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__6__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__6__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__6__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__6__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__6__PS EQU CYREG_PRT5_PS\r
-SCSI_In__6__SHIFT EQU 2\r
-SCSI_In__6__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__7__AG EQU CYREG_PRT5_AG\r
-SCSI_In__7__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__7__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__7__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__7__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__7__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__7__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__7__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__7__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__7__DR EQU CYREG_PRT5_DR\r
-SCSI_In__7__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__7__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__7__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__7__MASK EQU 0x08\r
-SCSI_In__7__PC EQU CYREG_PRT5_PC3\r
-SCSI_In__7__PORT EQU 5\r
-SCSI_In__7__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__7__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__7__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__7__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__7__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__7__PS EQU CYREG_PRT5_PS\r
-SCSI_In__7__SHIFT EQU 3\r
-SCSI_In__7__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__ACK__AG EQU CYREG_PRT6_AG\r
-SCSI_In__ACK__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__ACK__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__ACK__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__ACK__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__ACK__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__ACK__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__ACK__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__ACK__DR EQU CYREG_PRT6_DR\r
-SCSI_In__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__ACK__MASK EQU 0x20\r
-SCSI_In__ACK__PC EQU CYREG_PRT6_PC5\r
-SCSI_In__ACK__PORT EQU 6\r
-SCSI_In__ACK__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__ACK__PS EQU CYREG_PRT6_PS\r
-SCSI_In__ACK__SHIFT EQU 5\r
-SCSI_In__ACK__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In__BSY__AG EQU CYREG_PRT6_AG\r
-SCSI_In__BSY__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__BSY__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__BSY__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__BSY__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__BSY__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__BSY__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__BSY__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__BSY__DR EQU CYREG_PRT6_DR\r
-SCSI_In__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__BSY__MASK EQU 0x10\r
-SCSI_In__BSY__PC EQU CYREG_PRT6_PC4\r
-SCSI_In__BSY__PORT EQU 6\r
-SCSI_In__BSY__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__BSY__PS EQU CYREG_PRT6_PS\r
-SCSI_In__BSY__SHIFT EQU 4\r
-SCSI_In__BSY__SLW EQU CYREG_PRT6_SLW\r
SCSI_In__CD__AG EQU CYREG_PRT5_AG\r
SCSI_In__CD__AMUX EQU CYREG_PRT5_AMUX\r
SCSI_In__CD__BIE EQU CYREG_PRT5_BIE\r
SCSI_In__REQ__PS EQU CYREG_PRT5_PS\r
SCSI_In__REQ__SHIFT EQU 2\r
SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__SEL__AG EQU CYREG_PRT5_AG\r
-SCSI_In__SEL__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__SEL__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__SEL__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__SEL__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__SEL__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__SEL__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__SEL__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__SEL__DR EQU CYREG_PRT5_DR\r
-SCSI_In__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__SEL__MASK EQU 0x01\r
-SCSI_In__SEL__PC EQU CYREG_PRT5_PC0\r
-SCSI_In__SEL__PORT EQU 5\r
-SCSI_In__SEL__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__SEL__PS EQU CYREG_PRT5_PS\r
-SCSI_In__SEL__SHIFT EQU 0\r
-SCSI_In__SEL__SLW EQU CYREG_PRT5_SLW\r
\r
/* SD_DAT1 */\r
SD_DAT1__0__MASK EQU 0x01\r
CYDEV_ECC_ENABLE EQU 0\r
CYDEV_HEAP_SIZE EQU 0x0400\r
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x0000001E\r
+CYDEV_INTR_RISING EQU 0x0000003E\r
CYDEV_PROJ_TYPE EQU 2\r
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
; SCSI_TX_DMA_COMPLETE\r
SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x04\r
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 2\r
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08\r
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3\r
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; SD_RX_DMA_COMPLETE\r
SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x08\r
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 3\r
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; SD_TX_DMA_COMPLETE\r
SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; SCSI_Parity_Error\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
\r
; USBFS_bus_reset\r
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
; SCSI_CTL_PHASE\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+\r
+; SCSI_Filtered\r
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST\r
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB00_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB00_ST\r
\r
; SCSI_Out_Bits\r
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
\r
; USBFS_arb_int\r
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
; SCSI_Out_Ctl\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
\r
; SCSI_Out_DBx\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
; SCSI_RST_ISR\r
SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RST_ISR__INTC_MASK EQU 0x400\r
-SCSI_RST_ISR__INTC_NUMBER EQU 10\r
+SCSI_RST_ISR__INTC_MASK EQU 0x04\r
+SCSI_RST_ISR__INTC_NUMBER EQU 2\r
SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10\r
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB05_06_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB05_06_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB05_06_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB05_06_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB05_06_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB05_06_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB05_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB05_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB05_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB05_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB05_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB05_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB05_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB05_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB05_F1\r
\r
; USBFS_dp_int\r
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
timer_clock__PM_STBY_MSK EQU 0x04\r
\r
+; SCSI_Noise\r
+SCSI_Noise__0__AG EQU CYREG_PRT12_AG\r
+SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_Noise__0__DR EQU CYREG_PRT12_DR\r
+SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_Noise__0__MASK EQU 0x20\r
+SCSI_Noise__0__PC EQU CYREG_PRT12_PC5\r
+SCSI_Noise__0__PORT EQU 12\r
+SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_Noise__0__PS EQU CYREG_PRT12_PS\r
+SCSI_Noise__0__SHIFT EQU 5\r
+SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_Noise__1__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__1__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__1__MASK EQU 0x10\r
+SCSI_Noise__1__PC EQU CYREG_PRT6_PC4\r
+SCSI_Noise__1__PORT EQU 6\r
+SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__1__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__1__SHIFT EQU 4\r
+SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__2__AG EQU CYREG_PRT5_AG\r
+SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Noise__2__DR EQU CYREG_PRT5_DR\r
+SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Noise__2__MASK EQU 0x01\r
+SCSI_Noise__2__PC EQU CYREG_PRT5_PC0\r
+SCSI_Noise__2__PORT EQU 5\r
+SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Noise__2__PS EQU CYREG_PRT5_PS\r
+SCSI_Noise__2__SHIFT EQU 0\r
+SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW\r
+SCSI_Noise__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__3__MASK EQU 0x40\r
+SCSI_Noise__3__PC EQU CYREG_PRT6_PC6\r
+SCSI_Noise__3__PORT EQU 6\r
+SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__3__SHIFT EQU 6\r
+SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__4__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__4__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__4__MASK EQU 0x20\r
+SCSI_Noise__4__PC EQU CYREG_PRT6_PC5\r
+SCSI_Noise__4__PORT EQU 6\r
+SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__4__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__4__SHIFT EQU 5\r
+SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__ACK__MASK EQU 0x20\r
+SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5\r
+SCSI_Noise__ACK__PORT EQU 6\r
+SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__ACK__SHIFT EQU 5\r
+SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG\r
+SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE\r
+SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP\r
+SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR\r
+SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_Noise__ATN__MASK EQU 0x20\r
+SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5\r
+SCSI_Noise__ATN__PORT EQU 12\r
+SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT\r
+SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS\r
+SCSI_Noise__ATN__SHIFT EQU 5\r
+SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW\r
+SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__BSY__MASK EQU 0x10\r
+SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4\r
+SCSI_Noise__BSY__PORT EQU 6\r
+SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__BSY__SHIFT EQU 4\r
+SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__RST__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__RST__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__RST__MASK EQU 0x40\r
+SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6\r
+SCSI_Noise__RST__PORT EQU 6\r
+SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__RST__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__RST__SHIFT EQU 6\r
+SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG\r
+SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR\r
+SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Noise__SEL__MASK EQU 0x01\r
+SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0\r
+SCSI_Noise__SEL__PORT EQU 5\r
+SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS\r
+SCSI_Noise__SEL__SHIFT EQU 0\r
+SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW\r
+\r
; scsiTarget\r
scsiTarget_StatusReg__0__MASK EQU 0x01\r
scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL\r
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB04_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB04_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB04_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB04_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB04_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB04_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB04_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB04_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK\r
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB12_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB12_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB12_13_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB12_13_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB12_13_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB12_13_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB12_13_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB12_13_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB12_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB12_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB12_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB12_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB12_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB12_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB12_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB12_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB12_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
\r
; USBFS_ep_0\r
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
; USBFS_ep_1\r
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x20\r
-USBFS_ep_1__INTC_NUMBER EQU 5\r
+USBFS_ep_1__INTC_MASK EQU 0x40\r
+USBFS_ep_1__INTC_NUMBER EQU 6\r
USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; USBFS_ep_2\r
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x40\r
-USBFS_ep_2__INTC_NUMBER EQU 6\r
+USBFS_ep_2__INTC_MASK EQU 0x80\r
+USBFS_ep_2__INTC_NUMBER EQU 7\r
USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; USBFS_ep_3\r
USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_3__INTC_MASK EQU 0x80\r
-USBFS_ep_3__INTC_NUMBER EQU 7\r
+USBFS_ep_3__INTC_MASK EQU 0x100\r
+USBFS_ep_3__INTC_NUMBER EQU 8\r
USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; USBFS_ep_4\r
USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_4__INTC_MASK EQU 0x100\r
-USBFS_ep_4__INTC_NUMBER EQU 8\r
+USBFS_ep_4__INTC_MASK EQU 0x200\r
+USBFS_ep_4__INTC_NUMBER EQU 9\r
USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
\r
-; SCSI_ATN\r
-SCSI_ATN__0__MASK EQU 0x20\r
-SCSI_ATN__0__PC EQU CYREG_PRT12_PC5\r
-SCSI_ATN__0__PORT EQU 12\r
-SCSI_ATN__0__SHIFT EQU 5\r
-SCSI_ATN__AG EQU CYREG_PRT12_AG\r
-SCSI_ATN__BIE EQU CYREG_PRT12_BIE\r
-SCSI_ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_ATN__BYP EQU CYREG_PRT12_BYP\r
-SCSI_ATN__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_ATN__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_ATN__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_ATN__DR EQU CYREG_PRT12_DR\r
-SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_ATN__INT__MASK EQU 0x20\r
-SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5\r
-SCSI_ATN__INT__PORT EQU 12\r
-SCSI_ATN__INT__SHIFT EQU 5\r
-SCSI_ATN__MASK EQU 0x20\r
-SCSI_ATN__PORT EQU 12\r
-SCSI_ATN__PRT EQU CYREG_PRT12_PRT\r
-SCSI_ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_ATN__PS EQU CYREG_PRT12_PS\r
-SCSI_ATN__SHIFT EQU 5\r
-SCSI_ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_ATN__SLW EQU CYREG_PRT12_SLW\r
-\r
; SCSI_CLK\r
SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
SCSI_Out__SEL__SHIFT EQU 3\r
SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
\r
-; SCSI_RST\r
-SCSI_RST__0__MASK EQU 0x40\r
-SCSI_RST__0__PC EQU CYREG_PRT6_PC6\r
-SCSI_RST__0__PORT EQU 6\r
-SCSI_RST__0__SHIFT EQU 6\r
-SCSI_RST__AG EQU CYREG_PRT6_AG\r
-SCSI_RST__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_RST__BIE EQU CYREG_PRT6_BIE\r
-SCSI_RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_RST__BYP EQU CYREG_PRT6_BYP\r
-SCSI_RST__CTL EQU CYREG_PRT6_CTL\r
-SCSI_RST__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_RST__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_RST__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_RST__DR EQU CYREG_PRT6_DR\r
-SCSI_RST__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_RST__INTSTAT EQU CYREG_PICU6_INTSTAT\r
-SCSI_RST__INT__MASK EQU 0x40\r
-SCSI_RST__INT__PC EQU CYREG_PRT6_PC6\r
-SCSI_RST__INT__PORT EQU 6\r
-SCSI_RST__INT__SHIFT EQU 6\r
-SCSI_RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_RST__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_RST__MASK EQU 0x40\r
-SCSI_RST__PORT EQU 6\r
-SCSI_RST__PRT EQU CYREG_PRT6_PRT\r
-SCSI_RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_RST__PS EQU CYREG_PRT6_PS\r
-SCSI_RST__SHIFT EQU 6\r
-SCSI_RST__SLW EQU CYREG_PRT6_SLW\r
-SCSI_RST__SNAP EQU CYREG_PICU6_SNAP\r
-\r
; USBFS_Dm\r
USBFS_Dm__0__MASK EQU 0x80\r
USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__1__MASK EQU 0x10\r
-SCSI_In__1__PC EQU CYREG_PRT6_PC4\r
+SCSI_In__1__MASK EQU 0x80\r
+SCSI_In__1__PC EQU CYREG_PRT6_PC7\r
SCSI_In__1__PORT EQU 6\r
SCSI_In__1__PRT EQU CYREG_PRT6_PRT\r
SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
SCSI_In__1__PS EQU CYREG_PRT6_PS\r
-SCSI_In__1__SHIFT EQU 4\r
+SCSI_In__1__SHIFT EQU 7\r
SCSI_In__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In__2__AG EQU CYREG_PRT6_AG\r
-SCSI_In__2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__2__DR EQU CYREG_PRT6_DR\r
-SCSI_In__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__2__MASK EQU 0x20\r
-SCSI_In__2__PC EQU CYREG_PRT6_PC5\r
-SCSI_In__2__PORT EQU 6\r
-SCSI_In__2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__2__PS EQU CYREG_PRT6_PS\r
-SCSI_In__2__SHIFT EQU 5\r
-SCSI_In__2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In__3__AG EQU CYREG_PRT6_AG\r
-SCSI_In__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__3__DR EQU CYREG_PRT6_DR\r
-SCSI_In__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__3__MASK EQU 0x80\r
-SCSI_In__3__PC EQU CYREG_PRT6_PC7\r
-SCSI_In__3__PORT EQU 6\r
-SCSI_In__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__3__PS EQU CYREG_PRT6_PS\r
-SCSI_In__3__SHIFT EQU 7\r
-SCSI_In__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__2__AG EQU CYREG_PRT5_AG\r
+SCSI_In__2__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__2__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__2__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__2__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__2__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__2__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__2__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__2__DR EQU CYREG_PRT5_DR\r
+SCSI_In__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__2__MASK EQU 0x02\r
+SCSI_In__2__PC EQU CYREG_PRT5_PC1\r
+SCSI_In__2__PORT EQU 5\r
+SCSI_In__2__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__2__PS EQU CYREG_PRT5_PS\r
+SCSI_In__2__SHIFT EQU 1\r
+SCSI_In__2__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__3__AG EQU CYREG_PRT5_AG\r
+SCSI_In__3__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__3__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__3__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__3__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__3__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__3__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__3__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__3__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__3__DR EQU CYREG_PRT5_DR\r
+SCSI_In__3__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__3__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__3__MASK EQU 0x04\r
+SCSI_In__3__PC EQU CYREG_PRT5_PC2\r
+SCSI_In__3__PORT EQU 5\r
+SCSI_In__3__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__3__PS EQU CYREG_PRT5_PS\r
+SCSI_In__3__SHIFT EQU 2\r
+SCSI_In__3__SLW EQU CYREG_PRT5_SLW\r
SCSI_In__4__AG EQU CYREG_PRT5_AG\r
SCSI_In__4__AMUX EQU CYREG_PRT5_AMUX\r
SCSI_In__4__BIE EQU CYREG_PRT5_BIE\r
SCSI_In__4__INP_DIS EQU CYREG_PRT5_INP_DIS\r
SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
SCSI_In__4__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__4__MASK EQU 0x01\r
-SCSI_In__4__PC EQU CYREG_PRT5_PC0\r
+SCSI_In__4__MASK EQU 0x08\r
+SCSI_In__4__PC EQU CYREG_PRT5_PC3\r
SCSI_In__4__PORT EQU 5\r
SCSI_In__4__PRT EQU CYREG_PRT5_PRT\r
SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
SCSI_In__4__PS EQU CYREG_PRT5_PS\r
-SCSI_In__4__SHIFT EQU 0\r
+SCSI_In__4__SHIFT EQU 3\r
SCSI_In__4__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__5__AG EQU CYREG_PRT5_AG\r
-SCSI_In__5__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__5__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__5__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__5__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__5__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__5__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__5__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__5__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__5__DR EQU CYREG_PRT5_DR\r
-SCSI_In__5__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__5__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__5__MASK EQU 0x02\r
-SCSI_In__5__PC EQU CYREG_PRT5_PC1\r
-SCSI_In__5__PORT EQU 5\r
-SCSI_In__5__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__5__PS EQU CYREG_PRT5_PS\r
-SCSI_In__5__SHIFT EQU 1\r
-SCSI_In__5__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__6__AG EQU CYREG_PRT5_AG\r
-SCSI_In__6__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__6__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__6__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__6__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__6__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__6__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__6__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__6__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__6__DR EQU CYREG_PRT5_DR\r
-SCSI_In__6__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__6__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__6__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__6__MASK EQU 0x04\r
-SCSI_In__6__PC EQU CYREG_PRT5_PC2\r
-SCSI_In__6__PORT EQU 5\r
-SCSI_In__6__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__6__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__6__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__6__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__6__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__6__PS EQU CYREG_PRT5_PS\r
-SCSI_In__6__SHIFT EQU 2\r
-SCSI_In__6__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__7__AG EQU CYREG_PRT5_AG\r
-SCSI_In__7__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__7__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__7__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__7__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__7__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__7__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__7__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__7__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__7__DR EQU CYREG_PRT5_DR\r
-SCSI_In__7__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__7__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__7__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__7__MASK EQU 0x08\r
-SCSI_In__7__PC EQU CYREG_PRT5_PC3\r
-SCSI_In__7__PORT EQU 5\r
-SCSI_In__7__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__7__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__7__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__7__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__7__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__7__PS EQU CYREG_PRT5_PS\r
-SCSI_In__7__SHIFT EQU 3\r
-SCSI_In__7__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__ACK__AG EQU CYREG_PRT6_AG\r
-SCSI_In__ACK__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__ACK__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__ACK__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__ACK__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__ACK__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__ACK__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__ACK__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__ACK__DR EQU CYREG_PRT6_DR\r
-SCSI_In__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__ACK__MASK EQU 0x20\r
-SCSI_In__ACK__PC EQU CYREG_PRT6_PC5\r
-SCSI_In__ACK__PORT EQU 6\r
-SCSI_In__ACK__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__ACK__PS EQU CYREG_PRT6_PS\r
-SCSI_In__ACK__SHIFT EQU 5\r
-SCSI_In__ACK__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In__BSY__AG EQU CYREG_PRT6_AG\r
-SCSI_In__BSY__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__BSY__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__BSY__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__BSY__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__BSY__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__BSY__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__BSY__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__BSY__DR EQU CYREG_PRT6_DR\r
-SCSI_In__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__BSY__MASK EQU 0x10\r
-SCSI_In__BSY__PC EQU CYREG_PRT6_PC4\r
-SCSI_In__BSY__PORT EQU 6\r
-SCSI_In__BSY__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__BSY__PS EQU CYREG_PRT6_PS\r
-SCSI_In__BSY__SHIFT EQU 4\r
-SCSI_In__BSY__SLW EQU CYREG_PRT6_SLW\r
SCSI_In__CD__AG EQU CYREG_PRT5_AG\r
SCSI_In__CD__AMUX EQU CYREG_PRT5_AMUX\r
SCSI_In__CD__BIE EQU CYREG_PRT5_BIE\r
SCSI_In__REQ__PS EQU CYREG_PRT5_PS\r
SCSI_In__REQ__SHIFT EQU 2\r
SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__SEL__AG EQU CYREG_PRT5_AG\r
-SCSI_In__SEL__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__SEL__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__SEL__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__SEL__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__SEL__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__SEL__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__SEL__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__SEL__DR EQU CYREG_PRT5_DR\r
-SCSI_In__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__SEL__MASK EQU 0x01\r
-SCSI_In__SEL__PC EQU CYREG_PRT5_PC0\r
-SCSI_In__SEL__PORT EQU 5\r
-SCSI_In__SEL__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__SEL__PS EQU CYREG_PRT5_PS\r
-SCSI_In__SEL__SHIFT EQU 0\r
-SCSI_In__SEL__SLW EQU CYREG_PRT5_SLW\r
\r
; SD_DAT1\r
SD_DAT1__0__MASK EQU 0x01\r
CYDEV_ECC_ENABLE EQU 0\r
CYDEV_HEAP_SIZE EQU 0x0400\r
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x0000001E\r
+CYDEV_INTR_RISING EQU 0x0000003E\r
CYDEV_PROJ_TYPE EQU 2\r
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
#include <SD_MOSI_aliases.h>\r
#include <SD_MOSI.h>\r
#include <SCSI_CLK.h>\r
-#include <SCSI_RST_aliases.h>\r
-#include <SCSI_RST.h>\r
-#include <SCSI_ATN_aliases.h>\r
-#include <SCSI_ATN.h>\r
+#include <SCSI_Noise_aliases.h>\r
#include <SCSI_RST_ISR.h>\r
#include <LED1_aliases.h>\r
#include <LED1.h>\r
#include <SCSI_RX_DMA_dma.h>\r
#include <SCSI_RX_DMA_COMPLETE.h>\r
#include <SCSI_Parity_Error.h>\r
+#include <SCSI_Filtered.h>\r
#include <USBFS_Dm_aliases.h>\r
#include <USBFS_Dm.h>\r
#include <USBFS_Dp_aliases.h>\r
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard_PM.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard_INT.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard_PVT.h</File>
- <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_aliases.h</File>
- <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST.c</File>
- <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST.h</File>
- <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN_aliases.h</File>
- <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN.c</File>
- <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_ISR.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_ISR.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cymetadata.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RX_DMA_COMPLETE.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Parity_Error.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Parity_Error.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Noise_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Filtered.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Filtered.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\prebuild.bat</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\postbuild.bat</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyElfTool.exe</File>
<?xml version="1.0" encoding="utf-8"?>\r
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
- <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647E" bitWidth="8" desc="" />\r
- </block>\r
+ <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />\r
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" />\r
+ </block>\r
+ <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />\r
</block>\r
+ <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />\r
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />\r
</block>\r
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Filtered_STATUS_REG" address="0x40006460" bitWidth="8" desc="" />\r
+ <register name="SCSI_Filtered_MASK_REG" address="0x40006480" bitWidth="8" desc="" />\r
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006490" bitWidth="8" desc="">\r
+ <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
+ <value name="ENABLED" value="1" desc="Enable counter" />\r
+ <value name="DISABLED" value="0" desc="Disable counter" />\r
+ </field>\r
+ <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">\r
+ <value name="ENABLED" value="1" desc="Interrupt enabled" />\r
+ <value name="DISABLED" value="0" desc="Interrupt disabled" />\r
+ </field>\r
+ <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">\r
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
+ </field>\r
+ <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">\r
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
+ </field>\r
+ <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">\r
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
+ </field>\r
+ <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">\r
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
+ </field>\r
+ </register>\r
+ </block>\r
+ <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006467" bitWidth="8" desc="" />\r
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x40006487" bitWidth="8" desc="" />\r
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006497" bitWidth="8" desc="">\r
+ <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
+ <value name="ENABLED" value="1" desc="Enable counter" />\r
+ <value name="DISABLED" value="0" desc="Disable counter" />\r
+ </field>\r
+ <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">\r
+ <value name="ENABLED" value="1" desc="Interrupt enabled" />\r
+ <value name="DISABLED" value="0" desc="Interrupt disabled" />\r
+ </field>\r
+ <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">\r
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
+ </field>\r
+ <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">\r
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
+ </field>\r
+ <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">\r
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
+ </field>\r
+ <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">\r
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
+ </field>\r
+ </register>\r
+ </block>\r
+ <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />\r
+ </block>\r
+ <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />\r
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />\r
</block>\r
- <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646A" bitWidth="8" desc="" />\r
- <register name="SCSI_Parity_Error_MASK_REG" address="0x4000648A" bitWidth="8" desc="" />\r
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649A" bitWidth="8" desc="">\r
- <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
- <value name="ENABLED" value="1" desc="Enable counter" />\r
- <value name="DISABLED" value="0" desc="Disable counter" />\r
- </field>\r
- <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">\r
- <value name="ENABLED" value="1" desc="Interrupt enabled" />\r
- <value name="DISABLED" value="0" desc="Interrupt disabled" />\r
- </field>\r
- <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">\r
- <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
- <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
- </field>\r
- <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">\r
- <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
- <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
- </field>\r
- <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">\r
- <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
- <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
- </field>\r
- <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">\r
- <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
- <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
- </field>\r
- </register>\r
- </block>\r
- <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />\r
- </block>\r
- <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
</blockRegMap>
\ No newline at end of file
<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_RST" persistent="">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
<dependencies>\r
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_RST_aliases.h" persistent=".\Generated_Source\PSoC5\SCSI_RST_aliases.h">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
<build_action v="NONE" />\r
<PropertyDeltas />\r
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_RST.c" persistent=".\Generated_Source\PSoC5\SCSI_RST.c">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
<build_action v="ARM_C_FILE" />\r
<PropertyDeltas />\r
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_RST.h" persistent=".\Generated_Source\PSoC5\SCSI_RST.h">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
<build_action v="NONE" />\r
<PropertyDeltas />\r
<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_ATN" persistent="">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
<dependencies>\r
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_ATN_aliases.h" persistent=".\Generated_Source\PSoC5\SCSI_ATN_aliases.h">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
<build_action v="NONE" />\r
<PropertyDeltas />\r
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_ATN.c" persistent=".\Generated_Source\PSoC5\SCSI_ATN.c">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
<build_action v="ARM_C_FILE" />\r
<PropertyDeltas />\r
<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_ATN.h" persistent=".\Generated_Source\PSoC5\SCSI_ATN.h">\r
-<Hidden v="False" />\r
+<Hidden v="True" />\r
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
<build_action v="NONE" />\r
<PropertyDeltas />\r
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
<filters />\r
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="Status_Reg_1" persistent="">\r
+<Hidden v="True" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
+<dependencies>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="Status_Reg_1.c" persistent=".\Generated_Source\PSoC5\Status_Reg_1.c">\r
+<Hidden v="True" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="ARM_C_FILE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="Status_Reg_1.h" persistent=".\Generated_Source\PSoC5\Status_Reg_1.h">\r
+<Hidden v="True" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="NONE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
+</dependencies>\r
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
+<filters />\r
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Noise" persistent="">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
+<dependencies>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Noise_aliases.h" persistent=".\Generated_Source\PSoC5\SCSI_Noise_aliases.h">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="NONE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
+</dependencies>\r
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
+<filters />\r
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Filtered" persistent="">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
+<dependencies>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Filtered.c" persistent=".\Generated_Source\PSoC5\SCSI_Filtered.c">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="ARM_C_FILE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Filtered.h" persistent=".\Generated_Source\PSoC5\SCSI_Filtered.h">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="NONE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
+</dependencies>\r
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
+<filters />\r
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
</dependencies>\r
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
<width>32</width>\r
<peripherals>\r
<peripheral>\r
- <name>SCSI_Out_Ctl</name>\r
+ <name>SCSI_Out_Bits</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000647E</baseAddress>\r
+ <baseAddress>0x40006473</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x1</size>\r
</addressBlock>\r
<registers>\r
<register>\r
- <name>SCSI_Out_Ctl_CONTROL_REG</name>\r
+ <name>SCSI_Out_Bits_CONTROL_REG</name>\r
<description>No description available</description>\r
<addressOffset>0x0</addressOffset>\r
<size>8</size>\r
</registers>\r
</peripheral>\r
<peripheral>\r
- <name>SCSI_Out_Bits</name>\r
+ <name>SCSI_Out_Ctl</name>\r
<description>No description available</description>\r
<baseAddress>0x4000647B</baseAddress>\r
<addressBlock>\r
</addressBlock>\r
<registers>\r
<register>\r
- <name>SCSI_Out_Bits_CONTROL_REG</name>\r
+ <name>SCSI_Out_Ctl_CONTROL_REG</name>\r
<description>No description available</description>\r
<addressOffset>0x0</addressOffset>\r
<size>8</size>\r
</register>\r
</registers>\r
</peripheral>\r
+ <peripheral>\r
+ <name>SCSI_Filtered</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x40006460</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x31</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_Filtered_STATUS_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>SCSI_Filtered_MASK_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x20</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x30</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>FIFO0</name>\r
+ <description>FIFO0 clear</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Enable counter</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Disable counter</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>INTRENBL</name>\r
+ <description>Enables or disables the Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Interrupt enabled</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Interrupt disabled</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO1LEVEL</name>\r
+ <description>FIFO level</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO0LEVEL</name>\r
+ <description>FIFO level</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO1CLEAR</name>\r
+ <description>FIFO clear</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Clear FIFO state</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Normal FIFO operation</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO0CLEAR</name>\r
+ <description>FIFO clear</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Clear FIFO state</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Normal FIFO operation</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
+ <peripheral>\r
+ <name>SCSI_Parity_Error</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x40006467</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x31</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_Parity_Error_STATUS_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>SCSI_Parity_Error_MASK_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x20</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x30</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>FIFO0</name>\r
+ <description>FIFO0 clear</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Enable counter</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Disable counter</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>INTRENBL</name>\r
+ <description>Enables or disables the Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Interrupt enabled</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Interrupt disabled</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO1LEVEL</name>\r
+ <description>FIFO level</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO0LEVEL</name>\r
+ <description>FIFO level</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO1CLEAR</name>\r
+ <description>FIFO clear</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Clear FIFO state</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Normal FIFO operation</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO0CLEAR</name>\r
+ <description>FIFO clear</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Clear FIFO state</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Normal FIFO operation</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
+ <peripheral>\r
+ <name>SCSI_CTL_PHASE</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x40006472</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x1</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_CTL_PHASE_CONTROL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
<peripheral>\r
<name>USBFS</name>\r
<description>USBFS</description>\r
</register>\r
</registers>\r
</peripheral>\r
- <peripheral>\r
- <name>SCSI_Parity_Error</name>\r
- <description>No description available</description>\r
- <baseAddress>0x4000646A</baseAddress>\r
- <addressBlock>\r
- <offset>0</offset>\r
- <size>0x31</size>\r
- <usage>registers</usage>\r
- </addressBlock>\r
- <registers>\r
- <register>\r
- <name>SCSI_Parity_Error_STATUS_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>SCSI_Parity_Error_MASK_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x20</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x30</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- <fields>\r
- <field>\r
- <name>FIFO0</name>\r
- <description>FIFO0 clear</description>\r
- <lsb>5</lsb>\r
- <msb>5</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>Enable counter</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>Disable counter</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>INTRENBL</name>\r
- <description>Enables or disables the Interrupt</description>\r
- <lsb>4</lsb>\r
- <msb>4</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>Interrupt enabled</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>Interrupt disabled</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>FIFO1LEVEL</name>\r
- <description>FIFO level</description>\r
- <lsb>3</lsb>\r
- <msb>3</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>FIFO0LEVEL</name>\r
- <description>FIFO level</description>\r
- <lsb>2</lsb>\r
- <msb>2</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>FIFO1CLEAR</name>\r
- <description>FIFO clear</description>\r
- <lsb>1</lsb>\r
- <msb>1</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>Clear FIFO state</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>Normal FIFO operation</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>FIFO0CLEAR</name>\r
- <description>FIFO clear</description>\r
- <lsb>0</lsb>\r
- <msb>0</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>Clear FIFO state</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>Normal FIFO operation</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- </fields>\r
- </register>\r
- </registers>\r
- </peripheral>\r
- <peripheral>\r
- <name>SCSI_CTL_PHASE</name>\r
- <description>No description available</description>\r
- <baseAddress>0x40006471</baseAddress>\r
- <addressBlock>\r
- <offset>0</offset>\r
- <size>0x1</size>\r
- <usage>registers</usage>\r
- </addressBlock>\r
- <registers>\r
- <register>\r
- <name>SCSI_CTL_PHASE_CONTROL_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- </registers>\r
- </peripheral>\r
</peripherals>\r
</device>
\ No newline at end of file
localparam IO_READ = 1'b0;\r
\r
\r
-/////////////////////////////////////////////////////////////////////////////\r
-// Input filter\r
-/////////////////////////////////////////////////////////////////////////////\r
-// Do not respond to glitches in the ACK signal. This will cause us to\r
-// transfer rubbish data, or too many bytes, and generally leads to\r
-// hanging the SCSI bus. Reflected signals can cause the ACK signal\r
-// to be dirty. We don't care so much about the others as we don't\r
-// respond to them on the rising edge.\r
-// 4-stage shifter. Ass\r
-reg safeACK;\r
-reg[3:0] ackShift;\r
-always @(posedge op_clk) begin\r
- if (ackShift[3:1] == 0) begin\r
- safeACK <= 0;\r
- end\r
- else if (ackShift[3:1] == 1) begin\r
- safeACK <= 1;\r
- end\r
- ackShift <= {ackShift[2:0], ~nACK};\r
-end\r
-\r
/////////////////////////////////////////////////////////////////////////////\r
// STATE MACHINE\r
/////////////////////////////////////////////////////////////////////////////\r
wire f0_blk_stat; // Tx FIFO empty\r
wire f1_bus_stat; // Rx FIFO not empty\r
wire f1_blk_stat; // Rx FIFO full\r
-wire txComplete = f0_blk_stat && (state == STATE_IDLE) && ~safeACK;\r
+wire txComplete = f0_blk_stat && (state == STATE_IDLE) && nACK;\r
cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg\r
(\r
/* input */ .clock(op_clk),\r
// and output FIFO is not full.\r
// Note that output FIFO is unused in TX mode.\r
if (!nRST) state <= STATE_IDLE;\r
- else if (~safeACK & !f0_blk_stat && ((IO == IO_WRITE) || !f1_blk_stat))\r
+ else if (nACK & !f0_blk_stat && ((IO == IO_WRITE) || !f1_blk_stat))\r
state <= STATE_FIFOLOAD;\r
else\r
state <= STATE_IDLE;\r
\r
STATE_READY:\r
if (!nRST) state <= STATE_IDLE;\r
- else if (safeACK) begin\r
+ else if (~nACK) begin\r
state <= STATE_RX;\r
fifoStore <= 1'b1;\r
\r
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Filtered.c
+* Version 1.80
+*
+* Description:
+* This file contains API to enable firmware to read the value of a Status
+* Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Filtered.h"
+
+#if !defined(SCSI_Filtered_sts_sts_reg__REMOVED) /* Check for removal by optimization */
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_Read
+********************************************************************************
+*
+* Summary:
+* Reads the current value assigned to the Status Register.
+*
+* Parameters:
+* None.
+*
+* Return:
+* The current value in the Status Register.
+*
+*******************************************************************************/
+uint8 SCSI_Filtered_Read(void)
+{
+ return SCSI_Filtered_Status;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_InterruptEnable
+********************************************************************************
+*
+* Summary:
+* Enables the Status Register interrupt.
+*
+* Parameters:
+* None.
+*
+* Return:
+* None.
+*
+*******************************************************************************/
+void SCSI_Filtered_InterruptEnable(void)
+{
+ uint8 interruptState;
+ interruptState = CyEnterCriticalSection();
+ SCSI_Filtered_Status_Aux_Ctrl |= SCSI_Filtered_STATUS_INTR_ENBL;
+ CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_InterruptDisable
+********************************************************************************
+*
+* Summary:
+* Disables the Status Register interrupt.
+*
+* Parameters:
+* None.
+*
+* Return:
+* None.
+*
+*******************************************************************************/
+void SCSI_Filtered_InterruptDisable(void)
+{
+ uint8 interruptState;
+ interruptState = CyEnterCriticalSection();
+ SCSI_Filtered_Status_Aux_Ctrl &= (uint8)(~SCSI_Filtered_STATUS_INTR_ENBL);
+ CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_WriteMask
+********************************************************************************
+*
+* Summary:
+* Writes the current mask value assigned to the Status Register.
+*
+* Parameters:
+* mask: Value to write into the mask register.
+*
+* Return:
+* None.
+*
+*******************************************************************************/
+void SCSI_Filtered_WriteMask(uint8 mask)
+{
+ #if(SCSI_Filtered_INPUTS < 8u)
+ mask &= (uint8)((((uint8)1u) << SCSI_Filtered_INPUTS) - 1u);
+ #endif /* End SCSI_Filtered_INPUTS < 8u */
+ SCSI_Filtered_Status_Mask = mask;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Filtered_ReadMask
+********************************************************************************
+*
+* Summary:
+* Reads the current interrupt mask assigned to the Status Register.
+*
+* Parameters:
+* None.
+*
+* Return:
+* The value of the interrupt mask of the Status Register.
+*
+*******************************************************************************/
+uint8 SCSI_Filtered_ReadMask(void)
+{
+ return SCSI_Filtered_Status_Mask;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Filtered.h
+* Version 1.80
+*
+* Description:
+* This file containts Status Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_STATUS_REG_SCSI_Filtered_H) /* CY_STATUS_REG_SCSI_Filtered_H */
+#define CY_STATUS_REG_SCSI_Filtered_H
+
+#include "cytypes.h"
+#include "CyLib.h"
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+uint8 SCSI_Filtered_Read(void) ;
+void SCSI_Filtered_InterruptEnable(void) ;
+void SCSI_Filtered_InterruptDisable(void) ;
+void SCSI_Filtered_WriteMask(uint8 mask) ;
+uint8 SCSI_Filtered_ReadMask(void) ;
+
+
+/***************************************
+* API Constants
+***************************************/
+
+#define SCSI_Filtered_STATUS_INTR_ENBL 0x10u
+
+
+/***************************************
+* Parameter Constants
+***************************************/
+
+/* Status Register Inputs */
+#define SCSI_Filtered_INPUTS 5
+
+
+/***************************************
+* Registers
+***************************************/
+
+/* Status Register */
+#define SCSI_Filtered_Status (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG )
+#define SCSI_Filtered_Status_PTR ( (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG )
+#define SCSI_Filtered_Status_Mask (* (reg8 *) SCSI_Filtered_sts_sts_reg__MASK_REG )
+#define SCSI_Filtered_Status_Aux_Ctrl (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG )
+
+#endif /* End CY_STATUS_REG_SCSI_Filtered_H */
+
+
+/* [] END OF FILE */
#define SCSI_In_2 SCSI_In__2__PC
#define SCSI_In_3 SCSI_In__3__PC
#define SCSI_In_4 SCSI_In__4__PC
-#define SCSI_In_5 SCSI_In__5__PC
-#define SCSI_In_6 SCSI_In__6__PC
-#define SCSI_In_7 SCSI_In__7__PC
#define SCSI_In_DBP SCSI_In__DBP__PC
-#define SCSI_In_BSY SCSI_In__BSY__PC
-#define SCSI_In_ACK SCSI_In__ACK__PC
#define SCSI_In_MSG SCSI_In__MSG__PC
-#define SCSI_In_SEL SCSI_In__SEL__PC
#define SCSI_In_CD SCSI_In__CD__PC
#define SCSI_In_REQ SCSI_In__REQ__PC
#define SCSI_In_IO SCSI_In__IO__PC
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Noise.h
+* Version 1.90
+*
+* Description:
+* This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_PINS_SCSI_Noise_ALIASES_H) /* Pins SCSI_Noise_ALIASES_H */
+#define CY_PINS_SCSI_Noise_ALIASES_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+
+
+
+/***************************************
+* Constants
+***************************************/
+#define SCSI_Noise_0 SCSI_Noise__0__PC
+#define SCSI_Noise_1 SCSI_Noise__1__PC
+#define SCSI_Noise_2 SCSI_Noise__2__PC
+#define SCSI_Noise_3 SCSI_Noise__3__PC
+#define SCSI_Noise_4 SCSI_Noise__4__PC
+
+#define SCSI_Noise_ATN SCSI_Noise__ATN__PC
+#define SCSI_Noise_BSY SCSI_Noise__BSY__PC
+#define SCSI_Noise_SEL SCSI_Noise__SEL__PC
+#define SCSI_Noise_RST SCSI_Noise__RST__PC
+#define SCSI_Noise_ACK SCSI_Noise__ACK__PC
+
+#endif /* End Pins SCSI_Noise_ALIASES_H */
+
+/* [] END OF FILE */
/* bMaxPacketSize0 */ 0x08u,
/* idVendor */ 0xB4u, 0x04u,
/* idProduct */ 0x37u, 0x13u,
-/* bcdDevice */ 0x02u, 0x30u,
+/* bcdDevice */ 0x01u, 0x30u,
/* iManufacturer */ 0x02u,
/* iProduct */ 0x01u,
/* iSerialNumber */ 0x80u,
/* SCSI_TX_DMA_COMPLETE */
#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x04u
-#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 2u
+#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u
+#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u
#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3
#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SD_RX_DMA_COMPLETE */
#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SD_RX_DMA_COMPLETE__INTC_MASK 0x08u
-#define SD_RX_DMA_COMPLETE__INTC_NUMBER 3u
+#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u
+#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u
#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SD_TX_DMA_COMPLETE */
#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SD_TX_DMA_COMPLETE__INTC_MASK 0x10u
-#define SD_TX_DMA_COMPLETE__INTC_NUMBER 4u
+#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u
+#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u
#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5
#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK
-#define SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B1_UDB11_MSK
+#define SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG CYREG_B1_UDB11_ST_CTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG CYREG_B1_UDB11_ST_CTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B1_UDB11_ST
/* USBFS_bus_reset */
#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
+
+/* SCSI_Filtered */
+#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u
+#define SCSI_Filtered_sts_sts_reg__0__POS 0
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST
+#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
+#define SCSI_Filtered_sts_sts_reg__1__POS 1
+#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
+#define SCSI_Filtered_sts_sts_reg__2__POS 2
+#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
+#define SCSI_Filtered_sts_sts_reg__3__POS 3
+#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
+#define SCSI_Filtered_sts_sts_reg__4__POS 4
+#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB13_MSK
+#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
+#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB13_ST_CTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB13_ST_CTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB13_ST
/* SCSI_Out_Bits */
#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB11_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB11_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB11_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB11_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
/* USBFS_arb_int */
#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
/* SCSI_Out_Ctl */
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB09_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB09_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB11_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB11_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB11_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB11_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB11_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB09_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB11_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
/* SCSI_Out_DBx */
#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
/* SCSI_RST_ISR */
#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_RST_ISR__INTC_MASK 0x100u
-#define SCSI_RST_ISR__INTC_NUMBER 8u
+#define SCSI_RST_ISR__INTC_MASK 0x04u
+#define SCSI_RST_ISR__INTC_NUMBER 2u
#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u
-#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_8
+#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2
#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB09_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB09_ST
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB09_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB09_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB09_MSK
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB10_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB10_ST
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB06_MSK
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB06_ST
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
#define SDCard_BSPIM_TxStsReg__0__POS 0
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB11_MSK
-#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
-#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B1_UDB11_ST_CTL
-#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB11_ST_CTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB11_ST
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB09_10_A0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB09_10_A1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB09_10_D0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB09_10_D1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB09_10_F0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB09_10_F1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB09_A0_A1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB09_A0
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB09_A1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB09_D0_D1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB09_D0
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB09_D1
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB09_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB09_F0_F1
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB09_F0
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB09_F1
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB05_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB05_ST
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB05_06_A0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB05_06_A1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB05_06_D0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB05_06_D1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB05_06_F0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB05_06_F1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB05_A0_A1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB05_A0
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB05_A1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB05_D0_D1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB05_D0
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB05_D1
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB05_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB05_F0_F1
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB05_F0
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB05_F1
/* USBFS_dp_int */
#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2
#define timer_clock__PM_STBY_MSK 0x04u
+/* SCSI_Noise */
+#define SCSI_Noise__0__AG CYREG_PRT2_AG
+#define SCSI_Noise__0__AMUX CYREG_PRT2_AMUX
+#define SCSI_Noise__0__BIE CYREG_PRT2_BIE
+#define SCSI_Noise__0__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Noise__0__BYP CYREG_PRT2_BYP
+#define SCSI_Noise__0__CTL CYREG_PRT2_CTL
+#define SCSI_Noise__0__DM0 CYREG_PRT2_DM0
+#define SCSI_Noise__0__DM1 CYREG_PRT2_DM1
+#define SCSI_Noise__0__DM2 CYREG_PRT2_DM2
+#define SCSI_Noise__0__DR CYREG_PRT2_DR
+#define SCSI_Noise__0__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Noise__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Noise__0__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Noise__0__MASK 0x01u
+#define SCSI_Noise__0__PC CYREG_PRT2_PC0
+#define SCSI_Noise__0__PORT 2u
+#define SCSI_Noise__0__PRT CYREG_PRT2_PRT
+#define SCSI_Noise__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Noise__0__PS CYREG_PRT2_PS
+#define SCSI_Noise__0__SHIFT 0
+#define SCSI_Noise__0__SLW CYREG_PRT2_SLW
+#define SCSI_Noise__1__AG CYREG_PRT6_AG
+#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__1__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__1__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__1__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__1__DR CYREG_PRT6_DR
+#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__1__MASK 0x08u
+#define SCSI_Noise__1__PC CYREG_PRT6_PC3
+#define SCSI_Noise__1__PORT 6u
+#define SCSI_Noise__1__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__1__PS CYREG_PRT6_PS
+#define SCSI_Noise__1__SHIFT 3
+#define SCSI_Noise__1__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__2__AG CYREG_PRT4_AG
+#define SCSI_Noise__2__AMUX CYREG_PRT4_AMUX
+#define SCSI_Noise__2__BIE CYREG_PRT4_BIE
+#define SCSI_Noise__2__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Noise__2__BYP CYREG_PRT4_BYP
+#define SCSI_Noise__2__CTL CYREG_PRT4_CTL
+#define SCSI_Noise__2__DM0 CYREG_PRT4_DM0
+#define SCSI_Noise__2__DM1 CYREG_PRT4_DM1
+#define SCSI_Noise__2__DM2 CYREG_PRT4_DM2
+#define SCSI_Noise__2__DR CYREG_PRT4_DR
+#define SCSI_Noise__2__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Noise__2__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Noise__2__MASK 0x08u
+#define SCSI_Noise__2__PC CYREG_PRT4_PC3
+#define SCSI_Noise__2__PORT 4u
+#define SCSI_Noise__2__PRT CYREG_PRT4_PRT
+#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Noise__2__PS CYREG_PRT4_PS
+#define SCSI_Noise__2__SHIFT 3
+#define SCSI_Noise__2__SLW CYREG_PRT4_SLW
+#define SCSI_Noise__3__AG CYREG_PRT4_AG
+#define SCSI_Noise__3__AMUX CYREG_PRT4_AMUX
+#define SCSI_Noise__3__BIE CYREG_PRT4_BIE
+#define SCSI_Noise__3__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Noise__3__BYP CYREG_PRT4_BYP
+#define SCSI_Noise__3__CTL CYREG_PRT4_CTL
+#define SCSI_Noise__3__DM0 CYREG_PRT4_DM0
+#define SCSI_Noise__3__DM1 CYREG_PRT4_DM1
+#define SCSI_Noise__3__DM2 CYREG_PRT4_DM2
+#define SCSI_Noise__3__DR CYREG_PRT4_DR
+#define SCSI_Noise__3__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Noise__3__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Noise__3__MASK 0x80u
+#define SCSI_Noise__3__PC CYREG_PRT4_PC7
+#define SCSI_Noise__3__PORT 4u
+#define SCSI_Noise__3__PRT CYREG_PRT4_PRT
+#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Noise__3__PS CYREG_PRT4_PS
+#define SCSI_Noise__3__SHIFT 7
+#define SCSI_Noise__3__SLW CYREG_PRT4_SLW
+#define SCSI_Noise__4__AG CYREG_PRT6_AG
+#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__4__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__4__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__4__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__4__DR CYREG_PRT6_DR
+#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__4__MASK 0x04u
+#define SCSI_Noise__4__PC CYREG_PRT6_PC2
+#define SCSI_Noise__4__PORT 6u
+#define SCSI_Noise__4__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__4__PS CYREG_PRT6_PS
+#define SCSI_Noise__4__SHIFT 2
+#define SCSI_Noise__4__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__ACK__AG CYREG_PRT6_AG
+#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__ACK__DR CYREG_PRT6_DR
+#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__ACK__MASK 0x04u
+#define SCSI_Noise__ACK__PC CYREG_PRT6_PC2
+#define SCSI_Noise__ACK__PORT 6u
+#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__ACK__PS CYREG_PRT6_PS
+#define SCSI_Noise__ACK__SHIFT 2
+#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__ATN__AG CYREG_PRT2_AG
+#define SCSI_Noise__ATN__AMUX CYREG_PRT2_AMUX
+#define SCSI_Noise__ATN__BIE CYREG_PRT2_BIE
+#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Noise__ATN__BYP CYREG_PRT2_BYP
+#define SCSI_Noise__ATN__CTL CYREG_PRT2_CTL
+#define SCSI_Noise__ATN__DM0 CYREG_PRT2_DM0
+#define SCSI_Noise__ATN__DM1 CYREG_PRT2_DM1
+#define SCSI_Noise__ATN__DM2 CYREG_PRT2_DM2
+#define SCSI_Noise__ATN__DR CYREG_PRT2_DR
+#define SCSI_Noise__ATN__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Noise__ATN__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Noise__ATN__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Noise__ATN__MASK 0x01u
+#define SCSI_Noise__ATN__PC CYREG_PRT2_PC0
+#define SCSI_Noise__ATN__PORT 2u
+#define SCSI_Noise__ATN__PRT CYREG_PRT2_PRT
+#define SCSI_Noise__ATN__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Noise__ATN__PS CYREG_PRT2_PS
+#define SCSI_Noise__ATN__SHIFT 0
+#define SCSI_Noise__ATN__SLW CYREG_PRT2_SLW
+#define SCSI_Noise__BSY__AG CYREG_PRT6_AG
+#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__BSY__DR CYREG_PRT6_DR
+#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__BSY__MASK 0x08u
+#define SCSI_Noise__BSY__PC CYREG_PRT6_PC3
+#define SCSI_Noise__BSY__PORT 6u
+#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__BSY__PS CYREG_PRT6_PS
+#define SCSI_Noise__BSY__SHIFT 3
+#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__RST__AG CYREG_PRT4_AG
+#define SCSI_Noise__RST__AMUX CYREG_PRT4_AMUX
+#define SCSI_Noise__RST__BIE CYREG_PRT4_BIE
+#define SCSI_Noise__RST__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Noise__RST__BYP CYREG_PRT4_BYP
+#define SCSI_Noise__RST__CTL CYREG_PRT4_CTL
+#define SCSI_Noise__RST__DM0 CYREG_PRT4_DM0
+#define SCSI_Noise__RST__DM1 CYREG_PRT4_DM1
+#define SCSI_Noise__RST__DM2 CYREG_PRT4_DM2
+#define SCSI_Noise__RST__DR CYREG_PRT4_DR
+#define SCSI_Noise__RST__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Noise__RST__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Noise__RST__MASK 0x80u
+#define SCSI_Noise__RST__PC CYREG_PRT4_PC7
+#define SCSI_Noise__RST__PORT 4u
+#define SCSI_Noise__RST__PRT CYREG_PRT4_PRT
+#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Noise__RST__PS CYREG_PRT4_PS
+#define SCSI_Noise__RST__SHIFT 7
+#define SCSI_Noise__RST__SLW CYREG_PRT4_SLW
+#define SCSI_Noise__SEL__AG CYREG_PRT4_AG
+#define SCSI_Noise__SEL__AMUX CYREG_PRT4_AMUX
+#define SCSI_Noise__SEL__BIE CYREG_PRT4_BIE
+#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Noise__SEL__BYP CYREG_PRT4_BYP
+#define SCSI_Noise__SEL__CTL CYREG_PRT4_CTL
+#define SCSI_Noise__SEL__DM0 CYREG_PRT4_DM0
+#define SCSI_Noise__SEL__DM1 CYREG_PRT4_DM1
+#define SCSI_Noise__SEL__DM2 CYREG_PRT4_DM2
+#define SCSI_Noise__SEL__DR CYREG_PRT4_DR
+#define SCSI_Noise__SEL__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Noise__SEL__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Noise__SEL__MASK 0x08u
+#define SCSI_Noise__SEL__PC CYREG_PRT4_PC3
+#define SCSI_Noise__SEL__PORT 4u
+#define SCSI_Noise__SEL__PRT CYREG_PRT4_PRT
+#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Noise__SEL__PS CYREG_PRT4_PS
+#define SCSI_Noise__SEL__SHIFT 3
+#define SCSI_Noise__SEL__SLW CYREG_PRT4_SLW
+
/* scsiTarget */
#define scsiTarget_StatusReg__0__MASK 0x01u
#define scsiTarget_StatusReg__0__POS 0
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
#define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1
#define scsiTarget_StatusReg__2__MASK 0x04u
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB04_MSK
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB04_ST
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB11_MSK
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB11_ST
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB11_CTL
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB11_CTL
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB11_MSK
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB11_12_A0
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB11_12_A1
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB11_12_D0
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB11_12_D1
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB11_12_F0
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB11_12_F1
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB11_A0_A1
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB11_A0
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB11_A1
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB11_D0_D1
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB11_D0
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB11_D1
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB11_F0_F1
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB11_F0
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB11_F1
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_StatusReg__MASK_REG CYREG_B1_UDB04_MSK
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B1_UDB04_ST
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB08_MSK
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB08_ST
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB08_CTL
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB08_CTL
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB08_MSK
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB08_09_A0
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB08_09_A1
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB08_09_D0
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB08_09_D1
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB08_09_F0
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB08_09_F1
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB08_A0_A1
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB08_A0
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB08_A1
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB08_D0_D1
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB08_D0
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB08_D1
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB08_F0_F1
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB08_F0
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB08_F1
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
/* USBFS_ep_0 */
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
/* USBFS_ep_1 */
#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_1__INTC_MASK 0x20u
-#define USBFS_ep_1__INTC_NUMBER 5u
+#define USBFS_ep_1__INTC_MASK 0x40u
+#define USBFS_ep_1__INTC_NUMBER 6u
#define USBFS_ep_1__INTC_PRIOR_NUM 7u
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_5
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6
#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* USBFS_ep_2 */
#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_2__INTC_MASK 0x40u
-#define USBFS_ep_2__INTC_NUMBER 6u
+#define USBFS_ep_2__INTC_MASK 0x80u
+#define USBFS_ep_2__INTC_NUMBER 7u
#define USBFS_ep_2__INTC_PRIOR_NUM 7u
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_6
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7
#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* USBFS_ep_3 */
#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_3__INTC_MASK 0x80u
-#define USBFS_ep_3__INTC_NUMBER 7u
+#define USBFS_ep_3__INTC_MASK 0x100u
+#define USBFS_ep_3__INTC_NUMBER 8u
#define USBFS_ep_3__INTC_PRIOR_NUM 7u
-#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_7
+#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8
#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
#define SD_RX_DMA__DRQ_NUMBER 2u
#define SD_RX_DMA__NUMBEROF_TDS 0u
-#define SD_RX_DMA__PRIORITY 1u
+#define SD_RX_DMA__PRIORITY 2u
#define SD_RX_DMA__TERMIN_EN 0u
#define SD_RX_DMA__TERMIN_SEL 0u
#define SD_RX_DMA__TERMOUT0_EN 1u
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
-/* SCSI_ATN */
-#define SCSI_ATN__0__MASK 0x01u
-#define SCSI_ATN__0__PC CYREG_PRT2_PC0
-#define SCSI_ATN__0__PORT 2u
-#define SCSI_ATN__0__SHIFT 0
-#define SCSI_ATN__AG CYREG_PRT2_AG
-#define SCSI_ATN__AMUX CYREG_PRT2_AMUX
-#define SCSI_ATN__BIE CYREG_PRT2_BIE
-#define SCSI_ATN__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_ATN__BYP CYREG_PRT2_BYP
-#define SCSI_ATN__CTL CYREG_PRT2_CTL
-#define SCSI_ATN__DM0 CYREG_PRT2_DM0
-#define SCSI_ATN__DM1 CYREG_PRT2_DM1
-#define SCSI_ATN__DM2 CYREG_PRT2_DM2
-#define SCSI_ATN__DR CYREG_PRT2_DR
-#define SCSI_ATN__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_ATN__INT__MASK 0x01u
-#define SCSI_ATN__INT__PC CYREG_PRT2_PC0
-#define SCSI_ATN__INT__PORT 2u
-#define SCSI_ATN__INT__SHIFT 0
-#define SCSI_ATN__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_ATN__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_ATN__MASK 0x01u
-#define SCSI_ATN__PORT 2u
-#define SCSI_ATN__PRT CYREG_PRT2_PRT
-#define SCSI_ATN__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_ATN__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_ATN__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_ATN__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_ATN__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_ATN__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_ATN__PS CYREG_PRT2_PS
-#define SCSI_ATN__SHIFT 0
-#define SCSI_ATN__SLW CYREG_PRT2_SLW
-
/* SCSI_CLK */
#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0
#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1
#define SCSI_Out__SEL__SHIFT 7
#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW
-/* SCSI_RST */
-#define SCSI_RST__0__MASK 0x80u
-#define SCSI_RST__0__PC CYREG_PRT4_PC7
-#define SCSI_RST__0__PORT 4u
-#define SCSI_RST__0__SHIFT 7
-#define SCSI_RST__AG CYREG_PRT4_AG
-#define SCSI_RST__AMUX CYREG_PRT4_AMUX
-#define SCSI_RST__BIE CYREG_PRT4_BIE
-#define SCSI_RST__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_RST__BYP CYREG_PRT4_BYP
-#define SCSI_RST__CTL CYREG_PRT4_CTL
-#define SCSI_RST__DM0 CYREG_PRT4_DM0
-#define SCSI_RST__DM1 CYREG_PRT4_DM1
-#define SCSI_RST__DM2 CYREG_PRT4_DM2
-#define SCSI_RST__DR CYREG_PRT4_DR
-#define SCSI_RST__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_RST__INTSTAT CYREG_PICU4_INTSTAT
-#define SCSI_RST__INT__MASK 0x80u
-#define SCSI_RST__INT__PC CYREG_PRT4_PC7
-#define SCSI_RST__INT__PORT 4u
-#define SCSI_RST__INT__SHIFT 7
-#define SCSI_RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_RST__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_RST__MASK 0x80u
-#define SCSI_RST__PORT 4u
-#define SCSI_RST__PRT CYREG_PRT4_PRT
-#define SCSI_RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_RST__PS CYREG_PRT4_PS
-#define SCSI_RST__SHIFT 7
-#define SCSI_RST__SLW CYREG_PRT4_SLW
-#define SCSI_RST__SNAP CYREG_PICU4_SNAP
-
/* USBFS_Dm */
#define USBFS_Dm__0__MASK 0x80u
#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
#define SCSI_In__0__PS CYREG_PRT2_PS
#define SCSI_In__0__SHIFT 1
#define SCSI_In__0__SLW CYREG_PRT2_SLW
-#define SCSI_In__1__AG CYREG_PRT6_AG
-#define SCSI_In__1__AMUX CYREG_PRT6_AMUX
-#define SCSI_In__1__BIE CYREG_PRT6_BIE
-#define SCSI_In__1__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In__1__BYP CYREG_PRT6_BYP
-#define SCSI_In__1__CTL CYREG_PRT6_CTL
-#define SCSI_In__1__DM0 CYREG_PRT6_DM0
-#define SCSI_In__1__DM1 CYREG_PRT6_DM1
-#define SCSI_In__1__DM2 CYREG_PRT6_DM2
-#define SCSI_In__1__DR CYREG_PRT6_DR
-#define SCSI_In__1__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In__1__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In__1__MASK 0x08u
-#define SCSI_In__1__PC CYREG_PRT6_PC3
-#define SCSI_In__1__PORT 6u
-#define SCSI_In__1__PRT CYREG_PRT6_PRT
-#define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In__1__PS CYREG_PRT6_PS
-#define SCSI_In__1__SHIFT 3
-#define SCSI_In__1__SLW CYREG_PRT6_SLW
-#define SCSI_In__2__AG CYREG_PRT6_AG
-#define SCSI_In__2__AMUX CYREG_PRT6_AMUX
-#define SCSI_In__2__BIE CYREG_PRT6_BIE
-#define SCSI_In__2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In__2__BYP CYREG_PRT6_BYP
-#define SCSI_In__2__CTL CYREG_PRT6_CTL
-#define SCSI_In__2__DM0 CYREG_PRT6_DM0
-#define SCSI_In__2__DM1 CYREG_PRT6_DM1
-#define SCSI_In__2__DM2 CYREG_PRT6_DM2
-#define SCSI_In__2__DR CYREG_PRT6_DR
-#define SCSI_In__2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In__2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_In__1__AG CYREG_PRT4_AG
+#define SCSI_In__1__AMUX CYREG_PRT4_AMUX
+#define SCSI_In__1__BIE CYREG_PRT4_BIE
+#define SCSI_In__1__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_In__1__BYP CYREG_PRT4_BYP
+#define SCSI_In__1__CTL CYREG_PRT4_CTL
+#define SCSI_In__1__DM0 CYREG_PRT4_DM0
+#define SCSI_In__1__DM1 CYREG_PRT4_DM1
+#define SCSI_In__1__DM2 CYREG_PRT4_DM2
+#define SCSI_In__1__DR CYREG_PRT4_DR
+#define SCSI_In__1__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_In__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_In__1__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_In__1__MASK 0x40u
+#define SCSI_In__1__PC CYREG_PRT4_PC6
+#define SCSI_In__1__PORT 4u
+#define SCSI_In__1__PRT CYREG_PRT4_PRT
+#define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_In__1__PS CYREG_PRT4_PS
+#define SCSI_In__1__SHIFT 6
+#define SCSI_In__1__SLW CYREG_PRT4_SLW
+#define SCSI_In__2__AG CYREG_PRT4_AG
+#define SCSI_In__2__AMUX CYREG_PRT4_AMUX
+#define SCSI_In__2__BIE CYREG_PRT4_BIE
+#define SCSI_In__2__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_In__2__BYP CYREG_PRT4_BYP
+#define SCSI_In__2__CTL CYREG_PRT4_CTL
+#define SCSI_In__2__DM0 CYREG_PRT4_DM0
+#define SCSI_In__2__DM1 CYREG_PRT4_DM1
+#define SCSI_In__2__DM2 CYREG_PRT4_DM2
+#define SCSI_In__2__DR CYREG_PRT4_DR
+#define SCSI_In__2__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_In__2__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_In__2__LCD_EN CYREG_PRT4_LCD_EN
#define SCSI_In__2__MASK 0x04u
-#define SCSI_In__2__PC CYREG_PRT6_PC2
-#define SCSI_In__2__PORT 6u
-#define SCSI_In__2__PRT CYREG_PRT6_PRT
-#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In__2__PS CYREG_PRT6_PS
+#define SCSI_In__2__PC CYREG_PRT4_PC2
+#define SCSI_In__2__PORT 4u
+#define SCSI_In__2__PRT CYREG_PRT4_PRT
+#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_In__2__PS CYREG_PRT4_PS
#define SCSI_In__2__SHIFT 2
-#define SCSI_In__2__SLW CYREG_PRT6_SLW
-#define SCSI_In__3__AG CYREG_PRT4_AG
-#define SCSI_In__3__AMUX CYREG_PRT4_AMUX
-#define SCSI_In__3__BIE CYREG_PRT4_BIE
-#define SCSI_In__3__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_In__3__BYP CYREG_PRT4_BYP
-#define SCSI_In__3__CTL CYREG_PRT4_CTL
-#define SCSI_In__3__DM0 CYREG_PRT4_DM0
-#define SCSI_In__3__DM1 CYREG_PRT4_DM1
-#define SCSI_In__3__DM2 CYREG_PRT4_DM2
-#define SCSI_In__3__DR CYREG_PRT4_DR
-#define SCSI_In__3__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_In__3__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_In__3__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_In__3__MASK 0x40u
-#define SCSI_In__3__PC CYREG_PRT4_PC6
-#define SCSI_In__3__PORT 4u
-#define SCSI_In__3__PRT CYREG_PRT4_PRT
-#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_In__3__PS CYREG_PRT4_PS
-#define SCSI_In__3__SHIFT 6
-#define SCSI_In__3__SLW CYREG_PRT4_SLW
-#define SCSI_In__4__AG CYREG_PRT4_AG
-#define SCSI_In__4__AMUX CYREG_PRT4_AMUX
-#define SCSI_In__4__BIE CYREG_PRT4_BIE
-#define SCSI_In__4__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_In__4__BYP CYREG_PRT4_BYP
-#define SCSI_In__4__CTL CYREG_PRT4_CTL
-#define SCSI_In__4__DM0 CYREG_PRT4_DM0
-#define SCSI_In__4__DM1 CYREG_PRT4_DM1
-#define SCSI_In__4__DM2 CYREG_PRT4_DM2
-#define SCSI_In__4__DR CYREG_PRT4_DR
-#define SCSI_In__4__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_In__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_In__4__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_In__4__MASK 0x08u
-#define SCSI_In__4__PC CYREG_PRT4_PC3
-#define SCSI_In__4__PORT 4u
-#define SCSI_In__4__PRT CYREG_PRT4_PRT
-#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_In__4__PS CYREG_PRT4_PS
-#define SCSI_In__4__SHIFT 3
-#define SCSI_In__4__SLW CYREG_PRT4_SLW
-#define SCSI_In__5__AG CYREG_PRT4_AG
-#define SCSI_In__5__AMUX CYREG_PRT4_AMUX
-#define SCSI_In__5__BIE CYREG_PRT4_BIE
-#define SCSI_In__5__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_In__5__BYP CYREG_PRT4_BYP
-#define SCSI_In__5__CTL CYREG_PRT4_CTL
-#define SCSI_In__5__DM0 CYREG_PRT4_DM0
-#define SCSI_In__5__DM1 CYREG_PRT4_DM1
-#define SCSI_In__5__DM2 CYREG_PRT4_DM2
-#define SCSI_In__5__DR CYREG_PRT4_DR
-#define SCSI_In__5__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_In__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_In__5__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_In__5__MASK 0x04u
-#define SCSI_In__5__PC CYREG_PRT4_PC2
-#define SCSI_In__5__PORT 4u
-#define SCSI_In__5__PRT CYREG_PRT4_PRT
-#define SCSI_In__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_In__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_In__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_In__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_In__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_In__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_In__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_In__5__PS CYREG_PRT4_PS
-#define SCSI_In__5__SHIFT 2
-#define SCSI_In__5__SLW CYREG_PRT4_SLW
-#define SCSI_In__6__AG CYREG_PRT0_AG
-#define SCSI_In__6__AMUX CYREG_PRT0_AMUX
-#define SCSI_In__6__BIE CYREG_PRT0_BIE
-#define SCSI_In__6__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_In__6__BYP CYREG_PRT0_BYP
-#define SCSI_In__6__CTL CYREG_PRT0_CTL
-#define SCSI_In__6__DM0 CYREG_PRT0_DM0
-#define SCSI_In__6__DM1 CYREG_PRT0_DM1
-#define SCSI_In__6__DM2 CYREG_PRT0_DM2
-#define SCSI_In__6__DR CYREG_PRT0_DR
-#define SCSI_In__6__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_In__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_In__6__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_In__6__MASK 0x20u
-#define SCSI_In__6__PC CYREG_PRT0_PC5
-#define SCSI_In__6__PORT 0u
-#define SCSI_In__6__PRT CYREG_PRT0_PRT
-#define SCSI_In__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_In__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_In__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_In__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_In__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_In__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_In__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_In__6__PS CYREG_PRT0_PS
-#define SCSI_In__6__SHIFT 5
-#define SCSI_In__6__SLW CYREG_PRT0_SLW
-#define SCSI_In__7__AG CYREG_PRT0_AG
-#define SCSI_In__7__AMUX CYREG_PRT0_AMUX
-#define SCSI_In__7__BIE CYREG_PRT0_BIE
-#define SCSI_In__7__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_In__7__BYP CYREG_PRT0_BYP
-#define SCSI_In__7__CTL CYREG_PRT0_CTL
-#define SCSI_In__7__DM0 CYREG_PRT0_DM0
-#define SCSI_In__7__DM1 CYREG_PRT0_DM1
-#define SCSI_In__7__DM2 CYREG_PRT0_DM2
-#define SCSI_In__7__DR CYREG_PRT0_DR
-#define SCSI_In__7__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_In__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_In__7__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_In__7__MASK 0x10u
-#define SCSI_In__7__PC CYREG_PRT0_PC4
-#define SCSI_In__7__PORT 0u
-#define SCSI_In__7__PRT CYREG_PRT0_PRT
-#define SCSI_In__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_In__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_In__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_In__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_In__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_In__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_In__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_In__7__PS CYREG_PRT0_PS
-#define SCSI_In__7__SHIFT 4
-#define SCSI_In__7__SLW CYREG_PRT0_SLW
-#define SCSI_In__ACK__AG CYREG_PRT6_AG
-#define SCSI_In__ACK__AMUX CYREG_PRT6_AMUX
-#define SCSI_In__ACK__BIE CYREG_PRT6_BIE
-#define SCSI_In__ACK__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In__ACK__BYP CYREG_PRT6_BYP
-#define SCSI_In__ACK__CTL CYREG_PRT6_CTL
-#define SCSI_In__ACK__DM0 CYREG_PRT6_DM0
-#define SCSI_In__ACK__DM1 CYREG_PRT6_DM1
-#define SCSI_In__ACK__DM2 CYREG_PRT6_DM2
-#define SCSI_In__ACK__DR CYREG_PRT6_DR
-#define SCSI_In__ACK__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In__ACK__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In__ACK__MASK 0x04u
-#define SCSI_In__ACK__PC CYREG_PRT6_PC2
-#define SCSI_In__ACK__PORT 6u
-#define SCSI_In__ACK__PRT CYREG_PRT6_PRT
-#define SCSI_In__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In__ACK__PS CYREG_PRT6_PS
-#define SCSI_In__ACK__SHIFT 2
-#define SCSI_In__ACK__SLW CYREG_PRT6_SLW
-#define SCSI_In__BSY__AG CYREG_PRT6_AG
-#define SCSI_In__BSY__AMUX CYREG_PRT6_AMUX
-#define SCSI_In__BSY__BIE CYREG_PRT6_BIE
-#define SCSI_In__BSY__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In__BSY__BYP CYREG_PRT6_BYP
-#define SCSI_In__BSY__CTL CYREG_PRT6_CTL
-#define SCSI_In__BSY__DM0 CYREG_PRT6_DM0
-#define SCSI_In__BSY__DM1 CYREG_PRT6_DM1
-#define SCSI_In__BSY__DM2 CYREG_PRT6_DM2
-#define SCSI_In__BSY__DR CYREG_PRT6_DR
-#define SCSI_In__BSY__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In__BSY__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In__BSY__MASK 0x08u
-#define SCSI_In__BSY__PC CYREG_PRT6_PC3
-#define SCSI_In__BSY__PORT 6u
-#define SCSI_In__BSY__PRT CYREG_PRT6_PRT
-#define SCSI_In__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In__BSY__PS CYREG_PRT6_PS
-#define SCSI_In__BSY__SHIFT 3
-#define SCSI_In__BSY__SLW CYREG_PRT6_SLW
+#define SCSI_In__2__SLW CYREG_PRT4_SLW
+#define SCSI_In__3__AG CYREG_PRT0_AG
+#define SCSI_In__3__AMUX CYREG_PRT0_AMUX
+#define SCSI_In__3__BIE CYREG_PRT0_BIE
+#define SCSI_In__3__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_In__3__BYP CYREG_PRT0_BYP
+#define SCSI_In__3__CTL CYREG_PRT0_CTL
+#define SCSI_In__3__DM0 CYREG_PRT0_DM0
+#define SCSI_In__3__DM1 CYREG_PRT0_DM1
+#define SCSI_In__3__DM2 CYREG_PRT0_DM2
+#define SCSI_In__3__DR CYREG_PRT0_DR
+#define SCSI_In__3__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_In__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_In__3__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_In__3__MASK 0x20u
+#define SCSI_In__3__PC CYREG_PRT0_PC5
+#define SCSI_In__3__PORT 0u
+#define SCSI_In__3__PRT CYREG_PRT0_PRT
+#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_In__3__PS CYREG_PRT0_PS
+#define SCSI_In__3__SHIFT 5
+#define SCSI_In__3__SLW CYREG_PRT0_SLW
+#define SCSI_In__4__AG CYREG_PRT0_AG
+#define SCSI_In__4__AMUX CYREG_PRT0_AMUX
+#define SCSI_In__4__BIE CYREG_PRT0_BIE
+#define SCSI_In__4__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_In__4__BYP CYREG_PRT0_BYP
+#define SCSI_In__4__CTL CYREG_PRT0_CTL
+#define SCSI_In__4__DM0 CYREG_PRT0_DM0
+#define SCSI_In__4__DM1 CYREG_PRT0_DM1
+#define SCSI_In__4__DM2 CYREG_PRT0_DM2
+#define SCSI_In__4__DR CYREG_PRT0_DR
+#define SCSI_In__4__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_In__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_In__4__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_In__4__MASK 0x10u
+#define SCSI_In__4__PC CYREG_PRT0_PC4
+#define SCSI_In__4__PORT 0u
+#define SCSI_In__4__PRT CYREG_PRT0_PRT
+#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_In__4__PS CYREG_PRT0_PS
+#define SCSI_In__4__SHIFT 4
+#define SCSI_In__4__SLW CYREG_PRT0_SLW
#define SCSI_In__CD__AG CYREG_PRT4_AG
#define SCSI_In__CD__AMUX CYREG_PRT4_AMUX
#define SCSI_In__CD__BIE CYREG_PRT4_BIE
#define SCSI_In__REQ__PS CYREG_PRT0_PS
#define SCSI_In__REQ__SHIFT 5
#define SCSI_In__REQ__SLW CYREG_PRT0_SLW
-#define SCSI_In__SEL__AG CYREG_PRT4_AG
-#define SCSI_In__SEL__AMUX CYREG_PRT4_AMUX
-#define SCSI_In__SEL__BIE CYREG_PRT4_BIE
-#define SCSI_In__SEL__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_In__SEL__BYP CYREG_PRT4_BYP
-#define SCSI_In__SEL__CTL CYREG_PRT4_CTL
-#define SCSI_In__SEL__DM0 CYREG_PRT4_DM0
-#define SCSI_In__SEL__DM1 CYREG_PRT4_DM1
-#define SCSI_In__SEL__DM2 CYREG_PRT4_DM2
-#define SCSI_In__SEL__DR CYREG_PRT4_DR
-#define SCSI_In__SEL__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_In__SEL__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_In__SEL__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_In__SEL__MASK 0x08u
-#define SCSI_In__SEL__PC CYREG_PRT4_PC3
-#define SCSI_In__SEL__PORT 4u
-#define SCSI_In__SEL__PRT CYREG_PRT4_PRT
-#define SCSI_In__SEL__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_In__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_In__SEL__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_In__SEL__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_In__SEL__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_In__SEL__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_In__SEL__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_In__SEL__PS CYREG_PRT4_PS
-#define SCSI_In__SEL__SHIFT 3
-#define SCSI_In__SEL__SLW CYREG_PRT4_SLW
/* SD_MISO */
#define SD_MISO__0__MASK 0x02u
#define CYDEV_ECC_ENABLE 0
#define CYDEV_HEAP_SIZE 0x1000
#define CYDEV_INSTRUCT_CACHE_ENABLED 1
-#define CYDEV_INTR_RISING 0x0000001Eu
+#define CYDEV_INTR_RISING 0x0000003Eu
#define CYDEV_PROJ_TYPE 2
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LOADABLE 2
}
#endif
-#define CY_CFG_BASE_ADDR_COUNT 38u
+#define CY_CFG_BASE_ADDR_COUNT 40u
CYPACKED typedef struct
{
uint8 offset;
static const uint8 CYCODE BS_IOPINS0_2_VAL[] = {
0x33u, 0xCCu, 0xCCu, 0x00u, 0xCCu, 0x00u, 0x00u, 0x01u};
- /* IOPINS0_3 Address: CYREG_PRT3_DM0 Size (bytes): 8 */
+ /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */
static const uint8 CYCODE BS_IOPINS0_3_VAL[] = {
- 0x00u, 0x3Eu, 0x00u, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x00u};
+ 0x10u, 0x00u, 0x22u, 0x1Cu, 0x1Cu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x00u};
/* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */
static const uint8 CYCODE BS_IOPINS0_4_VAL[] = {
{
static const uint32 CYCODE cy_cfg_addr_table[] = {
- 0x40004502u, /* Base address: 0x40004500 Count: 2 */
+ 0x40004501u, /* Base address: 0x40004500 Count: 1 */
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */
- 0x40005210u, /* Base address: 0x40005200 Count: 16 */
- 0x40006402u, /* Base address: 0x40006400 Count: 2 */
- 0x40010104u, /* Base address: 0x40010100 Count: 4 */
- 0x4001023Du, /* Base address: 0x40010200 Count: 61 */
- 0x40010340u, /* Base address: 0x40010300 Count: 64 */
- 0x40010451u, /* Base address: 0x40010400 Count: 81 */
- 0x4001054Eu, /* Base address: 0x40010500 Count: 78 */
- 0x40010715u, /* Base address: 0x40010700 Count: 21 */
- 0x40010818u, /* Base address: 0x40010800 Count: 24 */
+ 0x4000520Fu, /* Base address: 0x40005200 Count: 15 */
+ 0x40006401u, /* Base address: 0x40006400 Count: 1 */
+ 0x40006501u, /* Base address: 0x40006500 Count: 1 */
+ 0x40010102u, /* Base address: 0x40010100 Count: 2 */
+ 0x40010306u, /* Base address: 0x40010300 Count: 6 */
+ 0x40010510u, /* Base address: 0x40010500 Count: 16 */
+ 0x4001064Eu, /* Base address: 0x40010600 Count: 78 */
+ 0x40010744u, /* Base address: 0x40010700 Count: 68 */
+ 0x40010843u, /* Base address: 0x40010800 Count: 67 */
0x40010952u, /* Base address: 0x40010900 Count: 82 */
- 0x40010A4Cu, /* Base address: 0x40010A00 Count: 76 */
- 0x40010B57u, /* Base address: 0x40010B00 Count: 87 */
- 0x40010C48u, /* Base address: 0x40010C00 Count: 72 */
- 0x40010D4Du, /* Base address: 0x40010D00 Count: 77 */
- 0x40010E53u, /* Base address: 0x40010E00 Count: 83 */
- 0x40010F3Cu, /* Base address: 0x40010F00 Count: 60 */
- 0x4001150Bu, /* Base address: 0x40011500 Count: 11 */
- 0x4001170Fu, /* Base address: 0x40011700 Count: 15 */
- 0x4001184Eu, /* Base address: 0x40011800 Count: 78 */
- 0x40011947u, /* Base address: 0x40011900 Count: 71 */
- 0x40011A48u, /* Base address: 0x40011A00 Count: 72 */
- 0x40011B57u, /* Base address: 0x40011B00 Count: 87 */
- 0x40014016u, /* Base address: 0x40014000 Count: 22 */
- 0x40014114u, /* Base address: 0x40014100 Count: 20 */
- 0x40014211u, /* Base address: 0x40014200 Count: 17 */
- 0x40014306u, /* Base address: 0x40014300 Count: 6 */
+ 0x40010A4Du, /* Base address: 0x40010A00 Count: 77 */
+ 0x40010B52u, /* Base address: 0x40010B00 Count: 82 */
+ 0x40010C3Bu, /* Base address: 0x40010C00 Count: 59 */
+ 0x40010D47u, /* Base address: 0x40010D00 Count: 71 */
+ 0x40010E4Du, /* Base address: 0x40010E00 Count: 77 */
+ 0x40010F34u, /* Base address: 0x40010F00 Count: 52 */
+ 0x40011455u, /* Base address: 0x40011400 Count: 85 */
+ 0x40011551u, /* Base address: 0x40011500 Count: 81 */
+ 0x40011657u, /* Base address: 0x40011600 Count: 87 */
+ 0x40011752u, /* Base address: 0x40011700 Count: 82 */
+ 0x40011850u, /* Base address: 0x40011800 Count: 80 */
+ 0x40011955u, /* Base address: 0x40011900 Count: 85 */
+ 0x40011A52u, /* Base address: 0x40011A00 Count: 82 */
+ 0x40011B60u, /* Base address: 0x40011B00 Count: 96 */
+ 0x40014015u, /* Base address: 0x40014000 Count: 21 */
+ 0x4001411Cu, /* Base address: 0x40014100 Count: 28 */
+ 0x40014212u, /* Base address: 0x40014200 Count: 18 */
+ 0x40014305u, /* Base address: 0x40014300 Count: 5 */
0x40014411u, /* Base address: 0x40014400 Count: 17 */
- 0x40014513u, /* Base address: 0x40014500 Count: 19 */
- 0x40014610u, /* Base address: 0x40014600 Count: 16 */
- 0x4001470Bu, /* Base address: 0x40014700 Count: 11 */
- 0x40014806u, /* Base address: 0x40014800 Count: 6 */
- 0x4001490Du, /* Base address: 0x40014900 Count: 13 */
- 0x40014C07u, /* Base address: 0x40014C00 Count: 7 */
- 0x40014D0Fu, /* Base address: 0x40014D00 Count: 15 */
- 0x40015004u, /* Base address: 0x40015000 Count: 4 */
+ 0x40014516u, /* Base address: 0x40014500 Count: 22 */
+ 0x40014611u, /* Base address: 0x40014600 Count: 17 */
+ 0x40014715u, /* Base address: 0x40014700 Count: 21 */
+ 0x40014807u, /* Base address: 0x40014800 Count: 7 */
+ 0x4001490Cu, /* Base address: 0x40014900 Count: 12 */
+ 0x40014C0Au, /* Base address: 0x40014C00 Count: 10 */
+ 0x40014D11u, /* Base address: 0x40014D00 Count: 17 */
+ 0x40015006u, /* Base address: 0x40015000 Count: 6 */
0x40015104u, /* Base address: 0x40015100 Count: 4 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
- {0x27u, 0x02u},
{0x7Eu, 0x02u},
{0x01u, 0x20u},
- {0x0Au, 0x4Bu},
+ {0x0Au, 0x36u},
{0x00u, 0x08u},
- {0x01u, 0x40u},
+ {0x01u, 0x08u},
{0x04u, 0x31u},
- {0x10u, 0x84u},
- {0x11u, 0x08u},
- {0x14u, 0x01u},
+ {0x10u, 0xC4u},
+ {0x11u, 0x8Cu},
{0x18u, 0x08u},
- {0x19u, 0x0Cu},
+ {0x19u, 0x04u},
{0x1Cu, 0x20u},
{0x21u, 0x10u},
- {0x24u, 0x4Cu},
- {0x28u, 0x02u},
- {0x31u, 0x20u},
- {0x34u, 0x08u},
+ {0x24u, 0x44u},
+ {0x28u, 0x01u},
+ {0x29u, 0x01u},
+ {0x31u, 0x10u},
{0x78u, 0x20u},
{0x7Cu, 0x40u},
- {0x2Bu, 0x02u},
- {0x89u, 0x0Fu},
- {0x8Bu, 0x01u},
- {0x8Eu, 0x40u},
+ {0x28u, 0x02u},
+ {0x87u, 0x0Fu},
+ {0x8Fu, 0x01u},
+ {0xE6u, 0x80u},
+ {0x93u, 0x01u},
+ {0xE0u, 0x40u},
+ {0xE4u, 0x10u},
+ {0xE6u, 0x41u},
+ {0xEAu, 0x04u},
+ {0xEEu, 0x08u},
+ {0x60u, 0x20u},
+ {0x61u, 0x08u},
+ {0x81u, 0x08u},
+ {0x82u, 0x80u},
+ {0x87u, 0x40u},
+ {0x88u, 0x80u},
+ {0x8Du, 0x20u},
+ {0x91u, 0x20u},
+ {0x93u, 0x01u},
+ {0x98u, 0x14u},
+ {0xACu, 0x14u},
+ {0xB1u, 0x10u},
+ {0xE2u, 0x2Du},
{0xE4u, 0x04u},
- {0xE6u, 0x22u},
- {0x04u, 0x01u},
+ {0xEAu, 0x08u},
+ {0xEEu, 0x02u},
+ {0x00u, 0x08u},
+ {0x01u, 0x01u},
+ {0x04u, 0x11u},
+ {0x05u, 0xA2u},
+ {0x06u, 0x22u},
+ {0x07u, 0x08u},
+ {0x08u, 0x40u},
+ {0x09u, 0x01u},
+ {0x0Cu, 0x40u},
+ {0x0Du, 0x01u},
+ {0x10u, 0x1Cu},
+ {0x11u, 0x08u},
+ {0x13u, 0x61u},
+ {0x14u, 0x10u},
+ {0x15u, 0x07u},
+ {0x16u, 0x0Cu},
+ {0x17u, 0xD8u},
+ {0x18u, 0x24u},
+ {0x1Au, 0x10u},
+ {0x1Bu, 0x40u},
+ {0x1Cu, 0x21u},
+ {0x1Eu, 0x1Eu},
+ {0x20u, 0x0Cu},
+ {0x21u, 0x01u},
+ {0x22u, 0x10u},
+ {0x24u, 0x14u},
+ {0x25u, 0x01u},
+ {0x26u, 0x08u},
+ {0x28u, 0x30u},
+ {0x29u, 0x10u},
+ {0x2Au, 0x0Fu},
+ {0x2Cu, 0x1Cu},
+ {0x2Du, 0x04u},
+ {0x30u, 0x40u},
+ {0x32u, 0x0Fu},
+ {0x34u, 0x30u},
+ {0x35u, 0xE0u},
+ {0x37u, 0x3Fu},
+ {0x38u, 0x02u},
+ {0x39u, 0x80u},
+ {0x3Au, 0x20u},
+ {0x3Fu, 0x40u},
+ {0x54u, 0x40u},
+ {0x56u, 0x04u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Fu, 0x01u},
+ {0x84u, 0x01u},
+ {0x85u, 0x44u},
+ {0x86u, 0x02u},
+ {0x87u, 0x88u},
+ {0x8Du, 0x99u},
+ {0x8Fu, 0x22u},
+ {0x90u, 0x02u},
+ {0x91u, 0xAAu},
+ {0x92u, 0x01u},
+ {0x93u, 0x55u},
+ {0x97u, 0x70u},
+ {0x9Cu, 0x02u},
+ {0x9Eu, 0x05u},
+ {0x9Fu, 0x07u},
+ {0xA3u, 0x08u},
+ {0xA4u, 0x02u},
+ {0xA6u, 0x09u},
+ {0xA8u, 0x02u},
+ {0xAAu, 0x01u},
+ {0xAFu, 0x80u},
+ {0xB0u, 0x04u},
+ {0xB3u, 0xF0u},
+ {0xB4u, 0x03u},
+ {0xB6u, 0x08u},
+ {0xB7u, 0x0Fu},
+ {0xBAu, 0x20u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDCu, 0x19u},
+ {0xDFu, 0x01u},
+ {0x00u, 0x04u},
+ {0x05u, 0x16u},
{0x07u, 0x02u},
- {0x0Fu, 0x01u},
- {0x15u, 0x01u},
- {0x17u, 0x02u},
- {0x1Cu, 0x01u},
- {0x28u, 0x01u},
- {0x2Cu, 0x01u},
- {0x31u, 0x03u},
+ {0x0Au, 0x82u},
+ {0x0Cu, 0x08u},
+ {0x0Du, 0x01u},
+ {0x0Eu, 0x0Au},
+ {0x10u, 0x10u},
+ {0x11u, 0x20u},
+ {0x15u, 0x08u},
+ {0x16u, 0x02u},
+ {0x17u, 0x21u},
+ {0x18u, 0x04u},
+ {0x1Au, 0x82u},
+ {0x1Bu, 0x01u},
+ {0x1Cu, 0x08u},
+ {0x1Du, 0x05u},
+ {0x1Eu, 0x28u},
+ {0x1Fu, 0x22u},
+ {0x21u, 0x88u},
+ {0x26u, 0x20u},
+ {0x27u, 0x02u},
+ {0x29u, 0x80u},
+ {0x2Au, 0x01u},
+ {0x2Eu, 0x01u},
+ {0x2Fu, 0x2Au},
+ {0x31u, 0x88u},
+ {0x32u, 0x02u},
+ {0x35u, 0x04u},
+ {0x36u, 0x21u},
+ {0x38u, 0x80u},
+ {0x3Bu, 0x04u},
+ {0x3Cu, 0x20u},
+ {0x3Du, 0x48u},
+ {0x3Eu, 0x02u},
+ {0x66u, 0x94u},
+ {0x67u, 0x40u},
+ {0x81u, 0x04u},
+ {0x85u, 0x80u},
+ {0x86u, 0x10u},
+ {0x8Bu, 0x04u},
+ {0x8Cu, 0x04u},
+ {0x90u, 0x80u},
+ {0x91u, 0x20u},
+ {0x93u, 0x01u},
+ {0x97u, 0x40u},
+ {0x98u, 0xB4u},
+ {0x9Au, 0x40u},
+ {0x9Du, 0x20u},
+ {0xA0u, 0x20u},
+ {0xA3u, 0x40u},
+ {0xA6u, 0x80u},
+ {0xA8u, 0x40u},
+ {0xABu, 0x40u},
+ {0xB0u, 0x20u},
+ {0xB2u, 0x40u},
+ {0xC0u, 0xF4u},
+ {0xC2u, 0xF9u},
+ {0xC4u, 0xF6u},
+ {0xCAu, 0xF9u},
+ {0xCCu, 0xEBu},
+ {0xCEu, 0xFAu},
+ {0xD8u, 0xF0u},
+ {0xE0u, 0x04u},
+ {0xE2u, 0x08u},
+ {0xE4u, 0x08u},
+ {0xEAu, 0x0Du},
+ {0xEEu, 0x01u},
+ {0x01u, 0x04u},
+ {0x02u, 0x01u},
+ {0x03u, 0x08u},
+ {0x05u, 0x02u},
+ {0x15u, 0x08u},
+ {0x17u, 0x04u},
+ {0x1Du, 0x18u},
+ {0x20u, 0x02u},
+ {0x25u, 0x04u},
+ {0x27u, 0x10u},
+ {0x2Du, 0x01u},
+ {0x30u, 0x02u},
+ {0x31u, 0x01u},
{0x32u, 0x01u},
- {0x38u, 0x08u},
- {0x3Eu, 0x04u},
- {0x3Fu, 0x01u},
- {0x54u, 0x01u},
+ {0x35u, 0x02u},
+ {0x37u, 0x1Cu},
+ {0x39u, 0x80u},
+ {0x3Eu, 0x01u},
+ {0x3Fu, 0x11u},
+ {0x40u, 0x24u},
+ {0x41u, 0x03u},
+ {0x42u, 0x50u},
+ {0x45u, 0xDEu},
+ {0x46u, 0x02u},
+ {0x47u, 0xCFu},
+ {0x48u, 0x37u},
+ {0x49u, 0xFFu},
+ {0x4Au, 0xFFu},
+ {0x4Bu, 0xFFu},
+ {0x4Fu, 0x2Cu},
+ {0x56u, 0x01u},
{0x58u, 0x04u},
{0x59u, 0x04u},
+ {0x5Au, 0x04u},
{0x5Bu, 0x04u},
- {0x5Du, 0x10u},
+ {0x5Cu, 0x09u},
+ {0x5Du, 0x01u},
{0x5Fu, 0x01u},
- {0x81u, 0x04u},
- {0x85u, 0x08u},
- {0x86u, 0x0Eu},
- {0x88u, 0x14u},
- {0x89u, 0x01u},
- {0x8Au, 0x0Au},
- {0x8Bu, 0x02u},
- {0x8Eu, 0x10u},
- {0x8Fu, 0x38u},
- {0x92u, 0x40u},
- {0x93u, 0x40u},
- {0x94u, 0x08u},
- {0x96u, 0x10u},
- {0x97u, 0x01u},
- {0x98u, 0x01u},
- {0x99u, 0x38u},
- {0x9Cu, 0x12u},
- {0x9Eu, 0x04u},
- {0x9Fu, 0x10u},
- {0xA0u, 0x01u},
- {0xA1u, 0x20u},
- {0xA4u, 0x20u},
- {0xA6u, 0x40u},
- {0xAAu, 0x20u},
- {0xABu, 0x02u},
+ {0x62u, 0xC0u},
+ {0x66u, 0x80u},
+ {0x68u, 0x40u},
+ {0x69u, 0x40u},
+ {0x6Eu, 0x08u},
+ {0x81u, 0x80u},
+ {0x8Bu, 0x07u},
+ {0x91u, 0x6Au},
+ {0x93u, 0x15u},
+ {0x95u, 0x19u},
+ {0x97u, 0x22u},
+ {0x99u, 0x14u},
+ {0x9Bu, 0x48u},
+ {0x9Fu, 0x08u},
+ {0xA3u, 0x20u},
+ {0xA7u, 0x70u},
+ {0xA8u, 0x02u},
{0xACu, 0x01u},
- {0xB1u, 0x04u},
- {0xB2u, 0x1Eu},
- {0xB3u, 0x38u},
- {0xB4u, 0x60u},
- {0xB5u, 0x40u},
- {0xB6u, 0x01u},
- {0xB7u, 0x03u},
- {0xBEu, 0x50u},
- {0xBFu, 0x44u},
- {0xD6u, 0x08u},
+ {0xB2u, 0x01u},
+ {0xB3u, 0x0Fu},
+ {0xB4u, 0x02u},
+ {0xB5u, 0x70u},
+ {0xB7u, 0x80u},
+ {0xBEu, 0x14u},
+ {0xBFu, 0x40u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
- {0xDBu, 0x04u},
- {0xDCu, 0x11u},
- {0xDDu, 0x90u},
+ {0xDCu, 0x10u},
{0xDFu, 0x01u},
- {0x01u, 0x28u},
- {0x02u, 0x02u},
- {0x04u, 0x04u},
- {0x08u, 0x40u},
- {0x09u, 0x04u},
- {0x0Au, 0x40u},
- {0x0Bu, 0x04u},
- {0x0Eu, 0x01u},
- {0x12u, 0x81u},
- {0x13u, 0x28u},
- {0x14u, 0x01u},
- {0x17u, 0x10u},
- {0x18u, 0x02u},
- {0x19u, 0x0Cu},
- {0x1Bu, 0x20u},
- {0x1Cu, 0x20u},
- {0x21u, 0x50u},
- {0x22u, 0x05u},
- {0x24u, 0x80u},
- {0x2Au, 0x11u},
- {0x2Bu, 0x80u},
- {0x31u, 0x14u},
- {0x32u, 0x81u},
+ {0x06u, 0x80u},
+ {0x09u, 0x02u},
+ {0x0Bu, 0x80u},
+ {0x12u, 0x05u},
+ {0x16u, 0x40u},
+ {0x18u, 0x10u},
+ {0x19u, 0x10u},
+ {0x1Du, 0x01u},
+ {0x1Eu, 0x20u},
+ {0x21u, 0x30u},
+ {0x23u, 0x16u},
+ {0x26u, 0x82u},
+ {0x27u, 0x08u},
+ {0x2Bu, 0x60u},
+ {0x2Eu, 0x08u},
+ {0x2Fu, 0x01u},
+ {0x31u, 0x2Au},
{0x33u, 0x40u},
- {0x37u, 0x08u},
- {0x38u, 0x40u},
- {0x3Au, 0x20u},
- {0x3Bu, 0x05u},
- {0x3Du, 0x80u},
- {0x3Eu, 0x04u},
- {0x5Au, 0x80u},
- {0x5Fu, 0x80u},
- {0x63u, 0x01u},
- {0x6Cu, 0x20u},
- {0x6Fu, 0x09u},
- {0x80u, 0x40u},
- {0x85u, 0x10u},
- {0x87u, 0x80u},
- {0x88u, 0x20u},
- {0x8Bu, 0x20u},
- {0x8Du, 0x10u},
- {0x8Eu, 0x10u},
- {0x8Fu, 0x08u},
- {0x92u, 0x80u},
- {0x93u, 0x40u},
- {0x95u, 0x20u},
- {0x9Fu, 0x01u},
- {0xA0u, 0x08u},
- {0xA8u, 0x08u},
- {0xADu, 0x10u},
- {0xB3u, 0x40u},
- {0xC0u, 0x27u},
- {0xC2u, 0x8Fu},
- {0xC4u, 0xCFu},
- {0xCAu, 0x05u},
- {0xCCu, 0x4Fu},
- {0xCEu, 0x5Fu},
- {0xD6u, 0x18u},
- {0xD8u, 0x08u},
- {0xE0u, 0x03u},
- {0xE2u, 0x18u},
- {0xE6u, 0x38u},
- {0xE8u, 0x02u},
- {0xEAu, 0x01u},
- {0x01u, 0x05u},
- {0x03u, 0x0Au},
- {0x04u, 0x05u},
- {0x06u, 0x0Au},
- {0x09u, 0xA0u},
- {0x0Bu, 0x4Fu},
- {0x0Du, 0x03u},
- {0x0Fu, 0x0Cu},
- {0x10u, 0x60u},
- {0x12u, 0x90u},
- {0x13u, 0x70u},
- {0x15u, 0x06u},
- {0x17u, 0x09u},
- {0x18u, 0x30u},
- {0x19u, 0x0Fu},
- {0x1Au, 0xC0u},
- {0x1Cu, 0x03u},
- {0x1Du, 0x90u},
- {0x1Eu, 0x0Cu},
- {0x1Fu, 0x2Fu},
- {0x21u, 0x80u},
- {0x24u, 0x50u},
- {0x26u, 0xA0u},
- {0x27u, 0x80u},
- {0x28u, 0x06u},
- {0x29u, 0xC0u},
- {0x2Au, 0x09u},
- {0x2Bu, 0x1Fu},
- {0x2Cu, 0x0Fu},
- {0x2Eu, 0xF0u},
- {0x30u, 0xFFu},
- {0x31u, 0x7Fu},
- {0x37u, 0x80u},
- {0x3Eu, 0x01u},
- {0x3Fu, 0x40u},
+ {0x34u, 0x40u},
+ {0x36u, 0x88u},
+ {0x3Bu, 0x11u},
+ {0x3Fu, 0x0Au},
+ {0x44u, 0x88u},
+ {0x45u, 0x2Au},
+ {0x49u, 0x80u},
+ {0x4Au, 0x02u},
+ {0x4Cu, 0x01u},
+ {0x4Du, 0x02u},
+ {0x4Eu, 0x20u},
+ {0x54u, 0x08u},
+ {0x56u, 0x02u},
+ {0x57u, 0x40u},
+ {0x5Cu, 0x10u},
+ {0x5Eu, 0x40u},
+ {0x5Fu, 0x0Au},
+ {0x65u, 0x95u},
+ {0x6Du, 0x02u},
+ {0x6Fu, 0x16u},
+ {0x74u, 0x60u},
+ {0x76u, 0x10u},
+ {0x77u, 0x40u},
+ {0x82u, 0x08u},
+ {0x87u, 0x03u},
+ {0x89u, 0x10u},
+ {0x8Eu, 0x20u},
+ {0x90u, 0xCCu},
+ {0x91u, 0x40u},
+ {0x92u, 0x10u},
+ {0x93u, 0x03u},
+ {0x96u, 0x20u},
+ {0x97u, 0x84u},
+ {0x9Au, 0x05u},
+ {0x9Cu, 0x92u},
+ {0x9Du, 0x40u},
+ {0x9Eu, 0xE2u},
+ {0x9Fu, 0x20u},
+ {0xA0u, 0x96u},
+ {0xA1u, 0x0Cu},
+ {0xA3u, 0x34u},
+ {0xA4u, 0x68u},
+ {0xA5u, 0x41u},
+ {0xA6u, 0x30u},
+ {0xA7u, 0x40u},
+ {0xA9u, 0x18u},
+ {0xAAu, 0x08u},
+ {0xACu, 0x40u},
+ {0xB1u, 0x08u},
+ {0xB2u, 0x40u},
+ {0xB3u, 0x09u},
+ {0xC0u, 0x10u},
+ {0xC4u, 0x13u},
+ {0xCAu, 0x53u},
+ {0xCCu, 0x5Fu},
+ {0xCEu, 0xC5u},
+ {0xD0u, 0xE0u},
+ {0xD2u, 0x10u},
+ {0xD6u, 0xF0u},
+ {0xD8u, 0xF0u},
+ {0xE4u, 0x40u},
+ {0xE6u, 0x20u},
+ {0xEAu, 0x08u},
+ {0xEEu, 0xADu},
+ {0x04u, 0x02u},
+ {0x05u, 0x01u},
+ {0x06u, 0x01u},
+ {0x07u, 0x02u},
+ {0x08u, 0x01u},
+ {0x09u, 0x02u},
+ {0x0Au, 0x02u},
+ {0x0Bu, 0x05u},
+ {0x14u, 0x02u},
+ {0x15u, 0x02u},
+ {0x16u, 0x05u},
+ {0x17u, 0x01u},
+ {0x1Cu, 0x02u},
+ {0x1Du, 0x02u},
+ {0x1Eu, 0x01u},
+ {0x1Fu, 0x01u},
+ {0x20u, 0x02u},
+ {0x21u, 0x02u},
+ {0x22u, 0x11u},
+ {0x23u, 0x09u},
+ {0x2Au, 0x08u},
+ {0x30u, 0x08u},
+ {0x32u, 0x03u},
+ {0x33u, 0x03u},
+ {0x34u, 0x10u},
+ {0x35u, 0x08u},
+ {0x36u, 0x04u},
+ {0x37u, 0x04u},
+ {0x3Au, 0x08u},
+ {0x3Bu, 0x08u},
+ {0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x10u},
+ {0x5Cu, 0x99u},
+ {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x81u, 0x03u},
- {0x83u, 0x0Cu},
- {0x85u, 0x09u},
- {0x87u, 0x06u},
- {0x89u, 0x50u},
- {0x8Au, 0xFFu},
- {0x8Bu, 0xA0u},
- {0x8Cu, 0xFFu},
- {0x8Du, 0x0Fu},
- {0x8Fu, 0xF0u},
- {0x90u, 0x05u},
- {0x92u, 0x0Au},
- {0x93u, 0xFFu},
- {0x94u, 0x50u},
- {0x95u, 0x90u},
- {0x96u, 0xA0u},
- {0x97u, 0x60u},
- {0x98u, 0x06u},
- {0x9Au, 0x09u},
- {0x9Bu, 0xFFu},
- {0x9Cu, 0x30u},
- {0x9Du, 0x05u},
- {0x9Eu, 0xC0u},
- {0x9Fu, 0x0Au},
- {0xA0u, 0x03u},
- {0xA1u, 0x30u},
- {0xA2u, 0x0Cu},
- {0xA3u, 0xC0u},
- {0xA6u, 0xFFu},
- {0xA7u, 0xFFu},
- {0xA8u, 0x60u},
- {0xAAu, 0x90u},
- {0xACu, 0x0Fu},
- {0xAEu, 0xF0u},
- {0xB3u, 0xFFu},
- {0xB6u, 0xFFu},
- {0xBEu, 0x40u},
- {0xBFu, 0x04u},
+ {0x80u, 0x80u},
+ {0x84u, 0x80u},
+ {0x85u, 0x44u},
+ {0x87u, 0x88u},
+ {0x88u, 0x07u},
+ {0x8Au, 0x28u},
+ {0x8Bu, 0x70u},
+ {0x8Cu, 0x80u},
+ {0x8Fu, 0x80u},
+ {0x92u, 0x02u},
+ {0x94u, 0x35u},
+ {0x96u, 0x4Au},
+ {0x9Au, 0x73u},
+ {0x9Bu, 0x07u},
+ {0x9Cu, 0x03u},
+ {0x9Eu, 0x0Cu},
+ {0xA0u, 0x46u},
+ {0xA1u, 0xAAu},
+ {0xA2u, 0x39u},
+ {0xA3u, 0x55u},
+ {0xA4u, 0x11u},
+ {0xA7u, 0x08u},
+ {0xA8u, 0x80u},
+ {0xA9u, 0x99u},
+ {0xABu, 0x22u},
+ {0xB0u, 0x80u},
+ {0xB2u, 0x70u},
+ {0xB3u, 0x0Fu},
+ {0xB5u, 0xF0u},
+ {0xB6u, 0x0Fu},
+ {0xB8u, 0x02u},
+ {0xBAu, 0x80u},
+ {0xBEu, 0x01u},
+ {0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
+ {0xDBu, 0x04u},
+ {0xDCu, 0x11u},
+ {0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x01u, 0x08u},
- {0x04u, 0x80u},
+ {0x00u, 0x04u},
+ {0x03u, 0x08u},
+ {0x04u, 0x02u},
+ {0x05u, 0x44u},
{0x06u, 0x08u},
- {0x09u, 0x40u},
- {0x0Au, 0x44u},
- {0x0Cu, 0x80u},
- {0x0Eu, 0x80u},
- {0x0Fu, 0x14u},
- {0x11u, 0x40u},
- {0x12u, 0x10u},
- {0x13u, 0x20u},
- {0x14u, 0x14u},
- {0x15u, 0x41u},
- {0x18u, 0x80u},
+ {0x0Au, 0x21u},
+ {0x0Eu, 0x1Au},
+ {0x0Fu, 0x80u},
+ {0x10u, 0x04u},
+ {0x12u, 0x80u},
+ {0x14u, 0x80u},
+ {0x15u, 0x04u},
+ {0x17u, 0x20u},
+ {0x18u, 0x04u},
{0x19u, 0x02u},
- {0x1Eu, 0x01u},
- {0x21u, 0x02u},
- {0x22u, 0x80u},
- {0x23u, 0x80u},
+ {0x1Au, 0x01u},
+ {0x1Bu, 0x08u},
+ {0x1Du, 0x08u},
+ {0x1Eu, 0x92u},
+ {0x21u, 0x14u},
+ {0x22u, 0x44u},
+ {0x25u, 0x10u},
+ {0x26u, 0x08u},
{0x27u, 0x10u},
- {0x29u, 0x04u},
- {0x2Au, 0x20u},
- {0x2Bu, 0x80u},
- {0x2Cu, 0x80u},
- {0x2Eu, 0x08u},
- {0x2Fu, 0x20u},
- {0x30u, 0x78u},
- {0x31u, 0x02u},
- {0x32u, 0x20u},
- {0x34u, 0x84u},
- {0x35u, 0x02u},
- {0x36u, 0x64u},
- {0x3Au, 0x01u},
- {0x3Bu, 0x60u},
- {0x3Du, 0x41u},
- {0x3Fu, 0x96u},
- {0x59u, 0x85u},
- {0x5Au, 0x10u},
- {0x62u, 0x80u},
- {0x80u, 0x80u},
- {0x83u, 0x40u},
- {0x84u, 0x40u},
- {0x86u, 0x02u},
- {0x8Eu, 0x01u},
- {0x8Fu, 0x80u},
- {0x92u, 0x10u},
- {0x93u, 0x40u},
- {0x94u, 0x44u},
- {0x96u, 0x45u},
- {0x99u, 0x08u},
- {0x9Bu, 0x20u},
- {0x9Cu, 0x41u},
- {0x9Du, 0x20u},
- {0x9Eu, 0x10u},
- {0x9Fu, 0xD0u},
- {0xA0u, 0x28u},
- {0xA3u, 0x40u},
- {0xA5u, 0x44u},
- {0xA6u, 0x02u},
- {0xA9u, 0x40u},
- {0xAEu, 0x04u},
- {0xAFu, 0x04u},
- {0xB0u, 0x10u},
- {0xB4u, 0x01u},
- {0xB6u, 0x20u},
- {0xB7u, 0x68u},
- {0xC0u, 0xC4u},
- {0xC2u, 0xFBu},
- {0xC4u, 0xF7u},
- {0xCAu, 0xC7u},
- {0xCCu, 0xFFu},
- {0xCEu, 0xFDu},
- {0xD6u, 0x0Fu},
- {0xD8u, 0x08u},
- {0xE2u, 0x0Eu},
- {0xE6u, 0x39u},
- {0xE8u, 0x01u},
- {0xEAu, 0x02u},
- {0x81u, 0x04u},
- {0x82u, 0x20u},
- {0x89u, 0x40u},
- {0x90u, 0x80u},
- {0x94u, 0x44u},
- {0x96u, 0x44u},
- {0x97u, 0x10u},
- {0x9Cu, 0x81u},
- {0x9Eu, 0x30u},
- {0xA5u, 0x44u},
- {0xA6u, 0x04u},
- {0xA7u, 0x20u},
+ {0x29u, 0x02u},
+ {0x2Cu, 0x20u},
+ {0x2Eu, 0x10u},
+ {0x2Fu, 0x40u},
+ {0x30u, 0x04u},
+ {0x32u, 0x40u},
+ {0x37u, 0x10u},
+ {0x39u, 0x28u},
+ {0x3Cu, 0x80u},
+ {0x3Du, 0x20u},
+ {0x3Eu, 0x08u},
+ {0x3Fu, 0x24u},
+ {0x58u, 0x41u},
+ {0x59u, 0x18u},
+ {0x5Eu, 0x40u},
+ {0x61u, 0x80u},
+ {0x62u, 0x05u},
+ {0x63u, 0x19u},
+ {0x67u, 0x02u},
+ {0x80u, 0x09u},
+ {0x88u, 0x01u},
+ {0x8Au, 0x20u},
+ {0x8Du, 0x04u},
+ {0x8Eu, 0x40u},
+ {0x90u, 0xC8u},
+ {0x91u, 0x44u},
+ {0x96u, 0x08u},
+ {0x97u, 0x96u},
+ {0x98u, 0x04u},
+ {0x9Bu, 0x09u},
+ {0x9Cu, 0x92u},
+ {0x9Eu, 0xEBu},
+ {0xA0u, 0x96u},
+ {0xA1u, 0x04u},
+ {0xA2u, 0x84u},
+ {0xA3u, 0x20u},
+ {0xA5u, 0xC9u},
+ {0xA6u, 0x19u},
+ {0xA7u, 0x0Cu},
{0xA9u, 0x80u},
- {0xADu, 0x20u},
+ {0xACu, 0x10u},
{0xAFu, 0x10u},
- {0xB3u, 0x05u},
- {0xB5u, 0x05u},
- {0xE2u, 0x04u},
- {0xE4u, 0x80u},
+ {0xB0u, 0x20u},
+ {0xB1u, 0x02u},
+ {0xB3u, 0x20u},
+ {0xB7u, 0x48u},
+ {0xC0u, 0xF6u},
+ {0xC2u, 0xF5u},
+ {0xC4u, 0x7Au},
+ {0xCAu, 0xE1u},
+ {0xCCu, 0x2Au},
+ {0xCEu, 0x76u},
+ {0xD6u, 0x1Fu},
+ {0xD8u, 0x1Fu},
+ {0xE0u, 0x10u},
+ {0xE2u, 0x2Cu},
{0xEAu, 0x04u},
- {0xEEu, 0x82u},
- {0x03u, 0x08u},
- {0x13u, 0x07u},
- {0x15u, 0x19u},
- {0x17u, 0x22u},
- {0x19u, 0x14u},
- {0x1Bu, 0x48u},
- {0x1Du, 0x80u},
- {0x21u, 0x6Au},
- {0x23u, 0x15u},
- {0x24u, 0x02u},
- {0x27u, 0x20u},
- {0x28u, 0x01u},
- {0x2Fu, 0x70u},
- {0x32u, 0x02u},
- {0x33u, 0x70u},
- {0x34u, 0x01u},
- {0x35u, 0x80u},
- {0x37u, 0x0Fu},
- {0x3Eu, 0x14u},
- {0x3Fu, 0x10u},
- {0x58u, 0x04u},
- {0x59u, 0x04u},
- {0x5Cu, 0x10u},
- {0x5Fu, 0x01u},
- {0x00u, 0xA0u},
- {0x01u, 0x01u},
- {0x0Au, 0xAAu},
- {0x11u, 0x40u},
- {0x12u, 0x60u},
- {0x13u, 0x02u},
- {0x14u, 0x28u},
- {0x17u, 0x08u},
- {0x19u, 0x02u},
- {0x1Cu, 0x10u},
- {0x1Fu, 0x10u},
- {0x20u, 0x04u},
- {0x21u, 0x10u},
- {0x22u, 0x15u},
- {0x23u, 0x10u},
- {0x27u, 0x15u},
- {0x29u, 0x20u},
- {0x2Au, 0x40u},
- {0x2Bu, 0x08u},
- {0x2Cu, 0x40u},
- {0x2Du, 0x88u},
- {0x2Fu, 0x40u},
- {0x32u, 0x55u},
- {0x34u, 0x80u},
- {0x35u, 0x04u},
- {0x37u, 0x11u},
- {0x39u, 0x55u},
- {0x3Cu, 0x02u},
- {0x40u, 0x40u},
- {0x41u, 0x14u},
- {0x46u, 0x20u},
- {0x47u, 0x04u},
- {0x48u, 0x40u},
- {0x49u, 0x41u},
- {0x4Bu, 0x14u},
- {0x52u, 0x11u},
- {0x53u, 0x0Cu},
- {0x62u, 0x08u},
- {0x68u, 0x1Cu},
- {0x69u, 0x55u},
- {0x73u, 0x02u},
- {0x83u, 0x10u},
- {0x89u, 0x04u},
- {0x8Bu, 0x01u},
- {0x90u, 0x08u},
- {0x92u, 0x04u},
- {0x93u, 0x82u},
- {0x94u, 0x10u},
- {0x95u, 0x65u},
- {0x96u, 0xEAu},
- {0x97u, 0x20u},
- {0x98u, 0x12u},
- {0x99u, 0x8Cu},
- {0x9Au, 0x82u},
- {0x9Cu, 0x88u},
- {0x9Du, 0x02u},
- {0x9Eu, 0x20u},
- {0x9Fu, 0x1Au},
- {0xA0u, 0x81u},
- {0xA1u, 0x08u},
- {0xA2u, 0x30u},
- {0xA4u, 0x54u},
- {0xA5u, 0x04u},
- {0xA6u, 0x02u},
- {0xA7u, 0x01u},
- {0xA9u, 0x20u},
- {0xADu, 0x80u},
- {0xB2u, 0x15u},
- {0xB6u, 0x09u},
- {0xC0u, 0x0Bu},
- {0xC2u, 0x0Fu},
- {0xC4u, 0x6Du},
- {0xCAu, 0xDCu},
- {0xCCu, 0xFFu},
- {0xCEu, 0x8Fu},
- {0xD0u, 0x07u},
- {0xD2u, 0x0Cu},
- {0xD8u, 0x02u},
- {0xE4u, 0x80u},
- {0xE6u, 0x20u},
- {0xEAu, 0x90u},
- {0xEEu, 0xE0u},
- {0x00u, 0xC0u},
- {0x02u, 0x02u},
- {0x04u, 0xC0u},
- {0x06u, 0x08u},
- {0x08u, 0xC0u},
- {0x0Au, 0x04u},
- {0x0Eu, 0x9Fu},
- {0x11u, 0x01u},
- {0x12u, 0xFFu},
- {0x14u, 0x1Fu},
- {0x16u, 0x20u},
- {0x18u, 0x7Fu},
- {0x1Au, 0x80u},
- {0x1Cu, 0x80u},
- {0x20u, 0xC0u},
- {0x21u, 0x02u},
- {0x22u, 0x01u},
- {0x26u, 0x60u},
- {0x29u, 0x02u},
- {0x2Cu, 0x90u},
- {0x2Du, 0x04u},
- {0x2Eu, 0x40u},
- {0x31u, 0x01u},
- {0x34u, 0xFFu},
- {0x35u, 0x02u},
- {0x37u, 0x04u},
- {0x39u, 0x20u},
- {0x3Eu, 0x10u},
- {0x3Fu, 0x41u},
+ {0xEEu, 0x20u},
+ {0x00u, 0x96u},
+ {0x02u, 0x69u},
+ {0x04u, 0xFFu},
+ {0x0Au, 0xFFu},
+ {0x10u, 0x0Fu},
+ {0x12u, 0xF0u},
+ {0x16u, 0xFFu},
+ {0x1Au, 0xFFu},
+ {0x1Bu, 0x01u},
+ {0x1Cu, 0x33u},
+ {0x1Eu, 0xCCu},
+ {0x20u, 0xFFu},
+ {0x24u, 0x55u},
+ {0x26u, 0xAAu},
+ {0x30u, 0xFFu},
+ {0x33u, 0x01u},
+ {0x3Au, 0x02u},
+ {0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x91u},
+ {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x80u, 0x01u},
- {0x86u, 0x58u},
- {0x89u, 0x01u},
- {0x8Eu, 0xFEu},
- {0x94u, 0x76u},
- {0x96u, 0x80u},
- {0x98u, 0x06u},
- {0x9Au, 0x08u},
- {0x9Cu, 0x9Eu},
- {0x9Eu, 0x60u},
- {0xA0u, 0x20u},
- {0xA2u, 0x02u},
- {0xA8u, 0x06u},
- {0xACu, 0x04u},
- {0xB0u, 0x01u},
- {0xB2u, 0xE0u},
- {0xB5u, 0x01u},
- {0xB6u, 0x1Eu},
- {0xBEu, 0x01u},
- {0xBFu, 0x10u},
- {0xC0u, 0x21u},
- {0xC1u, 0x03u},
- {0xC2u, 0x60u},
- {0xC5u, 0xF2u},
- {0xC6u, 0xE0u},
- {0xC7u, 0xDCu},
- {0xC8u, 0x3Bu},
- {0xC9u, 0xFFu},
- {0xCAu, 0xFFu},
- {0xCBu, 0xFFu},
- {0xCFu, 0x2Cu},
- {0xD6u, 0x01u},
+ {0x84u, 0x01u},
+ {0x86u, 0x02u},
+ {0x87u, 0xFFu},
+ {0x89u, 0xFFu},
+ {0x8Du, 0xFFu},
+ {0x90u, 0x02u},
+ {0x91u, 0x0Fu},
+ {0x92u, 0x09u},
+ {0x93u, 0xF0u},
+ {0x94u, 0x02u},
+ {0x96u, 0x01u},
+ {0x97u, 0xFFu},
+ {0x9Cu, 0x02u},
+ {0x9Eu, 0x11u},
+ {0xA1u, 0x55u},
+ {0xA3u, 0xAAu},
+ {0xA4u, 0x02u},
+ {0xA6u, 0x05u},
+ {0xA7u, 0xFFu},
+ {0xA9u, 0x69u},
+ {0xABu, 0x96u},
+ {0xADu, 0x33u},
+ {0xAFu, 0xCCu},
+ {0xB0u, 0x04u},
+ {0xB1u, 0xFFu},
+ {0xB2u, 0x10u},
+ {0xB4u, 0x03u},
+ {0xB6u, 0x08u},
+ {0xBAu, 0x20u},
+ {0xBBu, 0x02u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
- {0xDAu, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x01u},
- {0xDDu, 0x01u},
+ {0xDCu, 0x19u},
{0xDFu, 0x01u},
- {0xE2u, 0xC0u},
- {0xE6u, 0x80u},
- {0xE8u, 0x40u},
- {0xE9u, 0x40u},
- {0xEEu, 0x08u},
- {0x00u, 0xA8u},
- {0x01u, 0x01u},
- {0x03u, 0x20u},
- {0x05u, 0x80u},
- {0x06u, 0x40u},
- {0x07u, 0x10u},
- {0x08u, 0x01u},
- {0x0Au, 0xAAu},
+ {0x00u, 0x04u},
+ {0x06u, 0x68u},
+ {0x0Au, 0xA1u},
+ {0x0Cu, 0x01u},
{0x0Du, 0x08u},
- {0x0Eu, 0x0Au},
- {0x10u, 0x40u},
- {0x11u, 0x40u},
- {0x12u, 0x20u},
- {0x13u, 0x02u},
- {0x16u, 0x89u},
- {0x17u, 0x01u},
- {0x19u, 0x20u},
- {0x1Cu, 0x40u},
- {0x1Du, 0x8Cu},
- {0x1Eu, 0x02u},
- {0x1Fu, 0x4Cu},
- {0x22u, 0x20u},
- {0x23u, 0x41u},
- {0x24u, 0x04u},
- {0x29u, 0x62u},
- {0x31u, 0x01u},
- {0x3Fu, 0x10u},
- {0x45u, 0x88u},
- {0x47u, 0x10u},
- {0x4Cu, 0x40u},
- {0x4Du, 0x18u},
- {0x4Fu, 0x04u},
- {0x55u, 0x20u},
- {0x56u, 0x09u},
- {0x5Cu, 0x55u},
- {0x66u, 0x20u},
- {0x67u, 0x61u},
- {0x6Cu, 0x95u},
- {0x74u, 0x29u},
- {0x76u, 0x02u},
- {0x81u, 0x04u},
- {0x82u, 0x40u},
- {0x84u, 0x08u},
- {0x87u, 0x04u},
- {0x8Eu, 0x06u},
- {0x8Fu, 0x02u},
- {0x90u, 0x01u},
- {0x91u, 0x10u},
- {0x92u, 0x05u},
- {0x93u, 0x12u},
- {0x94u, 0xA2u},
- {0x95u, 0x65u},
- {0x96u, 0x48u},
- {0x97u, 0x84u},
- {0x98u, 0x12u},
- {0x99u, 0xC1u},
- {0x9Au, 0x40u},
- {0x9Bu, 0x01u},
- {0x9Cu, 0xC9u},
- {0x9Du, 0x04u},
- {0x9Fu, 0x18u},
- {0xA2u, 0x14u},
- {0xA3u, 0x02u},
- {0xA4u, 0x20u},
- {0xA5u, 0x2Cu},
- {0xA6u, 0x01u},
- {0xA7u, 0x29u},
- {0xADu, 0x10u},
- {0xB0u, 0x10u},
- {0xB4u, 0x02u},
- {0xB6u, 0x42u},
- {0xB7u, 0x01u},
- {0xC0u, 0xBFu},
- {0xC2u, 0xEFu},
- {0xC4u, 0xDDu},
- {0xCAu, 0x0Du},
- {0xCCu, 0x01u},
- {0xCEu, 0x20u},
- {0xD0u, 0x70u},
- {0xD2u, 0x20u},
- {0xD6u, 0xF0u},
- {0xD8u, 0xF0u},
- {0xE2u, 0x48u},
- {0xE6u, 0x70u},
- {0xE8u, 0x41u},
- {0xECu, 0x80u},
- {0xEEu, 0x50u},
- {0x02u, 0x08u},
- {0x04u, 0x99u},
- {0x05u, 0x20u},
- {0x06u, 0x22u},
- {0x0Au, 0x80u},
+ {0x0Eu, 0x88u},
{0x0Fu, 0x01u},
- {0x13u, 0x0Eu},
- {0x16u, 0x70u},
- {0x19u, 0x08u},
- {0x1Au, 0x07u},
- {0x1Bu, 0x10u},
- {0x1Cu, 0xAAu},
- {0x1Eu, 0x55u},
- {0x21u, 0x14u},
- {0x23u, 0x0Au},
+ {0x12u, 0x10u},
+ {0x14u, 0x90u},
+ {0x18u, 0x04u},
+ {0x19u, 0x20u},
+ {0x1Au, 0xA1u},
+ {0x1Eu, 0x80u},
+ {0x20u, 0x80u},
+ {0x21u, 0x02u},
{0x27u, 0x10u},
- {0x28u, 0x44u},
- {0x29u, 0x12u},
- {0x2Au, 0x88u},
- {0x2Bu, 0x04u},
- {0x31u, 0x1Eu},
- {0x32u, 0xF0u},
+ {0x28u, 0x02u},
+ {0x2Au, 0x01u},
+ {0x2Bu, 0x24u},
+ {0x31u, 0x0Au},
+ {0x36u, 0x10u},
+ {0x39u, 0x10u},
+ {0x3Au, 0x20u},
+ {0x3Bu, 0x84u},
+ {0x59u, 0x22u},
+ {0x5Au, 0x08u},
+ {0x5Bu, 0x40u},
+ {0x5Du, 0x80u},
+ {0x5Eu, 0x04u},
+ {0x5Fu, 0x20u},
+ {0x63u, 0x02u},
+ {0x64u, 0x04u},
+ {0x67u, 0x21u},
+ {0x68u, 0x90u},
+ {0x6Bu, 0x09u},
+ {0x70u, 0x66u},
+ {0x82u, 0x01u},
+ {0x85u, 0x10u},
+ {0x87u, 0x01u},
+ {0x8Au, 0x04u},
+ {0x8Du, 0x44u},
+ {0x8Fu, 0x20u},
+ {0x90u, 0x40u},
+ {0x91u, 0x04u},
+ {0x97u, 0x16u},
+ {0x9Au, 0x10u},
+ {0x9Cu, 0x81u},
+ {0x9Eu, 0xA2u},
+ {0x9Fu, 0x10u},
+ {0xA0u, 0x04u},
+ {0xA1u, 0x04u},
+ {0xA2u, 0x84u},
+ {0xA3u, 0x20u},
+ {0xA4u, 0xE0u},
+ {0xA5u, 0xC9u},
+ {0xA6u, 0x18u},
+ {0xA8u, 0x10u},
+ {0xAAu, 0x40u},
+ {0xADu, 0x10u},
+ {0xC0u, 0x74u},
+ {0xC2u, 0xFDu},
+ {0xC4u, 0x34u},
+ {0xCAu, 0x0Fu},
+ {0xCCu, 0x23u},
+ {0xCEu, 0x0Eu},
+ {0xD6u, 0x7Fu},
+ {0xD8u, 0x78u},
+ {0xE0u, 0x40u},
+ {0xE4u, 0x10u},
+ {0xE6u, 0x40u},
+ {0xECu, 0x01u},
+ {0x01u, 0x55u},
+ {0x03u, 0xAAu},
+ {0x06u, 0x17u},
+ {0x07u, 0xFFu},
+ {0x09u, 0x69u},
+ {0x0Bu, 0x96u},
+ {0x0Du, 0x0Fu},
+ {0x0Fu, 0xF0u},
+ {0x12u, 0x08u},
+ {0x14u, 0x09u},
+ {0x16u, 0x02u},
+ {0x17u, 0xFFu},
+ {0x18u, 0x04u},
+ {0x1Au, 0x08u},
+ {0x1Cu, 0x0Au},
+ {0x1Du, 0x33u},
+ {0x1Eu, 0x05u},
+ {0x1Fu, 0xCCu},
+ {0x21u, 0xFFu},
+ {0x22u, 0x20u},
+ {0x26u, 0x80u},
+ {0x27u, 0xFFu},
+ {0x29u, 0xFFu},
+ {0x2Au, 0x40u},
+ {0x2Cu, 0x50u},
+ {0x2Eu, 0xA0u},
+ {0x30u, 0x30u},
+ {0x32u, 0xC0u},
{0x34u, 0x0Fu},
- {0x35u, 0x01u},
- {0x37u, 0x20u},
- {0x3Fu, 0x40u},
+ {0x37u, 0xFFu},
+ {0x3Bu, 0x80u},
+ {0x3Eu, 0x05u},
+ {0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
+ {0x5Bu, 0x04u},
{0x5Cu, 0x11u},
+ {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x80u, 0x55u},
- {0x81u, 0x0Du},
- {0x82u, 0xAAu},
- {0x85u, 0x0Du},
- {0x86u, 0xFFu},
- {0x89u, 0x11u},
- {0x8Au, 0xFFu},
- {0x8Bu, 0x22u},
- {0x8Du, 0x0Du},
- {0x8Eu, 0xFFu},
- {0x90u, 0xFFu},
- {0x95u, 0x22u},
- {0x97u, 0x18u},
- {0x99u, 0x60u},
- {0x9Cu, 0x69u},
- {0x9Du, 0x02u},
- {0x9Eu, 0x96u},
- {0x9Fu, 0x0Du},
- {0xA1u, 0x0Du},
- {0xA4u, 0x33u},
- {0xA5u, 0x0Du},
- {0xA6u, 0xCCu},
- {0xAAu, 0xFFu},
- {0xACu, 0x0Fu},
- {0xADu, 0x12u},
- {0xAEu, 0xF0u},
- {0xAFu, 0x44u},
- {0xB0u, 0xFFu},
- {0xB5u, 0x70u},
- {0xB7u, 0x0Fu},
- {0xB8u, 0x80u},
- {0xB9u, 0x20u},
- {0xBAu, 0x02u},
- {0xBBu, 0x80u},
- {0xBEu, 0x40u},
- {0xD6u, 0x08u},
+ {0x80u, 0x02u},
+ {0x82u, 0x01u},
+ {0x83u, 0x80u},
+ {0x85u, 0xC0u},
+ {0x87u, 0x1Fu},
+ {0x8Bu, 0x80u},
+ {0x8Cu, 0x02u},
+ {0x8Du, 0x03u},
+ {0x8Eu, 0x01u},
+ {0x8Fu, 0x0Cu},
+ {0x93u, 0x70u},
+ {0x94u, 0x02u},
+ {0x96u, 0x01u},
+ {0x98u, 0x09u},
+ {0x9Au, 0x02u},
+ {0x9Du, 0xA0u},
+ {0x9Fu, 0x4Fu},
+ {0xA1u, 0x05u},
+ {0xA3u, 0x0Au},
+ {0xA5u, 0x0Fu},
+ {0xA8u, 0x02u},
+ {0xA9u, 0x90u},
+ {0xAAu, 0x05u},
+ {0xABu, 0x2Fu},
+ {0xADu, 0x06u},
+ {0xAFu, 0x09u},
+ {0xB0u, 0x08u},
+ {0xB1u, 0x7Fu},
+ {0xB4u, 0x03u},
+ {0xB6u, 0x04u},
+ {0xB7u, 0x80u},
+ {0xBAu, 0x20u},
+ {0xBFu, 0x40u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x01u},
- {0xDDu, 0x90u},
+ {0xDCu, 0x19u},
{0xDFu, 0x01u},
- {0x01u, 0x80u},
- {0x02u, 0x80u},
- {0x03u, 0x18u},
- {0x04u, 0x22u},
- {0x05u, 0x04u},
+ {0x00u, 0x0Cu},
+ {0x05u, 0x40u},
+ {0x06u, 0x80u},
{0x08u, 0x80u},
- {0x0Bu, 0x80u},
- {0x0Eu, 0x26u},
- {0x10u, 0x02u},
- {0x12u, 0x18u},
+ {0x09u, 0x09u},
+ {0x0Bu, 0x04u},
+ {0x0Eu, 0x28u},
+ {0x10u, 0xA0u},
+ {0x11u, 0x80u},
+ {0x12u, 0x08u},
{0x17u, 0x10u},
- {0x1Au, 0x01u},
- {0x1Bu, 0x02u},
- {0x1Eu, 0x24u},
- {0x1Fu, 0x04u},
- {0x22u, 0x50u},
- {0x24u, 0x01u},
- {0x25u, 0x10u},
+ {0x18u, 0x14u},
+ {0x1Au, 0x80u},
+ {0x1Du, 0x40u},
+ {0x1Eu, 0x08u},
+ {0x1Fu, 0x22u},
+ {0x21u, 0x40u},
+ {0x24u, 0x41u},
{0x26u, 0x02u},
- {0x28u, 0x41u},
+ {0x28u, 0x80u},
+ {0x2Au, 0x20u},
{0x2Bu, 0x20u},
- {0x2Cu, 0x22u},
- {0x2Fu, 0x4Au},
- {0x32u, 0x54u},
+ {0x2Cu, 0x09u},
+ {0x2Du, 0x04u},
+ {0x2Fu, 0x40u},
+ {0x30u, 0x08u},
+ {0x31u, 0x88u},
+ {0x34u, 0x80u},
{0x36u, 0x02u},
- {0x37u, 0x10u},
- {0x39u, 0x65u},
- {0x3Cu, 0x04u},
- {0x3Du, 0x80u},
- {0x58u, 0x04u},
- {0x59u, 0x12u},
- {0x5Bu, 0x40u},
- {0x60u, 0x04u},
- {0x61u, 0x01u},
- {0x62u, 0x50u},
- {0x63u, 0x10u},
- {0x80u, 0x80u},
- {0x81u, 0x02u},
- {0x83u, 0x50u},
- {0x85u, 0x60u},
- {0x86u, 0x04u},
- {0x8Bu, 0x01u},
- {0x8Cu, 0x40u},
- {0x8Eu, 0x10u},
- {0x91u, 0x10u},
- {0x96u, 0x40u},
- {0x97u, 0x1Cu},
- {0x98u, 0x04u},
- {0x99u, 0xD0u},
- {0x9Cu, 0x08u},
- {0x9Du, 0x01u},
- {0x9Eu, 0x40u},
- {0x9Fu, 0x19u},
- {0xA2u, 0x8Cu},
- {0xA4u, 0x80u},
- {0xA5u, 0x1Cu},
- {0xA6u, 0x01u},
- {0xA7u, 0x01u},
- {0xA9u, 0x40u},
- {0xABu, 0x40u},
- {0xACu, 0x20u},
- {0xB1u, 0x20u},
- {0xB7u, 0x02u},
- {0xC0u, 0x7Fu},
- {0xC2u, 0xE9u},
- {0xC4u, 0x47u},
- {0xCAu, 0xEBu},
- {0xCCu, 0xAEu},
- {0xCEu, 0x5Fu},
- {0xD6u, 0x0Fu},
- {0xD8u, 0x0Fu},
- {0xE0u, 0x81u},
- {0xE2u, 0x40u},
- {0xE4u, 0x20u},
- {0xE6u, 0x15u},
- {0xEAu, 0x20u},
- {0xEEu, 0x01u},
- {0x03u, 0xFFu},
+ {0x39u, 0x80u},
+ {0x3Bu, 0x96u},
+ {0x3Cu, 0x80u},
+ {0x3Eu, 0x22u},
+ {0x3Fu, 0x04u},
+ {0x58u, 0x50u},
+ {0x62u, 0x90u},
+ {0x6Du, 0x1Cu},
+ {0x6Eu, 0x40u},
+ {0x82u, 0x40u},
+ {0x88u, 0x50u},
+ {0x8Bu, 0x02u},
+ {0x8Cu, 0x01u},
+ {0xC0u, 0x94u},
+ {0xC2u, 0x6Fu},
+ {0xC4u, 0x4Fu},
+ {0xCAu, 0xF7u},
+ {0xCCu, 0x9Au},
+ {0xCEu, 0xFFu},
+ {0xD6u, 0x0Cu},
+ {0xD8u, 0x0Cu},
+ {0xE4u, 0x01u},
+ {0xE6u, 0x90u},
+ {0x00u, 0x05u},
+ {0x02u, 0x0Au},
+ {0x05u, 0x05u},
{0x06u, 0xFFu},
- {0x0Au, 0xFFu},
- {0x0Du, 0x0Fu},
- {0x0Eu, 0xFFu},
- {0x0Fu, 0xF0u},
- {0x11u, 0xFFu},
- {0x16u, 0xFFu},
- {0x17u, 0xFFu},
- {0x18u, 0x0Fu},
- {0x1Au, 0xF0u},
- {0x1Bu, 0xFFu},
- {0x20u, 0x33u},
- {0x21u, 0x96u},
- {0x22u, 0xCCu},
- {0x23u, 0x69u},
- {0x24u, 0x55u},
- {0x26u, 0xAAu},
+ {0x07u, 0x0Au},
+ {0x08u, 0xFFu},
+ {0x0Bu, 0xFFu},
+ {0x0Cu, 0x50u},
+ {0x0Du, 0x50u},
+ {0x0Eu, 0xA0u},
+ {0x0Fu, 0xA0u},
+ {0x10u, 0x0Fu},
+ {0x11u, 0x0Fu},
+ {0x12u, 0xF0u},
+ {0x13u, 0xF0u},
+ {0x14u, 0x06u},
+ {0x15u, 0x09u},
+ {0x16u, 0x09u},
+ {0x17u, 0x06u},
+ {0x19u, 0x90u},
+ {0x1Bu, 0x60u},
+ {0x1Cu, 0x03u},
+ {0x1Du, 0x03u},
+ {0x1Eu, 0x0Cu},
+ {0x1Fu, 0x0Cu},
+ {0x22u, 0xFFu},
+ {0x23u, 0xFFu},
+ {0x24u, 0x60u},
+ {0x26u, 0x90u},
{0x27u, 0xFFu},
- {0x28u, 0x69u},
- {0x29u, 0x55u},
- {0x2Au, 0x96u},
- {0x2Bu, 0xAAu},
- {0x2Cu, 0xFFu},
- {0x2Du, 0x33u},
- {0x2Fu, 0xCCu},
+ {0x28u, 0x30u},
+ {0x29u, 0x30u},
+ {0x2Au, 0xC0u},
+ {0x2Bu, 0xC0u},
{0x34u, 0xFFu},
{0x37u, 0xFFu},
- {0x3Au, 0x20u},
- {0x3Bu, 0x80u},
- {0x56u, 0x08u},
+ {0x3Eu, 0x10u},
+ {0x3Fu, 0x40u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x11u},
- {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x83u, 0x02u},
- {0x87u, 0x80u},
- {0x89u, 0x30u},
- {0x8Bu, 0x01u},
- {0x8Du, 0x30u},
- {0x8Eu, 0x03u},
- {0x90u, 0x03u},
- {0x91u, 0x06u},
- {0x92u, 0x0Cu},
- {0x93u, 0x08u},
- {0x94u, 0x05u},
- {0x95u, 0x10u},
- {0x96u, 0x0Au},
- {0x97u, 0x22u},
- {0x99u, 0x02u},
- {0x9Au, 0x02u},
- {0x9Bu, 0x0Cu},
- {0x9Cu, 0x06u},
- {0x9Du, 0x04u},
- {0x9Eu, 0x09u},
- {0x9Fu, 0x0Au},
- {0xA0u, 0x01u},
- {0xA1u, 0x04u},
- {0xA3u, 0x0Au},
- {0xA5u, 0x20u},
- {0xA7u, 0x10u},
- {0xA8u, 0x07u},
- {0xAAu, 0x08u},
- {0xABu, 0x40u},
- {0xADu, 0x40u},
- {0xAFu, 0x80u},
- {0xB0u, 0x0Fu},
- {0xB1u, 0x01u},
- {0xB3u, 0x30u},
- {0xB5u, 0x0Eu},
- {0xB7u, 0xC0u},
- {0xBAu, 0x02u},
- {0xBBu, 0x28u},
+ {0x83u, 0x01u},
+ {0x85u, 0x02u},
+ {0x8Du, 0x02u},
+ {0x93u, 0x02u},
+ {0x95u, 0x02u},
+ {0xA1u, 0x02u},
+ {0xB5u, 0x01u},
+ {0xB7u, 0x02u},
{0xBFu, 0x40u},
- {0xD6u, 0x08u},
- {0xD8u, 0x04u},
+ {0xC0u, 0x16u},
+ {0xC1u, 0x02u},
+ {0xC2u, 0x40u},
+ {0xC4u, 0x05u},
+ {0xC5u, 0xCEu},
+ {0xC6u, 0xFBu},
+ {0xC7u, 0xDBu},
+ {0xC8u, 0x3Fu},
+ {0xC9u, 0xFFu},
+ {0xCAu, 0xFFu},
+ {0xCBu, 0xFFu},
+ {0xCCu, 0x22u},
+ {0xCEu, 0xF0u},
+ {0xCFu, 0x08u},
+ {0xD0u, 0x04u},
+ {0xD4u, 0x09u},
+ {0xD6u, 0x04u},
{0xD9u, 0x04u},
+ {0xDAu, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x11u},
- {0xDDu, 0x90u},
+ {0xDCu, 0x90u},
{0xDFu, 0x01u},
- {0x01u, 0x80u},
- {0x02u, 0x08u},
- {0x03u, 0x10u},
- {0x05u, 0x80u},
- {0x09u, 0x08u},
- {0x0Au, 0x04u},
- {0x0Du, 0x08u},
- {0x0Eu, 0x82u},
- {0x0Fu, 0x24u},
- {0x10u, 0x01u},
- {0x12u, 0x40u},
- {0x13u, 0x18u},
- {0x17u, 0x11u},
+ {0xE2u, 0xC0u},
+ {0xE4u, 0x40u},
+ {0xE5u, 0x01u},
+ {0xE6u, 0x10u},
+ {0xE7u, 0x11u},
+ {0xE8u, 0xC0u},
+ {0xE9u, 0x01u},
+ {0xEBu, 0x11u},
+ {0xECu, 0x40u},
+ {0xEDu, 0x01u},
+ {0xEEu, 0x40u},
+ {0xEFu, 0x01u},
+ {0x00u, 0x52u},
+ {0x03u, 0x20u},
+ {0x09u, 0x8Au},
+ {0x10u, 0x64u},
{0x19u, 0x20u},
- {0x1Au, 0x04u},
- {0x1Eu, 0x80u},
- {0x21u, 0x40u},
- {0x24u, 0x48u},
- {0x26u, 0x2Cu},
+ {0x22u, 0x80u},
+ {0x25u, 0x10u},
{0x27u, 0x02u},
- {0x28u, 0x08u},
- {0x29u, 0x01u},
- {0x2Bu, 0x11u},
- {0x2Cu, 0xA0u},
- {0x2Eu, 0x40u},
- {0x2Fu, 0x04u},
- {0x30u, 0x01u},
- {0x32u, 0x08u},
- {0x33u, 0x10u},
- {0x34u, 0x01u},
- {0x36u, 0x29u},
- {0x37u, 0x80u},
- {0x39u, 0x80u},
- {0x3Bu, 0x01u},
- {0x3Cu, 0x40u},
- {0x3Du, 0x28u},
- {0x3Fu, 0x01u},
- {0x4Cu, 0x04u},
- {0x4Du, 0x10u},
- {0x5Bu, 0x40u},
- {0x5Du, 0x40u},
- {0x61u, 0x40u},
- {0x62u, 0x80u},
- {0x65u, 0x80u},
- {0x67u, 0x01u},
- {0x81u, 0x40u},
- {0x86u, 0x40u},
- {0x88u, 0x04u},
- {0x89u, 0x08u},
- {0x8Bu, 0x80u},
- {0x8Du, 0x10u},
- {0xC0u, 0x87u},
- {0xC2u, 0xF6u},
- {0xC4u, 0x5Fu},
- {0xCAu, 0xFFu},
- {0xCCu, 0xF7u},
- {0xCEu, 0xF9u},
- {0xD6u, 0x18u},
- {0xD8u, 0x18u},
- {0xE2u, 0x10u},
- {0x86u, 0x04u},
- {0x8Au, 0x10u},
- {0x96u, 0x04u},
- {0x9Eu, 0x10u},
- {0xA8u, 0xC0u},
- {0xB3u, 0x30u},
- {0xB6u, 0x44u},
- {0xE2u, 0x06u},
- {0xE6u, 0x01u},
- {0xE8u, 0x01u},
- {0xEEu, 0x01u},
- {0x80u, 0x40u},
+ {0x28u, 0x54u},
+ {0x2Bu, 0x20u},
+ {0x2Eu, 0x02u},
+ {0x30u, 0x20u},
+ {0x31u, 0x8Au},
+ {0x37u, 0x05u},
+ {0x38u, 0x50u},
+ {0x3Au, 0x60u},
+ {0x3Bu, 0x18u},
+ {0x3Cu, 0x80u},
+ {0x3Eu, 0x04u},
+ {0x3Fu, 0x02u},
+ {0x47u, 0x92u},
+ {0x4Du, 0x06u},
+ {0x4Eu, 0x08u},
+ {0x4Fu, 0x80u},
+ {0x55u, 0x40u},
+ {0x56u, 0x18u},
+ {0x57u, 0x0Au},
+ {0x58u, 0xA9u},
+ {0x5Du, 0x14u},
+ {0x5Eu, 0x80u},
+ {0x5Fu, 0x02u},
+ {0x63u, 0x01u},
+ {0x66u, 0x01u},
+ {0x67u, 0x02u},
+ {0x82u, 0x10u},
+ {0x83u, 0x40u},
{0x84u, 0x01u},
- {0x90u, 0x80u},
- {0x94u, 0x40u},
- {0x96u, 0x44u},
- {0x97u, 0x10u},
- {0x9Cu, 0x81u},
- {0x9Eu, 0x10u},
- {0xA6u, 0x04u},
- {0xA7u, 0x20u},
- {0xA8u, 0x04u},
+ {0x85u, 0x02u},
+ {0x86u, 0x20u},
+ {0x87u, 0x04u},
+ {0x89u, 0x9Au},
+ {0x8Au, 0x40u},
+ {0x8Cu, 0x20u},
+ {0x92u, 0x04u},
+ {0x93u, 0x13u},
+ {0x96u, 0x20u},
+ {0x98u, 0xFDu},
+ {0x9Au, 0x42u},
+ {0x9Bu, 0x95u},
+ {0x9Du, 0x22u},
+ {0x9Eu, 0x19u},
+ {0xA0u, 0x60u},
+ {0xA1u, 0x88u},
+ {0xA2u, 0x48u},
+ {0xA3u, 0x01u},
+ {0xA5u, 0x52u},
+ {0xA6u, 0x80u},
+ {0xA7u, 0x0Au},
+ {0xAFu, 0x01u},
+ {0xB0u, 0x01u},
+ {0xB1u, 0x10u},
+ {0xB2u, 0x09u},
+ {0xB4u, 0x80u},
+ {0xB5u, 0x04u},
+ {0xB7u, 0x01u},
+ {0xC0u, 0x0Fu},
+ {0xC2u, 0x0Du},
+ {0xC4u, 0x0Eu},
+ {0xCAu, 0x87u},
+ {0xCCu, 0xCFu},
+ {0xCEu, 0xDEu},
+ {0xD0u, 0xB0u},
+ {0xD2u, 0x30u},
+ {0xD6u, 0xFFu},
+ {0xD8u, 0x98u},
+ {0xE0u, 0x08u},
{0xE2u, 0x02u},
- {0xE6u, 0x04u},
- {0xEAu, 0x06u},
- {0xEEu, 0x08u},
- {0x01u, 0xFFu},
- {0x05u, 0x30u},
+ {0xE6u, 0x0Cu},
+ {0xE8u, 0x02u},
+ {0xEAu, 0x20u},
+ {0xEEu, 0x01u},
+ {0x01u, 0x6Cu},
+ {0x02u, 0x60u},
+ {0x04u, 0x7Fu},
+ {0x05u, 0x24u},
{0x06u, 0x80u},
- {0x07u, 0xC0u},
- {0x09u, 0x50u},
- {0x0Bu, 0xA0u},
- {0x0Eu, 0x08u},
- {0x0Fu, 0xFFu},
- {0x11u, 0x05u},
- {0x13u, 0x0Au},
- {0x14u, 0x99u},
- {0x16u, 0x22u},
- {0x19u, 0x03u},
- {0x1Au, 0x07u},
- {0x1Bu, 0x0Cu},
- {0x1Du, 0x0Fu},
- {0x1Eu, 0x70u},
- {0x1Fu, 0xF0u},
- {0x20u, 0xAAu},
- {0x22u, 0x55u},
- {0x25u, 0x06u},
- {0x27u, 0x09u},
- {0x28u, 0x44u},
- {0x2Au, 0x88u},
- {0x2Bu, 0xFFu},
- {0x2Du, 0x60u},
- {0x2Fu, 0x90u},
- {0x33u, 0xFFu},
- {0x34u, 0x0Fu},
- {0x36u, 0xF0u},
+ {0x09u, 0x08u},
+ {0x0Au, 0x9Fu},
+ {0x0Bu, 0x64u},
+ {0x0Cu, 0x90u},
+ {0x0Du, 0x64u},
+ {0x0Eu, 0x40u},
+ {0x0Fu, 0x08u},
+ {0x11u, 0x93u},
+ {0x13u, 0x60u},
+ {0x14u, 0x1Fu},
+ {0x15u, 0x10u},
+ {0x16u, 0x20u},
+ {0x17u, 0xE5u},
+ {0x18u, 0x80u},
+ {0x19u, 0x77u},
+ {0x1Bu, 0x80u},
+ {0x1Du, 0x6Cu},
+ {0x1Eu, 0xFFu},
+ {0x20u, 0xC0u},
+ {0x21u, 0x40u},
+ {0x22u, 0x02u},
+ {0x23u, 0x02u},
+ {0x24u, 0xC0u},
+ {0x25u, 0x2Cu},
+ {0x26u, 0x04u},
+ {0x27u, 0x40u},
+ {0x28u, 0xC0u},
+ {0x2Au, 0x08u},
+ {0x2Cu, 0xC0u},
+ {0x2Eu, 0x01u},
+ {0x2Fu, 0x08u},
+ {0x31u, 0xF0u},
+ {0x33u, 0x07u},
+ {0x34u, 0xFFu},
+ {0x35u, 0x08u},
+ {0x37u, 0x80u},
+ {0x39u, 0x02u},
+ {0x3Bu, 0x0Cu},
+ {0x3Eu, 0x10u},
+ {0x3Fu, 0x50u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Fu, 0x01u},
+ {0x84u, 0x21u},
+ {0x86u, 0xC2u},
+ {0x89u, 0x60u},
+ {0x8Bu, 0x90u},
+ {0x8Du, 0x30u},
+ {0x8Fu, 0xC0u},
+ {0x90u, 0x80u},
+ {0x91u, 0x0Fu},
+ {0x92u, 0x60u},
+ {0x93u, 0xF0u},
+ {0x96u, 0x01u},
+ {0x99u, 0x05u},
+ {0x9Au, 0x0Cu},
+ {0x9Bu, 0x0Au},
+ {0x9Eu, 0x12u},
+ {0xA1u, 0x06u},
+ {0xA3u, 0x09u},
+ {0xA5u, 0x50u},
+ {0xA7u, 0xA0u},
+ {0xA8u, 0xA8u},
+ {0xA9u, 0x03u},
+ {0xAAu, 0x43u},
+ {0xABu, 0x0Cu},
+ {0xACu, 0x64u},
+ {0xAEu, 0x83u},
+ {0xB0u, 0xE0u},
+ {0xB2u, 0x10u},
+ {0xB3u, 0xFFu},
+ {0xB4u, 0x0Fu},
+ {0xB8u, 0x80u},
+ {0xBAu, 0x02u},
+ {0xBEu, 0x40u},
+ {0xBFu, 0x04u},
+ {0xD6u, 0x02u},
+ {0xD7u, 0x2Cu},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDBu, 0x04u},
+ {0xDFu, 0x01u},
+ {0x03u, 0x10u},
+ {0x05u, 0x01u},
+ {0x06u, 0x08u},
+ {0x07u, 0x21u},
+ {0x09u, 0x40u},
+ {0x0Au, 0x98u},
+ {0x0Eu, 0x2Au},
+ {0x12u, 0x08u},
+ {0x13u, 0x80u},
+ {0x15u, 0x1Au},
+ {0x16u, 0x02u},
+ {0x18u, 0x44u},
+ {0x1Au, 0x9Au},
+ {0x1Du, 0x10u},
+ {0x23u, 0x10u},
+ {0x24u, 0x08u},
+ {0x25u, 0x04u},
+ {0x26u, 0x49u},
+ {0x27u, 0xA0u},
+ {0x29u, 0x04u},
+ {0x2Au, 0x20u},
+ {0x2Bu, 0x40u},
+ {0x2Du, 0x02u},
+ {0x2Eu, 0x84u},
+ {0x2Fu, 0x02u},
+ {0x31u, 0x02u},
+ {0x32u, 0x10u},
+ {0x35u, 0x40u},
+ {0x36u, 0x19u},
+ {0x37u, 0x10u},
+ {0x38u, 0x88u},
+ {0x39u, 0x20u},
+ {0x3Au, 0x04u},
+ {0x3Cu, 0x08u},
+ {0x3Du, 0x50u},
+ {0x3Eu, 0x01u},
+ {0x60u, 0x40u},
+ {0x68u, 0xD8u},
+ {0x69u, 0x5Au},
+ {0x6Au, 0x05u},
+ {0x6Bu, 0x05u},
+ {0x71u, 0x40u},
+ {0x72u, 0x02u},
+ {0x80u, 0x0Cu},
+ {0x82u, 0x01u},
+ {0x84u, 0x50u},
+ {0x88u, 0x10u},
+ {0x89u, 0x40u},
+ {0x8Cu, 0x40u},
+ {0x8Eu, 0x01u},
+ {0x91u, 0x20u},
+ {0x93u, 0x01u},
+ {0x95u, 0x4Au},
+ {0x96u, 0x01u},
+ {0x98u, 0xA4u},
+ {0x99u, 0x01u},
+ {0x9Au, 0x60u},
+ {0x9Du, 0x32u},
+ {0x9Eu, 0x96u},
+ {0x9Fu, 0x21u},
+ {0xA0u, 0x24u},
+ {0xA1u, 0x88u},
+ {0xA2u, 0x14u},
+ {0xA3u, 0x41u},
+ {0xA4u, 0x18u},
+ {0xA5u, 0x14u},
+ {0xA6u, 0x81u},
+ {0xA7u, 0x08u},
+ {0xAAu, 0x22u},
+ {0xB2u, 0x20u},
+ {0xB6u, 0x01u},
+ {0xC0u, 0xF4u},
+ {0xC2u, 0xEFu},
+ {0xC4u, 0xF3u},
+ {0xCAu, 0xD7u},
+ {0xCCu, 0xF5u},
+ {0xCEu, 0xFCu},
+ {0xD8u, 0x01u},
+ {0xE0u, 0x04u},
+ {0xE4u, 0x01u},
+ {0xE6u, 0x4Eu},
+ {0xEAu, 0x01u},
+ {0x00u, 0x02u},
+ {0x01u, 0x3Fu},
+ {0x02u, 0x0Du},
+ {0x03u, 0x40u},
+ {0x04u, 0x0Du},
+ {0x07u, 0x01u},
+ {0x08u, 0x82u},
+ {0x09u, 0x27u},
+ {0x0Au, 0x24u},
+ {0x0Bu, 0x50u},
+ {0x0Cu, 0x0Du},
+ {0x11u, 0x02u},
+ {0x12u, 0x70u},
+ {0x14u, 0x0Du},
+ {0x15u, 0x20u},
+ {0x17u, 0x5Cu},
+ {0x18u, 0x0Du},
+ {0x19u, 0x80u},
+ {0x1Cu, 0x91u},
+ {0x1Du, 0x10u},
+ {0x1Eu, 0x02u},
+ {0x1Fu, 0x60u},
+ {0x20u, 0x70u},
+ {0x21u, 0x03u},
+ {0x24u, 0xC2u},
+ {0x26u, 0x08u},
+ {0x27u, 0x1Fu},
+ {0x28u, 0x0Du},
+ {0x29u, 0x18u},
+ {0x2Bu, 0x03u},
+ {0x30u, 0x0Fu},
+ {0x31u, 0x0Fu},
+ {0x32u, 0x70u},
+ {0x33u, 0x80u},
+ {0x36u, 0x80u},
+ {0x37u, 0x70u},
+ {0x3Au, 0x02u},
+ {0x3Bu, 0x80u},
+ {0x3Eu, 0x44u},
{0x3Fu, 0x04u},
+ {0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
- {0x5Cu, 0x01u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x10u},
+ {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x80u, 0x36u},
- {0x84u, 0x07u},
- {0x85u, 0x11u},
{0x86u, 0x08u},
- {0x87u, 0x62u},
- {0x88u, 0x32u},
- {0x89u, 0x58u},
- {0x8Au, 0x04u},
- {0x8Bu, 0x23u},
- {0x8Cu, 0x06u},
- {0x8Du, 0x34u},
- {0x8Eu, 0x30u},
- {0x8Fu, 0x43u},
- {0x90u, 0x09u},
- {0x92u, 0x06u},
- {0x94u, 0x01u},
- {0x95u, 0x40u},
- {0x96u, 0x0Eu},
- {0x97u, 0x30u},
- {0x98u, 0x04u},
- {0x9Bu, 0x0Cu},
- {0x9Cu, 0x02u},
- {0x9Fu, 0x01u},
- {0xA0u, 0x36u},
- {0xA3u, 0x82u},
- {0xA8u, 0x30u},
- {0xAAu, 0x06u},
- {0xAEu, 0x20u},
- {0xB0u, 0x0Fu},
- {0xB3u, 0x70u},
- {0xB4u, 0x20u},
- {0xB5u, 0x0Fu},
- {0xB6u, 0x10u},
- {0xB7u, 0x80u},
- {0xB8u, 0x02u},
- {0xBBu, 0x08u},
- {0xBEu, 0x50u},
+ {0x87u, 0x20u},
+ {0x8Du, 0x04u},
+ {0x8Fu, 0x88u},
+ {0x90u, 0x04u},
+ {0x96u, 0x01u},
+ {0x9Cu, 0x01u},
+ {0x9Du, 0x08u},
+ {0x9Eu, 0x02u},
+ {0x9Fu, 0x04u},
+ {0xA1u, 0x02u},
+ {0xA3u, 0x01u},
+ {0xA5u, 0x01u},
+ {0xA7u, 0x42u},
+ {0xABu, 0x10u},
+ {0xADu, 0x53u},
+ {0xAEu, 0x02u},
+ {0xAFu, 0xACu},
+ {0xB0u, 0x04u},
+ {0xB1u, 0x30u},
+ {0xB2u, 0x08u},
+ {0xB3u, 0xC0u},
+ {0xB4u, 0x03u},
+ {0xB7u, 0x0Fu},
+ {0xBEu, 0x11u},
+ {0xBFu, 0x45u},
{0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
+ {0xDCu, 0x09u},
{0xDDu, 0x90u},
{0xDFu, 0x01u},
{0x00u, 0x24u},
- {0x01u, 0x41u},
- {0x04u, 0x08u},
- {0x06u, 0x02u},
- {0x0Au, 0x82u},
- {0x0Bu, 0x18u},
- {0x0Du, 0x08u},
- {0x0Eu, 0x0Au},
- {0x10u, 0x08u},
- {0x12u, 0x01u},
- {0x13u, 0x02u},
+ {0x02u, 0x04u},
+ {0x05u, 0x09u},
+ {0x06u, 0x09u},
+ {0x08u, 0x02u},
+ {0x09u, 0x40u},
+ {0x0Bu, 0x10u},
+ {0x0Cu, 0x04u},
+ {0x0Fu, 0x86u},
+ {0x10u, 0x02u},
+ {0x12u, 0x02u},
{0x14u, 0x40u},
- {0x17u, 0x10u},
- {0x18u, 0x40u},
- {0x19u, 0x40u},
- {0x1Au, 0x81u},
- {0x1Bu, 0x10u},
- {0x1Eu, 0x0Au},
- {0x1Fu, 0x10u},
- {0x22u, 0x98u},
- {0x24u, 0x20u},
- {0x29u, 0x01u},
- {0x2Eu, 0x14u},
- {0x2Fu, 0x02u},
- {0x32u, 0x98u},
- {0x36u, 0x11u},
- {0x37u, 0x40u},
- {0x38u, 0x44u},
- {0x3Bu, 0x10u},
- {0x3Cu, 0x02u},
- {0x3Du, 0x08u},
- {0x3Eu, 0xA0u},
- {0x58u, 0x16u},
- {0x59u, 0x80u},
- {0x60u, 0xA8u},
- {0x63u, 0x02u},
- {0x69u, 0x80u},
- {0x6Au, 0x40u},
- {0x81u, 0x80u},
- {0x82u, 0x10u},
- {0x87u, 0x01u},
- {0x90u, 0x0Cu},
- {0x91u, 0x61u},
- {0x92u, 0x06u},
- {0x93u, 0x9Eu},
- {0x94u, 0x60u},
- {0x96u, 0xC0u},
- {0x98u, 0x52u},
- {0x99u, 0x21u},
- {0x9Au, 0x93u},
- {0x9Bu, 0x12u},
- {0x9Cu, 0xA8u},
- {0x9Du, 0x40u},
- {0xA0u, 0x98u},
- {0xA1u, 0x08u},
- {0xA2u, 0x10u},
- {0xA5u, 0x04u},
- {0xA6u, 0x0Au},
- {0xA7u, 0x01u},
- {0xA8u, 0x10u},
- {0xC0u, 0xAFu},
- {0xC2u, 0xEFu},
- {0xC4u, 0x5Bu},
- {0xCAu, 0x71u},
- {0xCCu, 0xBEu},
- {0xCEu, 0xFEu},
- {0xD6u, 0x0Fu},
- {0xD8u, 0x0Fu},
- {0xE2u, 0x04u},
- {0xEAu, 0x02u},
- {0xEEu, 0x08u},
- {0x02u, 0x07u},
- {0x04u, 0x04u},
- {0x06u, 0x08u},
- {0x09u, 0x01u},
- {0x0Bu, 0x12u},
- {0x0Du, 0x08u},
- {0x0Fu, 0x84u},
- {0x10u, 0x0Au},
- {0x12u, 0x05u},
+ {0x15u, 0x10u},
+ {0x17u, 0x08u},
+ {0x19u, 0x10u},
+ {0x1Au, 0x60u},
+ {0x1Du, 0x01u},
+ {0x1Fu, 0x88u},
+ {0x20u, 0x82u},
+ {0x22u, 0x88u},
+ {0x24u, 0x02u},
+ {0x25u, 0x0Bu},
+ {0x26u, 0x40u},
+ {0x28u, 0x80u},
+ {0x29u, 0x20u},
+ {0x2Bu, 0x12u},
+ {0x2Eu, 0x22u},
+ {0x2Fu, 0x20u},
+ {0x30u, 0x80u},
+ {0x31u, 0x0Cu},
+ {0x34u, 0x18u},
+ {0x35u, 0x02u},
+ {0x36u, 0x60u},
+ {0x37u, 0x01u},
+ {0x38u, 0x80u},
+ {0x3Au, 0x04u},
+ {0x3Du, 0x0Au},
+ {0x3Eu, 0x10u},
+ {0x5Au, 0x80u},
+ {0x5Du, 0x40u},
+ {0x62u, 0x40u},
+ {0x66u, 0x80u},
+ {0x7Du, 0x08u},
+ {0x7Fu, 0x10u},
+ {0x82u, 0x0Au},
+ {0x83u, 0x40u},
+ {0x84u, 0x41u},
+ {0x87u, 0x10u},
+ {0x88u, 0x04u},
+ {0x89u, 0x10u},
+ {0x8Eu, 0x0Au},
+ {0x90u, 0xCCu},
+ {0x91u, 0x40u},
+ {0x92u, 0x90u},
+ {0x93u, 0x10u},
+ {0x94u, 0x02u},
+ {0x96u, 0x60u},
+ {0x98u, 0x48u},
+ {0x99u, 0x02u},
+ {0x9Au, 0x32u},
+ {0x9Bu, 0x04u},
+ {0x9Cu, 0x12u},
+ {0x9Du, 0x44u},
+ {0x9Eu, 0xC8u},
+ {0x9Fu, 0x20u},
+ {0xA0u, 0x96u},
+ {0xA1u, 0x24u},
+ {0xA3u, 0x31u},
+ {0xA5u, 0x42u},
+ {0xA9u, 0x02u},
+ {0xAAu, 0x40u},
+ {0xB3u, 0x10u},
+ {0xB7u, 0x10u},
+ {0xC0u, 0xF4u},
+ {0xC2u, 0xFDu},
+ {0xC4u, 0x71u},
+ {0xCAu, 0xEFu},
+ {0xCCu, 0xF8u},
+ {0xCEu, 0xEAu},
+ {0xD6u, 0x18u},
+ {0xD8u, 0x18u},
+ {0xE0u, 0x82u},
+ {0xE4u, 0x80u},
+ {0xE6u, 0x10u},
+ {0xEEu, 0xC1u},
+ {0x02u, 0x17u},
+ {0x03u, 0x17u},
+ {0x07u, 0x20u},
+ {0x0Au, 0x08u},
+ {0x0Cu, 0x10u},
+ {0x0Eu, 0x20u},
+ {0x11u, 0x50u},
+ {0x12u, 0x20u},
+ {0x13u, 0xA0u},
{0x14u, 0x09u},
+ {0x15u, 0x09u},
{0x16u, 0x02u},
- {0x1Du, 0x53u},
- {0x1Fu, 0xACu},
- {0x21u, 0x02u},
- {0x22u, 0x08u},
- {0x23u, 0x41u},
- {0x2Du, 0x04u},
- {0x2Fu, 0x28u},
+ {0x17u, 0x02u},
+ {0x18u, 0x04u},
+ {0x19u, 0x04u},
+ {0x1Au, 0x08u},
+ {0x1Bu, 0x08u},
+ {0x20u, 0x0Au},
+ {0x21u, 0x0Au},
+ {0x22u, 0x05u},
+ {0x23u, 0x05u},
+ {0x27u, 0x40u},
+ {0x2Bu, 0x08u},
+ {0x2Fu, 0x80u},
{0x30u, 0x0Fu},
- {0x31u, 0xC0u},
- {0x33u, 0x30u},
- {0x37u, 0x0Fu},
- {0x3Fu, 0x45u},
- {0x54u, 0x40u},
- {0x56u, 0x04u},
+ {0x31u, 0x0Fu},
+ {0x32u, 0x30u},
+ {0x33u, 0xC0u},
+ {0x35u, 0x30u},
+ {0x3Eu, 0x04u},
+ {0x3Fu, 0x14u},
+ {0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x01u},
+ {0x5Cu, 0x11u},
+ {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x81u, 0xFFu},
- {0x82u, 0x10u},
- {0x85u, 0x30u},
- {0x86u, 0x01u},
- {0x87u, 0xC0u},
- {0x8Cu, 0x80u},
- {0x8Du, 0x90u},
- {0x8Eu, 0x05u},
- {0x8Fu, 0x60u},
+ {0x80u, 0x90u},
+ {0x82u, 0x60u},
+ {0x83u, 0xFFu},
+ {0x84u, 0x03u},
+ {0x86u, 0x0Cu},
+ {0x87u, 0xFFu},
+ {0x89u, 0x30u},
+ {0x8Au, 0xFFu},
+ {0x8Bu, 0xC0u},
+ {0x8Cu, 0x0Fu},
+ {0x8Du, 0x0Fu},
+ {0x8Eu, 0xF0u},
+ {0x8Fu, 0xF0u},
+ {0x90u, 0xFFu},
{0x91u, 0x05u},
{0x93u, 0x0Au},
- {0x94u, 0x06u},
+ {0x94u, 0x30u},
{0x95u, 0x50u},
- {0x96u, 0x80u},
+ {0x96u, 0xC0u},
{0x97u, 0xA0u},
- {0x99u, 0x03u},
- {0x9Au, 0x08u},
- {0x9Bu, 0x0Cu},
- {0x9Du, 0x0Fu},
- {0x9Eu, 0x20u},
- {0x9Fu, 0xF0u},
- {0xA5u, 0x09u},
- {0xA6u, 0x40u},
- {0xA7u, 0x06u},
- {0xA9u, 0xFFu},
- {0xAAu, 0x83u},
- {0xACu, 0x28u},
- {0xAEu, 0x50u},
- {0xAFu, 0xFFu},
- {0xB0u, 0x80u},
- {0xB2u, 0x07u},
- {0xB4u, 0x60u},
- {0xB6u, 0x18u},
- {0xB7u, 0xFFu},
- {0xBEu, 0x51u},
- {0xBFu, 0x40u},
- {0xD4u, 0x09u},
- {0xD6u, 0x04u},
+ {0x98u, 0x09u},
+ {0x9Au, 0x06u},
+ {0x9Du, 0xFFu},
+ {0xA0u, 0x05u},
+ {0xA2u, 0x0Au},
+ {0xA4u, 0x50u},
+ {0xA5u, 0x06u},
+ {0xA6u, 0xA0u},
+ {0xA7u, 0x09u},
+ {0xA9u, 0x03u},
+ {0xABu, 0x0Cu},
+ {0xACu, 0xFFu},
+ {0xADu, 0x60u},
+ {0xAFu, 0x90u},
+ {0xB3u, 0xFFu},
+ {0xB6u, 0xFFu},
+ {0xBEu, 0x40u},
+ {0xBFu, 0x04u},
+ {0xD4u, 0x01u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
+ {0xDDu, 0x10u},
{0xDFu, 0x01u},
{0x01u, 0x02u},
- {0x03u, 0x10u},
- {0x04u, 0x42u},
- {0x05u, 0x04u},
- {0x09u, 0x08u},
+ {0x02u, 0x40u},
+ {0x03u, 0x05u},
+ {0x06u, 0xA8u},
+ {0x07u, 0x01u},
+ {0x08u, 0x04u},
+ {0x09u, 0x20u},
+ {0x0Au, 0x10u},
{0x0Bu, 0x80u},
- {0x0Eu, 0x06u},
- {0x0Fu, 0x10u},
- {0x10u, 0x80u},
- {0x15u, 0xA0u},
- {0x16u, 0x20u},
- {0x17u, 0x44u},
+ {0x0Eu, 0x84u},
+ {0x0Fu, 0x20u},
+ {0x10u, 0x40u},
+ {0x11u, 0x02u},
+ {0x16u, 0x42u},
+ {0x17u, 0x08u},
+ {0x18u, 0x20u},
{0x19u, 0x02u},
- {0x1Cu, 0x01u},
- {0x1Du, 0x04u},
- {0x1Eu, 0x48u},
- {0x20u, 0x82u},
- {0x22u, 0x04u},
- {0x27u, 0x01u},
- {0x29u, 0x42u},
- {0x2Eu, 0x94u},
- {0x33u, 0x40u},
- {0x36u, 0x11u},
- {0x37u, 0x44u},
- {0x38u, 0x80u},
- {0x3Bu, 0x20u},
- {0x3Cu, 0x02u},
- {0x3Du, 0x88u},
- {0x44u, 0x02u},
- {0x46u, 0x01u},
- {0x5Du, 0x20u},
- {0x5Eu, 0x41u},
- {0x5Fu, 0x04u},
+ {0x1Du, 0x40u},
+ {0x20u, 0x10u},
+ {0x21u, 0x01u},
+ {0x22u, 0x10u},
+ {0x27u, 0x20u},
+ {0x28u, 0x40u},
+ {0x2Au, 0x90u},
+ {0x2Bu, 0x20u},
+ {0x2Du, 0x20u},
+ {0x2Eu, 0xA4u},
+ {0x2Fu, 0x20u},
+ {0x30u, 0x04u},
+ {0x31u, 0x20u},
+ {0x33u, 0x01u},
+ {0x35u, 0x02u},
+ {0x36u, 0xC0u},
+ {0x37u, 0x08u},
+ {0x38u, 0x08u},
+ {0x39u, 0x02u},
+ {0x3Bu, 0x02u},
+ {0x3Cu, 0x20u},
+ {0x3Du, 0x89u},
+ {0x3Eu, 0x0Au},
+ {0x3Fu, 0x20u},
+ {0x58u, 0x10u},
+ {0x5Au, 0x40u},
+ {0x5Cu, 0x40u},
{0x60u, 0x02u},
- {0x62u, 0x12u},
- {0x63u, 0x20u},
- {0x65u, 0x01u},
- {0x67u, 0x02u},
- {0x6Cu, 0x41u},
- {0x6Du, 0x88u},
- {0x6Fu, 0x06u},
- {0x74u, 0x08u},
- {0x75u, 0x40u},
- {0x77u, 0x88u},
- {0x80u, 0x01u},
- {0x81u, 0x05u},
- {0x82u, 0x04u},
- {0x86u, 0x04u},
- {0x87u, 0x80u},
- {0x88u, 0x08u},
- {0x90u, 0x40u},
- {0x91u, 0xA0u},
- {0x92u, 0x15u},
- {0x93u, 0xB6u},
- {0x94u, 0x02u},
- {0x99u, 0x20u},
- {0x9Au, 0x91u},
- {0x9Bu, 0x10u},
- {0x9Eu, 0x20u},
- {0x9Fu, 0x49u},
- {0xA0u, 0x80u},
- {0xA1u, 0x08u},
- {0xA2u, 0x11u},
- {0xA3u, 0x10u},
- {0xA4u, 0x41u},
- {0xA5u, 0x04u},
- {0xA6u, 0x02u},
+ {0x62u, 0x20u},
+ {0x6Du, 0x80u},
+ {0x6Fu, 0x03u},
+ {0x80u, 0x10u},
+ {0x82u, 0x40u},
+ {0x83u, 0x01u},
+ {0x84u, 0x10u},
+ {0x85u, 0x43u},
+ {0x89u, 0x20u},
+ {0x8Au, 0x04u},
+ {0x8Bu, 0x48u},
+ {0x8Cu, 0x10u},
+ {0x8Eu, 0x90u},
+ {0x90u, 0x48u},
+ {0x92u, 0x10u},
+ {0x9Au, 0x10u},
+ {0x9Bu, 0x04u},
+ {0x9Cu, 0x02u},
+ {0x9Du, 0x60u},
+ {0x9Fu, 0x20u},
+ {0xA0u, 0x10u},
+ {0xA1u, 0x25u},
+ {0xA2u, 0x80u},
+ {0xA5u, 0x40u},
+ {0xA6u, 0x20u},
{0xA7u, 0x02u},
- {0xAAu, 0x11u},
- {0xACu, 0x04u},
- {0xB0u, 0x41u},
- {0xB2u, 0x20u},
- {0xB4u, 0x01u},
- {0xB7u, 0x08u},
- {0xC0u, 0xBCu},
- {0xC2u, 0xECu},
- {0xC4u, 0xE8u},
- {0xCAu, 0x79u},
- {0xCCu, 0xF8u},
- {0xCEu, 0xDCu},
- {0xD6u, 0xF0u},
- {0xD8u, 0x9Fu},
- {0xE0u, 0x01u},
- {0xE4u, 0x0Cu},
- {0xE6u, 0x20u},
- {0xEAu, 0xC8u},
- {0xEEu, 0xC0u},
+ {0xA9u, 0x10u},
+ {0xABu, 0x08u},
+ {0xAFu, 0x04u},
+ {0xB0u, 0x84u},
+ {0xB1u, 0x08u},
+ {0xB3u, 0x09u},
+ {0xB4u, 0x04u},
+ {0xB6u, 0x01u},
+ {0xB7u, 0x80u},
+ {0xC0u, 0xFBu},
+ {0xC2u, 0x7Eu},
+ {0xC4u, 0xB8u},
+ {0xCAu, 0x7Fu},
+ {0xCCu, 0xD7u},
+ {0xCEu, 0xF3u},
+ {0xD6u, 0x1Cu},
+ {0xD8u, 0x0Cu},
+ {0xE0u, 0x20u},
+ {0xE2u, 0x04u},
+ {0xE4u, 0xB1u},
+ {0xE6u, 0x02u},
+ {0xE8u, 0x80u},
+ {0xEAu, 0x50u},
+ {0xECu, 0xC4u},
+ {0xEEu, 0x20u},
+ {0x04u, 0x80u},
{0x0Fu, 0x08u},
- {0x12u, 0x08u},
- {0x15u, 0x80u},
- {0x17u, 0x04u},
- {0x33u, 0x04u},
- {0x36u, 0x88u},
- {0x39u, 0x81u},
- {0x3Cu, 0x01u},
+ {0x13u, 0x10u},
+ {0x17u, 0x48u},
+ {0x33u, 0x02u},
+ {0x36u, 0x80u},
+ {0x37u, 0x08u},
+ {0x39u, 0x04u},
+ {0x3Bu, 0x10u},
{0x3Du, 0x20u},
+ {0x3Eu, 0x08u},
{0x40u, 0x04u},
- {0x62u, 0x02u},
- {0x83u, 0x04u},
- {0x86u, 0x08u},
- {0x8Au, 0x02u},
+ {0x62u, 0x08u},
+ {0x8Bu, 0x02u},
+ {0xC0u, 0x80u},
{0xC2u, 0x80u},
{0xC4u, 0xE0u},
{0xCCu, 0xE0u},
{0xCEu, 0xF0u},
{0xD0u, 0x10u},
{0xD8u, 0x40u},
- {0xE4u, 0x20u},
- {0xE6u, 0x40u},
- {0x33u, 0x81u},
+ {0x30u, 0x02u},
+ {0x33u, 0x40u},
+ {0x34u, 0x02u},
{0x35u, 0x80u},
- {0x3Au, 0x10u},
- {0x50u, 0x08u},
- {0x56u, 0x08u},
- {0x63u, 0x20u},
- {0x85u, 0x01u},
- {0x88u, 0x08u},
- {0x8Du, 0x10u},
- {0x8Fu, 0x10u},
- {0x94u, 0x05u},
- {0x95u, 0x01u},
- {0x9Au, 0x08u},
+ {0x3Bu, 0x10u},
+ {0x50u, 0x10u},
+ {0x5Cu, 0x10u},
+ {0x63u, 0x02u},
+ {0x80u, 0x10u},
+ {0x8Cu, 0x50u},
+ {0x8Fu, 0x04u},
+ {0x90u, 0x80u},
+ {0x94u, 0x04u},
+ {0x95u, 0x04u},
+ {0x9Bu, 0x40u},
+ {0x9Eu, 0x08u},
+ {0xA3u, 0x05u},
{0xA5u, 0x10u},
{0xA6u, 0x80u},
- {0xCCu, 0x70u},
+ {0xAAu, 0x08u},
+ {0xAFu, 0x01u},
+ {0xCCu, 0xF0u},
{0xCEu, 0x10u},
- {0xD4u, 0x60u},
- {0xD8u, 0x40u},
- {0xE2u, 0x10u},
+ {0xD4u, 0x20u},
+ {0xD6u, 0x60u},
+ {0xE6u, 0x80u},
+ {0xEAu, 0x20u},
+ {0xEEu, 0x10u},
{0x12u, 0x80u},
- {0x5Bu, 0x08u},
+ {0x80u, 0x02u},
+ {0x81u, 0x10u},
{0x85u, 0x80u},
- {0x8Au, 0x10u},
- {0x8Cu, 0x01u},
- {0x94u, 0x05u},
+ {0x86u, 0x08u},
+ {0x89u, 0x04u},
+ {0x94u, 0x04u},
+ {0x95u, 0x04u},
+ {0x97u, 0x10u},
+ {0x9Cu, 0x02u},
{0x9Du, 0x80u},
- {0x9Eu, 0x10u},
- {0x9Fu, 0x01u},
- {0xA2u, 0x10u},
+ {0x9Eu, 0x08u},
+ {0xA4u, 0x02u},
+ {0xA5u, 0x10u},
{0xA6u, 0x80u},
- {0xA7u, 0x80u},
- {0xAEu, 0x10u},
{0xC4u, 0x10u},
- {0xD6u, 0x40u},
- {0xE2u, 0x10u},
- {0xEEu, 0x10u},
- {0x8Au, 0x20u},
+ {0xE2u, 0xB0u},
+ {0xE6u, 0x40u},
{0x94u, 0x04u},
- {0x9Fu, 0x01u},
- {0xA2u, 0x10u},
- {0xA7u, 0x80u},
- {0xB3u, 0x08u},
- {0x01u, 0x20u},
+ {0xA8u, 0x02u},
+ {0xAFu, 0x10u},
+ {0xEAu, 0x10u},
+ {0xEEu, 0x80u},
+ {0x02u, 0x02u},
+ {0x05u, 0x20u},
{0x08u, 0x20u},
- {0x0Eu, 0x01u},
- {0x13u, 0x02u},
- {0x14u, 0x80u},
+ {0x0Fu, 0x08u},
+ {0x12u, 0x80u},
+ {0x17u, 0x08u},
{0x58u, 0x01u},
{0x60u, 0x10u},
- {0x8Au, 0x01u},
- {0x8Cu, 0x20u},
- {0x8Du, 0x20u},
- {0xC0u, 0x02u},
+ {0x80u, 0x10u},
+ {0x89u, 0x20u},
+ {0x8Bu, 0x80u},
+ {0xC0u, 0x03u},
{0xC2u, 0x03u},
{0xC4u, 0x0Cu},
{0xD6u, 0x02u},
{0xD8u, 0x02u},
- {0xE2u, 0x0Au},
- {0xE6u, 0x01u},
- {0x04u, 0x04u},
- {0x0Au, 0x20u},
+ {0xE2u, 0x05u},
+ {0x03u, 0x80u},
+ {0x07u, 0x10u},
+ {0x08u, 0x02u},
{0x0Du, 0x01u},
- {0x52u, 0x02u},
- {0x56u, 0x80u},
- {0x63u, 0x02u},
- {0x65u, 0x40u},
- {0x82u, 0x98u},
- {0x8Bu, 0x01u},
- {0x9Bu, 0x02u},
+ {0x59u, 0x10u},
+ {0x5Du, 0x40u},
+ {0x5Fu, 0x02u},
+ {0x66u, 0x20u},
+ {0x8Au, 0x02u},
+ {0x98u, 0x20u},
+ {0x9Bu, 0x0Au},
{0x9Cu, 0x01u},
- {0xA8u, 0x80u},
- {0xB4u, 0x10u},
- {0xC0u, 0x04u},
+ {0xA2u, 0x82u},
+ {0xA3u, 0x04u},
+ {0xA7u, 0x80u},
+ {0xABu, 0x02u},
+ {0xC0u, 0x0Cu},
{0xC2u, 0x0Cu},
- {0xD4u, 0x03u},
- {0xD6u, 0x03u},
- {0xE0u, 0x01u},
- {0xE8u, 0x08u},
- {0x54u, 0x10u},
+ {0xD4u, 0x01u},
+ {0xD6u, 0x05u},
+ {0xD8u, 0x01u},
+ {0xE6u, 0x04u},
+ {0x57u, 0x08u},
+ {0x82u, 0x40u},
{0x87u, 0x10u},
- {0x8Au, 0x04u},
- {0x90u, 0x04u},
+ {0x8Bu, 0x01u},
+ {0x8Fu, 0x08u},
+ {0x91u, 0x02u},
+ {0x95u, 0x40u},
+ {0x98u, 0x22u},
+ {0x9Bu, 0x08u},
{0x9Cu, 0x01u},
- {0x9Du, 0x40u},
- {0x9Eu, 0x08u},
- {0xA0u, 0x10u},
- {0xAAu, 0x02u},
- {0xB0u, 0x10u},
- {0xB1u, 0x01u},
- {0xB7u, 0x02u},
+ {0x9Du, 0x10u},
+ {0x9Eu, 0x20u},
+ {0xA2u, 0x80u},
+ {0xA3u, 0x04u},
+ {0xABu, 0x10u},
{0xD4u, 0x02u},
- {0xE6u, 0x04u},
- {0xEAu, 0x0Cu},
- {0xECu, 0x01u},
- {0x08u, 0x08u},
- {0x0Bu, 0x04u},
- {0x0Eu, 0x04u},
- {0x0Fu, 0x10u},
- {0x90u, 0x04u},
- {0x96u, 0x04u},
+ {0xE6u, 0x06u},
+ {0x08u, 0x80u},
+ {0x0Bu, 0x10u},
+ {0x0Eu, 0x41u},
+ {0x91u, 0x02u},
+ {0x95u, 0x40u},
+ {0x96u, 0x41u},
{0x97u, 0x10u},
- {0x9Cu, 0x01u},
- {0x9Du, 0x40u},
- {0x9Eu, 0x08u},
- {0xC2u, 0x0Fu},
- {0x94u, 0x04u},
+ {0x98u, 0x02u},
+ {0x9Cu, 0x81u},
+ {0x9Du, 0x10u},
{0x9Eu, 0x20u},
- {0xA2u, 0x10u},
- {0xAFu, 0x81u},
- {0xEAu, 0x40u},
- {0xEEu, 0x10u},
- {0x06u, 0x20u},
- {0x5Bu, 0x40u},
- {0x5Eu, 0x20u},
- {0x80u, 0x04u},
- {0x83u, 0x40u},
+ {0x9Fu, 0x01u},
+ {0xA8u, 0x80u},
+ {0xABu, 0x04u},
+ {0xACu, 0x20u},
+ {0xAEu, 0x01u},
+ {0xB2u, 0x80u},
+ {0xB3u, 0x08u},
+ {0xC2u, 0x0Fu},
+ {0xE8u, 0x04u},
+ {0xEAu, 0x01u},
+ {0x66u, 0x08u},
+ {0x8Cu, 0x04u},
{0x94u, 0x04u},
- {0x9Eu, 0x20u},
- {0xA2u, 0x10u},
+ {0x99u, 0x20u},
+ {0xA9u, 0x20u},
+ {0xD8u, 0x80u},
+ {0xEEu, 0x80u},
+ {0x05u, 0x01u},
+ {0x57u, 0x08u},
+ {0x59u, 0x20u},
+ {0x81u, 0x01u},
+ {0x99u, 0x20u},
+ {0xA3u, 0x08u},
+ {0xABu, 0x08u},
+ {0xB2u, 0x08u},
{0xC0u, 0x20u},
- {0xD4u, 0x80u},
- {0xD6u, 0x20u},
- {0xE2u, 0x20u},
- {0xE6u, 0x80u},
- {0x80u, 0x04u},
- {0x90u, 0x04u},
+ {0xD4u, 0xC0u},
+ {0xE0u, 0x20u},
+ {0xEEu, 0x80u},
+ {0x84u, 0x01u},
+ {0x8Eu, 0x20u},
+ {0x91u, 0x02u},
+ {0x95u, 0x40u},
{0x9Cu, 0x01u},
- {0x9Du, 0x40u},
- {0x9Eu, 0x08u},
- {0xACu, 0x08u},
- {0xAFu, 0x04u},
- {0x00u, 0x20u},
- {0x06u, 0x08u},
- {0x53u, 0x80u},
- {0x56u, 0x80u},
- {0x82u, 0x80u},
- {0x83u, 0x80u},
- {0x85u, 0x40u},
- {0x9Du, 0x40u},
- {0x9Eu, 0x08u},
- {0xA4u, 0x10u},
- {0xACu, 0x10u},
- {0xB0u, 0x01u},
+ {0x9Du, 0x10u},
+ {0x9Eu, 0x20u},
+ {0x9Fu, 0x01u},
+ {0xA8u, 0x02u},
+ {0xE4u, 0x02u},
+ {0x03u, 0x01u},
+ {0x04u, 0x20u},
+ {0x50u, 0x04u},
+ {0x5Eu, 0x40u},
+ {0x80u, 0x14u},
+ {0x85u, 0x01u},
+ {0x8Du, 0x10u},
+ {0x8Eu, 0x40u},
+ {0x91u, 0x02u},
+ {0x9Du, 0x10u},
+ {0x9Fu, 0x01u},
+ {0xA9u, 0x40u},
{0xC0u, 0x03u},
- {0xD4u, 0x06u},
- {0xECu, 0x04u},
+ {0xD4u, 0x04u},
+ {0xD6u, 0x04u},
+ {0xE0u, 0x02u},
+ {0xE4u, 0x02u},
{0x10u, 0x03u},
{0x11u, 0x01u},
+ {0x1Au, 0x01u},
+ {0x1Bu, 0x01u},
{0x1Cu, 0x03u},
{0x1Du, 0x01u},
{0x00u, 0xFDu},
- {0x01u, 0xABu},
- {0x02u, 0x08u},
+ {0x01u, 0xAFu},
+ {0x02u, 0x0Au},
{0x10u, 0x55u},
};
/* address, size */
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},
{(void CYFAR *)(CYREG_PRT1_DR), 16u},
- {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 2176u},
- {(void CYFAR *)(CYDEV_UCFG_B0_P4_ROUTE_BASE), 1792u},
+ {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
{(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},
};
- /* UDB_0_2_0_CONFIG Address: CYDEV_UCFG_B0_P4_U1_BASE Size (bytes): 128 */
- static const uint8 CYCODE BS_UDB_0_2_0_CONFIG_VAL[] = {
- 0x01u, 0x74u, 0x00u, 0x00u, 0x00u, 0x54u, 0x00u, 0x20u, 0x01u, 0x40u, 0x00u, 0x34u, 0x10u, 0x34u, 0x00u, 0x40u,
- 0x08u, 0x94u, 0x21u, 0x40u, 0x07u, 0xC0u, 0x18u, 0x3Du, 0x22u, 0x47u, 0x08u, 0x88u, 0x01u, 0x83u, 0x00u, 0x78u,
- 0x01u, 0x00u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x00u, 0x02u, 0x01u, 0x74u, 0x00u, 0x00u,
- 0x3Fu, 0xC0u, 0x00u, 0x07u, 0x00u, 0x39u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x0Eu, 0x00u, 0x00u, 0x01u, 0x00u,
- 0x46u, 0x02u, 0x50u, 0x00u, 0x03u, 0xBEu, 0xF0u, 0xDCu, 0x3Bu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x28u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u,
- 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
-
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x02u, 0x00u, 0x03u, 0x00u, 0x03u, 0x01u};
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u};
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
- {(void CYFAR *)(CYDEV_UCFG_B0_P4_U1_BASE), BS_UDB_0_2_0_CONFIG_VAL, 128u},
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},
};
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DM0 + 0x00000009u), (const void CYCODE *)(BS_IOPINS1_7_VAL), 5u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u);
- CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DM0), (const void CYCODE *)(BS_IOPINS0_3_VAL), 8u);
+ CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DR), (const void CYCODE *)(BS_IOPINS0_3_VAL), 10u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT5_DM0), (const void CYCODE *)(BS_IOPINS0_5_VAL), 8u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u);
/* SCSI_TX_DMA_COMPLETE */
.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x04
-.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 2
+.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x08
+.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 3
.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3
.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SD_RX_DMA_COMPLETE */
.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x08
-.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 3
+.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x10
+.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 4
.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4
.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SD_TX_DMA_COMPLETE */
.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x10
-.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 4
+.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x20
+.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 5
.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5
.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK
-.set SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB02_ST_CTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB02_ST_CTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B1_UDB11_MSK
+.set SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG, CYREG_B1_UDB11_ST_CTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B1_UDB11_ST_CTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B1_UDB11_ST
/* USBFS_bus_reset */
.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
+
+/* SCSI_Filtered */
+.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01
+.set SCSI_Filtered_sts_sts_reg__0__POS, 0
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST
+.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
+.set SCSI_Filtered_sts_sts_reg__1__POS, 1
+.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
+.set SCSI_Filtered_sts_sts_reg__2__POS, 2
+.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
+.set SCSI_Filtered_sts_sts_reg__3__POS, 3
+.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
+.set SCSI_Filtered_sts_sts_reg__4__POS, 4
+.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB13_MSK
+.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
+.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB13_ST_CTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB13_ST_CTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB13_ST
/* SCSI_Out_Bits */
.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB11_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB11_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB11_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
/* USBFS_arb_int */
.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
/* SCSI_Out_Ctl */
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB09_10_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB09_10_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB09_10_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB09_10_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB09_10_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB09_10_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB09_10_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB09_10_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB09_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB09_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB09_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB09_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB11_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB11_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB11_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB11_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB09_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB11_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
/* SCSI_Out_DBx */
.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
/* SCSI_RST_ISR */
.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_RST_ISR__INTC_MASK, 0x100
-.set SCSI_RST_ISR__INTC_NUMBER, 8
+.set SCSI_RST_ISR__INTC_MASK, 0x04
+.set SCSI_RST_ISR__INTC_NUMBER, 2
.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7
-.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_8
+.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2
.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB09_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB09_ST
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB09_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB09_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB09_MSK
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB10_11_ST
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB10_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB10_ST
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB06_MSK
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB06_ST
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
.set SDCard_BSPIM_TxStsReg__0__POS, 0
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB11_MSK
-.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
-.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B1_UDB11_ST_CTL
-.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB11_ST_CTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB11_ST
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB09_10_A0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB09_10_A1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB09_10_D0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB09_10_D1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB09_10_F0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB09_10_F1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB09_A0_A1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB09_A0
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB09_A1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB09_D0_D1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB09_D0
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB09_D1
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB09_F0_F1
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB09_F0
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB09_F1
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB05_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB05_ST
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB05_06_A0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB05_06_A1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB05_06_D0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB05_06_D1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB05_06_F0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB05_06_F1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB05_A0_A1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB05_A0
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB05_A1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB05_D0_D1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB05_D0
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB05_D1
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB05_F0_F1
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB05_F0
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB05_F1
/* USBFS_dp_int */
.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2
.set timer_clock__PM_STBY_MSK, 0x04
+/* SCSI_Noise */
+.set SCSI_Noise__0__AG, CYREG_PRT2_AG
+.set SCSI_Noise__0__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Noise__0__BIE, CYREG_PRT2_BIE
+.set SCSI_Noise__0__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Noise__0__BYP, CYREG_PRT2_BYP
+.set SCSI_Noise__0__CTL, CYREG_PRT2_CTL
+.set SCSI_Noise__0__DM0, CYREG_PRT2_DM0
+.set SCSI_Noise__0__DM1, CYREG_PRT2_DM1
+.set SCSI_Noise__0__DM2, CYREG_PRT2_DM2
+.set SCSI_Noise__0__DR, CYREG_PRT2_DR
+.set SCSI_Noise__0__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Noise__0__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Noise__0__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Noise__0__MASK, 0x01
+.set SCSI_Noise__0__PC, CYREG_PRT2_PC0
+.set SCSI_Noise__0__PORT, 2
+.set SCSI_Noise__0__PRT, CYREG_PRT2_PRT
+.set SCSI_Noise__0__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Noise__0__PS, CYREG_PRT2_PS
+.set SCSI_Noise__0__SHIFT, 0
+.set SCSI_Noise__0__SLW, CYREG_PRT2_SLW
+.set SCSI_Noise__1__AG, CYREG_PRT6_AG
+.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__1__DR, CYREG_PRT6_DR
+.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__1__MASK, 0x08
+.set SCSI_Noise__1__PC, CYREG_PRT6_PC3
+.set SCSI_Noise__1__PORT, 6
+.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__1__PS, CYREG_PRT6_PS
+.set SCSI_Noise__1__SHIFT, 3
+.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__2__AG, CYREG_PRT4_AG
+.set SCSI_Noise__2__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Noise__2__BIE, CYREG_PRT4_BIE
+.set SCSI_Noise__2__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Noise__2__BYP, CYREG_PRT4_BYP
+.set SCSI_Noise__2__CTL, CYREG_PRT4_CTL
+.set SCSI_Noise__2__DM0, CYREG_PRT4_DM0
+.set SCSI_Noise__2__DM1, CYREG_PRT4_DM1
+.set SCSI_Noise__2__DM2, CYREG_PRT4_DM2
+.set SCSI_Noise__2__DR, CYREG_PRT4_DR
+.set SCSI_Noise__2__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Noise__2__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Noise__2__MASK, 0x08
+.set SCSI_Noise__2__PC, CYREG_PRT4_PC3
+.set SCSI_Noise__2__PORT, 4
+.set SCSI_Noise__2__PRT, CYREG_PRT4_PRT
+.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Noise__2__PS, CYREG_PRT4_PS
+.set SCSI_Noise__2__SHIFT, 3
+.set SCSI_Noise__2__SLW, CYREG_PRT4_SLW
+.set SCSI_Noise__3__AG, CYREG_PRT4_AG
+.set SCSI_Noise__3__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Noise__3__BIE, CYREG_PRT4_BIE
+.set SCSI_Noise__3__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Noise__3__BYP, CYREG_PRT4_BYP
+.set SCSI_Noise__3__CTL, CYREG_PRT4_CTL
+.set SCSI_Noise__3__DM0, CYREG_PRT4_DM0
+.set SCSI_Noise__3__DM1, CYREG_PRT4_DM1
+.set SCSI_Noise__3__DM2, CYREG_PRT4_DM2
+.set SCSI_Noise__3__DR, CYREG_PRT4_DR
+.set SCSI_Noise__3__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Noise__3__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Noise__3__MASK, 0x80
+.set SCSI_Noise__3__PC, CYREG_PRT4_PC7
+.set SCSI_Noise__3__PORT, 4
+.set SCSI_Noise__3__PRT, CYREG_PRT4_PRT
+.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Noise__3__PS, CYREG_PRT4_PS
+.set SCSI_Noise__3__SHIFT, 7
+.set SCSI_Noise__3__SLW, CYREG_PRT4_SLW
+.set SCSI_Noise__4__AG, CYREG_PRT6_AG
+.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__4__DR, CYREG_PRT6_DR
+.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__4__MASK, 0x04
+.set SCSI_Noise__4__PC, CYREG_PRT6_PC2
+.set SCSI_Noise__4__PORT, 6
+.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__4__PS, CYREG_PRT6_PS
+.set SCSI_Noise__4__SHIFT, 2
+.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG
+.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR
+.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__ACK__MASK, 0x04
+.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC2
+.set SCSI_Noise__ACK__PORT, 6
+.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS
+.set SCSI_Noise__ACK__SHIFT, 2
+.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__ATN__AG, CYREG_PRT2_AG
+.set SCSI_Noise__ATN__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Noise__ATN__BIE, CYREG_PRT2_BIE
+.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Noise__ATN__BYP, CYREG_PRT2_BYP
+.set SCSI_Noise__ATN__CTL, CYREG_PRT2_CTL
+.set SCSI_Noise__ATN__DM0, CYREG_PRT2_DM0
+.set SCSI_Noise__ATN__DM1, CYREG_PRT2_DM1
+.set SCSI_Noise__ATN__DM2, CYREG_PRT2_DM2
+.set SCSI_Noise__ATN__DR, CYREG_PRT2_DR
+.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Noise__ATN__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Noise__ATN__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Noise__ATN__MASK, 0x01
+.set SCSI_Noise__ATN__PC, CYREG_PRT2_PC0
+.set SCSI_Noise__ATN__PORT, 2
+.set SCSI_Noise__ATN__PRT, CYREG_PRT2_PRT
+.set SCSI_Noise__ATN__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Noise__ATN__PS, CYREG_PRT2_PS
+.set SCSI_Noise__ATN__SHIFT, 0
+.set SCSI_Noise__ATN__SLW, CYREG_PRT2_SLW
+.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG
+.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR
+.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__BSY__MASK, 0x08
+.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC3
+.set SCSI_Noise__BSY__PORT, 6
+.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS
+.set SCSI_Noise__BSY__SHIFT, 3
+.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__RST__AG, CYREG_PRT4_AG
+.set SCSI_Noise__RST__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Noise__RST__BIE, CYREG_PRT4_BIE
+.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Noise__RST__BYP, CYREG_PRT4_BYP
+.set SCSI_Noise__RST__CTL, CYREG_PRT4_CTL
+.set SCSI_Noise__RST__DM0, CYREG_PRT4_DM0
+.set SCSI_Noise__RST__DM1, CYREG_PRT4_DM1
+.set SCSI_Noise__RST__DM2, CYREG_PRT4_DM2
+.set SCSI_Noise__RST__DR, CYREG_PRT4_DR
+.set SCSI_Noise__RST__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Noise__RST__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Noise__RST__MASK, 0x80
+.set SCSI_Noise__RST__PC, CYREG_PRT4_PC7
+.set SCSI_Noise__RST__PORT, 4
+.set SCSI_Noise__RST__PRT, CYREG_PRT4_PRT
+.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Noise__RST__PS, CYREG_PRT4_PS
+.set SCSI_Noise__RST__SHIFT, 7
+.set SCSI_Noise__RST__SLW, CYREG_PRT4_SLW
+.set SCSI_Noise__SEL__AG, CYREG_PRT4_AG
+.set SCSI_Noise__SEL__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Noise__SEL__BIE, CYREG_PRT4_BIE
+.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Noise__SEL__BYP, CYREG_PRT4_BYP
+.set SCSI_Noise__SEL__CTL, CYREG_PRT4_CTL
+.set SCSI_Noise__SEL__DM0, CYREG_PRT4_DM0
+.set SCSI_Noise__SEL__DM1, CYREG_PRT4_DM1
+.set SCSI_Noise__SEL__DM2, CYREG_PRT4_DM2
+.set SCSI_Noise__SEL__DR, CYREG_PRT4_DR
+.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Noise__SEL__MASK, 0x08
+.set SCSI_Noise__SEL__PC, CYREG_PRT4_PC3
+.set SCSI_Noise__SEL__PORT, 4
+.set SCSI_Noise__SEL__PRT, CYREG_PRT4_PRT
+.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Noise__SEL__PS, CYREG_PRT4_PS
+.set SCSI_Noise__SEL__SHIFT, 3
+.set SCSI_Noise__SEL__SLW, CYREG_PRT4_SLW
+
/* scsiTarget */
.set scsiTarget_StatusReg__0__MASK, 0x01
.set scsiTarget_StatusReg__0__POS, 0
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
.set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1
.set scsiTarget_StatusReg__2__MASK, 0x04
.set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB04_MSK
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB04_ST
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB11_MSK
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB11_ST
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB11_CTL
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB11_CTL
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB11_MSK
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB11_12_A0
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB11_12_A1
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB11_12_D0
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB11_12_D1
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB11_12_F0
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB11_12_F1
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB11_A0_A1
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB11_A0
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB11_A1
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB11_D0_D1
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB11_D0
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB11_D1
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB11_F0_F1
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB11_F0
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB11_F1
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B1_UDB04_MSK
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B1_UDB04_ST
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB08_MSK
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB08_ST
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB08_CTL
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB08_CTL
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB08_MSK
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB08_09_A0
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB08_09_A1
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB08_09_D0
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB08_09_D1
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB08_09_F0
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB08_09_F1
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB08_A0_A1
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB08_A0
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB08_A1
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB08_D0_D1
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB08_D0
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB08_D1
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB08_F0_F1
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB08_F0
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB08_F1
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
/* USBFS_ep_0 */
.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
/* USBFS_ep_1 */
.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_1__INTC_MASK, 0x20
-.set USBFS_ep_1__INTC_NUMBER, 5
+.set USBFS_ep_1__INTC_MASK, 0x40
+.set USBFS_ep_1__INTC_NUMBER, 6
.set USBFS_ep_1__INTC_PRIOR_NUM, 7
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_5
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_6
.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* USBFS_ep_2 */
.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_2__INTC_MASK, 0x40
-.set USBFS_ep_2__INTC_NUMBER, 6
+.set USBFS_ep_2__INTC_MASK, 0x80
+.set USBFS_ep_2__INTC_NUMBER, 7
.set USBFS_ep_2__INTC_PRIOR_NUM, 7
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_6
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_7
.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* USBFS_ep_3 */
.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_3__INTC_MASK, 0x80
-.set USBFS_ep_3__INTC_NUMBER, 7
+.set USBFS_ep_3__INTC_MASK, 0x100
+.set USBFS_ep_3__INTC_NUMBER, 8
.set USBFS_ep_3__INTC_PRIOR_NUM, 7
-.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_7
+.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_8
.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
.set SD_RX_DMA__DRQ_NUMBER, 2
.set SD_RX_DMA__NUMBEROF_TDS, 0
-.set SD_RX_DMA__PRIORITY, 1
+.set SD_RX_DMA__PRIORITY, 2
.set SD_RX_DMA__TERMIN_EN, 0
.set SD_RX_DMA__TERMIN_SEL, 0
.set SD_RX_DMA__TERMOUT0_EN, 1
.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN
-/* SCSI_ATN */
-.set SCSI_ATN__0__MASK, 0x01
-.set SCSI_ATN__0__PC, CYREG_PRT2_PC0
-.set SCSI_ATN__0__PORT, 2
-.set SCSI_ATN__0__SHIFT, 0
-.set SCSI_ATN__AG, CYREG_PRT2_AG
-.set SCSI_ATN__AMUX, CYREG_PRT2_AMUX
-.set SCSI_ATN__BIE, CYREG_PRT2_BIE
-.set SCSI_ATN__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_ATN__BYP, CYREG_PRT2_BYP
-.set SCSI_ATN__CTL, CYREG_PRT2_CTL
-.set SCSI_ATN__DM0, CYREG_PRT2_DM0
-.set SCSI_ATN__DM1, CYREG_PRT2_DM1
-.set SCSI_ATN__DM2, CYREG_PRT2_DM2
-.set SCSI_ATN__DR, CYREG_PRT2_DR
-.set SCSI_ATN__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_ATN__INT__MASK, 0x01
-.set SCSI_ATN__INT__PC, CYREG_PRT2_PC0
-.set SCSI_ATN__INT__PORT, 2
-.set SCSI_ATN__INT__SHIFT, 0
-.set SCSI_ATN__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_ATN__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_ATN__MASK, 0x01
-.set SCSI_ATN__PORT, 2
-.set SCSI_ATN__PRT, CYREG_PRT2_PRT
-.set SCSI_ATN__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_ATN__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_ATN__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_ATN__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_ATN__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_ATN__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_ATN__PS, CYREG_PRT2_PS
-.set SCSI_ATN__SHIFT, 0
-.set SCSI_ATN__SLW, CYREG_PRT2_SLW
-
/* SCSI_CLK */
.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0
.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1
.set SCSI_Out__SEL__SHIFT, 7
.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW
-/* SCSI_RST */
-.set SCSI_RST__0__MASK, 0x80
-.set SCSI_RST__0__PC, CYREG_PRT4_PC7
-.set SCSI_RST__0__PORT, 4
-.set SCSI_RST__0__SHIFT, 7
-.set SCSI_RST__AG, CYREG_PRT4_AG
-.set SCSI_RST__AMUX, CYREG_PRT4_AMUX
-.set SCSI_RST__BIE, CYREG_PRT4_BIE
-.set SCSI_RST__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_RST__BYP, CYREG_PRT4_BYP
-.set SCSI_RST__CTL, CYREG_PRT4_CTL
-.set SCSI_RST__DM0, CYREG_PRT4_DM0
-.set SCSI_RST__DM1, CYREG_PRT4_DM1
-.set SCSI_RST__DM2, CYREG_PRT4_DM2
-.set SCSI_RST__DR, CYREG_PRT4_DR
-.set SCSI_RST__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_RST__INTSTAT, CYREG_PICU4_INTSTAT
-.set SCSI_RST__INT__MASK, 0x80
-.set SCSI_RST__INT__PC, CYREG_PRT4_PC7
-.set SCSI_RST__INT__PORT, 4
-.set SCSI_RST__INT__SHIFT, 7
-.set SCSI_RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_RST__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_RST__MASK, 0x80
-.set SCSI_RST__PORT, 4
-.set SCSI_RST__PRT, CYREG_PRT4_PRT
-.set SCSI_RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_RST__PS, CYREG_PRT4_PS
-.set SCSI_RST__SHIFT, 7
-.set SCSI_RST__SLW, CYREG_PRT4_SLW
-.set SCSI_RST__SNAP, CYREG_PICU4_SNAP
-
/* USBFS_Dm */
.set USBFS_Dm__0__MASK, 0x80
.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
.set SCSI_In__0__PS, CYREG_PRT2_PS
.set SCSI_In__0__SHIFT, 1
.set SCSI_In__0__SLW, CYREG_PRT2_SLW
-.set SCSI_In__1__AG, CYREG_PRT6_AG
-.set SCSI_In__1__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In__1__BIE, CYREG_PRT6_BIE
-.set SCSI_In__1__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In__1__BYP, CYREG_PRT6_BYP
-.set SCSI_In__1__CTL, CYREG_PRT6_CTL
-.set SCSI_In__1__DM0, CYREG_PRT6_DM0
-.set SCSI_In__1__DM1, CYREG_PRT6_DM1
-.set SCSI_In__1__DM2, CYREG_PRT6_DM2
-.set SCSI_In__1__DR, CYREG_PRT6_DR
-.set SCSI_In__1__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In__1__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In__1__MASK, 0x08
-.set SCSI_In__1__PC, CYREG_PRT6_PC3
-.set SCSI_In__1__PORT, 6
-.set SCSI_In__1__PRT, CYREG_PRT6_PRT
-.set SCSI_In__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In__1__PS, CYREG_PRT6_PS
-.set SCSI_In__1__SHIFT, 3
-.set SCSI_In__1__SLW, CYREG_PRT6_SLW
-.set SCSI_In__2__AG, CYREG_PRT6_AG
-.set SCSI_In__2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In__2__BIE, CYREG_PRT6_BIE
-.set SCSI_In__2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In__2__BYP, CYREG_PRT6_BYP
-.set SCSI_In__2__CTL, CYREG_PRT6_CTL
-.set SCSI_In__2__DM0, CYREG_PRT6_DM0
-.set SCSI_In__2__DM1, CYREG_PRT6_DM1
-.set SCSI_In__2__DM2, CYREG_PRT6_DM2
-.set SCSI_In__2__DR, CYREG_PRT6_DR
-.set SCSI_In__2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In__2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_In__1__AG, CYREG_PRT4_AG
+.set SCSI_In__1__AMUX, CYREG_PRT4_AMUX
+.set SCSI_In__1__BIE, CYREG_PRT4_BIE
+.set SCSI_In__1__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_In__1__BYP, CYREG_PRT4_BYP
+.set SCSI_In__1__CTL, CYREG_PRT4_CTL
+.set SCSI_In__1__DM0, CYREG_PRT4_DM0
+.set SCSI_In__1__DM1, CYREG_PRT4_DM1
+.set SCSI_In__1__DM2, CYREG_PRT4_DM2
+.set SCSI_In__1__DR, CYREG_PRT4_DR
+.set SCSI_In__1__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_In__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_In__1__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_In__1__MASK, 0x40
+.set SCSI_In__1__PC, CYREG_PRT4_PC6
+.set SCSI_In__1__PORT, 4
+.set SCSI_In__1__PRT, CYREG_PRT4_PRT
+.set SCSI_In__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_In__1__PS, CYREG_PRT4_PS
+.set SCSI_In__1__SHIFT, 6
+.set SCSI_In__1__SLW, CYREG_PRT4_SLW
+.set SCSI_In__2__AG, CYREG_PRT4_AG
+.set SCSI_In__2__AMUX, CYREG_PRT4_AMUX
+.set SCSI_In__2__BIE, CYREG_PRT4_BIE
+.set SCSI_In__2__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_In__2__BYP, CYREG_PRT4_BYP
+.set SCSI_In__2__CTL, CYREG_PRT4_CTL
+.set SCSI_In__2__DM0, CYREG_PRT4_DM0
+.set SCSI_In__2__DM1, CYREG_PRT4_DM1
+.set SCSI_In__2__DM2, CYREG_PRT4_DM2
+.set SCSI_In__2__DR, CYREG_PRT4_DR
+.set SCSI_In__2__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_In__2__LCD_EN, CYREG_PRT4_LCD_EN
.set SCSI_In__2__MASK, 0x04
-.set SCSI_In__2__PC, CYREG_PRT6_PC2
-.set SCSI_In__2__PORT, 6
-.set SCSI_In__2__PRT, CYREG_PRT6_PRT
-.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In__2__PS, CYREG_PRT6_PS
+.set SCSI_In__2__PC, CYREG_PRT4_PC2
+.set SCSI_In__2__PORT, 4
+.set SCSI_In__2__PRT, CYREG_PRT4_PRT
+.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_In__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_In__2__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_In__2__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_In__2__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_In__2__PS, CYREG_PRT4_PS
.set SCSI_In__2__SHIFT, 2
-.set SCSI_In__2__SLW, CYREG_PRT6_SLW
-.set SCSI_In__3__AG, CYREG_PRT4_AG
-.set SCSI_In__3__AMUX, CYREG_PRT4_AMUX
-.set SCSI_In__3__BIE, CYREG_PRT4_BIE
-.set SCSI_In__3__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_In__3__BYP, CYREG_PRT4_BYP
-.set SCSI_In__3__CTL, CYREG_PRT4_CTL
-.set SCSI_In__3__DM0, CYREG_PRT4_DM0
-.set SCSI_In__3__DM1, CYREG_PRT4_DM1
-.set SCSI_In__3__DM2, CYREG_PRT4_DM2
-.set SCSI_In__3__DR, CYREG_PRT4_DR
-.set SCSI_In__3__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_In__3__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_In__3__MASK, 0x40
-.set SCSI_In__3__PC, CYREG_PRT4_PC6
-.set SCSI_In__3__PORT, 4
-.set SCSI_In__3__PRT, CYREG_PRT4_PRT
-.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_In__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_In__3__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_In__3__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_In__3__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_In__3__PS, CYREG_PRT4_PS
-.set SCSI_In__3__SHIFT, 6
-.set SCSI_In__3__SLW, CYREG_PRT4_SLW
-.set SCSI_In__4__AG, CYREG_PRT4_AG
-.set SCSI_In__4__AMUX, CYREG_PRT4_AMUX
-.set SCSI_In__4__BIE, CYREG_PRT4_BIE
-.set SCSI_In__4__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_In__4__BYP, CYREG_PRT4_BYP
-.set SCSI_In__4__CTL, CYREG_PRT4_CTL
-.set SCSI_In__4__DM0, CYREG_PRT4_DM0
-.set SCSI_In__4__DM1, CYREG_PRT4_DM1
-.set SCSI_In__4__DM2, CYREG_PRT4_DM2
-.set SCSI_In__4__DR, CYREG_PRT4_DR
-.set SCSI_In__4__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_In__4__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_In__4__MASK, 0x08
-.set SCSI_In__4__PC, CYREG_PRT4_PC3
-.set SCSI_In__4__PORT, 4
-.set SCSI_In__4__PRT, CYREG_PRT4_PRT
-.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_In__4__PS, CYREG_PRT4_PS
-.set SCSI_In__4__SHIFT, 3
-.set SCSI_In__4__SLW, CYREG_PRT4_SLW
-.set SCSI_In__5__AG, CYREG_PRT4_AG
-.set SCSI_In__5__AMUX, CYREG_PRT4_AMUX
-.set SCSI_In__5__BIE, CYREG_PRT4_BIE
-.set SCSI_In__5__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_In__5__BYP, CYREG_PRT4_BYP
-.set SCSI_In__5__CTL, CYREG_PRT4_CTL
-.set SCSI_In__5__DM0, CYREG_PRT4_DM0
-.set SCSI_In__5__DM1, CYREG_PRT4_DM1
-.set SCSI_In__5__DM2, CYREG_PRT4_DM2
-.set SCSI_In__5__DR, CYREG_PRT4_DR
-.set SCSI_In__5__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_In__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_In__5__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_In__5__MASK, 0x04
-.set SCSI_In__5__PC, CYREG_PRT4_PC2
-.set SCSI_In__5__PORT, 4
-.set SCSI_In__5__PRT, CYREG_PRT4_PRT
-.set SCSI_In__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_In__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_In__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_In__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_In__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_In__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_In__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_In__5__PS, CYREG_PRT4_PS
-.set SCSI_In__5__SHIFT, 2
-.set SCSI_In__5__SLW, CYREG_PRT4_SLW
-.set SCSI_In__6__AG, CYREG_PRT0_AG
-.set SCSI_In__6__AMUX, CYREG_PRT0_AMUX
-.set SCSI_In__6__BIE, CYREG_PRT0_BIE
-.set SCSI_In__6__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_In__6__BYP, CYREG_PRT0_BYP
-.set SCSI_In__6__CTL, CYREG_PRT0_CTL
-.set SCSI_In__6__DM0, CYREG_PRT0_DM0
-.set SCSI_In__6__DM1, CYREG_PRT0_DM1
-.set SCSI_In__6__DM2, CYREG_PRT0_DM2
-.set SCSI_In__6__DR, CYREG_PRT0_DR
-.set SCSI_In__6__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_In__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_In__6__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_In__6__MASK, 0x20
-.set SCSI_In__6__PC, CYREG_PRT0_PC5
-.set SCSI_In__6__PORT, 0
-.set SCSI_In__6__PRT, CYREG_PRT0_PRT
-.set SCSI_In__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_In__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_In__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_In__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_In__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_In__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_In__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_In__6__PS, CYREG_PRT0_PS
-.set SCSI_In__6__SHIFT, 5
-.set SCSI_In__6__SLW, CYREG_PRT0_SLW
-.set SCSI_In__7__AG, CYREG_PRT0_AG
-.set SCSI_In__7__AMUX, CYREG_PRT0_AMUX
-.set SCSI_In__7__BIE, CYREG_PRT0_BIE
-.set SCSI_In__7__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_In__7__BYP, CYREG_PRT0_BYP
-.set SCSI_In__7__CTL, CYREG_PRT0_CTL
-.set SCSI_In__7__DM0, CYREG_PRT0_DM0
-.set SCSI_In__7__DM1, CYREG_PRT0_DM1
-.set SCSI_In__7__DM2, CYREG_PRT0_DM2
-.set SCSI_In__7__DR, CYREG_PRT0_DR
-.set SCSI_In__7__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_In__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_In__7__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_In__7__MASK, 0x10
-.set SCSI_In__7__PC, CYREG_PRT0_PC4
-.set SCSI_In__7__PORT, 0
-.set SCSI_In__7__PRT, CYREG_PRT0_PRT
-.set SCSI_In__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_In__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_In__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_In__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_In__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_In__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_In__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_In__7__PS, CYREG_PRT0_PS
-.set SCSI_In__7__SHIFT, 4
-.set SCSI_In__7__SLW, CYREG_PRT0_SLW
-.set SCSI_In__ACK__AG, CYREG_PRT6_AG
-.set SCSI_In__ACK__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In__ACK__BIE, CYREG_PRT6_BIE
-.set SCSI_In__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In__ACK__BYP, CYREG_PRT6_BYP
-.set SCSI_In__ACK__CTL, CYREG_PRT6_CTL
-.set SCSI_In__ACK__DM0, CYREG_PRT6_DM0
-.set SCSI_In__ACK__DM1, CYREG_PRT6_DM1
-.set SCSI_In__ACK__DM2, CYREG_PRT6_DM2
-.set SCSI_In__ACK__DR, CYREG_PRT6_DR
-.set SCSI_In__ACK__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In__ACK__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In__ACK__MASK, 0x04
-.set SCSI_In__ACK__PC, CYREG_PRT6_PC2
-.set SCSI_In__ACK__PORT, 6
-.set SCSI_In__ACK__PRT, CYREG_PRT6_PRT
-.set SCSI_In__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In__ACK__PS, CYREG_PRT6_PS
-.set SCSI_In__ACK__SHIFT, 2
-.set SCSI_In__ACK__SLW, CYREG_PRT6_SLW
-.set SCSI_In__BSY__AG, CYREG_PRT6_AG
-.set SCSI_In__BSY__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In__BSY__BIE, CYREG_PRT6_BIE
-.set SCSI_In__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In__BSY__BYP, CYREG_PRT6_BYP
-.set SCSI_In__BSY__CTL, CYREG_PRT6_CTL
-.set SCSI_In__BSY__DM0, CYREG_PRT6_DM0
-.set SCSI_In__BSY__DM1, CYREG_PRT6_DM1
-.set SCSI_In__BSY__DM2, CYREG_PRT6_DM2
-.set SCSI_In__BSY__DR, CYREG_PRT6_DR
-.set SCSI_In__BSY__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In__BSY__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In__BSY__MASK, 0x08
-.set SCSI_In__BSY__PC, CYREG_PRT6_PC3
-.set SCSI_In__BSY__PORT, 6
-.set SCSI_In__BSY__PRT, CYREG_PRT6_PRT
-.set SCSI_In__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In__BSY__PS, CYREG_PRT6_PS
-.set SCSI_In__BSY__SHIFT, 3
-.set SCSI_In__BSY__SLW, CYREG_PRT6_SLW
+.set SCSI_In__2__SLW, CYREG_PRT4_SLW
+.set SCSI_In__3__AG, CYREG_PRT0_AG
+.set SCSI_In__3__AMUX, CYREG_PRT0_AMUX
+.set SCSI_In__3__BIE, CYREG_PRT0_BIE
+.set SCSI_In__3__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_In__3__BYP, CYREG_PRT0_BYP
+.set SCSI_In__3__CTL, CYREG_PRT0_CTL
+.set SCSI_In__3__DM0, CYREG_PRT0_DM0
+.set SCSI_In__3__DM1, CYREG_PRT0_DM1
+.set SCSI_In__3__DM2, CYREG_PRT0_DM2
+.set SCSI_In__3__DR, CYREG_PRT0_DR
+.set SCSI_In__3__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_In__3__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_In__3__MASK, 0x20
+.set SCSI_In__3__PC, CYREG_PRT0_PC5
+.set SCSI_In__3__PORT, 0
+.set SCSI_In__3__PRT, CYREG_PRT0_PRT
+.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_In__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_In__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_In__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_In__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_In__3__PS, CYREG_PRT0_PS
+.set SCSI_In__3__SHIFT, 5
+.set SCSI_In__3__SLW, CYREG_PRT0_SLW
+.set SCSI_In__4__AG, CYREG_PRT0_AG
+.set SCSI_In__4__AMUX, CYREG_PRT0_AMUX
+.set SCSI_In__4__BIE, CYREG_PRT0_BIE
+.set SCSI_In__4__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_In__4__BYP, CYREG_PRT0_BYP
+.set SCSI_In__4__CTL, CYREG_PRT0_CTL
+.set SCSI_In__4__DM0, CYREG_PRT0_DM0
+.set SCSI_In__4__DM1, CYREG_PRT0_DM1
+.set SCSI_In__4__DM2, CYREG_PRT0_DM2
+.set SCSI_In__4__DR, CYREG_PRT0_DR
+.set SCSI_In__4__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_In__4__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_In__4__MASK, 0x10
+.set SCSI_In__4__PC, CYREG_PRT0_PC4
+.set SCSI_In__4__PORT, 0
+.set SCSI_In__4__PRT, CYREG_PRT0_PRT
+.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_In__4__PS, CYREG_PRT0_PS
+.set SCSI_In__4__SHIFT, 4
+.set SCSI_In__4__SLW, CYREG_PRT0_SLW
.set SCSI_In__CD__AG, CYREG_PRT4_AG
.set SCSI_In__CD__AMUX, CYREG_PRT4_AMUX
.set SCSI_In__CD__BIE, CYREG_PRT4_BIE
.set SCSI_In__REQ__PS, CYREG_PRT0_PS
.set SCSI_In__REQ__SHIFT, 5
.set SCSI_In__REQ__SLW, CYREG_PRT0_SLW
-.set SCSI_In__SEL__AG, CYREG_PRT4_AG
-.set SCSI_In__SEL__AMUX, CYREG_PRT4_AMUX
-.set SCSI_In__SEL__BIE, CYREG_PRT4_BIE
-.set SCSI_In__SEL__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_In__SEL__BYP, CYREG_PRT4_BYP
-.set SCSI_In__SEL__CTL, CYREG_PRT4_CTL
-.set SCSI_In__SEL__DM0, CYREG_PRT4_DM0
-.set SCSI_In__SEL__DM1, CYREG_PRT4_DM1
-.set SCSI_In__SEL__DM2, CYREG_PRT4_DM2
-.set SCSI_In__SEL__DR, CYREG_PRT4_DR
-.set SCSI_In__SEL__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_In__SEL__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_In__SEL__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_In__SEL__MASK, 0x08
-.set SCSI_In__SEL__PC, CYREG_PRT4_PC3
-.set SCSI_In__SEL__PORT, 4
-.set SCSI_In__SEL__PRT, CYREG_PRT4_PRT
-.set SCSI_In__SEL__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_In__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_In__SEL__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_In__SEL__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_In__SEL__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_In__SEL__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_In__SEL__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_In__SEL__PS, CYREG_PRT4_PS
-.set SCSI_In__SEL__SHIFT, 3
-.set SCSI_In__SEL__SLW, CYREG_PRT4_SLW
/* SD_MISO */
.set SD_MISO__0__MASK, 0x02
.set CYDEV_ECC_ENABLE, 0
.set CYDEV_HEAP_SIZE, 0x1000
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1
-.set CYDEV_INTR_RISING, 0x0000001E
+.set CYDEV_INTR_RISING, 0x0000003E
.set CYDEV_PROJ_TYPE, 2
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1
.set CYDEV_PROJ_TYPE_LOADABLE, 2
/* SCSI_TX_DMA_COMPLETE */
SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x04
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 2
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SD_RX_DMA_COMPLETE */
SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x08
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 3
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SD_TX_DMA_COMPLETE */
SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x10
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 4
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
-SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB11_MSK
+SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB11_ST
/* USBFS_bus_reset */
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+
+/* SCSI_Filtered */
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST
/* SCSI_Out_Bits */
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
/* USBFS_arb_int */
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
/* SCSI_Out_Ctl */
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
/* SCSI_Out_DBx */
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
/* SCSI_RST_ISR */
SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RST_ISR__INTC_MASK EQU 0x100
-SCSI_RST_ISR__INTC_NUMBER EQU 8
+SCSI_RST_ISR__INTC_MASK EQU 0x04
+SCSI_RST_ISR__INTC_NUMBER EQU 2
SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB09_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB09_ST
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB09_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB09_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB09_MSK
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
-SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL
-SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB09_10_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB09_10_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB09_10_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB09_10_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB09_10_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB09_10_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB09_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB09_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB09_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB09_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB09_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB09_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB09_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB09_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB09_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB05_06_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB05_06_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB05_06_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB05_06_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB05_06_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB05_06_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB05_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB05_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB05_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB05_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB05_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB05_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB05_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB05_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB05_F1
/* USBFS_dp_int */
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
timer_clock__PM_STBY_MSK EQU 0x04
+/* SCSI_Noise */
+SCSI_Noise__0__AG EQU CYREG_PRT2_AG
+SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE
+SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP
+SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL
+SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0
+SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1
+SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2
+SCSI_Noise__0__DR EQU CYREG_PRT2_DR
+SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Noise__0__MASK EQU 0x01
+SCSI_Noise__0__PC EQU CYREG_PRT2_PC0
+SCSI_Noise__0__PORT EQU 2
+SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT
+SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Noise__0__PS EQU CYREG_PRT2_PS
+SCSI_Noise__0__SHIFT EQU 0
+SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW
+SCSI_Noise__1__AG EQU CYREG_PRT6_AG
+SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__1__DR EQU CYREG_PRT6_DR
+SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__1__MASK EQU 0x08
+SCSI_Noise__1__PC EQU CYREG_PRT6_PC3
+SCSI_Noise__1__PORT EQU 6
+SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__1__PS EQU CYREG_PRT6_PS
+SCSI_Noise__1__SHIFT EQU 3
+SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__2__AG EQU CYREG_PRT4_AG
+SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__2__DR EQU CYREG_PRT4_DR
+SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__2__MASK EQU 0x08
+SCSI_Noise__2__PC EQU CYREG_PRT4_PC3
+SCSI_Noise__2__PORT EQU 4
+SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__2__PS EQU CYREG_PRT4_PS
+SCSI_Noise__2__SHIFT EQU 3
+SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__3__AG EQU CYREG_PRT4_AG
+SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__3__DR EQU CYREG_PRT4_DR
+SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__3__MASK EQU 0x80
+SCSI_Noise__3__PC EQU CYREG_PRT4_PC7
+SCSI_Noise__3__PORT EQU 4
+SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__3__PS EQU CYREG_PRT4_PS
+SCSI_Noise__3__SHIFT EQU 7
+SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__4__AG EQU CYREG_PRT6_AG
+SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__4__DR EQU CYREG_PRT6_DR
+SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__4__MASK EQU 0x04
+SCSI_Noise__4__PC EQU CYREG_PRT6_PC2
+SCSI_Noise__4__PORT EQU 6
+SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__4__PS EQU CYREG_PRT6_PS
+SCSI_Noise__4__SHIFT EQU 2
+SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG
+SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR
+SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__ACK__MASK EQU 0x04
+SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2
+SCSI_Noise__ACK__PORT EQU 6
+SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS
+SCSI_Noise__ACK__SHIFT EQU 2
+SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG
+SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE
+SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP
+SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL
+SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0
+SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1
+SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2
+SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR
+SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Noise__ATN__MASK EQU 0x01
+SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0
+SCSI_Noise__ATN__PORT EQU 2
+SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT
+SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS
+SCSI_Noise__ATN__SHIFT EQU 0
+SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW
+SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG
+SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR
+SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__BSY__MASK EQU 0x08
+SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3
+SCSI_Noise__BSY__PORT EQU 6
+SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS
+SCSI_Noise__BSY__SHIFT EQU 3
+SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__RST__AG EQU CYREG_PRT4_AG
+SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__RST__DR EQU CYREG_PRT4_DR
+SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__RST__MASK EQU 0x80
+SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7
+SCSI_Noise__RST__PORT EQU 4
+SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__RST__PS EQU CYREG_PRT4_PS
+SCSI_Noise__RST__SHIFT EQU 7
+SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG
+SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR
+SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__SEL__MASK EQU 0x08
+SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3
+SCSI_Noise__SEL__PORT EQU 4
+SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS
+SCSI_Noise__SEL__SHIFT EQU 3
+SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW
+
/* scsiTarget */
scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B1_UDB04_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B1_UDB04_ST
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB08_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB08_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB08_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB08_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB08_MSK
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB08_09_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB08_09_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB08_09_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB08_09_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB08_09_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB08_09_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB08_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB08_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB08_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB08_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB08_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB08_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB08_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB08_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB08_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
/* USBFS_ep_0 */
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
/* USBFS_ep_1 */
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x20
-USBFS_ep_1__INTC_NUMBER EQU 5
+USBFS_ep_1__INTC_MASK EQU 0x40
+USBFS_ep_1__INTC_NUMBER EQU 6
USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* USBFS_ep_2 */
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x40
-USBFS_ep_2__INTC_NUMBER EQU 6
+USBFS_ep_2__INTC_MASK EQU 0x80
+USBFS_ep_2__INTC_NUMBER EQU 7
USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* USBFS_ep_3 */
USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_3__INTC_MASK EQU 0x80
-USBFS_ep_3__INTC_NUMBER EQU 7
+USBFS_ep_3__INTC_MASK EQU 0x100
+USBFS_ep_3__INTC_NUMBER EQU 8
USBFS_ep_3__INTC_PRIOR_NUM EQU 7
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
SD_RX_DMA__DRQ_NUMBER EQU 2
SD_RX_DMA__NUMBEROF_TDS EQU 0
-SD_RX_DMA__PRIORITY EQU 1
+SD_RX_DMA__PRIORITY EQU 2
SD_RX_DMA__TERMIN_EN EQU 0
SD_RX_DMA__TERMIN_SEL EQU 0
SD_RX_DMA__TERMOUT0_EN EQU 1
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
-/* SCSI_ATN */
-SCSI_ATN__0__MASK EQU 0x01
-SCSI_ATN__0__PC EQU CYREG_PRT2_PC0
-SCSI_ATN__0__PORT EQU 2
-SCSI_ATN__0__SHIFT EQU 0
-SCSI_ATN__AG EQU CYREG_PRT2_AG
-SCSI_ATN__AMUX EQU CYREG_PRT2_AMUX
-SCSI_ATN__BIE EQU CYREG_PRT2_BIE
-SCSI_ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_ATN__BYP EQU CYREG_PRT2_BYP
-SCSI_ATN__CTL EQU CYREG_PRT2_CTL
-SCSI_ATN__DM0 EQU CYREG_PRT2_DM0
-SCSI_ATN__DM1 EQU CYREG_PRT2_DM1
-SCSI_ATN__DM2 EQU CYREG_PRT2_DM2
-SCSI_ATN__DR EQU CYREG_PRT2_DR
-SCSI_ATN__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_ATN__INT__MASK EQU 0x01
-SCSI_ATN__INT__PC EQU CYREG_PRT2_PC0
-SCSI_ATN__INT__PORT EQU 2
-SCSI_ATN__INT__SHIFT EQU 0
-SCSI_ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_ATN__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_ATN__MASK EQU 0x01
-SCSI_ATN__PORT EQU 2
-SCSI_ATN__PRT EQU CYREG_PRT2_PRT
-SCSI_ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_ATN__PS EQU CYREG_PRT2_PS
-SCSI_ATN__SHIFT EQU 0
-SCSI_ATN__SLW EQU CYREG_PRT2_SLW
-
/* SCSI_CLK */
SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
SCSI_Out__SEL__SHIFT EQU 7
SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
-/* SCSI_RST */
-SCSI_RST__0__MASK EQU 0x80
-SCSI_RST__0__PC EQU CYREG_PRT4_PC7
-SCSI_RST__0__PORT EQU 4
-SCSI_RST__0__SHIFT EQU 7
-SCSI_RST__AG EQU CYREG_PRT4_AG
-SCSI_RST__AMUX EQU CYREG_PRT4_AMUX
-SCSI_RST__BIE EQU CYREG_PRT4_BIE
-SCSI_RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_RST__BYP EQU CYREG_PRT4_BYP
-SCSI_RST__CTL EQU CYREG_PRT4_CTL
-SCSI_RST__DM0 EQU CYREG_PRT4_DM0
-SCSI_RST__DM1 EQU CYREG_PRT4_DM1
-SCSI_RST__DM2 EQU CYREG_PRT4_DM2
-SCSI_RST__DR EQU CYREG_PRT4_DR
-SCSI_RST__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_RST__INTSTAT EQU CYREG_PICU4_INTSTAT
-SCSI_RST__INT__MASK EQU 0x80
-SCSI_RST__INT__PC EQU CYREG_PRT4_PC7
-SCSI_RST__INT__PORT EQU 4
-SCSI_RST__INT__SHIFT EQU 7
-SCSI_RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_RST__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_RST__MASK EQU 0x80
-SCSI_RST__PORT EQU 4
-SCSI_RST__PRT EQU CYREG_PRT4_PRT
-SCSI_RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_RST__PS EQU CYREG_PRT4_PS
-SCSI_RST__SHIFT EQU 7
-SCSI_RST__SLW EQU CYREG_PRT4_SLW
-SCSI_RST__SNAP EQU CYREG_PICU4_SNAP
-
/* USBFS_Dm */
USBFS_Dm__0__MASK EQU 0x80
USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
SCSI_In__0__PS EQU CYREG_PRT2_PS
SCSI_In__0__SHIFT EQU 1
SCSI_In__0__SLW EQU CYREG_PRT2_SLW
-SCSI_In__1__AG EQU CYREG_PRT6_AG
-SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In__1__BIE EQU CYREG_PRT6_BIE
-SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In__1__BYP EQU CYREG_PRT6_BYP
-SCSI_In__1__CTL EQU CYREG_PRT6_CTL
-SCSI_In__1__DM0 EQU CYREG_PRT6_DM0
-SCSI_In__1__DM1 EQU CYREG_PRT6_DM1
-SCSI_In__1__DM2 EQU CYREG_PRT6_DM2
-SCSI_In__1__DR EQU CYREG_PRT6_DR
-SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In__1__MASK EQU 0x08
-SCSI_In__1__PC EQU CYREG_PRT6_PC3
-SCSI_In__1__PORT EQU 6
-SCSI_In__1__PRT EQU CYREG_PRT6_PRT
-SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In__1__PS EQU CYREG_PRT6_PS
-SCSI_In__1__SHIFT EQU 3
-SCSI_In__1__SLW EQU CYREG_PRT6_SLW
-SCSI_In__2__AG EQU CYREG_PRT6_AG
-SCSI_In__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In__2__BIE EQU CYREG_PRT6_BIE
-SCSI_In__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In__2__BYP EQU CYREG_PRT6_BYP
-SCSI_In__2__CTL EQU CYREG_PRT6_CTL
-SCSI_In__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_In__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_In__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_In__2__DR EQU CYREG_PRT6_DR
-SCSI_In__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In__1__AG EQU CYREG_PRT4_AG
+SCSI_In__1__AMUX EQU CYREG_PRT4_AMUX
+SCSI_In__1__BIE EQU CYREG_PRT4_BIE
+SCSI_In__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_In__1__BYP EQU CYREG_PRT4_BYP
+SCSI_In__1__CTL EQU CYREG_PRT4_CTL
+SCSI_In__1__DM0 EQU CYREG_PRT4_DM0
+SCSI_In__1__DM1 EQU CYREG_PRT4_DM1
+SCSI_In__1__DM2 EQU CYREG_PRT4_DM2
+SCSI_In__1__DR EQU CYREG_PRT4_DR
+SCSI_In__1__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_In__1__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_In__1__MASK EQU 0x40
+SCSI_In__1__PC EQU CYREG_PRT4_PC6
+SCSI_In__1__PORT EQU 4
+SCSI_In__1__PRT EQU CYREG_PRT4_PRT
+SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_In__1__PS EQU CYREG_PRT4_PS
+SCSI_In__1__SHIFT EQU 6
+SCSI_In__1__SLW EQU CYREG_PRT4_SLW
+SCSI_In__2__AG EQU CYREG_PRT4_AG
+SCSI_In__2__AMUX EQU CYREG_PRT4_AMUX
+SCSI_In__2__BIE EQU CYREG_PRT4_BIE
+SCSI_In__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_In__2__BYP EQU CYREG_PRT4_BYP
+SCSI_In__2__CTL EQU CYREG_PRT4_CTL
+SCSI_In__2__DM0 EQU CYREG_PRT4_DM0
+SCSI_In__2__DM1 EQU CYREG_PRT4_DM1
+SCSI_In__2__DM2 EQU CYREG_PRT4_DM2
+SCSI_In__2__DR EQU CYREG_PRT4_DR
+SCSI_In__2__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_In__2__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_In__2__MASK EQU 0x04
-SCSI_In__2__PC EQU CYREG_PRT6_PC2
-SCSI_In__2__PORT EQU 6
-SCSI_In__2__PRT EQU CYREG_PRT6_PRT
-SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In__2__PS EQU CYREG_PRT6_PS
+SCSI_In__2__PC EQU CYREG_PRT4_PC2
+SCSI_In__2__PORT EQU 4
+SCSI_In__2__PRT EQU CYREG_PRT4_PRT
+SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_In__2__PS EQU CYREG_PRT4_PS
SCSI_In__2__SHIFT EQU 2
-SCSI_In__2__SLW EQU CYREG_PRT6_SLW
-SCSI_In__3__AG EQU CYREG_PRT4_AG
-SCSI_In__3__AMUX EQU CYREG_PRT4_AMUX
-SCSI_In__3__BIE EQU CYREG_PRT4_BIE
-SCSI_In__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_In__3__BYP EQU CYREG_PRT4_BYP
-SCSI_In__3__CTL EQU CYREG_PRT4_CTL
-SCSI_In__3__DM0 EQU CYREG_PRT4_DM0
-SCSI_In__3__DM1 EQU CYREG_PRT4_DM1
-SCSI_In__3__DM2 EQU CYREG_PRT4_DM2
-SCSI_In__3__DR EQU CYREG_PRT4_DR
-SCSI_In__3__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_In__3__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_In__3__MASK EQU 0x40
-SCSI_In__3__PC EQU CYREG_PRT4_PC6
-SCSI_In__3__PORT EQU 4
-SCSI_In__3__PRT EQU CYREG_PRT4_PRT
-SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_In__3__PS EQU CYREG_PRT4_PS
-SCSI_In__3__SHIFT EQU 6
-SCSI_In__3__SLW EQU CYREG_PRT4_SLW
-SCSI_In__4__AG EQU CYREG_PRT4_AG
-SCSI_In__4__AMUX EQU CYREG_PRT4_AMUX
-SCSI_In__4__BIE EQU CYREG_PRT4_BIE
-SCSI_In__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_In__4__BYP EQU CYREG_PRT4_BYP
-SCSI_In__4__CTL EQU CYREG_PRT4_CTL
-SCSI_In__4__DM0 EQU CYREG_PRT4_DM0
-SCSI_In__4__DM1 EQU CYREG_PRT4_DM1
-SCSI_In__4__DM2 EQU CYREG_PRT4_DM2
-SCSI_In__4__DR EQU CYREG_PRT4_DR
-SCSI_In__4__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_In__4__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_In__4__MASK EQU 0x08
-SCSI_In__4__PC EQU CYREG_PRT4_PC3
-SCSI_In__4__PORT EQU 4
-SCSI_In__4__PRT EQU CYREG_PRT4_PRT
-SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_In__4__PS EQU CYREG_PRT4_PS
-SCSI_In__4__SHIFT EQU 3
-SCSI_In__4__SLW EQU CYREG_PRT4_SLW
-SCSI_In__5__AG EQU CYREG_PRT4_AG
-SCSI_In__5__AMUX EQU CYREG_PRT4_AMUX
-SCSI_In__5__BIE EQU CYREG_PRT4_BIE
-SCSI_In__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_In__5__BYP EQU CYREG_PRT4_BYP
-SCSI_In__5__CTL EQU CYREG_PRT4_CTL
-SCSI_In__5__DM0 EQU CYREG_PRT4_DM0
-SCSI_In__5__DM1 EQU CYREG_PRT4_DM1
-SCSI_In__5__DM2 EQU CYREG_PRT4_DM2
-SCSI_In__5__DR EQU CYREG_PRT4_DR
-SCSI_In__5__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_In__5__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_In__5__MASK EQU 0x04
-SCSI_In__5__PC EQU CYREG_PRT4_PC2
-SCSI_In__5__PORT EQU 4
-SCSI_In__5__PRT EQU CYREG_PRT4_PRT
-SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_In__5__PS EQU CYREG_PRT4_PS
-SCSI_In__5__SHIFT EQU 2
-SCSI_In__5__SLW EQU CYREG_PRT4_SLW
-SCSI_In__6__AG EQU CYREG_PRT0_AG
-SCSI_In__6__AMUX EQU CYREG_PRT0_AMUX
-SCSI_In__6__BIE EQU CYREG_PRT0_BIE
-SCSI_In__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_In__6__BYP EQU CYREG_PRT0_BYP
-SCSI_In__6__CTL EQU CYREG_PRT0_CTL
-SCSI_In__6__DM0 EQU CYREG_PRT0_DM0
-SCSI_In__6__DM1 EQU CYREG_PRT0_DM1
-SCSI_In__6__DM2 EQU CYREG_PRT0_DM2
-SCSI_In__6__DR EQU CYREG_PRT0_DR
-SCSI_In__6__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_In__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_In__6__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_In__6__MASK EQU 0x20
-SCSI_In__6__PC EQU CYREG_PRT0_PC5
-SCSI_In__6__PORT EQU 0
-SCSI_In__6__PRT EQU CYREG_PRT0_PRT
-SCSI_In__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_In__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_In__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_In__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_In__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_In__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_In__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_In__6__PS EQU CYREG_PRT0_PS
-SCSI_In__6__SHIFT EQU 5
-SCSI_In__6__SLW EQU CYREG_PRT0_SLW
-SCSI_In__7__AG EQU CYREG_PRT0_AG
-SCSI_In__7__AMUX EQU CYREG_PRT0_AMUX
-SCSI_In__7__BIE EQU CYREG_PRT0_BIE
-SCSI_In__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_In__7__BYP EQU CYREG_PRT0_BYP
-SCSI_In__7__CTL EQU CYREG_PRT0_CTL
-SCSI_In__7__DM0 EQU CYREG_PRT0_DM0
-SCSI_In__7__DM1 EQU CYREG_PRT0_DM1
-SCSI_In__7__DM2 EQU CYREG_PRT0_DM2
-SCSI_In__7__DR EQU CYREG_PRT0_DR
-SCSI_In__7__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_In__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_In__7__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_In__7__MASK EQU 0x10
-SCSI_In__7__PC EQU CYREG_PRT0_PC4
-SCSI_In__7__PORT EQU 0
-SCSI_In__7__PRT EQU CYREG_PRT0_PRT
-SCSI_In__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_In__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_In__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_In__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_In__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_In__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_In__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_In__7__PS EQU CYREG_PRT0_PS
-SCSI_In__7__SHIFT EQU 4
-SCSI_In__7__SLW EQU CYREG_PRT0_SLW
-SCSI_In__ACK__AG EQU CYREG_PRT6_AG
-SCSI_In__ACK__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In__ACK__BIE EQU CYREG_PRT6_BIE
-SCSI_In__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In__ACK__BYP EQU CYREG_PRT6_BYP
-SCSI_In__ACK__CTL EQU CYREG_PRT6_CTL
-SCSI_In__ACK__DM0 EQU CYREG_PRT6_DM0
-SCSI_In__ACK__DM1 EQU CYREG_PRT6_DM1
-SCSI_In__ACK__DM2 EQU CYREG_PRT6_DM2
-SCSI_In__ACK__DR EQU CYREG_PRT6_DR
-SCSI_In__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In__ACK__MASK EQU 0x04
-SCSI_In__ACK__PC EQU CYREG_PRT6_PC2
-SCSI_In__ACK__PORT EQU 6
-SCSI_In__ACK__PRT EQU CYREG_PRT6_PRT
-SCSI_In__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In__ACK__PS EQU CYREG_PRT6_PS
-SCSI_In__ACK__SHIFT EQU 2
-SCSI_In__ACK__SLW EQU CYREG_PRT6_SLW
-SCSI_In__BSY__AG EQU CYREG_PRT6_AG
-SCSI_In__BSY__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In__BSY__BIE EQU CYREG_PRT6_BIE
-SCSI_In__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In__BSY__BYP EQU CYREG_PRT6_BYP
-SCSI_In__BSY__CTL EQU CYREG_PRT6_CTL
-SCSI_In__BSY__DM0 EQU CYREG_PRT6_DM0
-SCSI_In__BSY__DM1 EQU CYREG_PRT6_DM1
-SCSI_In__BSY__DM2 EQU CYREG_PRT6_DM2
-SCSI_In__BSY__DR EQU CYREG_PRT6_DR
-SCSI_In__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In__BSY__MASK EQU 0x08
-SCSI_In__BSY__PC EQU CYREG_PRT6_PC3
-SCSI_In__BSY__PORT EQU 6
-SCSI_In__BSY__PRT EQU CYREG_PRT6_PRT
-SCSI_In__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In__BSY__PS EQU CYREG_PRT6_PS
-SCSI_In__BSY__SHIFT EQU 3
-SCSI_In__BSY__SLW EQU CYREG_PRT6_SLW
+SCSI_In__2__SLW EQU CYREG_PRT4_SLW
+SCSI_In__3__AG EQU CYREG_PRT0_AG
+SCSI_In__3__AMUX EQU CYREG_PRT0_AMUX
+SCSI_In__3__BIE EQU CYREG_PRT0_BIE
+SCSI_In__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_In__3__BYP EQU CYREG_PRT0_BYP
+SCSI_In__3__CTL EQU CYREG_PRT0_CTL
+SCSI_In__3__DM0 EQU CYREG_PRT0_DM0
+SCSI_In__3__DM1 EQU CYREG_PRT0_DM1
+SCSI_In__3__DM2 EQU CYREG_PRT0_DM2
+SCSI_In__3__DR EQU CYREG_PRT0_DR
+SCSI_In__3__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_In__3__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_In__3__MASK EQU 0x20
+SCSI_In__3__PC EQU CYREG_PRT0_PC5
+SCSI_In__3__PORT EQU 0
+SCSI_In__3__PRT EQU CYREG_PRT0_PRT
+SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_In__3__PS EQU CYREG_PRT0_PS
+SCSI_In__3__SHIFT EQU 5
+SCSI_In__3__SLW EQU CYREG_PRT0_SLW
+SCSI_In__4__AG EQU CYREG_PRT0_AG
+SCSI_In__4__AMUX EQU CYREG_PRT0_AMUX
+SCSI_In__4__BIE EQU CYREG_PRT0_BIE
+SCSI_In__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_In__4__BYP EQU CYREG_PRT0_BYP
+SCSI_In__4__CTL EQU CYREG_PRT0_CTL
+SCSI_In__4__DM0 EQU CYREG_PRT0_DM0
+SCSI_In__4__DM1 EQU CYREG_PRT0_DM1
+SCSI_In__4__DM2 EQU CYREG_PRT0_DM2
+SCSI_In__4__DR EQU CYREG_PRT0_DR
+SCSI_In__4__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_In__4__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_In__4__MASK EQU 0x10
+SCSI_In__4__PC EQU CYREG_PRT0_PC4
+SCSI_In__4__PORT EQU 0
+SCSI_In__4__PRT EQU CYREG_PRT0_PRT
+SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_In__4__PS EQU CYREG_PRT0_PS
+SCSI_In__4__SHIFT EQU 4
+SCSI_In__4__SLW EQU CYREG_PRT0_SLW
SCSI_In__CD__AG EQU CYREG_PRT4_AG
SCSI_In__CD__AMUX EQU CYREG_PRT4_AMUX
SCSI_In__CD__BIE EQU CYREG_PRT4_BIE
SCSI_In__REQ__PS EQU CYREG_PRT0_PS
SCSI_In__REQ__SHIFT EQU 5
SCSI_In__REQ__SLW EQU CYREG_PRT0_SLW
-SCSI_In__SEL__AG EQU CYREG_PRT4_AG
-SCSI_In__SEL__AMUX EQU CYREG_PRT4_AMUX
-SCSI_In__SEL__BIE EQU CYREG_PRT4_BIE
-SCSI_In__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_In__SEL__BYP EQU CYREG_PRT4_BYP
-SCSI_In__SEL__CTL EQU CYREG_PRT4_CTL
-SCSI_In__SEL__DM0 EQU CYREG_PRT4_DM0
-SCSI_In__SEL__DM1 EQU CYREG_PRT4_DM1
-SCSI_In__SEL__DM2 EQU CYREG_PRT4_DM2
-SCSI_In__SEL__DR EQU CYREG_PRT4_DR
-SCSI_In__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_In__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_In__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_In__SEL__MASK EQU 0x08
-SCSI_In__SEL__PC EQU CYREG_PRT4_PC3
-SCSI_In__SEL__PORT EQU 4
-SCSI_In__SEL__PRT EQU CYREG_PRT4_PRT
-SCSI_In__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_In__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_In__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_In__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_In__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_In__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_In__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_In__SEL__PS EQU CYREG_PRT4_PS
-SCSI_In__SEL__SHIFT EQU 3
-SCSI_In__SEL__SLW EQU CYREG_PRT4_SLW
/* SD_MISO */
SD_MISO__0__MASK EQU 0x02
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x1000
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
-CYDEV_INTR_RISING EQU 0x0000001E
+CYDEV_INTR_RISING EQU 0x0000003E
CYDEV_PROJ_TYPE EQU 2
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LOADABLE EQU 2
; SCSI_TX_DMA_COMPLETE
SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x04
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 2
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SD_RX_DMA_COMPLETE
SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x08
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 3
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SD_TX_DMA_COMPLETE
SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x10
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 4
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
-SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB11_MSK
+SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB11_ST
; USBFS_bus_reset
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+
+; SCSI_Filtered
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB13_MSK
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB13_ST
; SCSI_Out_Bits
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
; USBFS_arb_int
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
; SCSI_Out_Ctl
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
; SCSI_Out_DBx
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
; SCSI_RST_ISR
SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RST_ISR__INTC_MASK EQU 0x100
-SCSI_RST_ISR__INTC_NUMBER EQU 8
+SCSI_RST_ISR__INTC_MASK EQU 0x04
+SCSI_RST_ISR__INTC_NUMBER EQU 2
SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SDCard_BSPIM
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB09_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB09_ST
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB09_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB09_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB09_MSK
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
-SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL
-SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB09_10_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB09_10_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB09_10_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB09_10_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB09_10_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB09_10_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB09_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB09_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB09_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB09_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB09_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB09_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB09_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB09_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB09_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB05_06_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB05_06_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB05_06_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB05_06_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB05_06_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB05_06_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB05_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB05_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB05_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB05_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB05_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB05_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB05_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB05_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB05_F1
; USBFS_dp_int
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
timer_clock__PM_STBY_MSK EQU 0x04
+; SCSI_Noise
+SCSI_Noise__0__AG EQU CYREG_PRT2_AG
+SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE
+SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP
+SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL
+SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0
+SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1
+SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2
+SCSI_Noise__0__DR EQU CYREG_PRT2_DR
+SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Noise__0__MASK EQU 0x01
+SCSI_Noise__0__PC EQU CYREG_PRT2_PC0
+SCSI_Noise__0__PORT EQU 2
+SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT
+SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Noise__0__PS EQU CYREG_PRT2_PS
+SCSI_Noise__0__SHIFT EQU 0
+SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW
+SCSI_Noise__1__AG EQU CYREG_PRT6_AG
+SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__1__DR EQU CYREG_PRT6_DR
+SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__1__MASK EQU 0x08
+SCSI_Noise__1__PC EQU CYREG_PRT6_PC3
+SCSI_Noise__1__PORT EQU 6
+SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__1__PS EQU CYREG_PRT6_PS
+SCSI_Noise__1__SHIFT EQU 3
+SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__2__AG EQU CYREG_PRT4_AG
+SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__2__DR EQU CYREG_PRT4_DR
+SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__2__MASK EQU 0x08
+SCSI_Noise__2__PC EQU CYREG_PRT4_PC3
+SCSI_Noise__2__PORT EQU 4
+SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__2__PS EQU CYREG_PRT4_PS
+SCSI_Noise__2__SHIFT EQU 3
+SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__3__AG EQU CYREG_PRT4_AG
+SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__3__DR EQU CYREG_PRT4_DR
+SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__3__MASK EQU 0x80
+SCSI_Noise__3__PC EQU CYREG_PRT4_PC7
+SCSI_Noise__3__PORT EQU 4
+SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__3__PS EQU CYREG_PRT4_PS
+SCSI_Noise__3__SHIFT EQU 7
+SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__4__AG EQU CYREG_PRT6_AG
+SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__4__DR EQU CYREG_PRT6_DR
+SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__4__MASK EQU 0x04
+SCSI_Noise__4__PC EQU CYREG_PRT6_PC2
+SCSI_Noise__4__PORT EQU 6
+SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__4__PS EQU CYREG_PRT6_PS
+SCSI_Noise__4__SHIFT EQU 2
+SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG
+SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR
+SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__ACK__MASK EQU 0x04
+SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2
+SCSI_Noise__ACK__PORT EQU 6
+SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS
+SCSI_Noise__ACK__SHIFT EQU 2
+SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG
+SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE
+SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP
+SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL
+SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0
+SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1
+SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2
+SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR
+SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Noise__ATN__MASK EQU 0x01
+SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0
+SCSI_Noise__ATN__PORT EQU 2
+SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT
+SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS
+SCSI_Noise__ATN__SHIFT EQU 0
+SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW
+SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG
+SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR
+SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__BSY__MASK EQU 0x08
+SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3
+SCSI_Noise__BSY__PORT EQU 6
+SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS
+SCSI_Noise__BSY__SHIFT EQU 3
+SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__RST__AG EQU CYREG_PRT4_AG
+SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__RST__DR EQU CYREG_PRT4_DR
+SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__RST__MASK EQU 0x80
+SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7
+SCSI_Noise__RST__PORT EQU 4
+SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__RST__PS EQU CYREG_PRT4_PS
+SCSI_Noise__RST__SHIFT EQU 7
+SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG
+SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR
+SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__SEL__MASK EQU 0x08
+SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3
+SCSI_Noise__SEL__PORT EQU 4
+SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS
+SCSI_Noise__SEL__SHIFT EQU 3
+SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW
+
; scsiTarget
scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B1_UDB04_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B1_UDB04_ST
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB08_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB08_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB08_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB08_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB08_MSK
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB08_09_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB08_09_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB08_09_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB08_09_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB08_09_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB08_09_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB08_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB08_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB08_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB08_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB08_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB08_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB08_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB08_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB08_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
; USBFS_ep_0
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
; USBFS_ep_1
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x20
-USBFS_ep_1__INTC_NUMBER EQU 5
+USBFS_ep_1__INTC_MASK EQU 0x40
+USBFS_ep_1__INTC_NUMBER EQU 6
USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; USBFS_ep_2
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x40
-USBFS_ep_2__INTC_NUMBER EQU 6
+USBFS_ep_2__INTC_MASK EQU 0x80
+USBFS_ep_2__INTC_NUMBER EQU 7
USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; USBFS_ep_3
USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_3__INTC_MASK EQU 0x80
-USBFS_ep_3__INTC_NUMBER EQU 7
+USBFS_ep_3__INTC_MASK EQU 0x100
+USBFS_ep_3__INTC_NUMBER EQU 8
USBFS_ep_3__INTC_PRIOR_NUM EQU 7
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
SD_RX_DMA__DRQ_NUMBER EQU 2
SD_RX_DMA__NUMBEROF_TDS EQU 0
-SD_RX_DMA__PRIORITY EQU 1
+SD_RX_DMA__PRIORITY EQU 2
SD_RX_DMA__TERMIN_EN EQU 0
SD_RX_DMA__TERMIN_SEL EQU 0
SD_RX_DMA__TERMOUT0_EN EQU 1
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
-; SCSI_ATN
-SCSI_ATN__0__MASK EQU 0x01
-SCSI_ATN__0__PC EQU CYREG_PRT2_PC0
-SCSI_ATN__0__PORT EQU 2
-SCSI_ATN__0__SHIFT EQU 0
-SCSI_ATN__AG EQU CYREG_PRT2_AG
-SCSI_ATN__AMUX EQU CYREG_PRT2_AMUX
-SCSI_ATN__BIE EQU CYREG_PRT2_BIE
-SCSI_ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_ATN__BYP EQU CYREG_PRT2_BYP
-SCSI_ATN__CTL EQU CYREG_PRT2_CTL
-SCSI_ATN__DM0 EQU CYREG_PRT2_DM0
-SCSI_ATN__DM1 EQU CYREG_PRT2_DM1
-SCSI_ATN__DM2 EQU CYREG_PRT2_DM2
-SCSI_ATN__DR EQU CYREG_PRT2_DR
-SCSI_ATN__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_ATN__INT__MASK EQU 0x01
-SCSI_ATN__INT__PC EQU CYREG_PRT2_PC0
-SCSI_ATN__INT__PORT EQU 2
-SCSI_ATN__INT__SHIFT EQU 0
-SCSI_ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_ATN__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_ATN__MASK EQU 0x01
-SCSI_ATN__PORT EQU 2
-SCSI_ATN__PRT EQU CYREG_PRT2_PRT
-SCSI_ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_ATN__PS EQU CYREG_PRT2_PS
-SCSI_ATN__SHIFT EQU 0
-SCSI_ATN__SLW EQU CYREG_PRT2_SLW
-
; SCSI_CLK
SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
SCSI_Out__SEL__SHIFT EQU 7
SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
-; SCSI_RST
-SCSI_RST__0__MASK EQU 0x80
-SCSI_RST__0__PC EQU CYREG_PRT4_PC7
-SCSI_RST__0__PORT EQU 4
-SCSI_RST__0__SHIFT EQU 7
-SCSI_RST__AG EQU CYREG_PRT4_AG
-SCSI_RST__AMUX EQU CYREG_PRT4_AMUX
-SCSI_RST__BIE EQU CYREG_PRT4_BIE
-SCSI_RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_RST__BYP EQU CYREG_PRT4_BYP
-SCSI_RST__CTL EQU CYREG_PRT4_CTL
-SCSI_RST__DM0 EQU CYREG_PRT4_DM0
-SCSI_RST__DM1 EQU CYREG_PRT4_DM1
-SCSI_RST__DM2 EQU CYREG_PRT4_DM2
-SCSI_RST__DR EQU CYREG_PRT4_DR
-SCSI_RST__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_RST__INTSTAT EQU CYREG_PICU4_INTSTAT
-SCSI_RST__INT__MASK EQU 0x80
-SCSI_RST__INT__PC EQU CYREG_PRT4_PC7
-SCSI_RST__INT__PORT EQU 4
-SCSI_RST__INT__SHIFT EQU 7
-SCSI_RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_RST__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_RST__MASK EQU 0x80
-SCSI_RST__PORT EQU 4
-SCSI_RST__PRT EQU CYREG_PRT4_PRT
-SCSI_RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_RST__PS EQU CYREG_PRT4_PS
-SCSI_RST__SHIFT EQU 7
-SCSI_RST__SLW EQU CYREG_PRT4_SLW
-SCSI_RST__SNAP EQU CYREG_PICU4_SNAP
-
; USBFS_Dm
USBFS_Dm__0__MASK EQU 0x80
USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
SCSI_In__0__PS EQU CYREG_PRT2_PS
SCSI_In__0__SHIFT EQU 1
SCSI_In__0__SLW EQU CYREG_PRT2_SLW
-SCSI_In__1__AG EQU CYREG_PRT6_AG
-SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In__1__BIE EQU CYREG_PRT6_BIE
-SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In__1__BYP EQU CYREG_PRT6_BYP
-SCSI_In__1__CTL EQU CYREG_PRT6_CTL
-SCSI_In__1__DM0 EQU CYREG_PRT6_DM0
-SCSI_In__1__DM1 EQU CYREG_PRT6_DM1
-SCSI_In__1__DM2 EQU CYREG_PRT6_DM2
-SCSI_In__1__DR EQU CYREG_PRT6_DR
-SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In__1__MASK EQU 0x08
-SCSI_In__1__PC EQU CYREG_PRT6_PC3
-SCSI_In__1__PORT EQU 6
-SCSI_In__1__PRT EQU CYREG_PRT6_PRT
-SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In__1__PS EQU CYREG_PRT6_PS
-SCSI_In__1__SHIFT EQU 3
-SCSI_In__1__SLW EQU CYREG_PRT6_SLW
-SCSI_In__2__AG EQU CYREG_PRT6_AG
-SCSI_In__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In__2__BIE EQU CYREG_PRT6_BIE
-SCSI_In__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In__2__BYP EQU CYREG_PRT6_BYP
-SCSI_In__2__CTL EQU CYREG_PRT6_CTL
-SCSI_In__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_In__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_In__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_In__2__DR EQU CYREG_PRT6_DR
-SCSI_In__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In__1__AG EQU CYREG_PRT4_AG
+SCSI_In__1__AMUX EQU CYREG_PRT4_AMUX
+SCSI_In__1__BIE EQU CYREG_PRT4_BIE
+SCSI_In__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_In__1__BYP EQU CYREG_PRT4_BYP
+SCSI_In__1__CTL EQU CYREG_PRT4_CTL
+SCSI_In__1__DM0 EQU CYREG_PRT4_DM0
+SCSI_In__1__DM1 EQU CYREG_PRT4_DM1
+SCSI_In__1__DM2 EQU CYREG_PRT4_DM2
+SCSI_In__1__DR EQU CYREG_PRT4_DR
+SCSI_In__1__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_In__1__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_In__1__MASK EQU 0x40
+SCSI_In__1__PC EQU CYREG_PRT4_PC6
+SCSI_In__1__PORT EQU 4
+SCSI_In__1__PRT EQU CYREG_PRT4_PRT
+SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_In__1__PS EQU CYREG_PRT4_PS
+SCSI_In__1__SHIFT EQU 6
+SCSI_In__1__SLW EQU CYREG_PRT4_SLW
+SCSI_In__2__AG EQU CYREG_PRT4_AG
+SCSI_In__2__AMUX EQU CYREG_PRT4_AMUX
+SCSI_In__2__BIE EQU CYREG_PRT4_BIE
+SCSI_In__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_In__2__BYP EQU CYREG_PRT4_BYP
+SCSI_In__2__CTL EQU CYREG_PRT4_CTL
+SCSI_In__2__DM0 EQU CYREG_PRT4_DM0
+SCSI_In__2__DM1 EQU CYREG_PRT4_DM1
+SCSI_In__2__DM2 EQU CYREG_PRT4_DM2
+SCSI_In__2__DR EQU CYREG_PRT4_DR
+SCSI_In__2__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_In__2__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_In__2__MASK EQU 0x04
-SCSI_In__2__PC EQU CYREG_PRT6_PC2
-SCSI_In__2__PORT EQU 6
-SCSI_In__2__PRT EQU CYREG_PRT6_PRT
-SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In__2__PS EQU CYREG_PRT6_PS
+SCSI_In__2__PC EQU CYREG_PRT4_PC2
+SCSI_In__2__PORT EQU 4
+SCSI_In__2__PRT EQU CYREG_PRT4_PRT
+SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_In__2__PS EQU CYREG_PRT4_PS
SCSI_In__2__SHIFT EQU 2
-SCSI_In__2__SLW EQU CYREG_PRT6_SLW
-SCSI_In__3__AG EQU CYREG_PRT4_AG
-SCSI_In__3__AMUX EQU CYREG_PRT4_AMUX
-SCSI_In__3__BIE EQU CYREG_PRT4_BIE
-SCSI_In__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_In__3__BYP EQU CYREG_PRT4_BYP
-SCSI_In__3__CTL EQU CYREG_PRT4_CTL
-SCSI_In__3__DM0 EQU CYREG_PRT4_DM0
-SCSI_In__3__DM1 EQU CYREG_PRT4_DM1
-SCSI_In__3__DM2 EQU CYREG_PRT4_DM2
-SCSI_In__3__DR EQU CYREG_PRT4_DR
-SCSI_In__3__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_In__3__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_In__3__MASK EQU 0x40
-SCSI_In__3__PC EQU CYREG_PRT4_PC6
-SCSI_In__3__PORT EQU 4
-SCSI_In__3__PRT EQU CYREG_PRT4_PRT
-SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_In__3__PS EQU CYREG_PRT4_PS
-SCSI_In__3__SHIFT EQU 6
-SCSI_In__3__SLW EQU CYREG_PRT4_SLW
-SCSI_In__4__AG EQU CYREG_PRT4_AG
-SCSI_In__4__AMUX EQU CYREG_PRT4_AMUX
-SCSI_In__4__BIE EQU CYREG_PRT4_BIE
-SCSI_In__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_In__4__BYP EQU CYREG_PRT4_BYP
-SCSI_In__4__CTL EQU CYREG_PRT4_CTL
-SCSI_In__4__DM0 EQU CYREG_PRT4_DM0
-SCSI_In__4__DM1 EQU CYREG_PRT4_DM1
-SCSI_In__4__DM2 EQU CYREG_PRT4_DM2
-SCSI_In__4__DR EQU CYREG_PRT4_DR
-SCSI_In__4__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_In__4__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_In__4__MASK EQU 0x08
-SCSI_In__4__PC EQU CYREG_PRT4_PC3
-SCSI_In__4__PORT EQU 4
-SCSI_In__4__PRT EQU CYREG_PRT4_PRT
-SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_In__4__PS EQU CYREG_PRT4_PS
-SCSI_In__4__SHIFT EQU 3
-SCSI_In__4__SLW EQU CYREG_PRT4_SLW
-SCSI_In__5__AG EQU CYREG_PRT4_AG
-SCSI_In__5__AMUX EQU CYREG_PRT4_AMUX
-SCSI_In__5__BIE EQU CYREG_PRT4_BIE
-SCSI_In__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_In__5__BYP EQU CYREG_PRT4_BYP
-SCSI_In__5__CTL EQU CYREG_PRT4_CTL
-SCSI_In__5__DM0 EQU CYREG_PRT4_DM0
-SCSI_In__5__DM1 EQU CYREG_PRT4_DM1
-SCSI_In__5__DM2 EQU CYREG_PRT4_DM2
-SCSI_In__5__DR EQU CYREG_PRT4_DR
-SCSI_In__5__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_In__5__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_In__5__MASK EQU 0x04
-SCSI_In__5__PC EQU CYREG_PRT4_PC2
-SCSI_In__5__PORT EQU 4
-SCSI_In__5__PRT EQU CYREG_PRT4_PRT
-SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_In__5__PS EQU CYREG_PRT4_PS
-SCSI_In__5__SHIFT EQU 2
-SCSI_In__5__SLW EQU CYREG_PRT4_SLW
-SCSI_In__6__AG EQU CYREG_PRT0_AG
-SCSI_In__6__AMUX EQU CYREG_PRT0_AMUX
-SCSI_In__6__BIE EQU CYREG_PRT0_BIE
-SCSI_In__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_In__6__BYP EQU CYREG_PRT0_BYP
-SCSI_In__6__CTL EQU CYREG_PRT0_CTL
-SCSI_In__6__DM0 EQU CYREG_PRT0_DM0
-SCSI_In__6__DM1 EQU CYREG_PRT0_DM1
-SCSI_In__6__DM2 EQU CYREG_PRT0_DM2
-SCSI_In__6__DR EQU CYREG_PRT0_DR
-SCSI_In__6__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_In__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_In__6__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_In__6__MASK EQU 0x20
-SCSI_In__6__PC EQU CYREG_PRT0_PC5
-SCSI_In__6__PORT EQU 0
-SCSI_In__6__PRT EQU CYREG_PRT0_PRT
-SCSI_In__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_In__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_In__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_In__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_In__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_In__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_In__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_In__6__PS EQU CYREG_PRT0_PS
-SCSI_In__6__SHIFT EQU 5
-SCSI_In__6__SLW EQU CYREG_PRT0_SLW
-SCSI_In__7__AG EQU CYREG_PRT0_AG
-SCSI_In__7__AMUX EQU CYREG_PRT0_AMUX
-SCSI_In__7__BIE EQU CYREG_PRT0_BIE
-SCSI_In__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_In__7__BYP EQU CYREG_PRT0_BYP
-SCSI_In__7__CTL EQU CYREG_PRT0_CTL
-SCSI_In__7__DM0 EQU CYREG_PRT0_DM0
-SCSI_In__7__DM1 EQU CYREG_PRT0_DM1
-SCSI_In__7__DM2 EQU CYREG_PRT0_DM2
-SCSI_In__7__DR EQU CYREG_PRT0_DR
-SCSI_In__7__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_In__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_In__7__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_In__7__MASK EQU 0x10
-SCSI_In__7__PC EQU CYREG_PRT0_PC4
-SCSI_In__7__PORT EQU 0
-SCSI_In__7__PRT EQU CYREG_PRT0_PRT
-SCSI_In__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_In__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_In__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_In__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_In__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_In__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_In__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_In__7__PS EQU CYREG_PRT0_PS
-SCSI_In__7__SHIFT EQU 4
-SCSI_In__7__SLW EQU CYREG_PRT0_SLW
-SCSI_In__ACK__AG EQU CYREG_PRT6_AG
-SCSI_In__ACK__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In__ACK__BIE EQU CYREG_PRT6_BIE
-SCSI_In__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In__ACK__BYP EQU CYREG_PRT6_BYP
-SCSI_In__ACK__CTL EQU CYREG_PRT6_CTL
-SCSI_In__ACK__DM0 EQU CYREG_PRT6_DM0
-SCSI_In__ACK__DM1 EQU CYREG_PRT6_DM1
-SCSI_In__ACK__DM2 EQU CYREG_PRT6_DM2
-SCSI_In__ACK__DR EQU CYREG_PRT6_DR
-SCSI_In__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In__ACK__MASK EQU 0x04
-SCSI_In__ACK__PC EQU CYREG_PRT6_PC2
-SCSI_In__ACK__PORT EQU 6
-SCSI_In__ACK__PRT EQU CYREG_PRT6_PRT
-SCSI_In__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In__ACK__PS EQU CYREG_PRT6_PS
-SCSI_In__ACK__SHIFT EQU 2
-SCSI_In__ACK__SLW EQU CYREG_PRT6_SLW
-SCSI_In__BSY__AG EQU CYREG_PRT6_AG
-SCSI_In__BSY__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In__BSY__BIE EQU CYREG_PRT6_BIE
-SCSI_In__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In__BSY__BYP EQU CYREG_PRT6_BYP
-SCSI_In__BSY__CTL EQU CYREG_PRT6_CTL
-SCSI_In__BSY__DM0 EQU CYREG_PRT6_DM0
-SCSI_In__BSY__DM1 EQU CYREG_PRT6_DM1
-SCSI_In__BSY__DM2 EQU CYREG_PRT6_DM2
-SCSI_In__BSY__DR EQU CYREG_PRT6_DR
-SCSI_In__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In__BSY__MASK EQU 0x08
-SCSI_In__BSY__PC EQU CYREG_PRT6_PC3
-SCSI_In__BSY__PORT EQU 6
-SCSI_In__BSY__PRT EQU CYREG_PRT6_PRT
-SCSI_In__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In__BSY__PS EQU CYREG_PRT6_PS
-SCSI_In__BSY__SHIFT EQU 3
-SCSI_In__BSY__SLW EQU CYREG_PRT6_SLW
+SCSI_In__2__SLW EQU CYREG_PRT4_SLW
+SCSI_In__3__AG EQU CYREG_PRT0_AG
+SCSI_In__3__AMUX EQU CYREG_PRT0_AMUX
+SCSI_In__3__BIE EQU CYREG_PRT0_BIE
+SCSI_In__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_In__3__BYP EQU CYREG_PRT0_BYP
+SCSI_In__3__CTL EQU CYREG_PRT0_CTL
+SCSI_In__3__DM0 EQU CYREG_PRT0_DM0
+SCSI_In__3__DM1 EQU CYREG_PRT0_DM1
+SCSI_In__3__DM2 EQU CYREG_PRT0_DM2
+SCSI_In__3__DR EQU CYREG_PRT0_DR
+SCSI_In__3__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_In__3__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_In__3__MASK EQU 0x20
+SCSI_In__3__PC EQU CYREG_PRT0_PC5
+SCSI_In__3__PORT EQU 0
+SCSI_In__3__PRT EQU CYREG_PRT0_PRT
+SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_In__3__PS EQU CYREG_PRT0_PS
+SCSI_In__3__SHIFT EQU 5
+SCSI_In__3__SLW EQU CYREG_PRT0_SLW
+SCSI_In__4__AG EQU CYREG_PRT0_AG
+SCSI_In__4__AMUX EQU CYREG_PRT0_AMUX
+SCSI_In__4__BIE EQU CYREG_PRT0_BIE
+SCSI_In__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_In__4__BYP EQU CYREG_PRT0_BYP
+SCSI_In__4__CTL EQU CYREG_PRT0_CTL
+SCSI_In__4__DM0 EQU CYREG_PRT0_DM0
+SCSI_In__4__DM1 EQU CYREG_PRT0_DM1
+SCSI_In__4__DM2 EQU CYREG_PRT0_DM2
+SCSI_In__4__DR EQU CYREG_PRT0_DR
+SCSI_In__4__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_In__4__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_In__4__MASK EQU 0x10
+SCSI_In__4__PC EQU CYREG_PRT0_PC4
+SCSI_In__4__PORT EQU 0
+SCSI_In__4__PRT EQU CYREG_PRT0_PRT
+SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_In__4__PS EQU CYREG_PRT0_PS
+SCSI_In__4__SHIFT EQU 4
+SCSI_In__4__SLW EQU CYREG_PRT0_SLW
SCSI_In__CD__AG EQU CYREG_PRT4_AG
SCSI_In__CD__AMUX EQU CYREG_PRT4_AMUX
SCSI_In__CD__BIE EQU CYREG_PRT4_BIE
SCSI_In__REQ__PS EQU CYREG_PRT0_PS
SCSI_In__REQ__SHIFT EQU 5
SCSI_In__REQ__SLW EQU CYREG_PRT0_SLW
-SCSI_In__SEL__AG EQU CYREG_PRT4_AG
-SCSI_In__SEL__AMUX EQU CYREG_PRT4_AMUX
-SCSI_In__SEL__BIE EQU CYREG_PRT4_BIE
-SCSI_In__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_In__SEL__BYP EQU CYREG_PRT4_BYP
-SCSI_In__SEL__CTL EQU CYREG_PRT4_CTL
-SCSI_In__SEL__DM0 EQU CYREG_PRT4_DM0
-SCSI_In__SEL__DM1 EQU CYREG_PRT4_DM1
-SCSI_In__SEL__DM2 EQU CYREG_PRT4_DM2
-SCSI_In__SEL__DR EQU CYREG_PRT4_DR
-SCSI_In__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_In__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_In__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_In__SEL__MASK EQU 0x08
-SCSI_In__SEL__PC EQU CYREG_PRT4_PC3
-SCSI_In__SEL__PORT EQU 4
-SCSI_In__SEL__PRT EQU CYREG_PRT4_PRT
-SCSI_In__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_In__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_In__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_In__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_In__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_In__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_In__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_In__SEL__PS EQU CYREG_PRT4_PS
-SCSI_In__SEL__SHIFT EQU 3
-SCSI_In__SEL__SLW EQU CYREG_PRT4_SLW
; SD_MISO
SD_MISO__0__MASK EQU 0x02
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x1000
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
-CYDEV_INTR_RISING EQU 0x0000001E
+CYDEV_INTR_RISING EQU 0x0000003E
CYDEV_PROJ_TYPE EQU 2
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LOADABLE EQU 2
#include <cydisabledsheets.h>
#include <SCSI_In_DBx_aliases.h>
#include <SCSI_Out_DBx_aliases.h>
-#include <SD_TX_DMA_dma.h>
-#include <SD_RX_DMA_COMPLETE.h>
#include <SD_Data_Clk.h>
-#include <SD_RX_DMA_dma.h>
#include <SD_CD_aliases.h>
#include <SD_CD.h>
#include <SCSI_CTL_PHASE.h>
#include <SD_MOSI_aliases.h>
#include <SD_MOSI.h>
#include <SCSI_CLK.h>
-#include <SCSI_RST_aliases.h>
-#include <SCSI_RST.h>
-#include <SCSI_ATN_aliases.h>
-#include <SCSI_ATN.h>
+#include <SCSI_Noise_aliases.h>
#include <SCSI_RST_ISR.h>
#include <LED1_aliases.h>
#include <LED1.h>
#include <USBFS_midi.h>
#include <USBFS_pvt.h>
#include <Bootloadable_1.h>
-#include <SD_TX_DMA_COMPLETE.h>
-#include <SCSI_TX_DMA_dma.h>
-#include <SCSI_RX_DMA_dma.h>
-#include <SCSI_TX_DMA_COMPLETE.h>
-#include <SCSI_RX_DMA_COMPLETE.h>
#include <SCSI_Out_Bits.h>
#include <SCSI_Out_Ctl.h>
#include <Debug_Timer.h>
#include <timer_clock.h>
#include <Debug_Timer_Interrupt.h>
+#include <SCSI_TX_DMA_dma.h>
+#include <SCSI_TX_DMA_COMPLETE.h>
+#include <SD_RX_DMA_dma.h>
+#include <SD_TX_DMA_dma.h>
+#include <SD_RX_DMA_COMPLETE.h>
+#include <SD_TX_DMA_COMPLETE.h>
+#include <SCSI_RX_DMA_dma.h>
+#include <SCSI_RX_DMA_COMPLETE.h>
+#include <SCSI_Parity_Error.h>
+#include <SCSI_Filtered.h>
#include <EXTLED_aliases.h>
#include <EXTLED.h>
-#include <SCSI_Parity_Error.h>
#include <USBFS_Dm_aliases.h>
#include <USBFS_Dm.h>
#include <USBFS_Dp_aliases.h>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI.h</File>
- <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_aliases.h</File>
- <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST.c</File>
- <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST.h</File>
- <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN_aliases.h</File>
- <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN.c</File>
- <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_ISR.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_ISR.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\LED1_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Parity_Error.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_CLK.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_CLK.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Noise_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Filtered.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Filtered.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\prebuild.bat</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\postbuild.bat</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyElfTool.exe</File>
<?xml version="1.0" encoding="utf-8"?>
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
+ <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000657B" bitWidth="8" desc="" />
+ </block>
+ <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647D" bitWidth="8" desc="" />
+ </block>
+ <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">
+ <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />
+ </register>
+ <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">
+ <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />
+ <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">
+ <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
+ <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
+ </field>
+ <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />
+ <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />
+ <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />
+ <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">
+ <value name="Timer" value="0" desc="CMP and TC are output." />
+ <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
+ </field>
+ <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />
+ </register>
+ <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">
+ <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />
+ <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">
+ <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
+ <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
+ </field>
+ <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />
+ <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />
+ <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />
+ <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />
+ </register>
+ <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">
+ <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">
+ <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
+ <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
+ <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
+ <value name="Irq" value="11" desc="Timer runs until IRQ." />
+ </field>
+ <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />
+ <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />
+ <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">
+ <value name="Equal" value="0" desc="Compare Equal " />
+ <value name="Less than" value="1" desc="Compare Less Than " />
+ <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
+ <value name="Greater" value="11" desc="Compare Greater Than ." />
+ <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
+ </field>
+ <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />
+ </register>
+ <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />
+ <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
+ </block>
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x4000656B" bitWidth="8" desc="" />
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x4000658B" bitWidth="8" desc="" />
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000659B" bitWidth="8" desc="">
+ <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
+ <value name="ENABLED" value="1" desc="Enable counter" />
+ <value name="DISABLED" value="0" desc="Disable counter" />
+ </field>
+ <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
+ <value name="ENABLED" value="1" desc="Interrupt enabled" />
+ <value name="DISABLED" value="0" desc="Interrupt disabled" />
+ </field>
+ <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
+ </field>
+ <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
+ </field>
+ <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />
+ </field>
+ <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />
+ </field>
+ </register>
+ </block>
+ <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">
+ <register name="SCSI_Filtered_STATUS_REG" address="0x4000646D" bitWidth="8" desc="" />
+ <register name="SCSI_Filtered_MASK_REG" address="0x4000648D" bitWidth="8" desc="" />
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649D" bitWidth="8" desc="">
+ <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
+ <value name="ENABLED" value="1" desc="Enable counter" />
+ <value name="DISABLED" value="0" desc="Disable counter" />
+ </field>
+ <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
+ <value name="ENABLED" value="1" desc="Interrupt enabled" />
+ <value name="DISABLED" value="0" desc="Interrupt disabled" />
+ </field>
+ <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
+ </field>
+ <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
+ </field>
+ <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />
+ </field>
+ <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />
+ </field>
+ </register>
+ </block>
+ <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647F" bitWidth="8" desc="" />
+ </block>
+ <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
</block>
- <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
<block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />
</block>
- <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006462" bitWidth="8" desc="" />
- <register name="SCSI_Parity_Error_MASK_REG" address="0x40006482" bitWidth="8" desc="" />
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006492" bitWidth="8" desc="">
- <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
- <value name="ENABLED" value="1" desc="Enable counter" />
- <value name="DISABLED" value="0" desc="Disable counter" />
- </field>
- <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
- <value name="ENABLED" value="1" desc="Interrupt enabled" />
- <value name="DISABLED" value="0" desc="Interrupt disabled" />
- </field>
- <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
- <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
- <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
- </field>
- <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
- <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
- <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
- </field>
- <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
- <value name="ENABLED" value="1" desc="Clear FIFO state" />
- <value name="DISABLED" value="0" desc="Normal FIFO operation" />
- </field>
- <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
- <value name="ENABLED" value="1" desc="Clear FIFO state" />
- <value name="DISABLED" value="0" desc="Normal FIFO operation" />
- </field>
- </register>
- </block>
- <block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000657B" bitWidth="8" desc="" />
- </block>
- <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">
- <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />
- </register>
- <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">
- <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />
- <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">
- <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
- <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
- </field>
- <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />
- <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />
- <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />
- <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">
- <value name="Timer" value="0" desc="CMP and TC are output." />
- <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
- </field>
- <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />
- </register>
- <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">
- <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />
- <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">
- <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
- <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
- </field>
- <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />
- <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />
- <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />
- <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />
- </register>
- <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">
- <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">
- <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
- <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
- <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
- <value name="Irq" value="11" desc="Timer runs until IRQ." />
- </field>
- <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />
- <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />
- <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">
- <value name="Equal" value="0" desc="Compare Equal " />
- <value name="Less than" value="1" desc="Compare Less Than " />
- <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
- <value name="Greater" value="11" desc="Compare Greater Than ." />
- <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
- </field>
- <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />
- </register>
- <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />
- <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
- </block>
- <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006579" bitWidth="8" desc="" />
- </block>
- <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />
- </block>
- <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
</blockRegMap>
\ No newline at end of file
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-<Hidden v="False" />
+<Hidden v="True" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
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-<Hidden v="False" />
+<Hidden v="True" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
<build_action v="NONE" />
<PropertyDeltas />
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-<Hidden v="False" />
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</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
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-<Hidden v="False" />
+<Hidden v="True" />
</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
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</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
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+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
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+<Hidden v="False" />
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+<Hidden v="False" />
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+<Hidden v="False" />
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</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<width>32</width>
<peripherals>
<peripheral>
- <name>USBFS</name>
- <description>USBFS</description>
- <baseAddress>0x40004394</baseAddress>
+ <name>SCSI_Out_Ctl</name>
+ <description>No description available</description>
+ <baseAddress>0x4000657B</baseAddress>
<addressBlock>
<offset>0</offset>
- <size>0x1D0A</size>
+ <size>0x1</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
- <name>USBFS_PM_USB_CR0</name>
- <description>USB Power Mode Control Register 0</description>
+ <name>SCSI_Out_Ctl_CONTROL_REG</name>
+ <description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
- <fields>
- <field>
- <name>fsusbio_ref_en</name>
- <description>No description available</description>
- <lsb>0</lsb>
- <msb>0</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>fsusbio_pd_n</name>
- <description>No description available</description>
- <lsb>1</lsb>
- <msb>1</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>fsusbio_pd_pullup_n</name>
- <description>No description available</description>
- <lsb>2</lsb>
- <msb>2</msb>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>USBFS_PM_ACT_CFG</name>
- <description>Active Power Mode Configuration Register</description>
- <addressOffset>0x11</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
</register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>SCSI_Out_Bits</name>
+ <description>No description available</description>
+ <baseAddress>0x4000647D</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x1</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
<register>
- <name>USBFS_PM_STBY_CFG</name>
- <description>Standby Power Mode Configuration Register</description>
- <addressOffset>0x21</addressOffset>
+ <name>SCSI_Out_Bits_CONTROL_REG</name>
+ <description>No description available</description>
+ <addressOffset>0x0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>Debug_Timer</name>
+ <description>No description available</description>
+ <baseAddress>0x400043A3</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0xB64</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
<register>
- <name>USBFS_PRT_PS</name>
- <description>Port Pin State Register</description>
- <addressOffset>0xE5D</addressOffset>
+ <name>Debug_Timer_GLOBAL_ENABLE</name>
+ <description>PM.ACT.CFG</description>
+ <addressOffset>0x0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>PinState_DP</name>
- <description>No description available</description>
- <lsb>6</lsb>
- <msb>6</msb>
- <access>read-only</access>
- </field>
- <field>
- <name>PinState_DM</name>
- <description>No description available</description>
- <lsb>7</lsb>
- <msb>7</msb>
- <access>read-only</access>
+ <name>en_timer</name>
+ <description>Enable timer/counters.</description>
+ <lsb>0</lsb>
+ <msb>3</msb>
+ <access>read-write</access>
</field>
</fields>
</register>
<register>
- <name>USBFS_PRT_DM0</name>
- <description>Port Drive Mode Register</description>
- <addressOffset>0xE5E</addressOffset>
+ <name>Debug_Timer_CONTROL</name>
+ <description>TMRx.CFG0</description>
+ <addressOffset>0xB5D</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>DriveMode_DP</name>
- <description>No description available</description>
- <lsb>6</lsb>
- <msb>6</msb>
+ <name>EN</name>
+ <description>Enables timer/comparator.</description>
+ <lsb>0</lsb>
+ <msb>0</msb>
<access>read-write</access>
</field>
<field>
- <name>DriveMode_DM</name>
- <description>No description available</description>
- <lsb>7</lsb>
- <msb>7</msb>
+ <name>MODE</name>
+ <description>Mode. (0 = Timer; 1 = Comparator)</description>
+ <lsb>1</lsb>
+ <msb>1</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Timer</name>
+ <description>Timer mode. CNT/CMP register holds timer count value.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Comparator</name>
+ <description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>ONESHOT</name>
+ <description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>
+ <lsb>2</lsb>
+ <msb>2</msb>
<access>read-write</access>
</field>
- </fields>
- </register>
- <register>
- <name>USBFS_PRT_DM1</name>
- <description>Port Drive Mode Register</description>
- <addressOffset>0xE5F</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- <fields>
<field>
- <name>PullUp_en_DP</name>
- <description>No description available</description>
- <lsb>6</lsb>
- <msb>6</msb>
+ <name>CMP_BUFF</name>
+ <description>Buffer compare register. Compare register updates only on timer terminal count.</description>
+ <lsb>3</lsb>
+ <msb>3</msb>
<access>read-write</access>
</field>
<field>
- <name>PullUp_en_DM</name>
- <description>No description available</description>
- <lsb>7</lsb>
+ <name>INV</name>
+ <description>Invert sense of TIMEREN signal</description>
+ <lsb>4</lsb>
+ <msb>4</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>DB</name>
+ <description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>
+ <lsb>5</lsb>
+ <msb>5</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Timer</name>
+ <description>CMP and TC are output.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Deadband</name>
+ <description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DEADBAND_PERIOD</name>
+ <description>Deadband Period</description>
+ <lsb>6</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
- <name>USBFS_PRT_INP_DIS</name>
- <description>Input buffer disable override</description>
- <addressOffset>0xE64</addressOffset>
+ <name>Debug_Timer_CONTROL2</name>
+ <description>TMRx.CFG1</description>
+ <addressOffset>0xB5E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>seinput_dis_dp</name>
- <description>No description available</description>
- <lsb>6</lsb>
+ <name>IRQ_SEL</name>
+ <description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>
+ <lsb>0</lsb>
+ <msb>0</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>FTC</name>
+ <description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>
+ <lsb>1</lsb>
+ <msb>1</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Disable_FTC</name>
+ <description>Disable the single cycle pulse, which signifies the timer is starting.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Enable_FTC</name>
+ <description>Enable the single cycle pulse, which signifies the timer is starting.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DCOR</name>
+ <description>Disable Clear on Read (DCOR) of Status Register SR0.</description>
+ <lsb>2</lsb>
+ <msb>2</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>DBMODE</name>
+ <description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>
+ <lsb>3</lsb>
+ <msb>3</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>CLK_BUS_EN_SEL</name>
+ <description>Digital Global Clock selection.</description>
+ <lsb>4</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
- <name>seinput_dis_dm</name>
- <description>No description available</description>
+ <name>BUS_CLK_SEL</name>
+ <description>Bus Clock selection.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</fields>
</register>
<register>
- <name>USBFS_EP0_DR0</name>
- <description>bmRequestType</description>
- <addressOffset>0x1C6C</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_EP0_DR1</name>
- <description>bRequest</description>
- <addressOffset>0x1C6D</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_EP0_DR2</name>
- <description>wValueLo</description>
- <addressOffset>0x1C6E</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_EP0_DR3</name>
- <description>wValueHi</description>
- <addressOffset>0x1C6F</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_EP0_DR4</name>
- <description>wIndexLo</description>
- <addressOffset>0x1C70</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_EP0_DR5</name>
- <description>wIndexHi</description>
- <addressOffset>0x1C71</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_EP0_DR6</name>
- <description>lengthLo</description>
- <addressOffset>0x1C72</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_EP0_DR7</name>
- <description>lengthHi</description>
- <addressOffset>0x1C73</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_CR0</name>
- <description>USB Control Register 0</description>
- <addressOffset>0x1C74</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- <fields>
- <field>
- <name>device_address</name>
- <description>No description available</description>
- <lsb>6</lsb>
- <msb>0</msb>
- <access>read-only</access>
- </field>
- <field>
- <name>usb_enable</name>
- <description>No description available</description>
- <lsb>7</lsb>
- <msb>7</msb>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>USBFS_CR1</name>
- <description>USB Control Register 1</description>
- <addressOffset>0x1C75</addressOffset>
+ <name>Debug_Timer_CONTROL3_</name>
+ <description>TMRx.CFG2</description>
+ <addressOffset>0xB5F</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>reg_enable</name>
- <description>No description available</description>
+ <name>TMR_CFG</name>
+ <description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>
<lsb>0</lsb>
- <msb>0</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>enable_lock</name>
- <description>No description available</description>
- <lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Continuous</name>
+ <description>Timer runs while EN bit of CFG0 register is set to '1'.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Pulsewidth</name>
+ <description>Timer runs from positive to negative edge of TIMEREN.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Period</name>
+ <description>Timer runs from positive to positive edge of TIMEREN.</description>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Irq</name>
+ <description>Timer runs until IRQ.</description>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
</field>
<field>
- <name>bus_activity</name>
- <description>No description available</description>
+ <name>COD</name>
+ <description>Clear On Disable (COD). Clears or gates outputs to zero.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
- <name>trim_offset_msb</name>
- <description>No description available</description>
+ <name>ROD</name>
+ <description>Reset On Disable (ROD). Resets internal state of output logic</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
- </fields>
- </register>
- <register>
- <name>USBFS_SIE_EP1_CR0</name>
- <description>The Endpoint1 Control Register</description>
- <addressOffset>0x1C7A</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_USBIO_CR0</name>
- <description>USBIO Control Register 0</description>
- <addressOffset>0x1C7C</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- <fields>
- <field>
- <name>rd</name>
- <description>No description available</description>
- <lsb>0</lsb>
- <msb>0</msb>
- <access>read-only</access>
- </field>
- <field>
- <name>td</name>
- <description>No description available</description>
- <lsb>5</lsb>
- <msb>5</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>tse0</name>
- <description>No description available</description>
- <lsb>6</lsb>
- <msb>6</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>ten</name>
- <description>No description available</description>
- <lsb>7</lsb>
- <msb>7</msb>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>USBFS_USBIO_CR1</name>
- <description>USBIO Control Register 1</description>
- <addressOffset>0x1C7E</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- <fields>
- <field>
- <name>dmo</name>
- <description>No description available</description>
- <lsb>0</lsb>
- <msb>0</msb>
- <access>read-only</access>
- </field>
- <field>
- <name>dpo</name>
- <description>No description available</description>
- <lsb>1</lsb>
- <msb>1</msb>
- <access>read-only</access>
- </field>
- <field>
- <name>usbpuen</name>
- <description>No description available</description>
- <lsb>2</lsb>
- <msb>2</msb>
- <access>read-write</access>
- </field>
<field>
- <name>iomode</name>
- <description>No description available</description>
- <lsb>5</lsb>
- <msb>5</msb>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>USBFS_SIE_EP2_CR0</name>
- <description>The Endpoint2 Control Register</description>
- <addressOffset>0x1C8A</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_SIE_EP3_CR0</name>
- <description>The Endpoint3 Control Register</description>
- <addressOffset>0x1C9A</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_SIE_EP4_CR0</name>
- <description>The Endpoint4 Control Register</description>
- <addressOffset>0x1CAA</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_SIE_EP5_CR0</name>
- <description>The Endpoint5 Control Register</description>
- <addressOffset>0x1CBA</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_SIE_EP6_CR0</name>
- <description>The Endpoint6 Control Register</description>
- <addressOffset>0x1CCA</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_SIE_EP7_CR0</name>
- <description>The Endpoint7 Control Register</description>
- <addressOffset>0x1CDA</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
+ <name>CMP_CFG</name>
+ <description>Comparator configurations</description>
+ <lsb>4</lsb>
+ <msb>6</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Equal</name>
+ <description>Compare Equal </description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Less_than</name>
+ <description>Compare Less Than </description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Less_than_or_equal</name>
+ <description>Compare Less Than or Equal .</description>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Greater</name>
+ <description>Compare Greater Than .</description>
+ <value>3</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Greater_than_or_equal</name>
+ <description>Compare Greater Than or Equal </description>
+ <value>4</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>HW_EN</name>
+ <description>When set Timer Enable controls counting.</description>
+ <lsb>7</lsb>
+ <msb>7</msb>
+ <access>read-write</access>
+ </field>
+ </fields>
</register>
<register>
- <name>USBFS_SIE_EP8_CR0</name>
- <description>The Endpoint8 Control Register</description>
- <addressOffset>0x1CEA</addressOffset>
- <size>8</size>
+ <name>Debug_Timer_PERIOD</name>
+ <description>TMRx.PER0 - Assigned Period</description>
+ <addressOffset>0xB61</addressOffset>
+ <size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
- <name>USBFS_BUF_SIZE</name>
- <description>Dedicated Endpoint Buffer Size Register</description>
- <addressOffset>0x1CF8</addressOffset>
- <size>8</size>
+ <name>Debug_Timer_COUNTER</name>
+ <description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
+ <addressOffset>0xB63</addressOffset>
+ <size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>SCSI_Parity_Error</name>
+ <description>No description available</description>
+ <baseAddress>0x4000656B</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x31</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
<register>
- <name>USBFS_EP_ACTIVE</name>
- <description>Endpoint Active Indication Register</description>
- <addressOffset>0x1CFA</addressOffset>
+ <name>SCSI_Parity_Error_STATUS_REG</name>
+ <description>No description available</description>
+ <addressOffset>0x0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
- <name>USBFS_EP_TYPE</name>
- <description>Endpoint Type (IN/OUT) Indication</description>
- <addressOffset>0x1CFB</addressOffset>
+ <name>SCSI_Parity_Error_MASK_REG</name>
+ <description>No description available</description>
+ <addressOffset>0x20</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
- <name>USBFS_USB_CLK_EN</name>
- <description>USB Block Clock Enable Register</description>
- <addressOffset>0x1D09</addressOffset>
+ <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
+ <description>No description available</description>
+ <addressOffset>0x30</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>FIFO0</name>
+ <description>FIFO0 clear</description>
+ <lsb>5</lsb>
+ <msb>5</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>Enable counter</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disable counter</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>INTRENBL</name>
+ <description>Enables or disables the Interrupt</description>
+ <lsb>4</lsb>
+ <msb>4</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>Interrupt enabled</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Interrupt disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>FIFO1LEVEL</name>
+ <description>FIFO level</description>
+ <lsb>3</lsb>
+ <msb>3</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>FIFO0LEVEL</name>
+ <description>FIFO level</description>
+ <lsb>2</lsb>
+ <msb>2</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>FIFO1CLEAR</name>
+ <description>FIFO clear</description>
+ <lsb>1</lsb>
+ <msb>1</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>Clear FIFO state</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Normal FIFO operation</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>FIFO0CLEAR</name>
+ <description>FIFO clear</description>
+ <lsb>0</lsb>
+ <msb>0</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>Clear FIFO state</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Normal FIFO operation</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
</register>
</registers>
</peripheral>
<peripheral>
- <name>SCSI_Parity_Error</name>
+ <name>SCSI_Filtered</name>
<description>No description available</description>
- <baseAddress>0x40006462</baseAddress>
+ <baseAddress>0x4000646D</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x31</size>
</addressBlock>
<registers>
<register>
- <name>SCSI_Parity_Error_STATUS_REG</name>
+ <name>SCSI_Filtered_STATUS_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
<resetMask>0</resetMask>
</register>
<register>
- <name>SCSI_Parity_Error_MASK_REG</name>
+ <name>SCSI_Filtered_MASK_REG</name>
<description>No description available</description>
<addressOffset>0x20</addressOffset>
<size>8</size>
<resetMask>0</resetMask>
</register>
<register>
- <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
+ <name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>
<description>No description available</description>
<addressOffset>0x30</addressOffset>
<size>8</size>
</registers>
</peripheral>
<peripheral>
- <name>SCSI_Out_Bits</name>
+ <name>SCSI_CTL_PHASE</name>
<description>No description available</description>
- <baseAddress>0x4000657B</baseAddress>
+ <baseAddress>0x4000647F</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1</size>
</addressBlock>
<registers>
<register>
- <name>SCSI_Out_Bits_CONTROL_REG</name>
+ <name>SCSI_CTL_PHASE_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
</registers>
</peripheral>
<peripheral>
- <name>Debug_Timer</name>
- <description>No description available</description>
- <baseAddress>0x400043A3</baseAddress>
+ <name>USBFS</name>
+ <description>USBFS</description>
+ <baseAddress>0x40004394</baseAddress>
<addressBlock>
<offset>0</offset>
- <size>0xB64</size>
+ <size>0x1D0A</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
- <name>Debug_Timer_GLOBAL_ENABLE</name>
- <description>PM.ACT.CFG</description>
- <addressOffset>0x0</addressOffset>
+ <name>USBFS_PM_USB_CR0</name>
+ <description>USB Power Mode Control Register 0</description>
+ <addressOffset>0x0</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>fsusbio_ref_en</name>
+ <description>No description available</description>
+ <lsb>0</lsb>
+ <msb>0</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>fsusbio_pd_n</name>
+ <description>No description available</description>
+ <lsb>1</lsb>
+ <msb>1</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>fsusbio_pd_pullup_n</name>
+ <description>No description available</description>
+ <lsb>2</lsb>
+ <msb>2</msb>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>USBFS_PM_ACT_CFG</name>
+ <description>Active Power Mode Configuration Register</description>
+ <addressOffset>0x11</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_PM_STBY_CFG</name>
+ <description>Standby Power Mode Configuration Register</description>
+ <addressOffset>0x21</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_PRT_PS</name>
+ <description>Port Pin State Register</description>
+ <addressOffset>0xE5D</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>en_timer</name>
- <description>Enable timer/counters.</description>
- <lsb>0</lsb>
- <msb>3</msb>
- <access>read-write</access>
+ <name>PinState_DP</name>
+ <description>No description available</description>
+ <lsb>6</lsb>
+ <msb>6</msb>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>PinState_DM</name>
+ <description>No description available</description>
+ <lsb>7</lsb>
+ <msb>7</msb>
+ <access>read-only</access>
</field>
</fields>
</register>
<register>
- <name>Debug_Timer_CONTROL</name>
- <description>TMRx.CFG0</description>
- <addressOffset>0xB5D</addressOffset>
+ <name>USBFS_PRT_DM0</name>
+ <description>Port Drive Mode Register</description>
+ <addressOffset>0xE5E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>EN</name>
- <description>Enables timer/comparator.</description>
- <lsb>0</lsb>
- <msb>0</msb>
+ <name>DriveMode_DP</name>
+ <description>No description available</description>
+ <lsb>6</lsb>
+ <msb>6</msb>
<access>read-write</access>
</field>
<field>
- <name>MODE</name>
- <description>Mode. (0 = Timer; 1 = Comparator)</description>
- <lsb>1</lsb>
- <msb>1</msb>
+ <name>DriveMode_DM</name>
+ <description>No description available</description>
+ <lsb>7</lsb>
+ <msb>7</msb>
<access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>Timer</name>
- <description>Timer mode. CNT/CMP register holds timer count value.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Comparator</name>
- <description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
</field>
+ </fields>
+ </register>
+ <register>
+ <name>USBFS_PRT_DM1</name>
+ <description>Port Drive Mode Register</description>
+ <addressOffset>0xE5F</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
<field>
- <name>ONESHOT</name>
- <description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>
- <lsb>2</lsb>
- <msb>2</msb>
+ <name>PullUp_en_DP</name>
+ <description>No description available</description>
+ <lsb>6</lsb>
+ <msb>6</msb>
<access>read-write</access>
</field>
<field>
- <name>CMP_BUFF</name>
- <description>Buffer compare register. Compare register updates only on timer terminal count.</description>
- <lsb>3</lsb>
- <msb>3</msb>
+ <name>PullUp_en_DM</name>
+ <description>No description available</description>
+ <lsb>7</lsb>
+ <msb>7</msb>
<access>read-write</access>
</field>
+ </fields>
+ </register>
+ <register>
+ <name>USBFS_PRT_INP_DIS</name>
+ <description>Input buffer disable override</description>
+ <addressOffset>0xE64</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
<field>
- <name>INV</name>
- <description>Invert sense of TIMEREN signal</description>
- <lsb>4</lsb>
- <msb>4</msb>
+ <name>seinput_dis_dp</name>
+ <description>No description available</description>
+ <lsb>6</lsb>
+ <msb>6</msb>
<access>read-write</access>
</field>
<field>
- <name>DB</name>
- <description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>
- <lsb>5</lsb>
- <msb>5</msb>
+ <name>seinput_dis_dm</name>
+ <description>No description available</description>
+ <lsb>7</lsb>
+ <msb>7</msb>
<access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>Timer</name>
- <description>CMP and TC are output.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Deadband</name>
- <description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
</field>
+ </fields>
+ </register>
+ <register>
+ <name>USBFS_EP0_DR0</name>
+ <description>bmRequestType</description>
+ <addressOffset>0x1C6C</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_EP0_DR1</name>
+ <description>bRequest</description>
+ <addressOffset>0x1C6D</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_EP0_DR2</name>
+ <description>wValueLo</description>
+ <addressOffset>0x1C6E</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_EP0_DR3</name>
+ <description>wValueHi</description>
+ <addressOffset>0x1C6F</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_EP0_DR4</name>
+ <description>wIndexLo</description>
+ <addressOffset>0x1C70</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_EP0_DR5</name>
+ <description>wIndexHi</description>
+ <addressOffset>0x1C71</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_EP0_DR6</name>
+ <description>lengthLo</description>
+ <addressOffset>0x1C72</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_EP0_DR7</name>
+ <description>lengthHi</description>
+ <addressOffset>0x1C73</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_CR0</name>
+ <description>USB Control Register 0</description>
+ <addressOffset>0x1C74</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
<field>
- <name>DEADBAND_PERIOD</name>
- <description>Deadband Period</description>
+ <name>device_address</name>
+ <description>No description available</description>
<lsb>6</lsb>
+ <msb>0</msb>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>usb_enable</name>
+ <description>No description available</description>
+ <lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
- <name>Debug_Timer_CONTROL2</name>
- <description>TMRx.CFG1</description>
- <addressOffset>0xB5E</addressOffset>
+ <name>USBFS_CR1</name>
+ <description>USB Control Register 1</description>
+ <addressOffset>0x1C75</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>IRQ_SEL</name>
- <description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>
+ <name>reg_enable</name>
+ <description>No description available</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
- <name>FTC</name>
- <description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>
+ <name>enable_lock</name>
+ <description>No description available</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>Disable_FTC</name>
- <description>Disable the single cycle pulse, which signifies the timer is starting.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enable_FTC</name>
- <description>Enable the single cycle pulse, which signifies the timer is starting.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
</field>
<field>
- <name>DCOR</name>
- <description>Disable Clear on Read (DCOR) of Status Register SR0.</description>
+ <name>bus_activity</name>
+ <description>No description available</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
- <name>DBMODE</name>
- <description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>
+ <name>trim_offset_msb</name>
+ <description>No description available</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
+ </fields>
+ </register>
+ <register>
+ <name>USBFS_SIE_EP1_CR0</name>
+ <description>The Endpoint1 Control Register</description>
+ <addressOffset>0x1C7A</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_USBIO_CR0</name>
+ <description>USBIO Control Register 0</description>
+ <addressOffset>0x1C7C</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
<field>
- <name>CLK_BUS_EN_SEL</name>
- <description>Digital Global Clock selection.</description>
- <lsb>4</lsb>
+ <name>rd</name>
+ <description>No description available</description>
+ <lsb>0</lsb>
+ <msb>0</msb>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>td</name>
+ <description>No description available</description>
+ <lsb>5</lsb>
+ <msb>5</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>tse0</name>
+ <description>No description available</description>
+ <lsb>6</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
- <name>BUS_CLK_SEL</name>
- <description>Bus Clock selection.</description>
+ <name>ten</name>
+ <description>No description available</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</fields>
</register>
<register>
- <name>Debug_Timer_CONTROL3_</name>
- <description>TMRx.CFG2</description>
- <addressOffset>0xB5F</addressOffset>
+ <name>USBFS_USBIO_CR1</name>
+ <description>USBIO Control Register 1</description>
+ <addressOffset>0x1C7E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>TMR_CFG</name>
- <description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>
+ <name>dmo</name>
+ <description>No description available</description>
<lsb>0</lsb>
+ <msb>0</msb>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>dpo</name>
+ <description>No description available</description>
+ <lsb>1</lsb>
<msb>1</msb>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>Continuous</name>
- <description>Timer runs while EN bit of CFG0 register is set to '1'.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Pulsewidth</name>
- <description>Timer runs from positive to negative edge of TIMEREN.</description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Period</name>
- <description>Timer runs from positive to positive edge of TIMEREN.</description>
- <value>2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Irq</name>
- <description>Timer runs until IRQ.</description>
- <value>3</value>
- </enumeratedValue>
- </enumeratedValues>
+ <access>read-only</access>
</field>
<field>
- <name>COD</name>
- <description>Clear On Disable (COD). Clears or gates outputs to zero.</description>
+ <name>usbpuen</name>
+ <description>No description available</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
- <name>ROD</name>
- <description>Reset On Disable (ROD). Resets internal state of output logic</description>
- <lsb>3</lsb>
- <msb>3</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>CMP_CFG</name>
- <description>Comparator configurations</description>
- <lsb>4</lsb>
- <msb>6</msb>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>Equal</name>
- <description>Compare Equal </description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Less_than</name>
- <description>Compare Less Than </description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Less_than_or_equal</name>
- <description>Compare Less Than or Equal .</description>
- <value>2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Greater</name>
- <description>Compare Greater Than .</description>
- <value>3</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Greater_than_or_equal</name>
- <description>Compare Greater Than or Equal </description>
- <value>4</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>HW_EN</name>
- <description>When set Timer Enable controls counting.</description>
- <lsb>7</lsb>
- <msb>7</msb>
+ <name>iomode</name>
+ <description>No description available</description>
+ <lsb>5</lsb>
+ <msb>5</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
- <name>Debug_Timer_PERIOD</name>
- <description>TMRx.PER0 - Assigned Period</description>
- <addressOffset>0xB61</addressOffset>
- <size>16</size>
+ <name>USBFS_SIE_EP2_CR0</name>
+ <description>The Endpoint2 Control Register</description>
+ <addressOffset>0x1C8A</addressOffset>
+ <size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
- <name>Debug_Timer_COUNTER</name>
- <description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
- <addressOffset>0xB63</addressOffset>
- <size>16</size>
+ <name>USBFS_SIE_EP3_CR0</name>
+ <description>The Endpoint3 Control Register</description>
+ <addressOffset>0x1C9A</addressOffset>
+ <size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
- </registers>
- </peripheral>
- <peripheral>
- <name>SCSI_Out_Ctl</name>
- <description>No description available</description>
- <baseAddress>0x40006579</baseAddress>
- <addressBlock>
- <offset>0</offset>
- <size>0x1</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
<register>
- <name>SCSI_Out_Ctl_CONTROL_REG</name>
- <description>No description available</description>
- <addressOffset>0x0</addressOffset>
+ <name>USBFS_SIE_EP4_CR0</name>
+ <description>The Endpoint4 Control Register</description>
+ <addressOffset>0x1CAA</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
- </registers>
- </peripheral>
- <peripheral>
- <name>SCSI_CTL_PHASE</name>
- <description>No description available</description>
- <baseAddress>0x40006472</baseAddress>
- <addressBlock>
- <offset>0</offset>
- <size>0x1</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
<register>
- <name>SCSI_CTL_PHASE_CONTROL_REG</name>
- <description>No description available</description>
- <addressOffset>0x0</addressOffset>
+ <name>USBFS_SIE_EP5_CR0</name>
+ <description>The Endpoint5 Control Register</description>
+ <addressOffset>0x1CBA</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_SIE_EP6_CR0</name>
+ <description>The Endpoint6 Control Register</description>
+ <addressOffset>0x1CCA</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_SIE_EP7_CR0</name>
+ <description>The Endpoint7 Control Register</description>
+ <addressOffset>0x1CDA</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_SIE_EP8_CR0</name>
+ <description>The Endpoint8 Control Register</description>
+ <addressOffset>0x1CEA</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_BUF_SIZE</name>
+ <description>Dedicated Endpoint Buffer Size Register</description>
+ <addressOffset>0x1CF8</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_EP_ACTIVE</name>
+ <description>Endpoint Active Indication Register</description>
+ <addressOffset>0x1CFA</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_EP_TYPE</name>
+ <description>Endpoint Type (IN/OUT) Indication</description>
+ <addressOffset>0x1CFB</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_USB_CLK_EN</name>
+ <description>USB Block Clock Enable Register</description>
+ <addressOffset>0x1D09</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
projects / SCSI2SD-V6.git / commitdiff