+201507XX 4.4
+ - Added configuration option to allow SCSI2 mode. This option is OFF by
+ default, and should only be enabled when using the SCSI2SD with a SCSI2 host
+ controller. Extra timing delays are added in the default SCSI1/SASI mode to
+ work with slow hardware.
+ - Modified hot-swap card detection to work with longer (60cm) microSD to SD
+ cables.
+ - Fixed off-by-one error in scsi2sd-util "Auto" sector start feature.
+ - Fixed crashes and stalls of scsi2sd-util after saving/loading options
+ to/from the device
+ - Fixed synchronous transfer request negotiation.
+ SCSI2SD now negotiates back to async transfers instead of simply
+ rejecting the message.
+ - Fixed INQUIRY response to commands lacking an allocation length.
+
20150614 4.3
- Added configurable disk geometry.
- Added configuration import/export function to scsi2sd-util
Atari TT030 System V
Atari MEGA STE
needs J3 TERMPWR jumper
- 1GB limit (--blocks=2048000)
+ 1GB limit (--blocks=2048000). The OS will fail to read the boot sector if the disk is >= 1GB.
Sharp X68000
SASI models supported. See gamesx.com for information on building a custom cable.
needs J3 TERMPWR jumper
EMU E6400 w/ EOS2.80f
EMU Emax2
Ensoniq ASR-X, ASR-10 (from v3.4, 2GB size limit)
- ASR-20 Requires TERMPWR jumper.
+ ASR-10 Requires TERMPWR jumper (applies to pre. 5.0 SCSI2SD boards only)
ASR-X resets when writing to devices > 2Gb.
Kurzweil K2000R
See kurzweil.com for size limits which a dependant on the OS version. Older OS versions have a 1GB limit.
// systick timer interrupt saves us on the event of a race.\r
int scsiBusy = scsiDMABusy();\r
int sdBusy = sdDMABusy();\r
- if (scsiBusy && sdBusy) __WFI();\r
+ while (scsiBusy && sdBusy)\r
+ {\r
+ __WFI();\r
+ scsiBusy = scsiDMABusy();\r
+ sdBusy = sdDMABusy();\r
+ }\r
\r
if (sdActive && !sdBusy && sdReadSectorDMAPoll())\r
{\r
sdActive = 0;\r
prep++;\r
}\r
- else if (!sdActive &&\r
+\r
+ // Usually SD is slower than the SCSI interface.\r
+ // Prioritise starting the read of the next sector over starting a\r
+ // SCSI transfer for the last sector\r
+ // ie. NO "else" HERE.\r
+ if (!sdActive &&\r
(prep - i < buffers) &&\r
(prep < totalSDSectors))\r
{\r
scsiActive = 0;\r
++i;\r
}\r
- else if (!scsiActive && ((prep - i) > 0))\r
+ if (!scsiActive && ((prep - i) > 0))\r
{\r
int dmaBytes = SD_SECTOR_SIZE;\r
if ((i % sdPerScsi) == (sdPerScsi - 1))\r
// systick timer interrupt saves us on the event of a race.\r
int scsiBusy = scsiDMABusy();\r
int sdBusy = sdDMABusy();\r
- if (scsiBusy && sdBusy) __WFI();\r
+ while (scsiBusy && sdBusy)\r
+ {\r
+ __WFI();\r
+ scsiBusy = scsiDMABusy();\r
+ sdBusy = sdDMABusy();\r
+ }\r
\r
if (sdActive && !sdBusy && sdWriteSectorDMAPoll(i == (totalSDSectors - 1)))\r
{\r
sdActive = 0;\r
i++;\r
}\r
- else if (!sdActive && ((prep - i) > 0))\r
+ if (!sdActive && ((prep - i) > 0))\r
{\r
// Start an SD transfer if we have space.\r
sdWriteMultiSectorDMA(&scsiDev.data[SD_SECTOR_SIZE * (i % buffers)]);\r
++prep;\r
lastActivityTime = now;\r
}\r
- else if (!scsiActive &&\r
+ if (!scsiActive &&\r
((prep - i) < buffers) &&\r
(prep < totalSDSectors) &&\r
likely(!scsiDisconnected))\r
uint8 evpd = scsiDev.cdb[1] & 1; // enable vital product data.\r
uint8 pageCode = scsiDev.cdb[2];\r
uint32 allocationLength = scsiDev.cdb[4];\r
+\r
+ // SASI standard, X3T9.3_185_RevE states that 0 == 256 bytes\r
if (allocationLength == 0) allocationLength = 256;\r
- \r
+\r
if (!evpd)\r
{\r
if (pageCode)\r
// with zeroes. This only seems to happen for Inquiry responses, and not\r
// other commands that also supply an allocation length such as Mode Sense or\r
// Request Sense.\r
+ // (See below for exception to this rule when 0 allocation length)\r
if (scsiDev.dataLen < allocationLength)\r
{\r
memset(\r
0,\r
allocationLength - scsiDev.dataLen);\r
}\r
- // Spec 8.2.5 requires us to simply truncate the response if it's too big.\r
- scsiDev.dataLen = allocationLength;\r
- \r
+ if (scsiDev.cdb[4] == 0 && scsiDev.dataLen < allocationLength)\r
+ {\r
+ // Only send back the minimum number of bytes.\r
+ // Don't forcably send back 256 bytes, as that may cause problems\r
+ // with some machines (SGI Iris Indigo running IRIX)\r
+ // scsiDev.dataLen is already the correct value.\r
+ }\r
+ else\r
+ {\r
+ // Spec 8.2.5 requires us to simply truncate the response if it's\r
+ // too big.\r
+ scsiDev.dataLen = allocationLength;\r
+ }\r
+\r
// Set the device type as needed.\r
switch (scsiDev.target->cfg->deviceType)\r
{\r
int pc = scsiDev.cdb[2] >> 6; // Page Control\r
int pageCode = scsiDev.cdb[2] & 0x3F;\r
int allocLength = scsiDev.cdb[4];\r
- if (allocLength == 0) allocLength = 256;\r
+\r
+ // SCSI1 standard: (CCS X3T9.2/86-52)\r
+ // "An Allocation Length of zero indicates that no MODE SENSE data shall\r
+ // be transferred. This condition shall not be considered as an error."\r
doModeSense(1, dbd, pc, pageCode, allocLength);\r
}\r
else if (command == 0x5A)\r
target->unitAttention = 0;\r
scsiDev.compatMode = COMPAT_SCSI1;\r
}\r
+ else if (!(target->cfg->flags & CONFIG_ENABLE_SCSI2))\r
+ {\r
+ scsiDev.compatMode = COMPAT_SCSI1;\r
+ }\r
else if (scsiDev.compatMode == COMPAT_UNKNOWN)\r
{\r
scsiDev.compatMode = COMPAT_SCSI2;\r
// Discard bytes.\r
extmsg[i] = scsiReadByte();\r
}\r
- \r
+\r
if (extmsg[0] == 3 && msgLen == 2) // Wide Data Request\r
{\r
// Negotiate down to 8bit\r
static const uint8_t WDTR[] = {0x01, 0x02, 0x03, 0x00};\r
scsiWrite(WDTR, sizeof(WDTR));\r
}\r
- else if (extmsg[0] == 1 && msgLen == 5) // Synchronous data request\r
+ else if (extmsg[0] == 1 && msgLen == 3) // Synchronous data request\r
{\r
// Negotiate back to async\r
scsiEnterPhase(MESSAGE_IN);\r
\r
#define scsiTarget_AUX_CTL (* (reg8 *) scsiTarget_datapath__DP_AUX_CTL_REG)\r
\r
-// DMA controller can't handle any more bytes.\r
-#define MAX_DMA_BYTES 4095\r
+// DMA controller can't handle any more than 4095 bytes,\r
+// but we round down to nearest multiple of 4 bytes..\r
+#define MAX_DMA_BYTES 4088\r
\r
// Private DMA variables.\r
static int dmaInProgress = 0;\r
}\r
else\r
{\r
- scsiReadDMA(data, count);\r
+ uint32_t alignedCount = count & 0xFFFFFFF8;\r
+ scsiReadDMA(data, alignedCount);\r
\r
// Wait for the next DMA interrupt (or the 1ms systick)\r
// It's beneficial to halt the processor to\r
__WFI();\r
\r
trace(trace_spinReadDMAPoll);\r
- while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag)) {};\r
+ while (!scsiReadDMAPoll() && likely(!scsiDev.resetFlag))\r
+ {\r
+ __WFI();\r
+ };\r
+\r
+ if (count > alignedCount)\r
+ {\r
+ scsiReadPIO(data + alignedCount, count - alignedCount);\r
+ }\r
}\r
}\r
\r
}\r
else\r
{\r
- scsiWriteDMA(data, count);\r
+ uint32_t alignedCount = count & 0xFFFFFFF8;\r
+ scsiWriteDMA(data, alignedCount);\r
\r
// Wait for the next DMA interrupt (or the 1ms systick)\r
// It's beneficial to halt the processor to\r
__WFI();\r
\r
trace(trace_spinWriteDMAPoll);\r
- while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag)) {};\r
+ while (!scsiWriteDMAPoll() && likely(!scsiDev.resetFlag))\r
+ {\r
+ __WFI();\r
+ };\r
+ \r
+ if (count > alignedCount)\r
+ {\r
+ scsiWritePIO(data + alignedCount, count - alignedCount);\r
+ }\r
}\r
}\r
\r
{\r
scsiDmaRxChan =\r
SCSI_RX_DMA_DmaInitialize(\r
- 1, // Bytes per burst\r
+ 4, // Bytes per burst\r
1, // request per burst\r
HI16(CYDEV_PERIPH_BASE),\r
HI16(CYDEV_SRAM_BASE)\r
\r
scsiDmaTxChan =\r
SCSI_TX_DMA_DmaInitialize(\r
- 1, // Bytes per burst\r
+ 4, // Bytes per burst\r
1, // request per burst\r
HI16(CYDEV_SRAM_BASE),\r
HI16(CYDEV_PERIPH_BASE)\r
\r
SCSI_SEL_ISR_StartEx(scsiSelectionISR);\r
\r
+/*\r
+ // Disable the glitch filter for ACK to improve performance.\r
+ // TODO NEED SOME CONFIG\r
+ SCSI_Glitch_Ctl_Write(1);\r
+ CY_SET_REG8(scsiTarget_datapath__D0_REG, 0);\r
+*/\r
+\r
}\r
\r
// 1 = DBx error\r
static uint8 sdDMATxChan = CY_DMA_INVALID_CHANNEL;\r
\r
// Dummy location for DMA to send unchecked CRC bytes to\r
-static uint8 discardBuffer;\r
+static uint8 discardBuffer __attribute__((aligned(4)));\r
\r
// 2 bytes CRC, response, 8bits to close the clock..\r
// "NCR" time is up to 8 bytes.\r
-static uint8_t writeResponseBuffer[8];\r
+static uint8_t writeResponseBuffer[8] __attribute__((aligned(4)));\r
\r
-static uint8_t writeStartToken = 0xFC;\r
+// Padded with a dummy byte just to allow the tx DMA channel to\r
+// use 2-byte bursts for performance.\r
+static uint8_t writeStartToken[2] __attribute__((aligned(4))) = {0xFF, 0xFC};\r
\r
// Source of dummy SPI bytes for DMA\r
-static uint8 dummyBuffer = 0xFF;\r
+static uint8_t dummyBuffer[2] __attribute__((aligned(4))) = {0xFF, 0xFF};\r
\r
volatile uint8_t sdRxDMAComplete;\r
volatile uint8_t sdTxDMAComplete;\r
\r
// send is static as the address must remain consistent for the static\r
// DMA descriptors to work.\r
- static uint8_t send[7];\r
+ // Size must be divisible by 2 to suit 2-byte-burst TX DMA channel.\r
+ static uint8_t send[6] __attribute__((aligned(4)));\r
send[0] = cmd | 0x40;\r
send[1] = param >> 24;\r
send[2] = param >> 16;\r
{\r
send[5] = 1; // stop bit\r
}\r
- send[6] = 0xFF; // Result code or stuff byte.\r
\r
static uint8_t dmaRxTd = CY_DMA_INVALID_TD;\r
static uint8_t dmaTxTd = CY_DMA_INVALID_TD;\r
// The DMA controller is a bit trigger-happy. It will retain\r
// a drq request that was triggered while the channel was\r
// disabled.\r
- CyDmaClearPendingDrq(sdDMATxChan);\r
+ CyDmaChSetRequest(sdDMATxChan, CY_DMA_CPU_REQ);\r
CyDmaClearPendingDrq(sdDMARxChan);\r
\r
// There is no flow control, so we must ensure we can read the bytes\r
trace(trace_spinSDDMA);\r
while (!(sdTxDMAComplete && sdRxDMAComplete)) { __WFI(); }\r
\r
- uint16_t response = discardBuffer;\r
+ uint16_t response = sdSpiByte(0xFF); // Result code or stuff byte\r
if (unlikely(cmd == SD_STOP_TRANSMISSION))\r
{\r
// Stuff byte is required for this command only.\r
// The DMA controller is a bit trigger-happy. It will retain\r
// a drq request that was triggered while the channel was\r
// disabled.\r
- CyDmaClearPendingDrq(sdDMATxChan);\r
+ CyDmaChSetRequest(sdDMATxChan, CY_DMA_CPU_REQ);\r
CyDmaClearPendingDrq(sdDMARxChan);\r
\r
// There is no flow control, so we must ensure we can read the bytes\r
\r
// Transmit 512 bytes of data and then 2 bytes CRC, and then get the response byte\r
// We need to do this without stopping the clock\r
- CyDmaTdSetConfiguration(dmaTxTd[0], 1, dmaTxTd[1], TD_INC_SRC_ADR);\r
+ CyDmaTdSetConfiguration(dmaTxTd[0], 2, dmaTxTd[1], TD_INC_SRC_ADR);\r
CyDmaTdSetAddress(dmaTxTd[0], LO16((uint32)&writeStartToken), LO16((uint32)SDCard_TXDATA_PTR));\r
\r
CyDmaTdSetConfiguration(dmaTxTd[1], SD_SECTOR_SIZE, dmaTxTd[2], TD_INC_SRC_ADR);\r
CyDmaTdSetConfiguration(dmaTxTd[2], 2 + sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);\r
CyDmaTdSetAddress(dmaTxTd[2], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
\r
- CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE + 3, dmaRxTd[1], 0);\r
+ CyDmaTdSetConfiguration(dmaRxTd[0], SD_SECTOR_SIZE + 4, dmaRxTd[1], 0);\r
CyDmaTdSetAddress(dmaRxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));\r
CyDmaTdSetConfiguration(dmaRxTd[1], sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN|TD_INC_DST_ADR);\r
CyDmaTdSetAddress(dmaRxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&writeResponseBuffer));\r
// The DMA controller is a bit trigger-happy. It will retain\r
// a drq request that was triggered while the channel was\r
// disabled.\r
- CyDmaClearPendingDrq(sdDMATxChan);\r
+ CyDmaChSetRequest(sdDMATxChan, CY_DMA_CPU_REQ);\r
CyDmaClearPendingDrq(sdDMARxChan);\r
\r
sdTxDMAComplete = 0;\r
{\r
sdDMATxChan =\r
SD_TX_DMA_DmaInitialize(\r
- 1, // Bytes per burst\r
+ 2, // Bytes per burst\r
1, // request per burst\r
HI16(CYDEV_SRAM_BASE),\r
HI16(CYDEV_PERIPH_BASE)\r
SD_CS_Write(0);\r
SD_CS_SetDriveMode(SD_CS_DM_DIG_HIZ);\r
\r
- CyDelayCycles(64);\r
+ // Delay extended to work with 60cm cables running cards at 2.85V\r
+ CyDelayCycles(128);\r
uint8_t cs = SD_CS_Read();\r
SD_CS_SetDriveMode(SD_CS_DM_STRONG) ;\r
\r
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Glitch_Ctl.c
+* Version 1.70
+*
+* Description:
+* This file contains API to enable firmware control of a Control Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Glitch_Ctl.h"
+
+#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Write
+********************************************************************************
+*
+* Summary:
+* Write a byte to the Control Register.
+*
+* Parameters:
+* control: The value to be assigned to the Control Register.
+*
+* Return:
+* None.
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_Write(uint8 control)
+{
+ SCSI_Glitch_Ctl_Control = control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Read
+********************************************************************************
+*
+* Summary:
+* Reads the current value assigned to the Control Register.
+*
+* Parameters:
+* None.
+*
+* Return:
+* Returns the current value in the Control Register.
+*
+*******************************************************************************/
+uint8 SCSI_Glitch_Ctl_Read(void)
+{
+ return SCSI_Glitch_Ctl_Control;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Glitch_Ctl.h
+* Version 1.70
+*
+* Description:
+* This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CONTROL_REG_SCSI_Glitch_Ctl_H) /* CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
+#define CY_CONTROL_REG_SCSI_Glitch_Ctl_H
+
+#include "cytypes.h"
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+void SCSI_Glitch_Ctl_Write(uint8 control) ;
+uint8 SCSI_Glitch_Ctl_Read(void) ;
+
+
+/***************************************
+* Registers
+***************************************/
+
+/* Control Register */
+#define SCSI_Glitch_Ctl_Control (* (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG )
+#define SCSI_Glitch_Ctl_Control_PTR ( (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG )
+
+#endif /* End CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
+
+
+/* [] END OF FILE */
***************************************/\r
\r
#define SDCard_INT_ON_SPI_DONE ((uint8) (0u << SDCard_STS_SPI_DONE_SHIFT))\r
-#define SDCard_INT_ON_TX_EMPTY ((uint8) (0u << SDCard_STS_TX_FIFO_EMPTY_SHIFT))\r
-#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (1u << \\r
+#define SDCard_INT_ON_TX_EMPTY ((uint8) (1u << SDCard_STS_TX_FIFO_EMPTY_SHIFT))\r
+#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \\r
SDCard_STS_TX_FIFO_NOT_FULL_SHIFT))\r
#define SDCard_INT_ON_BYTE_COMP ((uint8) (0u << SDCard_STS_BYTE_COMPLETE_SHIFT))\r
#define SDCard_INT_ON_SPI_IDLE ((uint8) (0u << SDCard_STS_SPI_IDLE_SHIFT))\r
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1\r
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0\r
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB11_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB11_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB11_ST_CTL\r
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB11_MSK\r
\r
/* SCSI_Out_Ctl */\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
#define scsiTarget_StatusReg__0__POS 0\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__2__POS 2\r
#define scsiTarget_StatusReg__3__MASK 0x08u\r
#define scsiTarget_StatusReg__4__MASK 0x10u\r
#define scsiTarget_StatusReg__4__POS 4\r
#define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST\r
\r
/* Debug_Timer_Interrupt */\r
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK\r
-#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB07_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB07_ST\r
\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK\r
+\r
+/* SCSI_Glitch_Ctl */\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK\r
\r
/* SCSI_Parity_Error */\r
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST\r
\r
/* Miscellaneous */\r
#define BCLK__BUS_CLK__HZ 50000000U\r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 40u\r
+#define CY_CFG_BASE_ADDR_COUNT 42u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
0x4000520Cu, /* Base address: 0x40005200 Count: 12 */\r
0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
- 0x40010036u, /* Base address: 0x40010000 Count: 54 */\r
- 0x4001013Du, /* Base address: 0x40010100 Count: 61 */\r
+ 0x40010039u, /* Base address: 0x40010000 Count: 57 */\r
+ 0x40010135u, /* Base address: 0x40010100 Count: 53 */\r
0x40010243u, /* Base address: 0x40010200 Count: 67 */\r
- 0x40010358u, /* Base address: 0x40010300 Count: 88 */\r
- 0x40010448u, /* Base address: 0x40010400 Count: 72 */\r
- 0x40010555u, /* Base address: 0x40010500 Count: 85 */\r
- 0x4001064Cu, /* Base address: 0x40010600 Count: 76 */\r
- 0x40010746u, /* Base address: 0x40010700 Count: 70 */\r
- 0x4001083Fu, /* Base address: 0x40010800 Count: 63 */\r
- 0x40010948u, /* Base address: 0x40010900 Count: 72 */\r
- 0x40010A4Du, /* Base address: 0x40010A00 Count: 77 */\r
- 0x40010B4Au, /* Base address: 0x40010B00 Count: 74 */\r
- 0x40010C42u, /* Base address: 0x40010C00 Count: 66 */\r
- 0x40010D4Cu, /* Base address: 0x40010D00 Count: 76 */\r
- 0x40010E4Cu, /* Base address: 0x40010E00 Count: 76 */\r
- 0x40010F3Bu, /* Base address: 0x40010F00 Count: 59 */\r
- 0x4001142Cu, /* Base address: 0x40011400 Count: 44 */\r
- 0x40011550u, /* Base address: 0x40011500 Count: 80 */\r
- 0x4001163Eu, /* Base address: 0x40011600 Count: 62 */\r
- 0x4001173Fu, /* Base address: 0x40011700 Count: 63 */\r
- 0x40011904u, /* Base address: 0x40011900 Count: 4 */\r
- 0x40011B02u, /* Base address: 0x40011B00 Count: 2 */\r
+ 0x40010354u, /* Base address: 0x40010300 Count: 84 */\r
+ 0x4001043Fu, /* Base address: 0x40010400 Count: 63 */\r
+ 0x40010551u, /* Base address: 0x40010500 Count: 81 */\r
+ 0x4001064Au, /* Base address: 0x40010600 Count: 74 */\r
+ 0x4001074Du, /* Base address: 0x40010700 Count: 77 */\r
+ 0x40010804u, /* Base address: 0x40010800 Count: 4 */\r
+ 0x4001091Eu, /* Base address: 0x40010900 Count: 30 */\r
+ 0x40010A54u, /* Base address: 0x40010A00 Count: 84 */\r
+ 0x40010B53u, /* Base address: 0x40010B00 Count: 83 */\r
+ 0x40010C4Eu, /* Base address: 0x40010C00 Count: 78 */\r
+ 0x40010D52u, /* Base address: 0x40010D00 Count: 82 */\r
+ 0x40010E42u, /* Base address: 0x40010E00 Count: 66 */\r
+ 0x40010F3Cu, /* Base address: 0x40010F00 Count: 60 */\r
+ 0x4001145Du, /* Base address: 0x40011400 Count: 93 */\r
+ 0x40011552u, /* Base address: 0x40011500 Count: 82 */\r
+ 0x40011653u, /* Base address: 0x40011600 Count: 83 */\r
+ 0x40011744u, /* Base address: 0x40011700 Count: 68 */\r
+ 0x40011912u, /* Base address: 0x40011900 Count: 18 */\r
+ 0x40011A4Au, /* Base address: 0x40011A00 Count: 74 */\r
+ 0x40011B47u, /* Base address: 0x40011B00 Count: 71 */\r
0x4001401Bu, /* Base address: 0x40014000 Count: 27 */\r
- 0x4001411Bu, /* Base address: 0x40014100 Count: 27 */\r
+ 0x4001411Du, /* Base address: 0x40014100 Count: 29 */\r
0x40014211u, /* Base address: 0x40014200 Count: 17 */\r
- 0x4001430Du, /* Base address: 0x40014300 Count: 13 */\r
- 0x40014411u, /* Base address: 0x40014400 Count: 17 */\r
+ 0x4001430Eu, /* Base address: 0x40014300 Count: 14 */\r
+ 0x4001440Du, /* Base address: 0x40014400 Count: 13 */\r
0x40014517u, /* Base address: 0x40014500 Count: 23 */\r
- 0x40014608u, /* Base address: 0x40014600 Count: 8 */\r
- 0x4001470Du, /* Base address: 0x40014700 Count: 13 */\r
- 0x40014806u, /* Base address: 0x40014800 Count: 6 */\r
- 0x40014908u, /* Base address: 0x40014900 Count: 8 */\r
+ 0x4001460Fu, /* Base address: 0x40014600 Count: 15 */\r
+ 0x4001470Bu, /* Base address: 0x40014700 Count: 11 */\r
+ 0x4001480Eu, /* Base address: 0x40014800 Count: 14 */\r
+ 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */\r
+ 0x40014C03u, /* Base address: 0x40014C00 Count: 3 */\r
0x40014D04u, /* Base address: 0x40014D00 Count: 4 */\r
- 0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
+ 0x40015005u, /* Base address: 0x40015000 Count: 5 */\r
0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
\r
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
- {0x0Au, 0x4Bu},\r
- {0x00u, 0x11u},\r
- {0x01u, 0x02u},\r
+ {0x0Au, 0x1Bu},\r
+ {0x00u, 0x14u},\r
+ {0x01u, 0x11u},\r
{0x18u, 0x08u},\r
{0x19u, 0x04u},\r
{0x1Cu, 0x71u},\r
- {0x20u, 0xA0u},\r
- {0x21u, 0x68u},\r
+ {0x20u, 0x60u},\r
+ {0x21u, 0xA0u},\r
{0x2Cu, 0x0Eu},\r
- {0x30u, 0x0Au},\r
- {0x31u, 0x0Cu},\r
+ {0x30u, 0x06u},\r
+ {0x31u, 0x03u},\r
{0x34u, 0x80u},\r
{0x7Cu, 0x40u},\r
{0x20u, 0x02u},\r
- {0x84u, 0x0Fu},\r
- {0x00u, 0x80u},\r
- {0x04u, 0x10u},\r
- {0x0Cu, 0x02u},\r
- {0x0Du, 0x02u},\r
- {0x0Eu, 0x28u},\r
- {0x10u, 0x01u},\r
- {0x14u, 0x32u},\r
- {0x15u, 0x04u},\r
- {0x16u, 0x44u},\r
- {0x1Au, 0x04u},\r
- {0x1Du, 0x08u},\r
- {0x24u, 0x4Cu},\r
- {0x26u, 0x32u},\r
- {0x29u, 0x01u},\r
- {0x2Eu, 0x7Eu},\r
- {0x30u, 0x0Eu},\r
- {0x31u, 0x08u},\r
- {0x32u, 0x70u},\r
- {0x33u, 0x04u},\r
- {0x34u, 0x01u},\r
- {0x35u, 0x01u},\r
- {0x36u, 0x80u},\r
- {0x37u, 0x02u},\r
+ {0x85u, 0x0Fu},\r
+ {0x00u, 0x01u},\r
+ {0x02u, 0x02u},\r
+ {0x04u, 0x04u},\r
+ {0x05u, 0x04u},\r
+ {0x14u, 0x02u},\r
+ {0x15u, 0x08u},\r
+ {0x16u, 0x01u},\r
+ {0x18u, 0x02u},\r
+ {0x1Au, 0x01u},\r
+ {0x1Cu, 0x10u},\r
+ {0x21u, 0x01u},\r
+ {0x24u, 0x02u},\r
+ {0x26u, 0x01u},\r
+ {0x2Bu, 0x02u},\r
+ {0x2Cu, 0x02u},\r
+ {0x2Eu, 0x09u},\r
+ {0x30u, 0x03u},\r
+ {0x31u, 0x04u},\r
+ {0x32u, 0x08u},\r
+ {0x33u, 0x08u},\r
+ {0x34u, 0x04u},\r
+ {0x35u, 0x02u},\r
+ {0x36u, 0x10u},\r
+ {0x37u, 0x01u},\r
+ {0x3Au, 0x02u},\r
{0x3Eu, 0x50u},\r
- {0x3Fu, 0x55u},\r
- {0x40u, 0x42u},\r
- {0x41u, 0x03u},\r
+ {0x3Fu, 0x45u},\r
+ {0x40u, 0x34u},\r
+ {0x41u, 0x06u},\r
{0x42u, 0x50u},\r
- {0x45u, 0xF2u},\r
- {0x46u, 0xCDu},\r
- {0x47u, 0x0Eu},\r
+ {0x45u, 0xCDu},\r
+ {0x46u, 0xE2u},\r
+ {0x47u, 0x0Fu},\r
{0x48u, 0x1Fu},\r
{0x49u, 0xFFu},\r
{0x4Au, 0xFFu},\r
{0x59u, 0x04u},\r
{0x5Au, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x01u},\r
+ {0x5Cu, 0x99u},\r
{0x5Du, 0x01u},\r
{0x5Fu, 0x01u},\r
{0x62u, 0xC0u},\r
{0x68u, 0x40u},\r
{0x69u, 0x40u},\r
{0x6Eu, 0x08u},\r
- {0x88u, 0x01u},\r
- {0xB6u, 0x01u},\r
- {0xBEu, 0x40u},\r
- {0xD8u, 0x04u},\r
+ {0xADu, 0x01u},\r
+ {0xB3u, 0x01u},\r
+ {0xBFu, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x41u},\r
- {0x03u, 0x10u},\r
- {0x05u, 0x10u},\r
- {0x0Au, 0x10u},\r
- {0x0Bu, 0x44u},\r
+ {0x01u, 0x02u},\r
+ {0x02u, 0x10u},\r
+ {0x09u, 0x80u},\r
+ {0x0Au, 0x18u},\r
{0x11u, 0x40u},\r
{0x12u, 0x20u},\r
- {0x18u, 0x40u},\r
- {0x19u, 0x48u},\r
- {0x1Au, 0x10u},\r
- {0x1Bu, 0x12u},\r
- {0x1Du, 0x80u},\r
- {0x20u, 0x04u},\r
+ {0x19u, 0x12u},\r
+ {0x1Au, 0x12u},\r
+ {0x1Bu, 0x04u},\r
{0x21u, 0x02u},\r
- {0x23u, 0x22u},\r
- {0x2Bu, 0x04u},\r
- {0x31u, 0x04u},\r
- {0x32u, 0x80u},\r
- {0x3Au, 0x40u},\r
- {0x41u, 0x10u},\r
- {0x42u, 0x10u},\r
- {0x43u, 0x02u},\r
- {0x48u, 0x01u},\r
- {0x49u, 0x02u},\r
- {0x4Bu, 0x04u},\r
- {0x50u, 0x10u},\r
- {0x52u, 0x04u},\r
- {0x53u, 0x80u},\r
- {0x59u, 0x40u},\r
- {0x5Au, 0x08u},\r
- {0x5Bu, 0x22u},\r
- {0x60u, 0x04u},\r
- {0x61u, 0x82u},\r
- {0x63u, 0x20u},\r
- {0x68u, 0x90u},\r
- {0x69u, 0x10u},\r
- {0x6Au, 0x80u},\r
- {0x70u, 0x60u},\r
- {0x72u, 0x40u},\r
- {0x73u, 0x10u},\r
- {0x81u, 0x02u},\r
- {0x83u, 0x10u},\r
- {0x85u, 0x40u},\r
- {0x88u, 0x40u},\r
- {0x89u, 0x08u},\r
- {0x8Cu, 0x40u},\r
- {0x8Eu, 0x10u},\r
- {0xC0u, 0x4Du},\r
- {0xC2u, 0x0Eu},\r
+ {0x22u, 0xA8u},\r
+ {0x27u, 0x10u},\r
+ {0x2Bu, 0x44u},\r
+ {0x2Fu, 0x01u},\r
+ {0x31u, 0x08u},\r
+ {0x3Au, 0x04u},\r
+ {0x41u, 0x04u},\r
+ {0x43u, 0x01u},\r
+ {0x48u, 0xD4u},\r
+ {0x49u, 0x04u},\r
+ {0x4Au, 0x01u},\r
+ {0x50u, 0x40u},\r
+ {0x53u, 0xA4u},\r
+ {0x5Au, 0x46u},\r
+ {0x5Bu, 0x10u},\r
+ {0x61u, 0x12u},\r
+ {0x62u, 0x88u},\r
+ {0x69u, 0x86u},\r
+ {0x6Bu, 0x08u},\r
+ {0x6Cu, 0x30u},\r
+ {0x6Eu, 0x08u},\r
+ {0x6Fu, 0x0Au},\r
+ {0x72u, 0x02u},\r
+ {0x73u, 0x64u},\r
+ {0x82u, 0x04u},\r
+ {0x83u, 0x08u},\r
+ {0x85u, 0x02u},\r
+ {0x87u, 0x02u},\r
+ {0x89u, 0x01u},\r
+ {0x8Du, 0x40u},\r
+ {0x8Fu, 0x20u},\r
+ {0xC0u, 0x0Cu},\r
+ {0xC2u, 0x07u},\r
{0xC4u, 0x05u},\r
- {0xCAu, 0x04u},\r
- {0xCCu, 0x0Au},\r
- {0xCEu, 0x08u},\r
- {0xD0u, 0x07u},\r
- {0xD2u, 0x08u},\r
+ {0xCAu, 0x15u},\r
+ {0xCCu, 0x02u},\r
+ {0xCEu, 0x02u},\r
+ {0xD0u, 0x03u},\r
+ {0xD2u, 0x0Cu},\r
{0xD6u, 0x0Fu},\r
{0xD8u, 0x0Fu},\r
- {0xE0u, 0x06u},\r
- {0xE2u, 0x10u},\r
- {0xE4u, 0x04u},\r
- {0xE6u, 0x20u},\r
- {0x09u, 0x05u},\r
- {0x0Bu, 0x0Au},\r
- {0x0Du, 0x0Fu},\r
- {0x0Eu, 0x01u},\r
- {0x0Fu, 0xF0u},\r
- {0x10u, 0x01u},\r
- {0x12u, 0x02u},\r
- {0x15u, 0x60u},\r
- {0x17u, 0x90u},\r
- {0x19u, 0x30u},\r
- {0x1Bu, 0xC0u},\r
- {0x1Du, 0x06u},\r
- {0x1Fu, 0x09u},\r
- {0x21u, 0x03u},\r
- {0x23u, 0x0Cu},\r
- {0x25u, 0x50u},\r
- {0x26u, 0x02u},\r
- {0x27u, 0xA0u},\r
- {0x30u, 0x03u},\r
- {0x37u, 0xFFu},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x40u},\r
+ {0xE4u, 0x0Cu},\r
+ {0xE6u, 0x02u},\r
+ {0x04u, 0x09u},\r
+ {0x05u, 0x0Cu},\r
+ {0x06u, 0x02u},\r
+ {0x07u, 0x30u},\r
+ {0x09u, 0x13u},\r
+ {0x0Bu, 0x44u},\r
+ {0x0Cu, 0x0Au},\r
+ {0x0Du, 0x08u},\r
+ {0x0Eu, 0x05u},\r
+ {0x13u, 0x7Fu},\r
+ {0x14u, 0x04u},\r
+ {0x16u, 0x08u},\r
+ {0x17u, 0x02u},\r
+ {0x1Au, 0x07u},\r
+ {0x1Du, 0x6Cu},\r
+ {0x1Fu, 0x13u},\r
+ {0x23u, 0x20u},\r
+ {0x25u, 0x03u},\r
+ {0x26u, 0x08u},\r
+ {0x29u, 0x71u},\r
+ {0x34u, 0x0Fu},\r
+ {0x37u, 0x7Fu},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
+ {0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x83u, 0x1Fu},\r
- {0x85u, 0x3Fu},\r
- {0x86u, 0x70u},\r
- {0x87u, 0x40u},\r
- {0x89u, 0x03u},\r
- {0x8Cu, 0x44u},\r
- {0x8Du, 0x20u},\r
- {0x8Eu, 0x88u},\r
- {0x8Fu, 0x5Cu},\r
- {0x94u, 0x99u},\r
- {0x95u, 0x18u},\r
- {0x96u, 0x22u},\r
- {0x97u, 0x03u},\r
- {0x98u, 0xAAu},\r
- {0x9Au, 0x55u},\r
- {0x9Bu, 0x01u},\r
- {0x9Du, 0x10u},\r
- {0x9Eu, 0x07u},\r
- {0x9Fu, 0x60u},\r
- {0xA1u, 0x02u},\r
- {0xA5u, 0x27u},\r
+ {0x83u, 0x08u},\r
+ {0x84u, 0x09u},\r
+ {0x85u, 0x44u},\r
+ {0x86u, 0x02u},\r
+ {0x87u, 0x88u},\r
+ {0x8Au, 0x07u},\r
+ {0x8Bu, 0x07u},\r
+ {0x8Cu, 0x40u},\r
+ {0x8Eu, 0x80u},\r
+ {0x8Fu, 0x80u},\r
+ {0x90u, 0x20u},\r
+ {0x94u, 0x10u},\r
+ {0x97u, 0x70u},\r
+ {0x99u, 0x99u},\r
+ {0x9Au, 0x40u},\r
+ {0x9Bu, 0x22u},\r
+ {0x9Du, 0xAAu},\r
+ {0x9Fu, 0x55u},\r
+ {0xA0u, 0x0Au},\r
+ {0xA2u, 0x05u},\r
{0xA6u, 0x08u},\r
- {0xA7u, 0x50u},\r
- {0xA9u, 0x80u},\r
- {0xAAu, 0x80u},\r
- {0xB3u, 0x80u},\r
- {0xB4u, 0xF0u},\r
+ {0xA8u, 0x04u},\r
+ {0xAAu, 0x08u},\r
+ {0xAEu, 0x80u},\r
+ {0xB0u, 0x20u},\r
+ {0xB2u, 0x0Fu},\r
+ {0xB3u, 0xF0u},\r
+ {0xB4u, 0x10u},\r
{0xB5u, 0x0Fu},\r
- {0xB6u, 0x0Fu},\r
- {0xB7u, 0x70u},\r
- {0xBBu, 0x80u},\r
- {0xBFu, 0x04u},\r
+ {0xB6u, 0xC0u},\r
+ {0xBEu, 0x51u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDCu, 0x11u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x40u},\r
- {0x03u, 0x20u},\r
- {0x05u, 0x40u},\r
+ {0x00u, 0x04u},\r
+ {0x03u, 0x0Au},\r
+ {0x04u, 0x04u},\r
+ {0x07u, 0x01u},\r
+ {0x08u, 0x0Au},\r
{0x09u, 0x20u},\r
- {0x0Au, 0x12u},\r
- {0x0Cu, 0x02u},\r
- {0x0Fu, 0x80u},\r
- {0x10u, 0x20u},\r
- {0x13u, 0x10u},\r
- {0x17u, 0x04u},\r
+ {0x0Cu, 0x10u},\r
+ {0x0Eu, 0x08u},\r
+ {0x0Fu, 0x10u},\r
+ {0x12u, 0x82u},\r
+ {0x13u, 0x14u},\r
+ {0x17u, 0x08u},\r
{0x19u, 0x40u},\r
- {0x1Au, 0x02u},\r
- {0x1Bu, 0x30u},\r
- {0x1Cu, 0x80u},\r
- {0x20u, 0x06u},\r
- {0x21u, 0xB0u},\r
- {0x22u, 0x24u},\r
- {0x23u, 0x08u},\r
- {0x25u, 0x40u},\r
- {0x28u, 0x08u},\r
- {0x29u, 0x08u},\r
- {0x2Bu, 0x80u},\r
- {0x2Du, 0x01u},\r
- {0x2Eu, 0x04u},\r
- {0x31u, 0x80u},\r
- {0x32u, 0x08u},\r
- {0x33u, 0x10u},\r
- {0x34u, 0x10u},\r
- {0x35u, 0x40u},\r
- {0x37u, 0x04u},\r
- {0x38u, 0x64u},\r
+ {0x1Au, 0x44u},\r
+ {0x1Bu, 0x08u},\r
+ {0x1Eu, 0x08u},\r
+ {0x21u, 0x30u},\r
+ {0x22u, 0x08u},\r
+ {0x26u, 0x80u},\r
+ {0x27u, 0x01u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Eu, 0x20u},\r
+ {0x2Fu, 0x80u},\r
+ {0x32u, 0x98u},\r
+ {0x35u, 0x06u},\r
+ {0x36u, 0x80u},\r
+ {0x39u, 0xA8u},\r
{0x3Au, 0x02u},\r
- {0x3Fu, 0xA0u},\r
- {0x58u, 0x66u},\r
- {0x5Du, 0x80u},\r
- {0x5Fu, 0x20u},\r
- {0x61u, 0x04u},\r
- {0x62u, 0x80u},\r
- {0x63u, 0x48u},\r
- {0x65u, 0x30u},\r
- {0x66u, 0x40u},\r
- {0x67u, 0x02u},\r
- {0x6Du, 0x28u},\r
- {0x6Eu, 0x80u},\r
- {0x6Fu, 0x10u},\r
- {0x80u, 0x30u},\r
- {0x85u, 0x80u},\r
- {0x86u, 0x40u},\r
- {0x87u, 0xA0u},\r
- {0x88u, 0x42u},\r
- {0x8Au, 0x0Au},\r
- {0x8Du, 0x04u},\r
- {0x90u, 0x60u},\r
- {0x91u, 0x10u},\r
- {0x92u, 0xF0u},\r
- {0x93u, 0x14u},\r
- {0x94u, 0x01u},\r
- {0x95u, 0x60u},\r
- {0x96u, 0x08u},\r
- {0x97u, 0x40u},\r
- {0x99u, 0x08u},\r
- {0x9Du, 0x14u},\r
- {0x9Eu, 0x40u},\r
- {0x9Fu, 0x10u},\r
- {0xA0u, 0xA0u},\r
- {0xA3u, 0x82u},\r
- {0xA4u, 0x45u},\r
- {0xA5u, 0x40u},\r
- {0xA6u, 0xA0u},\r
- {0xA7u, 0x04u},\r
- {0xAAu, 0x04u},\r
- {0xACu, 0x14u},\r
- {0xADu, 0x10u},\r
- {0xB7u, 0x02u},\r
- {0xC0u, 0x85u},\r
- {0xC2u, 0x17u},\r
- {0xC4u, 0x26u},\r
- {0xCAu, 0xC7u},\r
- {0xCCu, 0x7Eu},\r
- {0xCEu, 0x3Fu},\r
- {0xD6u, 0x3Fu},\r
- {0xD8u, 0x3Fu},\r
- {0xE0u, 0x04u},\r
- {0xE2u, 0x0Au},\r
- {0xE4u, 0x08u},\r
- {0xE6u, 0x24u},\r
- {0xE8u, 0x0Bu},\r
- {0xEEu, 0x01u},\r
- {0x02u, 0x07u},\r
- {0x07u, 0x10u},\r
- {0x09u, 0x0Au},\r
- {0x0Bu, 0x05u},\r
- {0x0Cu, 0x44u},\r
- {0x0Du, 0x04u},\r
- {0x0Eu, 0x88u},\r
- {0x0Fu, 0x08u},\r
- {0x11u, 0x10u},\r
- {0x13u, 0x20u},\r
- {0x14u, 0x99u},\r
- {0x16u, 0x22u},\r
- {0x17u, 0x07u},\r
- {0x1Eu, 0x70u},\r
- {0x1Fu, 0x08u},\r
- {0x22u, 0x80u},\r
- {0x23u, 0x20u},\r
- {0x24u, 0xAAu},\r
- {0x25u, 0x09u},\r
- {0x26u, 0x55u},\r
- {0x27u, 0x02u},\r
- {0x2Au, 0x08u},\r
- {0x30u, 0x0Fu},\r
- {0x33u, 0x0Fu},\r
- {0x35u, 0x30u},\r
- {0x36u, 0xF0u},\r
+ {0x3Cu, 0x88u},\r
{0x3Fu, 0x10u},\r
+ {0x5Au, 0x80u},\r
+ {0x5Bu, 0x26u},\r
+ {0x5Fu, 0x80u},\r
+ {0x61u, 0x80u},\r
+ {0x62u, 0x14u},\r
+ {0x63u, 0xA0u},\r
+ {0x64u, 0x01u},\r
+ {0x67u, 0x02u},\r
+ {0x83u, 0x30u},\r
+ {0x85u, 0x40u},\r
+ {0x87u, 0x03u},\r
+ {0x88u, 0x10u},\r
+ {0x8Au, 0x10u},\r
+ {0x8Bu, 0x02u},\r
+ {0x90u, 0xA0u},\r
+ {0x91u, 0x84u},\r
+ {0x93u, 0x44u},\r
+ {0x95u, 0x08u},\r
+ {0x96u, 0x4Cu},\r
+ {0x97u, 0x02u},\r
+ {0x99u, 0x26u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Eu, 0x14u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA0u, 0x60u},\r
+ {0xA2u, 0x20u},\r
+ {0xA3u, 0x80u},\r
+ {0xA4u, 0x04u},\r
+ {0xA5u, 0x88u},\r
+ {0xA6u, 0x01u},\r
+ {0xA7u, 0x40u},\r
+ {0xABu, 0xC0u},\r
+ {0xACu, 0x10u},\r
+ {0xADu, 0x20u},\r
+ {0xAFu, 0x04u},\r
+ {0xB0u, 0x80u},\r
+ {0xB1u, 0x80u},\r
+ {0xB7u, 0x20u},\r
+ {0xC0u, 0xA7u},\r
+ {0xC2u, 0x6Eu},\r
+ {0xC4u, 0x2Fu},\r
+ {0xCAu, 0xE0u},\r
+ {0xCCu, 0xDEu},\r
+ {0xCEu, 0x7Fu},\r
+ {0xD6u, 0x1Fu},\r
+ {0xD8u, 0x1Fu},\r
+ {0xE0u, 0x02u},\r
+ {0xE2u, 0x01u},\r
+ {0xE4u, 0x01u},\r
+ {0xE6u, 0x02u},\r
+ {0xE8u, 0x0Cu},\r
+ {0xECu, 0x0Cu},\r
+ {0xEEu, 0x82u},\r
+ {0x04u, 0x02u},\r
+ {0x05u, 0x0Bu},\r
+ {0x07u, 0x90u},\r
+ {0x09u, 0x20u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Bu, 0x03u},\r
+ {0x0Cu, 0x02u},\r
+ {0x0Fu, 0x04u},\r
+ {0x12u, 0x20u},\r
+ {0x15u, 0x08u},\r
+ {0x16u, 0x08u},\r
+ {0x19u, 0x21u},\r
+ {0x1Au, 0x10u},\r
+ {0x1Bu, 0x44u},\r
+ {0x1Cu, 0x02u},\r
+ {0x1Du, 0x14u},\r
+ {0x1Fu, 0xABu},\r
+ {0x20u, 0x02u},\r
+ {0x21u, 0x40u},\r
+ {0x23u, 0xBFu},\r
+ {0x26u, 0x01u},\r
+ {0x28u, 0x14u},\r
+ {0x2Au, 0x28u},\r
+ {0x2Bu, 0x0Eu},\r
+ {0x30u, 0x02u},\r
+ {0x32u, 0x0Cu},\r
+ {0x33u, 0x1Fu},\r
+ {0x34u, 0x01u},\r
+ {0x35u, 0xE0u},\r
+ {0x36u, 0x30u},\r
+ {0x38u, 0x02u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Eu, 0x45u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
+ {0x5Cu, 0x19u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x10u},\r
- {0x85u, 0x69u},\r
- {0x86u, 0x20u},\r
- {0x87u, 0x96u},\r
- {0x88u, 0x06u},\r
- {0x8Au, 0x09u},\r
- {0x8Bu, 0xFFu},\r
- {0x8Cu, 0x07u},\r
- {0x8Eu, 0x08u},\r
- {0x8Fu, 0xFFu},\r
- {0x90u, 0x03u},\r
- {0x91u, 0x0Fu},\r
- {0x92u, 0x0Cu},\r
- {0x93u, 0xF0u},\r
- {0x94u, 0x05u},\r
- {0x95u, 0xFFu},\r
- {0x96u, 0x0Au},\r
- {0x99u, 0xFFu},\r
- {0x9Au, 0x02u},\r
- {0xA2u, 0x10u},\r
- {0xA3u, 0xFFu},\r
- {0xA6u, 0x20u},\r
- {0xA8u, 0x01u},\r
- {0xA9u, 0x55u},\r
- {0xABu, 0xAAu},\r
- {0xADu, 0x33u},\r
- {0xAEu, 0x03u},\r
- {0xAFu, 0xCCu},\r
- {0xB0u, 0x0Fu},\r
- {0xB4u, 0x30u},\r
- {0xB7u, 0xFFu},\r
- {0xBAu, 0x02u},\r
- {0xBBu, 0x80u},\r
+ {0x80u, 0x01u},\r
+ {0x85u, 0x01u},\r
+ {0x87u, 0x02u},\r
+ {0x88u, 0x02u},\r
+ {0x89u, 0x04u},\r
+ {0x8Bu, 0x03u},\r
+ {0x95u, 0x08u},\r
+ {0x97u, 0x03u},\r
+ {0x9Bu, 0x01u},\r
+ {0x9Cu, 0x0Eu},\r
+ {0x9Fu, 0x0Cu},\r
+ {0xA4u, 0x08u},\r
+ {0xAAu, 0x04u},\r
+ {0xABu, 0x02u},\r
+ {0xAEu, 0x0Eu},\r
+ {0xB0u, 0x01u},\r
+ {0xB1u, 0x0Fu},\r
+ {0xB4u, 0x0Eu},\r
{0xBEu, 0x10u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDCu, 0x11u},\r
+ {0xDCu, 0x09u},\r
{0xDFu, 0x01u},\r
{0x00u, 0x40u},\r
- {0x01u, 0x02u},\r
- {0x04u, 0x40u},\r
- {0x06u, 0x20u},\r
- {0x07u, 0x08u},\r
- {0x0Au, 0x12u},\r
- {0x0Eu, 0x90u},\r
- {0x0Fu, 0x04u},\r
+ {0x02u, 0x10u},\r
+ {0x03u, 0x08u},\r
+ {0x05u, 0x02u},\r
+ {0x06u, 0x08u},\r
+ {0x08u, 0x10u},\r
+ {0x09u, 0x02u},\r
+ {0x0Au, 0x11u},\r
+ {0x0Du, 0x40u},\r
{0x10u, 0x80u},\r
- {0x11u, 0x10u},\r
- {0x13u, 0x08u},\r
- {0x14u, 0x10u},\r
- {0x15u, 0x01u},\r
- {0x16u, 0x12u},\r
- {0x17u, 0x10u},\r
- {0x19u, 0x02u},\r
- {0x1Au, 0x02u},\r
- {0x1Du, 0x20u},\r
- {0x1Eu, 0x80u},\r
- {0x20u, 0x08u},\r
- {0x21u, 0x08u},\r
- {0x27u, 0x01u},\r
- {0x29u, 0x08u},\r
- {0x2Bu, 0x40u},\r
- {0x2Du, 0x20u},\r
- {0x2Eu, 0x02u},\r
- {0x2Fu, 0x01u},\r
- {0x30u, 0x02u},\r
- {0x31u, 0x08u},\r
- {0x32u, 0x40u},\r
- {0x36u, 0x28u},\r
- {0x37u, 0x01u},\r
- {0x38u, 0x48u},\r
- {0x39u, 0x20u},\r
- {0x3Cu, 0x40u},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x08u},\r
- {0x5Bu, 0xA0u},\r
- {0x60u, 0x09u},\r
- {0x68u, 0x02u},\r
- {0x80u, 0x01u},\r
- {0x83u, 0x10u},\r
- {0x85u, 0x02u},\r
- {0x89u, 0x10u},\r
- {0x8Au, 0x40u},\r
- {0x8Cu, 0x24u},\r
- {0x8Du, 0x10u},\r
- {0x8Eu, 0x02u},\r
- {0x90u, 0x40u},\r
- {0x91u, 0x30u},\r
- {0x92u, 0xF0u},\r
- {0x93u, 0x46u},\r
- {0x94u, 0x01u},\r
- {0x95u, 0x01u},\r
- {0x99u, 0x28u},\r
- {0x9Bu, 0x98u},\r
- {0x9Cu, 0x18u},\r
- {0x9Fu, 0x04u},\r
- {0xA0u, 0x80u},\r
- {0xA1u, 0x04u},\r
- {0xA2u, 0xA8u},\r
- {0xA3u, 0x06u},\r
- {0xA4u, 0x06u},\r
+ {0x12u, 0x24u},\r
+ {0x17u, 0x98u},\r
+ {0x19u, 0x08u},\r
+ {0x1Au, 0x88u},\r
+ {0x1Bu, 0x40u},\r
+ {0x1Du, 0x10u},\r
+ {0x1Eu, 0x40u},\r
+ {0x20u, 0x0Cu},\r
+ {0x21u, 0x14u},\r
+ {0x22u, 0x10u},\r
+ {0x23u, 0x10u},\r
+ {0x27u, 0x80u},\r
+ {0x29u, 0x02u},\r
+ {0x2Au, 0x20u},\r
+ {0x2Cu, 0x08u},\r
+ {0x31u, 0x04u},\r
+ {0x32u, 0x90u},\r
+ {0x36u, 0x10u},\r
+ {0x37u, 0x88u},\r
+ {0x38u, 0xA0u},\r
+ {0x39u, 0x18u},\r
+ {0x3Cu, 0x20u},\r
+ {0x3Eu, 0x0Cu},\r
+ {0x44u, 0x02u},\r
+ {0x45u, 0x40u},\r
+ {0x58u, 0x80u},\r
+ {0x5Bu, 0x24u},\r
+ {0x60u, 0x0Au},\r
+ {0x61u, 0x08u},\r
+ {0x82u, 0x40u},\r
+ {0x83u, 0x04u},\r
+ {0x86u, 0x02u},\r
+ {0x88u, 0x04u},\r
+ {0x89u, 0x14u},\r
+ {0x8Du, 0x08u},\r
+ {0x8Fu, 0x40u},\r
+ {0x90u, 0xA0u},\r
+ {0x91u, 0x04u},\r
+ {0x93u, 0x40u},\r
+ {0x94u, 0x04u},\r
+ {0x95u, 0x08u},\r
+ {0x96u, 0x28u},\r
+ {0x97u, 0x10u},\r
+ {0x98u, 0x11u},\r
+ {0x99u, 0x26u},\r
+ {0x9Cu, 0x0Au},\r
+ {0x9Eu, 0x20u},\r
+ {0xA1u, 0x20u},\r
+ {0xA2u, 0xA0u},\r
+ {0xA3u, 0x08u},\r
+ {0xA4u, 0x04u},\r
+ {0xA5u, 0x08u},\r
{0xA6u, 0x02u},\r
- {0xABu, 0xB0u},\r
- {0xACu, 0x04u},\r
- {0xB2u, 0x04u},\r
- {0xB3u, 0x08u},\r
- {0xB5u, 0x50u},\r
- {0xB6u, 0x02u},\r
- {0xC0u, 0xE9u},\r
- {0xC2u, 0x75u},\r
- {0xC4u, 0xFEu},\r
- {0xCAu, 0xB3u},\r
- {0xCCu, 0xEBu},\r
- {0xCEu, 0x7Eu},\r
- {0xD6u, 0x0Cu},\r
- {0xD8u, 0x0Cu},\r
- {0xE0u, 0x05u},\r
- {0xE2u, 0x20u},\r
- {0xE4u, 0x08u},\r
- {0xE6u, 0x80u},\r
- {0xEAu, 0x09u},\r
- {0xECu, 0x04u},\r
- {0xEEu, 0x10u},\r
+ {0xAAu, 0x01u},\r
+ {0xABu, 0x04u},\r
+ {0xAEu, 0x08u},\r
+ {0xAFu, 0x80u},\r
+ {0xB6u, 0x40u},\r
+ {0xC0u, 0x57u},\r
+ {0xC2u, 0x8Fu},\r
+ {0xC4u, 0xEEu},\r
+ {0xCAu, 0x25u},\r
+ {0xCCu, 0x7Eu},\r
+ {0xCEu, 0x6Eu},\r
+ {0xD6u, 0x0Eu},\r
+ {0xD8u, 0x0Eu},\r
+ {0xE0u, 0x02u},\r
+ {0xE2u, 0x41u},\r
+ {0xE8u, 0x08u},\r
+ {0xEAu, 0x07u},\r
+ {0xEEu, 0x41u},\r
{0x00u, 0x0Du},\r
- {0x04u, 0x01u},\r
- {0x05u, 0x0Fu},\r
- {0x06u, 0x32u},\r
- {0x08u, 0x62u},\r
- {0x09u, 0x03u},\r
- {0x0Au, 0x08u},\r
- {0x0Bu, 0x0Cu},\r
+ {0x04u, 0x0Du},\r
+ {0x07u, 0xFFu},\r
+ {0x08u, 0x0Du},\r
+ {0x0Bu, 0xFFu},\r
+ {0x0Du, 0x33u},\r
+ {0x0Fu, 0xCCu},\r
{0x10u, 0x02u},\r
- {0x11u, 0x05u},\r
+ {0x11u, 0x55u},\r
{0x12u, 0x0Du},\r
- {0x13u, 0x0Au},\r
- {0x14u, 0x0Du},\r
- {0x15u, 0x20u},\r
- {0x17u, 0x4Fu},\r
- {0x1Au, 0x10u},\r
- {0x1Cu, 0x02u},\r
- {0x1Eu, 0x54u},\r
- {0x1Fu, 0x70u},\r
+ {0x13u, 0xAAu},\r
+ {0x15u, 0x69u},\r
+ {0x16u, 0x80u},\r
+ {0x17u, 0x96u},\r
+ {0x18u, 0x01u},\r
+ {0x19u, 0x0Fu},\r
+ {0x1Au, 0x32u},\r
+ {0x1Bu, 0xF0u},\r
+ {0x1Du, 0xFFu},\r
+ {0x1Eu, 0x10u},\r
{0x20u, 0x0Du},\r
- {0x24u, 0x0Du},\r
- {0x25u, 0x06u},\r
- {0x27u, 0x09u},\r
- {0x29u, 0x10u},\r
- {0x2Bu, 0x2Fu},\r
+ {0x23u, 0xFFu},\r
+ {0x24u, 0x62u},\r
+ {0x26u, 0x08u},\r
+ {0x28u, 0x02u},\r
+ {0x29u, 0xFFu},\r
+ {0x2Au, 0x54u},\r
{0x2Cu, 0x0Du},\r
- {0x2Du, 0x40u},\r
- {0x2Fu, 0x1Fu},\r
{0x30u, 0x0Fu},\r
- {0x31u, 0x7Fu},\r
- {0x34u, 0x70u},\r
+ {0x32u, 0x80u},\r
+ {0x35u, 0xFFu},\r
+ {0x36u, 0x70u},\r
{0x3Au, 0x02u},\r
- {0x54u, 0x01u},\r
+ {0x3Bu, 0x20u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
{0x5Cu, 0x10u},\r
- {0x5Du, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x96u},\r
- {0x82u, 0x69u},\r
- {0x85u, 0x02u},\r
- {0x87u, 0x11u},\r
+ {0x80u, 0xFFu},\r
+ {0x84u, 0x30u},\r
+ {0x86u, 0xC0u},\r
+ {0x87u, 0x80u},\r
{0x88u, 0x0Fu},\r
+ {0x89u, 0x44u},\r
{0x8Au, 0xF0u},\r
- {0x8Du, 0x01u},\r
- {0x8Eu, 0xFFu},\r
- {0x8Fu, 0x02u},\r
- {0x90u, 0x55u},\r
- {0x92u, 0xAAu},\r
- {0x95u, 0x02u},\r
- {0x96u, 0xFFu},\r
- {0x97u, 0x05u},\r
- {0x99u, 0x02u},\r
- {0x9Au, 0xFFu},\r
- {0x9Bu, 0x09u},\r
- {0x9Cu, 0x33u},\r
- {0x9Du, 0x02u},\r
- {0x9Eu, 0xCCu},\r
- {0x9Fu, 0x01u},\r
- {0xA4u, 0xFFu},\r
- {0xA8u, 0xFFu},\r
- {0xB1u, 0x03u},\r
- {0xB3u, 0x08u},\r
- {0xB4u, 0xFFu},\r
- {0xB5u, 0x10u},\r
- {0xB7u, 0x04u},\r
- {0xBAu, 0x20u},\r
- {0xBBu, 0x02u},\r
- {0xD6u, 0x08u},\r
+ {0x8Bu, 0x88u},\r
+ {0x8Cu, 0xFFu},\r
+ {0x8Fu, 0x08u},\r
+ {0x90u, 0x50u},\r
+ {0x92u, 0xA0u},\r
+ {0x93u, 0x07u},\r
+ {0x94u, 0x09u},\r
+ {0x96u, 0x06u},\r
+ {0x97u, 0x70u},\r
+ {0x98u, 0x05u},\r
+ {0x99u, 0x99u},\r
+ {0x9Au, 0x0Au},\r
+ {0x9Bu, 0x22u},\r
+ {0x9Du, 0xAAu},\r
+ {0x9Fu, 0x55u},\r
+ {0xA4u, 0x03u},\r
+ {0xA6u, 0x0Cu},\r
+ {0xAAu, 0xFFu},\r
+ {0xACu, 0x90u},\r
+ {0xAEu, 0x60u},\r
+ {0xB0u, 0xFFu},\r
+ {0xB1u, 0x0Fu},\r
+ {0xB3u, 0xF0u},\r
+ {0xBEu, 0x01u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x91u},\r
- {0xDDu, 0x90u},\r
+ {0xDCu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x20u},\r
- {0x02u, 0x80u},\r
- {0x03u, 0x02u},\r
- {0x04u, 0x08u},\r
- {0x05u, 0x10u},\r
- {0x07u, 0x40u},\r
- {0x08u, 0x20u},\r
- {0x0Au, 0x10u},\r
- {0x0Bu, 0x41u},\r
- {0x0Cu, 0x08u},\r
- {0x0Eu, 0x8Au},\r
- {0x12u, 0x08u},\r
- {0x13u, 0x08u},\r
- {0x15u, 0x06u},\r
- {0x16u, 0x02u},\r
- {0x19u, 0x20u},\r
- {0x1Bu, 0x20u},\r
- {0x1Eu, 0x88u},\r
- {0x20u, 0x40u},\r
- {0x21u, 0x28u},\r
- {0x22u, 0x40u},\r
- {0x27u, 0x80u},\r
- {0x2Eu, 0x10u},\r
- {0x2Fu, 0x22u},\r
- {0x31u, 0x28u},\r
- {0x32u, 0x40u},\r
- {0x37u, 0x89u},\r
- {0x38u, 0x44u},\r
- {0x39u, 0x80u},\r
- {0x3Du, 0x28u},\r
+ {0x00u, 0x04u},\r
+ {0x01u, 0x80u},\r
+ {0x02u, 0x44u},\r
+ {0x03u, 0x08u},\r
+ {0x04u, 0x28u},\r
+ {0x07u, 0x40u},\r
+ {0x08u, 0x14u},\r
+ {0x09u, 0x02u},\r
+ {0x0Cu, 0x08u},\r
+ {0x0Eu, 0x46u},\r
+ {0x10u, 0x20u},\r
+ {0x11u, 0x10u},\r
+ {0x12u, 0x01u},\r
+ {0x15u, 0x41u},\r
+ {0x17u, 0x18u},\r
+ {0x18u, 0x40u},\r
+ {0x1Eu, 0x62u},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0x01u},\r
+ {0x26u, 0x20u},\r
+ {0x2Du, 0x02u},\r
+ {0x2Eu, 0x20u},\r
+ {0x31u, 0x08u},\r
+ {0x32u, 0x91u},\r
+ {0x34u, 0x09u},\r
+ {0x36u, 0xA0u},\r
+ {0x39u, 0x04u},\r
+ {0x3Bu, 0x50u},\r
+ {0x3Cu, 0x08u},\r
+ {0x3Du, 0x80u},\r
+ {0x3Fu, 0x10u},\r
{0x58u, 0x80u},\r
- {0x5Au, 0x20u},\r
- {0x5Fu, 0x80u},\r
- {0x60u, 0x04u},\r
- {0x63u, 0x01u},\r
- {0x83u, 0x40u},\r
- {0x8Au, 0x11u},\r
- {0x8Fu, 0x04u},\r
- {0x92u, 0x72u},\r
- {0x93u, 0x40u},\r
- {0x95u, 0x01u},\r
- {0x98u, 0xA0u},\r
- {0x99u, 0x08u},\r
- {0x9Bu, 0x09u},\r
- {0x9Eu, 0x10u},\r
- {0x9Fu, 0x04u},\r
- {0xA1u, 0x14u},\r
- {0xA2u, 0x88u},\r
- {0xA3u, 0x02u},\r
- {0xA6u, 0x02u},\r
- {0xA7u, 0x40u},\r
- {0xA8u, 0x02u},\r
- {0xAAu, 0x20u},\r
+ {0x59u, 0x22u},\r
+ {0x5Au, 0x08u},\r
+ {0x63u, 0x02u},\r
+ {0x80u, 0x80u},\r
+ {0x85u, 0x10u},\r
+ {0x88u, 0x20u},\r
+ {0x89u, 0x08u},\r
+ {0x8Au, 0x01u},\r
+ {0x8Bu, 0x01u},\r
+ {0x8Eu, 0x01u},\r
+ {0x91u, 0x14u},\r
+ {0x92u, 0x20u},\r
+ {0x93u, 0x50u},\r
+ {0x94u, 0x40u},\r
+ {0x95u, 0x80u},\r
+ {0x96u, 0x15u},\r
+ {0x98u, 0x19u},\r
+ {0x99u, 0x32u},\r
+ {0x9Au, 0x20u},\r
+ {0x9Eu, 0x14u},\r
+ {0x9Fu, 0x18u},\r
+ {0xA0u, 0x04u},\r
+ {0xA1u, 0x40u},\r
+ {0xA2u, 0x80u},\r
+ {0xA4u, 0x98u},\r
+ {0xA5u, 0x02u},\r
+ {0xA6u, 0x12u},\r
+ {0xAAu, 0x60u},\r
{0xABu, 0x20u},\r
{0xACu, 0x80u},\r
- {0xB1u, 0x28u},\r
- {0xB4u, 0x08u},\r
- {0xC0u, 0x7Bu},\r
- {0xC2u, 0xFFu},\r
- {0xC4u, 0xB6u},\r
- {0xCAu, 0x70u},\r
- {0xCCu, 0xDEu},\r
- {0xCEu, 0x6Au},\r
- {0xD6u, 0x1Cu},\r
- {0xD8u, 0x0Cu},\r
- {0xE2u, 0x44u},\r
- {0xE6u, 0xCAu},\r
- {0xE8u, 0x04u},\r
- {0xEAu, 0x01u},\r
- {0xEEu, 0x86u},\r
- {0x00u, 0x01u},\r
- {0x01u, 0x02u},\r
- {0x02u, 0x02u},\r
- {0x03u, 0x01u},\r
- {0x08u, 0x02u},\r
- {0x0Au, 0x01u},\r
- {0x0Cu, 0x04u},\r
- {0x0Eu, 0x08u},\r
- {0x15u, 0x02u},\r
- {0x16u, 0x20u},\r
- {0x17u, 0x01u},\r
- {0x19u, 0x02u},\r
- {0x1Au, 0x10u},\r
- {0x1Bu, 0x01u},\r
- {0x1Du, 0x01u},\r
- {0x1Eu, 0x40u},\r
- {0x1Fu, 0x02u},\r
- {0x20u, 0x08u},\r
- {0x22u, 0x04u},\r
- {0x28u, 0x03u},\r
- {0x2Au, 0x0Cu},\r
- {0x2Du, 0x02u},\r
- {0x2Fu, 0x01u},\r
- {0x30u, 0x10u},\r
- {0x32u, 0x40u},\r
- {0x34u, 0x20u},\r
- {0x36u, 0x0Fu},\r
- {0x37u, 0x03u},\r
- {0x3Bu, 0x80u},\r
- {0x3Eu, 0x40u},\r
- {0x58u, 0x04u},\r
+ {0xB1u, 0x08u},\r
+ {0xB5u, 0x20u},\r
+ {0xB7u, 0x08u},\r
+ {0xC0u, 0x7Fu},\r
+ {0xC2u, 0xFEu},\r
+ {0xC4u, 0xF7u},\r
+ {0xCAu, 0xA0u},\r
+ {0xCCu, 0xFFu},\r
+ {0xCEu, 0x7Eu},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x08u},\r
+ {0xE2u, 0x58u},\r
+ {0xE6u, 0x01u},\r
+ {0xEAu, 0x05u},\r
+ {0xEEu, 0x02u},\r
+ {0x39u, 0x80u},\r
+ {0x3Fu, 0x40u},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Cu, 0x99u},\r
{0x5Fu, 0x01u},\r
- {0x87u, 0x10u},\r
- {0x89u, 0x02u},\r
- {0x8Bu, 0x01u},\r
- {0x8Du, 0x02u},\r
- {0x8Fu, 0x01u},\r
- {0x91u, 0x01u},\r
- {0x93u, 0x02u},\r
- {0x95u, 0x10u},\r
- {0x97u, 0x20u},\r
- {0x9Du, 0x04u},\r
- {0xA3u, 0x20u},\r
- {0xA5u, 0x08u},\r
- {0xA9u, 0x02u},\r
- {0xABu, 0x01u},\r
- {0xADu, 0x02u},\r
- {0xAFu, 0x01u},\r
- {0xB1u, 0x03u},\r
- {0xB3u, 0x08u},\r
- {0xB5u, 0x04u},\r
- {0xB7u, 0x30u},\r
- {0xBBu, 0x02u},\r
- {0xBFu, 0x40u},\r
- {0xD6u, 0x08u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x90u},\r
- {0xDDu, 0x90u},\r
- {0xDFu, 0x01u},\r
- {0x05u, 0x01u},\r
- {0x06u, 0x09u},\r
- {0x0Eu, 0x28u},\r
- {0x0Fu, 0x02u},\r
- {0x14u, 0x04u},\r
- {0x15u, 0x01u},\r
- {0x1Du, 0x40u},\r
- {0x1Eu, 0x28u},\r
- {0x1Fu, 0x01u},\r
- {0x21u, 0x42u},\r
- {0x22u, 0x04u},\r
- {0x23u, 0x48u},\r
- {0x25u, 0x80u},\r
- {0x26u, 0x80u},\r
- {0x28u, 0x02u},\r
- {0x29u, 0x10u},\r
- {0x2Bu, 0xA0u},\r
- {0x2Fu, 0x01u},\r
- {0x30u, 0x04u},\r
- {0x31u, 0x82u},\r
- {0x32u, 0x08u},\r
- {0x36u, 0x94u},\r
- {0x38u, 0x90u},\r
- {0x3Au, 0x08u},\r
- {0x3Fu, 0x02u},\r
- {0x58u, 0x80u},\r
- {0x5Du, 0x06u},\r
- {0x5Fu, 0x60u},\r
- {0x63u, 0x02u},\r
- {0x65u, 0x80u},\r
- {0x6Cu, 0x16u},\r
- {0x6Du, 0x41u},\r
- {0x6Fu, 0x80u},\r
- {0x74u, 0x80u},\r
- {0x76u, 0x95u},\r
- {0x80u, 0x80u},\r
- {0x86u, 0x04u},\r
- {0x8Au, 0x88u},\r
- {0x8Bu, 0x08u},\r
- {0x8Eu, 0x04u},\r
- {0x90u, 0x90u},\r
- {0x94u, 0x28u},\r
- {0x95u, 0xC0u},\r
- {0x98u, 0x02u},\r
- {0x99u, 0x91u},\r
- {0x9Du, 0x40u},\r
- {0x9Eu, 0x10u},\r
- {0xA2u, 0x08u},\r
- {0xA3u, 0x20u},\r
- {0xA4u, 0x02u},\r
- {0xA8u, 0x80u},\r
- {0xAAu, 0x08u},\r
- {0xABu, 0x01u},\r
- {0xB0u, 0x40u},\r
- {0xB1u, 0x10u},\r
- {0xB2u, 0x80u},\r
- {0xB7u, 0x80u},\r
- {0xC0u, 0xD0u},\r
- {0xC2u, 0xE0u},\r
- {0xC4u, 0x50u},\r
- {0xCAu, 0x1Fu},\r
- {0xCCu, 0x7Bu},\r
- {0xCEu, 0x8Eu},\r
- {0xD6u, 0xF8u},\r
- {0xD8u, 0x18u},\r
- {0xE0u, 0x20u},\r
- {0xE2u, 0x40u},\r
- {0xE6u, 0xF2u},\r
- {0xE8u, 0x40u},\r
+ {0x24u, 0x02u},\r
+ {0x7Au, 0x30u},\r
+ {0x80u, 0x14u},\r
+ {0x88u, 0x20u},\r
+ {0x89u, 0x10u},\r
+ {0x8Au, 0x08u},\r
+ {0x8Cu, 0x01u},\r
+ {0x90u, 0x10u},\r
+ {0x91u, 0x02u},\r
+ {0x94u, 0x08u},\r
+ {0x95u, 0x01u},\r
+ {0x97u, 0x01u},\r
+ {0x98u, 0x28u},\r
+ {0x9Au, 0x22u},\r
+ {0x9Bu, 0x10u},\r
+ {0x9Du, 0x0Bu},\r
+ {0x9Eu, 0x18u},\r
+ {0xA2u, 0x62u},\r
+ {0xA4u, 0x80u},\r
+ {0xABu, 0x02u},\r
+ {0xB2u, 0x04u},\r
+ {0xB6u, 0x01u},\r
+ {0xB7u, 0x10u},\r
+ {0xE0u, 0x24u},\r
+ {0xE2u, 0xC8u},\r
+ {0xE4u, 0x20u},\r
+ {0xE8u, 0x10u},\r
{0xEAu, 0x01u},\r
- {0xECu, 0x20u},\r
+ {0xECu, 0x60u},\r
{0xEEu, 0x02u},\r
- {0x03u, 0xFFu},\r
- {0x05u, 0x50u},\r
- {0x07u, 0xA0u},\r
- {0x09u, 0x30u},\r
- {0x0Bu, 0xC0u},\r
- {0x0Du, 0x06u},\r
+ {0x00u, 0x04u},\r
+ {0x02u, 0x08u},\r
+ {0x04u, 0x02u},\r
+ {0x06u, 0x01u},\r
+ {0x07u, 0x20u},\r
+ {0x08u, 0x01u},\r
+ {0x09u, 0x04u},\r
+ {0x0Au, 0x02u},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Cu, 0x02u},\r
+ {0x0Du, 0x03u},\r
{0x0Eu, 0x01u},\r
- {0x0Fu, 0x09u},\r
- {0x11u, 0x60u},\r
- {0x12u, 0x04u},\r
- {0x13u, 0x90u},\r
- {0x17u, 0xFFu},\r
- {0x19u, 0x03u},\r
- {0x1Au, 0x08u},\r
- {0x1Bu, 0x0Cu},\r
- {0x1Du, 0x0Fu},\r
- {0x1Eu, 0x10u},\r
- {0x1Fu, 0xF0u},\r
- {0x20u, 0x01u},\r
- {0x21u, 0x05u},\r
- {0x22u, 0x02u},\r
- {0x23u, 0x0Au},\r
- {0x2Du, 0xFFu},\r
- {0x2Eu, 0x02u},\r
- {0x30u, 0x10u},\r
- {0x32u, 0x08u},\r
- {0x34u, 0x04u},\r
- {0x35u, 0xFFu},\r
- {0x36u, 0x03u},\r
- {0x3Eu, 0x40u},\r
+ {0x0Fu, 0x0Cu},\r
+ {0x11u, 0x02u},\r
+ {0x12u, 0x20u},\r
+ {0x13u, 0x01u},\r
+ {0x14u, 0x02u},\r
+ {0x16u, 0x01u},\r
+ {0x1Au, 0x10u},\r
+ {0x1Du, 0x08u},\r
+ {0x1Fu, 0x04u},\r
+ {0x21u, 0x01u},\r
+ {0x22u, 0x08u},\r
+ {0x23u, 0x02u},\r
+ {0x24u, 0x02u},\r
+ {0x26u, 0x01u},\r
+ {0x27u, 0x10u},\r
+ {0x2Au, 0x04u},\r
+ {0x2Cu, 0x10u},\r
+ {0x2Eu, 0x20u},\r
+ {0x30u, 0x30u},\r
+ {0x31u, 0x20u},\r
+ {0x32u, 0x03u},\r
+ {0x33u, 0x10u},\r
+ {0x34u, 0x0Cu},\r
+ {0x35u, 0x0Fu},\r
+ {0x3Au, 0x08u},\r
+ {0x3Eu, 0x11u},\r
{0x3Fu, 0x10u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x09u},\r
+ {0x5Cu, 0x99u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x50u},\r
- {0x85u, 0xFFu},\r
- {0x86u, 0xA0u},\r
- {0x88u, 0x30u},\r
- {0x89u, 0x33u},\r
- {0x8Au, 0xC0u},\r
- {0x8Bu, 0xCCu},\r
- {0x8Cu, 0xFFu},\r
- {0x8Fu, 0xFFu},\r
- {0x90u, 0x90u},\r
- {0x91u, 0x0Fu},\r
- {0x92u, 0x60u},\r
- {0x93u, 0xF0u},\r
- {0x94u, 0x05u},\r
- {0x96u, 0x0Au},\r
- {0x97u, 0xFFu},\r
- {0x99u, 0x55u},\r
- {0x9Bu, 0xAAu},\r
- {0x9Cu, 0x0Fu},\r
- {0x9Du, 0xFFu},\r
- {0x9Eu, 0xF0u},\r
- {0xA0u, 0x09u},\r
- {0xA1u, 0x69u},\r
- {0xA2u, 0x06u},\r
- {0xA3u, 0x96u},\r
- {0xA4u, 0x03u},\r
- {0xA6u, 0x0Cu},\r
- {0xA7u, 0xFFu},\r
- {0xA8u, 0xFFu},\r
- {0xAEu, 0xFFu},\r
- {0xB1u, 0xFFu},\r
- {0xB6u, 0xFFu},\r
- {0xB8u, 0x02u},\r
- {0xBBu, 0x02u},\r
- {0xBEu, 0x41u},\r
+ {0x81u, 0x60u},\r
+ {0x83u, 0x90u},\r
+ {0x84u, 0x03u},\r
+ {0x85u, 0x03u},\r
+ {0x86u, 0x0Cu},\r
+ {0x87u, 0x0Cu},\r
+ {0x88u, 0x06u},\r
+ {0x89u, 0x06u},\r
+ {0x8Au, 0x09u},\r
+ {0x8Bu, 0x09u},\r
+ {0x8Cu, 0x0Fu},\r
+ {0x92u, 0x70u},\r
+ {0x95u, 0x05u},\r
+ {0x97u, 0x0Au},\r
+ {0x98u, 0x20u},\r
+ {0x99u, 0x50u},\r
+ {0x9Au, 0x4Fu},\r
+ {0x9Bu, 0xA0u},\r
+ {0x9Cu, 0x05u},\r
+ {0x9Du, 0x0Fu},\r
+ {0x9Eu, 0x0Au},\r
+ {0x9Fu, 0xF0u},\r
+ {0xA1u, 0x30u},\r
+ {0xA3u, 0xC0u},\r
+ {0xA8u, 0x40u},\r
+ {0xAAu, 0x1Fu},\r
+ {0xACu, 0x10u},\r
+ {0xAEu, 0x2Fu},\r
+ {0xB0u, 0x7Fu},\r
+ {0xB3u, 0xFFu},\r
+ {0xBFu, 0x04u},\r
+ {0xD4u, 0x01u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDCu, 0x10u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x01u},\r
+ {0xDDu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x80u},\r
- {0x04u, 0x28u},\r
- {0x05u, 0x41u},\r
- {0x07u, 0x40u},\r
- {0x09u, 0x80u},\r
- {0x0Au, 0x44u},\r
- {0x0Cu, 0x82u},\r
- {0x0Eu, 0x20u},\r
- {0x10u, 0x80u},\r
- {0x11u, 0x40u},\r
- {0x14u, 0x14u},\r
- {0x16u, 0x81u},\r
- {0x18u, 0x92u},\r
- {0x19u, 0x10u},\r
- {0x1Au, 0x44u},\r
- {0x1Fu, 0x41u},\r
- {0x22u, 0x20u},\r
- {0x26u, 0x02u},\r
- {0x29u, 0x40u},\r
- {0x2Au, 0x02u},\r
- {0x2Fu, 0xA0u},\r
- {0x30u, 0x9Eu},\r
- {0x31u, 0x20u},\r
- {0x34u, 0x08u},\r
- {0x35u, 0xA0u},\r
- {0x36u, 0x02u},\r
- {0x38u, 0x28u},\r
- {0x3Au, 0x81u},\r
- {0x3Du, 0x20u},\r
- {0x3Fu, 0x84u},\r
+ {0x00u, 0x10u},\r
+ {0x01u, 0x08u},\r
+ {0x02u, 0x42u},\r
+ {0x03u, 0x80u},\r
+ {0x04u, 0x08u},\r
+ {0x06u, 0x02u},\r
+ {0x07u, 0x08u},\r
+ {0x08u, 0x22u},\r
+ {0x09u, 0x28u},\r
+ {0x0Cu, 0x20u},\r
+ {0x0Eu, 0x42u},\r
+ {0x10u, 0x08u},\r
+ {0x11u, 0x41u},\r
+ {0x13u, 0x04u},\r
+ {0x14u, 0x05u},\r
+ {0x18u, 0x90u},\r
+ {0x1Au, 0x08u},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Eu, 0x40u},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0x22u},\r
+ {0x27u, 0x10u},\r
+ {0x29u, 0x18u},\r
+ {0x2Au, 0x11u},\r
+ {0x2Cu, 0x08u},\r
+ {0x2Du, 0x02u},\r
+ {0x2Eu, 0x20u},\r
+ {0x30u, 0x80u},\r
+ {0x32u, 0x01u},\r
+ {0x35u, 0x10u},\r
+ {0x36u, 0x40u},\r
+ {0x37u, 0x04u},\r
+ {0x39u, 0x20u},\r
+ {0x3Au, 0x40u},\r
+ {0x3Bu, 0x04u},\r
+ {0x3Eu, 0x08u},\r
+ {0x3Fu, 0x21u},\r
{0x58u, 0x80u},\r
+ {0x5Bu, 0x20u},\r
+ {0x5Eu, 0x40u},\r
{0x60u, 0x02u},\r
- {0x61u, 0x80u},\r
- {0x81u, 0x10u},\r
- {0x82u, 0x01u},\r
- {0x84u, 0x80u},\r
- {0x86u, 0x12u},\r
- {0x8Bu, 0x04u},\r
- {0x8Cu, 0x40u},\r
- {0x8Eu, 0x02u},\r
- {0x8Fu, 0x60u},\r
- {0x90u, 0x40u},\r
- {0x94u, 0x2Au},\r
- {0x95u, 0xE0u},\r
- {0x97u, 0x80u},\r
- {0x98u, 0x08u},\r
- {0x99u, 0xA0u},\r
- {0x9Bu, 0x40u},\r
- {0x9Du, 0x40u},\r
+ {0x62u, 0x80u},\r
+ {0x63u, 0x04u},\r
+ {0x69u, 0x40u},\r
+ {0x7Au, 0x40u},\r
+ {0x7Bu, 0x80u},\r
+ {0x85u, 0x10u},\r
+ {0x88u, 0x05u},\r
+ {0x8Bu, 0x40u},\r
+ {0x91u, 0x02u},\r
+ {0x92u, 0x02u},\r
+ {0x94u, 0x80u},\r
+ {0x96u, 0x0Cu},\r
+ {0x97u, 0x40u},\r
+ {0x98u, 0x88u},\r
+ {0x9Au, 0x22u},\r
+ {0x9Bu, 0x2Cu},\r
+ {0x9Cu, 0x06u},\r
+ {0x9Du, 0x01u},\r
{0x9Eu, 0x10u},\r
- {0xA0u, 0x08u},\r
+ {0xA0u, 0x20u},\r
{0xA1u, 0x20u},\r
- {0xA3u, 0x40u},\r
+ {0xA2u, 0x41u},\r
{0xA4u, 0x80u},\r
- {0xA6u, 0x30u},\r
- {0xABu, 0x04u},\r
- {0xB2u, 0x10u},\r
- {0xB3u, 0x02u},\r
- {0xB4u, 0x40u},\r
- {0xB6u, 0x80u},\r
- {0xC0u, 0xE1u},\r
- {0xC2u, 0xBBu},\r
- {0xC4u, 0xF9u},\r
- {0xCAu, 0xC9u},\r
- {0xCCu, 0xFFu},\r
- {0xCEu, 0x7Fu},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0x08u},\r
- {0xE2u, 0x50u},\r
- {0xE4u, 0x20u},\r
- {0xE6u, 0x92u},\r
- {0xEAu, 0x49u},\r
- {0xECu, 0x80u},\r
- {0xEEu, 0x20u},\r
- {0x02u, 0x02u},\r
- {0x06u, 0x08u},\r
- {0x0Bu, 0x08u},\r
- {0x0Du, 0x04u},\r
- {0x0Fu, 0x08u},\r
- {0x15u, 0x09u},\r
- {0x17u, 0x02u},\r
- {0x1Au, 0x04u},\r
- {0x1Eu, 0x01u},\r
- {0x1Fu, 0x07u},\r
- {0x20u, 0x04u},\r
- {0x22u, 0x08u},\r
- {0x2Du, 0x0Au},\r
- {0x2Fu, 0x05u},\r
- {0x30u, 0x01u},\r
- {0x31u, 0x0Fu},\r
- {0x32u, 0x0Cu},\r
- {0x34u, 0x02u},\r
- {0x3Eu, 0x04u},\r
+ {0xA6u, 0x80u},\r
+ {0xA7u, 0x02u},\r
+ {0xAAu, 0x40u},\r
+ {0xACu, 0x80u},\r
+ {0xAEu, 0x20u},\r
+ {0xB6u, 0x40u},\r
+ {0xC0u, 0xEFu},\r
+ {0xC2u, 0xDEu},\r
+ {0xC4u, 0xCFu},\r
+ {0xCAu, 0x83u},\r
+ {0xCCu, 0x79u},\r
+ {0xCEu, 0xEEu},\r
+ {0xD6u, 0x1Cu},\r
+ {0xD8u, 0x0Cu},\r
+ {0xE0u, 0x20u},\r
+ {0xE2u, 0x01u},\r
+ {0xE4u, 0xE0u},\r
+ {0xEAu, 0x17u},\r
+ {0xEEu, 0x42u},\r
+ {0x00u, 0x08u},\r
+ {0x01u, 0x33u},\r
+ {0x02u, 0x16u},\r
+ {0x03u, 0xCCu},\r
+ {0x05u, 0xFFu},\r
+ {0x06u, 0x40u},\r
+ {0x09u, 0x0Fu},\r
+ {0x0Au, 0x04u},\r
+ {0x0Bu, 0xF0u},\r
+ {0x0Eu, 0x07u},\r
+ {0x0Fu, 0xFFu},\r
+ {0x10u, 0x07u},\r
+ {0x12u, 0x18u},\r
+ {0x15u, 0x96u},\r
+ {0x16u, 0x07u},\r
+ {0x17u, 0x69u},\r
+ {0x18u, 0x0Cu},\r
+ {0x1Au, 0x13u},\r
+ {0x1Bu, 0xFFu},\r
+ {0x1Cu, 0x20u},\r
+ {0x1Eu, 0x40u},\r
+ {0x20u, 0x01u},\r
+ {0x25u, 0x55u},\r
+ {0x26u, 0x20u},\r
+ {0x27u, 0xAAu},\r
+ {0x28u, 0x0Fu},\r
+ {0x2Au, 0x10u},\r
+ {0x2Bu, 0xFFu},\r
+ {0x2Cu, 0x01u},\r
+ {0x2Du, 0xFFu},\r
+ {0x2Eu, 0x02u},\r
+ {0x30u, 0x1Fu},\r
+ {0x34u, 0x60u},\r
+ {0x35u, 0xFFu},\r
+ {0x3Au, 0x02u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Eu, 0x10u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x19u},\r
+ {0x5Cu, 0x11u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x01u},\r
- {0x82u, 0x02u},\r
- {0x84u, 0x08u},\r
- {0x86u, 0x04u},\r
- {0x8Bu, 0x02u},\r
- {0x8Cu, 0x08u},\r
- {0x8Eu, 0x04u},\r
- {0x90u, 0x02u},\r
- {0x92u, 0x01u},\r
- {0x94u, 0x02u},\r
- {0x96u, 0x01u},\r
- {0x97u, 0x08u},\r
- {0x9Bu, 0x01u},\r
- {0x9Cu, 0x04u},\r
- {0x9Du, 0x01u},\r
- {0x9Eu, 0x08u},\r
- {0x9Fu, 0x02u},\r
- {0xA0u, 0x08u},\r
- {0xA2u, 0x04u},\r
- {0xA4u, 0x02u},\r
- {0xA6u, 0x01u},\r
- {0xA7u, 0x10u},\r
- {0xA8u, 0x02u},\r
- {0xAAu, 0x01u},\r
- {0xABu, 0x04u},\r
- {0xACu, 0x08u},\r
- {0xAEu, 0x04u},\r
- {0xB0u, 0x03u},\r
- {0xB1u, 0x04u},\r
- {0xB3u, 0x10u},\r
- {0xB5u, 0x08u},\r
- {0xB6u, 0x0Cu},\r
- {0xB7u, 0x03u},\r
- {0xBAu, 0x82u},\r
- {0xBFu, 0x40u},\r
+ {0x82u, 0x10u},\r
+ {0x85u, 0x02u},\r
+ {0x87u, 0x01u},\r
+ {0x8Cu, 0x10u},\r
+ {0x90u, 0x10u},\r
+ {0x92u, 0x60u},\r
+ {0x93u, 0x04u},\r
+ {0x98u, 0x3Au},\r
+ {0x99u, 0x01u},\r
+ {0x9Au, 0x45u},\r
+ {0x9Bu, 0x02u},\r
+ {0x9Du, 0x02u},\r
+ {0x9Eu, 0x07u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA1u, 0x02u},\r
+ {0xA3u, 0x01u},\r
+ {0xA6u, 0x08u},\r
+ {0xA8u, 0x24u},\r
+ {0xAAu, 0x58u},\r
+ {0xACu, 0x29u},\r
+ {0xADu, 0x02u},\r
+ {0xAEu, 0x52u},\r
+ {0xAFu, 0x01u},\r
+ {0xB0u, 0x70u},\r
+ {0xB3u, 0x04u},\r
+ {0xB5u, 0x03u},\r
+ {0xB6u, 0x0Fu},\r
+ {0xBAu, 0x02u},\r
+ {0xBBu, 0x20u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x99u},\r
+ {0xDCu, 0x91u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x88u},\r
- {0x02u, 0x80u},\r
- {0x05u, 0x01u},\r
- {0x06u, 0x10u},\r
- {0x08u, 0x02u},\r
- {0x0Au, 0x22u},\r
- {0x0Fu, 0x0Au},\r
- {0x12u, 0x4Au},\r
- {0x13u, 0x04u},\r
- {0x14u, 0x40u},\r
- {0x18u, 0x40u},\r
- {0x19u, 0x80u},\r
- {0x1Au, 0x03u},\r
- {0x1Cu, 0x88u},\r
- {0x1Du, 0x15u},\r
- {0x22u, 0x0Au},\r
- {0x23u, 0x06u},\r
- {0x27u, 0x40u},\r
- {0x28u, 0x10u},\r
- {0x29u, 0x10u},\r
+ {0x00u, 0x02u},\r
+ {0x03u, 0x02u},\r
+ {0x04u, 0x80u},\r
+ {0x05u, 0x10u},\r
+ {0x06u, 0x90u},\r
+ {0x0Au, 0x82u},\r
+ {0x0Bu, 0x06u},\r
+ {0x0Eu, 0x61u},\r
+ {0x0Fu, 0x04u},\r
+ {0x10u, 0x04u},\r
+ {0x11u, 0x04u},\r
+ {0x13u, 0x40u},\r
+ {0x14u, 0x14u},\r
+ {0x15u, 0x01u},\r
+ {0x16u, 0x02u},\r
+ {0x17u, 0x04u},\r
+ {0x1Au, 0x82u},\r
+ {0x1Eu, 0x40u},\r
+ {0x1Fu, 0x10u},\r
+ {0x21u, 0x28u},\r
+ {0x25u, 0x10u},\r
+ {0x27u, 0x08u},\r
+ {0x29u, 0x82u},\r
+ {0x2Cu, 0x04u},\r
+ {0x2Eu, 0x04u},\r
{0x2Fu, 0x02u},\r
- {0x30u, 0xC0u},\r
- {0x31u, 0x20u},\r
- {0x32u, 0x08u},\r
- {0x34u, 0x08u},\r
- {0x37u, 0x40u},\r
- {0x38u, 0x20u},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x80u},\r
- {0x58u, 0x10u},\r
- {0x5Au, 0x60u},\r
- {0x5Cu, 0x24u},\r
- {0x5Du, 0x02u},\r
- {0x5Fu, 0x80u},\r
- {0x62u, 0x40u},\r
- {0x63u, 0x02u},\r
- {0x64u, 0x01u},\r
- {0x80u, 0x04u},\r
- {0x81u, 0x40u},\r
- {0x85u, 0x02u},\r
+ {0x31u, 0x21u},\r
+ {0x32u, 0x80u},\r
+ {0x35u, 0x04u},\r
+ {0x36u, 0x10u},\r
+ {0x38u, 0x08u},\r
+ {0x3Du, 0x20u},\r
+ {0x3Eu, 0x80u},\r
+ {0x3Fu, 0x45u},\r
+ {0x59u, 0x40u},\r
+ {0x63u, 0x01u},\r
+ {0x6Cu, 0x02u},\r
+ {0x6Eu, 0x80u},\r
+ {0x81u, 0x04u},\r
+ {0x84u, 0x20u},\r
+ {0x86u, 0x04u},\r
+ {0x87u, 0x04u},\r
+ {0x88u, 0x0Au},\r
+ {0x89u, 0x41u},\r
{0x8Au, 0x01u},\r
- {0x8Cu, 0x01u},\r
- {0x8Du, 0x20u},\r
- {0x92u, 0x70u},\r
- {0x94u, 0x2Cu},\r
- {0x95u, 0x60u},\r
- {0x97u, 0x80u},\r
- {0x98u, 0x2Bu},\r
- {0x9Bu, 0x80u},\r
- {0x9Du, 0xC4u},\r
- {0x9Fu, 0x02u},\r
- {0xA0u, 0x08u},\r
- {0xA1u, 0x20u},\r
- {0xA3u, 0x40u},\r
- {0xA4u, 0x80u},\r
- {0xA6u, 0x30u},\r
- {0xA8u, 0x10u},\r
- {0xAAu, 0x40u},\r
- {0xABu, 0x80u},\r
- {0xACu, 0x20u},\r
- {0xADu, 0x01u},\r
- {0xB6u, 0x60u},\r
- {0xB7u, 0x40u},\r
- {0xC0u, 0x3Du},\r
- {0xC2u, 0xCDu},\r
- {0xC4u, 0x1Fu},\r
- {0xCAu, 0x16u},\r
- {0xCCu, 0x5Eu},\r
- {0xCEu, 0x34u},\r
- {0xD6u, 0xF8u},\r
- {0xD8u, 0x18u},\r
- {0xE0u, 0x11u},\r
- {0xE2u, 0xAAu},\r
- {0xE6u, 0x84u},\r
- {0xEAu, 0x04u},\r
- {0xECu, 0x40u},\r
- {0x07u, 0x02u},\r
- {0x08u, 0x30u},\r
- {0x0Au, 0xC0u},\r
- {0x0Cu, 0x60u},\r
- {0x0Eu, 0x90u},\r
- {0x10u, 0xFFu},\r
- {0x14u, 0x05u},\r
- {0x16u, 0x0Au},\r
+ {0x8Fu, 0x20u},\r
+ {0x90u, 0x08u},\r
+ {0x91u, 0x05u},\r
+ {0x94u, 0x80u},\r
+ {0x97u, 0x62u},\r
+ {0x98u, 0x18u},\r
+ {0x99u, 0x92u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Cu, 0x06u},\r
+ {0x9Du, 0x01u},\r
+ {0xA0u, 0x01u},\r
+ {0xA2u, 0x11u},\r
+ {0xA4u, 0xAAu},\r
+ {0xA5u, 0x08u},\r
+ {0xA9u, 0x10u},\r
+ {0xABu, 0x50u},\r
+ {0xADu, 0x11u},\r
+ {0xAEu, 0x01u},\r
+ {0xB2u, 0x08u},\r
+ {0xB3u, 0x08u},\r
+ {0xB5u, 0x40u},\r
+ {0xB6u, 0x40u},\r
+ {0xC0u, 0xF9u},\r
+ {0xC2u, 0xFBu},\r
+ {0xC4u, 0xF7u},\r
+ {0xCAu, 0x79u},\r
+ {0xCCu, 0x6Du},\r
+ {0xCEu, 0xF2u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x08u},\r
+ {0xE0u, 0x20u},\r
+ {0xE2u, 0x01u},\r
+ {0xE4u, 0x28u},\r
+ {0xE6u, 0x82u},\r
+ {0xE8u, 0x60u},\r
+ {0xECu, 0x80u},\r
+ {0xEEu, 0x01u},\r
+ {0x02u, 0x02u},\r
+ {0x03u, 0x04u},\r
+ {0x09u, 0x02u},\r
+ {0x0Bu, 0x01u},\r
+ {0x0Du, 0x01u},\r
+ {0x0Fu, 0x02u},\r
+ {0x11u, 0x04u},\r
+ {0x12u, 0x01u},\r
+ {0x13u, 0x08u},\r
+ {0x15u, 0x02u},\r
+ {0x16u, 0x04u},\r
{0x17u, 0x01u},\r
- {0x18u, 0x03u},\r
- {0x1Au, 0x0Cu},\r
- {0x1Du, 0x01u},\r
- {0x1Eu, 0xFFu},\r
- {0x1Fu, 0x02u},\r
- {0x20u, 0x0Fu},\r
- {0x22u, 0xF0u},\r
- {0x24u, 0x50u},\r
- {0x26u, 0xA0u},\r
- {0x28u, 0x06u},\r
- {0x2Au, 0x09u},\r
- {0x2Eu, 0xFFu},\r
- {0x2Fu, 0x04u},\r
- {0x30u, 0xFFu},\r
- {0x33u, 0x03u},\r
- {0x35u, 0x04u},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x04u},\r
+ {0x1Au, 0x08u},\r
+ {0x1Fu, 0x08u},\r
+ {0x21u, 0x02u},\r
+ {0x23u, 0x01u},\r
+ {0x29u, 0x02u},\r
+ {0x2Bu, 0x01u},\r
+ {0x30u, 0x08u},\r
+ {0x31u, 0x03u},\r
+ {0x32u, 0x04u},\r
+ {0x34u, 0x01u},\r
+ {0x36u, 0x02u},\r
+ {0x37u, 0x0Cu},\r
+ {0x3Bu, 0x02u},\r
+ {0x3Fu, 0x40u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x90u},\r
+ {0x5Cu, 0x99u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x83u, 0x10u},\r
- {0x84u, 0x50u},\r
- {0x86u, 0xA0u},\r
- {0x87u, 0x20u},\r
- {0x88u, 0x30u},\r
- {0x8Au, 0xC0u},\r
- {0x8Bu, 0x0Eu},\r
- {0x8Du, 0x01u},\r
- {0x8Eu, 0xFFu},\r
- {0x94u, 0x05u},\r
- {0x95u, 0x32u},\r
- {0x96u, 0x0Au},\r
- {0x97u, 0x04u},\r
- {0x98u, 0x03u},\r
- {0x99u, 0x01u},\r
- {0x9Au, 0x0Cu},\r
+ {0x84u, 0x55u},\r
+ {0x86u, 0xAAu},\r
+ {0x88u, 0x33u},\r
+ {0x8Au, 0xCCu},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Cu, 0xFFu},\r
+ {0x8Du, 0x19u},\r
+ {0x8Fu, 0x02u},\r
+ {0x92u, 0xFFu},\r
+ {0x93u, 0x10u},\r
+ {0x94u, 0x69u},\r
+ {0x96u, 0x96u},\r
+ {0x97u, 0x10u},\r
+ {0x98u, 0xFFu},\r
+ {0x9Bu, 0x07u},\r
{0x9Cu, 0x0Fu},\r
- {0x9Du, 0x01u},\r
{0x9Eu, 0xF0u},\r
- {0xA1u, 0x01u},\r
- {0xA2u, 0xFFu},\r
- {0xA5u, 0x34u},\r
+ {0xA5u, 0x1Au},\r
{0xA6u, 0xFFu},\r
- {0xA7u, 0x0Au},\r
- {0xA8u, 0x09u},\r
- {0xA9u, 0x28u},\r
- {0xAAu, 0x06u},\r
- {0xABu, 0x10u},\r
- {0xACu, 0x90u},\r
- {0xAEu, 0x60u},\r
- {0xAFu, 0x20u},\r
- {0xB0u, 0xFFu},\r
- {0xB3u, 0x01u},\r
- {0xB5u, 0x1Eu},\r
- {0xB7u, 0x20u},\r
- {0xB9u, 0x08u},\r
- {0xBEu, 0x01u},\r
- {0xBFu, 0x44u},\r
+ {0xA7u, 0x05u},\r
+ {0xA9u, 0x14u},\r
+ {0xAAu, 0xFFu},\r
+ {0xABu, 0x08u},\r
+ {0xB1u, 0x10u},\r
+ {0xB3u, 0x0Fu},\r
+ {0xB6u, 0xFFu},\r
+ {0xBAu, 0x80u},\r
+ {0xBFu, 0x01u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDCu, 0x10u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x11u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x40u},\r
- {0x02u, 0x04u},\r
- {0x04u, 0x28u},\r
- {0x05u, 0x40u},\r
- {0x06u, 0x14u},\r
- {0x09u, 0x1Au},\r
- {0x0Bu, 0x02u},\r
- {0x0Cu, 0x80u},\r
- {0x0Du, 0x28u},\r
- {0x0Eu, 0x20u},\r
- {0x10u, 0x86u},\r
- {0x12u, 0x10u},\r
- {0x14u, 0x04u},\r
- {0x15u, 0x60u},\r
- {0x17u, 0x09u},\r
- {0x18u, 0x40u},\r
- {0x1Eu, 0x80u},\r
- {0x22u, 0x10u},\r
- {0x23u, 0x20u},\r
- {0x24u, 0x10u},\r
- {0x25u, 0x30u},\r
- {0x26u, 0x80u},\r
- {0x28u, 0x02u},\r
- {0x2Cu, 0x20u},\r
- {0x2Du, 0x80u},\r
- {0x2Eu, 0x20u},\r
- {0x2Fu, 0x40u},\r
- {0x30u, 0x80u},\r
+ {0x01u, 0x02u},\r
+ {0x04u, 0x80u},\r
+ {0x06u, 0x08u},\r
+ {0x07u, 0x11u},\r
+ {0x08u, 0x02u},\r
+ {0x09u, 0x08u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Cu, 0x28u},\r
+ {0x0Eu, 0x02u},\r
+ {0x0Fu, 0x40u},\r
+ {0x14u, 0x24u},\r
+ {0x18u, 0x08u},\r
+ {0x19u, 0x82u},\r
+ {0x1Au, 0x04u},\r
+ {0x1Bu, 0x04u},\r
+ {0x1Eu, 0x02u},\r
+ {0x20u, 0x40u},\r
+ {0x22u, 0x41u},\r
+ {0x25u, 0x01u},\r
+ {0x27u, 0x20u},\r
+ {0x29u, 0x01u},\r
+ {0x2Bu, 0x04u},\r
+ {0x2Cu, 0x24u},\r
+ {0x30u, 0x82u},\r
{0x31u, 0x08u},\r
- {0x34u, 0x08u},\r
- {0x36u, 0x60u},\r
- {0x38u, 0x08u},\r
- {0x3Cu, 0x44u},\r
- {0x3Du, 0x21u},\r
- {0x5Au, 0x80u},\r
- {0x60u, 0x02u},\r
- {0x65u, 0x40u},\r
- {0x67u, 0x02u},\r
- {0x78u, 0x01u},\r
- {0x7Au, 0x80u},\r
- {0x80u, 0x22u},\r
- {0x83u, 0x2Au},\r
- {0x84u, 0x08u},\r
- {0x85u, 0x02u},\r
- {0x87u, 0x01u},\r
- {0x88u, 0x08u},\r
- {0x8Du, 0x04u},\r
- {0x8Eu, 0x10u},\r
- {0xC0u, 0xE3u},\r
- {0xC2u, 0xEFu},\r
- {0xC4u, 0xFFu},\r
- {0xCAu, 0xF8u},\r
- {0xCCu, 0x7Au},\r
- {0xCEu, 0xF2u},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0x08u},\r
- {0xE0u, 0x81u},\r
- {0xE2u, 0x50u},\r
- {0xE4u, 0x11u},\r
- {0x81u, 0x5Cu},\r
- {0x84u, 0x14u},\r
- {0x85u, 0x24u},\r
+ {0x34u, 0x10u},\r
+ {0x37u, 0x29u},\r
+ {0x38u, 0x40u},\r
+ {0x3Au, 0x10u},\r
+ {0x3Bu, 0x02u},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x40u},\r
+ {0x45u, 0x01u},\r
+ {0x46u, 0x40u},\r
+ {0x59u, 0x20u},\r
+ {0x5Bu, 0x40u},\r
+ {0x5Du, 0x51u},\r
+ {0x5Fu, 0x08u},\r
+ {0x60u, 0x08u},\r
+ {0x62u, 0x90u},\r
+ {0x66u, 0x40u},\r
+ {0x81u, 0x20u},\r
+ {0x82u, 0x02u},\r
+ {0x84u, 0x21u},\r
+ {0x86u, 0x10u},\r
{0x87u, 0x10u},\r
- {0x88u, 0x3Fu},\r
- {0x89u, 0x50u},\r
- {0x8Au, 0x40u},\r
- {0x8Bu, 0x0Cu},\r
- {0x8Cu, 0x34u},\r
- {0x90u, 0x34u},\r
- {0x91u, 0x21u},\r
- {0x93u, 0x1Eu},\r
- {0x94u, 0x20u},\r
- {0x95u, 0x11u},\r
- {0x96u, 0x02u},\r
- {0x97u, 0x22u},\r
- {0x98u, 0x08u},\r
- {0x99u, 0x30u},\r
- {0x9Au, 0x75u},\r
- {0x9Bu, 0x0Fu},\r
- {0x9Cu, 0x4Bu},\r
- {0x9Eu, 0x30u},\r
- {0xA0u, 0x34u},\r
- {0xA1u, 0x5Cu},\r
- {0xA5u, 0x54u},\r
- {0xA6u, 0x34u},\r
- {0xA7u, 0x08u},\r
- {0xA8u, 0x14u},\r
- {0xA9u, 0x08u},\r
- {0xAAu, 0x20u},\r
- {0xADu, 0x0Cu},\r
- {0xAFu, 0x50u},\r
- {0xB3u, 0x30u},\r
- {0xB4u, 0x07u},\r
- {0xB5u, 0x0Fu},\r
- {0xB6u, 0x78u},\r
- {0xB7u, 0x40u},\r
+ {0x89u, 0x04u},\r
+ {0x8Eu, 0x90u},\r
+ {0xC0u, 0xE8u},\r
+ {0xC2u, 0xFEu},\r
+ {0xC4u, 0x60u},\r
+ {0xCAu, 0x65u},\r
+ {0xCCu, 0xEBu},\r
+ {0xCEu, 0x3Du},\r
+ {0xD6u, 0xFCu},\r
+ {0xD8u, 0x1Cu},\r
+ {0xE0u, 0x20u},\r
+ {0xE2u, 0x40u},\r
+ {0xE4u, 0x10u},\r
+ {0xE6u, 0x01u},\r
+ {0x02u, 0x02u},\r
+ {0x08u, 0x01u},\r
+ {0x09u, 0x01u},\r
+ {0x0Au, 0x02u},\r
+ {0x1Eu, 0x01u},\r
+ {0x32u, 0x03u},\r
+ {0x35u, 0x01u},\r
+ {0x3Eu, 0x04u},\r
+ {0x40u, 0x36u},\r
+ {0x41u, 0x02u},\r
+ {0x42u, 0x10u},\r
+ {0x44u, 0x05u},\r
+ {0x45u, 0xDEu},\r
+ {0x46u, 0xF0u},\r
+ {0x47u, 0xCBu},\r
+ {0x48u, 0x3Bu},\r
+ {0x49u, 0xFFu},\r
+ {0x4Au, 0xFFu},\r
+ {0x4Bu, 0xFFu},\r
+ {0x4Cu, 0x22u},\r
+ {0x4Eu, 0xF0u},\r
+ {0x4Fu, 0x08u},\r
+ {0x50u, 0x04u},\r
+ {0x54u, 0x40u},\r
+ {0x56u, 0x04u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Au, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x90u},\r
+ {0x5Fu, 0x01u},\r
+ {0x62u, 0xC0u},\r
+ {0x64u, 0x40u},\r
+ {0x65u, 0x01u},\r
+ {0x66u, 0x10u},\r
+ {0x67u, 0x11u},\r
+ {0x68u, 0xC0u},\r
+ {0x69u, 0x01u},\r
+ {0x6Bu, 0x11u},\r
+ {0x6Cu, 0x40u},\r
+ {0x6Du, 0x01u},\r
+ {0x6Eu, 0x40u},\r
+ {0x6Fu, 0x01u},\r
+ {0x80u, 0x31u},\r
+ {0x81u, 0xC1u},\r
+ {0x84u, 0x01u},\r
+ {0x85u, 0x07u},\r
+ {0x86u, 0x30u},\r
+ {0x87u, 0x18u},\r
+ {0x88u, 0x43u},\r
+ {0x89u, 0xC0u},\r
+ {0x8Au, 0x3Cu},\r
+ {0x8Cu, 0x31u},\r
+ {0x8Du, 0x01u},\r
+ {0x8Fu, 0xC0u},\r
+ {0x90u, 0x30u},\r
+ {0x92u, 0x01u},\r
+ {0x93u, 0x40u},\r
+ {0x94u, 0x06u},\r
+ {0x95u, 0x22u},\r
+ {0x96u, 0xB9u},\r
+ {0x97u, 0x08u},\r
+ {0x98u, 0x05u},\r
+ {0x99u, 0x08u},\r
+ {0x9Au, 0x4Au},\r
+ {0x9Bu, 0x21u},\r
+ {0x9Cu, 0xC0u},\r
+ {0x9Du, 0xC1u},\r
+ {0xA0u, 0x20u},\r
+ {0xA1u, 0x04u},\r
+ {0xA4u, 0x11u},\r
+ {0xA5u, 0xC1u},\r
+ {0xA6u, 0x20u},\r
+ {0xA9u, 0x10u},\r
+ {0xACu, 0x12u},\r
+ {0xADu, 0x01u},\r
+ {0xAEu, 0x01u},\r
+ {0xB0u, 0x03u},\r
+ {0xB1u, 0x3Fu},\r
+ {0xB3u, 0x40u},\r
+ {0xB4u, 0x3Cu},\r
+ {0xB6u, 0xC4u},\r
+ {0xB7u, 0x80u},\r
{0xB8u, 0x80u},\r
- {0xBAu, 0x30u},\r
- {0xBBu, 0x08u},\r
- {0xBFu, 0x40u},\r
+ {0xB9u, 0x02u},\r
+ {0xBAu, 0x02u},\r
+ {0xBFu, 0x45u},\r
+ {0xD6u, 0x02u},\r
+ {0xD7u, 0x24u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x04u},\r
- {0x01u, 0x01u},\r
- {0x03u, 0x06u},\r
+ {0x00u, 0x02u},\r
+ {0x03u, 0x08u},\r
+ {0x04u, 0x08u},\r
+ {0x05u, 0x10u},\r
{0x06u, 0x02u},\r
- {0x07u, 0x14u},\r
- {0x09u, 0x20u},\r
- {0x0Bu, 0xA2u},\r
+ {0x07u, 0x40u},\r
+ {0x0Au, 0x02u},\r
{0x0Cu, 0x02u},\r
- {0x0Du, 0x08u},\r
- {0x0Eu, 0x06u},\r
- {0x10u, 0x82u},\r
- {0x11u, 0x04u},\r
- {0x12u, 0x08u},\r
- {0x15u, 0x01u},\r
- {0x17u, 0x28u},\r
- {0x18u, 0x04u},\r
- {0x19u, 0x80u},\r
- {0x1Bu, 0x03u},\r
- {0x1Du, 0x10u},\r
+ {0x0Du, 0x40u},\r
+ {0x0Eu, 0x26u},\r
+ {0x14u, 0x01u},\r
+ {0x15u, 0x06u},\r
+ {0x19u, 0x08u},\r
{0x1Eu, 0x06u},\r
- {0x1Fu, 0x70u},\r
- {0x21u, 0x20u},\r
- {0x24u, 0x29u},\r
- {0x25u, 0x04u},\r
- {0x26u, 0x08u},\r
- {0x27u, 0x15u},\r
- {0x29u, 0x01u},\r
- {0x2Bu, 0x21u},\r
- {0x2Cu, 0x02u},\r
- {0x2Du, 0x05u},\r
- {0x2Fu, 0x04u},\r
- {0x30u, 0x82u},\r
- {0x32u, 0x10u},\r
- {0x33u, 0x04u},\r
- {0x35u, 0x10u},\r
- {0x36u, 0x01u},\r
- {0x37u, 0x04u},\r
- {0x38u, 0x20u},\r
- {0x39u, 0x05u},\r
- {0x3Bu, 0x80u},\r
- {0x3Du, 0x08u},\r
- {0x3Eu, 0x12u},\r
- {0x40u, 0x01u},\r
- {0x43u, 0x24u},\r
- {0x49u, 0x05u},\r
- {0x4Au, 0x05u},\r
- {0x4Bu, 0x02u},\r
- {0x51u, 0x08u},\r
- {0x52u, 0x50u},\r
- {0x53u, 0x04u},\r
- {0x60u, 0x20u},\r
- {0x61u, 0x0Au},\r
- {0x68u, 0x0Au},\r
- {0x69u, 0x05u},\r
- {0x6Au, 0x30u},\r
- {0x6Bu, 0x68u},\r
- {0x70u, 0x80u},\r
- {0x72u, 0x02u},\r
- {0x8Eu, 0x04u},\r
- {0x94u, 0x08u},\r
- {0x95u, 0x04u},\r
- {0x96u, 0x10u},\r
- {0x97u, 0x82u},\r
- {0x9Cu, 0x20u},\r
- {0x9Du, 0x94u},\r
- {0x9Eu, 0x52u},\r
- {0x9Fu, 0x45u},\r
- {0xA1u, 0x02u},\r
- {0xA4u, 0x0Au},\r
- {0xA6u, 0x01u},\r
- {0xC0u, 0xEFu},\r
- {0xC2u, 0xFFu},\r
- {0xC4u, 0x7Fu},\r
- {0xCAu, 0xFBu},\r
- {0xCCu, 0xEFu},\r
- {0xCEu, 0xEFu},\r
+ {0x1Fu, 0x11u},\r
+ {0x21u, 0x10u},\r
+ {0x24u, 0x90u},\r
+ {0x25u, 0x80u},\r
+ {0x27u, 0x02u},\r
+ {0x2Cu, 0x09u},\r
+ {0x2Du, 0x04u},\r
+ {0x2Fu, 0x41u},\r
+ {0x35u, 0x02u},\r
+ {0x36u, 0x14u},\r
+ {0x37u, 0x40u},\r
+ {0x39u, 0x10u},\r
+ {0x3Du, 0xA0u},\r
+ {0x3Eu, 0x06u},\r
+ {0x41u, 0x88u},\r
+ {0x42u, 0x04u},\r
+ {0x49u, 0x86u},\r
+ {0x4Au, 0x84u},\r
+ {0x50u, 0x08u},\r
+ {0x51u, 0x01u},\r
+ {0x52u, 0x10u},\r
+ {0x60u, 0x10u},\r
+ {0x61u, 0x01u},\r
+ {0x62u, 0x90u},\r
+ {0x67u, 0x04u},\r
+ {0x6Cu, 0x16u},\r
+ {0x6Du, 0xE4u},\r
+ {0x6Fu, 0x40u},\r
+ {0x76u, 0x02u},\r
+ {0x84u, 0x01u},\r
+ {0x85u, 0x80u},\r
+ {0x89u, 0x10u},\r
+ {0x8Au, 0x06u},\r
+ {0x8Cu, 0x04u},\r
+ {0x92u, 0x02u},\r
+ {0x93u, 0x84u},\r
+ {0x94u, 0xACu},\r
+ {0x95u, 0xE6u},\r
+ {0x96u, 0x0Cu},\r
+ {0x97u, 0x22u},\r
+ {0x99u, 0x10u},\r
+ {0x9Du, 0x0Du},\r
+ {0x9Eu, 0x02u},\r
+ {0x9Fu, 0x42u},\r
+ {0xA1u, 0x08u},\r
+ {0xA2u, 0x14u},\r
+ {0xA3u, 0x08u},\r
+ {0xA4u, 0x08u},\r
+ {0xA5u, 0x50u},\r
+ {0xA6u, 0x02u},\r
+ {0xA8u, 0x02u},\r
+ {0xA9u, 0x82u},\r
+ {0xADu, 0x29u},\r
+ {0xB0u, 0x04u},\r
+ {0xB2u, 0x90u},\r
+ {0xB3u, 0x08u},\r
+ {0xB4u, 0x40u},\r
+ {0xC0u, 0xFAu},\r
+ {0xC2u, 0xF1u},\r
+ {0xC4u, 0xB0u},\r
+ {0xCAu, 0xF0u},\r
+ {0xCCu, 0xF0u},\r
+ {0xCEu, 0xF4u},\r
{0xD0u, 0x0Eu},\r
{0xD2u, 0x0Cu},\r
- {0xD8u, 0x01u},\r
- {0xE0u, 0x40u},\r
- {0x00u, 0x08u},\r
+ {0xD8u, 0x2Fu},\r
+ {0xE6u, 0x08u},\r
+ {0xEAu, 0x05u},\r
+ {0x00u, 0x34u},\r
+ {0x01u, 0xC0u},\r
{0x03u, 0x01u},\r
- {0x04u, 0x01u},\r
- {0x07u, 0x0Cu},\r
- {0x08u, 0x04u},\r
- {0x09u, 0x60u},\r
- {0x11u, 0x14u},\r
- {0x12u, 0x08u},\r
- {0x13u, 0x43u},\r
- {0x14u, 0x08u},\r
- {0x15u, 0x11u},\r
- {0x17u, 0x22u},\r
- {0x18u, 0x07u},\r
- {0x19u, 0x28u},\r
- {0x1Bu, 0x13u},\r
- {0x1Eu, 0x02u},\r
- {0x22u, 0x08u},\r
- {0x24u, 0x08u},\r
- {0x2Au, 0x07u},\r
- {0x2Cu, 0x08u},\r
- {0x2Fu, 0x82u},\r
- {0x30u, 0x07u},\r
- {0x33u, 0x0Fu},\r
- {0x34u, 0x08u},\r
- {0x35u, 0x70u},\r
- {0x37u, 0x80u},\r
- {0x39u, 0x20u},\r
- {0x3Eu, 0x11u},\r
- {0x54u, 0x40u},\r
- {0x56u, 0x04u},\r
+ {0x05u, 0x1Fu},\r
+ {0x06u, 0x34u},\r
+ {0x07u, 0x20u},\r
+ {0x08u, 0x14u},\r
+ {0x09u, 0xC0u},\r
+ {0x0Au, 0x20u},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Cu, 0x80u},\r
+ {0x0Du, 0x90u},\r
+ {0x0Fu, 0x40u},\r
+ {0x10u, 0x20u},\r
+ {0x12u, 0x02u},\r
+ {0x13u, 0x60u},\r
+ {0x14u, 0x4Bu},\r
+ {0x15u, 0x7Fu},\r
+ {0x16u, 0x30u},\r
+ {0x17u, 0x80u},\r
+ {0x18u, 0x3Fu},\r
+ {0x1Au, 0x40u},\r
+ {0x1Bu, 0xFFu},\r
+ {0x1Cu, 0x14u},\r
+ {0x1Du, 0xC0u},\r
+ {0x1Fu, 0x02u},\r
+ {0x20u, 0x34u},\r
+ {0x24u, 0x08u},\r
+ {0x25u, 0xC0u},\r
+ {0x26u, 0x75u},\r
+ {0x27u, 0x04u},\r
+ {0x28u, 0x80u},\r
+ {0x2Bu, 0x9Fu},\r
+ {0x2Cu, 0x34u},\r
+ {0x2Du, 0x80u},\r
+ {0x32u, 0x78u},\r
+ {0x33u, 0xFFu},\r
+ {0x34u, 0x07u},\r
+ {0x36u, 0x80u},\r
+ {0x38u, 0x88u},\r
+ {0x3Au, 0x30u},\r
+ {0x3Fu, 0x04u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
{0x5Fu, 0x01u},\r
- {0x82u, 0x07u},\r
- {0x84u, 0x09u},\r
- {0x85u, 0x09u},\r
- {0x86u, 0x02u},\r
- {0x87u, 0x06u},\r
- {0x8Cu, 0x04u},\r
- {0x8Du, 0x0Bu},\r
- {0x8Eu, 0x08u},\r
- {0x8Fu, 0x04u},\r
- {0x91u, 0x04u},\r
- {0x92u, 0x08u},\r
- {0x93u, 0x03u},\r
- {0xA4u, 0x0Au},\r
- {0xA6u, 0x05u},\r
- {0xA9u, 0x0Du},\r
- {0xABu, 0x02u},\r
- {0xB0u, 0x0Fu},\r
- {0xB1u, 0x07u},\r
- {0xB7u, 0x08u},\r
- {0xBBu, 0x02u},\r
- {0xBFu, 0x40u},\r
+ {0x82u, 0xFFu},\r
+ {0x84u, 0x30u},\r
+ {0x86u, 0xC0u},\r
+ {0x88u, 0x0Fu},\r
+ {0x89u, 0x11u},\r
+ {0x8Au, 0xF0u},\r
+ {0x8Bu, 0x0Eu},\r
+ {0x8Cu, 0x60u},\r
+ {0x8Eu, 0x90u},\r
+ {0x90u, 0x50u},\r
+ {0x92u, 0xA0u},\r
+ {0x94u, 0x06u},\r
+ {0x95u, 0x1Bu},\r
+ {0x96u, 0x09u},\r
+ {0x97u, 0x04u},\r
+ {0x98u, 0x05u},\r
+ {0x99u, 0x04u},\r
+ {0x9Au, 0x0Au},\r
+ {0x9Bu, 0x03u},\r
+ {0xA4u, 0x03u},\r
+ {0xA6u, 0x0Cu},\r
+ {0xA9u, 0x15u},\r
+ {0xAAu, 0xFFu},\r
+ {0xABu, 0x0Au},\r
+ {0xACu, 0xFFu},\r
+ {0xB1u, 0x08u},\r
+ {0xB5u, 0x07u},\r
+ {0xB6u, 0xFFu},\r
+ {0xB7u, 0x10u},\r
+ {0xBBu, 0x20u},\r
+ {0xBEu, 0x40u},\r
+ {0xBFu, 0x41u},\r
{0xD4u, 0x09u},\r
{0xD6u, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x01u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x0Bu},\r
- {0x03u, 0x02u},\r
- {0x04u, 0x08u},\r
- {0x05u, 0x10u},\r
+ {0x00u, 0x44u},\r
+ {0x02u, 0xC1u},\r
+ {0x03u, 0x08u},\r
+ {0x04u, 0xA8u},\r
{0x07u, 0x40u},\r
- {0x0Au, 0x40u},\r
- {0x0Cu, 0x02u},\r
- {0x0Du, 0x21u},\r
- {0x0Eu, 0x12u},\r
- {0x13u, 0x08u},\r
- {0x15u, 0x04u},\r
- {0x16u, 0x42u},\r
- {0x17u, 0x20u},\r
- {0x19u, 0x02u},\r
- {0x1Du, 0x01u},\r
- {0x1Fu, 0x10u},\r
- {0x21u, 0x02u},\r
- {0x23u, 0x01u},\r
- {0x24u, 0x01u},\r
- {0x25u, 0x34u},\r
+ {0x08u, 0x54u},\r
+ {0x09u, 0x02u},\r
+ {0x0Bu, 0x02u},\r
+ {0x0Cu, 0x40u},\r
+ {0x0Du, 0x01u},\r
+ {0x0Eu, 0x24u},\r
+ {0x10u, 0x22u},\r
+ {0x11u, 0x10u},\r
+ {0x15u, 0x41u},\r
+ {0x17u, 0x28u},\r
+ {0x1Au, 0x01u},\r
+ {0x1Cu, 0x20u},\r
+ {0x1Du, 0x18u},\r
+ {0x1Eu, 0x2Au},\r
+ {0x1Fu, 0x40u},\r
+ {0x22u, 0x10u},\r
+ {0x23u, 0x85u},\r
{0x27u, 0x20u},\r
{0x29u, 0x10u},\r
+ {0x2Cu, 0x08u},\r
+ {0x2Du, 0x04u},\r
{0x2Fu, 0x01u},\r
- {0x31u, 0x02u},\r
- {0x35u, 0x10u},\r
- {0x36u, 0x01u},\r
- {0x37u, 0x04u},\r
- {0x38u, 0x08u},\r
- {0x3Bu, 0x80u},\r
- {0x3Cu, 0x01u},\r
- {0x3Du, 0x28u},\r
- {0x58u, 0x20u},\r
- {0x59u, 0x84u},\r
- {0x5Bu, 0x01u},\r
- {0x62u, 0x02u},\r
- {0x63u, 0x01u},\r
- {0x66u, 0x51u},\r
- {0x67u, 0x20u},\r
+ {0x31u, 0x08u},\r
+ {0x32u, 0x10u},\r
+ {0x36u, 0x15u},\r
+ {0x37u, 0x58u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Du, 0xA1u},\r
+ {0x3Eu, 0x06u},\r
+ {0x59u, 0x24u},\r
+ {0x5Bu, 0x82u},\r
+ {0x63u, 0x41u},\r
{0x81u, 0x01u},\r
- {0x92u, 0x40u},\r
- {0x94u, 0x08u},\r
- {0x95u, 0x07u},\r
- {0x99u, 0x08u},\r
- {0x9Bu, 0x08u},\r
- {0x9Du, 0x10u},\r
- {0x9Eu, 0x03u},\r
- {0x9Fu, 0x40u},\r
- {0xA3u, 0x02u},\r
- {0xA4u, 0x08u},\r
- {0xA6u, 0x03u},\r
- {0xA9u, 0x40u},\r
- {0xAAu, 0x04u},\r
- {0xB6u, 0x01u},\r
- {0xC0u, 0x7Du},\r
- {0xC2u, 0xF8u},\r
- {0xC4u, 0xF4u},\r
- {0xCAu, 0x14u},\r
- {0xCCu, 0xE1u},\r
- {0xCEu, 0xEAu},\r
+ {0x87u, 0x40u},\r
+ {0x91u, 0x10u},\r
+ {0x92u, 0x02u},\r
+ {0x94u, 0x2Cu},\r
+ {0x95u, 0xE1u},\r
+ {0x96u, 0x0Du},\r
+ {0x98u, 0x10u},\r
+ {0x9Cu, 0x04u},\r
+ {0x9Du, 0x80u},\r
+ {0x9Eu, 0x51u},\r
+ {0x9Fu, 0x58u},\r
+ {0xA0u, 0x20u},\r
+ {0xA4u, 0x18u},\r
+ {0xA5u, 0x02u},\r
+ {0xA6u, 0x02u},\r
+ {0xA7u, 0x08u},\r
+ {0xA8u, 0x80u},\r
+ {0xA9u, 0x10u},\r
+ {0xAAu, 0x30u},\r
+ {0xC0u, 0xFFu},\r
+ {0xC2u, 0xFEu},\r
+ {0xC4u, 0xF7u},\r
+ {0xCAu, 0x74u},\r
+ {0xCCu, 0xF6u},\r
+ {0xCEu, 0xF4u},\r
{0xD6u, 0x0Fu},\r
- {0xD8u, 0xF9u},\r
- {0xE8u, 0x01u},\r
- {0xEEu, 0x40u},\r
- {0x9Cu, 0x80u},\r
- {0xABu, 0x20u},\r
- {0xB1u, 0x86u},\r
- {0xB3u, 0x20u},\r
- {0x88u, 0x80u},\r
- {0x9Cu, 0x80u},\r
+ {0xD8u, 0x09u},\r
+ {0xEAu, 0x07u},\r
+ {0xECu, 0x01u},\r
+ {0xEEu, 0x10u},\r
+ {0x38u, 0x02u},\r
+ {0x39u, 0x01u},\r
+ {0x91u, 0x22u},\r
+ {0x94u, 0x04u},\r
+ {0x95u, 0x01u},\r
+ {0x98u, 0x08u},\r
+ {0x9Au, 0x22u},\r
+ {0x9Bu, 0x10u},\r
+ {0x9Du, 0x0Bu},\r
+ {0x9Eu, 0x14u},\r
+ {0x9Fu, 0x08u},\r
+ {0xA2u, 0x52u},\r
+ {0xA4u, 0x80u},\r
+ {0xA8u, 0x04u},\r
+ {0xAAu, 0x04u},\r
+ {0xABu, 0x09u},\r
+ {0xEAu, 0x02u},\r
+ {0xEEu, 0x10u},\r
+ {0x06u, 0x02u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Eu, 0x08u},\r
+ {0x0Fu, 0x01u},\r
+ {0x10u, 0x01u},\r
+ {0x12u, 0x02u},\r
+ {0x15u, 0x02u},\r
+ {0x16u, 0x04u},\r
+ {0x17u, 0x09u},\r
+ {0x19u, 0x02u},\r
+ {0x1Au, 0x01u},\r
+ {0x1Bu, 0x05u},\r
+ {0x1Du, 0x01u},\r
+ {0x1Fu, 0x02u},\r
+ {0x2Du, 0x02u},\r
+ {0x2Fu, 0x11u},\r
+ {0x30u, 0x04u},\r
+ {0x31u, 0x04u},\r
+ {0x32u, 0x08u},\r
+ {0x33u, 0x10u},\r
+ {0x34u, 0x03u},\r
+ {0x35u, 0x08u},\r
+ {0x37u, 0x03u},\r
+ {0x3Bu, 0x80u},\r
+ {0x3Eu, 0x10u},\r
+ {0x56u, 0x08u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x99u},\r
+ {0x5Du, 0x90u},\r
+ {0x5Fu, 0x01u},\r
+ {0x80u, 0x90u},\r
+ {0x82u, 0x60u},\r
+ {0x83u, 0xFFu},\r
+ {0x84u, 0x09u},\r
+ {0x86u, 0x06u},\r
+ {0x87u, 0xFFu},\r
+ {0x88u, 0x30u},\r
+ {0x89u, 0xFFu},\r
+ {0x8Au, 0xC0u},\r
+ {0x8Du, 0x60u},\r
+ {0x8Eu, 0xFFu},\r
+ {0x8Fu, 0x90u},\r
+ {0x90u, 0x0Fu},\r
+ {0x92u, 0xF0u},\r
+ {0x95u, 0x50u},\r
+ {0x96u, 0xFFu},\r
+ {0x97u, 0xA0u},\r
+ {0x98u, 0x03u},\r
+ {0x99u, 0x03u},\r
+ {0x9Au, 0x0Cu},\r
+ {0x9Bu, 0x0Cu},\r
+ {0x9Du, 0x0Fu},\r
+ {0x9Fu, 0xF0u},\r
+ {0xA0u, 0x05u},\r
+ {0xA1u, 0x05u},\r
+ {0xA2u, 0x0Au},\r
+ {0xA3u, 0x0Au},\r
+ {0xA4u, 0x50u},\r
+ {0xA5u, 0x30u},\r
+ {0xA6u, 0xA0u},\r
+ {0xA7u, 0xC0u},\r
+ {0xA9u, 0x06u},\r
+ {0xAAu, 0xFFu},\r
+ {0xABu, 0x09u},\r
+ {0xB4u, 0xFFu},\r
+ {0xB5u, 0xFFu},\r
+ {0xBEu, 0x10u},\r
+ {0xBFu, 0x10u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDFu, 0x01u},\r
+ {0x02u, 0x02u},\r
+ {0x03u, 0x20u},\r
+ {0x04u, 0x22u},\r
+ {0x06u, 0x22u},\r
+ {0x08u, 0x18u},\r
+ {0x0Au, 0x40u},\r
+ {0x0Cu, 0x10u},\r
+ {0x0Du, 0x10u},\r
+ {0x0Eu, 0xE0u},\r
+ {0x0Fu, 0x10u},\r
+ {0x14u, 0x40u},\r
+ {0x15u, 0x02u},\r
+ {0x16u, 0x08u},\r
+ {0x17u, 0x14u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x09u},\r
+ {0x1Eu, 0x04u},\r
+ {0x20u, 0x02u},\r
+ {0x21u, 0xA8u},\r
+ {0x23u, 0x40u},\r
+ {0x27u, 0x08u},\r
+ {0x28u, 0x02u},\r
+ {0x2Cu, 0x40u},\r
+ {0x2Eu, 0x20u},\r
+ {0x2Fu, 0x20u},\r
+ {0x31u, 0xA8u},\r
+ {0x34u, 0x10u},\r
+ {0x36u, 0x40u},\r
+ {0x37u, 0x04u},\r
+ {0x3Bu, 0x40u},\r
+ {0x3Du, 0x80u},\r
+ {0x3Eu, 0x0Au},\r
+ {0x3Fu, 0x10u},\r
+ {0x59u, 0x80u},\r
+ {0x60u, 0x02u},\r
+ {0x6Cu, 0x91u},\r
+ {0x6Du, 0x80u},\r
+ {0x6Fu, 0x24u},\r
+ {0x74u, 0x40u},\r
+ {0x75u, 0x02u},\r
+ {0x76u, 0x14u},\r
+ {0x85u, 0x02u},\r
+ {0x88u, 0x41u},\r
+ {0x89u, 0x80u},\r
+ {0x8Cu, 0x10u},\r
+ {0x91u, 0x22u},\r
+ {0x94u, 0x06u},\r
+ {0x96u, 0x04u},\r
+ {0x98u, 0x08u},\r
+ {0x9Au, 0x22u},\r
+ {0x9Bu, 0x10u},\r
+ {0x9Du, 0x0Bu},\r
+ {0x9Eu, 0x14u},\r
+ {0x9Fu, 0x0Cu},\r
+ {0xA2u, 0x52u},\r
+ {0xA4u, 0x80u},\r
+ {0xABu, 0x14u},\r
+ {0xB2u, 0x74u},\r
+ {0xB4u, 0x01u},\r
+ {0xC0u, 0xF5u},\r
+ {0xC2u, 0x7Eu},\r
+ {0xC4u, 0x70u},\r
+ {0xCAu, 0xE8u},\r
+ {0xCCu, 0x7Eu},\r
+ {0xCEu, 0xF8u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x08u},\r
+ {0xE2u, 0x80u},\r
+ {0xE6u, 0x60u},\r
+ {0xEAu, 0xE0u},\r
+ {0xEEu, 0xA0u},\r
{0x12u, 0x08u},\r
{0x16u, 0x80u},\r
- {0x17u, 0x20u},\r
- {0x32u, 0x04u},\r
- {0x36u, 0x80u},\r
- {0x37u, 0x08u},\r
- {0x38u, 0x01u},\r
+ {0x17u, 0x80u},\r
+ {0x30u, 0x02u},\r
+ {0x36u, 0x22u},\r
+ {0x39u, 0x08u},\r
{0x3Au, 0x80u},\r
- {0x3Cu, 0x04u},\r
- {0x3Du, 0x40u},\r
- {0x41u, 0x10u},\r
- {0x5Au, 0x01u},\r
- {0x5Bu, 0x40u},\r
- {0x5Cu, 0x02u},\r
- {0x62u, 0x02u},\r
- {0x65u, 0x04u},\r
- {0x81u, 0x40u},\r
- {0x8Au, 0x02u},\r
- {0x8Du, 0x04u},\r
+ {0x3Du, 0x08u},\r
+ {0x3Fu, 0x10u},\r
+ {0x42u, 0x08u},\r
+ {0x53u, 0x08u},\r
+ {0x5Au, 0x08u},\r
+ {0x5Eu, 0x08u},\r
+ {0x60u, 0x08u},\r
+ {0x67u, 0x20u},\r
+ {0x82u, 0x10u},\r
+ {0x83u, 0x10u},\r
+ {0x87u, 0x50u},\r
{0xC4u, 0xE0u},\r
{0xCCu, 0xE0u},\r
{0xCEu, 0xF0u},\r
{0xD0u, 0x10u},\r
- {0xD4u, 0x80u},\r
+ {0xD4u, 0x20u},\r
{0xD6u, 0xC0u},\r
{0xD8u, 0xC0u},\r
- {0xE6u, 0x20u},\r
- {0x33u, 0x18u},\r
- {0x36u, 0x08u},\r
- {0x37u, 0x20u},\r
- {0x38u, 0x20u},\r
- {0x51u, 0x08u},\r
- {0x56u, 0x20u},\r
- {0x58u, 0x10u},\r
- {0x5Cu, 0x02u},\r
- {0x84u, 0x02u},\r
- {0x89u, 0x10u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x20u},\r
- {0x96u, 0x09u},\r
- {0x9Bu, 0x30u},\r
- {0x9Fu, 0x08u},\r
- {0xA6u, 0x80u},\r
- {0xA8u, 0x01u},\r
+ {0xE2u, 0x10u},\r
+ {0xE6u, 0xE0u},\r
+ {0x33u, 0x11u},\r
+ {0x37u, 0x88u},\r
+ {0x3Au, 0x40u},\r
+ {0x50u, 0x80u},\r
+ {0x57u, 0x10u},\r
+ {0x5Au, 0x20u},\r
+ {0x67u, 0x80u},\r
+ {0x84u, 0x08u},\r
+ {0x92u, 0x20u},\r
+ {0x93u, 0x80u},\r
+ {0x96u, 0x08u},\r
+ {0x9Bu, 0x90u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Eu, 0x08u},\r
+ {0xA3u, 0x10u},\r
+ {0xA4u, 0x02u},\r
+ {0xA5u, 0x04u},\r
+ {0xA6u, 0x26u},\r
+ {0xA7u, 0x08u},\r
{0xAAu, 0x08u},\r
- {0xABu, 0x50u},\r
- {0xACu, 0x02u},\r
+ {0xABu, 0x10u},\r
+ {0xAFu, 0x10u},\r
+ {0xB1u, 0x04u},\r
{0xCCu, 0xF0u},\r
{0xCEu, 0x10u},\r
{0xD4u, 0xE0u},\r
- {0xD6u, 0x80u},\r
- {0xE6u, 0x40u},\r
- {0xEAu, 0x80u},\r
- {0xEEu, 0xC0u},\r
- {0x12u, 0x80u},\r
- {0x32u, 0x10u},\r
- {0x58u, 0x08u},\r
- {0x88u, 0x10u},\r
- {0x8Au, 0x08u},\r
- {0x94u, 0x24u},\r
- {0x96u, 0x09u},\r
- {0x9Cu, 0x10u},\r
- {0x9Fu, 0x08u},\r
- {0xA6u, 0x88u},\r
+ {0xD8u, 0x80u},\r
+ {0xE6u, 0x10u},\r
+ {0xEAu, 0x10u},\r
+ {0x12u, 0x20u},\r
+ {0x30u, 0x20u},\r
+ {0x80u, 0x02u},\r
+ {0x8Eu, 0x04u},\r
+ {0x96u, 0x08u},\r
+ {0x9Eu, 0x48u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA4u, 0x02u},\r
+ {0xA5u, 0x04u},\r
+ {0xA6u, 0x26u},\r
{0xA7u, 0x08u},\r
- {0xAAu, 0x20u},\r
- {0xB5u, 0x08u},\r
+ {0xABu, 0x08u},\r
+ {0xB4u, 0x80u},\r
{0xC4u, 0x10u},\r
{0xCCu, 0x10u},\r
- {0xD6u, 0x40u},\r
+ {0xE2u, 0x20u},\r
{0xEAu, 0x20u},\r
- {0x86u, 0x04u},\r
- {0x87u, 0x08u},\r
- {0x8Bu, 0x08u},\r
- {0x8Cu, 0x10u},\r
- {0x8Eu, 0x10u},\r
- {0x94u, 0x24u},\r
- {0x96u, 0x28u},\r
- {0x9Fu, 0x08u},\r
- {0xA7u, 0x08u},\r
- {0xA8u, 0x08u},\r
- {0xB2u, 0x01u},\r
- {0xE6u, 0x50u},\r
- {0xEEu, 0x20u},\r
- {0x09u, 0x80u},\r
- {0x0Au, 0x20u},\r
- {0x0Cu, 0x02u},\r
- {0x10u, 0x20u},\r
- {0x15u, 0x04u},\r
- {0x50u, 0x08u},\r
- {0x52u, 0x02u},\r
- {0x57u, 0x08u},\r
- {0x5Cu, 0x40u},\r
- {0x82u, 0x02u},\r
- {0x83u, 0x08u},\r
- {0x8Eu, 0x10u},\r
+ {0x60u, 0x20u},\r
+ {0x86u, 0x42u},\r
+ {0x8Cu, 0x20u},\r
+ {0x8Du, 0x20u},\r
+ {0x96u, 0x08u},\r
+ {0x9Eu, 0x48u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA4u, 0x20u},\r
+ {0xA5u, 0x04u},\r
+ {0xA6u, 0x02u},\r
+ {0xABu, 0x08u},\r
+ {0xD8u, 0x40u},\r
+ {0xE2u, 0x50u},\r
+ {0xEEu, 0x80u},\r
+ {0x08u, 0x82u},\r
+ {0x0Fu, 0x40u},\r
+ {0x13u, 0x02u},\r
+ {0x17u, 0x04u},\r
+ {0x53u, 0x80u},\r
+ {0x56u, 0x01u},\r
+ {0x57u, 0x40u},\r
+ {0x5Bu, 0x40u},\r
+ {0x80u, 0x02u},\r
{0xC2u, 0x0Eu},\r
{0xC4u, 0x0Cu},\r
{0xD4u, 0x07u},\r
{0xD6u, 0x04u},\r
- {0xE2u, 0x02u},\r
- {0x00u, 0x08u},\r
- {0x03u, 0x08u},\r
- {0x05u, 0x02u},\r
- {0x06u, 0x02u},\r
- {0x09u, 0x12u},\r
- {0x0Du, 0x24u},\r
- {0x80u, 0x08u},\r
- {0x82u, 0x02u},\r
- {0x85u, 0x06u},\r
- {0x89u, 0x02u},\r
- {0x8Bu, 0x08u},\r
- {0x8Cu, 0x40u},\r
- {0x91u, 0x04u},\r
- {0x94u, 0x40u},\r
- {0xA0u, 0x20u},\r
- {0xA4u, 0x08u},\r
- {0xA8u, 0x02u},\r
- {0xB5u, 0x80u},\r
+ {0x02u, 0x02u},\r
+ {0x03u, 0x20u},\r
+ {0x04u, 0x80u},\r
+ {0x07u, 0x80u},\r
+ {0x09u, 0x10u},\r
+ {0x0Bu, 0x20u},\r
+ {0x0Cu, 0x20u},\r
+ {0x0Fu, 0x20u},\r
+ {0x80u, 0x40u},\r
+ {0x87u, 0x90u},\r
+ {0x8Bu, 0x20u},\r
+ {0x8Fu, 0x04u},\r
+ {0x93u, 0x40u},\r
+ {0x9Bu, 0x06u},\r
+ {0x9Eu, 0x01u},\r
+ {0xA7u, 0xC0u},\r
+ {0xA8u, 0x80u},\r
+ {0xB7u, 0x40u},\r
{0xC0u, 0x0Fu},\r
{0xC2u, 0x0Fu},\r
- {0xE0u, 0x02u},\r
- {0xE2u, 0x05u},\r
- {0xEAu, 0x08u},\r
- {0x85u, 0x04u},\r
- {0x88u, 0x02u},\r
- {0x91u, 0x04u},\r
- {0xA0u, 0x04u},\r
+ {0xE2u, 0x01u},\r
+ {0xE6u, 0x08u},\r
+ {0xE8u, 0x08u},\r
+ {0x82u, 0x02u},\r
+ {0x8Fu, 0x40u},\r
+ {0x96u, 0x40u},\r
+ {0x9Bu, 0x02u},\r
+ {0x9Eu, 0x01u},\r
{0xA1u, 0x10u},\r
- {0xA8u, 0x20u},\r
- {0xADu, 0x20u},\r
- {0xE6u, 0x01u},\r
- {0x09u, 0x20u},\r
- {0x0Bu, 0x20u},\r
- {0x0Cu, 0x02u},\r
- {0x0Eu, 0x08u},\r
- {0x87u, 0x10u},\r
- {0x8Du, 0x20u},\r
- {0x8Eu, 0x04u},\r
- {0xA4u, 0x02u},\r
+ {0xA2u, 0x02u},\r
+ {0xA7u, 0x40u},\r
+ {0xAAu, 0x40u},\r
+ {0xABu, 0x80u},\r
+ {0xACu, 0x20u},\r
+ {0xAFu, 0x40u},\r
+ {0xB7u, 0x10u},\r
+ {0xE4u, 0x02u},\r
+ {0xEAu, 0x08u},\r
+ {0x09u, 0x08u},\r
+ {0x0Au, 0x01u},\r
+ {0x0Eu, 0x40u},\r
+ {0x0Fu, 0x01u},\r
+ {0x82u, 0x01u},\r
+ {0x86u, 0x01u},\r
+ {0x96u, 0x40u},\r
+ {0x9Eu, 0x01u},\r
{0xA9u, 0x10u},\r
- {0xACu, 0x04u},\r
+ {0xAFu, 0x02u},\r
{0xC2u, 0x0Fu},\r
- {0xE2u, 0x02u},\r
- {0xE6u, 0x02u},\r
- {0x83u, 0x40u},\r
- {0x98u, 0x20u},\r
- {0xA8u, 0x20u},\r
- {0xB4u, 0x04u},\r
+ {0x81u, 0x04u},\r
+ {0x86u, 0x08u},\r
+ {0x96u, 0x08u},\r
+ {0x99u, 0x20u},\r
+ {0x9Eu, 0x08u},\r
+ {0xA3u, 0x04u},\r
+ {0xA5u, 0x04u},\r
+ {0xABu, 0x04u},\r
+ {0xAFu, 0x01u},\r
+ {0xB4u, 0x20u},\r
{0xE2u, 0x20u},\r
+ {0xE6u, 0x40u},\r
+ {0xEAu, 0x40u},\r
{0xEEu, 0x20u},\r
- {0x04u, 0x02u},\r
- {0x57u, 0x40u},\r
- {0x58u, 0x20u},\r
- {0x8Cu, 0x01u},\r
- {0x98u, 0x20u},\r
- {0xA3u, 0x40u},\r
+ {0x06u, 0x40u},\r
+ {0x57u, 0x04u},\r
+ {0x59u, 0x20u},\r
+ {0x86u, 0x40u},\r
+ {0x99u, 0x20u},\r
+ {0xA3u, 0x04u},\r
+ {0xAEu, 0x04u},\r
{0xC0u, 0x20u},\r
{0xD4u, 0xC0u},\r
- {0x01u, 0x04u},\r
- {0x89u, 0x04u},\r
+ {0xE0u, 0x10u},\r
+ {0xEEu, 0x10u},\r
+ {0xADu, 0x08u},\r
+ {0xB7u, 0x01u},\r
+ {0xEEu, 0x08u},\r
+ {0x02u, 0x40u},\r
+ {0x8Au, 0x40u},\r
{0xC0u, 0x08u},\r
- {0xE2u, 0x04u},\r
- {0x10u, 0x03u},\r
- {0x1Au, 0x03u},\r
+ {0xE6u, 0x01u},\r
+ {0x10u, 0x01u},\r
+ {0x11u, 0x01u},\r
+ {0x1Au, 0x01u},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Du, 0x01u},\r
{0x00u, 0xFDu},\r
{0x01u, 0xBFu},\r
{0x02u, 0x2Au},\r
- {0x10u, 0x55u},\r
+ {0x10u, 0x95u},\r
};\r
\r
\r
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
{(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
{(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},\r
};\r
\r
- /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */\r
- static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {\r
- 0x01u, 0xC0u, 0x00u, 0x02u, 0x40u, 0xC0u, 0x00u, 0x04u, 0x07u, 0x80u, 0x18u, 0x00u, 0x04u, 0x00u, 0x00u, 0xFFu, \r
- 0x08u, 0x90u, 0x21u, 0x40u, 0x22u, 0x1Fu, 0x08u, 0x20u, 0x40u, 0xC0u, 0x00u, 0x08u, 0x10u, 0xC0u, 0x00u, 0x01u, \r
- 0x01u, 0x00u, 0x00u, 0x9Fu, 0x01u, 0x7Fu, 0x00u, 0x80u, 0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x60u, \r
- 0x40u, 0x00u, 0x00u, 0x00u, 0x3Fu, 0xFFu, 0x08u, 0x00u, 0x22u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x10u, \r
- 0x52u, 0x03u, 0x10u, 0x00u, 0x06u, 0xBEu, 0xFDu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x2Cu, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, \r
- 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
-\r
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u},\r
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},\r
};\r
\r
.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1\r
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0\r
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB11_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB11_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB11_ST_CTL\r
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB11_MSK\r
\r
/* SCSI_Out_Ctl */\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK\r
\r
/* SCSI_Out_DBx */\r
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
.set scsiTarget_StatusReg__0__POS, 0\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__2__POS, 2\r
.set scsiTarget_StatusReg__3__MASK, 0x08\r
.set scsiTarget_StatusReg__4__MASK, 0x10\r
.set scsiTarget_StatusReg__4__POS, 4\r
.set scsiTarget_StatusReg__MASK, 0x1F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST\r
\r
/* Debug_Timer_Interrupt */\r
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK\r
-.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB07_MSK\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB07_ST\r
\r
/* SCSI_CTL_PHASE */\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK\r
+\r
+/* SCSI_Glitch_Ctl */\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK\r
\r
/* SCSI_Parity_Error */\r
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST\r
\r
/* Miscellaneous */\r
.set BCLK__BUS_CLK__HZ, 50000000\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK\r
\r
/* SCSI_Out_Ctl */\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
\r
/* SCSI_Out_DBx */\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST\r
\r
/* Debug_Timer_Interrupt */\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
\r
/* SCSI_CTL_PHASE */\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
+\r
+/* SCSI_Glitch_Ctl */\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
\r
/* SCSI_Parity_Error */\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
\r
/* Miscellaneous */\r
BCLK__BUS_CLK__HZ EQU 50000000\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
\r
; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK\r
\r
; SCSI_Out_Ctl\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
\r
; SCSI_Out_DBx\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST\r
\r
; Debug_Timer_Interrupt\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
\r
; SCSI_CTL_PHASE\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
+\r
+; SCSI_Glitch_Ctl\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
\r
; SCSI_Parity_Error\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
\r
; Miscellaneous\r
BCLK__BUS_CLK__HZ EQU 50000000\r
#include <SCSI_Parity_Error.h>\r
#include <SCSI_Filtered.h>\r
#include <SCSI_SEL_ISR.h>\r
+#include <SCSI_Glitch_Ctl.h>\r
#include <USBFS_Dm_aliases.h>\r
#include <USBFS_Dm.h>\r
#include <USBFS_Dp_aliases.h>\r
<?xml version="1.0" encoding="utf-8"?>\r
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
- <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646B" bitWidth="8" desc="" />\r
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x4000648B" bitWidth="8" desc="" />\r
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649B" bitWidth="8" desc="">\r
+ <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
+ <value name="ENABLED" value="1" desc="Enable counter" />\r
+ <value name="DISABLED" value="0" desc="Disable counter" />\r
+ </field>\r
+ <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">\r
+ <value name="ENABLED" value="1" desc="Interrupt enabled" />\r
+ <value name="DISABLED" value="0" desc="Interrupt disabled" />\r
+ </field>\r
+ <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">\r
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
+ </field>\r
+ <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">\r
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
+ </field>\r
+ <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">\r
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
+ </field>\r
+ <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">\r
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
+ </field>\r
+ </register>\r
+ </block>\r
+ <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />\r
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />\r
</block>\r
- <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" />\r
- </block>\r
+ <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" />\r
+ </block>\r
+ <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Filtered_STATUS_REG" address="0x40006468" bitWidth="8" desc="" />\r
- <register name="SCSI_Filtered_MASK_REG" address="0x40006488" bitWidth="8" desc="" />\r
- <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006498" bitWidth="8" desc="">\r
- <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
- <value name="ENABLED" value="1" desc="Enable counter" />\r
- <value name="DISABLED" value="0" desc="Disable counter" />\r
- </field>\r
- <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">\r
- <value name="ENABLED" value="1" desc="Interrupt enabled" />\r
- <value name="DISABLED" value="0" desc="Interrupt disabled" />\r
- </field>\r
- <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">\r
- <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
- <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
- </field>\r
- <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">\r
- <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
- <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
- </field>\r
- <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">\r
- <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
- <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
- </field>\r
- <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">\r
- <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
- <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
- </field>\r
- </register>\r
- </block>\r
- <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006466" bitWidth="8" desc="" />\r
- <register name="SCSI_Parity_Error_MASK_REG" address="0x40006486" bitWidth="8" desc="" />\r
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006496" bitWidth="8" desc="">\r
+ <register name="SCSI_Filtered_STATUS_REG" address="0x40006467" bitWidth="8" desc="" />\r
+ <register name="SCSI_Filtered_MASK_REG" address="0x40006487" bitWidth="8" desc="" />\r
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006497" bitWidth="8" desc="">\r
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
</field>\r
</register>\r
</block>\r
+ <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" />\r
+ <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />\r
</block>\r
+ <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />\r
- </block>\r
+ <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />\r
+ </block>\r
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- </block>\r
- <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">\r
<block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />\r
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />\r
</block>\r
+ <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ </block>\r
+ <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000657B" bitWidth="8" desc="" />\r
+ </block>\r
+ <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
<filters />\r
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctl" persistent="">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
+<dependencies>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctl.c" persistent=".\Generated_Source\PSoC5\SCSI_Glitch_Ctl.c">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="ARM_C_FILE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctl.h" persistent=".\Generated_Source\PSoC5\SCSI_Glitch_Ctl.h">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="NONE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
+</dependencies>\r
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
+<filters />\r
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
</dependencies>\r
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
<addressUnitBits>8</addressUnitBits>\r
<width>32</width>\r
<peripherals>\r
+ <peripheral>\r
+ <name>SCSI_Parity_Error</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x4000646B</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x0</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_Parity_Error_STATUS_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>SCSI_Parity_Error_MASK_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x20</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x30</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>FIFO0</name>\r
+ <description>FIFO0 clear</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Enable counter</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Disable counter</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>INTRENBL</name>\r
+ <description>Enables or disables the Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Interrupt enabled</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Interrupt disabled</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO1LEVEL</name>\r
+ <description>FIFO level</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO0LEVEL</name>\r
+ <description>FIFO level</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO1CLEAR</name>\r
+ <description>FIFO clear</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Clear FIFO state</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Normal FIFO operation</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO0CLEAR</name>\r
+ <description>FIFO clear</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Clear FIFO state</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Normal FIFO operation</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
<peripheral>\r
<name>Debug_Timer</name>\r
<description>No description available</description>\r
</registers>\r
</peripheral>\r
<peripheral>\r
- <name>SCSI_Out_Ctl</name>\r
+ <name>SCSI_Glitch_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006474</baseAddress>\r
+ <baseAddress>0x4000647A</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
</addressBlock>\r
<registers>\r
<register>\r
- <name>SCSI_Out_Ctl_CONTROL_REG</name>\r
+ <name>SCSI_Glitch_Ctl_CONTROL_REG</name>\r
<description>No description available</description>\r
<addressOffset>0x0</addressOffset>\r
<size>8</size>\r
<peripheral>\r
<name>SCSI_Filtered</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006468</baseAddress>\r
+ <baseAddress>0x40006467</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
</registers>\r
</peripheral>\r
<peripheral>\r
- <name>SCSI_Parity_Error</name>\r
- <description>No description available</description>\r
- <baseAddress>0x40006466</baseAddress>\r
- <addressBlock>\r
- <offset>0</offset>\r
- <size>0x0</size>\r
- <usage>registers</usage>\r
- </addressBlock>\r
- <registers>\r
- <register>\r
- <name>SCSI_Parity_Error_STATUS_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>SCSI_Parity_Error_MASK_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x20</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x30</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- <fields>\r
- <field>\r
- <name>FIFO0</name>\r
- <description>FIFO0 clear</description>\r
- <lsb>5</lsb>\r
- <msb>5</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>Enable counter</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>Disable counter</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>INTRENBL</name>\r
- <description>Enables or disables the Interrupt</description>\r
- <lsb>4</lsb>\r
- <msb>4</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>Interrupt enabled</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>Interrupt disabled</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>FIFO1LEVEL</name>\r
- <description>FIFO level</description>\r
- <lsb>3</lsb>\r
- <msb>3</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>FIFO0LEVEL</name>\r
- <description>FIFO level</description>\r
- <lsb>2</lsb>\r
- <msb>2</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>FIFO1CLEAR</name>\r
- <description>FIFO clear</description>\r
- <lsb>1</lsb>\r
- <msb>1</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>Clear FIFO state</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>Normal FIFO operation</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>FIFO0CLEAR</name>\r
- <description>FIFO clear</description>\r
- <lsb>0</lsb>\r
- <msb>0</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>Clear FIFO state</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>Normal FIFO operation</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- </fields>\r
- </register>\r
- </registers>\r
- </peripheral>\r
- <peripheral>\r
- <name>SCSI_Out_Bits</name>\r
+ <name>SCSI_Out_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006478</baseAddress>\r
+ <baseAddress>0x4000647C</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
</addressBlock>\r
<registers>\r
<register>\r
- <name>SCSI_Out_Bits_CONTROL_REG</name>\r
+ <name>SCSI_Out_Ctl_CONTROL_REG</name>\r
<description>No description available</description>\r
<addressOffset>0x0</addressOffset>\r
<size>8</size>\r
<peripheral>\r
<name>SCSI_CTL_PHASE</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006472</baseAddress>\r
+ <baseAddress>0x40006471</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
</register>\r
</registers>\r
</peripheral>\r
+ <peripheral>\r
+ <name>SCSI_Out_Bits</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x4000657B</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x0</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_Out_Bits_CONTROL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
</peripherals>\r
</device>
\ No newline at end of file
localparam STATE_TX = 3'b010;\r
localparam STATE_DESKEW_INIT = 3'b011;\r
localparam STATE_DESKEW = 3'b100;\r
-// This state intentionally not used.\r
+localparam STATE_WAIT_TIL_READY = 3'b101;\r
localparam STATE_READY = 3'b110;\r
localparam STATE_RX = 3'b111;\r
\r
wire txComplete = f0_blk_stat && (state == STATE_IDLE) && nACK;\r
cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg\r
(\r
- /* input */ .clock(op_clk),\r
- /* input [04:00] */ .status({3'b0, txComplete, f1_blk_stat, f0_blk_stat, f1_bus_stat, f0_bus_stat})\r
+ .clock(op_clk),\r
+ .status({3'b0, txComplete, f1_blk_stat, f0_blk_stat, f1_bus_stat, f0_bus_stat})\r
);\r
\r
// DMA outputs\r
-assign tx_intr = f0_bus_stat;\r
-assign rx_intr = f1_bus_stat;\r
+//assign tx_intr = f0_bus_stat;\r
+assign tx_intr = f0_blk_stat;\r
+//assign rx_intr = f1_bus_stat;\r
+assign rx_intr = f1_blk_stat;\r
\r
/////////////////////////////////////////////////////////////////////////////\r
// State machine\r
case (state)\r
STATE_IDLE:\r
begin\r
- // Check that SCSI initiator is ready, and input FIFO is not empty,\r
- // and output FIFO is not full.\r
- // Note that output FIFO is unused in TX mode.\r
if (!nRST) state <= STATE_IDLE;\r
- else if (nACK & !f0_blk_stat && ((IO == IO_WRITE) || !f1_blk_stat))\r
+ else if (!f0_blk_stat) // Input FIFO has some data\r
state <= STATE_FIFOLOAD;\r
else\r
state <= STATE_IDLE;\r
\r
// Clear our output pins\r
data <= 8'b0;\r
- \r
+\r
REQReg <= 1'b0;\r
fifoStore <= 1'b0;\r
parityErrReg <= 1'b0;\r
if (!nRST) state <= STATE_IDLE;\r
else if (IO == IO_WRITE)\r
state <= STATE_TX;\r
- else begin\r
+\r
+ // Check that SCSI initiator is ready, and output FIFO is not full.\r
+ else if (nACK && !f1_blk_stat) begin\r
state <= STATE_READY;\r
REQReg <= 1'b1;\r
+ end else begin\r
+ state <= STATE_WAIT_TIL_READY;\r
end\r
\r
STATE_TX:\r
\r
STATE_DESKEW:\r
if (!nRST) state <= STATE_IDLE;\r
- else if(deskewComplete) begin\r
+ else if(deskewComplete && nACK) begin\r
state <= STATE_READY;\r
REQReg <= 1'b1;\r
+ end else if (deskewComplete) begin\r
+ state <= STATE_WAIT_TIL_READY;\r
end else state <= STATE_DESKEW;\r
\r
+ STATE_WAIT_TIL_READY:\r
+ if (!nRST) state <= STATE_IDLE;\r
+\r
+ // Check that SCSI initiator is ready, and output FIFO is not full.\r
+ // Note that output FIFO is unused in TX mode.\r
+ else if (nACK && ((IO == IO_WRITE) || !f1_blk_stat)) begin\r
+ state <= STATE_READY;\r
+ REQReg <= 1'b1;\r
+ end else begin\r
+ state <= STATE_WAIT_TIL_READY;\r
+ end\r
+\r
STATE_READY:\r
if (!nRST) state <= STATE_IDLE;\r
else if (~nACK) begin\r
// D0 is used for the deskew count.\r
// The data output is valid during the DESKEW_INIT phase as well,\r
// so we subtract 1.\r
-// D0 = [0.000000055 / (1 / clk)] - 1\r
+// SCSI-1 deskew + cable skew = 55ns\r
+// D0 = [0.000000055 / (1 / clk)] - 1 = 2\r
+// SCSI-2 FAST deskew + cable skew = 25ns\r
+// D0 = [0.000000025 / (1 / clk)] - 1 = 0\r
cy_psoc3_dp #(.d0_init(2), \r
.cy_dpconfig(\r
{\r
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\r
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
- `CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE*/\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE*/\r
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,\r
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
- `CS_CMP_SEL_CFGA, /*CFGRAM1: FIFO Load*/\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM1: FIFO Load*/\r
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\r
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
- `CS_CMP_SEL_CFGA, /*CFGRAM2: TX*/\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM2: TX*/\r
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
`CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,\r
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
- `CS_CMP_SEL_CFGA, /*CFGRAM3: DESKEW INIT*/\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM3: DESKEW INIT*/\r
`CS_ALU_OP__DEC, `CS_SRCA_A0, `CS_SRCB_D0,\r
`CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\r
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
- `CS_CMP_SEL_CFGA, /*CFGRAM4: DESKEW*/\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM4: DESKEW*/\r
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\r
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
- `CS_CMP_SEL_CFGA, /*CFGRAM5: Not used*/\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM5: WAIT TIL READY*/\r
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\r
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
- `CS_CMP_SEL_CFGA, /*CFGRAM6: READY*/\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM6: READY*/\r
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\r
`CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
- `CS_CMP_SEL_CFGA, /*CFGRAM7: RX*/\r
- 8'hFF, 8'h00, /*CFG9: */\r
- 8'hFF, 8'hFF, /*CFG11-10: */\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM7: RX*/\r
+ 8'hFF, 8'h00, /*CFG9: */\r
+ 8'hFF, 8'hFF, /*CFG11-10: */\r
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,\r
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,\r
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,\r
- `SC_SI_A_DEFSI, /*CFG13-12: */\r
+ `SC_SI_A_DEFSI, /*CFG13-12: */\r
`SC_A0_SRC_ACC, `SC_SHIFT_SL, `SC_PI_DYN_EN,\r
1'h0, `SC_FIFO1_ALU, `SC_FIFO0_BUS,\r
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,\r
`SC_FB_NOCHN, `SC_CMP1_NOCHN,\r
- `SC_CMP0_NOCHN, /*CFG15-14: */\r
+ `SC_CMP0_NOCHN, /*CFG15-14: */\r
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,\r
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,\r
- `SC_WRK16CAT_DSBL /*CFG17-16: */\r
+ `SC_WRK16CAT_DSBL /*CFG17-16: */\r
}\r
)) datapath(\r
/* input */ .reset(1'b0),\r
//`#start footer` -- edit after this line, do not edit this line\r
//`#end` -- edit above this line, do not edit this line\r
\r
+\r
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Glitch_Ctl.c
+* Version 1.70
+*
+* Description:
+* This file contains API to enable firmware control of a Control Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Glitch_Ctl.h"
+
+#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Write
+********************************************************************************
+*
+* Summary:
+* Write a byte to the Control Register.
+*
+* Parameters:
+* control: The value to be assigned to the Control Register.
+*
+* Return:
+* None.
+*
+*******************************************************************************/
+void SCSI_Glitch_Ctl_Write(uint8 control)
+{
+ SCSI_Glitch_Ctl_Control = control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Glitch_Ctl_Read
+********************************************************************************
+*
+* Summary:
+* Reads the current value assigned to the Control Register.
+*
+* Parameters:
+* None.
+*
+* Return:
+* Returns the current value in the Control Register.
+*
+*******************************************************************************/
+uint8 SCSI_Glitch_Ctl_Read(void)
+{
+ return SCSI_Glitch_Ctl_Control;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Glitch_Ctl.h
+* Version 1.70
+*
+* Description:
+* This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CONTROL_REG_SCSI_Glitch_Ctl_H) /* CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
+#define CY_CONTROL_REG_SCSI_Glitch_Ctl_H
+
+#include "cytypes.h"
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+void SCSI_Glitch_Ctl_Write(uint8 control) ;
+uint8 SCSI_Glitch_Ctl_Read(void) ;
+
+
+/***************************************
+* Registers
+***************************************/
+
+/* Control Register */
+#define SCSI_Glitch_Ctl_Control (* (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG )
+#define SCSI_Glitch_Ctl_Control_PTR ( (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG )
+
+#endif /* End CY_CONTROL_REG_SCSI_Glitch_Ctl_H */
+
+
+/* [] END OF FILE */
***************************************/
#define SDCard_INT_ON_SPI_DONE ((uint8) (0u << SDCard_STS_SPI_DONE_SHIFT))
-#define SDCard_INT_ON_TX_EMPTY ((uint8) (0u << SDCard_STS_TX_FIFO_EMPTY_SHIFT))
-#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (1u << \
+#define SDCard_INT_ON_TX_EMPTY ((uint8) (1u << SDCard_STS_TX_FIFO_EMPTY_SHIFT))
+#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \
SDCard_STS_TX_FIFO_NOT_FULL_SHIFT))
#define SDCard_INT_ON_BYTE_COMP ((uint8) (0u << SDCard_STS_BYTE_COMPLETE_SHIFT))
#define SDCard_INT_ON_SPI_IDLE ((uint8) (0u << SDCard_STS_SPI_IDLE_SHIFT))
#define EXTLED__SLW CYREG_PRT0_SLW
/* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB09_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB09_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB09_MSK
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB09_10_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB09_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB09_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB09_ST
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB09_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB09_ST
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB09_10_A0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB09_10_A1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB09_10_D0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB09_10_D1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB09_10_F0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB09_10_F1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB09_A0_A1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB09_A0
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB09_A1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB09_D0_D1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB09_D0
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB09_D1
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB09_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB09_F0_F1
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB09_F0
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB09_F1
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
#define SDCard_BSPIM_TxStsReg__2__POS 2
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB10_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB10_ST
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
/* SD_SCK */
#define SD_SCK__0__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
/* SCSI_Out_Ctl */
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK
/* SCSI_Out_DBx */
#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
#define SCSI_Noise__SEL__SLW CYREG_PRT4_SLW
/* scsiTarget */
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB11_12_A0
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB11_12_A1
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB11_12_D0
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB11_12_D1
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB11_12_F0
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB11_12_F1
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB11_A0_A1
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB11_A0
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB11_A1
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB11_D0_D1
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB11_D0
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB11_D1
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB11_F0_F1
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB11_F0
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB11_F1
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB11_MSK
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB11_ST
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB11_CTL
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB11_CTL
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB11_MSK
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB00_01_A1
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB00_01_D0
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB00_01_D1
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB00_01_F0
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB00_01_F1
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB00_A0_A1
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB00_A0
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB00_A1
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB00_D0_D1
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB00_D0
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB00_D1
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB00_ACTL
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB00_F0_F1
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB00_F0
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB00_F1
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB00_MSK
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB00_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB00_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB00_ST
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB00_CTL
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB00_CTL
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB00_MSK
#define scsiTarget_StatusReg__0__MASK 0x01u
#define scsiTarget_StatusReg__0__POS 0
#define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
#define scsiTarget_StatusReg__2__MASK 0x04u
#define scsiTarget_StatusReg__2__POS 2
#define scsiTarget_StatusReg__3__MASK 0x08u
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB07_MSK
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB07_ST
/* Debug_Timer_Interrupt */
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_Filtered_sts_sts_reg__0__POS 0
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
#define SCSI_Filtered_sts_sts_reg__1__POS 1
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
#define SCSI_Filtered_sts_sts_reg__2__POS 2
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
#define SCSI_Filtered_sts_sts_reg__4__POS 4
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK
-#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB01_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB01_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK
+#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
+
+/* SCSI_Glitch_Ctl */
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB04_MSK
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB04_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB09_MSK
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB09_ST
/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 50000000U
}
#endif
-#define CY_CFG_BASE_ADDR_COUNT 40u
+#define CY_CFG_BASE_ADDR_COUNT 41u
CYPACKED typedef struct
{
uint8 offset;
/* Configure Digital Clocks based on settings from Clock DWR */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0000u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u);
- CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0000u);
- CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x58u);
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u);
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u);
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u);
0x40005210u, /* Base address: 0x40005200 Count: 16 */
0x40006401u, /* Base address: 0x40006400 Count: 1 */
0x40006501u, /* Base address: 0x40006500 Count: 1 */
- 0x40010041u, /* Base address: 0x40010000 Count: 65 */
- 0x40010141u, /* Base address: 0x40010100 Count: 65 */
- 0x40010259u, /* Base address: 0x40010200 Count: 89 */
- 0x40010351u, /* Base address: 0x40010300 Count: 81 */
- 0x4001044Eu, /* Base address: 0x40010400 Count: 78 */
- 0x4001054Bu, /* Base address: 0x40010500 Count: 75 */
- 0x40010716u, /* Base address: 0x40010700 Count: 22 */
- 0x40010849u, /* Base address: 0x40010800 Count: 73 */
- 0x40010950u, /* Base address: 0x40010900 Count: 80 */
- 0x40010A3Cu, /* Base address: 0x40010A00 Count: 60 */
- 0x40010B5Bu, /* Base address: 0x40010B00 Count: 91 */
- 0x40010C4Bu, /* Base address: 0x40010C00 Count: 75 */
- 0x40010D55u, /* Base address: 0x40010D00 Count: 85 */
- 0x40010E53u, /* Base address: 0x40010E00 Count: 83 */
- 0x40010F3Fu, /* Base address: 0x40010F00 Count: 63 */
- 0x40011505u, /* Base address: 0x40011500 Count: 5 */
- 0x40011711u, /* Base address: 0x40011700 Count: 17 */
- 0x4001181Cu, /* Base address: 0x40011800 Count: 28 */
- 0x40011950u, /* Base address: 0x40011900 Count: 80 */
- 0x40011A50u, /* Base address: 0x40011A00 Count: 80 */
- 0x40011B4Bu, /* Base address: 0x40011B00 Count: 75 */
- 0x40014018u, /* Base address: 0x40014000 Count: 24 */
- 0x40014117u, /* Base address: 0x40014100 Count: 23 */
- 0x40014218u, /* Base address: 0x40014200 Count: 24 */
+ 0x40010048u, /* Base address: 0x40010000 Count: 72 */
+ 0x40010145u, /* Base address: 0x40010100 Count: 69 */
+ 0x40010244u, /* Base address: 0x40010200 Count: 68 */
+ 0x40010362u, /* Base address: 0x40010300 Count: 98 */
+ 0x4001044Cu, /* Base address: 0x40010400 Count: 76 */
+ 0x4001055Eu, /* Base address: 0x40010500 Count: 94 */
+ 0x4001064Bu, /* Base address: 0x40010600 Count: 75 */
+ 0x40010759u, /* Base address: 0x40010700 Count: 89 */
+ 0x4001084Eu, /* Base address: 0x40010800 Count: 78 */
+ 0x40010955u, /* Base address: 0x40010900 Count: 85 */
+ 0x40010A47u, /* Base address: 0x40010A00 Count: 71 */
+ 0x40010B58u, /* Base address: 0x40010B00 Count: 88 */
+ 0x40010C4Fu, /* Base address: 0x40010C00 Count: 79 */
+ 0x40010D49u, /* Base address: 0x40010D00 Count: 73 */
+ 0x40010F08u, /* Base address: 0x40010F00 Count: 8 */
+ 0x40011417u, /* Base address: 0x40011400 Count: 23 */
+ 0x4001154Eu, /* Base address: 0x40011500 Count: 78 */
+ 0x4001164Du, /* Base address: 0x40011600 Count: 77 */
+ 0x4001175Bu, /* Base address: 0x40011700 Count: 91 */
+ 0x40011918u, /* Base address: 0x40011900 Count: 24 */
+ 0x40011A04u, /* Base address: 0x40011A00 Count: 4 */
+ 0x40011B12u, /* Base address: 0x40011B00 Count: 18 */
+ 0x40014015u, /* Base address: 0x40014000 Count: 21 */
+ 0x4001411Du, /* Base address: 0x40014100 Count: 29 */
+ 0x40014213u, /* Base address: 0x40014200 Count: 19 */
0x4001430Bu, /* Base address: 0x40014300 Count: 11 */
- 0x40014410u, /* Base address: 0x40014400 Count: 16 */
- 0x4001451Au, /* Base address: 0x40014500 Count: 26 */
- 0x4001460Eu, /* Base address: 0x40014600 Count: 14 */
- 0x40014715u, /* Base address: 0x40014700 Count: 21 */
- 0x40014805u, /* Base address: 0x40014800 Count: 5 */
- 0x4001490Cu, /* Base address: 0x40014900 Count: 12 */
- 0x40014C07u, /* Base address: 0x40014C00 Count: 7 */
- 0x40014D0Cu, /* Base address: 0x40014D00 Count: 12 */
- 0x40015004u, /* Base address: 0x40015000 Count: 4 */
+ 0x4001440Eu, /* Base address: 0x40014400 Count: 14 */
+ 0x40014516u, /* Base address: 0x40014500 Count: 22 */
+ 0x40014617u, /* Base address: 0x40014600 Count: 23 */
+ 0x4001470Eu, /* Base address: 0x40014700 Count: 14 */
+ 0x4001480Au, /* Base address: 0x40014800 Count: 10 */
+ 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */
+ 0x40014C0Du, /* Base address: 0x40014C00 Count: 13 */
+ 0x40014D0Eu, /* Base address: 0x40014D00 Count: 14 */
+ 0x40015002u, /* Base address: 0x40015000 Count: 2 */
0x40015104u, /* Base address: 0x40015100 Count: 4 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x7Eu, 0x02u},
{0x01u, 0x20u},
- {0x0Au, 0x4Bu},
- {0x00u, 0x04u},
- {0x01u, 0x48u},
+ {0x0Au, 0x36u},
+ {0x00u, 0x44u},
+ {0x01u, 0x01u},
{0x04u, 0x31u},
- {0x10u, 0x88u},
- {0x11u, 0x84u},
- {0x18u, 0x08u},
- {0x19u, 0x04u},
+ {0x10u, 0x48u},
+ {0x11u, 0x0Cu},
+ {0x18u, 0x04u},
+ {0x19u, 0x08u},
{0x1Cu, 0x30u},
- {0x20u, 0x10u},
{0x21u, 0x10u},
{0x24u, 0x44u},
- {0x29u, 0x01u},
- {0x30u, 0x20u},
- {0x31u, 0x30u},
+ {0x28u, 0x02u},
+ {0x29u, 0x02u},
+ {0x31u, 0x10u},
{0x78u, 0x20u},
+ {0x79u, 0x20u},
{0x7Cu, 0x40u},
- {0x2Bu, 0x02u},
- {0x89u, 0x0Fu},
- {0x01u, 0x02u},
- {0x02u, 0x02u},
- {0x03u, 0x11u},
- {0x05u, 0x80u},
- {0x07u, 0x40u},
- {0x09u, 0x01u},
- {0x0Bu, 0x02u},
- {0x0Du, 0x40u},
- {0x0Fu, 0x80u},
- {0x11u, 0x13u},
- {0x12u, 0x04u},
- {0x13u, 0x2Cu},
- {0x15u, 0x80u},
- {0x17u, 0x40u},
- {0x19u, 0x80u},
- {0x1Au, 0x01u},
- {0x1Bu, 0x40u},
- {0x1Du, 0x80u},
- {0x1Eu, 0x08u},
- {0x1Fu, 0x40u},
- {0x21u, 0x04u},
- {0x23u, 0x08u},
- {0x29u, 0x08u},
- {0x2Bu, 0x24u},
- {0x30u, 0x01u},
- {0x31u, 0xC0u},
+ {0x20u, 0x02u},
+ {0x86u, 0x0Fu},
+ {0x00u, 0x01u},
+ {0x01u, 0x03u},
+ {0x03u, 0x0Cu},
+ {0x07u, 0xFFu},
+ {0x09u, 0x05u},
+ {0x0Bu, 0x0Au},
+ {0x0Du, 0xFFu},
+ {0x10u, 0x08u},
+ {0x11u, 0x60u},
+ {0x13u, 0x90u},
+ {0x15u, 0x0Fu},
+ {0x17u, 0xF0u},
+ {0x18u, 0x02u},
+ {0x1Du, 0x06u},
+ {0x1Fu, 0x09u},
+ {0x21u, 0x30u},
+ {0x23u, 0xC0u},
+ {0x24u, 0x04u},
+ {0x25u, 0x50u},
+ {0x27u, 0xA0u},
+ {0x2Bu, 0xFFu},
+ {0x30u, 0x02u},
{0x32u, 0x04u},
- {0x33u, 0x30u},
- {0x34u, 0x08u},
- {0x35u, 0x0Fu},
- {0x36u, 0x02u},
- {0x3Bu, 0x02u},
- {0x3Fu, 0x14u},
- {0x56u, 0x08u},
+ {0x34u, 0x01u},
+ {0x36u, 0x08u},
+ {0x37u, 0xFFu},
+ {0x3Eu, 0x55u},
+ {0x3Fu, 0x40u},
+ {0x40u, 0x52u},
+ {0x41u, 0x04u},
+ {0x42u, 0x60u},
+ {0x45u, 0xE2u},
+ {0x46u, 0xCDu},
+ {0x47u, 0x0Fu},
+ {0x48u, 0x1Fu},
+ {0x49u, 0xFFu},
+ {0x4Au, 0xFFu},
+ {0x4Bu, 0xFFu},
+ {0x4Fu, 0x2Cu},
+ {0x56u, 0x01u},
{0x58u, 0x04u},
{0x59u, 0x04u},
+ {0x5Au, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x99u},
- {0x5Du, 0x90u},
+ {0x5Du, 0x01u},
{0x5Fu, 0x01u},
- {0x83u, 0x04u},
- {0x86u, 0x70u},
- {0x8Au, 0x08u},
- {0x8Cu, 0x99u},
- {0x8Eu, 0x22u},
- {0x8Fu, 0x01u},
- {0x93u, 0x08u},
- {0x98u, 0xAAu},
- {0x9Au, 0x55u},
- {0x9Bu, 0x02u},
- {0x9Eu, 0x07u},
- {0xA2u, 0x80u},
- {0xACu, 0x44u},
- {0xAEu, 0x88u},
- {0xB1u, 0x02u},
- {0xB3u, 0x01u},
- {0xB4u, 0xF0u},
- {0xB5u, 0x08u},
- {0xB6u, 0x0Fu},
- {0xB7u, 0x04u},
- {0xD8u, 0x04u},
+ {0x62u, 0xC0u},
+ {0x66u, 0x80u},
+ {0x68u, 0x40u},
+ {0x69u, 0x40u},
+ {0x6Eu, 0x08u},
+ {0x81u, 0x03u},
+ {0x83u, 0x0Cu},
+ {0x85u, 0xFFu},
+ {0x89u, 0x05u},
+ {0x8Bu, 0x0Au},
+ {0x8Du, 0x30u},
+ {0x8Fu, 0xC0u},
+ {0x91u, 0x50u},
+ {0x93u, 0xA0u},
+ {0x95u, 0x0Fu},
+ {0x97u, 0xF0u},
+ {0x9Du, 0x09u},
+ {0x9Fu, 0x06u},
+ {0xA1u, 0x90u},
+ {0xA3u, 0x60u},
+ {0xABu, 0xFFu},
+ {0xADu, 0xFFu},
+ {0xB5u, 0xFFu},
+ {0xBFu, 0x10u},
{0xD9u, 0x04u},
- {0xDBu, 0x04u},
- {0xDCu, 0x91u},
{0xDFu, 0x01u},
- {0x03u, 0x40u},
- {0x04u, 0x04u},
- {0x05u, 0x10u},
- {0x07u, 0x01u},
- {0x0Au, 0x89u},
- {0x0Cu, 0x80u},
- {0x0Eu, 0x02u},
- {0x0Fu, 0x04u},
- {0x15u, 0x02u},
- {0x16u, 0x01u},
- {0x19u, 0x80u},
- {0x1Au, 0xA8u},
- {0x1Cu, 0x04u},
- {0x1Eu, 0x02u},
- {0x1Fu, 0x10u},
- {0x20u, 0x08u},
- {0x21u, 0x18u},
- {0x22u, 0x02u},
- {0x23u, 0x40u},
- {0x24u, 0x80u},
- {0x25u, 0x64u},
- {0x26u, 0x20u},
- {0x27u, 0x50u},
+ {0x00u, 0x80u},
+ {0x01u, 0x40u},
+ {0x02u, 0x40u},
+ {0x08u, 0x20u},
+ {0x09u, 0x02u},
+ {0x12u, 0x10u},
+ {0x18u, 0x01u},
+ {0x19u, 0x09u},
+ {0x1Bu, 0x20u},
+ {0x21u, 0x80u},
+ {0x24u, 0x08u},
{0x28u, 0x04u},
+ {0x29u, 0x14u},
+ {0x2Au, 0x01u},
{0x2Bu, 0x40u},
- {0x2Du, 0x01u},
- {0x2Eu, 0x02u},
+ {0x2Cu, 0x04u},
+ {0x2Du, 0x40u},
+ {0x2Eu, 0x01u},
{0x30u, 0x02u},
- {0x32u, 0x54u},
- {0x34u, 0x02u},
- {0x36u, 0x20u},
- {0x39u, 0x08u},
- {0x3Au, 0x60u},
- {0x3Bu, 0x41u},
- {0x3Du, 0x80u},
- {0x3Fu, 0x02u},
- {0x58u, 0x80u},
- {0x5Du, 0x01u},
- {0x5Eu, 0x40u},
- {0x5Fu, 0x28u},
- {0x63u, 0x02u},
- {0x66u, 0x40u},
- {0x68u, 0x03u},
- {0x6Du, 0x04u},
- {0x6Fu, 0x2Au},
- {0x81u, 0x28u},
+ {0x31u, 0x08u},
+ {0x32u, 0x48u},
+ {0x33u, 0x40u},
+ {0x36u, 0x09u},
+ {0x37u, 0x40u},
+ {0x39u, 0x51u},
+ {0x3Au, 0x08u},
+ {0x3Du, 0x11u},
+ {0x3Eu, 0x08u},
+ {0x3Fu, 0x80u},
+ {0x41u, 0x20u},
+ {0x42u, 0x40u},
+ {0x48u, 0x10u},
+ {0x49u, 0x80u},
+ {0x4Bu, 0x22u},
+ {0x4Cu, 0x08u},
+ {0x4Du, 0x20u},
+ {0x50u, 0x28u},
+ {0x52u, 0x80u},
+ {0x53u, 0x80u},
+ {0x59u, 0x42u},
+ {0x5Au, 0x18u},
+ {0x60u, 0x05u},
+ {0x61u, 0x01u},
+ {0x63u, 0x10u},
+ {0x68u, 0x85u},
+ {0x69u, 0x08u},
+ {0x70u, 0x40u},
+ {0x73u, 0x64u},
+ {0x81u, 0x06u},
{0x82u, 0x01u},
- {0x87u, 0x0Au},
- {0x88u, 0x01u},
- {0x89u, 0x10u},
- {0x8Au, 0x20u},
- {0x8Bu, 0x10u},
- {0x8Cu, 0xC0u},
- {0x8Eu, 0x02u},
- {0x8Fu, 0x40u},
- {0xC0u, 0xE8u},
- {0xC2u, 0xCBu},
- {0xC4u, 0x90u},
- {0xCAu, 0x05u},
- {0xCCu, 0xAFu},
- {0xCEu, 0x9Fu},
- {0xD6u, 0xF8u},
- {0xD8u, 0x18u},
- {0xE0u, 0x05u},
- {0xE4u, 0x01u},
- {0x00u, 0x08u},
- {0x01u, 0x04u},
- {0x02u, 0x04u},
- {0x03u, 0x02u},
- {0x05u, 0x04u},
- {0x06u, 0x01u},
- {0x07u, 0x02u},
- {0x09u, 0x08u},
- {0x0Bu, 0x10u},
- {0x0Du, 0x04u},
- {0x0Fu, 0x02u},
- {0x10u, 0x04u},
- {0x11u, 0x10u},
- {0x12u, 0x08u},
- {0x13u, 0x08u},
- {0x15u, 0x10u},
- {0x17u, 0x08u},
- {0x19u, 0x02u},
- {0x1Au, 0x02u},
- {0x1Bu, 0x04u},
- {0x1Du, 0x10u},
- {0x1Fu, 0x08u},
- {0x20u, 0x08u},
- {0x22u, 0x04u},
- {0x24u, 0x08u},
- {0x25u, 0x04u},
- {0x26u, 0x04u},
- {0x27u, 0x02u},
- {0x28u, 0x08u},
- {0x2Au, 0x04u},
- {0x2Bu, 0x01u},
- {0x2Du, 0x10u},
- {0x2Fu, 0x08u},
- {0x30u, 0x0Cu},
- {0x33u, 0x06u},
- {0x34u, 0x01u},
- {0x35u, 0x18u},
- {0x36u, 0x02u},
- {0x37u, 0x01u},
- {0x3Au, 0x02u},
- {0x3Bu, 0x28u},
- {0x56u, 0x08u},
+ {0x83u, 0x20u},
+ {0x85u, 0x10u},
+ {0x87u, 0x80u},
+ {0x88u, 0x07u},
+ {0x8Au, 0x01u},
+ {0x8Eu, 0x40u},
+ {0x8Fu, 0x80u},
+ {0xC0u, 0x08u},
+ {0xC2u, 0x0Au},
+ {0xC4u, 0x04u},
+ {0xCAu, 0xB7u},
+ {0xCCu, 0xDBu},
+ {0xCEu, 0xFFu},
+ {0xD0u, 0x05u},
+ {0xD2u, 0x0Cu},
+ {0xD6u, 0x0Fu},
+ {0xD8u, 0x0Fu},
+ {0xE2u, 0x42u},
+ {0xE6u, 0x09u},
+ {0x04u, 0x0Fu},
+ {0x06u, 0xF0u},
+ {0x0Bu, 0x03u},
+ {0x0Cu, 0x06u},
+ {0x0Eu, 0x09u},
+ {0x10u, 0x05u},
+ {0x12u, 0x0Au},
+ {0x15u, 0x06u},
+ {0x1Bu, 0x01u},
+ {0x20u, 0x60u},
+ {0x22u, 0x90u},
+ {0x24u, 0x30u},
+ {0x26u, 0xC0u},
+ {0x27u, 0x05u},
+ {0x28u, 0x03u},
+ {0x2Au, 0x0Cu},
+ {0x2Cu, 0x50u},
+ {0x2Eu, 0xA0u},
+ {0x30u, 0xFFu},
+ {0x33u, 0x07u},
+ {0x3Eu, 0x01u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x99u},
- {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x80u, 0x90u},
- {0x82u, 0x60u},
- {0x84u, 0xFFu},
- {0x85u, 0xFFu},
- {0x88u, 0x50u},
- {0x8Au, 0xA0u},
- {0x8Bu, 0xFFu},
- {0x90u, 0xFFu},
- {0x91u, 0xFFu},
- {0x94u, 0x03u},
- {0x95u, 0x0Fu},
- {0x96u, 0x0Cu},
- {0x97u, 0xF0u},
- {0x98u, 0x05u},
- {0x9Au, 0x0Au},
- {0x9Du, 0x33u},
- {0x9Fu, 0xCCu},
- {0xA0u, 0x09u},
- {0xA2u, 0x06u},
- {0xA3u, 0xFFu},
- {0xA5u, 0x96u},
- {0xA6u, 0xFFu},
- {0xA7u, 0x69u},
- {0xA8u, 0x30u},
- {0xA9u, 0x55u},
- {0xAAu, 0xC0u},
- {0xABu, 0xAAu},
- {0xACu, 0x0Fu},
- {0xAEu, 0xF0u},
- {0xAFu, 0xFFu},
- {0xB2u, 0xFFu},
- {0xB3u, 0xFFu},
- {0xBBu, 0x08u},
- {0xBEu, 0x04u},
+ {0x83u, 0x04u},
+ {0x86u, 0x38u},
+ {0x8Au, 0x10u},
+ {0x8Cu, 0x2Cu},
+ {0x8Du, 0x20u},
+ {0x8Eu, 0x40u},
+ {0x8Fu, 0x10u},
+ {0x90u, 0x04u},
+ {0x91u, 0x18u},
+ {0x92u, 0x10u},
+ {0x93u, 0x20u},
+ {0x95u, 0x02u},
+ {0x96u, 0x7Cu},
+ {0x97u, 0x04u},
+ {0x98u, 0x50u},
+ {0x9Au, 0x2Cu},
+ {0x9Cu, 0x02u},
+ {0x9Fu, 0x02u},
+ {0xA0u, 0x20u},
+ {0xA5u, 0x20u},
+ {0xA6u, 0x0Cu},
+ {0xA7u, 0x10u},
+ {0xA8u, 0x01u},
+ {0xA9u, 0x01u},
+ {0xACu, 0x80u},
+ {0xB0u, 0x80u},
+ {0xB1u, 0x30u},
+ {0xB2u, 0x01u},
+ {0xB3u, 0x01u},
+ {0xB4u, 0x02u},
+ {0xB5u, 0x06u},
+ {0xB6u, 0x7Cu},
+ {0xB7u, 0x08u},
+ {0xBBu, 0x02u},
+ {0xBEu, 0x15u},
+ {0xBFu, 0x14u},
{0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x10u},
+ {0xDCu, 0x91u},
{0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x08u},
- {0x02u, 0x40u},
- {0x03u, 0x04u},
- {0x05u, 0x01u},
- {0x07u, 0x10u},
+ {0x00u, 0x28u},
+ {0x01u, 0x80u},
+ {0x04u, 0x40u},
+ {0x05u, 0x04u},
+ {0x08u, 0x04u},
{0x09u, 0x20u},
- {0x0Bu, 0xA0u},
- {0x0Eu, 0x48u},
- {0x10u, 0x82u},
- {0x11u, 0x04u},
- {0x12u, 0x04u},
- {0x15u, 0x10u},
- {0x16u, 0x20u},
- {0x17u, 0x02u},
- {0x18u, 0x10u},
- {0x1Eu, 0x46u},
- {0x22u, 0x08u},
- {0x25u, 0x10u},
- {0x27u, 0x2Au},
+ {0x0Au, 0x40u},
+ {0x0Bu, 0x01u},
+ {0x0Fu, 0x80u},
+ {0x11u, 0x08u},
+ {0x12u, 0x86u},
+ {0x14u, 0x01u},
+ {0x15u, 0x20u},
+ {0x16u, 0x80u},
+ {0x17u, 0x08u},
+ {0x18u, 0x04u},
+ {0x19u, 0x80u},
+ {0x1Au, 0x10u},
+ {0x1Bu, 0x82u},
+ {0x1Cu, 0x80u},
+ {0x1Eu, 0x80u},
+ {0x20u, 0x02u},
+ {0x21u, 0x01u},
+ {0x22u, 0x25u},
+ {0x27u, 0x10u},
{0x28u, 0x08u},
- {0x29u, 0x08u},
- {0x2Au, 0x82u},
- {0x2Du, 0x10u},
- {0x2Eu, 0x04u},
- {0x2Fu, 0x09u},
- {0x32u, 0x8Au},
- {0x35u, 0x40u},
- {0x36u, 0x05u},
- {0x37u, 0x20u},
- {0x38u, 0x20u},
- {0x3Bu, 0x04u},
- {0x3Du, 0xA8u},
- {0x3Fu, 0x02u},
- {0x5Bu, 0x40u},
- {0x5Du, 0x80u},
- {0x62u, 0x80u},
- {0x64u, 0x03u},
- {0x80u, 0x10u},
- {0x81u, 0x18u},
- {0x82u, 0x01u},
- {0x83u, 0x50u},
+ {0x2Bu, 0x10u},
+ {0x2Du, 0x08u},
+ {0x31u, 0x0Cu},
+ {0x32u, 0x41u},
+ {0x36u, 0x08u},
+ {0x37u, 0x10u},
+ {0x39u, 0x40u},
+ {0x3Au, 0x01u},
+ {0x3Du, 0x20u},
+ {0x41u, 0x10u},
+ {0x43u, 0x20u},
+ {0x5Au, 0x20u},
+ {0x5Bu, 0x86u},
+ {0x60u, 0x20u},
+ {0x61u, 0x02u},
+ {0x62u, 0x50u},
+ {0x6Cu, 0x18u},
+ {0x6Du, 0x08u},
+ {0x6Eu, 0x08u},
+ {0x6Fu, 0x01u},
+ {0x7Du, 0x01u},
+ {0x7Eu, 0x40u},
+ {0x81u, 0x40u},
+ {0x82u, 0x04u},
+ {0x84u, 0x20u},
+ {0x87u, 0x0Au},
{0x88u, 0x01u},
- {0x8Eu, 0x10u},
- {0x90u, 0x04u},
- {0x91u, 0x24u},
- {0x93u, 0x20u},
- {0x95u, 0x02u},
- {0x96u, 0x40u},
- {0x97u, 0x04u},
- {0x98u, 0x10u},
- {0x9Au, 0x02u},
- {0x9Bu, 0x10u},
- {0x9Cu, 0x06u},
- {0x9Du, 0x10u},
- {0x9Eu, 0x01u},
- {0x9Fu, 0x29u},
- {0xA0u, 0x86u},
- {0xA1u, 0x45u},
- {0xA2u, 0x02u},
- {0xA3u, 0x01u},
- {0xA9u, 0x81u},
- {0xABu, 0x01u},
- {0xADu, 0x04u},
- {0xAEu, 0x01u},
- {0xB0u, 0x10u},
- {0xB2u, 0x02u},
- {0xB3u, 0x20u},
- {0xC0u, 0x3Eu},
- {0xC2u, 0x5Eu},
- {0xC4u, 0x7Fu},
- {0xCAu, 0x7Fu},
- {0xCCu, 0xFBu},
- {0xCEu, 0xF6u},
- {0xD6u, 0x18u},
- {0xD8u, 0x18u},
+ {0x8Bu, 0x12u},
+ {0x8Du, 0x10u},
+ {0x8Eu, 0x44u},
+ {0x8Fu, 0x04u},
+ {0x90u, 0x88u},
+ {0x91u, 0x18u},
+ {0x93u, 0x46u},
+ {0x94u, 0x04u},
+ {0x95u, 0x01u},
+ {0x96u, 0x58u},
+ {0x97u, 0x10u},
+ {0x99u, 0x20u},
+ {0x9Au, 0x28u},
+ {0x9Bu, 0xA0u},
+ {0x9Cu, 0x20u},
+ {0x9Du, 0x90u},
+ {0x9Eu, 0x51u},
+ {0x9Fu, 0x01u},
+ {0xA0u, 0xB0u},
+ {0xA1u, 0x80u},
+ {0xA2u, 0x80u},
+ {0xA4u, 0x40u},
+ {0xA5u, 0x2Au},
+ {0xA8u, 0x02u},
+ {0xAAu, 0x08u},
+ {0xACu, 0x10u},
+ {0xADu, 0x48u},
+ {0xAEu, 0x20u},
+ {0xAFu, 0x11u},
+ {0xB4u, 0x20u},
+ {0xC0u, 0xA7u},
+ {0xC2u, 0x1Fu},
+ {0xC4u, 0xFFu},
+ {0xCAu, 0x46u},
+ {0xCCu, 0x6Bu},
+ {0xCEu, 0x29u},
+ {0xD6u, 0x0Fu},
+ {0xD8u, 0x0Fu},
{0xE0u, 0x01u},
- {0xE2u, 0x24u},
- {0xE6u, 0x05u},
- {0xE8u, 0x04u},
- {0xEAu, 0x09u},
- {0xEEu, 0x01u},
- {0x00u, 0x03u},
- {0x02u, 0x0Cu},
- {0x04u, 0x0Fu},
- {0x05u, 0x03u},
- {0x07u, 0x0Cu},
- {0x08u, 0x80u},
- {0x0Bu, 0xFFu},
- {0x0Cu, 0x80u},
- {0x0Du, 0xFFu},
- {0x10u, 0x10u},
- {0x11u, 0x0Fu},
- {0x12u, 0x2Fu},
- {0x13u, 0xF0u},
- {0x14u, 0x20u},
- {0x15u, 0x50u},
- {0x16u, 0x4Fu},
- {0x17u, 0xA0u},
- {0x19u, 0x05u},
+ {0xE2u, 0x68u},
+ {0xE4u, 0x09u},
+ {0xE6u, 0x06u},
+ {0xE8u, 0x09u},
+ {0xEAu, 0x04u},
+ {0xEEu, 0x13u},
+ {0x00u, 0x44u},
+ {0x02u, 0x88u},
+ {0x09u, 0x03u},
+ {0x0Du, 0x13u},
+ {0x0Fu, 0x44u},
+ {0x10u, 0x99u},
+ {0x11u, 0x6Cu},
+ {0x12u, 0x22u},
+ {0x13u, 0x13u},
+ {0x17u, 0x7Fu},
+ {0x19u, 0x08u},
{0x1Au, 0x70u},
- {0x1Bu, 0x0Au},
- {0x1Cu, 0x80u},
- {0x1Du, 0x06u},
- {0x1Fu, 0x09u},
- {0x20u, 0x05u},
- {0x22u, 0x0Au},
- {0x24u, 0x80u},
- {0x25u, 0x30u},
- {0x27u, 0xC0u},
- {0x28u, 0x06u},
- {0x2Au, 0x09u},
- {0x2Bu, 0xFFu},
- {0x2Cu, 0x40u},
- {0x2Du, 0x60u},
- {0x2Eu, 0x1Fu},
- {0x2Fu, 0x90u},
- {0x31u, 0xFFu},
- {0x32u, 0x80u},
- {0x34u, 0x7Fu},
- {0x38u, 0x08u},
- {0x3Eu, 0x04u},
- {0x3Fu, 0x01u},
- {0x54u, 0x01u},
+ {0x1Eu, 0x07u},
+ {0x1Fu, 0x02u},
+ {0x21u, 0x71u},
+ {0x24u, 0xAAu},
+ {0x26u, 0x55u},
+ {0x2Au, 0x08u},
+ {0x2Bu, 0x20u},
+ {0x2Du, 0x0Cu},
+ {0x2Eu, 0x80u},
+ {0x2Fu, 0x30u},
+ {0x34u, 0xF0u},
+ {0x35u, 0x7Fu},
+ {0x36u, 0x0Fu},
+ {0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x01u},
- {0x5Du, 0x10u},
+ {0x5Cu, 0x11u},
+ {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x82u, 0x08u},
- {0x85u, 0xFFu},
- {0x89u, 0x55u},
- {0x8Bu, 0xAAu},
- {0x8Eu, 0x01u},
- {0x8Fu, 0xFFu},
- {0x91u, 0xFFu},
- {0x95u, 0x33u},
- {0x97u, 0xCCu},
- {0x9Du, 0x0Fu},
- {0x9Fu, 0xF0u},
- {0xA3u, 0xFFu},
- {0xA5u, 0x69u},
- {0xA6u, 0x04u},
- {0xA7u, 0x96u},
- {0xAEu, 0x02u},
- {0xAFu, 0xFFu},
- {0xB0u, 0x04u},
- {0xB1u, 0xFFu},
- {0xB2u, 0x08u},
- {0xB4u, 0x01u},
- {0xB6u, 0x02u},
- {0xBBu, 0x02u},
- {0xD6u, 0x08u},
+ {0x81u, 0x6Cu},
+ {0x85u, 0x64u},
+ {0x87u, 0x08u},
+ {0x88u, 0xFFu},
+ {0x8Cu, 0x06u},
+ {0x8Eu, 0x09u},
+ {0x91u, 0x6Cu},
+ {0x92u, 0xFFu},
+ {0x94u, 0x0Fu},
+ {0x95u, 0x71u},
+ {0x96u, 0xF0u},
+ {0x97u, 0x82u},
+ {0x99u, 0xC0u},
+ {0x9Au, 0xFFu},
+ {0x9Bu, 0x2Fu},
+ {0x9Cu, 0x50u},
+ {0x9Du, 0xA4u},
+ {0x9Eu, 0xA0u},
+ {0x9Fu, 0x40u},
+ {0xA0u, 0x03u},
+ {0xA1u, 0x08u},
+ {0xA2u, 0x0Cu},
+ {0xA3u, 0x10u},
+ {0xA4u, 0x60u},
+ {0xA5u, 0x91u},
+ {0xA6u, 0x90u},
+ {0xA7u, 0x4Eu},
+ {0xA8u, 0x05u},
+ {0xA9u, 0x40u},
+ {0xAAu, 0x0Au},
+ {0xABu, 0x2Cu},
+ {0xACu, 0x30u},
+ {0xADu, 0x2Cu},
+ {0xAEu, 0xC0u},
+ {0xAFu, 0x40u},
+ {0xB1u, 0xC0u},
+ {0xB3u, 0x31u},
+ {0xB4u, 0xFFu},
+ {0xB5u, 0x0Fu},
+ {0xBBu, 0x0Eu},
+ {0xBEu, 0x10u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
- {0xDBu, 0x04u},
- {0xDCu, 0x19u},
- {0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x10u},
- {0x01u, 0x84u},
- {0x02u, 0x10u},
- {0x03u, 0x40u},
- {0x05u, 0x41u},
- {0x09u, 0x0Au},
- {0x0Au, 0x0Au},
- {0x10u, 0x10u},
- {0x11u, 0x02u},
- {0x12u, 0x09u},
- {0x14u, 0x02u},
- {0x16u, 0x20u},
- {0x1Au, 0x28u},
- {0x1Du, 0x41u},
- {0x1Eu, 0x08u},
- {0x1Fu, 0x08u},
- {0x22u, 0x01u},
- {0x27u, 0x40u},
- {0x2Au, 0x54u},
+ {0x03u, 0x80u},
+ {0x06u, 0x08u},
+ {0x07u, 0x02u},
+ {0x08u, 0x01u},
+ {0x0Au, 0x4Au},
+ {0x0Du, 0x18u},
+ {0x0Eu, 0x82u},
+ {0x12u, 0x20u},
+ {0x13u, 0x60u},
+ {0x15u, 0x15u},
+ {0x16u, 0x01u},
+ {0x1Au, 0x0Au},
+ {0x1Bu, 0x60u},
+ {0x1Du, 0x10u},
+ {0x21u, 0x20u},
+ {0x22u, 0x20u},
+ {0x25u, 0x10u},
+ {0x26u, 0x08u},
+ {0x27u, 0x58u},
+ {0x28u, 0xC1u},
+ {0x2Au, 0x20u},
+ {0x2Cu, 0x02u},
{0x2Du, 0x08u},
- {0x2Eu, 0x82u},
- {0x30u, 0x82u},
- {0x31u, 0x20u},
- {0x33u, 0x04u},
- {0x36u, 0x02u},
- {0x37u, 0x48u},
- {0x38u, 0x04u},
+ {0x2Fu, 0x48u},
+ {0x30u, 0x24u},
+ {0x31u, 0x01u},
+ {0x32u, 0x80u},
+ {0x37u, 0x59u},
+ {0x38u, 0x20u},
{0x39u, 0xA0u},
- {0x3Bu, 0x80u},
- {0x3Fu, 0xA4u},
- {0x58u, 0x40u},
- {0x5Eu, 0x10u},
- {0x5Fu, 0x40u},
- {0x64u, 0x02u},
- {0x66u, 0x20u},
+ {0x3Du, 0x02u},
+ {0x3Eu, 0x04u},
+ {0x41u, 0x40u},
+ {0x43u, 0x80u},
+ {0x58u, 0x10u},
+ {0x59u, 0x84u},
+ {0x5Au, 0x01u},
+ {0x60u, 0x08u},
+ {0x62u, 0x06u},
+ {0x63u, 0x01u},
+ {0x65u, 0x40u},
{0x67u, 0x02u},
- {0x81u, 0x10u},
- {0x83u, 0x04u},
- {0x85u, 0x08u},
- {0x87u, 0x04u},
- {0x8Eu, 0x04u},
- {0x90u, 0x14u},
- {0x91u, 0x24u},
- {0x92u, 0x10u},
- {0x95u, 0x02u},
- {0x97u, 0x86u},
- {0x98u, 0x10u},
- {0x9Au, 0x03u},
+ {0x81u, 0x25u},
+ {0x83u, 0x20u},
+ {0x84u, 0x10u},
+ {0x86u, 0x02u},
+ {0x89u, 0x01u},
+ {0x8Fu, 0x41u},
+ {0x90u, 0xA8u},
+ {0x91u, 0x5Au},
+ {0x92u, 0x01u},
+ {0x93u, 0x46u},
+ {0x94u, 0x40u},
+ {0x95u, 0x01u},
+ {0x96u, 0x60u},
+ {0x97u, 0x01u},
+ {0x99u, 0x20u},
+ {0x9Au, 0x28u},
+ {0x9Bu, 0x20u},
{0x9Cu, 0x0Cu},
- {0x9Du, 0x51u},
- {0x9Eu, 0xE4u},
- {0x9Fu, 0x05u},
- {0xA0u, 0x82u},
- {0xA1u, 0x01u},
- {0xA2u, 0x0Au},
- {0xA3u, 0x50u},
- {0xA5u, 0x20u},
- {0xA6u, 0x04u},
- {0xA7u, 0x08u},
- {0xABu, 0x40u},
- {0xADu, 0x04u},
+ {0x9Du, 0x08u},
+ {0x9Eu, 0x85u},
+ {0xA0u, 0xE0u},
+ {0xA1u, 0x84u},
+ {0xA2u, 0xC0u},
+ {0xA3u, 0x80u},
+ {0xA4u, 0x04u},
+ {0xA5u, 0x38u},
+ {0xA6u, 0x0Au},
+ {0xA7u, 0x70u},
+ {0xAAu, 0x20u},
+ {0xABu, 0x10u},
+ {0xAEu, 0x50u},
+ {0xB0u, 0x01u},
+ {0xB1u, 0x02u},
+ {0xB2u, 0x01u},
+ {0xB4u, 0x08u},
{0xB5u, 0x80u},
- {0xC0u, 0x9Fu},
- {0xC2u, 0x0Fu},
- {0xC4u, 0xAFu},
- {0xCAu, 0xDEu},
- {0xCCu, 0xDFu},
- {0xCEu, 0x7Eu},
- {0xD6u, 0x38u},
- {0xD8u, 0x30u},
- {0xE2u, 0x03u},
- {0xE6u, 0x0Du},
- {0xEAu, 0x09u},
- {0xECu, 0x40u},
- {0xEEu, 0x01u},
- {0x81u, 0x08u},
- {0x88u, 0x04u},
- {0x90u, 0x04u},
- {0x91u, 0x20u},
- {0x95u, 0x80u},
- {0x9Cu, 0x0Cu},
- {0x9Du, 0x88u},
- {0xA0u, 0x82u},
- {0xAAu, 0x10u},
- {0xADu, 0x03u},
- {0xAEu, 0x80u},
- {0xAFu, 0x09u},
- {0xB0u, 0x40u},
- {0xB2u, 0x44u},
- {0xB3u, 0x40u},
- {0xB5u, 0x20u},
- {0xE2u, 0x01u},
- {0xE6u, 0x64u},
- {0xE8u, 0x20u},
- {0xEAu, 0x4Au},
- {0xECu, 0x04u},
- {0xEEu, 0x22u},
- {0x06u, 0x02u},
- {0x09u, 0x50u},
- {0x0Bu, 0xA0u},
- {0x0Cu, 0x08u},
- {0x11u, 0x30u},
- {0x13u, 0xC0u},
- {0x15u, 0x60u},
- {0x17u, 0x90u},
- {0x19u, 0x06u},
- {0x1Bu, 0x09u},
- {0x24u, 0x04u},
- {0x25u, 0x03u},
- {0x27u, 0x0Cu},
- {0x28u, 0x01u},
- {0x29u, 0x0Fu},
- {0x2Au, 0x02u},
- {0x2Bu, 0xF0u},
- {0x2Du, 0x05u},
- {0x2Eu, 0x01u},
- {0x2Fu, 0x0Au},
- {0x30u, 0x03u},
- {0x31u, 0xFFu},
- {0x34u, 0x08u},
- {0x36u, 0x04u},
- {0x3Eu, 0x11u},
- {0x3Fu, 0x01u},
+ {0xC0u, 0xC8u},
+ {0xC2u, 0xFBu},
+ {0xC4u, 0xF7u},
+ {0xCAu, 0xFDu},
+ {0xCCu, 0xFFu},
+ {0xCEu, 0xCCu},
+ {0xD6u, 0x0Fu},
+ {0xD8u, 0x0Fu},
+ {0xE0u, 0x06u},
+ {0xE2u, 0x08u},
+ {0xE4u, 0x04u},
+ {0xE6u, 0x03u},
+ {0xE8u, 0x0Au},
+ {0xEAu, 0x80u},
+ {0xECu, 0x01u},
+ {0xEEu, 0x14u},
+ {0x01u, 0x02u},
+ {0x03u, 0x05u},
+ {0x04u, 0x24u},
+ {0x06u, 0x83u},
+ {0x09u, 0x02u},
+ {0x0Au, 0x12u},
+ {0x0Bu, 0x01u},
+ {0x14u, 0xC0u},
+ {0x19u, 0x01u},
+ {0x1Au, 0x0Cu},
+ {0x1Bu, 0x02u},
+ {0x1Eu, 0x01u},
+ {0x24u, 0x21u},
+ {0x26u, 0x42u},
+ {0x28u, 0x48u},
+ {0x2Au, 0x23u},
+ {0x32u, 0xE0u},
+ {0x33u, 0x03u},
+ {0x34u, 0x0Fu},
+ {0x35u, 0x04u},
+ {0x36u, 0x10u},
+ {0x38u, 0x08u},
+ {0x3Bu, 0x08u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x09u},
+ {0x5Cu, 0x90u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x83u, 0x01u},
- {0x84u, 0x10u},
- {0x86u, 0x0Cu},
- {0x87u, 0x20u},
- {0x88u, 0x08u},
- {0x8Cu, 0x21u},
- {0x8Du, 0x04u},
- {0x8Eu, 0x1Eu},
- {0x8Fu, 0xA3u},
- {0x94u, 0x24u},
- {0x95u, 0xC8u},
+ {0x81u, 0x1Eu},
+ {0x84u, 0x20u},
+ {0x85u, 0x01u},
+ {0x86u, 0x02u},
+ {0x88u, 0x07u},
+ {0x8Bu, 0xE0u},
+ {0x8Du, 0x20u},
+ {0x8Eu, 0x40u},
+ {0x8Fu, 0x5Eu},
+ {0x91u, 0x01u},
+ {0x94u, 0x08u},
+ {0x95u, 0x0Au},
{0x96u, 0x10u},
- {0x97u, 0x03u},
- {0x98u, 0x11u},
- {0x9Au, 0x22u},
- {0x9Bu, 0x0Cu},
- {0x9Cu, 0x1Cu},
- {0x9Fu, 0x12u},
- {0xA0u, 0x1Cu},
- {0xA4u, 0x14u},
- {0xA6u, 0x08u},
- {0xA8u, 0x30u},
- {0xAAu, 0x0Fu},
- {0xACu, 0x0Cu},
- {0xADu, 0x01u},
- {0xAEu, 0x10u},
- {0xAFu, 0x62u},
- {0xB2u, 0x30u},
- {0xB3u, 0xE0u},
- {0xB4u, 0x0Fu},
- {0xB5u, 0x0Fu},
- {0xB6u, 0x0Fu},
- {0xB7u, 0x10u},
- {0xBAu, 0x08u},
- {0xD4u, 0x40u},
- {0xD6u, 0x04u},
+ {0x97u, 0x14u},
+ {0x99u, 0x40u},
+ {0x9Au, 0x07u},
+ {0x9Bu, 0x9Eu},
+ {0x9Cu, 0x01u},
+ {0x9Du, 0x01u},
+ {0x9Eu, 0x20u},
+ {0xA1u, 0x80u},
+ {0xA2u, 0x08u},
+ {0xA3u, 0x3Eu},
+ {0xA5u, 0x06u},
+ {0xA6u, 0x10u},
+ {0xA7u, 0x18u},
+ {0xA8u, 0x04u},
+ {0xA9u, 0x01u},
+ {0xAAu, 0x20u},
+ {0xADu, 0x0Cu},
+ {0xAFu, 0x12u},
+ {0xB0u, 0x20u},
+ {0xB2u, 0x07u},
+ {0xB3u, 0xFEu},
+ {0xB4u, 0x40u},
+ {0xB6u, 0x18u},
+ {0xB7u, 0x01u},
+ {0xB9u, 0x80u},
+ {0xBEu, 0x45u},
+ {0xBFu, 0x40u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
+ {0xDCu, 0x19u},
{0xDFu, 0x01u},
- {0x00u, 0x48u},
- {0x02u, 0x04u},
- {0x05u, 0x40u},
- {0x06u, 0x20u},
- {0x09u, 0x40u},
- {0x0Au, 0x28u},
- {0x10u, 0x10u},
- {0x11u, 0x41u},
+ {0x00u, 0x20u},
+ {0x01u, 0x48u},
+ {0x05u, 0x08u},
+ {0x06u, 0x04u},
+ {0x09u, 0x28u},
+ {0x0Au, 0x41u},
+ {0x0Bu, 0x50u},
+ {0x0Du, 0x20u},
+ {0x0Eu, 0x22u},
+ {0x11u, 0x04u},
{0x12u, 0x08u},
- {0x14u, 0x05u},
- {0x17u, 0x04u},
- {0x18u, 0x06u},
- {0x19u, 0x80u},
- {0x1Au, 0x28u},
- {0x1Fu, 0x92u},
- {0x20u, 0x01u},
- {0x21u, 0x14u},
- {0x22u, 0x20u},
- {0x24u, 0x80u},
- {0x26u, 0x01u},
- {0x29u, 0x80u},
- {0x2Cu, 0x05u},
- {0x2Fu, 0x20u},
- {0x32u, 0xA8u},
- {0x35u, 0x02u},
- {0x37u, 0x18u},
- {0x38u, 0x41u},
- {0x39u, 0x08u},
- {0x3Eu, 0x20u},
- {0x5Fu, 0x50u},
- {0x60u, 0x10u},
- {0x61u, 0x20u},
- {0x62u, 0x41u},
- {0x65u, 0x10u},
- {0x67u, 0x02u},
- {0x6Cu, 0x2Au},
- {0x6Du, 0x20u},
- {0x6Eu, 0x01u},
- {0x74u, 0x80u},
- {0x75u, 0x22u},
- {0x76u, 0x20u},
- {0x77u, 0x08u},
- {0x81u, 0x10u},
- {0x87u, 0x40u},
- {0x8Au, 0x05u},
- {0x8Eu, 0x01u},
- {0x94u, 0xC0u},
- {0x95u, 0x41u},
- {0x96u, 0x08u},
- {0x97u, 0x22u},
- {0x9Au, 0x90u},
- {0x9Bu, 0x55u},
- {0x9Cu, 0x14u},
- {0x9Du, 0x32u},
- {0xA2u, 0x14u},
- {0xA3u, 0x19u},
- {0xA4u, 0xAEu},
- {0xA5u, 0x44u},
- {0xA6u, 0x08u},
- {0xA7u, 0xE2u},
- {0xAAu, 0x20u},
- {0xADu, 0x04u},
- {0xAEu, 0x42u},
- {0xB0u, 0x02u},
- {0xB2u, 0x02u},
- {0xB3u, 0x04u},
- {0xB5u, 0x04u},
- {0xC0u, 0xA7u},
- {0xC2u, 0x07u},
- {0xC4u, 0xEFu},
- {0xCAu, 0x78u},
- {0xCCu, 0xEEu},
- {0xCEu, 0x2Bu},
- {0xD6u, 0x30u},
- {0xD8u, 0x3Fu},
- {0xE2u, 0x01u},
- {0xE6u, 0xE2u},
- {0xEAu, 0x40u},
- {0xECu, 0x05u},
- {0xEEu, 0xE0u},
{0x13u, 0x02u},
- {0x23u, 0x01u},
- {0x25u, 0x04u},
- {0x29u, 0x01u},
- {0x2Bu, 0x02u},
- {0x33u, 0x04u},
- {0x35u, 0x03u},
- {0x3Fu, 0x14u},
- {0x59u, 0x04u},
- {0x5Fu, 0x01u},
- {0x80u, 0x04u},
- {0x81u, 0x02u},
- {0x85u, 0x08u},
- {0x87u, 0x03u},
- {0x88u, 0x01u},
- {0x8Bu, 0x7Fu},
- {0x91u, 0x4Fu},
- {0x93u, 0x30u},
- {0x97u, 0x2Cu},
- {0x98u, 0x08u},
- {0x99u, 0x10u},
- {0x9Bu, 0x01u},
- {0x9Du, 0x37u},
- {0x9Fu, 0x40u},
- {0xA5u, 0x03u},
- {0xA8u, 0x02u},
+ {0x17u, 0x18u},
+ {0x1Au, 0x90u},
+ {0x1Bu, 0x50u},
+ {0x1Cu, 0x20u},
+ {0x1Du, 0x20u},
+ {0x1Eu, 0x22u},
+ {0x20u, 0x12u},
+ {0x25u, 0x10u},
+ {0x27u, 0x20u},
+ {0x29u, 0x10u},
+ {0x2Au, 0x08u},
+ {0x2Bu, 0x81u},
+ {0x31u, 0x84u},
+ {0x32u, 0x22u},
+ {0x37u, 0x20u},
+ {0x38u, 0x18u},
+ {0x3Au, 0x01u},
+ {0x3Bu, 0x40u},
+ {0x3Du, 0x20u},
+ {0x3Fu, 0x01u},
+ {0x59u, 0x62u},
+ {0x5Bu, 0x04u},
+ {0x5Du, 0x80u},
+ {0x62u, 0x80u},
+ {0x67u, 0x01u},
+ {0x81u, 0x80u},
+ {0x82u, 0x08u},
+ {0x83u, 0x20u},
+ {0x84u, 0x40u},
+ {0x8Au, 0x02u},
+ {0x8Bu, 0x01u},
+ {0x8Cu, 0x10u},
+ {0x8Eu, 0x50u},
+ {0x90u, 0x88u},
+ {0x91u, 0x4Cu},
+ {0x93u, 0x04u},
+ {0x94u, 0x40u},
+ {0x95u, 0x01u},
+ {0x96u, 0x64u},
+ {0x97u, 0x80u},
+ {0x98u, 0x44u},
+ {0x99u, 0x72u},
+ {0x9Bu, 0x5Au},
+ {0x9Du, 0x08u},
+ {0x9Eu, 0x80u},
+ {0x9Fu, 0x01u},
+ {0xA0u, 0xE0u},
+ {0xA1u, 0x8Cu},
+ {0xA2u, 0x28u},
+ {0xA3u, 0x80u},
+ {0xA4u, 0x02u},
+ {0xA5u, 0x01u},
+ {0xA7u, 0x18u},
+ {0xA9u, 0x10u},
+ {0xAAu, 0x01u},
+ {0xABu, 0x02u},
+ {0xACu, 0x84u},
{0xADu, 0x80u},
{0xB0u, 0x04u},
- {0xB1u, 0x70u},
- {0xB2u, 0x02u},
- {0xB3u, 0x80u},
- {0xB4u, 0x01u},
- {0xB6u, 0x08u},
- {0xB7u, 0x0Fu},
- {0xBEu, 0x55u},
- {0xBFu, 0x04u},
- {0xC0u, 0x24u},
- {0xC1u, 0x05u},
- {0xC2u, 0x60u},
- {0xC5u, 0xE2u},
- {0xC6u, 0xF0u},
- {0xC7u, 0xDCu},
- {0xC8u, 0x3Bu},
- {0xC9u, 0xFFu},
- {0xCAu, 0xFFu},
- {0xCBu, 0xFFu},
- {0xCFu, 0x2Cu},
- {0xD6u, 0x01u},
+ {0xB1u, 0x0Eu},
+ {0xB2u, 0x80u},
+ {0xB4u, 0x08u},
+ {0xB6u, 0x09u},
+ {0xC0u, 0x67u},
+ {0xC2u, 0xE7u},
+ {0xC4u, 0x6Eu},
+ {0xCAu, 0x0Fu},
+ {0xCCu, 0x2Fu},
+ {0xCEu, 0xAFu},
+ {0xD6u, 0x1Fu},
+ {0xD8u, 0x18u},
+ {0xE0u, 0x03u},
+ {0xE2u, 0x0Cu},
+ {0xE6u, 0x13u},
+ {0xE8u, 0x01u},
+ {0xEAu, 0x0Cu},
+ {0xEEu, 0x03u},
+ {0x01u, 0x40u},
+ {0x02u, 0xFFu},
+ {0x03u, 0x80u},
+ {0x04u, 0x50u},
+ {0x05u, 0x0Au},
+ {0x06u, 0xA0u},
+ {0x07u, 0x05u},
+ {0x08u, 0x09u},
+ {0x0Au, 0x06u},
+ {0x0Cu, 0x0Fu},
+ {0x0Eu, 0xF0u},
+ {0x10u, 0x90u},
+ {0x11u, 0x30u},
+ {0x12u, 0x60u},
+ {0x13u, 0xC0u},
+ {0x14u, 0x05u},
+ {0x15u, 0x04u},
+ {0x16u, 0x0Au},
+ {0x17u, 0x08u},
+ {0x1Au, 0xFFu},
+ {0x1Bu, 0x07u},
+ {0x1Du, 0x20u},
+ {0x1Eu, 0xFFu},
+ {0x1Fu, 0x10u},
+ {0x21u, 0x80u},
+ {0x23u, 0x40u},
+ {0x24u, 0x03u},
+ {0x26u, 0x0Cu},
+ {0x27u, 0x08u},
+ {0x28u, 0x30u},
+ {0x29u, 0x10u},
+ {0x2Au, 0xC0u},
+ {0x2Bu, 0x20u},
+ {0x2Du, 0x09u},
+ {0x2Fu, 0x02u},
+ {0x30u, 0xFFu},
+ {0x31u, 0xF0u},
+ {0x35u, 0x0Fu},
+ {0x3Eu, 0x01u},
+ {0x3Fu, 0x01u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x10u},
+ {0x5Fu, 0x01u},
+ {0x80u, 0x0Fu},
+ {0x82u, 0xF0u},
+ {0x85u, 0x04u},
+ {0x86u, 0xFFu},
+ {0x8Fu, 0x08u},
+ {0x91u, 0x09u},
+ {0x93u, 0x12u},
+ {0x94u, 0xFFu},
+ {0x97u, 0x01u},
+ {0x98u, 0x55u},
+ {0x9Au, 0xAAu},
+ {0x9Cu, 0xFFu},
+ {0xA0u, 0x96u},
+ {0xA2u, 0x69u},
+ {0xA3u, 0x10u},
+ {0xA4u, 0x33u},
+ {0xA6u, 0xCCu},
+ {0xA7u, 0x02u},
+ {0xAAu, 0xFFu},
+ {0xAEu, 0xFFu},
+ {0xB1u, 0x18u},
+ {0xB3u, 0x04u},
+ {0xB5u, 0x03u},
+ {0xB6u, 0xFFu},
+ {0xBAu, 0x80u},
+ {0xBFu, 0x11u},
+ {0xD4u, 0x01u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
- {0xDAu, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x10u},
- {0xDDu, 0x01u},
+ {0xDCu, 0x91u},
+ {0xDDu, 0x10u},
{0xDFu, 0x01u},
- {0xE2u, 0xC0u},
- {0xE6u, 0x80u},
- {0xE8u, 0x40u},
- {0xE9u, 0x40u},
- {0xEEu, 0x08u},
- {0x05u, 0x10u},
- {0x06u, 0x40u},
- {0x0Au, 0x80u},
- {0x0Bu, 0x40u},
- {0x0Fu, 0x08u},
- {0x11u, 0x08u},
- {0x13u, 0x04u},
- {0x14u, 0x08u},
- {0x1Cu, 0x04u},
- {0x1Du, 0x40u},
- {0x1Eu, 0x80u},
- {0x1Fu, 0x04u},
- {0x20u, 0x10u},
- {0x22u, 0x20u},
- {0x25u, 0x08u},
- {0x26u, 0x02u},
- {0x27u, 0x41u},
- {0x28u, 0x04u},
+ {0x00u, 0x04u},
+ {0x02u, 0x20u},
+ {0x03u, 0x80u},
+ {0x04u, 0x18u},
+ {0x05u, 0x05u},
+ {0x07u, 0x01u},
+ {0x09u, 0x04u},
+ {0x0Au, 0x06u},
+ {0x0Cu, 0x20u},
+ {0x0Eu, 0x62u},
+ {0x10u, 0x42u},
+ {0x12u, 0x18u},
+ {0x17u, 0x18u},
+ {0x1Bu, 0x80u},
+ {0x1Cu, 0x80u},
+ {0x21u, 0x14u},
+ {0x22u, 0x02u},
+ {0x26u, 0x11u},
+ {0x27u, 0x04u},
{0x29u, 0x04u},
- {0x2Bu, 0x40u},
- {0x2Eu, 0x48u},
- {0x2Fu, 0x01u},
- {0x30u, 0x02u},
- {0x36u, 0x14u},
- {0x37u, 0x41u},
- {0x3Du, 0x02u},
- {0x3Eu, 0x04u},
- {0x3Fu, 0x20u},
- {0x45u, 0x28u},
- {0x46u, 0x20u},
- {0x47u, 0x01u},
- {0x4Cu, 0x14u},
- {0x4Du, 0x08u},
- {0x4Eu, 0x42u},
- {0x55u, 0x11u},
- {0x56u, 0x0Cu},
- {0x5Cu, 0x14u},
- {0x5Eu, 0x82u},
- {0x65u, 0x40u},
- {0x66u, 0x22u},
- {0x67u, 0x20u},
- {0x6Cu, 0x01u},
- {0x6Du, 0x04u},
- {0x6Eu, 0x01u},
- {0x6Fu, 0x08u},
- {0x74u, 0x10u},
- {0x76u, 0x91u},
- {0x80u, 0x09u},
- {0x82u, 0x40u},
- {0x87u, 0x81u},
+ {0x2Au, 0x02u},
+ {0x2Cu, 0x9Au},
+ {0x33u, 0x05u},
+ {0x35u, 0x40u},
+ {0x36u, 0x18u},
+ {0x37u, 0x01u},
+ {0x38u, 0x84u},
+ {0x3Du, 0x08u},
+ {0x3Eu, 0x02u},
+ {0x58u, 0x80u},
+ {0x5Cu, 0x02u},
+ {0x5Du, 0x04u},
+ {0x5Eu, 0x10u},
+ {0x5Fu, 0x40u},
+ {0x67u, 0x02u},
+ {0x6Fu, 0x01u},
+ {0x82u, 0x10u},
+ {0x83u, 0x29u},
+ {0x84u, 0x20u},
{0x88u, 0x40u},
- {0x8Cu, 0x20u},
- {0x8Fu, 0x02u},
- {0x90u, 0x08u},
- {0x92u, 0x04u},
- {0x94u, 0xE0u},
- {0x95u, 0x41u},
- {0x96u, 0x49u},
- {0x97u, 0x44u},
- {0x98u, 0x08u},
- {0x99u, 0x04u},
- {0x9Au, 0x40u},
- {0x9Bu, 0x14u},
- {0x9Cu, 0x50u},
- {0x9Du, 0x2Au},
- {0x9Eu, 0x05u},
- {0x9Fu, 0x41u},
- {0xA1u, 0x20u},
- {0xA2u, 0x15u},
- {0xA3u, 0x15u},
- {0xA4u, 0xBEu},
- {0xA5u, 0x51u},
- {0xA6u, 0x08u},
- {0xA7u, 0x20u},
- {0xA9u, 0x10u},
- {0xABu, 0x40u},
- {0xAFu, 0x60u},
- {0xC0u, 0x50u},
- {0xC2u, 0x40u},
- {0xC4u, 0x40u},
- {0xCAu, 0x57u},
- {0xCCu, 0xF1u},
- {0xCEu, 0xE0u},
- {0xD0u, 0xA0u},
- {0xD2u, 0x30u},
- {0xD6u, 0xF0u},
- {0xD8u, 0xF0u},
- {0xE6u, 0x10u},
- {0xE8u, 0x04u},
- {0xEAu, 0x02u},
- {0xEEu, 0x01u},
- {0x05u, 0x10u},
- {0x06u, 0x70u},
- {0x0Au, 0x20u},
- {0x0Bu, 0x08u},
- {0x0Eu, 0x08u},
- {0x11u, 0x3Au},
- {0x13u, 0x45u},
- {0x15u, 0x10u},
- {0x16u, 0x07u},
- {0x17u, 0x60u},
- {0x18u, 0x94u},
- {0x1Au, 0x48u},
- {0x1Bu, 0x07u},
- {0x1Du, 0x29u},
- {0x1Fu, 0x52u},
- {0x20u, 0xEAu},
- {0x22u, 0x15u},
- {0x25u, 0x24u},
- {0x26u, 0x80u},
- {0x27u, 0x58u},
- {0x2Au, 0x80u},
- {0x2Bu, 0x10u},
- {0x2Cu, 0x99u},
- {0x2Du, 0x80u},
- {0x2Eu, 0x22u},
- {0x30u, 0x80u},
- {0x31u, 0x80u},
- {0x32u, 0x0Fu},
- {0x33u, 0x0Fu},
- {0x34u, 0x70u},
- {0x35u, 0x70u},
- {0x38u, 0x80u},
+ {0x8Bu, 0x80u},
+ {0x8Cu, 0x82u},
+ {0x90u, 0x1Cu},
+ {0x91u, 0x04u},
+ {0x92u, 0xC6u},
+ {0x93u, 0x40u},
+ {0x95u, 0x09u},
+ {0x96u, 0x01u},
+ {0x97u, 0x08u},
+ {0x98u, 0x50u},
+ {0x9Au, 0x12u},
+ {0x9Bu, 0x10u},
+ {0x9Cu, 0x01u},
+ {0x9Du, 0x08u},
+ {0x9Eu, 0x08u},
+ {0x9Fu, 0x01u},
+ {0xA0u, 0x90u},
+ {0xA1u, 0x04u},
+ {0xA2u, 0x08u},
+ {0xA3u, 0x28u},
+ {0xA6u, 0x17u},
+ {0xA8u, 0x10u},
+ {0xABu, 0x14u},
+ {0xAEu, 0x01u},
+ {0xB0u, 0x20u},
+ {0xB2u, 0x40u},
+ {0xB3u, 0x09u},
+ {0xB4u, 0x04u},
+ {0xB7u, 0x44u},
+ {0xC0u, 0xFCu},
+ {0xC2u, 0xF7u},
+ {0xC4u, 0x6Fu},
+ {0xCAu, 0xF3u},
+ {0xCCu, 0xF3u},
+ {0xCEu, 0xCAu},
+ {0xD6u, 0xF8u},
+ {0xD8u, 0x10u},
+ {0xE0u, 0x10u},
+ {0xE2u, 0x8Cu},
+ {0xE4u, 0x40u},
+ {0xE6u, 0x22u},
+ {0xE8u, 0x40u},
+ {0xEAu, 0x38u},
+ {0xECu, 0x40u},
+ {0xEEu, 0xA0u},
+ {0x03u, 0x08u},
+ {0x05u, 0x01u},
+ {0x07u, 0x02u},
+ {0x08u, 0x04u},
+ {0x0Au, 0x09u},
+ {0x0Du, 0x02u},
+ {0x0Fu, 0x01u},
+ {0x14u, 0x08u},
+ {0x16u, 0x04u},
+ {0x1Du, 0x02u},
+ {0x1Fu, 0x05u},
+ {0x20u, 0x08u},
+ {0x22u, 0x06u},
+ {0x2Cu, 0x01u},
+ {0x2Eu, 0x02u},
+ {0x31u, 0x04u},
+ {0x33u, 0x08u},
+ {0x34u, 0x0Cu},
+ {0x35u, 0x03u},
+ {0x36u, 0x03u},
+ {0x3Au, 0x20u},
{0x3Bu, 0x20u},
- {0x3Eu, 0x41u},
- {0x3Fu, 0x01u},
+ {0x3Eu, 0x40u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x11u},
+ {0x5Cu, 0x99u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x84u, 0x0Du},
- {0x8Cu, 0x32u},
- {0x8Eu, 0x44u},
- {0x90u, 0x40u},
- {0x92u, 0x30u},
- {0x94u, 0x02u},
- {0x96u, 0x0Du},
- {0x98u, 0x11u},
- {0x9Au, 0x62u},
- {0x9Bu, 0x01u},
- {0x9Cu, 0x0Du},
- {0x9Du, 0x05u},
- {0x9Fu, 0x0Au},
- {0xA0u, 0x0Du},
- {0xA3u, 0x08u},
- {0xA4u, 0x0Du},
- {0xA7u, 0x04u},
- {0xA8u, 0x52u},
- {0xAAu, 0x28u},
- {0xABu, 0x02u},
- {0xACu, 0x0Du},
- {0xB0u, 0x70u},
- {0xB1u, 0x0Cu},
- {0xB2u, 0x0Fu},
- {0xB3u, 0x03u},
- {0xBAu, 0x0Au},
- {0xBFu, 0x05u},
- {0xD6u, 0x08u},
+ {0x82u, 0x01u},
+ {0x84u, 0x34u},
+ {0x88u, 0x34u},
+ {0x89u, 0x04u},
+ {0x8Bu, 0x02u},
+ {0x8Cu, 0x01u},
+ {0x8Du, 0x02u},
+ {0x8Eu, 0x02u},
+ {0x8Fu, 0x04u},
+ {0x90u, 0x08u},
+ {0x91u, 0x08u},
+ {0x92u, 0x20u},
+ {0x93u, 0x10u},
+ {0x94u, 0x08u},
+ {0x96u, 0x34u},
+ {0x98u, 0x08u},
+ {0x9Au, 0x10u},
+ {0x9Cu, 0x34u},
+ {0xA0u, 0x34u},
+ {0xA3u, 0x10u},
+ {0xA4u, 0x04u},
+ {0xA6u, 0x08u},
+ {0xAAu, 0x02u},
+ {0xABu, 0x08u},
+ {0xACu, 0x34u},
+ {0xADu, 0x04u},
+ {0xAFu, 0x03u},
+ {0xB2u, 0x3Cu},
+ {0xB3u, 0x18u},
+ {0xB5u, 0x01u},
+ {0xB6u, 0x03u},
+ {0xB7u, 0x06u},
+ {0xBAu, 0x08u},
+ {0xBBu, 0x80u},
+ {0xBEu, 0x40u},
+ {0xBFu, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDDu, 0x90u},
+ {0xDCu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x48u},
- {0x04u, 0x24u},
- {0x06u, 0x21u},
- {0x09u, 0x40u},
- {0x0Au, 0xA8u},
- {0x0Eu, 0x18u},
- {0x10u, 0x10u},
- {0x11u, 0x41u},
- {0x12u, 0x08u},
- {0x15u, 0x04u},
- {0x16u, 0x04u},
- {0x17u, 0x41u},
- {0x1Au, 0xA0u},
- {0x1Bu, 0x01u},
- {0x1Du, 0x30u},
- {0x1Eu, 0x18u},
- {0x1Fu, 0x51u},
- {0x21u, 0x04u},
- {0x22u, 0x02u},
- {0x24u, 0x08u},
- {0x26u, 0x01u},
- {0x27u, 0x18u},
- {0x29u, 0x22u},
- {0x2Bu, 0x20u},
- {0x2Eu, 0xA0u},
- {0x2Fu, 0x10u},
+ {0x01u, 0x20u},
+ {0x05u, 0x09u},
+ {0x06u, 0x08u},
+ {0x07u, 0x01u},
+ {0x09u, 0x08u},
+ {0x0Eu, 0x19u},
+ {0x0Fu, 0x80u},
+ {0x10u, 0x02u},
+ {0x13u, 0x01u},
+ {0x14u, 0x01u},
+ {0x15u, 0x01u},
+ {0x17u, 0x24u},
+ {0x19u, 0x60u},
+ {0x1Au, 0x02u},
+ {0x1Bu, 0x20u},
+ {0x1Cu, 0x02u},
+ {0x1Eu, 0x10u},
+ {0x20u, 0x44u},
+ {0x21u, 0x08u},
+ {0x23u, 0x08u},
+ {0x24u, 0x20u},
+ {0x25u, 0x50u},
+ {0x2Cu, 0x80u},
+ {0x2Fu, 0x05u},
{0x32u, 0x80u},
- {0x33u, 0x10u},
- {0x37u, 0x59u},
- {0x3Cu, 0x20u},
- {0x3Du, 0x04u},
- {0x3Eu, 0x04u},
- {0x58u, 0x64u},
- {0x5Du, 0x80u},
- {0x5Fu, 0x20u},
- {0x61u, 0x04u},
- {0x62u, 0x40u},
- {0x63u, 0x08u},
- {0x64u, 0x08u},
- {0x66u, 0x80u},
- {0x80u, 0x08u},
- {0x81u, 0x24u},
- {0x83u, 0x04u},
- {0x84u, 0x04u},
- {0x86u, 0x02u},
- {0x88u, 0x20u},
- {0x89u, 0x06u},
- {0x8Au, 0x40u},
- {0x8Du, 0x80u},
- {0x90u, 0x04u},
- {0x92u, 0x04u},
- {0x94u, 0x80u},
- {0x96u, 0x51u},
- {0x97u, 0x46u},
- {0x9Du, 0x18u},
- {0x9Eu, 0x84u},
- {0x9Fu, 0x41u},
- {0xA2u, 0xD0u},
- {0xA3u, 0x50u},
- {0xA4u, 0xAAu},
- {0xA5u, 0x13u},
- {0xA6u, 0x04u},
+ {0x34u, 0x02u},
+ {0x37u, 0x01u},
+ {0x38u, 0x44u},
+ {0x3Bu, 0x01u},
+ {0x3Du, 0xA0u},
+ {0x3Fu, 0x40u},
+ {0x58u, 0x20u},
+ {0x5Bu, 0x40u},
+ {0x62u, 0x10u},
+ {0x63u, 0x01u},
+ {0x68u, 0x02u},
+ {0x6Cu, 0x84u},
+ {0x6Eu, 0xC0u},
+ {0x6Fu, 0x10u},
+ {0x74u, 0x10u},
+ {0x76u, 0x42u},
+ {0x77u, 0x20u},
+ {0x81u, 0x04u},
+ {0x82u, 0x30u},
+ {0x84u, 0x01u},
+ {0x85u, 0x04u},
+ {0x86u, 0x04u},
+ {0x89u, 0x04u},
+ {0x8Au, 0x02u},
+ {0x8Cu, 0x20u},
+ {0x8Du, 0x01u},
+ {0x8Fu, 0x40u},
+ {0x90u, 0x10u},
+ {0x92u, 0x80u},
+ {0x93u, 0x02u},
+ {0x94u, 0x2Cu},
+ {0x96u, 0x60u},
+ {0x98u, 0x50u},
+ {0x9Cu, 0x02u},
+ {0x9Du, 0x40u},
+ {0x9Eu, 0x60u},
+ {0x9Fu, 0x28u},
+ {0xA2u, 0x88u},
+ {0xA3u, 0x08u},
+ {0xA4u, 0x20u},
+ {0xA5u, 0x04u},
+ {0xA6u, 0x11u},
{0xA7u, 0x04u},
- {0xA9u, 0x08u},
- {0xAAu, 0x20u},
- {0xABu, 0x10u},
- {0xAEu, 0x40u},
- {0xAFu, 0x80u},
- {0xB0u, 0x04u},
- {0xB2u, 0x16u},
- {0xC0u, 0xE5u},
- {0xC2u, 0x6Fu},
- {0xC4u, 0xFFu},
- {0xCAu, 0x77u},
- {0xCCu, 0xFCu},
- {0xCEu, 0x60u},
- {0xD6u, 0x3Eu},
- {0xD8u, 0x3Eu},
- {0xE0u, 0x02u},
- {0xE2u, 0x28u},
- {0xE4u, 0x20u},
- {0xE6u, 0x10u},
- {0xE8u, 0x80u},
- {0xEAu, 0x22u},
- {0xECu, 0x20u},
- {0x00u, 0x20u},
- {0x02u, 0x10u},
- {0x03u, 0xFFu},
- {0x04u, 0x20u},
- {0x05u, 0x05u},
- {0x06u, 0x10u},
- {0x07u, 0x0Au},
- {0x0Au, 0x04u},
- {0x0Bu, 0xFFu},
- {0x0Fu, 0xFFu},
- {0x10u, 0x20u},
- {0x11u, 0x90u},
- {0x12u, 0x10u},
- {0x13u, 0x60u},
- {0x15u, 0x50u},
- {0x16u, 0x01u},
- {0x17u, 0xA0u},
- {0x18u, 0x10u},
- {0x19u, 0x30u},
- {0x1Au, 0x20u},
+ {0xA8u, 0x10u},
+ {0xAFu, 0x41u},
+ {0xB2u, 0x14u},
+ {0xB3u, 0x40u},
+ {0xB6u, 0x08u},
+ {0xB7u, 0x12u},
+ {0xC0u, 0xF2u},
+ {0xC2u, 0xF4u},
+ {0xC4u, 0xF9u},
+ {0xCAu, 0xB0u},
+ {0xCCu, 0x88u},
+ {0xCEu, 0x3Bu},
+ {0xD6u, 0x0Cu},
+ {0xD8u, 0x0Cu},
+ {0xE0u, 0x20u},
+ {0xE4u, 0x58u},
+ {0xE6u, 0x03u},
+ {0xE8u, 0x04u},
+ {0xECu, 0x61u},
+ {0xEEu, 0x84u},
+ {0x01u, 0x01u},
+ {0x03u, 0x02u},
+ {0x04u, 0xFFu},
+ {0x07u, 0x27u},
+ {0x0Cu, 0xFFu},
+ {0x0Du, 0x48u},
+ {0x0Fu, 0xB6u},
+ {0x11u, 0x07u},
+ {0x13u, 0x18u},
+ {0x14u, 0x0Fu},
+ {0x15u, 0x01u},
+ {0x16u, 0xF0u},
+ {0x18u, 0x69u},
+ {0x19u, 0x20u},
+ {0x1Au, 0x96u},
{0x1Bu, 0xC0u},
- {0x1Cu, 0x05u},
- {0x1Eu, 0x0Au},
- {0x21u, 0x0Fu},
- {0x22u, 0x02u},
- {0x23u, 0xF0u},
- {0x25u, 0x09u},
- {0x26u, 0x08u},
- {0x27u, 0x06u},
- {0x29u, 0x03u},
- {0x2Bu, 0x0Cu},
- {0x2Cu, 0x20u},
- {0x2Eu, 0x10u},
- {0x32u, 0x0Cu},
- {0x34u, 0x30u},
- {0x35u, 0xFFu},
- {0x36u, 0x03u},
- {0x3Au, 0x20u},
- {0x3Eu, 0x44u},
- {0x3Fu, 0x10u},
+ {0x1Cu, 0x55u},
+ {0x1Du, 0x20u},
+ {0x1Eu, 0xAAu},
+ {0x1Fu, 0x07u},
+ {0x20u, 0x33u},
+ {0x22u, 0xCCu},
+ {0x23u, 0x04u},
+ {0x26u, 0xFFu},
+ {0x29u, 0x6Cu},
+ {0x2Au, 0xFFu},
+ {0x2Bu, 0x93u},
+ {0x2Du, 0x4Fu},
+ {0x2Eu, 0xFFu},
+ {0x2Fu, 0xB0u},
+ {0x32u, 0xFFu},
+ {0x35u, 0xE0u},
+ {0x37u, 0x1Fu},
+ {0x3Au, 0x08u},
+ {0x3Bu, 0xA0u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x09u},
+ {0x5Cu, 0x11u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x80u, 0x59u},
- {0x82u, 0xA2u},
- {0x85u, 0x55u},
- {0x86u, 0x20u},
- {0x87u, 0xAAu},
- {0x8Au, 0x30u},
- {0x8Bu, 0xFFu},
- {0x8Du, 0x69u},
- {0x8Fu, 0x96u},
- {0x90u, 0x30u},
- {0x91u, 0xFFu},
- {0x92u, 0xC0u},
- {0x95u, 0x0Fu},
- {0x96u, 0x07u},
- {0x97u, 0xF0u},
- {0x98u, 0x74u},
- {0x9Au, 0x88u},
- {0x9Bu, 0xFFu},
- {0x9Eu, 0x08u},
- {0x9Fu, 0xFFu},
- {0xA0u, 0x6Au},
- {0xA2u, 0x95u},
- {0xA5u, 0xFFu},
- {0xACu, 0x10u},
- {0xADu, 0x33u},
- {0xAFu, 0xCCu},
- {0xB0u, 0xF0u},
+ {0x81u, 0x0Fu},
+ {0x83u, 0xF0u},
+ {0x86u, 0x07u},
+ {0x87u, 0xFFu},
+ {0x88u, 0x04u},
+ {0x89u, 0xFFu},
+ {0x8Au, 0x08u},
+ {0x8Du, 0x33u},
+ {0x8Fu, 0xCCu},
+ {0x90u, 0x10u},
+ {0x92u, 0x20u},
+ {0x96u, 0x10u},
+ {0x97u, 0xFFu},
+ {0x99u, 0x69u},
+ {0x9Bu, 0x96u},
+ {0x9Du, 0xFFu},
+ {0xA2u, 0x20u},
+ {0xA3u, 0xFFu},
+ {0xA4u, 0x0Au},
+ {0xA6u, 0x05u},
+ {0xA9u, 0x55u},
+ {0xAAu, 0x08u},
+ {0xABu, 0xAAu},
+ {0xACu, 0x09u},
+ {0xAEu, 0x02u},
{0xB2u, 0x0Fu},
- {0xB5u, 0xFFu},
- {0xBAu, 0x02u},
- {0xBBu, 0x20u},
+ {0xB4u, 0x30u},
+ {0xB7u, 0xFFu},
+ {0xBBu, 0x80u},
+ {0xBEu, 0x10u},
+ {0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
{0xDCu, 0x11u},
+ {0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x01u},
- {0x03u, 0x18u},
- {0x05u, 0x28u},
- {0x07u, 0x40u},
- {0x08u, 0x40u},
- {0x09u, 0x02u},
- {0x0Au, 0x18u},
- {0x0Bu, 0x10u},
- {0x0Du, 0x08u},
- {0x0Eu, 0x89u},
- {0x10u, 0xA0u},
- {0x12u, 0x01u},
- {0x14u, 0x08u},
- {0x16u, 0x06u},
- {0x17u, 0x01u},
- {0x18u, 0x04u},
- {0x19u, 0x20u},
- {0x1Au, 0x28u},
- {0x1Bu, 0x70u},
+ {0x01u, 0x08u},
+ {0x02u, 0x08u},
+ {0x05u, 0x40u},
+ {0x06u, 0x20u},
+ {0x08u, 0x02u},
+ {0x0Au, 0x20u},
+ {0x0Du, 0x48u},
+ {0x0Fu, 0x08u},
+ {0x11u, 0x18u},
+ {0x12u, 0x41u},
+ {0x16u, 0x01u},
+ {0x17u, 0x19u},
+ {0x18u, 0x10u},
+ {0x19u, 0x08u},
+ {0x1Au, 0x08u},
{0x1Du, 0x08u},
- {0x1Eu, 0x80u},
- {0x20u, 0x08u},
+ {0x1Fu, 0x08u},
+ {0x20u, 0x01u},
+ {0x22u, 0x40u},
{0x26u, 0x20u},
- {0x27u, 0x08u},
- {0x28u, 0x40u},
- {0x2Au, 0x08u},
- {0x2Bu, 0x08u},
- {0x2Eu, 0x84u},
- {0x30u, 0x2Au},
- {0x35u, 0x10u},
- {0x37u, 0x49u},
- {0x38u, 0x80u},
- {0x3Au, 0x12u},
- {0x3Bu, 0x04u},
- {0x3Du, 0x03u},
- {0x3Eu, 0x40u},
- {0x3Fu, 0x28u},
- {0x45u, 0x10u},
- {0x47u, 0x20u},
- {0x5Bu, 0x80u},
- {0x5Cu, 0x08u},
- {0x5Du, 0x01u},
- {0x5Fu, 0x60u},
- {0x62u, 0x40u},
+ {0x27u, 0x02u},
+ {0x2Au, 0x11u},
+ {0x2Du, 0x01u},
+ {0x2Eu, 0x20u},
+ {0x2Fu, 0x02u},
+ {0x30u, 0x20u},
+ {0x31u, 0x40u},
+ {0x32u, 0x08u},
+ {0x35u, 0x40u},
+ {0x36u, 0x24u},
+ {0x37u, 0x02u},
+ {0x38u, 0x05u},
+ {0x3Au, 0x20u},
+ {0x3Bu, 0x80u},
+ {0x3Cu, 0x04u},
+ {0x3Eu, 0x02u},
+ {0x3Fu, 0x80u},
+ {0x5Bu, 0x40u},
+ {0x5Eu, 0x10u},
+ {0x5Fu, 0x40u},
+ {0x62u, 0x80u},
+ {0x64u, 0x08u},
{0x67u, 0x02u},
- {0x82u, 0x19u},
- {0x88u, 0x40u},
- {0x8Au, 0x90u},
- {0x8Bu, 0x18u},
- {0x8Cu, 0x81u},
- {0x8Fu, 0x20u},
- {0xC0u, 0x7Eu},
- {0xC2u, 0xFFu},
- {0xC4u, 0x9Du},
- {0xCAu, 0x57u},
- {0xCCu, 0xF7u},
- {0xCEu, 0x7Fu},
- {0xD6u, 0xF8u},
- {0xD8u, 0x18u},
- {0xE0u, 0xA1u},
- {0xE2u, 0x50u},
- {0xE4u, 0x34u},
- {0xE6u, 0xC0u},
- {0xA9u, 0x80u},
- {0xE4u, 0x80u},
- {0xE6u, 0x02u},
- {0xEAu, 0x04u},
- {0xEEu, 0x20u},
+ {0x80u, 0x08u},
+ {0x81u, 0x40u},
+ {0x83u, 0x40u},
+ {0x84u, 0x40u},
+ {0x86u, 0x40u},
+ {0x8Bu, 0x22u},
+ {0x8Eu, 0x03u},
+ {0x8Fu, 0x40u},
+ {0x91u, 0x11u},
+ {0x92u, 0x10u},
+ {0x94u, 0x18u},
+ {0x96u, 0x40u},
+ {0x98u, 0x10u},
+ {0xA2u, 0x04u},
+ {0xA6u, 0x31u},
+ {0xAAu, 0x51u},
+ {0xADu, 0x01u},
+ {0xAEu, 0x20u},
+ {0xC0u, 0xA6u},
+ {0xC2u, 0xECu},
+ {0xC4u, 0xFFu},
+ {0xCAu, 0xB5u},
+ {0xCCu, 0xFEu},
+ {0xCEu, 0xDFu},
+ {0xD6u, 0x38u},
+ {0xD8u, 0x38u},
+ {0xE0u, 0x40u},
+ {0xE2u, 0x20u},
+ {0xE4u, 0x40u},
+ {0xE6u, 0x32u},
{0x80u, 0x04u},
- {0x84u, 0x08u},
- {0x88u, 0x02u},
+ {0x86u, 0x10u},
+ {0x88u, 0x10u},
{0x89u, 0x10u},
- {0x90u, 0x04u},
- {0x91u, 0x20u},
- {0x9Cu, 0x08u},
- {0x9Du, 0x80u},
- {0xA0u, 0x02u},
- {0xA8u, 0x80u},
- {0xA9u, 0x40u},
- {0xE0u, 0x04u},
- {0xE2u, 0x08u},
- {0xE6u, 0x08u},
- {0xE8u, 0x04u},
- {0xEAu, 0x01u},
- {0xEEu, 0x08u},
- {0x05u, 0x05u},
- {0x07u, 0x0Au},
- {0x09u, 0x50u},
- {0x0Bu, 0xA0u},
- {0x0Du, 0x06u},
- {0x0Fu, 0x09u},
- {0x13u, 0xFFu},
- {0x14u, 0x01u},
- {0x15u, 0x03u},
- {0x17u, 0x0Cu},
- {0x1Bu, 0xFFu},
- {0x1Du, 0xFFu},
- {0x25u, 0x30u},
- {0x27u, 0xC0u},
- {0x29u, 0x0Fu},
- {0x2Bu, 0xF0u},
- {0x2Du, 0x60u},
- {0x2Fu, 0x90u},
- {0x33u, 0xFFu},
- {0x34u, 0x01u},
- {0x3Fu, 0x04u},
- {0x56u, 0x08u},
- {0x58u, 0x04u},
- {0x59u, 0x04u},
- {0x5Bu, 0x04u},
- {0x5Cu, 0x09u},
- {0x5Du, 0x90u},
- {0x5Fu, 0x01u},
- {0x00u, 0x64u},
- {0x01u, 0x02u},
- {0x09u, 0x40u},
- {0x0Au, 0x21u},
- {0x0Bu, 0x84u},
- {0x0Fu, 0x20u},
- {0x10u, 0x18u},
- {0x11u, 0x45u},
- {0x18u, 0x10u},
- {0x19u, 0x20u},
- {0x1Au, 0x02u},
- {0x1Bu, 0x80u},
- {0x1Eu, 0x04u},
- {0x21u, 0x80u},
- {0x22u, 0x20u},
- {0x23u, 0x20u},
- {0x27u, 0x10u},
- {0x2Cu, 0x26u},
- {0x32u, 0x28u},
- {0x36u, 0x11u},
- {0x37u, 0x88u},
- {0x38u, 0x44u},
- {0x39u, 0x20u},
- {0x3Du, 0x28u},
- {0x3Fu, 0x80u},
- {0x40u, 0x04u},
- {0x42u, 0x20u},
- {0x43u, 0x80u},
- {0x48u, 0x40u},
- {0x49u, 0x06u},
- {0x4Au, 0x8Au},
- {0x51u, 0x20u},
- {0x52u, 0x44u},
- {0x53u, 0x40u},
- {0x5Fu, 0x40u},
- {0x63u, 0x02u},
- {0x65u, 0x40u},
- {0x68u, 0x0Cu},
- {0x69u, 0x55u},
- {0x72u, 0x01u},
- {0x83u, 0x08u},
- {0x85u, 0x44u},
- {0x88u, 0x04u},
- {0x8Bu, 0x82u},
- {0x90u, 0x06u},
- {0x91u, 0x28u},
- {0x92u, 0x20u},
- {0x94u, 0x50u},
- {0x95u, 0x41u},
- {0x96u, 0x04u},
- {0x9Au, 0x90u},
- {0x9Bu, 0x41u},
- {0x9Cu, 0x14u},
- {0x9Du, 0x40u},
- {0x9Eu, 0x44u},
- {0xA0u, 0x22u},
- {0xA1u, 0x10u},
- {0xA2u, 0x15u},
- {0xA3u, 0x59u},
- {0xA4u, 0x04u},
- {0xA5u, 0x6Cu},
- {0xA6u, 0x88u},
- {0xA7u, 0x20u},
- {0xA8u, 0x40u},
- {0xABu, 0x40u},
- {0xB0u, 0x01u},
- {0xB1u, 0x08u},
- {0xB3u, 0x10u},
- {0xC0u, 0x0Fu},
- {0xC2u, 0x2Fu},
- {0xC4u, 0x0Fu},
- {0xCAu, 0x70u},
- {0xCCu, 0xF6u},
- {0xCEu, 0x7Eu},
- {0xD0u, 0x0Eu},
- {0xD2u, 0x0Cu},
- {0xD6u, 0x10u},
- {0xD8u, 0x18u},
- {0xE4u, 0xA0u},
- {0xEEu, 0x08u},
- {0x00u, 0xC0u},
- {0x01u, 0x77u},
- {0x02u, 0x02u},
- {0x03u, 0x80u},
- {0x04u, 0x1Fu},
- {0x05u, 0x24u},
- {0x06u, 0x20u},
- {0x07u, 0x40u},
- {0x08u, 0x7Fu},
- {0x0Au, 0x80u},
- {0x0Bu, 0x64u},
- {0x0Du, 0x64u},
- {0x0Eu, 0x9Fu},
- {0x11u, 0x93u},
- {0x12u, 0xFFu},
- {0x13u, 0x60u},
- {0x14u, 0x80u},
- {0x15u, 0x10u},
- {0x17u, 0xE5u},
- {0x19u, 0x24u},
- {0x1Au, 0x60u},
- {0x1Cu, 0xC0u},
- {0x1Du, 0x64u},
- {0x1Eu, 0x01u},
- {0x21u, 0x08u},
- {0x24u, 0xC0u},
- {0x25u, 0x40u},
- {0x26u, 0x04u},
- {0x27u, 0x02u},
- {0x28u, 0xC0u},
- {0x29u, 0x08u},
- {0x2Au, 0x08u},
- {0x2Cu, 0x90u},
- {0x2Du, 0x64u},
- {0x2Eu, 0x40u},
- {0x30u, 0xFFu},
- {0x31u, 0xF0u},
- {0x33u, 0x07u},
- {0x35u, 0x08u},
- {0x37u, 0x80u},
- {0x39u, 0x22u},
- {0x3Bu, 0x0Cu},
- {0x3Eu, 0x01u},
- {0x3Fu, 0x40u},
- {0x54u, 0x09u},
- {0x56u, 0x04u},
+ {0x8Cu, 0x10u},
+ {0x8Eu, 0x04u},
+ {0xE0u, 0xE0u},
+ {0xE2u, 0x12u},
+ {0x80u, 0x01u},
+ {0x84u, 0x08u},
+ {0x86u, 0x21u},
+ {0x8Cu, 0x01u},
+ {0x90u, 0x01u},
+ {0x94u, 0x10u},
+ {0x98u, 0x01u},
+ {0x99u, 0x01u},
+ {0x9Cu, 0x04u},
+ {0xA0u, 0x01u},
+ {0xA4u, 0x07u},
+ {0xA5u, 0x01u},
+ {0xA6u, 0x18u},
+ {0xA8u, 0x22u},
+ {0xAAu, 0x08u},
+ {0xB1u, 0x01u},
+ {0xB4u, 0x3Fu},
+ {0xB8u, 0x20u},
+ {0xB9u, 0x02u},
+ {0xBEu, 0x10u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDFu, 0x01u},
+ {0x01u, 0x04u},
+ {0x02u, 0x08u},
+ {0x03u, 0x41u},
+ {0x05u, 0x08u},
+ {0x07u, 0x41u},
+ {0x09u, 0x91u},
+ {0x0Au, 0x10u},
+ {0x0Cu, 0x0Au},
+ {0x0Eu, 0x06u},
+ {0x10u, 0x82u},
+ {0x13u, 0x08u},
+ {0x15u, 0x01u},
+ {0x17u, 0x18u},
+ {0x19u, 0x08u},
+ {0x1Au, 0x11u},
+ {0x1Bu, 0x10u},
+ {0x1Fu, 0x20u},
+ {0x20u, 0x04u},
+ {0x21u, 0x18u},
+ {0x26u, 0x03u},
+ {0x29u, 0x02u},
+ {0x2Fu, 0x20u},
+ {0x31u, 0x08u},
+ {0x32u, 0x20u},
+ {0x33u, 0x80u},
+ {0x37u, 0x20u},
+ {0x38u, 0x80u},
+ {0x39u, 0x28u},
+ {0x42u, 0x91u},
+ {0x43u, 0x10u},
+ {0x48u, 0x80u},
+ {0x49u, 0x04u},
+ {0x4Au, 0x04u},
+ {0x4Bu, 0x01u},
+ {0x50u, 0x08u},
+ {0x51u, 0x80u},
+ {0x52u, 0x14u},
+ {0x53u, 0x44u},
+ {0x62u, 0x11u},
+ {0x63u, 0x21u},
+ {0x81u, 0x08u},
+ {0x82u, 0x80u},
+ {0x88u, 0x10u},
+ {0x89u, 0x80u},
+ {0x8Cu, 0x04u},
+ {0x8Du, 0x08u},
+ {0x90u, 0x80u},
+ {0x91u, 0x0Du},
+ {0x92u, 0x04u},
+ {0x96u, 0x01u},
+ {0x97u, 0x88u},
+ {0x99u, 0x02u},
+ {0x9Bu, 0x79u},
+ {0x9Cu, 0x10u},
+ {0x9Du, 0x0Cu},
+ {0x9Eu, 0x05u},
+ {0xA0u, 0x02u},
+ {0xA1u, 0x11u},
+ {0xA2u, 0x2Cu},
+ {0xA3u, 0x80u},
+ {0xA6u, 0x02u},
+ {0xAAu, 0x11u},
+ {0xACu, 0x42u},
+ {0xB1u, 0x01u},
+ {0xB2u, 0x04u},
+ {0xB7u, 0x28u},
+ {0xC0u, 0xBFu},
+ {0xC2u, 0xFFu},
+ {0xC4u, 0x7Du},
+ {0xCAu, 0x41u},
+ {0xCCu, 0x2Eu},
+ {0xCEu, 0x0Eu},
+ {0xD0u, 0x0Fu},
+ {0xD2u, 0x04u},
+ {0xD8u, 0x0Fu},
+ {0xE4u, 0x04u},
+ {0xE8u, 0x0Au},
+ {0xEEu, 0x04u},
+ {0x01u, 0xC0u},
+ {0x03u, 0x02u},
+ {0x04u, 0x07u},
+ {0x05u, 0xC0u},
+ {0x06u, 0x08u},
+ {0x07u, 0x04u},
+ {0x09u, 0xC0u},
+ {0x0Bu, 0x08u},
+ {0x0Du, 0xC0u},
+ {0x0Fu, 0x01u},
+ {0x10u, 0x08u},
+ {0x12u, 0x06u},
+ {0x13u, 0x60u},
+ {0x15u, 0x1Fu},
+ {0x17u, 0x20u},
+ {0x19u, 0x7Fu},
+ {0x1Bu, 0x80u},
+ {0x1Du, 0x80u},
+ {0x24u, 0x03u},
+ {0x26u, 0x0Cu},
+ {0x27u, 0xFFu},
+ {0x28u, 0x0Bu},
+ {0x2Au, 0x04u},
+ {0x2Bu, 0x9Fu},
+ {0x2Du, 0x90u},
+ {0x2Fu, 0x40u},
+ {0x30u, 0x0Eu},
+ {0x33u, 0xFFu},
+ {0x34u, 0x0Eu},
+ {0x36u, 0x01u},
+ {0x3Au, 0x22u},
+ {0x3Eu, 0x40u},
+ {0x3Fu, 0x04u},
+ {0x56u, 0x02u},
+ {0x57u, 0x28u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
{0x5Fu, 0x01u},
- {0x82u, 0x80u},
- {0x8Au, 0x70u},
- {0x8Bu, 0x20u},
- {0x8Cu, 0xAAu},
- {0x8Eu, 0x55u},
- {0x91u, 0x0Au},
- {0x93u, 0x05u},
- {0x95u, 0x04u},
- {0x96u, 0x07u},
- {0x97u, 0x08u},
- {0x98u, 0x44u},
- {0x9Au, 0x88u},
- {0x9Bu, 0x17u},
- {0x9Du, 0x09u},
- {0x9Fu, 0x02u},
- {0xA6u, 0x08u},
- {0xABu, 0x08u},
- {0xACu, 0x99u},
- {0xADu, 0x10u},
- {0xAEu, 0x22u},
- {0xAFu, 0x20u},
- {0xB2u, 0x0Fu},
- {0xB3u, 0x0Fu},
- {0xB4u, 0xF0u},
- {0xB5u, 0x30u},
- {0xBFu, 0x10u},
+ {0x80u, 0x19u},
+ {0x82u, 0x22u},
+ {0x87u, 0x10u},
+ {0x89u, 0x20u},
+ {0x8Bu, 0x40u},
+ {0x8Fu, 0x2Eu},
+ {0x90u, 0x04u},
+ {0x91u, 0x09u},
+ {0x92u, 0x48u},
+ {0x93u, 0x10u},
+ {0x94u, 0x10u},
+ {0x97u, 0x01u},
+ {0x99u, 0x15u},
+ {0x9Au, 0x07u},
+ {0x9Bu, 0x0Au},
+ {0x9Fu, 0x01u},
+ {0xA1u, 0x13u},
+ {0xA2u, 0x08u},
+ {0xA3u, 0x04u},
+ {0xA4u, 0x0Au},
+ {0xA6u, 0x55u},
+ {0xA8u, 0x20u},
+ {0xAAu, 0x50u},
+ {0xAFu, 0x40u},
+ {0xB0u, 0x70u},
+ {0xB1u, 0x1Eu},
+ {0xB4u, 0x0Fu},
+ {0xB5u, 0x60u},
+ {0xB7u, 0x01u},
+ {0xBAu, 0x02u},
+ {0xBFu, 0x50u},
+ {0xD4u, 0x09u},
+ {0xD6u, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
+ {0xDBu, 0x04u},
{0xDCu, 0x11u},
{0xDFu, 0x01u},
- {0x00u, 0xA4u},
- {0x01u, 0x01u},
- {0x02u, 0x40u},
- {0x05u, 0x10u},
- {0x06u, 0x80u},
- {0x07u, 0x01u},
- {0x08u, 0x40u},
- {0x09u, 0x02u},
- {0x0Au, 0x21u},
- {0x0Bu, 0x04u},
- {0x0Eu, 0x28u},
- {0x10u, 0x08u},
- {0x11u, 0x44u},
- {0x16u, 0x10u},
- {0x17u, 0x40u},
+ {0x01u, 0x02u},
+ {0x05u, 0x08u},
+ {0x08u, 0x03u},
+ {0x09u, 0x04u},
+ {0x0Au, 0x08u},
+ {0x0Eu, 0x80u},
+ {0x10u, 0x84u},
+ {0x12u, 0x20u},
+ {0x17u, 0x18u},
{0x19u, 0x02u},
- {0x1Du, 0x18u},
- {0x1Eu, 0x20u},
- {0x1Fu, 0x20u},
- {0x20u, 0x60u},
- {0x21u, 0x02u},
- {0x22u, 0x4Au},
- {0x23u, 0x04u},
- {0x25u, 0x04u},
- {0x27u, 0x18u},
- {0x28u, 0x10u},
- {0x29u, 0x22u},
- {0x2Au, 0x44u},
- {0x2Fu, 0x0Au},
- {0x30u, 0x40u},
- {0x31u, 0x02u},
- {0x32u, 0x18u},
- {0x36u, 0x04u},
- {0x37u, 0x51u},
- {0x38u, 0x02u},
- {0x39u, 0x54u},
- {0x3Du, 0x20u},
+ {0x1Au, 0x48u},
+ {0x1Du, 0x80u},
+ {0x1Eu, 0x80u},
+ {0x1Fu, 0x10u},
+ {0x20u, 0x48u},
+ {0x22u, 0x80u},
+ {0x27u, 0x20u},
+ {0x29u, 0x02u},
+ {0x2Au, 0xC0u},
+ {0x2Cu, 0x02u},
+ {0x2Du, 0x08u},
+ {0x2Fu, 0x04u},
+ {0x30u, 0x41u},
+ {0x32u, 0x20u},
+ {0x33u, 0x04u},
+ {0x36u, 0x06u},
+ {0x37u, 0x58u},
+ {0x38u, 0x40u},
+ {0x3Bu, 0x14u},
+ {0x3Cu, 0x80u},
+ {0x3Du, 0x22u},
+ {0x3Eu, 0x04u},
+ {0x40u, 0x02u},
+ {0x43u, 0x80u},
{0x58u, 0x10u},
{0x59u, 0x04u},
- {0x5Au, 0x82u},
+ {0x5Au, 0x81u},
{0x61u, 0x80u},
{0x63u, 0x40u},
+ {0x67u, 0x20u},
+ {0x6Cu, 0x02u},
+ {0x6Du, 0x27u},
+ {0x6Eu, 0x04u},
+ {0x6Fu, 0x28u},
+ {0x74u, 0x40u},
+ {0x77u, 0x01u},
+ {0x86u, 0x40u},
{0x87u, 0x40u},
- {0x8Au, 0x20u},
- {0x8Fu, 0x08u},
- {0x90u, 0x06u},
- {0x91u, 0x55u},
- {0x92u, 0x23u},
+ {0x88u, 0x04u},
+ {0x8Fu, 0x40u},
+ {0x90u, 0x80u},
+ {0x91u, 0x08u},
+ {0x92u, 0x80u},
+ {0x93u, 0x14u},
{0x94u, 0x40u},
- {0x97u, 0x04u},
- {0x99u, 0x24u},
- {0x9Au, 0x94u},
- {0x9Bu, 0x41u},
- {0x9Eu, 0x20u},
- {0xA0u, 0x48u},
- {0xA1u, 0x90u},
- {0xA2u, 0x04u},
- {0xA3u, 0x0Au},
- {0xA4u, 0x10u},
- {0xA5u, 0x0Cu},
- {0xA6u, 0x0Au},
- {0xA7u, 0x20u},
- {0xABu, 0x10u},
- {0xAFu, 0x40u},
- {0xB3u, 0x20u},
- {0xC0u, 0xDFu},
- {0xC2u, 0x6Fu},
- {0xC4u, 0xA7u},
- {0xCAu, 0x3Fu},
+ {0x96u, 0x64u},
+ {0x97u, 0x80u},
+ {0x98u, 0x44u},
+ {0x9Bu, 0x5Cu},
+ {0x9Du, 0x08u},
+ {0x9Eu, 0x84u},
+ {0x9Fu, 0x01u},
+ {0xA0u, 0x80u},
+ {0xA1u, 0x04u},
+ {0xA2u, 0x28u},
+ {0xA3u, 0xC0u},
+ {0xA4u, 0x02u},
+ {0xA5u, 0x01u},
+ {0xA6u, 0x80u},
+ {0xA7u, 0x08u},
+ {0xA8u, 0x20u},
+ {0xA9u, 0x04u},
+ {0xABu, 0x04u},
+ {0xADu, 0x01u},
+ {0xB0u, 0x01u},
+ {0xB2u, 0x01u},
+ {0xB3u, 0x08u},
+ {0xB5u, 0x04u},
+ {0xB6u, 0x01u},
+ {0xC0u, 0x28u},
+ {0xC2u, 0x1Eu},
+ {0xC4u, 0x6Eu},
+ {0xCAu, 0x79u},
{0xCCu, 0xFFu},
- {0xCEu, 0x2Fu},
+ {0xCEu, 0xFEu},
{0xD6u, 0x0Fu},
- {0xD8u, 0x09u},
- {0xE4u, 0x80u},
- {0xEEu, 0x22u},
- {0x05u, 0x20u},
- {0x0Du, 0x20u},
+ {0xD8u, 0x49u},
+ {0xE2u, 0x08u},
+ {0xE6u, 0x01u},
+ {0xEAu, 0x08u},
+ {0xEEu, 0x21u},
+ {0x80u, 0x04u},
+ {0x84u, 0x10u},
+ {0x91u, 0x20u},
+ {0x94u, 0x80u},
+ {0x95u, 0x01u},
+ {0x96u, 0x01u},
+ {0x97u, 0x08u},
+ {0x9Cu, 0x01u},
+ {0x9Du, 0x48u},
+ {0x9Eu, 0x08u},
+ {0x9Fu, 0x08u},
+ {0xA0u, 0x10u},
+ {0xA6u, 0x04u},
+ {0xA8u, 0x48u},
+ {0xAAu, 0x40u},
+ {0xAFu, 0x08u},
+ {0xB0u, 0x02u},
+ {0xB2u, 0x20u},
+ {0xB5u, 0x01u},
+ {0xE0u, 0x20u},
+ {0xE4u, 0x40u},
+ {0xE8u, 0x80u},
+ {0xECu, 0x40u},
+ {0xEEu, 0x20u},
+ {0x38u, 0x20u},
+ {0x3Eu, 0x10u},
+ {0x58u, 0x04u},
+ {0x5Fu, 0x01u},
+ {0x18u, 0x08u},
+ {0x82u, 0x04u},
+ {0x8Cu, 0x40u},
+ {0x8Fu, 0x08u},
+ {0x94u, 0x88u},
+ {0x9Fu, 0x08u},
+ {0xA6u, 0x04u},
+ {0xACu, 0x01u},
+ {0xADu, 0x01u},
+ {0xB1u, 0x50u},
+ {0xB2u, 0x01u},
+ {0xB3u, 0x04u},
+ {0xB5u, 0x08u},
+ {0xB6u, 0x08u},
+ {0xE4u, 0x50u},
+ {0xE8u, 0xD0u},
+ {0xECu, 0x80u},
+ {0xEEu, 0x04u},
+ {0x07u, 0x04u},
+ {0x0Eu, 0x02u},
{0x12u, 0x08u},
{0x16u, 0x80u},
- {0x17u, 0x80u},
- {0x31u, 0x02u},
- {0x35u, 0x08u},
+ {0x17u, 0x20u},
+ {0x30u, 0x02u},
+ {0x35u, 0x02u},
{0x36u, 0x80u},
- {0x38u, 0x08u},
{0x3Au, 0x80u},
- {0x3Du, 0x28u},
- {0x40u, 0x02u},
- {0x67u, 0x80u},
- {0x84u, 0x80u},
- {0x87u, 0x40u},
+ {0x3Bu, 0x01u},
+ {0x3Cu, 0x44u},
+ {0x42u, 0x08u},
+ {0x62u, 0x02u},
+ {0x8Cu, 0x40u},
{0xC0u, 0x80u},
{0xC2u, 0x80u},
{0xC4u, 0xE0u},
{0xCCu, 0xE0u},
{0xCEu, 0xF0u},
{0xD0u, 0x10u},
- {0xD8u, 0x80u},
- {0xE2u, 0x10u},
- {0xE6u, 0x40u},
- {0x30u, 0x08u},
+ {0xD8u, 0x40u},
+ {0x32u, 0x01u},
{0x33u, 0x10u},
- {0x37u, 0x84u},
+ {0x34u, 0x04u},
+ {0x37u, 0x20u},
{0x39u, 0x40u},
- {0x51u, 0x01u},
- {0x56u, 0x08u},
- {0x60u, 0x80u},
- {0x89u, 0x01u},
- {0x94u, 0x08u},
- {0x98u, 0x80u},
- {0x99u, 0x20u},
- {0x9Bu, 0x90u},
- {0x9Cu, 0x02u},
- {0x9Du, 0x08u},
- {0xA1u, 0x20u},
- {0xA5u, 0x16u},
+ {0x53u, 0x10u},
+ {0x57u, 0x80u},
+ {0x5Cu, 0x01u},
+ {0x82u, 0x01u},
+ {0x8Bu, 0x10u},
+ {0x8Fu, 0x80u},
+ {0x94u, 0x04u},
+ {0x9Bu, 0x30u},
+ {0x9Du, 0x02u},
+ {0x9Eu, 0x08u},
+ {0xA2u, 0x01u},
+ {0xA4u, 0x02u},
{0xA6u, 0x80u},
{0xAAu, 0x08u},
- {0xABu, 0x10u},
+ {0xABu, 0x14u},
+ {0xAEu, 0x02u},
+ {0xB7u, 0x01u},
{0xCCu, 0xF0u},
{0xCEu, 0x10u},
- {0xD4u, 0xC0u},
- {0xD8u, 0x40u},
+ {0xD4u, 0x60u},
+ {0xD6u, 0x80u},
+ {0xE4u, 0x80u},
+ {0xE8u, 0x80u},
+ {0xEAu, 0x40u},
{0x12u, 0x80u},
- {0x33u, 0x80u},
- {0x5Au, 0x01u},
- {0x80u, 0x04u},
- {0x85u, 0x08u},
- {0x92u, 0x01u},
- {0x94u, 0x08u},
- {0x95u, 0x40u},
- {0x99u, 0x20u},
- {0x9Cu, 0x02u},
- {0x9Du, 0x08u},
- {0x9Fu, 0x04u},
- {0xA4u, 0x08u},
- {0xA5u, 0x06u},
+ {0x30u, 0x20u},
+ {0x84u, 0x02u},
+ {0x94u, 0x04u},
+ {0x96u, 0x02u},
+ {0x9Cu, 0x04u},
+ {0x9Eu, 0x08u},
+ {0xA3u, 0x40u},
+ {0xA4u, 0x02u},
{0xA6u, 0x80u},
- {0xA9u, 0x10u},
- {0xAEu, 0x09u},
- {0xB5u, 0x20u},
+ {0xA9u, 0x40u},
+ {0xABu, 0x40u},
+ {0xB1u, 0x02u},
+ {0xB4u, 0x01u},
{0xC4u, 0x10u},
{0xCCu, 0x10u},
- {0xD6u, 0x40u},
- {0xE6u, 0x90u},
- {0xEAu, 0x90u},
- {0xEEu, 0x40u},
- {0x83u, 0x04u},
- {0x89u, 0x02u},
- {0x8Du, 0x04u},
- {0x9Cu, 0x02u},
- {0x9Fu, 0x04u},
- {0xA5u, 0x06u},
- {0xA7u, 0x80u},
- {0xB0u, 0x08u},
- {0xB1u, 0x20u},
- {0xB5u, 0x40u},
- {0xE2u, 0x80u},
- {0x00u, 0x80u},
- {0x05u, 0x20u},
- {0x09u, 0x20u},
- {0x0Eu, 0x01u},
- {0x13u, 0x02u},
- {0x14u, 0x40u},
- {0x62u, 0x02u},
- {0x65u, 0x02u},
- {0x81u, 0x02u},
- {0x82u, 0x02u},
- {0x8Du, 0x20u},
+ {0xE2u, 0x10u},
+ {0xEAu, 0x20u},
+ {0xEEu, 0x20u},
+ {0x84u, 0x04u},
+ {0x86u, 0x01u},
+ {0x8Du, 0x02u},
+ {0x94u, 0x04u},
+ {0x96u, 0x02u},
+ {0x9Cu, 0x04u},
+ {0x9Eu, 0x08u},
+ {0xA3u, 0x40u},
+ {0xA4u, 0x20u},
+ {0xE2u, 0x10u},
+ {0xE6u, 0x40u},
+ {0x01u, 0x20u},
+ {0x06u, 0x01u},
+ {0x0Bu, 0x04u},
+ {0x0Du, 0x80u},
+ {0x13u, 0x08u},
+ {0x14u, 0x80u},
+ {0x58u, 0x02u},
+ {0x62u, 0x08u},
+ {0x87u, 0x04u},
{0xC0u, 0x03u},
{0xC2u, 0x03u},
{0xC4u, 0x0Cu},
- {0xD8u, 0x03u},
- {0xE2u, 0x08u},
- {0x00u, 0x01u},
- {0x07u, 0x40u},
- {0x08u, 0x01u},
- {0x0Eu, 0x80u},
- {0x51u, 0x02u},
- {0x56u, 0x20u},
- {0x58u, 0x04u},
- {0x65u, 0x01u},
- {0x84u, 0x10u},
- {0x85u, 0x02u},
- {0x88u, 0x44u},
- {0x8Cu, 0x01u},
- {0x8Du, 0x20u},
- {0x92u, 0x01u},
- {0x98u, 0x40u},
- {0x9Bu, 0x02u},
- {0xA1u, 0x20u},
- {0xACu, 0x40u},
+ {0xD6u, 0x02u},
+ {0xD8u, 0x02u},
+ {0x00u, 0x08u},
+ {0x05u, 0x02u},
+ {0x09u, 0x08u},
+ {0x0Cu, 0x02u},
+ {0x57u, 0x01u},
+ {0x59u, 0x40u},
+ {0x5Au, 0x04u},
+ {0x5Fu, 0x02u},
+ {0x84u, 0x80u},
+ {0x8Du, 0x08u},
+ {0x98u, 0x80u},
+ {0x99u, 0x20u},
+ {0x9Au, 0x01u},
+ {0x9Bu, 0x08u},
+ {0x9Cu, 0x02u},
+ {0xA1u, 0x80u},
+ {0xA6u, 0x08u},
{0xC0u, 0x0Cu},
{0xC2u, 0x0Cu},
- {0xD4u, 0x03u},
- {0xD6u, 0x02u},
- {0xD8u, 0x01u},
- {0xE2u, 0x01u},
- {0xE4u, 0x01u},
- {0xE6u, 0x0Au},
- {0x57u, 0x80u},
- {0x89u, 0x40u},
- {0x8Eu, 0x20u},
- {0x92u, 0x01u},
- {0x9Bu, 0x02u},
- {0x9Eu, 0x20u},
- {0xA2u, 0x40u},
- {0xA4u, 0x10u},
- {0xA9u, 0x01u},
- {0xABu, 0x40u},
- {0xACu, 0x01u},
- {0xD4u, 0x02u},
- {0xE2u, 0x01u},
- {0xE4u, 0x02u},
- {0x08u, 0x01u},
- {0x0Bu, 0x02u},
- {0x0Cu, 0x08u},
- {0x0Fu, 0x02u},
- {0x80u, 0x08u},
- {0x87u, 0x02u},
- {0x90u, 0x08u},
- {0x92u, 0x01u},
+ {0xD4u, 0x01u},
+ {0xD6u, 0x07u},
+ {0xE6u, 0x08u},
+ {0x80u, 0x10u},
+ {0x85u, 0x80u},
+ {0x87u, 0x01u},
+ {0x8Au, 0x04u},
+ {0x8Du, 0x20u},
+ {0x96u, 0x04u},
{0x97u, 0x02u},
- {0x9Bu, 0x02u},
- {0x9Cu, 0x01u},
- {0x9Du, 0x40u},
- {0xA2u, 0x40u},
- {0xA4u, 0x10u},
+ {0x99u, 0x22u},
+ {0x9Au, 0x01u},
+ {0x9Bu, 0x08u},
+ {0x9Fu, 0x02u},
+ {0xA1u, 0x80u},
+ {0xA7u, 0x01u},
+ {0xA8u, 0x02u},
+ {0xAAu, 0x08u},
+ {0xABu, 0x01u},
+ {0xB0u, 0x06u},
+ {0xB1u, 0x40u},
+ {0xE2u, 0x08u},
+ {0xE4u, 0x04u},
+ {0xE8u, 0x01u},
+ {0xEAu, 0x04u},
+ {0xEEu, 0x01u},
+ {0x0Bu, 0x22u},
+ {0x0Cu, 0x02u},
+ {0x0Eu, 0x04u},
+ {0x82u, 0x01u},
+ {0x84u, 0x02u},
+ {0x87u, 0x10u},
+ {0x94u, 0x10u},
+ {0x97u, 0x02u},
+ {0x9Au, 0x01u},
+ {0x9Fu, 0x02u},
+ {0xAFu, 0x08u},
+ {0xB1u, 0x02u},
+ {0xC2u, 0x0Fu},
+ {0xEAu, 0x01u},
+ {0x64u, 0x80u},
+ {0x80u, 0x80u},
+ {0x86u, 0x08u},
+ {0x94u, 0x04u},
+ {0x9Eu, 0x08u},
+ {0xA1u, 0x02u},
+ {0xA3u, 0x40u},
+ {0xB0u, 0x20u},
+ {0xD8u, 0x80u},
+ {0xE6u, 0xC0u},
+ {0x07u, 0x80u},
+ {0x51u, 0x02u},
+ {0x57u, 0x40u},
+ {0x83u, 0x80u},
+ {0xA1u, 0x02u},
+ {0xA3u, 0x40u},
{0xA8u, 0x04u},
- {0xABu, 0x80u},
+ {0xC0u, 0x20u},
+ {0xD4u, 0xC0u},
+ {0xE0u, 0x80u},
+ {0xEAu, 0x20u},
+ {0x74u, 0x01u},
+ {0x8Bu, 0x02u},
+ {0x8Cu, 0x02u},
+ {0x94u, 0x10u},
+ {0x9Fu, 0x02u},
+ {0xA0u, 0x01u},
{0xB0u, 0x01u},
- {0xB7u, 0x01u},
- {0xC2u, 0x0Fu},
- {0xEAu, 0x02u},
+ {0xB2u, 0x04u},
+ {0xDEu, 0x04u},
+ {0xE0u, 0x04u},
+ {0xE4u, 0x02u},
+ {0xE8u, 0x01u},
{0xEEu, 0x04u},
- {0x84u, 0x02u},
- {0x9Cu, 0x02u},
- {0xAFu, 0x80u},
- {0xE2u, 0x10u},
- {0xEEu, 0x10u},
- {0x06u, 0x20u},
- {0x50u, 0x02u},
- {0x56u, 0x80u},
- {0x84u, 0x02u},
- {0x8Au, 0x20u},
- {0x9Au, 0x80u},
- {0x9Cu, 0x02u},
+ {0x00u, 0x10u},
+ {0x06u, 0x02u},
+ {0x52u, 0x10u},
+ {0x54u, 0x02u},
+ {0x94u, 0x10u},
+ {0x9Au, 0x10u},
+ {0x9Eu, 0x02u},
{0xA0u, 0x02u},
- {0xB2u, 0x80u},
- {0xC0u, 0x20u},
- {0xD4u, 0xC0u},
- {0xE6u, 0x40u},
- {0x90u, 0x08u},
- {0x9Du, 0x40u},
- {0xA2u, 0x40u},
- {0xA4u, 0x10u},
- {0xAFu, 0x01u},
- {0xB2u, 0x01u},
- {0xEEu, 0x01u},
- {0x00u, 0x20u},
- {0x05u, 0x40u},
- {0x50u, 0x04u},
- {0x5Au, 0x40u},
- {0x8Eu, 0x40u},
- {0x90u, 0x08u},
- {0x9Du, 0x40u},
- {0xA4u, 0x10u},
- {0xAEu, 0x40u},
+ {0xAAu, 0x02u},
+ {0xB2u, 0x10u},
{0xC0u, 0x03u},
- {0xD4u, 0x05u},
- {0xE4u, 0x02u},
+ {0xD4u, 0x04u},
+ {0xD6u, 0x04u},
+ {0xECu, 0x04u},
{0x10u, 0x03u},
- {0x11u, 0x01u},
- {0x1Cu, 0x03u},
- {0x1Du, 0x01u},
+ {0x1Au, 0x03u},
{0x00u, 0xFDu},
{0x01u, 0xBFu},
{0x02u, 0x2Au},
- {0x10u, 0x55u},
+ {0x10u, 0x95u},
};
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},
{(void CYFAR *)(CYREG_PRT1_DR), 16u},
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 1152u},
- {(void CYFAR *)(CYDEV_UCFG_B1_P4_ROUTE_BASE), 768u},
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u},
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
{(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},
};
- /* UDB_0_1_0_CONFIG Address: CYDEV_UCFG_B1_P4_U1_BASE Size (bytes): 128 */
- static const uint8 CYCODE BS_UDB_0_1_0_CONFIG_VAL[] = {
- 0x10u, 0x00u, 0x00u, 0x00u, 0x07u, 0x13u, 0x18u, 0x20u, 0x22u, 0x00u, 0x08u, 0x0Eu, 0x08u, 0x11u, 0x21u, 0x44u,
- 0x00u, 0x00u, 0x80u, 0x00u, 0x01u, 0x29u, 0x00u, 0x10u, 0x04u, 0x6Eu, 0x00u, 0x00u, 0xC1u, 0x00u, 0x00u, 0x00u,
- 0xC1u, 0x00u, 0x00u, 0x00u, 0xC1u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0xC0u, 0x00u,
- 0x00u, 0x00u, 0x80u, 0x0Eu, 0x3Fu, 0x70u, 0x40u, 0x01u, 0x20u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x54u, 0x44u,
- 0x56u, 0x02u, 0x10u, 0x00u, 0x03u, 0xBEu, 0xFDu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u,
+ /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */
+ static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {
+ 0x02u, 0x00u, 0x00u, 0x00u, 0x32u, 0x00u, 0x04u, 0x08u, 0x01u, 0x00u, 0x0Eu, 0x07u, 0x36u, 0x00u, 0x00u, 0x80u,
+ 0x36u, 0x00u, 0x00u, 0x00u, 0x09u, 0x00u, 0x06u, 0x70u, 0x30u, 0xAAu, 0x06u, 0x55u, 0x04u, 0x44u, 0x00u, 0x88u,
+ 0x00u, 0x99u, 0x10u, 0x22u, 0x07u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x06u, 0x00u, 0x30u, 0x00u,
+ 0x00u, 0x00u, 0x0Fu, 0xF0u, 0x10u, 0x0Fu, 0x20u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x00u,
+ 0x32u, 0x06u, 0x10u, 0x00u, 0x04u, 0xDEu, 0xFCu, 0x0Bu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x04u, 0x00u, 0x04u, 0x04u, 0x04u, 0x04u, 0x10u, 0x00u, 0x00u, 0x01u,
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x02u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u};
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u};
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
- {(void CYFAR *)(CYDEV_UCFG_B1_P4_U1_BASE), BS_UDB_0_1_0_CONFIG_VAL, 128u},
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u},
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},
};
.set EXTLED__SLW, CYREG_PRT0_SLW
/* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB09_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB09_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB09_MSK
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB09_10_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB09_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB09_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB09_ST
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB09_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB09_ST
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB09_10_A0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB09_10_A1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB09_10_D0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB09_10_D1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB09_10_F0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB09_10_F1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB09_A0_A1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB09_A0
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB09_A1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB09_D0_D1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB09_D0
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB09_D1
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB09_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB09_F0_F1
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB09_F0
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB09_F1
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
.set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB10_11_ST
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
.set SDCard_BSPIM_TxStsReg__2__POS, 2
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB10_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB10_ST
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
/* SD_SCK */
.set SD_SCK__0__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
/* SCSI_Out_Ctl */
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK
/* SCSI_Out_DBx */
.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
.set SCSI_Noise__SEL__SLW, CYREG_PRT4_SLW
/* scsiTarget */
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB11_12_A0
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB11_12_A1
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB11_12_D0
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB11_12_D1
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB11_12_F0
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB11_12_F1
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB11_A0_A1
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB11_A0
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB11_A1
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB11_D0_D1
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB11_D0
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB11_D1
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB11_F0_F1
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB11_F0
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB11_F1
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB11_MSK
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB11_ST
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB11_CTL
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB11_CTL
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB11_MSK
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB00_01_A0
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB00_01_A1
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB00_01_D0
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB00_01_D1
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB00_01_F0
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB00_01_F1
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB00_A0_A1
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB00_A0
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB00_A1
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB00_D0_D1
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB00_D0
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB00_D1
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB00_F0_F1
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB00_F0
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB00_F1
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB00_MSK
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB00_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB00_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB00_ST
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB00_CTL
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB00_CTL
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB00_MSK
.set scsiTarget_StatusReg__0__MASK, 0x01
.set scsiTarget_StatusReg__0__POS, 0
.set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
.set scsiTarget_StatusReg__2__MASK, 0x04
.set scsiTarget_StatusReg__2__POS, 2
.set scsiTarget_StatusReg__3__MASK, 0x08
.set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB07_MSK
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB07_ST
/* Debug_Timer_Interrupt */
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SCSI_Filtered_sts_sts_reg__0__POS, 0
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
.set SCSI_Filtered_sts_sts_reg__1__POS, 1
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
.set SCSI_Filtered_sts_sts_reg__2__POS, 2
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
.set SCSI_Filtered_sts_sts_reg__4__POS, 4
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK
-.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB01_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB01_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK
+.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
+
+/* SCSI_Glitch_Ctl */
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB04_MSK
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB04_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB09_MSK
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB09_ST
/* Miscellaneous */
.set BCLK__BUS_CLK__HZ, 50000000
EXTLED__SLW EQU CYREG_PRT0_SLW
/* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB09_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB09_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB09_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB09_10_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB09_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB09_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB09_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB09_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB09_10_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB09_10_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB09_10_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB09_10_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB09_10_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB09_10_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB09_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB09_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB09_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB09_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB09_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB09_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB09_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB09_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB09_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
/* SD_SCK */
SD_SCK__0__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
/* SCSI_Out_Ctl */
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
/* SCSI_Out_DBx */
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW
/* scsiTarget */
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB00_01_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB00_01_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB00_01_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB00_01_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB00_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB00_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB00_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB00_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB00_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB00_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB00_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB00_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB00_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB00_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB00_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB00_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB00_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB00_MSK
scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB07_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST
/* Debug_Timer_Interrupt */
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+
+/* SCSI_Glitch_Ctl */
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST
/* Miscellaneous */
BCLK__BUS_CLK__HZ EQU 50000000
EXTLED__SLW EQU CYREG_PRT0_SLW
; SDCard_BSPIM
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB09_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB09_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB09_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB09_10_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB09_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB09_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB09_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB09_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB09_10_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB09_10_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB09_10_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB09_10_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB09_10_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB09_10_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB09_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB09_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB09_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB09_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB09_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB09_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB09_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB09_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB09_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
; SD_SCK
SD_SCK__0__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
; SCSI_Out_Ctl
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
; SCSI_Out_DBx
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW
; scsiTarget
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB00_01_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB00_01_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB00_01_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB00_01_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB00_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB00_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB00_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB00_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB00_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB00_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB00_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB00_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB00_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB00_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB00_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB00_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB00_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB00_MSK
scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB07_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB07_ST
; Debug_Timer_Interrupt
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+
+; SCSI_Glitch_Ctl
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST
; Miscellaneous
BCLK__BUS_CLK__HZ EQU 50000000
#include <EXTLED_aliases.h>
#include <EXTLED.h>
#include <SCSI_SEL_ISR.h>
+#include <SCSI_Glitch_Ctl.h>
#include <USBFS_Dm_aliases.h>
#include <USBFS_Dm.h>
#include <USBFS_Dp_aliases.h>
<?xml version="1.0" encoding="utf-8"?>
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
- <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">
- <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />
- </register>
- <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">
- <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />
- <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">
- <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
- <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
- </field>
- <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />
- <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />
- <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />
- <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">
- <value name="Timer" value="0" desc="CMP and TC are output." />
- <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
- </field>
- <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />
- </register>
- <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">
- <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />
- <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">
- <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
- <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
- </field>
- <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />
- <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />
- <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />
- <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />
- </register>
- <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">
- <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">
- <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
- <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
- <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
- <value name="Irq" value="11" desc="Timer runs until IRQ." />
- </field>
- <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />
- <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />
- <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">
- <value name="Equal" value="0" desc="Compare Equal " />
- <value name="Less than" value="1" desc="Compare Less Than " />
- <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
- <value name="Greater" value="11" desc="Compare Greater Than ." />
- <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
- </field>
- <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />
- </register>
- <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />
- <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
- </block>
- <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006464" bitWidth="8" desc="" />
- <register name="SCSI_Parity_Error_MASK_REG" address="0x40006484" bitWidth="8" desc="" />
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006494" bitWidth="8" desc="">
+ <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">
+ <register name="SCSI_Filtered_STATUS_REG" address="0x40006468" bitWidth="8" desc="" />
+ <register name="SCSI_Filtered_MASK_REG" address="0x40006488" bitWidth="8" desc="" />
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006498" bitWidth="8" desc="">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</field>
</register>
</block>
- <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Filtered_STATUS_REG" address="0x40006461" bitWidth="8" desc="" />
- <register name="SCSI_Filtered_MASK_REG" address="0x40006481" bitWidth="8" desc="" />
- <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006491" bitWidth="8" desc="">
+ <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006469" bitWidth="8" desc="" />
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x40006489" bitWidth="8" desc="" />
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006499" bitWidth="8" desc="">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</field>
</register>
</block>
+ <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
+ <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" />
+ </block>
+ <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />
</block>
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
<block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />
</block>
- <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">
+ <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />
+ </register>
+ <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">
+ <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />
+ <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">
+ <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
+ <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
+ </field>
+ <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />
+ <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />
+ <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />
+ <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">
+ <value name="Timer" value="0" desc="CMP and TC are output." />
+ <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
+ </field>
+ <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />
+ </register>
+ <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">
+ <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />
+ <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">
+ <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
+ <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
+ </field>
+ <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />
+ <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />
+ <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />
+ <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />
+ </register>
+ <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">
+ <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">
+ <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
+ <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
+ <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
+ <value name="Irq" value="11" desc="Timer runs until IRQ." />
+ </field>
+ <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />
+ <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />
+ <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">
+ <value name="Equal" value="0" desc="Compare Equal " />
+ <value name="Less than" value="1" desc="Compare Less Than " />
+ <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
+ <value name="Greater" value="11" desc="Compare Greater Than ." />
+ <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
+ </field>
+ <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />
+ </register>
+ <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />
+ <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
+ </block>
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006470" bitWidth="8" desc="" />
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" />
</block>
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" />
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />
</block>
- <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<filters />
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctrl" persistent="">
+<Hidden v="True" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctrl.c" persistent=".\Generated_Source\PSoC5\SCSI_Glitch_Ctrl.c">
+<Hidden v="True" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctrl.h" persistent=".\Generated_Source\PSoC5\SCSI_Glitch_Ctrl.h">
+<Hidden v="True" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctl" persistent="">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctl.c" persistent=".\Generated_Source\PSoC5\SCSI_Glitch_Ctl.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Glitch_Ctl.h" persistent=".\Generated_Source\PSoC5\SCSI_Glitch_Ctl.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
</dependencies>
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<width>32</width>
<peripherals>
<peripheral>
- <name>Debug_Timer</name>
- <description>No description available</description>
- <baseAddress>0x0</baseAddress>
- <addressBlock>
- <offset>0</offset>
- <size>0x0</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>Debug_Timer_GLOBAL_ENABLE</name>
- <description>PM.ACT.CFG</description>
- <addressOffset>0x400043A3</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- <fields>
- <field>
- <name>en_timer</name>
- <description>Enable timer/counters.</description>
- <lsb>0</lsb>
- <msb>3</msb>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>Debug_Timer_CONTROL</name>
- <description>TMRx.CFG0</description>
- <addressOffset>0x40004F00</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- <fields>
- <field>
- <name>EN</name>
- <description>Enables timer/comparator.</description>
- <lsb>0</lsb>
- <msb>0</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>MODE</name>
- <description>Mode. (0 = Timer; 1 = Comparator)</description>
- <lsb>1</lsb>
- <msb>1</msb>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>Timer</name>
- <description>Timer mode. CNT/CMP register holds timer count value.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Comparator</name>
- <description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>ONESHOT</name>
- <description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>
- <lsb>2</lsb>
- <msb>2</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>CMP_BUFF</name>
- <description>Buffer compare register. Compare register updates only on timer terminal count.</description>
- <lsb>3</lsb>
- <msb>3</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>INV</name>
- <description>Invert sense of TIMEREN signal</description>
- <lsb>4</lsb>
- <msb>4</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>DB</name>
- <description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>
- <lsb>5</lsb>
- <msb>5</msb>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>Timer</name>
- <description>CMP and TC are output.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Deadband</name>
- <description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>DEADBAND_PERIOD</name>
- <description>Deadband Period</description>
- <lsb>6</lsb>
- <msb>7</msb>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>Debug_Timer_CONTROL2</name>
- <description>TMRx.CFG1</description>
- <addressOffset>0x40004F01</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- <fields>
- <field>
- <name>IRQ_SEL</name>
- <description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>
- <lsb>0</lsb>
- <msb>0</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>FTC</name>
- <description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>
- <lsb>1</lsb>
- <msb>1</msb>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>Disable_FTC</name>
- <description>Disable the single cycle pulse, which signifies the timer is starting.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enable_FTC</name>
- <description>Enable the single cycle pulse, which signifies the timer is starting.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>DCOR</name>
- <description>Disable Clear on Read (DCOR) of Status Register SR0.</description>
- <lsb>2</lsb>
- <msb>2</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>DBMODE</name>
- <description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>
- <lsb>3</lsb>
- <msb>3</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>CLK_BUS_EN_SEL</name>
- <description>Digital Global Clock selection.</description>
- <lsb>4</lsb>
- <msb>6</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>BUS_CLK_SEL</name>
- <description>Bus Clock selection.</description>
- <lsb>7</lsb>
- <msb>7</msb>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>Debug_Timer_CONTROL3_</name>
- <description>TMRx.CFG2</description>
- <addressOffset>0x40004F02</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- <fields>
- <field>
- <name>TMR_CFG</name>
- <description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>
- <lsb>0</lsb>
- <msb>1</msb>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>Continuous</name>
- <description>Timer runs while EN bit of CFG0 register is set to '1'.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Pulsewidth</name>
- <description>Timer runs from positive to negative edge of TIMEREN.</description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Period</name>
- <description>Timer runs from positive to positive edge of TIMEREN.</description>
- <value>2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Irq</name>
- <description>Timer runs until IRQ.</description>
- <value>3</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COD</name>
- <description>Clear On Disable (COD). Clears or gates outputs to zero.</description>
- <lsb>2</lsb>
- <msb>2</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>ROD</name>
- <description>Reset On Disable (ROD). Resets internal state of output logic</description>
- <lsb>3</lsb>
- <msb>3</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>CMP_CFG</name>
- <description>Comparator configurations</description>
- <lsb>4</lsb>
- <msb>6</msb>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>Equal</name>
- <description>Compare Equal </description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Less_than</name>
- <description>Compare Less Than </description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Less_than_or_equal</name>
- <description>Compare Less Than or Equal .</description>
- <value>2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Greater</name>
- <description>Compare Greater Than .</description>
- <value>3</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Greater_than_or_equal</name>
- <description>Compare Greater Than or Equal </description>
- <value>4</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>HW_EN</name>
- <description>When set Timer Enable controls counting.</description>
- <lsb>7</lsb>
- <msb>7</msb>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>Debug_Timer_PERIOD</name>
- <description>TMRx.PER0 - Assigned Period</description>
- <addressOffset>0x40004F04</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>Debug_Timer_COUNTER</name>
- <description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
- <addressOffset>0x40004F06</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>SCSI_Parity_Error</name>
+ <name>SCSI_Filtered</name>
<description>No description available</description>
- <baseAddress>0x40006464</baseAddress>
+ <baseAddress>0x40006468</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
</addressBlock>
<registers>
<register>
- <name>SCSI_Parity_Error_STATUS_REG</name>
+ <name>SCSI_Filtered_STATUS_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
<resetMask>0</resetMask>
</register>
<register>
- <name>SCSI_Parity_Error_MASK_REG</name>
+ <name>SCSI_Filtered_MASK_REG</name>
<description>No description available</description>
<addressOffset>0x20</addressOffset>
<size>8</size>
<resetMask>0</resetMask>
</register>
<register>
- <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
+ <name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>
<description>No description available</description>
<addressOffset>0x30</addressOffset>
<size>8</size>
</registers>
</peripheral>
<peripheral>
- <name>SCSI_Filtered</name>
+ <name>SCSI_Parity_Error</name>
<description>No description available</description>
- <baseAddress>0x40006461</baseAddress>
+ <baseAddress>0x40006469</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
</addressBlock>
<registers>
<register>
- <name>SCSI_Filtered_STATUS_REG</name>
+ <name>SCSI_Parity_Error_STATUS_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
<resetMask>0</resetMask>
</register>
<register>
- <name>SCSI_Filtered_MASK_REG</name>
+ <name>SCSI_Parity_Error_MASK_REG</name>
<description>No description available</description>
<addressOffset>0x20</addressOffset>
<size>8</size>
<resetMask>0</resetMask>
</register>
<register>
- <name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>
+ <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
<description>No description available</description>
<addressOffset>0x30</addressOffset>
<size>8</size>
</register>
</registers>
</peripheral>
+ <peripheral>
+ <name>SCSI_Glitch_Ctl</name>
+ <description>No description available</description>
+ <baseAddress>0x4000647A</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x0</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>SCSI_Glitch_Ctl_CONTROL_REG</name>
+ <description>No description available</description>
+ <addressOffset>0x0</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ </registers>
+ </peripheral>
<peripheral>
<name>SCSI_CTL_PHASE</name>
<description>No description available</description>
- <baseAddress>0x40006471</baseAddress>
+ <baseAddress>0x40006472</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<resetMask>0</resetMask>
<fields>
<field>
- <name>PinState_DP</name>
+ <name>PinState_DP</name>
+ <description>No description available</description>
+ <lsb>6</lsb>
+ <msb>6</msb>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>PinState_DM</name>
+ <description>No description available</description>
+ <lsb>7</lsb>
+ <msb>7</msb>
+ <access>read-only</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>USBFS_PRT_DM0</name>
+ <description>Port Drive Mode Register</description>
+ <addressOffset>0x400051F2</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>DriveMode_DP</name>
+ <description>No description available</description>
+ <lsb>6</lsb>
+ <msb>6</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>DriveMode_DM</name>
+ <description>No description available</description>
+ <lsb>7</lsb>
+ <msb>7</msb>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>USBFS_PRT_DM1</name>
+ <description>Port Drive Mode Register</description>
+ <addressOffset>0x400051F3</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>PullUp_en_DP</name>
+ <description>No description available</description>
+ <lsb>6</lsb>
+ <msb>6</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>PullUp_en_DM</name>
+ <description>No description available</description>
+ <lsb>7</lsb>
+ <msb>7</msb>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>USBFS_PRT_INP_DIS</name>
+ <description>Input buffer disable override</description>
+ <addressOffset>0x400051F8</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>seinput_dis_dp</name>
+ <description>No description available</description>
+ <lsb>6</lsb>
+ <msb>6</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>seinput_dis_dm</name>
+ <description>No description available</description>
+ <lsb>7</lsb>
+ <msb>7</msb>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>USBFS_EP0_DR0</name>
+ <description>bmRequestType</description>
+ <addressOffset>0x40006000</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_EP0_DR1</name>
+ <description>bRequest</description>
+ <addressOffset>0x40006001</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_EP0_DR2</name>
+ <description>wValueLo</description>
+ <addressOffset>0x40006002</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_EP0_DR3</name>
+ <description>wValueHi</description>
+ <addressOffset>0x40006003</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_EP0_DR4</name>
+ <description>wIndexLo</description>
+ <addressOffset>0x40006004</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_EP0_DR5</name>
+ <description>wIndexHi</description>
+ <addressOffset>0x40006005</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_EP0_DR6</name>
+ <description>lengthLo</description>
+ <addressOffset>0x40006006</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_EP0_DR7</name>
+ <description>lengthHi</description>
+ <addressOffset>0x40006007</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_CR0</name>
+ <description>USB Control Register 0</description>
+ <addressOffset>0x40006008</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>device_address</name>
+ <description>No description available</description>
+ <lsb>0</lsb>
+ <msb>6</msb>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>usb_enable</name>
+ <description>No description available</description>
+ <lsb>7</lsb>
+ <msb>7</msb>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>USBFS_CR1</name>
+ <description>USB Control Register 1</description>
+ <addressOffset>0x40006009</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>reg_enable</name>
+ <description>No description available</description>
+ <lsb>0</lsb>
+ <msb>0</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>enable_lock</name>
+ <description>No description available</description>
+ <lsb>1</lsb>
+ <msb>1</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>bus_activity</name>
+ <description>No description available</description>
+ <lsb>2</lsb>
+ <msb>2</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>trim_offset_msb</name>
+ <description>No description available</description>
+ <lsb>3</lsb>
+ <msb>3</msb>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>USBFS_SIE_EP1_CR0</name>
+ <description>The Endpoint1 Control Register</description>
+ <addressOffset>0x4000600E</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_USBIO_CR0</name>
+ <description>USBIO Control Register 0</description>
+ <addressOffset>0x40006010</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>rd</name>
<description>No description available</description>
- <lsb>6</lsb>
- <msb>6</msb>
+ <lsb>0</lsb>
+ <msb>0</msb>
<access>read-only</access>
</field>
<field>
- <name>PinState_DM</name>
+ <name>td</name>
<description>No description available</description>
- <lsb>7</lsb>
- <msb>7</msb>
- <access>read-only</access>
+ <lsb>5</lsb>
+ <msb>5</msb>
+ <access>read-write</access>
</field>
- </fields>
- </register>
- <register>
- <name>USBFS_PRT_DM0</name>
- <description>Port Drive Mode Register</description>
- <addressOffset>0x400051F2</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- <fields>
<field>
- <name>DriveMode_DP</name>
+ <name>tse0</name>
<description>No description available</description>
<lsb>6</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
- <name>DriveMode_DM</name>
+ <name>ten</name>
<description>No description available</description>
<lsb>7</lsb>
<msb>7</msb>
</fields>
</register>
<register>
- <name>USBFS_PRT_DM1</name>
- <description>Port Drive Mode Register</description>
- <addressOffset>0x400051F3</addressOffset>
+ <name>USBFS_USBIO_CR1</name>
+ <description>USBIO Control Register 1</description>
+ <addressOffset>0x40006012</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>PullUp_en_DP</name>
+ <name>dmo</name>
<description>No description available</description>
- <lsb>6</lsb>
- <msb>6</msb>
- <access>read-write</access>
+ <lsb>0</lsb>
+ <msb>0</msb>
+ <access>read-only</access>
</field>
<field>
- <name>PullUp_en_DM</name>
+ <name>dpo</name>
<description>No description available</description>
- <lsb>7</lsb>
- <msb>7</msb>
- <access>read-write</access>
+ <lsb>1</lsb>
+ <msb>1</msb>
+ <access>read-only</access>
</field>
- </fields>
- </register>
- <register>
- <name>USBFS_PRT_INP_DIS</name>
- <description>Input buffer disable override</description>
- <addressOffset>0x400051F8</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- <fields>
<field>
- <name>seinput_dis_dp</name>
+ <name>usbpuen</name>
<description>No description available</description>
- <lsb>6</lsb>
- <msb>6</msb>
+ <lsb>2</lsb>
+ <msb>2</msb>
<access>read-write</access>
</field>
<field>
- <name>seinput_dis_dm</name>
+ <name>iomode</name>
<description>No description available</description>
- <lsb>7</lsb>
- <msb>7</msb>
+ <lsb>5</lsb>
+ <msb>5</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
- <name>USBFS_EP0_DR0</name>
- <description>bmRequestType</description>
- <addressOffset>0x40006000</addressOffset>
+ <name>USBFS_SIE_EP2_CR0</name>
+ <description>The Endpoint2 Control Register</description>
+ <addressOffset>0x4000601E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
- <name>USBFS_EP0_DR1</name>
- <description>bRequest</description>
- <addressOffset>0x40006001</addressOffset>
+ <name>USBFS_SIE_EP3_CR0</name>
+ <description>The Endpoint3 Control Register</description>
+ <addressOffset>0x4000602E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
- <name>USBFS_EP0_DR2</name>
- <description>wValueLo</description>
- <addressOffset>0x40006002</addressOffset>
+ <name>USBFS_SIE_EP4_CR0</name>
+ <description>The Endpoint4 Control Register</description>
+ <addressOffset>0x4000603E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
- <name>USBFS_EP0_DR3</name>
- <description>wValueHi</description>
- <addressOffset>0x40006003</addressOffset>
+ <name>USBFS_SIE_EP5_CR0</name>
+ <description>The Endpoint5 Control Register</description>
+ <addressOffset>0x4000604E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
- <name>USBFS_EP0_DR4</name>
- <description>wIndexLo</description>
- <addressOffset>0x40006004</addressOffset>
+ <name>USBFS_SIE_EP6_CR0</name>
+ <description>The Endpoint6 Control Register</description>
+ <addressOffset>0x4000605E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
- <name>USBFS_EP0_DR5</name>
- <description>wIndexHi</description>
- <addressOffset>0x40006005</addressOffset>
+ <name>USBFS_SIE_EP7_CR0</name>
+ <description>The Endpoint7 Control Register</description>
+ <addressOffset>0x4000606E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
- <name>USBFS_EP0_DR6</name>
- <description>lengthLo</description>
- <addressOffset>0x40006006</addressOffset>
+ <name>USBFS_SIE_EP8_CR0</name>
+ <description>The Endpoint8 Control Register</description>
+ <addressOffset>0x4000607E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
- <name>USBFS_EP0_DR7</name>
- <description>lengthHi</description>
- <addressOffset>0x40006007</addressOffset>
+ <name>USBFS_BUF_SIZE</name>
+ <description>Dedicated Endpoint Buffer Size Register</description>
+ <addressOffset>0x4000608C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
- <name>USBFS_CR0</name>
- <description>USB Control Register 0</description>
- <addressOffset>0x40006008</addressOffset>
+ <name>USBFS_EP_ACTIVE</name>
+ <description>Endpoint Active Indication Register</description>
+ <addressOffset>0x4000608E</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_EP_TYPE</name>
+ <description>Endpoint Type (IN/OUT) Indication</description>
+ <addressOffset>0x4000608F</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>USBFS_USB_CLK_EN</name>
+ <description>USB Block Clock Enable Register</description>
+ <addressOffset>0x4000609D</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>Debug_Timer</name>
+ <description>No description available</description>
+ <baseAddress>0x0</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x0</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>Debug_Timer_GLOBAL_ENABLE</name>
+ <description>PM.ACT.CFG</description>
+ <addressOffset>0x400043A3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>device_address</name>
- <description>No description available</description>
+ <name>en_timer</name>
+ <description>Enable timer/counters.</description>
<lsb>0</lsb>
- <msb>6</msb>
- <access>read-only</access>
- </field>
- <field>
- <name>usb_enable</name>
- <description>No description available</description>
- <lsb>7</lsb>
- <msb>7</msb>
+ <msb>3</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
- <name>USBFS_CR1</name>
- <description>USB Control Register 1</description>
- <addressOffset>0x40006009</addressOffset>
+ <name>Debug_Timer_CONTROL</name>
+ <description>TMRx.CFG0</description>
+ <addressOffset>0x40004F00</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>reg_enable</name>
- <description>No description available</description>
+ <name>EN</name>
+ <description>Enables timer/comparator.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
- <name>enable_lock</name>
- <description>No description available</description>
+ <name>MODE</name>
+ <description>Mode. (0 = Timer; 1 = Comparator)</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Timer</name>
+ <description>Timer mode. CNT/CMP register holds timer count value.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Comparator</name>
+ <description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
</field>
<field>
- <name>bus_activity</name>
- <description>No description available</description>
+ <name>ONESHOT</name>
+ <description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
- <name>trim_offset_msb</name>
- <description>No description available</description>
+ <name>CMP_BUFF</name>
+ <description>Buffer compare register. Compare register updates only on timer terminal count.</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
- </fields>
- </register>
- <register>
- <name>USBFS_SIE_EP1_CR0</name>
- <description>The Endpoint1 Control Register</description>
- <addressOffset>0x4000600E</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
+ <field>
+ <name>INV</name>
+ <description>Invert sense of TIMEREN signal</description>
+ <lsb>4</lsb>
+ <msb>4</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>DB</name>
+ <description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>
+ <lsb>5</lsb>
+ <msb>5</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Timer</name>
+ <description>CMP and TC are output.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Deadband</name>
+ <description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DEADBAND_PERIOD</name>
+ <description>Deadband Period</description>
+ <lsb>6</lsb>
+ <msb>7</msb>
+ <access>read-write</access>
+ </field>
+ </fields>
</register>
<register>
- <name>USBFS_USBIO_CR0</name>
- <description>USBIO Control Register 0</description>
- <addressOffset>0x40006010</addressOffset>
+ <name>Debug_Timer_CONTROL2</name>
+ <description>TMRx.CFG1</description>
+ <addressOffset>0x40004F01</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>rd</name>
- <description>No description available</description>
+ <name>IRQ_SEL</name>
+ <description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>
<lsb>0</lsb>
<msb>0</msb>
- <access>read-only</access>
+ <access>read-write</access>
</field>
<field>
- <name>td</name>
- <description>No description available</description>
- <lsb>5</lsb>
- <msb>5</msb>
+ <name>FTC</name>
+ <description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>
+ <lsb>1</lsb>
+ <msb>1</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Disable_FTC</name>
+ <description>Disable the single cycle pulse, which signifies the timer is starting.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Enable_FTC</name>
+ <description>Enable the single cycle pulse, which signifies the timer is starting.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DCOR</name>
+ <description>Disable Clear on Read (DCOR) of Status Register SR0.</description>
+ <lsb>2</lsb>
+ <msb>2</msb>
<access>read-write</access>
</field>
<field>
- <name>tse0</name>
- <description>No description available</description>
- <lsb>6</lsb>
+ <name>DBMODE</name>
+ <description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>
+ <lsb>3</lsb>
+ <msb>3</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>CLK_BUS_EN_SEL</name>
+ <description>Digital Global Clock selection.</description>
+ <lsb>4</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
- <name>ten</name>
- <description>No description available</description>
+ <name>BUS_CLK_SEL</name>
+ <description>Bus Clock selection.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</fields>
</register>
<register>
- <name>USBFS_USBIO_CR1</name>
- <description>USBIO Control Register 1</description>
- <addressOffset>0x40006012</addressOffset>
+ <name>Debug_Timer_CONTROL3_</name>
+ <description>TMRx.CFG2</description>
+ <addressOffset>0x40004F02</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>dmo</name>
- <description>No description available</description>
+ <name>TMR_CFG</name>
+ <description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>
<lsb>0</lsb>
- <msb>0</msb>
- <access>read-only</access>
- </field>
- <field>
- <name>dpo</name>
- <description>No description available</description>
- <lsb>1</lsb>
<msb>1</msb>
- <access>read-only</access>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Continuous</name>
+ <description>Timer runs while EN bit of CFG0 register is set to '1'.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Pulsewidth</name>
+ <description>Timer runs from positive to negative edge of TIMEREN.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Period</name>
+ <description>Timer runs from positive to positive edge of TIMEREN.</description>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Irq</name>
+ <description>Timer runs until IRQ.</description>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
</field>
<field>
- <name>usbpuen</name>
- <description>No description available</description>
+ <name>COD</name>
+ <description>Clear On Disable (COD). Clears or gates outputs to zero.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
- <name>iomode</name>
- <description>No description available</description>
- <lsb>5</lsb>
- <msb>5</msb>
+ <name>ROD</name>
+ <description>Reset On Disable (ROD). Resets internal state of output logic</description>
+ <lsb>3</lsb>
+ <msb>3</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>CMP_CFG</name>
+ <description>Comparator configurations</description>
+ <lsb>4</lsb>
+ <msb>6</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Equal</name>
+ <description>Compare Equal </description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Less_than</name>
+ <description>Compare Less Than </description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Less_than_or_equal</name>
+ <description>Compare Less Than or Equal .</description>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Greater</name>
+ <description>Compare Greater Than .</description>
+ <value>3</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Greater_than_or_equal</name>
+ <description>Compare Greater Than or Equal </description>
+ <value>4</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>HW_EN</name>
+ <description>When set Timer Enable controls counting.</description>
+ <lsb>7</lsb>
+ <msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
- <name>USBFS_SIE_EP2_CR0</name>
- <description>The Endpoint2 Control Register</description>
- <addressOffset>0x4000601E</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_SIE_EP3_CR0</name>
- <description>The Endpoint3 Control Register</description>
- <addressOffset>0x4000602E</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_SIE_EP4_CR0</name>
- <description>The Endpoint4 Control Register</description>
- <addressOffset>0x4000603E</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_SIE_EP5_CR0</name>
- <description>The Endpoint5 Control Register</description>
- <addressOffset>0x4000604E</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_SIE_EP6_CR0</name>
- <description>The Endpoint6 Control Register</description>
- <addressOffset>0x4000605E</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_SIE_EP7_CR0</name>
- <description>The Endpoint7 Control Register</description>
- <addressOffset>0x4000606E</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_SIE_EP8_CR0</name>
- <description>The Endpoint8 Control Register</description>
- <addressOffset>0x4000607E</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_BUF_SIZE</name>
- <description>Dedicated Endpoint Buffer Size Register</description>
- <addressOffset>0x4000608C</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_EP_ACTIVE</name>
- <description>Endpoint Active Indication Register</description>
- <addressOffset>0x4000608E</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>USBFS_EP_TYPE</name>
- <description>Endpoint Type (IN/OUT) Indication</description>
- <addressOffset>0x4000608F</addressOffset>
- <size>8</size>
+ <name>Debug_Timer_PERIOD</name>
+ <description>TMRx.PER0 - Assigned Period</description>
+ <addressOffset>0x40004F04</addressOffset>
+ <size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
- <name>USBFS_USB_CLK_EN</name>
- <description>USB Block Clock Enable Register</description>
- <addressOffset>0x4000609D</addressOffset>
- <size>8</size>
+ <name>Debug_Timer_COUNTER</name>
+ <description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
+ <addressOffset>0x40004F06</addressOffset>
+ <size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<peripheral>
<name>SCSI_Out_Ctl</name>
<description>No description available</description>
- <baseAddress>0x40006470</baseAddress>
+ <baseAddress>0x40006478</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
<peripheral>
<name>SCSI_Out_Bits</name>
<description>No description available</description>
- <baseAddress>0x40006478</baseAddress>
+ <baseAddress>0x4000647B</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x0</size>
{
CONFIG_ENABLE_UNIT_ATTENTION = 1,
CONFIG_ENABLE_PARITY = 2,
+ CONFIG_ENABLE_SCSI2 = 4
} CONFIG_FLAGS;
typedef enum
config.deviceType = CONFIG_FIXED;
// Default to maximum fail-safe options.
- config.flags = 0;// CONFIG_ENABLE_PARITY | CONFIG_ENABLE_UNIT_ATTENTION;
+ config.flags = 0;
config.deviceTypeModifier = 0;
config.sdSectorStart = 0;
(config.flags & CONFIG_ENABLE_PARITY ? "true" : "false") <<
"</parity>\n" <<
+ " <!-- Only set to true when using with a fast SCSI2 host\n " <<
+ " controller. This can cause problems with older/slower\n" <<
+ " hardware.-->\n" <<
+ " <enableScsi2>" <<
+ (config.flags & CONFIG_ENABLE_SCSI2 ? "true" : "false") <<
+ "</enableScsi2>\n" <<
+
"\n" <<
" <!-- ********************************************************\n" <<
" Space separated list. Available options:\n" <<
result.scsiId = result.scsiId & ~CONFIG_TARGET_ENABLED;
}
}
- if (child->GetName() == "unitAttention")
+ else if (child->GetName() == "unitAttention")
{
std::string s(child->GetNodeContent().mb_str());
if (s == "true")
result.flags = result.flags & ~CONFIG_ENABLE_UNIT_ATTENTION;
}
}
- if (child->GetName() == "parity")
+ else if (child->GetName() == "parity")
{
std::string s(child->GetNodeContent().mb_str());
if (s == "true")
result.flags = result.flags & ~CONFIG_ENABLE_PARITY;
}
}
+ else if (child->GetName() == "enableScsi2")
+ {
+ std::string s(child->GetNodeContent().mb_str());
+ if (s == "true")
+ {
+ result.flags |= CONFIG_ENABLE_SCSI2;
+ }
+ else
+ {
+ result.flags = result.flags & ~CONFIG_ENABLE_SCSI2;
+ }
+ }
else if (child->GetName() == "quirks")
{
std::stringstream s(std::string(child->GetNodeContent().mb_str()));
myNumSectorValidator(new wxIntegerValidator<uint32_t>),
mySizeValidator(new wxFloatingPointValidator<float>(2))
{
- wxFlexGridSizer *fgs = new wxFlexGridSizer(13, 3, 9, 25);
+ wxFlexGridSizer *fgs = new wxFlexGridSizer(14, 3, 9, 25);
fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
myEnableCtrl =
this,
ID_parityCtrl,
wxT("Enable Parity"));
+ myParityCtrl->SetToolTip(wxT("Enable to require valid SCSI parity bits when receiving data. Some hosts don't provide parity. SCSI2SD always outputs valid parity bits."));
fgs->Add(myParityCtrl);
fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
Bind(wxEVT_CHECKBOX, &TargetPanel::onInput<wxCommandEvent>, this, ID_parityCtrl);
this,
ID_unitAttCtrl,
wxT("Enable Unit Attention"));
-
+ myUnitAttCtrl->SetToolTip(wxT("Enable this to inform the host of changes after hot-swapping SD cards. Causes problems with Mac Plus."));
fgs->Add(myUnitAttCtrl);
fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
Bind(wxEVT_CHECKBOX, &TargetPanel::onInput<wxCommandEvent>, this, ID_unitAttCtrl);
+ fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
+ myScsi2Ctrl =
+ new wxCheckBox(
+ this,
+ ID_scsi2Ctrl,
+ wxT("Enable SCSI2 Mode"));
+ myScsi2Ctrl->SetToolTip(wxT("Enable high-performance mode. May cause problems with SASI/SCSI1 hosts."));
+ fgs->Add(myScsi2Ctrl);
+ fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
+ Bind(wxEVT_CHECKBOX, &TargetPanel::onInput<wxCommandEvent>, this, ID_scsi2Ctrl);
+
fgs->Add(new wxStaticText(this, wxID_ANY, wxT("SD card start sector")));
wxWrapSizer* startContainer = new wxWrapSizer();
myStartSDSectorCtrl =
myDeviceTypeCtrl->Enable(enabled);
myParityCtrl->Enable(enabled);
myUnitAttCtrl->Enable(enabled);
+ myScsi2Ctrl->Enable(enabled);
myStartSDSectorCtrl->Enable(enabled && !myAutoStartSectorCtrl->IsChecked());
myAutoStartSectorCtrl->Enable(enabled);
mySectorSizeCtrl->Enable(enabled);
config.flags =
(myParityCtrl->IsChecked() ? CONFIG_ENABLE_PARITY : 0) |
- (myUnitAttCtrl->IsChecked() ? CONFIG_ENABLE_UNIT_ATTENTION : 0);
+ (myUnitAttCtrl->IsChecked() ? CONFIG_ENABLE_UNIT_ATTENTION : 0) |
+ (myScsi2Ctrl->IsChecked() ? CONFIG_ENABLE_SCSI2 : 0);
auto startSDSector = CtrlGetValue<uint32_t>(myStartSDSectorCtrl);
config.sdSectorStart = startSDSector.first;
myParityCtrl->SetValue(config.flags & CONFIG_ENABLE_PARITY);
myUnitAttCtrl->SetValue(config.flags & CONFIG_ENABLE_UNIT_ATTENTION);
+ myScsi2Ctrl->SetValue(config.flags & CONFIG_ENABLE_SCSI2);
{
std::stringstream ss; ss << config.sdSectorStart;
ID_deviceTypeCtrl,
ID_parityCtrl,
ID_unitAttCtrl,
+ ID_scsi2Ctrl,
ID_startSDSectorCtrl,
ID_autoStartSectorCtrl,
ID_sectorSizeCtrl,
wxCheckBox* myParityCtrl;
wxCheckBox* myUnitAttCtrl;
+ wxCheckBox* myScsi2Ctrl;
wxIntegerValidator<uint32_t>* myStartSDSectorValidator;
wxTextCtrl* myStartSDSectorCtrl;
{
public:
AppFrame() :
- wxFrame(NULL, wxID_ANY, "scsi2sd-util", wxPoint(50, 50), wxSize(600, 650)),
+ wxFrame(NULL, wxID_ANY, "scsi2sd-util", wxPoint(50, 50), wxSize(600, 700)),
myInitialConfig(false),
myTickCounter(0),
myLastPollTime(0)
}
}
sdSectors.push_back(sdSectorRange);
- autoStartSector = sdSectorRange.second + 1;
+ autoStartSector = sdSectorRange.second;
}
else
{
" row " << (flashRow + j);
mmLogStatus(ss.str());
currentProgress += 1;
+ if (currentProgress == totalProgress)
+ {
+ ss.str("Load Complete.");
+ mmLogStatus("Load Complete.");
+ }
+
if (!progress->Update(
(100 * currentProgress) / totalProgress,
ss.str()
}
myInitialConfig = true;
- mmLogStatus("Load Complete");
- while (progress->Update(100, "Load Complete"))
- {
- // Wait for the user to click "Close"
- wxMilliSleep(50);
- }
goto out;
err:
mmLogStatus("Load failed");
- while (progress->Update(100, "Load failed"))
- {
- // Wait for the user to click "Close"
- wxMilliSleep(50);
- }
+ progress->Update(100, "Load failed");
goto out;
abort:
" row " << (flashRow + j);
mmLogStatus(ss.str());
currentProgress += 1;
+
+ if (currentProgress == totalProgress)
+ {
+ ss.str("Save Complete.");
+ mmLogStatus("Save Complete.");
+ }
if (!progress->Update(
(100 * currentProgress) / totalProgress,
ss.str()
myHID->enterBootloader();
myHID.reset();
- mmLogStatus("Save Complete");
- while (progress->Update(100, "Save Complete"))
- {
- // Wait for the user to click "Close"
- wxMilliSleep(50);
- }
+
goto out;
err:
mmLogStatus("Save failed");
- while (progress->Update(100, "Save failed"))
- {
- // Wait for the user to click "Close"
- wxMilliSleep(50);
- }
+ progress->Update(100, "Save failed");
goto out;
abort:
projects / SCSI2SD.git / commitdiff