Save a cycle in fpga memory interface

diff --git a/CHANGELOG b/CHANGELOG
index 92cf01db7feba301c87eb317e5d400d1cd6e3892..6af0a6109afa840ca347dc2892ff261176f96cbb 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,4 +1,5 @@
-201705XX               6.1.1
+20170520               6.1.1
+       - Performance improvements to improve throughput at all scsi speeds
        - Add new "turbo" speed option to boost speeds.
                - May not be reliable, and use is not supported.
                - Async timings trimmed

diff --git a/STM32CubeMX/SCSI2SD-V6/Src/fsmc.c b/STM32CubeMX/SCSI2SD-V6/Src/fsmc.c
index 8a7bf907b09ba696ba8642b872de2a6037a8da02..1e200f7ce64b24d02f6401103d76187ecc32eb72 100755 (executable)
--- a/STM32CubeMX/SCSI2SD-V6/Src/fsmc.c
+++ b/STM32CubeMX/SCSI2SD-V6/Src/fsmc.c
@@ -71,8 +71,15 @@ void MX_FSMC_Init(void)
   Timing.AddressSetupTime = 2;
   Timing.AddressHoldTime = 1;
 
-  // 1 for synchroniser skew, 1 to skip hold time, 1 to process read, 1 to output
-  Timing.DataSetupTime = 5;//4 doesn't work ? ?? ?
+  // Writes to device:
+  //   1 for synchroniser skew (dbx also delayed)
+  //   1 to skip hold time
+  //   1 to write data.
+
+  // Reads from device:
+  //   3 for syncroniser
+  //   1 to write back to fsmc bus.
+  Timing.DataSetupTime = 4;
 
   // Allow a clock for us to release signals, plus 3 for the synchroniser to
   // realise the cycle has ended. Need to avoid both devices acting as outputs

diff --git a/rtl/fpga_bitmap.o b/rtl/fpga_bitmap.o
index c535bdbd2776567e28eb6c23d61000ac3b2ae2f6..aa8447bf1e496a1cf2d12df11701fc359736f2f9 100644 (file)
Binary files a/rtl/fpga_bitmap.o and b/rtl/fpga_bitmap.o differ

diff --git a/src/firmware/scsiPhy.c b/src/firmware/scsiPhy.c
index 58d56f66a69b030a7deedfa1ccfd4a6e49add03c..d0e7002851756d3782d91c97bf64eecb11e50a6b 100755 (executable)
--- a/src/firmware/scsiPhy.c
+++ b/src/firmware/scsiPhy.c
@@ -594,7 +594,7 @@ void scsiPhyReset()
        scsiSetDefaultTiming();\r
 \r
        // DMA Benchmark code\r
-       // Currently 11MB/s.\r
+       // Currently 14.9MB/s.\r
        #ifdef DMA_BENCHMARK\r
        while(1)\r
        {\r
@@ -770,8 +770,11 @@ int scsiSelfTest()
                return 32;\r
        }\r
        *SCSI_CTRL_BSY = 1;\r
+       s2s_delay_ms(1);\r
        if (! scsiStatusBSY())\r
        {\r
+               *SCSI_CTRL_BSY = 0;\r
+\r
                // Error, BSY doesn't work.\r
                return 32;\r
        }\r
@@ -851,7 +854,6 @@ int scsiSelfTest()
        }\r
        */\r
 \r
-\r
        // FPGA comms test code\r
        for(i = 0; i < 10000; ++i)\r
        {\r