Fixed parity handling to respect the --no-parity config option.

- Automatically disable parity checks for old SASI/SCSI1 hosts.
- Add scsi disconnect/reconnect support for long SD card writes.

diff --git a/CHANGELOG b/CHANGELOG
index bd1346d99c6d422b3ea6df3988dd41e54009beb2..642d483433051423552bf55768a8ba6462825bd7 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -4,6 +4,7 @@
        multiple devices on the SCSI bus.
        - Re-add parity checking. This can be disabled using scsi2sd-config if
        required.
+       - Added disconnect/reconnect support during SD card writes.
 
 20140718               3.5.2
        - Fix blank SCSI ID in scsi2sd-config output.

diff --git a/readme.txt b/readme.txt
index 01881525edd07e45c34cec20fa045ecb28907d28..e39deee694e74a551fd0c37eecbfd49c711b6055 100644 (file)
--- a/readme.txt
+++ b/readme.txt
@@ -73,6 +73,9 @@ Compatibility
     Microvax 3100 Model 80 running VMS 7.3 (needs patch against v3.5.2 firmware) 
     Amiga 500+ with GVP A530
     Atari TT030 System V 
+    Atari MEGA STE
+        needs J3 TERMPWR jumper
+        1GB limit (--blocks=2048000)
 
 Samplers
 
@@ -93,5 +96,5 @@ Samplers
 
 Other
 
-    HP 16601A logic analyzer
+    HP 16601A, 16700A logic analyzers
     Fluke 9100 series 

diff --git a/software/SCSI2SD/src/disk.c b/software/SCSI2SD/src/disk.c
index d0f93ba7f52d0770a1bb7cf89c7f938830254765..965cee4d41bcf1911fe9383a861625007dc94a94 100755 (executable)
--- a/software/SCSI2SD/src/disk.c
+++ b/software/SCSI2SD/src/disk.c
@@ -22,6 +22,7 @@
 #include "config.h"\r
 #include "disk.h"\r
 #include "sd.h"\r
+#include "time.h"\r
 \r
 #include <string.h>\r
 \r
@@ -56,7 +57,7 @@ static void doFormatUnitSkipData(int bytes)
        int i;\r
        for (i = 0; i < bytes; ++i)\r
        {\r
-               scsiReadByte(); \r
+               scsiReadByte();\r
        }\r
 }\r
 \r
@@ -80,7 +81,7 @@ static void doFormatUnitHeader(void)
 {\r
        int IP = (scsiDev.data[1] & 0x08) ? 1 : 0;\r
        int DSP = (scsiDev.data[1] & 0x04) ? 1 : 0;\r
-       \r
+\r
        if (! DSP) // disable save parameters\r
        {\r
                configSave(); // Save the "MODE SELECT savable parameters"\r
@@ -520,15 +521,18 @@ void scsiDiskPoll()
                transfer.currentBlock != transfer.blocks)\r
        {\r
                scsiEnterPhase(DATA_OUT);\r
-               \r
+\r
                int totalSDSectors = transfer.blocks * SDSectorsPerSCSISector();\r
                int buffers = sizeof(scsiDev.data) / SD_SECTOR_SIZE;\r
                int prep = 0;\r
                int i = 0;\r
+               int scsiDisconnected = 0;\r
+               volatile uint32_t lastActivityTime = getTime_ms();\r
                int scsiActive = 0;\r
                int sdActive = 0;\r
+               \r
                while ((i < totalSDSectors) &&\r
-                       (scsiDev.phase == DATA_OUT) &&\r
+                       (scsiDev.phase == DATA_OUT) && // scsiDisconnect keeps our phase.\r
                        !scsiDev.resetFlag)\r
                {\r
                        if ((sdActive == 1) && sdWriteSectorDMAPoll())\r
@@ -547,8 +551,12 @@ void scsiDiskPoll()
                        {\r
                                scsiActive = 0;\r
                                ++prep;\r
+                               lastActivityTime = getTime_ms();\r
                        }\r
-                       else if ((scsiActive == 0) && ((prep - i) < buffers) && (prep < totalSDSectors))\r
+                       else if ((scsiActive == 0) &&\r
+                               ((prep - i) < buffers) &&\r
+                               (prep < totalSDSectors) &&\r
+                               !scsiDisconnected)\r
                        {\r
                                int dmaBytes = SD_SECTOR_SIZE;\r
                                if (prep % SDSectorsPerSCSISector() == SDSectorsPerSCSISector() - 1)\r
@@ -559,11 +567,62 @@ void scsiDiskPoll()
                                scsiReadDMA(&scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)], dmaBytes);\r
                                scsiActive = 1;\r
                        }\r
+                       else if (\r
+                               (scsiActive == 0) &&\r
+                               !scsiDisconnected &&\r
+                               scsiDev.discPriv &&\r
+                               (diffTime_ms(lastActivityTime, getTime_ms()) >= 20) &&\r
+                               (scsiDev.phase == DATA_OUT))\r
+                       {\r
+                               // We're transferring over the SCSI bus faster than the SD card\r
+                               // can write.  There is no more buffer space once we've finished\r
+                               // this SCSI transfer.\r
+                               // The NCR 53C700 interface chips have a 250ms "byte-to-byte"\r
+                               // timeout buffer. SD card writes are supposed to complete\r
+                               // within 200ms, but sometimes they don't.\r
+                               // The NCR 53C700 series is used on HP 9000 workstations.\r
+                               scsiDisconnect();\r
+                               scsiDisconnected = 1;\r
+                               lastActivityTime = getTime_ms();\r
+                       }\r
+                       else if (scsiDisconnected &&\r
+                               (\r
+                                       (prep == i) || // Buffers empty.\r
+                                       // Send some messages every 100ms so we don't timeout.\r
+                                       // At a minimum, a reselection involves an IDENTIFY message.\r
+                                       (diffTime_ms(lastActivityTime, getTime_ms()) >= 100)\r
+                               ))\r
+                       {\r
+                               int reconnected = scsiReconnect();\r
+                               if (reconnected)\r
+                               {\r
+                                       scsiDisconnected = 0;\r
+                                       lastActivityTime = getTime_ms(); // Don't disconnect immediately.\r
+                               }\r
+                               else if (diffTime_ms(lastActivityTime, getTime_ms()) >= 10000)\r
+                               {\r
+                                       // Give up after 10 seconds of trying to reconnect.\r
+                                       scsiDev.resetFlag = 1;\r
+                               }\r
+                       }\r
                }\r
-               \r
+\r
+               while (\r
+                       !scsiDev.resetFlag &&\r
+                       scsiDisconnected &&\r
+                       (diffTime_ms(lastActivityTime, getTime_ms()) <= 10000))\r
+               {\r
+                       scsiDisconnected = !scsiReconnect();\r
+               }\r
+               if (scsiDisconnected)\r
+               {\r
+                       // Failed to reconnect\r
+                       scsiDev.resetFlag = 1;\r
+               }\r
+\r
                if (scsiDev.phase == DATA_OUT)\r
                {\r
-                       if (scsiDev.parityError)\r
+                       if (scsiDev.parityError && config->enableParity && !scsiDev.compatMode)\r
                        {\r
                                scsiDev.sense.code = ABORTED_COMMAND;\r
                                scsiDev.sense.asc = SCSI_PARITY_ERROR;\r

diff --git a/software/SCSI2SD/src/main.c b/software/SCSI2SD/src/main.c
index 779f112fd493211e85f760e9dbe8fa97701ecbac..35e3bf7ce06f1f2f670ef0e826f8bd09c11d3c5a 100755 (executable)
--- a/software/SCSI2SD/src/main.c
+++ b/software/SCSI2SD/src/main.c
@@ -21,11 +21,13 @@
 #include "config.h"\r
 #include "disk.h"\r
 #include "led.h"\r
+#include "time.h"\r
 \r
 const char* Notice = "Copyright (C) 2014 Michael McMaster <michael@codesrc.com>";\r
 \r
 int main()\r
 {\r
+       timeInit();\r
        ledInit();\r
 \r
        // Enable global interrupts.\r

diff --git a/software/SCSI2SD/src/scsi.c b/software/SCSI2SD/src/scsi.c
index eb0972113af99f41f4b880cc5f99dd84ef9e490e..8d642702960e0fef69333e4469305fd3370084cd 100755 (executable)
--- a/software/SCSI2SD/src/scsi.c
+++ b/software/SCSI2SD/src/scsi.c
@@ -26,6 +26,7 @@
 #include "led.h"\r
 #include "mode.h"\r
 #include "disk.h"\r
+#include "time.h"\r
 \r
 #include <string.h>\r
 \r
@@ -197,7 +198,7 @@ static void process_DataOut()
                scsiRead(scsiDev.data + scsiDev.dataPtr, len);\r
                scsiDev.dataPtr += len;\r
 \r
-               if (scsiDev.parityError && config->enableParity)\r
+               if (scsiDev.parityError && config->enableParity && !scsiDev.compatMode)\r
                {\r
                        scsiDev.sense.code = ABORTED_COMMAND;\r
                        scsiDev.sense.asc = SCSI_PARITY_ERROR;\r
@@ -255,7 +256,7 @@ static void process_Command()
                memset(scsiDev.cdb, 0xff, sizeof(scsiDev.cdb));\r
                return;\r
        }\r
-       else if (scsiDev.parityError)\r
+       else if (scsiDev.parityError && config->enableParity && !scsiDev.compatMode)\r
        {\r
                scsiDev.sense.code = ABORTED_COMMAND;\r
                scsiDev.sense.asc = SCSI_PARITY_ERROR;\r
@@ -464,6 +465,8 @@ static void enter_SelectionPhase()
        scsiDev.status = GOOD;\r
        scsiDev.phase = SELECTION;\r
        scsiDev.lun = -1;\r
+       scsiDev.discPriv = 0;\r
+       scsiDev.compatMode = 0;\r
 \r
        transfer.blocks = 0;\r
        transfer.currentBlock = 0;\r
@@ -481,21 +484,26 @@ static void process_SelectionPhase()
        uint8 mask = scsiReadDBxPins();\r
        int maskBitCount = countBits(mask);\r
        int goodParity = (Lookup_OddParity[mask] == SCSI_ReadPin(SCSI_In_DBP));\r
+       int atnFlag = SCSI_ReadFilt(SCSI_Filt_ATN);\r
 \r
        if (!bsy && sel &&\r
                (mask & scsiDev.scsiIdMask) &&\r
-               (goodParity || !config->enableParity) && (maskBitCount <= 2))\r
+               (goodParity || !config->enableParity || !atnFlag) &&\r
+               (maskBitCount <= 2))\r
        {\r
                // Do we enter MESSAGE OUT immediately ? SCSI 1 and 2 standards says\r
                // move to MESSAGE OUT if ATN is true before we assert BSY.\r
                // The initiator should assert ATN with SEL.\r
-               scsiDev.atnFlag = SCSI_ReadFilt(SCSI_Filt_ATN);\r
-               \r
-               // Unit attention breaks many older SCSI hosts. Disable it completely for\r
-               // SCSI-1 (and older) hosts, regardless of our configured setting.\r
+               scsiDev.atnFlag = atnFlag;\r
+\r
+               // Unit attention breaks many older SCSI hosts. Disable it completely\r
+               // for SCSI-1 (and older) hosts, regardless of our configured setting.\r
+               // Enable the compatability mode also as many SASI and SCSI1\r
+               // controllers don't generate parity bits.\r
                if (!scsiDev.atnFlag)\r
                {\r
                        scsiDev.unitAttention = 0;\r
+                       scsiDev.compatMode = 1;\r
                }\r
 \r
                // We've been selected!\r
@@ -557,7 +565,7 @@ static void process_MessageOut()
        scsiDev.msgOut = scsiReadByte();\r
        scsiDev.msgCount++;\r
 \r
-       if (scsiDev.parityError)\r
+       if (scsiDev.parityError && config->enableParity && !scsiDev.compatMode)\r
        {\r
                // Skip the remaining message bytes, and then start the MESSAGE_OUT\r
                // phase again from the start. The initiator will re-send the\r
@@ -630,7 +638,6 @@ static void process_MessageOut()
        else if (scsiDev.msgOut & 0x80) // 0x80 -> 0xFF\r
        {\r
                // IDENTIFY\r
-               // We don't disconnect, so ignore disconnect privilege.\r
                if ((scsiDev.msgOut & 0x18) || // Reserved bits set.\r
                        (scsiDev.msgOut & 0x20))  // We don't have any target routines!\r
                {\r
@@ -638,7 +645,9 @@ static void process_MessageOut()
                }\r
 \r
                scsiDev.lun = scsiDev.msgOut & 0x7;\r
-               //scsiDev.allowDisconnect = scsiDev.msgOut & 0x40;\r
+               scsiDev.discPriv =\r
+                       ((scsiDev.msgOut & 0x40) && (scsiDev.initiatorId >= 0))\r
+                               ? 1 : 0;\r
        }\r
        else if (scsiDev.msgOut >= 0x20 && scsiDev.msgOut <= 0x2F)\r
        {\r
@@ -811,3 +820,105 @@ void scsiInit()
        scsiDev.unitAttention = POWER_ON_RESET;\r
 }\r
 \r
+void scsiDisconnect()\r
+{\r
+       scsiEnterPhase(MESSAGE_IN);\r
+       scsiWriteByte(0x02); // save data pointer\r
+       scsiWriteByte(0x04); // disconnect msg.\r
+\r
+       // For now, the caller is responsible for tracking the disconnected\r
+       // state, and calling scsiReconnect.\r
+       // Ideally the client would exit their loop and we'd implement this\r
+       // as part of scsiPoll\r
+       int phase = scsiDev.phase;\r
+       enter_BusFree();\r
+       scsiDev.phase = phase;\r
+}\r
+\r
+int scsiReconnect()\r
+{\r
+       int reconnected = 0;\r
+\r
+       int sel = SCSI_ReadFilt(SCSI_Filt_SEL);\r
+       int bsy = SCSI_ReadFilt(SCSI_Filt_BSY);\r
+       if (!sel && !bsy)\r
+       {\r
+               CyDelayUs(1);\r
+               sel = SCSI_ReadFilt(SCSI_Filt_SEL);\r
+               bsy = SCSI_ReadFilt(SCSI_Filt_BSY);\r
+       }\r
+\r
+       if (!sel && !bsy)\r
+       {\r
+               // Arbitrate.\r
+               ledOn();\r
+               SCSI_Out_Bits_Write(scsiDev.scsiIdMask);\r
+               SCSI_Out_Ctl_Write(1); // Write bits manually.\r
+               SCSI_SetPin(SCSI_Out_BSY);\r
+\r
+               CyDelayUs(3); // arbitrate delay. 2.4us.\r
+\r
+               uint8_t dbx = scsiReadDBxPins();\r
+               sel = SCSI_ReadFilt(SCSI_Filt_SEL);\r
+               if (sel || ((dbx ^ scsiDev.scsiIdMask) > scsiDev.scsiIdMask))\r
+               {\r
+                       // Lost arbitration.\r
+                       SCSI_Out_Ctl_Write(0);\r
+                       SCSI_ClearPin(SCSI_Out_BSY);\r
+                       ledOff();\r
+               }\r
+               else\r
+               {\r
+                       // Won arbitration\r
+                       SCSI_SetPin(SCSI_Out_SEL);\r
+                       CyDelayUs(1); // Bus clear + Bus settle.\r
+\r
+                       // Reselection phase\r
+                       SCSI_CTL_PHASE_Write(__scsiphase_io);\r
+                       SCSI_Out_Bits_Write(scsiDev.scsiIdMask | (1 << scsiDev.initiatorId));\r
+                       scsiDeskewDelay(); // 2 deskew delays\r
+                       scsiDeskewDelay(); // 2 deskew delays\r
+                       SCSI_ClearPin(SCSI_Out_BSY);\r
+                       CyDelayUs(1);  // Bus Settle Delay\r
+\r
+                       uint32_t waitStart_ms = getTime_ms();\r
+                       bsy = SCSI_ReadFilt(SCSI_Filt_BSY);\r
+                       // Wait for initiator.\r
+                       while (\r
+                               !bsy &&\r
+                               !scsiDev.resetFlag &&\r
+                               (diffTime_ms(waitStart_ms, getTime_ms()) < 250))\r
+                       {\r
+                               bsy = SCSI_ReadFilt(SCSI_Filt_BSY);\r
+                       }\r
+\r
+                       if (bsy)\r
+                       {\r
+                               SCSI_SetPin(SCSI_Out_BSY);\r
+                               scsiDeskewDelay(); // 2 deskew delays\r
+                               scsiDeskewDelay(); // 2 deskew delays\r
+                               SCSI_ClearPin(SCSI_Out_SEL);\r
+\r
+                               // Prepare for the initial IDENTIFY message.\r
+                               SCSI_Out_Ctl_Write(0);\r
+                               scsiEnterPhase(MESSAGE_IN);\r
+\r
+                               // Send identify command\r
+                               scsiWriteByte(0x80);\r
+\r
+                               scsiEnterPhase(scsiDev.phase);\r
+                               reconnected = 1;\r
+                       }\r
+                       else\r
+                       {\r
+                               // reselect timeout.\r
+                               SCSI_Out_Ctl_Write(0);\r
+                               SCSI_ClearPin(SCSI_Out_SEL);\r
+                               SCSI_CTL_PHASE_Write(0);\r
+                               ledOff();\r
+                       }\r
+               }\r
+       }\r
+       return reconnected;\r
+}\r
+\r

diff --git a/software/SCSI2SD/src/scsi.h b/software/SCSI2SD/src/scsi.h
index b0f5b8435f9188698aec81b74a374c3e10b97372..26e8930059c2b07103b03c12ab17be5df4c61805 100755 (executable)
--- a/software/SCSI2SD/src/scsi.h
+++ b/software/SCSI2SD/src/scsi.h
@@ -85,6 +85,8 @@ typedef struct
        uint8 cdb[12]; // command descriptor block
        uint8 cdbLen; // 6, 10, or 12 byte message.
        int8 lun; // Target lun, set by IDENTIFY message.
+       uint8 discPriv; // Disconnect priviledge.
+       uint8_t compatMode; // true for SCSI1 and SASI hosts.
 
        // Only let the reserved initiator talk to us.
        // A 3rd party may be sending the RESERVE/RELEASE commands
@@ -93,7 +95,7 @@ typedef struct
        int reserverId; // 0 -> 7 if reserved. -1 if not reserved.
 
        // SCSI_STATUS value.
-       // Change to SCSI_STATUS_CHECK_CONDITION when setting a SENSE value
+       // Change to CHECK_CONDITION when setting a SENSE value
        uint8 status;
 
        ScsiSense sense;
@@ -118,6 +120,7 @@ extern ScsiDevice scsiDev;
 
 void scsiInit(void);
 void scsiPoll(void);
-
+void scsiDisconnect(void);
+int scsiReconnect(void);
 
 #endif

diff --git a/software/SCSI2SD/src/scsiPhy.h b/software/SCSI2SD/src/scsiPhy.h
index 97e5f4522a4eb5d7100c5983aaa138848ea83aeb..bee298713d1afda75cf2784d05c472fc6b0a7a20 100755 (executable)
--- a/software/SCSI2SD/src/scsiPhy.h
+++ b/software/SCSI2SD/src/scsiPhy.h
@@ -60,6 +60,10 @@ enum FilteredInputs
 #define SCSI_ReadFilt(filt) \
        ((SCSI_Filtered_Read() & (filt)) == 0)
 
+// SCSI delays, as referenced to the cpu clock
+#define CPU_CLK_PERIOD_NS (1000000000U / BCLK__BUS_CLK__HZ)
+#define scsiDeskewDelay() CyDelayCycles((55 / CPU_CLK_PERIOD_NS) + 1)
+
 // Contains the odd-parity flag for a given 8-bit value.
 extern const uint8_t Lookup_OddParity[256];
 

diff --git a/software/SCSI2SD/src/time.c b/software/SCSI2SD/src/time.c
new file mode 100755 (executable)
index 0000000..3880a9d
--- /dev/null
+++ b/software/SCSI2SD/src/time.c
@@ -0,0 +1,56 @@
+//     Copyright (C) 2014 Michael McMaster <michael@codesrc.com>
+//
+//     This file is part of SCSI2SD.
+//
+//     SCSI2SD is free software: you can redistribute it and/or modify
+//     it under the terms of the GNU General Public License as published by
+//     the Free Software Foundation, either version 3 of the License, or
+//     (at your option) any later version.
+//
+//     SCSI2SD is distributed in the hope that it will be useful,
+//     but WITHOUT ANY WARRANTY; without even the implied warranty of
+//     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//     GNU General Public License for more details.
+//
+//     You should have received a copy of the GNU General Public License
+//     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+
+#include "time.h"
+#include "limits.h"
+
+static volatile uint32_t counter = 0;
+
+CY_ISR_PROTO(TickISR);
+CY_ISR(TickISR)
+{
+       // Should be atomic at 32bit word size. Limits runtime to 49 days.
+       ++counter;
+}
+
+void timeInit()
+{
+       // Interrupt 15. SysTick_IRQn is -1.
+       // The SysTick timer is integrated into the Arm Cortex M3
+       CyIntSetSysVector((SysTick_IRQn + 16), TickISR);
+
+       // Ensure the cycle count is < 24bit.
+       // At 50MHz bus clock, counter is 50000.
+       SysTick_Config((BCLK__BUS_CLK__HZ + 999u) / 1000u);
+}
+
+uint32_t getTime_ms()
+{
+       return counter;
+}
+
+uint32_t diffTime_ms(uint32_t start, uint32_t end)
+{
+       if (end >= start)
+       {
+               return  end - start;
+       }
+       else
+       {
+               return (UINT_MAX - start) + end;
+       }
+}

diff --git a/software/SCSI2SD/src/time.h b/software/SCSI2SD/src/time.h
new file mode 100755 (executable)
index 0000000..69b88eb
--- /dev/null
+++ b/software/SCSI2SD/src/time.h
@@ -0,0 +1,26 @@
+//     Copyright (C) 2014 Michael McMaster <michael@codesrc.com>
+//
+//     This file is part of SCSI2SD.
+//
+//     SCSI2SD is free software: you can redistribute it and/or modify
+//     it under the terms of the GNU General Public License as published by
+//     the Free Software Foundation, either version 3 of the License, or
+//     (at your option) any later version.
+//
+//     SCSI2SD is distributed in the hope that it will be useful,
+//     but WITHOUT ANY WARRANTY; without even the implied warranty of
+//     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//     GNU General Public License for more details.
+//
+//     You should have received a copy of the GNU General Public License
+//     along with SCSI2SD.  If not, see <http://www.gnu.org/licenses/>.
+#ifndef TIME_H
+#define TIME_H
+
+#include "device.h"
+
+void timeInit(void);
+uint32_t getTime_ms(void); // Returns milliseconds since init
+uint32_t diffTime_ms(uint32_t start, uint32_t end);
+
+#endif

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml
index b2b424aacdc9ca8352c42e8933081bd7b51dc3f7..53af611f8cc932c3d67b7ea465b9890c5d39e96b 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml
@@ -18,7 +18,7 @@
       <Tool Name="postbuild" Command="" Options="" />
     </Toolchain>
   </Toolchains>
-  <Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" Version="4.0" Type="Bootloadable">
+  <Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" Version="4.0" Type="Bootloadable">
     <CMSIS_SVD_File>SCSI2SD.svd</CMSIS_SVD_File>
     <Datasheet />
     <LinkerFiles>
@@ -27,8 +27,8 @@
       <LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile>
     </LinkerFiles>
     <Folders>
-      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\src">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
+      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\src">
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="">..\..\src\main.c</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\diagnostic.c</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\disk.c</File>
@@ -41,6 +41,7 @@
           <File BuildType="BUILD" Toolchain="">..\..\src\sd.c</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\config.c</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\led.c</File>
+          <File BuildType="BUILD" Toolchain="">..\..\src\time.c</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\diagnostic.h</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\disk.h</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\geometry.h</File>
@@ -53,15 +54,16 @@
           <File BuildType="BUILD" Toolchain="">..\..\src\bits.h</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\sd.h</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\config.h</File>
+          <File BuildType="BUILD" Toolchain="">..\..\src\time.h</File>
         </Files>
       </Folder>
-      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
+      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="">.\device.h</File>
         </Files>
       </Folder>
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn\Generated_Source\PSoC5">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn\Generated_Source\PSoC5">
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.h</File>
           <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.c</File>
           <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevice.h</File>
@@ -209,41 +211,41 @@
           <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\libelf.dll</File>
         </Files>
       </Folder>
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_GCC">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_GCC">
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="ARM GCC">.\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a</File>
         </Files>
       </Folder>
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a</File>
         </Files>
       </Folder>
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn\Generated_Source\PSoC5\IAR">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn\Generated_Source\PSoC5\IAR">
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="IAR">.\Generated_Source\PSoC5\IAR\CyComponentLibrary.a</File>
         </Files>
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\codegentemp">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_441">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_473">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\DP8051_Keil_951">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\DP8051">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\CortexM0">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\CortexM3">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
       </Folder>
     </Folders>
   </Project>

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit
index a39399e55c2624b81947273080306daa7f52f0b8..514a296728696e877545285e78d12ee098e55ddf 100644 (file)
Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit differ

diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj
index 9e13a8a7834cecf3de104687fad17b562d6a3a5a..9c35e69dfb933c3d6390a7ee01b8fc4ec0687df5 100755 (executable)
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyprj
@@ -102,6 +102,13 @@
 <build_action v="C_FILE" />\r
 <PropertyDeltas />\r
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="time.c" persistent="..\..\src\time.c">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="C_FILE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
 </dependencies>\r
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
@@ -210,6 +217,13 @@
 <build_action v="NONE" />\r
 <PropertyDeltas />\r
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="time.h" persistent="..\..\src\time.h">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="NONE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
 </dependencies>\r
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r

diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml
index 7f621fb7a0f9ed2741c4298d5bf59adb1b07379e..6cfd4f26a372e42f0dd5ad56435098ea334d2438 100755 (executable)
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml
@@ -18,7 +18,7 @@
       <Tool Name="postbuild" Command="" Options="" />\r
     </Toolchain>\r
   </Toolchains>\r
-  <Project Name="USB_Bootloader" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" Version="4.0" Type="Bootloader">\r
+  <Project Name="USB_Bootloader" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" Version="4.0" Type="Bootloader">\r
     <CMSIS_SVD_File>USB_Bootloader.svd</CMSIS_SVD_File>\r
     <Datasheet />\r
     <LinkerFiles>\r
@@ -27,13 +27,13 @@
       <LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile>\r
     </LinkerFiles>\r
     <Folders>\r
-      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">\r
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">\r
+      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">\r
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">\r
           <File BuildType="BUILD" Toolchain="">.\main.c</File>\r
         </Files>\r
       </Folder>\r
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5">\r
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">\r
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5">\r
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">\r
           <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.h</File>\r
           <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.c</File>\r
           <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cymetadata.c</File>\r
@@ -111,41 +111,41 @@
           <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\libelf.dll</File>\r
         </Files>\r
       </Folder>\r
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5\ARM_GCC">\r
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">\r
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5\ARM_GCC">\r
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">\r
           <File BuildType="BUILD" Toolchain="ARM GCC">.\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a</File>\r
         </Files>\r
       </Folder>\r
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">\r
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">\r
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">\r
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">\r
           <File BuildType="BUILD" Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a</File>\r
         </Files>\r
       </Folder>\r
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5\IAR">\r
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">\r
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5\IAR">\r
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn">\r
           <File BuildType="BUILD" Toolchain="IAR">.\Generated_Source\PSoC5\IAR\CyComponentLibrary.a</File>\r
         </Files>\r
       </Folder>\r
       <Folder BuildType="EXCLUDE" Path=".\codegentemp">\r
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />\r
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />\r
       </Folder>\r
       <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_441">\r
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />\r
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />\r
       </Folder>\r
       <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_473">\r
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />\r
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />\r
       </Folder>\r
       <Folder BuildType="EXCLUDE" Path=".\DP8051_Keil_951">\r
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />\r
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />\r
       </Folder>\r
       <Folder BuildType="EXCLUDE" Path=".\DP8051">\r
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />\r
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />\r
       </Folder>\r
       <Folder BuildType="EXCLUDE" Path=".\CortexM0">\r
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />\r
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />\r
       </Folder>\r
       <Folder BuildType="EXCLUDE" Path=".\CortexM3">\r
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />\r
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn" />\r
       </Folder>\r
     </Folders>\r
   </Project>\r

diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyfit b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyfit
index e16d539de8bd4f3816f4f7de6e392057322a2f13..aeeabb3544a8d8d0b42ab4b1f589f9341e32ec74 100644 (file)
Binary files a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyfit and b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyfit differ

diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000
index 7fd05fffd4e65824f68be73887f0cbe414eab2c7..42f3368ca9fbb3fd15c98eaa5f958e8be08574f9 100755 (executable)
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000
+++ b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000
@@ -1082,6 +1082,7 @@
 <name_val_pair name="Z:\projects\SCSI2SD\git-3.5\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />\r
 <name_val_pair name="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />\r
 <name_val_pair name="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />\r
+<name_val_pair name="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Release\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />\r
 </name>\r
 <name v="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3">\r
 <name_val_pair name=".\main.c" v="&quot;-I. &quot;&quot;-I./Generated_Source/PSoC5 &quot;&quot;-Wno-main &quot;&quot;-mcpu=cortex-m3 &quot;&quot;-mthumb &quot;&quot;-Wall &quot;&quot;-g &quot;&quot;-D &quot;&quot;DEBUG &quot;&quot;-Wa,-alh=${OutputDir}\${CompileFile}.lst &quot;&quot;-ffunction-sections &quot;" />\r
@@ -1115,7 +1116,7 @@
 <name_val_pair name="W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\CortexM3\ARM_GCC_473\Debug\USB_Bootloader.hex" v="&quot;-mthumb &quot;&quot;-march=armv7-m &quot;&quot;-mfix-cortex-m3-ldrd &quot;&quot;-T &quot;&quot;.\Generated_Source\PSoC5\cm3gcc.ld &quot;&quot;-g &quot;&quot;-Wl,-Map,${OutputDir}\${ProjectShortName}.map &quot;&quot;-specs=nano.specs &quot;&quot;-Wl,--gc-sections &quot;" />\r
 </name>\r
 </genericCmdLineData>\r
-<codeGenCmdLineTag v="&quot;-.appdatapath&quot; &quot;C:\Users\Micha_000\AppData\Local\Cypress Semiconductor\PSoC Creator\3.0&quot; &quot;-.fdsnotice&quot; &quot;-.fdswarpdepfile=warp_dependencies.txt&quot; &quot;-.fdselabdepfile=elab_dependencies.txt&quot; &quot;-.fdsbldfile=generated_files.txt&quot; &quot;-p&quot; &quot;Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj&quot; &quot;-d&quot; &quot;CY8C5267AXI-LP051&quot; &quot;-s&quot; &quot;Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5&quot; &quot;--&quot; &quot;-yv2&quot; &quot;-v3&quot; &quot;-ygs&quot; &quot;-q10&quot; &quot;-o2&quot; &quot;-.fftcfgtype=LE&quot; " />\r
+<codeGenCmdLineTag v="&quot;-.appdatapath&quot; &quot;C:\Users\Micha_000\AppData\Local\Cypress Semiconductor\PSoC Creator\3.0&quot; &quot;-.fdsnotice&quot; &quot;-.fdswarpdepfile=warp_dependencies.txt&quot; &quot;-.fdselabdepfile=elab_dependencies.txt&quot; &quot;-.fdsbldfile=generated_files.txt&quot; &quot;-p&quot; &quot;Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj&quot; &quot;-d&quot; &quot;CY8C5267AXI-LP051&quot; &quot;-s&quot; &quot;Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5&quot; &quot;--&quot; &quot;-yv2&quot; &quot;-v3&quot; &quot;-ygs&quot; &quot;-q10&quot; &quot;-o2&quot; &quot;-.fftcfgtype=LE&quot; " />\r
 </CyGuid_b0374e30-ce3a-47f2-ad85-821643292c68>\r
 </dataGuid>\r
 <dataGuid v="597c5b74-0c46-4204-8b7f-96f3570671dc">\r
@@ -1668,14 +1669,14 @@
 <v>C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif</v>\r
 <v>C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif</v>\r
 </warp_dep>\r
-<deps_time v="130537023991022657" />\r
+<deps_time v="130571566842994698" />\r
 <top_block v="TopDesign" />\r
 <last_generation v="0" />\r
 </CyGuid_925cc1e1-309e-4e08-b0a1-09a83c35b157>\r
 </dataGuid>\r
 <dataGuid v="769d31ea-68b1-4f0c-b90a-7c10a43ee563">\r
 <CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563 type_name="CyDesigner.Common.ProjMgmt.Model.CyLinkCustomData" version="1">\r
-<deps_time v="130537025103831962" />\r
+<deps_time v="130571567839248780" />\r
 </CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563>\r
 </dataGuid>\r
 <dataGuid v="bf610382-39c6-441f-80b8-b04622ea7845">\r

diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.rpt b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.rpt
deleted file mode 100644 (file)
index d51d329..0000000
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader.rpt
+++ /dev/null
@@ -1,2695 +0,0 @@
-Loading plugins phase: Elapsed time ==> 0s.529ms\r
-Initializing data phase: Elapsed time ==> 4s.249ms\r
-<CYPRESSTAG name="CyDsfit arguments...">\r
-cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE</CYPRESSTAG>\r
-<CYPRESSTAG name="Design elaboration results...">\r
-</CYPRESSTAG>\r
-Elaboration phase: Elapsed time ==> 8s.312ms\r
-<CYPRESSTAG name="HDL generation results...">\r
-</CYPRESSTAG>\r
-HDL generation phase: Elapsed time ==> 1s.015ms\r
-<CYPRESSTAG name="Synthesis results...">\r
-\r
-     | | | | | | |\r
-   _________________\r
-  -|               |-\r
-  -|               |-\r
-  -|               |-\r
-  -|    CYPRESS    |-\r
-  -|               |-\r
-  -|               |-   Warp Verilog Synthesis Compiler: Version 6.3 IR 41\r
-  -|               |-   Copyright (C) 1991-2001 Cypress Semiconductor\r
-   |_______________|\r
-     | | | | | | |\r
-\r
-======================================================================\r
-Compiling:  USB_Bootloader.v\r
-Program  :   C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe\r
-Options  :    -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
-======================================================================\r
-\r
-======================================================================\r
-Compiling:  USB_Bootloader.v\r
-Program  :   C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe\r
-Options  :    -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
-======================================================================\r
-\r
-======================================================================\r
-Compiling:  USB_Bootloader.v\r
-Program  :   vlogfe\r
-Options  :    -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
-======================================================================\r
-\r
-vlogfe V6.3 IR 41:  Verilog parser\r
-Thu Aug 28 22:24:58 2014\r
-\r
-\r
-======================================================================\r
-Compiling:  USB_Bootloader.v\r
-Program  :   vpp\r
-Options  :    -yv2 -q10 USB_Bootloader.v\r
-======================================================================\r
-\r
-vpp V6.3 IR 41:  Verilog Pre-Processor\r
-Thu Aug 28 22:24:59 2014\r
-\r
-\r
-vpp:  No errors.\r
-\r
-Library 'work' => directory 'lcpsoc3'\r
-General_symbol_table\r
-General_symbol_table\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\work\cypress.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.\r
-Using control file 'USB_Bootloader.ctl'.\r
-\r
-vlogfe:  No errors.\r
-\r
-\r
-======================================================================\r
-Compiling:  USB_Bootloader.v\r
-Program  :   tovif\r
-Options  :    -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
-======================================================================\r
-\r
-tovif V6.3 IR 41:  High-level synthesis\r
-Thu Aug 28 22:25:00 2014\r
-\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\work\cypress.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.\r
-Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.\r
-Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.\r
-\r
-tovif:  No errors.\r
-\r
-\r
-======================================================================\r
-Compiling:  USB_Bootloader.v\r
-Program  :   topld\r
-Options  :    -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
-======================================================================\r
-\r
-topld V6.3 IR 41:  Synthesis and optimization\r
-Thu Aug 28 22:25:02 2014\r
-\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\work\cypress.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.\r
-Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.\r
-Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.\r
-Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'.\r
-\r
-----------------------------------------------------------\r
-Detecting unused logic.\r
-----------------------------------------------------------\r
-\r
-\r
-\r
-------------------------------------------------------\r
-Alias Detection\r
-------------------------------------------------------\r
-Aliasing one to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing \USBFS:tmpOE__Dp_net_0\ to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_DBx_net_7 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_DBx_net_6 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_DBx_net_5 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_DBx_net_4 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_DBx_net_3 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_DBx_net_2 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_DBx_net_1 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_DBx_net_0 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_net_9 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_net_8 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_net_7 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_net_6 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_net_5 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_net_4 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_net_3 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_net_2 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_net_1 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SCSI_Out_net_0 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SD_PULLUP_net_4 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SD_PULLUP_net_3 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SD_PULLUP_net_2 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SD_PULLUP_net_1 to \USBFS:tmpOE__Dm_net_0\\r
-Aliasing tmpOE__SD_PULLUP_net_0 to \USBFS:tmpOE__Dm_net_0\\r
-Removing Rhs of wire one[37] = \USBFS:tmpOE__Dm_net_0\[32]\r
-Removing Lhs of wire \USBFS:tmpOE__Dp_net_0\[40] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_7[49] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_6[50] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_5[51] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_4[52] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_3[53] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_2[54] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_1[55] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_0[56] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_net_9[84] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_net_8[85] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_net_7[86] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_net_6[87] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_net_5[88] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_net_4[89] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_net_3[90] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_net_2[91] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_net_1[92] = one[37]\r
-Removing Lhs of wire tmpOE__SCSI_Out_net_0[93] = one[37]\r
-Removing Lhs of wire tmpOE__SD_PULLUP_net_4[127] = one[37]\r
-Removing Lhs of wire tmpOE__SD_PULLUP_net_3[128] = one[37]\r
-Removing Lhs of wire tmpOE__SD_PULLUP_net_2[129] = one[37]\r
-Removing Lhs of wire tmpOE__SD_PULLUP_net_1[130] = one[37]\r
-Removing Lhs of wire tmpOE__SD_PULLUP_net_0[131] = one[37]\r
-\r
-------------------------------------------------------\r
-Aliased 0 equations, 25 wires.\r
-------------------------------------------------------\r
-\r
-----------------------------------------------------------\r
-Circuit simplification\r
-----------------------------------------------------------\r
-\r
-Substituting virtuals - pass 1:\r
-\r
-\r
-----------------------------------------------------------\r
-Circuit simplification results:\r
-\r
-       Expanded 0 signals.\r
-       Turned 0 signals into soft nodes.\r
-       Maximum default expansion cost was set at 3.\r
-----------------------------------------------------------\r
-\r
-topld:  No errors.\r
-\r
-CYPRESS_DIR    : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\r
-Warp Program   : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe\r
-Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
-</CYPRESSTAG>\r
-Warp synthesis phase: Elapsed time ==> 10s.236ms\r
-<CYPRESSTAG name="Fitter results...">\r
-<CYPRESSTAG name="Fitter startup details...">\r
-cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Thursday, 28 August 2014 22:25:08\r
-Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Design parsing">\r
-Design parsing phase: Elapsed time ==> 0s.344ms\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Tech mapping">\r
-<CYPRESSTAG name="Initial Mapping" icon="FILE_RPT_TECHM">\r
-Assigning clock USBFS_Clock_vbus to clock BUS_CLK because it is a pass-through\r
-<CYPRESSTAG name="Global Clock Selection" icon="FILE_RPT_TECHM">\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="UDB Clock/Enable Remapping Results">\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Duplicate Macrocell detection">\r
-</CYPRESSTAG>\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Duplicate Macrocell detection">\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Design Equations" icon="FILE_RPT_EQUATION">\r
-\r
-------------------------------------------------------------\r
-Design Equations\r
-------------------------------------------------------------\r
-    <CYPRESSTAG name="Pin listing">\r
-\r
-    ------------------------------------------------------------\r
-    Pin listing\r
-    ------------------------------------------------------------\r
-\r
-    Pin : Name = SCSI_Out(0)\r
-        Attributes:\r
-            Alias: DBP_raw\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 5\r
-        PORT MAP (\r
-            pa_out => SCSI_Out(0)__PA ,\r
-            pad => SCSI_Out(0)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SCSI_Out(1)\r
-        Attributes:\r
-            Alias: ATN\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 5\r
-        PORT MAP (\r
-            pa_out => SCSI_Out(1)__PA ,\r
-            pad => SCSI_Out(1)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SCSI_Out(2)\r
-        Attributes:\r
-            Alias: BSY\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 5\r
-        PORT MAP (\r
-            pa_out => SCSI_Out(2)__PA ,\r
-            pad => SCSI_Out(2)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SCSI_Out(3)\r
-        Attributes:\r
-            Alias: ACK\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 5\r
-        PORT MAP (\r
-            pa_out => SCSI_Out(3)__PA ,\r
-            pad => SCSI_Out(3)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SCSI_Out(4)\r
-        Attributes:\r
-            Alias: RST\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 5\r
-        PORT MAP (\r
-            pa_out => SCSI_Out(4)__PA ,\r
-            pad => SCSI_Out(4)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SCSI_Out(5)\r
-        Attributes:\r
-            Alias: MSG\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 5\r
-        PORT MAP (\r
-            pa_out => SCSI_Out(5)__PA ,\r
-            pad => SCSI_Out(5)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SCSI_Out(6)\r
-        Attributes:\r
-            Alias: SEL\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 5\r
-        PORT MAP (\r
-            pa_out => SCSI_Out(6)__PA ,\r
-            pad => SCSI_Out(6)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SCSI_Out(7)\r
-        Attributes:\r
-            Alias: CD\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 5\r
-        PORT MAP (\r
-            pa_out => SCSI_Out(7)__PA ,\r
-            pad => SCSI_Out(7)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SCSI_Out(8)\r
-        Attributes:\r
-            Alias: REQ\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 5\r
-        PORT MAP (\r
-            pa_out => SCSI_Out(8)__PA ,\r
-            pad => SCSI_Out(8)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SCSI_Out(9)\r
-        Attributes:\r
-            Alias: IO_raw\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 5\r
-        PORT MAP (\r
-            pa_out => SCSI_Out(9)__PA ,\r
-            pad => SCSI_Out(9)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SCSI_Out_DBx(0)\r
-        Attributes:\r
-            Alias: DB0\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 0\r
-        PORT MAP (\r
-            pa_out => SCSI_Out_DBx(0)__PA ,\r
-            pad => SCSI_Out_DBx(0)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SCSI_Out_DBx(1)\r
-        Attributes:\r
-            Alias: DB1\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 0\r
-        PORT MAP (\r
-            pa_out => SCSI_Out_DBx(1)__PA ,\r
-            pad => SCSI_Out_DBx(1)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SCSI_Out_DBx(2)\r
-        Attributes:\r
-            Alias: DB2\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 0\r
-        PORT MAP (\r
-            pa_out => SCSI_Out_DBx(2)__PA ,\r
-            pad => SCSI_Out_DBx(2)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SCSI_Out_DBx(3)\r
-        Attributes:\r
-            Alias: DB3\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 0\r
-        PORT MAP (\r
-            pa_out => SCSI_Out_DBx(3)__PA ,\r
-            pad => SCSI_Out_DBx(3)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SCSI_Out_DBx(4)\r
-        Attributes:\r
-            Alias: DB4\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 0\r
-        PORT MAP (\r
-            pa_out => SCSI_Out_DBx(4)__PA ,\r
-            pad => SCSI_Out_DBx(4)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SCSI_Out_DBx(5)\r
-        Attributes:\r
-            Alias: DB5\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 0\r
-        PORT MAP (\r
-            pa_out => SCSI_Out_DBx(5)__PA ,\r
-            pad => SCSI_Out_DBx(5)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SCSI_Out_DBx(6)\r
-        Attributes:\r
-            Alias: DB6\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 0\r
-        PORT MAP (\r
-            pa_out => SCSI_Out_DBx(6)__PA ,\r
-            pad => SCSI_Out_DBx(6)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SCSI_Out_DBx(7)\r
-        Attributes:\r
-            Alias: DB7\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: NOSYNC\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: CMOS_OUT\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 0\r
-            IO Voltage: 5\r
-        PORT MAP (\r
-            pa_out => SCSI_Out_DBx(7)__PA ,\r
-            pad => SCSI_Out_DBx(7)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SD_PULLUP(0)\r
-        Attributes:\r
-            In Group/Port: True\r
-            In Sync Option: SYNC\r
-            Out Sync Option: AUTO\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: RES_PULL_UP\r
-            VTrip: CMOS\r
-            Slew: FAST\r
-            Input Sync needed: True\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: False\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 1\r
-            IO Voltage: 3.3\r
-        PORT MAP (\r
-            pa_out => SD_PULLUP(0)__PA ,\r
-            pad => SD_PULLUP(0)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SD_PULLUP(1)\r
-        Attributes:\r
-            In Group/Port: True\r
-            In Sync Option: SYNC\r
-            Out Sync Option: AUTO\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: RES_PULL_UP\r
-            VTrip: CMOS\r
-            Slew: FAST\r
-            Input Sync needed: True\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: False\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 1\r
-            IO Voltage: 0\r
-        PORT MAP (\r
-            pa_out => SD_PULLUP(1)__PA ,\r
-            pad => SD_PULLUP(1)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SD_PULLUP(2)\r
-        Attributes:\r
-            In Group/Port: True\r
-            In Sync Option: SYNC\r
-            Out Sync Option: AUTO\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: RES_PULL_UP\r
-            VTrip: CMOS\r
-            Slew: FAST\r
-            Input Sync needed: True\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: False\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 1\r
-            IO Voltage: 0\r
-        PORT MAP (\r
-            pa_out => SD_PULLUP(2)__PA ,\r
-            pad => SD_PULLUP(2)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SD_PULLUP(3)\r
-        Attributes:\r
-            In Group/Port: True\r
-            In Sync Option: SYNC\r
-            Out Sync Option: AUTO\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: RES_PULL_UP\r
-            VTrip: CMOS\r
-            Slew: FAST\r
-            Input Sync needed: True\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: False\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 1\r
-            IO Voltage: 0\r
-        PORT MAP (\r
-            pa_out => SD_PULLUP(3)__PA ,\r
-            pad => SD_PULLUP(3)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = SD_PULLUP(4)\r
-        Attributes:\r
-            In Group/Port: True\r
-            In Sync Option: SYNC\r
-            Out Sync Option: AUTO\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: RES_PULL_UP\r
-            VTrip: CMOS\r
-            Slew: FAST\r
-            Input Sync needed: True\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: False\r
-            Is OE Registered: False\r
-            Uses Analog: False\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: DIGITAL\r
-            Initial Value: 1\r
-            IO Voltage: 0\r
-        PORT MAP (\r
-            pa_out => SD_PULLUP(4)__PA ,\r
-            pad => SD_PULLUP(4)_PAD );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = \USBFS:Dm(0)\\r
-        Attributes:\r
-            In Group/Port: True\r
-            In Sync Option: AUTO\r
-            Out Sync Option: AUTO\r
-            Interrupt generated: False\r
-            Interrupt mode: NONE\r
-            Drive mode: HI_Z_ANALOG\r
-            VTrip: EITHER\r
-            Slew: FAST\r
-            Input Sync needed: False\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: True\r
-            Is OE Registered: False\r
-            Uses Analog: True\r
-            Can contain Digital: False\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: USB_D_MINUS\r
-            Initial Value: 0\r
-            IO Voltage: 0\r
-        PORT MAP (\r
-            pa_out => \USBFS:Dm(0)\__PA ,\r
-            analog_term => \USBFS:Net_597\ ,\r
-            pad => \USBFS:Dm(0)_PAD\ );\r
-        Properties:\r
-        {\r
-        }\r
-\r
-    Pin : Name = \USBFS:Dp(0)\\r
-        Attributes:\r
-            In Group/Port: True\r
-            In Sync Option: SYNC\r
-            Out Sync Option: AUTO\r
-            Interrupt generated: True\r
-            Interrupt mode: FALLING\r
-            Drive mode: HI_Z_ANALOG\r
-            VTrip: CMOS\r
-            Slew: FAST\r
-            Input Sync needed: True\r
-            Output Sync needed: False\r
-            SC shield enabled: False\r
-            POR State: ANY\r
-            LCD Mode: COMMON\r
-            Register Mode: RegComb\r
-            CaSense Mode: NEITHER\r
-            Treat as pin: False\r
-            Is OE Registered: False\r
-            Uses Analog: True\r
-            Can contain Digital: True\r
-            Is SIO: False\r
-            SIO Output Buf: NONREGULATED\r
-            SIO Input Buf: SINGLE_ENDED\r
-            SIO HiFreq: LOW\r
-            SIO Hyst: DISABLED\r
-            SIO Vtrip: MULTIPLIER_0_5\r
-            SIO RefSel: VCC_IO\r
-            Required Capabilitites: USB_D_PLUS\r
-            Initial Value: 0\r
-            IO Voltage: 0\r
-        PORT MAP (\r
-            pa_out => \USBFS:Dp(0)\__PA ,\r
-            analog_term => \USBFS:Net_1000\ ,\r
-            pad => \USBFS:Dp(0)_PAD\ );\r
-        Properties:\r
-        {\r
-        }\r
-    </CYPRESSTAG>\r
-    <CYPRESSTAG name="Macrocell listing" icon="FILE_RPT_EQUATION">\r
-    </CYPRESSTAG>\r
-    <CYPRESSTAG name="Datapath listing">\r
-    </CYPRESSTAG>\r
-    <CYPRESSTAG name="Status register listing">\r
-    </CYPRESSTAG>\r
-    <CYPRESSTAG name="StatusI register listing">\r
-    </CYPRESSTAG>\r
-    <CYPRESSTAG name="Sync listing">\r
-    </CYPRESSTAG>\r
-    <CYPRESSTAG name="Control register listing">\r
-    </CYPRESSTAG>\r
-    <CYPRESSTAG name="Count7 listing">\r
-    </CYPRESSTAG>\r
-    <CYPRESSTAG name="DRQ listing">\r
-    </CYPRESSTAG>\r
-    <CYPRESSTAG name="Interrupt listing">\r
-\r
-    ------------------------------------------------------------\r
-    Interrupt listing\r
-    ------------------------------------------------------------\r
-\r
-    interrupt: Name =\USBFS:arb_int\\r
-        PORT MAP (\r
-            interrupt => \USBFS:Net_79\ );\r
-        Properties:\r
-        {\r
-            int_type = "10"\r
-        }\r
-\r
-    interrupt: Name =\USBFS:bus_reset\\r
-        PORT MAP (\r
-            interrupt => \USBFS:Net_81\ );\r
-        Properties:\r
-        {\r
-            int_type = "10"\r
-        }\r
-\r
-    interrupt: Name =\USBFS:dp_int\\r
-        PORT MAP (\r
-            interrupt => \USBFS:Net_1010\ );\r
-        Properties:\r
-        {\r
-            int_type = "10"\r
-        }\r
-\r
-    interrupt: Name =\USBFS:ep_0\\r
-        PORT MAP (\r
-            interrupt => \USBFS:ept_int_0\ );\r
-        Properties:\r
-        {\r
-            int_type = "10"\r
-        }\r
-\r
-    interrupt: Name =\USBFS:ep_1\\r
-        PORT MAP (\r
-            interrupt => \USBFS:ept_int_1\ );\r
-        Properties:\r
-        {\r
-            int_type = "10"\r
-        }\r
-\r
-    interrupt: Name =\USBFS:ep_2\\r
-        PORT MAP (\r
-            interrupt => \USBFS:ept_int_2\ );\r
-        Properties:\r
-        {\r
-            int_type = "10"\r
-        }\r
-\r
-    interrupt: Name =\USBFS:sof_int\\r
-        PORT MAP (\r
-            interrupt => Net_40 );\r
-        Properties:\r
-        {\r
-            int_type = "10"\r
-        }\r
-    </CYPRESSTAG>\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Technology mapping summary" expanded>\r
-\r
-------------------------------------------------------------\r
-Technology mapping summary\r
-------------------------------------------------------------\r
-\r
-Resource Type                 : Used : Free :  Max :  % Used\r
-============================================================\r
-Digital clock dividers        :    0 :    8 :    8 :   0.00%\r
-Analog clock dividers         :    0 :    4 :    4 :   0.00%\r
-Pins                          :   28 :   44 :   72 :  38.89%\r
-UDB Macrocells                :    0 :  192 :  192 :   0.00%\r
-UDB Unique Pterms             :    0 :  384 :  384 :   0.00%\r
-UDB Datapath Cells            :    0 :   24 :   24 :   0.00%\r
-UDB Status Cells              :    0 :   24 :   24 :   0.00%\r
-UDB Control Cells             :    0 :   24 :   24 :   0.00%\r
-DMA Channels                  :    0 :   24 :   24 :   0.00%\r
-Interrupts                    :    7 :   25 :   32 :  21.88%\r
-VIDAC Fixed Blocks            :    0 :    1 :    1 :   0.00%\r
-Comparator Fixed Blocks       :    0 :    2 :    2 :   0.00%\r
-CapSense Buffers              :    0 :    2 :    2 :   0.00%\r
-I2C Fixed Blocks              :    0 :    1 :    1 :   0.00%\r
-Timer Fixed Blocks            :    0 :    4 :    4 :   0.00%\r
-USB Fixed Blocks              :    1 :    0 :    1 : 100.00%\r
-LCD Fixed Blocks              :    0 :    1 :    1 :   0.00%\r
-EMIF Fixed Blocks             :    0 :    1 :    1 :   0.00%\r
-LPF Fixed Blocks              :    0 :    2 :    2 :   0.00%\r
-SAR Fixed Blocks              :    0 :    1 :    1 :   0.00%\r
-</CYPRESSTAG>\r
-Technology Mapping: Elapsed time ==> 0s.406ms\r
-Tech mapping phase: Elapsed time ==> 0s.702ms\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Analog Placement">\r
-Initial Analog Placement Results:\r
-IO_3@[IOP=(4)][IoId=(3)] : SCSI_Out(0) (fixed)\r
-IO_2@[IOP=(4)][IoId=(2)] : SCSI_Out(1) (fixed)\r
-IO_7@[IOP=(0)][IoId=(7)] : SCSI_Out(2) (fixed)\r
-IO_6@[IOP=(0)][IoId=(6)] : SCSI_Out(3) (fixed)\r
-IO_5@[IOP=(0)][IoId=(5)] : SCSI_Out(4) (fixed)\r
-IO_4@[IOP=(0)][IoId=(4)] : SCSI_Out(5) (fixed)\r
-IO_3@[IOP=(0)][IoId=(3)] : SCSI_Out(6) (fixed)\r
-IO_2@[IOP=(0)][IoId=(2)] : SCSI_Out(7) (fixed)\r
-IO_1@[IOP=(0)][IoId=(1)] : SCSI_Out(8) (fixed)\r
-IO_0@[IOP=(0)][IoId=(0)] : SCSI_Out(9) (fixed)\r
-IO_3@[IOP=(6)][IoId=(3)] : SCSI_Out_DBx(0) (fixed)\r
-IO_2@[IOP=(6)][IoId=(2)] : SCSI_Out_DBx(1) (fixed)\r
-IO_1@[IOP=(6)][IoId=(1)] : SCSI_Out_DBx(2) (fixed)\r
-IO_0@[IOP=(6)][IoId=(0)] : SCSI_Out_DBx(3) (fixed)\r
-IO_7@[IOP=(4)][IoId=(7)] : SCSI_Out_DBx(4) (fixed)\r
-IO_6@[IOP=(4)][IoId=(6)] : SCSI_Out_DBx(5) (fixed)\r
-IO_5@[IOP=(4)][IoId=(5)] : SCSI_Out_DBx(6) (fixed)\r
-IO_4@[IOP=(4)][IoId=(4)] : SCSI_Out_DBx(7) (fixed)\r
-IO_1@[IOP=(3)][IoId=(1)] : SD_PULLUP(0) (fixed)\r
-IO_2@[IOP=(3)][IoId=(2)] : SD_PULLUP(1) (fixed)\r
-IO_3@[IOP=(3)][IoId=(3)] : SD_PULLUP(2) (fixed)\r
-IO_4@[IOP=(3)][IoId=(4)] : SD_PULLUP(3) (fixed)\r
-IO_5@[IOP=(3)][IoId=(5)] : SD_PULLUP(4) (fixed)\r
-IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed)\r
-IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed)\r
-USB[0]@[FFB(USB,0)] : \USBFS:USB\\r
-Analog Placement phase: Elapsed time ==> 0s.109ms\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Analog Routing">\r
-Analog Routing phase: Elapsed time ==> 0s.000ms\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Analog Code Generation">\r
-============ Analog Final Answer Routes ============\r
-Dump of CyAnalogRoutingResultsDB\r
-Map of net to items {\r
-}\r
-Map of item to net {\r
-}\r
-Mux Info {\r
-}\r
-Dump of CyP35AnalogRoutingResultsDB\r
-IsVddaHalfUsedForComp = False\r
-IsVddaHalfUsedForSar0 = False\r
-IsVddaHalfUsedForSar1 = False\r
-Analog Code Generation phase: Elapsed time ==> 1s.453ms\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Digital Placement">\r
-<CYPRESSTAG name="Detailed placement messages">\r
-I2659: No Constrained paths were found. The placer will run in non-timing driven mode.\r
-I2076: Total run-time: 4.1 sec.\r
-\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="PLD Packing">\r
-<CYPRESSTAG name="PLD Packing Summary">\r
-No PLDs were packed.\r
-</CYPRESSTAG>\r
-PLD Packing: Elapsed time ==> 0s.000ms\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Partitioning">\r
-<CYPRESSTAG name="Initial Partitioning Summary">\r
-Initial Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>\r
-<CYPRESSTAG name="Final Partitioning Summary">\r
-Final Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>\r
-Partitioning: Elapsed time ==> 0s.063ms\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Simulated Annealing">\r
-Annealing: Elapsed time ==> 0s.014ms\r
-<CYPRESSTAG name="Simulated Annealing Results">\r
-The seed used for moves was 114161200.\r
-Inital cost was 120, final cost is 120 (0.00% improvement).</CYPRESSTAG>\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Final Placement Summary">\r
-\r
-------------------------------------------------------------\r
-Final Placement Summary\r
-------------------------------------------------------------\r
-\r
-       Resource Type :      Count : Avg Inputs : Avg Outputs\r
-    ========================================================\r
-                 UDB :          0 :       0.00 :       0.00\r
-<CYPRESSTAG name="Final Placement Details">\r
-<CYPRESSTAG name="Component Details">\r
-\r
-------------------------------------------------------------\r
-Component Placement Details\r
-------------------------------------------------------------\r
-UDB [UDB=(0,0)] is empty.\r
-UDB [UDB=(0,1)] is empty.\r
-UDB [UDB=(0,2)] is empty.\r
-UDB [UDB=(0,3)] is empty.\r
-UDB [UDB=(0,4)] is empty.\r
-UDB [UDB=(0,5)] is empty.\r
-UDB [UDB=(1,0)] is empty.\r
-UDB [UDB=(1,1)] is empty.\r
-UDB [UDB=(1,2)] is empty.\r
-UDB [UDB=(1,3)] is empty.\r
-UDB [UDB=(1,4)] is empty.\r
-UDB [UDB=(1,5)] is empty.\r
-UDB [UDB=(2,0)] is empty.\r
-UDB [UDB=(2,1)] is empty.\r
-UDB [UDB=(2,2)] is empty.\r
-UDB [UDB=(2,3)] is empty.\r
-UDB [UDB=(2,4)] is empty.\r
-UDB [UDB=(2,5)] is empty.\r
-UDB [UDB=(3,0)] is empty.\r
-UDB [UDB=(3,1)] is empty.\r
-UDB [UDB=(3,2)] is empty.\r
-UDB [UDB=(3,3)] is empty.\r
-UDB [UDB=(3,4)] is empty.\r
-UDB [UDB=(3,5)] is empty.\r
-Intr hod @ [IntrHod=(0)]: \r
-  Intr@ [IntrHod=(0)][IntrId=(0)] \r
-    interrupt: Name =\USBFS:ep_1\\r
-        PORT MAP (\r
-            interrupt => \USBFS:ept_int_1\ );\r
-        Properties:\r
-        {\r
-            int_type = "10"\r
-        }\r
-  Intr@ [IntrHod=(0)][IntrId=(1)] \r
-    interrupt: Name =\USBFS:ep_2\\r
-        PORT MAP (\r
-            interrupt => \USBFS:ept_int_2\ );\r
-        Properties:\r
-        {\r
-            int_type = "10"\r
-        }\r
-  Intr@ [IntrHod=(0)][IntrId=(12)] \r
-    interrupt: Name =\USBFS:dp_int\\r
-        PORT MAP (\r
-            interrupt => \USBFS:Net_1010\ );\r
-        Properties:\r
-        {\r
-            int_type = "10"\r
-        }\r
-  Intr@ [IntrHod=(0)][IntrId=(21)] \r
-    interrupt: Name =\USBFS:sof_int\\r
-        PORT MAP (\r
-            interrupt => Net_40 );\r
-        Properties:\r
-        {\r
-            int_type = "10"\r
-        }\r
-  Intr@ [IntrHod=(0)][IntrId=(22)] \r
-    interrupt: Name =\USBFS:arb_int\\r
-        PORT MAP (\r
-            interrupt => \USBFS:Net_79\ );\r
-        Properties:\r
-        {\r
-            int_type = "10"\r
-        }\r
-  Intr@ [IntrHod=(0)][IntrId=(23)] \r
-    interrupt: Name =\USBFS:bus_reset\\r
-        PORT MAP (\r
-            interrupt => \USBFS:Net_81\ );\r
-        Properties:\r
-        {\r
-            int_type = "10"\r
-        }\r
-  Intr@ [IntrHod=(0)][IntrId=(24)] \r
-    interrupt: Name =\USBFS:ep_0\\r
-        PORT MAP (\r
-            interrupt => \USBFS:ept_int_0\ );\r
-        Properties:\r
-        {\r
-            int_type = "10"\r
-        }\r
-Drq hod @ [DrqHod=(0)]: empty\r
-Port 0 contains the following IO cells:\r
-[IoId=0]: \r
-Pin : Name = SCSI_Out(9)\r
-    Attributes:\r
-        Alias: IO_raw\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 5\r
-    PORT MAP (\r
-        pa_out => SCSI_Out(9)__PA ,\r
-        pad => SCSI_Out(9)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=1]: \r
-Pin : Name = SCSI_Out(8)\r
-    Attributes:\r
-        Alias: REQ\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 5\r
-    PORT MAP (\r
-        pa_out => SCSI_Out(8)__PA ,\r
-        pad => SCSI_Out(8)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=2]: \r
-Pin : Name = SCSI_Out(7)\r
-    Attributes:\r
-        Alias: CD\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 5\r
-    PORT MAP (\r
-        pa_out => SCSI_Out(7)__PA ,\r
-        pad => SCSI_Out(7)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=3]: \r
-Pin : Name = SCSI_Out(6)\r
-    Attributes:\r
-        Alias: SEL\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 5\r
-    PORT MAP (\r
-        pa_out => SCSI_Out(6)__PA ,\r
-        pad => SCSI_Out(6)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=4]: \r
-Pin : Name = SCSI_Out(5)\r
-    Attributes:\r
-        Alias: MSG\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 5\r
-    PORT MAP (\r
-        pa_out => SCSI_Out(5)__PA ,\r
-        pad => SCSI_Out(5)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=5]: \r
-Pin : Name = SCSI_Out(4)\r
-    Attributes:\r
-        Alias: RST\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 5\r
-    PORT MAP (\r
-        pa_out => SCSI_Out(4)__PA ,\r
-        pad => SCSI_Out(4)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=6]: \r
-Pin : Name = SCSI_Out(3)\r
-    Attributes:\r
-        Alias: ACK\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 5\r
-    PORT MAP (\r
-        pa_out => SCSI_Out(3)__PA ,\r
-        pad => SCSI_Out(3)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=7]: \r
-Pin : Name = SCSI_Out(2)\r
-    Attributes:\r
-        Alias: BSY\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 5\r
-    PORT MAP (\r
-        pa_out => SCSI_Out(2)__PA ,\r
-        pad => SCSI_Out(2)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-Port 1 is empty\r
-Port 2 is empty\r
-Port 3 contains the following IO cells:\r
-[IoId=1]: \r
-Pin : Name = SD_PULLUP(0)\r
-    Attributes:\r
-        In Group/Port: True\r
-        In Sync Option: SYNC\r
-        Out Sync Option: AUTO\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: RES_PULL_UP\r
-        VTrip: CMOS\r
-        Slew: FAST\r
-        Input Sync needed: True\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: False\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 1\r
-        IO Voltage: 3.3\r
-    PORT MAP (\r
-        pa_out => SD_PULLUP(0)__PA ,\r
-        pad => SD_PULLUP(0)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=2]: \r
-Pin : Name = SD_PULLUP(1)\r
-    Attributes:\r
-        In Group/Port: True\r
-        In Sync Option: SYNC\r
-        Out Sync Option: AUTO\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: RES_PULL_UP\r
-        VTrip: CMOS\r
-        Slew: FAST\r
-        Input Sync needed: True\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: False\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 1\r
-        IO Voltage: 0\r
-    PORT MAP (\r
-        pa_out => SD_PULLUP(1)__PA ,\r
-        pad => SD_PULLUP(1)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=3]: \r
-Pin : Name = SD_PULLUP(2)\r
-    Attributes:\r
-        In Group/Port: True\r
-        In Sync Option: SYNC\r
-        Out Sync Option: AUTO\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: RES_PULL_UP\r
-        VTrip: CMOS\r
-        Slew: FAST\r
-        Input Sync needed: True\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: False\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 1\r
-        IO Voltage: 0\r
-    PORT MAP (\r
-        pa_out => SD_PULLUP(2)__PA ,\r
-        pad => SD_PULLUP(2)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=4]: \r
-Pin : Name = SD_PULLUP(3)\r
-    Attributes:\r
-        In Group/Port: True\r
-        In Sync Option: SYNC\r
-        Out Sync Option: AUTO\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: RES_PULL_UP\r
-        VTrip: CMOS\r
-        Slew: FAST\r
-        Input Sync needed: True\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: False\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 1\r
-        IO Voltage: 0\r
-    PORT MAP (\r
-        pa_out => SD_PULLUP(3)__PA ,\r
-        pad => SD_PULLUP(3)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=5]: \r
-Pin : Name = SD_PULLUP(4)\r
-    Attributes:\r
-        In Group/Port: True\r
-        In Sync Option: SYNC\r
-        Out Sync Option: AUTO\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: RES_PULL_UP\r
-        VTrip: CMOS\r
-        Slew: FAST\r
-        Input Sync needed: True\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: False\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 1\r
-        IO Voltage: 0\r
-    PORT MAP (\r
-        pa_out => SD_PULLUP(4)__PA ,\r
-        pad => SD_PULLUP(4)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-Port 4 contains the following IO cells:\r
-[IoId=2]: \r
-Pin : Name = SCSI_Out(1)\r
-    Attributes:\r
-        Alias: ATN\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 5\r
-    PORT MAP (\r
-        pa_out => SCSI_Out(1)__PA ,\r
-        pad => SCSI_Out(1)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=3]: \r
-Pin : Name = SCSI_Out(0)\r
-    Attributes:\r
-        Alias: DBP_raw\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 5\r
-    PORT MAP (\r
-        pa_out => SCSI_Out(0)__PA ,\r
-        pad => SCSI_Out(0)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=4]: \r
-Pin : Name = SCSI_Out_DBx(7)\r
-    Attributes:\r
-        Alias: DB7\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 5\r
-    PORT MAP (\r
-        pa_out => SCSI_Out_DBx(7)__PA ,\r
-        pad => SCSI_Out_DBx(7)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=5]: \r
-Pin : Name = SCSI_Out_DBx(6)\r
-    Attributes:\r
-        Alias: DB6\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 0\r
-    PORT MAP (\r
-        pa_out => SCSI_Out_DBx(6)__PA ,\r
-        pad => SCSI_Out_DBx(6)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=6]: \r
-Pin : Name = SCSI_Out_DBx(5)\r
-    Attributes:\r
-        Alias: DB5\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 0\r
-    PORT MAP (\r
-        pa_out => SCSI_Out_DBx(5)__PA ,\r
-        pad => SCSI_Out_DBx(5)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=7]: \r
-Pin : Name = SCSI_Out_DBx(4)\r
-    Attributes:\r
-        Alias: DB4\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 0\r
-    PORT MAP (\r
-        pa_out => SCSI_Out_DBx(4)__PA ,\r
-        pad => SCSI_Out_DBx(4)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-Port 5 is empty\r
-Port 6 contains the following IO cells:\r
-[IoId=0]: \r
-Pin : Name = SCSI_Out_DBx(3)\r
-    Attributes:\r
-        Alias: DB3\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 0\r
-    PORT MAP (\r
-        pa_out => SCSI_Out_DBx(3)__PA ,\r
-        pad => SCSI_Out_DBx(3)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=1]: \r
-Pin : Name = SCSI_Out_DBx(2)\r
-    Attributes:\r
-        Alias: DB2\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 0\r
-    PORT MAP (\r
-        pa_out => SCSI_Out_DBx(2)__PA ,\r
-        pad => SCSI_Out_DBx(2)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=2]: \r
-Pin : Name = SCSI_Out_DBx(1)\r
-    Attributes:\r
-        Alias: DB1\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 0\r
-    PORT MAP (\r
-        pa_out => SCSI_Out_DBx(1)__PA ,\r
-        pad => SCSI_Out_DBx(1)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=3]: \r
-Pin : Name = SCSI_Out_DBx(0)\r
-    Attributes:\r
-        Alias: DB0\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: NOSYNC\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: CMOS_OUT\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: False\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: DIGITAL\r
-        Initial Value: 0\r
-        IO Voltage: 0\r
-    PORT MAP (\r
-        pa_out => SCSI_Out_DBx(0)__PA ,\r
-        pad => SCSI_Out_DBx(0)_PAD );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-Port 12 is empty\r
-Port 15 generates interrupt for logical port:\r
-    logicalport: Name =\USBFS:Dp\\r
-        PORT MAP (\r
-            in_clock_en => one ,\r
-            in_reset => zero ,\r
-            out_clock_en => one ,\r
-            out_reset => zero ,\r
-            interrupt => \USBFS:Net_1010\ ,\r
-            in_clock => ClockBlock_BUS_CLK );\r
-        Properties:\r
-        {\r
-            drive_mode = "000"\r
-            ibuf_enabled = "0"\r
-            id = "f9248435-5d3e-4e4d-bbae-bdae8795c3dd/618a72fc-5ddd-4df5-958f-a3d55102db42"\r
-            init_dr_st = "0"\r
-            input_clk_en = 0\r
-            input_sync = "1"\r
-            input_sync_mode = "0"\r
-            intr_mode = "10"\r
-            invert_in_clock = 0\r
-            invert_in_clock_en = 0\r
-            invert_in_reset = 0\r
-            invert_out_clock = 0\r
-            invert_out_clock_en = 0\r
-            invert_out_reset = 0\r
-            io_voltage = ""\r
-            layout_mode = "CONTIGUOUS"\r
-            oe_conn = "0"\r
-            oe_reset = 0\r
-            oe_sync = "0"\r
-            output_clk_en = 0\r
-            output_clock_mode = "0"\r
-            output_conn = "0"\r
-            output_mode = "0"\r
-            output_reset = 0\r
-            output_sync = "0"\r
-            pa_in_clock = -1\r
-            pa_in_clock_en = -1\r
-            pa_in_reset = -1\r
-            pa_out_clock = -1\r
-            pa_out_clock_en = -1\r
-            pa_out_reset = -1\r
-            pin_aliases = ""\r
-            pin_mode = "I"\r
-            por_state = 4\r
-            port_alias_group = ""\r
-            port_alias_required = 0\r
-            sio_group_cnt = 0\r
-            sio_hifreq = ""\r
-            sio_hyst = "0"\r
-            sio_ibuf = "00000000"\r
-            sio_info = "00"\r
-            sio_obuf = "00000000"\r
-            sio_refsel = "00000000"\r
-            sio_vtrip = "00000000"\r
-            slew_rate = "0"\r
-            spanning = 0\r
-            sw_only = 0\r
-            use_annotation = "0"\r
-            vtrip = "00"\r
-            width = 1\r
-        }\r
-    and contains the following IO cells:\r
-[IoId=6]: \r
-Pin : Name = \USBFS:Dp(0)\\r
-    Attributes:\r
-        In Group/Port: True\r
-        In Sync Option: SYNC\r
-        Out Sync Option: AUTO\r
-        Interrupt generated: True\r
-        Interrupt mode: FALLING\r
-        Drive mode: HI_Z_ANALOG\r
-        VTrip: CMOS\r
-        Slew: FAST\r
-        Input Sync needed: True\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: False\r
-        Is OE Registered: False\r
-        Uses Analog: True\r
-        Can contain Digital: True\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: USB_D_PLUS\r
-        Initial Value: 0\r
-        IO Voltage: 0\r
-    PORT MAP (\r
-        pa_out => \USBFS:Dp(0)\__PA ,\r
-        analog_term => \USBFS:Net_1000\ ,\r
-        pad => \USBFS:Dp(0)_PAD\ );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-[IoId=7]: \r
-Pin : Name = \USBFS:Dm(0)\\r
-    Attributes:\r
-        In Group/Port: True\r
-        In Sync Option: AUTO\r
-        Out Sync Option: AUTO\r
-        Interrupt generated: False\r
-        Interrupt mode: NONE\r
-        Drive mode: HI_Z_ANALOG\r
-        VTrip: EITHER\r
-        Slew: FAST\r
-        Input Sync needed: False\r
-        Output Sync needed: False\r
-        SC shield enabled: False\r
-        POR State: ANY\r
-        LCD Mode: COMMON\r
-        Register Mode: RegComb\r
-        CaSense Mode: NEITHER\r
-        Treat as pin: True\r
-        Is OE Registered: False\r
-        Uses Analog: True\r
-        Can contain Digital: False\r
-        Is SIO: False\r
-        SIO Output Buf: NONREGULATED\r
-        SIO Input Buf: SINGLE_ENDED\r
-        SIO HiFreq: LOW\r
-        SIO Hyst: DISABLED\r
-        SIO Vtrip: MULTIPLIER_0_5\r
-        SIO RefSel: VCC_IO\r
-        Required Capabilitites: USB_D_MINUS\r
-        Initial Value: 0\r
-        IO Voltage: 0\r
-    PORT MAP (\r
-        pa_out => \USBFS:Dm(0)\__PA ,\r
-        analog_term => \USBFS:Net_597\ ,\r
-        pad => \USBFS:Dm(0)_PAD\ );\r
-    Properties:\r
-    {\r
-    }\r
-\r
-Fixed Function block hod @ [FFB(CAN,0)]: empty\r
-Fixed Function block hod @ [FFB(Cache,0)]: empty\r
-Fixed Function block hod @ [FFB(CapSense,0)]: empty\r
-Fixed Function block hod @ [FFB(Clock,0)]: \r
-    Clock Block @ [FFB(Clock,0)]: \r
-    clockblockcell: Name =ClockBlock\r
-        PORT MAP (\r
-            clk_bus_glb => ClockBlock_BUS_CLK ,\r
-            clk_bus => ClockBlock_BUS_CLK_local ,\r
-            clk_sync => ClockBlock_MASTER_CLK ,\r
-            clk_32k_xtal => ClockBlock_XTAL_32KHZ ,\r
-            xtal => ClockBlock_XTAL ,\r
-            ilo => ClockBlock_ILO ,\r
-            clk_100k => ClockBlock_100k ,\r
-            clk_1k => ClockBlock_1k ,\r
-            clk_32k => ClockBlock_32k ,\r
-            pllout => ClockBlock_PLL_OUT ,\r
-            imo => ClockBlock_IMO );\r
-        Properties:\r
-        {\r
-        }\r
-Fixed Function block hod @ [FFB(Comparator,0)]: empty\r
-Fixed Function block hod @ [FFB(DFB,0)]: empty\r
-Fixed Function block hod @ [FFB(DSM,0)]: empty\r
-Fixed Function block hod @ [FFB(Decimator,0)]: empty\r
-Fixed Function block hod @ [FFB(EMIF,0)]: empty\r
-Fixed Function block hod @ [FFB(I2C,0)]: empty\r
-Fixed Function block hod @ [FFB(LCD,0)]: empty\r
-Fixed Function block hod @ [FFB(LVD,0)]: empty\r
-Fixed Function block hod @ [FFB(PM,0)]: empty\r
-Fixed Function block hod @ [FFB(SPC,0)]: empty\r
-Fixed Function block hod @ [FFB(Timer,0)]: empty\r
-Fixed Function block hod @ [FFB(USB,0)]: \r
-    USB Block @ [FFB(USB,0)]: \r
-    usbcell: Name =\USBFS:USB\\r
-        PORT MAP (\r
-            dp => \USBFS:Net_1000\ ,\r
-            dm => \USBFS:Net_597\ ,\r
-            sof_int => Net_40 ,\r
-            arb_int => \USBFS:Net_79\ ,\r
-            usb_int => \USBFS:Net_81\ ,\r
-            ept_int_8 => \USBFS:ept_int_8\ ,\r
-            ept_int_7 => \USBFS:ept_int_7\ ,\r
-            ept_int_6 => \USBFS:ept_int_6\ ,\r
-            ept_int_5 => \USBFS:ept_int_5\ ,\r
-            ept_int_4 => \USBFS:ept_int_4\ ,\r
-            ept_int_3 => \USBFS:ept_int_3\ ,\r
-            ept_int_2 => \USBFS:ept_int_2\ ,\r
-            ept_int_1 => \USBFS:ept_int_1\ ,\r
-            ept_int_0 => \USBFS:ept_int_0\ ,\r
-            ord_int => \USBFS:Net_95\ ,\r
-            dma_req_7 => \USBFS:dma_req_7\ ,\r
-            dma_req_6 => \USBFS:dma_req_6\ ,\r
-            dma_req_5 => \USBFS:dma_req_5\ ,\r
-            dma_req_4 => \USBFS:dma_req_4\ ,\r
-            dma_req_3 => \USBFS:dma_req_3\ ,\r
-            dma_req_2 => \USBFS:dma_req_2\ ,\r
-            dma_req_1 => \USBFS:dma_req_1\ ,\r
-            dma_req_0 => \USBFS:dma_req_0\ ,\r
-            dma_termin => \USBFS:Net_824\ );\r
-        Properties:\r
-        {\r
-            cy_registers = ""\r
-        }\r
-Fixed Function block hod @ [FFB(VIDAC,0)]: empty\r
-Fixed Function block hod @ [FFB(CsAbuf,0)]: empty\r
-Fixed Function block hod @ [FFB(Vref,0)]: empty\r
-Fixed Function block hod @ [FFB(LPF,0)]: empty\r
-Fixed Function block hod @ [FFB(SAR,0)]: empty\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Port Configuration Details">\r
-\r
-------------------------------------------------------------\r
-Port Configuration report\r
-------------------------------------------------------------\r
-     |     |       | Interrupt |                  |                 | \r
-Port | Pin | Fixed |      Type |       Drive Mode |            Name | Connections\r
------+-----+-------+-----------+------------------+-----------------+-------------------------\r
-   0 |   0 |     * |      NONE |         CMOS_OUT |     SCSI_Out(9) | \r
-     |   1 |     * |      NONE |         CMOS_OUT |     SCSI_Out(8) | \r
-     |   2 |     * |      NONE |         CMOS_OUT |     SCSI_Out(7) | \r
-     |   3 |     * |      NONE |         CMOS_OUT |     SCSI_Out(6) | \r
-     |   4 |     * |      NONE |         CMOS_OUT |     SCSI_Out(5) | \r
-     |   5 |     * |      NONE |         CMOS_OUT |     SCSI_Out(4) | \r
-     |   6 |     * |      NONE |         CMOS_OUT |     SCSI_Out(3) | \r
-     |   7 |     * |      NONE |         CMOS_OUT |     SCSI_Out(2) | \r
------+-----+-------+-----------+------------------+-----------------+-------------------------\r
-   3 |   1 |     * |      NONE |      RES_PULL_UP |    SD_PULLUP(0) | \r
-     |   2 |     * |      NONE |      RES_PULL_UP |    SD_PULLUP(1) | \r
-     |   3 |     * |      NONE |      RES_PULL_UP |    SD_PULLUP(2) | \r
-     |   4 |     * |      NONE |      RES_PULL_UP |    SD_PULLUP(3) | \r
-     |   5 |     * |      NONE |      RES_PULL_UP |    SD_PULLUP(4) | \r
------+-----+-------+-----------+------------------+-----------------+-------------------------\r
-   4 |   2 |     * |      NONE |         CMOS_OUT |     SCSI_Out(1) | \r
-     |   3 |     * |      NONE |         CMOS_OUT |     SCSI_Out(0) | \r
-     |   4 |     * |      NONE |         CMOS_OUT | SCSI_Out_DBx(7) | \r
-     |   5 |     * |      NONE |         CMOS_OUT | SCSI_Out_DBx(6) | \r
-     |   6 |     * |      NONE |         CMOS_OUT | SCSI_Out_DBx(5) | \r
-     |   7 |     * |      NONE |         CMOS_OUT | SCSI_Out_DBx(4) | \r
------+-----+-------+-----------+------------------+-----------------+-------------------------\r
-   6 |   0 |     * |      NONE |         CMOS_OUT | SCSI_Out_DBx(3) | \r
-     |   1 |     * |      NONE |         CMOS_OUT | SCSI_Out_DBx(2) | \r
-     |   2 |     * |      NONE |         CMOS_OUT | SCSI_Out_DBx(1) | \r
-     |   3 |     * |      NONE |         CMOS_OUT | SCSI_Out_DBx(0) | \r
------+-----+-------+-----------+------------------+-----------------+-------------------------\r
-  15 |   6 |     * |   FALLING |      HI_Z_ANALOG |   \USBFS:Dp(0)\ | Analog(\USBFS:Net_1000\)\r
-     |   7 |     * |      NONE |      HI_Z_ANALOG |   \USBFS:Dm(0)\ | Analog(\USBFS:Net_597\)\r
-----------------------------------------------------------------------------------------------\r
-</CYPRESSTAG>\r
-</CYPRESSTAG>\r
-</CYPRESSTAG>\r
-Digital component placer commit/Report: Elapsed time ==> 0s.359ms\r
-Digital Placement phase: Elapsed time ==> 7s.578ms\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Digital Routing">\r
-Routing successful.\r
-Digital Routing phase: Elapsed time ==> 9s.796ms\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Bitstream and API generation">\r
-Bitstream and API generation phase: Elapsed time ==> 25s.390ms\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Bitstream verification">\r
-Bitstream verification phase: Elapsed time ==> 0s.158ms\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Static timing analysis">\r
-Timing report is in USB_Bootloader_timing.html.\r
-Static timing analysis phase: Elapsed time ==> 4s.278ms\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Data reporting">\r
-Data reporting phase: Elapsed time ==> 0s.000ms\r
-</CYPRESSTAG>\r
-<CYPRESSTAG name="Database update...">\r
-Design database save phase: Elapsed time ==> 0s.656ms\r
-</CYPRESSTAG>\r
-cydsfit: Elapsed time ==> 50s.921ms\r
-</CYPRESSTAG>\r
-Fitter phase: Elapsed time ==> 50s.997ms\r
-API generation phase: Elapsed time ==> 24s.640ms\r
-Dependency generation phase: Elapsed time ==> 0s.859ms\r
-Cleanup phase: Elapsed time ==> 0s.844ms\r

diff --git a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader_timing.html b/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader_timing.html
deleted file mode 100644 (file)
index d079f1a..0000000
--- a/software/SCSI2SD/v3/USB_Bootloader.cydsn/USB_Bootloader_timing.html
+++ /dev/null
@@ -1,642 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>\r
-<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd">\r
-<html xmlns="http://www.w3.org/1999/xhtml">\r
-<head>\r
-<title>Static Timing Analysis Report</title>\r
-<style type="text/css">\r
-<!--\r
-body { \r
-    font:normal normal 100%/1.0 verdana, times new roman, serif, sans-serif; \r
-}\r
-\r
-table.sta_tsu > thead > tr > th.Delay,\r
-table.sta_tsu > tbody > tr > td.Delay,\r
-table.sta_tscs > thead > tr > th.Period,\r
-table.sta_tscs > tbody > tr > td.Period,\r
-table.sta_tscs > thead > tr > th.MaxFreq,\r
-table.sta_tscs > tbody > tr > td.MaxFreq,\r
-table.sta_tscs > thead > tr > th.Frequency,\r
-table.sta_tscs > tbody > tr > td.Frequency,\r
-table.sta_tco > thead > tr > th.Delay,\r
-table.sta_tco > tbody > tr > td.Delay,\r
-table.sta_tpd > thead > tr > th.Delay,\r
-table.sta_tpd > tbody > tr > td.Delay,\r
-table.sta_toe > thead > tr > th.Delay,\r
-table.sta_toe > tbody > tr > td.Delay,\r
-table.sta_tcoe > thead > tr > th.Delay,\r
-table.sta_tcoe > tbody > tr > td.Delay,\r
-table.sta_path > thead > tr > th.Delay,\r
-table.sta_path > tbody > tr > td.Delay,\r
-table.sta_path > thead > tr > th.Total,\r
-table.sta_path > tbody > tr > td.Total,\r
-table.sta_clocksummary > thead > tr > th.ActualFreq,\r
-table.sta_clocksummary > tbody > tr > td.ActualFreq,\r
-table.sta_clocksummary > thead > tr > th.MaxFreq,\r
-table.sta_clocksummary > tbody > tr > td.MaxFreq,\r
-table > tbody > tr > td.number\r
-{\r
-       text-align: right;\r
-}\r
-\r
-\r
-table.sta_tsu {\r
-   border: solid 2px;\r
-   border-collapse: collapse;\r
-   width: 90%;\r
-}\r
-\r
-table.sta_tpd {\r
-   border: solid 2px;\r
-   border-collapse: collapse;\r
-   width: 90%;\r
-}\r
-\r
-table.sta_tscs {\r
-   border: solid 2px;\r
-   border-collapse: collapse;\r
-   width: 90%;\r
-}\r
-\r
-table.sta_tco {\r
-   border: solid 2px;\r
-   border-collapse: collapse;\r
-   width: 90%;\r
-}\r
-\r
-table.sta_toe {\r
-   border: solid 2px;\r
-   border-collapse: collapse;\r
-   width: 90%;\r
-}\r
-\r
-table.sta_tcoe {\r
-   border: solid 2px;\r
-   border-collapse: collapse;\r
-   width: 90%;\r
-}\r
-\r
-th {\r
-   border: solid 1px;\r
-   vertical-align: top;\r
-   font-family: monospace;\r
-   text-align: center;\r
-   white-space: pre-line;\r
-}\r
-\r
-td {\r
-   border: solid 1px;\r
-   vertical-align: top;\r
-   font-family: monospace;\r
-   white-space: pre-line;\r
-}\r
-\r
-table.sta_tpd > tbody > tr:hover,\r
-table.sta_tsu > tbody > tr:hover,\r
-table.sta_tscs > tbody > tr:hover,\r
-table.sta_tco > tbody > tr:hover,\r
-table.sta_toe > tbody > tr:hover,\r
-table.sta_tcoe > tbody > tr:hover\r
-{\r
-   background-color: #e8e8ff;\r
-}\r
-\r
-table.sta_path > tbody > tr:hover {\r
-   background-color: #e8e8ff;\r
-}\r
-\r
-table.sta_path {\r
-   background-color: #f8f8f8;\r
-   border: none;\r
-   border-collapse: collapse;\r
-   width: 90%;\r
-   margin-left: 1em;\r
-   margin-right: 1em;\r
-}\r
-\r
-table.sta_clocksummary {\r
-   border: solid 2px;\r
-   border-collapse: collapse;\r
-}\r
-\r
-div.sta_sec {\r
-   padding: 0.5em;\r
-}\r
-\r
-div.sta_sec div.sta_sec {\r
-   margin-left: 0.75em;\r
-}\r
-\r
-.proptext {\r
-   font:normal normal 100%/1.0 verdana, times new roman, serif, sans-serif;\r
-   border: 0px;\r
-}\r
-\r
-.prop {\r
-   font: normal normal 100%/1.0 verdana, times new roman, serif, sans-serif;\r
-   font-weight: bolder;\r
-   border: 0px;\r
-}\r
-\r
-.sec_head {\r
-   display: block;\r
-   font-size: 1.17em;\r
-   font-weight: bolder;\r
-   margin: .83em 0;\r
-}\r
-\r
-div.sta_secbody {\r
-   margin-left: 0.75em;\r
-}\r
-\r
-div.vio_sta_secbody {\r
-   margin-left: 0.75em;\r
-}\r
-\r
-.sta_sec_desc {\r
-   margin-bottom: 0.5em;\r
-   white-space: pre-line;\r
-}\r
-\r
-.violation_color {\r
-   color: red;\r
-   border-color: black;\r
-}\r
-\r
--->\r
-</style>   \r
-<script type="text/javascript">\r
-<!--\r
-\r
-function HideElement(element)  {\r
-    var headerDiv = getChildElementsByTagName(element, "div")[0];\r
-    var expandLink = getChildElementsByTagName(headerDiv, "a")[0];\r
-    expandLink.onclick = clicked;\r
-    var children = element.childNodes;\r
-    var secBody = null;\r
-    for (var j = 0; j < children.length; j++)\r
-    {\r
-        if (children[j].nodeType == document.ELEMENT_NODE &&\r
-            (children[j].className == "sta_secbody" ||\r
-             children[j].className == "vio_sta_secbody" ||\r
-             children[j].className == "sta_sec" )) \r
-        {\r
-            secBody = children[j];\r
-            secBody.style.display = "none";\r
-        }\r
-    }\r
-}\r
-\r
-function HideElements(elements)  {\r
-    for( var i=0; i<elements.length; i++)\r
-        HideElement(elements[i]);\r
-}\r
-\r
-\r
-// Description : returns boolean indicating whether the object has the class name\r
-//    built with the understanding that there may be multiple classes\r
-//\r
-// Arguments:\r
-//    objElement              - element to check for.\r
-//    strClass                - class name to be checked.\r
-//\r
-function HasClassName(objElement, strClass)\r
-{\r
-    if ( objElement.className )\r
-    {\r
-        // the classes are just a space separated list, so first get the list\r
-        var arrList = objElement.className.split(' ');\r
-\r
-        for ( var i = 0; i < arrList.length; i++ )\r
-        {\r
-            if ( arrList[i] == strClass )\r
-            {\r
-                return true;\r
-            }\r
-        }\r
-    }\r
-    return false;\r
-}\r
-\r
-function initialize() {\r
-    if (document.ELEMENT_NODE == null)\r
-    {\r
-        /* Workaround for old IE */\r
-        document.ELEMENT_NODE = 1;\r
-        document.ATTRIBUTE_NODE = 2;\r
-        document.TEXT_NODE = 3;\r
-        document.CDATA_SECTION_MODE = 4;\r
-        document.ENTITY_REFERENCE_MODE = 5;\r
-        document.ENTITY_NODE = 6;\r
-        document.PROCESSING_INSTRUCTION_NODE = 7;\r
-        document.COMMENT_NODE = 8;\r
-        document.DOCUMENT_NODE = 9;\r
-        document.DOCUMENT_TYPE_NODE = 10;\r
-        document.DOCUMENT_FRAGMENT_NODE = 11;\r
-        document.NOTATION_NODE = 12;\r
-    }\r
-    \r
-    HideElements(getElementsByClass(document, 'div', 'sta_sec'));\r
-    toggleExpandSection(document.getElementById('clock_summary'));\r
-    toggleExpandSection(document.getElementById('violations'));\r
-\r
-    var allTD = document.getElementsByTagName("td");\r
-    for( var i=0; i< allTD.length; i++)\r
-    {\r
-        if(allTD[i].className != "proptext" && allTD[i].innerHTML.match(/^\s*[-]?[0-9]+[\.]?[0-9]*$/))\r
-        {\r
-            allTD[i].align = "right";\r
-            //allTD[i].style.textAlign = "right";\r
-        }\r
-    }\r
-\r
-    var allTables = document.getElementsByTagName("table");\r
-    for (var i = 0; i < allTables.length; i++)\r
-    {\r
-        var table = allTables[i];\r
-        if (table.className == "sta_tsu" ||\r
-            table.className == "sta_tscs" ||\r
-            table.className == "sta_tco" ||\r
-            table.className == "sta_toe" ||\r
-            table.className == "sta_tcoe")\r
-        {\r
-            var tbodyList = getChildElementsByTagName(table, "tbody");\r
-            if (tbodyList.length != 0)\r
-            {\r
-                for (var row = tbodyList[0].firstChild; row != null; row = row.nextSibling)\r
-                {\r
-                    if (row.nodeName.toLowerCase() == "tr")\r
-                    {\r
-                        if (HasClassName(row,"sta_path"))\r
-                        {\r
-                            row.style.display = "none";\r
-                        }\r
-                        else\r
-                        {\r
-                            row.style.cursor = "pointer";\r
-                            row.onclick = rowClicked;\r
-                        }\r
-                    }\r
-                }\r
-            }\r
-        }\r
-        else if(table.className == "sta_tpd" )\r
-        {\r
-            var tbodyList = getChildElementsByTagName(table, "tbody");\r
-            if (tbodyList.length != 0)\r
-            {\r
-                for (var row = tbodyList[0].firstChild; row != null; row = row.nextSibling)\r
-                {\r
-                    if (row.nodeName.toLowerCase() == "tr")\r
-                    {\r
-                        if(HasClassName(row, "sta_tv"))\r
-                        {\r
-                            row.style.cursor = "pointer";\r
-                            row.onclick = violationClicked;\r
-                        }\r
-                    }\r
-                }\r
-            }\r
-        }\r
-    }\r
-}\r
-\r
-function clicked()\r
-{\r
-    var parent = findAncestorByClass(this, "sta_sec");\r
-    toggleExpandSection(parent);\r
-    return false;\r
-}\r
-\r
-function toggleExpandSection(section)\r
-{\r
-    if (section == null)\r
-        return false;\r
-\r
-    var children = section.childNodes;\r
-    for (var i = 0; i < children.length; i++)\r
-    {\r
-        if (children[i].nodeType == document.ELEMENT_NODE &&\r
-            (children[i].className == "sta_secbody" ||\r
-             children[i].className == "vio_sta_secbody"))\r
-            toggleVisible(children[i]);\r
-    }\r
-}\r
-\r
-function findAncestorByClass(node, className)\r
-{\r
-    var parent;\r
-    for (parent = node; parent != null; parent = parent.parentNode)\r
-    {\r
-        if (parent.nodeType == document.ELEMENT_NODE &&\r
-            parent.className == className)\r
-        {\r
-            return parent;\r
-        }\r
-    }\r
-\r
-    return null;\r
-}\r
-\r
-function rowClicked()\r
-{\r
-    for (var next = this.nextSibling; next != null; next = next.nextSibling)\r
-    {\r
-        if (next.nodeType == document.ELEMENT_NODE &&\r
-            next.nodeName.toLowerCase() == "tr" &&\r
-            HasClassName(next,"sta_path"))\r
-        {\r
-            if (next.style.display == "none")\r
-                next.style.display = "table-row";\r
-            else\r
-                next.style.display = "none";\r
-            break;\r
-        }\r
-    }\r
-    return false;\r
-}\r
-function findPos(obj)\r
-{\r
-    var curtop = 0;\r
-    if (obj.offsetParent)\r
-    {\r
-        do\r
-        {\r
-            curtop += obj.offsetTop;\r
-        } while (obj = obj.offsetParent);\r
-        return [curtop];\r
-    }\r
-}\r
-\r
-function jumpto(ClassName)\r
-{\r
-    var classname = 'sta_path';\r
-    classname += ' ';\r
-    classname += ClassName;\r
-    if((obj = getElementsByClass(document, 'tr', classname)) &&\r
-            obj.length > 0 ){\r
-        window.scrollTo(0, findPos(obj[0]));\r
-    }\r
-}\r
-\r
-function violationClicked()\r
-{\r
-    expandAllSections(0);\r
-    expandViolations(1);\r
-    var ident=this.id;\r
-    var rlist= document.getElementsByTagName( "tr");\r
-\r
-    var clickedElementClassNames = this.className.split(' ');\r
-\r
-    //The second class name is to match the violation element with the\r
-    //corresponding path element in the detailed section.\r
-    var identificationClassValue = clickedElementClassNames[1];\r
-\r
-    for(var i=0 ; i < rlist.length ; i++)\r
-    {\r
-        if( rlist[i].nodeType == document.ELEMENT_NODE && HasClassName(rlist[i],"sta_path") )\r
-        {\r
-            var staPathClassNames = rlist[i].className.split(' ');\r
-            // Assumption: There will be two class names, one indicating\r
-            // style (sta_path), other to identify elements tv1.\r
-\r
-            if(staPathClassNames.length > 1)\r
-            {\r
-                // Matching second class Names of both elements.\r
-                if(staPathClassNames[1] == identificationClassValue)\r
-                {\r
-\r
-                    var parent= findAncestorByClass ( rlist[i] , "sta_tscs" );\r
-                    if(parent == null)\r
-                        parent= findAncestorByClass ( rlist[i] , "sta_tco" );\r
-                    for( ; (parent!= null && parent.nodeName!="body") ; parent= parent.parentNode )\r
-                    {\r
-                        if( parent.nodeType == document.ELEMENT_NODE && parent.className == "sta_secbody")\r
-                        {\r
-                            //parent.style.display = "block";\r
-                            visible(parent);\r
-                            rlist[i].style.display = "table-row" ;\r
-                            //alert(rlist[i].id);\r
-                        }\r
-                    }\r
-                }\r
-            }\r
-        }\r
-    }\r
-    //document.getElementById(this.id).scrollIntoView(true);\r
-    // location = location + this.id;\r
-    jumpto(identificationClassValue);\r
-    return false;\r
-}\r
-\r
-\r
-function toggleVisible(elem)\r
-{\r
-    if (elem.style.display == "none")\r
-        elem.style.display = "block";\r
-    else\r
-        elem.style.display = "none";\r
-\r
-    headerDiv = getChildElementsByTagName(elem.parentNode, "div")[0];\r
-    link = getChildElementsByTagName(headerDiv, "a")[0];\r
-    innerSpan = getChildElementsByTagName(link, "span")[0];\r
-    textNode = getChildElementsByTagName(innerSpan, "span")[0].firstChild;\r
-    textNode.data = (elem.style.display == "none") ? "+" : "-";\r
-}\r
-\r
-function visible(elem)\r
-{\r
-    elem.style.display = "block";\r
-\r
-    headerDiv = getChildElementsByTagName(elem.parentNode, "div")[0];\r
-    link = getChildElementsByTagName(headerDiv, "a")[0];\r
-    innerSpan = getChildElementsByTagName(link, "span")[0];\r
-    textNode = getChildElementsByTagName(innerSpan, "span")[0].firstChild;\r
-    textNode.data = (elem.style.display == "none") ? "+" : "-";\r
-}\r
-\r
-function getChildElementsByTagName(node, name)\r
-{\r
-    var result = new Array(), i = 0;\r
-    name = name.toLowerCase();\r
-    for (var child = node.firstChild; child != null; child = child.nextSibling)\r
-    {\r
-        if (child.nodeType == document.ELEMENT_NODE &&\r
-            child.nodeName.toLowerCase() == name)\r
-        {\r
-            result[i++] = child;\r
-        }\r
-    }\r
-\r
-    return result;\r
-}\r
-\r
-function expandAllPaths(rootNode, show)\r
-{\r
-    var show = show ? "table-row" : "none";\r
-    var elements = getElementsByClass(rootNode, "tr", "sta_path");\r
-    for (var i = 0; i < elements.length; i++)\r
-    {\r
-        elements[i].style.display = show;\r
-    }\r
-}\r
-\r
-function expandAllSections(show)\r
-{\r
-    var show = show ? "block" : "none";\r
-    var elements = getElementsByClass(document, "div", "sta_secbody");\r
-    for (var i = 0; i < elements.length; i++)\r
-    {\r
-        if (elements[i].style.display != show)\r
-            toggleVisible(elements[i]);\r
-    }\r
-\r
-    var elements1 = getElementsByClass(document, "div", "vio_sta_secbody");\r
-    for (var i = 0; i < elements1.length; i++)\r
-    {\r
-        if (elements1[i].style.display != show)\r
-            toggleVisible(elements1[i]);\r
-    }\r
-}\r
-\r
-function expandViolations(show)\r
-{\r
-    var show = show ? "block" : "none";\r
-    var elements = getElementsByClass(document, "div", "vio_sta_secbody");\r
-    for (var i = 0; i < elements.length; i++)\r
-    {\r
-        if (elements[i].style.display != show)\r
-            toggleVisible(elements[i]);\r
-    }\r
-}\r
-\r
-function expandViolationSections(show)\r
-{\r
-    var show =show ? "block" :"none" ;\r
-}\r
-\r
-function getElementsByClass(rootNode, elemName, className)\r
-{\r
-    var result = new Array(), idx = 0;\r
-    var elements = rootNode.getElementsByTagName(elemName);\r
-    for (var i = 0; i < elements.length; i++)\r
-    {\r
-        if (elements[i].className == className)\r
-            result[idx++] = elements[i];\r
-    }\r
-    return result;\r
-}\r
-\r
-//-->\r
-</script>\r
-</head>\r
-\r
-<body onload="initialize();">\r
-<noscript>\r
-<p style="display: block; border: 1px solid; margin: 4em; padding: 1.5em">View this file with a JavaScript-enabled browser to enable all features.</p>\r
-</noscript>\r
-<h1> Static Timing Analysis </h1>\r
-<table class="property">\r
-<tr> <td class="prop"> Project :</td>\r
-<td class="proptext"> USB_Bootloader</td></tr>\r
-<tr> <td class="prop"> Build Time :</td>\r
-<td class="proptext"> 08/28/14 22:25:58</td></tr>\r
-<tr> <td class="prop"> Device :</td>\r
-<td class="proptext"> CY8C5267AXI-LP051</td></tr>\r
-<tr> <td class="prop"> Temperature :</td>\r
-<td class="proptext"> -40C - 85/125C</td></tr>\r
-<tr> <td class="prop"> Vdda :</td>\r
-<td class="proptext"> 5.00</td></tr>\r
-<tr> <td class="prop"> Vddd :</td>\r
-<td class="proptext"> 5.00</td></tr>\r
-<tr> <td class="prop"> Vio0 :</td>\r
-<td class="proptext"> 5.00</td></tr>\r
-<tr> <td class="prop"> Vio1 :</td>\r
-<td class="proptext"> 5.00</td></tr>\r
-<tr> <td class="prop"> Vio2 :</td>\r
-<td class="proptext"> 5.00</td></tr>\r
-<tr> <td class="prop"> Vio3 :</td>\r
-<td class="proptext"> 5.00</td></tr>\r
-<tr> <td class="prop"> Voltage :</td>\r
-<td class="proptext"> 5.0</td></tr>\r
-<tr> <td class="prop"> Vusb :</td>\r
-<td class="proptext"> 5.00</td></tr>\r
-</table>\r
-<div>\r
-<a href="#" onclick="expandAllSections(1);return false;">Expand All</a> |\r
-<a href="#" onclick="expandAllSections(0);return false;">Collapse All</a> |\r
-<a href="#" onclick="expandAllPaths(document, 1);return false;">Show All Paths</a> |\r
-<a href="#" onclick="expandAllPaths(document, 0);return false;">Hide All Paths</a>\r
-</div>\r
-<div class="sta_sec" id="violations">\r
-<div>\r
-<a href="#" style="text-decoration: none; color: inherit;">\r
-<span class="sec_head"><span style="font-family: monospace;">+</span>\r
-Timing Violation Section</span>\r
-</a>\r
-</div><div class="vio_sta_secbody"><div class="sta_sec_desc">No Timing Violations</div>\r
-</div>\r
-</div>\r
-<div class="sta_sec" id="clock_summary">\r
-<div>\r
-<a href="#" style="text-decoration: none; color: inherit;">\r
-<span class="sec_head"><span style="font-family: monospace;">+</span>\r
-Clock Summary Section</span>\r
-</a>\r
-</div><div class="sta_secbody"><table class="sta_clocksummary">\r
- <thead> \r
-<tr> \r
-<th>Clock</th>\r
-<th>Domain</th>\r
-<th>Nominal Frequency</th>\r
-<th>Required Frequency</th>\r
-<th>Maximum Frequency</th>\r
-<th>Violation</th>\r
-</tr>\r
-</thead> \r
-<tbody>\r
-<tr> \r
- <td class = "text_info">CyILO</td>\r
- <td class = "text_info">CyILO</td>\r
- <td class = "number">100.000&nbsp;kHz</td>\r
- <td class = "number">100.000&nbsp;kHz</td>\r
- <td class = "number"> N/A </td>\r
- <td class = "text_info"> </td>\r
-</tr>\r
-<tr> \r
- <td class = "text_info">CyIMO</td>\r
- <td class = "text_info">CyIMO</td>\r
- <td class = "number">24.000&nbsp;MHz</td>\r
- <td class = "number">24.000&nbsp;MHz</td>\r
- <td class = "number"> N/A </td>\r
- <td class = "text_info"> </td>\r
-</tr>\r
-<tr> \r
- <td class = "text_info">CyMASTER_CLK</td>\r
- <td class = "text_info">CyMASTER_CLK</td>\r
- <td class = "number">64.000&nbsp;MHz</td>\r
- <td class = "number">64.000&nbsp;MHz</td>\r
- <td class = "number"> N/A </td>\r
- <td class = "text_info"> </td>\r
-</tr>\r
-<tr> \r
- <td class = "text_info">CyBUS_CLK</td>\r
- <td class = "text_info">CyMASTER_CLK</td>\r
- <td class = "number">64.000&nbsp;MHz</td>\r
- <td class = "number">64.000&nbsp;MHz</td>\r
- <td class = "number"> N/A </td>\r
- <td class = "text_info"> </td>\r
-</tr>\r
-<tr> \r
- <td class = "text_info">CyPLL_OUT</td>\r
- <td class = "text_info">CyPLL_OUT</td>\r
- <td class = "number">64.000&nbsp;MHz</td>\r
- <td class = "number">64.000&nbsp;MHz</td>\r
- <td class = "number"> N/A </td>\r
- <td class = "text_info"> </td>\r
-</tr>\r
-</tbody>\r
- </table> \r
-</div>\r
-</div>\r
-</body>\r
-</html>
\ No newline at end of file

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml
index 61c4816ad0d755af412072c4281dccad61049287..46533e6fe9484d9bb0176e2c9c7aa375d110f77f 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml
@@ -18,7 +18,7 @@
       <Tool Name="postbuild" Command="" Options="" />
     </Toolchain>
   </Toolchains>
-  <Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" Version="4.0" Type="Bootloadable">
+  <Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" Version="4.0" Type="Bootloadable">
     <CMSIS_SVD_File>SCSI2SD.svd</CMSIS_SVD_File>
     <Datasheet />
     <LinkerFiles>
@@ -27,8 +27,8 @@
       <LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile>
     </LinkerFiles>
     <Folders>
-      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\src">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\src">
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="">..\..\src\main.c</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\diagnostic.c</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\disk.c</File>
@@ -41,6 +41,7 @@
           <File BuildType="BUILD" Toolchain="">..\..\src\sd.c</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\config.c</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\led.c</File>
+          <File BuildType="BUILD" Toolchain="">..\..\src\time.c</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\diagnostic.h</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\disk.h</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\geometry.h</File>
@@ -53,15 +54,16 @@
           <File BuildType="BUILD" Toolchain="">..\..\src\bits.h</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\sd.h</File>
           <File BuildType="BUILD" Toolchain="">..\..\src\config.h</File>
+          <File BuildType="BUILD" Toolchain="">..\..\src\time.h</File>
         </Files>
       </Folder>
-      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+      <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="">.\device.h</File>
         </Files>
       </Folder>
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5">
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.h</File>
           <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.c</File>
           <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cybootloader.c</File>
@@ -206,41 +208,41 @@
           <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\libelf.dll</File>
         </Files>
       </Folder>
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_GCC">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_GCC">
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="ARM GCC">.\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a</File>
         </Files>
       </Folder>
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a</File>
         </Files>
       </Folder>
-      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\IAR">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+      <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\IAR">
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
           <File BuildType="BUILD" Toolchain="IAR">.\Generated_Source\PSoC5\IAR\CyComponentLibrary.a</File>
         </Files>
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\codegentemp">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_441">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_473">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\DP8051_Keil_951">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\DP8051">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\CortexM0">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
       </Folder>
       <Folder BuildType="EXCLUDE" Path=".\CortexM3">
-        <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+        <Files Root="Z:\projects\SCSI2SD\git-timeout\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
       </Folder>
     </Folders>
   </Project>

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit
index 39d0086b59c45f3d4b10433ed2bf8626ebcf02dd..7ac12a4d29e91db8a0b9269b98b55a5df68d5a14 100644 (file)
Binary files a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit differ

diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj
index 9183ed865c122fd2f67449b22114e8d6e3db6252..b30c720a81ba3f9bac7531127202a3ec2a8e5ffc 100755 (executable)
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyprj
@@ -102,6 +102,13 @@
 <build_action v="C_FILE" />
 <PropertyDeltas />
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="time.c" persistent="..\..\src\time.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
 </dependencies>
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
@@ -210,6 +217,13 @@
 <build_action v="NONE" />
 <PropertyDeltas />
 </CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="time.h" persistent="..\..\src\time.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
 </dependencies>
 </CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
 </CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>

diff --git a/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyfit b/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyfit
index dedaf4e618452ae3a240f3e3cde7771cdb36f031..e534dcd33e004ec47e23da71a25f16830557a4ce 100644 (file)
Binary files a/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyfit and b/software/SCSI2SD/v4/USB_Bootloader.cydsn/USB_Bootloader.cyfit differ