Reduce IRQ priority of the SDIO device to speed up USB HS interrupt

handling

diff --git a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sd.c b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sd.c
index cd27bd7418747c8ab303408de7c480e7430d624f..569c8b1c033f243f21158b3348375a79d66f08f8 100644 (file)
--- a/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sd.c
+++ b/STM32CubeMX/2020c/Drivers/STM32F2xx_HAL_Driver/Src/stm32f2xx_hal_sd.c
@@ -430,10 +430,6 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
   /* Enable SDIO Clock */
   __HAL_SD_ENABLE(hsd);
 
-  /* 1ms: required power up waiting time before starting the SD initialization 
-     sequence */
-  HAL_Delay(1);
-
   /* Identify card operating voltage */
   errorstate = SD_PowerON(hsd);
   if(errorstate != HAL_SD_ERROR_NONE)
@@ -1231,22 +1227,22 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
     else
     {
       /* Enable SD DMA transfer */
-      // MM disabled, as this fails on fast cards. __HAL_SD_DMA_ENABLE(hsd);
+      __HAL_SD_DMA_ENABLE(hsd);
 
       if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
       {
         add *= 512U;
+      }
 
-        /* Set Block Size for Card */
-        errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
-        if(errorstate != HAL_SD_ERROR_NONE)
-        {
-          /* Clear all the static flags */
-          __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-          hsd->ErrorCode |= errorstate;
-          hsd->State = HAL_SD_STATE_READY;
-          return HAL_ERROR;
-        }
+      /* Set Block Size for Card */
+      errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_ERROR;
       }
 
       /* Configure the SD DPSM (Data Path State Machine) */
@@ -1256,11 +1252,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
       config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
       config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
       config.DPSM          = SDIO_DPSM_ENABLE;
-
-      // We cannot enable DMA too early on UHS-I class 3 SD cards, or else the
-      // data is just discarded before the dpsm is started.
-      __HAL_SD_DMA_ENABLE(hsd);
-
       (void)SDIO_ConfigData(hsd->Instance, &config);
 
       /* Read Blocks in DMA mode */
@@ -1352,17 +1343,17 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
     {
       add *= 512U;
+    }
 
-      /* Set Block Size for Card */
-      errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
-      if(errorstate != HAL_SD_ERROR_NONE)
-      {
-        /* Clear all the static flags */
-        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-        hsd->ErrorCode |= errorstate;
-        hsd->State = HAL_SD_STATE_READY;
-        return HAL_ERROR;
-      }
+    /* Set Block Size for Card */
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
     }
 
     /* Write Blocks in Polling mode */
@@ -1370,18 +1361,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
     {
       hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
 
-      /* MM: Prepare for write */
-/* TODO
-      SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->RCA << 16));
-      SDIO_CmdInitTypeDef  mm_cmdinit;
-      mm_cmdinit.Argument         = (uint32_t)NumberOfBlocks;
-      mm_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCK_COUNT;
-      mm_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-      mm_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-      mm_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-      (void)SDIO_SendCommand(hsd->Instance, &mm_cmdinit);
-      SDMMC_GetCmdResp1(hsd->Instance, SDMMC_CMD_SET_BLOCK_COUNT, SDIO_CMDTIMEOUT);*/
-
       /* Write Multi Block command */
       errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
     }
@@ -1403,7 +1382,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
     }
 
     /* Enable SDIO DMA transfer */
-    // MM disabled, as this fails on fast cards. __HAL_SD_DMA_ENABLE(hsd);
+    __HAL_SD_DMA_ENABLE(hsd);
 
     /* Enable the DMA Channel */
     if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
@@ -1424,11 +1403,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
       config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
       config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
       config.DPSM          = SDIO_DPSM_ENABLE;
-
-      // We cannot enable DMA too early on UHS-I class 3 SD cards, or else the
-      // data is just discarded before the dpsm is started.
-      __HAL_SD_DMA_ENABLE();
-
       (void)SDIO_ConfigData(hsd->Instance, &config);
 
       return HAL_OK;

diff --git a/STM32CubeMX/2020c/SCSI2SD-V6.ioc b/STM32CubeMX/2020c/SCSI2SD-V6.ioc
index 0f883d08e538fc7d6ef48262577c2da306064e64..98f5b7a9bb84fb5aab39d2fc3fcc98009185fa81 100644 (file)
--- a/STM32CubeMX/2020c/SCSI2SD-V6.ioc
+++ b/STM32CubeMX/2020c/SCSI2SD-V6.ioc
@@ -181,11 +181,11 @@ NVIC.ForceEnableDMAVector=true
 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:false\:false
 NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:false\:false
 NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:false\:false
-NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.OTG_FS_IRQn=true\:1\:0\:true\:false\:true\:false\:true
 NVIC.OTG_HS_IRQn=true\:0\:0\:false\:false\:true\:false\:true
 NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false
 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
-NVIC.SDIO_IRQn=true\:0\:0\:true\:false\:true\:true\:true
+NVIC.SDIO_IRQn=true\:2\:0\:true\:false\:true\:true\:true
 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false
 NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:false\:false

diff --git a/STM32CubeMX/2020c/Src/fsmc.c b/STM32CubeMX/2020c/Src/fsmc.c
index 1b01446fc190bca91946f7a6ecd5170f9d0c89dc..03a1b12ba77de7b705e076b5aa84a71a546d690a 100644 (file)
--- a/STM32CubeMX/2020c/Src/fsmc.c
+++ b/STM32CubeMX/2020c/Src/fsmc.c
@@ -50,28 +50,12 @@ void MX_FSMC_Init(void)
   hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
   hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
   /* Timing */
-
-  // 1 clock to read the address, + 1 for synchroniser skew
   Timing.AddressSetupTime = 2;
   Timing.AddressHoldTime = 1;
-
-  // Writes to device:
-  //   1 for synchroniser skew (dbx also delayed)
-  //   1 to skip hold time
-  //   1 to write data.
-
-  // Reads from device:
-  //   3 for syncroniser
-  //   1 to write back to fsmc bus.
   Timing.DataSetupTime = 4;
-
-  // Allow a clock for us to release signals
-  // Need to avoid both devices acting as outputs
-  // on the multiplexed lines at the same time.
   Timing.BusTurnAroundDuration = 1;
-
-  Timing.CLKDivision = 16; // Ignored for async
-  Timing.DataLatency = 17; // Ignored for async
+  Timing.CLKDivision = 16;
+  Timing.DataLatency = 17;
   Timing.AccessMode = FSMC_ACCESS_MODE_A;
   /* ExtTiming */
 
@@ -121,10 +105,6 @@ static void HAL_FSMC_MspInit(void){
   PE0   ------> FSMC_NBL0
   PE1   ------> FSMC_NBL1
   */
-
-  // MM: GPIO_SPEED_FREQ_MEDIUM is rated up to 50MHz, which is fine as all the
-  // fsmc timings are > 1 (ie. so clock speed / 2 is around 50MHz).
-
   /* GPIO_InitStruct */
   GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 
                           |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 

diff --git a/STM32CubeMX/2020c/Src/sdio.c b/STM32CubeMX/2020c/Src/sdio.c
index 01f716a12e894a3daa41fb98fa46cb6a3a45efbe..f2a0b7cea656aacaff8ba3ef7a84289b011298b1 100644 (file)
--- a/STM32CubeMX/2020c/Src/sdio.c
+++ b/STM32CubeMX/2020c/Src/sdio.c
@@ -40,8 +40,6 @@ void MX_SDIO_SD_Init(void)
   hsd.Init.BusWide = SDIO_BUS_WIDE_1B;
   hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
   hsd.Init.ClockDiv = 0;
-
-  /*
   if (HAL_SD_Init(&hsd) != HAL_OK)
   {
     Error_Handler();
@@ -49,7 +47,8 @@ void MX_SDIO_SD_Init(void)
   if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK)
   {
     Error_Handler();
-  }*/
+  }
+
 }
 
 void HAL_SD_MspInit(SD_HandleTypeDef* sdHandle)
@@ -139,7 +138,7 @@ void HAL_SD_MspInit(SD_HandleTypeDef* sdHandle)
     __HAL_LINKDMA(sdHandle,hdmarx,hdma_sdio_rx);
 
     /* SDIO interrupt Init */
-    HAL_NVIC_SetPriority(SDIO_IRQn, 0, 0);
+    HAL_NVIC_SetPriority(SDIO_IRQn, 2, 0);
     HAL_NVIC_EnableIRQ(SDIO_IRQn);
   /* USER CODE BEGIN SDIO_MspInit 1 */
 

diff --git a/STM32CubeMX/2020c/Src/spi.c b/STM32CubeMX/2020c/Src/spi.c
index 4935bf00a455e915fe9bcbf1eb667ba94735368c..902bdb2d84856420aa8b6afd616a73c8265f36a0 100644 (file)
--- a/STM32CubeMX/2020c/Src/spi.c
+++ b/STM32CubeMX/2020c/Src/spi.c
@@ -37,8 +37,6 @@ void MX_SPI1_Init(void)
   hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
   hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;
   hspi1.Init.NSS = SPI_NSS_SOFT;
-
-  // 13.5Mbaud FPGA device allows up to 25MHz write
   hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
   hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
   hspi1.Init.TIMode = SPI_TIMODE_DISABLE;

diff --git a/STM32CubeMX/2020c/Src/usbd_conf.c b/STM32CubeMX/2020c/Src/usbd_conf.c
index 9b9b800106dcf5be1d9043a42f876a566dff6793..eee1fd89fbe611af2c9d69d0c1732b25441f7e73 100644 (file)
--- a/STM32CubeMX/2020c/Src/usbd_conf.c
+++ b/STM32CubeMX/2020c/Src/usbd_conf.c
@@ -94,7 +94,7 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
     __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
     /* Peripheral interrupt init */
-    HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0);
+    HAL_NVIC_SetPriority(OTG_FS_IRQn, 1, 0);
     HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
   /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
 
@@ -458,12 +458,9 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
   HAL_PCD_RegisterIsoOutIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOOUTIncompleteCallback);
   HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_FS, PCD_ISOINIncompleteCallback);
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
-
-  // Sum of all FIFOs must be <= 320.
   HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80);
   HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40);
-  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x40);
-  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 2, 0x40);
+  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80);
   }
   if (pdev->id == DEVICE_HS) {
   /* Link the driver to the stack. */
@@ -501,9 +498,8 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
   HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_HS, PCD_ISOINIncompleteCallback);
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
   HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_HS, 0x200);
-  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 0, 0x40);
-  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x40);
-  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 2, 0x174);
+  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 0, 0x80);
+  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x174);
   }
   return USBD_OK;
 }

diff --git a/STM32CubeMX/2021/2021.ioc b/STM32CubeMX/2021/2021.ioc
index e3ca27fbc2e0202ccec2e3c0246f1cca027f93ed..fb8897f8b39ba09d7f917e34d73859d8a549c261 100644 (file)
--- a/STM32CubeMX/2021/2021.ioc
+++ b/STM32CubeMX/2021/2021.ioc
@@ -175,11 +175,11 @@ NVIC.ForceEnableDMAVector=true
 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:false\:false\:false
 NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:false\:false\:false
 NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:false\:false\:false
-NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:false\:true
+NVIC.OTG_FS_IRQn=true\:1\:0\:true\:false\:true\:false\:true
 NVIC.OTG_HS_IRQn=true\:0\:0\:false\:false\:true\:false\:true
 NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
-NVIC.SDIO_IRQn=true\:0\:0\:true\:false\:true\:true\:true
+NVIC.SDIO_IRQn=true\:2\:0\:true\:false\:true\:true\:true
 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false
 NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:true\:true\:true
 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:false\:false\:false

diff --git a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c
index 6fffb51416f983d368167efeb95f052f0b364f22..d2a88d750e79aae12bae73a77d6dd63813afd0b8 100644 (file)
--- a/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c
+++ b/STM32CubeMX/2021/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_sd.c
@@ -430,10 +430,6 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd)
   /* Enable SDIO Clock */
   __HAL_SD_ENABLE(hsd);
 
-  /* 1ms: required power up waiting time before starting the SD initialization 
-     sequence */
-  HAL_Delay(1);
-
   /* Identify card operating voltage */
   errorstate = SD_PowerON(hsd);
   if(errorstate != HAL_SD_ERROR_NONE)
@@ -1251,22 +1247,22 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
     else
     {
       /* Enable SD DMA transfer */
-      // MM disabled, as this fails on fast cards. __HAL_SD_DMA_ENABLE(hsd);
+      __HAL_SD_DMA_ENABLE(hsd);
 
       if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
       {
         add *= 512U;
+      }
 
-        /* Set Block Size for Card */
-        errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
-        if(errorstate != HAL_SD_ERROR_NONE)
-        {
-          /* Clear all the static flags */
-          __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-          hsd->ErrorCode |= errorstate;
-          hsd->State = HAL_SD_STATE_READY;
-          return HAL_ERROR;
-        }
+      /* Set Block Size for Card */
+      errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+      if(errorstate != HAL_SD_ERROR_NONE)
+      {
+        /* Clear all the static flags */
+        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+        hsd->ErrorCode |= errorstate;
+        hsd->State = HAL_SD_STATE_READY;
+        return HAL_ERROR;
       }
 
       /* Configure the SD DPSM (Data Path State Machine) */
@@ -1276,11 +1272,6 @@ HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, u
       config.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
       config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
       config.DPSM          = SDIO_DPSM_ENABLE;
-
-      // We cannot enable DMA too early on UHS-I class 3 SD cards, or else the
-      // data is just discarded before the dpsm is started.
-      __HAL_SD_DMA_ENABLE();
-
       (void)SDIO_ConfigData(hsd->Instance, &config);
 
       /* Read Blocks in DMA mode */
@@ -1376,17 +1367,17 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
     if(hsd->SdCard.CardType != CARD_SDHC_SDXC)
     {
       add *= 512U;
+    }
 
-      /* Set Block Size for Card */
-      errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
-      if(errorstate != HAL_SD_ERROR_NONE)
-      {
-        /* Clear all the static flags */
-        __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-        hsd->ErrorCode |= errorstate;
-        hsd->State = HAL_SD_STATE_READY;
-        return HAL_ERROR;
-      }
+    /* Set Block Size for Card */
+    errorstate = SDMMC_CmdBlockLength(hsd->Instance, BLOCKSIZE);
+    if(errorstate != HAL_SD_ERROR_NONE)
+    {
+      /* Clear all the static flags */
+      __HAL_SD_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
+      hsd->ErrorCode |= errorstate;
+      hsd->State = HAL_SD_STATE_READY;
+      return HAL_ERROR;
     }
 
     /* Write Blocks in Polling mode */
@@ -1394,18 +1385,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
     {
       hsd->Context = (SD_CONTEXT_WRITE_MULTIPLE_BLOCK | SD_CONTEXT_DMA);
 
-      /* MM: Prepare for write */
-/* TODO
-      SDMMC_CmdAppCommand(hsd->Instance, (uint32_t)(hsd->RCA << 16));
-      SDIO_CmdInitTypeDef  mm_cmdinit;
-      mm_cmdinit.Argument         = (uint32_t)NumberOfBlocks;
-      mm_cmdinit.CmdIndex         = SDMMC_CMD_SET_BLOCK_COUNT;
-      mm_cmdinit.Response         = SDIO_RESPONSE_SHORT;
-      mm_cmdinit.WaitForInterrupt = SDIO_WAIT_NO;
-      mm_cmdinit.CPSM             = SDIO_CPSM_ENABLE;
-      (void)SDIO_SendCommand(hsd->Instance, &mm_cmdinit);
-      SDMMC_GetCmdResp1(hsd->Instance, SDMMC_CMD_SET_BLOCK_COUNT, SDIO_CMDTIMEOUT);*/
-
       /* Write Multi Block command */
       errorstate = SDMMC_CmdWriteMultiBlock(hsd->Instance, add);
     }
@@ -1427,7 +1406,7 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
     }
 
     /* Enable SDIO DMA transfer */
-    // MM disabled, as this fails on fast cards. __HAL_SD_DMA_ENABLE(hsd);
+    __HAL_SD_DMA_ENABLE(hsd);
 
     /* Enable the DMA Channel */
     if(HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pData, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BLOCKSIZE * NumberOfBlocks)/4U) != HAL_OK)
@@ -1452,11 +1431,6 @@ HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData,
       config.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
       config.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
       config.DPSM          = SDIO_DPSM_ENABLE;
-
-      // We cannot enable DMA too early on UHS-I class 3 SD cards, or else the
-      // data is just discarded before the dpsm is started.
-      __HAL_SD_DMA_ENABLE();
-
       (void)SDIO_ConfigData(hsd->Instance, &config);
 
       return HAL_OK;

diff --git a/STM32CubeMX/2021/Src/fmc.c b/STM32CubeMX/2021/Src/fmc.c
index 995fd15dcb35c9137bac64df83981544733cb3f4..dae179a854648b26d9eea9fd02ae832728dfaf24 100644 (file)
--- a/STM32CubeMX/2021/Src/fmc.c
+++ b/STM32CubeMX/2021/Src/fmc.c
@@ -52,28 +52,12 @@ void MX_FMC_Init(void)
   hsram1.Init.WriteFifo = FMC_WRITE_FIFO_ENABLE;
   hsram1.Init.PageSize = FMC_PAGE_SIZE_NONE;
   /* Timing */
-
-  // 1 clock to read the address, + 1 for synchroniser skew
   Timing.AddressSetupTime = 2;
   Timing.AddressHoldTime = 1;
-
-  // Writes to device:
-  //   1 for synchroniser skew (dbx also delayed)
-  //   1 to skip hold time
-  //   1 to write data.
-
-  // Reads from device:
-  //   3 for syncroniser
-  //   1 to write back to fsmc bus.
   Timing.DataSetupTime = 4;
-
-  // Allow a clock for us to release signals
-  // Need to avoid both devices acting as outputs
-  // on the multiplexed lines at the same time.
   Timing.BusTurnAroundDuration = 1;
-
-  Timing.CLKDivision = 16; // Ignored for async
-  Timing.DataLatency = 17; // Ignored for async
+  Timing.CLKDivision = 16;
+  Timing.DataLatency = 17;
   Timing.AccessMode = FMC_ACCESS_MODE_A;
   /* ExtTiming */
 
@@ -123,10 +107,6 @@ static void HAL_FMC_MspInit(void){
   PE0   ------> FMC_NBL0
   PE1   ------> FMC_NBL1
   */
-
-  // MM: GPIO_SPEED_FREQ_MEDIUM is rated up to 50MHz, which is fine as all the
-  // fsmc timings are > 1 (ie. so clock speed / 2 is around 50MHz).
-
   /* GPIO_InitStruct */
   GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 
                           |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 

diff --git a/STM32CubeMX/2021/Src/sdio.c b/STM32CubeMX/2021/Src/sdio.c
index f8901ce96b4e1718f7e20ac9596fa6432d8e39eb..01e38956cedf03b598b010c876c6b6b72b6b4676 100644 (file)
--- a/STM32CubeMX/2021/Src/sdio.c
+++ b/STM32CubeMX/2021/Src/sdio.c
@@ -40,8 +40,6 @@ void MX_SDIO_SD_Init(void)
   hsd.Init.BusWide = SDIO_BUS_WIDE_1B;
   hsd.Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_ENABLE;
   hsd.Init.ClockDiv = 0;
-
-  /*
   if (HAL_SD_Init(&hsd) != HAL_OK)
   {
     Error_Handler();
@@ -49,7 +47,8 @@ void MX_SDIO_SD_Init(void)
   if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK)
   {
     Error_Handler();
-  }*/
+  }
+
 }
 
 void HAL_SD_MspInit(SD_HandleTypeDef* sdHandle)
@@ -139,7 +138,7 @@ void HAL_SD_MspInit(SD_HandleTypeDef* sdHandle)
     __HAL_LINKDMA(sdHandle,hdmarx,hdma_sdio_rx);
 
     /* SDIO interrupt Init */
-    HAL_NVIC_SetPriority(SDIO_IRQn, 0, 0);
+    HAL_NVIC_SetPriority(SDIO_IRQn, 2, 0);
     HAL_NVIC_EnableIRQ(SDIO_IRQn);
   /* USER CODE BEGIN SDIO_MspInit 1 */
 

diff --git a/STM32CubeMX/2021/Src/spi.c b/STM32CubeMX/2021/Src/spi.c
index aa786dd29b158f294e4771a8adcd1147411b6967..2f9fbfbcbf5d54f8ad1d374470883b5d82a5e578 100644 (file)
--- a/STM32CubeMX/2021/Src/spi.c
+++ b/STM32CubeMX/2021/Src/spi.c
@@ -37,8 +37,6 @@ void MX_SPI1_Init(void)
   hspi1.Init.CLKPolarity = SPI_POLARITY_HIGH;
   hspi1.Init.CLKPhase = SPI_PHASE_2EDGE;
   hspi1.Init.NSS = SPI_NSS_SOFT;
-
-  // 22.5Mbaud. FPGA device allows up to 25MHz write
   hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
   hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
   hspi1.Init.TIMode = SPI_TIMODE_DISABLE;

diff --git a/STM32CubeMX/2021/Src/usbd_conf.c b/STM32CubeMX/2021/Src/usbd_conf.c
index 110da2f9c8bcfbec23b0fd5821c30e18b9a8afe3..5b1012660d1ada227b9323e82101a6c4337616ce 100644 (file)
--- a/STM32CubeMX/2021/Src/usbd_conf.c
+++ b/STM32CubeMX/2021/Src/usbd_conf.c
@@ -101,7 +101,7 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* pcdHandle)
     __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
 
     /* Peripheral interrupt init */
-    HAL_NVIC_SetPriority(OTG_FS_IRQn, 0, 0);
+    HAL_NVIC_SetPriority(OTG_FS_IRQn, 1, 0);
     HAL_NVIC_EnableIRQ(OTG_FS_IRQn);
   /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */
 
@@ -468,8 +468,7 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
   HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_FS, 0x80);
   HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 0, 0x40);
-  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x40);
-  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 2, 0x40);
+  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_FS, 1, 0x80);
   }
   if (pdev->id == DEVICE_HS) {
   /* Link the driver to the stack. */
@@ -508,9 +507,8 @@ USBD_StatusTypeDef USBD_LL_Init(USBD_HandleTypeDef *pdev)
   HAL_PCD_RegisterIsoInIncpltCallback(&hpcd_USB_OTG_HS, PCD_ISOINIncompleteCallback);
 #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
   HAL_PCDEx_SetRxFiFo(&hpcd_USB_OTG_HS, 0x200);
-  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 0, 0x40);
-  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x40);
-  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 2, 0x174);
+  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 0, 0x80);
+  HAL_PCDEx_SetTxFiFo(&hpcd_USB_OTG_HS, 1, 0x174);
   }
   return USBD_OK;
 }