-201404?? 3.4
+20140418 3.4
+ - Critical fix for writes when using non-standard block sizes.
- Fix to ensure SCSI phase bits are set atomically.
- Always return the requested number of bytes for a REQUEST SENSE command
This is required to support the Ensoniq ASR-10.
- Decreased (unused) heap and stack sizes to prepare for a memory
write cache
+ - Increased the maximum sector size to 8192 bytes.
20140416 3.3
- Fix to SCSI Reset handling to avoid lockups
EMU Emulator E4X with EOS 3.00b and E6400 (classic) with Eos 4.01
Ensoniq ASR-X, ASR-10 (from v3.4, 2GB size limit)
HP 16601A logic analyzer
+ Apple IIgs using Apple II High Speed SCSI controller card (from v3.3)
+ Symbolics List Machine XL1200, using 1280 byte sectors (from v3.4)
define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + (32768 / 2) - 1;\r
/*-Sizes-*/\r
define symbol __ICFEDIT_size_cstack__ = 0x2000;\r
-define symbol __ICFEDIT_size_heap__ = 0x0256;\r
+define symbol __ICFEDIT_size_heap__ = 0x0400;\r
/**** End of ICF editor section. ###ICF###*/\r
\r
\r
.ANY (+RW, +ZI)\r
}\r
\r
- ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0256 - 0x2000) EMPTY 0x0256\r
+ ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0400 - 0x2000) EMPTY 0x0400\r
{\r
}\r
\r
/*******************************************************************************
-* File Name: SCSI_CMD_TIMER.c
+* File Name: Debug_Timer.c
* Version 2.50
*
* Description:
* the software package with which this file was provided.
********************************************************************************/
-#include "SCSI_CMD_TIMER.h"
+#include "Debug_Timer.h"
-uint8 SCSI_CMD_TIMER_initVar = 0u;
+uint8 Debug_Timer_initVar = 0u;
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_Init
+* Function Name: Debug_Timer_Init
********************************************************************************
*
* Summary:
* void
*
*******************************************************************************/
-void SCSI_CMD_TIMER_Init(void)
+void Debug_Timer_Init(void)
{
- #if(!SCSI_CMD_TIMER_UsingFixedFunction)
+ #if(!Debug_Timer_UsingFixedFunction)
/* Interrupt State Backup for Critical Region*/
- uint8 SCSI_CMD_TIMER_interruptState;
+ uint8 Debug_Timer_interruptState;
#endif /* Interrupt state back up for Fixed Function only */
- #if (SCSI_CMD_TIMER_UsingFixedFunction)
+ #if (Debug_Timer_UsingFixedFunction)
/* Clear all bits but the enable bit (if it's already set) for Timer operation */
- SCSI_CMD_TIMER_CONTROL &= SCSI_CMD_TIMER_CTRL_ENABLE;
+ Debug_Timer_CONTROL &= Debug_Timer_CTRL_ENABLE;
/* Clear the mode bits for continuous run mode */
#if (CY_PSOC5A)
- SCSI_CMD_TIMER_CONTROL2 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_MODE_MASK));
+ Debug_Timer_CONTROL2 &= ((uint8)(~Debug_Timer_CTRL_MODE_MASK));
#endif /* Clear bits in CONTROL2 only in PSOC5A */
#if (CY_PSOC3 || CY_PSOC5LP)
- SCSI_CMD_TIMER_CONTROL3 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_MODE_MASK));
+ Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_MODE_MASK));
#endif /* CONTROL3 register exists only in PSoC3 OR PSoC5LP */
/* Check if One Shot mode is enabled i.e. RunMode !=0*/
- #if (SCSI_CMD_TIMER_RunModeUsed != 0x0u)
+ #if (Debug_Timer_RunModeUsed != 0x0u)
/* Set 3rd bit of Control register to enable one shot mode */
- SCSI_CMD_TIMER_CONTROL |= 0x04u;
+ Debug_Timer_CONTROL |= 0x04u;
#endif /* One Shot enabled only when RunModeUsed is not Continuous*/
- #if (SCSI_CMD_TIMER_RunModeUsed == 2)
+ #if (Debug_Timer_RunModeUsed == 2)
#if (CY_PSOC5A)
/* Set last 2 bits of control2 register if one shot(halt on
interrupt) is enabled*/
- SCSI_CMD_TIMER_CONTROL2 |= 0x03u;
+ Debug_Timer_CONTROL2 |= 0x03u;
#endif /* Set One-Shot Halt on Interrupt bit in CONTROL2 for PSoC5A */
#if (CY_PSOC3 || CY_PSOC5LP)
/* Set last 2 bits of control3 register if one shot(halt on
interrupt) is enabled*/
- SCSI_CMD_TIMER_CONTROL3 |= 0x03u;
+ Debug_Timer_CONTROL3 |= 0x03u;
#endif /* Set One-Shot Halt on Interrupt bit in CONTROL3 for PSoC3 or PSoC5LP */
#endif /* Remove section if One Shot Halt on Interrupt is not enabled */
- #if (SCSI_CMD_TIMER_UsingHWEnable != 0)
+ #if (Debug_Timer_UsingHWEnable != 0)
#if (CY_PSOC5A)
/* Set the default Run Mode of the Timer to Continuous */
- SCSI_CMD_TIMER_CONTROL2 |= SCSI_CMD_TIMER_CTRL_MODE_PULSEWIDTH;
+ Debug_Timer_CONTROL2 |= Debug_Timer_CTRL_MODE_PULSEWIDTH;
#endif /* Set Continuous Run Mode in CONTROL2 for PSoC5A */
#if (CY_PSOC3 || CY_PSOC5LP)
/* Clear and Set ROD and COD bits of CFG2 register */
- SCSI_CMD_TIMER_CONTROL3 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_RCOD_MASK));
- SCSI_CMD_TIMER_CONTROL3 |= SCSI_CMD_TIMER_CTRL_RCOD;
+ Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_RCOD_MASK));
+ Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_RCOD;
/* Clear and Enable the HW enable bit in CFG2 register */
- SCSI_CMD_TIMER_CONTROL3 &= ((uint8)(~SCSI_CMD_TIMER_CTRL_ENBL_MASK));
- SCSI_CMD_TIMER_CONTROL3 |= SCSI_CMD_TIMER_CTRL_ENBL;
+ Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_ENBL_MASK));
+ Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_ENBL;
/* Set the default Run Mode of the Timer to Continuous */
- SCSI_CMD_TIMER_CONTROL3 |= SCSI_CMD_TIMER_CTRL_MODE_CONTINUOUS;
+ Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_MODE_CONTINUOUS;
#endif /* Set Continuous Run Mode in CONTROL3 for PSoC3ES3 or PSoC5A */
#endif /* Configure Run Mode with hardware enable */
/* Clear and Set SYNCTC and SYNCCMP bits of RT1 register */
- SCSI_CMD_TIMER_RT1 &= ((uint8)(~SCSI_CMD_TIMER_RT1_MASK));
- SCSI_CMD_TIMER_RT1 |= SCSI_CMD_TIMER_SYNC;
+ Debug_Timer_RT1 &= ((uint8)(~Debug_Timer_RT1_MASK));
+ Debug_Timer_RT1 |= Debug_Timer_SYNC;
/*Enable DSI Sync all all inputs of the Timer*/
- SCSI_CMD_TIMER_RT1 &= ((uint8)(~SCSI_CMD_TIMER_SYNCDSI_MASK));
- SCSI_CMD_TIMER_RT1 |= SCSI_CMD_TIMER_SYNCDSI_EN;
+ Debug_Timer_RT1 &= ((uint8)(~Debug_Timer_SYNCDSI_MASK));
+ Debug_Timer_RT1 |= Debug_Timer_SYNCDSI_EN;
/* Set the IRQ to use the status register interrupts */
- SCSI_CMD_TIMER_CONTROL2 |= SCSI_CMD_TIMER_CTRL2_IRQ_SEL;
+ Debug_Timer_CONTROL2 |= Debug_Timer_CTRL2_IRQ_SEL;
#endif /* Configuring registers of fixed function implementation */
/* Set Initial values from Configuration */
- SCSI_CMD_TIMER_WritePeriod(SCSI_CMD_TIMER_INIT_PERIOD);
- SCSI_CMD_TIMER_WriteCounter(SCSI_CMD_TIMER_INIT_PERIOD);
+ Debug_Timer_WritePeriod(Debug_Timer_INIT_PERIOD);
+ Debug_Timer_WriteCounter(Debug_Timer_INIT_PERIOD);
- #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)/* Capture counter is enabled */
- SCSI_CMD_TIMER_CAPTURE_COUNT_CTRL |= SCSI_CMD_TIMER_CNTR_ENABLE;
- SCSI_CMD_TIMER_SetCaptureCount(SCSI_CMD_TIMER_INIT_CAPTURE_COUNT);
+ #if (Debug_Timer_UsingHWCaptureCounter)/* Capture counter is enabled */
+ Debug_Timer_CAPTURE_COUNT_CTRL |= Debug_Timer_CNTR_ENABLE;
+ Debug_Timer_SetCaptureCount(Debug_Timer_INIT_CAPTURE_COUNT);
#endif /* Configure capture counter value */
- #if (!SCSI_CMD_TIMER_UsingFixedFunction)
- #if (SCSI_CMD_TIMER_SoftwareCaptureMode)
- SCSI_CMD_TIMER_SetCaptureMode(SCSI_CMD_TIMER_INIT_CAPTURE_MODE);
+ #if (!Debug_Timer_UsingFixedFunction)
+ #if (Debug_Timer_SoftwareCaptureMode)
+ Debug_Timer_SetCaptureMode(Debug_Timer_INIT_CAPTURE_MODE);
#endif /* Set Capture Mode for UDB implementation if capture mode is software controlled */
- #if (SCSI_CMD_TIMER_SoftwareTriggerMode)
- if (0u == (SCSI_CMD_TIMER_CONTROL & SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE))
+ #if (Debug_Timer_SoftwareTriggerMode)
+ if (0u == (Debug_Timer_CONTROL & Debug_Timer__B_TIMER__TM_SOFTWARE))
{
- SCSI_CMD_TIMER_SetTriggerMode(SCSI_CMD_TIMER_INIT_TRIGGER_MODE);
+ Debug_Timer_SetTriggerMode(Debug_Timer_INIT_TRIGGER_MODE);
}
#endif /* Set trigger mode for UDB Implementation if trigger mode is software controlled */
/* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
/* Enter Critical Region*/
- SCSI_CMD_TIMER_interruptState = CyEnterCriticalSection();
+ Debug_Timer_interruptState = CyEnterCriticalSection();
/* Use the interrupt output of the status register for IRQ output */
- SCSI_CMD_TIMER_STATUS_AUX_CTRL |= SCSI_CMD_TIMER_STATUS_ACTL_INT_EN_MASK;
+ Debug_Timer_STATUS_AUX_CTRL |= Debug_Timer_STATUS_ACTL_INT_EN_MASK;
/* Exit Critical Region*/
- CyExitCriticalSection(SCSI_CMD_TIMER_interruptState);
+ CyExitCriticalSection(Debug_Timer_interruptState);
- #if (SCSI_CMD_TIMER_EnableTriggerMode)
- SCSI_CMD_TIMER_EnableTrigger();
+ #if (Debug_Timer_EnableTriggerMode)
+ Debug_Timer_EnableTrigger();
#endif /* Set Trigger enable bit for UDB implementation in the control register*/
- #if (SCSI_CMD_TIMER_InterruptOnCaptureCount)
- #if (!SCSI_CMD_TIMER_ControlRegRemoved)
- SCSI_CMD_TIMER_SetInterruptCount(SCSI_CMD_TIMER_INIT_INT_CAPTURE_COUNT);
+ #if (Debug_Timer_InterruptOnCaptureCount)
+ #if (!Debug_Timer_ControlRegRemoved)
+ Debug_Timer_SetInterruptCount(Debug_Timer_INIT_INT_CAPTURE_COUNT);
#endif /* Set interrupt count in control register if control register is not removed */
#endif /*Set interrupt count in UDB implementation if interrupt count feature is checked.*/
- SCSI_CMD_TIMER_ClearFIFO();
+ Debug_Timer_ClearFIFO();
#endif /* Configure additional features of UDB implementation */
- SCSI_CMD_TIMER_SetInterruptMode(SCSI_CMD_TIMER_INIT_INTERRUPT_MODE);
+ Debug_Timer_SetInterruptMode(Debug_Timer_INIT_INTERRUPT_MODE);
}
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_Enable
+* Function Name: Debug_Timer_Enable
********************************************************************************
*
* Summary:
* void
*
*******************************************************************************/
-void SCSI_CMD_TIMER_Enable(void)
+void Debug_Timer_Enable(void)
{
/* Globally Enable the Fixed Function Block chosen */
- #if (SCSI_CMD_TIMER_UsingFixedFunction)
- SCSI_CMD_TIMER_GLOBAL_ENABLE |= SCSI_CMD_TIMER_BLOCK_EN_MASK;
- SCSI_CMD_TIMER_GLOBAL_STBY_ENABLE |= SCSI_CMD_TIMER_BLOCK_STBY_EN_MASK;
+ #if (Debug_Timer_UsingFixedFunction)
+ Debug_Timer_GLOBAL_ENABLE |= Debug_Timer_BLOCK_EN_MASK;
+ Debug_Timer_GLOBAL_STBY_ENABLE |= Debug_Timer_BLOCK_STBY_EN_MASK;
#endif /* Set Enable bit for enabling Fixed function timer*/
/* Remove assignment if control register is removed */
- #if (!SCSI_CMD_TIMER_ControlRegRemoved || SCSI_CMD_TIMER_UsingFixedFunction)
- SCSI_CMD_TIMER_CONTROL |= SCSI_CMD_TIMER_CTRL_ENABLE;
+ #if (!Debug_Timer_ControlRegRemoved || Debug_Timer_UsingFixedFunction)
+ Debug_Timer_CONTROL |= Debug_Timer_CTRL_ENABLE;
#endif /* Remove assignment if control register is removed */
}
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_Start
+* Function Name: Debug_Timer_Start
********************************************************************************
*
* Summary:
* void
*
* Global variables:
-* SCSI_CMD_TIMER_initVar: Is modified when this function is called for the
+* Debug_Timer_initVar: Is modified when this function is called for the
* first time. Is used to ensure that initialization happens only once.
*
*******************************************************************************/
-void SCSI_CMD_TIMER_Start(void)
+void Debug_Timer_Start(void)
{
- if(SCSI_CMD_TIMER_initVar == 0u)
+ if(Debug_Timer_initVar == 0u)
{
- SCSI_CMD_TIMER_Init();
+ Debug_Timer_Init();
- SCSI_CMD_TIMER_initVar = 1u; /* Clear this bit for Initialization */
+ Debug_Timer_initVar = 1u; /* Clear this bit for Initialization */
}
/* Enable the Timer */
- SCSI_CMD_TIMER_Enable();
+ Debug_Timer_Enable();
}
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_Stop
+* Function Name: Debug_Timer_Stop
********************************************************************************
*
* Summary:
* has no effect on the operation of the timer.
*
*******************************************************************************/
-void SCSI_CMD_TIMER_Stop(void)
+void Debug_Timer_Stop(void)
{
/* Disable Timer */
- #if(!SCSI_CMD_TIMER_ControlRegRemoved || SCSI_CMD_TIMER_UsingFixedFunction)
- SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_ENABLE));
+ #if(!Debug_Timer_ControlRegRemoved || Debug_Timer_UsingFixedFunction)
+ Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_ENABLE));
#endif /* Remove assignment if control register is removed */
/* Globally disable the Fixed Function Block chosen */
- #if (SCSI_CMD_TIMER_UsingFixedFunction)
- SCSI_CMD_TIMER_GLOBAL_ENABLE &= ((uint8)(~SCSI_CMD_TIMER_BLOCK_EN_MASK));
- SCSI_CMD_TIMER_GLOBAL_STBY_ENABLE &= ((uint8)(~SCSI_CMD_TIMER_BLOCK_STBY_EN_MASK));
+ #if (Debug_Timer_UsingFixedFunction)
+ Debug_Timer_GLOBAL_ENABLE &= ((uint8)(~Debug_Timer_BLOCK_EN_MASK));
+ Debug_Timer_GLOBAL_STBY_ENABLE &= ((uint8)(~Debug_Timer_BLOCK_STBY_EN_MASK));
#endif /* Disable global enable for the Timer Fixed function block to stop the Timer*/
}
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_SetInterruptMode
+* Function Name: Debug_Timer_SetInterruptMode
********************************************************************************
*
* Summary:
* void
*
*******************************************************************************/
-void SCSI_CMD_TIMER_SetInterruptMode(uint8 interruptMode)
+void Debug_Timer_SetInterruptMode(uint8 interruptMode)
{
- SCSI_CMD_TIMER_STATUS_MASK = interruptMode;
+ Debug_Timer_STATUS_MASK = interruptMode;
}
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_SoftwareCapture
+* Function Name: Debug_Timer_SoftwareCapture
********************************************************************************
*
* Summary:
* An existing hardware capture could be overwritten.
*
*******************************************************************************/
-void SCSI_CMD_TIMER_SoftwareCapture(void)
+void Debug_Timer_SoftwareCapture(void)
{
/* Generate a software capture by reading the counter register */
- (void)SCSI_CMD_TIMER_COUNTER_LSB;
+ (void)Debug_Timer_COUNTER_LSB;
/* Capture Data is now in the FIFO */
}
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ReadStatusRegister
+* Function Name: Debug_Timer_ReadStatusRegister
********************************************************************************
*
* Summary:
* Status register bits may be clear on read.
*
*******************************************************************************/
-uint8 SCSI_CMD_TIMER_ReadStatusRegister(void)
+uint8 Debug_Timer_ReadStatusRegister(void)
{
- return (SCSI_CMD_TIMER_STATUS);
+ return (Debug_Timer_STATUS);
}
-#if (!SCSI_CMD_TIMER_ControlRegRemoved) /* Remove API if control register is removed */
+#if (!Debug_Timer_ControlRegRemoved) /* Remove API if control register is removed */
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ReadControlRegister
+* Function Name: Debug_Timer_ReadControlRegister
********************************************************************************
*
* Summary:
* The contents of the control register
*
*******************************************************************************/
-uint8 SCSI_CMD_TIMER_ReadControlRegister(void)
+uint8 Debug_Timer_ReadControlRegister(void)
{
- return ((uint8)SCSI_CMD_TIMER_CONTROL);
+ return ((uint8)Debug_Timer_CONTROL);
}
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_WriteControlRegister
+* Function Name: Debug_Timer_WriteControlRegister
********************************************************************************
*
* Summary:
* Return:
*
*******************************************************************************/
-void SCSI_CMD_TIMER_WriteControlRegister(uint8 control)
+void Debug_Timer_WriteControlRegister(uint8 control)
{
- SCSI_CMD_TIMER_CONTROL = control;
+ Debug_Timer_CONTROL = control;
}
#endif /* Remove API if control register is removed */
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ReadPeriod
+* Function Name: Debug_Timer_ReadPeriod
********************************************************************************
*
* Summary:
* The present value of the counter.
*
*******************************************************************************/
-uint16 SCSI_CMD_TIMER_ReadPeriod(void)
+uint16 Debug_Timer_ReadPeriod(void)
{
- #if(SCSI_CMD_TIMER_UsingFixedFunction)
- return ((uint16)CY_GET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR));
+ #if(Debug_Timer_UsingFixedFunction)
+ return ((uint16)CY_GET_REG16(Debug_Timer_PERIOD_LSB_PTR));
#else
- return (CY_GET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR));
- #endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */
+ return (CY_GET_REG16(Debug_Timer_PERIOD_LSB_PTR));
+ #endif /* (Debug_Timer_UsingFixedFunction) */
}
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_WritePeriod
+* Function Name: Debug_Timer_WritePeriod
********************************************************************************
*
* Summary:
* void
*
*******************************************************************************/
-void SCSI_CMD_TIMER_WritePeriod(uint16 period)
+void Debug_Timer_WritePeriod(uint16 period)
{
- #if(SCSI_CMD_TIMER_UsingFixedFunction)
+ #if(Debug_Timer_UsingFixedFunction)
uint16 period_temp = (uint16)period;
- CY_SET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR, period_temp);
+ CY_SET_REG16(Debug_Timer_PERIOD_LSB_PTR, period_temp);
#else
- CY_SET_REG16(SCSI_CMD_TIMER_PERIOD_LSB_PTR, period);
+ CY_SET_REG16(Debug_Timer_PERIOD_LSB_PTR, period);
#endif /*Write Period value with appropriate resolution suffix depending on UDB or fixed function implementation */
}
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ReadCapture
+* Function Name: Debug_Timer_ReadCapture
********************************************************************************
*
* Summary:
* Present Capture value.
*
*******************************************************************************/
-uint16 SCSI_CMD_TIMER_ReadCapture(void)
+uint16 Debug_Timer_ReadCapture(void)
{
- #if(SCSI_CMD_TIMER_UsingFixedFunction)
- return ((uint16)CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR));
+ #if(Debug_Timer_UsingFixedFunction)
+ return ((uint16)CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
#else
- return (CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR));
- #endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */
+ return (CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
+ #endif /* (Debug_Timer_UsingFixedFunction) */
}
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_WriteCounter
+* Function Name: Debug_Timer_WriteCounter
********************************************************************************
*
* Summary:
* void
*
*******************************************************************************/
-void SCSI_CMD_TIMER_WriteCounter(uint16 counter) \
+void Debug_Timer_WriteCounter(uint16 counter) \
{
- #if(SCSI_CMD_TIMER_UsingFixedFunction)
+ #if(Debug_Timer_UsingFixedFunction)
/* This functionality is removed until a FixedFunction HW update to
* allow this register to be written
*/
- CY_SET_REG16(SCSI_CMD_TIMER_COUNTER_LSB_PTR, (uint16)counter);
+ CY_SET_REG16(Debug_Timer_COUNTER_LSB_PTR, (uint16)counter);
#else
- CY_SET_REG16(SCSI_CMD_TIMER_COUNTER_LSB_PTR, counter);
+ CY_SET_REG16(Debug_Timer_COUNTER_LSB_PTR, counter);
#endif /* Set Write Counter only for the UDB implementation (Write Counter not available in fixed function Timer */
}
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ReadCounter
+* Function Name: Debug_Timer_ReadCounter
********************************************************************************
*
* Summary:
* Present compare value.
*
*******************************************************************************/
-uint16 SCSI_CMD_TIMER_ReadCounter(void)
+uint16 Debug_Timer_ReadCounter(void)
{
/* Force capture by reading Accumulator */
/* Must first do a software capture to be able to read the counter */
/* It is up to the user code to make sure there isn't already captured data in the FIFO */
- (void)SCSI_CMD_TIMER_COUNTER_LSB;
+ (void)Debug_Timer_COUNTER_LSB;
/* Read the data from the FIFO (or capture register for Fixed Function)*/
- #if(SCSI_CMD_TIMER_UsingFixedFunction)
- return ((uint16)CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR));
+ #if(Debug_Timer_UsingFixedFunction)
+ return ((uint16)CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
#else
- return (CY_GET_REG16(SCSI_CMD_TIMER_CAPTURE_LSB_PTR));
- #endif /* (SCSI_CMD_TIMER_UsingFixedFunction) */
+ return (CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR));
+ #endif /* (Debug_Timer_UsingFixedFunction) */
}
-#if(!SCSI_CMD_TIMER_UsingFixedFunction) /* UDB Specific Functions */
+#if(!Debug_Timer_UsingFixedFunction) /* UDB Specific Functions */
/*******************************************************************************
* The functions below this point are only available using the UDB
******************************************************************************/
-#if (SCSI_CMD_TIMER_SoftwareCaptureMode)
+#if (Debug_Timer_SoftwareCaptureMode)
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_SetCaptureMode
+* Function Name: Debug_Timer_SetCaptureMode
********************************************************************************
*
* Summary:
* Parameters:
* captureMode: This parameter sets the capture mode of the UDB capture feature
* The parameter values are defined using the
-* #define SCSI_CMD_TIMER__B_TIMER__CM_NONE 0
-#define SCSI_CMD_TIMER__B_TIMER__CM_RISINGEDGE 1
-#define SCSI_CMD_TIMER__B_TIMER__CM_FALLINGEDGE 2
-#define SCSI_CMD_TIMER__B_TIMER__CM_EITHEREDGE 3
-#define SCSI_CMD_TIMER__B_TIMER__CM_SOFTWARE 4
+* #define Debug_Timer__B_TIMER__CM_NONE 0
+#define Debug_Timer__B_TIMER__CM_RISINGEDGE 1
+#define Debug_Timer__B_TIMER__CM_FALLINGEDGE 2
+#define Debug_Timer__B_TIMER__CM_EITHEREDGE 3
+#define Debug_Timer__B_TIMER__CM_SOFTWARE 4
identifiers
* The following are the possible values of the parameter
-* SCSI_CMD_TIMER__B_TIMER__CM_NONE - Set Capture mode to None
-* SCSI_CMD_TIMER__B_TIMER__CM_RISINGEDGE - Rising edge of Capture input
-* SCSI_CMD_TIMER__B_TIMER__CM_FALLINGEDGE - Falling edge of Capture input
-* SCSI_CMD_TIMER__B_TIMER__CM_EITHEREDGE - Either edge of Capture input
+* Debug_Timer__B_TIMER__CM_NONE - Set Capture mode to None
+* Debug_Timer__B_TIMER__CM_RISINGEDGE - Rising edge of Capture input
+* Debug_Timer__B_TIMER__CM_FALLINGEDGE - Falling edge of Capture input
+* Debug_Timer__B_TIMER__CM_EITHEREDGE - Either edge of Capture input
*
* Return:
* void
*
*******************************************************************************/
-void SCSI_CMD_TIMER_SetCaptureMode(uint8 captureMode)
+void Debug_Timer_SetCaptureMode(uint8 captureMode)
{
/* This must only set to two bits of the control register associated */
- captureMode = ((uint8)((uint8)captureMode << SCSI_CMD_TIMER_CTRL_CAP_MODE_SHIFT));
- captureMode &= (SCSI_CMD_TIMER_CTRL_CAP_MODE_MASK);
+ captureMode = ((uint8)((uint8)captureMode << Debug_Timer_CTRL_CAP_MODE_SHIFT));
+ captureMode &= (Debug_Timer_CTRL_CAP_MODE_MASK);
/* Clear the Current Setting */
- SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_CAP_MODE_MASK));
+ Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_CAP_MODE_MASK));
/* Write The New Setting */
- SCSI_CMD_TIMER_CONTROL |= captureMode;
+ Debug_Timer_CONTROL |= captureMode;
}
#endif /* Remove API if Capture Mode is not Software Controlled */
-#if (SCSI_CMD_TIMER_SoftwareTriggerMode)
+#if (Debug_Timer_SoftwareTriggerMode)
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_SetTriggerMode
+* Function Name: Debug_Timer_SetTriggerMode
********************************************************************************
*
* Summary:
*
* Parameters:
* triggerMode: Pass one of the pre-defined Trigger Modes (except Software)
- #define SCSI_CMD_TIMER__B_TIMER__TM_NONE 0x00u
- #define SCSI_CMD_TIMER__B_TIMER__TM_RISINGEDGE 0x04u
- #define SCSI_CMD_TIMER__B_TIMER__TM_FALLINGEDGE 0x08u
- #define SCSI_CMD_TIMER__B_TIMER__TM_EITHEREDGE 0x0Cu
- #define SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE 0x10u
+ #define Debug_Timer__B_TIMER__TM_NONE 0x00u
+ #define Debug_Timer__B_TIMER__TM_RISINGEDGE 0x04u
+ #define Debug_Timer__B_TIMER__TM_FALLINGEDGE 0x08u
+ #define Debug_Timer__B_TIMER__TM_EITHEREDGE 0x0Cu
+ #define Debug_Timer__B_TIMER__TM_SOFTWARE 0x10u
*
* Return:
* void
*
*******************************************************************************/
-void SCSI_CMD_TIMER_SetTriggerMode(uint8 triggerMode)
+void Debug_Timer_SetTriggerMode(uint8 triggerMode)
{
/* This must only set to two bits of the control register associated */
- triggerMode &= SCSI_CMD_TIMER_CTRL_TRIG_MODE_MASK;
+ triggerMode &= Debug_Timer_CTRL_TRIG_MODE_MASK;
/* Clear the Current Setting */
- SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_TRIG_MODE_MASK));
+ Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_MODE_MASK));
/* Write The New Setting */
- SCSI_CMD_TIMER_CONTROL |= (triggerMode | SCSI_CMD_TIMER__B_TIMER__TM_SOFTWARE);
+ Debug_Timer_CONTROL |= (triggerMode | Debug_Timer__B_TIMER__TM_SOFTWARE);
}
#endif /* Remove API if Trigger Mode is not Software Controlled */
-#if (SCSI_CMD_TIMER_EnableTriggerMode)
+#if (Debug_Timer_EnableTriggerMode)
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_EnableTrigger
+* Function Name: Debug_Timer_EnableTrigger
********************************************************************************
*
* Summary:
* void
*
*******************************************************************************/
-void SCSI_CMD_TIMER_EnableTrigger(void)
+void Debug_Timer_EnableTrigger(void)
{
- #if (!SCSI_CMD_TIMER_ControlRegRemoved) /* Remove assignment if control register is removed */
- SCSI_CMD_TIMER_CONTROL |= SCSI_CMD_TIMER_CTRL_TRIG_EN;
+ #if (!Debug_Timer_ControlRegRemoved) /* Remove assignment if control register is removed */
+ Debug_Timer_CONTROL |= Debug_Timer_CTRL_TRIG_EN;
#endif /* Remove code section if control register is not used */
}
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_DisableTrigger
+* Function Name: Debug_Timer_DisableTrigger
********************************************************************************
*
* Summary:
* void
*
*******************************************************************************/
-void SCSI_CMD_TIMER_DisableTrigger(void)
+void Debug_Timer_DisableTrigger(void)
{
- #if (!SCSI_CMD_TIMER_ControlRegRemoved) /* Remove assignment if control register is removed */
- SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_TRIG_EN));
+ #if (!Debug_Timer_ControlRegRemoved) /* Remove assignment if control register is removed */
+ Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_EN));
#endif /* Remove code section if control register is not used */
}
#endif /* Remove API is Trigger Mode is set to None */
-#if(SCSI_CMD_TIMER_InterruptOnCaptureCount)
-#if (!SCSI_CMD_TIMER_ControlRegRemoved) /* Remove API if control register is removed */
+#if(Debug_Timer_InterruptOnCaptureCount)
+#if (!Debug_Timer_ControlRegRemoved) /* Remove API if control register is removed */
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_SetInterruptCount
+* Function Name: Debug_Timer_SetInterruptCount
********************************************************************************
*
* Summary:
* void
*
*******************************************************************************/
-void SCSI_CMD_TIMER_SetInterruptCount(uint8 interruptCount)
+void Debug_Timer_SetInterruptCount(uint8 interruptCount)
{
/* This must only set to two bits of the control register associated */
- interruptCount &= SCSI_CMD_TIMER_CTRL_INTCNT_MASK;
+ interruptCount &= Debug_Timer_CTRL_INTCNT_MASK;
/* Clear the Current Setting */
- SCSI_CMD_TIMER_CONTROL &= ((uint8)(~SCSI_CMD_TIMER_CTRL_INTCNT_MASK));
+ Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_INTCNT_MASK));
/* Write The New Setting */
- SCSI_CMD_TIMER_CONTROL |= interruptCount;
+ Debug_Timer_CONTROL |= interruptCount;
}
#endif /* Remove API if control register is removed */
-#endif /* SCSI_CMD_TIMER_InterruptOnCaptureCount */
+#endif /* Debug_Timer_InterruptOnCaptureCount */
-#if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
+#if (Debug_Timer_UsingHWCaptureCounter)
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_SetCaptureCount
+* Function Name: Debug_Timer_SetCaptureCount
********************************************************************************
*
* Summary:
* void
*
*******************************************************************************/
-void SCSI_CMD_TIMER_SetCaptureCount(uint8 captureCount)
+void Debug_Timer_SetCaptureCount(uint8 captureCount)
{
- SCSI_CMD_TIMER_CAP_COUNT = captureCount;
+ Debug_Timer_CAP_COUNT = captureCount;
}
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ReadCaptureCount
+* Function Name: Debug_Timer_ReadCaptureCount
********************************************************************************
*
* Summary:
* Returns the Capture Count Setting
*
*******************************************************************************/
-uint8 SCSI_CMD_TIMER_ReadCaptureCount(void)
+uint8 Debug_Timer_ReadCaptureCount(void)
{
- return ((uint8)SCSI_CMD_TIMER_CAP_COUNT);
+ return ((uint8)Debug_Timer_CAP_COUNT);
}
-#endif /* SCSI_CMD_TIMER_UsingHWCaptureCounter */
+#endif /* Debug_Timer_UsingHWCaptureCounter */
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ClearFIFO
+* Function Name: Debug_Timer_ClearFIFO
********************************************************************************
*
* Summary:
* void
*
*******************************************************************************/
-void SCSI_CMD_TIMER_ClearFIFO(void)
+void Debug_Timer_ClearFIFO(void)
{
- while(0u != (SCSI_CMD_TIMER_ReadStatusRegister() & SCSI_CMD_TIMER_STATUS_FIFONEMP))
+ while(0u != (Debug_Timer_ReadStatusRegister() & Debug_Timer_STATUS_FIFONEMP))
{
- (void)SCSI_CMD_TIMER_ReadCapture();
+ (void)Debug_Timer_ReadCapture();
}
}
--- /dev/null
+/*******************************************************************************
+* File Name: Debug_Timer.h
+* Version 2.50
+*
+* Description:
+* Contains the function prototypes and constants available to the timer
+* user module.
+*
+* Note:
+* None
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
+
+#if !defined(CY_Timer_v2_30_Debug_Timer_H)
+#define CY_Timer_v2_30_Debug_Timer_H
+
+#include "cytypes.h"
+#include "cyfitter.h"
+#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */
+
+extern uint8 Debug_Timer_initVar;
+
+/* Check to see if required defines such as CY_PSOC5LP are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5LP)
+ #error Component Timer_v2_50 requires cy_boot v3.0 or later
+#endif /* (CY_ PSOC5LP) */
+
+
+/**************************************
+* Parameter Defaults
+**************************************/
+
+#define Debug_Timer_Resolution 16u
+#define Debug_Timer_UsingFixedFunction 1u
+#define Debug_Timer_UsingHWCaptureCounter 0u
+#define Debug_Timer_SoftwareCaptureMode 0u
+#define Debug_Timer_SoftwareTriggerMode 0u
+#define Debug_Timer_UsingHWEnable 0u
+#define Debug_Timer_EnableTriggerMode 0u
+#define Debug_Timer_InterruptOnCaptureCount 0u
+#define Debug_Timer_RunModeUsed 0u
+#define Debug_Timer_ControlRegRemoved 0u
+
+
+/***************************************
+* Type defines
+***************************************/
+
+
+/**************************************************************************
+ * Sleep Wakeup Backup structure for Timer Component
+ *************************************************************************/
+typedef struct
+{
+ uint8 TimerEnableState;
+ #if(!Debug_Timer_UsingFixedFunction)
+ #if (CY_UDB_V0)
+ uint16 TimerUdb; /* Timer internal counter value */
+ uint16 TimerPeriod; /* Timer Period value */
+ uint8 InterruptMaskValue; /* Timer Compare Value */
+ #if (Debug_Timer_UsingHWCaptureCounter)
+ uint8 TimerCaptureCounter; /* Timer Capture Counter Value */
+ #endif /* variable declaration for backing up Capture Counter value*/
+ #endif /* variables for non retention registers in CY_UDB_V0 */
+
+ #if (CY_UDB_V1)
+ uint16 TimerUdb;
+ uint8 InterruptMaskValue;
+ #if (Debug_Timer_UsingHWCaptureCounter)
+ uint8 TimerCaptureCounter;
+ #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */
+ #endif /* (CY_UDB_V1) */
+
+ #if (!Debug_Timer_ControlRegRemoved)
+ uint8 TimerControlRegister;
+ #endif /* variable declaration for backing up enable state of the Timer */
+ #endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */
+}Debug_Timer_backupStruct;
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+void Debug_Timer_Start(void) ;
+void Debug_Timer_Stop(void) ;
+
+void Debug_Timer_SetInterruptMode(uint8 interruptMode) ;
+uint8 Debug_Timer_ReadStatusRegister(void) ;
+/* Deprecated function. Do not use this in future. Retained for backward compatibility */
+#define Debug_Timer_GetInterruptSource() Debug_Timer_ReadStatusRegister()
+
+#if(!Debug_Timer_ControlRegRemoved)
+ uint8 Debug_Timer_ReadControlRegister(void) ;
+ void Debug_Timer_WriteControlRegister(uint8 control) \
+ ;
+#endif /* (!Debug_Timer_ControlRegRemoved) */
+
+uint16 Debug_Timer_ReadPeriod(void) ;
+void Debug_Timer_WritePeriod(uint16 period) \
+ ;
+uint16 Debug_Timer_ReadCounter(void) ;
+void Debug_Timer_WriteCounter(uint16 counter) \
+ ;
+uint16 Debug_Timer_ReadCapture(void) ;
+void Debug_Timer_SoftwareCapture(void) ;
+
+
+#if(!Debug_Timer_UsingFixedFunction) /* UDB Prototypes */
+ #if (Debug_Timer_SoftwareCaptureMode)
+ void Debug_Timer_SetCaptureMode(uint8 captureMode) ;
+ #endif /* (!Debug_Timer_UsingFixedFunction) */
+
+ #if (Debug_Timer_SoftwareTriggerMode)
+ void Debug_Timer_SetTriggerMode(uint8 triggerMode) ;
+ #endif /* (Debug_Timer_SoftwareTriggerMode) */
+ #if (Debug_Timer_EnableTriggerMode)
+ void Debug_Timer_EnableTrigger(void) ;
+ void Debug_Timer_DisableTrigger(void) ;
+ #endif /* (Debug_Timer_EnableTriggerMode) */
+
+ #if(Debug_Timer_InterruptOnCaptureCount)
+ #if(!Debug_Timer_ControlRegRemoved)
+ void Debug_Timer_SetInterruptCount(uint8 interruptCount) \
+ ;
+ #endif /* (!Debug_Timer_ControlRegRemoved) */
+ #endif /* (Debug_Timer_InterruptOnCaptureCount) */
+
+ #if (Debug_Timer_UsingHWCaptureCounter)
+ void Debug_Timer_SetCaptureCount(uint8 captureCount) \
+ ;
+ uint8 Debug_Timer_ReadCaptureCount(void) ;
+ #endif /* (Debug_Timer_UsingHWCaptureCounter) */
+
+ void Debug_Timer_ClearFIFO(void) ;
+#endif /* UDB Prototypes */
+
+/* Sleep Retention APIs */
+void Debug_Timer_Init(void) ;
+void Debug_Timer_Enable(void) ;
+void Debug_Timer_SaveConfig(void) ;
+void Debug_Timer_RestoreConfig(void) ;
+void Debug_Timer_Sleep(void) ;
+void Debug_Timer_Wakeup(void) ;
+
+
+/***************************************
+* Enumerated Types and Parameters
+***************************************/
+
+/* Enumerated Type B_Timer__CaptureModes, Used in Capture Mode */
+#define Debug_Timer__B_TIMER__CM_NONE 0
+#define Debug_Timer__B_TIMER__CM_RISINGEDGE 1
+#define Debug_Timer__B_TIMER__CM_FALLINGEDGE 2
+#define Debug_Timer__B_TIMER__CM_EITHEREDGE 3
+#define Debug_Timer__B_TIMER__CM_SOFTWARE 4
+
+
+
+/* Enumerated Type B_Timer__TriggerModes, Used in Trigger Mode */
+#define Debug_Timer__B_TIMER__TM_NONE 0x00u
+#define Debug_Timer__B_TIMER__TM_RISINGEDGE 0x04u
+#define Debug_Timer__B_TIMER__TM_FALLINGEDGE 0x08u
+#define Debug_Timer__B_TIMER__TM_EITHEREDGE 0x0Cu
+#define Debug_Timer__B_TIMER__TM_SOFTWARE 0x10u
+
+
+/***************************************
+* Initialial Parameter Constants
+***************************************/
+
+#define Debug_Timer_INIT_PERIOD 31999u
+#define Debug_Timer_INIT_CAPTURE_MODE ((uint8)((uint8)0u << Debug_Timer_CTRL_CAP_MODE_SHIFT))
+#define Debug_Timer_INIT_TRIGGER_MODE ((uint8)((uint8)0u << Debug_Timer_CTRL_TRIG_MODE_SHIFT))
+#if (Debug_Timer_UsingFixedFunction)
+ #define Debug_Timer_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT)) | \
+ ((uint8)((uint8)0 << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT)))
+#else
+ #define Debug_Timer_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT)) | \
+ ((uint8)((uint8)0 << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT)) | \
+ ((uint8)((uint8)0 << Debug_Timer_STATUS_FIFOFULL_INT_MASK_SHIFT)))
+#endif /* (Debug_Timer_UsingFixedFunction) */
+#define Debug_Timer_INIT_CAPTURE_COUNT (2u)
+#define Debug_Timer_INIT_INT_CAPTURE_COUNT ((uint8)((uint8)(1u - 1u) << Debug_Timer_CTRL_INTCNT_SHIFT))
+
+
+/***************************************
+* Registers
+***************************************/
+
+#if (Debug_Timer_UsingFixedFunction) /* Implementation Specific Registers and Register Constants */
+
+
+ /***************************************
+ * Fixed Function Registers
+ ***************************************/
+
+ #define Debug_Timer_STATUS (*(reg8 *) Debug_Timer_TimerHW__SR0 )
+ /* In Fixed Function Block Status and Mask are the same register */
+ #define Debug_Timer_STATUS_MASK (*(reg8 *) Debug_Timer_TimerHW__SR0 )
+ #define Debug_Timer_CONTROL (*(reg8 *) Debug_Timer_TimerHW__CFG0)
+ #define Debug_Timer_CONTROL2 (*(reg8 *) Debug_Timer_TimerHW__CFG1)
+ #define Debug_Timer_CONTROL2_PTR ( (reg8 *) Debug_Timer_TimerHW__CFG1)
+ #define Debug_Timer_RT1 (*(reg8 *) Debug_Timer_TimerHW__RT1)
+ #define Debug_Timer_RT1_PTR ( (reg8 *) Debug_Timer_TimerHW__RT1)
+
+ #if (CY_PSOC3 || CY_PSOC5LP)
+ #define Debug_Timer_CONTROL3 (*(reg8 *) Debug_Timer_TimerHW__CFG2)
+ #define Debug_Timer_CONTROL3_PTR ( (reg8 *) Debug_Timer_TimerHW__CFG2)
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */
+ #define Debug_Timer_GLOBAL_ENABLE (*(reg8 *) Debug_Timer_TimerHW__PM_ACT_CFG)
+ #define Debug_Timer_GLOBAL_STBY_ENABLE (*(reg8 *) Debug_Timer_TimerHW__PM_STBY_CFG)
+
+ #define Debug_Timer_CAPTURE_LSB (* (reg16 *) Debug_Timer_TimerHW__CAP0 )
+ #define Debug_Timer_CAPTURE_LSB_PTR ((reg16 *) Debug_Timer_TimerHW__CAP0 )
+ #define Debug_Timer_PERIOD_LSB (* (reg16 *) Debug_Timer_TimerHW__PER0 )
+ #define Debug_Timer_PERIOD_LSB_PTR ((reg16 *) Debug_Timer_TimerHW__PER0 )
+ #define Debug_Timer_COUNTER_LSB (* (reg16 *) Debug_Timer_TimerHW__CNT_CMP0 )
+ #define Debug_Timer_COUNTER_LSB_PTR ((reg16 *) Debug_Timer_TimerHW__CNT_CMP0 )
+
+
+ /***************************************
+ * Register Constants
+ ***************************************/
+
+ /* Fixed Function Block Chosen */
+ #define Debug_Timer_BLOCK_EN_MASK Debug_Timer_TimerHW__PM_ACT_MSK
+ #define Debug_Timer_BLOCK_STBY_EN_MASK Debug_Timer_TimerHW__PM_STBY_MSK
+
+ /* Control Register Bit Locations */
+ /* Interrupt Count - Not valid for Fixed Function Block */
+ #define Debug_Timer_CTRL_INTCNT_SHIFT 0x00u
+ /* Trigger Polarity - Not valid for Fixed Function Block */
+ #define Debug_Timer_CTRL_TRIG_MODE_SHIFT 0x00u
+ /* Trigger Enable - Not valid for Fixed Function Block */
+ #define Debug_Timer_CTRL_TRIG_EN_SHIFT 0x00u
+ /* Capture Polarity - Not valid for Fixed Function Block */
+ #define Debug_Timer_CTRL_CAP_MODE_SHIFT 0x00u
+ /* Timer Enable - As defined in Register Map, part of TMRX_CFG0 register */
+ #define Debug_Timer_CTRL_ENABLE_SHIFT 0x00u
+
+ /* Control Register Bit Masks */
+ #define Debug_Timer_CTRL_ENABLE ((uint8)((uint8)0x01u << Debug_Timer_CTRL_ENABLE_SHIFT))
+
+ /* Control2 Register Bit Masks */
+ /* As defined in Register Map, Part of the TMRX_CFG1 register */
+ #define Debug_Timer_CTRL2_IRQ_SEL_SHIFT 0x00u
+ #define Debug_Timer_CTRL2_IRQ_SEL ((uint8)((uint8)0x01u << Debug_Timer_CTRL2_IRQ_SEL_SHIFT))
+
+ #if (CY_PSOC5A)
+ /* Use CFG1 Mode bits to set run mode */
+ /* As defined by Verilog Implementation */
+ #define Debug_Timer_CTRL_MODE_SHIFT 0x01u
+ #define Debug_Timer_CTRL_MODE_MASK ((uint8)((uint8)0x07u << Debug_Timer_CTRL_MODE_SHIFT))
+ #endif /* (CY_PSOC5A) */
+ #if (CY_PSOC3 || CY_PSOC5LP)
+ /* Control3 Register Bit Locations */
+ #define Debug_Timer_CTRL_RCOD_SHIFT 0x02u
+ #define Debug_Timer_CTRL_ENBL_SHIFT 0x00u
+ #define Debug_Timer_CTRL_MODE_SHIFT 0x00u
+
+ /* Control3 Register Bit Masks */
+ #define Debug_Timer_CTRL_RCOD_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_RCOD_SHIFT)) /* ROD and COD bit masks */
+ #define Debug_Timer_CTRL_ENBL_MASK ((uint8)((uint8)0x80u << Debug_Timer_CTRL_ENBL_SHIFT)) /* HW_EN bit mask */
+ #define Debug_Timer_CTRL_MODE_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_MODE_SHIFT)) /* Run mode bit mask */
+
+ #define Debug_Timer_CTRL_RCOD ((uint8)((uint8)0x03u << Debug_Timer_CTRL_RCOD_SHIFT))
+ #define Debug_Timer_CTRL_ENBL ((uint8)((uint8)0x80u << Debug_Timer_CTRL_ENBL_SHIFT))
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+ /*RT1 Synch Constants: Applicable for PSoC3 and PSoC5LP */
+ #define Debug_Timer_RT1_SHIFT 0x04u
+ /* Sync TC and CMP bit masks */
+ #define Debug_Timer_RT1_MASK ((uint8)((uint8)0x03u << Debug_Timer_RT1_SHIFT))
+ #define Debug_Timer_SYNC ((uint8)((uint8)0x03u << Debug_Timer_RT1_SHIFT))
+ #define Debug_Timer_SYNCDSI_SHIFT 0x00u
+ /* Sync all DSI inputs with Mask */
+ #define Debug_Timer_SYNCDSI_MASK ((uint8)((uint8)0x0Fu << Debug_Timer_SYNCDSI_SHIFT))
+ /* Sync all DSI inputs */
+ #define Debug_Timer_SYNCDSI_EN ((uint8)((uint8)0x0Fu << Debug_Timer_SYNCDSI_SHIFT))
+
+ #define Debug_Timer_CTRL_MODE_PULSEWIDTH ((uint8)((uint8)0x01u << Debug_Timer_CTRL_MODE_SHIFT))
+ #define Debug_Timer_CTRL_MODE_PERIOD ((uint8)((uint8)0x02u << Debug_Timer_CTRL_MODE_SHIFT))
+ #define Debug_Timer_CTRL_MODE_CONTINUOUS ((uint8)((uint8)0x00u << Debug_Timer_CTRL_MODE_SHIFT))
+
+ /* Status Register Bit Locations */
+ /* As defined in Register Map, part of TMRX_SR0 register */
+ #define Debug_Timer_STATUS_TC_SHIFT 0x07u
+ /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
+ #define Debug_Timer_STATUS_CAPTURE_SHIFT 0x06u
+ /* As defined in Register Map, part of TMRX_SR0 register */
+ #define Debug_Timer_STATUS_TC_INT_MASK_SHIFT (Debug_Timer_STATUS_TC_SHIFT - 0x04u)
+ /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */
+ #define Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT (Debug_Timer_STATUS_CAPTURE_SHIFT - 0x04u)
+
+ /* Status Register Bit Masks */
+ #define Debug_Timer_STATUS_TC ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
+ #define Debug_Timer_STATUS_CAPTURE ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
+ /* Interrupt Enable Bit-Mask for interrupt on TC */
+ #define Debug_Timer_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT))
+ /* Interrupt Enable Bit-Mask for interrupt on Capture */
+ #define Debug_Timer_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT))
+
+#else /* UDB Registers and Register Constants */
+
+
+ /***************************************
+ * UDB Registers
+ ***************************************/
+
+ #define Debug_Timer_STATUS (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__STATUS_REG )
+ #define Debug_Timer_STATUS_MASK (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__MASK_REG)
+ #define Debug_Timer_STATUS_AUX_CTRL (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG)
+ #define Debug_Timer_CONTROL (* (reg8 *) Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG )
+
+ #if(Debug_Timer_Resolution <= 8u) /* 8-bit Timer */
+ #define Debug_Timer_CAPTURE_LSB (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
+ #define Debug_Timer_CAPTURE_LSB_PTR ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
+ #define Debug_Timer_PERIOD_LSB (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
+ #define Debug_Timer_PERIOD_LSB_PTR ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
+ #define Debug_Timer_COUNTER_LSB (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+ #define Debug_Timer_COUNTER_LSB_PTR ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+ #elif(Debug_Timer_Resolution <= 16u) /* 8-bit Timer */
+ #if(CY_PSOC3) /* 8-bit addres space */
+ #define Debug_Timer_CAPTURE_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
+ #define Debug_Timer_CAPTURE_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
+ #define Debug_Timer_PERIOD_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
+ #define Debug_Timer_PERIOD_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
+ #define Debug_Timer_COUNTER_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+ #define Debug_Timer_COUNTER_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+ #else /* 16-bit address space */
+ #define Debug_Timer_CAPTURE_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
+ #define Debug_Timer_CAPTURE_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG )
+ #define Debug_Timer_PERIOD_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
+ #define Debug_Timer_PERIOD_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG )
+ #define Debug_Timer_COUNTER_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
+ #define Debug_Timer_COUNTER_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG )
+ #endif /* CY_PSOC3 */
+ #elif(Debug_Timer_Resolution <= 24u)/* 24-bit Timer */
+ #define Debug_Timer_CAPTURE_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
+ #define Debug_Timer_CAPTURE_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
+ #define Debug_Timer_PERIOD_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
+ #define Debug_Timer_PERIOD_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
+ #define Debug_Timer_COUNTER_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+ #define Debug_Timer_COUNTER_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+ #else /* 32-bit Timer */
+ #if(CY_PSOC3 || CY_PSOC5) /* 8-bit address space */
+ #define Debug_Timer_CAPTURE_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
+ #define Debug_Timer_CAPTURE_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG )
+ #define Debug_Timer_PERIOD_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
+ #define Debug_Timer_PERIOD_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG )
+ #define Debug_Timer_COUNTER_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+ #define Debug_Timer_COUNTER_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+ #else /* 32-bit address space */
+ #define Debug_Timer_CAPTURE_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
+ #define Debug_Timer_CAPTURE_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG )
+ #define Debug_Timer_PERIOD_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
+ #define Debug_Timer_PERIOD_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG )
+ #define Debug_Timer_COUNTER_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
+ #define Debug_Timer_COUNTER_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG )
+ #endif /* CY_PSOC3 || CY_PSOC5 */
+ #endif
+
+ #if (Debug_Timer_UsingHWCaptureCounter)
+ #define Debug_Timer_CAP_COUNT (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
+ #define Debug_Timer_CAP_COUNT_PTR ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
+ #define Debug_Timer_CAPTURE_COUNT_CTRL (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
+ #define Debug_Timer_CAPTURE_COUNT_CTRL_PTR ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG )
+ #endif /* (Debug_Timer_UsingHWCaptureCounter) */
+
+
+ /***************************************
+ * Register Constants
+ ***************************************/
+
+ /* Control Register Bit Locations */
+ #define Debug_Timer_CTRL_INTCNT_SHIFT 0x00u /* As defined by Verilog Implementation */
+ #define Debug_Timer_CTRL_TRIG_MODE_SHIFT 0x02u /* As defined by Verilog Implementation */
+ #define Debug_Timer_CTRL_TRIG_EN_SHIFT 0x04u /* As defined by Verilog Implementation */
+ #define Debug_Timer_CTRL_CAP_MODE_SHIFT 0x05u /* As defined by Verilog Implementation */
+ #define Debug_Timer_CTRL_ENABLE_SHIFT 0x07u /* As defined by Verilog Implementation */
+
+ /* Control Register Bit Masks */
+ #define Debug_Timer_CTRL_INTCNT_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_INTCNT_SHIFT))
+ #define Debug_Timer_CTRL_TRIG_MODE_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_TRIG_MODE_SHIFT))
+ #define Debug_Timer_CTRL_TRIG_EN ((uint8)((uint8)0x01u << Debug_Timer_CTRL_TRIG_EN_SHIFT))
+ #define Debug_Timer_CTRL_CAP_MODE_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_CAP_MODE_SHIFT))
+ #define Debug_Timer_CTRL_ENABLE ((uint8)((uint8)0x01u << Debug_Timer_CTRL_ENABLE_SHIFT))
+
+ /* Bit Counter (7-bit) Control Register Bit Definitions */
+ /* As defined by the Register map for the AUX Control Register */
+ #define Debug_Timer_CNTR_ENABLE 0x20u
+
+ /* Status Register Bit Locations */
+ #define Debug_Timer_STATUS_TC_SHIFT 0x00u /* As defined by Verilog Implementation */
+ #define Debug_Timer_STATUS_CAPTURE_SHIFT 0x01u /* As defined by Verilog Implementation */
+ #define Debug_Timer_STATUS_TC_INT_MASK_SHIFT Debug_Timer_STATUS_TC_SHIFT
+ #define Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT Debug_Timer_STATUS_CAPTURE_SHIFT
+ #define Debug_Timer_STATUS_FIFOFULL_SHIFT 0x02u /* As defined by Verilog Implementation */
+ #define Debug_Timer_STATUS_FIFONEMP_SHIFT 0x03u /* As defined by Verilog Implementation */
+ #define Debug_Timer_STATUS_FIFOFULL_INT_MASK_SHIFT Debug_Timer_STATUS_FIFOFULL_SHIFT
+
+ /* Status Register Bit Masks */
+ /* Sticky TC Event Bit-Mask */
+ #define Debug_Timer_STATUS_TC ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
+ /* Sticky Capture Event Bit-Mask */
+ #define Debug_Timer_STATUS_CAPTURE ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
+ /* Interrupt Enable Bit-Mask */
+ #define Debug_Timer_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT))
+ /* Interrupt Enable Bit-Mask */
+ #define Debug_Timer_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT))
+ /* NOT-Sticky FIFO Full Bit-Mask */
+ #define Debug_Timer_STATUS_FIFOFULL ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFOFULL_SHIFT))
+ /* NOT-Sticky FIFO Not Empty Bit-Mask */
+ #define Debug_Timer_STATUS_FIFONEMP ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFONEMP_SHIFT))
+ /* Interrupt Enable Bit-Mask */
+ #define Debug_Timer_STATUS_FIFOFULL_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFOFULL_SHIFT))
+
+ #define Debug_Timer_STATUS_ACTL_INT_EN 0x10u /* As defined for the ACTL Register */
+
+ /* Datapath Auxillary Control Register definitions */
+ #define Debug_Timer_AUX_CTRL_FIFO0_CLR 0x01u /* As defined by Register map */
+ #define Debug_Timer_AUX_CTRL_FIFO1_CLR 0x02u /* As defined by Register map */
+ #define Debug_Timer_AUX_CTRL_FIFO0_LVL 0x04u /* As defined by Register map */
+ #define Debug_Timer_AUX_CTRL_FIFO1_LVL 0x08u /* As defined by Register map */
+ #define Debug_Timer_STATUS_ACTL_INT_EN_MASK 0x10u /* As defined for the ACTL Register */
+
+#endif /* Implementation Specific Registers and Register Constants */
+
+#endif /* CY_Timer_v2_30_Debug_Timer_H */
+
+
+/* [] END OF FILE */
-/*******************************************************************************\r
-* File Name: SCSI_ATN_ISR.c \r
-* Version 1.70\r
-*\r
-* Description:\r
-* API for controlling the state of an interrupt.\r
-*\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-\r
-#include <cydevice_trm.h>\r
-#include <CyLib.h>\r
-#include <SCSI_ATN_ISR.h>\r
-\r
-#if !defined(SCSI_ATN_ISR__REMOVED) /* Check for removal by optimization */\r
-\r
-/*******************************************************************************\r
-* Place your includes, defines and code here \r
-********************************************************************************/\r
-/* `#START SCSI_ATN_ISR_intc` */\r
-\r
-/* `#END` */\r
-\r
-#ifndef CYINT_IRQ_BASE\r
-#define CYINT_IRQ_BASE 16\r
-#endif /* CYINT_IRQ_BASE */\r
-#ifndef CYINT_VECT_TABLE\r
-#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)\r
-#endif /* CYINT_VECT_TABLE */\r
-\r
-/* Declared in startup, used to set unused interrupts to. */\r
-CY_ISR_PROTO(IntDefaultHandler);\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_ATN_ISR_Start\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Set up the interrupt and enable it.\r
-*\r
-* Parameters: \r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SCSI_ATN_ISR_Start(void)\r
-{\r
- /* For all we know the interrupt is active. */\r
- SCSI_ATN_ISR_Disable();\r
-\r
- /* Set the ISR to point to the SCSI_ATN_ISR Interrupt. */\r
- SCSI_ATN_ISR_SetVector(&SCSI_ATN_ISR_Interrupt);\r
-\r
- /* Set the priority. */\r
- SCSI_ATN_ISR_SetPriority((uint8)SCSI_ATN_ISR_INTC_PRIOR_NUMBER);\r
-\r
- /* Enable it. */\r
- SCSI_ATN_ISR_Enable();\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_ATN_ISR_StartEx\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Set up the interrupt and enable it.\r
-*\r
-* Parameters: \r
-* address: Address of the ISR to set in the interrupt vector table.\r
-*\r
-* Return:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SCSI_ATN_ISR_StartEx(cyisraddress address)\r
-{\r
- /* For all we know the interrupt is active. */\r
- SCSI_ATN_ISR_Disable();\r
-\r
- /* Set the ISR to point to the SCSI_ATN_ISR Interrupt. */\r
- SCSI_ATN_ISR_SetVector(address);\r
-\r
- /* Set the priority. */\r
- SCSI_ATN_ISR_SetPriority((uint8)SCSI_ATN_ISR_INTC_PRIOR_NUMBER);\r
-\r
- /* Enable it. */\r
- SCSI_ATN_ISR_Enable();\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_ATN_ISR_Stop\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Disables and removes the interrupt.\r
-*\r
-* Parameters: \r
-*\r
-* Return:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SCSI_ATN_ISR_Stop(void)\r
-{\r
- /* Disable this interrupt. */\r
- SCSI_ATN_ISR_Disable();\r
-\r
- /* Set the ISR to point to the passive one. */\r
- SCSI_ATN_ISR_SetVector(&IntDefaultHandler);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_ATN_ISR_Interrupt\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* The default Interrupt Service Routine for SCSI_ATN_ISR.\r
-*\r
-* Add custom code between the coments to keep the next version of this file\r
-* from over writting your code.\r
-*\r
-* Parameters: \r
-*\r
-* Return:\r
-* None\r
-*\r
-*******************************************************************************/\r
-CY_ISR(SCSI_ATN_ISR_Interrupt)\r
-{\r
- /* Place your Interrupt code here. */\r
- /* `#START SCSI_ATN_ISR_Interrupt` */\r
-\r
- /* `#END` */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_ATN_ISR_SetVector\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Change the ISR vector for the Interrupt. Note calling SCSI_ATN_ISR_Start\r
-* will override any effect this method would have had. To set the vector \r
-* before the component has been started use SCSI_ATN_ISR_StartEx instead.\r
-*\r
-* Parameters:\r
-* address: Address of the ISR to set in the interrupt vector table.\r
-*\r
-* Return:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SCSI_ATN_ISR_SetVector(cyisraddress address)\r
-{\r
- cyisraddress * ramVectorTable;\r
-\r
- ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;\r
-\r
- ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_ATN_ISR__INTC_NUMBER] = address;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_ATN_ISR_GetVector\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Gets the "address" of the current ISR vector for the Interrupt.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* Address of the ISR in the interrupt vector table.\r
-*\r
-*******************************************************************************/\r
-cyisraddress SCSI_ATN_ISR_GetVector(void)\r
-{\r
- cyisraddress * ramVectorTable;\r
-\r
- ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;\r
-\r
- return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_ATN_ISR__INTC_NUMBER];\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_ATN_ISR_SetPriority\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Sets the Priority of the Interrupt. Note calling SCSI_ATN_ISR_Start\r
-* or SCSI_ATN_ISR_StartEx will override any effect this method \r
-* would have had. This method should only be called after \r
-* SCSI_ATN_ISR_Start or SCSI_ATN_ISR_StartEx has been called. To set \r
-* the initial priority for the component use the cydwr file in the tool.\r
-*\r
-* Parameters:\r
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.\r
-*\r
-* Return:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SCSI_ATN_ISR_SetPriority(uint8 priority)\r
-{\r
- *SCSI_ATN_ISR_INTC_PRIOR = priority << 5;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_ATN_ISR_GetPriority\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Gets the Priority of the Interrupt.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* Priority of the interrupt. 0 - 7, 0 being the highest.\r
-*\r
-*******************************************************************************/\r
-uint8 SCSI_ATN_ISR_GetPriority(void)\r
-{\r
- uint8 priority;\r
-\r
-\r
- priority = *SCSI_ATN_ISR_INTC_PRIOR >> 5;\r
-\r
- return priority;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_ATN_ISR_Enable\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Enables the interrupt.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SCSI_ATN_ISR_Enable(void)\r
-{\r
- /* Enable the general interrupt. */\r
- *SCSI_ATN_ISR_INTC_SET_EN = SCSI_ATN_ISR__INTC_MASK;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_ATN_ISR_GetState\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Gets the state (enabled, disabled) of the Interrupt.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* 1 if enabled, 0 if disabled.\r
-*\r
-*******************************************************************************/\r
-uint8 SCSI_ATN_ISR_GetState(void)\r
-{\r
- /* Get the state of the general interrupt. */\r
- return ((*SCSI_ATN_ISR_INTC_SET_EN & (uint32)SCSI_ATN_ISR__INTC_MASK) != 0u) ? 1u:0u;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_ATN_ISR_Disable\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Disables the Interrupt.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SCSI_ATN_ISR_Disable(void)\r
-{\r
- /* Disable the general interrupt. */\r
- *SCSI_ATN_ISR_INTC_CLR_EN = SCSI_ATN_ISR__INTC_MASK;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_ATN_ISR_SetPending\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Causes the Interrupt to enter the pending state, a software method of\r
-* generating the interrupt.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SCSI_ATN_ISR_SetPending(void)\r
-{\r
- *SCSI_ATN_ISR_INTC_SET_PD = SCSI_ATN_ISR__INTC_MASK;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_ATN_ISR_ClearPending\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Clears a pending interrupt.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SCSI_ATN_ISR_ClearPending(void)\r
-{\r
- *SCSI_ATN_ISR_INTC_CLR_PD = SCSI_ATN_ISR__INTC_MASK;\r
-}\r
-\r
-#endif /* End check for removal by optimization */\r
-\r
-\r
-/* [] END OF FILE */\r
+/*******************************************************************************
+* File Name: Debug_Timer_Interrupt.c
+* Version 1.70
+*
+* Description:
+* API for controlling the state of an interrupt.
+*
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+
+#include <cydevice_trm.h>
+#include <CyLib.h>
+#include <Debug_Timer_Interrupt.h>
+
+#if !defined(Debug_Timer_Interrupt__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Place your includes, defines and code here
+********************************************************************************/
+/* `#START Debug_Timer_Interrupt_intc` */
+
+/* `#END` */
+
+#ifndef CYINT_IRQ_BASE
+#define CYINT_IRQ_BASE 16
+#endif /* CYINT_IRQ_BASE */
+#ifndef CYINT_VECT_TABLE
+#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
+#endif /* CYINT_VECT_TABLE */
+
+/* Declared in startup, used to set unused interrupts to. */
+CY_ISR_PROTO(IntDefaultHandler);
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_Start
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_Start(void)
+{
+ /* For all we know the interrupt is active. */
+ Debug_Timer_Interrupt_Disable();
+
+ /* Set the ISR to point to the Debug_Timer_Interrupt Interrupt. */
+ Debug_Timer_Interrupt_SetVector(&Debug_Timer_Interrupt_Interrupt);
+
+ /* Set the priority. */
+ Debug_Timer_Interrupt_SetPriority((uint8)Debug_Timer_Interrupt_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ Debug_Timer_Interrupt_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_StartEx
+********************************************************************************
+*
+* Summary:
+* Set up the interrupt and enable it.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_StartEx(cyisraddress address)
+{
+ /* For all we know the interrupt is active. */
+ Debug_Timer_Interrupt_Disable();
+
+ /* Set the ISR to point to the Debug_Timer_Interrupt Interrupt. */
+ Debug_Timer_Interrupt_SetVector(address);
+
+ /* Set the priority. */
+ Debug_Timer_Interrupt_SetPriority((uint8)Debug_Timer_Interrupt_INTC_PRIOR_NUMBER);
+
+ /* Enable it. */
+ Debug_Timer_Interrupt_Enable();
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_Stop
+********************************************************************************
+*
+* Summary:
+* Disables and removes the interrupt.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_Stop(void)
+{
+ /* Disable this interrupt. */
+ Debug_Timer_Interrupt_Disable();
+
+ /* Set the ISR to point to the passive one. */
+ Debug_Timer_Interrupt_SetVector(&IntDefaultHandler);
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_Interrupt
+********************************************************************************
+*
+* Summary:
+* The default Interrupt Service Routine for Debug_Timer_Interrupt.
+*
+* Add custom code between the coments to keep the next version of this file
+* from over writting your code.
+*
+* Parameters:
+*
+* Return:
+* None
+*
+*******************************************************************************/
+CY_ISR(Debug_Timer_Interrupt_Interrupt)
+{
+ /* Place your Interrupt code here. */
+ /* `#START Debug_Timer_Interrupt_Interrupt` */
+
+ /* `#END` */
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_SetVector
+********************************************************************************
+*
+* Summary:
+* Change the ISR vector for the Interrupt. Note calling Debug_Timer_Interrupt_Start
+* will override any effect this method would have had. To set the vector
+* before the component has been started use Debug_Timer_Interrupt_StartEx instead.
+*
+* Parameters:
+* address: Address of the ISR to set in the interrupt vector table.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_SetVector(cyisraddress address)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ ramVectorTable[CYINT_IRQ_BASE + (uint32)Debug_Timer_Interrupt__INTC_NUMBER] = address;
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_GetVector
+********************************************************************************
+*
+* Summary:
+* Gets the "address" of the current ISR vector for the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Address of the ISR in the interrupt vector table.
+*
+*******************************************************************************/
+cyisraddress Debug_Timer_Interrupt_GetVector(void)
+{
+ cyisraddress * ramVectorTable;
+
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
+
+ return ramVectorTable[CYINT_IRQ_BASE + (uint32)Debug_Timer_Interrupt__INTC_NUMBER];
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_SetPriority
+********************************************************************************
+*
+* Summary:
+* Sets the Priority of the Interrupt. Note calling Debug_Timer_Interrupt_Start
+* or Debug_Timer_Interrupt_StartEx will override any effect this method
+* would have had. This method should only be called after
+* Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx has been called. To set
+* the initial priority for the component use the cydwr file in the tool.
+*
+* Parameters:
+* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_SetPriority(uint8 priority)
+{
+ *Debug_Timer_Interrupt_INTC_PRIOR = priority << 5;
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_GetPriority
+********************************************************************************
+*
+* Summary:
+* Gets the Priority of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* Priority of the interrupt. 0 - 7, 0 being the highest.
+*
+*******************************************************************************/
+uint8 Debug_Timer_Interrupt_GetPriority(void)
+{
+ uint8 priority;
+
+
+ priority = *Debug_Timer_Interrupt_INTC_PRIOR >> 5;
+
+ return priority;
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_Enable
+********************************************************************************
+*
+* Summary:
+* Enables the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_Enable(void)
+{
+ /* Enable the general interrupt. */
+ *Debug_Timer_Interrupt_INTC_SET_EN = Debug_Timer_Interrupt__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_GetState
+********************************************************************************
+*
+* Summary:
+* Gets the state (enabled, disabled) of the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* 1 if enabled, 0 if disabled.
+*
+*******************************************************************************/
+uint8 Debug_Timer_Interrupt_GetState(void)
+{
+ /* Get the state of the general interrupt. */
+ return ((*Debug_Timer_Interrupt_INTC_SET_EN & (uint32)Debug_Timer_Interrupt__INTC_MASK) != 0u) ? 1u:0u;
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_Disable
+********************************************************************************
+*
+* Summary:
+* Disables the Interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_Disable(void)
+{
+ /* Disable the general interrupt. */
+ *Debug_Timer_Interrupt_INTC_CLR_EN = Debug_Timer_Interrupt__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_SetPending
+********************************************************************************
+*
+* Summary:
+* Causes the Interrupt to enter the pending state, a software method of
+* generating the interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_SetPending(void)
+{
+ *Debug_Timer_Interrupt_INTC_SET_PD = Debug_Timer_Interrupt__INTC_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: Debug_Timer_Interrupt_ClearPending
+********************************************************************************
+*
+* Summary:
+* Clears a pending interrupt.
+*
+* Parameters:
+* None
+*
+* Return:
+* None
+*
+*******************************************************************************/
+void Debug_Timer_Interrupt_ClearPending(void)
+{
+ *Debug_Timer_Interrupt_INTC_CLR_PD = Debug_Timer_Interrupt__INTC_MASK;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: Debug_Timer_Interrupt.h
+* Version 1.70
+*
+* Description:
+* Provides the function definitions for the Interrupt Controller.
+*
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+#if !defined(CY_ISR_Debug_Timer_Interrupt_H)
+#define CY_ISR_Debug_Timer_Interrupt_H
+
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+/* Interrupt Controller API. */
+void Debug_Timer_Interrupt_Start(void);
+void Debug_Timer_Interrupt_StartEx(cyisraddress address);
+void Debug_Timer_Interrupt_Stop(void);
+
+CY_ISR_PROTO(Debug_Timer_Interrupt_Interrupt);
+
+void Debug_Timer_Interrupt_SetVector(cyisraddress address);
+cyisraddress Debug_Timer_Interrupt_GetVector(void);
+
+void Debug_Timer_Interrupt_SetPriority(uint8 priority);
+uint8 Debug_Timer_Interrupt_GetPriority(void);
+
+void Debug_Timer_Interrupt_Enable(void);
+uint8 Debug_Timer_Interrupt_GetState(void);
+void Debug_Timer_Interrupt_Disable(void);
+
+void Debug_Timer_Interrupt_SetPending(void);
+void Debug_Timer_Interrupt_ClearPending(void);
+
+
+/* Interrupt Controller Constants */
+
+/* Address of the INTC.VECT[x] register that contains the Address of the Debug_Timer_Interrupt ISR. */
+#define Debug_Timer_Interrupt_INTC_VECTOR ((reg32 *) Debug_Timer_Interrupt__INTC_VECT)
+
+/* Address of the Debug_Timer_Interrupt ISR priority. */
+#define Debug_Timer_Interrupt_INTC_PRIOR ((reg8 *) Debug_Timer_Interrupt__INTC_PRIOR_REG)
+
+/* Priority of the Debug_Timer_Interrupt interrupt. */
+#define Debug_Timer_Interrupt_INTC_PRIOR_NUMBER Debug_Timer_Interrupt__INTC_PRIOR_NUM
+
+/* Address of the INTC.SET_EN[x] byte to bit enable Debug_Timer_Interrupt interrupt. */
+#define Debug_Timer_Interrupt_INTC_SET_EN ((reg32 *) Debug_Timer_Interrupt__INTC_SET_EN_REG)
+
+/* Address of the INTC.CLR_EN[x] register to bit clear the Debug_Timer_Interrupt interrupt. */
+#define Debug_Timer_Interrupt_INTC_CLR_EN ((reg32 *) Debug_Timer_Interrupt__INTC_CLR_EN_REG)
+
+/* Address of the INTC.SET_PD[x] register to set the Debug_Timer_Interrupt interrupt state to pending. */
+#define Debug_Timer_Interrupt_INTC_SET_PD ((reg32 *) Debug_Timer_Interrupt__INTC_SET_PD_REG)
+
+/* Address of the INTC.CLR_PD[x] register to clear the Debug_Timer_Interrupt interrupt. */
+#define Debug_Timer_Interrupt_INTC_CLR_PD ((reg32 *) Debug_Timer_Interrupt__INTC_CLR_PD_REG)
+
+
+#endif /* CY_ISR_Debug_Timer_Interrupt_H */
+
+
+/* [] END OF FILE */
/*******************************************************************************
-* File Name: SCSI_CMD_TIMER_PM.c
+* File Name: Debug_Timer_PM.c
* Version 2.50
*
* Description:
* the software package with which this file was provided.
********************************************************************************/
-#include "SCSI_CMD_TIMER.h"
-static SCSI_CMD_TIMER_backupStruct SCSI_CMD_TIMER_backup;
+#include "Debug_Timer.h"
+static Debug_Timer_backupStruct Debug_Timer_backup;
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_SaveConfig
+* Function Name: Debug_Timer_SaveConfig
********************************************************************************
*
* Summary:
* void
*
* Global variables:
-* SCSI_CMD_TIMER_backup: Variables of this global structure are modified to
+* Debug_Timer_backup: Variables of this global structure are modified to
* store the values of non retention configuration registers when Sleep() API is
* called.
*
*******************************************************************************/
-void SCSI_CMD_TIMER_SaveConfig(void)
+void Debug_Timer_SaveConfig(void)
{
- #if (!SCSI_CMD_TIMER_UsingFixedFunction)
+ #if (!Debug_Timer_UsingFixedFunction)
/* Backup the UDB non-rentention registers for CY_UDB_V0 */
#if (CY_UDB_V0)
- SCSI_CMD_TIMER_backup.TimerUdb = SCSI_CMD_TIMER_ReadCounter();
- SCSI_CMD_TIMER_backup.TimerPeriod = SCSI_CMD_TIMER_ReadPeriod();
- SCSI_CMD_TIMER_backup.InterruptMaskValue = SCSI_CMD_TIMER_STATUS_MASK;
- #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
- SCSI_CMD_TIMER_backup.TimerCaptureCounter = SCSI_CMD_TIMER_ReadCaptureCount();
+ Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
+ Debug_Timer_backup.TimerPeriod = Debug_Timer_ReadPeriod();
+ Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
+ #if (Debug_Timer_UsingHWCaptureCounter)
+ Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
#endif /* Backup the UDB non-rentention register capture counter for CY_UDB_V0 */
#endif /* Backup the UDB non-rentention registers for CY_UDB_V0 */
#if (CY_UDB_V1)
- SCSI_CMD_TIMER_backup.TimerUdb = SCSI_CMD_TIMER_ReadCounter();
- SCSI_CMD_TIMER_backup.InterruptMaskValue = SCSI_CMD_TIMER_STATUS_MASK;
- #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
- SCSI_CMD_TIMER_backup.TimerCaptureCounter = SCSI_CMD_TIMER_ReadCaptureCount();
+ Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
+ Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
+ #if (Debug_Timer_UsingHWCaptureCounter)
+ Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
#endif /* Back Up capture counter register */
#endif /* Backup non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
- #if(!SCSI_CMD_TIMER_ControlRegRemoved)
- SCSI_CMD_TIMER_backup.TimerControlRegister = SCSI_CMD_TIMER_ReadControlRegister();
+ #if(!Debug_Timer_ControlRegRemoved)
+ Debug_Timer_backup.TimerControlRegister = Debug_Timer_ReadControlRegister();
#endif /* Backup the enable state of the Timer component */
#endif /* Backup non retention registers in UDB implementation. All fixed function registers are retention */
}
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_RestoreConfig
+* Function Name: Debug_Timer_RestoreConfig
********************************************************************************
*
* Summary:
* void
*
* Global variables:
-* SCSI_CMD_TIMER_backup: Variables of this global structure are used to
+* Debug_Timer_backup: Variables of this global structure are used to
* restore the values of non retention registers on wakeup from sleep mode.
*
*******************************************************************************/
-void SCSI_CMD_TIMER_RestoreConfig(void)
+void Debug_Timer_RestoreConfig(void)
{
- #if (!SCSI_CMD_TIMER_UsingFixedFunction)
+ #if (!Debug_Timer_UsingFixedFunction)
/* Restore the UDB non-rentention registers for CY_UDB_V0 */
#if (CY_UDB_V0)
/* Interrupt State Backup for Critical Region*/
- uint8 SCSI_CMD_TIMER_interruptState;
+ uint8 Debug_Timer_interruptState;
- SCSI_CMD_TIMER_WriteCounter(SCSI_CMD_TIMER_backup.TimerUdb);
- SCSI_CMD_TIMER_WritePeriod(SCSI_CMD_TIMER_backup.TimerPeriod);
+ Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
+ Debug_Timer_WritePeriod(Debug_Timer_backup.TimerPeriod);
/* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
/* Enter Critical Region*/
- SCSI_CMD_TIMER_interruptState = CyEnterCriticalSection();
+ Debug_Timer_interruptState = CyEnterCriticalSection();
/* Use the interrupt output of the status register for IRQ output */
- SCSI_CMD_TIMER_STATUS_AUX_CTRL |= SCSI_CMD_TIMER_STATUS_ACTL_INT_EN_MASK;
+ Debug_Timer_STATUS_AUX_CTRL |= Debug_Timer_STATUS_ACTL_INT_EN_MASK;
/* Exit Critical Region*/
- CyExitCriticalSection(SCSI_CMD_TIMER_interruptState);
- SCSI_CMD_TIMER_STATUS_MASK =SCSI_CMD_TIMER_backup.InterruptMaskValue;
- #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
- SCSI_CMD_TIMER_SetCaptureCount(SCSI_CMD_TIMER_backup.TimerCaptureCounter);
+ CyExitCriticalSection(Debug_Timer_interruptState);
+ Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
+ #if (Debug_Timer_UsingHWCaptureCounter)
+ Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
#endif /* Restore the UDB non-rentention register capture counter for CY_UDB_V0 */
#endif /* Restore the UDB non-rentention registers for CY_UDB_V0 */
#if (CY_UDB_V1)
- SCSI_CMD_TIMER_WriteCounter(SCSI_CMD_TIMER_backup.TimerUdb);
- SCSI_CMD_TIMER_STATUS_MASK =SCSI_CMD_TIMER_backup.InterruptMaskValue;
- #if (SCSI_CMD_TIMER_UsingHWCaptureCounter)
- SCSI_CMD_TIMER_SetCaptureCount(SCSI_CMD_TIMER_backup.TimerCaptureCounter);
+ Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
+ Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
+ #if (Debug_Timer_UsingHWCaptureCounter)
+ Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
#endif /* Restore Capture counter register*/
#endif /* Restore up non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
- #if(!SCSI_CMD_TIMER_ControlRegRemoved)
- SCSI_CMD_TIMER_WriteControlRegister(SCSI_CMD_TIMER_backup.TimerControlRegister);
+ #if(!Debug_Timer_ControlRegRemoved)
+ Debug_Timer_WriteControlRegister(Debug_Timer_backup.TimerControlRegister);
#endif /* Restore the enable state of the Timer component */
#endif /* Restore non retention registers in the UDB implementation only */
}
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_Sleep
+* Function Name: Debug_Timer_Sleep
********************************************************************************
*
* Summary:
* void
*
* Global variables:
-* SCSI_CMD_TIMER_backup.TimerEnableState: Is modified depending on the
+* Debug_Timer_backup.TimerEnableState: Is modified depending on the
* enable state of the block before entering sleep mode.
*
*******************************************************************************/
-void SCSI_CMD_TIMER_Sleep(void)
+void Debug_Timer_Sleep(void)
{
- #if(!SCSI_CMD_TIMER_ControlRegRemoved)
+ #if(!Debug_Timer_ControlRegRemoved)
/* Save Counter's enable state */
- if(SCSI_CMD_TIMER_CTRL_ENABLE == (SCSI_CMD_TIMER_CONTROL & SCSI_CMD_TIMER_CTRL_ENABLE))
+ if(Debug_Timer_CTRL_ENABLE == (Debug_Timer_CONTROL & Debug_Timer_CTRL_ENABLE))
{
/* Timer is enabled */
- SCSI_CMD_TIMER_backup.TimerEnableState = 1u;
+ Debug_Timer_backup.TimerEnableState = 1u;
}
else
{
/* Timer is disabled */
- SCSI_CMD_TIMER_backup.TimerEnableState = 0u;
+ Debug_Timer_backup.TimerEnableState = 0u;
}
#endif /* Back up enable state from the Timer control register */
- SCSI_CMD_TIMER_Stop();
- SCSI_CMD_TIMER_SaveConfig();
+ Debug_Timer_Stop();
+ Debug_Timer_SaveConfig();
}
/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_Wakeup
+* Function Name: Debug_Timer_Wakeup
********************************************************************************
*
* Summary:
* void
*
* Global variables:
-* SCSI_CMD_TIMER_backup.enableState: Is used to restore the enable state of
+* Debug_Timer_backup.enableState: Is used to restore the enable state of
* block on wakeup from sleep mode.
*
*******************************************************************************/
-void SCSI_CMD_TIMER_Wakeup(void)
+void Debug_Timer_Wakeup(void)
{
- SCSI_CMD_TIMER_RestoreConfig();
- #if(!SCSI_CMD_TIMER_ControlRegRemoved)
- if(SCSI_CMD_TIMER_backup.TimerEnableState == 1u)
+ Debug_Timer_RestoreConfig();
+ #if(!Debug_Timer_ControlRegRemoved)
+ if(Debug_Timer_backup.TimerEnableState == 1u)
{ /* Enable Timer's operation */
- SCSI_CMD_TIMER_Enable();
+ Debug_Timer_Enable();
} /* Do nothing if Timer was disabled before */
#endif /* Remove this code section if Control register is removed */
}
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SCSI_ATN_ISR.h\r
-* Version 1.70\r
-*\r
-* Description:\r
-* Provides the function definitions for the Interrupt Controller.\r
-*\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-#if !defined(CY_ISR_SCSI_ATN_ISR_H)\r
-#define CY_ISR_SCSI_ATN_ISR_H\r
-\r
-\r
-#include <cytypes.h>\r
-#include <cyfitter.h>\r
-\r
-/* Interrupt Controller API. */\r
-void SCSI_ATN_ISR_Start(void);\r
-void SCSI_ATN_ISR_StartEx(cyisraddress address);\r
-void SCSI_ATN_ISR_Stop(void);\r
-\r
-CY_ISR_PROTO(SCSI_ATN_ISR_Interrupt);\r
-\r
-void SCSI_ATN_ISR_SetVector(cyisraddress address);\r
-cyisraddress SCSI_ATN_ISR_GetVector(void);\r
-\r
-void SCSI_ATN_ISR_SetPriority(uint8 priority);\r
-uint8 SCSI_ATN_ISR_GetPriority(void);\r
-\r
-void SCSI_ATN_ISR_Enable(void);\r
-uint8 SCSI_ATN_ISR_GetState(void);\r
-void SCSI_ATN_ISR_Disable(void);\r
-\r
-void SCSI_ATN_ISR_SetPending(void);\r
-void SCSI_ATN_ISR_ClearPending(void);\r
-\r
-\r
-/* Interrupt Controller Constants */\r
-\r
-/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_ATN_ISR ISR. */\r
-#define SCSI_ATN_ISR_INTC_VECTOR ((reg32 *) SCSI_ATN_ISR__INTC_VECT)\r
-\r
-/* Address of the SCSI_ATN_ISR ISR priority. */\r
-#define SCSI_ATN_ISR_INTC_PRIOR ((reg8 *) SCSI_ATN_ISR__INTC_PRIOR_REG)\r
-\r
-/* Priority of the SCSI_ATN_ISR interrupt. */\r
-#define SCSI_ATN_ISR_INTC_PRIOR_NUMBER SCSI_ATN_ISR__INTC_PRIOR_NUM\r
-\r
-/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_ATN_ISR interrupt. */\r
-#define SCSI_ATN_ISR_INTC_SET_EN ((reg32 *) SCSI_ATN_ISR__INTC_SET_EN_REG)\r
-\r
-/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_ATN_ISR interrupt. */\r
-#define SCSI_ATN_ISR_INTC_CLR_EN ((reg32 *) SCSI_ATN_ISR__INTC_CLR_EN_REG)\r
-\r
-/* Address of the INTC.SET_PD[x] register to set the SCSI_ATN_ISR interrupt state to pending. */\r
-#define SCSI_ATN_ISR_INTC_SET_PD ((reg32 *) SCSI_ATN_ISR__INTC_SET_PD_REG)\r
-\r
-/* Address of the INTC.CLR_PD[x] register to clear the SCSI_ATN_ISR interrupt. */\r
-#define SCSI_ATN_ISR_INTC_CLR_PD ((reg32 *) SCSI_ATN_ISR__INTC_CLR_PD_REG)\r
-\r
-\r
-#endif /* CY_ISR_SCSI_ATN_ISR_H */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************
-* File Name: SCSI_CMD_TIMER_ISR.c
-* Version 1.70
-*
-* Description:
-* API for controlling the state of an interrupt.
-*
-*
-* Note:
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-
-
-#include <cydevice_trm.h>
-#include <CyLib.h>
-#include <SCSI_CMD_TIMER_ISR.h>
-
-#if !defined(SCSI_CMD_TIMER_ISR__REMOVED) /* Check for removal by optimization */
-
-/*******************************************************************************
-* Place your includes, defines and code here
-********************************************************************************/
-/* `#START SCSI_CMD_TIMER_ISR_intc` */
-
-/* `#END` */
-
-#ifndef CYINT_IRQ_BASE
-#define CYINT_IRQ_BASE 16
-#endif /* CYINT_IRQ_BASE */
-#ifndef CYINT_VECT_TABLE
-#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
-#endif /* CYINT_VECT_TABLE */
-
-/* Declared in startup, used to set unused interrupts to. */
-CY_ISR_PROTO(IntDefaultHandler);
-
-
-/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ISR_Start
-********************************************************************************
-*
-* Summary:
-* Set up the interrupt and enable it.
-*
-* Parameters:
-* None
-*
-* Return:
-* None
-*
-*******************************************************************************/
-void SCSI_CMD_TIMER_ISR_Start(void)
-{
- /* For all we know the interrupt is active. */
- SCSI_CMD_TIMER_ISR_Disable();
-
- /* Set the ISR to point to the SCSI_CMD_TIMER_ISR Interrupt. */
- SCSI_CMD_TIMER_ISR_SetVector(&SCSI_CMD_TIMER_ISR_Interrupt);
-
- /* Set the priority. */
- SCSI_CMD_TIMER_ISR_SetPriority((uint8)SCSI_CMD_TIMER_ISR_INTC_PRIOR_NUMBER);
-
- /* Enable it. */
- SCSI_CMD_TIMER_ISR_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ISR_StartEx
-********************************************************************************
-*
-* Summary:
-* Set up the interrupt and enable it.
-*
-* Parameters:
-* address: Address of the ISR to set in the interrupt vector table.
-*
-* Return:
-* None
-*
-*******************************************************************************/
-void SCSI_CMD_TIMER_ISR_StartEx(cyisraddress address)
-{
- /* For all we know the interrupt is active. */
- SCSI_CMD_TIMER_ISR_Disable();
-
- /* Set the ISR to point to the SCSI_CMD_TIMER_ISR Interrupt. */
- SCSI_CMD_TIMER_ISR_SetVector(address);
-
- /* Set the priority. */
- SCSI_CMD_TIMER_ISR_SetPriority((uint8)SCSI_CMD_TIMER_ISR_INTC_PRIOR_NUMBER);
-
- /* Enable it. */
- SCSI_CMD_TIMER_ISR_Enable();
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ISR_Stop
-********************************************************************************
-*
-* Summary:
-* Disables and removes the interrupt.
-*
-* Parameters:
-*
-* Return:
-* None
-*
-*******************************************************************************/
-void SCSI_CMD_TIMER_ISR_Stop(void)
-{
- /* Disable this interrupt. */
- SCSI_CMD_TIMER_ISR_Disable();
-
- /* Set the ISR to point to the passive one. */
- SCSI_CMD_TIMER_ISR_SetVector(&IntDefaultHandler);
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ISR_Interrupt
-********************************************************************************
-*
-* Summary:
-* The default Interrupt Service Routine for SCSI_CMD_TIMER_ISR.
-*
-* Add custom code between the coments to keep the next version of this file
-* from over writting your code.
-*
-* Parameters:
-*
-* Return:
-* None
-*
-*******************************************************************************/
-CY_ISR(SCSI_CMD_TIMER_ISR_Interrupt)
-{
- /* Place your Interrupt code here. */
- /* `#START SCSI_CMD_TIMER_ISR_Interrupt` */
-
- /* `#END` */
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ISR_SetVector
-********************************************************************************
-*
-* Summary:
-* Change the ISR vector for the Interrupt. Note calling SCSI_CMD_TIMER_ISR_Start
-* will override any effect this method would have had. To set the vector
-* before the component has been started use SCSI_CMD_TIMER_ISR_StartEx instead.
-*
-* Parameters:
-* address: Address of the ISR to set in the interrupt vector table.
-*
-* Return:
-* None
-*
-*******************************************************************************/
-void SCSI_CMD_TIMER_ISR_SetVector(cyisraddress address)
-{
- cyisraddress * ramVectorTable;
-
- ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
-
- ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_CMD_TIMER_ISR__INTC_NUMBER] = address;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ISR_GetVector
-********************************************************************************
-*
-* Summary:
-* Gets the "address" of the current ISR vector for the Interrupt.
-*
-* Parameters:
-* None
-*
-* Return:
-* Address of the ISR in the interrupt vector table.
-*
-*******************************************************************************/
-cyisraddress SCSI_CMD_TIMER_ISR_GetVector(void)
-{
- cyisraddress * ramVectorTable;
-
- ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
-
- return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_CMD_TIMER_ISR__INTC_NUMBER];
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ISR_SetPriority
-********************************************************************************
-*
-* Summary:
-* Sets the Priority of the Interrupt. Note calling SCSI_CMD_TIMER_ISR_Start
-* or SCSI_CMD_TIMER_ISR_StartEx will override any effect this method
-* would have had. This method should only be called after
-* SCSI_CMD_TIMER_ISR_Start or SCSI_CMD_TIMER_ISR_StartEx has been called. To set
-* the initial priority for the component use the cydwr file in the tool.
-*
-* Parameters:
-* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
-*
-* Return:
-* None
-*
-*******************************************************************************/
-void SCSI_CMD_TIMER_ISR_SetPriority(uint8 priority)
-{
- *SCSI_CMD_TIMER_ISR_INTC_PRIOR = priority << 5;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ISR_GetPriority
-********************************************************************************
-*
-* Summary:
-* Gets the Priority of the Interrupt.
-*
-* Parameters:
-* None
-*
-* Return:
-* Priority of the interrupt. 0 - 7, 0 being the highest.
-*
-*******************************************************************************/
-uint8 SCSI_CMD_TIMER_ISR_GetPriority(void)
-{
- uint8 priority;
-
-
- priority = *SCSI_CMD_TIMER_ISR_INTC_PRIOR >> 5;
-
- return priority;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ISR_Enable
-********************************************************************************
-*
-* Summary:
-* Enables the interrupt.
-*
-* Parameters:
-* None
-*
-* Return:
-* None
-*
-*******************************************************************************/
-void SCSI_CMD_TIMER_ISR_Enable(void)
-{
- /* Enable the general interrupt. */
- *SCSI_CMD_TIMER_ISR_INTC_SET_EN = SCSI_CMD_TIMER_ISR__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ISR_GetState
-********************************************************************************
-*
-* Summary:
-* Gets the state (enabled, disabled) of the Interrupt.
-*
-* Parameters:
-* None
-*
-* Return:
-* 1 if enabled, 0 if disabled.
-*
-*******************************************************************************/
-uint8 SCSI_CMD_TIMER_ISR_GetState(void)
-{
- /* Get the state of the general interrupt. */
- return ((*SCSI_CMD_TIMER_ISR_INTC_SET_EN & (uint32)SCSI_CMD_TIMER_ISR__INTC_MASK) != 0u) ? 1u:0u;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ISR_Disable
-********************************************************************************
-*
-* Summary:
-* Disables the Interrupt.
-*
-* Parameters:
-* None
-*
-* Return:
-* None
-*
-*******************************************************************************/
-void SCSI_CMD_TIMER_ISR_Disable(void)
-{
- /* Disable the general interrupt. */
- *SCSI_CMD_TIMER_ISR_INTC_CLR_EN = SCSI_CMD_TIMER_ISR__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ISR_SetPending
-********************************************************************************
-*
-* Summary:
-* Causes the Interrupt to enter the pending state, a software method of
-* generating the interrupt.
-*
-* Parameters:
-* None
-*
-* Return:
-* None
-*
-*******************************************************************************/
-void SCSI_CMD_TIMER_ISR_SetPending(void)
-{
- *SCSI_CMD_TIMER_ISR_INTC_SET_PD = SCSI_CMD_TIMER_ISR__INTC_MASK;
-}
-
-
-/*******************************************************************************
-* Function Name: SCSI_CMD_TIMER_ISR_ClearPending
-********************************************************************************
-*
-* Summary:
-* Clears a pending interrupt.
-*
-* Parameters:
-* None
-*
-* Return:
-* None
-*
-*******************************************************************************/
-void SCSI_CMD_TIMER_ISR_ClearPending(void)
-{
- *SCSI_CMD_TIMER_ISR_INTC_CLR_PD = SCSI_CMD_TIMER_ISR__INTC_MASK;
-}
-
-#endif /* End check for removal by optimization */
-
-
-/* [] END OF FILE */
+++ /dev/null
-/*******************************************************************************
-* File Name: SCSI_CMD_TIMER_ISR.h
-* Version 1.70
-*
-* Description:
-* Provides the function definitions for the Interrupt Controller.
-*
-*
-********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
-* You may use this file only in accordance with the license, terms, conditions,
-* disclaimers, and limitations in the end user license agreement accompanying
-* the software package with which this file was provided.
-*******************************************************************************/
-#if !defined(CY_ISR_SCSI_CMD_TIMER_ISR_H)
-#define CY_ISR_SCSI_CMD_TIMER_ISR_H
-
-
-#include <cytypes.h>
-#include <cyfitter.h>
-
-/* Interrupt Controller API. */
-void SCSI_CMD_TIMER_ISR_Start(void);
-void SCSI_CMD_TIMER_ISR_StartEx(cyisraddress address);
-void SCSI_CMD_TIMER_ISR_Stop(void);
-
-CY_ISR_PROTO(SCSI_CMD_TIMER_ISR_Interrupt);
-
-void SCSI_CMD_TIMER_ISR_SetVector(cyisraddress address);
-cyisraddress SCSI_CMD_TIMER_ISR_GetVector(void);
-
-void SCSI_CMD_TIMER_ISR_SetPriority(uint8 priority);
-uint8 SCSI_CMD_TIMER_ISR_GetPriority(void);
-
-void SCSI_CMD_TIMER_ISR_Enable(void);
-uint8 SCSI_CMD_TIMER_ISR_GetState(void);
-void SCSI_CMD_TIMER_ISR_Disable(void);
-
-void SCSI_CMD_TIMER_ISR_SetPending(void);
-void SCSI_CMD_TIMER_ISR_ClearPending(void);
-
-
-/* Interrupt Controller Constants */
-
-/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_CMD_TIMER_ISR ISR. */
-#define SCSI_CMD_TIMER_ISR_INTC_VECTOR ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_VECT)
-
-/* Address of the SCSI_CMD_TIMER_ISR ISR priority. */
-#define SCSI_CMD_TIMER_ISR_INTC_PRIOR ((reg8 *) SCSI_CMD_TIMER_ISR__INTC_PRIOR_REG)
-
-/* Priority of the SCSI_CMD_TIMER_ISR interrupt. */
-#define SCSI_CMD_TIMER_ISR_INTC_PRIOR_NUMBER SCSI_CMD_TIMER_ISR__INTC_PRIOR_NUM
-
-/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_CMD_TIMER_ISR interrupt. */
-#define SCSI_CMD_TIMER_ISR_INTC_SET_EN ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_SET_EN_REG)
-
-/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_CMD_TIMER_ISR interrupt. */
-#define SCSI_CMD_TIMER_ISR_INTC_CLR_EN ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_CLR_EN_REG)
-
-/* Address of the INTC.SET_PD[x] register to set the SCSI_CMD_TIMER_ISR interrupt state to pending. */
-#define SCSI_CMD_TIMER_ISR_INTC_SET_PD ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_SET_PD_REG)
-
-/* Address of the INTC.CLR_PD[x] register to clear the SCSI_CMD_TIMER_ISR interrupt. */
-#define SCSI_CMD_TIMER_ISR_INTC_CLR_PD ((reg32 *) SCSI_CMD_TIMER_ISR__INTC_CLR_PD_REG)
-
-
-#endif /* CY_ISR_SCSI_CMD_TIMER_ISR_H */
-
-
-/* [] END OF FILE */
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SCSI_In_DBx.c \r
-* Version 1.90\r
-*\r
-* Description:\r
-* This file contains API to enable firmware control of a Pins component.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "cytypes.h"\r
-#include "SCSI_In_DBx.h"\r
-\r
-/* APIs are not generated for P15[7:6] on PSoC 5 */\r
-#if !(CY_PSOC5A &&\\r
- SCSI_In_DBx__PORT == 15 && ((SCSI_In_DBx__MASK & 0xC0) != 0))\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_In_DBx_Write\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
-*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
-*\r
-* Return: \r
-* None\r
-* \r
-*******************************************************************************/\r
-void SCSI_In_DBx_Write(uint8 value) \r
-{\r
- uint8 staticBits = (SCSI_In_DBx_DR & (uint8)(~SCSI_In_DBx_MASK));\r
- SCSI_In_DBx_DR = staticBits | ((uint8)(value << SCSI_In_DBx_SHIFT) & SCSI_In_DBx_MASK);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_In_DBx_SetDriveMode\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
-* \r
-* Parameters: \r
-* mode: Change the pins to this drive mode.\r
-*\r
-* Return: \r
-* None\r
-*\r
-*******************************************************************************/\r
-void SCSI_In_DBx_SetDriveMode(uint8 mode) \r
-{\r
- CyPins_SetPinDriveMode(SCSI_In_DBx_0, mode);\r
- CyPins_SetPinDriveMode(SCSI_In_DBx_1, mode);\r
- CyPins_SetPinDriveMode(SCSI_In_DBx_2, mode);\r
- CyPins_SetPinDriveMode(SCSI_In_DBx_3, mode);\r
- CyPins_SetPinDriveMode(SCSI_In_DBx_4, mode);\r
- CyPins_SetPinDriveMode(SCSI_In_DBx_5, mode);\r
- CyPins_SetPinDriveMode(SCSI_In_DBx_6, mode);\r
- CyPins_SetPinDriveMode(SCSI_In_DBx_7, mode);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_In_DBx_Read\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
-*\r
-* Parameters: \r
-* None\r
-*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro SCSI_In_DBx_ReadPS calls this function. \r
-* \r
-*******************************************************************************/\r
-uint8 SCSI_In_DBx_Read(void) \r
-{\r
- return (SCSI_In_DBx_PS & SCSI_In_DBx_MASK) >> SCSI_In_DBx_SHIFT;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_In_DBx_ReadDataReg\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
-*\r
-* Parameters: \r
-* None \r
-*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
-*******************************************************************************/\r
-uint8 SCSI_In_DBx_ReadDataReg(void) \r
-{\r
- return (SCSI_In_DBx_DR & SCSI_In_DBx_MASK) >> SCSI_In_DBx_SHIFT;\r
-}\r
-\r
-\r
-/* If Interrupts Are Enabled for this Pins component */ \r
-#if defined(SCSI_In_DBx_INTSTAT) \r
-\r
- /*******************************************************************************\r
- * Function Name: SCSI_In_DBx_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
- *\r
- * Parameters: \r
- * None \r
- *\r
- * Return: \r
- * Returns the value of the interrupt status register\r
- * \r
- *******************************************************************************/\r
- uint8 SCSI_In_DBx_ClearInterrupt(void) \r
- {\r
- return (SCSI_In_DBx_INTSTAT & SCSI_In_DBx_MASK) >> SCSI_In_DBx_SHIFT;\r
- }\r
-\r
-#endif /* If Interrupts Are Enabled for this Pins component */ \r
-\r
-#endif /* CY_PSOC5A... */\r
-\r
- \r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SCSI_In_DBx.h \r
-* Version 1.90\r
-*\r
-* Description:\r
-* This file containts Control Register function prototypes and register defines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_PINS_SCSI_In_DBx_H) /* Pins SCSI_In_DBx_H */\r
-#define CY_PINS_SCSI_In_DBx_H\r
-\r
-#include "cytypes.h"\r
-#include "cyfitter.h"\r
-#include "cypins.h"\r
-#include "SCSI_In_DBx_aliases.h"\r
-\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
-/* APIs are not generated for P15[7:6] */\r
-#if !(CY_PSOC5A &&\\r
- SCSI_In_DBx__PORT == 15 && ((SCSI_In_DBx__MASK & 0xC0) != 0))\r
-\r
-\r
-/***************************************\r
-* Function Prototypes \r
-***************************************/ \r
-\r
-void SCSI_In_DBx_Write(uint8 value) ;\r
-void SCSI_In_DBx_SetDriveMode(uint8 mode) ;\r
-uint8 SCSI_In_DBx_ReadDataReg(void) ;\r
-uint8 SCSI_In_DBx_Read(void) ;\r
-uint8 SCSI_In_DBx_ClearInterrupt(void) ;\r
-\r
-\r
-/***************************************\r
-* API Constants \r
-***************************************/\r
-\r
-/* Drive Modes */\r
-#define SCSI_In_DBx_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define SCSI_In_DBx_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define SCSI_In_DBx_DM_RES_UP PIN_DM_RES_UP\r
-#define SCSI_In_DBx_DM_RES_DWN PIN_DM_RES_DWN\r
-#define SCSI_In_DBx_DM_OD_LO PIN_DM_OD_LO\r
-#define SCSI_In_DBx_DM_OD_HI PIN_DM_OD_HI\r
-#define SCSI_In_DBx_DM_STRONG PIN_DM_STRONG\r
-#define SCSI_In_DBx_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
-/* Digital Port Constants */\r
-#define SCSI_In_DBx_MASK SCSI_In_DBx__MASK\r
-#define SCSI_In_DBx_SHIFT SCSI_In_DBx__SHIFT\r
-#define SCSI_In_DBx_WIDTH 8u\r
-\r
-\r
-/***************************************\r
-* Registers \r
-***************************************/\r
-\r
-/* Main Port Registers */\r
-/* Pin State */\r
-#define SCSI_In_DBx_PS (* (reg8 *) SCSI_In_DBx__PS)\r
-/* Data Register */\r
-#define SCSI_In_DBx_DR (* (reg8 *) SCSI_In_DBx__DR)\r
-/* Port Number */\r
-#define SCSI_In_DBx_PRT_NUM (* (reg8 *) SCSI_In_DBx__PRT) \r
-/* Connect to Analog Globals */ \r
-#define SCSI_In_DBx_AG (* (reg8 *) SCSI_In_DBx__AG) \r
-/* Analog MUX bux enable */\r
-#define SCSI_In_DBx_AMUX (* (reg8 *) SCSI_In_DBx__AMUX) \r
-/* Bidirectional Enable */ \r
-#define SCSI_In_DBx_BIE (* (reg8 *) SCSI_In_DBx__BIE)\r
-/* Bit-mask for Aliased Register Access */\r
-#define SCSI_In_DBx_BIT_MASK (* (reg8 *) SCSI_In_DBx__BIT_MASK)\r
-/* Bypass Enable */\r
-#define SCSI_In_DBx_BYP (* (reg8 *) SCSI_In_DBx__BYP)\r
-/* Port wide control signals */ \r
-#define SCSI_In_DBx_CTL (* (reg8 *) SCSI_In_DBx__CTL)\r
-/* Drive Modes */\r
-#define SCSI_In_DBx_DM0 (* (reg8 *) SCSI_In_DBx__DM0) \r
-#define SCSI_In_DBx_DM1 (* (reg8 *) SCSI_In_DBx__DM1)\r
-#define SCSI_In_DBx_DM2 (* (reg8 *) SCSI_In_DBx__DM2) \r
-/* Input Buffer Disable Override */\r
-#define SCSI_In_DBx_INP_DIS (* (reg8 *) SCSI_In_DBx__INP_DIS)\r
-/* LCD Common or Segment Drive */\r
-#define SCSI_In_DBx_LCD_COM_SEG (* (reg8 *) SCSI_In_DBx__LCD_COM_SEG)\r
-/* Enable Segment LCD */\r
-#define SCSI_In_DBx_LCD_EN (* (reg8 *) SCSI_In_DBx__LCD_EN)\r
-/* Slew Rate Control */\r
-#define SCSI_In_DBx_SLW (* (reg8 *) SCSI_In_DBx__SLW)\r
-\r
-/* DSI Port Registers */\r
-/* Global DSI Select Register */\r
-#define SCSI_In_DBx_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_In_DBx__PRTDSI__CAPS_SEL) \r
-/* Double Sync Enable */\r
-#define SCSI_In_DBx_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_In_DBx__PRTDSI__DBL_SYNC_IN) \r
-/* Output Enable Select Drive Strength */\r
-#define SCSI_In_DBx_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_In_DBx__PRTDSI__OE_SEL0) \r
-#define SCSI_In_DBx_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_In_DBx__PRTDSI__OE_SEL1) \r
-/* Port Pin Output Select Registers */\r
-#define SCSI_In_DBx_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_In_DBx__PRTDSI__OUT_SEL0) \r
-#define SCSI_In_DBx_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_In_DBx__PRTDSI__OUT_SEL1) \r
-/* Sync Output Enable Registers */\r
-#define SCSI_In_DBx_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_In_DBx__PRTDSI__SYNC_OUT) \r
-\r
-\r
-#if defined(SCSI_In_DBx__INTSTAT) /* Interrupt Registers */\r
-\r
- #define SCSI_In_DBx_INTSTAT (* (reg8 *) SCSI_In_DBx__INTSTAT)\r
- #define SCSI_In_DBx_SNAP (* (reg8 *) SCSI_In_DBx__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
-\r
-#endif /* CY_PSOC5A... */\r
-\r
-#endif /* CY_PINS_SCSI_In_DBx_H */\r
-\r
-\r
-/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Out_Bits.c
+* Version 1.70
+*
+* Description:
+* This file contains API to enable firmware control of a Control Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Out_Bits.h"
+
+#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_Write
+********************************************************************************
+*
+* Summary:
+* Write a byte to the Control Register.
+*
+* Parameters:
+* control: The value to be assigned to the Control Register.
+*
+* Return:
+* None.
+*
+*******************************************************************************/
+void SCSI_Out_Bits_Write(uint8 control)
+{
+ SCSI_Out_Bits_Control = control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Bits_Read
+********************************************************************************
+*
+* Summary:
+* Reads the current value assigned to the Control Register.
+*
+* Parameters:
+* None.
+*
+* Return:
+* Returns the current value in the Control Register.
+*
+*******************************************************************************/
+uint8 SCSI_Out_Bits_Read(void)
+{
+ return SCSI_Out_Bits_Control;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
-/*******************************************************************************\r
-* File Name: USBFS_1_Dp.h \r
-* Version 1.90\r
-*\r
-* Description:\r
-* This file containts Control Register function prototypes and register defines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_PINS_USBFS_1_Dp_ALIASES_H) /* Pins USBFS_1_Dp_ALIASES_H */\r
-#define CY_PINS_USBFS_1_Dp_ALIASES_H\r
-\r
-#include "cytypes.h"\r
-#include "cyfitter.h"\r
-\r
-\r
-\r
-/***************************************\r
-* Constants \r
-***************************************/\r
-#define USBFS_1_Dp_0 USBFS_1_Dp__0__PC\r
-\r
-#endif /* End Pins USBFS_1_Dp_ALIASES_H */\r
-\r
-/* [] END OF FILE */\r
+/*******************************************************************************
+* File Name: SCSI_Out_Bits.h
+* Version 1.70
+*
+* Description:
+* This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CONTROL_REG_SCSI_Out_Bits_H) /* CY_CONTROL_REG_SCSI_Out_Bits_H */
+#define CY_CONTROL_REG_SCSI_Out_Bits_H
+
+#include "cytypes.h"
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+void SCSI_Out_Bits_Write(uint8 control) ;
+uint8 SCSI_Out_Bits_Read(void) ;
+
+
+/***************************************
+* Registers
+***************************************/
+
+/* Control Register */
+#define SCSI_Out_Bits_Control (* (reg8 *) SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG )
+#define SCSI_Out_Bits_Control_PTR ( (reg8 *) SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG )
+
+#endif /* End CY_CONTROL_REG_SCSI_Out_Bits_H */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Out_Ctl.c
+* Version 1.70
+*
+* Description:
+* This file contains API to enable firmware control of a Control Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Out_Ctl.h"
+
+#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_Write
+********************************************************************************
+*
+* Summary:
+* Write a byte to the Control Register.
+*
+* Parameters:
+* control: The value to be assigned to the Control Register.
+*
+* Return:
+* None.
+*
+*******************************************************************************/
+void SCSI_Out_Ctl_Write(uint8 control)
+{
+ SCSI_Out_Ctl_Control = control;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Out_Ctl_Read
+********************************************************************************
+*
+* Summary:
+* Reads the current value assigned to the Control Register.
+*
+* Parameters:
+* None.
+*
+* Return:
+* Returns the current value in the Control Register.
+*
+*******************************************************************************/
+uint8 SCSI_Out_Ctl_Read(void)
+{
+ return SCSI_Out_Ctl_Control;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
-/*******************************************************************************\r
-* File Name: SD_WP.h \r
-* Version 1.90\r
-*\r
-* Description:\r
-* This file containts Control Register function prototypes and register defines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_PINS_SD_WP_ALIASES_H) /* Pins SD_WP_ALIASES_H */\r
-#define CY_PINS_SD_WP_ALIASES_H\r
-\r
-#include "cytypes.h"\r
-#include "cyfitter.h"\r
-\r
-\r
-\r
-/***************************************\r
-* Constants \r
-***************************************/\r
-#define SD_WP_0 SD_WP__0__PC\r
-\r
-#endif /* End Pins SD_WP_ALIASES_H */\r
-\r
-/* [] END OF FILE */\r
+/*******************************************************************************
+* File Name: SCSI_Out_Ctl.h
+* Version 1.70
+*
+* Description:
+* This file containts Control Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CONTROL_REG_SCSI_Out_Ctl_H) /* CY_CONTROL_REG_SCSI_Out_Ctl_H */
+#define CY_CONTROL_REG_SCSI_Out_Ctl_H
+
+#include "cytypes.h"
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+void SCSI_Out_Ctl_Write(uint8 control) ;
+uint8 SCSI_Out_Ctl_Read(void) ;
+
+
+/***************************************
+* Registers
+***************************************/
+
+/* Control Register */
+#define SCSI_Out_Ctl_Control (* (reg8 *) SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG )
+#define SCSI_Out_Ctl_Control_PTR ( (reg8 *) SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG )
+
+#endif /* End CY_CONTROL_REG_SCSI_Out_Ctl_H */
+
+
+/* [] END OF FILE */
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SCSI_Out_DBx.c \r
-* Version 1.90\r
-*\r
-* Description:\r
-* This file contains API to enable firmware control of a Pins component.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "cytypes.h"\r
-#include "SCSI_Out_DBx.h"\r
-\r
-/* APIs are not generated for P15[7:6] on PSoC 5 */\r
-#if !(CY_PSOC5A &&\\r
- SCSI_Out_DBx__PORT == 15 && ((SCSI_Out_DBx__MASK & 0xC0) != 0))\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_Out_DBx_Write\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
-*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
-*\r
-* Return: \r
-* None\r
-* \r
-*******************************************************************************/\r
-void SCSI_Out_DBx_Write(uint8 value) \r
-{\r
- uint8 staticBits = (SCSI_Out_DBx_DR & (uint8)(~SCSI_Out_DBx_MASK));\r
- SCSI_Out_DBx_DR = staticBits | ((uint8)(value << SCSI_Out_DBx_SHIFT) & SCSI_Out_DBx_MASK);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_Out_DBx_SetDriveMode\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
-* \r
-* Parameters: \r
-* mode: Change the pins to this drive mode.\r
-*\r
-* Return: \r
-* None\r
-*\r
-*******************************************************************************/\r
-void SCSI_Out_DBx_SetDriveMode(uint8 mode) \r
-{\r
- CyPins_SetPinDriveMode(SCSI_Out_DBx_0, mode);\r
- CyPins_SetPinDriveMode(SCSI_Out_DBx_1, mode);\r
- CyPins_SetPinDriveMode(SCSI_Out_DBx_2, mode);\r
- CyPins_SetPinDriveMode(SCSI_Out_DBx_3, mode);\r
- CyPins_SetPinDriveMode(SCSI_Out_DBx_4, mode);\r
- CyPins_SetPinDriveMode(SCSI_Out_DBx_5, mode);\r
- CyPins_SetPinDriveMode(SCSI_Out_DBx_6, mode);\r
- CyPins_SetPinDriveMode(SCSI_Out_DBx_7, mode);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_Out_DBx_Read\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
-*\r
-* Parameters: \r
-* None\r
-*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro SCSI_Out_DBx_ReadPS calls this function. \r
-* \r
-*******************************************************************************/\r
-uint8 SCSI_Out_DBx_Read(void) \r
-{\r
- return (SCSI_Out_DBx_PS & SCSI_Out_DBx_MASK) >> SCSI_Out_DBx_SHIFT;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SCSI_Out_DBx_ReadDataReg\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
-*\r
-* Parameters: \r
-* None \r
-*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
-*******************************************************************************/\r
-uint8 SCSI_Out_DBx_ReadDataReg(void) \r
-{\r
- return (SCSI_Out_DBx_DR & SCSI_Out_DBx_MASK) >> SCSI_Out_DBx_SHIFT;\r
-}\r
-\r
-\r
-/* If Interrupts Are Enabled for this Pins component */ \r
-#if defined(SCSI_Out_DBx_INTSTAT) \r
-\r
- /*******************************************************************************\r
- * Function Name: SCSI_Out_DBx_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
- *\r
- * Parameters: \r
- * None \r
- *\r
- * Return: \r
- * Returns the value of the interrupt status register\r
- * \r
- *******************************************************************************/\r
- uint8 SCSI_Out_DBx_ClearInterrupt(void) \r
- {\r
- return (SCSI_Out_DBx_INTSTAT & SCSI_Out_DBx_MASK) >> SCSI_Out_DBx_SHIFT;\r
- }\r
-\r
-#endif /* If Interrupts Are Enabled for this Pins component */ \r
-\r
-#endif /* CY_PSOC5A... */\r
-\r
- \r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SCSI_Out_DBx.h \r
-* Version 1.90\r
-*\r
-* Description:\r
-* This file containts Control Register function prototypes and register defines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_PINS_SCSI_Out_DBx_H) /* Pins SCSI_Out_DBx_H */\r
-#define CY_PINS_SCSI_Out_DBx_H\r
-\r
-#include "cytypes.h"\r
-#include "cyfitter.h"\r
-#include "cypins.h"\r
-#include "SCSI_Out_DBx_aliases.h"\r
-\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
-/* APIs are not generated for P15[7:6] */\r
-#if !(CY_PSOC5A &&\\r
- SCSI_Out_DBx__PORT == 15 && ((SCSI_Out_DBx__MASK & 0xC0) != 0))\r
-\r
-\r
-/***************************************\r
-* Function Prototypes \r
-***************************************/ \r
-\r
-void SCSI_Out_DBx_Write(uint8 value) ;\r
-void SCSI_Out_DBx_SetDriveMode(uint8 mode) ;\r
-uint8 SCSI_Out_DBx_ReadDataReg(void) ;\r
-uint8 SCSI_Out_DBx_Read(void) ;\r
-uint8 SCSI_Out_DBx_ClearInterrupt(void) ;\r
-\r
-\r
-/***************************************\r
-* API Constants \r
-***************************************/\r
-\r
-/* Drive Modes */\r
-#define SCSI_Out_DBx_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define SCSI_Out_DBx_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define SCSI_Out_DBx_DM_RES_UP PIN_DM_RES_UP\r
-#define SCSI_Out_DBx_DM_RES_DWN PIN_DM_RES_DWN\r
-#define SCSI_Out_DBx_DM_OD_LO PIN_DM_OD_LO\r
-#define SCSI_Out_DBx_DM_OD_HI PIN_DM_OD_HI\r
-#define SCSI_Out_DBx_DM_STRONG PIN_DM_STRONG\r
-#define SCSI_Out_DBx_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
-/* Digital Port Constants */\r
-#define SCSI_Out_DBx_MASK SCSI_Out_DBx__MASK\r
-#define SCSI_Out_DBx_SHIFT SCSI_Out_DBx__SHIFT\r
-#define SCSI_Out_DBx_WIDTH 8u\r
-\r
-\r
-/***************************************\r
-* Registers \r
-***************************************/\r
-\r
-/* Main Port Registers */\r
-/* Pin State */\r
-#define SCSI_Out_DBx_PS (* (reg8 *) SCSI_Out_DBx__PS)\r
-/* Data Register */\r
-#define SCSI_Out_DBx_DR (* (reg8 *) SCSI_Out_DBx__DR)\r
-/* Port Number */\r
-#define SCSI_Out_DBx_PRT_NUM (* (reg8 *) SCSI_Out_DBx__PRT) \r
-/* Connect to Analog Globals */ \r
-#define SCSI_Out_DBx_AG (* (reg8 *) SCSI_Out_DBx__AG) \r
-/* Analog MUX bux enable */\r
-#define SCSI_Out_DBx_AMUX (* (reg8 *) SCSI_Out_DBx__AMUX) \r
-/* Bidirectional Enable */ \r
-#define SCSI_Out_DBx_BIE (* (reg8 *) SCSI_Out_DBx__BIE)\r
-/* Bit-mask for Aliased Register Access */\r
-#define SCSI_Out_DBx_BIT_MASK (* (reg8 *) SCSI_Out_DBx__BIT_MASK)\r
-/* Bypass Enable */\r
-#define SCSI_Out_DBx_BYP (* (reg8 *) SCSI_Out_DBx__BYP)\r
-/* Port wide control signals */ \r
-#define SCSI_Out_DBx_CTL (* (reg8 *) SCSI_Out_DBx__CTL)\r
-/* Drive Modes */\r
-#define SCSI_Out_DBx_DM0 (* (reg8 *) SCSI_Out_DBx__DM0) \r
-#define SCSI_Out_DBx_DM1 (* (reg8 *) SCSI_Out_DBx__DM1)\r
-#define SCSI_Out_DBx_DM2 (* (reg8 *) SCSI_Out_DBx__DM2) \r
-/* Input Buffer Disable Override */\r
-#define SCSI_Out_DBx_INP_DIS (* (reg8 *) SCSI_Out_DBx__INP_DIS)\r
-/* LCD Common or Segment Drive */\r
-#define SCSI_Out_DBx_LCD_COM_SEG (* (reg8 *) SCSI_Out_DBx__LCD_COM_SEG)\r
-/* Enable Segment LCD */\r
-#define SCSI_Out_DBx_LCD_EN (* (reg8 *) SCSI_Out_DBx__LCD_EN)\r
-/* Slew Rate Control */\r
-#define SCSI_Out_DBx_SLW (* (reg8 *) SCSI_Out_DBx__SLW)\r
-\r
-/* DSI Port Registers */\r
-/* Global DSI Select Register */\r
-#define SCSI_Out_DBx_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_Out_DBx__PRTDSI__CAPS_SEL) \r
-/* Double Sync Enable */\r
-#define SCSI_Out_DBx_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_Out_DBx__PRTDSI__DBL_SYNC_IN) \r
-/* Output Enable Select Drive Strength */\r
-#define SCSI_Out_DBx_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_Out_DBx__PRTDSI__OE_SEL0) \r
-#define SCSI_Out_DBx_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_Out_DBx__PRTDSI__OE_SEL1) \r
-/* Port Pin Output Select Registers */\r
-#define SCSI_Out_DBx_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_Out_DBx__PRTDSI__OUT_SEL0) \r
-#define SCSI_Out_DBx_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_Out_DBx__PRTDSI__OUT_SEL1) \r
-/* Sync Output Enable Registers */\r
-#define SCSI_Out_DBx_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_Out_DBx__PRTDSI__SYNC_OUT) \r
-\r
-\r
-#if defined(SCSI_Out_DBx__INTSTAT) /* Interrupt Registers */\r
-\r
- #define SCSI_Out_DBx_INTSTAT (* (reg8 *) SCSI_Out_DBx__INTSTAT)\r
- #define SCSI_Out_DBx_SNAP (* (reg8 *) SCSI_Out_DBx__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
-\r
-#endif /* CY_PSOC5A... */\r
-\r
-#endif /* CY_PINS_SCSI_Out_DBx_H */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SD_WP.c \r
-* Version 1.90\r
-*\r
-* Description:\r
-* This file contains API to enable firmware control of a Pins component.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "cytypes.h"\r
-#include "SD_WP.h"\r
-\r
-/* APIs are not generated for P15[7:6] on PSoC 5 */\r
-#if !(CY_PSOC5A &&\\r
- SD_WP__PORT == 15 && ((SD_WP__MASK & 0xC0) != 0))\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_WP_Write\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
-*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
-*\r
-* Return: \r
-* None\r
-* \r
-*******************************************************************************/\r
-void SD_WP_Write(uint8 value) \r
-{\r
- uint8 staticBits = (SD_WP_DR & (uint8)(~SD_WP_MASK));\r
- SD_WP_DR = staticBits | ((uint8)(value << SD_WP_SHIFT) & SD_WP_MASK);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_WP_SetDriveMode\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
-* \r
-* Parameters: \r
-* mode: Change the pins to this drive mode.\r
-*\r
-* Return: \r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_WP_SetDriveMode(uint8 mode) \r
-{\r
- CyPins_SetPinDriveMode(SD_WP_0, mode);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_WP_Read\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
-*\r
-* Parameters: \r
-* None\r
-*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro SD_WP_ReadPS calls this function. \r
-* \r
-*******************************************************************************/\r
-uint8 SD_WP_Read(void) \r
-{\r
- return (SD_WP_PS & SD_WP_MASK) >> SD_WP_SHIFT;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_WP_ReadDataReg\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
-*\r
-* Parameters: \r
-* None \r
-*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
-*******************************************************************************/\r
-uint8 SD_WP_ReadDataReg(void) \r
-{\r
- return (SD_WP_DR & SD_WP_MASK) >> SD_WP_SHIFT;\r
-}\r
-\r
-\r
-/* If Interrupts Are Enabled for this Pins component */ \r
-#if defined(SD_WP_INTSTAT) \r
-\r
- /*******************************************************************************\r
- * Function Name: SD_WP_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
- *\r
- * Parameters: \r
- * None \r
- *\r
- * Return: \r
- * Returns the value of the interrupt status register\r
- * \r
- *******************************************************************************/\r
- uint8 SD_WP_ClearInterrupt(void) \r
- {\r
- return (SD_WP_INTSTAT & SD_WP_MASK) >> SD_WP_SHIFT;\r
- }\r
-\r
-#endif /* If Interrupts Are Enabled for this Pins component */ \r
-\r
-#endif /* CY_PSOC5A... */\r
-\r
- \r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SD_WP.h \r
-* Version 1.90\r
-*\r
-* Description:\r
-* This file containts Control Register function prototypes and register defines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_PINS_SD_WP_H) /* Pins SD_WP_H */\r
-#define CY_PINS_SD_WP_H\r
-\r
-#include "cytypes.h"\r
-#include "cyfitter.h"\r
-#include "cypins.h"\r
-#include "SD_WP_aliases.h"\r
-\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
-/* APIs are not generated for P15[7:6] */\r
-#if !(CY_PSOC5A &&\\r
- SD_WP__PORT == 15 && ((SD_WP__MASK & 0xC0) != 0))\r
-\r
-\r
-/***************************************\r
-* Function Prototypes \r
-***************************************/ \r
-\r
-void SD_WP_Write(uint8 value) ;\r
-void SD_WP_SetDriveMode(uint8 mode) ;\r
-uint8 SD_WP_ReadDataReg(void) ;\r
-uint8 SD_WP_Read(void) ;\r
-uint8 SD_WP_ClearInterrupt(void) ;\r
-\r
-\r
-/***************************************\r
-* API Constants \r
-***************************************/\r
-\r
-/* Drive Modes */\r
-#define SD_WP_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define SD_WP_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define SD_WP_DM_RES_UP PIN_DM_RES_UP\r
-#define SD_WP_DM_RES_DWN PIN_DM_RES_DWN\r
-#define SD_WP_DM_OD_LO PIN_DM_OD_LO\r
-#define SD_WP_DM_OD_HI PIN_DM_OD_HI\r
-#define SD_WP_DM_STRONG PIN_DM_STRONG\r
-#define SD_WP_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
-/* Digital Port Constants */\r
-#define SD_WP_MASK SD_WP__MASK\r
-#define SD_WP_SHIFT SD_WP__SHIFT\r
-#define SD_WP_WIDTH 1u\r
-\r
-\r
-/***************************************\r
-* Registers \r
-***************************************/\r
-\r
-/* Main Port Registers */\r
-/* Pin State */\r
-#define SD_WP_PS (* (reg8 *) SD_WP__PS)\r
-/* Data Register */\r
-#define SD_WP_DR (* (reg8 *) SD_WP__DR)\r
-/* Port Number */\r
-#define SD_WP_PRT_NUM (* (reg8 *) SD_WP__PRT) \r
-/* Connect to Analog Globals */ \r
-#define SD_WP_AG (* (reg8 *) SD_WP__AG) \r
-/* Analog MUX bux enable */\r
-#define SD_WP_AMUX (* (reg8 *) SD_WP__AMUX) \r
-/* Bidirectional Enable */ \r
-#define SD_WP_BIE (* (reg8 *) SD_WP__BIE)\r
-/* Bit-mask for Aliased Register Access */\r
-#define SD_WP_BIT_MASK (* (reg8 *) SD_WP__BIT_MASK)\r
-/* Bypass Enable */\r
-#define SD_WP_BYP (* (reg8 *) SD_WP__BYP)\r
-/* Port wide control signals */ \r
-#define SD_WP_CTL (* (reg8 *) SD_WP__CTL)\r
-/* Drive Modes */\r
-#define SD_WP_DM0 (* (reg8 *) SD_WP__DM0) \r
-#define SD_WP_DM1 (* (reg8 *) SD_WP__DM1)\r
-#define SD_WP_DM2 (* (reg8 *) SD_WP__DM2) \r
-/* Input Buffer Disable Override */\r
-#define SD_WP_INP_DIS (* (reg8 *) SD_WP__INP_DIS)\r
-/* LCD Common or Segment Drive */\r
-#define SD_WP_LCD_COM_SEG (* (reg8 *) SD_WP__LCD_COM_SEG)\r
-/* Enable Segment LCD */\r
-#define SD_WP_LCD_EN (* (reg8 *) SD_WP__LCD_EN)\r
-/* Slew Rate Control */\r
-#define SD_WP_SLW (* (reg8 *) SD_WP__SLW)\r
-\r
-/* DSI Port Registers */\r
-/* Global DSI Select Register */\r
-#define SD_WP_PRTDSI__CAPS_SEL (* (reg8 *) SD_WP__PRTDSI__CAPS_SEL) \r
-/* Double Sync Enable */\r
-#define SD_WP_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_WP__PRTDSI__DBL_SYNC_IN) \r
-/* Output Enable Select Drive Strength */\r
-#define SD_WP_PRTDSI__OE_SEL0 (* (reg8 *) SD_WP__PRTDSI__OE_SEL0) \r
-#define SD_WP_PRTDSI__OE_SEL1 (* (reg8 *) SD_WP__PRTDSI__OE_SEL1) \r
-/* Port Pin Output Select Registers */\r
-#define SD_WP_PRTDSI__OUT_SEL0 (* (reg8 *) SD_WP__PRTDSI__OUT_SEL0) \r
-#define SD_WP_PRTDSI__OUT_SEL1 (* (reg8 *) SD_WP__PRTDSI__OUT_SEL1) \r
-/* Sync Output Enable Registers */\r
-#define SD_WP_PRTDSI__SYNC_OUT (* (reg8 *) SD_WP__PRTDSI__SYNC_OUT) \r
-\r
-\r
-#if defined(SD_WP__INTSTAT) /* Interrupt Registers */\r
-\r
- #define SD_WP_INTSTAT (* (reg8 *) SD_WP__INTSTAT)\r
- #define SD_WP_SNAP (* (reg8 *) SD_WP__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
-\r
-#endif /* CY_PSOC5A... */\r
-\r
-#endif /* CY_PINS_SD_WP_H */\r
-\r
-\r
-/* [] END OF FILE */\r
#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE (65u)\r
#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_OUT_RPTS (1u)\r
#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT (1u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE (65u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_IN_RPTS (1u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE (65u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_OUT_RPTS (1u)\r
+#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_COUNT (1u)\r
#define USBFS_ENABLE_HID_CLASS \r
#define USBFS_HID_RPT_1_SIZE_LSB (0x24u)\r
#define USBFS_HID_RPT_1_SIZE_MSB (0x00u)\r
#define USBFS_EXTERN_VBUS (0u)\r
#define USBFS_EXTERN_VND (0u)\r
#define USBFS_EXTERN_CLS (0u)\r
-#define USBFS_MAX_INTERFACES_NUMBER (1u)\r
+#define USBFS_MAX_INTERFACES_NUMBER (2u)\r
#define USBFS_EP0_ISR_REMOVE (0u)\r
#define USBFS_EP1_ISR_REMOVE (0u)\r
#define USBFS_EP2_ISR_REMOVE (0u)\r
-#define USBFS_EP3_ISR_REMOVE (1u)\r
-#define USBFS_EP4_ISR_REMOVE (1u)\r
+#define USBFS_EP3_ISR_REMOVE (0u)\r
+#define USBFS_EP4_ISR_REMOVE (0u)\r
#define USBFS_EP5_ISR_REMOVE (1u)\r
#define USBFS_EP6_ISR_REMOVE (1u)\r
#define USBFS_EP7_ISR_REMOVE (1u)\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1.c\r
-* Version 2.60\r
-*\r
-* Description:\r
-* API for USBFS Component.\r
-*\r
-* Note:\r
-* Many of the functions use endpoint number. RAM arrays are sized with 9\r
-* elements so they are indexed directly by epNumber. The SIE and ARB\r
-* registers are indexed by variations of epNumber - 1.\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include <CyDmac.h>\r
-#include "USBFS_1.h"\r
-#include "USBFS_1_pvt.h"\r
-#include "USBFS_1_hid.h"\r
-#if(USBFS_1_DMA1_REMOVE == 0u)\r
- #include "USBFS_1_ep1_dma.h"\r
-#endif /* End USBFS_1_DMA1_REMOVE */\r
-#if(USBFS_1_DMA2_REMOVE == 0u)\r
- #include "USBFS_1_ep2_dma.h"\r
-#endif /* End USBFS_1_DMA2_REMOVE */\r
-#if(USBFS_1_DMA3_REMOVE == 0u)\r
- #include "USBFS_1_ep3_dma.h"\r
-#endif /* End USBFS_1_DMA3_REMOVE */\r
-#if(USBFS_1_DMA4_REMOVE == 0u)\r
- #include "USBFS_1_ep4_dma.h"\r
-#endif /* End USBFS_1_DMA4_REMOVE */\r
-#if(USBFS_1_DMA5_REMOVE == 0u)\r
- #include "USBFS_1_ep5_dma.h"\r
-#endif /* End USBFS_1_DMA5_REMOVE */\r
-#if(USBFS_1_DMA6_REMOVE == 0u)\r
- #include "USBFS_1_ep6_dma.h"\r
-#endif /* End USBFS_1_DMA6_REMOVE */\r
-#if(USBFS_1_DMA7_REMOVE == 0u)\r
- #include "USBFS_1_ep7_dma.h"\r
-#endif /* End USBFS_1_DMA7_REMOVE */\r
-#if(USBFS_1_DMA8_REMOVE == 0u)\r
- #include "USBFS_1_ep8_dma.h"\r
-#endif /* End USBFS_1_DMA8_REMOVE */\r
-\r
-\r
-/***************************************\r
-* Global data allocation\r
-***************************************/\r
-\r
-uint8 USBFS_1_initVar = 0u;\r
-#if(USBFS_1_EP_MM != USBFS_1__EP_MANUAL)\r
- uint8 USBFS_1_DmaChan[USBFS_1_MAX_EP];\r
- uint8 USBFS_1_DmaTd[USBFS_1_MAX_EP];\r
-#endif /* End USBFS_1_EP_MM */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_Start\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This function initialize the USB SIE, arbiter and the\r
-* endpoint APIs, including setting the D+ Pullup\r
-*\r
-* Parameters:\r
-* device: Contains the device number of the desired device descriptor.\r
-* The device number can be found in the Device Descriptor Tab of\r
-* "Configure" dialog, under the settings of desired Device Descriptor,\r
-* in the "Device Number" field.\r
-* mode: The operating voltage. This determines whether the voltage regulator\r
-* is enabled for 5V operation or if pass through mode is used for 3.3V\r
-* operation. Symbolic names and their associated values are given in the\r
-* following table.\r
-* USBFS_1_3V_OPERATION - Disable voltage regulator and pass-thru\r
-* Vcc for pull-up\r
-* USBFS_1_5V_OPERATION - Enable voltage regulator and use\r
-* regulator for pull-up\r
-* USBFS_1_DWR_VDDD_OPERATION - Enable or Disable voltage\r
-* regulator depend on Vddd Voltage configuration in DWR.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* The USBFS_1_intiVar variable is used to indicate initial\r
-* configuration of this component. The variable is initialized to zero (0u)\r
-* and set to one (1u) the first time USBFS_1_Start() is called.\r
-* This allows for component Re-Start without unnecessary re-initialization\r
-* in all subsequent calls to the USBFS_1_Start() routine.\r
-* If re-initialization of the component is required the variable should be set\r
-* to zero before call of UART_Start() routine, or the user may call\r
-* USBFS_1_Init() and USBFS_1_InitComponent() as done\r
-* in the USBFS_1_Start() routine.\r
-*\r
-* Side Effects:\r
-* This function will reset all communication states to default.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_Start(uint8 device, uint8 mode) \r
-{\r
- /* If not Initialized then initialize all required hardware and software */\r
- if(USBFS_1_initVar == 0u)\r
- {\r
- USBFS_1_Init();\r
- USBFS_1_initVar = 1u;\r
- }\r
- USBFS_1_InitComponent(device, mode);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_Init\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Initialize component's hardware. Usually called in USBFS_1_Start().\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_Init(void) \r
-{\r
- uint8 enableInterrupts;\r
- #if(USBFS_1_EP_MM != USBFS_1__EP_MANUAL)\r
- uint16 i;\r
- #endif /* End USBFS_1_EP_MM != USBFS_1__EP_MANUAL */\r
-\r
- enableInterrupts = CyEnterCriticalSection();\r
-\r
- /* Enable USB block */\r
- USBFS_1_PM_ACT_CFG_REG |= USBFS_1_PM_ACT_EN_FSUSB;\r
- /* Enable USB block for Standby Power Mode */\r
- USBFS_1_PM_STBY_CFG_REG |= USBFS_1_PM_STBY_EN_FSUSB;\r
-\r
- /* Enable core clock */\r
- USBFS_1_USB_CLK_EN_REG = USBFS_1_USB_CLK_ENABLE;\r
-\r
- USBFS_1_CR1_REG = USBFS_1_CR1_ENABLE_LOCK;\r
-\r
- /* ENABLING USBIO PADS IN USB MODE FROM I/O MODE */\r
- /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */\r
- USBFS_1_USBIO_CR0_REG &= ((uint8)(~USBFS_1_USBIO_CR0_TEN));\r
- CyDelayUs(0u); /*~50ns delay */\r
- /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted)\r
- * high. This will have been set low by the power manger out of reset.\r
- * Also confirm USBIO pull-up disabled\r
- */\r
- USBFS_1_PM_USB_CR0_REG &= ((uint8)(~(USBFS_1_PM_USB_CR0_PD_N |\r
- USBFS_1_PM_USB_CR0_PD_PULLUP_N)));\r
-\r
- /* Select iomode to USB mode*/\r
- USBFS_1_USBIO_CR1_REG &= ((uint8)(~USBFS_1_USBIO_CR1_IOMODE));\r
-\r
- /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/\r
- USBFS_1_PM_USB_CR0_REG |= USBFS_1_PM_USB_CR0_REF_EN;\r
- /* The reference will be available 1 us after the regulator is enabled */\r
- CyDelayUs(1u);\r
- /* OR 40us after power restored */\r
- CyDelayUs(40u);\r
- /* Ensure the single ended disable bits are low (PRT15.INP_DIS[7:6])(input receiver enabled). */\r
- USBFS_1_DM_INP_DIS_REG &= ((uint8)(~USBFS_1_DM_MASK));\r
- USBFS_1_DP_INP_DIS_REG &= ((uint8)(~USBFS_1_DP_MASK));\r
-\r
- /* Enable USBIO */\r
- USBFS_1_PM_USB_CR0_REG |= USBFS_1_PM_USB_CR0_PD_N;\r
- CyDelayUs(2u);\r
- /* Set the USBIO pull-up enable */\r
- USBFS_1_PM_USB_CR0_REG |= USBFS_1_PM_USB_CR0_PD_PULLUP_N;\r
-\r
- /* Write WAx */\r
- CY_SET_REG8(USBFS_1_ARB_RW1_WA_PTR, 0u);\r
- CY_SET_REG8(USBFS_1_ARB_RW1_WA_MSB_PTR, 0u);\r
-\r
- #if(USBFS_1_EP_MM != USBFS_1__EP_MANUAL)\r
- /* Init transfer descriptor. This will be used to detect the DMA state - initialized or not. */\r
- for (i = 0u; i < USBFS_1_MAX_EP; i++)\r
- {\r
- USBFS_1_DmaTd[i] = DMA_INVALID_TD;\r
- }\r
- #endif /* End USBFS_1_EP_MM != USBFS_1__EP_MANUAL */\r
-\r
- CyExitCriticalSection(enableInterrupts);\r
-\r
-\r
- /* Set the bus reset Interrupt. */\r
- (void) CyIntSetVector(USBFS_1_BUS_RESET_VECT_NUM, &USBFS_1_BUS_RESET_ISR);\r
- CyIntSetPriority(USBFS_1_BUS_RESET_VECT_NUM, USBFS_1_BUS_RESET_PRIOR);\r
-\r
- /* Set the SOF Interrupt. */\r
- #if(USBFS_1_SOF_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_1_SOF_VECT_NUM, &USBFS_1_SOF_ISR);\r
- CyIntSetPriority(USBFS_1_SOF_VECT_NUM, USBFS_1_SOF_PRIOR);\r
- #endif /* End USBFS_1_SOF_ISR_REMOVE */\r
-\r
- /* Set the Control Endpoint Interrupt. */\r
- (void) CyIntSetVector(USBFS_1_EP_0_VECT_NUM, &USBFS_1_EP_0_ISR);\r
- CyIntSetPriority(USBFS_1_EP_0_VECT_NUM, USBFS_1_EP_0_PRIOR);\r
-\r
- /* Set the Data Endpoint 1 Interrupt. */\r
- #if(USBFS_1_EP1_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_1_EP_1_VECT_NUM, &USBFS_1_EP_1_ISR);\r
- CyIntSetPriority(USBFS_1_EP_1_VECT_NUM, USBFS_1_EP_1_PRIOR);\r
- #endif /* End USBFS_1_EP1_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 2 Interrupt. */\r
- #if(USBFS_1_EP2_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_1_EP_2_VECT_NUM, &USBFS_1_EP_2_ISR);\r
- CyIntSetPriority(USBFS_1_EP_2_VECT_NUM, USBFS_1_EP_2_PRIOR);\r
- #endif /* End USBFS_1_EP2_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 3 Interrupt. */\r
- #if(USBFS_1_EP3_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_1_EP_3_VECT_NUM, &USBFS_1_EP_3_ISR);\r
- CyIntSetPriority(USBFS_1_EP_3_VECT_NUM, USBFS_1_EP_3_PRIOR);\r
- #endif /* End USBFS_1_EP3_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 4 Interrupt. */\r
- #if(USBFS_1_EP4_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_1_EP_4_VECT_NUM, &USBFS_1_EP_4_ISR);\r
- CyIntSetPriority(USBFS_1_EP_4_VECT_NUM, USBFS_1_EP_4_PRIOR);\r
- #endif /* End USBFS_1_EP4_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 5 Interrupt. */\r
- #if(USBFS_1_EP5_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_1_EP_5_VECT_NUM, &USBFS_1_EP_5_ISR);\r
- CyIntSetPriority(USBFS_1_EP_5_VECT_NUM, USBFS_1_EP_5_PRIOR);\r
- #endif /* End USBFS_1_EP5_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 6 Interrupt. */\r
- #if(USBFS_1_EP6_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_1_EP_6_VECT_NUM, &USBFS_1_EP_6_ISR);\r
- CyIntSetPriority(USBFS_1_EP_6_VECT_NUM, USBFS_1_EP_6_PRIOR);\r
- #endif /* End USBFS_1_EP6_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 7 Interrupt. */\r
- #if(USBFS_1_EP7_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_1_EP_7_VECT_NUM, &USBFS_1_EP_7_ISR);\r
- CyIntSetPriority(USBFS_1_EP_7_VECT_NUM, USBFS_1_EP_7_PRIOR);\r
- #endif /* End USBFS_1_EP7_ISR_REMOVE */\r
-\r
- /* Set the Data Endpoint 8 Interrupt. */\r
- #if(USBFS_1_EP8_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_1_EP_8_VECT_NUM, &USBFS_1_EP_8_ISR);\r
- CyIntSetPriority(USBFS_1_EP_8_VECT_NUM, USBFS_1_EP_8_PRIOR);\r
- #endif /* End USBFS_1_EP8_ISR_REMOVE */\r
-\r
- #if((USBFS_1_EP_MM != USBFS_1__EP_MANUAL) && (USBFS_1_ARB_ISR_REMOVE == 0u))\r
- /* Set the ARB Interrupt. */\r
- (void) CyIntSetVector(USBFS_1_ARB_VECT_NUM, &USBFS_1_ARB_ISR);\r
- CyIntSetPriority(USBFS_1_ARB_VECT_NUM, USBFS_1_ARB_PRIOR);\r
- #endif /* End USBFS_1_EP_MM != USBFS_1__EP_MANUAL */\r
-\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_InitComponent\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Initialize the component, except for the HW which is done one time in\r
-* the Start function. This function pulls up D+.\r
-*\r
-* Parameters:\r
-* device: Contains the device number of the desired device descriptor.\r
-* The device number can be found in the Device Descriptor Tab of\r
-* "Configure" dialog, under the settings of desired Device Descriptor,\r
-* in the "Device Number" field.\r
-* mode: The operating voltage. This determines whether the voltage regulator\r
-* is enabled for 5V operation or if pass through mode is used for 3.3V\r
-* operation. Symbolic names and their associated values are given in the\r
-* following table.\r
-* USBFS_1_3V_OPERATION - Disable voltage regulator and pass-thru\r
-* Vcc for pull-up\r
-* USBFS_1_5V_OPERATION - Enable voltage regulator and use\r
-* regulator for pull-up\r
-* USBFS_1_DWR_VDDD_OPERATION - Enable or Disable voltage\r
-* regulator depend on Vddd Voltage configuration in DWR.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_1_device: Contains the device number of the desired device\r
-* descriptor. The device number can be found in the Device Descriptor Tab\r
-* of "Configure" dialog, under the settings of desired Device Descriptor,\r
-* in the "Device Number" field.\r
-* USBFS_1_transferState: This variable used by the communication\r
-* functions to handle current transfer state. Initialized to\r
-* TRANS_STATE_IDLE in this API.\r
-* USBFS_1_configuration: Contains current configuration number\r
-* which is set by the Host using SET_CONFIGURATION request.\r
-* Initialized to zero in this API.\r
-* USBFS_1_deviceAddress: Contains current device address. This\r
-* variable is initialized to zero in this API. Host starts to communicate\r
-* to device with address 0 and then set it to whatever value using\r
-* SET_ADDRESS request.\r
-* USBFS_1_deviceStatus: initialized to 0.\r
-* This is two bit variable which contain power status in first bit\r
-* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote\r
-* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit.\r
-* USBFS_1_lastPacketSize initialized to 0;\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_InitComponent(uint8 device, uint8 mode) \r
-{\r
- /* Initialize _hidProtocol variable to comply with\r
- * HID 7.2.6 Set_Protocol Request:\r
- * "When initialized, all devices default to report protocol."\r
- */\r
- #if defined(USBFS_1_ENABLE_HID_CLASS)\r
- uint8 i;\r
-\r
- for (i = 0u; i < USBFS_1_MAX_INTERFACES_NUMBER; i++)\r
- {\r
- USBFS_1_hidProtocol[i] = USBFS_1_PROTOCOL_REPORT;\r
- }\r
- #endif /* USBFS_1_ENABLE_HID_CLASS */\r
-\r
- /* Enable Interrupts. */\r
- CyIntEnable(USBFS_1_BUS_RESET_VECT_NUM);\r
- CyIntEnable(USBFS_1_EP_0_VECT_NUM);\r
- #if(USBFS_1_EP1_ISR_REMOVE == 0u)\r
- CyIntEnable(USBFS_1_EP_1_VECT_NUM);\r
- #endif /* End USBFS_1_EP1_ISR_REMOVE */\r
- #if(USBFS_1_EP2_ISR_REMOVE == 0u)\r
- CyIntEnable(USBFS_1_EP_2_VECT_NUM);\r
- #endif /* End USBFS_1_EP2_ISR_REMOVE */\r
- #if(USBFS_1_EP3_ISR_REMOVE == 0u)\r
- CyIntEnable(USBFS_1_EP_3_VECT_NUM);\r
- #endif /* End USBFS_1_EP3_ISR_REMOVE */\r
- #if(USBFS_1_EP4_ISR_REMOVE == 0u)\r
- CyIntEnable(USBFS_1_EP_4_VECT_NUM);\r
- #endif /* End USBFS_1_EP4_ISR_REMOVE */\r
- #if(USBFS_1_EP5_ISR_REMOVE == 0u)\r
- CyIntEnable(USBFS_1_EP_5_VECT_NUM);\r
- #endif /* End USBFS_1_EP5_ISR_REMOVE */\r
- #if(USBFS_1_EP6_ISR_REMOVE == 0u)\r
- CyIntEnable(USBFS_1_EP_6_VECT_NUM);\r
- #endif /* End USBFS_1_EP6_ISR_REMOVE */\r
- #if(USBFS_1_EP7_ISR_REMOVE == 0u)\r
- CyIntEnable(USBFS_1_EP_7_VECT_NUM);\r
- #endif /* End USBFS_1_EP7_ISR_REMOVE */\r
- #if(USBFS_1_EP8_ISR_REMOVE == 0u)\r
- CyIntEnable(USBFS_1_EP_8_VECT_NUM);\r
- #endif /* End USBFS_1_EP8_ISR_REMOVE */\r
- #if((USBFS_1_EP_MM != USBFS_1__EP_MANUAL) && (USBFS_1_ARB_ISR_REMOVE == 0u))\r
- /* usb arb interrupt enable */\r
- USBFS_1_ARB_INT_EN_REG = USBFS_1_ARB_INT_MASK;\r
- CyIntEnable(USBFS_1_ARB_VECT_NUM);\r
- #endif /* End USBFS_1_EP_MM != USBFS_1__EP_MANUAL */\r
-\r
- /* Arbiter configuration for DMA transfers */\r
- #if(USBFS_1_EP_MM != USBFS_1__EP_MANUAL)\r
-\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL)\r
- USBFS_1_ARB_CFG_REG = USBFS_1_ARB_CFG_MANUAL_DMA;\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL */\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO)\r
- /*Set cfg cmplt this rises DMA request when the full configuration is done */\r
- USBFS_1_ARB_CFG_REG = USBFS_1_ARB_CFG_AUTO_DMA | USBFS_1_ARB_CFG_AUTO_MEM;\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO */\r
- #endif /* End USBFS_1_EP_MM != USBFS_1__EP_MANUAL */\r
-\r
- USBFS_1_transferState = USBFS_1_TRANS_STATE_IDLE;\r
-\r
- /* USB Locking: Enabled, VRegulator: depend on mode or DWR Voltage configuration*/\r
- switch(mode)\r
- {\r
- case USBFS_1_3V_OPERATION:\r
- USBFS_1_CR1_REG = USBFS_1_CR1_ENABLE_LOCK;\r
- break;\r
- case USBFS_1_5V_OPERATION:\r
- USBFS_1_CR1_REG = USBFS_1_CR1_ENABLE_LOCK | USBFS_1_CR1_REG_ENABLE;\r
- break;\r
- default: /*USBFS_1_DWR_VDDD_OPERATION */\r
- #if(USBFS_1_VDDD_MV < USBFS_1_3500MV)\r
- USBFS_1_CR1_REG = USBFS_1_CR1_ENABLE_LOCK;\r
- #else\r
- USBFS_1_CR1_REG = USBFS_1_CR1_ENABLE_LOCK | USBFS_1_CR1_REG_ENABLE;\r
- #endif /* End USBFS_1_VDDD_MV < USBFS_1_3500MV */\r
- break;\r
- }\r
-\r
- /* Record the descriptor selection */\r
- USBFS_1_device = device;\r
-\r
- /* Clear all of the component data */\r
- USBFS_1_configuration = 0u;\r
- USBFS_1_interfaceNumber = 0u;\r
- USBFS_1_configurationChanged = 0u;\r
- USBFS_1_deviceAddress = 0u;\r
- USBFS_1_deviceStatus = 0u;\r
-\r
- USBFS_1_lastPacketSize = 0u;\r
-\r
- /* ACK Setup, Stall IN/OUT */\r
- CY_SET_REG8(USBFS_1_EP0_CR_PTR, USBFS_1_MODE_STALL_IN_OUT);\r
-\r
- /* Enable the SIE with an address 0 */\r
- CY_SET_REG8(USBFS_1_CR0_PTR, USBFS_1_CR0_ENABLE);\r
-\r
- /* Workaround for PSOC5LP */\r
- CyDelayCycles(1u);\r
-\r
- /* Finally, Enable d+ pullup and select iomode to USB mode*/\r
- CY_SET_REG8(USBFS_1_USBIO_CR1_PTR, USBFS_1_USBIO_CR1_USBPUEN);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_ReInitComponent\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This function reinitialize the component configuration and is\r
-* intend to be called from the Reset interrupt.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_1_device: Contains the device number of the desired device\r
-* descriptor. The device number can be found in the Device Descriptor Tab\r
-* of "Configure" dialog, under the settings of desired Device Descriptor,\r
-* in the "Device Number" field.\r
-* USBFS_1_transferState: This variable used by the communication\r
-* functions to handle current transfer state. Initialized to\r
-* TRANS_STATE_IDLE in this API.\r
-* USBFS_1_configuration: Contains current configuration number\r
-* which is set by the Host using SET_CONFIGURATION request.\r
-* Initialized to zero in this API.\r
-* USBFS_1_deviceAddress: Contains current device address. This\r
-* variable is initialized to zero in this API. Host starts to communicate\r
-* to device with address 0 and then set it to whatever value using\r
-* SET_ADDRESS request.\r
-* USBFS_1_deviceStatus: initialized to 0.\r
-* This is two bit variable which contain power status in first bit\r
-* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote\r
-* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit.\r
-* USBFS_1_lastPacketSize initialized to 0;\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_ReInitComponent(void) \r
-{\r
- /* Initialize _hidProtocol variable to comply with HID 7.2.6 Set_Protocol\r
- * Request: "When initialized, all devices default to report protocol."\r
- */\r
- #if defined(USBFS_1_ENABLE_HID_CLASS)\r
- uint8 i;\r
-\r
- for (i = 0u; i < USBFS_1_MAX_INTERFACES_NUMBER; i++)\r
- {\r
- USBFS_1_hidProtocol[i] = USBFS_1_PROTOCOL_REPORT;\r
- }\r
- #endif /* USBFS_1_ENABLE_HID_CLASS */\r
-\r
- USBFS_1_transferState = USBFS_1_TRANS_STATE_IDLE;\r
-\r
- /* Clear all of the component data */\r
- USBFS_1_configuration = 0u;\r
- USBFS_1_interfaceNumber = 0u;\r
- USBFS_1_configurationChanged = 0u;\r
- USBFS_1_deviceAddress = 0u;\r
- USBFS_1_deviceStatus = 0u;\r
-\r
- USBFS_1_lastPacketSize = 0u;\r
-\r
-\r
- /* ACK Setup, Stall IN/OUT */\r
- CY_SET_REG8(USBFS_1_EP0_CR_PTR, USBFS_1_MODE_STALL_IN_OUT);\r
-\r
- /* Enable the SIE with an address 0 */\r
- CY_SET_REG8(USBFS_1_CR0_PTR, USBFS_1_CR0_ENABLE);\r
-\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_Stop\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This function shuts down the USB function including to release\r
-* the D+ Pullup and disabling the SIE.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_1_configuration: Contains current configuration number\r
-* which is set by the Host using SET_CONFIGURATION request.\r
-* Initialized to zero in this API.\r
-* USBFS_1_deviceAddress: Contains current device address. This\r
-* variable is initialized to zero in this API. Host starts to communicate\r
-* to device with address 0 and then set it to whatever value using\r
-* SET_ADDRESS request.\r
-* USBFS_1_deviceStatus: initialized to 0.\r
-* This is two bit variable which contain power status in first bit\r
-* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote\r
-* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit.\r
-* USBFS_1_configurationChanged: This variable is set to one after\r
-* SET_CONFIGURATION request and cleared in this function.\r
-* USBFS_1_intiVar variable is set to zero\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_Stop(void) \r
-{\r
-\r
- #if(USBFS_1_EP_MM != USBFS_1__EP_MANUAL)\r
- USBFS_1_Stop_DMA(USBFS_1_MAX_EP); /* Stop all DMAs */\r
- #endif /* End USBFS_1_EP_MM != USBFS_1__EP_MANUAL */\r
-\r
- /* Disable the SIE */\r
- USBFS_1_CR0_REG &= (uint8)(~USBFS_1_CR0_ENABLE);\r
- /* Disable the d+ pullup */\r
- USBFS_1_USBIO_CR1_REG &= (uint8)(~USBFS_1_USBIO_CR1_USBPUEN);\r
- /* Disable USB in ACT PM */\r
- USBFS_1_PM_ACT_CFG_REG &= (uint8)(~USBFS_1_PM_ACT_EN_FSUSB);\r
- /* Disable USB block for Standby Power Mode */\r
- USBFS_1_PM_STBY_CFG_REG &= (uint8)(~USBFS_1_PM_STBY_EN_FSUSB);\r
-\r
- /* Disable the reset and EP interrupts */\r
- CyIntDisable(USBFS_1_BUS_RESET_VECT_NUM);\r
- CyIntDisable(USBFS_1_EP_0_VECT_NUM);\r
- #if(USBFS_1_EP1_ISR_REMOVE == 0u)\r
- CyIntDisable(USBFS_1_EP_1_VECT_NUM);\r
- #endif /* End USBFS_1_EP1_ISR_REMOVE */\r
- #if(USBFS_1_EP2_ISR_REMOVE == 0u)\r
- CyIntDisable(USBFS_1_EP_2_VECT_NUM);\r
- #endif /* End USBFS_1_EP2_ISR_REMOVE */\r
- #if(USBFS_1_EP3_ISR_REMOVE == 0u)\r
- CyIntDisable(USBFS_1_EP_3_VECT_NUM);\r
- #endif /* End USBFS_1_EP3_ISR_REMOVE */\r
- #if(USBFS_1_EP4_ISR_REMOVE == 0u)\r
- CyIntDisable(USBFS_1_EP_4_VECT_NUM);\r
- #endif /* End USBFS_1_EP4_ISR_REMOVE */\r
- #if(USBFS_1_EP5_ISR_REMOVE == 0u)\r
- CyIntDisable(USBFS_1_EP_5_VECT_NUM);\r
- #endif /* End USBFS_1_EP5_ISR_REMOVE */\r
- #if(USBFS_1_EP6_ISR_REMOVE == 0u)\r
- CyIntDisable(USBFS_1_EP_6_VECT_NUM);\r
- #endif /* End USBFS_1_EP6_ISR_REMOVE */\r
- #if(USBFS_1_EP7_ISR_REMOVE == 0u)\r
- CyIntDisable(USBFS_1_EP_7_VECT_NUM);\r
- #endif /* End USBFS_1_EP7_ISR_REMOVE */\r
- #if(USBFS_1_EP8_ISR_REMOVE == 0u)\r
- CyIntDisable(USBFS_1_EP_8_VECT_NUM);\r
- #endif /* End USBFS_1_EP8_ISR_REMOVE */\r
-\r
- /* Clear all of the component data */\r
- USBFS_1_configuration = 0u;\r
- USBFS_1_interfaceNumber = 0u;\r
- USBFS_1_configurationChanged = 0u;\r
- USBFS_1_deviceAddress = 0u;\r
- USBFS_1_deviceStatus = 0u;\r
- USBFS_1_initVar = 0u;\r
-\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_CheckActivity\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Returns the activity status of the bus. Clears the status hardware to\r
-* provide fresh activity status on the next call of this routine.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* 1 - If bus activity was detected since the last call to this function\r
-* 0 - If bus activity not was detected since the last call to this function\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_CheckActivity(void) \r
-{\r
- uint8 r;\r
-\r
- r = CY_GET_REG8(USBFS_1_CR1_PTR);\r
- CY_SET_REG8(USBFS_1_CR1_PTR, (r & ((uint8)(~USBFS_1_CR1_BUS_ACTIVITY))));\r
-\r
- return((r & USBFS_1_CR1_BUS_ACTIVITY) >> USBFS_1_CR1_BUS_ACTIVITY_SHIFT);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_GetConfiguration\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Returns the current configuration setting\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* configuration.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_GetConfiguration(void) \r
-{\r
- return(USBFS_1_configuration);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_IsConfigurationChanged\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Returns the clear on read configuration state. It is usefull when PC send\r
-* double SET_CONFIGURATION request with same configuration number.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* Not zero value when new configuration has been changed, otherwise zero is\r
-* returned.\r
-*\r
-* Global variables:\r
-* USBFS_1_configurationChanged: This variable is set to one after\r
-* SET_CONFIGURATION request and cleared in this function.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_IsConfigurationChanged(void) \r
-{\r
- uint8 res = 0u;\r
-\r
- if(USBFS_1_configurationChanged != 0u)\r
- {\r
- res = USBFS_1_configurationChanged;\r
- USBFS_1_configurationChanged = 0u;\r
- }\r
-\r
- return(res);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_GetInterfaceSetting\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Returns the alternate setting from current interface\r
-*\r
-* Parameters:\r
-* uint8 interfaceNumber, interface number\r
-*\r
-* Return:\r
-* Alternate setting.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_GetInterfaceSetting(uint8 interfaceNumber)\r
- \r
-{\r
- return(USBFS_1_interfaceSetting[interfaceNumber]);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_GetEPState\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Returned the state of the requested endpoint.\r
-*\r
-* Parameters:\r
-* epNumber: Endpoint Number\r
-*\r
-* Return:\r
-* State of the requested endpoint.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_GetEPState(uint8 epNumber) \r
-{\r
- return(USBFS_1_EP[epNumber].apiEpState);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_GetEPCount\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This function supports Data Endpoints only(EP1-EP8).\r
-* Returns the transfer count for the requested endpoint. The value from\r
-* the count registers includes 2 counts for the two byte checksum of the\r
-* packet. This function subtracts the two counts.\r
-*\r
-* Parameters:\r
-* epNumber: Data Endpoint Number.\r
-* Valid values are between 1 and 8.\r
-*\r
-* Return:\r
-* Returns the current byte count from the specified endpoint or 0 for an\r
-* invalid endpoint.\r
-*\r
-*******************************************************************************/\r
-uint16 USBFS_1_GetEPCount(uint8 epNumber) \r
-{\r
- uint8 ri;\r
- uint16 result = 0u;\r
-\r
- if((epNumber > USBFS_1_EP0) && (epNumber < USBFS_1_MAX_EP))\r
- {\r
- ri = ((epNumber - USBFS_1_EP1) << USBFS_1_EPX_CNTX_ADDR_SHIFT);\r
-\r
- result = (uint8)(CY_GET_REG8((reg8 *)(USBFS_1_SIE_EP1_CNT0_IND + ri)) &\r
- USBFS_1_EPX_CNT0_MASK);\r
- result = (result << 8u) | CY_GET_REG8((reg8 *)(USBFS_1_SIE_EP1_CNT1_IND + ri));\r
- result -= USBFS_1_EPX_CNTX_CRC_COUNT;\r
- }\r
- return(result);\r
-}\r
-\r
-\r
-#if(USBFS_1_EP_MM != USBFS_1__EP_MANUAL)\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_InitEP_DMA\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function allocates and initializes a DMA channel to be used by the\r
- * USBFS_1_LoadInEP() or USBFS_1_ReadOutEP() APIs for data\r
- * transfer.\r
- *\r
- * Parameters:\r
- * epNumber: Contains the data endpoint number.\r
- * Valid values are between 1 and 8.\r
- * *pData: Pointer to a data array that is related to the EP transfers.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- void USBFS_1_InitEP_DMA(uint8 epNumber, const uint8 *pData)\r
- \r
- {\r
- uint16 src;\r
- uint16 dst;\r
- #if (CY_PSOC3) /* PSoC 3 */\r
- src = HI16(CYDEV_SRAM_BASE);\r
- dst = HI16(CYDEV_PERIPH_BASE);\r
- pData = pData;\r
- #else /* PSoC 5 */\r
- if((USBFS_1_EP[epNumber].addr & USBFS_1_DIR_IN) != 0u )\r
- { /* for the IN EP source is the SRAM memory buffer */\r
- src = HI16(pData);\r
- dst = HI16(CYDEV_PERIPH_BASE);\r
- }\r
- else\r
- { /* for the OUT EP source is the SIE register */\r
- src = HI16(CYDEV_PERIPH_BASE);\r
- dst = HI16(pData);\r
- }\r
- #endif /* End C51 */\r
- switch(epNumber)\r
- {\r
- case USBFS_1_EP1:\r
- #if(USBFS_1_DMA1_REMOVE == 0u)\r
- USBFS_1_DmaChan[epNumber] = USBFS_1_ep1_DmaInitialize(\r
- USBFS_1_DMA_BYTES_PER_BURST, USBFS_1_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_1_DMA1_REMOVE */\r
- break;\r
- case USBFS_1_EP2:\r
- #if(USBFS_1_DMA2_REMOVE == 0u)\r
- USBFS_1_DmaChan[epNumber] = USBFS_1_ep2_DmaInitialize(\r
- USBFS_1_DMA_BYTES_PER_BURST, USBFS_1_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_1_DMA2_REMOVE */\r
- break;\r
- case USBFS_1_EP3:\r
- #if(USBFS_1_DMA3_REMOVE == 0u)\r
- USBFS_1_DmaChan[epNumber] = USBFS_1_ep3_DmaInitialize(\r
- USBFS_1_DMA_BYTES_PER_BURST, USBFS_1_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_1_DMA3_REMOVE */\r
- break;\r
- case USBFS_1_EP4:\r
- #if(USBFS_1_DMA4_REMOVE == 0u)\r
- USBFS_1_DmaChan[epNumber] = USBFS_1_ep4_DmaInitialize(\r
- USBFS_1_DMA_BYTES_PER_BURST, USBFS_1_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_1_DMA4_REMOVE */\r
- break;\r
- case USBFS_1_EP5:\r
- #if(USBFS_1_DMA5_REMOVE == 0u)\r
- USBFS_1_DmaChan[epNumber] = USBFS_1_ep5_DmaInitialize(\r
- USBFS_1_DMA_BYTES_PER_BURST, USBFS_1_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_1_DMA5_REMOVE */\r
- break;\r
- case USBFS_1_EP6:\r
- #if(USBFS_1_DMA6_REMOVE == 0u)\r
- USBFS_1_DmaChan[epNumber] = USBFS_1_ep6_DmaInitialize(\r
- USBFS_1_DMA_BYTES_PER_BURST, USBFS_1_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_1_DMA6_REMOVE */\r
- break;\r
- case USBFS_1_EP7:\r
- #if(USBFS_1_DMA7_REMOVE == 0u)\r
- USBFS_1_DmaChan[epNumber] = USBFS_1_ep7_DmaInitialize(\r
- USBFS_1_DMA_BYTES_PER_BURST, USBFS_1_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_1_DMA7_REMOVE */\r
- break;\r
- case USBFS_1_EP8:\r
- #if(USBFS_1_DMA8_REMOVE == 0u)\r
- USBFS_1_DmaChan[epNumber] = USBFS_1_ep8_DmaInitialize(\r
- USBFS_1_DMA_BYTES_PER_BURST, USBFS_1_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_1_DMA8_REMOVE */\r
- break;\r
- default:\r
- /* Do not support EP0 DMA transfers */\r
- break;\r
- }\r
- if((epNumber > USBFS_1_EP0) && (epNumber < USBFS_1_MAX_EP))\r
- {\r
- USBFS_1_DmaTd[epNumber] = CyDmaTdAllocate();\r
- }\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_Stop_DMA\r
- ********************************************************************************\r
- *\r
- * Summary: Stops and free DMA\r
- *\r
- * Parameters:\r
- * epNumber: Contains the data endpoint number or\r
- * USBFS_1_MAX_EP to stop all DMAs\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- void USBFS_1_Stop_DMA(uint8 epNumber) \r
- {\r
- uint8 i;\r
- i = (epNumber < USBFS_1_MAX_EP) ? epNumber : USBFS_1_EP1;\r
- do\r
- {\r
- if(USBFS_1_DmaTd[i] != DMA_INVALID_TD)\r
- {\r
- (void) CyDmaChDisable(USBFS_1_DmaChan[i]);\r
- CyDmaTdFree(USBFS_1_DmaTd[i]);\r
- USBFS_1_DmaTd[i] = DMA_INVALID_TD;\r
- }\r
- i++;\r
- }while((i < USBFS_1_MAX_EP) && (epNumber == USBFS_1_MAX_EP));\r
- }\r
-\r
-#endif /* End USBFS_1_EP_MM != USBFS_1__EP_MANUAL */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_LoadInEP\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Loads and enables the specified USB data endpoint for an IN interrupt or bulk\r
-* transfer.\r
-*\r
-* Parameters:\r
-* epNumber: Contains the data endpoint number.\r
-* Valid values are between 1 and 8.\r
-* *pData: A pointer to a data array from which the data for the endpoint space\r
-* is loaded.\r
-* length: The number of bytes to transfer from the array and then send as a\r
-* result of an IN request. Valid values are between 0 and 512.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)\r
- \r
-{\r
- uint8 ri;\r
- reg8 *p;\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_MANUAL)\r
- uint16 i;\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_MANUAL */\r
-\r
- if((epNumber > USBFS_1_EP0) && (epNumber < USBFS_1_MAX_EP))\r
- {\r
- ri = ((epNumber - USBFS_1_EP1) << USBFS_1_EPX_CNTX_ADDR_SHIFT);\r
- p = (reg8 *)(USBFS_1_ARB_RW1_DR_IND + ri);\r
-\r
- #if(USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO)\r
- /* Limits length to available buffer space, auto MM could send packets up to 1024 bytes */\r
- if(length > (USBFS_1_EPX_DATA_BUF_MAX - USBFS_1_EP[epNumber].buffOffset))\r
- {\r
- length = USBFS_1_EPX_DATA_BUF_MAX - USBFS_1_EP[epNumber].buffOffset;\r
- }\r
- #endif /* End USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO */\r
-\r
- /* Set the count and data toggle */\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CNT0_IND + ri),\r
- (length >> 8u) | (USBFS_1_EP[epNumber].epToggle));\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CNT1_IND + ri), length & 0xFFu);\r
-\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_MANUAL)\r
- if(pData != NULL)\r
- {\r
- /* Copy the data using the arbiter data register */\r
- for (i = 0u; i < length; i++)\r
- {\r
- CY_SET_REG8(p, pData[i]);\r
- }\r
- }\r
- USBFS_1_EP[epNumber].apiEpState = USBFS_1_NO_EVENT_PENDING;\r
- /* Write the Mode register */\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_EP[epNumber].epMode);\r
- #else\r
- /* Init DMA if it was not initialized */\r
- if(USBFS_1_DmaTd[epNumber] == DMA_INVALID_TD)\r
- {\r
- USBFS_1_InitEP_DMA(epNumber, pData);\r
- }\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_MANUAL */\r
-\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL)\r
- USBFS_1_EP[epNumber].apiEpState = USBFS_1_NO_EVENT_PENDING;\r
- if((pData != NULL) && (length > 0u))\r
- {\r
- /* Enable DMA in mode2 for transferring data */\r
- (void) CyDmaChDisable(USBFS_1_DmaChan[epNumber]);\r
- (void) CyDmaTdSetConfiguration(USBFS_1_DmaTd[epNumber], length, CY_DMA_DISABLE_TD,\r
- TD_TERMIN_EN | TD_INC_SRC_ADR);\r
- (void) CyDmaTdSetAddress(USBFS_1_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));\r
- /* Enable the DMA */\r
- (void) CyDmaChSetInitialTd(USBFS_1_DmaChan[epNumber], USBFS_1_DmaTd[epNumber]);\r
- (void) CyDmaChEnable(USBFS_1_DmaChan[epNumber], 1u);\r
- /* Generate DMA request */\r
- * (reg8 *)(USBFS_1_ARB_EP1_CFG_IND + ri) |= USBFS_1_ARB_EPX_CFG_DMA_REQ;\r
- * (reg8 *)(USBFS_1_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_1_ARB_EPX_CFG_DMA_REQ));\r
- /* Mode register will be written in arb ISR after DMA transfer complete */\r
- }\r
- else\r
- {\r
- /* When zero-length packet - write the Mode register directly */\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_EP[epNumber].epMode);\r
- }\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL */\r
-\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO)\r
- if(pData != NULL)\r
- {\r
- /* Enable DMA in mode3 for transferring data */\r
- (void) CyDmaChDisable(USBFS_1_DmaChan[epNumber]);\r
- (void) CyDmaTdSetConfiguration(USBFS_1_DmaTd[epNumber], length,\r
- USBFS_1_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);\r
- (void) CyDmaTdSetAddress(USBFS_1_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));\r
- /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */\r
- (void) CyDmaClearPendingDrq(USBFS_1_DmaChan[epNumber]);\r
- /* Enable the DMA */\r
- (void) CyDmaChSetInitialTd(USBFS_1_DmaChan[epNumber], USBFS_1_DmaTd[epNumber]);\r
- (void) CyDmaChEnable(USBFS_1_DmaChan[epNumber], 1u);\r
- }\r
- else\r
- {\r
- USBFS_1_EP[epNumber].apiEpState = USBFS_1_NO_EVENT_PENDING;\r
- if(length > 0u)\r
- {\r
- /* Set Data ready status, This will generate DMA request */\r
- * (reg8 *)(USBFS_1_ARB_EP1_CFG_IND + ri) |= USBFS_1_ARB_EPX_CFG_IN_DATA_RDY;\r
- /* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */\r
- }\r
- else\r
- {\r
- /* When zero-length packet - write the Mode register directly */\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_EP[epNumber].epMode);\r
- }\r
- }\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO */\r
-\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_ReadOutEP\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Read data from an endpoint. The application must call\r
-* USBFS_1_GetEPState to see if an event is pending.\r
-*\r
-* Parameters:\r
-* epNumber: Contains the data endpoint number.\r
-* Valid values are between 1 and 8.\r
-* pData: A pointer to a data array from which the data for the endpoint space\r
-* is loaded.\r
-* length: The number of bytes to transfer from the USB Out endpoint and loads\r
-* it into data array. Valid values are between 0 and 1023. The function\r
-* moves fewer than the requested number of bytes if the host sends\r
-* fewer bytes than requested.\r
-*\r
-* Returns:\r
-* Number of bytes received, 0 for an invalid endpoint.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint16 USBFS_1_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)\r
- \r
-{\r
- uint8 ri;\r
- reg8 *p;\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_MANUAL)\r
- uint16 i;\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_MANUAL */\r
- #if(USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO)\r
- uint16 xferCount;\r
- #endif /* End USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO */\r
-\r
- if((epNumber > USBFS_1_EP0) && (epNumber < USBFS_1_MAX_EP) && (pData != NULL))\r
- {\r
- ri = ((epNumber - USBFS_1_EP1) << USBFS_1_EPX_CNTX_ADDR_SHIFT);\r
- p = (reg8 *)(USBFS_1_ARB_RW1_DR_IND + ri);\r
-\r
- #if(USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO)\r
- /* Determine which is smaller the requested data or the available data */\r
- xferCount = USBFS_1_GetEPCount(epNumber);\r
- if (length > xferCount)\r
- {\r
- length = xferCount;\r
- }\r
- #endif /* End USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO */\r
-\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_MANUAL)\r
- /* Copy the data using the arbiter data register */\r
- for (i = 0u; i < length; i++)\r
- {\r
- pData[i] = CY_GET_REG8(p);\r
- }\r
-\r
- /* (re)arming of OUT endpoint */\r
- USBFS_1_EnableOutEP(epNumber);\r
- #else\r
- /*Init DMA if it was not initialized */\r
- if(USBFS_1_DmaTd[epNumber] == DMA_INVALID_TD)\r
- {\r
- USBFS_1_InitEP_DMA(epNumber, pData);\r
- }\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_MANUAL */\r
-\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL)\r
- /* Enable DMA in mode2 for transferring data */\r
- (void) CyDmaChDisable(USBFS_1_DmaChan[epNumber]);\r
- (void) CyDmaTdSetConfiguration(USBFS_1_DmaTd[epNumber], length, CY_DMA_DISABLE_TD,\r
- TD_TERMIN_EN | TD_INC_DST_ADR);\r
- (void) CyDmaTdSetAddress(USBFS_1_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData));\r
- /* Enable the DMA */\r
- (void) CyDmaChSetInitialTd(USBFS_1_DmaChan[epNumber], USBFS_1_DmaTd[epNumber]);\r
- (void) CyDmaChEnable(USBFS_1_DmaChan[epNumber], 1u);\r
-\r
- /* Generate DMA request */\r
- * (reg8 *)(USBFS_1_ARB_EP1_CFG_IND + ri) |= USBFS_1_ARB_EPX_CFG_DMA_REQ;\r
- * (reg8 *)(USBFS_1_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_1_ARB_EPX_CFG_DMA_REQ));\r
- /* Out EP will be (re)armed in arb ISR after transfer complete */\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL */\r
-\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO)\r
- /* Enable DMA in mode3 for transferring data */\r
- (void) CyDmaChDisable(USBFS_1_DmaChan[epNumber]);\r
- (void) CyDmaTdSetConfiguration(USBFS_1_DmaTd[epNumber], length, USBFS_1_DmaTd[epNumber],\r
- TD_TERMIN_EN | TD_INC_DST_ADR);\r
- (void) CyDmaTdSetAddress(USBFS_1_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData));\r
-\r
- /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */\r
- (void) CyDmaClearPendingDrq(USBFS_1_DmaChan[epNumber]);\r
- /* Enable the DMA */\r
- (void) CyDmaChSetInitialTd(USBFS_1_DmaChan[epNumber], USBFS_1_DmaTd[epNumber]);\r
- (void) CyDmaChEnable(USBFS_1_DmaChan[epNumber], 1u);\r
- /* Out EP will be (re)armed in arb ISR after transfer complete */\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO */\r
-\r
- }\r
- else\r
- {\r
- length = 0u;\r
- }\r
-\r
- return(length);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_EnableOutEP\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This function enables an OUT endpoint. It should not be\r
-* called for an IN endpoint.\r
-*\r
-* Parameters:\r
-* epNumber: Endpoint Number\r
-* Valid values are between 1 and 8.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_1_EP[epNumber].apiEpState - set to NO_EVENT_PENDING\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_EnableOutEP(uint8 epNumber) \r
-{\r
- uint8 ri;\r
-\r
- if((epNumber > USBFS_1_EP0) && (epNumber < USBFS_1_MAX_EP))\r
- {\r
- ri = ((epNumber - USBFS_1_EP1) << USBFS_1_EPX_CNTX_ADDR_SHIFT);\r
- USBFS_1_EP[epNumber].apiEpState = USBFS_1_NO_EVENT_PENDING;\r
- /* Write the Mode register */\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_EP[epNumber].epMode);\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_DisableOutEP\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This function disables an OUT endpoint. It should not be\r
-* called for an IN endpoint.\r
-*\r
-* Parameters:\r
-* epNumber: Endpoint Number\r
-* Valid values are between 1 and 8.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_DisableOutEP(uint8 epNumber) \r
-{\r
- uint8 ri ;\r
-\r
- if((epNumber > USBFS_1_EP0) && (epNumber < USBFS_1_MAX_EP))\r
- {\r
- ri = ((epNumber - USBFS_1_EP1) << USBFS_1_EPX_CNTX_ADDR_SHIFT);\r
- /* Write the Mode register */\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_MODE_NAK_OUT);\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_Force\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Forces the bus state\r
-*\r
-* Parameters:\r
-* bState\r
-* USBFS_1_FORCE_J\r
-* USBFS_1_FORCE_K\r
-* USBFS_1_FORCE_SE0\r
-* USBFS_1_FORCE_NONE\r
-*\r
-* Return:\r
-* None.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_Force(uint8 bState) \r
-{\r
- CY_SET_REG8(USBFS_1_USBIO_CR0_PTR, bState);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_GetEPAckState\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Returns the ACK of the CR0 Register (ACKD)\r
-*\r
-* Parameters:\r
-* epNumber: Endpoint Number\r
-* Valid values are between 1 and 8.\r
-*\r
-* Returns\r
-* 0 if nothing has been ACKD, non-=zero something has been ACKD\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_GetEPAckState(uint8 epNumber) \r
-{\r
- uint8 ri;\r
- uint8 cr = 0u;\r
-\r
- if((epNumber > USBFS_1_EP0) && (epNumber < USBFS_1_MAX_EP))\r
- {\r
- ri = ((epNumber - USBFS_1_EP1) << USBFS_1_EPX_CNTX_ADDR_SHIFT);\r
- cr = CY_GET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri)) & USBFS_1_MODE_ACKD;\r
- }\r
-\r
- return(cr);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_SetPowerStatus\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Sets the device power status for reporting in the Get Device Status\r
-* request\r
-*\r
-* Parameters:\r
-* powerStatus: USBFS_1_DEVICE_STATUS_BUS_POWERED(0) - Bus Powered,\r
-* USBFS_1_DEVICE_STATUS_SELF_POWERED(1) - Self Powered\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_1_deviceStatus - set power status\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_SetPowerStatus(uint8 powerStatus) \r
-{\r
- if (powerStatus != USBFS_1_DEVICE_STATUS_BUS_POWERED)\r
- {\r
- USBFS_1_deviceStatus |= USBFS_1_DEVICE_STATUS_SELF_POWERED;\r
- }\r
- else\r
- {\r
- USBFS_1_deviceStatus &= ((uint8)(~USBFS_1_DEVICE_STATUS_SELF_POWERED));\r
- }\r
-}\r
-\r
-\r
-#if (USBFS_1_MON_VBUS == 1u)\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_VBusPresent\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Determines VBUS presence for Self Powered Devices.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * 1 if VBUS is present, otherwise 0.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_1_VBusPresent(void) \r
- {\r
- return((0u != (CY_GET_REG8(USBFS_1_VBUS_PS_PTR) & USBFS_1_VBUS_MASK)) ? 1u : 0u);\r
- }\r
-\r
-#endif /* USBFS_1_MON_VBUS */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_RWUEnabled\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Returns TRUE if Remote Wake Up is enabled, otherwise FALSE\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* TRUE - Remote Wake Up Enabled\r
-* FALSE - Remote Wake Up Disabled\r
-*\r
-* Global variables:\r
-* USBFS_1_deviceStatus - checked to determine remote status\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_RWUEnabled(void) \r
-{\r
- uint8 result = USBFS_1_FALSE;\r
- if((USBFS_1_deviceStatus & USBFS_1_DEVICE_STATUS_REMOTE_WAKEUP) != 0u)\r
- {\r
- result = USBFS_1_TRUE;\r
- }\r
-\r
- return(result);\r
-}\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1.h\r
-* Version 2.60\r
-*\r
-* Description:\r
-* Header File for the USFS component. Contains prototypes and constant values.\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_USBFS_USBFS_1_H)\r
-#define CY_USBFS_USBFS_1_H\r
-\r
-#include "cytypes.h"\r
-#include "cydevice_trm.h"\r
-#include "cyfitter.h"\r
-#include "CyLib.h"\r
-\r
-\r
-/***************************************\r
-* Conditional Compilation Parameters\r
-***************************************/\r
-\r
-/* Check to see if required defines such as CY_PSOC5LP are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5LP)\r
- #error Component USBFS_v2_60 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5LP) */\r
-\r
-\r
-/***************************************\r
-* Memory Type Definitions\r
-***************************************/\r
-\r
-/* Renamed Type Definitions for backward compatibility.\r
-* Should not be used in new designs.\r
-*/\r
-#define USBFS_1_CODE CYCODE\r
-#define USBFS_1_FAR CYFAR\r
-#if defined(__C51__) || defined(__CX51__)\r
- #define USBFS_1_DATA data\r
- #define USBFS_1_XDATA xdata\r
-#else\r
- #define USBFS_1_DATA\r
- #define USBFS_1_XDATA\r
-#endif /* End __C51__ */\r
-#define USBFS_1_NULL NULL\r
-\r
-\r
-/***************************************\r
-* Enumerated Types and Parameters\r
-***************************************/\r
-\r
-#define USBFS_1__EP_MANUAL 0\r
-#define USBFS_1__EP_DMAMANUAL 1\r
-#define USBFS_1__EP_DMAAUTO 2\r
-\r
-#define USBFS_1__MA_STATIC 0\r
-#define USBFS_1__MA_DYNAMIC 1\r
-\r
-\r
-\r
-/***************************************\r
-* Initial Parameter Constants\r
-***************************************/\r
-\r
-#define USBFS_1_NUM_DEVICES (1u)\r
-#define USBFS_1_MAX_REPORTID_NUMBER (0u)\r
-\r
-#define USBFS_1_MON_VBUS (0u)\r
-#define USBFS_1_EXTERN_VBUS (0u)\r
-#define USBFS_1_EXTERN_VND (0u)\r
-#define USBFS_1_EXTERN_CLS (0u)\r
-#define USBFS_1_MAX_INTERFACES_NUMBER (1u)\r
-#define USBFS_1_EP0_ISR_REMOVE (0u)\r
-#define USBFS_1_EP1_ISR_REMOVE (0u)\r
-#define USBFS_1_EP2_ISR_REMOVE (1u)\r
-#define USBFS_1_EP3_ISR_REMOVE (1u)\r
-#define USBFS_1_EP4_ISR_REMOVE (1u)\r
-#define USBFS_1_EP5_ISR_REMOVE (1u)\r
-#define USBFS_1_EP6_ISR_REMOVE (1u)\r
-#define USBFS_1_EP7_ISR_REMOVE (1u)\r
-#define USBFS_1_EP8_ISR_REMOVE (1u)\r
-#define USBFS_1_EP_MM (0u)\r
-#define USBFS_1_EP_MA (0u)\r
-#define USBFS_1_DMA1_REMOVE (1u)\r
-#define USBFS_1_DMA2_REMOVE (1u)\r
-#define USBFS_1_DMA3_REMOVE (1u)\r
-#define USBFS_1_DMA4_REMOVE (1u)\r
-#define USBFS_1_DMA5_REMOVE (1u)\r
-#define USBFS_1_DMA6_REMOVE (1u)\r
-#define USBFS_1_DMA7_REMOVE (1u)\r
-#define USBFS_1_DMA8_REMOVE (1u)\r
-#define USBFS_1_SOF_ISR_REMOVE (0u)\r
-#define USBFS_1_ARB_ISR_REMOVE (0u)\r
-#define USBFS_1_DP_ISR_REMOVE (0u)\r
-#define USBFS_1_ENABLE_CDC_CLASS_API (1u)\r
-#define USBFS_1_ENABLE_MIDI_API (1u)\r
-#define USBFS_1_MIDI_EXT_MODE (0u)\r
-\r
-\r
-/***************************************\r
-* Data Struct Definition\r
-***************************************/\r
-\r
-typedef struct\r
-{\r
- uint8 attrib;\r
- uint8 apiEpState;\r
- uint8 hwEpState;\r
- uint8 epToggle;\r
- uint8 addr;\r
- uint8 epMode;\r
- uint16 buffOffset;\r
- uint16 bufferSize;\r
- uint8 interface;\r
-} T_USBFS_1_EP_CTL_BLOCK;\r
-\r
-typedef struct\r
-{\r
- uint8 interface;\r
- uint8 altSetting;\r
- uint8 addr;\r
- uint8 attributes;\r
- uint16 bufferSize;\r
- uint8 bMisc;\r
-} T_USBFS_1_EP_SETTINGS_BLOCK;\r
-\r
-typedef struct\r
-{\r
- uint8 status;\r
- uint16 length;\r
-} T_USBFS_1_XFER_STATUS_BLOCK;\r
-\r
-typedef struct\r
-{\r
- uint16 count;\r
- volatile uint8 *pData;\r
- T_USBFS_1_XFER_STATUS_BLOCK *pStatusBlock;\r
-} T_USBFS_1_TD;\r
-\r
-\r
-typedef struct\r
-{\r
- uint8 c;\r
- const void *p_list;\r
-} T_USBFS_1_LUT;\r
-\r
-/* Resume/Suspend API Support */\r
-typedef struct\r
-{\r
- uint8 enableState;\r
- uint8 mode;\r
-} USBFS_1_BACKUP_STRUCT;\r
-\r
-\r
-/* Renamed structure fields for backward compatibility.\r
-* Should not be used in new designs.\r
-*/\r
-#define wBuffOffset buffOffset\r
-#define wBufferSize bufferSize\r
-#define bStatus status\r
-#define wLength length\r
-#define wCount count\r
-\r
-/* Renamed global variable for backward compatibility.\r
-* Should not be used in new designs.\r
-*/\r
-#define CurrentTD USBFS_1_currentTD\r
-\r
-\r
-/***************************************\r
-* Function Prototypes\r
-***************************************/\r
-\r
-void USBFS_1_Start(uint8 device, uint8 mode) ;\r
-void USBFS_1_Init(void) ;\r
-void USBFS_1_InitComponent(uint8 device, uint8 mode) ;\r
-void USBFS_1_Stop(void) ;\r
-uint8 USBFS_1_CheckActivity(void) ;\r
-uint8 USBFS_1_GetConfiguration(void) ;\r
-uint8 USBFS_1_IsConfigurationChanged(void) ;\r
-uint8 USBFS_1_GetInterfaceSetting(uint8 interfaceNumber)\r
- ;\r
-uint8 USBFS_1_GetEPState(uint8 epNumber) ;\r
-uint16 USBFS_1_GetEPCount(uint8 epNumber) ;\r
-void USBFS_1_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length)\r
- ;\r
-uint16 USBFS_1_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length)\r
- ;\r
-void USBFS_1_EnableOutEP(uint8 epNumber) ;\r
-void USBFS_1_DisableOutEP(uint8 epNumber) ;\r
-void USBFS_1_Force(uint8 bState) ;\r
-uint8 USBFS_1_GetEPAckState(uint8 epNumber) ;\r
-void USBFS_1_SetPowerStatus(uint8 powerStatus) ;\r
-uint8 USBFS_1_RWUEnabled(void) ;\r
-void USBFS_1_TerminateEP(uint8 ep) ;\r
-\r
-void USBFS_1_Suspend(void) ;\r
-void USBFS_1_Resume(void) ;\r
-\r
-#if defined(USBFS_1_ENABLE_FWSN_STRING)\r
- void USBFS_1_SerialNumString(uint8 snString[]) ;\r
-#endif /* USBFS_1_ENABLE_FWSN_STRING */\r
-#if (USBFS_1_MON_VBUS == 1u)\r
- uint8 USBFS_1_VBusPresent(void) ;\r
-#endif /* End USBFS_1_MON_VBUS */\r
-\r
-#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS_1) || \\r
- (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))\r
-\r
- void USBFS_1_CyBtldrCommStart(void) ;\r
- void USBFS_1_CyBtldrCommStop(void) ;\r
- void USBFS_1_CyBtldrCommReset(void) ;\r
- cystatus USBFS_1_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
- ;\r
- cystatus USBFS_1_CyBtldrCommRead( uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
- ;\r
-\r
- #define USBFS_1_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* EP 1 OUT */\r
- #define USBFS_1_BTLDR_SIZEOF_READ_BUFFER (64u) /* EP 2 IN */\r
- #define USBFS_1_BTLDR_MAX_PACKET_SIZE USBFS_1_BTLDR_SIZEOF_WRITE_BUFFER\r
-\r
- /* These defines active if used USBFS interface as an\r
- * IO Component for bootloading. When Custom_Interface selected\r
- * in Bootloder configuration as the IO Component, user must\r
- * provide these functions\r
- */\r
- #if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS_1)\r
- #define CyBtldrCommStart USBFS_1_CyBtldrCommStart\r
- #define CyBtldrCommStop USBFS_1_CyBtldrCommStop\r
- #define CyBtldrCommReset USBFS_1_CyBtldrCommReset\r
- #define CyBtldrCommWrite USBFS_1_CyBtldrCommWrite\r
- #define CyBtldrCommRead USBFS_1_CyBtldrCommRead\r
- #endif /*End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS_1 */\r
-\r
-#endif /* End CYDEV_BOOTLOADER_IO_COMP */\r
-\r
-#if(USBFS_1_EP_MM != USBFS_1__EP_MANUAL)\r
- void USBFS_1_InitEP_DMA(uint8 epNumber, const uint8 *pData)\r
- ;\r
- void USBFS_1_Stop_DMA(uint8 epNumber) ;\r
-#endif /* End USBFS_1_EP_MM != USBFS_1__EP_MANUAL) */\r
-\r
-#if defined(USBFS_1_ENABLE_MIDI_STREAMING) && (USBFS_1_ENABLE_MIDI_API != 0u)\r
- void USBFS_1_MIDI_EP_Init(void) ;\r
-\r
- #if (USBFS_1_MIDI_IN_BUFF_SIZE > 0)\r
- void USBFS_1_MIDI_IN_Service(void) ;\r
- uint8 USBFS_1_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable)\r
- ;\r
- #endif /* USBFS_1_MIDI_IN_BUFF_SIZE > 0 */\r
-\r
- #if (USBFS_1_MIDI_OUT_BUFF_SIZE > 0)\r
- void USBFS_1_MIDI_OUT_EP_Service(void) ;\r
- #endif /* USBFS_1_MIDI_OUT_BUFF_SIZE > 0 */\r
-\r
-#endif /* End USBFS_1_ENABLE_MIDI_API != 0u */\r
-\r
-/* Renamed Functions for backward compatibility.\r
-* Should not be used in new designs.\r
-*/\r
-\r
-#define USBFS_1_bCheckActivity USBFS_1_CheckActivity\r
-#define USBFS_1_bGetConfiguration USBFS_1_GetConfiguration\r
-#define USBFS_1_bGetInterfaceSetting USBFS_1_GetInterfaceSetting\r
-#define USBFS_1_bGetEPState USBFS_1_GetEPState\r
-#define USBFS_1_wGetEPCount USBFS_1_GetEPCount\r
-#define USBFS_1_bGetEPAckState USBFS_1_GetEPAckState\r
-#define USBFS_1_bRWUEnabled USBFS_1_RWUEnabled\r
-#define USBFS_1_bVBusPresent USBFS_1_VBusPresent\r
-\r
-#define USBFS_1_bConfiguration USBFS_1_configuration\r
-#define USBFS_1_bInterfaceSetting USBFS_1_interfaceSetting\r
-#define USBFS_1_bDeviceAddress USBFS_1_deviceAddress\r
-#define USBFS_1_bDeviceStatus USBFS_1_deviceStatus\r
-#define USBFS_1_bDevice USBFS_1_device\r
-#define USBFS_1_bTransferState USBFS_1_transferState\r
-#define USBFS_1_bLastPacketSize USBFS_1_lastPacketSize\r
-\r
-#define USBFS_1_LoadEP USBFS_1_LoadInEP\r
-#define USBFS_1_LoadInISOCEP USBFS_1_LoadInEP\r
-#define USBFS_1_EnableOutISOCEP USBFS_1_EnableOutEP\r
-\r
-#define USBFS_1_SetVector CyIntSetVector\r
-#define USBFS_1_SetPriority CyIntSetPriority\r
-#define USBFS_1_EnableInt CyIntEnable\r
-\r
-\r
-/***************************************\r
-* API Constants\r
-***************************************/\r
-\r
-#define USBFS_1_EP0 (0u)\r
-#define USBFS_1_EP1 (1u)\r
-#define USBFS_1_EP2 (2u)\r
-#define USBFS_1_EP3 (3u)\r
-#define USBFS_1_EP4 (4u)\r
-#define USBFS_1_EP5 (5u)\r
-#define USBFS_1_EP6 (6u)\r
-#define USBFS_1_EP7 (7u)\r
-#define USBFS_1_EP8 (8u)\r
-#define USBFS_1_MAX_EP (9u)\r
-\r
-#define USBFS_1_TRUE (1u)\r
-#define USBFS_1_FALSE (0u)\r
-\r
-#define USBFS_1_NO_EVENT_ALLOWED (2u)\r
-#define USBFS_1_EVENT_PENDING (1u)\r
-#define USBFS_1_NO_EVENT_PENDING (0u)\r
-\r
-#define USBFS_1_IN_BUFFER_FULL USBFS_1_NO_EVENT_PENDING\r
-#define USBFS_1_IN_BUFFER_EMPTY USBFS_1_EVENT_PENDING\r
-#define USBFS_1_OUT_BUFFER_FULL USBFS_1_EVENT_PENDING\r
-#define USBFS_1_OUT_BUFFER_EMPTY USBFS_1_NO_EVENT_PENDING\r
-\r
-#define USBFS_1_FORCE_J (0xA0u)\r
-#define USBFS_1_FORCE_K (0x80u)\r
-#define USBFS_1_FORCE_SE0 (0xC0u)\r
-#define USBFS_1_FORCE_NONE (0x00u)\r
-\r
-#define USBFS_1_IDLE_TIMER_RUNNING (0x02u)\r
-#define USBFS_1_IDLE_TIMER_EXPIRED (0x01u)\r
-#define USBFS_1_IDLE_TIMER_INDEFINITE (0x00u)\r
-\r
-#define USBFS_1_DEVICE_STATUS_BUS_POWERED (0x00u)\r
-#define USBFS_1_DEVICE_STATUS_SELF_POWERED (0x01u)\r
-\r
-#define USBFS_1_3V_OPERATION (0x00u)\r
-#define USBFS_1_5V_OPERATION (0x01u)\r
-#define USBFS_1_DWR_VDDD_OPERATION (0x02u)\r
-\r
-#define USBFS_1_MODE_DISABLE (0x00u)\r
-#define USBFS_1_MODE_NAK_IN_OUT (0x01u)\r
-#define USBFS_1_MODE_STATUS_OUT_ONLY (0x02u)\r
-#define USBFS_1_MODE_STALL_IN_OUT (0x03u)\r
-#define USBFS_1_MODE_RESERVED_0100 (0x04u)\r
-#define USBFS_1_MODE_ISO_OUT (0x05u)\r
-#define USBFS_1_MODE_STATUS_IN_ONLY (0x06u)\r
-#define USBFS_1_MODE_ISO_IN (0x07u)\r
-#define USBFS_1_MODE_NAK_OUT (0x08u)\r
-#define USBFS_1_MODE_ACK_OUT (0x09u)\r
-#define USBFS_1_MODE_RESERVED_1010 (0x0Au)\r
-#define USBFS_1_MODE_ACK_OUT_STATUS_IN (0x0Bu)\r
-#define USBFS_1_MODE_NAK_IN (0x0Cu)\r
-#define USBFS_1_MODE_ACK_IN (0x0Du)\r
-#define USBFS_1_MODE_RESERVED_1110 (0x0Eu)\r
-#define USBFS_1_MODE_ACK_IN_STATUS_OUT (0x0Fu)\r
-#define USBFS_1_MODE_MASK (0x0Fu)\r
-#define USBFS_1_MODE_STALL_DATA_EP (0x80u)\r
-\r
-#define USBFS_1_MODE_ACKD (0x10u)\r
-#define USBFS_1_MODE_OUT_RCVD (0x20u)\r
-#define USBFS_1_MODE_IN_RCVD (0x40u)\r
-#define USBFS_1_MODE_SETUP_RCVD (0x80u)\r
-\r
-#define USBFS_1_RQST_TYPE_MASK (0x60u)\r
-#define USBFS_1_RQST_TYPE_STD (0x00u)\r
-#define USBFS_1_RQST_TYPE_CLS (0x20u)\r
-#define USBFS_1_RQST_TYPE_VND (0x40u)\r
-#define USBFS_1_RQST_DIR_MASK (0x80u)\r
-#define USBFS_1_RQST_DIR_D2H (0x80u)\r
-#define USBFS_1_RQST_DIR_H2D (0x00u)\r
-#define USBFS_1_RQST_RCPT_MASK (0x03u)\r
-#define USBFS_1_RQST_RCPT_DEV (0x00u)\r
-#define USBFS_1_RQST_RCPT_IFC (0x01u)\r
-#define USBFS_1_RQST_RCPT_EP (0x02u)\r
-#define USBFS_1_RQST_RCPT_OTHER (0x03u)\r
-\r
-/* USB Class Codes */\r
-#define USBFS_1_CLASS_DEVICE (0x00u) /* Use class code info from Interface Descriptors */\r
-#define USBFS_1_CLASS_AUDIO (0x01u) /* Audio device */\r
-#define USBFS_1_CLASS_CDC (0x02u) /* Communication device class */\r
-#define USBFS_1_CLASS_HID (0x03u) /* Human Interface Device */\r
-#define USBFS_1_CLASS_PDC (0x05u) /* Physical device class */\r
-#define USBFS_1_CLASS_IMAGE (0x06u) /* Still Imaging device */\r
-#define USBFS_1_CLASS_PRINTER (0x07u) /* Printer device */\r
-#define USBFS_1_CLASS_MSD (0x08u) /* Mass Storage device */\r
-#define USBFS_1_CLASS_HUB (0x09u) /* Full/Hi speed Hub */\r
-#define USBFS_1_CLASS_CDC_DATA (0x0Au) /* CDC data device */\r
-#define USBFS_1_CLASS_SMART_CARD (0x0Bu) /* Smart Card device */\r
-#define USBFS_1_CLASS_CSD (0x0Du) /* Content Security device */\r
-#define USBFS_1_CLASS_VIDEO (0x0Eu) /* Video device */\r
-#define USBFS_1_CLASS_PHD (0x0Fu) /* Personal Healthcare device */\r
-#define USBFS_1_CLASS_WIRELESSD (0xDCu) /* Wireless Controller */\r
-#define USBFS_1_CLASS_MIS (0xE0u) /* Miscellaneous */\r
-#define USBFS_1_CLASS_APP (0xEFu) /* Application Specific */\r
-#define USBFS_1_CLASS_VENDOR (0xFFu) /* Vendor specific */\r
-\r
-\r
-/* Standard Request Types (Table 9-4) */\r
-#define USBFS_1_GET_STATUS (0x00u)\r
-#define USBFS_1_CLEAR_FEATURE (0x01u)\r
-#define USBFS_1_SET_FEATURE (0x03u)\r
-#define USBFS_1_SET_ADDRESS (0x05u)\r
-#define USBFS_1_GET_DESCRIPTOR (0x06u)\r
-#define USBFS_1_SET_DESCRIPTOR (0x07u)\r
-#define USBFS_1_GET_CONFIGURATION (0x08u)\r
-#define USBFS_1_SET_CONFIGURATION (0x09u)\r
-#define USBFS_1_GET_INTERFACE (0x0Au)\r
-#define USBFS_1_SET_INTERFACE (0x0Bu)\r
-#define USBFS_1_SYNCH_FRAME (0x0Cu)\r
-\r
-/* Vendor Specific Request Types */\r
-/* Request for Microsoft OS String Descriptor */\r
-#define USBFS_1_GET_EXTENDED_CONFIG_DESCRIPTOR (0x01u)\r
-\r
-/* Descriptor Types (Table 9-5) */\r
-#define USBFS_1_DESCR_DEVICE (1u)\r
-#define USBFS_1_DESCR_CONFIG (2u)\r
-#define USBFS_1_DESCR_STRING (3u)\r
-#define USBFS_1_DESCR_INTERFACE (4u)\r
-#define USBFS_1_DESCR_ENDPOINT (5u)\r
-#define USBFS_1_DESCR_DEVICE_QUALIFIER (6u)\r
-#define USBFS_1_DESCR_OTHER_SPEED (7u)\r
-#define USBFS_1_DESCR_INTERFACE_POWER (8u)\r
-\r
-/* Device Descriptor Defines */\r
-#define USBFS_1_DEVICE_DESCR_LENGTH (18u)\r
-#define USBFS_1_DEVICE_DESCR_SN_SHIFT (16u)\r
-\r
-/* Config Descriptor Shifts and Masks */\r
-#define USBFS_1_CONFIG_DESCR_LENGTH (0u)\r
-#define USBFS_1_CONFIG_DESCR_TYPE (1u)\r
-#define USBFS_1_CONFIG_DESCR_TOTAL_LENGTH_LOW (2u)\r
-#define USBFS_1_CONFIG_DESCR_TOTAL_LENGTH_HI (3u)\r
-#define USBFS_1_CONFIG_DESCR_NUM_INTERFACES (4u)\r
-#define USBFS_1_CONFIG_DESCR_CONFIG_VALUE (5u)\r
-#define USBFS_1_CONFIG_DESCR_CONFIGURATION (6u)\r
-#define USBFS_1_CONFIG_DESCR_ATTRIB (7u)\r
-#define USBFS_1_CONFIG_DESCR_ATTRIB_SELF_POWERED (0x40u)\r
-#define USBFS_1_CONFIG_DESCR_ATTRIB_RWU_EN (0x20u)\r
-\r
-/* Feature Selectors (Table 9-6) */\r
-#define USBFS_1_DEVICE_REMOTE_WAKEUP (0x01u)\r
-#define USBFS_1_ENDPOINT_HALT (0x00u)\r
-#define USBFS_1_TEST_MODE (0x02u)\r
-\r
-/* USB Device Status (Figure 9-4) */\r
-#define USBFS_1_DEVICE_STATUS_BUS_POWERED (0x00u)\r
-#define USBFS_1_DEVICE_STATUS_SELF_POWERED (0x01u)\r
-#define USBFS_1_DEVICE_STATUS_REMOTE_WAKEUP (0x02u)\r
-\r
-/* USB Endpoint Status (Figure 9-4) */\r
-#define USBFS_1_ENDPOINT_STATUS_HALT (0x01u)\r
-\r
-/* USB Endpoint Directions */\r
-#define USBFS_1_DIR_IN (0x80u)\r
-#define USBFS_1_DIR_OUT (0x00u)\r
-#define USBFS_1_DIR_UNUSED (0x7Fu)\r
-\r
-/* USB Endpoint Attributes */\r
-#define USBFS_1_EP_TYPE_CTRL (0x00u)\r
-#define USBFS_1_EP_TYPE_ISOC (0x01u)\r
-#define USBFS_1_EP_TYPE_BULK (0x02u)\r
-#define USBFS_1_EP_TYPE_INT (0x03u)\r
-#define USBFS_1_EP_TYPE_MASK (0x03u)\r
-\r
-#define USBFS_1_EP_SYNC_TYPE_NO_SYNC (0x00u)\r
-#define USBFS_1_EP_SYNC_TYPE_ASYNC (0x04u)\r
-#define USBFS_1_EP_SYNC_TYPE_ADAPTIVE (0x08u)\r
-#define USBFS_1_EP_SYNC_TYPE_SYNCHRONOUS (0x0Cu)\r
-#define USBFS_1_EP_SYNC_TYPE_MASK (0x0Cu)\r
-\r
-#define USBFS_1_EP_USAGE_TYPE_DATA (0x00u)\r
-#define USBFS_1_EP_USAGE_TYPE_FEEDBACK (0x10u)\r
-#define USBFS_1_EP_USAGE_TYPE_IMPLICIT (0x20u)\r
-#define USBFS_1_EP_USAGE_TYPE_RESERVED (0x30u)\r
-#define USBFS_1_EP_USAGE_TYPE_MASK (0x30u)\r
-\r
-/* Endpoint Status defines */\r
-#define USBFS_1_EP_STATUS_LENGTH (0x02u)\r
-\r
-/* Endpoint Device defines */\r
-#define USBFS_1_DEVICE_STATUS_LENGTH (0x02u)\r
-\r
-#define USBFS_1_STATUS_LENGTH_MAX \\r
- ( (USBFS_1_EP_STATUS_LENGTH > USBFS_1_DEVICE_STATUS_LENGTH) ? \\r
- USBFS_1_EP_STATUS_LENGTH : USBFS_1_DEVICE_STATUS_LENGTH )\r
-/* Transfer Completion Notification */\r
-#define USBFS_1_XFER_IDLE (0x00u)\r
-#define USBFS_1_XFER_STATUS_ACK (0x01u)\r
-#define USBFS_1_XFER_PREMATURE (0x02u)\r
-#define USBFS_1_XFER_ERROR (0x03u)\r
-\r
-/* Driver State defines */\r
-#define USBFS_1_TRANS_STATE_IDLE (0x00u)\r
-#define USBFS_1_TRANS_STATE_CONTROL_READ (0x02u)\r
-#define USBFS_1_TRANS_STATE_CONTROL_WRITE (0x04u)\r
-#define USBFS_1_TRANS_STATE_NO_DATA_CONTROL (0x06u)\r
-\r
-/* String Descriptor defines */\r
-#define USBFS_1_STRING_MSOS (0xEEu)\r
-#define USBFS_1_MSOS_DESCRIPTOR_LENGTH (18u)\r
-#define USBFS_1_MSOS_CONF_DESCR_LENGTH (40u)\r
-\r
-#if(USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL)\r
- /* DMA manual mode defines */\r
- #define USBFS_1_DMA_BYTES_PER_BURST (0u)\r
- #define USBFS_1_DMA_REQUEST_PER_BURST (0u)\r
-#endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL */\r
-#if(USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO)\r
- /* DMA automatic mode defines */\r
- #define USBFS_1_DMA_BYTES_PER_BURST (32u)\r
- /* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */\r
- #define USBFS_1_DMA_BUF_SIZE (0x55u)\r
- #define USBFS_1_DMA_REQUEST_PER_BURST (1u)\r
-#endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO */\r
-\r
-/* DIE ID string descriptor defines */\r
-#if defined(USBFS_1_ENABLE_IDSN_STRING)\r
- #define USBFS_1_IDSN_DESCR_LENGTH (0x22u)\r
-#endif /* USBFS_1_ENABLE_IDSN_STRING */\r
-\r
-\r
-/***************************************\r
-* External data references\r
-***************************************/\r
-\r
-extern uint8 USBFS_1_initVar;\r
-extern volatile uint8 USBFS_1_device;\r
-extern volatile uint8 USBFS_1_transferState;\r
-extern volatile uint8 USBFS_1_configuration;\r
-extern volatile uint8 USBFS_1_configurationChanged;\r
-extern volatile uint8 USBFS_1_deviceStatus;\r
-\r
-/* HID Variables */\r
-#if defined(USBFS_1_ENABLE_HID_CLASS)\r
- extern volatile uint8 USBFS_1_hidProtocol[USBFS_1_MAX_INTERFACES_NUMBER];\r
- extern volatile uint8 USBFS_1_hidIdleRate[USBFS_1_MAX_INTERFACES_NUMBER];\r
- extern volatile uint8 USBFS_1_hidIdleTimer[USBFS_1_MAX_INTERFACES_NUMBER];\r
-#endif /* USBFS_1_ENABLE_HID_CLASS */\r
-\r
-\r
-/***************************************\r
-* Registers\r
-***************************************/\r
-\r
-#define USBFS_1_ARB_CFG_PTR ( (reg8 *) USBFS_1_USB__ARB_CFG)\r
-#define USBFS_1_ARB_CFG_REG (* (reg8 *) USBFS_1_USB__ARB_CFG)\r
-\r
-#define USBFS_1_ARB_EP1_CFG_PTR ( (reg8 *) USBFS_1_USB__ARB_EP1_CFG)\r
-#define USBFS_1_ARB_EP1_CFG_REG (* (reg8 *) USBFS_1_USB__ARB_EP1_CFG)\r
-#define USBFS_1_ARB_EP1_CFG_IND USBFS_1_USB__ARB_EP1_CFG\r
-#define USBFS_1_ARB_EP1_INT_EN_PTR ( (reg8 *) USBFS_1_USB__ARB_EP1_INT_EN)\r
-#define USBFS_1_ARB_EP1_INT_EN_REG (* (reg8 *) USBFS_1_USB__ARB_EP1_INT_EN)\r
-#define USBFS_1_ARB_EP1_INT_EN_IND USBFS_1_USB__ARB_EP1_INT_EN\r
-#define USBFS_1_ARB_EP1_SR_PTR ( (reg8 *) USBFS_1_USB__ARB_EP1_SR)\r
-#define USBFS_1_ARB_EP1_SR_REG (* (reg8 *) USBFS_1_USB__ARB_EP1_SR)\r
-#define USBFS_1_ARB_EP1_SR_IND USBFS_1_USB__ARB_EP1_SR\r
-\r
-#define USBFS_1_ARB_EP2_CFG_PTR ( (reg8 *) USBFS_1_USB__ARB_EP2_CFG)\r
-#define USBFS_1_ARB_EP2_CFG_REG (* (reg8 *) USBFS_1_USB__ARB_EP2_CFG)\r
-#define USBFS_1_ARB_EP2_INT_EN_PTR ( (reg8 *) USBFS_1_USB__ARB_EP2_INT_EN)\r
-#define USBFS_1_ARB_EP2_INT_EN_REG (* (reg8 *) USBFS_1_USB__ARB_EP2_INT_EN)\r
-#define USBFS_1_ARB_EP2_SR_PTR ( (reg8 *) USBFS_1_USB__ARB_EP2_SR)\r
-#define USBFS_1_ARB_EP2_SR_REG (* (reg8 *) USBFS_1_USB__ARB_EP2_SR)\r
-\r
-#define USBFS_1_ARB_EP3_CFG_PTR ( (reg8 *) USBFS_1_USB__ARB_EP3_CFG)\r
-#define USBFS_1_ARB_EP3_CFG_REG (* (reg8 *) USBFS_1_USB__ARB_EP3_CFG)\r
-#define USBFS_1_ARB_EP3_INT_EN_PTR ( (reg8 *) USBFS_1_USB__ARB_EP3_INT_EN)\r
-#define USBFS_1_ARB_EP3_INT_EN_REG (* (reg8 *) USBFS_1_USB__ARB_EP3_INT_EN)\r
-#define USBFS_1_ARB_EP3_SR_PTR ( (reg8 *) USBFS_1_USB__ARB_EP3_SR)\r
-#define USBFS_1_ARB_EP3_SR_REG (* (reg8 *) USBFS_1_USB__ARB_EP3_SR)\r
-\r
-#define USBFS_1_ARB_EP4_CFG_PTR ( (reg8 *) USBFS_1_USB__ARB_EP4_CFG)\r
-#define USBFS_1_ARB_EP4_CFG_REG (* (reg8 *) USBFS_1_USB__ARB_EP4_CFG)\r
-#define USBFS_1_ARB_EP4_INT_EN_PTR ( (reg8 *) USBFS_1_USB__ARB_EP4_INT_EN)\r
-#define USBFS_1_ARB_EP4_INT_EN_REG (* (reg8 *) USBFS_1_USB__ARB_EP4_INT_EN)\r
-#define USBFS_1_ARB_EP4_SR_PTR ( (reg8 *) USBFS_1_USB__ARB_EP4_SR)\r
-#define USBFS_1_ARB_EP4_SR_REG (* (reg8 *) USBFS_1_USB__ARB_EP4_SR)\r
-\r
-#define USBFS_1_ARB_EP5_CFG_PTR ( (reg8 *) USBFS_1_USB__ARB_EP5_CFG)\r
-#define USBFS_1_ARB_EP5_CFG_REG (* (reg8 *) USBFS_1_USB__ARB_EP5_CFG)\r
-#define USBFS_1_ARB_EP5_INT_EN_PTR ( (reg8 *) USBFS_1_USB__ARB_EP5_INT_EN)\r
-#define USBFS_1_ARB_EP5_INT_EN_REG (* (reg8 *) USBFS_1_USB__ARB_EP5_INT_EN)\r
-#define USBFS_1_ARB_EP5_SR_PTR ( (reg8 *) USBFS_1_USB__ARB_EP5_SR)\r
-#define USBFS_1_ARB_EP5_SR_REG (* (reg8 *) USBFS_1_USB__ARB_EP5_SR)\r
-\r
-#define USBFS_1_ARB_EP6_CFG_PTR ( (reg8 *) USBFS_1_USB__ARB_EP6_CFG)\r
-#define USBFS_1_ARB_EP6_CFG_REG (* (reg8 *) USBFS_1_USB__ARB_EP6_CFG)\r
-#define USBFS_1_ARB_EP6_INT_EN_PTR ( (reg8 *) USBFS_1_USB__ARB_EP6_INT_EN)\r
-#define USBFS_1_ARB_EP6_INT_EN_REG (* (reg8 *) USBFS_1_USB__ARB_EP6_INT_EN)\r
-#define USBFS_1_ARB_EP6_SR_PTR ( (reg8 *) USBFS_1_USB__ARB_EP6_SR)\r
-#define USBFS_1_ARB_EP6_SR_REG (* (reg8 *) USBFS_1_USB__ARB_EP6_SR)\r
-\r
-#define USBFS_1_ARB_EP7_CFG_PTR ( (reg8 *) USBFS_1_USB__ARB_EP7_CFG)\r
-#define USBFS_1_ARB_EP7_CFG_REG (* (reg8 *) USBFS_1_USB__ARB_EP7_CFG)\r
-#define USBFS_1_ARB_EP7_INT_EN_PTR ( (reg8 *) USBFS_1_USB__ARB_EP7_INT_EN)\r
-#define USBFS_1_ARB_EP7_INT_EN_REG (* (reg8 *) USBFS_1_USB__ARB_EP7_INT_EN)\r
-#define USBFS_1_ARB_EP7_SR_PTR ( (reg8 *) USBFS_1_USB__ARB_EP7_SR)\r
-#define USBFS_1_ARB_EP7_SR_REG (* (reg8 *) USBFS_1_USB__ARB_EP7_SR)\r
-\r
-#define USBFS_1_ARB_EP8_CFG_PTR ( (reg8 *) USBFS_1_USB__ARB_EP8_CFG)\r
-#define USBFS_1_ARB_EP8_CFG_REG (* (reg8 *) USBFS_1_USB__ARB_EP8_CFG)\r
-#define USBFS_1_ARB_EP8_INT_EN_PTR ( (reg8 *) USBFS_1_USB__ARB_EP8_INT_EN)\r
-#define USBFS_1_ARB_EP8_INT_EN_REG (* (reg8 *) USBFS_1_USB__ARB_EP8_INT_EN)\r
-#define USBFS_1_ARB_EP8_SR_PTR ( (reg8 *) USBFS_1_USB__ARB_EP8_SR)\r
-#define USBFS_1_ARB_EP8_SR_REG (* (reg8 *) USBFS_1_USB__ARB_EP8_SR)\r
-\r
-#define USBFS_1_ARB_INT_EN_PTR ( (reg8 *) USBFS_1_USB__ARB_INT_EN)\r
-#define USBFS_1_ARB_INT_EN_REG (* (reg8 *) USBFS_1_USB__ARB_INT_EN)\r
-#define USBFS_1_ARB_INT_SR_PTR ( (reg8 *) USBFS_1_USB__ARB_INT_SR)\r
-#define USBFS_1_ARB_INT_SR_REG (* (reg8 *) USBFS_1_USB__ARB_INT_SR)\r
-\r
-#define USBFS_1_ARB_RW1_DR_PTR ((reg8 *) USBFS_1_USB__ARB_RW1_DR)\r
-#define USBFS_1_ARB_RW1_DR_IND USBFS_1_USB__ARB_RW1_DR\r
-#define USBFS_1_ARB_RW1_RA_PTR ((reg8 *) USBFS_1_USB__ARB_RW1_RA)\r
-#define USBFS_1_ARB_RW1_RA_IND USBFS_1_USB__ARB_RW1_RA\r
-#define USBFS_1_ARB_RW1_RA_MSB_PTR ((reg8 *) USBFS_1_USB__ARB_RW1_RA_MSB)\r
-#define USBFS_1_ARB_RW1_RA_MSB_IND USBFS_1_USB__ARB_RW1_RA_MSB\r
-#define USBFS_1_ARB_RW1_WA_PTR ((reg8 *) USBFS_1_USB__ARB_RW1_WA)\r
-#define USBFS_1_ARB_RW1_WA_IND USBFS_1_USB__ARB_RW1_WA\r
-#define USBFS_1_ARB_RW1_WA_MSB_PTR ((reg8 *) USBFS_1_USB__ARB_RW1_WA_MSB)\r
-#define USBFS_1_ARB_RW1_WA_MSB_IND USBFS_1_USB__ARB_RW1_WA_MSB\r
-\r
-#define USBFS_1_ARB_RW2_DR_PTR ((reg8 *) USBFS_1_USB__ARB_RW2_DR)\r
-#define USBFS_1_ARB_RW2_RA_PTR ((reg8 *) USBFS_1_USB__ARB_RW2_RA)\r
-#define USBFS_1_ARB_RW2_RA_MSB_PTR ((reg8 *) USBFS_1_USB__ARB_RW2_RA_MSB)\r
-#define USBFS_1_ARB_RW2_WA_PTR ((reg8 *) USBFS_1_USB__ARB_RW2_WA)\r
-#define USBFS_1_ARB_RW2_WA_MSB_PTR ((reg8 *) USBFS_1_USB__ARB_RW2_WA_MSB)\r
-\r
-#define USBFS_1_ARB_RW3_DR_PTR ((reg8 *) USBFS_1_USB__ARB_RW3_DR)\r
-#define USBFS_1_ARB_RW3_RA_PTR ((reg8 *) USBFS_1_USB__ARB_RW3_RA)\r
-#define USBFS_1_ARB_RW3_RA_MSB_PTR ((reg8 *) USBFS_1_USB__ARB_RW3_RA_MSB)\r
-#define USBFS_1_ARB_RW3_WA_PTR ((reg8 *) USBFS_1_USB__ARB_RW3_WA)\r
-#define USBFS_1_ARB_RW3_WA_MSB_PTR ((reg8 *) USBFS_1_USB__ARB_RW3_WA_MSB)\r
-\r
-#define USBFS_1_ARB_RW4_DR_PTR ((reg8 *) USBFS_1_USB__ARB_RW4_DR)\r
-#define USBFS_1_ARB_RW4_RA_PTR ((reg8 *) USBFS_1_USB__ARB_RW4_RA)\r
-#define USBFS_1_ARB_RW4_RA_MSB_PTR ((reg8 *) USBFS_1_USB__ARB_RW4_RA_MSB)\r
-#define USBFS_1_ARB_RW4_WA_PTR ((reg8 *) USBFS_1_USB__ARB_RW4_WA)\r
-#define USBFS_1_ARB_RW4_WA_MSB_PTR ((reg8 *) USBFS_1_USB__ARB_RW4_WA_MSB)\r
-\r
-#define USBFS_1_ARB_RW5_DR_PTR ((reg8 *) USBFS_1_USB__ARB_RW5_DR)\r
-#define USBFS_1_ARB_RW5_RA_PTR ((reg8 *) USBFS_1_USB__ARB_RW5_RA)\r
-#define USBFS_1_ARB_RW5_RA_MSB_PTR ((reg8 *) USBFS_1_USB__ARB_RW5_RA_MSB)\r
-#define USBFS_1_ARB_RW5_WA_PTR ((reg8 *) USBFS_1_USB__ARB_RW5_WA)\r
-#define USBFS_1_ARB_RW5_WA_MSB_PTR ((reg8 *) USBFS_1_USB__ARB_RW5_WA_MSB)\r
-\r
-#define USBFS_1_ARB_RW6_DR_PTR ((reg8 *) USBFS_1_USB__ARB_RW6_DR)\r
-#define USBFS_1_ARB_RW6_RA_PTR ((reg8 *) USBFS_1_USB__ARB_RW6_RA)\r
-#define USBFS_1_ARB_RW6_RA_MSB_PTR ((reg8 *) USBFS_1_USB__ARB_RW6_RA_MSB)\r
-#define USBFS_1_ARB_RW6_WA_PTR ((reg8 *) USBFS_1_USB__ARB_RW6_WA)\r
-#define USBFS_1_ARB_RW6_WA_MSB_PTR ((reg8 *) USBFS_1_USB__ARB_RW6_WA_MSB)\r
-\r
-#define USBFS_1_ARB_RW7_DR_PTR ((reg8 *) USBFS_1_USB__ARB_RW7_DR)\r
-#define USBFS_1_ARB_RW7_RA_PTR ((reg8 *) USBFS_1_USB__ARB_RW7_RA)\r
-#define USBFS_1_ARB_RW7_RA_MSB_PTR ((reg8 *) USBFS_1_USB__ARB_RW7_RA_MSB)\r
-#define USBFS_1_ARB_RW7_WA_PTR ((reg8 *) USBFS_1_USB__ARB_RW7_WA)\r
-#define USBFS_1_ARB_RW7_WA_MSB_PTR ((reg8 *) USBFS_1_USB__ARB_RW7_WA_MSB)\r
-\r
-#define USBFS_1_ARB_RW8_DR_PTR ((reg8 *) USBFS_1_USB__ARB_RW8_DR)\r
-#define USBFS_1_ARB_RW8_RA_PTR ((reg8 *) USBFS_1_USB__ARB_RW8_RA)\r
-#define USBFS_1_ARB_RW8_RA_MSB_PTR ((reg8 *) USBFS_1_USB__ARB_RW8_RA_MSB)\r
-#define USBFS_1_ARB_RW8_WA_PTR ((reg8 *) USBFS_1_USB__ARB_RW8_WA)\r
-#define USBFS_1_ARB_RW8_WA_MSB_PTR ((reg8 *) USBFS_1_USB__ARB_RW8_WA_MSB)\r
-\r
-#define USBFS_1_BUF_SIZE_PTR ( (reg8 *) USBFS_1_USB__BUF_SIZE)\r
-#define USBFS_1_BUF_SIZE_REG (* (reg8 *) USBFS_1_USB__BUF_SIZE)\r
-#define USBFS_1_BUS_RST_CNT_PTR ( (reg8 *) USBFS_1_USB__BUS_RST_CNT)\r
-#define USBFS_1_BUS_RST_CNT_REG (* (reg8 *) USBFS_1_USB__BUS_RST_CNT)\r
-#define USBFS_1_CWA_PTR ( (reg8 *) USBFS_1_USB__CWA)\r
-#define USBFS_1_CWA_REG (* (reg8 *) USBFS_1_USB__CWA)\r
-#define USBFS_1_CWA_MSB_PTR ( (reg8 *) USBFS_1_USB__CWA_MSB)\r
-#define USBFS_1_CWA_MSB_REG (* (reg8 *) USBFS_1_USB__CWA_MSB)\r
-#define USBFS_1_CR0_PTR ( (reg8 *) USBFS_1_USB__CR0)\r
-#define USBFS_1_CR0_REG (* (reg8 *) USBFS_1_USB__CR0)\r
-#define USBFS_1_CR1_PTR ( (reg8 *) USBFS_1_USB__CR1)\r
-#define USBFS_1_CR1_REG (* (reg8 *) USBFS_1_USB__CR1)\r
-\r
-#define USBFS_1_DMA_THRES_PTR ( (reg8 *) USBFS_1_USB__DMA_THRES)\r
-#define USBFS_1_DMA_THRES_REG (* (reg8 *) USBFS_1_USB__DMA_THRES)\r
-#define USBFS_1_DMA_THRES_MSB_PTR ( (reg8 *) USBFS_1_USB__DMA_THRES_MSB)\r
-#define USBFS_1_DMA_THRES_MSB_REG (* (reg8 *) USBFS_1_USB__DMA_THRES_MSB)\r
-\r
-#define USBFS_1_EP_ACTIVE_PTR ( (reg8 *) USBFS_1_USB__EP_ACTIVE)\r
-#define USBFS_1_EP_ACTIVE_REG (* (reg8 *) USBFS_1_USB__EP_ACTIVE)\r
-#define USBFS_1_EP_TYPE_PTR ( (reg8 *) USBFS_1_USB__EP_TYPE)\r
-#define USBFS_1_EP_TYPE_REG (* (reg8 *) USBFS_1_USB__EP_TYPE)\r
-\r
-#define USBFS_1_EP0_CNT_PTR ( (reg8 *) USBFS_1_USB__EP0_CNT)\r
-#define USBFS_1_EP0_CNT_REG (* (reg8 *) USBFS_1_USB__EP0_CNT)\r
-#define USBFS_1_EP0_CR_PTR ( (reg8 *) USBFS_1_USB__EP0_CR)\r
-#define USBFS_1_EP0_CR_REG (* (reg8 *) USBFS_1_USB__EP0_CR)\r
-#define USBFS_1_EP0_DR0_PTR ( (reg8 *) USBFS_1_USB__EP0_DR0)\r
-#define USBFS_1_EP0_DR0_REG (* (reg8 *) USBFS_1_USB__EP0_DR0)\r
-#define USBFS_1_EP0_DR0_IND USBFS_1_USB__EP0_DR0\r
-#define USBFS_1_EP0_DR1_PTR ( (reg8 *) USBFS_1_USB__EP0_DR1)\r
-#define USBFS_1_EP0_DR1_REG (* (reg8 *) USBFS_1_USB__EP0_DR1)\r
-#define USBFS_1_EP0_DR2_PTR ( (reg8 *) USBFS_1_USB__EP0_DR2)\r
-#define USBFS_1_EP0_DR2_REG (* (reg8 *) USBFS_1_USB__EP0_DR2)\r
-#define USBFS_1_EP0_DR3_PTR ( (reg8 *) USBFS_1_USB__EP0_DR3)\r
-#define USBFS_1_EP0_DR3_REG (* (reg8 *) USBFS_1_USB__EP0_DR3)\r
-#define USBFS_1_EP0_DR4_PTR ( (reg8 *) USBFS_1_USB__EP0_DR4)\r
-#define USBFS_1_EP0_DR4_REG (* (reg8 *) USBFS_1_USB__EP0_DR4)\r
-#define USBFS_1_EP0_DR5_PTR ( (reg8 *) USBFS_1_USB__EP0_DR5)\r
-#define USBFS_1_EP0_DR5_REG (* (reg8 *) USBFS_1_USB__EP0_DR5)\r
-#define USBFS_1_EP0_DR6_PTR ( (reg8 *) USBFS_1_USB__EP0_DR6)\r
-#define USBFS_1_EP0_DR6_REG (* (reg8 *) USBFS_1_USB__EP0_DR6)\r
-#define USBFS_1_EP0_DR7_PTR ( (reg8 *) USBFS_1_USB__EP0_DR7)\r
-#define USBFS_1_EP0_DR7_REG (* (reg8 *) USBFS_1_USB__EP0_DR7)\r
-\r
-#define USBFS_1_OSCLK_DR0_PTR ( (reg8 *) USBFS_1_USB__OSCLK_DR0)\r
-#define USBFS_1_OSCLK_DR0_REG (* (reg8 *) USBFS_1_USB__OSCLK_DR0)\r
-#define USBFS_1_OSCLK_DR1_PTR ( (reg8 *) USBFS_1_USB__OSCLK_DR1)\r
-#define USBFS_1_OSCLK_DR1_REG (* (reg8 *) USBFS_1_USB__OSCLK_DR1)\r
-\r
-#define USBFS_1_PM_ACT_CFG_PTR ( (reg8 *) USBFS_1_USB__PM_ACT_CFG)\r
-#define USBFS_1_PM_ACT_CFG_REG (* (reg8 *) USBFS_1_USB__PM_ACT_CFG)\r
-#define USBFS_1_PM_STBY_CFG_PTR ( (reg8 *) USBFS_1_USB__PM_STBY_CFG)\r
-#define USBFS_1_PM_STBY_CFG_REG (* (reg8 *) USBFS_1_USB__PM_STBY_CFG)\r
-\r
-#define USBFS_1_SIE_EP_INT_EN_PTR ( (reg8 *) USBFS_1_USB__SIE_EP_INT_EN)\r
-#define USBFS_1_SIE_EP_INT_EN_REG (* (reg8 *) USBFS_1_USB__SIE_EP_INT_EN)\r
-#define USBFS_1_SIE_EP_INT_SR_PTR ( (reg8 *) USBFS_1_USB__SIE_EP_INT_SR)\r
-#define USBFS_1_SIE_EP_INT_SR_REG (* (reg8 *) USBFS_1_USB__SIE_EP_INT_SR)\r
-\r
-#define USBFS_1_SIE_EP1_CNT0_PTR ( (reg8 *) USBFS_1_USB__SIE_EP1_CNT0)\r
-#define USBFS_1_SIE_EP1_CNT0_REG (* (reg8 *) USBFS_1_USB__SIE_EP1_CNT0)\r
-#define USBFS_1_SIE_EP1_CNT0_IND USBFS_1_USB__SIE_EP1_CNT0\r
-#define USBFS_1_SIE_EP1_CNT1_PTR ( (reg8 *) USBFS_1_USB__SIE_EP1_CNT1)\r
-#define USBFS_1_SIE_EP1_CNT1_REG (* (reg8 *) USBFS_1_USB__SIE_EP1_CNT1)\r
-#define USBFS_1_SIE_EP1_CNT1_IND USBFS_1_USB__SIE_EP1_CNT1\r
-#define USBFS_1_SIE_EP1_CR0_PTR ( (reg8 *) USBFS_1_USB__SIE_EP1_CR0)\r
-#define USBFS_1_SIE_EP1_CR0_REG (* (reg8 *) USBFS_1_USB__SIE_EP1_CR0)\r
-#define USBFS_1_SIE_EP1_CR0_IND USBFS_1_USB__SIE_EP1_CR0\r
-\r
-#define USBFS_1_SIE_EP2_CNT0_PTR ( (reg8 *) USBFS_1_USB__SIE_EP2_CNT0)\r
-#define USBFS_1_SIE_EP2_CNT0_REG (* (reg8 *) USBFS_1_USB__SIE_EP2_CNT0)\r
-#define USBFS_1_SIE_EP2_CNT1_PTR ( (reg8 *) USBFS_1_USB__SIE_EP2_CNT1)\r
-#define USBFS_1_SIE_EP2_CNT1_REG (* (reg8 *) USBFS_1_USB__SIE_EP2_CNT1)\r
-#define USBFS_1_SIE_EP2_CR0_PTR ( (reg8 *) USBFS_1_USB__SIE_EP2_CR0)\r
-#define USBFS_1_SIE_EP2_CR0_REG (* (reg8 *) USBFS_1_USB__SIE_EP2_CR0)\r
-\r
-#define USBFS_1_SIE_EP3_CNT0_PTR ( (reg8 *) USBFS_1_USB__SIE_EP3_CNT0)\r
-#define USBFS_1_SIE_EP3_CNT0_REG (* (reg8 *) USBFS_1_USB__SIE_EP3_CNT0)\r
-#define USBFS_1_SIE_EP3_CNT1_PTR ( (reg8 *) USBFS_1_USB__SIE_EP3_CNT1)\r
-#define USBFS_1_SIE_EP3_CNT1_REG (* (reg8 *) USBFS_1_USB__SIE_EP3_CNT1)\r
-#define USBFS_1_SIE_EP3_CR0_PTR ( (reg8 *) USBFS_1_USB__SIE_EP3_CR0)\r
-#define USBFS_1_SIE_EP3_CR0_REG (* (reg8 *) USBFS_1_USB__SIE_EP3_CR0)\r
-\r
-#define USBFS_1_SIE_EP4_CNT0_PTR ( (reg8 *) USBFS_1_USB__SIE_EP4_CNT0)\r
-#define USBFS_1_SIE_EP4_CNT0_REG (* (reg8 *) USBFS_1_USB__SIE_EP4_CNT0)\r
-#define USBFS_1_SIE_EP4_CNT1_PTR ( (reg8 *) USBFS_1_USB__SIE_EP4_CNT1)\r
-#define USBFS_1_SIE_EP4_CNT1_REG (* (reg8 *) USBFS_1_USB__SIE_EP4_CNT1)\r
-#define USBFS_1_SIE_EP4_CR0_PTR ( (reg8 *) USBFS_1_USB__SIE_EP4_CR0)\r
-#define USBFS_1_SIE_EP4_CR0_REG (* (reg8 *) USBFS_1_USB__SIE_EP4_CR0)\r
-\r
-#define USBFS_1_SIE_EP5_CNT0_PTR ( (reg8 *) USBFS_1_USB__SIE_EP5_CNT0)\r
-#define USBFS_1_SIE_EP5_CNT0_REG (* (reg8 *) USBFS_1_USB__SIE_EP5_CNT0)\r
-#define USBFS_1_SIE_EP5_CNT1_PTR ( (reg8 *) USBFS_1_USB__SIE_EP5_CNT1)\r
-#define USBFS_1_SIE_EP5_CNT1_REG (* (reg8 *) USBFS_1_USB__SIE_EP5_CNT1)\r
-#define USBFS_1_SIE_EP5_CR0_PTR ( (reg8 *) USBFS_1_USB__SIE_EP5_CR0)\r
-#define USBFS_1_SIE_EP5_CR0_REG (* (reg8 *) USBFS_1_USB__SIE_EP5_CR0)\r
-\r
-#define USBFS_1_SIE_EP6_CNT0_PTR ( (reg8 *) USBFS_1_USB__SIE_EP6_CNT0)\r
-#define USBFS_1_SIE_EP6_CNT0_REG (* (reg8 *) USBFS_1_USB__SIE_EP6_CNT0)\r
-#define USBFS_1_SIE_EP6_CNT1_PTR ( (reg8 *) USBFS_1_USB__SIE_EP6_CNT1)\r
-#define USBFS_1_SIE_EP6_CNT1_REG (* (reg8 *) USBFS_1_USB__SIE_EP6_CNT1)\r
-#define USBFS_1_SIE_EP6_CR0_PTR ( (reg8 *) USBFS_1_USB__SIE_EP6_CR0)\r
-#define USBFS_1_SIE_EP6_CR0_REG (* (reg8 *) USBFS_1_USB__SIE_EP6_CR0)\r
-\r
-#define USBFS_1_SIE_EP7_CNT0_PTR ( (reg8 *) USBFS_1_USB__SIE_EP7_CNT0)\r
-#define USBFS_1_SIE_EP7_CNT0_REG (* (reg8 *) USBFS_1_USB__SIE_EP7_CNT0)\r
-#define USBFS_1_SIE_EP7_CNT1_PTR ( (reg8 *) USBFS_1_USB__SIE_EP7_CNT1)\r
-#define USBFS_1_SIE_EP7_CNT1_REG (* (reg8 *) USBFS_1_USB__SIE_EP7_CNT1)\r
-#define USBFS_1_SIE_EP7_CR0_PTR ( (reg8 *) USBFS_1_USB__SIE_EP7_CR0)\r
-#define USBFS_1_SIE_EP7_CR0_REG (* (reg8 *) USBFS_1_USB__SIE_EP7_CR0)\r
-\r
-#define USBFS_1_SIE_EP8_CNT0_PTR ( (reg8 *) USBFS_1_USB__SIE_EP8_CNT0)\r
-#define USBFS_1_SIE_EP8_CNT0_REG (* (reg8 *) USBFS_1_USB__SIE_EP8_CNT0)\r
-#define USBFS_1_SIE_EP8_CNT1_PTR ( (reg8 *) USBFS_1_USB__SIE_EP8_CNT1)\r
-#define USBFS_1_SIE_EP8_CNT1_REG (* (reg8 *) USBFS_1_USB__SIE_EP8_CNT1)\r
-#define USBFS_1_SIE_EP8_CR0_PTR ( (reg8 *) USBFS_1_USB__SIE_EP8_CR0)\r
-#define USBFS_1_SIE_EP8_CR0_REG (* (reg8 *) USBFS_1_USB__SIE_EP8_CR0)\r
-\r
-#define USBFS_1_SOF0_PTR ( (reg8 *) USBFS_1_USB__SOF0)\r
-#define USBFS_1_SOF0_REG (* (reg8 *) USBFS_1_USB__SOF0)\r
-#define USBFS_1_SOF1_PTR ( (reg8 *) USBFS_1_USB__SOF1)\r
-#define USBFS_1_SOF1_REG (* (reg8 *) USBFS_1_USB__SOF1)\r
-\r
-#define USBFS_1_USB_CLK_EN_PTR ( (reg8 *) USBFS_1_USB__USB_CLK_EN)\r
-#define USBFS_1_USB_CLK_EN_REG (* (reg8 *) USBFS_1_USB__USB_CLK_EN)\r
-\r
-#define USBFS_1_USBIO_CR0_PTR ( (reg8 *) USBFS_1_USB__USBIO_CR0)\r
-#define USBFS_1_USBIO_CR0_REG (* (reg8 *) USBFS_1_USB__USBIO_CR0)\r
-#define USBFS_1_USBIO_CR1_PTR ( (reg8 *) USBFS_1_USB__USBIO_CR1)\r
-#define USBFS_1_USBIO_CR1_REG (* (reg8 *) USBFS_1_USB__USBIO_CR1)\r
-#if(!CY_PSOC5LP)\r
- #define USBFS_1_USBIO_CR2_PTR ( (reg8 *) USBFS_1_USB__USBIO_CR2)\r
- #define USBFS_1_USBIO_CR2_REG (* (reg8 *) USBFS_1_USB__USBIO_CR2)\r
-#endif /* End CY_PSOC5LP */\r
-\r
-#define USBFS_1_DIE_ID CYDEV_FLSHID_CUST_TABLES_BASE\r
-\r
-#define USBFS_1_PM_USB_CR0_PTR ( (reg8 *) CYREG_PM_USB_CR0)\r
-#define USBFS_1_PM_USB_CR0_REG (* (reg8 *) CYREG_PM_USB_CR0)\r
-#define USBFS_1_DYN_RECONFIG_PTR ( (reg8 *) USBFS_1_USB__DYN_RECONFIG)\r
-#define USBFS_1_DYN_RECONFIG_REG (* (reg8 *) USBFS_1_USB__DYN_RECONFIG)\r
-\r
-#define USBFS_1_DM_INP_DIS_PTR ( (reg8 *) USBFS_1_Dm__INP_DIS)\r
-#define USBFS_1_DM_INP_DIS_REG (* (reg8 *) USBFS_1_Dm__INP_DIS)\r
-#define USBFS_1_DP_INP_DIS_PTR ( (reg8 *) USBFS_1_Dp__INP_DIS)\r
-#define USBFS_1_DP_INP_DIS_REG (* (reg8 *) USBFS_1_Dp__INP_DIS)\r
-#define USBFS_1_DP_INTSTAT_PTR ( (reg8 *) USBFS_1_Dp__INTSTAT)\r
-#define USBFS_1_DP_INTSTAT_REG (* (reg8 *) USBFS_1_Dp__INTSTAT)\r
-\r
-#if (USBFS_1_MON_VBUS == 1u)\r
- #if (USBFS_1_EXTERN_VBUS == 0u)\r
- #define USBFS_1_VBUS_DR_PTR ( (reg8 *) USBFS_1_VBUS__DR)\r
- #define USBFS_1_VBUS_DR_REG (* (reg8 *) USBFS_1_VBUS__DR)\r
- #define USBFS_1_VBUS_PS_PTR ( (reg8 *) USBFS_1_VBUS__PS)\r
- #define USBFS_1_VBUS_PS_REG (* (reg8 *) USBFS_1_VBUS__PS)\r
- #define USBFS_1_VBUS_MASK USBFS_1_VBUS__MASK\r
- #else\r
- #define USBFS_1_VBUS_PS_PTR ( (reg8 *) USBFS_1_Vbus_ps_sts_sts_reg__STATUS_REG )\r
- #define USBFS_1_VBUS_MASK (0x01u)\r
- #endif /* End USBFS_1_EXTERN_VBUS == 0u */\r
-#endif /* End USBFS_1_MON_VBUS */\r
-\r
-/* Renamed Registers for backward compatibility.\r
-* Should not be used in new designs.\r
-*/\r
-#define USBFS_1_ARB_CFG USBFS_1_ARB_CFG_PTR\r
-\r
-#define USBFS_1_ARB_EP1_CFG USBFS_1_ARB_EP1_CFG_PTR\r
-#define USBFS_1_ARB_EP1_INT_EN USBFS_1_ARB_EP1_INT_EN_PTR\r
-#define USBFS_1_ARB_EP1_SR USBFS_1_ARB_EP1_SR_PTR\r
-\r
-#define USBFS_1_ARB_EP2_CFG USBFS_1_ARB_EP2_CFG_PTR\r
-#define USBFS_1_ARB_EP2_INT_EN USBFS_1_ARB_EP2_INT_EN_PTR\r
-#define USBFS_1_ARB_EP2_SR USBFS_1_ARB_EP2_SR_PTR\r
-\r
-#define USBFS_1_ARB_EP3_CFG USBFS_1_ARB_EP3_CFG_PTR\r
-#define USBFS_1_ARB_EP3_INT_EN USBFS_1_ARB_EP3_INT_EN_PTR\r
-#define USBFS_1_ARB_EP3_SR USBFS_1_ARB_EP3_SR_PTR\r
-\r
-#define USBFS_1_ARB_EP4_CFG USBFS_1_ARB_EP4_CFG_PTR\r
-#define USBFS_1_ARB_EP4_INT_EN USBFS_1_ARB_EP4_INT_EN_PTR\r
-#define USBFS_1_ARB_EP4_SR USBFS_1_ARB_EP4_SR_PTR\r
-\r
-#define USBFS_1_ARB_EP5_CFG USBFS_1_ARB_EP5_CFG_PTR\r
-#define USBFS_1_ARB_EP5_INT_EN USBFS_1_ARB_EP5_INT_EN_PTR\r
-#define USBFS_1_ARB_EP5_SR USBFS_1_ARB_EP5_SR_PTR\r
-\r
-#define USBFS_1_ARB_EP6_CFG USBFS_1_ARB_EP6_CFG_PTR\r
-#define USBFS_1_ARB_EP6_INT_EN USBFS_1_ARB_EP6_INT_EN_PTR\r
-#define USBFS_1_ARB_EP6_SR USBFS_1_ARB_EP6_SR_PTR\r
-\r
-#define USBFS_1_ARB_EP7_CFG USBFS_1_ARB_EP7_CFG_PTR\r
-#define USBFS_1_ARB_EP7_INT_EN USBFS_1_ARB_EP7_INT_EN_PTR\r
-#define USBFS_1_ARB_EP7_SR USBFS_1_ARB_EP7_SR_PTR\r
-\r
-#define USBFS_1_ARB_EP8_CFG USBFS_1_ARB_EP8_CFG_PTR\r
-#define USBFS_1_ARB_EP8_INT_EN USBFS_1_ARB_EP8_INT_EN_PTR\r
-#define USBFS_1_ARB_EP8_SR USBFS_1_ARB_EP8_SR_PTR\r
-\r
-#define USBFS_1_ARB_INT_EN USBFS_1_ARB_INT_EN_PTR\r
-#define USBFS_1_ARB_INT_SR USBFS_1_ARB_INT_SR_PTR\r
-\r
-#define USBFS_1_ARB_RW1_DR USBFS_1_ARB_RW1_DR_PTR\r
-#define USBFS_1_ARB_RW1_RA USBFS_1_ARB_RW1_RA_PTR\r
-#define USBFS_1_ARB_RW1_RA_MSB USBFS_1_ARB_RW1_RA_MSB_PTR\r
-#define USBFS_1_ARB_RW1_WA USBFS_1_ARB_RW1_WA_PTR\r
-#define USBFS_1_ARB_RW1_WA_MSB USBFS_1_ARB_RW1_WA_MSB_PTR\r
-\r
-#define USBFS_1_ARB_RW2_DR USBFS_1_ARB_RW2_DR_PTR\r
-#define USBFS_1_ARB_RW2_RA USBFS_1_ARB_RW2_RA_PTR\r
-#define USBFS_1_ARB_RW2_RA_MSB USBFS_1_ARB_RW2_RA_MSB_PTR\r
-#define USBFS_1_ARB_RW2_WA USBFS_1_ARB_RW2_WA_PTR\r
-#define USBFS_1_ARB_RW2_WA_MSB USBFS_1_ARB_RW2_WA_MSB_PTR\r
-\r
-#define USBFS_1_ARB_RW3_DR USBFS_1_ARB_RW3_DR_PTR\r
-#define USBFS_1_ARB_RW3_RA USBFS_1_ARB_RW3_RA_PTR\r
-#define USBFS_1_ARB_RW3_RA_MSB USBFS_1_ARB_RW3_RA_MSB_PTR\r
-#define USBFS_1_ARB_RW3_WA USBFS_1_ARB_RW3_WA_PTR\r
-#define USBFS_1_ARB_RW3_WA_MSB USBFS_1_ARB_RW3_WA_MSB_PTR\r
-\r
-#define USBFS_1_ARB_RW4_DR USBFS_1_ARB_RW4_DR_PTR\r
-#define USBFS_1_ARB_RW4_RA USBFS_1_ARB_RW4_RA_PTR\r
-#define USBFS_1_ARB_RW4_RA_MSB USBFS_1_ARB_RW4_RA_MSB_PTR\r
-#define USBFS_1_ARB_RW4_WA USBFS_1_ARB_RW4_WA_PTR\r
-#define USBFS_1_ARB_RW4_WA_MSB USBFS_1_ARB_RW4_WA_MSB_PTR\r
-\r
-#define USBFS_1_ARB_RW5_DR USBFS_1_ARB_RW5_DR_PTR\r
-#define USBFS_1_ARB_RW5_RA USBFS_1_ARB_RW5_RA_PTR\r
-#define USBFS_1_ARB_RW5_RA_MSB USBFS_1_ARB_RW5_RA_MSB_PTR\r
-#define USBFS_1_ARB_RW5_WA USBFS_1_ARB_RW5_WA_PTR\r
-#define USBFS_1_ARB_RW5_WA_MSB USBFS_1_ARB_RW5_WA_MSB_PTR\r
-\r
-#define USBFS_1_ARB_RW6_DR USBFS_1_ARB_RW6_DR_PTR\r
-#define USBFS_1_ARB_RW6_RA USBFS_1_ARB_RW6_RA_PTR\r
-#define USBFS_1_ARB_RW6_RA_MSB USBFS_1_ARB_RW6_RA_MSB_PTR\r
-#define USBFS_1_ARB_RW6_WA USBFS_1_ARB_RW6_WA_PTR\r
-#define USBFS_1_ARB_RW6_WA_MSB USBFS_1_ARB_RW6_WA_MSB_PTR\r
-\r
-#define USBFS_1_ARB_RW7_DR USBFS_1_ARB_RW7_DR_PTR\r
-#define USBFS_1_ARB_RW7_RA USBFS_1_ARB_RW7_RA_PTR\r
-#define USBFS_1_ARB_RW7_RA_MSB USBFS_1_ARB_RW7_RA_MSB_PTR\r
-#define USBFS_1_ARB_RW7_WA USBFS_1_ARB_RW7_WA_PTR\r
-#define USBFS_1_ARB_RW7_WA_MSB USBFS_1_ARB_RW7_WA_MSB_PTR\r
-\r
-#define USBFS_1_ARB_RW8_DR USBFS_1_ARB_RW8_DR_PTR\r
-#define USBFS_1_ARB_RW8_RA USBFS_1_ARB_RW8_RA_PTR\r
-#define USBFS_1_ARB_RW8_RA_MSB USBFS_1_ARB_RW8_RA_MSB_PTR\r
-#define USBFS_1_ARB_RW8_WA USBFS_1_ARB_RW8_WA_PTR\r
-#define USBFS_1_ARB_RW8_WA_MSB USBFS_1_ARB_RW8_WA_MSB_PTR\r
-\r
-#define USBFS_1_BUF_SIZE USBFS_1_BUF_SIZE_PTR\r
-#define USBFS_1_BUS_RST_CNT USBFS_1_BUS_RST_CNT_PTR\r
-#define USBFS_1_CR0 USBFS_1_CR0_PTR\r
-#define USBFS_1_CR1 USBFS_1_CR1_PTR\r
-#define USBFS_1_CWA USBFS_1_CWA_PTR\r
-#define USBFS_1_CWA_MSB USBFS_1_CWA_MSB_PTR\r
-\r
-#define USBFS_1_DMA_THRES USBFS_1_DMA_THRES_PTR\r
-#define USBFS_1_DMA_THRES_MSB USBFS_1_DMA_THRES_MSB_PTR\r
-\r
-#define USBFS_1_EP_ACTIVE USBFS_1_EP_ACTIVE_PTR\r
-#define USBFS_1_EP_TYPE USBFS_1_EP_TYPE_PTR\r
-\r
-#define USBFS_1_EP0_CNT USBFS_1_EP0_CNT_PTR\r
-#define USBFS_1_EP0_CR USBFS_1_EP0_CR_PTR\r
-#define USBFS_1_EP0_DR0 USBFS_1_EP0_DR0_PTR\r
-#define USBFS_1_EP0_DR1 USBFS_1_EP0_DR1_PTR\r
-#define USBFS_1_EP0_DR2 USBFS_1_EP0_DR2_PTR\r
-#define USBFS_1_EP0_DR3 USBFS_1_EP0_DR3_PTR\r
-#define USBFS_1_EP0_DR4 USBFS_1_EP0_DR4_PTR\r
-#define USBFS_1_EP0_DR5 USBFS_1_EP0_DR5_PTR\r
-#define USBFS_1_EP0_DR6 USBFS_1_EP0_DR6_PTR\r
-#define USBFS_1_EP0_DR7 USBFS_1_EP0_DR7_PTR\r
-\r
-#define USBFS_1_OSCLK_DR0 USBFS_1_OSCLK_DR0_PTR\r
-#define USBFS_1_OSCLK_DR1 USBFS_1_OSCLK_DR1_PTR\r
-\r
-#define USBFS_1_PM_ACT_CFG USBFS_1_PM_ACT_CFG_PTR\r
-#define USBFS_1_PM_STBY_CFG USBFS_1_PM_STBY_CFG_PTR\r
-\r
-#define USBFS_1_SIE_EP_INT_EN USBFS_1_SIE_EP_INT_EN_PTR\r
-#define USBFS_1_SIE_EP_INT_SR USBFS_1_SIE_EP_INT_SR_PTR\r
-\r
-#define USBFS_1_SIE_EP1_CNT0 USBFS_1_SIE_EP1_CNT0_PTR\r
-#define USBFS_1_SIE_EP1_CNT1 USBFS_1_SIE_EP1_CNT1_PTR\r
-#define USBFS_1_SIE_EP1_CR0 USBFS_1_SIE_EP1_CR0_PTR\r
-\r
-#define USBFS_1_SIE_EP2_CNT0 USBFS_1_SIE_EP2_CNT0_PTR\r
-#define USBFS_1_SIE_EP2_CNT1 USBFS_1_SIE_EP2_CNT1_PTR\r
-#define USBFS_1_SIE_EP2_CR0 USBFS_1_SIE_EP2_CR0_PTR\r
-\r
-#define USBFS_1_SIE_EP3_CNT0 USBFS_1_SIE_EP3_CNT0_PTR\r
-#define USBFS_1_SIE_EP3_CNT1 USBFS_1_SIE_EP3_CNT1_PTR\r
-#define USBFS_1_SIE_EP3_CR0 USBFS_1_SIE_EP3_CR0_PTR\r
-\r
-#define USBFS_1_SIE_EP4_CNT0 USBFS_1_SIE_EP4_CNT0_PTR\r
-#define USBFS_1_SIE_EP4_CNT1 USBFS_1_SIE_EP4_CNT1_PTR\r
-#define USBFS_1_SIE_EP4_CR0 USBFS_1_SIE_EP4_CR0_PTR\r
-\r
-#define USBFS_1_SIE_EP5_CNT0 USBFS_1_SIE_EP5_CNT0_PTR\r
-#define USBFS_1_SIE_EP5_CNT1 USBFS_1_SIE_EP5_CNT1_PTR\r
-#define USBFS_1_SIE_EP5_CR0 USBFS_1_SIE_EP5_CR0_PTR\r
-\r
-#define USBFS_1_SIE_EP6_CNT0 USBFS_1_SIE_EP6_CNT0_PTR\r
-#define USBFS_1_SIE_EP6_CNT1 USBFS_1_SIE_EP6_CNT1_PTR\r
-#define USBFS_1_SIE_EP6_CR0 USBFS_1_SIE_EP6_CR0_PTR\r
-\r
-#define USBFS_1_SIE_EP7_CNT0 USBFS_1_SIE_EP7_CNT0_PTR\r
-#define USBFS_1_SIE_EP7_CNT1 USBFS_1_SIE_EP7_CNT1_PTR\r
-#define USBFS_1_SIE_EP7_CR0 USBFS_1_SIE_EP7_CR0_PTR\r
-\r
-#define USBFS_1_SIE_EP8_CNT0 USBFS_1_SIE_EP8_CNT0_PTR\r
-#define USBFS_1_SIE_EP8_CNT1 USBFS_1_SIE_EP8_CNT1_PTR\r
-#define USBFS_1_SIE_EP8_CR0 USBFS_1_SIE_EP8_CR0_PTR\r
-\r
-#define USBFS_1_SOF0 USBFS_1_SOF0_PTR\r
-#define USBFS_1_SOF1 USBFS_1_SOF1_PTR\r
-\r
-#define USBFS_1_USB_CLK_EN USBFS_1_USB_CLK_EN_PTR\r
-\r
-#define USBFS_1_USBIO_CR0 USBFS_1_USBIO_CR0_PTR\r
-#define USBFS_1_USBIO_CR1 USBFS_1_USBIO_CR1_PTR\r
-#define USBFS_1_USBIO_CR2 USBFS_1_USBIO_CR2_PTR\r
-\r
-#define USBFS_1_USB_MEM ((reg8 *) CYDEV_USB_MEM_BASE)\r
-\r
-#if(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_LEOPARD)\r
- /* PSoC3 interrupt registers*/\r
- #define USBFS_1_USB_ISR_PRIOR ((reg8 *) CYDEV_INTC_PRIOR0)\r
- #define USBFS_1_USB_ISR_SET_EN ((reg8 *) CYDEV_INTC_SET_EN0)\r
- #define USBFS_1_USB_ISR_CLR_EN ((reg8 *) CYDEV_INTC_CLR_EN0)\r
- #define USBFS_1_USB_ISR_VECT ((cyisraddress *) CYDEV_INTC_VECT_MBASE)\r
-#elif(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_PANTHER)\r
- /* PSoC5 interrupt registers*/\r
- #define USBFS_1_USB_ISR_PRIOR ((reg8 *) CYDEV_NVIC_PRI_0)\r
- #define USBFS_1_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0)\r
- #define USBFS_1_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0)\r
- #define USBFS_1_USB_ISR_VECT ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET)\r
-#endif /* End CYDEV_CHIP_DIE_EXPECT */\r
-\r
-\r
-/***************************************\r
-* Interrupt vectors, masks and priorities\r
-***************************************/\r
-\r
-#define USBFS_1_BUS_RESET_PRIOR USBFS_1_bus_reset__INTC_PRIOR_NUM\r
-#define USBFS_1_BUS_RESET_MASK USBFS_1_bus_reset__INTC_MASK\r
-#define USBFS_1_BUS_RESET_VECT_NUM USBFS_1_bus_reset__INTC_NUMBER\r
-\r
-#define USBFS_1_SOF_PRIOR USBFS_1_sof_int__INTC_PRIOR_NUM\r
-#define USBFS_1_SOF_MASK USBFS_1_sof_int__INTC_MASK\r
-#define USBFS_1_SOF_VECT_NUM USBFS_1_sof_int__INTC_NUMBER\r
-\r
-#define USBFS_1_EP_0_PRIOR USBFS_1_ep_0__INTC_PRIOR_NUM\r
-#define USBFS_1_EP_0_MASK USBFS_1_ep_0__INTC_MASK\r
-#define USBFS_1_EP_0_VECT_NUM USBFS_1_ep_0__INTC_NUMBER\r
-\r
-#define USBFS_1_EP_1_PRIOR USBFS_1_ep_1__INTC_PRIOR_NUM\r
-#define USBFS_1_EP_1_MASK USBFS_1_ep_1__INTC_MASK\r
-#define USBFS_1_EP_1_VECT_NUM USBFS_1_ep_1__INTC_NUMBER\r
-\r
-#define USBFS_1_EP_2_PRIOR USBFS_1_ep_2__INTC_PRIOR_NUM\r
-#define USBFS_1_EP_2_MASK USBFS_1_ep_2__INTC_MASK\r
-#define USBFS_1_EP_2_VECT_NUM USBFS_1_ep_2__INTC_NUMBER\r
-\r
-#define USBFS_1_EP_3_PRIOR USBFS_1_ep_3__INTC_PRIOR_NUM\r
-#define USBFS_1_EP_3_MASK USBFS_1_ep_3__INTC_MASK\r
-#define USBFS_1_EP_3_VECT_NUM USBFS_1_ep_3__INTC_NUMBER\r
-\r
-#define USBFS_1_EP_4_PRIOR USBFS_1_ep_4__INTC_PRIOR_NUM\r
-#define USBFS_1_EP_4_MASK USBFS_1_ep_4__INTC_MASK\r
-#define USBFS_1_EP_4_VECT_NUM USBFS_1_ep_4__INTC_NUMBER\r
-\r
-#define USBFS_1_EP_5_PRIOR USBFS_1_ep_5__INTC_PRIOR_NUM\r
-#define USBFS_1_EP_5_MASK USBFS_1_ep_5__INTC_MASK\r
-#define USBFS_1_EP_5_VECT_NUM USBFS_1_ep_5__INTC_NUMBER\r
-\r
-#define USBFS_1_EP_6_PRIOR USBFS_1_ep_6__INTC_PRIOR_NUM\r
-#define USBFS_1_EP_6_MASK USBFS_1_ep_6__INTC_MASK\r
-#define USBFS_1_EP_6_VECT_NUM USBFS_1_ep_6__INTC_NUMBER\r
-\r
-#define USBFS_1_EP_7_PRIOR USBFS_1_ep_7__INTC_PRIOR_NUM\r
-#define USBFS_1_EP_7_MASK USBFS_1_ep_7__INTC_MASK\r
-#define USBFS_1_EP_7_VECT_NUM USBFS_1_ep_7__INTC_NUMBER\r
-\r
-#define USBFS_1_EP_8_PRIOR USBFS_1_ep_8__INTC_PRIOR_NUM\r
-#define USBFS_1_EP_8_MASK USBFS_1_ep_8__INTC_MASK\r
-#define USBFS_1_EP_8_VECT_NUM USBFS_1_ep_8__INTC_NUMBER\r
-\r
-#define USBFS_1_DP_INTC_PRIOR USBFS_1_dp_int__INTC_PRIOR_NUM\r
-#define USBFS_1_DP_INTC_MASK USBFS_1_dp_int__INTC_MASK\r
-#define USBFS_1_DP_INTC_VECT_NUM USBFS_1_dp_int__INTC_NUMBER\r
-\r
-/* ARB ISR should have higher priority from EP_X ISR, therefore it is defined to highest (0) */\r
-#define USBFS_1_ARB_PRIOR (0u)\r
-#define USBFS_1_ARB_MASK USBFS_1_arb_int__INTC_MASK\r
-#define USBFS_1_ARB_VECT_NUM USBFS_1_arb_int__INTC_NUMBER\r
-\r
-/***************************************\r
- * Endpoint 0 offsets (Table 9-2)\r
- **************************************/\r
-\r
-#define USBFS_1_bmRequestType USBFS_1_EP0_DR0_PTR\r
-#define USBFS_1_bRequest USBFS_1_EP0_DR1_PTR\r
-#define USBFS_1_wValue USBFS_1_EP0_DR2_PTR\r
-#define USBFS_1_wValueHi USBFS_1_EP0_DR3_PTR\r
-#define USBFS_1_wValueLo USBFS_1_EP0_DR2_PTR\r
-#define USBFS_1_wIndex USBFS_1_EP0_DR4_PTR\r
-#define USBFS_1_wIndexHi USBFS_1_EP0_DR5_PTR\r
-#define USBFS_1_wIndexLo USBFS_1_EP0_DR4_PTR\r
-#define USBFS_1_length USBFS_1_EP0_DR6_PTR\r
-#define USBFS_1_lengthHi USBFS_1_EP0_DR7_PTR\r
-#define USBFS_1_lengthLo USBFS_1_EP0_DR6_PTR\r
-\r
-\r
-/***************************************\r
-* Register Constants\r
-***************************************/\r
-#define USBFS_1_VDDD_MV CYDEV_VDDD_MV\r
-#define USBFS_1_3500MV (3500u)\r
-\r
-#define USBFS_1_CR1_REG_ENABLE (0x01u)\r
-#define USBFS_1_CR1_ENABLE_LOCK (0x02u)\r
-#define USBFS_1_CR1_BUS_ACTIVITY_SHIFT (0x02u)\r
-#define USBFS_1_CR1_BUS_ACTIVITY ((uint8)(0x01u << USBFS_1_CR1_BUS_ACTIVITY_SHIFT))\r
-#define USBFS_1_CR1_TRIM_MSB_EN (0x08u)\r
-\r
-#define USBFS_1_EP0_CNT_DATA_TOGGLE (0x80u)\r
-#define USBFS_1_EPX_CNT_DATA_TOGGLE (0x80u)\r
-#define USBFS_1_EPX_CNT0_MASK (0x0Fu)\r
-#define USBFS_1_EPX_CNTX_MSB_MASK (0x07u)\r
-#define USBFS_1_EPX_CNTX_ADDR_SHIFT (0x04u)\r
-#define USBFS_1_EPX_CNTX_ADDR_OFFSET (0x10u)\r
-#define USBFS_1_EPX_CNTX_CRC_COUNT (0x02u)\r
-#define USBFS_1_EPX_DATA_BUF_MAX (512u)\r
-\r
-#define USBFS_1_CR0_ENABLE (0x80u)\r
-\r
-/* A 100 KHz clock is used for BUS reset count. Recommended is to count 10 pulses */\r
-#define USBFS_1_BUS_RST_COUNT (0x0au)\r
-\r
-#define USBFS_1_USBIO_CR1_IOMODE (0x20u)\r
-#define USBFS_1_USBIO_CR1_USBPUEN (0x04u)\r
-#define USBFS_1_USBIO_CR1_DP0 (0x02u)\r
-#define USBFS_1_USBIO_CR1_DM0 (0x01u)\r
-\r
-#define USBFS_1_USBIO_CR0_TEN (0x80u)\r
-#define USBFS_1_USBIO_CR0_TSE0 (0x40u)\r
-#define USBFS_1_USBIO_CR0_TD (0x20u)\r
-#define USBFS_1_USBIO_CR0_RD (0x01u)\r
-\r
-#define USBFS_1_FASTCLK_IMO_CR_USBCLK_ON (0x40u)\r
-#define USBFS_1_FASTCLK_IMO_CR_XCLKEN (0x20u)\r
-#define USBFS_1_FASTCLK_IMO_CR_FX2ON (0x10u)\r
-\r
-#define USBFS_1_ARB_EPX_CFG_RESET (0x08u)\r
-#define USBFS_1_ARB_EPX_CFG_CRC_BYPASS (0x04u)\r
-#define USBFS_1_ARB_EPX_CFG_DMA_REQ (0x02u)\r
-#define USBFS_1_ARB_EPX_CFG_IN_DATA_RDY (0x01u)\r
-\r
-#define USBFS_1_ARB_EPX_SR_IN_BUF_FULL (0x01u)\r
-#define USBFS_1_ARB_EPX_SR_DMA_GNT (0x02u)\r
-#define USBFS_1_ARB_EPX_SR_BUF_OVER (0x04u)\r
-#define USBFS_1_ARB_EPX_SR_BUF_UNDER (0x08u)\r
-\r
-#define USBFS_1_ARB_CFG_AUTO_MEM (0x10u)\r
-#define USBFS_1_ARB_CFG_MANUAL_DMA (0x20u)\r
-#define USBFS_1_ARB_CFG_AUTO_DMA (0x40u)\r
-#define USBFS_1_ARB_CFG_CFG_CPM (0x80u)\r
-\r
-#if(USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO)\r
- #define USBFS_1_ARB_EPX_INT_MASK (0x1Du)\r
-#else\r
- #define USBFS_1_ARB_EPX_INT_MASK (0x1Fu)\r
-#endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO */\r
-#define USBFS_1_ARB_INT_MASK (uint8)((USBFS_1_DMA1_REMOVE ^ 1u) | \\r
- (uint8)((USBFS_1_DMA2_REMOVE ^ 1u) << 1u) | \\r
- (uint8)((USBFS_1_DMA3_REMOVE ^ 1u) << 2u) | \\r
- (uint8)((USBFS_1_DMA4_REMOVE ^ 1u) << 3u) | \\r
- (uint8)((USBFS_1_DMA5_REMOVE ^ 1u) << 4u) | \\r
- (uint8)((USBFS_1_DMA6_REMOVE ^ 1u) << 5u) | \\r
- (uint8)((USBFS_1_DMA7_REMOVE ^ 1u) << 6u) | \\r
- (uint8)((USBFS_1_DMA8_REMOVE ^ 1u) << 7u) )\r
-\r
-#define USBFS_1_SIE_EP_INT_EP1_MASK (0x01u)\r
-#define USBFS_1_SIE_EP_INT_EP2_MASK (0x02u)\r
-#define USBFS_1_SIE_EP_INT_EP3_MASK (0x04u)\r
-#define USBFS_1_SIE_EP_INT_EP4_MASK (0x08u)\r
-#define USBFS_1_SIE_EP_INT_EP5_MASK (0x10u)\r
-#define USBFS_1_SIE_EP_INT_EP6_MASK (0x20u)\r
-#define USBFS_1_SIE_EP_INT_EP7_MASK (0x40u)\r
-#define USBFS_1_SIE_EP_INT_EP8_MASK (0x80u)\r
-\r
-#define USBFS_1_PM_ACT_EN_FSUSB USBFS_1_USB__PM_ACT_MSK\r
-#define USBFS_1_PM_STBY_EN_FSUSB USBFS_1_USB__PM_STBY_MSK\r
-#define USBFS_1_PM_AVAIL_EN_FSUSBIO (0x10u)\r
-\r
-#define USBFS_1_PM_USB_CR0_REF_EN (0x01u)\r
-#define USBFS_1_PM_USB_CR0_PD_N (0x02u)\r
-#define USBFS_1_PM_USB_CR0_PD_PULLUP_N (0x04u)\r
-\r
-#define USBFS_1_USB_CLK_ENABLE (0x01u)\r
-\r
-#define USBFS_1_DM_MASK USBFS_1_Dm__0__MASK\r
-#define USBFS_1_DP_MASK USBFS_1_Dp__0__MASK\r
-\r
-#define USBFS_1_DYN_RECONFIG_ENABLE (0x01u)\r
-#define USBFS_1_DYN_RECONFIG_EP_SHIFT (0x01u)\r
-#define USBFS_1_DYN_RECONFIG_RDY_STS (0x10u)\r
-\r
-\r
-#endif /* End CY_USBFS_USBFS_1_H */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_Dm.c \r
-* Version 1.90\r
-*\r
-* Description:\r
-* This file contains API to enable firmware control of a Pins component.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "cytypes.h"\r
-#include "USBFS_1_Dm.h"\r
-\r
-/* APIs are not generated for P15[7:6] on PSoC 5 */\r
-#if !(CY_PSOC5A &&\\r
- USBFS_1_Dm__PORT == 15 && ((USBFS_1_Dm__MASK & 0xC0) != 0))\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_Dm_Write\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
-*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
-*\r
-* Return: \r
-* None\r
-* \r
-*******************************************************************************/\r
-void USBFS_1_Dm_Write(uint8 value) \r
-{\r
- uint8 staticBits = (USBFS_1_Dm_DR & (uint8)(~USBFS_1_Dm_MASK));\r
- USBFS_1_Dm_DR = staticBits | ((uint8)(value << USBFS_1_Dm_SHIFT) & USBFS_1_Dm_MASK);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_Dm_SetDriveMode\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
-* \r
-* Parameters: \r
-* mode: Change the pins to this drive mode.\r
-*\r
-* Return: \r
-* None\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_Dm_SetDriveMode(uint8 mode) \r
-{\r
- CyPins_SetPinDriveMode(USBFS_1_Dm_0, mode);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_Dm_Read\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
-*\r
-* Parameters: \r
-* None\r
-*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro USBFS_1_Dm_ReadPS calls this function. \r
-* \r
-*******************************************************************************/\r
-uint8 USBFS_1_Dm_Read(void) \r
-{\r
- return (USBFS_1_Dm_PS & USBFS_1_Dm_MASK) >> USBFS_1_Dm_SHIFT;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_Dm_ReadDataReg\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
-*\r
-* Parameters: \r
-* None \r
-*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
-*******************************************************************************/\r
-uint8 USBFS_1_Dm_ReadDataReg(void) \r
-{\r
- return (USBFS_1_Dm_DR & USBFS_1_Dm_MASK) >> USBFS_1_Dm_SHIFT;\r
-}\r
-\r
-\r
-/* If Interrupts Are Enabled for this Pins component */ \r
-#if defined(USBFS_1_Dm_INTSTAT) \r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_Dm_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
- *\r
- * Parameters: \r
- * None \r
- *\r
- * Return: \r
- * Returns the value of the interrupt status register\r
- * \r
- *******************************************************************************/\r
- uint8 USBFS_1_Dm_ClearInterrupt(void) \r
- {\r
- return (USBFS_1_Dm_INTSTAT & USBFS_1_Dm_MASK) >> USBFS_1_Dm_SHIFT;\r
- }\r
-\r
-#endif /* If Interrupts Are Enabled for this Pins component */ \r
-\r
-#endif /* CY_PSOC5A... */\r
-\r
- \r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_Dm.h \r
-* Version 1.90\r
-*\r
-* Description:\r
-* This file containts Control Register function prototypes and register defines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_PINS_USBFS_1_Dm_H) /* Pins USBFS_1_Dm_H */\r
-#define CY_PINS_USBFS_1_Dm_H\r
-\r
-#include "cytypes.h"\r
-#include "cyfitter.h"\r
-#include "cypins.h"\r
-#include "USBFS_1_Dm_aliases.h"\r
-\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
-/* APIs are not generated for P15[7:6] */\r
-#if !(CY_PSOC5A &&\\r
- USBFS_1_Dm__PORT == 15 && ((USBFS_1_Dm__MASK & 0xC0) != 0))\r
-\r
-\r
-/***************************************\r
-* Function Prototypes \r
-***************************************/ \r
-\r
-void USBFS_1_Dm_Write(uint8 value) ;\r
-void USBFS_1_Dm_SetDriveMode(uint8 mode) ;\r
-uint8 USBFS_1_Dm_ReadDataReg(void) ;\r
-uint8 USBFS_1_Dm_Read(void) ;\r
-uint8 USBFS_1_Dm_ClearInterrupt(void) ;\r
-\r
-\r
-/***************************************\r
-* API Constants \r
-***************************************/\r
-\r
-/* Drive Modes */\r
-#define USBFS_1_Dm_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define USBFS_1_Dm_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define USBFS_1_Dm_DM_RES_UP PIN_DM_RES_UP\r
-#define USBFS_1_Dm_DM_RES_DWN PIN_DM_RES_DWN\r
-#define USBFS_1_Dm_DM_OD_LO PIN_DM_OD_LO\r
-#define USBFS_1_Dm_DM_OD_HI PIN_DM_OD_HI\r
-#define USBFS_1_Dm_DM_STRONG PIN_DM_STRONG\r
-#define USBFS_1_Dm_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
-/* Digital Port Constants */\r
-#define USBFS_1_Dm_MASK USBFS_1_Dm__MASK\r
-#define USBFS_1_Dm_SHIFT USBFS_1_Dm__SHIFT\r
-#define USBFS_1_Dm_WIDTH 1u\r
-\r
-\r
-/***************************************\r
-* Registers \r
-***************************************/\r
-\r
-/* Main Port Registers */\r
-/* Pin State */\r
-#define USBFS_1_Dm_PS (* (reg8 *) USBFS_1_Dm__PS)\r
-/* Data Register */\r
-#define USBFS_1_Dm_DR (* (reg8 *) USBFS_1_Dm__DR)\r
-/* Port Number */\r
-#define USBFS_1_Dm_PRT_NUM (* (reg8 *) USBFS_1_Dm__PRT) \r
-/* Connect to Analog Globals */ \r
-#define USBFS_1_Dm_AG (* (reg8 *) USBFS_1_Dm__AG) \r
-/* Analog MUX bux enable */\r
-#define USBFS_1_Dm_AMUX (* (reg8 *) USBFS_1_Dm__AMUX) \r
-/* Bidirectional Enable */ \r
-#define USBFS_1_Dm_BIE (* (reg8 *) USBFS_1_Dm__BIE)\r
-/* Bit-mask for Aliased Register Access */\r
-#define USBFS_1_Dm_BIT_MASK (* (reg8 *) USBFS_1_Dm__BIT_MASK)\r
-/* Bypass Enable */\r
-#define USBFS_1_Dm_BYP (* (reg8 *) USBFS_1_Dm__BYP)\r
-/* Port wide control signals */ \r
-#define USBFS_1_Dm_CTL (* (reg8 *) USBFS_1_Dm__CTL)\r
-/* Drive Modes */\r
-#define USBFS_1_Dm_DM0 (* (reg8 *) USBFS_1_Dm__DM0) \r
-#define USBFS_1_Dm_DM1 (* (reg8 *) USBFS_1_Dm__DM1)\r
-#define USBFS_1_Dm_DM2 (* (reg8 *) USBFS_1_Dm__DM2) \r
-/* Input Buffer Disable Override */\r
-#define USBFS_1_Dm_INP_DIS (* (reg8 *) USBFS_1_Dm__INP_DIS)\r
-/* LCD Common or Segment Drive */\r
-#define USBFS_1_Dm_LCD_COM_SEG (* (reg8 *) USBFS_1_Dm__LCD_COM_SEG)\r
-/* Enable Segment LCD */\r
-#define USBFS_1_Dm_LCD_EN (* (reg8 *) USBFS_1_Dm__LCD_EN)\r
-/* Slew Rate Control */\r
-#define USBFS_1_Dm_SLW (* (reg8 *) USBFS_1_Dm__SLW)\r
-\r
-/* DSI Port Registers */\r
-/* Global DSI Select Register */\r
-#define USBFS_1_Dm_PRTDSI__CAPS_SEL (* (reg8 *) USBFS_1_Dm__PRTDSI__CAPS_SEL) \r
-/* Double Sync Enable */\r
-#define USBFS_1_Dm_PRTDSI__DBL_SYNC_IN (* (reg8 *) USBFS_1_Dm__PRTDSI__DBL_SYNC_IN) \r
-/* Output Enable Select Drive Strength */\r
-#define USBFS_1_Dm_PRTDSI__OE_SEL0 (* (reg8 *) USBFS_1_Dm__PRTDSI__OE_SEL0) \r
-#define USBFS_1_Dm_PRTDSI__OE_SEL1 (* (reg8 *) USBFS_1_Dm__PRTDSI__OE_SEL1) \r
-/* Port Pin Output Select Registers */\r
-#define USBFS_1_Dm_PRTDSI__OUT_SEL0 (* (reg8 *) USBFS_1_Dm__PRTDSI__OUT_SEL0) \r
-#define USBFS_1_Dm_PRTDSI__OUT_SEL1 (* (reg8 *) USBFS_1_Dm__PRTDSI__OUT_SEL1) \r
-/* Sync Output Enable Registers */\r
-#define USBFS_1_Dm_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_1_Dm__PRTDSI__SYNC_OUT) \r
-\r
-\r
-#if defined(USBFS_1_Dm__INTSTAT) /* Interrupt Registers */\r
-\r
- #define USBFS_1_Dm_INTSTAT (* (reg8 *) USBFS_1_Dm__INTSTAT)\r
- #define USBFS_1_Dm_SNAP (* (reg8 *) USBFS_1_Dm__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
-\r
-#endif /* CY_PSOC5A... */\r
-\r
-#endif /* CY_PINS_USBFS_1_Dm_H */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_Dm.h \r
-* Version 1.90\r
-*\r
-* Description:\r
-* This file containts Control Register function prototypes and register defines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_PINS_USBFS_1_Dm_ALIASES_H) /* Pins USBFS_1_Dm_ALIASES_H */\r
-#define CY_PINS_USBFS_1_Dm_ALIASES_H\r
-\r
-#include "cytypes.h"\r
-#include "cyfitter.h"\r
-\r
-\r
-\r
-/***************************************\r
-* Constants \r
-***************************************/\r
-#define USBFS_1_Dm_0 USBFS_1_Dm__0__PC\r
-\r
-#endif /* End Pins USBFS_1_Dm_ALIASES_H */\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_Dp.c \r
-* Version 1.90\r
-*\r
-* Description:\r
-* This file contains API to enable firmware control of a Pins component.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "cytypes.h"\r
-#include "USBFS_1_Dp.h"\r
-\r
-/* APIs are not generated for P15[7:6] on PSoC 5 */\r
-#if !(CY_PSOC5A &&\\r
- USBFS_1_Dp__PORT == 15 && ((USBFS_1_Dp__MASK & 0xC0) != 0))\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_Dp_Write\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
-*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
-*\r
-* Return: \r
-* None\r
-* \r
-*******************************************************************************/\r
-void USBFS_1_Dp_Write(uint8 value) \r
-{\r
- uint8 staticBits = (USBFS_1_Dp_DR & (uint8)(~USBFS_1_Dp_MASK));\r
- USBFS_1_Dp_DR = staticBits | ((uint8)(value << USBFS_1_Dp_SHIFT) & USBFS_1_Dp_MASK);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_Dp_SetDriveMode\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
-* \r
-* Parameters: \r
-* mode: Change the pins to this drive mode.\r
-*\r
-* Return: \r
-* None\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_Dp_SetDriveMode(uint8 mode) \r
-{\r
- CyPins_SetPinDriveMode(USBFS_1_Dp_0, mode);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_Dp_Read\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
-*\r
-* Parameters: \r
-* None\r
-*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro USBFS_1_Dp_ReadPS calls this function. \r
-* \r
-*******************************************************************************/\r
-uint8 USBFS_1_Dp_Read(void) \r
-{\r
- return (USBFS_1_Dp_PS & USBFS_1_Dp_MASK) >> USBFS_1_Dp_SHIFT;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_Dp_ReadDataReg\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
-*\r
-* Parameters: \r
-* None \r
-*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
-*******************************************************************************/\r
-uint8 USBFS_1_Dp_ReadDataReg(void) \r
-{\r
- return (USBFS_1_Dp_DR & USBFS_1_Dp_MASK) >> USBFS_1_Dp_SHIFT;\r
-}\r
-\r
-\r
-/* If Interrupts Are Enabled for this Pins component */ \r
-#if defined(USBFS_1_Dp_INTSTAT) \r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_Dp_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
- *\r
- * Parameters: \r
- * None \r
- *\r
- * Return: \r
- * Returns the value of the interrupt status register\r
- * \r
- *******************************************************************************/\r
- uint8 USBFS_1_Dp_ClearInterrupt(void) \r
- {\r
- return (USBFS_1_Dp_INTSTAT & USBFS_1_Dp_MASK) >> USBFS_1_Dp_SHIFT;\r
- }\r
-\r
-#endif /* If Interrupts Are Enabled for this Pins component */ \r
-\r
-#endif /* CY_PSOC5A... */\r
-\r
- \r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_Dp.h \r
-* Version 1.90\r
-*\r
-* Description:\r
-* This file containts Control Register function prototypes and register defines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_PINS_USBFS_1_Dp_H) /* Pins USBFS_1_Dp_H */\r
-#define CY_PINS_USBFS_1_Dp_H\r
-\r
-#include "cytypes.h"\r
-#include "cyfitter.h"\r
-#include "cypins.h"\r
-#include "USBFS_1_Dp_aliases.h"\r
-\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
-/* APIs are not generated for P15[7:6] */\r
-#if !(CY_PSOC5A &&\\r
- USBFS_1_Dp__PORT == 15 && ((USBFS_1_Dp__MASK & 0xC0) != 0))\r
-\r
-\r
-/***************************************\r
-* Function Prototypes \r
-***************************************/ \r
-\r
-void USBFS_1_Dp_Write(uint8 value) ;\r
-void USBFS_1_Dp_SetDriveMode(uint8 mode) ;\r
-uint8 USBFS_1_Dp_ReadDataReg(void) ;\r
-uint8 USBFS_1_Dp_Read(void) ;\r
-uint8 USBFS_1_Dp_ClearInterrupt(void) ;\r
-\r
-\r
-/***************************************\r
-* API Constants \r
-***************************************/\r
-\r
-/* Drive Modes */\r
-#define USBFS_1_Dp_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define USBFS_1_Dp_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define USBFS_1_Dp_DM_RES_UP PIN_DM_RES_UP\r
-#define USBFS_1_Dp_DM_RES_DWN PIN_DM_RES_DWN\r
-#define USBFS_1_Dp_DM_OD_LO PIN_DM_OD_LO\r
-#define USBFS_1_Dp_DM_OD_HI PIN_DM_OD_HI\r
-#define USBFS_1_Dp_DM_STRONG PIN_DM_STRONG\r
-#define USBFS_1_Dp_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
-/* Digital Port Constants */\r
-#define USBFS_1_Dp_MASK USBFS_1_Dp__MASK\r
-#define USBFS_1_Dp_SHIFT USBFS_1_Dp__SHIFT\r
-#define USBFS_1_Dp_WIDTH 1u\r
-\r
-\r
-/***************************************\r
-* Registers \r
-***************************************/\r
-\r
-/* Main Port Registers */\r
-/* Pin State */\r
-#define USBFS_1_Dp_PS (* (reg8 *) USBFS_1_Dp__PS)\r
-/* Data Register */\r
-#define USBFS_1_Dp_DR (* (reg8 *) USBFS_1_Dp__DR)\r
-/* Port Number */\r
-#define USBFS_1_Dp_PRT_NUM (* (reg8 *) USBFS_1_Dp__PRT) \r
-/* Connect to Analog Globals */ \r
-#define USBFS_1_Dp_AG (* (reg8 *) USBFS_1_Dp__AG) \r
-/* Analog MUX bux enable */\r
-#define USBFS_1_Dp_AMUX (* (reg8 *) USBFS_1_Dp__AMUX) \r
-/* Bidirectional Enable */ \r
-#define USBFS_1_Dp_BIE (* (reg8 *) USBFS_1_Dp__BIE)\r
-/* Bit-mask for Aliased Register Access */\r
-#define USBFS_1_Dp_BIT_MASK (* (reg8 *) USBFS_1_Dp__BIT_MASK)\r
-/* Bypass Enable */\r
-#define USBFS_1_Dp_BYP (* (reg8 *) USBFS_1_Dp__BYP)\r
-/* Port wide control signals */ \r
-#define USBFS_1_Dp_CTL (* (reg8 *) USBFS_1_Dp__CTL)\r
-/* Drive Modes */\r
-#define USBFS_1_Dp_DM0 (* (reg8 *) USBFS_1_Dp__DM0) \r
-#define USBFS_1_Dp_DM1 (* (reg8 *) USBFS_1_Dp__DM1)\r
-#define USBFS_1_Dp_DM2 (* (reg8 *) USBFS_1_Dp__DM2) \r
-/* Input Buffer Disable Override */\r
-#define USBFS_1_Dp_INP_DIS (* (reg8 *) USBFS_1_Dp__INP_DIS)\r
-/* LCD Common or Segment Drive */\r
-#define USBFS_1_Dp_LCD_COM_SEG (* (reg8 *) USBFS_1_Dp__LCD_COM_SEG)\r
-/* Enable Segment LCD */\r
-#define USBFS_1_Dp_LCD_EN (* (reg8 *) USBFS_1_Dp__LCD_EN)\r
-/* Slew Rate Control */\r
-#define USBFS_1_Dp_SLW (* (reg8 *) USBFS_1_Dp__SLW)\r
-\r
-/* DSI Port Registers */\r
-/* Global DSI Select Register */\r
-#define USBFS_1_Dp_PRTDSI__CAPS_SEL (* (reg8 *) USBFS_1_Dp__PRTDSI__CAPS_SEL) \r
-/* Double Sync Enable */\r
-#define USBFS_1_Dp_PRTDSI__DBL_SYNC_IN (* (reg8 *) USBFS_1_Dp__PRTDSI__DBL_SYNC_IN) \r
-/* Output Enable Select Drive Strength */\r
-#define USBFS_1_Dp_PRTDSI__OE_SEL0 (* (reg8 *) USBFS_1_Dp__PRTDSI__OE_SEL0) \r
-#define USBFS_1_Dp_PRTDSI__OE_SEL1 (* (reg8 *) USBFS_1_Dp__PRTDSI__OE_SEL1) \r
-/* Port Pin Output Select Registers */\r
-#define USBFS_1_Dp_PRTDSI__OUT_SEL0 (* (reg8 *) USBFS_1_Dp__PRTDSI__OUT_SEL0) \r
-#define USBFS_1_Dp_PRTDSI__OUT_SEL1 (* (reg8 *) USBFS_1_Dp__PRTDSI__OUT_SEL1) \r
-/* Sync Output Enable Registers */\r
-#define USBFS_1_Dp_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_1_Dp__PRTDSI__SYNC_OUT) \r
-\r
-\r
-#if defined(USBFS_1_Dp__INTSTAT) /* Interrupt Registers */\r
-\r
- #define USBFS_1_Dp_INTSTAT (* (reg8 *) USBFS_1_Dp__INTSTAT)\r
- #define USBFS_1_Dp_SNAP (* (reg8 *) USBFS_1_Dp__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
-\r
-#endif /* CY_PSOC5A... */\r
-\r
-#endif /* CY_PINS_USBFS_1_Dp_H */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_audio.c\r
-* Version 2.60\r
-*\r
-* Description:\r
-* USB AUDIO Class request handler.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "USBFS_1.h"\r
-\r
-#if defined(USBFS_1_ENABLE_AUDIO_CLASS)\r
-\r
-#include "USBFS_1_audio.h"\r
-#include "USBFS_1_pvt.h"\r
-#if defined(USBFS_1_ENABLE_MIDI_STREAMING) \r
- #include "USBFS_1_midi.h"\r
-#endif /* End USBFS_1_ENABLE_MIDI_STREAMING*/\r
-\r
-\r
-/***************************************\r
-* Custom Declarations\r
-***************************************/\r
-\r
-/* `#START CUSTOM_DECLARATIONS` Place your declaration here */\r
-\r
-/* `#END` */\r
-\r
-\r
-#if !defined(USER_SUPPLIED_AUDIO_HANDLER)\r
-\r
-\r
-/***************************************\r
-* AUDIO Variables\r
-***************************************/\r
-\r
-#if defined(USBFS_1_ENABLE_AUDIO_STREAMING)\r
- volatile uint8 USBFS_1_currentSampleFrequency[USBFS_1_MAX_EP][USBFS_1_SAMPLE_FREQ_LEN];\r
- volatile uint8 USBFS_1_frequencyChanged;\r
- volatile uint8 USBFS_1_currentMute;\r
- volatile uint8 USBFS_1_currentVolume[USBFS_1_VOLUME_LEN];\r
- volatile uint8 USBFS_1_minimumVolume[USBFS_1_VOLUME_LEN] = {USBFS_1_VOL_MIN_LSB,\r
- USBFS_1_VOL_MIN_MSB};\r
- volatile uint8 USBFS_1_maximumVolume[USBFS_1_VOLUME_LEN] = {USBFS_1_VOL_MAX_LSB,\r
- USBFS_1_VOL_MAX_MSB};\r
- volatile uint8 USBFS_1_resolutionVolume[USBFS_1_VOLUME_LEN] = {USBFS_1_VOL_RES_LSB,\r
- USBFS_1_VOL_RES_MSB};\r
-#endif /* End USBFS_1_ENABLE_AUDIO_STREAMING */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_DispatchAUDIOClassRqst\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine dispatches class requests\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* requestHandled\r
-*\r
-* Global variables:\r
-* USBFS_1_currentSampleFrequency: Contains the current audio Sample\r
-* Frequency. It is set by the Host using SET_CUR request to the endpoint.\r
-* USBFS_1_frequencyChanged: This variable is used as a flag for the\r
-* user code, to be aware that Host has been sent request for changing\r
-* Sample Frequency. Sample frequency will be sent on the next OUT\r
-* transaction. It is contains endpoint address when set. The following\r
-* code is recommended for detecting new Sample Frequency in main code:\r
-* if((USBFS_1_frequencyChanged != 0) &&\r
-* (USBFS_1_transferState == USBFS_1_TRANS_STATE_IDLE))\r
-* {\r
-* USBFS_1_frequencyChanged = 0;\r
-* }\r
-* USBFS_1_transferState variable is checked to be sure that\r
-* transfer completes.\r
-* USBFS_1_currentMute: Contains mute configuration set by Host.\r
-* USBFS_1_currentVolume: Contains volume level set by Host.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_DispatchAUDIOClassRqst(void) \r
-{\r
- uint8 requestHandled = USBFS_1_FALSE;\r
-\r
- #if defined(USBFS_1_ENABLE_AUDIO_STREAMING)\r
- uint8 epNumber;\r
- epNumber = CY_GET_REG8(USBFS_1_wIndexLo) & USBFS_1_DIR_UNUSED;\r
- #endif /* End USBFS_1_ENABLE_AUDIO_STREAMING */\r
-\r
- if ((CY_GET_REG8(USBFS_1_bmRequestType) & USBFS_1_RQST_DIR_MASK) == USBFS_1_RQST_DIR_D2H)\r
- {\r
- /* Control Read */\r
- if((CY_GET_REG8(USBFS_1_bmRequestType) & USBFS_1_RQST_RCPT_MASK) == \\r
- USBFS_1_RQST_RCPT_EP)\r
- {\r
- /* Endpoint */\r
- switch (CY_GET_REG8(USBFS_1_bRequest))\r
- {\r
- case USBFS_1_GET_CUR:\r
- #if defined(USBFS_1_ENABLE_AUDIO_STREAMING)\r
- if(CY_GET_REG8(USBFS_1_wValueHi) == USBFS_1_SAMPLING_FREQ_CONTROL)\r
- {\r
- /* Endpoint Control Selector is Sampling Frequency */\r
- USBFS_1_currentTD.wCount = USBFS_1_SAMPLE_FREQ_LEN;\r
- USBFS_1_currentTD.pData = USBFS_1_currentSampleFrequency[epNumber];\r
- requestHandled = USBFS_1_InitControlRead();\r
- }\r
- #endif /* End USBFS_1_ENABLE_AUDIO_STREAMING */\r
-\r
- /* `#START AUDIO_READ_REQUESTS` Place other request handler here */\r
-\r
- /* `#END` */\r
- break;\r
- default:\r
- break;\r
- }\r
- }\r
- else if((CY_GET_REG8(USBFS_1_bmRequestType) & USBFS_1_RQST_RCPT_MASK) == \\r
- USBFS_1_RQST_RCPT_IFC)\r
- {\r
- /* Interface or Entity ID */\r
- switch (CY_GET_REG8(USBFS_1_bRequest))\r
- {\r
- case USBFS_1_GET_CUR:\r
- #if defined(USBFS_1_ENABLE_AUDIO_STREAMING)\r
- if(CY_GET_REG8(USBFS_1_wValueHi) == USBFS_1_MUTE_CONTROL)\r
- {\r
- /* `#START MUTE_CONTROL_GET_REQUEST` Place multi-channel handler here */\r
-\r
- /* `#END` */\r
- \r
- /* Entity ID Control Selector is MUTE */\r
- USBFS_1_currentTD.wCount = 1u;\r
- USBFS_1_currentTD.pData = &USBFS_1_currentMute;\r
- requestHandled = USBFS_1_InitControlRead();\r
- }\r
- else if(CY_GET_REG8(USBFS_1_wValueHi) == USBFS_1_VOLUME_CONTROL)\r
- {\r
- /* `#START VOLUME_CONTROL_GET_REQUEST` Place multi-channel handler here */\r
-\r
- /* `#END` */\r
-\r
- /* Entity ID Control Selector is VOLUME, */\r
- USBFS_1_currentTD.wCount = USBFS_1_VOLUME_LEN;\r
- USBFS_1_currentTD.pData = USBFS_1_currentVolume;\r
- requestHandled = USBFS_1_InitControlRead();\r
- }\r
- else\r
- {\r
- /* `#START OTHER_GET_CUR_REQUESTS` Place other request handler here */\r
-\r
- /* `#END` */\r
- }\r
- break;\r
- case USBFS_1_GET_MIN: /* GET_MIN */\r
- if(CY_GET_REG8(USBFS_1_wValueHi) == USBFS_1_VOLUME_CONTROL)\r
- {\r
- /* Entity ID Control Selector is VOLUME, */\r
- USBFS_1_currentTD.wCount = USBFS_1_VOLUME_LEN;\r
- USBFS_1_currentTD.pData = &USBFS_1_minimumVolume[0];\r
- requestHandled = USBFS_1_InitControlRead();\r
- }\r
- break;\r
- case USBFS_1_GET_MAX: /* GET_MAX */\r
- if(CY_GET_REG8(USBFS_1_wValueHi) == USBFS_1_VOLUME_CONTROL)\r
- {\r
- /* Entity ID Control Selector is VOLUME, */\r
- USBFS_1_currentTD.wCount = USBFS_1_VOLUME_LEN;\r
- USBFS_1_currentTD.pData = &USBFS_1_maximumVolume[0];\r
- requestHandled = USBFS_1_InitControlRead();\r
- }\r
- break;\r
- case USBFS_1_GET_RES: /* GET_RES */\r
- if(CY_GET_REG8(USBFS_1_wValueHi) == USBFS_1_VOLUME_CONTROL)\r
- {\r
- /* Entity ID Control Selector is VOLUME, */\r
- USBFS_1_currentTD.wCount = USBFS_1_VOLUME_LEN;\r
- USBFS_1_currentTD.pData = &USBFS_1_resolutionVolume[0];\r
- requestHandled = USBFS_1_InitControlRead();\r
- }\r
- break;\r
- /* The contents of the status message is reserved for future use.\r
- * For the time being, a null packet should be returned in the data stage of the\r
- * control transfer, and the received null packet should be ACKed.\r
- */\r
- case USBFS_1_GET_STAT:\r
- USBFS_1_currentTD.wCount = 0u;\r
- requestHandled = USBFS_1_InitControlWrite();\r
-\r
- #endif /* End USBFS_1_ENABLE_AUDIO_STREAMING */\r
-\r
- /* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */\r
-\r
- /* `#END` */\r
- break;\r
- default:\r
- break;\r
- }\r
- }\r
- else\r
- { /* USBFS_1_RQST_RCPT_OTHER */\r
- }\r
- }\r
- else if ((CY_GET_REG8(USBFS_1_bmRequestType) & USBFS_1_RQST_DIR_MASK) == \\r
- USBFS_1_RQST_DIR_H2D)\r
- {\r
- /* Control Write */\r
- if((CY_GET_REG8(USBFS_1_bmRequestType) & USBFS_1_RQST_RCPT_MASK) == \\r
- USBFS_1_RQST_RCPT_EP)\r
- {\r
- /* Endpoint */\r
- switch (CY_GET_REG8(USBFS_1_bRequest))\r
- {\r
- case USBFS_1_SET_CUR:\r
- #if defined(USBFS_1_ENABLE_AUDIO_STREAMING)\r
- if(CY_GET_REG8(USBFS_1_wValueHi) == USBFS_1_SAMPLING_FREQ_CONTROL)\r
- {\r
- /* Endpoint Control Selector is Sampling Frequency */\r
- USBFS_1_currentTD.wCount = USBFS_1_SAMPLE_FREQ_LEN;\r
- USBFS_1_currentTD.pData = USBFS_1_currentSampleFrequency[epNumber];\r
- requestHandled = USBFS_1_InitControlWrite();\r
- USBFS_1_frequencyChanged = epNumber;\r
- }\r
- #endif /* End USBFS_1_ENABLE_AUDIO_STREAMING */\r
-\r
- /* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */\r
-\r
- /* `#END` */\r
- break;\r
- default:\r
- break;\r
- }\r
- }\r
- else if((CY_GET_REG8(USBFS_1_bmRequestType) & USBFS_1_RQST_RCPT_MASK) == \\r
- USBFS_1_RQST_RCPT_IFC)\r
- {\r
- /* Interface or Entity ID */\r
- switch (CY_GET_REG8(USBFS_1_bRequest))\r
- {\r
- case USBFS_1_SET_CUR:\r
- #if defined(USBFS_1_ENABLE_AUDIO_STREAMING)\r
- if(CY_GET_REG8(USBFS_1_wValueHi) == USBFS_1_MUTE_CONTROL)\r
- {\r
- /* `#START MUTE_SET_REQUEST` Place multi-channel handler here */\r
-\r
- /* `#END` */\r
-\r
- /* Entity ID Control Selector is MUTE */\r
- USBFS_1_currentTD.wCount = 1u;\r
- USBFS_1_currentTD.pData = &USBFS_1_currentMute;\r
- requestHandled = USBFS_1_InitControlWrite();\r
- }\r
- else if(CY_GET_REG8(USBFS_1_wValueHi) == USBFS_1_VOLUME_CONTROL)\r
- {\r
- /* `#START VOLUME_CONTROL_SET_REQUEST` Place multi-channel handler here */\r
-\r
- /* `#END` */\r
-\r
- /* Entity ID Control Selector is VOLUME */\r
- USBFS_1_currentTD.wCount = USBFS_1_VOLUME_LEN;\r
- USBFS_1_currentTD.pData = USBFS_1_currentVolume;\r
- requestHandled = USBFS_1_InitControlWrite();\r
- }\r
- else\r
- {\r
- /* `#START OTHER_SET_CUR_REQUESTS` Place other request handler here */\r
-\r
- /* `#END` */\r
- }\r
- #endif /* End USBFS_1_ENABLE_AUDIO_STREAMING */\r
-\r
- /* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */\r
-\r
- /* `#END` */\r
- break;\r
- default:\r
- break;\r
- }\r
- }\r
- else\r
- { /* USBFS_1_RQST_RCPT_OTHER */\r
- }\r
- }\r
- else\r
- { /* requestHandled is initialized as FALSE by default */\r
- }\r
-\r
- return(requestHandled);\r
-}\r
-\r
-\r
-#endif /* USER_SUPPLIED_AUDIO_HANDLER */\r
-\r
-\r
-/*******************************************************************************\r
-* Additional user functions supporting AUDIO Requests\r
-********************************************************************************/\r
-\r
-/* `#START AUDIO_FUNCTIONS` Place any additional functions here */\r
-\r
-/* `#END` */\r
-\r
-#endif /* End USBFS_1_ENABLE_AUDIO_CLASS*/\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_audio.h\r
-* Version 2.60\r
-*\r
-* Description:\r
-* Header File for the USFS component. Contains prototypes and constant values.\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_USBFS_USBFS_1_audio_H)\r
-#define CY_USBFS_USBFS_1_audio_H\r
-\r
-#include "cytypes.h"\r
-\r
-\r
-/***************************************\r
-* Custom Declarations\r
-***************************************/\r
-\r
-/* `#START CUSTOM_CONSTANTS` Place your declaration here */\r
-\r
-/* `#END` */\r
-\r
-\r
-/***************************************\r
-* Constants for USBFS_1_audio API.\r
-***************************************/\r
-\r
-/* Audio Class-Specific Request Codes (AUDIO Table A-9) */\r
-#define USBFS_1_REQUEST_CODE_UNDEFINED (0x00u)\r
-#define USBFS_1_SET_CUR (0x01u)\r
-#define USBFS_1_GET_CUR (0x81u)\r
-#define USBFS_1_SET_MIN (0x02u)\r
-#define USBFS_1_GET_MIN (0x82u)\r
-#define USBFS_1_SET_MAX (0x03u)\r
-#define USBFS_1_GET_MAX (0x83u)\r
-#define USBFS_1_SET_RES (0x04u)\r
-#define USBFS_1_GET_RES (0x84u)\r
-#define USBFS_1_SET_MEM (0x05u)\r
-#define USBFS_1_GET_MEM (0x85u)\r
-#define USBFS_1_GET_STAT (0xFFu)\r
-\r
-/* Endpoint Control Selectors (AUDIO Table A-19) */\r
-#define USBFS_1_EP_CONTROL_UNDEFINED (0x00u)\r
-#define USBFS_1_SAMPLING_FREQ_CONTROL (0x01u)\r
-#define USBFS_1_PITCH_CONTROL (0x02u)\r
-\r
-/* Feature Unit Control Selectors (AUDIO Table A-11) */\r
-#define USBFS_1_FU_CONTROL_UNDEFINED (0x00u)\r
-#define USBFS_1_MUTE_CONTROL (0x01u)\r
-#define USBFS_1_VOLUME_CONTROL (0x02u)\r
-#define USBFS_1_BASS_CONTROL (0x03u)\r
-#define USBFS_1_MID_CONTROL (0x04u)\r
-#define USBFS_1_TREBLE_CONTROL (0x05u)\r
-#define USBFS_1_GRAPHIC_EQUALIZER_CONTROL (0x06u)\r
-#define USBFS_1_AUTOMATIC_GAIN_CONTROL (0x07u)\r
-#define USBFS_1_DELAY_CONTROL (0x08u)\r
-#define USBFS_1_BASS_BOOST_CONTROL (0x09u)\r
-#define USBFS_1_LOUDNESS_CONTROL (0x0Au)\r
-\r
-#define USBFS_1_SAMPLE_FREQ_LEN (3u)\r
-#define USBFS_1_VOLUME_LEN (2u)\r
-\r
-#if !defined(USER_SUPPLIED_DEFAULT_VOLUME_VALUE)\r
- #define USBFS_1_VOL_MIN_MSB (0x80u)\r
- #define USBFS_1_VOL_MIN_LSB (0x01u)\r
- #define USBFS_1_VOL_MAX_MSB (0x7Fu)\r
- #define USBFS_1_VOL_MAX_LSB (0xFFu)\r
- #define USBFS_1_VOL_RES_MSB (0x00u)\r
- #define USBFS_1_VOL_RES_LSB (0x01u)\r
-#endif /* USER_SUPPLIED_DEFAULT_VOLUME_VALUE */\r
-\r
-\r
-/***************************************\r
-* External data references\r
-***************************************/\r
-\r
-extern volatile uint8 USBFS_1_currentSampleFrequency[USBFS_1_MAX_EP]\r
- [USBFS_1_SAMPLE_FREQ_LEN];\r
-extern volatile uint8 USBFS_1_frequencyChanged;\r
-extern volatile uint8 USBFS_1_currentMute;\r
-extern volatile uint8 USBFS_1_currentVolume[USBFS_1_VOLUME_LEN];\r
-extern volatile uint8 USBFS_1_minimumVolume[USBFS_1_VOLUME_LEN];\r
-extern volatile uint8 USBFS_1_maximumVolume[USBFS_1_VOLUME_LEN];\r
-extern volatile uint8 USBFS_1_resolutionVolume[USBFS_1_VOLUME_LEN];\r
-\r
-#endif /* End CY_USBFS_USBFS_1_audio_H */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_boot.c\r
-* Version 2.60\r
-*\r
-* Description:\r
-* Boot loader API for USBFS Component.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "USBFS_1.h"\r
-\r
-#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS_1) || \\r
- (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))\r
-\r
-\r
-/***************************************\r
-* Bootloader defines\r
-***************************************/\r
-\r
-#define USBFS_1_CyBtLdrStarttimer(X, T) {USBFS_1_universalTime = T * 10; X = 0u;}\r
-#define USBFS_1_CyBtLdrChecktimer(X) ((X++ < USBFS_1_universalTime) ? 1u : 0u)\r
-\r
-#define USBFS_1_BTLDR_OUT_EP (0x01u)\r
-#define USBFS_1_BTLDR_IN_EP (0x02u)\r
-\r
-\r
-/***************************************\r
-* Bootloader Variables\r
-***************************************/\r
-\r
-static uint16 USBFS_1_universalTime;\r
-static uint8 USBFS_1_started = 0u;\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_CyBtldrCommStart\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Starts the component and enables the interrupt.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Side Effects:\r
-* This function starts the USB with 3V or 5V operation.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_CyBtldrCommStart(void) \r
-{\r
- CyGlobalIntEnable; /* Enable Global Interrupts */\r
-\r
- /*Start USBFS Operation/device 0 and with 5V or 3V operation depend on Voltage Configuration in DWR */\r
- USBFS_1_Start(0u, USBFS_1_DWR_VDDD_OPERATION);\r
-\r
- /* USB component started, the correct enumeration will be checked in first Read operation */\r
- USBFS_1_started = 1u;\r
-\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_CyBtldrCommStop.\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Disable the component and disable the interrupt.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_CyBtldrCommStop(void) \r
-{\r
- USBFS_1_Stop();\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_CyBtldrCommReset.\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Resets the receive and transmit communication Buffers.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_CyBtldrCommReset(void) \r
-{\r
- USBFS_1_EnableOutEP(USBFS_1_BTLDR_OUT_EP); /* Enable the OUT endpoint */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_CyBtldrCommWrite.\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Allows the caller to write data to the boot loader host. The function will\r
-* handle polling to allow a block of data to be completely sent to the host\r
-* device.\r
-*\r
-* Parameters:\r
-* pData: A pointer to the block of data to send to the device\r
-* size: The number of bytes to write.\r
-* count: Pointer to an unsigned short variable to write the number of\r
-* bytes actually written.\r
-* timeOut: Number of units to wait before returning because of a timeout.\r
-*\r
-* Return:\r
-* Returns the value that best describes the problem.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-cystatus USBFS_1_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
- \r
-{\r
- uint16 time;\r
- cystatus status;\r
-\r
- /* Enable IN transfer */\r
- USBFS_1_LoadInEP(USBFS_1_BTLDR_IN_EP, pData, USBFS_1_BTLDR_SIZEOF_READ_BUFFER);\r
-\r
- /* Start a timer to wait on. */\r
- USBFS_1_CyBtLdrStarttimer(time, timeOut);\r
-\r
- /* Wait for the master to read it. */\r
- while((USBFS_1_GetEPState(USBFS_1_BTLDR_IN_EP) == USBFS_1_IN_BUFFER_FULL) && \\r
- USBFS_1_CyBtLdrChecktimer(time))\r
- {\r
- CyDelay(1u); /* 1ms delay */\r
- }\r
-\r
- if (USBFS_1_GetEPState(USBFS_1_BTLDR_IN_EP) == USBFS_1_IN_BUFFER_FULL)\r
- {\r
- status = CYRET_TIMEOUT;\r
- }\r
- else\r
- {\r
- *count = size;\r
- status = CYRET_SUCCESS;\r
- }\r
-\r
- return(status);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_CyBtldrCommRead.\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Allows the caller to read data from the boot loader host. The function will\r
-* handle polling to allow a block of data to be completely received from the\r
-* host device.\r
-*\r
-* Parameters:\r
-* pData: A pointer to the area to store the block of data received\r
-* from the device.\r
-* size: The number of bytes to read.\r
-* count: Pointer to an unsigned short variable to write the number\r
-* of bytes actually read.\r
-* timeOut: Number of units to wait before returning because of a timeOut.\r
-* Timeout is measured in 10s of ms.\r
-*\r
-* Return:\r
-* Returns the value that best describes the problem.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-cystatus USBFS_1_CyBtldrCommRead(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
- \r
-{\r
- cystatus status;\r
- uint16 time;\r
-\r
- if(size > USBFS_1_BTLDR_SIZEOF_WRITE_BUFFER)\r
- {\r
- size = USBFS_1_BTLDR_SIZEOF_WRITE_BUFFER;\r
- }\r
- /* Start a timer to wait on. */\r
- USBFS_1_CyBtLdrStarttimer(time, timeOut);\r
-\r
- /* Wait on enumeration in first time */\r
- if(USBFS_1_started)\r
- {\r
- /* Wait for Device to enumerate */\r
- while(!USBFS_1_GetConfiguration() && USBFS_1_CyBtLdrChecktimer(time))\r
- {\r
- CyDelay(1u); /* 1ms delay */\r
- }\r
- /* Enable first OUT, if enumeration complete */\r
- if(USBFS_1_GetConfiguration())\r
- {\r
- USBFS_1_IsConfigurationChanged(); /* Clear configuration changes state status */\r
- USBFS_1_CyBtldrCommReset();\r
- USBFS_1_started = 0u;\r
- }\r
- }\r
- else /* Check for configuration changes, has been done by Host */\r
- {\r
- if(USBFS_1_IsConfigurationChanged() != 0u) /* Host could send double SET_INTERFACE request or RESET */\r
- {\r
- if(USBFS_1_GetConfiguration() != 0u) /* Init OUT endpoints when device reconfigured */\r
- {\r
- USBFS_1_CyBtldrCommReset();\r
- }\r
- }\r
- }\r
- /* Wait on next packet */\r
- while((USBFS_1_GetEPState(USBFS_1_BTLDR_OUT_EP) != USBFS_1_OUT_BUFFER_FULL) && \\r
- USBFS_1_CyBtLdrChecktimer(time))\r
- {\r
- CyDelay(1u); /* 1ms delay */\r
- }\r
-\r
- /* OUT EP has completed */\r
- if (USBFS_1_GetEPState(USBFS_1_BTLDR_OUT_EP) == USBFS_1_OUT_BUFFER_FULL)\r
- {\r
- *count = USBFS_1_ReadOutEP(USBFS_1_BTLDR_OUT_EP, pData, size);\r
- status = CYRET_SUCCESS;\r
- }\r
- else\r
- {\r
- *count = 0u;\r
- status = CYRET_TIMEOUT;\r
- }\r
- return(status);\r
-}\r
-\r
-#endif /* End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS_1 */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_cdc.c\r
-* Version 2.60\r
-*\r
-* Description:\r
-* USB HID Class request handler.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2012-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "USBFS_1.h"\r
-\r
-#if defined(USBFS_1_ENABLE_CDC_CLASS)\r
-\r
-#include "USBFS_1_cdc.h"\r
-#include "USBFS_1_pvt.h"\r
-\r
-\r
-/***************************************\r
-* CDC Variables\r
-***************************************/\r
-\r
-volatile uint8 USBFS_1_lineCoding[USBFS_1_LINE_CODING_SIZE];\r
-volatile uint8 USBFS_1_lineChanged;\r
-volatile uint16 USBFS_1_lineControlBitmap;\r
-volatile uint8 USBFS_1_cdc_data_in_ep;\r
-volatile uint8 USBFS_1_cdc_data_out_ep;\r
-\r
-\r
-/***************************************\r
-* Static Function Prototypes\r
-***************************************/\r
-static uint16 USBFS_1_StrLen(const char8 string[]) ;\r
-\r
-\r
-/***************************************\r
-* Custom Declarations\r
-***************************************/\r
-\r
-/* `#START CDC_CUSTOM_DECLARATIONS` Place your declaration here */\r
-\r
-/* `#END` */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_DispatchCDCClassRqst\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine dispatches CDC class requests.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* requestHandled\r
-*\r
-* Global variables:\r
-* USBFS_1_lineCoding: Contains the current line coding structure.\r
-* It is set by the Host using SET_LINE_CODING request and returned to the\r
-* user code by the USBFS_GetDTERate(), USBFS_GetCharFormat(),\r
-* USBFS_GetParityType(), USBFS_GetDataBits() APIs.\r
-* USBFS_1_lineControlBitmap: Contains the current control signal\r
-* bitmap. It is set by the Host using SET_CONTROL_LINE request and returned\r
-* to the user code by the USBFS_GetLineControl() API.\r
-* USBFS_1_lineChanged: This variable is used as a flag for the\r
-* USBFS_IsLineChanged() API, to be aware that Host has been sent request\r
-* for changing Line Coding or Control Bitmap.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_DispatchCDCClassRqst(void) \r
-{\r
- uint8 requestHandled = USBFS_1_FALSE;\r
-\r
- if ((CY_GET_REG8(USBFS_1_bmRequestType) & USBFS_1_RQST_DIR_MASK) == USBFS_1_RQST_DIR_D2H)\r
- { /* Control Read */\r
- switch (CY_GET_REG8(USBFS_1_bRequest))\r
- {\r
- case USBFS_1_CDC_GET_LINE_CODING:\r
- USBFS_1_currentTD.count = USBFS_1_LINE_CODING_SIZE;\r
- USBFS_1_currentTD.pData = USBFS_1_lineCoding;\r
- requestHandled = USBFS_1_InitControlRead();\r
- break;\r
-\r
- /* `#START CDC_READ_REQUESTS` Place other request handler here */\r
-\r
- /* `#END` */\r
-\r
- default: /* requestHandled is initialized as FALSE by default */\r
- break;\r
- }\r
- }\r
- else if ((CY_GET_REG8(USBFS_1_bmRequestType) & USBFS_1_RQST_DIR_MASK) == \\r
- USBFS_1_RQST_DIR_H2D)\r
- { /* Control Write */\r
- switch (CY_GET_REG8(USBFS_1_bRequest))\r
- {\r
- case USBFS_1_CDC_SET_LINE_CODING:\r
- USBFS_1_currentTD.count = USBFS_1_LINE_CODING_SIZE;\r
- USBFS_1_currentTD.pData = USBFS_1_lineCoding;\r
- USBFS_1_lineChanged |= USBFS_1_LINE_CODING_CHANGED;\r
- requestHandled = USBFS_1_InitControlWrite();\r
- break;\r
-\r
- case USBFS_1_CDC_SET_CONTROL_LINE_STATE:\r
- USBFS_1_lineControlBitmap = CY_GET_REG8(USBFS_1_wValueLo);\r
- USBFS_1_lineChanged |= USBFS_1_LINE_CONTROL_CHANGED;\r
- requestHandled = USBFS_1_InitNoDataControlTransfer();\r
- break;\r
-\r
- /* `#START CDC_WRITE_REQUESTS` Place other request handler here */\r
-\r
- /* `#END` */\r
-\r
- default: /* requestHandled is initialized as FALSE by default */\r
- break;\r
- }\r
- }\r
- else\r
- { /* requestHandled is initialized as FALSE by default */\r
- }\r
-\r
- return(requestHandled);\r
-}\r
-\r
-\r
-/***************************************\r
-* Optional CDC APIs\r
-***************************************/\r
-#if (USBFS_1_ENABLE_CDC_CLASS_API != 0u)\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_CDC_Init\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function initialize the CDC interface to be ready for the receive data\r
- * from the PC.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Global variables:\r
- * USBFS_1_lineChanged: Initialized to zero.\r
- * USBFS_1_cdc_data_out_ep: Used as an OUT endpoint number.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- void USBFS_1_CDC_Init(void) \r
- {\r
- USBFS_1_lineChanged = 0u;\r
- USBFS_1_EnableOutEP(USBFS_1_cdc_data_out_ep);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_PutData\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Sends a specified number of bytes from the location specified by a\r
- * pointer to the PC.\r
- *\r
- * Parameters:\r
- * pData: pointer to the buffer containing data to be sent.\r
- * length: Specifies the number of bytes to send from the pData\r
- * buffer. Maximum length will be limited by the maximum packet\r
- * size for the endpoint.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Global variables:\r
- * USBFS_1_cdc_data_in_ep: CDC IN endpoint number used for sending\r
- * data.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- void USBFS_1_PutData(const uint8* pData, uint16 length) \r
- {\r
- /* Limits length to maximum packet size for the EP */\r
- if(length > USBFS_1_EP[USBFS_1_cdc_data_in_ep].bufferSize)\r
- {\r
- /* Caution: Data will be lost if length is greater than Max Packet Length */\r
- length = USBFS_1_EP[USBFS_1_cdc_data_in_ep].bufferSize;\r
- /* Halt CPU in debug mode */\r
- CYASSERT(0u != 0u);\r
- }\r
- USBFS_1_LoadInEP(USBFS_1_cdc_data_in_ep, pData, length);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_StrLen\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Calculates length of a null terminated string.\r
- *\r
- * Parameters:\r
- * string: pointer to the string.\r
- *\r
- * Return:\r
- * Length of the string\r
- *\r
- *******************************************************************************/\r
- static uint16 USBFS_1_StrLen(const char8 string[]) \r
- {\r
- uint16 len = 0u;\r
-\r
- while (string[len] != (char8)0)\r
- {\r
- len++;\r
- }\r
-\r
- return (len);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_PutString\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Sends a null terminated string to the PC.\r
- *\r
- * Parameters:\r
- * string: pointer to the string to be sent to the PC\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Global variables:\r
- * USBFS_1_cdc_data_in_ep: CDC IN endpoint number used for sending\r
- * data.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- * Theory:\r
- * This function will block if there is not enough memory to place the whole\r
- * string, it will block until the entire string has been written to the\r
- * transmit buffer.\r
- *\r
- *******************************************************************************/\r
- void USBFS_1_PutString(const char8 string[]) \r
- {\r
- uint16 str_length;\r
- uint16 send_length;\r
- uint16 buf_index = 0u;\r
-\r
- /* Get length of the null terminated string */\r
- str_length = USBFS_1_StrLen(string);\r
- do\r
- {\r
- /* Limits length to maximum packet size for the EP */\r
- send_length = (str_length > USBFS_1_EP[USBFS_1_cdc_data_in_ep].bufferSize) ?\r
- USBFS_1_EP[USBFS_1_cdc_data_in_ep].bufferSize : str_length;\r
- /* Enable IN transfer */\r
- USBFS_1_LoadInEP(USBFS_1_cdc_data_in_ep, (const uint8 *)&string[buf_index], send_length);\r
- str_length -= send_length;\r
-\r
- /* If more data are present to send */\r
- if(str_length > 0u)\r
- {\r
- buf_index += send_length;\r
- /* Wait for the Host to read it. */\r
- while(USBFS_1_EP[USBFS_1_cdc_data_in_ep].apiEpState ==\r
- USBFS_1_IN_BUFFER_FULL)\r
- {\r
- ;\r
- }\r
- }\r
- }while(str_length > 0u);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_PutChar\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Writes a single character to the PC.\r
- *\r
- * Parameters:\r
- * txDataByte: Character to be sent to the PC.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Global variables:\r
- * USBFS_1_cdc_data_in_ep: CDC IN endpoint number used for sending\r
- * data.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- void USBFS_1_PutChar(char8 txDataByte) \r
- {\r
- uint8 dataByte;\r
- dataByte = (uint8)txDataByte;\r
-\r
- USBFS_1_LoadInEP(USBFS_1_cdc_data_in_ep, &dataByte, 1u);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_PutCRLF\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Sends a carriage return (0x0D) and line feed (0x0A) to the PC\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Global variables:\r
- * USBFS_1_cdc_data_in_ep: CDC IN endpoint number used for sending\r
- * data.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- void USBFS_1_PutCRLF(void) \r
- {\r
- const uint8 CYCODE txData[] = {0x0Du, 0x0Au};\r
-\r
- USBFS_1_LoadInEP(USBFS_1_cdc_data_in_ep, (const uint8 *)txData, 2u);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_GetCount\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function returns the number of bytes that were received from the PC.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns the number of received bytes.\r
- *\r
- * Global variables:\r
- * USBFS_1_cdc_data_out_ep: CDC OUT endpoint number used.\r
- *\r
- *******************************************************************************/\r
- uint16 USBFS_1_GetCount(void) \r
- {\r
- uint16 bytesCount = 0u;\r
-\r
- if (USBFS_1_EP[USBFS_1_cdc_data_out_ep].apiEpState == USBFS_1_OUT_BUFFER_FULL)\r
- {\r
- bytesCount = USBFS_1_GetEPCount(USBFS_1_cdc_data_out_ep);\r
- }\r
-\r
- return(bytesCount);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_DataIsReady\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns a nonzero value if the component received data or received\r
- * zero-length packet. The GetAll() or GetData() API should be called to read\r
- * data from the buffer and re-init OUT endpoint even when zero-length packet\r
- * received.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * If the OUT packet received this function returns a nonzero value.\r
- * Otherwise zero is returned.\r
- *\r
- * Global variables:\r
- * USBFS_1_cdc_data_out_ep: CDC OUT endpoint number used.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_1_DataIsReady(void) \r
- {\r
- return(USBFS_1_EP[USBFS_1_cdc_data_out_ep].apiEpState);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_CDCIsReady\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns a nonzero value if the component is ready to send more data to the\r
- * PC. Otherwise returns zero. Should be called before sending new data to\r
- * ensure the previous data has finished sending.This function returns the\r
- * number of bytes that were received from the PC.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * If the buffer can accept new data then this function returns a nonzero value.\r
- * Otherwise zero is returned.\r
- *\r
- * Global variables:\r
- * USBFS_1_cdc_data_in_ep: CDC IN endpoint number used.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_1_CDCIsReady(void) \r
- {\r
- return(USBFS_1_EP[USBFS_1_cdc_data_in_ep].apiEpState);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_GetData\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Gets a specified number of bytes from the input buffer and places it in a\r
- * data array specified by the passed pointer.\r
- * USBFS_1_DataIsReady() API should be called before, to be sure\r
- * that data is received from the Host.\r
- *\r
- * Parameters:\r
- * pData: Pointer to the data array where data will be placed.\r
- * Length: Number of bytes to read into the data array from the RX buffer.\r
- * Maximum length is limited by the the number of received bytes.\r
- *\r
- * Return:\r
- * Number of bytes received.\r
- *\r
- * Global variables:\r
- * USBFS_1_cdc_data_out_ep: CDC OUT endpoint number used.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- uint16 USBFS_1_GetData(uint8* pData, uint16 length) \r
- {\r
- return(USBFS_1_ReadOutEP(USBFS_1_cdc_data_out_ep, pData, length));\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_GetAll\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Gets all bytes of received data from the input buffer and places it into a\r
- * specified data array. USBFS_1_DataIsReady() API should be called\r
- * before, to be sure that data is received from the Host.\r
- *\r
- * Parameters:\r
- * pData: Pointer to the data array where data will be placed.\r
- *\r
- * Return:\r
- * Number of bytes received.\r
- *\r
- * Global variables:\r
- * USBFS_1_cdc_data_out_ep: CDC OUT endpoint number used.\r
- * USBFS_1_EP[].bufferSize: EP max packet size is used as a length\r
- * to read all data from the EP buffer.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- uint16 USBFS_1_GetAll(uint8* pData) \r
- {\r
- return (USBFS_1_ReadOutEP(USBFS_1_cdc_data_out_ep, pData,\r
- USBFS_1_EP[USBFS_1_cdc_data_out_ep].bufferSize));\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_GetChar\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Reads one byte of received data from the buffer.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Received one character.\r
- *\r
- * Global variables:\r
- * USBFS_1_cdc_data_out_ep: CDC OUT endpoint number used.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_1_GetChar(void) \r
- {\r
- uint8 rxData;\r
-\r
- (void) USBFS_1_ReadOutEP(USBFS_1_cdc_data_out_ep, &rxData, 1u);\r
-\r
- return(rxData);\r
- }\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_IsLineChanged\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This function returns clear on read status of the line.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE request received then not\r
- * zero value returned. Otherwise zero is returned.\r
- *\r
- * Global variables:\r
- * USBFS_1_transferState - it is checked to be sure then OUT data\r
- * phase has been complete, and data written to the lineCoding or Control\r
- * Bitmap buffer.\r
- * USBFS_1_lineChanged: used as a flag to be aware that Host has been\r
- * sent request for changing Line Coding or Control Bitmap.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_1_IsLineChanged(void) \r
- {\r
- uint8 state = 0u;\r
-\r
- /* transferState is checked to be sure then OUT data phase has been complete */\r
- if(USBFS_1_transferState == USBFS_1_TRANS_STATE_IDLE)\r
- {\r
- if(USBFS_1_lineChanged != 0u)\r
- {\r
- state = USBFS_1_lineChanged;\r
- USBFS_1_lineChanged = 0u;\r
- }\r
- }\r
-\r
- return(state);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_GetDTERate\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns the data terminal rate set for this port in bits per second.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns a uint32 value of the data rate in bits per second.\r
- *\r
- * Global variables:\r
- * USBFS_1_lineCoding: First four bytes converted to uint32\r
- * depend on compiler, and returned as a data rate.\r
- *\r
- *******************************************************************************/\r
- uint32 USBFS_1_GetDTERate(void) \r
- {\r
- uint32 rate;\r
-\r
- rate = USBFS_1_lineCoding[USBFS_1_LINE_CODING_RATE + 3u];\r
- rate = (rate << 8u) | USBFS_1_lineCoding[USBFS_1_LINE_CODING_RATE + 2u];\r
- rate = (rate << 8u) | USBFS_1_lineCoding[USBFS_1_LINE_CODING_RATE + 1u];\r
- rate = (rate << 8u) | USBFS_1_lineCoding[USBFS_1_LINE_CODING_RATE];\r
-\r
- return(rate);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_GetCharFormat\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns the number of stop bits.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns the number of stop bits.\r
- *\r
- * Global variables:\r
- * USBFS_1_lineCoding: used to get a parameter.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_1_GetCharFormat(void) \r
- {\r
- return(USBFS_1_lineCoding[USBFS_1_LINE_CODING_STOP_BITS]);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_GetParityType\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns the parity type for the CDC port.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns the parity type.\r
- *\r
- * Global variables:\r
- * USBFS_1_lineCoding: used to get a parameter.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_1_GetParityType(void) \r
- {\r
- return(USBFS_1_lineCoding[USBFS_1_LINE_CODING_PARITY]);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_GetDataBits\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns the number of data bits for the CDC port.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns the number of data bits.\r
- * The number of data bits can be 5, 6, 7, 8 or 16.\r
- *\r
- * Global variables:\r
- * USBFS_1_lineCoding: used to get a parameter.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_1_GetDataBits(void) \r
- {\r
- return(USBFS_1_lineCoding[USBFS_1_LINE_CODING_DATA_BITS]);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_GetLineControl\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Returns Line control bitmap.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * Returns Line control bitmap.\r
- *\r
- * Global variables:\r
- * USBFS_1_lineControlBitmap: used to get a parameter.\r
- *\r
- *******************************************************************************/\r
- uint16 USBFS_1_GetLineControl(void) \r
- {\r
- return(USBFS_1_lineControlBitmap);\r
- }\r
-\r
-#endif /* End USBFS_1_ENABLE_CDC_CLASS_API*/\r
-\r
-\r
-/*******************************************************************************\r
-* Additional user functions supporting CDC Requests\r
-********************************************************************************/\r
-\r
-/* `#START CDC_FUNCTIONS` Place any additional functions here */\r
-\r
-/* `#END` */\r
-\r
-#endif /* End USBFS_1_ENABLE_CDC_CLASS*/\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_cdc.h\r
-* Version 2.60\r
-*\r
-* Description:\r
-* Header File for the USFS component.\r
-* Contains CDC class prototypes and constant values.\r
-*\r
-********************************************************************************\r
-* Copyright 2012-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_USBFS_USBFS_1_cdc_H)\r
-#define CY_USBFS_USBFS_1_cdc_H\r
-\r
-#include "cytypes.h"\r
-\r
-\r
-/***************************************\r
-* Prototypes of the USBFS_1_cdc API.\r
-***************************************/\r
-\r
-#if (USBFS_1_ENABLE_CDC_CLASS_API != 0u)\r
- void USBFS_1_CDC_Init(void) ;\r
- void USBFS_1_PutData(const uint8* pData, uint16 length) ;\r
- void USBFS_1_PutString(const char8 string[]) ;\r
- void USBFS_1_PutChar(char8 txDataByte) ;\r
- void USBFS_1_PutCRLF(void) ;\r
- uint16 USBFS_1_GetCount(void) ;\r
- uint8 USBFS_1_CDCIsReady(void) ;\r
- uint8 USBFS_1_DataIsReady(void) ;\r
- uint16 USBFS_1_GetData(uint8* pData, uint16 length) ;\r
- uint16 USBFS_1_GetAll(uint8* pData) ;\r
- uint8 USBFS_1_GetChar(void) ;\r
- uint8 USBFS_1_IsLineChanged(void) ;\r
- uint32 USBFS_1_GetDTERate(void) ;\r
- uint8 USBFS_1_GetCharFormat(void) ;\r
- uint8 USBFS_1_GetParityType(void) ;\r
- uint8 USBFS_1_GetDataBits(void) ;\r
- uint16 USBFS_1_GetLineControl(void) ;\r
-#endif /* End USBFS_1_ENABLE_CDC_CLASS_API*/\r
-\r
-\r
-/***************************************\r
-* Constants for USBFS_1_cdc API.\r
-***************************************/\r
-\r
-/* CDC Class-Specific Request Codes (CDC ver 1.2 Table 19) */\r
-#define USBFS_1_CDC_SET_LINE_CODING (0x20u)\r
-#define USBFS_1_CDC_GET_LINE_CODING (0x21u)\r
-#define USBFS_1_CDC_SET_CONTROL_LINE_STATE (0x22u)\r
-\r
-#define USBFS_1_LINE_CODING_CHANGED (0x01u)\r
-#define USBFS_1_LINE_CONTROL_CHANGED (0x02u)\r
-\r
-#define USBFS_1_1_STOPBIT (0x00u)\r
-#define USBFS_1_1_5_STOPBITS (0x01u)\r
-#define USBFS_1_2_STOPBITS (0x02u)\r
-\r
-#define USBFS_1_PARITY_NONE (0x00u)\r
-#define USBFS_1_PARITY_ODD (0x01u)\r
-#define USBFS_1_PARITY_EVEN (0x02u)\r
-#define USBFS_1_PARITY_MARK (0x03u)\r
-#define USBFS_1_PARITY_SPACE (0x04u)\r
-\r
-#define USBFS_1_LINE_CODING_SIZE (0x07u)\r
-#define USBFS_1_LINE_CODING_RATE (0x00u)\r
-#define USBFS_1_LINE_CODING_STOP_BITS (0x04u)\r
-#define USBFS_1_LINE_CODING_PARITY (0x05u)\r
-#define USBFS_1_LINE_CODING_DATA_BITS (0x06u)\r
-\r
-#define USBFS_1_LINE_CONTROL_DTR (0x01u)\r
-#define USBFS_1_LINE_CONTROL_RTS (0x02u)\r
-\r
-\r
-/***************************************\r
-* External data references\r
-***************************************/\r
-\r
-extern volatile uint8 USBFS_1_lineCoding[USBFS_1_LINE_CODING_SIZE];\r
-extern volatile uint8 USBFS_1_lineChanged;\r
-extern volatile uint16 USBFS_1_lineControlBitmap;\r
-extern volatile uint8 USBFS_1_cdc_data_in_ep;\r
-extern volatile uint8 USBFS_1_cdc_data_out_ep;\r
-\r
-#endif /* End CY_USBFS_USBFS_1_cdc_H */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-;******************************************************************************\r
-; File Name: USBFS_1_cdc.inf\r
-; Version 2.60\r
-;\r
-; Description:\r
-; Windows USB CDC setup file for USBUART Device.\r
-;\r
-;******************************************************************************\r
-; Copyright 2007-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-; You may use this file only in accordance with the license, terms, conditions,\r
-; disclaimers, and limitations in the end user license agreement accompanying\r
-; the software package with which this file was provided.\r
-;******************************************************************************\r
-\r
-[Version]\r
-Signature="$Windows NT$"\r
-Class=Ports\r
-ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318}\r
-Provider=%PROVIDER%\r
-LayoutFile=layout.inf\r
-DriverVer=03/05/2007,2.0.0000.0\r
-\r
-[Manufacturer]\r
-%MFGNAME%=DeviceList, NTx86, NTia64, NTamd64\r
-\r
-[DestinationDirs]\r
-DefaultDestDir=12\r
-\r
-[SourceDisksFiles]\r
-\r
-[SourceDisksNames]\r
-\r
-[DeviceList.NTx86]\r
-%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232\r
-\r
-[DeviceList.NTia64]\r
-%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232\r
-\r
-[DeviceList.NTamd64]\r
-%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232\r
-\r
-\r
-;------------------------------------------------------------------------------\r
-; 32 bit section for Windows 2000/2003/XP/Vista\r
-;------------------------------------------------------------------------------\r
-\r
-[DriverInstall.NTx86]\r
-include=mdmcpq.inf\r
-CopyFiles=DriverCopyFiles\r
-AddReg=DriverInstall.NTx86.AddReg\r
-\r
-[DriverCopyFiles]\r
-usbser.sys,,,0x20\r
-\r
-[DriverInstall.NTx86.AddReg]\r
-HKR,,DevLoader,,*ntkern\r
-HKR,,NTMPDriver,,usbser.sys\r
-HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"\r
-\r
-[DriverInstall.NTx86.Services]\r
-AddService=usbser, 0x00000002, DriverService\r
-\r
-;------------------------------------------------------------------------------\r
-; 64 bit section for Intel Itanium based systems\r
-;------------------------------------------------------------------------------\r
-\r
-[DriverInstall.NTia64]\r
-include=mdmcpq.inf\r
-CopyFiles=DriverCopyFiles\r
-AddReg=DriverInstall.NTia64.AddReg\r
-\r
-[DriverCopyFiles]\r
-usbser.sys,,,0x20\r
-\r
-[DriverInstall.NTia64.AddReg]\r
-HKR,,DevLoader,,*ntkern\r
-HKR,,NTMPDriver,,usbser.sys\r
-HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"\r
-\r
-[DriverInstall.NTia64.Services]\r
-AddService=usbser, 0x00000002, DriverService\r
-\r
-;------------------------------------------------------------------------------\r
-; 64 bit section for AMD64 and Intel EM64T based systems\r
-;------------------------------------------------------------------------------\r
-\r
-[DriverInstall.NTamd64]\r
-include=mdmcpq.inf\r
-CopyFiles=DriverCopyFiles\r
-AddReg=DriverInstall.NTamd64.AddReg\r
-\r
-[DriverCopyFiles]\r
-usbser.sys,,,0x20\r
-\r
-[DriverInstall.NTamd64.AddReg]\r
-HKR,,DevLoader,,*ntkern\r
-HKR,,NTMPDriver,,usbser.sys\r
-HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"\r
-\r
-[DriverInstall.NTamd64.Services]\r
-AddService=usbser, 0x00000002, DriverService\r
-\r
-;------------------------------------------------------------------------------\r
-;\r
-;------------------------------------------------------------------------------\r
-\r
-[DriverService]\r
-DisplayName=%SERVICE%\r
-ServiceType=1\r
-StartType=3\r
-ErrorControl=1\r
-ServiceBinary=%12%\usbser.sys\r
-\r
-;------------------------------------------------------------------------------\r
-; String Definitions\r
-;------------------------------------------------------------------------------\r
-\r
-[Strings]\r
-PROVIDER="Cypress"\r
-MFGNAME="Cypress Semiconductor Corporation"\r
-DESCRIPTION="Cypress USB UART"\r
-SERVICE="USB UART"\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_cls.c\r
-* Version 2.60\r
-*\r
-* Description:\r
-* USB Class request handler.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "USBFS_1.h"\r
-\r
-#if(USBFS_1_EXTERN_CLS == USBFS_1_FALSE)\r
-\r
-#include "USBFS_1_pvt.h"\r
-\r
-\r
-/***************************************\r
-* User Implemented Class Driver Declarations.\r
-***************************************/\r
-/* `#START USER_DEFINED_CLASS_DECLARATIONS` Place your declaration here */\r
-\r
-/* `#END` */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_DispatchClassRqst\r
-********************************************************************************\r
-* Summary:\r
-* This routine dispatches class specific requests depend on interface class.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* requestHandled.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_DispatchClassRqst(void) \r
-{\r
- uint8 requestHandled = USBFS_1_FALSE;\r
- uint8 interfaceNumber = 0u;\r
-\r
- switch(CY_GET_REG8(USBFS_1_bmRequestType) & USBFS_1_RQST_RCPT_MASK)\r
- {\r
- case USBFS_1_RQST_RCPT_IFC: /* Class-specific request directed to an interface */\r
- interfaceNumber = CY_GET_REG8(USBFS_1_wIndexLo); /* wIndexLo contain Interface number */\r
- break;\r
- case USBFS_1_RQST_RCPT_EP: /* Class-specific request directed to the endpoint */\r
- /* Find related interface to the endpoint, wIndexLo contain EP number */\r
- interfaceNumber =\r
- USBFS_1_EP[CY_GET_REG8(USBFS_1_wIndexLo) & USBFS_1_DIR_UNUSED].interface;\r
- break;\r
- default: /* RequestHandled is initialized as FALSE by default */\r
- break;\r
- }\r
- /* Handle Class request depend on interface type */\r
- switch(USBFS_1_interfaceClass[interfaceNumber])\r
- {\r
- case USBFS_1_CLASS_HID:\r
- #if defined(USBFS_1_ENABLE_HID_CLASS)\r
- requestHandled = USBFS_1_DispatchHIDClassRqst();\r
- #endif /* USBFS_1_ENABLE_HID_CLASS */\r
- break;\r
- case USBFS_1_CLASS_AUDIO:\r
- #if defined(USBFS_1_ENABLE_AUDIO_CLASS)\r
- requestHandled = USBFS_1_DispatchAUDIOClassRqst();\r
- #endif /* USBFS_1_ENABLE_HID_CLASS */\r
- break;\r
- case USBFS_1_CLASS_CDC:\r
- #if defined(USBFS_1_ENABLE_CDC_CLASS)\r
- requestHandled = USBFS_1_DispatchCDCClassRqst();\r
- #endif /* USBFS_1_ENABLE_CDC_CLASS */\r
- break;\r
- default: /* requestHandled is initialized as FALSE by default */\r
- break;\r
- }\r
-\r
- /* `#START USER_DEFINED_CLASS_CODE` Place your Class request here */\r
-\r
- /* `#END` */\r
-\r
- return(requestHandled);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Additional user functions supporting Class Specific Requests\r
-********************************************************************************/\r
-\r
-/* `#START CLASS_SPECIFIC_FUNCTIONS` Place any additional functions here */\r
-\r
-/* `#END` */\r
-\r
-#endif /* USBFS_1_EXTERN_CLS */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_descr.c\r
-* Version 2.60\r
-*\r
-* Description:\r
-* USB descriptors and storage.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "USBFS_1.h"\r
-#include "USBFS_1_pvt.h"\r
-\r
-\r
-/*****************************************************************************\r
-* User supplied descriptors. If you want to specify your own descriptors,\r
-* remove the comments around the define USER_SUPPLIED_DESCRIPTORS below and\r
-* add your descriptors.\r
-*****************************************************************************/\r
-/* `#START USER_DESCRIPTORS_DECLARATIONS` Place your declaration here */\r
-\r
-/* `#END` */\r
-\r
-\r
-/***************************************\r
-* USB Customizer Generated Descriptors\r
-***************************************/\r
-\r
-#if !defined(USER_SUPPLIED_DESCRIPTORS)\r
-/*********************************************************************\r
-* Device Descriptors\r
-*********************************************************************/\r
-const uint8 CYCODE USBFS_1_DEVICE0_DESCR[18u] = {\r
-/* Descriptor Length */ 0x12u,\r
-/* DescriptorType: DEVICE */ 0x01u,\r
-/* bcdUSB (ver 2.0) */ 0x00u, 0x02u,\r
-/* bDeviceClass */ 0x00u,\r
-/* bDeviceSubClass */ 0x00u,\r
-/* bDeviceProtocol */ 0x00u,\r
-/* bMaxPacketSize0 */ 0x08u,\r
-/* idVendor */ 0xB4u, 0x04u,\r
-/* idProduct */ 0x51u, 0x80u,\r
-/* bcdDevice */ 0x00u, 0x00u,\r
-/* iManufacturer */ 0x00u,\r
-/* iProduct */ 0x00u,\r
-/* iSerialNumber */ 0x00u,\r
-/* bNumConfigurations */ 0x01u\r
-};\r
-/*********************************************************************\r
-* Config Descriptor \r
-*********************************************************************/\r
-const uint8 CYCODE USBFS_1_DEVICE0_CONFIGURATION0_DESCR[25u] = {\r
-/* Config Descriptor Length */ 0x09u,\r
-/* DescriptorType: CONFIG */ 0x02u,\r
-/* wTotalLength */ 0x19u, 0x00u,\r
-/* bNumInterfaces */ 0x01u,\r
-/* bConfigurationValue */ 0x01u,\r
-/* iConfiguration */ 0x00u,\r
-/* bmAttributes */ 0xC0u,\r
-/* bMaxPower */ 0x00u,\r
-/*********************************************************************\r
-* Interface Descriptor\r
-*********************************************************************/\r
-/* Interface Descriptor Length */ 0x09u,\r
-/* DescriptorType: INTERFACE */ 0x04u,\r
-/* bInterfaceNumber */ 0x00u,\r
-/* bAlternateSetting */ 0x00u,\r
-/* bNumEndpoints */ 0x01u,\r
-/* bInterfaceClass */ 0x00u,\r
-/* bInterfaceSubClass */ 0x00u,\r
-/* bInterfaceProtocol */ 0x00u,\r
-/* iInterface */ 0x00u,\r
-/*********************************************************************\r
-* Endpoint Descriptor\r
-*********************************************************************/\r
-/* Endpoint Descriptor Length */ 0x07u,\r
-/* DescriptorType: ENDPOINT */ 0x05u,\r
-/* bEndpointAddress */ 0x01u,\r
-/* bmAttributes */ 0x02u,\r
-/* wMaxPacketSize */ 0x08u, 0x00u,\r
-/* bInterval */ 0x0Au\r
-};\r
-\r
-\r
-\r
-\r
-\r
-/*********************************************************************\r
-* Endpoint Setting Table -- This table contain the endpoint setting\r
-* for each endpoint in the configuration. It\r
-* contains the necessary information to\r
-* configure the endpoint hardware for each\r
-* interface and alternate setting.\r
-*********************************************************************/\r
-const T_USBFS_1_EP_SETTINGS_BLOCK CYCODE USBFS_1_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[1u] = {\r
-/* IFC ALT EPAddr bmAttr MaxPktSize Class ********************/\r
-{0x00u, 0x00u, 0x01u, 0x02u, 0x0008u, 0x00u}\r
-};\r
-const uint8 CYCODE USBFS_1_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[1u] = {\r
-0x00u\r
-};\r
-/*********************************************************************\r
-* Config Dispatch Table -- Points to the Config Descriptor and each of\r
-* and endpoint setup table and to each\r
-* interface table if it specifies a USB Class\r
-*********************************************************************/\r
-const T_USBFS_1_LUT CYCODE USBFS_1_DEVICE0_CONFIGURATION0_TABLE[4u] = {\r
- {0x01u, &USBFS_1_DEVICE0_CONFIGURATION0_DESCR},\r
- {0x01u, &USBFS_1_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE},\r
- {0x00u, NULL},\r
- {0x00u, &USBFS_1_DEVICE0_CONFIGURATION0_INTERFACE_CLASS}\r
-};\r
-/*********************************************************************\r
-* Device Dispatch Table -- Points to the Device Descriptor and each of\r
-* and Configuration Tables for this Device \r
-*********************************************************************/\r
-const T_USBFS_1_LUT CYCODE USBFS_1_DEVICE0_TABLE[2u] = {\r
- {0x01u, &USBFS_1_DEVICE0_DESCR},\r
- {0x01u, &USBFS_1_DEVICE0_CONFIGURATION0_TABLE}\r
-};\r
-/*********************************************************************\r
-* Device Table -- Indexed by the device number.\r
-*********************************************************************/\r
-const T_USBFS_1_LUT CYCODE USBFS_1_TABLE[1u] = {\r
- {0x01u, &USBFS_1_DEVICE0_TABLE}\r
-};\r
-\r
-#endif /* USER_SUPPLIED_DESCRIPTORS */\r
-\r
-#if defined(USBFS_1_ENABLE_MSOS_STRING)\r
-\r
- /******************************************************************************\r
- * USB Microsoft OS String Descriptor\r
- * "MSFT" identifies a Microsoft host\r
- * "100" specifies version 1.00\r
- * USBFS_1_GET_EXTENDED_CONFIG_DESCRIPTOR becomes the bRequest value\r
- * in a host vendor device/class request\r
- ******************************************************************************/\r
-\r
- const uint8 CYCODE USBFS_1_MSOS_DESCRIPTOR[USBFS_1_MSOS_DESCRIPTOR_LENGTH] = {\r
- /* Descriptor Length */ 0x12u,\r
- /* DescriptorType: STRING */ 0x03u,\r
- /* qwSignature - "MSFT100" */ (uint8)'M', 0u, (uint8)'S', 0u, (uint8)'F', 0u, (uint8)'T', 0u,\r
- (uint8)'1', 0u, (uint8)'0', 0u, (uint8)'0', 0u,\r
- /* bMS_VendorCode: */ USBFS_1_GET_EXTENDED_CONFIG_DESCRIPTOR,\r
- /* bPad */ 0x00u\r
- };\r
-\r
- /* Extended Configuration Descriptor */\r
-\r
- const uint8 CYCODE USBFS_1_MSOS_CONFIGURATION_DESCR[USBFS_1_MSOS_CONF_DESCR_LENGTH] = {\r
- /* Length of the descriptor 4 bytes */ 0x28u, 0x00u, 0x00u, 0x00u,\r
- /* Version of the descriptor 2 bytes */ 0x00u, 0x01u,\r
- /* wIndex - Fixed:INDEX_CONFIG_DESCRIPTOR */ 0x04u, 0x00u,\r
- /* bCount - Count of device functions. */ 0x01u,\r
- /* Reserved : 7 bytes */ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
- /* bFirstInterfaceNumber */ 0x00u,\r
- /* Reserved */ 0x01u,\r
- /* compatibleID - "CYUSB\0\0" */ (uint8)'C', (uint8)'Y', (uint8)'U', (uint8)'S', (uint8)'B',\r
- 0x00u, 0x00u, 0x00u,\r
- /* subcompatibleID - "00001\0\0" */ (uint8)'0', (uint8)'0', (uint8)'0', (uint8)'0', (uint8)'1',\r
- 0x00u, 0x00u, 0x00u,\r
- /* Reserved : 6 bytes */ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u\r
- };\r
-\r
-#endif /* USBFS_1_ENABLE_MSOS_STRING */\r
-\r
-/* DIE ID string descriptor for 8 bytes ID */\r
-#if defined(USBFS_1_ENABLE_IDSN_STRING)\r
- uint8 USBFS_1_idSerialNumberStringDescriptor[USBFS_1_IDSN_DESCR_LENGTH];\r
-#endif /* USBFS_1_ENABLE_IDSN_STRING */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_drv.c\r
-* Version 2.60\r
-*\r
-* Description:\r
-* Endpoint 0 Driver for the USBFS Component.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "USBFS_1.h"\r
-#include "USBFS_1_pvt.h"\r
-\r
-\r
-/***************************************\r
-* Global data allocation\r
-***************************************/\r
-\r
-volatile T_USBFS_1_EP_CTL_BLOCK USBFS_1_EP[USBFS_1_MAX_EP];\r
-volatile uint8 USBFS_1_configuration;\r
-volatile uint8 USBFS_1_interfaceNumber;\r
-volatile uint8 USBFS_1_configurationChanged;\r
-volatile uint8 USBFS_1_deviceAddress;\r
-volatile uint8 USBFS_1_deviceStatus;\r
-volatile uint8 USBFS_1_interfaceSetting[USBFS_1_MAX_INTERFACES_NUMBER];\r
-volatile uint8 USBFS_1_interfaceSetting_last[USBFS_1_MAX_INTERFACES_NUMBER];\r
-volatile uint8 USBFS_1_interfaceStatus[USBFS_1_MAX_INTERFACES_NUMBER];\r
-volatile uint8 USBFS_1_device;\r
-const uint8 CYCODE *USBFS_1_interfaceClass;\r
-\r
-\r
-/***************************************\r
-* Local data allocation\r
-***************************************/\r
-\r
-volatile uint8 USBFS_1_ep0Toggle;\r
-volatile uint8 USBFS_1_lastPacketSize;\r
-volatile uint8 USBFS_1_transferState;\r
-volatile T_USBFS_1_TD USBFS_1_currentTD;\r
-volatile uint8 USBFS_1_ep0Mode;\r
-volatile uint8 USBFS_1_ep0Count;\r
-volatile uint16 USBFS_1_transferByteCount;\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_ep_0_Interrupt\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This Interrupt Service Routine handles Endpoint 0 (Control Pipe) traffic.\r
-* It dispatches setup requests and handles the data and status stages.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-*******************************************************************************/\r
-CY_ISR(USBFS_1_EP_0_ISR)\r
-{\r
- uint8 bRegTemp;\r
- uint8 modifyReg;\r
-\r
-\r
- bRegTemp = CY_GET_REG8(USBFS_1_EP0_CR_PTR);\r
- if ((bRegTemp & USBFS_1_MODE_ACKD) != 0u)\r
- {\r
- modifyReg = 1u;\r
- if ((bRegTemp & USBFS_1_MODE_SETUP_RCVD) != 0u)\r
- {\r
- if((bRegTemp & USBFS_1_MODE_MASK) != USBFS_1_MODE_NAK_IN_OUT)\r
- {\r
- modifyReg = 0u; /* When mode not NAK_IN_OUT => invalid setup */\r
- }\r
- else\r
- {\r
- USBFS_1_HandleSetup();\r
- if((USBFS_1_ep0Mode & USBFS_1_MODE_SETUP_RCVD) != 0u)\r
- {\r
- modifyReg = 0u; /* if SETUP bit set -> exit without modifying the mode */\r
- }\r
-\r
- }\r
- }\r
- else if ((bRegTemp & USBFS_1_MODE_IN_RCVD) != 0u)\r
- {\r
- USBFS_1_HandleIN();\r
- }\r
- else if ((bRegTemp & USBFS_1_MODE_OUT_RCVD) != 0u)\r
- {\r
- USBFS_1_HandleOUT();\r
- }\r
- else\r
- {\r
- modifyReg = 0u;\r
- }\r
- if(modifyReg != 0u)\r
- {\r
- bRegTemp = CY_GET_REG8(USBFS_1_EP0_CR_PTR); /* unlock registers */\r
- if((bRegTemp & USBFS_1_MODE_SETUP_RCVD) == 0u) /* Check if SETUP bit is not set, otherwise exit */\r
- {\r
- /* Update the count register */\r
- bRegTemp = USBFS_1_ep0Toggle | USBFS_1_ep0Count;\r
- CY_SET_REG8(USBFS_1_EP0_CNT_PTR, bRegTemp);\r
- if(bRegTemp == CY_GET_REG8(USBFS_1_EP0_CNT_PTR)) /* continue if writing was successful */\r
- {\r
- do\r
- {\r
- modifyReg = USBFS_1_ep0Mode; /* Init temporary variable */\r
- /* Unlock registers */\r
- bRegTemp = CY_GET_REG8(USBFS_1_EP0_CR_PTR) & USBFS_1_MODE_SETUP_RCVD;\r
- if(bRegTemp == 0u) /* Check if SETUP bit is not set */\r
- {\r
- /* Set the Mode Register */\r
- CY_SET_REG8(USBFS_1_EP0_CR_PTR, USBFS_1_ep0Mode);\r
- /* Writing check */\r
- modifyReg = CY_GET_REG8(USBFS_1_EP0_CR_PTR) & USBFS_1_MODE_MASK;\r
- }\r
- }while(modifyReg != USBFS_1_ep0Mode); /* Repeat if writing was not successful */\r
- }\r
- }\r
- }\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_HandleSetup\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This Routine dispatches requests for the four USB request types\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_HandleSetup(void) \r
-{\r
- uint8 requestHandled;\r
-\r
- requestHandled = CY_GET_REG8(USBFS_1_EP0_CR_PTR); /* unlock registers */\r
- CY_SET_REG8(USBFS_1_EP0_CR_PTR, requestHandled); /* clear setup bit */\r
- requestHandled = CY_GET_REG8(USBFS_1_EP0_CR_PTR); /* reread register */\r
- if((requestHandled & USBFS_1_MODE_SETUP_RCVD) != 0u)\r
- {\r
- USBFS_1_ep0Mode = requestHandled; /* if SETUP bit set -> exit without modifying the mode */\r
- }\r
- else\r
- {\r
- /* In case the previous transfer did not complete, close it out */\r
- USBFS_1_UpdateStatusBlock(USBFS_1_XFER_PREMATURE);\r
-\r
- switch (CY_GET_REG8(USBFS_1_bmRequestType) & USBFS_1_RQST_TYPE_MASK)\r
- {\r
- case USBFS_1_RQST_TYPE_STD:\r
- requestHandled = USBFS_1_HandleStandardRqst();\r
- break;\r
- case USBFS_1_RQST_TYPE_CLS:\r
- requestHandled = USBFS_1_DispatchClassRqst();\r
- break;\r
- case USBFS_1_RQST_TYPE_VND:\r
- requestHandled = USBFS_1_HandleVendorRqst();\r
- break;\r
- default:\r
- requestHandled = USBFS_1_FALSE;\r
- break;\r
- }\r
- if (requestHandled == USBFS_1_FALSE)\r
- {\r
- USBFS_1_ep0Mode = USBFS_1_MODE_STALL_IN_OUT;\r
- }\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_HandleIN\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine handles EP0 IN transfers.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_HandleIN(void) \r
-{\r
- switch (USBFS_1_transferState)\r
- {\r
- case USBFS_1_TRANS_STATE_IDLE:\r
- break;\r
- case USBFS_1_TRANS_STATE_CONTROL_READ:\r
- USBFS_1_ControlReadDataStage();\r
- break;\r
- case USBFS_1_TRANS_STATE_CONTROL_WRITE:\r
- USBFS_1_ControlWriteStatusStage();\r
- break;\r
- case USBFS_1_TRANS_STATE_NO_DATA_CONTROL:\r
- USBFS_1_NoDataControlStatusStage();\r
- break;\r
- default: /* there are no more states */\r
- break;\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_HandleOUT\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine handles EP0 OUT transfers.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_HandleOUT(void) \r
-{\r
- switch (USBFS_1_transferState)\r
- {\r
- case USBFS_1_TRANS_STATE_IDLE:\r
- break;\r
- case USBFS_1_TRANS_STATE_CONTROL_READ:\r
- USBFS_1_ControlReadStatusStage();\r
- break;\r
- case USBFS_1_TRANS_STATE_CONTROL_WRITE:\r
- USBFS_1_ControlWriteDataStage();\r
- break;\r
- case USBFS_1_TRANS_STATE_NO_DATA_CONTROL:\r
- /* Update the completion block */\r
- USBFS_1_UpdateStatusBlock(USBFS_1_XFER_ERROR);\r
- /* We expect no more data, so stall INs and OUTs */\r
- USBFS_1_ep0Mode = USBFS_1_MODE_STALL_IN_OUT;\r
- break;\r
- default: /* There are no more states */\r
- break;\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_LoadEP0\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine loads the EP0 data registers for OUT transfers. It uses the\r
-* currentTD (previously initialized by the _InitControlWrite function and\r
-* updated for each OUT transfer, and the bLastPacketSize) to determine how\r
-* many uint8s to transfer on the current OUT.\r
-*\r
-* If the number of uint8s remaining is zero and the last transfer was full,\r
-* we need to send a zero length packet. Otherwise we send the minimum\r
-* of the control endpoint size (8) or remaining number of uint8s for the\r
-* transaction.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_1_transferByteCount - Update the transfer byte count from the\r
-* last transaction.\r
-* USBFS_1_ep0Count - counts the data loaded to the SIE memory in\r
-* current packet.\r
-* USBFS_1_lastPacketSize - remembers the USBFS_ep0Count value for the\r
-* next packet.\r
-* USBFS_1_transferByteCount - sum of the previous bytes transferred\r
-* on previous packets(sum of USBFS_lastPacketSize)\r
-* USBFS_1_ep0Toggle - inverted\r
-* USBFS_1_ep0Mode - prepare for mode register content.\r
-* USBFS_1_transferState - set to TRANS_STATE_CONTROL_READ\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_LoadEP0(void) \r
-{\r
- uint8 ep0Count = 0u;\r
-\r
- /* Update the transfer byte count from the last transaction */\r
- USBFS_1_transferByteCount += USBFS_1_lastPacketSize;\r
- /* Now load the next transaction */\r
- while ((USBFS_1_currentTD.count > 0u) && (ep0Count < 8u))\r
- {\r
- CY_SET_REG8((reg8 *)(USBFS_1_EP0_DR0_IND + ep0Count), *USBFS_1_currentTD.pData);\r
- USBFS_1_currentTD.pData = &USBFS_1_currentTD.pData[1u];\r
- ep0Count++;\r
- USBFS_1_currentTD.count--;\r
- }\r
- /* Support zero-length packet*/\r
- if( (USBFS_1_lastPacketSize == 8u) || (ep0Count > 0u) )\r
- {\r
- /* Update the data toggle */\r
- USBFS_1_ep0Toggle ^= USBFS_1_EP0_CNT_DATA_TOGGLE;\r
- /* Set the Mode Register */\r
- USBFS_1_ep0Mode = USBFS_1_MODE_ACK_IN_STATUS_OUT;\r
- /* Update the state (or stay the same) */\r
- USBFS_1_transferState = USBFS_1_TRANS_STATE_CONTROL_READ;\r
- }\r
- else\r
- {\r
- /* Expect Status Stage Out */\r
- USBFS_1_ep0Mode = USBFS_1_MODE_STATUS_OUT_ONLY;\r
- /* Update the state (or stay the same) */\r
- USBFS_1_transferState = USBFS_1_TRANS_STATE_CONTROL_READ;\r
- }\r
-\r
- /* Save the packet size for next time */\r
- USBFS_1_lastPacketSize = ep0Count;\r
- USBFS_1_ep0Count = ep0Count;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_InitControlRead\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Initialize a control read transaction, usable to send data to the host.\r
-* The following global variables should be initialized before this function\r
-* called. To send zero length packet use InitZeroLengthControlTransfer\r
-* function.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* requestHandled state.\r
-*\r
-* Global variables:\r
-* USBFS_1_currentTD.count - counts of data to be sent.\r
-* USBFS_1_currentTD.pData - data pointer.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_InitControlRead(void) \r
-{\r
- uint16 xferCount;\r
- if(USBFS_1_currentTD.count == 0u)\r
- {\r
- (void) USBFS_1_InitZeroLengthControlTransfer();\r
- }\r
- else\r
- {\r
- /* Set up the state machine */\r
- USBFS_1_transferState = USBFS_1_TRANS_STATE_CONTROL_READ;\r
- /* Set the toggle, it gets updated in LoadEP */\r
- USBFS_1_ep0Toggle = 0u;\r
- /* Initialize the Status Block */\r
- USBFS_1_InitializeStatusBlock();\r
- xferCount = (((uint16)CY_GET_REG8(USBFS_1_lengthHi) << 8u) | (CY_GET_REG8(USBFS_1_lengthLo)));\r
-\r
- if (USBFS_1_currentTD.count > xferCount)\r
- {\r
- USBFS_1_currentTD.count = xferCount;\r
- }\r
- USBFS_1_LoadEP0();\r
- }\r
-\r
- return(USBFS_1_TRUE);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_InitZeroLengthControlTransfer\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Initialize a zero length data IN transfer.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* requestHandled state.\r
-*\r
-* Global variables:\r
-* USBFS_1_ep0Toggle - set to EP0_CNT_DATA_TOGGLE\r
-* USBFS_1_ep0Mode - prepare for mode register content.\r
-* USBFS_1_transferState - set to TRANS_STATE_CONTROL_READ\r
-* USBFS_1_ep0Count - cleared, means the zero-length packet.\r
-* USBFS_1_lastPacketSize - cleared.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_InitZeroLengthControlTransfer(void)\r
- \r
-{\r
- /* Update the state */\r
- USBFS_1_transferState = USBFS_1_TRANS_STATE_CONTROL_READ;\r
- /* Set the data toggle */\r
- USBFS_1_ep0Toggle = USBFS_1_EP0_CNT_DATA_TOGGLE;\r
- /* Set the Mode Register */\r
- USBFS_1_ep0Mode = USBFS_1_MODE_ACK_IN_STATUS_OUT;\r
- /* Save the packet size for next time */\r
- USBFS_1_lastPacketSize = 0u;\r
- USBFS_1_ep0Count = 0u;\r
-\r
- return(USBFS_1_TRUE);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_ControlReadDataStage\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Handle the Data Stage of a control read transfer.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_ControlReadDataStage(void) \r
-\r
-{\r
- USBFS_1_LoadEP0();\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_ControlReadStatusStage\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Handle the Status Stage of a control read transfer.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_1_USBFS_transferByteCount - updated with last packet size.\r
-* USBFS_1_transferState - set to TRANS_STATE_IDLE.\r
-* USBFS_1_ep0Mode - set to MODE_STALL_IN_OUT.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_ControlReadStatusStage(void) \r
-{\r
- /* Update the transfer byte count */\r
- USBFS_1_transferByteCount += USBFS_1_lastPacketSize;\r
- /* Go Idle */\r
- USBFS_1_transferState = USBFS_1_TRANS_STATE_IDLE;\r
- /* Update the completion block */\r
- USBFS_1_UpdateStatusBlock(USBFS_1_XFER_STATUS_ACK);\r
- /* We expect no more data, so stall INs and OUTs */\r
- USBFS_1_ep0Mode = USBFS_1_MODE_STALL_IN_OUT;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_InitControlWrite\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Initialize a control write transaction\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* requestHandled state.\r
-*\r
-* Global variables:\r
-* USBFS_1_USBFS_transferState - set to TRANS_STATE_CONTROL_WRITE\r
-* USBFS_1_ep0Toggle - set to EP0_CNT_DATA_TOGGLE\r
-* USBFS_1_ep0Mode - set to MODE_ACK_OUT_STATUS_IN\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_InitControlWrite(void) \r
-{\r
- uint16 xferCount;\r
-\r
- /* Set up the state machine */\r
- USBFS_1_transferState = USBFS_1_TRANS_STATE_CONTROL_WRITE;\r
- /* This might not be necessary */\r
- USBFS_1_ep0Toggle = USBFS_1_EP0_CNT_DATA_TOGGLE;\r
- /* Initialize the Status Block */\r
- USBFS_1_InitializeStatusBlock();\r
-\r
- xferCount = (((uint16)CY_GET_REG8(USBFS_1_lengthHi) << 8u) | (CY_GET_REG8(USBFS_1_lengthLo)));\r
-\r
- if (USBFS_1_currentTD.count > xferCount)\r
- {\r
- USBFS_1_currentTD.count = xferCount;\r
- }\r
-\r
- /* Expect Data or Status Stage */\r
- USBFS_1_ep0Mode = USBFS_1_MODE_ACK_OUT_STATUS_IN;\r
-\r
- return(USBFS_1_TRUE);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_ControlWriteDataStage\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Handle the Data Stage of a control write transfer\r
-* 1. Get the data (We assume the destination was validated previously)\r
-* 2. Update the count and data toggle\r
-* 3. Update the mode register for the next transaction\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_1_transferByteCount - Update the transfer byte count from the\r
-* last transaction.\r
-* USBFS_1_ep0Count - counts the data loaded from the SIE memory\r
-* in current packet.\r
-* USBFS_1_transferByteCount - sum of the previous bytes transferred\r
-* on previous packets(sum of USBFS_lastPacketSize)\r
-* USBFS_1_ep0Toggle - inverted\r
-* USBFS_1_ep0Mode - set to MODE_ACK_OUT_STATUS_IN.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_ControlWriteDataStage(void) \r
-{\r
- uint8 ep0Count;\r
- uint8 regIndex = 0u;\r
-\r
- ep0Count = (CY_GET_REG8(USBFS_1_EP0_CNT_PTR) & USBFS_1_EPX_CNT0_MASK) -\r
- USBFS_1_EPX_CNTX_CRC_COUNT;\r
-\r
- USBFS_1_transferByteCount += ep0Count;\r
-\r
- while ((USBFS_1_currentTD.count > 0u) && (ep0Count > 0u))\r
- {\r
- *USBFS_1_currentTD.pData = CY_GET_REG8((reg8 *)(USBFS_1_EP0_DR0_IND + regIndex));\r
- USBFS_1_currentTD.pData = &USBFS_1_currentTD.pData[1u];\r
- regIndex++;\r
- ep0Count--;\r
- USBFS_1_currentTD.count--;\r
- }\r
- USBFS_1_ep0Count = ep0Count;\r
- /* Update the data toggle */\r
- USBFS_1_ep0Toggle ^= USBFS_1_EP0_CNT_DATA_TOGGLE;\r
- /* Expect Data or Status Stage */\r
- USBFS_1_ep0Mode = USBFS_1_MODE_ACK_OUT_STATUS_IN;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_ControlWriteStatusStage\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Handle the Status Stage of a control write transfer\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_1_transferState - set to TRANS_STATE_IDLE.\r
-* USBFS_1_USBFS_ep0Mode - set to MODE_STALL_IN_OUT.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_ControlWriteStatusStage(void) \r
-{\r
- /* Go Idle */\r
- USBFS_1_transferState = USBFS_1_TRANS_STATE_IDLE;\r
- /* Update the completion block */\r
- USBFS_1_UpdateStatusBlock(USBFS_1_XFER_STATUS_ACK);\r
- /* We expect no more data, so stall INs and OUTs */\r
- USBFS_1_ep0Mode = USBFS_1_MODE_STALL_IN_OUT;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_InitNoDataControlTransfer\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Initialize a no data control transfer\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* requestHandled state.\r
-*\r
-* Global variables:\r
-* USBFS_1_transferState - set to TRANS_STATE_NO_DATA_CONTROL.\r
-* USBFS_1_ep0Mode - set to MODE_STATUS_IN_ONLY.\r
-* USBFS_1_ep0Count - cleared.\r
-* USBFS_1_ep0Toggle - set to EP0_CNT_DATA_TOGGLE\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_InitNoDataControlTransfer(void) \r
-{\r
- USBFS_1_transferState = USBFS_1_TRANS_STATE_NO_DATA_CONTROL;\r
- USBFS_1_ep0Mode = USBFS_1_MODE_STATUS_IN_ONLY;\r
- USBFS_1_ep0Toggle = USBFS_1_EP0_CNT_DATA_TOGGLE;\r
- USBFS_1_ep0Count = 0u;\r
-\r
- return(USBFS_1_TRUE);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_NoDataControlStatusStage\r
-********************************************************************************\r
-* Summary:\r
-* Handle the Status Stage of a no data control transfer.\r
-*\r
-* SET_ADDRESS is special, since we need to receive the status stage with\r
-* the old address.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_1_transferState - set to TRANS_STATE_IDLE.\r
-* USBFS_1_ep0Mode - set to MODE_STALL_IN_OUT.\r
-* USBFS_1_ep0Toggle - set to EP0_CNT_DATA_TOGGLE\r
-* USBFS_1_deviceAddress - used to set new address and cleared\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_NoDataControlStatusStage(void) \r
-{\r
- /* Change the USB address register if we got a SET_ADDRESS. */\r
- if (USBFS_1_deviceAddress != 0u)\r
- {\r
- CY_SET_REG8(USBFS_1_CR0_PTR, USBFS_1_deviceAddress | USBFS_1_CR0_ENABLE);\r
- USBFS_1_deviceAddress = 0u;\r
- }\r
- /* Go Idle */\r
- USBFS_1_transferState = USBFS_1_TRANS_STATE_IDLE;\r
- /* Update the completion block */\r
- USBFS_1_UpdateStatusBlock(USBFS_1_XFER_STATUS_ACK);\r
- /* We expect no more data, so stall INs and OUTs */\r
- USBFS_1_ep0Mode = USBFS_1_MODE_STALL_IN_OUT;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_UpdateStatusBlock\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Update the Completion Status Block for a Request. The block is updated\r
-* with the completion code the USBFS_1_transferByteCount. The\r
-* StatusBlock Pointer is set to NULL.\r
-*\r
-* Parameters:\r
-* completionCode - status.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_1_currentTD.pStatusBlock->status - updated by the\r
-* completionCode parameter.\r
-* USBFS_1_currentTD.pStatusBlock->length - updated.\r
-* USBFS_1_currentTD.pStatusBlock - cleared.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_UpdateStatusBlock(uint8 completionCode) \r
-{\r
- if (USBFS_1_currentTD.pStatusBlock != NULL)\r
- {\r
- USBFS_1_currentTD.pStatusBlock->status = completionCode;\r
- USBFS_1_currentTD.pStatusBlock->length = USBFS_1_transferByteCount;\r
- USBFS_1_currentTD.pStatusBlock = NULL;\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_InitializeStatusBlock\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Initialize the Completion Status Block for a Request. The completion\r
-* code is set to USB_XFER_IDLE.\r
-*\r
-* Also, initializes USBFS_1_transferByteCount. Save some space,\r
-* this is the only consumer.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_1_currentTD.pStatusBlock->status - set to XFER_IDLE.\r
-* USBFS_1_currentTD.pStatusBlock->length - cleared.\r
-* USBFS_1_transferByteCount - cleared.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_InitializeStatusBlock(void) \r
-{\r
- USBFS_1_transferByteCount = 0u;\r
- if(USBFS_1_currentTD.pStatusBlock != NULL)\r
- {\r
- USBFS_1_currentTD.pStatusBlock->status = USBFS_1_XFER_IDLE;\r
- USBFS_1_currentTD.pStatusBlock->length = 0u;\r
- }\r
-}\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_episr.c\r
-* Version 2.60\r
-*\r
-* Description:\r
-* Data endpoint Interrupt Service Routines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "USBFS_1.h"\r
-#include "USBFS_1_pvt.h"\r
-#if defined(USBFS_1_ENABLE_MIDI_STREAMING) && (USBFS_1_ENABLE_MIDI_API != 0u)\r
- #include "USBFS_1_midi.h"\r
-#endif /* End USBFS_1_ENABLE_MIDI_STREAMING*/\r
-\r
-\r
-/***************************************\r
-* Custom Declarations\r
-***************************************/\r
-/* `#START CUSTOM_DECLARATIONS` Place your declaration here */\r
-\r
-/* `#END` */\r
-\r
-\r
-#if(USBFS_1_EP1_ISR_REMOVE == 0u)\r
-\r
-\r
- /******************************************************************************\r
- * Function Name: USBFS_1_EP_1_ISR\r
- *******************************************************************************\r
- *\r
- * Summary:\r
- * Endpoint 1 Interrupt Service Routine\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- ******************************************************************************/\r
- CY_ISR(USBFS_1_EP_1_ISR)\r
- {\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
-\r
- /* `#START EP1_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
-\r
- CY_GET_REG8(USBFS_1_SIE_EP1_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_1_EP[USBFS_1_EP1].attrib & USBFS_1_EP_TYPE_MASK) !=\r
- USBFS_1_EP_TYPE_ISOC)\r
- {\r
- USBFS_1_EP[USBFS_1_EP1].epToggle ^= USBFS_1_EPX_CNT_DATA_TOGGLE;\r
- }\r
- USBFS_1_EP[USBFS_1_EP1].apiEpState = USBFS_1_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_1_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_1_SIE_EP_INT_SR_PTR) &\r
- (uint8)~USBFS_1_SIE_EP_INT_EP1_MASK);\r
-\r
- #if( defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT )\r
- if(USBFS_1_midi_out_ep == USBFS_1_EP1)\r
- {\r
- USBFS_1_MIDI_OUT_EP_Service();\r
- }\r
- #endif /* End USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- /* `#START EP1_END_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- #if ( defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )\r
- EA = int_en;\r
- #endif /* USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
- }\r
-\r
-#endif /* End USBFS_1_EP1_ISR_REMOVE */\r
-\r
-\r
-#if(USBFS_1_EP2_ISR_REMOVE == 0u)\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_EP_2_ISR\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Endpoint 2 Interrupt Service Routine\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- *******************************************************************************/\r
- CY_ISR(USBFS_1_EP_2_ISR)\r
- {\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
-\r
- /* `#START EP2_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
-\r
- CY_GET_REG8(USBFS_1_SIE_EP2_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_1_EP[USBFS_1_EP2].attrib & USBFS_1_EP_TYPE_MASK) !=\r
- USBFS_1_EP_TYPE_ISOC)\r
- {\r
- USBFS_1_EP[USBFS_1_EP2].epToggle ^= USBFS_1_EPX_CNT_DATA_TOGGLE;\r
- }\r
- USBFS_1_EP[USBFS_1_EP2].apiEpState = USBFS_1_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_1_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_1_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_1_SIE_EP_INT_EP2_MASK);\r
-\r
- #if( defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT )\r
- if(USBFS_1_midi_out_ep == USBFS_1_EP2)\r
- {\r
- USBFS_1_MIDI_OUT_EP_Service();\r
- }\r
- #endif /* End USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- /* `#START EP2_END_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
- }\r
-\r
-#endif /* End USBFS_1_EP2_ISR_REMOVE */\r
-\r
-\r
-#if(USBFS_1_EP3_ISR_REMOVE == 0u)\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_EP_3_ISR\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Endpoint 3 Interrupt Service Routine\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- *******************************************************************************/\r
- CY_ISR(USBFS_1_EP_3_ISR)\r
- {\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
-\r
- /* `#START EP3_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- CY_GET_REG8(USBFS_1_SIE_EP3_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_1_EP[USBFS_1_EP3].attrib & USBFS_1_EP_TYPE_MASK) !=\r
- USBFS_1_EP_TYPE_ISOC)\r
- {\r
- USBFS_1_EP[USBFS_1_EP3].epToggle ^= USBFS_1_EPX_CNT_DATA_TOGGLE;\r
- }\r
- USBFS_1_EP[USBFS_1_EP3].apiEpState = USBFS_1_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_1_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_1_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_1_SIE_EP_INT_EP3_MASK);\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_1_midi_out_ep == USBFS_1_EP3)\r
- {\r
- USBFS_1_MIDI_OUT_EP_Service();\r
- }\r
- #endif /* End USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- /* `#START EP3_END_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_1_ISR_SERVICE_MIDI_OUT */\r
- }\r
-\r
-#endif /* End USBFS_1_EP3_ISR_REMOVE */\r
-\r
-\r
-#if(USBFS_1_EP4_ISR_REMOVE == 0u)\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_EP_4_ISR\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Endpoint 4 Interrupt Service Routine\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- *******************************************************************************/\r
- CY_ISR(USBFS_1_EP_4_ISR)\r
- {\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* CY_PSOC3 & USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- /* `#START EP4_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- CY_GET_REG8(USBFS_1_SIE_EP4_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_1_EP[USBFS_1_EP4].attrib & USBFS_1_EP_TYPE_MASK) !=\r
- USBFS_1_EP_TYPE_ISOC)\r
- {\r
- USBFS_1_EP[USBFS_1_EP4].epToggle ^= USBFS_1_EPX_CNT_DATA_TOGGLE;\r
- }\r
- USBFS_1_EP[USBFS_1_EP4].apiEpState = USBFS_1_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_1_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_1_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_1_SIE_EP_INT_EP4_MASK);\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_1_midi_out_ep == USBFS_1_EP4)\r
- {\r
- USBFS_1_MIDI_OUT_EP_Service();\r
- }\r
- #endif /* End USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- /* `#START EP4_END_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_1_ISR_SERVICE_MIDI_OUT */\r
- }\r
-\r
-#endif /* End USBFS_1_EP4_ISR_REMOVE */\r
-\r
-\r
-#if(USBFS_1_EP5_ISR_REMOVE == 0u)\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_EP_5_ISR\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Endpoint 5 Interrupt Service Routine\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- *******************************************************************************/\r
- CY_ISR(USBFS_1_EP_5_ISR)\r
- {\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* CY_PSOC3 & USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- /* `#START EP5_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- CY_GET_REG8(USBFS_1_SIE_EP5_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_1_EP[USBFS_1_EP5].attrib & USBFS_1_EP_TYPE_MASK) !=\r
- USBFS_1_EP_TYPE_ISOC)\r
- {\r
- USBFS_1_EP[USBFS_1_EP5].epToggle ^= USBFS_1_EPX_CNT_DATA_TOGGLE;\r
- }\r
- USBFS_1_EP[USBFS_1_EP5].apiEpState = USBFS_1_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_1_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_1_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_1_SIE_EP_INT_EP5_MASK);\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_1_midi_out_ep == USBFS_1_EP5)\r
- {\r
- USBFS_1_MIDI_OUT_EP_Service();\r
- }\r
- #endif /* End USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- /* `#START EP5_END_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_1_ISR_SERVICE_MIDI_OUT */\r
- }\r
-#endif /* End USBFS_1_EP5_ISR_REMOVE */\r
-\r
-\r
-#if(USBFS_1_EP6_ISR_REMOVE == 0u)\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_EP_6_ISR\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Endpoint 6 Interrupt Service Routine\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- *******************************************************************************/\r
- CY_ISR(USBFS_1_EP_6_ISR)\r
- {\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* CY_PSOC3 & USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- /* `#START EP6_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- CY_GET_REG8(USBFS_1_SIE_EP6_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_1_EP[USBFS_1_EP6].attrib & USBFS_1_EP_TYPE_MASK) !=\r
- USBFS_1_EP_TYPE_ISOC)\r
- {\r
- USBFS_1_EP[USBFS_1_EP6].epToggle ^= USBFS_1_EPX_CNT_DATA_TOGGLE;\r
- }\r
- USBFS_1_EP[USBFS_1_EP6].apiEpState = USBFS_1_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_1_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_1_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_1_SIE_EP_INT_EP6_MASK);\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_1_midi_out_ep == USBFS_1_EP6)\r
- {\r
- USBFS_1_MIDI_OUT_EP_Service();\r
- }\r
- #endif /* End USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- /* `#START EP6_END_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_1_ISR_SERVICE_MIDI_OUT */\r
- }\r
-\r
-#endif /* End USBFS_1_EP6_ISR_REMOVE */\r
-\r
-\r
-#if(USBFS_1_EP7_ISR_REMOVE == 0u)\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_EP_7_ISR\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Endpoint 7 Interrupt Service Routine\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- *******************************************************************************/\r
- CY_ISR(USBFS_1_EP_7_ISR)\r
- {\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* CY_PSOC3 & USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- /* `#START EP7_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- CY_GET_REG8(USBFS_1_SIE_EP7_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_1_EP[USBFS_1_EP7].attrib & USBFS_1_EP_TYPE_MASK) !=\r
- USBFS_1_EP_TYPE_ISOC)\r
- {\r
- USBFS_1_EP[USBFS_1_EP7].epToggle ^= USBFS_1_EPX_CNT_DATA_TOGGLE;\r
- }\r
- USBFS_1_EP[USBFS_1_EP7].apiEpState = USBFS_1_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_1_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_1_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_1_SIE_EP_INT_EP7_MASK);\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_1_midi_out_ep == USBFS_1_EP7)\r
- {\r
- USBFS_1_MIDI_OUT_EP_Service();\r
- }\r
- #endif /* End USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- /* `#START EP7_END_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_1_ISR_SERVICE_MIDI_OUT */\r
- }\r
-\r
-#endif /* End USBFS_1_EP7_ISR_REMOVE */\r
-\r
-\r
-#if(USBFS_1_EP8_ISR_REMOVE == 0u)\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_EP_8_ISR\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Endpoint 8 Interrupt Service Routine\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- *******************************************************************************/\r
- CY_ISR(USBFS_1_EP_8_ISR)\r
- {\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- uint8 int_en;\r
- #endif /* CY_PSOC3 & USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- /* `#START EP8_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- int_en = EA;\r
- CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
- #endif /* CY_PSOC3 & USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- CY_GET_REG8(USBFS_1_SIE_EP8_CR0_PTR); /* Must read the mode reg */\r
- /* Do not toggle ISOC endpoint */\r
- if((USBFS_1_EP[USBFS_1_EP8].attrib & USBFS_1_EP_TYPE_MASK) !=\r
- USBFS_1_EP_TYPE_ISOC)\r
- {\r
- USBFS_1_EP[USBFS_1_EP8].epToggle ^= USBFS_1_EPX_CNT_DATA_TOGGLE;\r
- }\r
- USBFS_1_EP[USBFS_1_EP8].apiEpState = USBFS_1_EVENT_PENDING;\r
- CY_SET_REG8(USBFS_1_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_1_SIE_EP_INT_SR_PTR)\r
- & (uint8)~USBFS_1_SIE_EP_INT_EP8_MASK);\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT)\r
- if(USBFS_1_midi_out_ep == USBFS_1_EP8)\r
- {\r
- USBFS_1_MIDI_OUT_EP_Service();\r
- }\r
- #endif /* End USBFS_1_ISR_SERVICE_MIDI_OUT */\r
-\r
- /* `#START EP8_END_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
- EA = int_en;\r
- #endif /* CY_PSOC3 & USBFS_1_ISR_SERVICE_MIDI_OUT */\r
- }\r
-\r
-#endif /* End USBFS_1_EP8_ISR_REMOVE */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_SOF_ISR\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Start of Frame Interrupt Service Routine\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-*******************************************************************************/\r
-CY_ISR(USBFS_1_SOF_ISR)\r
-{\r
- /* `#START SOF_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_BUS_RESET_ISR\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* USB Bus Reset Interrupt Service Routine. Calls _Start with the same\r
-* parameters as the last USER call to _Start\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-*******************************************************************************/\r
-CY_ISR(USBFS_1_BUS_RESET_ISR)\r
-{\r
- /* `#START BUS_RESET_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- USBFS_1_ReInitComponent();\r
-}\r
-\r
-\r
-#if((USBFS_1_EP_MM != USBFS_1__EP_MANUAL) && (USBFS_1_ARB_ISR_REMOVE == 0u))\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_ARB_ISR\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Arbiter Interrupt Service Routine\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Side effect:\r
- * Search for EP8 int_status will be much slower than search for EP1 int_status.\r
- *\r
- *******************************************************************************/\r
- CY_ISR(USBFS_1_ARB_ISR)\r
- {\r
- uint8 int_status;\r
- uint8 ep_status;\r
- uint8 ep = USBFS_1_EP1;\r
- uint8 ptr = 0u;\r
-\r
- /* `#START ARB_BEGIN_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- int_status = USBFS_1_ARB_INT_SR_REG; /* read Arbiter Status Register */\r
- USBFS_1_ARB_INT_SR_REG = int_status; /* Clear Serviced Interrupts */\r
-\r
- while(int_status != 0u)\r
- {\r
- if((int_status & 1u) != 0u) /* If EpX interrupt present */\r
- { /* read Endpoint Status Register */\r
- ep_status = CY_GET_REG8((reg8 *)(USBFS_1_ARB_EP1_SR_IND + ptr));\r
- /* If In Buffer Full */\r
- if((ep_status & USBFS_1_ARB_EPX_SR_IN_BUF_FULL) != 0u)\r
- {\r
- if((USBFS_1_EP[ep].addr & USBFS_1_DIR_IN) != 0u)\r
- {\r
- /* Clear Data ready status */\r
- *(reg8 *)(USBFS_1_ARB_EP1_CFG_IND + ptr) &=\r
- (uint8)~USBFS_1_ARB_EPX_CFG_IN_DATA_RDY;\r
- /* Write the Mode register */\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ptr), USBFS_1_EP[ep].epMode);\r
- #if (defined(USBFS_1_ENABLE_MIDI_STREAMING) && USBFS_1_ISR_SERVICE_MIDI_IN)\r
- if(ep == USBFS_1_midi_in_ep)\r
- { /* Clear MIDI input pointer */\r
- USBFS_1_midiInPointer = 0u;\r
- }\r
- #endif /* End USBFS_1_ENABLE_MIDI_STREAMING*/\r
- }\r
- }\r
- /* (re)arm Out EP only for mode2 */\r
- #if(USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO)\r
- /* If DMA Grant */\r
- if((ep_status & USBFS_1_ARB_EPX_SR_DMA_GNT) != 0u)\r
- {\r
- if((USBFS_1_EP[ep].addr & USBFS_1_DIR_IN) == 0u)\r
- {\r
- USBFS_1_EP[ep].apiEpState = USBFS_1_NO_EVENT_PENDING;\r
- /* Write the Mode register */\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ptr),\r
- USBFS_1_EP[ep].epMode);\r
- }\r
- }\r
- #endif /* End USBFS_1_EP_MM */\r
-\r
- /* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */\r
-\r
- /* `#END` */\r
-\r
- CY_SET_REG8((reg8 *)(USBFS_1_ARB_EP1_SR_IND + ptr), ep_status); /* Clear Serviced events */\r
- }\r
- ptr += USBFS_1_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */\r
- ep++;\r
- int_status >>= 1u;\r
- }\r
-\r
- /* `#START ARB_END_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
- }\r
-\r
-#endif /* End USBFS_1_EP_MM */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_hid.c\r
-* Version 2.60\r
-*\r
-* Description:\r
-* USB HID Class request handler.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "USBFS_1.h"\r
-\r
-#if defined(USBFS_1_ENABLE_HID_CLASS)\r
-\r
-#include "USBFS_1_pvt.h"\r
-#include "USBFS_1_hid.h"\r
-\r
-\r
-/***************************************\r
-* HID Variables\r
-***************************************/\r
-\r
-volatile uint8 USBFS_1_hidProtocol[USBFS_1_MAX_INTERFACES_NUMBER]; /* HID device protocol status */\r
-volatile uint8 USBFS_1_hidIdleRate[USBFS_1_MAX_INTERFACES_NUMBER]; /* HID device idle reload value */\r
-volatile uint8 USBFS_1_hidIdleTimer[USBFS_1_MAX_INTERFACES_NUMBER]; /* HID device idle rate value */\r
-\r
-\r
-/***************************************\r
-* Custom Declarations\r
-***************************************/\r
-\r
-/* `#START HID_CUSTOM_DECLARATIONS` Place your declaration here */\r
-\r
-/* `#END` */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_UpdateHIDTimer\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Updates the HID report timer and reloads it if expired\r
-*\r
-* Parameters:\r
-* interface: Interface Number.\r
-*\r
-* Return:\r
-* status.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_UpdateHIDTimer(uint8 interface) \r
-{\r
- uint8 stat = USBFS_1_IDLE_TIMER_INDEFINITE;\r
-\r
- if(USBFS_1_hidIdleRate[interface] != 0u)\r
- {\r
- if(USBFS_1_hidIdleTimer[interface] > 0u)\r
- {\r
- USBFS_1_hidIdleTimer[interface]--;\r
- stat = USBFS_1_IDLE_TIMER_RUNNING;\r
- }\r
- else\r
- {\r
- USBFS_1_hidIdleTimer[interface] = USBFS_1_hidIdleRate[interface];\r
- stat = USBFS_1_IDLE_TIMER_EXPIRED;\r
- }\r
- }\r
-\r
- return(stat);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_GetProtocol\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Returns the selected protocol value to the application\r
-*\r
-* Parameters:\r
-* interface: Interface Number.\r
-*\r
-* Return:\r
-* Interface protocol.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_GetProtocol(uint8 interface) \r
-{\r
- return(USBFS_1_hidProtocol[interface]);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_DispatchHIDClassRqst\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine dispatches class requests\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* requestHandled\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_DispatchHIDClassRqst(void) \r
-{\r
- uint8 requestHandled = USBFS_1_FALSE;\r
- uint8 interfaceNumber;\r
-\r
- interfaceNumber = CY_GET_REG8(USBFS_1_wIndexLo);\r
- if ((CY_GET_REG8(USBFS_1_bmRequestType) & USBFS_1_RQST_DIR_MASK) == USBFS_1_RQST_DIR_D2H)\r
- { /* Control Read */\r
- switch (CY_GET_REG8(USBFS_1_bRequest))\r
- {\r
- case USBFS_1_GET_DESCRIPTOR:\r
- if (CY_GET_REG8(USBFS_1_wValueHi) == USBFS_1_DESCR_HID_CLASS)\r
- {\r
- USBFS_1_FindHidClassDecriptor();\r
- if (USBFS_1_currentTD.count != 0u)\r
- {\r
- requestHandled = USBFS_1_InitControlRead();\r
- }\r
- }\r
- else if (CY_GET_REG8(USBFS_1_wValueHi) == USBFS_1_DESCR_HID_REPORT)\r
- {\r
- USBFS_1_FindReportDescriptor();\r
- if (USBFS_1_currentTD.count != 0u)\r
- {\r
- requestHandled = USBFS_1_InitControlRead();\r
- }\r
- }\r
- else\r
- { /* requestHandled is initialezed as FALSE by default */\r
- }\r
- break;\r
- case USBFS_1_HID_GET_REPORT:\r
- USBFS_1_FindReport();\r
- if (USBFS_1_currentTD.count != 0u)\r
- {\r
- requestHandled = USBFS_1_InitControlRead();\r
- }\r
- break;\r
-\r
- case USBFS_1_HID_GET_IDLE:\r
- /* This function does not support multiple reports per interface*/\r
- /* Validate interfaceNumber and Report ID (should be 0) */\r
- if( (interfaceNumber < USBFS_1_MAX_INTERFACES_NUMBER) &&\r
- (CY_GET_REG8(USBFS_1_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */\r
- {\r
- USBFS_1_currentTD.count = 1u;\r
- USBFS_1_currentTD.pData = &USBFS_1_hidIdleRate[interfaceNumber];\r
- requestHandled = USBFS_1_InitControlRead();\r
- }\r
- break;\r
- case USBFS_1_HID_GET_PROTOCOL:\r
- /* Validate interfaceNumber */\r
- if( interfaceNumber < USBFS_1_MAX_INTERFACES_NUMBER)\r
- {\r
- USBFS_1_currentTD.count = 1u;\r
- USBFS_1_currentTD.pData = &USBFS_1_hidProtocol[interfaceNumber];\r
- requestHandled = USBFS_1_InitControlRead();\r
- }\r
- break;\r
- default: /* requestHandled is initialized as FALSE by default */\r
- break;\r
- }\r
- }\r
- else if ((CY_GET_REG8(USBFS_1_bmRequestType) & USBFS_1_RQST_DIR_MASK) ==\r
- USBFS_1_RQST_DIR_H2D)\r
- { /* Control Write */\r
- switch (CY_GET_REG8(USBFS_1_bRequest))\r
- {\r
- case USBFS_1_HID_SET_REPORT:\r
- USBFS_1_FindReport();\r
- if (USBFS_1_currentTD.count != 0u)\r
- {\r
- requestHandled = USBFS_1_InitControlWrite();\r
- }\r
- break;\r
- case USBFS_1_HID_SET_IDLE:\r
- /* This function does not support multiple reports per interface */\r
- /* Validate interfaceNumber and Report ID (should be 0) */\r
- if( (interfaceNumber < USBFS_1_MAX_INTERFACES_NUMBER) &&\r
- (CY_GET_REG8(USBFS_1_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */\r
- {\r
- USBFS_1_hidIdleRate[interfaceNumber] = CY_GET_REG8(USBFS_1_wValueHi);\r
- /* With regards to HID spec: "7.2.4 Set_Idle Request"\r
- * Latency. If the current period has gone past the\r
- * newly proscribed time duration, then a report\r
- * will be generated immediately.\r
- */\r
- if(USBFS_1_hidIdleRate[interfaceNumber] <\r
- USBFS_1_hidIdleTimer[interfaceNumber])\r
- {\r
- /* Set the timer to zero and let the UpdateHIDTimer() API return IDLE_TIMER_EXPIRED status*/\r
- USBFS_1_hidIdleTimer[interfaceNumber] = 0u;\r
- }\r
- /* If the new request is received within 4 milliseconds\r
- * (1 count) of the end of the current period, then the\r
- * new request will have no effect until after the report.\r
- */\r
- else if(USBFS_1_hidIdleTimer[interfaceNumber] <= 1u)\r
- {\r
- /* Do nothing.\r
- * Let the UpdateHIDTimer() API continue to work and\r
- * return IDLE_TIMER_EXPIRED status\r
- */\r
- }\r
- else\r
- { /* Reload the timer*/\r
- USBFS_1_hidIdleTimer[interfaceNumber] =\r
- USBFS_1_hidIdleRate[interfaceNumber];\r
- }\r
- requestHandled = USBFS_1_InitNoDataControlTransfer();\r
- }\r
- break;\r
-\r
- case USBFS_1_HID_SET_PROTOCOL:\r
- /* Validate interfaceNumber and protocol (must be 0 or 1) */\r
- if( (interfaceNumber < USBFS_1_MAX_INTERFACES_NUMBER) &&\r
- (CY_GET_REG8(USBFS_1_wValueLo) <= 1u) )\r
- {\r
- USBFS_1_hidProtocol[interfaceNumber] = CY_GET_REG8(USBFS_1_wValueLo);\r
- requestHandled = USBFS_1_InitNoDataControlTransfer();\r
- }\r
- break;\r
- default: /* requestHandled is initialized as FALSE by default */\r
- break;\r
- }\r
- }\r
- else\r
- { /* requestHandled is initialized as FALSE by default */\r
- }\r
-\r
- return(requestHandled);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USB_FindHidClassDescriptor\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine find Hid Class Descriptor pointer based on the Interface number\r
-* and Alternate setting then loads the currentTD structure with the address of\r
-* the buffer and the size.\r
-* The HID Class Descriptor resides inside the config descriptor.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* currentTD\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_FindHidClassDecriptor(void) \r
-{\r
- const T_USBFS_1_LUT CYCODE *pTmp;\r
- volatile uint8 *pDescr;\r
- uint8 interfaceN;\r
-\r
- pTmp = USBFS_1_GetConfigTablePtr(USBFS_1_configuration - 1u);\r
- interfaceN = CY_GET_REG8(USBFS_1_wIndexLo);\r
- /* Third entry in the LUT starts the Interface Table pointers */\r
- /* Now use the request interface number*/\r
- pTmp = &pTmp[interfaceN + 2u];\r
- /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */\r
- pTmp = (const T_USBFS_1_LUT CYCODE *) pTmp->p_list;\r
- /* Now use Alternate setting number */\r
- pTmp = &pTmp[USBFS_1_interfaceSetting[interfaceN]];\r
- /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */\r
- pTmp = (const T_USBFS_1_LUT CYCODE *) pTmp->p_list;\r
- /* Fifth entry in the LUT points to Hid Class Descriptor in Configuration Descriptor */\r
- pTmp = &pTmp[4u];\r
- pDescr = (volatile uint8 *)pTmp->p_list;\r
- /* The first byte contains the descriptor length */\r
- USBFS_1_currentTD.count = *pDescr;\r
- USBFS_1_currentTD.pData = pDescr;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USB_FindReportDescriptor\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine find Hid Report Descriptor pointer based on the Interface\r
-* number, then loads the currentTD structure with the address of the buffer\r
-* and the size.\r
-* Hid Report Descriptor is located after IN/OUT/FEATURE reports.\r
-*\r
-* Parameters:\r
-* void\r
-*\r
-* Return:\r
-* currentTD\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_FindReportDescriptor(void) \r
-{\r
- const T_USBFS_1_LUT CYCODE *pTmp;\r
- volatile uint8 *pDescr;\r
- uint8 interfaceN;\r
-\r
- pTmp = USBFS_1_GetConfigTablePtr(USBFS_1_configuration - 1u);\r
- interfaceN = CY_GET_REG8(USBFS_1_wIndexLo);\r
- /* Third entry in the LUT starts the Interface Table pointers */\r
- /* Now use the request interface number */\r
- pTmp = &pTmp[interfaceN + 2u];\r
- /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */\r
- pTmp = (const T_USBFS_1_LUT CYCODE *) pTmp->p_list;\r
- /* Now use Alternate setting number */\r
- pTmp = &pTmp[USBFS_1_interfaceSetting[interfaceN]];\r
- /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */\r
- pTmp = (const T_USBFS_1_LUT CYCODE *) pTmp->p_list;\r
- /* Fourth entry in the LUT starts the Hid Report Descriptor */\r
- pTmp = &pTmp[3u];\r
- pDescr = (volatile uint8 *)pTmp->p_list;\r
- /* The 1st and 2nd bytes of descriptor contain its length. LSB is 1st. */\r
- USBFS_1_currentTD.count = (((uint16)pDescr[1u] << 8u) | pDescr[0u]);\r
- USBFS_1_currentTD.pData = &pDescr[2u];\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_FindReport\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine sets up a transfer based on the Interface number, Report Type\r
-* and Report ID, then loads the currentTD structure with the address of the\r
-* buffer and the size. The caller has to decide if it is a control read or\r
-* control write.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* currentTD\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_FindReport(void) \r
-{\r
- const T_USBFS_1_LUT CYCODE *pTmp;\r
- T_USBFS_1_TD *pTD;\r
- uint8 interfaceN;\r
- uint8 reportType;\r
-\r
- /* `#START HID_FINDREPORT` Place custom handling here */\r
-\r
- /* `#END` */\r
- USBFS_1_currentTD.count = 0u; /* Init not supported condition */\r
- pTmp = USBFS_1_GetConfigTablePtr(USBFS_1_configuration - 1u);\r
- reportType = CY_GET_REG8(USBFS_1_wValueHi);\r
- interfaceN = CY_GET_REG8(USBFS_1_wIndexLo);\r
- /* Third entry in the LUT COnfiguration Table starts the Interface Table pointers */\r
- /* Now use the request interface number */\r
- pTmp = &pTmp[interfaceN + 2u];\r
- /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE*/\r
- pTmp = (const T_USBFS_1_LUT CYCODE *) pTmp->p_list;\r
- if(interfaceN < USBFS_1_MAX_INTERFACES_NUMBER)\r
- {\r
- /* Now use Alternate setting number */\r
- pTmp = &pTmp[USBFS_1_interfaceSetting[interfaceN]];\r
- /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */\r
- pTmp = (const T_USBFS_1_LUT CYCODE *) pTmp->p_list;\r
- /* Validate reportType to comply with "7.2.1 Get_Report Request" */\r
- if((reportType >= USBFS_1_HID_GET_REPORT_INPUT) &&\r
- (reportType <= USBFS_1_HID_GET_REPORT_FEATURE))\r
- {\r
- /* Get the entry proper TD (IN, OUT or Feature Report Table)*/\r
- pTmp = &pTmp[reportType - 1u];\r
- reportType = CY_GET_REG8(USBFS_1_wValueLo); /* Get reportID */\r
- /* Validate table support by the HID descriptor, compare table count with reportID */\r
- if(pTmp->c >= reportType)\r
- {\r
- pTD = (T_USBFS_1_TD *) pTmp->p_list;\r
- pTD = &pTD[reportType]; /* select entry depend on report ID*/\r
- USBFS_1_currentTD.pData = pTD->pData; /* Buffer pointer */\r
- USBFS_1_currentTD.count = pTD->count; /* Buffer Size */\r
- USBFS_1_currentTD.pStatusBlock = pTD->pStatusBlock;\r
- }\r
- }\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Additional user functions supporting HID Requests\r
-********************************************************************************/\r
-\r
-/* `#START HID_FUNCTIONS` Place any additional functions here */\r
-\r
-/* `#END` */\r
-\r
-#endif /* End USBFS_1_ENABLE_HID_CLASS */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_hid.h\r
-* Version 2.60\r
-*\r
-* Description:\r
-* Header File for the USFS component. Contains prototypes and constant values.\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_USBFS_USBFS_1_hid_H)\r
-#define CY_USBFS_USBFS_1_hid_H\r
-\r
-#include "cytypes.h"\r
-\r
-\r
-/***************************************\r
-* Prototypes of the USBFS_1_hid API.\r
-***************************************/\r
-\r
-uint8 USBFS_1_UpdateHIDTimer(uint8 interface) ;\r
-uint8 USBFS_1_GetProtocol(uint8 interface) ;\r
-\r
-\r
-/***************************************\r
-*Renamed Functions for backward compatible\r
-***************************************/\r
-\r
-#define USBFS_1_bGetProtocol USBFS_1_GetProtocol\r
-\r
-\r
-/***************************************\r
-* Constants for USBFS_1_hid API.\r
-***************************************/\r
-\r
-#define USBFS_1_PROTOCOL_BOOT (0x00u)\r
-#define USBFS_1_PROTOCOL_REPORT (0x01u)\r
-\r
-/* Request Types (HID Chapter 7.2) */\r
-#define USBFS_1_HID_GET_REPORT (0x01u)\r
-#define USBFS_1_HID_GET_IDLE (0x02u)\r
-#define USBFS_1_HID_GET_PROTOCOL (0x03u)\r
-#define USBFS_1_HID_SET_REPORT (0x09u)\r
-#define USBFS_1_HID_SET_IDLE (0x0Au)\r
-#define USBFS_1_HID_SET_PROTOCOL (0x0Bu)\r
-\r
-/* Descriptor Types (HID Chapter 7.1) */\r
-#define USBFS_1_DESCR_HID_CLASS (0x21u)\r
-#define USBFS_1_DESCR_HID_REPORT (0x22u)\r
-#define USBFS_1_DESCR_HID_PHYSICAL (0x23u)\r
-\r
-/* Report Request Types (HID Chapter 7.2.1) */\r
-#define USBFS_1_HID_GET_REPORT_INPUT (0x01u)\r
-#define USBFS_1_HID_GET_REPORT_OUTPUT (0x02u)\r
-#define USBFS_1_HID_GET_REPORT_FEATURE (0x03u)\r
-\r
-#endif /* End CY_USBFS_USBFS_1_hid_H */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_midi.c\r
-* Version 2.60\r
-*\r
-* Description:\r
-* MIDI Streaming request handler.\r
-* This file contains routines for sending and receiving MIDI\r
-* messages, and handles running status in both directions.\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "USBFS_1.h"\r
-\r
-#if defined(USBFS_1_ENABLE_MIDI_STREAMING)\r
-\r
-#include "USBFS_1_midi.h"\r
-#include "USBFS_1_pvt.h"\r
-\r
-\r
-/***************************************\r
-* MIDI Constants\r
-***************************************/\r
-\r
-#if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF)\r
- /* The Size of the MIDI messages (MIDI Table 4-1) */\r
- static const uint8 CYCODE USBFS_1_MIDI_SIZE[] = {\r
- /* Miscellaneous function codes(Reserved) */ 0x03u,\r
- /* Cable events (Reserved) */ 0x03u,\r
- /* Two-byte System Common messages */ 0x02u,\r
- /* Three-byte System Common messages */ 0x03u,\r
- /* SysEx starts or continues */ 0x03u,\r
- /* Single-byte System Common Message or\r
- SysEx ends with following single byte */ 0x01u,\r
- /* SysEx ends with following two bytes */ 0x02u,\r
- /* SysEx ends with following three bytes */ 0x03u,\r
- /* Note-off */ 0x03u,\r
- /* Note-on */ 0x03u,\r
- /* Poly-KeyPress */ 0x03u,\r
- /* Control Change */ 0x03u,\r
- /* Program Change */ 0x02u,\r
- /* Channel Pressure */ 0x02u,\r
- /* PitchBend Change */ 0x03u,\r
- /* Single Byte */ 0x01u\r
- };\r
-#endif /* USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF */\r
-\r
-\r
-\r
-/***************************************\r
-* Global variables\r
-***************************************/\r
-\r
-#if (USBFS_1_MIDI_IN_BUFF_SIZE > 0)\r
- #if (USBFS_1_MIDI_IN_BUFF_SIZE >= 256)\r
- volatile uint16 USBFS_1_midiInPointer; /* Input endpoint buffer pointer */\r
- #else\r
- volatile uint8 USBFS_1_midiInPointer; /* Input endpoint buffer pointer */\r
- #endif /* End USBFS_1_MIDI_IN_BUFF_SIZE >=256 */\r
- volatile uint8 USBFS_1_midi_in_ep; /* Input endpoint number */\r
- uint8 USBFS_1_midiInBuffer[USBFS_1_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */\r
-#endif /* USBFS_1_MIDI_IN_BUFF_SIZE > 0 */\r
-\r
-#if (USBFS_1_MIDI_OUT_BUFF_SIZE > 0)\r
- volatile uint8 USBFS_1_midi_out_ep; /* Output endpoint number */\r
- uint8 USBFS_1_midiOutBuffer[USBFS_1_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */\r
-#endif /* USBFS_1_MIDI_OUT_BUFF_SIZE > 0 */\r
-\r
-#if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF)\r
- static USBFS_1_MIDI_RX_STATUS USBFS_1_MIDI1_Event; /* MIDI RX status structure */\r
- static volatile uint8 USBFS_1_MIDI1_TxRunStat; /* MIDI Output running status */\r
- volatile uint8 USBFS_1_MIDI1_InqFlags; /* Device inquiry flag */\r
-\r
- #if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF)\r
- static USBFS_1_MIDI_RX_STATUS USBFS_1_MIDI2_Event; /* MIDI RX status structure */\r
- static volatile uint8 USBFS_1_MIDI2_TxRunStat; /* MIDI Output running status */\r
- volatile uint8 USBFS_1_MIDI2_InqFlags; /* Device inquiry flag */\r
- #endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF */\r
-#endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF */\r
-\r
-\r
-/***************************************\r
-* Custom Declarations\r
-***************************************/\r
-\r
-/* `#START MIDI_CUSTOM_DECLARATIONS` Place your declaration here */\r
-\r
-/* `#END` */\r
-\r
-\r
-/***************************************\r
-* Optional MIDI APIs\r
-***************************************/\r
-#if (USBFS_1_ENABLE_MIDI_API != 0u)\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_MIDI_EP_Init\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This function initializes the MIDI interface and UART(s) to be ready to\r
-* receive data from the PC and MIDI ports.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
-* Global variables:\r
-* USBFS_1_midiInBuffer: This buffer is used for saving and combining\r
-* the received data from UART(s) and(or) generated internally by\r
-* PutUsbMidiIn() function messages. USBFS_1_MIDI_IN_EP_Service()\r
-* function transfers the data from this buffer to the PC.\r
-* USBFS_1_midiOutBuffer: This buffer is used by the\r
-* USBFS_1_MIDI_OUT_EP_Service() function for saving the received\r
-* from the PC data, then the data are parsed and transferred to UART(s)\r
-* buffer and to the internal processing by the\r
-* USBFS_1_callbackLocalMidiEvent function.\r
-* USBFS_1_midi_out_ep: Used as an OUT endpoint number.\r
-* USBFS_1_midi_in_ep: Used as an IN endpoint number.\r
-* USBFS_1_midiInPointer: Initialized to zero.\r
-*\r
-* Reentrant:\r
-* No\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_MIDI_EP_Init(void) \r
-{\r
- #if (USBFS_1_MIDI_IN_BUFF_SIZE > 0)\r
- USBFS_1_midiInPointer = 0u;\r
- #endif /* USBFS_1_MIDI_IN_BUFF_SIZE > 0 */\r
-\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO)\r
- #if (USBFS_1_MIDI_IN_BUFF_SIZE > 0)\r
- /* Init DMA configurations for IN EP*/\r
- USBFS_1_LoadInEP(USBFS_1_midi_in_ep, USBFS_1_midiInBuffer,\r
- USBFS_1_MIDI_IN_BUFF_SIZE);\r
- \r
- #endif /* USBFS_1_MIDI_IN_BUFF_SIZE > 0 */\r
- #if (USBFS_1_MIDI_OUT_BUFF_SIZE > 0)\r
- /* Init DMA configurations for OUT EP*/\r
- (void)USBFS_1_ReadOutEP(USBFS_1_midi_out_ep, USBFS_1_midiOutBuffer,\r
- USBFS_1_MIDI_OUT_BUFF_SIZE);\r
- #endif /*USBFS_1_MIDI_OUT_BUFF_SIZE > 0 */\r
- #endif /* End USBFS_1__EP_DMAAUTO */\r
-\r
- #if (USBFS_1_MIDI_OUT_BUFF_SIZE > 0)\r
- USBFS_1_EnableOutEP(USBFS_1_midi_out_ep);\r
- #endif /* USBFS_1_MIDI_OUT_BUFF_SIZE > 0 */\r
-\r
- /* Initialize the MIDI port(s) */\r
- #if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF)\r
- USBFS_1_MIDI_Init();\r
- #endif /* USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF */\r
-}\r
-\r
-#if (USBFS_1_MIDI_OUT_BUFF_SIZE > 0)\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_MIDI_OUT_EP_Service\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Services the USB MIDI OUT endpoints.\r
- * This function is called from OUT EP ISR. It transfers the received from PC\r
- * data to the external MIDI port(UART TX buffer) and calls the\r
- * USBFS_1_callbackLocalMidiEvent() function to internal process\r
- * of the MIDI data.\r
- * This function is blocked by UART, if not enough space is available in UART\r
- * TX buffer. Therefore it is recommended to use large UART TX buffer size.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Global variables:\r
- * USBFS_1_midiOutBuffer: Used as temporary buffer between USB internal\r
- * memory and UART TX buffer.\r
- * USBFS_1_midi_out_ep: Used as an OUT endpoint number.\r
- *\r
- * Reentrant:\r
- * No\r
- *\r
- *******************************************************************************/\r
- void USBFS_1_MIDI_OUT_EP_Service(void) \r
- {\r
- #if USBFS_1_MIDI_OUT_BUFF_SIZE >= 256\r
- uint16 outLength;\r
- uint16 outPointer;\r
- #else\r
- uint8 outLength;\r
- uint8 outPointer;\r
- #endif /* End USBFS_1_MIDI_OUT_BUFF_SIZE >=256 */\r
-\r
- uint8 dmaState = 0u;\r
-\r
- /* Service the USB MIDI output endpoint */\r
- if (USBFS_1_GetEPState(USBFS_1_midi_out_ep) == USBFS_1_OUT_BUFFER_FULL)\r
- {\r
- #if USBFS_1_MIDI_OUT_BUFF_SIZE >= 256\r
- outLength = USBFS_1_GetEPCount(USBFS_1_midi_out_ep);\r
- #else\r
- outLength = (uint8)USBFS_1_GetEPCount(USBFS_1_midi_out_ep);\r
- #endif /* End USBFS_1_MIDI_OUT_BUFF_SIZE >= 256 */\r
- #if(USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO)\r
- #if USBFS_1_MIDI_OUT_BUFF_SIZE >= 256\r
- outLength = USBFS_1_ReadOutEP(USBFS_1_midi_out_ep,\r
- USBFS_1_midiOutBuffer, outLength);\r
- #else\r
- outLength = (uint8)USBFS_1_ReadOutEP(USBFS_1_midi_out_ep,\r
- USBFS_1_midiOutBuffer, (uint16)outLength);\r
- #endif /* End USBFS_1_MIDI_OUT_BUFF_SIZE >= 256 */\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL)\r
- do /* wait for DMA transfer complete */\r
- {\r
- (void)CyDmaChStatus(USBFS_1_DmaChan[USBFS_1_midi_out_ep], NULL, &dmaState);\r
- }while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
- #endif /* End USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO */\r
- if(dmaState != 0u)\r
- {\r
- /* Suppress compiler warning */\r
- }\r
- if (outLength >= USBFS_1_EVENT_LENGTH)\r
- {\r
- outPointer = 0u;\r
- while (outPointer < outLength)\r
- {\r
- /* In some OS OUT packet could be appended by nulls which could be skipped */\r
- if (USBFS_1_midiOutBuffer[outPointer] == 0u)\r
- {\r
- break;\r
- }\r
- /* Route USB MIDI to the External connection */\r
- #if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF)\r
- if ((USBFS_1_midiOutBuffer[outPointer] & USBFS_1_CABLE_MASK) ==\r
- USBFS_1_MIDI_CABLE_00)\r
- {\r
- USBFS_1_MIDI1_ProcessUsbOut(&USBFS_1_midiOutBuffer[outPointer]);\r
- }\r
- else if ((USBFS_1_midiOutBuffer[outPointer] & USBFS_1_CABLE_MASK) ==\r
- USBFS_1_MIDI_CABLE_01)\r
- {\r
- #if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF)\r
- USBFS_1_MIDI2_ProcessUsbOut(&USBFS_1_midiOutBuffer[outPointer]);\r
- #endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF */\r
- }\r
- else\r
- {\r
- /* `#START CUSTOM_MIDI_OUT_EP_SERV` Place your code here */\r
-\r
- /* `#END` */\r
- }\r
- #endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF */\r
-\r
- /* Process any local MIDI output functions */\r
- USBFS_1_callbackLocalMidiEvent(\r
- USBFS_1_midiOutBuffer[outPointer] & USBFS_1_CABLE_MASK,\r
- &USBFS_1_midiOutBuffer[outPointer + USBFS_1_EVENT_BYTE1]);\r
- outPointer += USBFS_1_EVENT_LENGTH;\r
- }\r
- }\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO)\r
- /* Enable Out EP*/\r
- USBFS_1_EnableOutEP(USBFS_1_midi_out_ep);\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO */\r
- }\r
- }\r
-\r
-#endif /* #if (USBFS_1_MIDI_OUT_BUFF_SIZE > 0) */\r
-\r
-#if (USBFS_1_MIDI_IN_BUFF_SIZE > 0)\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_MIDI_IN_EP_Service\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Services the USB MIDI IN endpoint. Non-blocking.\r
- * Checks that previous packet was processed by HOST, otherwise service the\r
- * input endpoint on the subsequent call. It is called from the\r
- * USBFS_1_MIDI_IN_Service() and from the\r
- * USBFS_1_PutUsbMidiIn() function.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Global variables:\r
- * USBFS_1_midi_in_ep: Used as an IN endpoint number.\r
- * USBFS_1_midiInBuffer: Function loads the data from this buffer to\r
- * the USB IN endpoint.\r
- * USBFS_1_midiInPointer: Cleared to zero when data are sent.\r
- *\r
- * Reentrant:\r
- * No\r
- *\r
- *******************************************************************************/\r
- void USBFS_1_MIDI_IN_EP_Service(void) \r
- {\r
- /* Service the USB MIDI input endpoint */\r
- /* Check that previous packet was processed by HOST, otherwise service the USB later */\r
- if (USBFS_1_midiInPointer != 0u)\r
- {\r
- if(USBFS_1_GetEPState(USBFS_1_midi_in_ep) == USBFS_1_EVENT_PENDING)\r
- {\r
- #if(USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO)\r
- USBFS_1_LoadInEP(USBFS_1_midi_in_ep, USBFS_1_midiInBuffer,\r
- (uint16)USBFS_1_midiInPointer);\r
- #else /* USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO */\r
- /* rearm IN EP */\r
- USBFS_1_LoadInEP(USBFS_1_midi_in_ep, NULL, (uint16)USBFS_1_midiInPointer);\r
- #endif /* End USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO*/\r
-\r
- /* Clear the midiInPointer. For DMA mode, clear this pointer in the ARB ISR when data are moved by DMA */\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_MANUAL)\r
- USBFS_1_midiInPointer = 0u;\r
- #endif /* USBFS_1_EP_MM == USBFS_1__EP_MANUAL */\r
- }\r
- }\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_MIDI_IN_Service\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Services the traffic from the MIDI input ports (RX UART) and prepare data\r
- * in USB MIDI IN endpoint buffer.\r
- * Calls the USBFS_1_MIDI_IN_EP_Service() function to sent the\r
- * data from buffer to PC. Non-blocking. Should be called from main foreground\r
- * task.\r
- * This function is not protected from the reentrant calls. When it is required\r
- * to use this function in UART RX ISR to guaranty low latency, care should be\r
- * taken to protect from reentrant calls.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Global variables:\r
- * USBFS_1_midiInPointer: Cleared to zero when data are sent.\r
- *\r
- * Reentrant:\r
- * No\r
- *\r
- *******************************************************************************/\r
- void USBFS_1_MIDI_IN_Service(void) \r
- {\r
- /* Service the MIDI UART inputs until either both receivers have no more\r
- * events or until the input endpoint buffer fills up.\r
- */\r
- #if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF)\r
- uint8 m1 = 0u;\r
- uint8 m2 = 0u;\r
- do\r
- {\r
- if (USBFS_1_midiInPointer <= (USBFS_1_MIDI_IN_BUFF_SIZE - USBFS_1_EVENT_LENGTH))\r
- {\r
- /* Check MIDI1 input port for a complete event */\r
- m1 = USBFS_1_MIDI1_GetEvent();\r
- if (m1 != 0u)\r
- {\r
- USBFS_1_PrepareInBuffer(m1, (uint8 *)&USBFS_1_MIDI1_Event.msgBuff[0],\r
- USBFS_1_MIDI1_Event.size, USBFS_1_MIDI_CABLE_00);\r
- }\r
- }\r
-\r
- #if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF)\r
- if (USBFS_1_midiInPointer <= (USBFS_1_MIDI_IN_BUFF_SIZE - USBFS_1_EVENT_LENGTH))\r
- {\r
- /* Check MIDI2 input port for a complete event */\r
- m2 = USBFS_1_MIDI2_GetEvent();\r
- if (m2 != 0u)\r
- {\r
- USBFS_1_PrepareInBuffer(m2, (uint8 *)&USBFS_1_MIDI2_Event.msgBuff[0],\r
- USBFS_1_MIDI2_Event.size, USBFS_1_MIDI_CABLE_01);\r
- }\r
- }\r
- #endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF */\r
-\r
- }while( (USBFS_1_midiInPointer <= (USBFS_1_MIDI_IN_BUFF_SIZE - USBFS_1_EVENT_LENGTH))\r
- && ((m1 != 0u) || (m2 != 0u)) );\r
- #endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF */\r
-\r
- /* Service the USB MIDI input endpoint */\r
- USBFS_1_MIDI_IN_EP_Service();\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_PutUsbMidiIn\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Puts one MIDI messages into the USB MIDI In endpoint buffer. These are\r
- * MIDI input messages to the host. This function is only used if the device\r
- * has internal MIDI input functionality. USBMIDI_MIDI_IN_Service() function\r
- * should additionally be called to send the message from local buffer to\r
- * IN endpoint.\r
- *\r
- * Parameters:\r
- * ic: 0 = No message (should never happen)\r
- * 1 - 3 = Complete MIDI message in midiMsg\r
- * 3 - IN EP LENGTH = Complete SySEx message(without EOSEX byte) in\r
- * midiMsg. The length is limited by the max BULK EP size(64)\r
- * MIDI_SYSEX = Start or continuation of SysEx message\r
- * (put event bytes in midiMsg buffer)\r
- * MIDI_EOSEX = End of SysEx message\r
- * (put event bytes in midiMsg buffer)\r
- * MIDI_TUNEREQ = Tune Request message (single byte system common msg)\r
- * 0xf8 - 0xff = Single byte real-time message\r
- * midiMsg: pointer to MIDI message.\r
- * cable: cable number.\r
- *\r
- * Return:\r
- * USBFS_1_TRUE if error.\r
- * USBFS_1_FALSE if success.\r
- *\r
- * Global variables:\r
- * USBFS_1_midi_in_ep: MIDI IN endpoint number used for sending data.\r
- * USBFS_1_midiInPointer: Checked this variable to see if there is\r
- * enough free space in the IN endpoint buffer. If buffer is full, initiate\r
- * sending to PC.\r
- *\r
- * Reentrant:\r
- * No\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_1_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable)\r
- \r
- {\r
- uint8 retError = USBFS_1_FALSE;\r
- uint8 msgIndex;\r
-\r
- /* Protect PrepareInBuffer() function from concurrent calls */\r
- #if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF)\r
- MIDI1_UART_DisableRxInt();\r
- #if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF)\r
- MIDI2_UART_DisableRxInt();\r
- #endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF */\r
- #endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF */\r
-\r
- if (USBFS_1_midiInPointer >\r
- (USBFS_1_EP[USBFS_1_midi_in_ep].bufferSize - USBFS_1_EVENT_LENGTH))\r
- {\r
- USBFS_1_MIDI_IN_EP_Service();\r
- }\r
- if (USBFS_1_midiInPointer <=\r
- (USBFS_1_EP[USBFS_1_midi_in_ep].bufferSize - USBFS_1_EVENT_LENGTH))\r
- {\r
- if((ic < USBFS_1_EVENT_LENGTH) || (ic >= USBFS_1_MIDI_STATUS_MASK))\r
- {\r
- USBFS_1_PrepareInBuffer(ic, midiMsg, ic, cable);\r
- }\r
- else\r
- { /* Only SysEx message is greater than 4 bytes */\r
- msgIndex = 0u;\r
- do\r
- {\r
- USBFS_1_PrepareInBuffer(USBFS_1_MIDI_SYSEX, &midiMsg[msgIndex],\r
- USBFS_1_EVENT_BYTE3, cable);\r
- ic -= USBFS_1_EVENT_BYTE3;\r
- msgIndex += USBFS_1_EVENT_BYTE3;\r
- if (USBFS_1_midiInPointer >\r
- (USBFS_1_EP[USBFS_1_midi_in_ep].bufferSize - USBFS_1_EVENT_LENGTH))\r
- {\r
- USBFS_1_MIDI_IN_EP_Service();\r
- if (USBFS_1_midiInPointer >\r
- (USBFS_1_EP[USBFS_1_midi_in_ep].bufferSize - USBFS_1_EVENT_LENGTH))\r
- {\r
- /* Error condition. HOST is not ready to receive this packet. */\r
- retError = USBFS_1_TRUE;\r
- break;\r
- }\r
- }\r
- }while(ic > USBFS_1_EVENT_BYTE3);\r
-\r
- if(retError == USBFS_1_FALSE)\r
- {\r
- USBFS_1_PrepareInBuffer(USBFS_1_MIDI_EOSEX, midiMsg, ic, cable);\r
- }\r
- }\r
- }\r
- else\r
- {\r
- /* Error condition. HOST is not ready to receive this packet. */\r
- retError = USBFS_1_TRUE;\r
- }\r
-\r
- #if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF)\r
- MIDI1_UART_EnableRxInt();\r
- #if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF)\r
- MIDI2_UART_EnableRxInt();\r
- #endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF */\r
- #endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF */\r
-\r
- return (retError);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_PrepareInBuffer\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Builds a USB MIDI event in the input endpoint buffer at the current pointer.\r
- * Puts one MIDI message into the USB MIDI In endpoint buffer.\r
- *\r
- * Parameters:\r
- * ic: 0 = No message (should never happen)\r
- * 1 - 3 = Complete MIDI message at pMdat[0]\r
- * MIDI_SYSEX = Start or continuation of SysEx message\r
- * (put eventLen bytes in buffer)\r
- * MIDI_EOSEX = End of SysEx message\r
- * (put eventLen bytes in buffer,\r
- * and append MIDI_EOSEX)\r
- * MIDI_TUNEREQ = Tune Request message (single byte system common msg)\r
- * 0xf8 - 0xff = Single byte real-time message\r
- *\r
- * srcBuff: pointer to MIDI data\r
- * eventLen: number of bytes in MIDI event\r
- * cable: MIDI source port number\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Global variables:\r
- * USBFS_1_midiInBuffer: This buffer is used for saving and combine the\r
- * received from UART(s) and(or) generated internally by\r
- * USBFS_1_PutUsbMidiIn() function messages.\r
- * USBFS_1_midiInPointer: Used as an index for midiInBuffer to\r
- * write data.\r
- *\r
- * Reentrant:\r
- * No\r
- *\r
- *******************************************************************************/\r
- void USBFS_1_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint8 cable)\r
- \r
- {\r
- uint8 srcBuffZero;\r
- uint8 srcBuffOne;\r
-\r
- srcBuffZero = srcBuff[0u];\r
- srcBuffOne = srcBuff[1u];\r
-\r
- if (ic >= (USBFS_1_MIDI_STATUS_MASK | USBFS_1_MIDI_SINGLE_BYTE_MASK))\r
- {\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = USBFS_1_SINGLE_BYTE | cable;\r
- USBFS_1_midiInPointer++;\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = ic;\r
- USBFS_1_midiInPointer++;\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = 0u;\r
- USBFS_1_midiInPointer++;\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = 0u;\r
- USBFS_1_midiInPointer++;\r
- }\r
- else if((ic < USBFS_1_EVENT_LENGTH) || (ic == USBFS_1_MIDI_SYSEX))\r
- {\r
- if(ic == USBFS_1_MIDI_SYSEX)\r
- {\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = USBFS_1_SYSEX | cable;\r
- USBFS_1_midiInPointer++;\r
- }\r
- else if (srcBuffZero < USBFS_1_MIDI_SYSEX)\r
- {\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = (srcBuffZero >> 4u) | cable;\r
- USBFS_1_midiInPointer++;\r
- }\r
- else if (srcBuffZero == USBFS_1_MIDI_TUNEREQ)\r
- {\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = USBFS_1_1BYTE_COMMON | cable;\r
- USBFS_1_midiInPointer++;\r
- }\r
- else if ((srcBuffZero == USBFS_1_MIDI_QFM) || (srcBuffZero == USBFS_1_MIDI_SONGSEL))\r
- {\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = USBFS_1_2BYTE_COMMON | cable;\r
- USBFS_1_midiInPointer++;\r
- }\r
- else if (srcBuffZero == USBFS_1_MIDI_SPP)\r
- {\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = USBFS_1_3BYTE_COMMON | cable;\r
- USBFS_1_midiInPointer++;\r
- }\r
- else\r
- {\r
- }\r
-\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = srcBuffZero;\r
- USBFS_1_midiInPointer++;\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = srcBuffOne;\r
- USBFS_1_midiInPointer++;\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = srcBuff[2u];\r
- USBFS_1_midiInPointer++;\r
- }\r
- else if (ic == USBFS_1_MIDI_EOSEX)\r
- {\r
- switch (eventLen)\r
- {\r
- case 0u:\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] =\r
- USBFS_1_SYSEX_ENDS_WITH1 | cable;\r
- USBFS_1_midiInPointer++;\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = USBFS_1_MIDI_EOSEX;\r
- USBFS_1_midiInPointer++;\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = 0u;\r
- USBFS_1_midiInPointer++;\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = 0u;\r
- USBFS_1_midiInPointer++;\r
- break;\r
- case 1u:\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] =\r
- USBFS_1_SYSEX_ENDS_WITH2 | cable;\r
- USBFS_1_midiInPointer++;\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = srcBuffZero;\r
- USBFS_1_midiInPointer++;\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = USBFS_1_MIDI_EOSEX;\r
- USBFS_1_midiInPointer++;\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = 0u;\r
- USBFS_1_midiInPointer++;\r
- break;\r
- case 2u:\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] =\r
- USBFS_1_SYSEX_ENDS_WITH3 | cable;\r
- USBFS_1_midiInPointer++;\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = srcBuffZero;\r
- USBFS_1_midiInPointer++;\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = srcBuffOne;\r
- USBFS_1_midiInPointer++;\r
- USBFS_1_midiInBuffer[USBFS_1_midiInPointer] = USBFS_1_MIDI_EOSEX;\r
- USBFS_1_midiInPointer++;\r
- break;\r
- default:\r
- break;\r
- }\r
- }\r
- else\r
- {\r
- }\r
- }\r
-\r
-#endif /* #if (USBFS_1_MIDI_IN_BUFF_SIZE > 0) */\r
-\r
-\r
-/* The implementation for external serial input and output connections\r
-* to route USB MIDI data to and from those connections.\r
-*/\r
-#if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF)\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_MIDI_Init\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Initializes MIDI variables and starts the UART(s) hardware block(s).\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Side Effects:\r
- * Change the priority of the UART(s) TX interrupts to be higher than the\r
- * default EP ISR priority.\r
- *\r
- * Global variables:\r
- * USBFS_1_MIDI_Event: initialized to zero.\r
- * USBFS_1_MIDI_TxRunStat: initialized to zero.\r
- *\r
- *******************************************************************************/\r
- void USBFS_1_MIDI_Init(void) \r
- {\r
- USBFS_1_MIDI1_Event.length = 0u;\r
- USBFS_1_MIDI1_Event.count = 0u;\r
- USBFS_1_MIDI1_Event.size = 0u;\r
- USBFS_1_MIDI1_Event.runstat = 0u;\r
- USBFS_1_MIDI1_TxRunStat = 0u;\r
- USBFS_1_MIDI1_InqFlags = 0u;\r
- /* Start UART block */\r
- MIDI1_UART_Start();\r
- /* Change the priority of the UART TX and RX interrupt */\r
- CyIntSetPriority(MIDI1_UART_TX_VECT_NUM, USBFS_1_CUSTOM_UART_TX_PRIOR_NUM);\r
- CyIntSetPriority(MIDI1_UART_RX_VECT_NUM, USBFS_1_CUSTOM_UART_RX_PRIOR_NUM);\r
-\r
- #if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF)\r
- USBFS_1_MIDI2_Event.length = 0u;\r
- USBFS_1_MIDI2_Event.count = 0u;\r
- USBFS_1_MIDI2_Event.size = 0u;\r
- USBFS_1_MIDI2_Event.runstat = 0u;\r
- USBFS_1_MIDI2_TxRunStat = 0u;\r
- USBFS_1_MIDI2_InqFlags = 0u;\r
- /* Start second UART block */\r
- MIDI2_UART_Start();\r
- /* Change the priority of the UART TX interrupt */\r
- CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_1_CUSTOM_UART_TX_PRIOR_NUM);\r
- CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_1_CUSTOM_UART_RX_PRIOR_NUM);\r
- #endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF*/\r
-\r
- /* `#START MIDI_INIT_CUSTOM` Init other extended UARTs here */\r
-\r
- /* `#END` */\r
-\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_ProcessMidiIn\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Processes one byte of incoming MIDI data.\r
- *\r
- * Parameters:\r
- * mData = current MIDI input data byte\r
- * *rxStat = pointer to a MIDI_RX_STATUS structure\r
- *\r
- * Return:\r
- * 0, if no complete message\r
- * 1 - 4, if message complete\r
- * MIDI_SYSEX, if start or continuation of system exclusive\r
- * MIDI_EOSEX, if end of system exclusive\r
- * 0xf8 - 0xff, if single byte real time message\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_1_ProcessMidiIn(uint8 mData, USBFS_1_MIDI_RX_STATUS *rxStat)\r
- \r
- {\r
- uint8 midiReturn = 0u;\r
-\r
- /* Check for a MIDI status byte. All status bytes, except real time messages,\r
- * which are a single byte, force the start of a new buffer cycle.\r
- */\r
- if ((mData & USBFS_1_MIDI_STATUS_BYTE_MASK) != 0u)\r
- {\r
- if ((mData & USBFS_1_MIDI_STATUS_MASK) == USBFS_1_MIDI_STATUS_MASK)\r
- {\r
- if ((mData & USBFS_1_MIDI_SINGLE_BYTE_MASK) != 0u) /* System Real-Time Messages(single byte) */\r
- {\r
- midiReturn = mData;\r
- }\r
- else /* System Common Messages */\r
- {\r
- switch (mData)\r
- {\r
- case USBFS_1_MIDI_SYSEX:\r
- rxStat->msgBuff[0u] = USBFS_1_MIDI_SYSEX;\r
- rxStat->runstat = USBFS_1_MIDI_SYSEX;\r
- rxStat->count = 1u;\r
- rxStat->length = 3u;\r
- break;\r
- case USBFS_1_MIDI_EOSEX:\r
- rxStat->runstat = 0u;\r
- rxStat->size = rxStat->count;\r
- rxStat->count = 0u;\r
- midiReturn = USBFS_1_MIDI_EOSEX;\r
- break;\r
- case USBFS_1_MIDI_SPP:\r
- rxStat->msgBuff[0u] = USBFS_1_MIDI_SPP;\r
- rxStat->runstat = 0u;\r
- rxStat->count = 1u;\r
- rxStat->length = 3u;\r
- break;\r
- case USBFS_1_MIDI_SONGSEL:\r
- rxStat->msgBuff[0u] = USBFS_1_MIDI_SONGSEL;\r
- rxStat->runstat = 0u;\r
- rxStat->count = 1u;\r
- rxStat->length = 2u;\r
- break;\r
- case USBFS_1_MIDI_QFM:\r
- rxStat->msgBuff[0u] = USBFS_1_MIDI_QFM;\r
- rxStat->runstat = 0u;\r
- rxStat->count = 1u;\r
- rxStat->length = 2u;\r
- break;\r
- case USBFS_1_MIDI_TUNEREQ:\r
- rxStat->msgBuff[0u] = USBFS_1_MIDI_TUNEREQ;\r
- rxStat->runstat = 0u;\r
- rxStat->size = 1u;\r
- rxStat->count = 0u;\r
- midiReturn = rxStat->size;\r
- break;\r
- default:\r
- break;\r
- }\r
- }\r
- }\r
- else /* Channel Messages */\r
- {\r
- rxStat->msgBuff[0u] = mData;\r
- rxStat->runstat = mData;\r
- rxStat->count = 1u;\r
- switch (mData & USBFS_1_MIDI_STATUS_MASK)\r
- {\r
- case USBFS_1_MIDI_NOTE_OFF:\r
- case USBFS_1_MIDI_NOTE_ON:\r
- case USBFS_1_MIDI_POLY_KEY_PRESSURE:\r
- case USBFS_1_MIDI_CONTROL_CHANGE:\r
- case USBFS_1_MIDI_PITCH_BEND_CHANGE:\r
- rxStat->length = 3u;\r
- break;\r
- case USBFS_1_MIDI_PROGRAM_CHANGE:\r
- case USBFS_1_MIDI_CHANNEL_PRESSURE:\r
- rxStat->length = 2u;\r
- break;\r
- default:\r
- rxStat->runstat = 0u;\r
- rxStat->count = 0u;\r
- break;\r
- }\r
- }\r
- }\r
-\r
- /* Otherwise, it's a data byte */\r
- else\r
- {\r
- if (rxStat->runstat == USBFS_1_MIDI_SYSEX)\r
- {\r
- rxStat->msgBuff[rxStat->count] = mData;\r
- rxStat->count++;\r
- if (rxStat->count >= rxStat->length)\r
- {\r
- rxStat->size = rxStat->count;\r
- rxStat->count = 0u;\r
- midiReturn = USBFS_1_MIDI_SYSEX;\r
- }\r
- }\r
- else if (rxStat->count > 0u)\r
- {\r
- rxStat->msgBuff[rxStat->count] = mData;\r
- rxStat->count++;\r
- if (rxStat->count >= rxStat->length)\r
- {\r
- rxStat->size = rxStat->count;\r
- rxStat->count = 0u;\r
- midiReturn = rxStat->size;\r
- }\r
- }\r
- else if (rxStat->runstat != 0u)\r
- {\r
- rxStat->msgBuff[0u] = rxStat->runstat;\r
- rxStat->msgBuff[1u] = mData;\r
- rxStat->count = 2u;\r
- switch (rxStat->runstat & USBFS_1_MIDI_STATUS_MASK)\r
- {\r
- case USBFS_1_MIDI_NOTE_OFF:\r
- case USBFS_1_MIDI_NOTE_ON:\r
- case USBFS_1_MIDI_POLY_KEY_PRESSURE:\r
- case USBFS_1_MIDI_CONTROL_CHANGE:\r
- case USBFS_1_MIDI_PITCH_BEND_CHANGE:\r
- rxStat->length = 3u;\r
- break;\r
- case USBFS_1_MIDI_PROGRAM_CHANGE:\r
- case USBFS_1_MIDI_CHANNEL_PRESSURE:\r
- rxStat->size =rxStat->count;\r
- rxStat->count = 0u;\r
- midiReturn = rxStat->size;\r
- break;\r
- default:\r
- rxStat->count = 0u;\r
- break;\r
- }\r
- }\r
- else\r
- {\r
- }\r
- }\r
- return (midiReturn);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_MIDI1_GetEvent\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Checks for incoming MIDI data, calls the MIDI event builder if so.\r
- * Returns either empty or with a complete event.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * 0, if no complete message\r
- * 1 - 4, if message complete\r
- * MIDI_SYSEX, if start or continuation of system exclusive\r
- * MIDI_EOSEX, if end of system exclusive\r
- * 0xf8 - 0xff, if single byte real time message\r
- *\r
- * Global variables:\r
- * USBFS_1_MIDI1_Event: RX status structure used to parse received\r
- * data.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_1_MIDI1_GetEvent(void) \r
- {\r
- uint8 msgRtn = 0u;\r
- uint8 rxData;\r
- #if (MIDI1_UART_RXBUFFERSIZE >= 256u)\r
- uint16 rxBufferRead;\r
- #if CY_PSOC3 /* This local variable is required only for PSOC3 and large buffer */\r
- uint16 rxBufferWrite;\r
- #endif /* end CY_PSOC3 */\r
- #else\r
- uint8 rxBufferRead;\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
- uint8 rxBufferLoopDetect;\r
- /* Read buffer loop condition to the local variable */\r
- rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect;\r
-\r
- if ( (MIDI1_UART_rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u) )\r
- {\r
- /* Protect variables that could change on interrupt by disabling Rx interrupt.*/\r
- #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
- rxBufferRead = MIDI1_UART_rxBufferRead;\r
- #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- rxBufferWrite = MIDI1_UART_rxBufferWrite;\r
- CyIntEnable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
-\r
- /* Stay here until either the buffer is empty or we have a complete message\r
- * in the message buffer. Note that we must use a temporary buffer pointer\r
- * since it takes two instructions to increment with a wrap, and we can't\r
- * risk doing that with the real pointer and getting an interrupt in between\r
- * instructions.\r
- */\r
-\r
- #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )\r
- #else\r
- while ( ((rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */\r
- {\r
- rxData = MIDI1_UART_rxBuffer[rxBufferRead];\r
- /* Increment pointer with a wrap */\r
- rxBufferRead++;\r
- if(rxBufferRead >= MIDI1_UART_RXBUFFERSIZE)\r
- {\r
- rxBufferRead = 0u;\r
- }\r
- /* If loop condition was set - update real read buffer pointer\r
- * to avoid overflow status\r
- */\r
- if(rxBufferLoopDetect != 0u )\r
- {\r
- MIDI1_UART_rxBufferLoopDetect = 0u;\r
- #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
- MIDI1_UART_rxBufferRead = rxBufferRead;\r
- #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntEnable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
- }\r
-\r
- msgRtn = USBFS_1_ProcessMidiIn(rxData,\r
- (USBFS_1_MIDI_RX_STATUS *)&USBFS_1_MIDI1_Event);\r
-\r
- /* Read buffer loop condition to the local variable */\r
- rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect;\r
- }\r
-\r
- /* Finally, update the real output pointer, then return with\r
- * an indication as to whether there's a complete message in the buffer.\r
- */\r
- #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
- MIDI1_UART_rxBufferRead = rxBufferRead;\r
- #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntEnable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
- }\r
-\r
- return (msgRtn);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_MIDI1_ProcessUsbOut\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Process a USB MIDI output event.\r
- * Puts data into the MIDI TX output buffer.\r
- *\r
- * Parameters:\r
- * *epBuf: pointer on MIDI event.\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Global variables:\r
- * USBFS_1_MIDI1_TxRunStat: This variable used to save the MIDI\r
- * status byte and skip to send the repeated status byte in subsequent event.\r
- * USBFS_1_MIDI1_InqFlags: The following flags are set when SysEx\r
- * message comes.\r
- * USBFS_1_INQ_SYSEX_FLAG: Non-Real Time SySEx message received.\r
- * USBFS_1_INQ_IDENTITY_REQ_FLAG: Identity Request received.\r
- * This bit should be cleared by user when Identity Reply message generated.\r
- *\r
- *******************************************************************************/\r
- void USBFS_1_MIDI1_ProcessUsbOut(const uint8 epBuf[])\r
- \r
- {\r
- uint8 cmd;\r
- uint8 len;\r
- uint8 i;\r
-\r
- /* User code is required at the beginning of the procedure */\r
- /* `#START MIDI1_PROCESS_OUT_BEGIN` */\r
-\r
- /* `#END` */\r
-\r
- cmd = epBuf[USBFS_1_EVENT_BYTE0] & USBFS_1_CIN_MASK;\r
- if((cmd != USBFS_1_RESERVED0) && (cmd != USBFS_1_RESERVED1))\r
- {\r
- len = USBFS_1_MIDI_SIZE[cmd];\r
- i = USBFS_1_EVENT_BYTE1;\r
- /* Universal System Exclusive message parsing */\r
- if(cmd == USBFS_1_SYSEX)\r
- {\r
- if((epBuf[USBFS_1_EVENT_BYTE1] == USBFS_1_MIDI_SYSEX) &&\r
- (epBuf[USBFS_1_EVENT_BYTE2] == USBFS_1_MIDI_SYSEX_NON_REAL_TIME))\r
- { /* Non-Real Time SySEx starts */\r
- USBFS_1_MIDI1_InqFlags |= USBFS_1_INQ_SYSEX_FLAG;\r
- }\r
- else\r
- {\r
- USBFS_1_MIDI1_InqFlags &= (uint8)~USBFS_1_INQ_SYSEX_FLAG;\r
- }\r
- }\r
- else if(cmd == USBFS_1_SYSEX_ENDS_WITH1)\r
- {\r
- USBFS_1_MIDI1_InqFlags &= (uint8)~USBFS_1_INQ_SYSEX_FLAG;\r
- }\r
- else if(cmd == USBFS_1_SYSEX_ENDS_WITH2)\r
- {\r
- USBFS_1_MIDI1_InqFlags &= (uint8)~USBFS_1_INQ_SYSEX_FLAG;\r
- }\r
- else if(cmd == USBFS_1_SYSEX_ENDS_WITH3)\r
- {\r
- /* Identify Request support */\r
- if((USBFS_1_MIDI1_InqFlags & USBFS_1_INQ_SYSEX_FLAG) != 0u)\r
- {\r
- USBFS_1_MIDI1_InqFlags &= (uint8)~USBFS_1_INQ_SYSEX_FLAG;\r
- if((epBuf[USBFS_1_EVENT_BYTE1] == USBFS_1_MIDI_SYSEX_GEN_INFORMATION) &&\r
- (epBuf[USBFS_1_EVENT_BYTE2] == USBFS_1_MIDI_SYSEX_IDENTITY_REQ))\r
- { /* Set the flag about received the Identity Request.\r
- * The Identity Reply message may be send by user code.\r
- */\r
- USBFS_1_MIDI1_InqFlags |= USBFS_1_INQ_IDENTITY_REQ_FLAG;\r
- }\r
- }\r
- }\r
- else /* Do nothing for other command */\r
- {\r
- }\r
- /* Running Status for Voice and Mode messages only. */\r
- if((cmd >= USBFS_1_NOTE_OFF) && ( cmd <= USBFS_1_PITCH_BEND_CHANGE))\r
- {\r
- if(USBFS_1_MIDI1_TxRunStat == epBuf[USBFS_1_EVENT_BYTE1])\r
- { /* Skip the repeated Status byte */\r
- i++;\r
- }\r
- else\r
- { /* Save Status byte for next event */\r
- USBFS_1_MIDI1_TxRunStat = epBuf[USBFS_1_EVENT_BYTE1];\r
- }\r
- }\r
- else\r
- { /* Clear Running Status */\r
- USBFS_1_MIDI1_TxRunStat = 0u;\r
- }\r
- /* Puts data into the MIDI TX output buffer.*/\r
- do\r
- {\r
- MIDI1_UART_PutChar(epBuf[i]);\r
- i++;\r
- } while (i <= len);\r
- }\r
-\r
- /* User code is required at the end of the procedure */\r
- /* `#START MIDI1_PROCESS_OUT_END` */\r
-\r
- /* `#END` */\r
- }\r
-\r
-#if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF)\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_MIDI2_GetEvent\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Checks for incoming MIDI data, calls the MIDI event builder if so.\r
- * Returns either empty or with a complete event.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * 0, if no complete message\r
- * 1 - 4, if message complete\r
- * MIDI_SYSEX, if start or continuation of system exclusive\r
- * MIDI_EOSEX, if end of system exclusive\r
- * 0xf8 - 0xff, if single byte real time message\r
- *\r
- * Global variables:\r
- * USBFS_1_MIDI2_Event: RX status structure used to parse received\r
- * data.\r
- *\r
- *******************************************************************************/\r
- uint8 USBFS_1_MIDI2_GetEvent(void) \r
- {\r
- uint8 msgRtn = 0u;\r
- uint8 rxData;\r
- #if (MIDI2_UART_RXBUFFERSIZE >= 256u)\r
- uint16 rxBufferRead;\r
- #if CY_PSOC3 /* This local variable required only for PSOC3 and large buffer */\r
- uint16 rxBufferWrite;\r
- #endif /* end CY_PSOC3 */\r
- #else\r
- uint8 rxBufferRead;\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
- uint8 rxBufferLoopDetect;\r
- /* Read buffer loop condition to the local variable */\r
- rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect;\r
-\r
- if ( (MIDI2_UART_rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u) )\r
- {\r
- /* Protect variables that could change on interrupt by disabling Rx interrupt.*/\r
- #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntDisable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
- rxBufferRead = MIDI2_UART_rxBufferRead;\r
- #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- rxBufferWrite = MIDI2_UART_rxBufferWrite;\r
- CyIntEnable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
-\r
- /* Stay here until either the buffer is empty or we have a complete message\r
- * in the message buffer. Note that we must use a temporary output pointer to\r
- * since it takes two instructions to increment with a wrap, and we can't\r
- * risk doing that with the real pointer and getting an interrupt in between\r
- * instructions.\r
- */\r
-\r
- #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )\r
- #else\r
- while ( ((rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */\r
- {\r
- rxData = MIDI2_UART_rxBuffer[rxBufferRead];\r
- rxBufferRead++;\r
- if(rxBufferRead >= MIDI2_UART_RXBUFFERSIZE)\r
- {\r
- rxBufferRead = 0u;\r
- }\r
- /* If loop condition was set - update real read buffer pointer\r
- * to avoid overflow status\r
- */\r
- if(rxBufferLoopDetect != 0u )\r
- {\r
- MIDI2_UART_rxBufferLoopDetect = 0u;\r
- #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntDisable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
- MIDI2_UART_rxBufferRead = rxBufferRead;\r
- #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntEnable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
- }\r
-\r
- msgRtn = USBFS_1_ProcessMidiIn(rxData,\r
- (USBFS_1_MIDI_RX_STATUS *)&USBFS_1_MIDI2_Event);\r
-\r
- /* Read buffer loop condition to the local variable */\r
- rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect;\r
- }\r
-\r
- /* Finally, update the real output pointer, then return with\r
- * an indication as to whether there's a complete message in the buffer.\r
- */\r
- #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntDisable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
- MIDI2_UART_rxBufferRead = rxBufferRead;\r
- #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
- CyIntEnable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
- }\r
-\r
- return (msgRtn);\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_MIDI2_ProcessUsbOut\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Process a USB MIDI output event.\r
- * Puts data into the MIDI TX output buffer.\r
- *\r
- * Parameters:\r
- * *epBuf: pointer on MIDI event.\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Global variables:\r
- * USBFS_1_MIDI2_TxRunStat: This variable used to save the MIDI\r
- * status byte and skip to send the repeated status byte in subsequent event.\r
- * USBFS_1_MIDI2_InqFlags: The following flags are set when SysEx\r
- * message comes.\r
- * USBFS_1_INQ_SYSEX_FLAG: Non-Real Time SySEx message received.\r
- * USBFS_1_INQ_IDENTITY_REQ_FLAG: Identity Request received.\r
- * This bit should be cleared by user when Identity Reply message generated.\r
- *\r
- *******************************************************************************/\r
- void USBFS_1_MIDI2_ProcessUsbOut(const uint8 epBuf[])\r
- \r
- {\r
- uint8 cmd;\r
- uint8 len;\r
- uint8 i;\r
-\r
- /* User code is required at the beginning of the procedure */\r
- /* `#START MIDI2_PROCESS_OUT_START` */\r
-\r
- /* `#END` */\r
-\r
- cmd = epBuf[USBFS_1_EVENT_BYTE0] & USBFS_1_CIN_MASK;\r
- if((cmd != USBFS_1_RESERVED0) && (cmd != USBFS_1_RESERVED1))\r
- {\r
- len = USBFS_1_MIDI_SIZE[cmd];\r
- i = USBFS_1_EVENT_BYTE1;\r
- /* Universal System Exclusive message parsing */\r
- if(cmd == USBFS_1_SYSEX)\r
- {\r
- if((epBuf[USBFS_1_EVENT_BYTE1] == USBFS_1_MIDI_SYSEX) &&\r
- (epBuf[USBFS_1_EVENT_BYTE2] == USBFS_1_MIDI_SYSEX_NON_REAL_TIME))\r
- { /* SySEx starts */\r
- USBFS_1_MIDI2_InqFlags |= USBFS_1_INQ_SYSEX_FLAG;\r
- }\r
- else\r
- {\r
- USBFS_1_MIDI2_InqFlags &= (uint8)~USBFS_1_INQ_SYSEX_FLAG;\r
- }\r
- }\r
- else if(cmd == USBFS_1_SYSEX_ENDS_WITH1)\r
- {\r
- USBFS_1_MIDI2_InqFlags &= (uint8)~USBFS_1_INQ_SYSEX_FLAG;\r
- }\r
- else if(cmd == USBFS_1_SYSEX_ENDS_WITH2)\r
- {\r
- USBFS_1_MIDI2_InqFlags &= (uint8)~USBFS_1_INQ_SYSEX_FLAG;\r
- }\r
- else if(cmd == USBFS_1_SYSEX_ENDS_WITH3)\r
- {\r
- /* Identify Request support */\r
- if((USBFS_1_MIDI2_InqFlags & USBFS_1_INQ_SYSEX_FLAG) != 0u)\r
- {\r
- USBFS_1_MIDI2_InqFlags &= (uint8)~USBFS_1_INQ_SYSEX_FLAG;\r
- if((epBuf[USBFS_1_EVENT_BYTE1] == USBFS_1_MIDI_SYSEX_GEN_INFORMATION) &&\r
- (epBuf[USBFS_1_EVENT_BYTE2] == USBFS_1_MIDI_SYSEX_IDENTITY_REQ))\r
- { /* Set the flag about received the Identity Request.\r
- * The Identity Reply message may be send by user code.\r
- */\r
- USBFS_1_MIDI2_InqFlags |= USBFS_1_INQ_IDENTITY_REQ_FLAG;\r
- }\r
- }\r
- }\r
- else /* Do nothing for other command */\r
- {\r
- }\r
- /* Running Status for Voice and Mode messages only. */\r
- if((cmd >= USBFS_1_NOTE_OFF) && ( cmd <= USBFS_1_PITCH_BEND_CHANGE))\r
- {\r
- if(USBFS_1_MIDI2_TxRunStat == epBuf[USBFS_1_EVENT_BYTE1])\r
- { /* Skip the repeated Status byte */\r
- i++;\r
- }\r
- else\r
- { /* Save Status byte for next event */\r
- USBFS_1_MIDI2_TxRunStat = epBuf[USBFS_1_EVENT_BYTE1];\r
- }\r
- }\r
- else\r
- { /* Clear Running Status */\r
- USBFS_1_MIDI2_TxRunStat = 0u;\r
- }\r
- /* Puts data into the MIDI TX output buffer.*/\r
- do\r
- {\r
- MIDI2_UART_PutChar(epBuf[i]);\r
- i++;\r
- } while (i <= len);\r
- }\r
-\r
- /* User code is required at the end of the procedure */\r
- /* `#START MIDI2_PROCESS_OUT_END` */\r
-\r
- /* `#END` */\r
- }\r
-#endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF */\r
-#endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF */\r
-\r
-#endif /* End (USBFS_1_ENABLE_MIDI_API != 0u) */\r
-\r
-\r
-/* `#START MIDI_FUNCTIONS` Place any additional functions here */\r
-\r
-/* `#END` */\r
-\r
-#endif /* End defined(USBFS_1_ENABLE_MIDI_STREAMING) */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_midi.h\r
-* Version 2.60\r
-*\r
-* Description:\r
-* Header File for the USBFS MIDI module.\r
-* Contains prototypes and constant values.\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_USBFS_USBFS_1_midi_H)\r
-#define CY_USBFS_USBFS_1_midi_H\r
-\r
-#include "cytypes.h"\r
-#include "USBFS_1.h"\r
-\r
-\r
-/***************************************\r
-* Data Struct Definition\r
-***************************************/\r
-\r
-/* The following structure is used to hold status information for\r
- building and parsing incoming MIDI messages. */\r
-typedef struct\r
-{\r
- uint8 length; /* expected length */\r
- uint8 count; /* current byte count */\r
- uint8 size; /* complete size */\r
- uint8 runstat; /* running status */\r
- uint8 msgBuff[4]; /* message buffer */\r
-} USBFS_1_MIDI_RX_STATUS;\r
-\r
-\r
-/***************************************\r
-* MIDI Constants.\r
-***************************************/\r
-\r
-#define USBFS_1_ONE_EXT_INTRF (0x01u)\r
-#define USBFS_1_TWO_EXT_INTRF (0x02u)\r
-\r
-/* Flag definitions for use with MIDI device inquiry */\r
-#define USBFS_1_INQ_SYSEX_FLAG (0x01u)\r
-#define USBFS_1_INQ_IDENTITY_REQ_FLAG (0x02u)\r
-\r
-/* USB-MIDI Code Index Number Classifications (MIDI Table 4-1) */\r
-#define USBFS_1_CIN_MASK (0x0Fu)\r
-#define USBFS_1_RESERVED0 (0x00u)\r
-#define USBFS_1_RESERVED1 (0x01u)\r
-#define USBFS_1_2BYTE_COMMON (0x02u)\r
-#define USBFS_1_3BYTE_COMMON (0x03u)\r
-#define USBFS_1_SYSEX (0x04u)\r
-#define USBFS_1_1BYTE_COMMON (0x05u)\r
-#define USBFS_1_SYSEX_ENDS_WITH1 (0x05u)\r
-#define USBFS_1_SYSEX_ENDS_WITH2 (0x06u)\r
-#define USBFS_1_SYSEX_ENDS_WITH3 (0x07u)\r
-#define USBFS_1_NOTE_OFF (0x08u)\r
-#define USBFS_1_NOTE_ON (0x09u)\r
-#define USBFS_1_POLY_KEY_PRESSURE (0x0Au)\r
-#define USBFS_1_CONTROL_CHANGE (0x0Bu)\r
-#define USBFS_1_PROGRAM_CHANGE (0x0Cu)\r
-#define USBFS_1_CHANNEL_PRESSURE (0x0Du)\r
-#define USBFS_1_PITCH_BEND_CHANGE (0x0Eu)\r
-#define USBFS_1_SINGLE_BYTE (0x0Fu)\r
-\r
-#define USBFS_1_CABLE_MASK (0xF0u)\r
-#define USBFS_1_MIDI_CABLE_00 (0x00u)\r
-#define USBFS_1_MIDI_CABLE_01 (0x10u)\r
-\r
-#define USBFS_1_EVENT_BYTE0 (0x00u)\r
-#define USBFS_1_EVENT_BYTE1 (0x01u)\r
-#define USBFS_1_EVENT_BYTE2 (0x02u)\r
-#define USBFS_1_EVENT_BYTE3 (0x03u)\r
-#define USBFS_1_EVENT_LENGTH (0x04u)\r
-\r
-#define USBFS_1_MIDI_STATUS_BYTE_MASK (0x80u)\r
-#define USBFS_1_MIDI_STATUS_MASK (0xF0u)\r
-#define USBFS_1_MIDI_SINGLE_BYTE_MASK (0x08u)\r
-#define USBFS_1_MIDI_NOTE_OFF (0x80u)\r
-#define USBFS_1_MIDI_NOTE_ON (0x90u)\r
-#define USBFS_1_MIDI_POLY_KEY_PRESSURE (0xA0u)\r
-#define USBFS_1_MIDI_CONTROL_CHANGE (0xB0u)\r
-#define USBFS_1_MIDI_PROGRAM_CHANGE (0xC0u)\r
-#define USBFS_1_MIDI_CHANNEL_PRESSURE (0xD0u)\r
-#define USBFS_1_MIDI_PITCH_BEND_CHANGE (0xE0u)\r
-#define USBFS_1_MIDI_SYSEX (0xF0u)\r
-#define USBFS_1_MIDI_EOSEX (0xF7u)\r
-#define USBFS_1_MIDI_QFM (0xF1u)\r
-#define USBFS_1_MIDI_SPP (0xF2u)\r
-#define USBFS_1_MIDI_SONGSEL (0xF3u)\r
-#define USBFS_1_MIDI_TUNEREQ (0xF6u)\r
-#define USBFS_1_MIDI_ACTIVESENSE (0xFEu)\r
-\r
-/* MIDI Universal System Exclusive defines */\r
-#define USBFS_1_MIDI_SYSEX_NON_REAL_TIME (0x7Eu)\r
-#define USBFS_1_MIDI_SYSEX_REALTIME (0x7Fu)\r
-/* ID of target device */\r
-#define USBFS_1_MIDI_SYSEX_ID_ALL (0x7Fu)\r
-/* Sub-ID#1*/\r
-#define USBFS_1_MIDI_SYSEX_GEN_INFORMATION (0x06u)\r
-#define USBFS_1_MIDI_SYSEX_GEN_MESSAGE (0x09u)\r
-/* Sub-ID#2*/\r
-#define USBFS_1_MIDI_SYSEX_IDENTITY_REQ (0x01u)\r
-#define USBFS_1_MIDI_SYSEX_IDENTITY_REPLY (0x02u)\r
-#define USBFS_1_MIDI_SYSEX_SYSTEM_ON (0x01u)\r
-#define USBFS_1_MIDI_SYSEX_SYSTEM_OFF (0x02u)\r
-\r
-#define USBFS_1_CUSTOM_UART_TX_PRIOR_NUM (0x04u)\r
-#define USBFS_1_CUSTOM_UART_RX_PRIOR_NUM (0x02u)\r
-\r
-#define USBFS_1_ISR_SERVICE_MIDI_OUT \\r
- ( (USBFS_1_ENABLE_MIDI_API != 0u) && \\r
- (USBFS_1_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO) )\r
-#define USBFS_1_ISR_SERVICE_MIDI_IN \\r
- ( (USBFS_1_ENABLE_MIDI_API != 0u) && (USBFS_1_MIDI_IN_BUFF_SIZE > 0) )\r
-\r
-/***************************************\r
-* External function references\r
-***************************************/\r
-\r
-void USBFS_1_callbackLocalMidiEvent(uint8 cable, uint8 *midiMsg)\r
- ;\r
-\r
-\r
-/***************************************\r
-* External references\r
-***************************************/\r
-\r
-#if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF)\r
- #include "MIDI1_UART.h"\r
-#endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF */\r
-#if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF)\r
- #include "MIDI2_UART.h"\r
-#endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF */\r
-#if(USBFS_1_EP_MM != USBFS_1__EP_MANUAL)\r
- #include <CyDmac.h>\r
-#endif /* End USBFS_1_EP_MM */\r
-\r
-\r
-/***************************************\r
-* Private function prototypes\r
-***************************************/\r
-\r
-void USBFS_1_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint8 cable)\r
- ;\r
-#if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF)\r
- void USBFS_1_MIDI_Init(void) ;\r
- uint8 USBFS_1_ProcessMidiIn(uint8 mData, USBFS_1_MIDI_RX_STATUS *rxStat)\r
- ;\r
- uint8 USBFS_1_MIDI1_GetEvent(void) ;\r
- void USBFS_1_MIDI1_ProcessUsbOut(const uint8 epBuf[])\r
- ;\r
-\r
- #if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF)\r
- uint8 USBFS_1_MIDI2_GetEvent(void) ;\r
- void USBFS_1_MIDI2_ProcessUsbOut(const uint8 epBuf[])\r
- ;\r
- #endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF */\r
-#endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF */\r
-\r
-\r
-/***************************************\r
-* External data references\r
-***************************************/\r
-\r
-#if defined(USBFS_1_ENABLE_MIDI_STREAMING)\r
-\r
-#if (USBFS_1_MIDI_IN_BUFF_SIZE > 0)\r
- #if (USBFS_1_MIDI_IN_BUFF_SIZE >= 256)\r
- extern volatile uint16 USBFS_1_midiInPointer; /* Input endpoint buffer pointer */\r
- #else\r
- extern volatile uint8 USBFS_1_midiInPointer; /* Input endpoint buffer pointer */\r
- #endif /* End USBFS_1_MIDI_IN_BUFF_SIZE >=256 */\r
- extern volatile uint8 USBFS_1_midi_in_ep; /* Input endpoint number */\r
- extern uint8 USBFS_1_midiInBuffer[USBFS_1_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */\r
-#endif /* USBFS_1_MIDI_IN_BUFF_SIZE > 0 */\r
-\r
-#if (USBFS_1_MIDI_OUT_BUFF_SIZE > 0)\r
- extern volatile uint8 USBFS_1_midi_out_ep; /* Output endpoint number */\r
- extern uint8 USBFS_1_midiOutBuffer[USBFS_1_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */\r
-#endif /* USBFS_1_MIDI_OUT_BUFF_SIZE > 0 */\r
-\r
-#if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF)\r
- extern volatile uint8 USBFS_1_MIDI1_InqFlags; /* Device inquiry flag */\r
- #if (USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF)\r
- extern volatile uint8 USBFS_1_MIDI2_InqFlags; /* Device inquiry flag */\r
- #endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_TWO_EXT_INTRF */\r
-#endif /* End USBFS_1_MIDI_EXT_MODE >= USBFS_1_ONE_EXT_INTRF */\r
-\r
-#endif /* USBFS_1_ENABLE_MIDI_STREAMING */\r
-\r
-\r
-#endif /* End CY_USBFS_USBFS_1_midi_H */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_pm.c\r
-* Version 2.60\r
-*\r
-* Description:\r
-* This file provides Suspend/Resume APIs functionality.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "project.h"\r
-#include "USBFS_1.h"\r
-#include "USBFS_1_pvt.h"\r
-\r
-\r
-/***************************************\r
-* Custom Declarations\r
-***************************************/\r
-/* `#START PM_CUSTOM_DECLARATIONS` Place your declaration here */\r
-\r
-/* `#END` */\r
-\r
-\r
-/***************************************\r
-* Local data allocation\r
-***************************************/\r
-\r
-static USBFS_1_BACKUP_STRUCT USBFS_1_backup;\r
-\r
-\r
-#if(USBFS_1_DP_ISR_REMOVE == 0u)\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_DP_Interrupt\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This Interrupt Service Routine handles DP pin changes for wake-up from\r
- * the sleep mode.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- *******************************************************************************/\r
- CY_ISR(USBFS_1_DP_ISR)\r
- {\r
- /* `#START DP_USER_CODE` Place your code here */\r
-\r
- /* `#END` */\r
-\r
- /* Clears active interrupt */\r
- CY_GET_REG8(USBFS_1_DP_INTSTAT_PTR);\r
- }\r
-\r
-#endif /* (USBFS_1_DP_ISR_REMOVE == 0u) */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_SaveConfig\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Saves the current user configuration.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_SaveConfig(void) \r
-{\r
-\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_RestoreConfig\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Restores the current user configuration.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_RestoreConfig(void) \r
-{\r
- if(USBFS_1_configuration != 0u)\r
- {\r
- USBFS_1_ConfigReg();\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_Suspend\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This function disables the USBFS block and prepares for power donwn mode.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_1_backup.enable: modified.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_Suspend(void) \r
-{\r
- uint8 enableInterrupts;\r
- enableInterrupts = CyEnterCriticalSection();\r
-\r
- if((CY_GET_REG8(USBFS_1_CR0_PTR) & USBFS_1_CR0_ENABLE) != 0u)\r
- { /* USB block is enabled */\r
- USBFS_1_backup.enableState = 1u;\r
-\r
- #if(USBFS_1_EP_MM != USBFS_1__EP_MANUAL)\r
- USBFS_1_Stop_DMA(USBFS_1_MAX_EP); /* Stop all DMAs */\r
- #endif /* End USBFS_1_EP_MM != USBFS_1__EP_MANUAL */\r
-\r
- /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */\r
- USBFS_1_USBIO_CR0_REG &= (uint8)~USBFS_1_USBIO_CR0_TEN;\r
- CyDelayUs(0u); /*~50ns delay */\r
-\r
- /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) and pd_pullup_hv(Inverted) high. */\r
- USBFS_1_PM_USB_CR0_REG &=\r
- (uint8)~(USBFS_1_PM_USB_CR0_PD_N | USBFS_1_PM_USB_CR0_PD_PULLUP_N);\r
-\r
- /* Disable the SIE */\r
- USBFS_1_CR0_REG &= (uint8)~USBFS_1_CR0_ENABLE;\r
-\r
- CyDelayUs(0u); /*~50ns delay */\r
- /* Store mode and Disable VRegulator*/\r
- USBFS_1_backup.mode = USBFS_1_CR1_REG & USBFS_1_CR1_REG_ENABLE;\r
- USBFS_1_CR1_REG &= (uint8)~USBFS_1_CR1_REG_ENABLE;\r
-\r
- CyDelayUs(1u); /* 0.5 us min delay */\r
- /* Disable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/\r
- USBFS_1_PM_USB_CR0_REG &= (uint8)~USBFS_1_PM_USB_CR0_REF_EN;\r
-\r
- /* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pullup*/\r
- USBFS_1_USBIO_CR1_REG |= USBFS_1_USBIO_CR1_IOMODE;\r
-\r
- /* Disable USB in ACT PM */\r
- USBFS_1_PM_ACT_CFG_REG &= (uint8)~USBFS_1_PM_ACT_EN_FSUSB;\r
- /* Disable USB block for Standby Power Mode */\r
- USBFS_1_PM_STBY_CFG_REG &= (uint8)~USBFS_1_PM_STBY_EN_FSUSB;\r
- CyDelayUs(1u); /* min 0.5us delay required */\r
-\r
- }\r
- else\r
- {\r
- USBFS_1_backup.enableState = 0u;\r
- }\r
- CyExitCriticalSection(enableInterrupts);\r
-\r
- /* Set the DP Interrupt for wake-up from sleep mode. */\r
- #if(USBFS_1_DP_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_1_DP_INTC_VECT_NUM, &USBFS_1_DP_ISR);\r
- CyIntSetPriority(USBFS_1_DP_INTC_VECT_NUM, USBFS_1_DP_INTC_PRIOR);\r
- CyIntClearPending(USBFS_1_DP_INTC_VECT_NUM);\r
- CyIntEnable(USBFS_1_DP_INTC_VECT_NUM);\r
- #endif /* (USBFS_1_DP_ISR_REMOVE == 0u) */\r
-\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_Resume\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This function enables the USBFS block after power down mode.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* USBFS_1_backup - checked.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_Resume(void) \r
-{\r
- uint8 enableInterrupts;\r
- enableInterrupts = CyEnterCriticalSection();\r
-\r
- if(USBFS_1_backup.enableState != 0u)\r
- {\r
- #if(USBFS_1_DP_ISR_REMOVE == 0u)\r
- CyIntDisable(USBFS_1_DP_INTC_VECT_NUM);\r
- #endif /* End USBFS_1_DP_ISR_REMOVE */\r
-\r
- /* Enable USB block */\r
- USBFS_1_PM_ACT_CFG_REG |= USBFS_1_PM_ACT_EN_FSUSB;\r
- /* Enable USB block for Standby Power Mode */\r
- USBFS_1_PM_STBY_CFG_REG |= USBFS_1_PM_STBY_EN_FSUSB;\r
- /* Enable core clock */\r
- USBFS_1_USB_CLK_EN_REG |= USBFS_1_USB_CLK_ENABLE;\r
-\r
- /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/\r
- USBFS_1_PM_USB_CR0_REG |= USBFS_1_PM_USB_CR0_REF_EN;\r
- /* The reference will be available ~40us after power restored */\r
- CyDelayUs(40u);\r
- /* Return VRegulator*/\r
- USBFS_1_CR1_REG |= USBFS_1_backup.mode;\r
- CyDelayUs(0u); /*~50ns delay */\r
- /* Enable USBIO */\r
- USBFS_1_PM_USB_CR0_REG |= USBFS_1_PM_USB_CR0_PD_N;\r
- CyDelayUs(2u);\r
- /* Set the USBIO pull-up enable */\r
- USBFS_1_PM_USB_CR0_REG |= USBFS_1_PM_USB_CR0_PD_PULLUP_N;\r
-\r
- /* Reinit Arbiter configuration for DMA transfers */\r
- #if(USBFS_1_EP_MM != USBFS_1__EP_MANUAL)\r
- /* usb arb interrupt enable */\r
- USBFS_1_ARB_INT_EN_REG = USBFS_1_ARB_INT_MASK;\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL)\r
- USBFS_1_ARB_CFG_REG = USBFS_1_ARB_CFG_MANUAL_DMA;\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAMANUAL */\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO)\r
- /*Set cfg cmplt this rises DMA request when the full configuration is done */\r
- USBFS_1_ARB_CFG_REG = USBFS_1_ARB_CFG_AUTO_DMA | USBFS_1_ARB_CFG_AUTO_MEM;\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO */\r
- #endif /* End USBFS_1_EP_MM != USBFS_1__EP_MANUAL */\r
-\r
- /* STALL_IN_OUT */\r
- CY_SET_REG8(USBFS_1_EP0_CR_PTR, USBFS_1_MODE_STALL_IN_OUT);\r
- /* Enable the SIE with a last address */\r
- USBFS_1_CR0_REG |= USBFS_1_CR0_ENABLE;\r
- CyDelayCycles(1u);\r
- /* Finally, Enable d+ pullup and select iomode to USB mode*/\r
- CY_SET_REG8(USBFS_1_USBIO_CR1_PTR, USBFS_1_USBIO_CR1_USBPUEN);\r
-\r
- /* Restore USB register settings */\r
- USBFS_1_RestoreConfig();\r
-\r
- }\r
- CyExitCriticalSection(enableInterrupts);\r
-}\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: .h\r
-* Version 2.60\r
-*\r
-* Description:\r
-* This private file provides constants and parameter values for the\r
-* USBFS Component.\r
-* Please do not use this file or its content in your project.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_USBFS_USBFS_1_pvt_H)\r
-#define CY_USBFS_USBFS_1_pvt_H\r
-\r
-\r
-/***************************************\r
-* Private Variables\r
-***************************************/\r
-\r
-/* Generated external references for descriptors*/\r
-extern const uint8 CYCODE USBFS_1_DEVICE0_DESCR[18u];\r
-extern const uint8 CYCODE USBFS_1_DEVICE0_CONFIGURATION0_DESCR[25u];\r
-extern const T_USBFS_1_EP_SETTINGS_BLOCK CYCODE USBFS_1_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[1u];\r
-extern const uint8 CYCODE USBFS_1_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[1u];\r
-extern const T_USBFS_1_LUT CYCODE USBFS_1_DEVICE0_CONFIGURATION0_TABLE[4u];\r
-extern const T_USBFS_1_LUT CYCODE USBFS_1_DEVICE0_TABLE[2u];\r
-extern const T_USBFS_1_LUT CYCODE USBFS_1_TABLE[1u];\r
-\r
-\r
-extern const uint8 CYCODE USBFS_1_MSOS_DESCRIPTOR[USBFS_1_MSOS_DESCRIPTOR_LENGTH];\r
-extern const uint8 CYCODE USBFS_1_MSOS_CONFIGURATION_DESCR[USBFS_1_MSOS_CONF_DESCR_LENGTH];\r
-#if defined(USBFS_1_ENABLE_IDSN_STRING)\r
- extern uint8 USBFS_1_idSerialNumberStringDescriptor[USBFS_1_IDSN_DESCR_LENGTH];\r
-#endif /* USBFS_1_ENABLE_IDSN_STRING */\r
-\r
-extern volatile uint8 USBFS_1_interfaceNumber;\r
-extern volatile uint8 USBFS_1_interfaceSetting[USBFS_1_MAX_INTERFACES_NUMBER];\r
-extern volatile uint8 USBFS_1_interfaceSetting_last[USBFS_1_MAX_INTERFACES_NUMBER];\r
-extern volatile uint8 USBFS_1_deviceAddress;\r
-extern volatile uint8 USBFS_1_interfaceStatus[USBFS_1_MAX_INTERFACES_NUMBER];\r
-extern const uint8 CYCODE *USBFS_1_interfaceClass;\r
-\r
-extern volatile T_USBFS_1_EP_CTL_BLOCK USBFS_1_EP[USBFS_1_MAX_EP];\r
-extern volatile T_USBFS_1_TD USBFS_1_currentTD;\r
-\r
-#if(USBFS_1_EP_MM != USBFS_1__EP_MANUAL)\r
- extern uint8 USBFS_1_DmaChan[USBFS_1_MAX_EP];\r
- extern uint8 USBFS_1_DmaTd[USBFS_1_MAX_EP];\r
-#endif /* End USBFS_1_EP_MM */\r
-\r
-extern volatile uint8 USBFS_1_ep0Toggle;\r
-extern volatile uint8 USBFS_1_lastPacketSize;\r
-extern volatile uint8 USBFS_1_ep0Mode;\r
-extern volatile uint8 USBFS_1_ep0Count;\r
-extern volatile uint16 USBFS_1_transferByteCount;\r
-\r
-\r
-/***************************************\r
-* Private Function Prototypes\r
-***************************************/\r
-void USBFS_1_ReInitComponent(void) ;\r
-void USBFS_1_HandleSetup(void) ;\r
-void USBFS_1_HandleIN(void) ;\r
-void USBFS_1_HandleOUT(void) ;\r
-void USBFS_1_LoadEP0(void) ;\r
-uint8 USBFS_1_InitControlRead(void) ;\r
-uint8 USBFS_1_InitControlWrite(void) ;\r
-void USBFS_1_ControlReadDataStage(void) ;\r
-void USBFS_1_ControlReadStatusStage(void) ;\r
-void USBFS_1_ControlReadPrematureStatus(void)\r
- ;\r
-uint8 USBFS_1_InitControlWrite(void) ;\r
-uint8 USBFS_1_InitZeroLengthControlTransfer(void)\r
- ;\r
-void USBFS_1_ControlWriteDataStage(void) ;\r
-void USBFS_1_ControlWriteStatusStage(void) ;\r
-void USBFS_1_ControlWritePrematureStatus(void)\r
- ;\r
-uint8 USBFS_1_InitNoDataControlTransfer(void) ;\r
-void USBFS_1_NoDataControlStatusStage(void) ;\r
-void USBFS_1_InitializeStatusBlock(void) ;\r
-void USBFS_1_UpdateStatusBlock(uint8 completionCode) ;\r
-uint8 USBFS_1_DispatchClassRqst(void) ;\r
-\r
-void USBFS_1_Config(uint8 clearAltSetting) ;\r
-void USBFS_1_ConfigAltChanged(void) ;\r
-void USBFS_1_ConfigReg(void) ;\r
-\r
-const T_USBFS_1_LUT CYCODE *USBFS_1_GetConfigTablePtr(uint8 c)\r
- ;\r
-const T_USBFS_1_LUT CYCODE *USBFS_1_GetDeviceTablePtr(void)\r
- ;\r
-const uint8 CYCODE *USBFS_1_GetInterfaceClassTablePtr(void)\r
- ;\r
-uint8 USBFS_1_ClearEndpointHalt(void) ;\r
-uint8 USBFS_1_SetEndpointHalt(void) ;\r
-uint8 USBFS_1_ValidateAlternateSetting(void) ;\r
-\r
-void USBFS_1_SaveConfig(void) ;\r
-void USBFS_1_RestoreConfig(void) ;\r
-\r
-#if defined(USBFS_1_ENABLE_IDSN_STRING)\r
- void USBFS_1_ReadDieID(uint8 descr[]) ;\r
-#endif /* USBFS_1_ENABLE_IDSN_STRING */\r
-\r
-#if defined(USBFS_1_ENABLE_HID_CLASS)\r
- uint8 USBFS_1_DispatchHIDClassRqst(void);\r
-#endif /* End USBFS_1_ENABLE_HID_CLASS */\r
-#if defined(USBFS_1_ENABLE_AUDIO_CLASS)\r
- uint8 USBFS_1_DispatchAUDIOClassRqst(void);\r
-#endif /* End USBFS_1_ENABLE_HID_CLASS */\r
-#if defined(USBFS_1_ENABLE_CDC_CLASS)\r
- uint8 USBFS_1_DispatchCDCClassRqst(void);\r
-#endif /* End USBFS_1_ENABLE_CDC_CLASS */\r
-\r
-CY_ISR_PROTO(USBFS_1_EP_0_ISR);\r
-#if(USBFS_1_EP1_ISR_REMOVE == 0u)\r
- CY_ISR_PROTO(USBFS_1_EP_1_ISR);\r
-#endif /* End USBFS_1_EP1_ISR_REMOVE */\r
-#if(USBFS_1_EP2_ISR_REMOVE == 0u)\r
- CY_ISR_PROTO(USBFS_1_EP_2_ISR);\r
-#endif /* End USBFS_1_EP2_ISR_REMOVE */\r
-#if(USBFS_1_EP3_ISR_REMOVE == 0u)\r
- CY_ISR_PROTO(USBFS_1_EP_3_ISR);\r
-#endif /* End USBFS_1_EP3_ISR_REMOVE */\r
-#if(USBFS_1_EP4_ISR_REMOVE == 0u)\r
- CY_ISR_PROTO(USBFS_1_EP_4_ISR);\r
-#endif /* End USBFS_1_EP4_ISR_REMOVE */\r
-#if(USBFS_1_EP5_ISR_REMOVE == 0u)\r
- CY_ISR_PROTO(USBFS_1_EP_5_ISR);\r
-#endif /* End USBFS_1_EP5_ISR_REMOVE */\r
-#if(USBFS_1_EP6_ISR_REMOVE == 0u)\r
- CY_ISR_PROTO(USBFS_1_EP_6_ISR);\r
-#endif /* End USBFS_1_EP6_ISR_REMOVE */\r
-#if(USBFS_1_EP7_ISR_REMOVE == 0u)\r
- CY_ISR_PROTO(USBFS_1_EP_7_ISR);\r
-#endif /* End USBFS_1_EP7_ISR_REMOVE */\r
-#if(USBFS_1_EP8_ISR_REMOVE == 0u)\r
- CY_ISR_PROTO(USBFS_1_EP_8_ISR);\r
-#endif /* End USBFS_1_EP8_ISR_REMOVE */\r
-CY_ISR_PROTO(USBFS_1_BUS_RESET_ISR);\r
-#if(USBFS_1_SOF_ISR_REMOVE == 0u)\r
- CY_ISR_PROTO(USBFS_1_SOF_ISR);\r
-#endif /* End USBFS_1_SOF_ISR_REMOVE */\r
-#if(USBFS_1_EP_MM != USBFS_1__EP_MANUAL)\r
- CY_ISR_PROTO(USBFS_1_ARB_ISR);\r
-#endif /* End USBFS_1_EP_MM */\r
-#if(USBFS_1_DP_ISR_REMOVE == 0u)\r
- CY_ISR_PROTO(USBFS_1_DP_ISR);\r
-#endif /* End USBFS_1_DP_ISR_REMOVE */\r
-\r
-\r
-/***************************************\r
-* Request Handlers\r
-***************************************/\r
-\r
-uint8 USBFS_1_HandleStandardRqst(void) ;\r
-uint8 USBFS_1_DispatchClassRqst(void) ;\r
-uint8 USBFS_1_HandleVendorRqst(void) ;\r
-\r
-\r
-/***************************************\r
-* HID Internal references\r
-***************************************/\r
-#if defined(USBFS_1_ENABLE_HID_CLASS)\r
- void USBFS_1_FindReport(void) ;\r
- void USBFS_1_FindReportDescriptor(void) ;\r
- void USBFS_1_FindHidClassDecriptor(void) ;\r
-#endif /* USBFS_1_ENABLE_HID_CLASS */\r
-\r
-\r
-/***************************************\r
-* MIDI Internal references\r
-***************************************/\r
-#if defined(USBFS_1_ENABLE_MIDI_STREAMING)\r
- void USBFS_1_MIDI_IN_EP_Service(void) ;\r
-#endif /* USBFS_1_ENABLE_MIDI_STREAMING */\r
-\r
-\r
-#endif /* CY_USBFS_USBFS_1_pvt_H */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_std.c\r
-* Version 2.60\r
-*\r
-* Description:\r
-* USB Standard request handler.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "USBFS_1.h"\r
-#include "USBFS_1_cdc.h"\r
-#include "USBFS_1_pvt.h"\r
-#if defined(USBFS_1_ENABLE_MIDI_STREAMING) \r
- #include "USBFS_1_midi.h"\r
-#endif /* End USBFS_1_ENABLE_MIDI_STREAMING*/\r
-\r
-\r
-/***************************************\r
-* Static data allocation\r
-***************************************/\r
-\r
-#if defined(USBFS_1_ENABLE_FWSN_STRING)\r
- static volatile uint8 *USBFS_1_fwSerialNumberStringDescriptor;\r
- static volatile uint8 USBFS_1_snStringConfirm = USBFS_1_FALSE;\r
-#endif /* USBFS_1_ENABLE_FWSN_STRING */\r
-\r
-#if defined(USBFS_1_ENABLE_FWSN_STRING)\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: USBFS_1_SerialNumString\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Application firmware may supply the source of the USB device descriptors\r
- * serial number string during runtime.\r
- *\r
- * Parameters:\r
- * snString: pointer to string.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- *******************************************************************************/\r
- void USBFS_1_SerialNumString(uint8 snString[]) \r
- {\r
- USBFS_1_snStringConfirm = USBFS_1_FALSE;\r
- if(snString != NULL)\r
- {\r
- USBFS_1_fwSerialNumberStringDescriptor = snString;\r
- /* Check descriptor validation */\r
- if( (snString[0u] > 1u ) && (snString[1u] == USBFS_1_DESCR_STRING) )\r
- {\r
- USBFS_1_snStringConfirm = USBFS_1_TRUE;\r
- }\r
- }\r
- }\r
-\r
-#endif /* USBFS_1_ENABLE_FWSN_STRING */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_HandleStandardRqst\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This Routine dispatches standard requests\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* TRUE if request handled.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_HandleStandardRqst(void) \r
-{\r
- uint8 requestHandled = USBFS_1_FALSE;\r
- uint8 interfaceNumber;\r
- #if defined(USBFS_1_ENABLE_STRINGS)\r
- volatile uint8 *pStr = 0u;\r
- #if defined(USBFS_1_ENABLE_DESCRIPTOR_STRINGS)\r
- uint8 nStr;\r
- uint8 descrLength;\r
- #endif /* USBFS_1_ENABLE_DESCRIPTOR_STRINGS */\r
- #endif /* USBFS_1_ENABLE_STRINGS */\r
- static volatile uint8 USBFS_1_tBuffer[USBFS_1_STATUS_LENGTH_MAX];\r
- const T_USBFS_1_LUT CYCODE *pTmp;\r
- USBFS_1_currentTD.count = 0u;\r
-\r
- if ((CY_GET_REG8(USBFS_1_bmRequestType) & USBFS_1_RQST_DIR_MASK) == USBFS_1_RQST_DIR_D2H)\r
- {\r
- /* Control Read */\r
- switch (CY_GET_REG8(USBFS_1_bRequest))\r
- {\r
- case USBFS_1_GET_DESCRIPTOR:\r
- if (CY_GET_REG8(USBFS_1_wValueHi) == USBFS_1_DESCR_DEVICE)\r
- {\r
- pTmp = USBFS_1_GetDeviceTablePtr();\r
- USBFS_1_currentTD.pData = (volatile uint8 *)pTmp->p_list;\r
- USBFS_1_currentTD.count = USBFS_1_DEVICE_DESCR_LENGTH;\r
- requestHandled = USBFS_1_InitControlRead();\r
- }\r
- else if (CY_GET_REG8(USBFS_1_wValueHi) == USBFS_1_DESCR_CONFIG)\r
- {\r
- pTmp = USBFS_1_GetConfigTablePtr(CY_GET_REG8(USBFS_1_wValueLo));\r
- USBFS_1_currentTD.pData = (volatile uint8 *)pTmp->p_list;\r
- USBFS_1_currentTD.count = ((uint16)(USBFS_1_currentTD.pData)[ \\r
- USBFS_1_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \\r
- (USBFS_1_currentTD.pData)[USBFS_1_CONFIG_DESCR_TOTAL_LENGTH_LOW];\r
- requestHandled = USBFS_1_InitControlRead();\r
- }\r
- #if defined(USBFS_1_ENABLE_STRINGS)\r
- else if (CY_GET_REG8(USBFS_1_wValueHi) == USBFS_1_DESCR_STRING)\r
- {\r
- /* Descriptor Strings*/\r
- #if defined(USBFS_1_ENABLE_DESCRIPTOR_STRINGS)\r
- nStr = 0u;\r
- pStr = (volatile uint8 *)&USBFS_1_STRING_DESCRIPTORS[0u];\r
- while ( (CY_GET_REG8(USBFS_1_wValueLo) > nStr) && (*pStr != 0u) )\r
- {\r
- /* Read descriptor length from 1st byte */\r
- descrLength = *pStr;\r
- /* Move to next string descriptor */\r
- pStr = &pStr[descrLength];\r
- nStr++;\r
- }\r
- #endif /* End USBFS_1_ENABLE_DESCRIPTOR_STRINGS */\r
- /* Microsoft OS String*/\r
- #if defined(USBFS_1_ENABLE_MSOS_STRING)\r
- if( CY_GET_REG8(USBFS_1_wValueLo) == USBFS_1_STRING_MSOS )\r
- {\r
- pStr = (volatile uint8 *)&USBFS_1_MSOS_DESCRIPTOR[0u];\r
- }\r
- #endif /* End USBFS_1_ENABLE_MSOS_STRING*/\r
- /* SN string */\r
- #if defined(USBFS_1_ENABLE_SN_STRING)\r
- if( (CY_GET_REG8(USBFS_1_wValueLo) != 0u) &&\r
- (CY_GET_REG8(USBFS_1_wValueLo) ==\r
- USBFS_1_DEVICE0_DESCR[USBFS_1_DEVICE_DESCR_SN_SHIFT]) )\r
- {\r
- pStr = (volatile uint8 *)&USBFS_1_SN_STRING_DESCRIPTOR[0u];\r
- #if defined(USBFS_1_ENABLE_FWSN_STRING)\r
- if(USBFS_1_snStringConfirm != USBFS_1_FALSE)\r
- {\r
- pStr = USBFS_1_fwSerialNumberStringDescriptor;\r
- }\r
- #endif /* USBFS_1_ENABLE_FWSN_STRING */\r
- #if defined(USBFS_1_ENABLE_IDSN_STRING)\r
- /* Read DIE ID and generate string descriptor in RAM */\r
- USBFS_1_ReadDieID(USBFS_1_idSerialNumberStringDescriptor);\r
- pStr = USBFS_1_idSerialNumberStringDescriptor;\r
- #endif /* End USBFS_1_ENABLE_IDSN_STRING */\r
- }\r
- #endif /* End USBFS_1_ENABLE_SN_STRING */\r
- if (*pStr != 0u)\r
- {\r
- USBFS_1_currentTD.count = *pStr;\r
- USBFS_1_currentTD.pData = pStr;\r
- requestHandled = USBFS_1_InitControlRead();\r
- }\r
- }\r
- #endif /* End USBFS_1_ENABLE_STRINGS */\r
- else\r
- {\r
- requestHandled = USBFS_1_DispatchClassRqst();\r
- }\r
- break;\r
- case USBFS_1_GET_STATUS:\r
- switch ((CY_GET_REG8(USBFS_1_bmRequestType) & USBFS_1_RQST_RCPT_MASK))\r
- {\r
- case USBFS_1_RQST_RCPT_EP:\r
- USBFS_1_currentTD.count = USBFS_1_EP_STATUS_LENGTH;\r
- USBFS_1_tBuffer[0u] = USBFS_1_EP[ \\r
- CY_GET_REG8(USBFS_1_wIndexLo) & USBFS_1_DIR_UNUSED].hwEpState;\r
- USBFS_1_tBuffer[1u] = 0u;\r
- USBFS_1_currentTD.pData = &USBFS_1_tBuffer[0u];\r
- requestHandled = USBFS_1_InitControlRead();\r
- break;\r
- case USBFS_1_RQST_RCPT_DEV:\r
- USBFS_1_currentTD.count = USBFS_1_DEVICE_STATUS_LENGTH;\r
- USBFS_1_tBuffer[0u] = USBFS_1_deviceStatus;\r
- USBFS_1_tBuffer[1u] = 0u;\r
- USBFS_1_currentTD.pData = &USBFS_1_tBuffer[0u];\r
- requestHandled = USBFS_1_InitControlRead();\r
- break;\r
- default: /* requestHandled is initialized as FALSE by default */\r
- break;\r
- }\r
- break;\r
- case USBFS_1_GET_CONFIGURATION:\r
- USBFS_1_currentTD.count = 1u;\r
- USBFS_1_currentTD.pData = (volatile uint8 *)&USBFS_1_configuration;\r
- requestHandled = USBFS_1_InitControlRead();\r
- break;\r
- case USBFS_1_GET_INTERFACE:\r
- USBFS_1_currentTD.count = 1u;\r
- USBFS_1_currentTD.pData = (volatile uint8 *)&USBFS_1_interfaceSetting[ \\r
- CY_GET_REG8(USBFS_1_wIndexLo)];\r
- requestHandled = USBFS_1_InitControlRead();\r
- break;\r
- default: /* requestHandled is initialized as FALSE by default */\r
- break;\r
- }\r
- }\r
- else {\r
- /* Control Write */\r
- switch (CY_GET_REG8(USBFS_1_bRequest))\r
- {\r
- case USBFS_1_SET_ADDRESS:\r
- USBFS_1_deviceAddress = CY_GET_REG8(USBFS_1_wValueLo);\r
- requestHandled = USBFS_1_InitNoDataControlTransfer();\r
- break;\r
- case USBFS_1_SET_CONFIGURATION:\r
- USBFS_1_configuration = CY_GET_REG8(USBFS_1_wValueLo);\r
- USBFS_1_configurationChanged = USBFS_1_TRUE;\r
- USBFS_1_Config(USBFS_1_TRUE);\r
- requestHandled = USBFS_1_InitNoDataControlTransfer();\r
- break;\r
- case USBFS_1_SET_INTERFACE:\r
- if (USBFS_1_ValidateAlternateSetting() != 0u)\r
- {\r
- interfaceNumber = CY_GET_REG8(USBFS_1_wIndexLo);\r
- USBFS_1_interfaceNumber = interfaceNumber;\r
- USBFS_1_configurationChanged = USBFS_1_TRUE;\r
- #if ((USBFS_1_EP_MA == USBFS_1__MA_DYNAMIC) && \\r
- (USBFS_1_EP_MM == USBFS_1__EP_MANUAL) )\r
- USBFS_1_Config(USBFS_1_FALSE);\r
- #else\r
- USBFS_1_ConfigAltChanged();\r
- #endif /* End (USBFS_1_EP_MA == USBFS_1__MA_DYNAMIC) */\r
- /* Update handled Alt setting changes status */\r
- USBFS_1_interfaceSetting_last[interfaceNumber] =\r
- USBFS_1_interfaceSetting[interfaceNumber];\r
- requestHandled = USBFS_1_InitNoDataControlTransfer();\r
- }\r
- break;\r
- case USBFS_1_CLEAR_FEATURE:\r
- switch (CY_GET_REG8(USBFS_1_bmRequestType) & USBFS_1_RQST_RCPT_MASK)\r
- {\r
- case USBFS_1_RQST_RCPT_EP:\r
- if (CY_GET_REG8(USBFS_1_wValueLo) == USBFS_1_ENDPOINT_HALT)\r
- {\r
- requestHandled = USBFS_1_ClearEndpointHalt();\r
- }\r
- break;\r
- case USBFS_1_RQST_RCPT_DEV:\r
- /* Clear device REMOTE_WAKEUP */\r
- if (CY_GET_REG8(USBFS_1_wValueLo) == USBFS_1_DEVICE_REMOTE_WAKEUP)\r
- {\r
- USBFS_1_deviceStatus &= (uint8)~USBFS_1_DEVICE_STATUS_REMOTE_WAKEUP;\r
- requestHandled = USBFS_1_InitNoDataControlTransfer();\r
- }\r
- break;\r
- case USBFS_1_RQST_RCPT_IFC:\r
- /* Validate interfaceNumber */\r
- if (CY_GET_REG8(USBFS_1_wIndexLo) < USBFS_1_MAX_INTERFACES_NUMBER)\r
- {\r
- USBFS_1_interfaceStatus[CY_GET_REG8(USBFS_1_wIndexLo)] &=\r
- (uint8)~(CY_GET_REG8(USBFS_1_wValueLo));\r
- requestHandled = USBFS_1_InitNoDataControlTransfer();\r
- }\r
- break;\r
- default: /* requestHandled is initialized as FALSE by default */\r
- break;\r
- }\r
- break;\r
- case USBFS_1_SET_FEATURE:\r
- switch (CY_GET_REG8(USBFS_1_bmRequestType) & USBFS_1_RQST_RCPT_MASK)\r
- {\r
- case USBFS_1_RQST_RCPT_EP:\r
- if (CY_GET_REG8(USBFS_1_wValueLo) == USBFS_1_ENDPOINT_HALT)\r
- {\r
- requestHandled = USBFS_1_SetEndpointHalt();\r
- }\r
- break;\r
- case USBFS_1_RQST_RCPT_DEV:\r
- /* Set device REMOTE_WAKEUP */\r
- if (CY_GET_REG8(USBFS_1_wValueLo) == USBFS_1_DEVICE_REMOTE_WAKEUP)\r
- {\r
- USBFS_1_deviceStatus |= USBFS_1_DEVICE_STATUS_REMOTE_WAKEUP;\r
- requestHandled = USBFS_1_InitNoDataControlTransfer();\r
- }\r
- break;\r
- case USBFS_1_RQST_RCPT_IFC:\r
- /* Validate interfaceNumber */\r
- if (CY_GET_REG8(USBFS_1_wIndexLo) < USBFS_1_MAX_INTERFACES_NUMBER)\r
- {\r
- USBFS_1_interfaceStatus[CY_GET_REG8(USBFS_1_wIndexLo)] &=\r
- (uint8)~(CY_GET_REG8(USBFS_1_wValueLo));\r
- requestHandled = USBFS_1_InitNoDataControlTransfer();\r
- }\r
- break;\r
- default: /* requestHandled is initialized as FALSE by default */\r
- break;\r
- }\r
- break;\r
- default: /* requestHandled is initialized as FALSE by default */\r
- break;\r
- }\r
- }\r
- return(requestHandled);\r
-}\r
-\r
-\r
-#if defined(USBFS_1_ENABLE_IDSN_STRING)\r
-\r
- /***************************************************************************\r
- * Function Name: USBFS_1_ReadDieID\r
- ****************************************************************************\r
- *\r
- * Summary:\r
- * This routine read Die ID and generate Serial Number string descriptor.\r
- *\r
- * Parameters:\r
- * descr: pointer on string descriptor.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- * Reentrant:\r
- * No.\r
- *\r
- ***************************************************************************/\r
- void USBFS_1_ReadDieID(uint8 descr[]) \r
- {\r
- uint8 i;\r
- uint8 j = 0u;\r
- uint8 value;\r
- const char8 CYCODE hex[16u] = "0123456789ABCDEF";\r
-\r
-\r
- /* Check descriptor validation */\r
- if( descr != NULL)\r
- {\r
- descr[0u] = USBFS_1_IDSN_DESCR_LENGTH;\r
- descr[1u] = USBFS_1_DESCR_STRING;\r
-\r
- /* fill descriptor */\r
- for(i = 2u; i < USBFS_1_IDSN_DESCR_LENGTH; i += 4u)\r
- {\r
- value = CY_GET_XTND_REG8((void CYFAR *)(USBFS_1_DIE_ID + j));\r
- j++;\r
- descr[i] = (uint8)hex[value >> 4u];\r
- descr[i + 2u] = (uint8)hex[value & 0x0Fu];\r
- }\r
- }\r
- }\r
-\r
-#endif /* End USBFS_1_ENABLE_IDSN_STRING */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_ConfigReg\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine configures hardware registers from the variables.\r
-* It is called from USBFS_1_Config() function and from RestoreConfig\r
-* after Wakeup.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_ConfigReg(void) \r
-{\r
- uint8 ep;\r
- uint8 i;\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO)\r
- uint8 ep_type = 0u;\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO */\r
-\r
- /* Set the endpoint buffer addresses */\r
- ep = USBFS_1_EP1;\r
- for (i = 0u; i < 0x80u; i+= 0x10u)\r
- {\r
- CY_SET_REG8((reg8 *)(USBFS_1_ARB_EP1_CFG_IND + i), USBFS_1_ARB_EPX_CFG_CRC_BYPASS |\r
- USBFS_1_ARB_EPX_CFG_RESET);\r
-\r
- #if(USBFS_1_EP_MM != USBFS_1__EP_MANUAL)\r
- /* Enable all Arbiter EP Interrupts : err, buf under, buf over, dma gnt(mode2 only), in buf full */\r
- CY_SET_REG8((reg8 *)(USBFS_1_ARB_EP1_INT_EN_IND + i), USBFS_1_ARB_EPX_INT_MASK);\r
- #endif /* End USBFS_1_EP_MM != USBFS_1__EP_MANUAL */\r
-\r
- if(USBFS_1_EP[ep].epMode != USBFS_1_MODE_DISABLE)\r
- {\r
- if((USBFS_1_EP[ep].addr & USBFS_1_DIR_IN) != 0u )\r
- {\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + i), USBFS_1_MODE_NAK_IN);\r
- }\r
- else\r
- {\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + i), USBFS_1_MODE_NAK_OUT);\r
- /* Prepare EP type mask for automatic memory allocation */\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO)\r
- ep_type |= (uint8)(0x01u << (ep - USBFS_1_EP1));\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO */\r
- }\r
- }\r
- else\r
- {\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + i), USBFS_1_MODE_STALL_DATA_EP);\r
- }\r
-\r
- #if(USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO)\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CNT0_IND + i), USBFS_1_EP[ep].bufferSize >> 8u);\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CNT1_IND + i), USBFS_1_EP[ep].bufferSize & 0xFFu);\r
-\r
- CY_SET_REG8((reg8 *)(USBFS_1_ARB_RW1_RA_IND + i), USBFS_1_EP[ep].buffOffset & 0xFFu);\r
- CY_SET_REG8((reg8 *)(USBFS_1_ARB_RW1_RA_MSB_IND + i), USBFS_1_EP[ep].buffOffset >> 8u);\r
- CY_SET_REG8((reg8 *)(USBFS_1_ARB_RW1_WA_IND + i), USBFS_1_EP[ep].buffOffset & 0xFFu);\r
- CY_SET_REG8((reg8 *)(USBFS_1_ARB_RW1_WA_MSB_IND + i), USBFS_1_EP[ep].buffOffset >> 8u);\r
- #endif /* End USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO */\r
-\r
- ep++;\r
- }\r
-\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO)\r
- /* BUF_SIZE depend on DMA_THRESS value: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */\r
- USBFS_1_BUF_SIZE_REG = USBFS_1_DMA_BUF_SIZE;\r
- USBFS_1_DMA_THRES_REG = USBFS_1_DMA_BYTES_PER_BURST; /* DMA burst threshold */\r
- USBFS_1_DMA_THRES_MSB_REG = 0u;\r
- USBFS_1_EP_ACTIVE_REG = USBFS_1_ARB_INT_MASK;\r
- USBFS_1_EP_TYPE_REG = ep_type;\r
- /* Cfg_cmp bit set to 1 once configuration is complete. */\r
- USBFS_1_ARB_CFG_REG = USBFS_1_ARB_CFG_AUTO_DMA | USBFS_1_ARB_CFG_AUTO_MEM |\r
- USBFS_1_ARB_CFG_CFG_CPM;\r
- /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */\r
- USBFS_1_ARB_CFG_REG = USBFS_1_ARB_CFG_AUTO_DMA | USBFS_1_ARB_CFG_AUTO_MEM;\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO */\r
-\r
- CY_SET_REG8(USBFS_1_SIE_EP_INT_EN_PTR, 0xFFu);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_Config\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine configures endpoints for the entire configuration by scanning\r
-* the configuration descriptor.\r
-*\r
-* Parameters:\r
-* clearAltSetting: It configures the bAlternateSetting 0 for each interface.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* USBFS_1_interfaceClass - Initialized class array for each interface.\r
-* It is used for handling Class specific requests depend on interface class.\r
-* Different classes in multiple Alternate settings does not supported.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_Config(uint8 clearAltSetting) \r
-{\r
- uint8 ep;\r
- uint8 cur_ep;\r
- uint8 i;\r
- uint8 ep_type;\r
- const uint8 *pDescr;\r
- #if(USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO)\r
- uint16 buffCount = 0u;\r
- #endif /* End USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO */\r
-\r
- const T_USBFS_1_LUT CYCODE *pTmp;\r
- const T_USBFS_1_EP_SETTINGS_BLOCK CYCODE *pEP;\r
-\r
- /* Clear all of the endpoints */\r
- for (ep = 0u; ep < USBFS_1_MAX_EP; ep++)\r
- {\r
- USBFS_1_EP[ep].attrib = 0u;\r
- USBFS_1_EP[ep].hwEpState = 0u;\r
- USBFS_1_EP[ep].apiEpState = USBFS_1_NO_EVENT_PENDING;\r
- USBFS_1_EP[ep].epToggle = 0u;\r
- USBFS_1_EP[ep].epMode = USBFS_1_MODE_DISABLE;\r
- USBFS_1_EP[ep].bufferSize = 0u;\r
- USBFS_1_EP[ep].interface = 0u;\r
-\r
- }\r
-\r
- /* Clear Alternate settings for all interfaces */\r
- if(clearAltSetting != 0u)\r
- {\r
- for (i = 0u; i < USBFS_1_MAX_INTERFACES_NUMBER; i++)\r
- {\r
- USBFS_1_interfaceSetting[i] = 0x00u;\r
- USBFS_1_interfaceSetting_last[i] = 0x00u;\r
- }\r
- }\r
-\r
- /* Init Endpoints and Device Status if configured */\r
- if(USBFS_1_configuration > 0u)\r
- {\r
- pTmp = USBFS_1_GetConfigTablePtr(USBFS_1_configuration - 1u);\r
- /* Set Power status for current configuration */\r
- pDescr = (const uint8 *)pTmp->p_list;\r
- if((pDescr[USBFS_1_CONFIG_DESCR_ATTRIB] & USBFS_1_CONFIG_DESCR_ATTRIB_SELF_POWERED) != 0u)\r
- {\r
- USBFS_1_deviceStatus |= USBFS_1_DEVICE_STATUS_SELF_POWERED;\r
- }\r
- else\r
- {\r
- USBFS_1_deviceStatus &= (uint8)~USBFS_1_DEVICE_STATUS_SELF_POWERED;\r
- }\r
- /* Move to next element */\r
- pTmp = &pTmp[1u];\r
- ep = pTmp->c; /* For this table, c is the number of endpoints configurations */\r
-\r
- #if ((USBFS_1_EP_MA == USBFS_1__MA_DYNAMIC) && \\r
- (USBFS_1_EP_MM == USBFS_1__EP_MANUAL) )\r
- /* Configure for dynamic EP memory allocation */\r
- /* p_list points the endpoint setting table. */\r
- pEP = (T_USBFS_1_EP_SETTINGS_BLOCK *) pTmp->p_list;\r
- for (i = 0u; i < ep; i++)\r
- {\r
- /* Compare current Alternate setting with EP Alt*/\r
- if(USBFS_1_interfaceSetting[pEP->interface] == pEP->altSetting)\r
- {\r
- cur_ep = pEP->addr & USBFS_1_DIR_UNUSED;\r
- ep_type = pEP->attributes & USBFS_1_EP_TYPE_MASK;\r
- if (pEP->addr & USBFS_1_DIR_IN)\r
- {\r
- /* IN Endpoint */\r
- USBFS_1_EP[cur_ep].apiEpState = USBFS_1_EVENT_PENDING;\r
- USBFS_1_EP[cur_ep].epMode = (ep_type == USBFS_1_EP_TYPE_ISOC) ?\r
- USBFS_1_MODE_ISO_IN : USBFS_1_MODE_ACK_IN;\r
- #if defined(USBFS_1_ENABLE_CDC_CLASS)\r
- if(((pEP->bMisc == USBFS_1_CLASS_CDC_DATA) ||\r
- (pEP->bMisc == USBFS_1_CLASS_CDC)) &&\r
- (ep_type != USBFS_1_EP_TYPE_INT))\r
- {\r
- USBFS_1_cdc_data_in_ep = cur_ep;\r
- }\r
- #endif /* End USBFS_1_ENABLE_CDC_CLASS*/\r
- #if ( defined(USBFS_1_ENABLE_MIDI_STREAMING) && \\r
- (USBFS_1_MIDI_IN_BUFF_SIZE > 0) )\r
- if((pEP->bMisc == USBFS_1_CLASS_AUDIO) &&\r
- (ep_type == USBFS_1_EP_TYPE_BULK))\r
- {\r
- USBFS_1_midi_in_ep = cur_ep;\r
- }\r
- #endif /* End USBFS_1_ENABLE_MIDI_STREAMING*/\r
- }\r
- else\r
- {\r
- /* OUT Endpoint */\r
- USBFS_1_EP[cur_ep].apiEpState = USBFS_1_NO_EVENT_PENDING;\r
- USBFS_1_EP[cur_ep].epMode = (ep_type == USBFS_1_EP_TYPE_ISOC) ?\r
- USBFS_1_MODE_ISO_OUT : USBFS_1_MODE_ACK_OUT;\r
- #if defined(USBFS_1_ENABLE_CDC_CLASS)\r
- if(((pEP->bMisc == USBFS_1_CLASS_CDC_DATA) ||\r
- (pEP->bMisc == USBFS_1_CLASS_CDC)) &&\r
- (ep_type != USBFS_1_EP_TYPE_INT))\r
- {\r
- USBFS_1_cdc_data_out_ep = cur_ep;\r
- }\r
- #endif /* End USBFS_1_ENABLE_CDC_CLASS*/\r
- #if ( defined(USBFS_1_ENABLE_MIDI_STREAMING) && \\r
- (USBFS_1_MIDI_OUT_BUFF_SIZE > 0) )\r
- if((pEP->bMisc == USBFS_1_CLASS_AUDIO) &&\r
- (ep_type == USBFS_1_EP_TYPE_BULK))\r
- {\r
- USBFS_1_midi_out_ep = cur_ep;\r
- }\r
- #endif /* End USBFS_1_ENABLE_MIDI_STREAMING*/\r
- }\r
- USBFS_1_EP[cur_ep].bufferSize = pEP->bufferSize;\r
- USBFS_1_EP[cur_ep].addr = pEP->addr;\r
- USBFS_1_EP[cur_ep].attrib = pEP->attributes;\r
- }\r
- pEP = &pEP[1u];\r
- }\r
- #else /* Config for static EP memory allocation */\r
- for (i = USBFS_1_EP1; i < USBFS_1_MAX_EP; i++)\r
- {\r
- /* p_list points the endpoint setting table. */\r
- pEP = (const T_USBFS_1_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list;\r
- /* Find max length for each EP and select it (length could be different in different Alt settings) */\r
- /* but other settings should be correct with regards to Interface alt Setting */\r
- for (cur_ep = 0u; cur_ep < ep; cur_ep++)\r
- {\r
- /* EP count is equal to EP # in table and we found larger EP length than have before*/\r
- if(i == (pEP->addr & USBFS_1_DIR_UNUSED))\r
- {\r
- if(USBFS_1_EP[i].bufferSize < pEP->bufferSize)\r
- {\r
- USBFS_1_EP[i].bufferSize = pEP->bufferSize;\r
- }\r
- /* Compare current Alternate setting with EP Alt*/\r
- if(USBFS_1_interfaceSetting[pEP->interface] == pEP->altSetting)\r
- {\r
- ep_type = pEP->attributes & USBFS_1_EP_TYPE_MASK;\r
- if ((pEP->addr & USBFS_1_DIR_IN) != 0u)\r
- {\r
- /* IN Endpoint */\r
- USBFS_1_EP[i].apiEpState = USBFS_1_EVENT_PENDING;\r
- USBFS_1_EP[i].epMode = (ep_type == USBFS_1_EP_TYPE_ISOC) ?\r
- USBFS_1_MODE_ISO_IN : USBFS_1_MODE_ACK_IN;\r
- /* Find and init CDC IN endpoint number */\r
- #if defined(USBFS_1_ENABLE_CDC_CLASS)\r
- if(((pEP->bMisc == USBFS_1_CLASS_CDC_DATA) ||\r
- (pEP->bMisc == USBFS_1_CLASS_CDC)) &&\r
- (ep_type != USBFS_1_EP_TYPE_INT))\r
- {\r
- USBFS_1_cdc_data_in_ep = i;\r
- }\r
- #endif /* End USBFS_1_ENABLE_CDC_CLASS*/\r
- #if ( defined(USBFS_1_ENABLE_MIDI_STREAMING) && \\r
- (USBFS_1_MIDI_IN_BUFF_SIZE > 0) )\r
- if((pEP->bMisc == USBFS_1_CLASS_AUDIO) &&\r
- (ep_type == USBFS_1_EP_TYPE_BULK))\r
- {\r
- USBFS_1_midi_in_ep = i;\r
- }\r
- #endif /* End USBFS_1_ENABLE_MIDI_STREAMING*/\r
- }\r
- else\r
- {\r
- /* OUT Endpoint */\r
- USBFS_1_EP[i].apiEpState = USBFS_1_NO_EVENT_PENDING;\r
- USBFS_1_EP[i].epMode = (ep_type == USBFS_1_EP_TYPE_ISOC) ?\r
- USBFS_1_MODE_ISO_OUT : USBFS_1_MODE_ACK_OUT;\r
- /* Find and init CDC IN endpoint number */\r
- #if defined(USBFS_1_ENABLE_CDC_CLASS)\r
- if(((pEP->bMisc == USBFS_1_CLASS_CDC_DATA) ||\r
- (pEP->bMisc == USBFS_1_CLASS_CDC)) &&\r
- (ep_type != USBFS_1_EP_TYPE_INT))\r
- {\r
- USBFS_1_cdc_data_out_ep = i;\r
- }\r
- #endif /* End USBFS_1_ENABLE_CDC_CLASS*/\r
- #if ( defined(USBFS_1_ENABLE_MIDI_STREAMING) && \\r
- (USBFS_1_MIDI_OUT_BUFF_SIZE > 0) )\r
- if((pEP->bMisc == USBFS_1_CLASS_AUDIO) &&\r
- (ep_type == USBFS_1_EP_TYPE_BULK))\r
- {\r
- USBFS_1_midi_out_ep = i;\r
- }\r
- #endif /* End USBFS_1_ENABLE_MIDI_STREAMING*/\r
- }\r
- USBFS_1_EP[i].addr = pEP->addr;\r
- USBFS_1_EP[i].attrib = pEP->attributes;\r
-\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO)\r
- break; /* use first EP setting in Auto memory managment */\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO */\r
- }\r
- }\r
- pEP = &pEP[1u];\r
- }\r
- }\r
- #endif /* End (USBFS_1_EP_MA == USBFS_1__MA_DYNAMIC) */\r
-\r
- /* Init class array for each interface and interface number for each EP.\r
- * It is used for handling Class specific requests directed to either an\r
- * interface or the endpoint.\r
- */\r
- /* p_list points the endpoint setting table. */\r
- pEP = (const T_USBFS_1_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list;\r
- for (i = 0u; i < ep; i++)\r
- {\r
- /* Configure interface number for each EP*/\r
- USBFS_1_EP[pEP->addr & USBFS_1_DIR_UNUSED].interface = pEP->interface;\r
- pEP = &pEP[1u];\r
- }\r
- /* Init pointer on interface class table*/\r
- USBFS_1_interfaceClass = USBFS_1_GetInterfaceClassTablePtr();\r
- /* Set the endpoint buffer addresses */\r
-\r
- #if(USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO)\r
- for (ep = USBFS_1_EP1; ep < USBFS_1_MAX_EP; ep++)\r
- {\r
- USBFS_1_EP[ep].buffOffset = buffCount;\r
- buffCount += USBFS_1_EP[ep].bufferSize;\r
- }\r
- #endif /* End USBFS_1_EP_MM != USBFS_1__EP_DMAAUTO */\r
-\r
- /* Configure hardware registers */\r
- USBFS_1_ConfigReg();\r
- } /* USBFS_1_configuration > 0 */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_ConfigAltChanged\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine update configuration for the required endpoints only.\r
-* It is called after SET_INTERFACE request when Static memory allocation used.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_ConfigAltChanged(void) \r
-{\r
- uint8 ep;\r
- uint8 cur_ep;\r
- uint8 i;\r
- uint8 ep_type;\r
- uint8 ri;\r
-\r
- const T_USBFS_1_LUT CYCODE *pTmp;\r
- const T_USBFS_1_EP_SETTINGS_BLOCK CYCODE *pEP;\r
-\r
-\r
- /* Init Endpoints and Device Status if configured */\r
- if(USBFS_1_configuration > 0u)\r
- {\r
- pTmp = USBFS_1_GetConfigTablePtr(USBFS_1_configuration - 1u);\r
- pTmp = &pTmp[1u];\r
- ep = pTmp->c; /* For this table, c is the number of endpoints configurations */\r
-\r
- /* Do not touch EP which doesn't need reconfiguration */\r
- /* When Alt setting changed, the only required endpoints need to be reconfigured */\r
- /* p_list points the endpoint setting table. */\r
- pEP = (const T_USBFS_1_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list;\r
- for (i = 0u; i < ep; i++)\r
- {\r
- /*If Alt setting changed and new is same with EP Alt */\r
- if((USBFS_1_interfaceSetting[pEP->interface] !=\r
- USBFS_1_interfaceSetting_last[pEP->interface] ) &&\r
- (USBFS_1_interfaceSetting[pEP->interface] == pEP->altSetting) &&\r
- (pEP->interface == CY_GET_REG8(USBFS_1_wIndexLo)))\r
- {\r
- cur_ep = pEP->addr & USBFS_1_DIR_UNUSED;\r
- ri = ((cur_ep - USBFS_1_EP1) << USBFS_1_EPX_CNTX_ADDR_SHIFT);\r
- ep_type = pEP->attributes & USBFS_1_EP_TYPE_MASK;\r
- if ((pEP->addr & USBFS_1_DIR_IN) != 0u)\r
- {\r
- /* IN Endpoint */\r
- USBFS_1_EP[cur_ep].apiEpState = USBFS_1_EVENT_PENDING;\r
- USBFS_1_EP[cur_ep].epMode = (ep_type == USBFS_1_EP_TYPE_ISOC) ?\r
- USBFS_1_MODE_ISO_IN : USBFS_1_MODE_ACK_IN;\r
- }\r
- else\r
- {\r
- /* OUT Endpoint */\r
- USBFS_1_EP[cur_ep].apiEpState = USBFS_1_NO_EVENT_PENDING;\r
- USBFS_1_EP[cur_ep].epMode = (ep_type == USBFS_1_EP_TYPE_ISOC) ?\r
- USBFS_1_MODE_ISO_OUT : USBFS_1_MODE_ACK_OUT;\r
- }\r
- /* Change the SIE mode for the selected EP to NAK ALL */\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_MODE_NAK_IN_OUT);\r
- USBFS_1_EP[cur_ep].bufferSize = pEP->bufferSize;\r
- USBFS_1_EP[cur_ep].addr = pEP->addr;\r
- USBFS_1_EP[cur_ep].attrib = pEP->attributes;\r
-\r
- /* Clear the data toggle */\r
- USBFS_1_EP[cur_ep].epToggle = 0u;\r
-\r
- /* Dynamic reconfiguration for mode 3 transfer */\r
- #if(USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO)\r
- /* In_data_rdy for selected EP should be set to 0 */\r
- * (reg8 *)(USBFS_1_ARB_EP1_CFG_IND + ri) &= (uint8)~USBFS_1_ARB_EPX_CFG_IN_DATA_RDY;\r
-\r
- /* write the EP number for which reconfiguration is required */\r
- USBFS_1_DYN_RECONFIG_REG = (cur_ep - USBFS_1_EP1) <<\r
- USBFS_1_DYN_RECONFIG_EP_SHIFT;\r
- /* Set the dyn_config_en bit in dynamic reconfiguration register */\r
- USBFS_1_DYN_RECONFIG_REG |= USBFS_1_DYN_RECONFIG_ENABLE;\r
- /* wait for the dyn_config_rdy bit to set by the block,\r
- * this bit will be set to 1 when block is ready for reconfiguration.\r
- */\r
- while((USBFS_1_DYN_RECONFIG_REG & USBFS_1_DYN_RECONFIG_RDY_STS) == 0u)\r
- {\r
- ;\r
- }\r
- /* Once dyn_config_rdy bit is set, FW can change the EP configuration. */\r
- /* Change EP Type with new direction */\r
- if((pEP->addr & USBFS_1_DIR_IN) == 0u)\r
- {\r
- USBFS_1_EP_TYPE_REG |= (uint8)(0x01u << (cur_ep - USBFS_1_EP1));\r
- }\r
- else\r
- {\r
- USBFS_1_EP_TYPE_REG &= (uint8)~(uint8)(0x01u << (cur_ep - USBFS_1_EP1));\r
- }\r
- /* dynamic reconfiguration enable bit cleared, pointers and control/status\r
- * signals for the selected EP is cleared/re-initialized on negative edge\r
- * of dynamic reconfiguration enable bit).\r
- */\r
- USBFS_1_DYN_RECONFIG_REG &= (uint8)~USBFS_1_DYN_RECONFIG_ENABLE;\r
- /* The main loop has to re-enable DMA and OUT endpoint*/\r
- #else\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CNT0_IND + ri),\r
- USBFS_1_EP[cur_ep].bufferSize >> 8u);\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CNT1_IND + ri),\r
- USBFS_1_EP[cur_ep].bufferSize & 0xFFu);\r
- CY_SET_REG8((reg8 *)(USBFS_1_ARB_RW1_RA_IND + ri),\r
- USBFS_1_EP[cur_ep].buffOffset & 0xFFu);\r
- CY_SET_REG8((reg8 *)(USBFS_1_ARB_RW1_RA_MSB_IND + ri),\r
- USBFS_1_EP[cur_ep].buffOffset >> 8u);\r
- CY_SET_REG8((reg8 *)(USBFS_1_ARB_RW1_WA_IND + ri),\r
- USBFS_1_EP[cur_ep].buffOffset & 0xFFu);\r
- CY_SET_REG8((reg8 *)(USBFS_1_ARB_RW1_WA_MSB_IND + ri),\r
- USBFS_1_EP[cur_ep].buffOffset >> 8u);\r
- #endif /* End USBFS_1_EP_MM == USBFS_1__EP_DMAAUTO */\r
- }\r
- /* Get next EP element */\r
- pEP = &pEP[1u];\r
- }\r
- } /* USBFS_1_configuration > 0 */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_GetConfigTablePtr\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine returns a pointer a configuration table entry\r
-*\r
-* Parameters:\r
-* c: Configuration Index\r
-*\r
-* Return:\r
-* Device Descriptor pointer.\r
-*\r
-*******************************************************************************/\r
-const T_USBFS_1_LUT CYCODE *USBFS_1_GetConfigTablePtr(uint8 c)\r
- \r
-{\r
- /* Device Table */\r
- const T_USBFS_1_LUT CYCODE *pTmp;\r
-\r
- pTmp = (const T_USBFS_1_LUT CYCODE *) USBFS_1_TABLE[USBFS_1_device].p_list;\r
-\r
- /* The first entry points to the Device Descriptor,\r
- * the rest configuration entries.\r
- */\r
- return( (const T_USBFS_1_LUT CYCODE *) pTmp[c + 1u].p_list );\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_GetDeviceTablePtr\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine returns a pointer to the Device table\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* Device Table pointer\r
-*\r
-*******************************************************************************/\r
-const T_USBFS_1_LUT CYCODE *USBFS_1_GetDeviceTablePtr(void)\r
- \r
-{\r
- /* Device Table */\r
- return( (const T_USBFS_1_LUT CYCODE *) USBFS_1_TABLE[USBFS_1_device].p_list );\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USB_GetInterfaceClassTablePtr\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine returns Interface Class table pointer, which contains\r
-* the relation between interface number and interface class.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* Interface Class table pointer.\r
-*\r
-*******************************************************************************/\r
-const uint8 CYCODE *USBFS_1_GetInterfaceClassTablePtr(void)\r
- \r
-{\r
- const T_USBFS_1_LUT CYCODE *pTmp;\r
- uint8 currentInterfacesNum;\r
-\r
- pTmp = USBFS_1_GetConfigTablePtr(USBFS_1_configuration - 1u);\r
- currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_1_CONFIG_DESCR_NUM_INTERFACES];\r
- /* Third entry in the LUT starts the Interface Table pointers */\r
- /* The INTERFACE_CLASS table is located after all interfaces */\r
- pTmp = &pTmp[currentInterfacesNum + 2u];\r
- return( (const uint8 CYCODE *) pTmp->p_list );\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_TerminateEP\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This function terminates the specified USBFS endpoint.\r
-* This function should be used before endpoint reconfiguration.\r
-*\r
-* Parameters:\r
-* Endpoint number.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void USBFS_1_TerminateEP(uint8 ep) \r
-{\r
- uint8 ri;\r
-\r
- ep &= USBFS_1_DIR_UNUSED;\r
- ri = ((ep - USBFS_1_EP1) << USBFS_1_EPX_CNTX_ADDR_SHIFT);\r
-\r
- if ((ep > USBFS_1_EP0) && (ep < USBFS_1_MAX_EP))\r
- {\r
- /* Set the endpoint Halt */\r
- USBFS_1_EP[ep].hwEpState |= (USBFS_1_ENDPOINT_STATUS_HALT);\r
-\r
- /* Clear the data toggle */\r
- USBFS_1_EP[ep].epToggle = 0u;\r
- USBFS_1_EP[ep].apiEpState = USBFS_1_NO_EVENT_ALLOWED;\r
-\r
- if ((USBFS_1_EP[ep].addr & USBFS_1_DIR_IN) != 0u)\r
- {\r
- /* IN Endpoint */\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_MODE_NAK_IN);\r
- }\r
- else\r
- {\r
- /* OUT Endpoint */\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_MODE_NAK_OUT);\r
- }\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_SetEndpointHalt\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine handles set endpoint halt.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* requestHandled.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_SetEndpointHalt(void) \r
-{\r
- uint8 ep;\r
- uint8 ri;\r
- uint8 requestHandled = USBFS_1_FALSE;\r
-\r
- /* Set endpoint halt */\r
- ep = CY_GET_REG8(USBFS_1_wIndexLo) & USBFS_1_DIR_UNUSED;\r
- ri = ((ep - USBFS_1_EP1) << USBFS_1_EPX_CNTX_ADDR_SHIFT);\r
-\r
- if ((ep > USBFS_1_EP0) && (ep < USBFS_1_MAX_EP))\r
- {\r
- /* Set the endpoint Halt */\r
- USBFS_1_EP[ep].hwEpState |= (USBFS_1_ENDPOINT_STATUS_HALT);\r
-\r
- /* Clear the data toggle */\r
- USBFS_1_EP[ep].epToggle = 0u;\r
- USBFS_1_EP[ep].apiEpState |= USBFS_1_NO_EVENT_ALLOWED;\r
-\r
- if ((USBFS_1_EP[ep].addr & USBFS_1_DIR_IN) != 0u)\r
- {\r
- /* IN Endpoint */\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_MODE_STALL_DATA_EP |\r
- USBFS_1_MODE_ACK_IN);\r
- }\r
- else\r
- {\r
- /* OUT Endpoint */\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_MODE_STALL_DATA_EP |\r
- USBFS_1_MODE_ACK_OUT);\r
- }\r
- requestHandled = USBFS_1_InitNoDataControlTransfer();\r
- }\r
-\r
- return(requestHandled);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_ClearEndpointHalt\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine handles clear endpoint halt.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* requestHandled.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_ClearEndpointHalt(void) \r
-{\r
- uint8 ep;\r
- uint8 ri;\r
- uint8 requestHandled = USBFS_1_FALSE;\r
-\r
- /* Clear endpoint halt */\r
- ep = CY_GET_REG8(USBFS_1_wIndexLo) & USBFS_1_DIR_UNUSED;\r
- ri = ((ep - USBFS_1_EP1) << USBFS_1_EPX_CNTX_ADDR_SHIFT);\r
-\r
- if ((ep > USBFS_1_EP0) && (ep < USBFS_1_MAX_EP))\r
- {\r
- /* Clear the endpoint Halt */\r
- USBFS_1_EP[ep].hwEpState &= (uint8)~(USBFS_1_ENDPOINT_STATUS_HALT);\r
-\r
- /* Clear the data toggle */\r
- USBFS_1_EP[ep].epToggle = 0u;\r
- /* Clear toggle bit for already armed packet */\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CNT0_IND + ri), CY_GET_REG8(\r
- (reg8 *)(USBFS_1_SIE_EP1_CNT0_IND + ri)) & (uint8)~USBFS_1_EPX_CNT_DATA_TOGGLE);\r
- /* Return API State as it was defined before */\r
- USBFS_1_EP[ep].apiEpState &= (uint8)~USBFS_1_NO_EVENT_ALLOWED;\r
-\r
- if ((USBFS_1_EP[ep].addr & USBFS_1_DIR_IN) != 0u)\r
- {\r
- /* IN Endpoint */\r
- if(USBFS_1_EP[ep].apiEpState == USBFS_1_IN_BUFFER_EMPTY)\r
- { /* Wait for next packet from application */\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_MODE_NAK_IN);\r
- }\r
- else /* Continue armed transfer */\r
- {\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_MODE_ACK_IN);\r
- }\r
- }\r
- else\r
- {\r
- /* OUT Endpoint */\r
- if(USBFS_1_EP[ep].apiEpState == USBFS_1_OUT_BUFFER_FULL)\r
- { /* Allow application to read full buffer */\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_MODE_NAK_OUT);\r
- }\r
- else /* Mark endpoint as empty, so it will be reloaded */\r
- {\r
- CY_SET_REG8((reg8 *)(USBFS_1_SIE_EP1_CR0_IND + ri), USBFS_1_MODE_ACK_OUT);\r
- }\r
- }\r
- requestHandled = USBFS_1_InitNoDataControlTransfer();\r
- }\r
-\r
- return(requestHandled);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_ValidateAlternateSetting\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Validates (and records) a SET INTERFACE request.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* requestHandled.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_ValidateAlternateSetting(void) \r
-{\r
- uint8 requestHandled = USBFS_1_TRUE;\r
- uint8 interfaceNum;\r
- const T_USBFS_1_LUT CYCODE *pTmp;\r
- uint8 currentInterfacesNum;\r
-\r
- interfaceNum = CY_GET_REG8(USBFS_1_wIndexLo);\r
- /* Validate interface setting, stall if invalid. */\r
- pTmp = USBFS_1_GetConfigTablePtr(USBFS_1_configuration - 1u);\r
- currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_1_CONFIG_DESCR_NUM_INTERFACES];\r
-\r
- if((interfaceNum >= currentInterfacesNum) || (interfaceNum >= USBFS_1_MAX_INTERFACES_NUMBER))\r
- { /* Wrong interface number */\r
- requestHandled = USBFS_1_FALSE;\r
- }\r
- else\r
- {\r
- /* Save current Alt setting to find out the difference in Config() function */\r
- USBFS_1_interfaceSetting_last[interfaceNum] = USBFS_1_interfaceSetting[interfaceNum];\r
- USBFS_1_interfaceSetting[interfaceNum] = CY_GET_REG8(USBFS_1_wValueLo);\r
- }\r
-\r
- return (requestHandled);\r
-}\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: USBFS_1_vnd.c\r
-* Version 2.60\r
-*\r
-* Description:\r
-* USB vendor request handler.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "USBFS_1.h"\r
-#include "USBFS_1_pvt.h"\r
-\r
-#if(USBFS_1_EXTERN_VND == USBFS_1_FALSE)\r
-\r
-\r
-/***************************************\r
-* Vendor Specific Declarations\r
-***************************************/\r
-\r
-/* `#START VENDOR_SPECIFIC_DECLARATIONS` Place your declaration here */\r
-\r
-/* `#END` */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: USBFS_1_HandleVendorRqst\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* This routine provide users with a method to implement vendor specifc\r
-* requests.\r
-*\r
-* To implement vendor specific requests, add your code in this function to\r
-* decode and disposition the request. If the request is handled, your code\r
-* must set the variable "requestHandled" to TRUE, indicating that the\r
-* request has been handled.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* requestHandled.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 USBFS_1_HandleVendorRqst(void) \r
-{\r
- uint8 requestHandled = USBFS_1_FALSE;\r
-\r
- if ((CY_GET_REG8(USBFS_1_bmRequestType) & USBFS_1_RQST_DIR_MASK) == USBFS_1_RQST_DIR_D2H)\r
- {\r
- /* Control Read */\r
- switch (CY_GET_REG8(USBFS_1_bRequest))\r
- {\r
- case USBFS_1_GET_EXTENDED_CONFIG_DESCRIPTOR:\r
- #if defined(USBFS_1_ENABLE_MSOS_STRING)\r
- USBFS_1_currentTD.pData = (volatile uint8 *)&USBFS_1_MSOS_CONFIGURATION_DESCR[0u];\r
- USBFS_1_currentTD.count = USBFS_1_MSOS_CONFIGURATION_DESCR[0u];\r
- requestHandled = USBFS_1_InitControlRead();\r
- #endif /* End USBFS_1_ENABLE_MSOS_STRING */\r
- break;\r
- default:\r
- break;\r
- }\r
- }\r
-\r
- /* `#START VENDOR_SPECIFIC_CODE` Place your vendor specific request here */\r
-\r
- /* `#END` */\r
-\r
- return(requestHandled);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Additional user functions supporting Vendor Specific Requests\r
-********************************************************************************/\r
-\r
-/* `#START VENDOR_SPECIFIC_FUNCTIONS` Place any additional functions here */\r
-\r
-/* `#END` */\r
-\r
-\r
-#endif /* USBFS_1_EXTERN_VND */\r
-\r
-\r
-/* [] END OF FILE */\r
/*********************************************************************\r
* Config Descriptor \r
*********************************************************************/\r
-const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[41u] = {\r
+const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[73u] = {\r
/* Config Descriptor Length */ 0x09u,\r
/* DescriptorType: CONFIG */ 0x02u,\r
-/* wTotalLength */ 0x29u, 0x00u,\r
-/* bNumInterfaces */ 0x01u,\r
+/* wTotalLength */ 0x49u, 0x00u,\r
+/* bNumInterfaces */ 0x02u,\r
/* bConfigurationValue */ 0x01u,\r
/* iConfiguration */ 0x00u,\r
/* bmAttributes */ 0x80u,\r
/* bEndpointAddress */ 0x82u,\r
/* bmAttributes */ 0x03u,\r
/* wMaxPacketSize */ 0x40u, 0x00u,\r
+/* bInterval */ 0x40u,\r
+/*********************************************************************\r
+* Interface Descriptor\r
+*********************************************************************/\r
+/* Interface Descriptor Length */ 0x09u,\r
+/* DescriptorType: INTERFACE */ 0x04u,\r
+/* bInterfaceNumber */ 0x01u,\r
+/* bAlternateSetting */ 0x00u,\r
+/* bNumEndpoints */ 0x02u,\r
+/* bInterfaceClass */ 0x03u,\r
+/* bInterfaceSubClass */ 0x00u,\r
+/* bInterfaceProtocol */ 0x00u,\r
+/* iInterface */ 0x00u,\r
+/*********************************************************************\r
+* HID Class Descriptor\r
+*********************************************************************/\r
+/* HID Class Descriptor Length */ 0x09u,\r
+/* DescriptorType: HID_CLASS */ 0x21u,\r
+/* bcdHID */ 0x11u, 0x01u,\r
+/* bCountryCode */ 0x00u,\r
+/* bNumDescriptors */ 0x01u,\r
+/* bDescriptorType */ 0x22u,\r
+/* wDescriptorLength (LSB) */ USBFS_HID_RPT_1_SIZE_LSB,\r
+/* wDescriptorLength (MSB) */ USBFS_HID_RPT_1_SIZE_MSB,\r
+/*********************************************************************\r
+* Endpoint Descriptor\r
+*********************************************************************/\r
+/* Endpoint Descriptor Length */ 0x07u,\r
+/* DescriptorType: ENDPOINT */ 0x05u,\r
+/* bEndpointAddress */ 0x03u,\r
+/* bmAttributes */ 0x03u,\r
+/* wMaxPacketSize */ 0x40u, 0x00u,\r
+/* bInterval */ 0x80u,\r
+/*********************************************************************\r
+* Endpoint Descriptor\r
+*********************************************************************/\r
+/* Endpoint Descriptor Length */ 0x07u,\r
+/* DescriptorType: ENDPOINT */ 0x05u,\r
+/* bEndpointAddress */ 0x84u,\r
+/* bmAttributes */ 0x03u,\r
+/* wMaxPacketSize */ 0x40u, 0x00u,\r
/* bInterval */ 0x40u\r
};\r
\r
{0x01u, (const void *)&USBFS_DEVICE0_CONFIGURATION0_DESCR[18]}\r
};\r
#endif /* USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_HID_RPT_STORAGE */\r
+#if !defined(USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_HID_RPT_STORAGE)\r
+/*********************************************************************\r
+* HID Input Report Storage\r
+*********************************************************************/\r
+T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_SCB;\r
+uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF[\r
+ USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE];\r
+\r
+/*********************************************************************\r
+* HID Input Report TD Table\r
+*********************************************************************/\r
+const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_TABLE[1u] = {\r
+ {USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE,\r
+ &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF[0u],\r
+ &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_SCB},\r
+};\r
+/*********************************************************************\r
+* HID Output Report Storage\r
+*********************************************************************/\r
+T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_SCB;\r
+uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF[\r
+ USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE];\r
+\r
+/*********************************************************************\r
+* HID Output Report TD Table\r
+*********************************************************************/\r
+const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_TABLE[1u] = {\r
+ {USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE,\r
+ &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF[0u],\r
+ &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_SCB},\r
+};\r
+/*********************************************************************\r
+* HID Report Look Up Table This table has four entries:\r
+* IN Report Table\r
+* OUT Report Table\r
+* Feature Report Table\r
+* HID Report Descriptor\r
+* HID Class Descriptor\r
+*********************************************************************/\r
+const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_TABLE[5u] = {\r
+ {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_TABLE},\r
+ {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_TABLE},\r
+ {0x00u, NULL},\r
+ {0x01u, (const void *)&USBFS_HIDREPORT_DESCRIPTOR1[0]},\r
+ {0x01u, (const void *)&USBFS_DEVICE0_CONFIGURATION0_DESCR[50]}\r
+};\r
+#endif /* USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_HID_RPT_STORAGE */\r
\r
/*********************************************************************\r
* Interface Dispatch Table -- Points to the Class Dispatch Tables\r
&USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE}\r
};\r
/*********************************************************************\r
+* Interface Dispatch Table -- Points to the Class Dispatch Tables\r
+*********************************************************************/\r
+const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_TABLE[1u] = {\r
+ {USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_COUNT, \r
+ &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_TABLE}\r
+};\r
+/*********************************************************************\r
* Endpoint Setting Table -- This table contain the endpoint setting\r
* for each endpoint in the configuration. It\r
* contains the necessary information to\r
* configure the endpoint hardware for each\r
* interface and alternate setting.\r
*********************************************************************/\r
-const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[2u] = {\r
+const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[4u] = {\r
/* IFC ALT EPAddr bmAttr MaxPktSize Class ********************/\r
{0x00u, 0x00u, 0x01u, 0x03u, 0x0040u, 0x03u},\r
-{0x00u, 0x00u, 0x82u, 0x03u, 0x0040u, 0x03u}\r
+{0x00u, 0x00u, 0x82u, 0x03u, 0x0040u, 0x03u},\r
+{0x01u, 0x00u, 0x03u, 0x03u, 0x0040u, 0x03u},\r
+{0x01u, 0x00u, 0x84u, 0x03u, 0x0040u, 0x03u}\r
};\r
-const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[1u] = {\r
-0x03u\r
+const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[2u] = {\r
+0x03u, 0x03u\r
};\r
/*********************************************************************\r
* Config Dispatch Table -- Points to the Config Descriptor and each of\r
* and endpoint setup table and to each\r
* interface table if it specifies a USB Class\r
*********************************************************************/\r
-const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[4u] = {\r
+const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[5u] = {\r
{0x01u, &USBFS_DEVICE0_CONFIGURATION0_DESCR},\r
- {0x02u, &USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE},\r
+ {0x04u, &USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE},\r
{0x01u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE},\r
+ {0x01u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_TABLE},\r
{0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS}\r
};\r
/*********************************************************************\r
\r
/* Generated external references for descriptors*/\r
extern const uint8 CYCODE USBFS_DEVICE0_DESCR[18u];\r
-extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[41u];\r
+extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[73u];\r
extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE[1u];\r
-extern const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[2u];\r
-extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[1u];\r
-extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[4u];\r
+extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_TABLE[1u];\r
+extern const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[4u];\r
+extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[2u];\r
+extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[5u];\r
extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[2u];\r
extern const T_USBFS_LUT CYCODE USBFS_TABLE[1u];\r
extern const uint8 CYCODE USBFS_SN_STRING_DESCRIPTOR[10];\r
extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_SCB;\r
extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF[\r
USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE];\r
+extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_SCB;\r
+extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF[\r
+ USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE];\r
+extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_SCB;\r
+extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF[\r
+ USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE];\r
extern const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR1[40u];\r
extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_TABLE[1u];\r
extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_TABLE[1u];\r
extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE[5u];\r
+extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_TABLE[1u];\r
+extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_TABLE[1u];\r
+extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_TABLE[5u];\r
\r
\r
extern const uint8 CYCODE USBFS_MSOS_DESCRIPTOR[USBFS_MSOS_DESCRIPTOR_LENGTH];\r
.heap (NOLOAD) :\r
{\r
. = _end;\r
- . += 0x0256;\r
+ . += 0x0400;\r
__cy_heap_limit = .;\r
} >ram\r
\r
+++ /dev/null
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-:00000001FF\r
#include <cydevice.h>\r
#include <cydevice_trm.h>\r
\r
+/* Debug_Timer_Interrupt */\r
+#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define Debug_Timer_Interrupt__INTC_MASK 0x01u\r
+#define Debug_Timer_Interrupt__INTC_NUMBER 0u\r
+#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u\r
+#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
+#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* Debug_Timer_TimerHW */\r
+#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0\r
+#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1\r
+#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0\r
+#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1\r
+#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2\r
+#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0\r
+#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1\r
+#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0\r
+#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1\r
+#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3\r
+#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u\r
+#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3\r
+#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u\r
+#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0\r
+#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1\r
+#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0\r
+\r
/* USBFS_bus_reset */\r
#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+\r
+/* SCSI_Out_Bits */\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
\r
/* USBFS_arb_int */\r
#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
+/* SCSI_Out_Ctl */\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX\r
#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB07_ST\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB04_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB04_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB06_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB06_ST\r
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB07_08_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB07_08_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB07_08_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB07_08_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB07_08_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB07_08_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB07_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB07_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB07_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB07_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB07_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB07_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB07_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB07_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB07_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB04_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB04_ST\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1\r
\r
/* USBFS_dp_int */\r
#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SD_Data_Clk__PM_STBY_MSK 0x01u\r
\r
/* SD_Init_Clk */\r
-#define SD_Init_Clk__CFG0 CYREG_CLKDIST_DCFG2_CFG0\r
-#define SD_Init_Clk__CFG1 CYREG_CLKDIST_DCFG2_CFG1\r
-#define SD_Init_Clk__CFG2 CYREG_CLKDIST_DCFG2_CFG2\r
+#define SD_Init_Clk__CFG0 CYREG_CLKDIST_DCFG3_CFG0\r
+#define SD_Init_Clk__CFG1 CYREG_CLKDIST_DCFG3_CFG1\r
+#define SD_Init_Clk__CFG2 CYREG_CLKDIST_DCFG3_CFG2\r
#define SD_Init_Clk__CFG2_SRC_SEL_MASK 0x07u\r
-#define SD_Init_Clk__INDEX 0x02u\r
+#define SD_Init_Clk__INDEX 0x03u\r
#define SD_Init_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
-#define SD_Init_Clk__PM_ACT_MSK 0x04u\r
+#define SD_Init_Clk__PM_ACT_MSK 0x08u\r
#define SD_Init_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
-#define SD_Init_Clk__PM_STBY_MSK 0x04u\r
+#define SD_Init_Clk__PM_STBY_MSK 0x08u\r
+\r
+/* timer_clock */\r
+#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0\r
+#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1\r
+#define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2\r
+#define timer_clock__CFG2_SRC_SEL_MASK 0x07u\r
+#define timer_clock__INDEX 0x02u\r
+#define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
+#define timer_clock__PM_ACT_MSK 0x04u\r
+#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
+#define timer_clock__PM_STBY_MSK 0x04u\r
\r
/* scsiTarget */\r
#define scsiTarget_StatusReg__0__MASK 0x01u\r
#define scsiTarget_StatusReg__0__POS 0\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__3__MASK 0x08u\r
#define scsiTarget_StatusReg__3__POS 3\r
#define scsiTarget_StatusReg__MASK 0x0Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK\r
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB03_ST\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB03_CTL\r
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB03_CTL\r
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB03_MSK\r
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB03_04_A0\r
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB03_04_A1\r
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB03_04_D0\r
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB03_04_D1\r
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB03_04_F0\r
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB03_04_F1\r
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB03_A0_A1\r
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB03_A0\r
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB03_A1\r
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB03_D0_D1\r
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB03_D0\r
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB03_D1\r
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB03_F0_F1\r
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB03_F0\r
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB03_F1\r
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB13_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB13_ST\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB12_MSK\r
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB12_ST\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB12_CTL\r
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB12_CTL\r
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB12_MSK\r
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB12_13_A0\r
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB12_13_A1\r
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB12_13_D0\r
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB12_13_D1\r
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB12_13_F0\r
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB12_13_F1\r
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB12_A0_A1\r
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB12_A0\r
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB12_A1\r
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB12_D0_D1\r
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB12_D0\r
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB12_D1\r
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB12_F0_F1\r
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB12_F0\r
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB12_F1\r
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
\r
/* SD_Clk_Ctl */\r
#define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
/* USBFS_ep_1 */\r
#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_1__INTC_MASK 0x01u\r
-#define USBFS_ep_1__INTC_NUMBER 0u\r
+#define USBFS_ep_1__INTC_MASK 0x02u\r
+#define USBFS_ep_1__INTC_NUMBER 1u\r
#define USBFS_ep_1__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_2 */\r
#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_2__INTC_MASK 0x02u\r
-#define USBFS_ep_2__INTC_NUMBER 1u\r
+#define USBFS_ep_2__INTC_MASK 0x04u\r
+#define USBFS_ep_2__INTC_NUMBER 2u\r
#define USBFS_ep_2__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
+/* USBFS_ep_3 */\r
+#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_3__INTC_MASK 0x08u\r
+#define USBFS_ep_3__INTC_NUMBER 3u\r
+#define USBFS_ep_3__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
+#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_4 */\r
+#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_4__INTC_MASK 0x10u\r
+#define USBFS_ep_4__INTC_NUMBER 4u\r
+#define USBFS_ep_4__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
+#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
/* USBFS_USB */\r
#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG\r
#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG\r
#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG\r
#define CYDEV_DMA_CHANNELS_AVAILABLE 24u\r
#define CYDEV_ECC_ENABLE 0\r
-#define CYDEV_HEAP_SIZE 0x0256\r
+#define CYDEV_HEAP_SIZE 0x0400\r
#define CYDEV_INSTRUCT_CACHE_ENABLED 1\r
-#define CYDEV_INTR_RISING 0x00000000u\r
+#define CYDEV_INTR_RISING 0x00000001u\r
#define CYDEV_PROJ_TYPE 2\r
#define CYDEV_PROJ_TYPE_BOOTLOADER 1\r
#define CYDEV_PROJ_TYPE_LOADABLE 2\r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 33u\r
+#define CY_CFG_BASE_ADDR_COUNT 35u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x10u);\r
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u);\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u);\r
- CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x001Du);\r
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u);\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u);\r
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0), 0x001Du);\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0 + 0x2u), 0x19u);\r
\r
/* Configure ILO based on settings from Clock DWR */\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u);\r
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);\r
\r
- CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x06u)));\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x0Eu)));\r
}\r
\r
\r
{\r
static const uint32 CYCODE cy_cfg_addr_table[] = {\r
0x40004502u, /* Base address: 0x40004500 Count: 2 */\r
- 0x4000520Au, /* Base address: 0x40005200 Count: 10 */\r
- 0x40006402u, /* Base address: 0x40006400 Count: 2 */\r
- 0x40010048u, /* Base address: 0x40010000 Count: 72 */\r
- 0x4001012Cu, /* Base address: 0x40010100 Count: 44 */\r
- 0x40010235u, /* Base address: 0x40010200 Count: 53 */\r
- 0x4001034Fu, /* Base address: 0x40010300 Count: 79 */\r
- 0x40010448u, /* Base address: 0x40010400 Count: 72 */\r
+ 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
+ 0x40005209u, /* Base address: 0x40005200 Count: 9 */\r
+ 0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
+ 0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
+ 0x4001004Au, /* Base address: 0x40010000 Count: 74 */\r
+ 0x40010134u, /* Base address: 0x40010100 Count: 52 */\r
+ 0x40010252u, /* Base address: 0x40010200 Count: 82 */\r
+ 0x40010355u, /* Base address: 0x40010300 Count: 85 */\r
+ 0x40010449u, /* Base address: 0x40010400 Count: 73 */\r
0x40010555u, /* Base address: 0x40010500 Count: 85 */\r
- 0x40010606u, /* Base address: 0x40010600 Count: 6 */\r
+ 0x4001060Eu, /* Base address: 0x40010600 Count: 14 */\r
0x40010747u, /* Base address: 0x40010700 Count: 71 */\r
- 0x40010901u, /* Base address: 0x40010900 Count: 1 */\r
+ 0x40010903u, /* Base address: 0x40010900 Count: 3 */\r
0x40010B0Cu, /* Base address: 0x40010B00 Count: 12 */\r
- 0x40010C3Bu, /* Base address: 0x40010C00 Count: 59 */\r
- 0x40010D39u, /* Base address: 0x40010D00 Count: 57 */\r
+ 0x40010C45u, /* Base address: 0x40010C00 Count: 69 */\r
+ 0x40010D4Du, /* Base address: 0x40010D00 Count: 77 */\r
0x40010F04u, /* Base address: 0x40010F00 Count: 4 */\r
- 0x40011504u, /* Base address: 0x40011500 Count: 4 */\r
- 0x4001164Du, /* Base address: 0x40011600 Count: 77 */\r
- 0x4001173Fu, /* Base address: 0x40011700 Count: 63 */\r
- 0x40011901u, /* Base address: 0x40011900 Count: 1 */\r
- 0x4001400Cu, /* Base address: 0x40014000 Count: 12 */\r
- 0x4001410Fu, /* Base address: 0x40014100 Count: 15 */\r
- 0x4001420Bu, /* Base address: 0x40014200 Count: 11 */\r
- 0x40014306u, /* Base address: 0x40014300 Count: 6 */\r
- 0x4001440Eu, /* Base address: 0x40014400 Count: 14 */\r
- 0x40014513u, /* Base address: 0x40014500 Count: 19 */\r
- 0x4001460Au, /* Base address: 0x40014600 Count: 10 */\r
- 0x40014703u, /* Base address: 0x40014700 Count: 3 */\r
- 0x4001480Du, /* Base address: 0x40014800 Count: 13 */\r
- 0x40014908u, /* Base address: 0x40014900 Count: 8 */\r
- 0x40014C02u, /* Base address: 0x40014C00 Count: 2 */\r
- 0x4001500Au, /* Base address: 0x40015000 Count: 10 */\r
- 0x40015101u, /* Base address: 0x40015100 Count: 1 */\r
+ 0x40011501u, /* Base address: 0x40011500 Count: 1 */\r
+ 0x40011657u, /* Base address: 0x40011600 Count: 87 */\r
+ 0x40011753u, /* Base address: 0x40011700 Count: 83 */\r
+ 0x40011903u, /* Base address: 0x40011900 Count: 3 */\r
+ 0x40011B02u, /* Base address: 0x40011B00 Count: 2 */\r
+ 0x40014012u, /* Base address: 0x40014000 Count: 18 */\r
+ 0x40014110u, /* Base address: 0x40014100 Count: 16 */\r
+ 0x40014215u, /* Base address: 0x40014200 Count: 21 */\r
+ 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */\r
+ 0x40014410u, /* Base address: 0x40014400 Count: 16 */\r
+ 0x40014517u, /* Base address: 0x40014500 Count: 23 */\r
+ 0x40014607u, /* Base address: 0x40014600 Count: 7 */\r
+ 0x4001470Au, /* Base address: 0x40014700 Count: 10 */\r
+ 0x4001480Cu, /* Base address: 0x40014800 Count: 12 */\r
+ 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */\r
+ 0x4001500Bu, /* Base address: 0x40015000 Count: 11 */\r
+ 0x40015102u, /* Base address: 0x40015100 Count: 2 */\r
};\r
\r
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
{0x36u, 0x02u},\r
{0x7Eu, 0x02u},\r
- {0x00u, 0x12u},\r
- {0x01u, 0x01u},\r
- {0x18u, 0x04u},\r
- {0x19u, 0x08u},\r
+ {0x01u, 0x20u},\r
+ {0x0Au, 0x36u},\r
+ {0x00u, 0x13u},\r
+ {0x01u, 0x05u},\r
+ {0x19u, 0x04u},\r
{0x1Cu, 0x61u},\r
{0x20u, 0xA8u},\r
- {0x21u, 0xC8u},\r
- {0x30u, 0x03u},\r
- {0x31u, 0x06u},\r
+ {0x21u, 0x60u},\r
+ {0x30u, 0x09u},\r
+ {0x31u, 0x0Au},\r
{0x7Cu, 0x40u},\r
- {0x33u, 0x01u},\r
- {0x87u, 0x0Fu},\r
- {0x03u, 0x08u},\r
- {0x04u, 0x21u},\r
- {0x06u, 0x42u},\r
- {0x07u, 0x40u},\r
- {0x08u, 0x42u},\r
- {0x0Au, 0x28u},\r
- {0x0Bu, 0x48u},\r
- {0x0Cu, 0x0Du},\r
- {0x0Fu, 0x06u},\r
- {0x10u, 0x02u},\r
- {0x11u, 0x01u},\r
- {0x12u, 0x0Du},\r
- {0x14u, 0x22u},\r
- {0x15u, 0x48u},\r
- {0x16u, 0x84u},\r
- {0x17u, 0x12u},\r
- {0x18u, 0xC0u},\r
- {0x1Bu, 0x30u},\r
- {0x1Cu, 0x0Du},\r
- {0x1Du, 0x01u},\r
- {0x20u, 0x0Du},\r
- {0x21u, 0x48u},\r
- {0x23u, 0x24u},\r
- {0x24u, 0x0Du},\r
- {0x25u, 0x01u},\r
- {0x28u, 0x0Du},\r
- {0x29u, 0x01u},\r
- {0x2Cu, 0x10u},\r
- {0x30u, 0x0Fu},\r
- {0x33u, 0x01u},\r
- {0x34u, 0xE0u},\r
- {0x35u, 0x70u},\r
- {0x36u, 0x10u},\r
- {0x37u, 0x0Eu},\r
- {0x38u, 0x20u},\r
- {0x39u, 0x08u},\r
- {0x3Au, 0x02u},\r
- {0x3Eu, 0x40u},\r
- {0x3Fu, 0x04u},\r
- {0x58u, 0x0Bu},\r
+ {0x3Cu, 0x01u},\r
+ {0x86u, 0x0Fu},\r
+ {0x05u, 0x08u},\r
+ {0x06u, 0x40u},\r
+ {0x07u, 0x44u},\r
+ {0x0Au, 0x10u},\r
+ {0x0Cu, 0x55u},\r
+ {0x0Du, 0x04u},\r
+ {0x0Eu, 0xAAu},\r
+ {0x0Fu, 0x09u},\r
+ {0x11u, 0x4Du},\r
+ {0x12u, 0x04u},\r
+ {0x13u, 0xB2u},\r
+ {0x16u, 0x20u},\r
+ {0x1Au, 0x02u},\r
+ {0x1Du, 0x20u},\r
+ {0x1Fu, 0x90u},\r
+ {0x22u, 0x01u},\r
+ {0x2Au, 0x80u},\r
+ {0x2Du, 0x10u},\r
+ {0x2Eu, 0x08u},\r
+ {0x2Fu, 0x22u},\r
+ {0x30u, 0xC0u},\r
+ {0x31u, 0xC0u},\r
+ {0x32u, 0x0Cu},\r
+ {0x33u, 0x03u},\r
+ {0x34u, 0x30u},\r
+ {0x35u, 0x3Cu},\r
+ {0x36u, 0x03u},\r
+ {0x3Eu, 0x55u},\r
+ {0x3Fu, 0x15u},\r
+ {0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Cu, 0x19u},\r
+ {0x5Bu, 0x04u},\r
{0x5Fu, 0x01u},\r
- {0x83u, 0x04u},\r
- {0x84u, 0x02u},\r
- {0x87u, 0x10u},\r
- {0x8Cu, 0x01u},\r
- {0x8Eu, 0x02u},\r
- {0x8Fu, 0x08u},\r
- {0x90u, 0x07u},\r
- {0x95u, 0x01u},\r
- {0x97u, 0x04u},\r
- {0x99u, 0x01u},\r
- {0x9Bu, 0x02u},\r
- {0xA0u, 0x02u},\r
- {0xA1u, 0x06u},\r
- {0xA3u, 0x01u},\r
- {0xA4u, 0x06u},\r
- {0xAAu, 0x05u},\r
- {0xABu, 0x07u},\r
- {0xADu, 0x08u},\r
- {0xAEu, 0x07u},\r
- {0xAFu, 0x10u},\r
- {0xB3u, 0x07u},\r
- {0xB6u, 0x07u},\r
- {0xB7u, 0x18u},\r
- {0xBFu, 0x40u},\r
+ {0x80u, 0x03u},\r
+ {0x81u, 0x06u},\r
+ {0x82u, 0x0Cu},\r
+ {0x83u, 0x09u},\r
+ {0x84u, 0x05u},\r
+ {0x86u, 0x0Au},\r
+ {0x87u, 0xFFu},\r
+ {0x89u, 0x30u},\r
+ {0x8Au, 0xFFu},\r
+ {0x8Bu, 0xC0u},\r
+ {0x8Cu, 0x0Fu},\r
+ {0x8Du, 0x60u},\r
+ {0x8Eu, 0xF0u},\r
+ {0x8Fu, 0x90u},\r
+ {0x90u, 0x90u},\r
+ {0x91u, 0x0Fu},\r
+ {0x92u, 0x60u},\r
+ {0x93u, 0xF0u},\r
+ {0x94u, 0xFFu},\r
+ {0x95u, 0x50u},\r
+ {0x97u, 0xA0u},\r
+ {0x98u, 0xFFu},\r
+ {0x99u, 0xFFu},\r
+ {0xA1u, 0x03u},\r
+ {0xA3u, 0x0Cu},\r
+ {0xA4u, 0x50u},\r
+ {0xA6u, 0xA0u},\r
+ {0xA7u, 0xFFu},\r
+ {0xA8u, 0x30u},\r
+ {0xA9u, 0x05u},\r
+ {0xAAu, 0xC0u},\r
+ {0xABu, 0x0Au},\r
+ {0xACu, 0x09u},\r
+ {0xAEu, 0x06u},\r
+ {0xB2u, 0xFFu},\r
+ {0xB5u, 0xFFu},\r
+ {0xBEu, 0x04u},\r
+ {0xBFu, 0x10u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x20u},\r
- {0x03u, 0x21u},\r
- {0x05u, 0x08u},\r
- {0x06u, 0x01u},\r
- {0x08u, 0x40u},\r
- {0x0Au, 0x64u},\r
- {0x0Fu, 0x80u},\r
- {0x10u, 0x88u},\r
- {0x11u, 0x04u},\r
- {0x12u, 0x02u},\r
- {0x16u, 0x42u},\r
+ {0x00u, 0x08u},\r
+ {0x01u, 0x10u},\r
+ {0x03u, 0x01u},\r
+ {0x05u, 0x02u},\r
+ {0x06u, 0x28u},\r
+ {0x07u, 0x03u},\r
+ {0x08u, 0x01u},\r
+ {0x0Au, 0x14u},\r
+ {0x0Eu, 0x60u},\r
+ {0x0Fu, 0x04u},\r
+ {0x10u, 0x08u},\r
+ {0x11u, 0x41u},\r
+ {0x14u, 0x01u},\r
+ {0x16u, 0x02u},\r
{0x17u, 0x24u},\r
- {0x19u, 0x80u},\r
- {0x1Au, 0x44u},\r
- {0x1Fu, 0x80u},\r
- {0x21u, 0x68u},\r
- {0x24u, 0x20u},\r
- {0x26u, 0x44u},\r
- {0x27u, 0x20u},\r
- {0x28u, 0x08u},\r
- {0x2Au, 0x04u},\r
- {0x2Bu, 0xC0u},\r
- {0x2Du, 0x40u},\r
- {0x2Fu, 0x84u},\r
- {0x30u, 0x02u},\r
- {0x31u, 0x20u},\r
- {0x33u, 0x44u},\r
- {0x37u, 0x24u},\r
- {0x38u, 0x20u},\r
- {0x39u, 0x89u},\r
- {0x3Du, 0x80u},\r
- {0x3Fu, 0x09u},\r
- {0x6Du, 0x40u},\r
- {0x78u, 0x01u},\r
- {0x81u, 0x2Cu},\r
- {0x8Eu, 0x05u},\r
- {0xC0u, 0xA7u},\r
- {0xC2u, 0x1Fu},\r
- {0xC4u, 0xFFu},\r
- {0xCAu, 0xB7u},\r
- {0xCCu, 0x6Fu},\r
- {0xCEu, 0xDFu},\r
- {0xDEu, 0x01u},\r
- {0xE0u, 0x04u},\r
- {0x05u, 0x01u},\r
- {0x37u, 0x01u},\r
- {0x3Fu, 0x40u},\r
+ {0x19u, 0x18u},\r
+ {0x1Au, 0x80u},\r
+ {0x1Bu, 0x80u},\r
+ {0x1Du, 0x04u},\r
+ {0x20u, 0x80u},\r
+ {0x23u, 0x14u},\r
+ {0x26u, 0x20u},\r
+ {0x29u, 0x40u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Du, 0x13u},\r
+ {0x2Eu, 0x20u},\r
+ {0x33u, 0x41u},\r
+ {0x34u, 0x10u},\r
+ {0x36u, 0x10u},\r
+ {0x37u, 0x06u},\r
+ {0x39u, 0x88u},\r
+ {0x3Cu, 0x20u},\r
+ {0x3Eu, 0x42u},\r
+ {0x3Fu, 0x04u},\r
+ {0x41u, 0xC0u},\r
+ {0x68u, 0x10u},\r
+ {0x69u, 0x40u},\r
+ {0x6Au, 0x54u},\r
+ {0x6Bu, 0x64u},\r
+ {0x70u, 0x18u},\r
+ {0x71u, 0x41u},\r
+ {0x80u, 0x08u},\r
+ {0x8Bu, 0x80u},\r
+ {0x8Eu, 0x40u},\r
+ {0xC0u, 0xF7u},\r
+ {0xC2u, 0x7Eu},\r
+ {0xC4u, 0xEBu},\r
+ {0xCAu, 0xE8u},\r
+ {0xCCu, 0xE9u},\r
+ {0xCEu, 0xFAu},\r
+ {0xE2u, 0x10u},\r
+ {0xE6u, 0x05u},\r
+ {0x01u, 0x03u},\r
+ {0x03u, 0x0Cu},\r
+ {0x04u, 0x30u},\r
+ {0x06u, 0xC0u},\r
+ {0x07u, 0xFFu},\r
+ {0x0Au, 0xFFu},\r
+ {0x0Bu, 0xFFu},\r
+ {0x0Cu, 0x06u},\r
+ {0x0Du, 0x90u},\r
+ {0x0Eu, 0x09u},\r
+ {0x0Fu, 0x60u},\r
+ {0x10u, 0x60u},\r
+ {0x11u, 0x0Fu},\r
+ {0x12u, 0x90u},\r
+ {0x13u, 0xF0u},\r
+ {0x15u, 0x50u},\r
+ {0x16u, 0xFFu},\r
+ {0x17u, 0xA0u},\r
+ {0x18u, 0xFFu},\r
+ {0x19u, 0x30u},\r
+ {0x1Bu, 0xC0u},\r
+ {0x1Cu, 0x03u},\r
+ {0x1Eu, 0x0Cu},\r
+ {0x20u, 0x0Fu},\r
+ {0x21u, 0x09u},\r
+ {0x22u, 0xF0u},\r
+ {0x23u, 0x06u},\r
+ {0x24u, 0x50u},\r
+ {0x26u, 0xA0u},\r
+ {0x27u, 0xFFu},\r
+ {0x28u, 0x05u},\r
+ {0x29u, 0x05u},\r
+ {0x2Au, 0x0Au},\r
+ {0x2Bu, 0x0Au},\r
+ {0x34u, 0xFFu},\r
+ {0x35u, 0xFFu},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x10u},\r
+ {0x56u, 0x08u},\r
+ {0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x01u},\r
- {0x83u, 0x04u},\r
- {0x85u, 0x80u},\r
- {0x88u, 0x04u},\r
- {0x8Bu, 0x24u},\r
- {0x8Fu, 0x20u},\r
- {0x93u, 0x18u},\r
- {0x95u, 0x24u},\r
- {0x97u, 0x09u},\r
- {0x9Fu, 0x03u},\r
- {0xA1u, 0x24u},\r
- {0xA3u, 0x12u},\r
- {0xA9u, 0x40u},\r
- {0xACu, 0x02u},\r
- {0xB0u, 0x01u},\r
- {0xB1u, 0x38u},\r
- {0xB3u, 0x40u},\r
- {0xB4u, 0x04u},\r
- {0xB5u, 0x80u},\r
- {0xB6u, 0x02u},\r
- {0xB7u, 0x07u},\r
- {0xBEu, 0x51u},\r
- {0xBFu, 0x14u},\r
- {0xC0u, 0x61u},\r
- {0xC1u, 0x03u},\r
- {0xC2u, 0x20u},\r
- {0xC5u, 0x2Cu},\r
- {0xC6u, 0x0Du},\r
- {0xC7u, 0xFEu},\r
- {0xC8u, 0x37u},\r
- {0xC9u, 0xFFu},\r
- {0xCAu, 0xFFu},\r
- {0xCBu, 0xFFu},\r
- {0xCFu, 0x2Cu},\r
- {0xD6u, 0x01u},\r
- {0xD8u, 0x04u},\r
+ {0x84u, 0x0Du},\r
+ {0x87u, 0x06u},\r
+ {0x88u, 0x0Du},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Cu, 0x0Du},\r
+ {0x92u, 0x10u},\r
+ {0x94u, 0x80u},\r
+ {0x95u, 0x09u},\r
+ {0x97u, 0x52u},\r
+ {0x98u, 0x02u},\r
+ {0x9Au, 0x54u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Eu, 0x0Du},\r
+ {0x9Fu, 0x30u},\r
+ {0xA0u, 0x0Du},\r
+ {0xA1u, 0x09u},\r
+ {0xA3u, 0x24u},\r
+ {0xA4u, 0x01u},\r
+ {0xA6u, 0x32u},\r
+ {0xA7u, 0x01u},\r
+ {0xA8u, 0x62u},\r
+ {0xAAu, 0x08u},\r
+ {0xABu, 0x49u},\r
+ {0xACu, 0x0Du},\r
+ {0xB0u, 0x70u},\r
+ {0xB3u, 0x07u},\r
+ {0xB4u, 0x80u},\r
+ {0xB5u, 0x40u},\r
+ {0xB6u, 0x0Fu},\r
+ {0xB7u, 0x38u},\r
+ {0xBAu, 0x80u},\r
+ {0xBEu, 0x10u},\r
+ {0xBFu, 0x10u},\r
+ {0xD8u, 0x0Bu},\r
{0xD9u, 0x04u},\r
- {0xDAu, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x10u},\r
- {0xDDu, 0x01u},\r
+ {0xDCu, 0x19u},\r
{0xDFu, 0x01u},\r
- {0xE2u, 0xC0u},\r
- {0xE6u, 0x80u},\r
- {0xE8u, 0x40u},\r
- {0xE9u, 0x40u},\r
- {0xEEu, 0x08u},\r
- {0x01u, 0x02u},\r
- {0x03u, 0x08u},\r
- {0x12u, 0x02u},\r
- {0x19u, 0x51u},\r
- {0x21u, 0x09u},\r
- {0x22u, 0x81u},\r
- {0x23u, 0x08u},\r
- {0x27u, 0x02u},\r
- {0x2Au, 0x20u},\r
- {0x2Bu, 0x80u},\r
- {0x32u, 0x81u},\r
- {0x33u, 0x04u},\r
- {0x38u, 0x08u},\r
- {0x39u, 0x40u},\r
- {0x3Au, 0x02u},\r
- {0x3Bu, 0x10u},\r
- {0x3Eu, 0x08u},\r
- {0x43u, 0x94u},\r
- {0x49u, 0x08u},\r
- {0x4Au, 0x04u},\r
- {0x4Bu, 0x11u},\r
- {0x51u, 0x02u},\r
- {0x52u, 0x48u},\r
- {0x59u, 0x90u},\r
- {0x5Bu, 0x0Au},\r
- {0x60u, 0x04u},\r
- {0x61u, 0x49u},\r
- {0x69u, 0x59u},\r
- {0x6Cu, 0x20u},\r
- {0x6Eu, 0x20u},\r
- {0x6Fu, 0x02u},\r
- {0x72u, 0x92u},\r
- {0x73u, 0x04u},\r
- {0x81u, 0x0Au},\r
- {0x82u, 0x28u},\r
- {0x85u, 0x01u},\r
- {0x86u, 0x10u},\r
- {0x88u, 0x20u},\r
- {0x89u, 0x02u},\r
- {0x8Au, 0x40u},\r
- {0x8Eu, 0x08u},\r
- {0x8Fu, 0x40u},\r
- {0x91u, 0x80u},\r
- {0x92u, 0x04u},\r
- {0x93u, 0x08u},\r
- {0x95u, 0x0Du},\r
- {0x96u, 0x20u},\r
- {0x97u, 0x01u},\r
- {0x99u, 0x80u},\r
- {0x9Bu, 0x20u},\r
- {0x9Cu, 0x49u},\r
- {0x9Du, 0x0Cu},\r
- {0x9Eu, 0x40u},\r
- {0x9Fu, 0x45u},\r
- {0xA2u, 0x44u},\r
- {0xA3u, 0x80u},\r
- {0xA4u, 0x98u},\r
- {0xA5u, 0x41u},\r
- {0xA7u, 0x24u},\r
- {0xA8u, 0x02u},\r
- {0xA9u, 0x01u},\r
- {0xAEu, 0x02u},\r
- {0xAFu, 0x04u},\r
- {0xB2u, 0x02u},\r
- {0xC0u, 0x0Au},\r
- {0xC4u, 0x01u},\r
- {0xCAu, 0x05u},\r
- {0xCCu, 0x0Bu},\r
- {0xCEu, 0x4Fu},\r
- {0xD0u, 0x0Eu},\r
- {0xD2u, 0x04u},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x0Fu},\r
- {0xE0u, 0x01u},\r
- {0xE2u, 0x04u},\r
- {0xE4u, 0x06u},\r
- {0xE6u, 0x21u},\r
- {0xEAu, 0x04u},\r
- {0xEEu, 0x08u},\r
- {0x01u, 0x01u},\r
- {0x04u, 0x21u},\r
- {0x05u, 0x01u},\r
- {0x06u, 0x02u},\r
- {0x0Au, 0x01u},\r
- {0x0Bu, 0x08u},\r
- {0x0Fu, 0x06u},\r
- {0x13u, 0x01u},\r
- {0x14u, 0x04u},\r
- {0x15u, 0x01u},\r
- {0x16u, 0x43u},\r
- {0x18u, 0xE0u},\r
- {0x19u, 0x08u},\r
- {0x1Bu, 0x02u},\r
- {0x1Du, 0x01u},\r
- {0x1Eu, 0xECu},\r
+ {0x03u, 0x19u},\r
+ {0x06u, 0x0Au},\r
+ {0x07u, 0x20u},\r
+ {0x08u, 0x04u},\r
+ {0x09u, 0x20u},\r
+ {0x0Au, 0x81u},\r
+ {0x0Eu, 0x50u},\r
+ {0x0Fu, 0x05u},\r
+ {0x10u, 0x80u},\r
+ {0x11u, 0x40u},\r
+ {0x13u, 0x18u},\r
+ {0x14u, 0x40u},\r
+ {0x15u, 0x10u},\r
+ {0x17u, 0x06u},\r
+ {0x19u, 0x20u},\r
+ {0x1Au, 0x81u},\r
+ {0x1Eu, 0x04u},\r
+ {0x20u, 0x04u},\r
+ {0x21u, 0x84u},\r
+ {0x25u, 0x10u},\r
+ {0x28u, 0x80u},\r
+ {0x2Au, 0x10u},\r
+ {0x2Bu, 0x10u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Du, 0x10u},\r
+ {0x2Eu, 0x0Au},\r
+ {0x31u, 0x80u},\r
+ {0x32u, 0x04u},\r
+ {0x37u, 0xE6u},\r
+ {0x39u, 0x08u},\r
+ {0x3Au, 0x20u},\r
+ {0x3Du, 0x03u},\r
+ {0x3Eu, 0x50u},\r
+ {0x3Fu, 0x05u},\r
+ {0x58u, 0x10u},\r
+ {0x5Au, 0x10u},\r
+ {0x5Fu, 0x80u},\r
+ {0x61u, 0x01u},\r
+ {0x62u, 0x02u},\r
+ {0x64u, 0x02u},\r
+ {0x6Bu, 0x02u},\r
+ {0x6Cu, 0x02u},\r
+ {0x78u, 0x02u},\r
+ {0x82u, 0x02u},\r
+ {0x83u, 0x10u},\r
+ {0x84u, 0x80u},\r
+ {0x86u, 0xA0u},\r
+ {0x88u, 0x04u},\r
+ {0x89u, 0x10u},\r
+ {0x8Bu, 0x40u},\r
+ {0x8Cu, 0x04u},\r
+ {0x8Du, 0x40u},\r
+ {0x90u, 0x20u},\r
+ {0x92u, 0x40u},\r
+ {0x93u, 0x04u},\r
+ {0x95u, 0x19u},\r
+ {0x98u, 0x08u},\r
+ {0x99u, 0x05u},\r
+ {0x9Bu, 0x24u},\r
+ {0x9Cu, 0x10u},\r
+ {0x9Eu, 0x0Au},\r
+ {0x9Fu, 0x02u},\r
+ {0xA0u, 0x08u},\r
+ {0xA2u, 0x20u},\r
+ {0xA4u, 0x24u},\r
+ {0xA5u, 0x80u},\r
+ {0xACu, 0x40u},\r
+ {0xADu, 0x08u},\r
+ {0xB3u, 0x10u},\r
+ {0xB5u, 0x10u},\r
+ {0xC0u, 0xE7u},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0x7Fu},\r
+ {0xCAu, 0xE7u},\r
+ {0xCCu, 0xEAu},\r
+ {0xCEu, 0xF6u},\r
+ {0xD6u, 0x10u},\r
+ {0xD8u, 0x10u},\r
+ {0xDEu, 0x01u},\r
+ {0xE2u, 0x0Au},\r
+ {0xE6u, 0x47u},\r
+ {0xE8u, 0x02u},\r
+ {0xEAu, 0x08u},\r
+ {0xECu, 0x08u},\r
+ {0xEEu, 0x80u},\r
+ {0x01u, 0x44u},\r
+ {0x05u, 0xE1u},\r
+ {0x06u, 0x46u},\r
+ {0x07u, 0x12u},\r
+ {0x08u, 0x09u},\r
+ {0x09u, 0x80u},\r
+ {0x0Au, 0x12u},\r
+ {0x0Bu, 0x5Fu},\r
+ {0x0Du, 0x4Cu},\r
+ {0x0Eu, 0x80u},\r
+ {0x11u, 0x4Cu},\r
+ {0x12u, 0x30u},\r
+ {0x16u, 0x08u},\r
+ {0x17u, 0x4Cu},\r
+ {0x19u, 0xB1u},\r
+ {0x1Au, 0x09u},\r
+ {0x1Bu, 0x0Eu},\r
+ {0x1Cu, 0x09u},\r
+ {0x1Du, 0x4Cu},\r
+ {0x1Eu, 0x24u},\r
+ {0x20u, 0x40u},\r
{0x21u, 0x08u},\r
- {0x23u, 0x04u},\r
- {0x27u, 0x01u},\r
- {0x28u, 0x88u},\r
- {0x2Au, 0x03u},\r
- {0x2Bu, 0x08u},\r
- {0x2Eu, 0x12u},\r
- {0x30u, 0xE0u},\r
- {0x33u, 0x01u},\r
- {0x34u, 0x10u},\r
- {0x36u, 0x0Fu},\r
- {0x37u, 0x0Eu},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x04u},\r
- {0x54u, 0x40u},\r
- {0x58u, 0x0Bu},\r
- {0x59u, 0x04u},\r
+ {0x22u, 0x80u},\r
+ {0x23u, 0x20u},\r
+ {0x25u, 0x44u},\r
+ {0x26u, 0x01u},\r
+ {0x27u, 0x08u},\r
+ {0x30u, 0x38u},\r
+ {0x31u, 0x10u},\r
+ {0x33u, 0x61u},\r
+ {0x34u, 0x07u},\r
+ {0x35u, 0x0Fu},\r
+ {0x36u, 0xC0u},\r
+ {0x37u, 0x80u},\r
+ {0x3Bu, 0x0Cu},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x41u},\r
+ {0x54u, 0x09u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x0Bu},\r
{0x5Bu, 0x0Bu},\r
- {0x5Cu, 0x19u},\r
+ {0x5Cu, 0x91u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x18u},\r
- {0x82u, 0x60u},\r
- {0x83u, 0x30u},\r
- {0x84u, 0x28u},\r
- {0x86u, 0x53u},\r
- {0x87u, 0x40u},\r
- {0x8Cu, 0x30u},\r
- {0x8Eu, 0x48u},\r
- {0x95u, 0x43u},\r
- {0x96u, 0x04u},\r
- {0x97u, 0x1Cu},\r
- {0x9Bu, 0x4Au},\r
- {0xA0u, 0x04u},\r
- {0xA1u, 0x44u},\r
- {0xA2u, 0x02u},\r
- {0xA3u, 0x2Bu},\r
- {0xA4u, 0x04u},\r
- {0xA5u, 0x01u},\r
- {0xA6u, 0x01u},\r
- {0xAAu, 0x04u},\r
- {0xABu, 0x07u},\r
- {0xB1u, 0x70u},\r
- {0xB2u, 0x07u},\r
- {0xB3u, 0x08u},\r
- {0xB4u, 0x78u},\r
- {0xB5u, 0x07u},\r
+ {0x82u, 0x38u},\r
+ {0x85u, 0x04u},\r
+ {0x88u, 0x01u},\r
+ {0x89u, 0x04u},\r
+ {0x8Au, 0x14u},\r
+ {0x90u, 0x3Eu},\r
+ {0x94u, 0x22u},\r
+ {0x95u, 0x04u},\r
+ {0x96u, 0x01u},\r
+ {0x99u, 0x04u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA4u, 0x09u},\r
+ {0xA6u, 0x02u},\r
+ {0xABu, 0x02u},\r
+ {0xADu, 0x01u},\r
+ {0xAFu, 0x02u},\r
+ {0xB0u, 0x07u},\r
+ {0xB1u, 0x03u},\r
+ {0xB4u, 0x38u},\r
+ {0xB7u, 0x04u},\r
+ {0xB8u, 0x02u},\r
+ {0xB9u, 0x80u},\r
{0xBEu, 0x10u},\r
- {0xBFu, 0x04u},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0x04u},\r
+ {0xBFu, 0x41u},\r
+ {0xD8u, 0x0Bu},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
- {0xDDu, 0x90u},\r
+ {0xDCu, 0x09u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x20u},\r
+ {0x00u, 0x20u},\r
+ {0x02u, 0x02u},\r
{0x03u, 0x20u},\r
- {0x04u, 0x80u},\r
- {0x05u, 0x05u},\r
- {0x0Au, 0x26u},\r
- {0x0Eu, 0x10u},\r
- {0x12u, 0x01u},\r
- {0x13u, 0x10u},\r
- {0x15u, 0x01u},\r
- {0x17u, 0x24u},\r
+ {0x04u, 0x02u},\r
+ {0x05u, 0x10u},\r
+ {0x08u, 0x80u},\r
+ {0x09u, 0x01u},\r
+ {0x0Au, 0xA0u},\r
+ {0x0Bu, 0x04u},\r
+ {0x0Eu, 0x80u},\r
+ {0x0Fu, 0x10u},\r
+ {0x10u, 0x40u},\r
+ {0x11u, 0x08u},\r
+ {0x17u, 0x08u},\r
{0x19u, 0x20u},\r
- {0x1Au, 0x42u},\r
- {0x1Cu, 0x08u},\r
- {0x1Du, 0x04u},\r
- {0x21u, 0x40u},\r
- {0x22u, 0x08u},\r
- {0x24u, 0x80u},\r
- {0x25u, 0x01u},\r
- {0x26u, 0x20u},\r
- {0x27u, 0x14u},\r
- {0x29u, 0x10u},\r
- {0x2Au, 0x04u},\r
- {0x2Bu, 0x80u},\r
- {0x2Cu, 0x20u},\r
- {0x2Du, 0x01u},\r
- {0x2Fu, 0x84u},\r
- {0x30u, 0x48u},\r
- {0x32u, 0x20u},\r
- {0x33u, 0x41u},\r
- {0x34u, 0x10u},\r
- {0x35u, 0x10u},\r
- {0x37u, 0x24u},\r
- {0x39u, 0x94u},\r
- {0x3Au, 0x02u},\r
- {0x3Du, 0x02u},\r
- {0x3Fu, 0x04u},\r
- {0x5Eu, 0x80u},\r
- {0x61u, 0x20u},\r
- {0x62u, 0x08u},\r
- {0x63u, 0x01u},\r
- {0x64u, 0x01u},\r
- {0x67u, 0x02u},\r
- {0x78u, 0x01u},\r
- {0x81u, 0x40u},\r
- {0x82u, 0x40u},\r
+ {0x1Au, 0x82u},\r
+ {0x1Bu, 0x20u},\r
+ {0x1Eu, 0x80u},\r
+ {0x1Fu, 0x10u},\r
+ {0x20u, 0x04u},\r
+ {0x21u, 0x84u},\r
+ {0x23u, 0x98u},\r
+ {0x25u, 0x40u},\r
+ {0x27u, 0x40u},\r
+ {0x2Au, 0x0Bu},\r
+ {0x2Cu, 0x02u},\r
+ {0x2Fu, 0x04u},\r
+ {0x30u, 0x80u},\r
+ {0x31u, 0x10u},\r
+ {0x33u, 0x09u},\r
+ {0x35u, 0x04u},\r
+ {0x36u, 0xA0u},\r
+ {0x38u, 0x04u},\r
+ {0x39u, 0x41u},\r
+ {0x3Bu, 0x10u},\r
+ {0x3Du, 0x20u},\r
+ {0x3Eu, 0x04u},\r
+ {0x58u, 0x20u},\r
+ {0x59u, 0x09u},\r
+ {0x5Bu, 0x80u},\r
+ {0x61u, 0x80u},\r
+ {0x65u, 0x08u},\r
+ {0x66u, 0x14u},\r
+ {0x67u, 0x04u},\r
+ {0x6Cu, 0x20u},\r
+ {0x6Fu, 0x06u},\r
+ {0x78u, 0x02u},\r
+ {0x7Cu, 0x02u},\r
+ {0x82u, 0x80u},\r
{0x85u, 0x40u},\r
- {0x8Du, 0x10u},\r
- {0x91u, 0x10u},\r
- {0x92u, 0x14u},\r
- {0x93u, 0x0Cu},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x04u},\r
- {0x96u, 0x20u},\r
+ {0x86u, 0x01u},\r
+ {0x87u, 0x02u},\r
+ {0x90u, 0x20u},\r
+ {0x91u, 0x80u},\r
+ {0x92u, 0x24u},\r
+ {0x93u, 0x40u},\r
+ {0x95u, 0x40u},\r
+ {0x96u, 0x18u},\r
+ {0x97u, 0x10u},\r
+ {0x98u, 0xCAu},\r
+ {0x99u, 0x04u},\r
{0x9Au, 0x80u},\r
- {0x9Bu, 0x20u},\r
- {0x9Cu, 0x41u},\r
- {0x9Du, 0x04u},\r
- {0x9Fu, 0x15u},\r
- {0xA0u, 0x20u},\r
- {0xA2u, 0x40u},\r
- {0xA3u, 0x80u},\r
- {0xA4u, 0x98u},\r
- {0xA5u, 0x41u},\r
- {0xA7u, 0x24u},\r
- {0xA9u, 0x40u},\r
- {0xAAu, 0x80u},\r
- {0xABu, 0x08u},\r
- {0xACu, 0x08u},\r
- {0xAEu, 0x02u},\r
- {0xAFu, 0x02u},\r
- {0xB4u, 0x04u},\r
- {0xC0u, 0xB6u},\r
- {0xC2u, 0x27u},\r
- {0xC4u, 0x73u},\r
- {0xCAu, 0xE7u},\r
- {0xCCu, 0x6Fu},\r
- {0xCEu, 0xCFu},\r
- {0xD6u, 0x10u},\r
- {0xD8u, 0x1Eu},\r
- {0xDEu, 0x01u},\r
- {0xE0u, 0x01u},\r
- {0xE8u, 0x01u},\r
- {0xEAu, 0x02u},\r
- {0xECu, 0x04u},\r
- {0xEEu, 0x09u},\r
- {0x17u, 0x01u},\r
- {0x1Bu, 0x01u},\r
- {0x35u, 0x01u},\r
- {0x3Fu, 0x10u},\r
- {0x59u, 0x04u},\r
- {0x5Fu, 0x01u},\r
- {0x01u, 0x02u},\r
- {0x03u, 0x29u},\r
- {0x09u, 0x08u},\r
- {0x0Au, 0x01u},\r
- {0x0Bu, 0x04u},\r
- {0x11u, 0x25u},\r
- {0x12u, 0x01u},\r
- {0x18u, 0x04u},\r
- {0x19u, 0x80u},\r
- {0x1Au, 0x80u},\r
+ {0x9Eu, 0x10u},\r
+ {0x9Fu, 0x59u},\r
+ {0xA0u, 0x0Au},\r
+ {0xA1u, 0x14u},\r
+ {0xA2u, 0x22u},\r
+ {0xA4u, 0xA4u},\r
+ {0xA5u, 0x21u},\r
+ {0xA7u, 0x08u},\r
+ {0xA8u, 0x20u},\r
+ {0xB1u, 0x20u},\r
+ {0xB5u, 0x04u},\r
+ {0xB6u, 0x50u},\r
+ {0xC0u, 0x57u},\r
+ {0xC2u, 0x3Fu},\r
+ {0xC4u, 0x2Cu},\r
+ {0xCAu, 0x33u},\r
+ {0xCCu, 0x7Fu},\r
+ {0xCEu, 0x6Fu},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x08u},\r
+ {0xDEu, 0x81u},\r
+ {0xE2u, 0x01u},\r
+ {0xEAu, 0x10u},\r
+ {0x87u, 0x11u},\r
+ {0x8Bu, 0x06u},\r
+ {0x8Fu, 0x01u},\r
+ {0x95u, 0x19u},\r
+ {0x97u, 0x22u},\r
+ {0x99u, 0x08u},\r
+ {0xA1u, 0x21u},\r
+ {0xA3u, 0x1Cu},\r
+ {0xABu, 0x38u},\r
+ {0xB3u, 0x38u},\r
+ {0xB5u, 0x07u},\r
+ {0xD9u, 0x04u},\r
+ {0xDCu, 0x10u},\r
+ {0xDFu, 0x01u},\r
+ {0x04u, 0x04u},\r
+ {0x05u, 0x10u},\r
+ {0x07u, 0x42u},\r
+ {0x0Eu, 0xA2u},\r
+ {0x0Fu, 0x08u},\r
+ {0x15u, 0x48u},\r
+ {0x16u, 0x08u},\r
+ {0x17u, 0x11u},\r
+ {0x1Eu, 0xA0u},\r
{0x20u, 0x28u},\r
- {0x21u, 0x09u},\r
- {0x22u, 0x11u},\r
- {0x23u, 0x14u},\r
- {0x26u, 0x20u},\r
- {0x2Au, 0x40u},\r
- {0x2Bu, 0x28u},\r
- {0x31u, 0x08u},\r
- {0x32u, 0x10u},\r
- {0x33u, 0x41u},\r
- {0x34u, 0x10u},\r
- {0x37u, 0x04u},\r
- {0x38u, 0x80u},\r
- {0x39u, 0x14u},\r
- {0x41u, 0x09u},\r
- {0x43u, 0x20u},\r
- {0x48u, 0x04u},\r
- {0x49u, 0x08u},\r
- {0x4Bu, 0x80u},\r
- {0x50u, 0x01u},\r
- {0x51u, 0x20u},\r
- {0x52u, 0x45u},\r
- {0x61u, 0x10u},\r
- {0x68u, 0x08u},\r
- {0x69u, 0x15u},\r
- {0x6Bu, 0x41u},\r
- {0x70u, 0xC0u},\r
- {0x72u, 0x03u},\r
- {0x78u, 0x01u},\r
- {0x8Eu, 0x20u},\r
- {0x93u, 0x02u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x04u},\r
- {0x96u, 0x20u},\r
- {0x97u, 0x10u},\r
- {0x98u, 0x11u},\r
+ {0x21u, 0x10u},\r
+ {0x22u, 0x04u},\r
+ {0x27u, 0x02u},\r
+ {0x28u, 0x88u},\r
+ {0x2Fu, 0x1Au},\r
+ {0x30u, 0x20u},\r
+ {0x32u, 0x04u},\r
+ {0x36u, 0x10u},\r
+ {0x37u, 0x49u},\r
+ {0x39u, 0x20u},\r
+ {0x3Bu, 0x44u},\r
+ {0x3Du, 0x41u},\r
+ {0x3Eu, 0x01u},\r
+ {0x3Fu, 0x18u},\r
+ {0x45u, 0x22u},\r
+ {0x46u, 0x20u},\r
+ {0x47u, 0x08u},\r
+ {0x4Du, 0x80u},\r
+ {0x4Eu, 0x20u},\r
+ {0x4Fu, 0x18u},\r
+ {0x56u, 0x55u},\r
+ {0x57u, 0x40u},\r
+ {0x65u, 0x04u},\r
+ {0x66u, 0x50u},\r
+ {0x7Cu, 0x02u},\r
+ {0x87u, 0x04u},\r
+ {0x90u, 0x24u},\r
+ {0x91u, 0x88u},\r
+ {0x93u, 0x50u},\r
+ {0x94u, 0x02u},\r
+ {0x95u, 0x41u},\r
+ {0x96u, 0x18u},\r
+ {0x97u, 0x0Cu},\r
+ {0x98u, 0xCAu},\r
+ {0x99u, 0x20u},\r
{0x9Au, 0x80u},\r
- {0x9Bu, 0x04u},\r
- {0x9Eu, 0x07u},\r
- {0x9Fu, 0x41u},\r
- {0xA1u, 0x10u},\r
- {0xA3u, 0x80u},\r
- {0xA4u, 0x98u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Du, 0x11u},\r
+ {0x9Eu, 0x0Du},\r
+ {0x9Fu, 0x11u},\r
+ {0xA0u, 0x28u},\r
+ {0xA2u, 0x02u},\r
+ {0xA4u, 0x94u},\r
{0xA5u, 0x20u},\r
- {0xA7u, 0x24u},\r
- {0xAAu, 0x04u},\r
- {0xABu, 0x01u},\r
- {0xACu, 0x04u},\r
- {0xB5u, 0x01u},\r
- {0xC0u, 0x0Fu},\r
- {0xC2u, 0x07u},\r
- {0xC4u, 0x0Fu},\r
- {0xCAu, 0x0Eu},\r
- {0xCCu, 0x6Fu},\r
- {0xCEu, 0x0Eu},\r
- {0xD0u, 0x07u},\r
- {0xD2u, 0x0Cu},\r
- {0xD8u, 0x04u},\r
- {0xDEu, 0x01u},\r
- {0xE2u, 0x10u},\r
- {0xECu, 0x42u},\r
- {0xAFu, 0x08u},\r
- {0x80u, 0x40u},\r
- {0x94u, 0x80u},\r
{0xA7u, 0x08u},\r
- {0xA8u, 0x28u},\r
- {0xA9u, 0x18u},\r
+ {0xA8u, 0x20u},\r
{0xAAu, 0x02u},\r
- {0xAFu, 0x80u},\r
- {0xE0u, 0x01u},\r
- {0xE6u, 0x10u},\r
- {0xE8u, 0x01u},\r
- {0xEAu, 0x12u},\r
- {0xEEu, 0x01u},\r
- {0x00u, 0x0Fu},\r
- {0x02u, 0xF0u},\r
- {0x0Bu, 0xFFu},\r
- {0x0Cu, 0x33u},\r
- {0x0Eu, 0xCCu},\r
- {0x0Fu, 0xFFu},\r
- {0x11u, 0x33u},\r
- {0x13u, 0xCCu},\r
- {0x14u, 0xFFu},\r
- {0x18u, 0x96u},\r
- {0x19u, 0x55u},\r
- {0x1Au, 0x69u},\r
- {0x1Bu, 0xAAu},\r
- {0x1Cu, 0x55u},\r
- {0x1Eu, 0xAAu},\r
- {0x21u, 0xFFu},\r
- {0x26u, 0xFFu},\r
- {0x29u, 0x96u},\r
- {0x2Au, 0xFFu},\r
- {0x2Bu, 0x69u},\r
- {0x2Du, 0x0Fu},\r
- {0x2Fu, 0xF0u},\r
- {0x35u, 0xFFu},\r
- {0x36u, 0xFFu},\r
- {0x3Eu, 0x40u},\r
- {0x3Fu, 0x10u},\r
+ {0xAFu, 0x10u},\r
+ {0xB7u, 0x04u},\r
+ {0xC0u, 0xF0u},\r
+ {0xC2u, 0xF0u},\r
+ {0xC4u, 0xF0u},\r
+ {0xCAu, 0x75u},\r
+ {0xCCu, 0xF6u},\r
+ {0xCEu, 0xFEu},\r
+ {0xD0u, 0xE0u},\r
+ {0xD2u, 0x30u},\r
+ {0xD8u, 0x70u},\r
+ {0xDEu, 0x80u},\r
+ {0xEAu, 0x08u},\r
+ {0xEEu, 0x10u},\r
+ {0x9Eu, 0x40u},\r
+ {0x9Fu, 0x08u},\r
+ {0xEAu, 0x08u},\r
+ {0x9Eu, 0x40u},\r
+ {0x9Fu, 0x08u},\r
+ {0xABu, 0x01u},\r
+ {0xAFu, 0x40u},\r
+ {0xB0u, 0x04u},\r
+ {0xB3u, 0x40u},\r
+ {0xB5u, 0x01u},\r
+ {0xB6u, 0x04u},\r
+ {0xE2u, 0x01u},\r
+ {0xE8u, 0x20u},\r
+ {0xEAu, 0x49u},\r
+ {0xEEu, 0x40u},\r
+ {0x00u, 0x12u},\r
+ {0x02u, 0x24u},\r
+ {0x05u, 0x02u},\r
+ {0x06u, 0x12u},\r
+ {0x0Au, 0x0Cu},\r
+ {0x0Eu, 0x02u},\r
+ {0x11u, 0x06u},\r
+ {0x13u, 0x08u},\r
+ {0x16u, 0x60u},\r
+ {0x17u, 0x0Du},\r
+ {0x1Bu, 0x07u},\r
+ {0x1Cu, 0x12u},\r
+ {0x1Du, 0x07u},\r
+ {0x1Eu, 0x48u},\r
+ {0x1Fu, 0x08u},\r
+ {0x20u, 0x01u},\r
+ {0x21u, 0x02u},\r
+ {0x25u, 0x01u},\r
+ {0x26u, 0x10u},\r
+ {0x27u, 0x02u},\r
+ {0x29u, 0x10u},\r
+ {0x30u, 0x01u},\r
+ {0x32u, 0x70u},\r
+ {0x33u, 0x08u},\r
+ {0x34u, 0x0Eu},\r
+ {0x35u, 0x10u},\r
+ {0x37u, 0x07u},\r
+ {0x3Eu, 0x01u},\r
+ {0x3Fu, 0x14u},\r
+ {0x40u, 0x31u},\r
+ {0x41u, 0x04u},\r
+ {0x42u, 0x60u},\r
+ {0x45u, 0xEFu},\r
+ {0x46u, 0x20u},\r
+ {0x47u, 0xDCu},\r
+ {0x48u, 0x3Bu},\r
+ {0x49u, 0xFFu},\r
+ {0x4Au, 0xFFu},\r
+ {0x4Bu, 0xFFu},\r
+ {0x4Fu, 0x2Cu},\r
+ {0x56u, 0x01u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
+ {0x5Au, 0x04u},\r
{0x5Bu, 0x04u},\r
+ {0x5Cu, 0x11u},\r
+ {0x5Du, 0x01u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0xFFu},\r
- {0x88u, 0x69u},\r
- {0x8Au, 0x96u},\r
- {0x8Bu, 0xFFu},\r
- {0x8Cu, 0x33u},\r
- {0x8Du, 0x33u},\r
- {0x8Eu, 0xCCu},\r
- {0x8Fu, 0xCCu},\r
- {0x91u, 0x0Fu},\r
- {0x92u, 0xFFu},\r
- {0x93u, 0xF0u},\r
- {0x97u, 0xFFu},\r
- {0x98u, 0xFFu},\r
- {0x99u, 0x55u},\r
- {0x9Bu, 0xAAu},\r
- {0x9Cu, 0x0Fu},\r
- {0x9Eu, 0xF0u},\r
- {0xA3u, 0xFFu},\r
- {0xA4u, 0x55u},\r
- {0xA6u, 0xAAu},\r
- {0xA9u, 0x69u},\r
- {0xABu, 0x96u},\r
- {0xB0u, 0xFFu},\r
- {0xB7u, 0xFFu},\r
- {0xBEu, 0x01u},\r
- {0xBFu, 0x40u},\r
+ {0x62u, 0xC0u},\r
+ {0x66u, 0x80u},\r
+ {0x68u, 0x40u},\r
+ {0x69u, 0x40u},\r
+ {0x6Eu, 0x08u},\r
+ {0x81u, 0x02u},\r
+ {0x84u, 0x02u},\r
+ {0x89u, 0x01u},\r
+ {0x8Du, 0x04u},\r
+ {0xACu, 0x01u},\r
+ {0xB3u, 0x01u},\r
+ {0xB4u, 0x02u},\r
+ {0xB5u, 0x02u},\r
+ {0xB6u, 0x01u},\r
+ {0xB7u, 0x04u},\r
+ {0xBEu, 0x50u},\r
+ {0xBFu, 0x54u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
{0x01u, 0x08u},\r
- {0x03u, 0x09u},\r
- {0x04u, 0x80u},\r
- {0x05u, 0x01u},\r
+ {0x05u, 0x10u},\r
+ {0x06u, 0x60u},\r
{0x07u, 0x01u},\r
- {0x09u, 0x12u},\r
- {0x0Bu, 0x02u},\r
- {0x0Cu, 0x08u},\r
+ {0x08u, 0x08u},\r
+ {0x09u, 0x08u},\r
{0x0Du, 0x80u},\r
- {0x0Fu, 0x08u},\r
+ {0x0Eu, 0x20u},\r
{0x10u, 0x10u},\r
- {0x14u, 0x20u},\r
- {0x15u, 0x20u},\r
- {0x1Au, 0x80u},\r
- {0x1Fu, 0x80u},\r
+ {0x12u, 0x22u},\r
+ {0x14u, 0x80u},\r
+ {0x17u, 0x04u},\r
+ {0x19u, 0xA0u},\r
+ {0x1Cu, 0x40u},\r
+ {0x1Du, 0x10u},\r
+ {0x1Eu, 0x20u},\r
{0x20u, 0x01u},\r
- {0x25u, 0x20u},\r
- {0x2Au, 0x02u},\r
- {0x2Bu, 0x0Cu},\r
- {0x2Cu, 0x02u},\r
+ {0x21u, 0x08u},\r
+ {0x23u, 0x04u},\r
+ {0x25u, 0x80u},\r
+ {0x26u, 0xA8u},\r
+ {0x2Cu, 0x04u},\r
+ {0x2Du, 0x02u},\r
{0x2Eu, 0x02u},\r
- {0x2Fu, 0x09u},\r
- {0x30u, 0x1Au},\r
- {0x31u, 0x01u},\r
- {0x34u, 0x10u},\r
- {0x37u, 0x01u},\r
- {0x38u, 0x80u},\r
+ {0x2Fu, 0x10u},\r
+ {0x34u, 0x20u},\r
+ {0x36u, 0x80u},\r
+ {0x37u, 0x0Au},\r
{0x39u, 0x20u},\r
- {0x3Cu, 0x80u},\r
- {0x3Du, 0x20u},\r
- {0x5Cu, 0x08u},\r
- {0x5Du, 0x80u},\r
- {0x5Eu, 0x11u},\r
- {0x80u, 0x08u},\r
- {0x82u, 0x10u},\r
- {0x84u, 0x10u},\r
+ {0x3Bu, 0x81u},\r
+ {0x3Eu, 0x04u},\r
+ {0x3Fu, 0x08u},\r
+ {0x45u, 0x80u},\r
+ {0x46u, 0x60u},\r
+ {0x47u, 0x0Au},\r
+ {0x4Eu, 0x58u},\r
+ {0x55u, 0x10u},\r
+ {0x56u, 0x02u},\r
+ {0x57u, 0x04u},\r
+ {0x59u, 0x02u},\r
+ {0x5Au, 0xA4u},\r
+ {0x5Cu, 0x49u},\r
+ {0x5Du, 0x20u},\r
+ {0x64u, 0x10u},\r
+ {0x65u, 0x80u},\r
+ {0x67u, 0x44u},\r
+ {0x6Eu, 0x08u},\r
+ {0x6Fu, 0x45u},\r
+ {0x74u, 0xA4u},\r
+ {0x75u, 0x01u},\r
+ {0x81u, 0x10u},\r
+ {0x82u, 0x02u},\r
+ {0x83u, 0x40u},\r
+ {0x84u, 0xA0u},\r
{0x85u, 0x80u},\r
- {0x88u, 0x40u},\r
- {0x89u, 0x12u},\r
- {0x8Au, 0x01u},\r
- {0x8Du, 0x80u},\r
- {0x8Eu, 0x40u},\r
- {0x94u, 0x01u},\r
- {0xA0u, 0x02u},\r
- {0xA5u, 0x20u},\r
- {0xA9u, 0x20u},\r
- {0xC0u, 0x97u},\r
- {0xC2u, 0xEBu},\r
- {0xC4u, 0x64u},\r
- {0xCAu, 0xB5u},\r
- {0xCCu, 0xA7u},\r
- {0xCEu, 0x3Cu},\r
- {0xD6u, 0xF0u},\r
- {0xE2u, 0x94u},\r
- {0xE4u, 0xE2u},\r
- {0xE6u, 0x01u},\r
- {0xEEu, 0x28u},\r
- {0x80u, 0x02u},\r
- {0x8Cu, 0x01u},\r
- {0xE0u, 0x04u},\r
- {0xE6u, 0x50u},\r
- {0x8Cu, 0x40u},\r
- {0x90u, 0x40u},\r
- {0xABu, 0x21u},\r
- {0xE2u, 0x40u},\r
- {0x04u, 0x08u},\r
- {0x06u, 0x33u},\r
- {0x08u, 0x20u},\r
- {0x0Au, 0x18u},\r
- {0x0Eu, 0x01u},\r
- {0x14u, 0x2Eu},\r
- {0x15u, 0x04u},\r
- {0x16u, 0x10u},\r
+ {0x88u, 0x04u},\r
+ {0x89u, 0x10u},\r
+ {0x8Au, 0x10u},\r
+ {0x8Du, 0x18u},\r
+ {0x93u, 0x20u},\r
+ {0x98u, 0xA0u},\r
+ {0xB0u, 0x80u},\r
+ {0xC0u, 0xF4u},\r
+ {0xC2u, 0xA0u},\r
+ {0xC4u, 0x31u},\r
+ {0xCAu, 0xE0u},\r
+ {0xCCu, 0xF0u},\r
+ {0xCEu, 0x4Du},\r
+ {0xD0u, 0xD0u},\r
+ {0xD2u, 0x20u},\r
+ {0xD6u, 0xFFu},\r
+ {0xD8u, 0xF0u},\r
+ {0xE2u, 0xA1u},\r
+ {0xE6u, 0x90u},\r
+ {0xE8u, 0x42u},\r
+ {0xEAu, 0x08u},\r
+ {0xECu, 0x08u},\r
+ {0x80u, 0x20u},\r
+ {0x87u, 0x10u},\r
+ {0xE0u, 0x80u},\r
+ {0xE6u, 0x07u},\r
+ {0xB4u, 0x04u},\r
+ {0x00u, 0xD6u},\r
+ {0x04u, 0xD2u},\r
+ {0x05u, 0x40u},\r
+ {0x06u, 0x04u},\r
+ {0x07u, 0x30u},\r
+ {0x08u, 0x29u},\r
+ {0x09u, 0x58u},\r
+ {0x0Au, 0x16u},\r
+ {0x0Bu, 0x23u},\r
+ {0x0Cu, 0x04u},\r
+ {0x0Fu, 0x0Cu},\r
+ {0x12u, 0x80u},\r
+ {0x14u, 0x31u},\r
+ {0x16u, 0x0Eu},\r
{0x17u, 0x01u},\r
- {0x18u, 0x18u},\r
- {0x1Au, 0x25u},\r
- {0x1Bu, 0x03u},\r
- {0x21u, 0x04u},\r
- {0x23u, 0x02u},\r
- {0x27u, 0x04u},\r
- {0x2Fu, 0x04u},\r
- {0x30u, 0x07u},\r
- {0x33u, 0x07u},\r
- {0x34u, 0x38u},\r
- {0x3Au, 0x20u},\r
- {0x58u, 0x08u},\r
- {0x59u, 0x04u},\r
- {0x5Cu, 0x19u},\r
+ {0x1Bu, 0x82u},\r
+ {0x1Cu, 0x22u},\r
+ {0x1Eu, 0x10u},\r
+ {0x20u, 0xD6u},\r
+ {0x24u, 0x17u},\r
+ {0x25u, 0x34u},\r
+ {0x26u, 0x28u},\r
+ {0x27u, 0x43u},\r
+ {0x28u, 0xD0u},\r
+ {0x29u, 0x11u},\r
+ {0x2Au, 0x06u},\r
+ {0x2Bu, 0x62u},\r
+ {0x2Cu, 0x06u},\r
+ {0x2Eu, 0xD0u},\r
+ {0x30u, 0x40u},\r
+ {0x32u, 0x80u},\r
+ {0x33u, 0x80u},\r
+ {0x34u, 0x0Fu},\r
+ {0x35u, 0x70u},\r
+ {0x36u, 0x30u},\r
+ {0x37u, 0x0Fu},\r
+ {0x38u, 0x20u},\r
+ {0x39u, 0x02u},\r
+ {0x3Au, 0x80u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Eu, 0x05u},\r
+ {0x3Fu, 0x01u},\r
+ {0x56u, 0x02u},\r
+ {0x57u, 0x28u},\r
+ {0x58u, 0x0Bu},\r
+ {0x59u, 0x0Bu},\r
+ {0x5Bu, 0x0Bu},\r
+ {0x5Cu, 0x99u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x2Cu},\r
- {0x83u, 0x9Fu},\r
- {0x84u, 0x24u},\r
- {0x85u, 0xC0u},\r
- {0x86u, 0x08u},\r
- {0x87u, 0x04u},\r
- {0x88u, 0x44u},\r
- {0x89u, 0xC0u},\r
- {0x8Au, 0x20u},\r
- {0x8Bu, 0x08u},\r
- {0x8Cu, 0x0Cu},\r
- {0x8Du, 0xC0u},\r
- {0x8Eu, 0x20u},\r
- {0x8Fu, 0x01u},\r
- {0x90u, 0x10u},\r
- {0x91u, 0x90u},\r
- {0x93u, 0x40u},\r
- {0x94u, 0xE0u},\r
- {0x95u, 0x7Fu},\r
- {0x96u, 0x0Fu},\r
- {0x97u, 0x80u},\r
- {0x98u, 0xA1u},\r
- {0x9Au, 0x42u},\r
- {0x9Bu, 0xFFu},\r
- {0x9Cu, 0x10u},\r
- {0x9Du, 0xC0u},\r
- {0x9Fu, 0x02u},\r
- {0xA0u, 0x08u},\r
- {0xA3u, 0x60u},\r
- {0xA4u, 0xC1u},\r
- {0xA5u, 0x1Fu},\r
- {0xA6u, 0x2Eu},\r
- {0xA7u, 0x20u},\r
- {0xA8u, 0x20u},\r
- {0xA9u, 0x80u},\r
- {0xAAu, 0x0Cu},\r
- {0xACu, 0x2Cu},\r
- {0xB0u, 0x10u},\r
- {0xB2u, 0x60u},\r
- {0xB4u, 0x0Fu},\r
- {0xB6u, 0x80u},\r
- {0xB7u, 0xFFu},\r
- {0xB8u, 0x02u},\r
- {0xBAu, 0x08u},\r
- {0xBEu, 0x40u},\r
- {0xBFu, 0x40u},\r
- {0xD4u, 0x09u},\r
- {0xD8u, 0x0Bu},\r
+ {0x84u, 0x05u},\r
+ {0x86u, 0x0Au},\r
+ {0x87u, 0x70u},\r
+ {0x88u, 0x03u},\r
+ {0x8Au, 0x0Cu},\r
+ {0x8Bu, 0x80u},\r
+ {0x8Cu, 0x30u},\r
+ {0x8Eu, 0xC0u},\r
+ {0x8Fu, 0x04u},\r
+ {0x95u, 0x09u},\r
+ {0x97u, 0x14u},\r
+ {0x98u, 0x06u},\r
+ {0x99u, 0x01u},\r
+ {0x9Au, 0x09u},\r
+ {0x9Bu, 0x0Au},\r
+ {0x9Du, 0x40u},\r
+ {0x9Fu, 0x80u},\r
+ {0xA0u, 0x0Fu},\r
+ {0xA1u, 0x0Eu},\r
+ {0xA2u, 0xF0u},\r
+ {0xA3u, 0x21u},\r
+ {0xA4u, 0x60u},\r
+ {0xA6u, 0x90u},\r
+ {0xA8u, 0x50u},\r
+ {0xAAu, 0xA0u},\r
+ {0xABu, 0x07u},\r
+ {0xAFu, 0x08u},\r
+ {0xB1u, 0xC0u},\r
+ {0xB2u, 0xFFu},\r
+ {0xB3u, 0x38u},\r
+ {0xB5u, 0x07u},\r
+ {0xBEu, 0x04u},\r
+ {0xBFu, 0x01u},\r
+ {0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x0Bu},\r
- {0xDCu, 0x09u},\r
- {0xDDu, 0x90u},\r
+ {0xDCu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x04u},\r
- {0x03u, 0x49u},\r
- {0x04u, 0x48u},\r
+ {0x00u, 0x08u},\r
+ {0x01u, 0x20u},\r
+ {0x02u, 0x02u},\r
{0x05u, 0x10u},\r
- {0x09u, 0x88u},\r
- {0x0Au, 0x84u},\r
- {0x0Du, 0x08u},\r
- {0x0Fu, 0x04u},\r
- {0x11u, 0x50u},\r
- {0x12u, 0x40u},\r
- {0x13u, 0x05u},\r
- {0x18u, 0x08u},\r
- {0x19u, 0x42u},\r
- {0x1Au, 0x04u},\r
- {0x1Bu, 0x28u},\r
- {0x1Cu, 0x40u},\r
- {0x1Du, 0x10u},\r
- {0x21u, 0x80u},\r
- {0x27u, 0x10u},\r
- {0x29u, 0x02u},\r
- {0x2Bu, 0x28u},\r
- {0x2Cu, 0x10u},\r
- {0x2Eu, 0x80u},\r
- {0x2Fu, 0x80u},\r
- {0x31u, 0x08u},\r
- {0x32u, 0x10u},\r
- {0x33u, 0x41u},\r
- {0x37u, 0x14u},\r
- {0x38u, 0x82u},\r
- {0x39u, 0x54u},\r
- {0x59u, 0x88u},\r
- {0x5Au, 0x02u},\r
- {0x5Bu, 0x20u},\r
- {0x61u, 0x40u},\r
- {0x78u, 0x01u},\r
- {0x7Fu, 0x01u},\r
- {0x83u, 0x10u},\r
- {0x8Fu, 0x04u},\r
- {0x90u, 0x82u},\r
- {0x91u, 0x14u},\r
- {0x92u, 0xA2u},\r
- {0x93u, 0x06u},\r
- {0x98u, 0x11u},\r
- {0x99u, 0x88u},\r
- {0x9Au, 0xC0u},\r
- {0x9Bu, 0x45u},\r
- {0x9Du, 0x12u},\r
- {0xA1u, 0x08u},\r
- {0xA3u, 0x80u},\r
- {0xA7u, 0x2Cu},\r
- {0xB3u, 0x40u},\r
- {0xC0u, 0xEFu},\r
- {0xC2u, 0x6Fu},\r
- {0xC4u, 0x0Fu},\r
- {0xCAu, 0xD7u},\r
- {0xCCu, 0x6Fu},\r
- {0xCEu, 0x0Fu},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x08u},\r
- {0xDEu, 0x11u},\r
- {0xE0u, 0x40u},\r
+ {0x06u, 0x01u},\r
+ {0x07u, 0x50u},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Eu, 0x02u},\r
+ {0x0Fu, 0x90u},\r
+ {0x10u, 0x48u},\r
+ {0x12u, 0x10u},\r
+ {0x15u, 0x50u},\r
+ {0x17u, 0x09u},\r
+ {0x1Au, 0x10u},\r
+ {0x1Du, 0x37u},\r
+ {0x1Eu, 0x03u},\r
+ {0x1Fu, 0x10u},\r
+ {0x20u, 0x04u},\r
+ {0x21u, 0x05u},\r
+ {0x22u, 0x10u},\r
+ {0x23u, 0x04u},\r
+ {0x24u, 0x02u},\r
+ {0x25u, 0x51u},\r
+ {0x26u, 0x08u},\r
+ {0x28u, 0x88u},\r
+ {0x2Au, 0x80u},\r
+ {0x2Eu, 0x20u},\r
+ {0x2Fu, 0x10u},\r
+ {0x30u, 0x40u},\r
+ {0x32u, 0x14u},\r
+ {0x36u, 0x28u},\r
+ {0x38u, 0x20u},\r
+ {0x39u, 0x88u},\r
+ {0x3Au, 0x10u},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Du, 0x80u},\r
+ {0x3Eu, 0x08u},\r
+ {0x3Fu, 0x10u},\r
+ {0x45u, 0x10u},\r
+ {0x46u, 0x08u},\r
+ {0x66u, 0x08u},\r
+ {0x6Cu, 0x80u},\r
+ {0x6Du, 0x50u},\r
+ {0x6Fu, 0x58u},\r
+ {0x77u, 0x01u},\r
+ {0x7Cu, 0x02u},\r
+ {0x83u, 0x12u},\r
+ {0x8Du, 0x01u},\r
+ {0x90u, 0x20u},\r
+ {0x91u, 0x80u},\r
+ {0x92u, 0x08u},\r
+ {0x93u, 0x10u},\r
+ {0x94u, 0x02u},\r
+ {0x95u, 0x42u},\r
+ {0x96u, 0x11u},\r
+ {0x97u, 0x24u},\r
+ {0x98u, 0xCAu},\r
+ {0x99u, 0x20u},\r
+ {0x9Au, 0xA1u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Du, 0x15u},\r
+ {0x9Fu, 0x51u},\r
+ {0xA0u, 0x0Cu},\r
+ {0xA2u, 0x22u},\r
+ {0xA3u, 0x40u},\r
+ {0xA4u, 0x80u},\r
+ {0xA5u, 0x22u},\r
+ {0xA6u, 0x01u},\r
+ {0xA7u, 0x0Au},\r
+ {0xB0u, 0x10u},\r
+ {0xB1u, 0x01u},\r
+ {0xB5u, 0x80u},\r
+ {0xC0u, 0xF7u},\r
+ {0xC2u, 0xB2u},\r
+ {0xC4u, 0xFEu},\r
+ {0xCAu, 0x6Du},\r
+ {0xCCu, 0x6Eu},\r
+ {0xCEu, 0x7Eu},\r
+ {0xD8u, 0x40u},\r
+ {0xDEu, 0x80u},\r
+ {0xE2u, 0x10u},\r
+ {0xEAu, 0x20u},\r
+ {0xECu, 0x40u},\r
+ {0x9Fu, 0x08u},\r
+ {0xB2u, 0x40u},\r
{0xECu, 0x80u},\r
- {0xEEu, 0x0Au},\r
- {0xEEu, 0x0Au},\r
- {0x33u, 0x80u},\r
- {0x36u, 0x40u},\r
- {0x5Bu, 0x08u},\r
- {0x5Fu, 0x22u},\r
- {0x60u, 0x10u},\r
- {0x64u, 0x20u},\r
- {0x83u, 0x22u},\r
- {0xCCu, 0x30u},\r
- {0xD6u, 0xE0u},\r
+ {0xB7u, 0x08u},\r
+ {0xECu, 0x40u},\r
+ {0x30u, 0x20u},\r
+ {0x33u, 0x02u},\r
+ {0x34u, 0x04u},\r
+ {0x35u, 0x20u},\r
+ {0x38u, 0x80u},\r
+ {0x56u, 0x80u},\r
+ {0x5Bu, 0x02u},\r
+ {0x5Eu, 0x01u},\r
+ {0x63u, 0x40u},\r
+ {0x65u, 0x04u},\r
+ {0x81u, 0x20u},\r
+ {0x8Du, 0x04u},\r
+ {0xCCu, 0xF0u},\r
+ {0xCEu, 0x10u},\r
+ {0xD4u, 0x40u},\r
+ {0xD6u, 0xC0u},\r
{0xD8u, 0xC0u},\r
- {0xE2u, 0x80u},\r
{0xE6u, 0x80u},\r
- {0x52u, 0x80u},\r
- {0x57u, 0x10u},\r
- {0x5Bu, 0x20u},\r
+ {0x51u, 0x02u},\r
+ {0x56u, 0x20u},\r
{0x5Eu, 0x01u},\r
+ {0x5Fu, 0x20u},\r
+ {0x8Eu, 0x20u},\r
+ {0x94u, 0x80u},\r
+ {0x97u, 0x40u},\r
+ {0x9Cu, 0x04u},\r
+ {0x9Eu, 0x80u},\r
+ {0x9Fu, 0x02u},\r
+ {0xA4u, 0x20u},\r
+ {0xAFu, 0x02u},\r
+ {0xB2u, 0x01u},\r
+ {0xD4u, 0xC0u},\r
+ {0xD6u, 0xA0u},\r
+ {0xEAu, 0x10u},\r
+ {0x10u, 0x20u},\r
+ {0x80u, 0x40u},\r
+ {0x83u, 0x80u},\r
+ {0x86u, 0x81u},\r
+ {0x87u, 0x02u},\r
+ {0x94u, 0x80u},\r
+ {0x96u, 0x01u},\r
+ {0x97u, 0x40u},\r
+ {0x9Bu, 0x40u},\r
+ {0x9Cu, 0x04u},\r
+ {0x9Eu, 0x80u},\r
+ {0x9Fu, 0x02u},\r
+ {0xA4u, 0x20u},\r
+ {0xA5u, 0x02u},\r
+ {0xABu, 0x20u},\r
+ {0xB7u, 0x40u},\r
+ {0xC4u, 0x10u},\r
+ {0xE2u, 0xD0u},\r
+ {0xE4u, 0x20u},\r
+ {0xE6u, 0x40u},\r
+ {0xEAu, 0x80u},\r
{0x86u, 0x80u},\r
- {0x8Bu, 0x20u},\r
- {0x9Cu, 0x20u},\r
- {0x9Fu, 0x08u},\r
- {0xA6u, 0x40u},\r
+ {0x97u, 0x40u},\r
+ {0x9Bu, 0x40u},\r
+ {0xA1u, 0x80u},\r
{0xA7u, 0x80u},\r
- {0xA8u, 0x10u},\r
- {0xD4u, 0xE0u},\r
- {0xD6u, 0x80u},\r
- {0xE6u, 0x10u},\r
- {0xEEu, 0x80u},\r
- {0x80u, 0x02u},\r
- {0x87u, 0x20u},\r
- {0x9Fu, 0x08u},\r
- {0xA6u, 0x40u},\r
- {0xA7u, 0x90u},\r
- {0xA8u, 0x20u},\r
- {0xAEu, 0x01u},\r
- {0xE0u, 0x40u},\r
- {0xE2u, 0x20u},\r
+ {0xACu, 0x04u},\r
+ {0xADu, 0x80u},\r
+ {0xB5u, 0x02u},\r
+ {0xE4u, 0x10u},\r
{0xEAu, 0x10u},\r
- {0xEEu, 0x20u},\r
- {0x8Fu, 0x10u},\r
- {0x9Fu, 0x28u},\r
- {0xA0u, 0x02u},\r
- {0xA6u, 0x40u},\r
- {0xA7u, 0x90u},\r
- {0xB7u, 0x08u},\r
- {0x0Bu, 0x08u},\r
- {0x0Cu, 0x02u},\r
- {0x12u, 0x10u},\r
- {0x53u, 0x10u},\r
- {0x55u, 0x08u},\r
- {0x5Au, 0x10u},\r
- {0x5Eu, 0x40u},\r
- {0x82u, 0x40u},\r
- {0x8Cu, 0x02u},\r
+ {0xEEu, 0x40u},\r
+ {0x0Bu, 0x02u},\r
+ {0x0Fu, 0x40u},\r
+ {0x10u, 0x10u},\r
+ {0x52u, 0x80u},\r
+ {0x54u, 0x40u},\r
+ {0x58u, 0x20u},\r
+ {0x5Eu, 0x20u},\r
+ {0x80u, 0x02u},\r
+ {0x83u, 0x01u},\r
+ {0x87u, 0x40u},\r
+ {0x88u, 0x20u},\r
{0xC2u, 0x06u},\r
{0xC4u, 0x08u},\r
{0xD4u, 0x07u},\r
{0xD6u, 0x04u},\r
- {0xE6u, 0x02u},\r
- {0x01u, 0x80u},\r
- {0x04u, 0x80u},\r
- {0x05u, 0x02u},\r
- {0x08u, 0x81u},\r
- {0x0Eu, 0x02u},\r
- {0x0Fu, 0x20u},\r
- {0x81u, 0x80u},\r
- {0x83u, 0x10u},\r
- {0x87u, 0x10u},\r
- {0x89u, 0x02u},\r
- {0x96u, 0x10u},\r
- {0x97u, 0x20u},\r
- {0xA5u, 0x08u},\r
- {0xAFu, 0x04u},\r
- {0xB2u, 0x10u},\r
+ {0xE0u, 0x01u},\r
+ {0x00u, 0x20u},\r
+ {0x06u, 0x40u},\r
+ {0x07u, 0x04u},\r
+ {0x09u, 0x02u},\r
+ {0x0Bu, 0x04u},\r
+ {0x0Eu, 0x08u},\r
+ {0x0Fu, 0x10u},\r
+ {0x81u, 0x02u},\r
+ {0x8Au, 0x40u},\r
+ {0x8Bu, 0x04u},\r
+ {0x8Eu, 0x04u},\r
+ {0x9Cu, 0x02u},\r
+ {0xA4u, 0x02u},\r
+ {0xACu, 0x42u},\r
+ {0xAEu, 0x10u},\r
+ {0xB0u, 0x10u},\r
+ {0xB6u, 0x80u},\r
{0xC0u, 0x07u},\r
{0xC2u, 0x0Fu},\r
- {0xE2u, 0x01u},\r
- {0xEEu, 0x04u},\r
- {0x82u, 0x10u},\r
- {0x8Cu, 0x40u},\r
- {0x90u, 0x80u},\r
- {0x96u, 0x10u},\r
- {0xA9u, 0x08u},\r
- {0xAAu, 0x01u},\r
- {0xACu, 0x01u},\r
- {0xB4u, 0x80u},\r
- {0xE6u, 0x08u},\r
- {0xEAu, 0x08u},\r
- {0x08u, 0x08u},\r
- {0x0Fu, 0x40u},\r
- {0xC2u, 0x0Cu},\r
+ {0xE2u, 0x02u},\r
+ {0xE6u, 0x05u},\r
+ {0xE8u, 0x02u},\r
+ {0xEAu, 0x04u},\r
+ {0x81u, 0x40u},\r
+ {0x9Cu, 0x02u},\r
+ {0xA4u, 0x02u},\r
+ {0xABu, 0x04u},\r
+ {0xAFu, 0x10u},\r
+ {0xB0u, 0x10u},\r
+ {0xEEu, 0x01u},\r
+ {0x08u, 0x02u},\r
+ {0x0Au, 0x01u},\r
+ {0x0Cu, 0x02u},\r
+ {0x0Du, 0x40u},\r
+ {0x95u, 0x80u},\r
+ {0x96u, 0x01u},\r
+ {0x9Cu, 0x02u},\r
+ {0xA4u, 0x02u},\r
+ {0xAEu, 0x01u},\r
+ {0xC2u, 0x0Fu},\r
{0x26u, 0x80u},\r
- {0x27u, 0x20u},\r
- {0x83u, 0x08u},\r
- {0x8Eu, 0x80u},\r
- {0x9Eu, 0x40u},\r
- {0x9Fu, 0x28u},\r
- {0xA0u, 0x02u},\r
- {0xAEu, 0x40u},\r
- {0xAFu, 0x80u},\r
- {0xB2u, 0x40u},\r
- {0xC8u, 0xA0u},\r
- {0xE2u, 0x20u},\r
- {0xEEu, 0x50u},\r
- {0x06u, 0x40u},\r
- {0x50u, 0x02u},\r
- {0x57u, 0x80u},\r
- {0x8Fu, 0x80u},\r
- {0x9Eu, 0x40u},\r
- {0xA0u, 0x02u},\r
+ {0x65u, 0x04u},\r
+ {0x8Du, 0x04u},\r
+ {0x9Bu, 0x40u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA1u, 0x80u},\r
+ {0xA6u, 0x80u},\r
+ {0xA7u, 0x80u},\r
+ {0xB3u, 0x40u},\r
+ {0xB7u, 0x10u},\r
+ {0xC8u, 0x20u},\r
+ {0xD8u, 0x80u},\r
+ {0x07u, 0x10u},\r
+ {0x1Bu, 0x80u},\r
+ {0x51u, 0x80u},\r
+ {0x5Bu, 0x40u},\r
+ {0x9Bu, 0x40u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA1u, 0x80u},\r
+ {0xA7u, 0x80u},\r
{0xC0u, 0x20u},\r
- {0xD4u, 0xC0u},\r
- {0xACu, 0x08u},\r
- {0xAFu, 0x40u},\r
+ {0xC6u, 0x40u},\r
+ {0xD4u, 0xA0u},\r
{0x00u, 0x02u},\r
{0x01u, 0x01u},\r
{0x08u, 0x02u},\r
{0x09u, 0x01u},\r
{0x0Au, 0x02u},\r
{0x0Bu, 0x01u},\r
+ {0x0Eu, 0x02u},\r
{0x10u, 0x02u},\r
{0x11u, 0x01u},\r
{0x1Au, 0x02u},\r
{0x1Bu, 0x01u},\r
- {0x00u, 0x0Au},\r
+ {0x00u, 0xABu},\r
+ {0x01u, 0x02u},\r
};\r
\r
\r
\r
static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
/* address, size */\r
+ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
{(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1664u},\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P3_ROUTE_BASE), 2304u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1536u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), 2432u},\r
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},\r
};\r
\r
- /* UDB_1_2_0_CONFIG Address: CYDEV_UCFG_B0_P3_U1_BASE Size (bytes): 128 */\r
- static const uint8 CYCODE BS_UDB_1_2_0_CONFIG_VAL[] = {\r
- 0x04u, 0x00u, 0x00u, 0x00u, 0x07u, 0xC2u, 0x18u, 0x04u, 0x01u, 0x80u, 0x00u, 0x46u, 0x01u, 0xC6u, 0x00u, 0x00u, \r
- 0x00u, 0x46u, 0x00u, 0x80u, 0x22u, 0x01u, 0x08u, 0x5Eu, 0x08u, 0x39u, 0x21u, 0x06u, 0x01u, 0xC6u, 0x00u, 0x00u, \r
- 0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x77u, 0x00u, 0x08u, 0x40u, 0x42u, 0x00u, 0x00u, 0x10u, 0x04u, 0x00u, 0x20u, \r
- 0x3Fu, 0x80u, 0x00u, 0x70u, 0x40u, 0x0Fu, 0x08u, 0x00u, 0x02u, 0x20u, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x51u, 0x01u, \r
- 0x63u, 0x02u, 0x40u, 0x00u, 0x05u, 0x0Eu, 0xFCu, 0xBDu, 0x3Du, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u, \r
+ /* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */\r
+ static const uint8 CYCODE BS_UDB_1_2_1_CONFIG_VAL[] = {\r
+ 0x01u, 0x80u, 0x00u, 0x00u, 0x07u, 0x00u, 0x18u, 0x9Fu, 0x08u, 0x7Fu, 0x21u, 0x80u, 0x40u, 0x90u, 0x00u, 0x40u, \r
+ 0x40u, 0xC0u, 0x00u, 0x01u, 0x04u, 0x1Fu, 0x00u, 0x20u, 0x10u, 0x00u, 0x00u, 0x60u, 0x01u, 0xC0u, 0x00u, 0x02u, \r
+ 0x01u, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x08u, 0xFFu, 0x01u, 0xC0u, 0x00u, 0x08u, 0x01u, 0xC0u, 0x00u, 0x04u, \r
+ 0x3Fu, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x0Au, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, \r
+ 0x26u, 0x03u, 0x40u, 0x00u, 0x05u, 0x0Bu, 0xFDu, 0xCEu, 0x3Du, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x0Bu, 0x04u, 0x0Bu, 0x0Bu, 0x09u, 0x99u, 0x00u, 0x01u, \r
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), BS_UDB_1_2_0_CONFIG_VAL, 128u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P3_U0_BASE), BS_UDB_1_2_1_CONFIG_VAL, 128u},\r
};\r
\r
uint8 CYDATA i;\r
.include "cydevicegnu.inc"\r
.include "cydevicegnu_trm.inc"\r
\r
+/* Debug_Timer_Interrupt */\r
+.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set Debug_Timer_Interrupt__INTC_MASK, 0x01\r
+.set Debug_Timer_Interrupt__INTC_NUMBER, 0\r
+.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7\r
+.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* Debug_Timer_TimerHW */\r
+.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0\r
+.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1\r
+.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0\r
+.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1\r
+.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2\r
+.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0\r
+.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1\r
+.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0\r
+.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1\r
+.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3\r
+.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01\r
+.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3\r
+.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01\r
+.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0\r
+.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1\r
+.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0\r
+\r
/* USBFS_bus_reset */\r
.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
/* SCSI_CTL_PHASE */\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+\r
+/* SCSI_Out_Bits */\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
\r
/* USBFS_arb_int */\r
.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
+/* SCSI_Out_Ctl */\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+\r
/* SCSI_Out_DBx */\r
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX\r
.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB07_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB07_ST\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB07_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB07_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB07_MSK\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB04_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB04_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB06_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB06_ST\r
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB07_08_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB07_08_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB07_08_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB07_08_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB07_08_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB07_08_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB07_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB07_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB07_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB07_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB07_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB07_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB07_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB07_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB07_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB04_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB04_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1\r
\r
/* USBFS_dp_int */\r
.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SD_Data_Clk__PM_STBY_MSK, 0x01\r
\r
/* SD_Init_Clk */\r
-.set SD_Init_Clk__CFG0, CYREG_CLKDIST_DCFG2_CFG0\r
-.set SD_Init_Clk__CFG1, CYREG_CLKDIST_DCFG2_CFG1\r
-.set SD_Init_Clk__CFG2, CYREG_CLKDIST_DCFG2_CFG2\r
+.set SD_Init_Clk__CFG0, CYREG_CLKDIST_DCFG3_CFG0\r
+.set SD_Init_Clk__CFG1, CYREG_CLKDIST_DCFG3_CFG1\r
+.set SD_Init_Clk__CFG2, CYREG_CLKDIST_DCFG3_CFG2\r
.set SD_Init_Clk__CFG2_SRC_SEL_MASK, 0x07\r
-.set SD_Init_Clk__INDEX, 0x02\r
+.set SD_Init_Clk__INDEX, 0x03\r
.set SD_Init_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
-.set SD_Init_Clk__PM_ACT_MSK, 0x04\r
+.set SD_Init_Clk__PM_ACT_MSK, 0x08\r
.set SD_Init_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
-.set SD_Init_Clk__PM_STBY_MSK, 0x04\r
+.set SD_Init_Clk__PM_STBY_MSK, 0x08\r
+\r
+/* timer_clock */\r
+.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0\r
+.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1\r
+.set timer_clock__CFG2, CYREG_CLKDIST_DCFG2_CFG2\r
+.set timer_clock__CFG2_SRC_SEL_MASK, 0x07\r
+.set timer_clock__INDEX, 0x02\r
+.set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
+.set timer_clock__PM_ACT_MSK, 0x04\r
+.set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
+.set timer_clock__PM_STBY_MSK, 0x04\r
\r
/* scsiTarget */\r
.set scsiTarget_StatusReg__0__MASK, 0x01\r
.set scsiTarget_StatusReg__0__POS, 0\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__3__MASK, 0x08\r
.set scsiTarget_StatusReg__3__POS, 3\r
.set scsiTarget_StatusReg__MASK, 0x0F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK\r
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB03_ST\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB03_CTL\r
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB03_CTL\r
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB03_MSK\r
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB03_04_A0\r
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB03_04_A1\r
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB03_04_D0\r
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB03_04_D1\r
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB03_04_F0\r
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB03_04_F1\r
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB03_A0_A1\r
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB03_A0\r
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB03_A1\r
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB03_D0_D1\r
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB03_D0\r
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB03_D1\r
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB03_F0_F1\r
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB03_F0\r
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB03_F1\r
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB13_MSK\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB13_ST\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST\r
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB12_MSK\r
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB12_ST\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB12_CTL\r
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB12_CTL\r
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB12_MSK\r
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB12_13_A0\r
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB12_13_A1\r
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB12_13_D0\r
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB12_13_D1\r
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB12_13_F0\r
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB12_13_F1\r
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB12_A0_A1\r
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB12_A0\r
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB12_A1\r
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB12_D0_D1\r
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB12_D0\r
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB12_D1\r
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB12_F0_F1\r
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB12_F0\r
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB12_F1\r
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
\r
/* SD_Clk_Ctl */\r
.set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
/* USBFS_ep_1 */\r
.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_1__INTC_MASK, 0x01\r
-.set USBFS_ep_1__INTC_NUMBER, 0\r
+.set USBFS_ep_1__INTC_MASK, 0x02\r
+.set USBFS_ep_1__INTC_NUMBER, 1\r
.set USBFS_ep_1__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_2 */\r
.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_2__INTC_MASK, 0x02\r
-.set USBFS_ep_2__INTC_NUMBER, 1\r
+.set USBFS_ep_2__INTC_MASK, 0x04\r
+.set USBFS_ep_2__INTC_NUMBER, 2\r
.set USBFS_ep_2__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
+/* USBFS_ep_3 */\r
+.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_3__INTC_MASK, 0x08\r
+.set USBFS_ep_3__INTC_NUMBER, 3\r
+.set USBFS_ep_3__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
+.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_4 */\r
+.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_4__INTC_MASK, 0x10\r
+.set USBFS_ep_4__INTC_NUMBER, 4\r
+.set USBFS_ep_4__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
+.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
/* USBFS_USB */\r
.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG\r
.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG\r
.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG\r
.set CYDEV_DMA_CHANNELS_AVAILABLE, 24\r
.set CYDEV_ECC_ENABLE, 0\r
-.set CYDEV_HEAP_SIZE, 0x0256\r
+.set CYDEV_HEAP_SIZE, 0x0400\r
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1\r
-.set CYDEV_INTR_RISING, 0x00000000\r
+.set CYDEV_INTR_RISING, 0x00000001\r
.set CYDEV_PROJ_TYPE, 2\r
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1\r
.set CYDEV_PROJ_TYPE_LOADABLE, 2\r
INCLUDE cydeviceiar.inc\r
INCLUDE cydeviceiar_trm.inc\r
\r
+/* Debug_Timer_Interrupt */\r
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+Debug_Timer_Interrupt__INTC_MASK EQU 0x01\r
+Debug_Timer_Interrupt__INTC_NUMBER EQU 0\r
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* Debug_Timer_TimerHW */\r
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
+\r
/* USBFS_bus_reset */\r
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
/* SCSI_CTL_PHASE */\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+\r
+/* SCSI_Out_Bits */\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
\r
/* USBFS_arb_int */\r
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
+/* SCSI_Out_Ctl */\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+\r
/* SCSI_Out_DBx */\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1\r
\r
/* USBFS_dp_int */\r
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
\r
/* SD_Init_Clk */\r
-SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
-SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
-SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2\r
+SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG3_CFG0\r
+SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG3_CFG1\r
+SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG3_CFG2\r
SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
-SD_Init_Clk__INDEX EQU 0x02\r
+SD_Init_Clk__INDEX EQU 0x03\r
SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SD_Init_Clk__PM_ACT_MSK EQU 0x04\r
+SD_Init_Clk__PM_ACT_MSK EQU 0x08\r
SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SD_Init_Clk__PM_STBY_MSK EQU 0x04\r
+SD_Init_Clk__PM_STBY_MSK EQU 0x08\r
+\r
+/* timer_clock */\r
+timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
+timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
+timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2\r
+timer_clock__CFG2_SRC_SEL_MASK EQU 0x07\r
+timer_clock__INDEX EQU 0x02\r
+timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+timer_clock__PM_ACT_MSK EQU 0x04\r
+timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+timer_clock__PM_STBY_MSK EQU 0x04\r
\r
/* scsiTarget */\r
scsiTarget_StatusReg__0__MASK EQU 0x01\r
scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__3__POS EQU 3\r
scsiTarget_StatusReg__MASK EQU 0x0F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB13_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB13_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB12_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB12_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB12_13_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB12_13_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB12_13_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB12_13_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB12_13_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB12_13_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB12_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB12_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB12_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB12_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB12_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB12_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB12_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB12_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB12_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
\r
/* SD_Clk_Ctl */\r
SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
/* USBFS_ep_1 */\r
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x01\r
-USBFS_ep_1__INTC_NUMBER EQU 0\r
+USBFS_ep_1__INTC_MASK EQU 0x02\r
+USBFS_ep_1__INTC_NUMBER EQU 1\r
USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* USBFS_ep_2 */\r
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x02\r
-USBFS_ep_2__INTC_NUMBER EQU 1\r
+USBFS_ep_2__INTC_MASK EQU 0x04\r
+USBFS_ep_2__INTC_NUMBER EQU 2\r
USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
+/* USBFS_ep_3 */\r
+USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_3__INTC_MASK EQU 0x08\r
+USBFS_ep_3__INTC_NUMBER EQU 3\r
+USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_4 */\r
+USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_4__INTC_MASK EQU 0x10\r
+USBFS_ep_4__INTC_NUMBER EQU 4\r
+USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
/* USBFS_USB */\r
USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG\r
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24\r
CYDEV_ECC_ENABLE EQU 0\r
-CYDEV_HEAP_SIZE EQU 0x0256\r
+CYDEV_HEAP_SIZE EQU 0x0400\r
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x00000000\r
+CYDEV_INTR_RISING EQU 0x00000001\r
CYDEV_PROJ_TYPE EQU 2\r
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
GET cydevicerv.inc\r
GET cydevicerv_trm.inc\r
\r
+; Debug_Timer_Interrupt\r
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+Debug_Timer_Interrupt__INTC_MASK EQU 0x01\r
+Debug_Timer_Interrupt__INTC_NUMBER EQU 0\r
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; Debug_Timer_TimerHW\r
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
+\r
; USBFS_bus_reset\r
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
; SCSI_CTL_PHASE\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+\r
+; SCSI_Out_Bits\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
\r
; USBFS_arb_int\r
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
+; SCSI_Out_Ctl\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+\r
; SCSI_Out_DBx\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1\r
\r
; USBFS_dp_int\r
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
\r
; SD_Init_Clk\r
-SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
-SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
-SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2\r
+SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG3_CFG0\r
+SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG3_CFG1\r
+SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG3_CFG2\r
SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
-SD_Init_Clk__INDEX EQU 0x02\r
+SD_Init_Clk__INDEX EQU 0x03\r
SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SD_Init_Clk__PM_ACT_MSK EQU 0x04\r
+SD_Init_Clk__PM_ACT_MSK EQU 0x08\r
SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SD_Init_Clk__PM_STBY_MSK EQU 0x04\r
+SD_Init_Clk__PM_STBY_MSK EQU 0x08\r
+\r
+; timer_clock\r
+timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
+timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
+timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2\r
+timer_clock__CFG2_SRC_SEL_MASK EQU 0x07\r
+timer_clock__INDEX EQU 0x02\r
+timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+timer_clock__PM_ACT_MSK EQU 0x04\r
+timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+timer_clock__PM_STBY_MSK EQU 0x04\r
\r
; scsiTarget\r
scsiTarget_StatusReg__0__MASK EQU 0x01\r
scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__3__POS EQU 3\r
scsiTarget_StatusReg__MASK EQU 0x0F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB13_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB13_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB12_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB12_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB12_13_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB12_13_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB12_13_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB12_13_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB12_13_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB12_13_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB12_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB12_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB12_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB12_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB12_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB12_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB12_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB12_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB12_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
\r
; SD_Clk_Ctl\r
SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
\r
; USBFS_ep_0\r
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
; USBFS_ep_1\r
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x01\r
-USBFS_ep_1__INTC_NUMBER EQU 0\r
+USBFS_ep_1__INTC_MASK EQU 0x02\r
+USBFS_ep_1__INTC_NUMBER EQU 1\r
USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; USBFS_ep_2\r
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x02\r
-USBFS_ep_2__INTC_NUMBER EQU 1\r
+USBFS_ep_2__INTC_MASK EQU 0x04\r
+USBFS_ep_2__INTC_NUMBER EQU 2\r
USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
+; USBFS_ep_3\r
+USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_3__INTC_MASK EQU 0x08\r
+USBFS_ep_3__INTC_NUMBER EQU 3\r
+USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; USBFS_ep_4\r
+USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_4__INTC_MASK EQU 0x10\r
+USBFS_ep_4__INTC_NUMBER EQU 4\r
+USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
; USBFS_USB\r
USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG\r
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24\r
CYDEV_ECC_ENABLE EQU 0\r
-CYDEV_HEAP_SIZE EQU 0x0256\r
+CYDEV_HEAP_SIZE EQU 0x0400\r
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x00000000\r
+CYDEV_INTR_RISING EQU 0x00000001\r
CYDEV_PROJ_TYPE EQU 2\r
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
#include <USBFS_midi.h>\r
#include <USBFS_pvt.h>\r
#include <Bootloadable_1.h>\r
+#include <SCSI_Out_Bits.h>\r
+#include <SCSI_Out_Ctl.h>\r
+#include <Debug_Timer.h>\r
+#include <timer_clock.h>\r
+#include <Debug_Timer_Interrupt.h>\r
#include <USBFS_Dm_aliases.h>\r
#include <USBFS_Dm.h>\r
#include <USBFS_Dp_aliases.h>\r
--- /dev/null
+/*******************************************************************************
+* File Name: timer_clock.c
+* Version 2.10
+*
+* Description:
+* This file provides the source code to the API for the clock component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include <cydevice_trm.h>
+#include "timer_clock.h"
+
+/* Clock Distribution registers. */
+#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD)
+#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2)
+#define BCFG2_MASK (0x80u)
+#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK)
+#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK)
+
+#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP)
+
+
+/*******************************************************************************
+* Function Name: timer_clock_Start
+********************************************************************************
+*
+* Summary:
+* Starts the clock. Note that on startup, clocks may be already running if the
+* "Start on Reset" option is enabled in the DWR.
+*
+* Parameters:
+* None
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void timer_clock_Start(void)
+{
+ /* Set the bit to enable the clock. */
+ timer_clock_CLKEN |= timer_clock_CLKEN_MASK;
+ timer_clock_CLKSTBY |= timer_clock_CLKSTBY_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: timer_clock_Stop
+********************************************************************************
+*
+* Summary:
+* Stops the clock and returns immediately. This API does not require the
+* source clock to be running but may return before the hardware is actually
+* disabled. If the settings of the clock are changed after calling this
+* function, the clock may glitch when it is started. To avoid the clock
+* glitch, use the StopBlock function.
+*
+* Parameters:
+* None
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void timer_clock_Stop(void)
+{
+ /* Clear the bit to disable the clock. */
+ timer_clock_CLKEN &= (uint8)(~timer_clock_CLKEN_MASK);
+ timer_clock_CLKSTBY &= (uint8)(~timer_clock_CLKSTBY_MASK);
+}
+
+
+#if(CY_PSOC3 || CY_PSOC5LP)
+
+
+/*******************************************************************************
+* Function Name: timer_clock_StopBlock
+********************************************************************************
+*
+* Summary:
+* Stops the clock and waits for the hardware to actually be disabled before
+* returning. This ensures that the clock is never truncated (high part of the
+* cycle will terminate before the clock is disabled and the API returns).
+* Note that the source clock must be running or this API will never return as
+* a stopped clock cannot be disabled.
+*
+* Parameters:
+* None
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void timer_clock_StopBlock(void)
+{
+ if ((timer_clock_CLKEN & timer_clock_CLKEN_MASK) != 0u)
+ {
+#if HAS_CLKDIST_LD_DISABLE
+ uint16 oldDivider;
+
+ CLK_DIST_LD = 0u;
+
+ /* Clear all the mask bits except ours. */
+#if defined(timer_clock__CFG3)
+ CLK_DIST_AMASK = timer_clock_CLKEN_MASK;
+ CLK_DIST_DMASK = 0x00u;
+#else
+ CLK_DIST_DMASK = timer_clock_CLKEN_MASK;
+ CLK_DIST_AMASK = 0x00u;
+#endif /* timer_clock__CFG3 */
+
+ /* Clear mask of bus clock. */
+ CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
+
+ oldDivider = CY_GET_REG16(timer_clock_DIV_PTR);
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
+ CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;
+
+ /* Wait for clock to be disabled */
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+#endif /* HAS_CLKDIST_LD_DISABLE */
+
+ /* Clear the bit to disable the clock. */
+ timer_clock_CLKEN &= (uint8)(~timer_clock_CLKEN_MASK);
+ timer_clock_CLKSTBY &= (uint8)(~timer_clock_CLKSTBY_MASK);
+
+#if HAS_CLKDIST_LD_DISABLE
+ /* Clear the disable bit */
+ CLK_DIST_LD = 0x00u;
+ CY_SET_REG16(timer_clock_DIV_PTR, oldDivider);
+#endif /* HAS_CLKDIST_LD_DISABLE */
+ }
+}
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+
+/*******************************************************************************
+* Function Name: timer_clock_StandbyPower
+********************************************************************************
+*
+* Summary:
+* Sets whether the clock is active in standby mode.
+*
+* Parameters:
+* state: 0 to disable clock during standby, nonzero to enable.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void timer_clock_StandbyPower(uint8 state)
+{
+ if(state == 0u)
+ {
+ timer_clock_CLKSTBY &= (uint8)(~timer_clock_CLKSTBY_MASK);
+ }
+ else
+ {
+ timer_clock_CLKSTBY |= timer_clock_CLKSTBY_MASK;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: timer_clock_SetDividerRegister
+********************************************************************************
+*
+* Summary:
+* Modifies the clock divider and, thus, the frequency. When the clock divider
+* register is set to zero or changed from zero, the clock will be temporarily
+* disabled in order to change the SSS mode bit. If the clock is enabled when
+* SetDividerRegister is called, then the source clock must be running.
+*
+* Parameters:
+* clkDivider: Divider register value (0-65,535). This value is NOT the
+* divider; the clock hardware divides by clkDivider plus one. For example,
+* to divide the clock by 2, this parameter should be set to 1.
+* restart: If nonzero, restarts the clock divider: the current clock cycle
+* will be truncated and the new divide value will take effect immediately. If
+* zero, the new divide value will take effect at the end of the current clock
+* cycle.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void timer_clock_SetDividerRegister(uint16 clkDivider, uint8 restart)
+
+{
+ uint8 enabled;
+
+ uint8 currSrc = timer_clock_GetSourceRegister();
+ uint16 oldDivider = timer_clock_GetDividerRegister();
+
+ if (clkDivider != oldDivider)
+ {
+ enabled = timer_clock_CLKEN & timer_clock_CLKEN_MASK;
+
+ if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))
+ {
+ /* Moving to/from SSS requires correct ordering to prevent halting the clock */
+ if (oldDivider == 0u)
+ {
+ /* Moving away from SSS, set the divider first so when SSS is cleared we */
+ /* don't halt the clock. Using the shadow load isn't required as the */
+ /* divider is ignored while SSS is set. */
+ CY_SET_REG16(timer_clock_DIV_PTR, clkDivider);
+ timer_clock_MOD_SRC &= (uint8)(~CYCLK_SSS);
+ }
+ else
+ {
+ /* Moving to SSS, set SSS which then ignores the divider and we can set */
+ /* it without bothering with the shadow load. */
+ timer_clock_MOD_SRC |= CYCLK_SSS;
+ CY_SET_REG16(timer_clock_DIV_PTR, clkDivider);
+ }
+ }
+ else
+ {
+
+ if (enabled != 0u)
+ {
+ CLK_DIST_LD = 0x00u;
+
+ /* Clear all the mask bits except ours. */
+#if defined(timer_clock__CFG3)
+ CLK_DIST_AMASK = timer_clock_CLKEN_MASK;
+ CLK_DIST_DMASK = 0x00u;
+#else
+ CLK_DIST_DMASK = timer_clock_CLKEN_MASK;
+ CLK_DIST_AMASK = 0x00u;
+#endif /* timer_clock__CFG3 */
+ /* Clear mask of bus clock. */
+ CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
+
+ /* If clock is currently enabled, disable it if async or going from N-to-1*/
+ if (((timer_clock_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))
+ {
+#if HAS_CLKDIST_LD_DISABLE
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
+ CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;
+
+ /* Wait for clock to be disabled */
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+#endif /* HAS_CLKDIST_LD_DISABLE */
+
+ timer_clock_CLKEN &= (uint8)(~timer_clock_CLKEN_MASK);
+
+#if HAS_CLKDIST_LD_DISABLE
+ /* Clear the disable bit */
+ CLK_DIST_LD = 0x00u;
+#endif /* HAS_CLKDIST_LD_DISABLE */
+ }
+ }
+
+ /* Load divide value. */
+ if ((timer_clock_CLKEN & timer_clock_CLKEN_MASK) != 0u)
+ {
+ /* If the clock is still enabled, use the shadow registers */
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);
+
+ CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+ }
+ else
+ {
+ /* If the clock is disabled, set the divider directly */
+ CY_SET_REG16(timer_clock_DIV_PTR, clkDivider);
+ timer_clock_CLKEN |= enabled;
+ }
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: timer_clock_GetDividerRegister
+********************************************************************************
+*
+* Summary:
+* Gets the clock divider register value.
+*
+* Parameters:
+* None
+*
+* Returns:
+* Divide value of the clock minus 1. For example, if the clock is set to
+* divide by 2, the return value will be 1.
+*
+*******************************************************************************/
+uint16 timer_clock_GetDividerRegister(void)
+{
+ return CY_GET_REG16(timer_clock_DIV_PTR);
+}
+
+
+/*******************************************************************************
+* Function Name: timer_clock_SetModeRegister
+********************************************************************************
+*
+* Summary:
+* Sets flags that control the operating mode of the clock. This function only
+* changes flags from 0 to 1; flags that are already 1 will remain unchanged.
+* To clear flags, use the ClearModeRegister function. The clock must be
+* disabled before changing the mode.
+*
+* Parameters:
+* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,
+* clkMode should be a set of the following optional bits or'ed together.
+* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
+* occur when the divider count reaches half of the divide
+* value.
+* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock
+* is asserted for approximately half of its period. When
+* disabled, the output clock is asserted for one period of the
+* source clock.
+* - CYCLK_SYNC Enable output synchronization to master clock. This should
+* be enabled for all synchronous clocks.
+* See the Technical Reference Manual for details about setting the mode of
+* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void timer_clock_SetModeRegister(uint8 modeBitMask)
+{
+ timer_clock_MOD_SRC |= modeBitMask & (uint8)timer_clock_MODE_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: timer_clock_ClearModeRegister
+********************************************************************************
+*
+* Summary:
+* Clears flags that control the operating mode of the clock. This function
+* only changes flags from 1 to 0; flags that are already 0 will remain
+* unchanged. To set flags, use the SetModeRegister function. The clock must be
+* disabled before changing the mode.
+*
+* Parameters:
+* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,
+* clkMode should be a set of the following optional bits or'ed together.
+* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
+* occur when the divider count reaches half of the divide
+* value.
+* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock
+* is asserted for approximately half of its period. When
+* disabled, the output clock is asserted for one period of the
+* source clock.
+* - CYCLK_SYNC Enable output synchronization to master clock. This should
+* be enabled for all synchronous clocks.
+* See the Technical Reference Manual for details about setting the mode of
+* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void timer_clock_ClearModeRegister(uint8 modeBitMask)
+{
+ timer_clock_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(timer_clock_MODE_MASK));
+}
+
+
+/*******************************************************************************
+* Function Name: timer_clock_GetModeRegister
+********************************************************************************
+*
+* Summary:
+* Gets the clock mode register value.
+*
+* Parameters:
+* None
+*
+* Returns:
+* Bit mask representing the enabled mode bits. See the SetModeRegister and
+* ClearModeRegister descriptions for details about the mode bits.
+*
+*******************************************************************************/
+uint8 timer_clock_GetModeRegister(void)
+{
+ return timer_clock_MOD_SRC & (uint8)(timer_clock_MODE_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: timer_clock_SetSourceRegister
+********************************************************************************
+*
+* Summary:
+* Sets the input source of the clock. The clock must be disabled before
+* changing the source. The old and new clock sources must be running.
+*
+* Parameters:
+* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the
+* following input sources:
+* - CYCLK_SRC_SEL_SYNC_DIG
+* - CYCLK_SRC_SEL_IMO
+* - CYCLK_SRC_SEL_XTALM
+* - CYCLK_SRC_SEL_ILO
+* - CYCLK_SRC_SEL_PLL
+* - CYCLK_SRC_SEL_XTALK
+* - CYCLK_SRC_SEL_DSI_G
+* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A
+* See the Technical Reference Manual for details on clock sources.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void timer_clock_SetSourceRegister(uint8 clkSource)
+{
+ uint16 currDiv = timer_clock_GetDividerRegister();
+ uint8 oldSrc = timer_clock_GetSourceRegister();
+
+ if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) &&
+ (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
+ {
+ /* Switching to Master and divider is 1, set SSS, which will output master, */
+ /* then set the source so we are consistent. */
+ timer_clock_MOD_SRC |= CYCLK_SSS;
+ timer_clock_MOD_SRC =
+ (timer_clock_MOD_SRC & (uint8)(~timer_clock_SRC_SEL_MSK)) | clkSource;
+ }
+ else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) &&
+ (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
+ {
+ /* Switching from Master to not and divider is 1, set source, so we don't */
+ /* lock when we clear SSS. */
+ timer_clock_MOD_SRC =
+ (timer_clock_MOD_SRC & (uint8)(~timer_clock_SRC_SEL_MSK)) | clkSource;
+ timer_clock_MOD_SRC &= (uint8)(~CYCLK_SSS);
+ }
+ else
+ {
+ timer_clock_MOD_SRC =
+ (timer_clock_MOD_SRC & (uint8)(~timer_clock_SRC_SEL_MSK)) | clkSource;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: timer_clock_GetSourceRegister
+********************************************************************************
+*
+* Summary:
+* Gets the input source of the clock.
+*
+* Parameters:
+* None
+*
+* Returns:
+* The input source of the clock. See SetSourceRegister for details.
+*
+*******************************************************************************/
+uint8 timer_clock_GetSourceRegister(void)
+{
+ return timer_clock_MOD_SRC & timer_clock_SRC_SEL_MSK;
+}
+
+
+#if defined(timer_clock__CFG3)
+
+
+/*******************************************************************************
+* Function Name: timer_clock_SetPhaseRegister
+********************************************************************************
+*
+* Summary:
+* Sets the phase delay of the analog clock. This function is only available
+* for analog clocks. The clock must be disabled before changing the phase
+* delay to avoid glitches.
+*
+* Parameters:
+* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.
+* clkPhase must be from 1 to 11 inclusive. Other values, including 0,
+* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11
+* produces a 10ns delay.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void timer_clock_SetPhaseRegister(uint8 clkPhase)
+{
+ timer_clock_PHASE = clkPhase & timer_clock_PHASE_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: timer_clock_GetPhase
+********************************************************************************
+*
+* Summary:
+* Gets the phase delay of the analog clock. This function is only available
+* for analog clocks.
+*
+* Parameters:
+* None
+*
+* Returns:
+* Phase of the analog clock. See SetPhaseRegister for details.
+*
+*******************************************************************************/
+uint8 timer_clock_GetPhaseRegister(void)
+{
+ return timer_clock_PHASE & timer_clock_PHASE_MASK;
+}
+
+#endif /* timer_clock__CFG3 */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: timer_clock.h
+* Version 2.10
+*
+* Description:
+* Provides the function and constant definitions for the clock component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CLOCK_timer_clock_H)
+#define CY_CLOCK_timer_clock_H
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+
+/***************************************
+* Conditional Compilation Parameters
+***************************************/
+
+/* Check to see if required defines such as CY_PSOC5LP are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5LP)
+ #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5LP) */
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+void timer_clock_Start(void) ;
+void timer_clock_Stop(void) ;
+
+#if(CY_PSOC3 || CY_PSOC5LP)
+void timer_clock_StopBlock(void) ;
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+void timer_clock_StandbyPower(uint8 state) ;
+void timer_clock_SetDividerRegister(uint16 clkDivider, uint8 restart)
+ ;
+uint16 timer_clock_GetDividerRegister(void) ;
+void timer_clock_SetModeRegister(uint8 modeBitMask) ;
+void timer_clock_ClearModeRegister(uint8 modeBitMask) ;
+uint8 timer_clock_GetModeRegister(void) ;
+void timer_clock_SetSourceRegister(uint8 clkSource) ;
+uint8 timer_clock_GetSourceRegister(void) ;
+#if defined(timer_clock__CFG3)
+void timer_clock_SetPhaseRegister(uint8 clkPhase) ;
+uint8 timer_clock_GetPhaseRegister(void) ;
+#endif /* defined(timer_clock__CFG3) */
+
+#define timer_clock_Enable() timer_clock_Start()
+#define timer_clock_Disable() timer_clock_Stop()
+#define timer_clock_SetDivider(clkDivider) timer_clock_SetDividerRegister(clkDivider, 1u)
+#define timer_clock_SetDividerValue(clkDivider) timer_clock_SetDividerRegister((clkDivider) - 1u, 1u)
+#define timer_clock_SetMode(clkMode) timer_clock_SetModeRegister(clkMode)
+#define timer_clock_SetSource(clkSource) timer_clock_SetSourceRegister(clkSource)
+#if defined(timer_clock__CFG3)
+#define timer_clock_SetPhase(clkPhase) timer_clock_SetPhaseRegister(clkPhase)
+#define timer_clock_SetPhaseValue(clkPhase) timer_clock_SetPhaseRegister((clkPhase) + 1u)
+#endif /* defined(timer_clock__CFG3) */
+
+
+/***************************************
+* Registers
+***************************************/
+
+/* Register to enable or disable the clock */
+#define timer_clock_CLKEN (* (reg8 *) timer_clock__PM_ACT_CFG)
+#define timer_clock_CLKEN_PTR ((reg8 *) timer_clock__PM_ACT_CFG)
+
+/* Register to enable or disable the clock */
+#define timer_clock_CLKSTBY (* (reg8 *) timer_clock__PM_STBY_CFG)
+#define timer_clock_CLKSTBY_PTR ((reg8 *) timer_clock__PM_STBY_CFG)
+
+/* Clock LSB divider configuration register. */
+#define timer_clock_DIV_LSB (* (reg8 *) timer_clock__CFG0)
+#define timer_clock_DIV_LSB_PTR ((reg8 *) timer_clock__CFG0)
+#define timer_clock_DIV_PTR ((reg16 *) timer_clock__CFG0)
+
+/* Clock MSB divider configuration register. */
+#define timer_clock_DIV_MSB (* (reg8 *) timer_clock__CFG1)
+#define timer_clock_DIV_MSB_PTR ((reg8 *) timer_clock__CFG1)
+
+/* Mode and source configuration register */
+#define timer_clock_MOD_SRC (* (reg8 *) timer_clock__CFG2)
+#define timer_clock_MOD_SRC_PTR ((reg8 *) timer_clock__CFG2)
+
+#if defined(timer_clock__CFG3)
+/* Analog clock phase configuration register */
+#define timer_clock_PHASE (* (reg8 *) timer_clock__CFG3)
+#define timer_clock_PHASE_PTR ((reg8 *) timer_clock__CFG3)
+#endif /* defined(timer_clock__CFG3) */
+
+
+/**************************************
+* Register Constants
+**************************************/
+
+/* Power manager register masks */
+#define timer_clock_CLKEN_MASK timer_clock__PM_ACT_MSK
+#define timer_clock_CLKSTBY_MASK timer_clock__PM_STBY_MSK
+
+/* CFG2 field masks */
+#define timer_clock_SRC_SEL_MSK timer_clock__CFG2_SRC_SEL_MASK
+#define timer_clock_MODE_MASK (~(timer_clock_SRC_SEL_MSK))
+
+#if defined(timer_clock__CFG3)
+/* CFG3 phase mask */
+#define timer_clock_PHASE_MASK timer_clock__CFG3_PHASE_DLY_MASK
+#endif /* defined(timer_clock__CFG3) */
+
+#endif /* CY_CLOCK_timer_clock_H */
+
+
+/* [] END OF FILE */
<?xml version="1.0" encoding="utf-8"?>\r
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
- <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ </block>\r
<block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">\r
<block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0">\r
<field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />\r
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />\r
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />\r
</block>\r
- <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG">\r
+ <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />\r
+ </register>\r
+ <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0">\r
+ <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />\r
+ <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">\r
+ <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />\r
+ <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />\r
+ </field>\r
+ <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />\r
+ <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />\r
+ <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />\r
+ <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">\r
+ <value name="Timer" value="0" desc="CMP and TC are output." />\r
+ <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />\r
+ </field>\r
+ <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />\r
+ </register>\r
+ <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1">\r
+ <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />\r
+ <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">\r
+ <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />\r
+ <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />\r
+ </field>\r
+ <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />\r
+ <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />\r
+ <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />\r
+ <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />\r
+ </register>\r
+ <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2">\r
+ <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">\r
+ <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />\r
+ <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />\r
+ <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />\r
+ <value name="Irq" value="11" desc="Timer runs until IRQ." />\r
+ </field>\r
+ <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />\r
+ <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />\r
+ <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">\r
+ <value name="Equal" value="0" desc="Compare Equal " />\r
+ <value name="Less than" value="1" desc="Compare Less Than " />\r
+ <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />\r
+ <value name="Greater" value="11" desc="Compare Greater Than ." />\r
+ <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />\r
+ </field>\r
+ <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />\r
+ </register>\r
+ <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />\r
+ <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />\r
+ </block>\r
+ <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" />\r
+ </block>\r
+ <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006470" bitWidth="8" desc="" />\r
</block>\r
- <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_Init_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SD_Clk_Ctl_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />\r
+ <register name="SD_Clk_Ctl_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />\r
</block>\r
- <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />\r
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" />\r
</block>\r
+ <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
</blockRegMap>
\ No newline at end of file
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<filters />\r
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Out_Bits" persistent="">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
+<dependencies>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Out_Bits.c" persistent=".\Generated_Source\PSoC5\SCSI_Out_Bits.c">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="ARM_C_FILE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Out_Bits.h" persistent=".\Generated_Source\PSoC5\SCSI_Out_Bits.h">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="NONE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
+</dependencies>\r
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
+<filters />\r
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Out_Ctl" persistent="">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
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</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
</name>\r
</platform>\r
</platforms>\r
-<project_current_platform v="c9323d49-d323-40b8-9b59-cc008d68a989" />\r
+<project_current_platform v="b98f980c-3bd1-4fc7-a887-c56a20a46fdd" />\r
<project_current_processor v="CortexM3" />\r
<component_generation v="PSoC Creator 2.2 Component Pack 6" />\r
<last_selected_tab v="Cypress" />\r
</CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>\r
<boot_component v="cy_boot_v4_0" />\r
<BootloaderTag hexFile="" elfFile="" />\r
-<current_generation v="2" />\r
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</CyXmlSerializer>
\ No newline at end of file
</register>\r
</registers>\r
</peripheral>\r
+ <peripheral>\r
+ <name>Debug_Timer</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x400043A3</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0xB64</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>Debug_Timer_GLOBAL_ENABLE</name>\r
+ <description>PM.ACT.CFG</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>en_timer</name>\r
+ <description>Enable timer/counters.</description>\r
+ <lsb>0</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>Debug_Timer_CONTROL</name>\r
+ <description>TMRx.CFG0</description>\r
+ <addressOffset>0xB5D</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>EN</name>\r
+ <description>Enables timer/comparator.</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>MODE</name>\r
+ <description>Mode. (0 = Timer; 1 = Comparator)</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Timer</name>\r
+ <description>Timer mode. CNT/CMP register holds timer count value.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Comparator</name>\r
+ <description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>ONESHOT</name>\r
+ <description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>CMP_BUFF</name>\r
+ <description>Buffer compare register. Compare register updates only on timer terminal count.</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>INV</name>\r
+ <description>Invert sense of TIMEREN signal</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DB</name>\r
+ <description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Timer</name>\r
+ <description>CMP and TC are output.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Deadband</name>\r
+ <description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>DEADBAND_PERIOD</name>\r
+ <description>Deadband Period</description>\r
+ <lsb>6</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>Debug_Timer_CONTROL2</name>\r
+ <description>TMRx.CFG1</description>\r
+ <addressOffset>0xB5E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>IRQ_SEL</name>\r
+ <description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>FTC</name>\r
+ <description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Disable_FTC</name>\r
+ <description>Disable the single cycle pulse, which signifies the timer is starting.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Enable_FTC</name>\r
+ <description>Enable the single cycle pulse, which signifies the timer is starting.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>DCOR</name>\r
+ <description>Disable Clear on Read (DCOR) of Status Register SR0.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>DBMODE</name>\r
+ <description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>CLK_BUS_EN_SEL</name>\r
+ <description>Digital Global Clock selection.</description>\r
+ <lsb>4</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>BUS_CLK_SEL</name>\r
+ <description>Bus Clock selection.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>Debug_Timer_CONTROL3_</name>\r
+ <description>TMRx.CFG2</description>\r
+ <addressOffset>0xB5F</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>TMR_CFG</name>\r
+ <description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>\r
+ <lsb>0</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Continuous</name>\r
+ <description>Timer runs while EN bit of CFG0 register is set to '1'.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Pulsewidth</name>\r
+ <description>Timer runs from positive to negative edge of TIMEREN.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Period</name>\r
+ <description>Timer runs from positive to positive edge of TIMEREN.</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Irq</name>\r
+ <description>Timer runs until IRQ.</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>COD</name>\r
+ <description>Clear On Disable (COD). Clears or gates outputs to zero.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ROD</name>\r
+ <description>Reset On Disable (ROD). Resets internal state of output logic</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>CMP_CFG</name>\r
+ <description>Comparator configurations</description>\r
+ <lsb>4</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Equal</name>\r
+ <description>Compare Equal </description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Less_than</name>\r
+ <description>Compare Less Than </description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Less_than_or_equal</name>\r
+ <description>Compare Less Than or Equal .</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Greater</name>\r
+ <description>Compare Greater Than .</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Greater_than_or_equal</name>\r
+ <description>Compare Greater Than or Equal </description>\r
+ <value>4</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>HW_EN</name>\r
+ <description>When set Timer Enable controls counting.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ <register>\r
+ <name>Debug_Timer_PERIOD</name>\r
+ <description>TMRx.PER0 - Assigned Period</description>\r
+ <addressOffset>0xB61</addressOffset>\r
+ <size>16</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>Debug_Timer_COUNTER</name>\r
+ <description>TMRx.CNT_CMP0 - Current Down Counter Value</description>\r
+ <addressOffset>0xB63</addressOffset>\r
+ <size>16</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
+ <peripheral>\r
+ <name>SCSI_Out_Ctl</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x40006473</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x1</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_Out_Ctl_CONTROL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
+ <peripheral>\r
+ <name>SCSI_Out_Bits</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x40006470</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x1</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_Out_Bits_CONTROL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
<peripheral>\r
<name>SD_Clk_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006471</baseAddress>\r
+ <baseAddress>0x40006472</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x1</size>\r
<peripheral>\r
<name>SCSI_CTL_PHASE</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006472</baseAddress>\r
+ <baseAddress>0x40006475</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x1</size>\r
enum USB_ENDPOINTS\r
{\r
USB_EP_OUT = 1,\r
- USB_EP_IN = 2\r
+ USB_EP_IN = 2,\r
+ USB_EP_DEBUG = 4\r
};\r
enum USB_STATE\r
{\r
USB_DATA_SENT\r
};\r
int usbInEpState;\r
+int usbDebugEpState;\r
+uint8_t debugBuffer[64];\r
\r
int usbReady;\r
\r
// The PSoC must be operating between 4.6V and 5V for the regulator\r
// to work.\r
USBFS_Start(0, USBFS_5V_OPERATION);\r
- usbInEpState = USB_IDLE;\r
+ usbInEpState = usbDebugEpState = USB_IDLE;\r
usbReady = 0; // We don't know if host is connected yet.\r
}\r
\r
if (reset)\r
{\r
USBFS_EnableOutEP(USB_EP_OUT);\r
- usbInEpState = USB_IDLE;\r
+ usbInEpState = usbDebugEpState = USB_IDLE;\r
}\r
\r
if(USBFS_GetEPState(USB_EP_OUT) == USBFS_OUT_BUFFER_FULL)\r
shadow.maxSectors = htonl(shadow.maxSectors);\r
shadow.bytesPerSector = htons(shadow.bytesPerSector);\r
\r
- #ifdef MM_DEBUG\r
- memcpy(&shadow.reserved, &scsiDev.cdb, 12);\r
- shadow.reserved[12] = scsiDev.msgIn;\r
- shadow.reserved[13] = scsiDev.msgOut;\r
- shadow.reserved[14] = scsiDev.lastStatus;\r
- shadow.reserved[15] = scsiDev.lastSense;\r
- shadow.reserved[16] = scsiDev.phase;\r
- shadow.reserved[17] = SCSI_ReadPin(SCSI_In_BSY);\r
- shadow.reserved[18] = SCSI_ReadPin(SCSI_In_SEL);\r
- shadow.reserved[19] = SCSI_ReadPin(SCSI_ATN_INT);\r
- shadow.reserved[20] = SCSI_ReadPin(SCSI_RST_INT);\r
- shadow.reserved[21] = scsiDev.rstCount;\r
- shadow.reserved[22] = scsiDev.selCount;\r
- shadow.reserved[23] = scsiDev.msgCount;\r
- shadow.reserved[24] = scsiDev.cmdCount;\r
- shadow.reserved[25] = scsiDev.watchdogTick;\r
- #endif\r
-\r
USBFS_LoadInEP(USB_EP_IN, (uint8 *)&shadow, sizeof(shadow));\r
shadow.maxSectors = ntohl(shadow.maxSectors);\r
shadow.bytesPerSector = ntohs(shadow.bytesPerSector);\r
}\r
}\r
\r
+void debugPoll()\r
+{\r
+ if (!usbReady)\r
+ {\r
+ return;\r
+ }\r
+ \r
+ switch (usbDebugEpState)\r
+ {\r
+ case USB_IDLE:\r
+ memcpy(&debugBuffer, &scsiDev.cdb, 12);\r
+ debugBuffer[12] = scsiDev.msgIn;\r
+ debugBuffer[13] = scsiDev.msgOut;\r
+ debugBuffer[14] = scsiDev.lastStatus;\r
+ debugBuffer[15] = scsiDev.lastSense;\r
+ debugBuffer[16] = scsiDev.phase;\r
+ debugBuffer[17] = SCSI_ReadPin(SCSI_In_BSY);\r
+ debugBuffer[18] = SCSI_ReadPin(SCSI_In_SEL);\r
+ debugBuffer[19] = SCSI_ReadPin(SCSI_ATN_INT);\r
+ debugBuffer[20] = SCSI_ReadPin(SCSI_RST_INT);\r
+ debugBuffer[21] = scsiDev.rstCount;\r
+ debugBuffer[22] = scsiDev.selCount;\r
+ debugBuffer[23] = scsiDev.msgCount;\r
+ debugBuffer[24] = scsiDev.cmdCount;\r
+ debugBuffer[25] = scsiDev.watchdogTick;\r
+\r
+ USBFS_LoadInEP(USB_EP_DEBUG, (uint8 *)&debugBuffer, sizeof(debugBuffer));\r
+ usbDebugEpState = USB_DATA_SENT;\r
+ break;\r
+\r
+ case USB_DATA_SENT:\r
+ if (USBFS_bGetEPAckState(USB_EP_DEBUG))\r
+ {\r
+ // Data accepted.\r
+ usbDebugEpState = USB_IDLE;\r
+ }\r
+ break;\r
+ }\r
+}\r
+\r
+CY_ISR(debugTimerISR)\r
+{\r
+ Debug_Timer_ReadStatusRegister();\r
+ Debug_Timer_Interrupt_ClearPending();\r
+ uint8 savedIntrStatus = CyEnterCriticalSection();\r
+ debugPoll();\r
+ CyExitCriticalSection(savedIntrStatus); \r
+}\r
+\r
+void debugInit()\r
+{\r
+#ifdef MM_DEBUG\r
+ Debug_Timer_Interrupt_StartEx(debugTimerISR);\r
+ Debug_Timer_Start();\r
+#else\r
+ Debug_Timer_Interrupt_Stop();\r
+ Debug_Timer_Stop();\r
+#endif\r
+ \r
+}\r
+\r
// Public method for storing MODE SELECT results.\r
void configSave()\r
{\r
extern Config* config;\r
\r
void configInit(void);\r
+void debugInit(void);\r
void configPoll(void);\r
void configSave(void);\r
\r
// No need for single-block writes atm. Overhead of the\r
// multi-block write is minimal.\r
transfer.multiBlock = 1;\r
+ \r
+ if (blocks > 1) scsiDev.needReconnect = 1;\r
sdPrepareWrite();\r
}\r
}\r
else\r
{\r
transfer.multiBlock = 1;\r
+ scsiDev.needReconnect = 1;\r
sdPrepareRead();\r
}\r
}\r
scsiPhyInit();\r
\r
configInit();\r
+ debugInit();\r
\r
scsiInit();\r
scsiDiskInit();\r
#endif\r
}\r
\r
+static void doReselectTest()\r
+{\r
+ scsiDev.needReconnect = 0;\r
+ scsiEnterPhase(MESSAGE_IN);\r
+ scsiWriteByte(0x02); // save data pointer\r
+\r
+ // TODO check if this message was rejected.\r
+\r
+ scsiWriteByte(0x04); // disconnect msg.\r
+ enter_BusFree();\r
+ \r
+ CyDelay(100);\r
+\r
+ while (1)\r
+ {\r
+ int sel = SCSI_ReadPin(SCSI_In_SEL);\r
+ int bsy = SCSI_ReadPin(SCSI_In_BSY);\r
+ if (!sel && !bsy)\r
+ {\r
+ // TODO wait bus settle delay\r
+ CyDelayUs(1); // TODO bus free delay 800ns\r
+ \r
+ // Arbitrate.\r
+ ledOn();\r
+ SCSI_Out_Bits_Write(scsiDev.scsiIdMask);\r
+ SCSI_Out_Ctl_Write(1); // Write bits manually.\r
+ SCSI_SetPin(SCSI_Out_BSY);\r
+ \r
+ CyDelayUs(3); // arbitrate delay. 2.4us.\r
+ \r
+ uint8_t dbx = scsiReadDBxPins();\r
+ sel = SCSI_ReadPin(SCSI_In_SEL);\r
+ if (sel || ((dbx ^ scsiDev.scsiIdMask) > scsiDev.scsiIdMask))\r
+ {\r
+ // Lost arbitration.\r
+ SCSI_Out_Ctl_Write(0);\r
+ SCSI_ClearPin(SCSI_Out_BSY);\r
+ ledOff();\r
+ }\r
+ else\r
+ {\r
+ // Won arbitration \r
+ SCSI_SetPin(SCSI_Out_SEL);\r
+ CyDelayUs(1); // Bus clear + Bus settle.\r
+\r
+ // Reselection phase\r
+ scsiEnterPhase(__scsiphase_io); // TODO get rid of delay\r
+ SCSI_Out_Bits_Write(scsiDev.scsiIdMask | (1 << scsiDev.initiatorId));\r
+ CyDelayCycles(4); // 2 deskew delays\r
+ SCSI_ClearPin(SCSI_Out_BSY);\r
+ CyDelayUs(1); // Bus Settle Delay\r
+\r
+ bsy = SCSI_ReadPin(SCSI_In_BSY);\r
+ while (!bsy) { bsy = SCSI_ReadPin(SCSI_In_BSY); } // Wait for initiator.\r
+ SCSI_SetPin(SCSI_Out_BSY);\r
+\r
+ // Prepare for the initial IDENTIFY message.\r
+ scsiEnterPhase(MESSAGE_IN);\r
+\r
+ SCSI_Out_Ctl_Write(0);\r
+ SCSI_ClearPin(SCSI_Out_SEL);\r
+\r
+ // Send identify command\r
+ scsiWriteByte(0x80);\r
+ break;\r
+ }\r
+ }\r
+\r
+ }\r
+\r
+ // Continue with status.\r
+ \r
+}\r
+\r
static void process_Status()\r
{\r
+ if (scsiDev.status == GOOD && scsiDev.needReconnect && scsiDev.allowDisconnect)\r
+ {\r
+ // doReselectTest();\r
+ }\r
scsiEnterPhase(STATUS);\r
\r
uint8 message;\r
ledOff();\r
\r
scsiPhyReset();\r
+ SCSI_Out_Ctl_Write(0);\r
\r
scsiDev.parityError = 0;\r
scsiDev.phase = BUS_FREE;\r
scsiDev.atnFlag = 0;\r
scsiDev.resetFlag = 0;\r
+ scsiDev.needReconnect = 0;\r
\r
if (scsiDev.unitAttention != POWER_ON_RESET)\r
{\r
scsiDev.dataLen = 0;\r
scsiDev.status = GOOD;\r
scsiDev.phase = SELECTION;\r
+ scsiDev.needReconnect = 0;\r
+ scsiDev.allowDisconnect = 0;\r
\r
transfer.blocks = 0;\r
transfer.currentBlock = 0;\r
(scsiDev.msgOut & 0x7) // We only support LUN 0!\r
)\r
{\r
+ //scsiDev.sense.code = ILLEGAL_REQUEST;\r
+ //scsiDev.sense.asc = INVALID_BITS_IN_IDENTIFY_MESSAGE;\r
+ //enter_Status(CHECK_CONDITION);\r
messageReject();\r
}\r
+ scsiDev.allowDisconnect = scsiDev.msgOut & 0x40;\r
}\r
else if (scsiDev.msgOut >= 0x20 && scsiDev.msgOut <= 0x2F)\r
{\r
} SCSI_MESSAGE;
// Maximum value for bytes-per-sector.
-#define MAX_SECTOR_SIZE 2048
+#define MAX_SECTOR_SIZE 8192
#define MIN_SECTOR_SIZE 64
typedef struct
uint8 lastStatus;
uint8 lastSense;
#endif
+
+uint8 allowDisconnect;
+uint8 needReconnect;
} ScsiDevice;
extern ScsiDevice scsiDev;
CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO\r
CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO\r
CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO\r
-\r
+ \r
i = 0;\r
guard = 0;\r
-\r
+ \r
// This loop is critically important for performance.\r
// We stream data straight from the SDCard fifos into the SCSI component\r
// FIFO's. If the loop isn't fast enough, the transmit FIFO's will empty,\r
// Read from the SPIM fifo if there is room to stream the byte to the\r
// SCSI fifos\r
if((sdRxStatus & SDCard_STS_RX_FIFO_NOT_EMPTY) &&\r
- (scsiDev.resetFlag || (scsiStatus & 1)) // SCSI TX FIFO NOT FULL\r
+ (scsiStatus & 1) // SCSI TX FIFO NOT FULL\r
)\r
{\r
uint8_t val = CY_GET_REG8(SDCard_RXDATA_PTR);\r
CY_SET_REG8(scsiTarget_datapath__F0_REG, val);\r
guard++;\r
- }\r
\r
+ // How many bytes are in a 4-byte FIFO ? 5. 4 FIFO bytes PLUS one byte\r
+ // being processed bit-by-bit. Artifically limit the number of bytes in the \r
+ // "combined" SPIM TX and RX FIFOS to the individual FIFO size.\r
+ // Unlike the SCSI component, SPIM doesn't check if there's room in\r
+ // the output FIFO before starting to transmit.\r
+\r
+ if (prep < numBytes)\r
+ {\r
+ CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO\r
+ prep++;\r
+ }\r
+\r
+ }\r
+ \r
// Byte has been sent out the SCSI interface.\r
- if (scsiDev.resetFlag || (scsiStatus & 2)) // SCSI RX FIFO NOT EMPTY\r
+ if (scsiStatus & 2) // SCSI RX FIFO NOT EMPTY\r
{\r
CY_GET_REG8(scsiTarget_datapath__F1_REG);\r
++i;\r
}\r
-\r
- // How many bytes are in a 4-byte FIFO ? 5. 4 FIFO bytes PLUS one byte\r
- // being processed bit-by-bit. Artifically limit the number of bytes in the \r
- // "combined" SPIM TX and RX FIFOS to the individual FIFO size.\r
- // Unlike the SCSI component, SPIM doesn't check if there's room in\r
- // the output FIFO before starting to transmit.\r
- if ((prep - guard < 4) && (prep < numBytes))\r
- {\r
- CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO\r
- prep++;\r
- }\r
}\r
\r
- // Read and discard remaining bytes.\r
- while (i < SD_SECTOR_SIZE)\r
+ // Read and discard remaining bytes. This applis for non-512 byte sectors,\r
+ // or if a SCSI reset was triggered.\r
+ while (guard < SD_SECTOR_SIZE)\r
{\r
uint8_t sdRxStatus = CY_GET_REG8(SDCard_RX_STATUS_PTR);\r
if(sdRxStatus & SDCard_STS_RX_FIFO_NOT_EMPTY)\r
{\r
CY_GET_REG8(SDCard_RXDATA_PTR);\r
guard++;\r
- i++;\r
}\r
\r
if ((prep - guard < 4) && (prep < SD_SECTOR_SIZE))\r
{\r
uint8_t sdRxStatus = CY_GET_REG8(SDCard_RX_STATUS_PTR);\r
\r
- if(guard - i < 4)\r
+ if((guard - i < 4) && (guard < SD_SECTOR_SIZE))\r
{\r
CY_SET_REG8(SDCard_TXDATA_PTR, 0x00);\r
guard++;\r
printf("\t\trequired by the SCSI-2 standard.\n\n");
printf("--no-attention\tDisable Unit Attention responses.\n\n");
printf("--blocks={0-4294967295}\n\t\tSet a limit to the reported device size.\n");
- printf("\t\tEach block is 512 bytes. The maximum possible size is 2TB.\n");
+ printf("\t\tThe size of each block/sector is set by the --sector parameter.\n");
printf("\t\tThe reported size will be the lower of this value and the SD\n");
- printf("\t\tcard size. 0 disables the limit.\n\n");
- printf("--sector={64-2048}\n\t\tSet the bytes-per-sector. Normally 512 bytes.\n");
+ printf("\t\tcard size. 0 disables the limit.\n");
+ printf("\t\tThe maximum possible size is 2TB.\n\n");
+ printf("--sector={64-8192}\n\t\tSet the bytes-per-sector. Normally 512 bytes.\n");
printf("\t\tCan also be set with a SCSI MODE SELECT command.\n\n");
printf("--apple\t\tSet the vendor, product ID and revision fields to simulate an \n");
printf("\t\tapple-suppled disk. Provides support for the Apple Drive Setup\n");
{
int64_t bytesPerSector = -1;
if (sscanf(optarg, "%" PRId64, &bytesPerSector) == 1 &&
- bytesPerSector >= 64 && bytesPerSector <= 2048)
+ bytesPerSector >= 64 && bytesPerSector <= 8192)
{
packet.bytesPerSector = bytesPerSector;
}
--- /dev/null
+all: build/scsi2sd-debug
+
+CFLAGS += -Wall
+
+UNAME_S := $(shell uname -s)
+ifeq ($(UNAME_S),Linux)
+ HID_C = ../bootloaderhost/hidapi/linux/hid.c
+ LDFLAGS += -ludev
+endif
+ifeq ($(UNAME_S),Darwin)
+ # Should match OSX
+ HID_C = ../bootloaderhost/hidapi/mac/hid.c
+ LDFLAGS += -framework IOKit -framework CoreFoundation
+ CFLAGS += -mmacosx-version-min=10.5 -arch x86_64 -arch i386 -arch ppc -isysroot /Xcode3.1.4/SDKs/MacOSX10.5.sdk
+ CC=/Xcode3.1.4/usr/bin/gcc
+endif
+
+
+build/scsi2sd-debug: main.c $(HID_C) $(CYAPI)
+ mkdir -p $(dir $@)
+ $(CC) $(CFLAGS) -I ../bootloaderhost/hidapi/hidapi $^ $(LDFLAGS) -o $@
+
+clean:
+ rm build/scsi2sd-debug
--- /dev/null
+all: build/windows/32bit/scsi2sd-debug.exe build/windows/64bit/scsi2sd-debug.exe
+
+CFLAGS += -Wall
+LDFLAGS=-mconsole -mwindows -lsetupapi -lws2_32
+
+HID_C = ../bootloaderhost/hidapi/windows/hid.c
+
+
+build/windows/32bit/scsi2sd-debug.exe: main.c $(HID_C)
+ mkdir -p $(dir $@)
+ i686-w64-mingw32-gcc $(CFLAGS) -I ../bootloaderhost/hidapi/hidapi $^ $(LDFLAGS) -o $@
+
+build/windows/64bit/scsi2sd-debug.exe: main.c $(HID_C)
+ mkdir -p $(dir $@)
+ x86_64-w64-mingw32-gcc $(CFLAGS) -I ../bootloaderhost/hidapi/hidapi $^ $(LDFLAGS) -o $@
+
+clean:
+ rm -r build/windows
+
--- /dev/null
+// Copyright (C) 2014 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+
+#include <getopt.h>
+#include <inttypes.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+// htonl/ntohl includes.
+#ifdef WIN32
+#include <winsock2.h>
+#else
+#include <arpa/inet.h>
+#endif
+
+#include "hidapi.h"
+
+#define MIN(a,b) (a < b ? a : b)
+
+FILE* logfile = NULL;
+
+static void readConfig(hid_device* handle)
+{
+ // First byte is the report ID (0)
+ unsigned char buf[65];
+ memset(buf, 0, sizeof(buf));
+ int result = hid_read(handle, buf, sizeof(buf));
+
+ if (result < 0)
+ {
+ fprintf(stderr, "USB HID Read Failure: %ls\n", hid_error(handle));
+ }
+ int i;
+ for (i = 0; i < 32; ++i)
+ {
+ fprintf(logfile, "%02x ", buf[i]);
+ }
+ fprintf(logfile, "\n");
+ fflush(logfile);
+}
+
+static void usage()
+{
+ printf("Usage: scsi2sd-debug outputfile\n");
+ printf("\n");
+ printf("outputfile\tPath to the output log file.\n\n");
+ printf("\n\n");
+ exit(1);
+}
+
+
+int main(int argc, char* argv[])
+{
+ printf("SCSI2SD Debug Utility.\n");
+ printf("Copyright (C) 2014 Michael McMaster <michael@codesrc.com>\n\n");
+
+ if (argc != 2)
+ {
+ usage();
+ exit(1);
+ }
+
+ logfile = fopen(argv[1], "w");
+ if (!logfile)
+ {
+ fprintf(stderr, "Could not write to file %s.\n", argv[1]);
+ exit(1);
+ }
+
+
+ uint16_t vendorId = 0x04B4; // Cypress
+ uint16_t productId = 0x1337; // SCSI2SD
+
+ printf(
+ "USB device parameters\n\tVendor ID:\t0x%04X\n\tProduct ID:\t0x%04X\n",
+ vendorId,
+ productId);
+
+ // Enumerate and print the HID devices on the system
+ struct hid_device_info *dev = hid_enumerate(vendorId, productId);
+
+ // We need the SECOND interface for debug data
+ if (!dev)
+ {
+ fprintf(stderr, "ERROR: SCSI2SD USB device not found.\n");
+ exit(1);
+ }
+ else if (!dev->next)
+ {
+ fprintf(stderr, "ERROR: SCSI2SD Debug firmware not enabled.\n");
+ exit(1);
+ }
+ dev = dev->next;
+
+ printf("USB Device Found\n type: %04hx %04hx\n path: %s\n serial_number: %ls",
+ dev->vendor_id, dev->product_id, dev->path, dev->serial_number);
+ printf("\n");
+ printf(" Manufacturer: %ls\n", dev->manufacturer_string);
+ printf(" Product: %ls\n", dev->product_string);
+ printf("\n");
+
+ hid_device* handle = hid_open_path(dev->path);
+ if (!handle)
+ {
+ fprintf(
+ stderr,
+ "ERROR: Could not open device %s. Check permissions.\n", dev->path
+ );
+ exit(1);
+ }
+
+
+ while (1)
+ {
+ readConfig(handle);
+ }
+
+ return 0;
+}
+
projects / SCSI2SD-V6.git / commitdiff