- USB bootloader is not implemented yet.
-- Configuration options are not yet loaded from EEPROM.
- Configuration options cannot be set via USB.
- SCSI ID hardcoded to 0
- Partity checking is on
- Unit Attention Condition is off
+ - SPI overclock to 32MHz off.
- DMA is not used for SPI transfers
+- Parity checking not implemented for the PSoC Datapath implementation
--- /dev/null
+/*******************************************************************************\r
+* File Name: CFG_EEPROM.c\r
+* Version 2.10\r
+*\r
+* Description:\r
+* Provides the source code to the API for the EEPROM component.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "CFG_EEPROM.h"\r
+\r
+\r
+#if (CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CFG_EEPROM_Enable\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Enable the EEPROM.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CFG_EEPROM_Enable(void) \r
+ {\r
+ CyEEPROM_Start();\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CFG_EEPROM_Start\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Starts EEPROM.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CFG_EEPROM_Start(void) \r
+ {\r
+ /* Enable the EEPROM */\r
+ CFG_EEPROM_Enable();\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CFG_EEPROM_Stop\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Stops and powers down EEPROM.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CFG_EEPROM_Stop (void) \r
+ {\r
+ /* Disable EEPROM */\r
+ CyEEPROM_Stop();\r
+ }\r
+\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CFG_EEPROM_EraseSector\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Erases a sector of memory. This function blocks until the operation is\r
+* complete.\r
+*\r
+* Parameters:\r
+* sectorNumber: Sector number to erase.\r
+*\r
+* Return:\r
+* CYRET_SUCCESS, if the operation was successful.\r
+* CYRET_BAD_PARAM, if the parameter sectorNumber out of range.\r
+* CYRET_LOCKED, if the spc is being used.\r
+* CYRET_UNKNOWN, if there was an SPC error.\r
+*\r
+*******************************************************************************/\r
+cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) \r
+{\r
+ cystatus status;\r
+\r
+ /* Start the SPC */\r
+ CySpcStart();\r
+\r
+ if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS)\r
+ {\r
+ /* See if we can get the SPC. */\r
+ if(CySpcLock() == CYRET_SUCCESS)\r
+ {\r
+ #if(CY_PSOC5A)\r
+\r
+ /* Plan for failure */\r
+ status = CYRET_UNKNOWN;\r
+\r
+ /* Command to load a row of data */\r
+ if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, 0, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)\r
+ {\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Wait until SPC becomes idle */\r
+ }\r
+\r
+ /* SPC is idle now */\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ }\r
+\r
+ /* Command to erase a sector */\r
+ if(status == CYRET_SUCCESS)\r
+ {\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+ if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED)\r
+ {\r
+ /* Plan for failure */\r
+ status = CYRET_UNKNOWN;\r
+\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Wait until SPC becomes idle */\r
+ }\r
+\r
+ /* SPC is idle now */\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
+\r
+ #if(CY_PSOC5A)\r
+\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+ /* Unlock the SPC so someone else can use it. */\r
+ CySpcUnlock();\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CFG_EEPROM_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Writes a row, CYDEV_EEPROM_ROW_SIZE of data to the EEPROM. This is\r
+* a blocking call. It will not return until the function succeeds or fails.\r
+*\r
+* Parameters:\r
+* rowData: Address of the data to write to the EEPROM.\r
+* rowNumber: EEPROM row number to program.\r
+*\r
+* Return:\r
+* CYRET_SUCCESS, if the operation was successful.\r
+* CYRET_BAD_PARAM, if the parameter rowNumber out of range.\r
+* CYRET_LOCKED, if the spc is being used.\r
+* CYRET_UNKNOWN, if there was an SPC error.\r
+*\r
+*******************************************************************************/\r
+cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) \r
+{\r
+ cystatus status;\r
+\r
+ /* Start the SPC */\r
+ CySpcStart();\r
+\r
+ if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)\r
+ {\r
+ /* See if we can get the SPC. */\r
+ if(CySpcLock() == CYRET_SUCCESS)\r
+ {\r
+ /* Plan for failure */\r
+ status = CYRET_UNKNOWN;\r
+\r
+ /* Command to load a row of data */\r
+ if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)\r
+ {\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Wait until SPC becomes idle */\r
+ }\r
+\r
+ /* SPC is idle now */\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ /* Command to erase and program the row. */\r
+ if(status == CYRET_SUCCESS)\r
+ {\r
+ if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],\r
+ dieTemperature[1]) == CYRET_STARTED)\r
+ {\r
+ /* Plan for failure */\r
+ status = CYRET_UNKNOWN;\r
+\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Wait until SPC becomes idle */\r
+ }\r
+\r
+ /* SPC is idle now */\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
+ }\r
+\r
+ /* Unlock the SPC so someone else can use it. */\r
+ CySpcUnlock();\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CFG_EEPROM_StartWrite\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Starts the SPC write function. This function does not block, it returns\r
+* once the command has begun the SPC write function. This function must be used\r
+* in combination with CFG_EEPROM_QueryWrite(). Once this function has\r
+* been called the SPC will be locked until CFG_EEPROM_QueryWrite()\r
+* returns CYRET_SUCCESS.\r
+*\r
+* Parameters:\r
+* rowData: Address of buffer containing a row of data to write to the EEPROM.\r
+* rowNumber: EEPROM row number to program.\r
+*\r
+* Return:\r
+* CYRET_STARTED, if the spc command to write was successfuly started.\r
+* CYRET_BAD_PARAM, if the parameter rowNumber out of range.\r
+* CYRET_LOCKED, if the spc is being used.\r
+* CYRET_UNKNOWN, if there was an SPC error.\r
+*\r
+*******************************************************************************/\r
+cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \\r
+\r
+{\r
+ cystatus status;\r
+\r
+ if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS)\r
+ {\r
+ /* See if we can get the SPC. */\r
+ if(CySpcLock() == CYRET_SUCCESS)\r
+ {\r
+ /* Plan for failure */\r
+ status = CYRET_UNKNOWN;\r
+\r
+ /* Command to load a row of data */\r
+ if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED)\r
+ {\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Wait until SPC becomes idle */\r
+ }\r
+\r
+ /* SPC is idle now */\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ /* Command to erase and program the row. */\r
+ if(status == CYRET_SUCCESS)\r
+ {\r
+ if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],\r
+ dieTemperature[1]) == CYRET_STARTED)\r
+ {\r
+ status = CYRET_STARTED;\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CFG_EEPROM_QueryWrite\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Checks the state of write to EEPROM. This function must be called until\r
+* the return value is not CYRET_STARTED.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* CYRET_STARTED, if the spc command is still processing.\r
+* CYRET_SUCCESS, if the operation was successful.\r
+* CYRET_UNKNOWN, if there was an SPC error.\r
+*\r
+*******************************************************************************/\r
+cystatus CFG_EEPROM_QueryWrite(void) \r
+{\r
+ cystatus status;\r
+\r
+ /* Check if SPC is idle */\r
+ if(CY_SPC_IDLE)\r
+ {\r
+ /* SPC is idle now */\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
+\r
+ /* Unlock the SPC so someone else can use it. */\r
+ CySpcUnlock();\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_STARTED;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CFG_EEPROM_ByteWrite\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Writes a byte of data to the EEPROM. This is a blocking call. It will not\r
+* return until the function succeeds or fails.\r
+*\r
+* Parameters:\r
+* dataByte: Byte of data to write to the EEPROM.\r
+* rowNumber: EEPROM row number to program.\r
+* byteNumber: Byte number within the row to program.\r
+*\r
+* Return:\r
+* CYRET_SUCCESS, if the operation was successful.\r
+* CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber out of range.\r
+* CYRET_LOCKED, if the spc is being used.\r
+* CYRET_UNKNOWN, if there was an SPC error.\r
+*\r
+*******************************************************************************/\r
+cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \\r
+\r
+{\r
+ cystatus status;\r
+\r
+ /* Start the SPC */\r
+ CySpcStart();\r
+\r
+ if((rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) && (byteNumber < (uint8) SIZEOF_EEPROM_ROW))\r
+ {\r
+ /* See if we can get the SPC. */\r
+ if(CySpcLock() == CYRET_SUCCESS)\r
+ {\r
+ /* Plan for failure */\r
+ status = CYRET_UNKNOWN;\r
+\r
+ /* Command to load a byte of data */\r
+ if(CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, (uint16)byteNumber, &dataByte,\\r
+ CFG_EEPROM_SPC_BYTE_WRITE_SIZE) == CYRET_STARTED)\r
+ {\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Wait until SPC becomes idle */\r
+ }\r
+\r
+ /* SPC is idle now */\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ /* Command to erase and program the row. */\r
+ if(status == CYRET_SUCCESS)\r
+ {\r
+ if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0],\r
+ dieTemperature[1]) == CYRET_STARTED)\r
+ {\r
+ /* Plan for failure */\r
+ status = CYRET_UNKNOWN;\r
+\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Wait until SPC becomes idle */\r
+ }\r
+\r
+ /* SPC is idle now */\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
+ }\r
+\r
+ /* Unlock the SPC so someone else can use it. */\r
+ CySpcUnlock();\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: CFG_EEPROM.h\r
+* Version 2.10\r
+*\r
+* Description:\r
+* Provides the function definitions for the EEPROM APIs.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_EEPROM_CFG_EEPROM_H)\r
+#define CY_EEPROM_CFG_EEPROM_H\r
+\r
+#include "cydevice_trm.h"\r
+#include "CyFlash.h"\r
+\r
+#if !defined(CY_PSOC5LP)\r
+ #error Component EEPROM_v2_10 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5LP) */\r
+\r
+\r
+/***************************************\r
+* Function Prototypes\r
+***************************************/\r
+\r
+#if (CY_PSOC3 || CY_PSOC5LP) \r
+ void CFG_EEPROM_Enable(void) ;\r
+ void CFG_EEPROM_Start(void); \r
+ void CFG_EEPROM_Stop(void) ;\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) ;\r
+cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) ;\r
+cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \\r
+ ;\r
+cystatus CFG_EEPROM_QueryWrite(void) ;\r
+cystatus CFG_EEPROM_ByteWrite(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \\r
+ ;\r
+\r
+\r
+/****************************************\r
+* API Constants\r
+****************************************/\r
+\r
+#define CFG_EEPROM_EEPROM_SIZE CYDEV_EE_SIZE\r
+#define CFG_EEPROM_SPC_BYTE_WRITE_SIZE (0x01u)\r
+\r
+\r
+/*******************************************************************************\r
+* Following code are OBSOLETE and must not be used starting from EEPROM 2.10\r
+*******************************************************************************/\r
+#define SPC_BYTE_WRITE_SIZE (CFG_EEPROM_SPC_BYTE_WRITE_SIZE)\r
+\r
+#endif /* CY_EEPROM_CFG_EEPROM_H */\r
+\r
+/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: PARITY_EN.c \r
-* Version 1.90\r
-*\r
-* Description:\r
-* This file contains API to enable firmware control of a Pins component.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "cytypes.h"\r
-#include "PARITY_EN.h"\r
-\r
-/* APIs are not generated for P15[7:6] on PSoC 5 */\r
-#if !(CY_PSOC5A &&\\r
- PARITY_EN__PORT == 15 && ((PARITY_EN__MASK & 0xC0) != 0))\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: PARITY_EN_Write\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Assign a new value to the digital port's data output register. \r
-*\r
-* Parameters: \r
-* prtValue: The value to be assigned to the Digital Port. \r
-*\r
-* Return: \r
-* None\r
-* \r
-*******************************************************************************/\r
-void PARITY_EN_Write(uint8 value) \r
-{\r
- uint8 staticBits = (PARITY_EN_DR & (uint8)(~PARITY_EN_MASK));\r
- PARITY_EN_DR = staticBits | ((uint8)(value << PARITY_EN_SHIFT) & PARITY_EN_MASK);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: PARITY_EN_SetDriveMode\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Change the drive mode on the pins of the port.\r
-* \r
-* Parameters: \r
-* mode: Change the pins to this drive mode.\r
-*\r
-* Return: \r
-* None\r
-*\r
-*******************************************************************************/\r
-void PARITY_EN_SetDriveMode(uint8 mode) \r
-{\r
- CyPins_SetPinDriveMode(PARITY_EN_0, mode);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: PARITY_EN_Read\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Read the current value on the pins of the Digital Port in right justified \r
-* form.\r
-*\r
-* Parameters: \r
-* None\r
-*\r
-* Return: \r
-* Returns the current value of the Digital Port as a right justified number\r
-* \r
-* Note:\r
-* Macro PARITY_EN_ReadPS calls this function. \r
-* \r
-*******************************************************************************/\r
-uint8 PARITY_EN_Read(void) \r
-{\r
- return (PARITY_EN_PS & PARITY_EN_MASK) >> PARITY_EN_SHIFT;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: PARITY_EN_ReadDataReg\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Read the current value assigned to a Digital Port's data output register\r
-*\r
-* Parameters: \r
-* None \r
-*\r
-* Return: \r
-* Returns the current value assigned to the Digital Port's data output register\r
-* \r
-*******************************************************************************/\r
-uint8 PARITY_EN_ReadDataReg(void) \r
-{\r
- return (PARITY_EN_DR & PARITY_EN_MASK) >> PARITY_EN_SHIFT;\r
-}\r
-\r
-\r
-/* If Interrupts Are Enabled for this Pins component */ \r
-#if defined(PARITY_EN_INTSTAT) \r
-\r
- /*******************************************************************************\r
- * Function Name: PARITY_EN_ClearInterrupt\r
- ********************************************************************************\r
- * Summary:\r
- * Clears any active interrupts attached to port and returns the value of the \r
- * interrupt status register.\r
- *\r
- * Parameters: \r
- * None \r
- *\r
- * Return: \r
- * Returns the value of the interrupt status register\r
- * \r
- *******************************************************************************/\r
- uint8 PARITY_EN_ClearInterrupt(void) \r
- {\r
- return (PARITY_EN_INTSTAT & PARITY_EN_MASK) >> PARITY_EN_SHIFT;\r
- }\r
-\r
-#endif /* If Interrupts Are Enabled for this Pins component */ \r
-\r
-#endif /* CY_PSOC5A... */\r
-\r
- \r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: PARITY_EN.h \r
-* Version 1.90\r
-*\r
-* Description:\r
-* This file containts Control Register function prototypes and register defines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_PINS_PARITY_EN_H) /* Pins PARITY_EN_H */\r
-#define CY_PINS_PARITY_EN_H\r
-\r
-#include "cytypes.h"\r
-#include "cyfitter.h"\r
-#include "cypins.h"\r
-#include "PARITY_EN_aliases.h"\r
-\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
-/* APIs are not generated for P15[7:6] */\r
-#if !(CY_PSOC5A &&\\r
- PARITY_EN__PORT == 15 && ((PARITY_EN__MASK & 0xC0) != 0))\r
-\r
-\r
-/***************************************\r
-* Function Prototypes \r
-***************************************/ \r
-\r
-void PARITY_EN_Write(uint8 value) ;\r
-void PARITY_EN_SetDriveMode(uint8 mode) ;\r
-uint8 PARITY_EN_ReadDataReg(void) ;\r
-uint8 PARITY_EN_Read(void) ;\r
-uint8 PARITY_EN_ClearInterrupt(void) ;\r
-\r
-\r
-/***************************************\r
-* API Constants \r
-***************************************/\r
-\r
-/* Drive Modes */\r
-#define PARITY_EN_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
-#define PARITY_EN_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
-#define PARITY_EN_DM_RES_UP PIN_DM_RES_UP\r
-#define PARITY_EN_DM_RES_DWN PIN_DM_RES_DWN\r
-#define PARITY_EN_DM_OD_LO PIN_DM_OD_LO\r
-#define PARITY_EN_DM_OD_HI PIN_DM_OD_HI\r
-#define PARITY_EN_DM_STRONG PIN_DM_STRONG\r
-#define PARITY_EN_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
-\r
-/* Digital Port Constants */\r
-#define PARITY_EN_MASK PARITY_EN__MASK\r
-#define PARITY_EN_SHIFT PARITY_EN__SHIFT\r
-#define PARITY_EN_WIDTH 1u\r
-\r
-\r
-/***************************************\r
-* Registers \r
-***************************************/\r
-\r
-/* Main Port Registers */\r
-/* Pin State */\r
-#define PARITY_EN_PS (* (reg8 *) PARITY_EN__PS)\r
-/* Data Register */\r
-#define PARITY_EN_DR (* (reg8 *) PARITY_EN__DR)\r
-/* Port Number */\r
-#define PARITY_EN_PRT_NUM (* (reg8 *) PARITY_EN__PRT) \r
-/* Connect to Analog Globals */ \r
-#define PARITY_EN_AG (* (reg8 *) PARITY_EN__AG) \r
-/* Analog MUX bux enable */\r
-#define PARITY_EN_AMUX (* (reg8 *) PARITY_EN__AMUX) \r
-/* Bidirectional Enable */ \r
-#define PARITY_EN_BIE (* (reg8 *) PARITY_EN__BIE)\r
-/* Bit-mask for Aliased Register Access */\r
-#define PARITY_EN_BIT_MASK (* (reg8 *) PARITY_EN__BIT_MASK)\r
-/* Bypass Enable */\r
-#define PARITY_EN_BYP (* (reg8 *) PARITY_EN__BYP)\r
-/* Port wide control signals */ \r
-#define PARITY_EN_CTL (* (reg8 *) PARITY_EN__CTL)\r
-/* Drive Modes */\r
-#define PARITY_EN_DM0 (* (reg8 *) PARITY_EN__DM0) \r
-#define PARITY_EN_DM1 (* (reg8 *) PARITY_EN__DM1)\r
-#define PARITY_EN_DM2 (* (reg8 *) PARITY_EN__DM2) \r
-/* Input Buffer Disable Override */\r
-#define PARITY_EN_INP_DIS (* (reg8 *) PARITY_EN__INP_DIS)\r
-/* LCD Common or Segment Drive */\r
-#define PARITY_EN_LCD_COM_SEG (* (reg8 *) PARITY_EN__LCD_COM_SEG)\r
-/* Enable Segment LCD */\r
-#define PARITY_EN_LCD_EN (* (reg8 *) PARITY_EN__LCD_EN)\r
-/* Slew Rate Control */\r
-#define PARITY_EN_SLW (* (reg8 *) PARITY_EN__SLW)\r
-\r
-/* DSI Port Registers */\r
-/* Global DSI Select Register */\r
-#define PARITY_EN_PRTDSI__CAPS_SEL (* (reg8 *) PARITY_EN__PRTDSI__CAPS_SEL) \r
-/* Double Sync Enable */\r
-#define PARITY_EN_PRTDSI__DBL_SYNC_IN (* (reg8 *) PARITY_EN__PRTDSI__DBL_SYNC_IN) \r
-/* Output Enable Select Drive Strength */\r
-#define PARITY_EN_PRTDSI__OE_SEL0 (* (reg8 *) PARITY_EN__PRTDSI__OE_SEL0) \r
-#define PARITY_EN_PRTDSI__OE_SEL1 (* (reg8 *) PARITY_EN__PRTDSI__OE_SEL1) \r
-/* Port Pin Output Select Registers */\r
-#define PARITY_EN_PRTDSI__OUT_SEL0 (* (reg8 *) PARITY_EN__PRTDSI__OUT_SEL0) \r
-#define PARITY_EN_PRTDSI__OUT_SEL1 (* (reg8 *) PARITY_EN__PRTDSI__OUT_SEL1) \r
-/* Sync Output Enable Registers */\r
-#define PARITY_EN_PRTDSI__SYNC_OUT (* (reg8 *) PARITY_EN__PRTDSI__SYNC_OUT) \r
-\r
-\r
-#if defined(PARITY_EN__INTSTAT) /* Interrupt Registers */\r
-\r
- #define PARITY_EN_INTSTAT (* (reg8 *) PARITY_EN__INTSTAT)\r
- #define PARITY_EN_SNAP (* (reg8 *) PARITY_EN__SNAP)\r
-\r
-#endif /* Interrupt Registers */\r
-\r
-#endif /* CY_PSOC5A... */\r
-\r
-#endif /* CY_PINS_PARITY_EN_H */\r
-\r
-\r
-/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_CTL_IO.c \r
+* Version 1.70\r
+*\r
+* Description:\r
+* This file contains API to enable firmware control of a Control Register.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "SCSI_CTL_IO.h"\r
+\r
+#if !defined(SCSI_CTL_IO_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_CTL_IO_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Write a byte to the Control Register.\r
+*\r
+* Parameters:\r
+* control: The value to be assigned to the Control Register.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+*******************************************************************************/\r
+void SCSI_CTL_IO_Write(uint8 control) \r
+{\r
+ SCSI_CTL_IO_Control = control;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_CTL_IO_Read\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Reads the current value assigned to the Control Register.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* Returns the current value in the Control Register.\r
+*\r
+*******************************************************************************/\r
+uint8 SCSI_CTL_IO_Read(void) \r
+{\r
+ return SCSI_CTL_IO_Control;\r
+}\r
+\r
+#endif /* End check for removal by optimization */\r
+\r
+\r
+/* [] END OF FILE */\r
/*******************************************************************************\r
-* File Name: PARITY_EN.h \r
-* Version 1.90\r
+* File Name: SCSI_CTL_IO.h \r
+* Version 1.70\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
-#if !defined(CY_PINS_PARITY_EN_ALIASES_H) /* Pins PARITY_EN_ALIASES_H */\r
-#define CY_PINS_PARITY_EN_ALIASES_H\r
+#if !defined(CY_CONTROL_REG_SCSI_CTL_IO_H) /* CY_CONTROL_REG_SCSI_CTL_IO_H */\r
+#define CY_CONTROL_REG_SCSI_CTL_IO_H\r
\r
#include "cytypes.h"\r
-#include "cyfitter.h"\r
\r
\r
+/***************************************\r
+* Function Prototypes \r
+***************************************/\r
+\r
+void SCSI_CTL_IO_Write(uint8 control) ;\r
+uint8 SCSI_CTL_IO_Read(void) ;\r
+\r
\r
/***************************************\r
-* Constants \r
+* Registers \r
***************************************/\r
-#define PARITY_EN_0 PARITY_EN__0__PC\r
\r
-#endif /* End Pins PARITY_EN_ALIASES_H */\r
+/* Control Register */\r
+#define SCSI_CTL_IO_Control (* (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG )\r
+#define SCSI_CTL_IO_Control_PTR ( (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG )\r
+\r
+#endif /* End CY_CONTROL_REG_SCSI_CTL_IO_H */\r
+\r
\r
/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SCSI_ID.h \r
-* Version 1.90\r
-*\r
-* Description:\r
-* This file containts Control Register function prototypes and register defines\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_PINS_SCSI_ID_ALIASES_H) /* Pins SCSI_ID_ALIASES_H */\r
-#define CY_PINS_SCSI_ID_ALIASES_H\r
-\r
-#include "cytypes.h"\r
-#include "cyfitter.h"\r
-\r
-\r
-\r
-/***************************************\r
-* Constants \r
-***************************************/\r
-#define SCSI_ID_0 SCSI_ID__0__PC\r
-#define SCSI_ID_1 SCSI_ID__1__PC\r
-#define SCSI_ID_2 SCSI_ID__2__PC\r
-\r
-#endif /* End Pins SCSI_ID_ALIASES_H */\r
-\r
-/* [] END OF FILE */\r
#define SCSI_Out_8 SCSI_Out__8__PC\r
#define SCSI_Out_9 SCSI_Out__9__PC\r
\r
-#define SCSI_Out_DBP SCSI_Out__DBP__PC\r
+#define SCSI_Out_DBP_raw SCSI_Out__DBP_raw__PC\r
#define SCSI_Out_ATN SCSI_Out__ATN__PC\r
#define SCSI_Out_BSY SCSI_Out__BSY__PC\r
#define SCSI_Out_ACK SCSI_Out__ACK__PC\r
#define SCSI_Out_SEL SCSI_Out__SEL__PC\r
#define SCSI_Out_CD SCSI_Out__CD__PC\r
#define SCSI_Out_REQ SCSI_Out__REQ__PC\r
-#define SCSI_Out_IO SCSI_Out__IO__PC\r
+#define SCSI_Out_IO_raw SCSI_Out__IO_raw__PC\r
\r
#endif /* End Pins SCSI_Out_ALIASES_H */\r
\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SD.c\r
-* Version 2.40\r
-*\r
-* Description:\r
-* This file provides all API functionality of the SPI Master component.\r
-*\r
-* Note:\r
-* None.\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "SD_PVT.h"\r
-\r
-#if(SD_TX_SOFTWARE_BUF_ENABLED)\r
- volatile uint8 SD_txBuffer[SD_TX_BUFFER_SIZE] = {0u};\r
- volatile uint8 SD_txBufferFull;\r
- volatile uint8 SD_txBufferRead;\r
- volatile uint8 SD_txBufferWrite;\r
-#endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
-#if(SD_RX_SOFTWARE_BUF_ENABLED)\r
- volatile uint8 SD_rxBuffer[SD_RX_BUFFER_SIZE] = {0u};\r
- volatile uint8 SD_rxBufferFull;\r
- volatile uint8 SD_rxBufferRead;\r
- volatile uint8 SD_rxBufferWrite;\r
-#endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
-uint8 SD_initVar = 0u;\r
-\r
-volatile uint8 SD_swStatusTx;\r
-volatile uint8 SD_swStatusRx;\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Init\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Inits/Restores default SPIM configuration provided with customizer.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Side Effects:\r
-* When this function is called it initializes all of the necessary parameters\r
-* for execution. i.e. setting the initial interrupt mask, configuring the\r
-* interrupt service routine, configuring the bit-counter parameters and\r
-* clearing the FIFO and Status Register.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void SD_Init(void) \r
-{\r
- /* Initialize the Bit counter */\r
- SD_COUNTER_PERIOD_REG = SD_BITCTR_INIT;\r
-\r
- /* Init TX ISR */\r
- #if(0u != SD_INTERNAL_TX_INT_ENABLED)\r
- CyIntDisable (SD_TX_ISR_NUMBER);\r
- CyIntSetPriority (SD_TX_ISR_NUMBER, SD_TX_ISR_PRIORITY);\r
- (void) CyIntSetVector(SD_TX_ISR_NUMBER, &SD_TX_ISR);\r
- #endif /* (0u != SD_INTERNAL_TX_INT_ENABLED) */\r
-\r
- /* Init RX ISR */\r
- #if(0u != SD_INTERNAL_RX_INT_ENABLED)\r
- CyIntDisable (SD_RX_ISR_NUMBER);\r
- CyIntSetPriority (SD_RX_ISR_NUMBER, SD_RX_ISR_PRIORITY);\r
- (void) CyIntSetVector(SD_RX_ISR_NUMBER, &SD_RX_ISR);\r
- #endif /* (0u != SD_INTERNAL_RX_INT_ENABLED) */\r
-\r
- /* Clear any stray data from the RX and TX FIFO */\r
- SD_ClearFIFO();\r
-\r
- #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
- SD_rxBufferFull = 0u;\r
- SD_rxBufferRead = 0u;\r
- SD_rxBufferWrite = 0u;\r
- #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
- #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
- SD_txBufferFull = 0u;\r
- SD_txBufferRead = 0u;\r
- SD_txBufferWrite = 0u;\r
- #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
- (void) SD_ReadTxStatus(); /* Clear Tx status and swStatusTx */\r
- (void) SD_ReadRxStatus(); /* Clear Rx status and swStatusRx */\r
-\r
- /* Configure TX and RX interrupt mask */\r
- SD_TX_STATUS_MASK_REG = SD_TX_INIT_INTERRUPTS_MASK;\r
- SD_RX_STATUS_MASK_REG = SD_RX_INIT_INTERRUPTS_MASK;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Enable\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Enable SPIM component.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-*******************************************************************************/\r
-void SD_Enable(void) \r
-{\r
- uint8 enableInterrupts;\r
-\r
- enableInterrupts = CyEnterCriticalSection();\r
- SD_COUNTER_CONTROL_REG |= SD_CNTR_ENABLE;\r
- SD_TX_STATUS_ACTL_REG |= SD_INT_ENABLE;\r
- SD_RX_STATUS_ACTL_REG |= SD_INT_ENABLE;\r
- CyExitCriticalSection(enableInterrupts);\r
-\r
- #if(0u != SD_INTERNAL_CLOCK)\r
- SD_IntClock_Enable();\r
- #endif /* (0u != SD_INTERNAL_CLOCK) */\r
-\r
- SD_EnableTxInt();\r
- SD_EnableRxInt();\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Start\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Initialize and Enable the SPI Master component.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* SD_initVar - used to check initial configuration, modified on\r
-* first function call.\r
-*\r
-* Theory:\r
-* Enable the clock input to enable operation.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void SD_Start(void) \r
-{\r
- if(0u == SD_initVar)\r
- {\r
- SD_Init();\r
- SD_initVar = 1u;\r
- }\r
-\r
- SD_Enable();\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Stop\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Disable the SPI Master component.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Theory:\r
-* Disable the clock input to enable operation.\r
-*\r
-*******************************************************************************/\r
-void SD_Stop(void) \r
-{\r
- uint8 enableInterrupts;\r
-\r
- enableInterrupts = CyEnterCriticalSection();\r
- SD_TX_STATUS_ACTL_REG &= ((uint8) ~SD_INT_ENABLE);\r
- SD_RX_STATUS_ACTL_REG &= ((uint8) ~SD_INT_ENABLE);\r
- CyExitCriticalSection(enableInterrupts);\r
-\r
- #if(0u != SD_INTERNAL_CLOCK)\r
- SD_IntClock_Disable();\r
- #endif /* (0u != SD_INTERNAL_CLOCK) */\r
-\r
- SD_DisableTxInt();\r
- SD_DisableRxInt();\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_EnableTxInt\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Enable internal Tx interrupt generation.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Theory:\r
-* Enable the internal Tx interrupt output -or- the interrupt component itself.\r
-*\r
-*******************************************************************************/\r
-void SD_EnableTxInt(void) \r
-{\r
- #if(0u != SD_INTERNAL_TX_INT_ENABLED)\r
- CyIntEnable(SD_TX_ISR_NUMBER);\r
- #endif /* (0u != SD_INTERNAL_TX_INT_ENABLED) */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_EnableRxInt\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Enable internal Rx interrupt generation.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Theory:\r
-* Enable the internal Rx interrupt output -or- the interrupt component itself.\r
-*\r
-*******************************************************************************/\r
-void SD_EnableRxInt(void) \r
-{\r
- #if(0u != SD_INTERNAL_RX_INT_ENABLED)\r
- CyIntEnable(SD_RX_ISR_NUMBER);\r
- #endif /* (0u != SD_INTERNAL_RX_INT_ENABLED) */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_DisableTxInt\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Disable internal Tx interrupt generation.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Theory:\r
-* Disable the internal Tx interrupt output -or- the interrupt component itself.\r
-*\r
-*******************************************************************************/\r
-void SD_DisableTxInt(void) \r
-{\r
- #if(0u != SD_INTERNAL_TX_INT_ENABLED)\r
- CyIntDisable(SD_TX_ISR_NUMBER);\r
- #endif /* (0u != SD_INTERNAL_TX_INT_ENABLED) */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_DisableRxInt\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Disable internal Rx interrupt generation.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Theory:\r
-* Disable the internal Rx interrupt output -or- the interrupt component itself.\r
-*\r
-*******************************************************************************/\r
-void SD_DisableRxInt(void) \r
-{\r
- #if(0u != SD_INTERNAL_RX_INT_ENABLED)\r
- CyIntDisable(SD_RX_ISR_NUMBER);\r
- #endif /* (0u != SD_INTERNAL_RX_INT_ENABLED) */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_SetTxInterruptMode\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Configure which status bits trigger an interrupt event.\r
-*\r
-* Parameters:\r
-* intSrc: An or'd combination of the desired status bit masks (defined in the\r
-* header file).\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Theory:\r
-* Enables the output of specific status bits to the interrupt controller.\r
-*\r
-*******************************************************************************/\r
-void SD_SetTxInterruptMode(uint8 intSrc) \r
-{\r
- SD_TX_STATUS_MASK_REG = intSrc;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_SetRxInterruptMode\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Configure which status bits trigger an interrupt event.\r
-*\r
-* Parameters:\r
-* intSrc: An or'd combination of the desired status bit masks (defined in the\r
-* header file).\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Theory:\r
-* Enables the output of specific status bits to the interrupt controller.\r
-*\r
-*******************************************************************************/\r
-void SD_SetRxInterruptMode(uint8 intSrc) \r
-{\r
- SD_RX_STATUS_MASK_REG = intSrc;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_ReadTxStatus\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Read the Tx status register for the component.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* Contents of the Tx status register.\r
-*\r
-* Global variables:\r
-* SD_swStatusTx - used to store in software status register,\r
-* modified every function call - resets to zero.\r
-*\r
-* Theory:\r
-* Allows the user and the API to read the Tx status register for error\r
-* detection and flow control.\r
-*\r
-* Side Effects:\r
-* Clear Tx status register of the component.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_ReadTxStatus(void) \r
-{\r
- uint8 tmpStatus;\r
-\r
- #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
- /* Disable TX interrupt to protect global veriables */\r
- SD_DisableTxInt();\r
-\r
- tmpStatus = SD_GET_STATUS_TX(SD_swStatusTx);\r
- SD_swStatusTx = 0u;\r
-\r
- SD_EnableTxInt();\r
-\r
- #else\r
-\r
- tmpStatus = SD_TX_STATUS_REG;\r
-\r
- #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
- return(tmpStatus);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_ReadRxStatus\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Read the Rx status register for the component.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* Contents of the Rx status register.\r
-*\r
-* Global variables:\r
-* SD_swStatusRx - used to store in software Rx status register,\r
-* modified every function call - resets to zero.\r
-*\r
-* Theory:\r
-* Allows the user and the API to read the Rx status register for error\r
-* detection and flow control.\r
-*\r
-* Side Effects:\r
-* Clear Rx status register of the component.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_ReadRxStatus(void) \r
-{\r
- uint8 tmpStatus;\r
-\r
- #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
- /* Disable RX interrupt to protect global veriables */\r
- SD_DisableRxInt();\r
-\r
- tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx);\r
- SD_swStatusRx = 0u;\r
-\r
- SD_EnableRxInt();\r
-\r
- #else\r
-\r
- tmpStatus = SD_RX_STATUS_REG;\r
-\r
- #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
- return(tmpStatus);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_WriteTxData\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Write a byte of data to be sent across the SPI.\r
-*\r
-* Parameters:\r
-* txDataByte: The data value to send across the SPI.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* SD_txBufferWrite - used for the account of the bytes which\r
-* have been written down in the TX software buffer, modified every function\r
-* call if TX Software Buffer is used.\r
-* SD_txBufferRead - used for the account of the bytes which\r
-* have been read from the TX software buffer.\r
-* SD_txBuffer[SD_TX_BUFFER_SIZE] - used to store\r
-* data to sending, modified every function call if TX Software Buffer is used.\r
-*\r
-* Theory:\r
-* Allows the user to transmit any byte of data in a single transfer.\r
-*\r
-* Side Effects:\r
-* If this function is called again before the previous byte is finished then\r
-* the next byte will be appended to the transfer with no time between\r
-* the byte transfers. Clear Tx status register of the component.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void SD_WriteTxData(uint8 txData) \r
-{\r
- #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
-\r
- uint8 tempStatus;\r
- uint8 tmpTxBufferRead;\r
-\r
- /* Block if TX buffer is FULL: don't overwrite */\r
- do\r
- {\r
- tmpTxBufferRead = SD_txBufferRead;\r
- if(0u == tmpTxBufferRead)\r
- {\r
- tmpTxBufferRead = (SD_TX_BUFFER_SIZE - 1u);\r
- }\r
- else\r
- {\r
- tmpTxBufferRead--;\r
- }\r
-\r
- }while(tmpTxBufferRead == SD_txBufferWrite);\r
-\r
- /* Disable TX interrupt to protect global veriables */\r
- SD_DisableTxInt();\r
-\r
- tempStatus = SD_GET_STATUS_TX(SD_swStatusTx);\r
- SD_swStatusTx = tempStatus;\r
-\r
-\r
- if((SD_txBufferRead == SD_txBufferWrite) &&\r
- (0u != (SD_swStatusTx & SD_STS_TX_FIFO_NOT_FULL)))\r
- {\r
- /* Add directly to the TX FIFO */\r
- CY_SET_REG8(SD_TXDATA_PTR, txData);\r
- }\r
- else\r
- {\r
- /* Add to the TX software buffer */\r
- SD_txBufferWrite++;\r
- if(SD_txBufferWrite >= SD_TX_BUFFER_SIZE)\r
- {\r
- SD_txBufferWrite = 0u;\r
- }\r
-\r
- if(SD_txBufferWrite == SD_txBufferRead)\r
- {\r
- SD_txBufferRead++;\r
- if(SD_txBufferRead >= SD_TX_BUFFER_SIZE)\r
- {\r
- SD_txBufferRead = 0u;\r
- }\r
- SD_txBufferFull = 1u;\r
- }\r
-\r
- SD_txBuffer[SD_txBufferWrite] = txData;\r
-\r
- SD_TX_STATUS_MASK_REG |= SD_STS_TX_FIFO_NOT_FULL;\r
- }\r
-\r
- SD_EnableTxInt();\r
-\r
- #else\r
-\r
- while(0u == (SD_TX_STATUS_REG & SD_STS_TX_FIFO_NOT_FULL))\r
- {\r
- ; /* Wait for room in FIFO */\r
- }\r
-\r
- /* Put byte in TX FIFO */\r
- CY_SET_REG8(SD_TXDATA_PTR, txData);\r
-\r
- #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_ReadRxData\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Read the next byte of data received across the SPI.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* The next byte of data read from the FIFO.\r
-*\r
-* Global variables:\r
-* SD_rxBufferWrite - used for the account of the bytes which\r
-* have been written down in the RX software buffer.\r
-* SD_rxBufferRead - used for the account of the bytes which\r
-* have been read from the RX software buffer, modified every function\r
-* call if RX Software Buffer is used.\r
-* SD_rxBuffer[SD_RX_BUFFER_SIZE] - used to store\r
-* received data.\r
-*\r
-* Theory:\r
-* Allows the user to read a byte of data received.\r
-*\r
-* Side Effects:\r
-* Will return invalid data if the FIFO is empty. The user should Call\r
-* GetRxBufferSize() and if it returns a non-zero value then it is safe to call\r
-* ReadByte() function.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_ReadRxData(void) \r
-{\r
- uint8 rxData;\r
-\r
- #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
-\r
- /* Disable RX interrupt to protect global veriables */\r
- SD_DisableRxInt();\r
-\r
- if(SD_rxBufferRead != SD_rxBufferWrite)\r
- {\r
- if(0u == SD_rxBufferFull)\r
- {\r
- SD_rxBufferRead++;\r
- if(SD_rxBufferRead >= SD_RX_BUFFER_SIZE)\r
- {\r
- SD_rxBufferRead = 0u;\r
- }\r
- }\r
- else\r
- {\r
- SD_rxBufferFull = 0u;\r
- }\r
- }\r
-\r
- rxData = SD_rxBuffer[SD_rxBufferRead];\r
-\r
- SD_EnableRxInt();\r
-\r
- #else\r
-\r
- rxData = CY_GET_REG8(SD_RXDATA_PTR);\r
-\r
- #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
- return(rxData);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_GetRxBufferSize\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Returns the number of bytes/words of data currently held in the RX buffer.\r
-* If RX Software Buffer not used then function return 0 if FIFO empty or 1 if\r
-* FIFO not empty. In another case function return size of RX Software Buffer.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* Integer count of the number of bytes/words in the RX buffer.\r
-*\r
-* Global variables:\r
-* SD_rxBufferWrite - used for the account of the bytes which\r
-* have been written down in the RX software buffer.\r
-* SD_rxBufferRead - used for the account of the bytes which\r
-* have been read from the RX software buffer.\r
-*\r
-* Side Effects:\r
-* Clear status register of the component.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_GetRxBufferSize(void) \r
-{\r
- uint8 size;\r
-\r
- #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
-\r
- /* Disable RX interrupt to protect global veriables */\r
- SD_DisableRxInt();\r
-\r
- if(SD_rxBufferRead == SD_rxBufferWrite)\r
- {\r
- size = 0u;\r
- }\r
- else if(SD_rxBufferRead < SD_rxBufferWrite)\r
- {\r
- size = (SD_rxBufferWrite - SD_rxBufferRead);\r
- }\r
- else\r
- {\r
- size = (SD_RX_BUFFER_SIZE - SD_rxBufferRead) + SD_rxBufferWrite;\r
- }\r
-\r
- SD_EnableRxInt();\r
-\r
- #else\r
-\r
- /* We can only know if there is data in the RX FIFO */\r
- size = (0u != (SD_RX_STATUS_REG & SD_STS_RX_FIFO_NOT_EMPTY)) ? 1u : 0u;\r
-\r
- #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
- return(size);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_GetTxBufferSize\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Returns the number of bytes/words of data currently held in the TX buffer.\r
-* If TX Software Buffer not used then function return 0 - if FIFO empty, 1 - if\r
-* FIFO not full, 4 - if FIFO full. In another case function return size of TX\r
-* Software Buffer.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* Integer count of the number of bytes/words in the TX buffer.\r
-*\r
-* Global variables:\r
-* SD_txBufferWrite - used for the account of the bytes which\r
-* have been written down in the TX software buffer.\r
-* SD_txBufferRead - used for the account of the bytes which\r
-* have been read from the TX software buffer.\r
-*\r
-* Side Effects:\r
-* Clear status register of the component.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_GetTxBufferSize(void) \r
-{\r
- uint8 size;\r
-\r
- #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
- /* Disable TX interrupt to protect global veriables */\r
- SD_DisableTxInt();\r
-\r
- if(SD_txBufferRead == SD_txBufferWrite)\r
- {\r
- size = 0u;\r
- }\r
- else if(SD_txBufferRead < SD_txBufferWrite)\r
- {\r
- size = (SD_txBufferWrite - SD_txBufferRead);\r
- }\r
- else\r
- {\r
- size = (SD_TX_BUFFER_SIZE - SD_txBufferRead) + SD_txBufferWrite;\r
- }\r
-\r
- SD_EnableTxInt();\r
-\r
- #else\r
-\r
- size = SD_TX_STATUS_REG;\r
-\r
- if(0u != (size & SD_STS_TX_FIFO_EMPTY))\r
- {\r
- size = 0u;\r
- }\r
- else if(0u != (size & SD_STS_TX_FIFO_NOT_FULL))\r
- {\r
- size = 1u;\r
- }\r
- else\r
- {\r
- size = SD_FIFO_SIZE;\r
- }\r
-\r
- #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
- return(size);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_ClearRxBuffer\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Clear the RX RAM buffer by setting the read and write pointers both to zero.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* SD_rxBufferWrite - used for the account of the bytes which\r
-* have been written down in the RX software buffer, modified every function\r
-* call - resets to zero.\r
-* SD_rxBufferRead - used for the account of the bytes which\r
-* have been read from the RX software buffer, modified every function call -\r
-* resets to zero.\r
-*\r
-* Theory:\r
-* Setting the pointers to zero makes the system believe there is no data to\r
-* read and writing will resume at address 0 overwriting any data that may have\r
-* remained in the RAM.\r
-*\r
-* Side Effects:\r
-* Any received data not read from the RAM buffer will be lost when overwritten.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void SD_ClearRxBuffer(void) \r
-{\r
- /* Clear Hardware RX FIFO */\r
- while(0u !=(SD_RX_STATUS_REG & SD_STS_RX_FIFO_NOT_EMPTY))\r
- {\r
- (void) CY_GET_REG8(SD_RXDATA_PTR);\r
- }\r
-\r
- #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
- /* Disable RX interrupt to protect global veriables */\r
- SD_DisableRxInt();\r
-\r
- SD_rxBufferFull = 0u;\r
- SD_rxBufferRead = 0u;\r
- SD_rxBufferWrite = 0u;\r
-\r
- SD_EnableRxInt();\r
- #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_ClearTxBuffer\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Clear the TX RAM buffer by setting the read and write pointers both to zero.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* SD_txBufferWrite - used for the account of the bytes which\r
-* have been written down in the TX software buffer, modified every function\r
-* call - resets to zero.\r
-* SD_txBufferRead - used for the account of the bytes which\r
-* have been read from the TX software buffer, modified every function call -\r
-* resets to zero.\r
-*\r
-* Theory:\r
-* Setting the pointers to zero makes the system believe there is no data to\r
-* read and writing will resume at address 0 overwriting any data that may have\r
-* remained in the RAM.\r
-*\r
-* Side Effects:\r
-* Any data not yet transmitted from the RAM buffer will be lost when\r
-* overwritten.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void SD_ClearTxBuffer(void) \r
-{\r
- uint8 enableInterrupts;\r
-\r
- enableInterrupts = CyEnterCriticalSection();\r
- /* Clear TX FIFO */\r
- SD_AUX_CONTROL_DP0_REG |= ((uint8) SD_TX_FIFO_CLR);\r
- SD_AUX_CONTROL_DP0_REG &= ((uint8) ~SD_TX_FIFO_CLR);\r
-\r
- #if(SD_USE_SECOND_DATAPATH)\r
- /* Clear TX FIFO for 2nd Datapath */\r
- SD_AUX_CONTROL_DP1_REG |= ((uint8) SD_TX_FIFO_CLR);\r
- SD_AUX_CONTROL_DP1_REG &= ((uint8) ~SD_TX_FIFO_CLR);\r
- #endif /* (SD_USE_SECOND_DATAPATH) */\r
- CyExitCriticalSection(enableInterrupts);\r
-\r
- #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
- /* Disable TX interrupt to protect global veriables */\r
- SD_DisableTxInt();\r
-\r
- SD_txBufferFull = 0u;\r
- SD_txBufferRead = 0u;\r
- SD_txBufferWrite = 0u;\r
-\r
- /* Buffer is EMPTY: disable TX FIFO NOT FULL interrupt */\r
- SD_TX_STATUS_MASK_REG &= ((uint8) ~SD_STS_TX_FIFO_NOT_FULL);\r
-\r
- SD_EnableTxInt();\r
- #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-}\r
-\r
-\r
-#if(0u != SD_BIDIRECTIONAL_MODE)\r
- /*******************************************************************************\r
- * Function Name: SD_TxEnable\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * If the SPI master is configured to use a single bi-directional pin then this\r
- * will set the bi-directional pin to transmit.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- *******************************************************************************/\r
- void SD_TxEnable(void) \r
- {\r
- SD_CONTROL_REG |= SD_CTRL_TX_SIGNAL_EN;\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: SD_TxDisable\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * If the SPI master is configured to use a single bi-directional pin then this\r
- * will set the bi-directional pin to receive.\r
- *\r
- * Parameters:\r
- * None.\r
- *\r
- * Return:\r
- * None.\r
- *\r
- *******************************************************************************/\r
- void SD_TxDisable(void) \r
- {\r
- SD_CONTROL_REG &= ((uint8) ~SD_CTRL_TX_SIGNAL_EN);\r
- }\r
-\r
-#endif /* (0u != SD_BIDIRECTIONAL_MODE) */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_PutArray\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Write available data from ROM/RAM to the TX buffer while space is available\r
-* in the TX buffer. Keep trying until all data is passed to the TX buffer.\r
-*\r
-* Parameters:\r
-* *buffer: Pointer to the location in RAM containing the data to send\r
-* byteCount: The number of bytes to move to the transmit buffer.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Side Effects:\r
-* Will stay in this routine until all data has been sent. May get locked in\r
-* this loop if data is not being initiated by the master if there is not\r
-* enough room in the TX FIFO.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void SD_PutArray(const uint8 buffer[], uint8 byteCount)\r
- \r
-{\r
- uint8 bufIndex;\r
-\r
- bufIndex = 0u;\r
-\r
- while(byteCount > 0u)\r
- {\r
- SD_WriteTxData(buffer[bufIndex]);\r
- bufIndex++;\r
- byteCount--;\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_ClearFIFO\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Clear the RX and TX FIFO's of all data for a fresh start.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Side Effects:\r
-* Clear status register of the component.\r
-*\r
-*******************************************************************************/\r
-void SD_ClearFIFO(void) \r
-{\r
- uint8 enableInterrupts;\r
-\r
- /* Clear Hardware RX FIFO */\r
- while(0u !=(SD_RX_STATUS_REG & SD_STS_RX_FIFO_NOT_EMPTY))\r
- {\r
- (void) CY_GET_REG8(SD_RXDATA_PTR);\r
- }\r
-\r
- enableInterrupts = CyEnterCriticalSection();\r
- /* Clear TX FIFO */\r
- SD_AUX_CONTROL_DP0_REG |= ((uint8) SD_TX_FIFO_CLR);\r
- SD_AUX_CONTROL_DP0_REG &= ((uint8) ~SD_TX_FIFO_CLR);\r
-\r
- #if(SD_USE_SECOND_DATAPATH)\r
- /* Clear TX FIFO for 2nd Datapath */\r
- SD_AUX_CONTROL_DP1_REG |= ((uint8) SD_TX_FIFO_CLR);\r
- SD_AUX_CONTROL_DP1_REG &= ((uint8) ~SD_TX_FIFO_CLR);\r
- #endif /* (SD_USE_SECOND_DATAPATH) */\r
- CyExitCriticalSection(enableInterrupts);\r
-}\r
-\r
-\r
-/* Following functions are for version Compatibility, they are obsolete.\r
-* Please do not use it in new projects.\r
-*/\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_EnableInt\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Enable internal interrupt generation.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Theory:\r
-* Enable the internal interrupt output -or- the interrupt component itself.\r
-*\r
-*******************************************************************************/\r
-void SD_EnableInt(void) \r
-{\r
- SD_EnableRxInt();\r
- SD_EnableTxInt();\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_DisableInt\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Disable internal interrupt generation.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Theory:\r
-* Disable the internal interrupt output -or- the interrupt component itself.\r
-*\r
-*******************************************************************************/\r
-void SD_DisableInt(void) \r
-{\r
- SD_DisableTxInt();\r
- SD_DisableRxInt();\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_SetInterruptMode\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Configure which status bits trigger an interrupt event.\r
-*\r
-* Parameters:\r
-* intSrc: An or'd combination of the desired status bit masks (defined in the\r
-* header file).\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Theory:\r
-* Enables the output of specific status bits to the interrupt controller.\r
-*\r
-*******************************************************************************/\r
-void SD_SetInterruptMode(uint8 intSrc) \r
-{\r
- SD_TX_STATUS_MASK_REG = (intSrc & ((uint8) ~SD_STS_SPI_IDLE));\r
- SD_RX_STATUS_MASK_REG = intSrc;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_ReadStatus\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Read the status register for the component.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* Contents of the status register.\r
-*\r
-* Global variables:\r
-* SD_swStatus - used to store in software status register,\r
-* modified every function call - resets to zero.\r
-*\r
-* Theory:\r
-* Allows the user and the API to read the status register for error detection\r
-* and flow control.\r
-*\r
-* Side Effects:\r
-* Clear status register of the component.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_ReadStatus(void) \r
-{\r
- uint8 tmpStatus;\r
-\r
- #if(SD_TX_SOFTWARE_BUF_ENABLED || SD_RX_SOFTWARE_BUF_ENABLED)\r
-\r
- SD_DisableInt();\r
-\r
- tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx);\r
- tmpStatus |= SD_GET_STATUS_TX(SD_swStatusTx);\r
- tmpStatus &= ((uint8) ~SD_STS_SPI_IDLE);\r
-\r
- SD_swStatusTx = 0u;\r
- SD_swStatusRx = 0u;\r
-\r
- SD_EnableInt();\r
-\r
- #else\r
-\r
- tmpStatus = SD_RX_STATUS_REG;\r
- tmpStatus |= SD_TX_STATUS_REG;\r
- tmpStatus &= ((uint8) ~SD_STS_SPI_IDLE);\r
-\r
- #endif /* (SD_TX_SOFTWARE_BUF_ENABLED || SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
- return(tmpStatus);\r
-}\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SD.h\r
-* Version 2.40\r
-*\r
-* Description:\r
-* Contains the function prototypes, constants and register definition\r
-* of the SPI Master Component.\r
-*\r
-* Note:\r
-* None\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_SPIM_SD_H)\r
-#define CY_SPIM_SD_H\r
-\r
-#include "cytypes.h"\r
-#include "cyfitter.h"\r
-#include "CyLib.h"\r
-\r
-/* Check to see if required defines such as CY_PSOC5A are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5A)\r
- #error Component SPI_Master_v2_40 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5A) */\r
-\r
-\r
-/***************************************\r
-* Conditional Compilation Parameters\r
-***************************************/\r
-\r
-#define SD_INTERNAL_CLOCK (0u)\r
-\r
-#if(0u != SD_INTERNAL_CLOCK)\r
- #include "SD_IntClock.h"\r
-#endif /* (0u != SD_INTERNAL_CLOCK) */\r
-\r
-#define SD_MODE (1u)\r
-#define SD_DATA_WIDTH (8u)\r
-#define SD_MODE_USE_ZERO (1u)\r
-#define SD_BIDIRECTIONAL_MODE (0u)\r
-\r
-/* Internal interrupt handling */\r
-#define SD_TX_BUFFER_SIZE (4u)\r
-#define SD_RX_BUFFER_SIZE (4u)\r
-#define SD_INTERNAL_TX_INT_ENABLED (0u)\r
-#define SD_INTERNAL_RX_INT_ENABLED (0u)\r
-\r
-#define SD_SINGLE_REG_SIZE (8u)\r
-#define SD_USE_SECOND_DATAPATH (SD_DATA_WIDTH > SD_SINGLE_REG_SIZE)\r
-\r
-#define SD_FIFO_SIZE (4u)\r
-#define SD_TX_SOFTWARE_BUF_ENABLED ((0u != SD_INTERNAL_TX_INT_ENABLED) && \\r
- (SD_TX_BUFFER_SIZE > SD_FIFO_SIZE))\r
-\r
-#define SD_RX_SOFTWARE_BUF_ENABLED ((0u != SD_INTERNAL_RX_INT_ENABLED) && \\r
- (SD_RX_BUFFER_SIZE > SD_FIFO_SIZE))\r
-\r
-\r
-/***************************************\r
-* Data Struct Definition\r
-***************************************/\r
-\r
-/* Sleep Mode API Support */\r
-typedef struct\r
-{\r
- uint8 enableState;\r
- uint8 cntrPeriod;\r
- #if(CY_UDB_V0)\r
- uint8 saveSrTxIntMask;\r
- uint8 saveSrRxIntMask;\r
- #endif /* (CY_UDB_V0) */\r
-\r
-} SD_BACKUP_STRUCT;\r
-\r
-\r
-/***************************************\r
-* Function Prototypes\r
-***************************************/\r
-\r
-void SD_Init(void) ;\r
-void SD_Enable(void) ;\r
-void SD_Start(void) ;\r
-void SD_Stop(void) ;\r
-\r
-void SD_EnableTxInt(void) ;\r
-void SD_EnableRxInt(void) ;\r
-void SD_DisableTxInt(void) ;\r
-void SD_DisableRxInt(void) ;\r
-\r
-void SD_Sleep(void) ;\r
-void SD_Wakeup(void) ;\r
-void SD_SaveConfig(void) ;\r
-void SD_RestoreConfig(void) ;\r
-\r
-void SD_SetTxInterruptMode(uint8 intSrc) ;\r
-void SD_SetRxInterruptMode(uint8 intSrc) ;\r
-uint8 SD_ReadTxStatus(void) ;\r
-uint8 SD_ReadRxStatus(void) ;\r
-void SD_WriteTxData(uint8 txData) \\r
- ;\r
-uint8 SD_ReadRxData(void) \\r
- ;\r
-uint8 SD_GetRxBufferSize(void) ;\r
-uint8 SD_GetTxBufferSize(void) ;\r
-void SD_ClearRxBuffer(void) ;\r
-void SD_ClearTxBuffer(void) ;\r
-void SD_ClearFIFO(void) ;\r
-void SD_PutArray(const uint8 buffer[], uint8 byteCount) \\r
- ;\r
-\r
-#if(0u != SD_BIDIRECTIONAL_MODE)\r
- void SD_TxEnable(void) ;\r
- void SD_TxDisable(void) ;\r
-#endif /* (0u != SD_BIDIRECTIONAL_MODE) */\r
-\r
-CY_ISR_PROTO(SD_TX_ISR);\r
-CY_ISR_PROTO(SD_RX_ISR);\r
-\r
-\r
-/**********************************\r
-* Variable with external linkage\r
-**********************************/\r
-\r
-extern uint8 SD_initVar;\r
-\r
-\r
-/***************************************\r
-* API Constants\r
-***************************************/\r
-\r
-#define SD_TX_ISR_NUMBER ((uint8) (SD_TxInternalInterrupt__INTC_NUMBER))\r
-#define SD_RX_ISR_NUMBER ((uint8) (SD_RxInternalInterrupt__INTC_NUMBER))\r
-\r
-#define SD_TX_ISR_PRIORITY ((uint8) (SD_TxInternalInterrupt__INTC_PRIOR_NUM))\r
-#define SD_RX_ISR_PRIORITY ((uint8) (SD_RxInternalInterrupt__INTC_PRIOR_NUM))\r
-\r
-\r
-/***************************************\r
-* Initial Parameter Constants\r
-***************************************/\r
-\r
-#define SD_INT_ON_SPI_DONE ((uint8) (0u << SD_STS_SPI_DONE_SHIFT))\r
-#define SD_INT_ON_TX_EMPTY ((uint8) (0u << SD_STS_TX_FIFO_EMPTY_SHIFT))\r
-#define SD_INT_ON_TX_NOT_FULL ((uint8) (0u << \\r
- SD_STS_TX_FIFO_NOT_FULL_SHIFT))\r
-#define SD_INT_ON_BYTE_COMP ((uint8) (0u << SD_STS_BYTE_COMPLETE_SHIFT))\r
-#define SD_INT_ON_SPI_IDLE ((uint8) (0u << SD_STS_SPI_IDLE_SHIFT))\r
-\r
-/* Disable TX_NOT_FULL if software buffer is used */\r
-#define SD_INT_ON_TX_NOT_FULL_DEF ((SD_TX_SOFTWARE_BUF_ENABLED) ? \\r
- (0u) : (SD_INT_ON_TX_NOT_FULL))\r
-\r
-/* TX interrupt mask */\r
-#define SD_TX_INIT_INTERRUPTS_MASK (SD_INT_ON_SPI_DONE | \\r
- SD_INT_ON_TX_EMPTY | \\r
- SD_INT_ON_TX_NOT_FULL_DEF | \\r
- SD_INT_ON_BYTE_COMP | \\r
- SD_INT_ON_SPI_IDLE)\r
-\r
-#define SD_INT_ON_RX_FULL ((uint8) (0u << \\r
- SD_STS_RX_FIFO_FULL_SHIFT))\r
-#define SD_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \\r
- SD_STS_RX_FIFO_NOT_EMPTY_SHIFT))\r
-#define SD_INT_ON_RX_OVER ((uint8) (0u << \\r
- SD_STS_RX_FIFO_OVERRUN_SHIFT))\r
-\r
-/* RX interrupt mask */\r
-#define SD_RX_INIT_INTERRUPTS_MASK (SD_INT_ON_RX_FULL | \\r
- SD_INT_ON_RX_NOT_EMPTY | \\r
- SD_INT_ON_RX_OVER)\r
-/* Nubmer of bits to receive/transmit */\r
-#define SD_BITCTR_INIT (((uint8) (SD_DATA_WIDTH << 1u)) - 1u)\r
-\r
-\r
-/***************************************\r
-* Registers\r
-***************************************/\r
-\r
-#if(CY_PSOC3 || CY_PSOC5)\r
- #define SD_TXDATA_REG (* (reg8 *) \\r
- SD_BSPIM_sR8_Dp_u0__F0_REG)\r
- #define SD_TXDATA_PTR ( (reg8 *) \\r
- SD_BSPIM_sR8_Dp_u0__F0_REG)\r
- #define SD_RXDATA_REG (* (reg8 *) \\r
- SD_BSPIM_sR8_Dp_u0__F1_REG)\r
- #define SD_RXDATA_PTR ( (reg8 *) \\r
- SD_BSPIM_sR8_Dp_u0__F1_REG)\r
-#else /* PSOC4 */\r
- #if(SD_USE_SECOND_DATAPATH)\r
- #define SD_TXDATA_REG (* (reg16 *) \\r
- SD_BSPIM_sR8_Dp_u0__16BIT_F0_REG)\r
- #define SD_TXDATA_PTR ( (reg16 *) \\r
- SD_BSPIM_sR8_Dp_u0__16BIT_F0_REG)\r
- #define SD_RXDATA_REG (* (reg16 *) \\r
- SD_BSPIM_sR8_Dp_u0__16BIT_F1_REG)\r
- #define SD_RXDATA_PTR ( (reg16 *) \\r
- SD_BSPIM_sR8_Dp_u0__16BIT_F1_REG)\r
- #else\r
- #define SD_TXDATA_REG (* (reg8 *) \\r
- SD_BSPIM_sR8_Dp_u0__F0_REG)\r
- #define SD_TXDATA_PTR ( (reg8 *) \\r
- SD_BSPIM_sR8_Dp_u0__F0_REG)\r
- #define SD_RXDATA_REG (* (reg8 *) \\r
- SD_BSPIM_sR8_Dp_u0__F1_REG)\r
- #define SD_RXDATA_PTR ( (reg8 *) \\r
- SD_BSPIM_sR8_Dp_u0__F1_REG)\r
- #endif /* (SD_USE_SECOND_DATAPATH) */\r
-#endif /* (CY_PSOC3 || CY_PSOC5) */\r
-\r
-#define SD_AUX_CONTROL_DP0_REG (* (reg8 *) \\r
- SD_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)\r
-#define SD_AUX_CONTROL_DP0_PTR ( (reg8 *) \\r
- SD_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)\r
-\r
-#if(SD_USE_SECOND_DATAPATH)\r
- #define SD_AUX_CONTROL_DP1_REG (* (reg8 *) \\r
- SD_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)\r
- #define SD_AUX_CONTROL_DP1_PTR ( (reg8 *) \\r
- SD_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)\r
-#endif /* (SD_USE_SECOND_DATAPATH) */\r
-\r
-#define SD_COUNTER_PERIOD_REG (* (reg8 *) SD_BSPIM_BitCounter__PERIOD_REG)\r
-#define SD_COUNTER_PERIOD_PTR ( (reg8 *) SD_BSPIM_BitCounter__PERIOD_REG)\r
-#define SD_COUNTER_CONTROL_REG (* (reg8 *) SD_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)\r
-#define SD_COUNTER_CONTROL_PTR ( (reg8 *) SD_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)\r
-\r
-#define SD_TX_STATUS_REG (* (reg8 *) SD_BSPIM_TxStsReg__STATUS_REG)\r
-#define SD_TX_STATUS_PTR ( (reg8 *) SD_BSPIM_TxStsReg__STATUS_REG)\r
-#define SD_RX_STATUS_REG (* (reg8 *) SD_BSPIM_RxStsReg__STATUS_REG)\r
-#define SD_RX_STATUS_PTR ( (reg8 *) SD_BSPIM_RxStsReg__STATUS_REG)\r
-\r
-#define SD_CONTROL_REG (* (reg8 *) \\r
- SD_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)\r
-#define SD_CONTROL_PTR ( (reg8 *) \\r
- SD_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)\r
-\r
-#define SD_TX_STATUS_MASK_REG (* (reg8 *) SD_BSPIM_TxStsReg__MASK_REG)\r
-#define SD_TX_STATUS_MASK_PTR ( (reg8 *) SD_BSPIM_TxStsReg__MASK_REG)\r
-#define SD_RX_STATUS_MASK_REG (* (reg8 *) SD_BSPIM_RxStsReg__MASK_REG)\r
-#define SD_RX_STATUS_MASK_PTR ( (reg8 *) SD_BSPIM_RxStsReg__MASK_REG)\r
-\r
-#define SD_TX_STATUS_ACTL_REG (* (reg8 *) SD_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)\r
-#define SD_TX_STATUS_ACTL_PTR ( (reg8 *) SD_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)\r
-#define SD_RX_STATUS_ACTL_REG (* (reg8 *) SD_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)\r
-#define SD_RX_STATUS_ACTL_PTR ( (reg8 *) SD_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)\r
-\r
-#if(SD_USE_SECOND_DATAPATH)\r
- #define SD_AUX_CONTROLDP1 (SD_AUX_CONTROL_DP1_REG)\r
-#endif /* (SD_USE_SECOND_DATAPATH) */\r
-\r
-\r
-/***************************************\r
-* Register Constants\r
-***************************************/\r
-\r
-/* Status Register Definitions */\r
-#define SD_STS_SPI_DONE_SHIFT (0x00u)\r
-#define SD_STS_TX_FIFO_EMPTY_SHIFT (0x01u)\r
-#define SD_STS_TX_FIFO_NOT_FULL_SHIFT (0x02u)\r
-#define SD_STS_BYTE_COMPLETE_SHIFT (0x03u)\r
-#define SD_STS_SPI_IDLE_SHIFT (0x04u)\r
-#define SD_STS_RX_FIFO_FULL_SHIFT (0x04u)\r
-#define SD_STS_RX_FIFO_NOT_EMPTY_SHIFT (0x05u)\r
-#define SD_STS_RX_FIFO_OVERRUN_SHIFT (0x06u)\r
-\r
-#define SD_STS_SPI_DONE ((uint8) (0x01u << SD_STS_SPI_DONE_SHIFT))\r
-#define SD_STS_TX_FIFO_EMPTY ((uint8) (0x01u << SD_STS_TX_FIFO_EMPTY_SHIFT))\r
-#define SD_STS_TX_FIFO_NOT_FULL ((uint8) (0x01u << SD_STS_TX_FIFO_NOT_FULL_SHIFT))\r
-#define SD_STS_BYTE_COMPLETE ((uint8) (0x01u << SD_STS_BYTE_COMPLETE_SHIFT))\r
-#define SD_STS_SPI_IDLE ((uint8) (0x01u << SD_STS_SPI_IDLE_SHIFT))\r
-#define SD_STS_RX_FIFO_FULL ((uint8) (0x01u << SD_STS_RX_FIFO_FULL_SHIFT))\r
-#define SD_STS_RX_FIFO_NOT_EMPTY ((uint8) (0x01u << SD_STS_RX_FIFO_NOT_EMPTY_SHIFT))\r
-#define SD_STS_RX_FIFO_OVERRUN ((uint8) (0x01u << SD_STS_RX_FIFO_OVERRUN_SHIFT))\r
-\r
-/* TX and RX masks for clear on read bits */\r
-#define SD_TX_STS_CLR_ON_RD_BYTES_MASK (0x09u)\r
-#define SD_RX_STS_CLR_ON_RD_BYTES_MASK (0x40u)\r
-\r
-/* StatusI Register Interrupt Enable Control Bits */\r
-/* As defined by the Register map for the AUX Control Register */\r
-#define SD_INT_ENABLE (0x10u) /* Enable interrupt from statusi */\r
-#define SD_TX_FIFO_CLR (0x01u) /* F0 - TX FIFO */\r
-#define SD_RX_FIFO_CLR (0x02u) /* F1 - RX FIFO */\r
-#define SD_FIFO_CLR (SD_TX_FIFO_CLR | SD_RX_FIFO_CLR)\r
-\r
-/* Bit Counter (7-bit) Control Register Bit Definitions */\r
-/* As defined by the Register map for the AUX Control Register */\r
-#define SD_CNTR_ENABLE (0x20u) /* Enable CNT7 */\r
-\r
-/* Bi-Directional mode control bit */\r
-#define SD_CTRL_TX_SIGNAL_EN (0x01u)\r
-\r
-/* Datapath Auxillary Control Register definitions */\r
-#define SD_AUX_CTRL_FIFO0_CLR (0x01u)\r
-#define SD_AUX_CTRL_FIFO1_CLR (0x02u)\r
-#define SD_AUX_CTRL_FIFO0_LVL (0x04u)\r
-#define SD_AUX_CTRL_FIFO1_LVL (0x08u)\r
-#define SD_STATUS_ACTL_INT_EN_MASK (0x10u)\r
-\r
-/* Component disabled */\r
-#define SD_DISABLED (0u)\r
-\r
-\r
-/***************************************\r
-* Macros\r
-***************************************/\r
-\r
-/* Returns true if componentn enabled */\r
-#define SD_IS_ENABLED (0u != (SD_TX_STATUS_ACTL_REG & SD_INT_ENABLE))\r
-\r
-/* Retuns TX status register */\r
-#define SD_GET_STATUS_TX(swTxSts) ( (uint8)(SD_TX_STATUS_REG | \\r
- ((swTxSts) & SD_TX_STS_CLR_ON_RD_BYTES_MASK)) )\r
-/* Retuns RX status register */\r
-#define SD_GET_STATUS_RX(swRxSts) ( (uint8)(SD_RX_STATUS_REG | \\r
- ((swRxSts) & SD_RX_STS_CLR_ON_RD_BYTES_MASK)) )\r
-\r
-\r
-/***************************************\r
-* Obsolete definitions\r
-***************************************/\r
-\r
-/* Following definitions are for version compatibility.\r
-* They are obsolete in SPIM v2_30.\r
-* Please do not use it in new projects\r
-*/\r
-\r
-#define SD_WriteByte SD_WriteTxData\r
-#define SD_ReadByte SD_ReadRxData\r
-void SD_SetInterruptMode(uint8 intSrc) ;\r
-uint8 SD_ReadStatus(void) ;\r
-void SD_EnableInt(void) ;\r
-void SD_DisableInt(void) ;\r
-\r
-/* Obsolete register names. Not to be used in new designs */\r
-#define SD_TXDATA (SD_TXDATA_REG)\r
-#define SD_RXDATA (SD_RXDATA_REG)\r
-#define SD_AUX_CONTROLDP0 (SD_AUX_CONTROL_DP0_REG)\r
-#define SD_TXBUFFERREAD (SD_txBufferRead)\r
-#define SD_TXBUFFERWRITE (SD_txBufferWrite)\r
-#define SD_RXBUFFERREAD (SD_rxBufferRead)\r
-#define SD_RXBUFFERWRITE (SD_rxBufferWrite)\r
-\r
-#define SD_COUNTER_PERIOD (SD_COUNTER_PERIOD_REG)\r
-#define SD_COUNTER_CONTROL (SD_COUNTER_CONTROL_REG)\r
-#define SD_STATUS (SD_TX_STATUS_REG)\r
-#define SD_CONTROL (SD_CONTROL_REG)\r
-#define SD_STATUS_MASK (SD_TX_STATUS_MASK_REG)\r
-#define SD_STATUS_ACTL (SD_TX_STATUS_ACTL_REG)\r
-\r
-#define SD_INIT_INTERRUPTS_MASK (SD_INT_ON_SPI_DONE | \\r
- SD_INT_ON_TX_EMPTY | \\r
- SD_INT_ON_TX_NOT_FULL_DEF | \\r
- SD_INT_ON_RX_FULL | \\r
- SD_INT_ON_RX_NOT_EMPTY | \\r
- SD_INT_ON_RX_OVER | \\r
- SD_INT_ON_BYTE_COMP)\r
- \r
-/* Following definitions are for version Compatibility.\r
-* They are obsolete in SPIM v2_40.\r
-* Please do not use it in new projects\r
-*/\r
-\r
-#define SD_DataWidth (SD_DATA_WIDTH)\r
-#define SD_InternalClockUsed (SD_INTERNAL_CLOCK)\r
-#define SD_InternalTxInterruptEnabled (SD_INTERNAL_TX_INT_ENABLED)\r
-#define SD_InternalRxInterruptEnabled (SD_INTERNAL_RX_INT_ENABLED)\r
-#define SD_ModeUseZero (SD_MODE_USE_ZERO)\r
-#define SD_BidirectionalMode (SD_BIDIRECTIONAL_MODE)\r
-#define SD_Mode (SD_MODE)\r
-#define SD_DATAWIDHT (SD_DATA_WIDTH)\r
-#define SD_InternalInterruptEnabled (0u)\r
-\r
-#define SD_TXBUFFERSIZE (SD_TX_BUFFER_SIZE)\r
-#define SD_RXBUFFERSIZE (SD_RX_BUFFER_SIZE)\r
-\r
-#define SD_TXBUFFER SD_txBuffer\r
-#define SD_RXBUFFER SD_rxBuffer\r
-\r
-#endif /* (CY_SPIM_SD_H) */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SD_INT.c\r
-* Version 2.40\r
-*\r
-* Description:\r
-* This file provides all Interrupt Service Routine (ISR) for the SPI Master\r
-* component.\r
-*\r
-* Note:\r
-* None.\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "SD_PVT.h"\r
-\r
-/* User code required at start of ISR */\r
-/* `#START SD_ISR_START_DEF` */\r
-\r
-/* `#END` */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_TX_ISR\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Interrupt Service Routine for TX portion of the SPI Master.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* SD_txBufferWrite - used for the account of the bytes which\r
-* have been written down in the TX software buffer.\r
-* SD_txBufferRead - used for the account of the bytes which\r
-* have been read from the TX software buffer, modified when exist data to\r
-* sending and FIFO Not Full.\r
-* SD_txBuffer[SD_TX_BUFFER_SIZE] - used to store\r
-* data to sending.\r
-* All described above Global variables are used when Software Buffer is used.\r
-*\r
-*******************************************************************************/\r
-CY_ISR(SD_TX_ISR)\r
-{\r
- #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
- uint8 tmpStatus;\r
- #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
- /* User code required at start of ISR */\r
- /* `#START SD_TX_ISR_START` */\r
-\r
- /* `#END` */\r
-\r
- #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
- /* Check if TX data buffer is not empty and there is space in TX FIFO */\r
- while(SD_txBufferRead != SD_txBufferWrite)\r
- {\r
- tmpStatus = SD_GET_STATUS_TX(SD_swStatusTx);\r
- SD_swStatusTx = tmpStatus;\r
-\r
- if(0u != (SD_swStatusTx & SD_STS_TX_FIFO_NOT_FULL))\r
- {\r
- if(0u == SD_txBufferFull)\r
- {\r
- SD_txBufferRead++;\r
-\r
- if(SD_txBufferRead >= SD_TX_BUFFER_SIZE)\r
- {\r
- SD_txBufferRead = 0u;\r
- }\r
- }\r
- else\r
- {\r
- SD_txBufferFull = 0u;\r
- }\r
-\r
- /* Move data from the Buffer to the FIFO */\r
- CY_SET_REG8(SD_TXDATA_PTR,\r
- SD_txBuffer[SD_txBufferRead]);\r
- }\r
- else\r
- {\r
- break;\r
- }\r
- }\r
-\r
- if(SD_txBufferRead == SD_txBufferWrite)\r
- {\r
- /* TX Buffer is EMPTY: disable interrupt on TX NOT FULL */\r
- SD_TX_STATUS_MASK_REG &= ((uint8) ~SD_STS_TX_FIFO_NOT_FULL);\r
- }\r
-\r
- #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
- /* User code required at end of ISR (Optional) */\r
- /* `#START SD_TX_ISR_END` */\r
-\r
- /* `#END` */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_RX_ISR\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Interrupt Service Routine for RX portion of the SPI Master.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global variables:\r
-* SD_rxBufferWrite - used for the account of the bytes which\r
-* have been written down in the RX software buffer modified when FIFO contains\r
-* new data.\r
-* SD_rxBufferRead - used for the account of the bytes which\r
-* have been read from the RX software buffer, modified when overflow occurred.\r
-* SD_rxBuffer[SD_RX_BUFFER_SIZE] - used to store\r
-* received data, modified when FIFO contains new data.\r
-* All described above Global variables are used when Software Buffer is used.\r
-*\r
-*******************************************************************************/\r
-CY_ISR(SD_RX_ISR)\r
-{\r
- #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
- uint8 tmpStatus;\r
- uint8 rxData;\r
- #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
- /* User code required at start of ISR */\r
- /* `#START SD_RX_ISR_START` */\r
-\r
- /* `#END` */\r
-\r
- #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
-\r
- tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx);\r
- SD_swStatusRx = tmpStatus;\r
-\r
- /* Check if RX data FIFO has some data to be moved into the RX Buffer */\r
- while(0u != (SD_swStatusRx & SD_STS_RX_FIFO_NOT_EMPTY))\r
- {\r
- rxData = CY_GET_REG8(SD_RXDATA_PTR);\r
-\r
- /* Set next pointer. */\r
- SD_rxBufferWrite++;\r
- if(SD_rxBufferWrite >= SD_RX_BUFFER_SIZE)\r
- {\r
- SD_rxBufferWrite = 0u;\r
- }\r
-\r
- if(SD_rxBufferWrite == SD_rxBufferRead)\r
- {\r
- SD_rxBufferRead++;\r
- if(SD_rxBufferRead >= SD_RX_BUFFER_SIZE)\r
- {\r
- SD_rxBufferRead = 0u;\r
- }\r
-\r
- SD_rxBufferFull = 1u;\r
- }\r
-\r
- /* Move data from the FIFO to the Buffer */\r
- SD_rxBuffer[SD_rxBufferWrite] = rxData;\r
-\r
- tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx);\r
- SD_swStatusRx = tmpStatus;\r
- }\r
-\r
- #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
- /* User code required at end of ISR (Optional) */\r
- /* `#START SD_RX_ISR_END` */\r
-\r
- /* `#END` */\r
-}\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SD_IntClock.c\r
-* Version 2.0\r
-*\r
-* Description:\r
-* This file provides the source code to the API for the clock component.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include <cydevice_trm.h>\r
-#include "SD_IntClock.h"\r
-\r
-/* Clock Distribution registers. */\r
-#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD)\r
-#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2)\r
-#define BCFG2_MASK (0x80u)\r
-#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK)\r
-#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK)\r
-\r
-#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP)\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_Start\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Starts the clock. Note that on startup, clocks may be already running if the\r
-* "Start on Reset" option is enabled in the DWR.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_Start(void) \r
-{\r
- /* Set the bit to enable the clock. */\r
- SD_IntClock_CLKEN |= SD_IntClock_CLKEN_MASK;\r
- SD_IntClock_CLKSTBY |= SD_IntClock_CLKSTBY_MASK;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_Stop\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Stops the clock and returns immediately. This API does not require the\r
-* source clock to be running but may return before the hardware is actually\r
-* disabled. If the settings of the clock are changed after calling this\r
-* function, the clock may glitch when it is started. To avoid the clock\r
-* glitch, use the StopBlock function.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_Stop(void) \r
-{\r
- /* Clear the bit to disable the clock. */\r
- SD_IntClock_CLKEN &= (uint8)(~SD_IntClock_CLKEN_MASK);\r
- SD_IntClock_CLKSTBY &= (uint8)(~SD_IntClock_CLKSTBY_MASK);\r
-}\r
-\r
-\r
-#if(CY_PSOC3 || CY_PSOC5LP)\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_StopBlock\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Stops the clock and waits for the hardware to actually be disabled before\r
-* returning. This ensures that the clock is never truncated (high part of the\r
-* cycle will terminate before the clock is disabled and the API returns).\r
-* Note that the source clock must be running or this API will never return as\r
-* a stopped clock cannot be disabled.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_StopBlock(void) \r
-{\r
- if ((SD_IntClock_CLKEN & SD_IntClock_CLKEN_MASK) != 0u)\r
- {\r
-#if HAS_CLKDIST_LD_DISABLE\r
- uint16 oldDivider;\r
-\r
- CLK_DIST_LD = 0u;\r
-\r
- /* Clear all the mask bits except ours. */\r
-#if defined(SD_IntClock__CFG3)\r
- CLK_DIST_AMASK = SD_IntClock_CLKEN_MASK;\r
- CLK_DIST_DMASK = 0x00u;\r
-#else\r
- CLK_DIST_DMASK = SD_IntClock_CLKEN_MASK;\r
- CLK_DIST_AMASK = 0x00u;\r
-#endif /* SD_IntClock__CFG3 */\r
-\r
- /* Clear mask of bus clock. */\r
- CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);\r
-\r
- oldDivider = CY_GET_REG16(SD_IntClock_DIV_PTR);\r
- CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);\r
- CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;\r
-\r
- /* Wait for clock to be disabled */\r
- while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
-#endif /* HAS_CLKDIST_LD_DISABLE */\r
-\r
- /* Clear the bit to disable the clock. */\r
- SD_IntClock_CLKEN &= (uint8)(~SD_IntClock_CLKEN_MASK);\r
- SD_IntClock_CLKSTBY &= (uint8)(~SD_IntClock_CLKSTBY_MASK);\r
-\r
-#if HAS_CLKDIST_LD_DISABLE\r
- /* Clear the disable bit */\r
- CLK_DIST_LD = 0x00u;\r
- CY_SET_REG16(SD_IntClock_DIV_PTR, oldDivider);\r
-#endif /* HAS_CLKDIST_LD_DISABLE */\r
- }\r
-}\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_StandbyPower\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Sets whether the clock is active in standby mode.\r
-*\r
-* Parameters:\r
-* state: 0 to disable clock during standby, nonzero to enable.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_StandbyPower(uint8 state) \r
-{\r
- if(state == 0u)\r
- {\r
- SD_IntClock_CLKSTBY &= (uint8)(~SD_IntClock_CLKSTBY_MASK);\r
- }\r
- else\r
- {\r
- SD_IntClock_CLKSTBY |= SD_IntClock_CLKSTBY_MASK;\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_SetDividerRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Modifies the clock divider and, thus, the frequency. When the clock divider\r
-* register is set to zero or changed from zero, the clock will be temporarily\r
-* disabled in order to change the SSS mode bit. If the clock is enabled when\r
-* SetDividerRegister is called, then the source clock must be running.\r
-*\r
-* Parameters:\r
-* clkDivider: Divider register value (0-65,535). This value is NOT the\r
-* divider; the clock hardware divides by clkDivider plus one. For example,\r
-* to divide the clock by 2, this parameter should be set to 1.\r
-* restart: If nonzero, restarts the clock divider: the current clock cycle\r
-* will be truncated and the new divide value will take effect immediately. If\r
-* zero, the new divide value will take effect at the end of the current clock\r
-* cycle.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_SetDividerRegister(uint16 clkDivider, uint8 restart)\r
- \r
-{\r
- uint8 enabled;\r
-\r
- uint8 currSrc = SD_IntClock_GetSourceRegister();\r
- uint16 oldDivider = SD_IntClock_GetDividerRegister();\r
-\r
- if (clkDivider != oldDivider)\r
- {\r
- enabled = SD_IntClock_CLKEN & SD_IntClock_CLKEN_MASK;\r
-\r
- if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))\r
- {\r
- /* Moving to/from SSS requires correct ordering to prevent halting the clock */\r
- if (oldDivider == 0u)\r
- {\r
- /* Moving away from SSS, set the divider first so when SSS is cleared we */\r
- /* don't halt the clock. Using the shadow load isn't required as the */\r
- /* divider is ignored while SSS is set. */\r
- CY_SET_REG16(SD_IntClock_DIV_PTR, clkDivider);\r
- SD_IntClock_MOD_SRC &= (uint8)(~CYCLK_SSS);\r
- }\r
- else\r
- {\r
- /* Moving to SSS, set SSS which then ignores the divider and we can set */\r
- /* it without bothering with the shadow load. */\r
- SD_IntClock_MOD_SRC |= CYCLK_SSS;\r
- CY_SET_REG16(SD_IntClock_DIV_PTR, clkDivider);\r
- }\r
- }\r
- else\r
- {\r
- \r
- if (enabled != 0u)\r
- {\r
- CLK_DIST_LD = 0x00u;\r
-\r
- /* Clear all the mask bits except ours. */\r
-#if defined(SD_IntClock__CFG3)\r
- CLK_DIST_AMASK = SD_IntClock_CLKEN_MASK;\r
- CLK_DIST_DMASK = 0x00u;\r
-#else\r
- CLK_DIST_DMASK = SD_IntClock_CLKEN_MASK;\r
- CLK_DIST_AMASK = 0x00u;\r
-#endif /* SD_IntClock__CFG3 */\r
- /* Clear mask of bus clock. */\r
- CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);\r
-\r
- /* If clock is currently enabled, disable it if async or going from N-to-1*/\r
- if (((SD_IntClock_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))\r
- {\r
-#if HAS_CLKDIST_LD_DISABLE\r
- CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);\r
- CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;\r
-\r
- /* Wait for clock to be disabled */\r
- while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
-#endif /* HAS_CLKDIST_LD_DISABLE */\r
-\r
- SD_IntClock_CLKEN &= (uint8)(~SD_IntClock_CLKEN_MASK);\r
-\r
-#if HAS_CLKDIST_LD_DISABLE\r
- /* Clear the disable bit */\r
- CLK_DIST_LD = 0x00u;\r
-#endif /* HAS_CLKDIST_LD_DISABLE */\r
- }\r
- }\r
-\r
- /* Load divide value. */\r
- if ((SD_IntClock_CLKEN & SD_IntClock_CLKEN_MASK) != 0u)\r
- {\r
- /* If the clock is still enabled, use the shadow registers */\r
- CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);\r
-\r
- CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));\r
- while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
- }\r
- else\r
- {\r
- /* If the clock is disabled, set the divider directly */\r
- CY_SET_REG16(SD_IntClock_DIV_PTR, clkDivider);\r
- SD_IntClock_CLKEN |= enabled;\r
- }\r
- }\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_GetDividerRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Gets the clock divider register value.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* Divide value of the clock minus 1. For example, if the clock is set to\r
-* divide by 2, the return value will be 1.\r
-*\r
-*******************************************************************************/\r
-uint16 SD_IntClock_GetDividerRegister(void) \r
-{\r
- return CY_GET_REG16(SD_IntClock_DIV_PTR);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_SetModeRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Sets flags that control the operating mode of the clock. This function only\r
-* changes flags from 0 to 1; flags that are already 1 will remain unchanged.\r
-* To clear flags, use the ClearModeRegister function. The clock must be\r
-* disabled before changing the mode.\r
-*\r
-* Parameters:\r
-* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,\r
-* clkMode should be a set of the following optional bits or'ed together.\r
-* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will\r
-* occur when the divider count reaches half of the divide\r
-* value.\r
-* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock\r
-* is asserted for approximately half of its period. When\r
-* disabled, the output clock is asserted for one period of the\r
-* source clock.\r
-* - CYCLK_SYNC Enable output synchronization to master clock. This should\r
-* be enabled for all synchronous clocks.\r
-* See the Technical Reference Manual for details about setting the mode of\r
-* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_SetModeRegister(uint8 modeBitMask) \r
-{\r
- SD_IntClock_MOD_SRC |= modeBitMask & (uint8)SD_IntClock_MODE_MASK;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_ClearModeRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Clears flags that control the operating mode of the clock. This function\r
-* only changes flags from 1 to 0; flags that are already 0 will remain\r
-* unchanged. To set flags, use the SetModeRegister function. The clock must be\r
-* disabled before changing the mode.\r
-*\r
-* Parameters:\r
-* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,\r
-* clkMode should be a set of the following optional bits or'ed together.\r
-* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will\r
-* occur when the divider count reaches half of the divide\r
-* value.\r
-* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock\r
-* is asserted for approximately half of its period. When\r
-* disabled, the output clock is asserted for one period of the\r
-* source clock.\r
-* - CYCLK_SYNC Enable output synchronization to master clock. This should\r
-* be enabled for all synchronous clocks.\r
-* See the Technical Reference Manual for details about setting the mode of\r
-* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_ClearModeRegister(uint8 modeBitMask) \r
-{\r
- SD_IntClock_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_IntClock_MODE_MASK));\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_GetModeRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Gets the clock mode register value.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* Bit mask representing the enabled mode bits. See the SetModeRegister and\r
-* ClearModeRegister descriptions for details about the mode bits.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_IntClock_GetModeRegister(void) \r
-{\r
- return SD_IntClock_MOD_SRC & (uint8)(SD_IntClock_MODE_MASK);\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_SetSourceRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Sets the input source of the clock. The clock must be disabled before\r
-* changing the source. The old and new clock sources must be running.\r
-*\r
-* Parameters:\r
-* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the\r
-* following input sources:\r
-* - CYCLK_SRC_SEL_SYNC_DIG\r
-* - CYCLK_SRC_SEL_IMO\r
-* - CYCLK_SRC_SEL_XTALM\r
-* - CYCLK_SRC_SEL_ILO\r
-* - CYCLK_SRC_SEL_PLL\r
-* - CYCLK_SRC_SEL_XTALK\r
-* - CYCLK_SRC_SEL_DSI_G\r
-* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A\r
-* See the Technical Reference Manual for details on clock sources.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_SetSourceRegister(uint8 clkSource) \r
-{\r
- uint16 currDiv = SD_IntClock_GetDividerRegister();\r
- uint8 oldSrc = SD_IntClock_GetSourceRegister();\r
-\r
- if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && \r
- (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))\r
- {\r
- /* Switching to Master and divider is 1, set SSS, which will output master, */\r
- /* then set the source so we are consistent. */\r
- SD_IntClock_MOD_SRC |= CYCLK_SSS;\r
- SD_IntClock_MOD_SRC =\r
- (SD_IntClock_MOD_SRC & (uint8)(~SD_IntClock_SRC_SEL_MSK)) | clkSource;\r
- }\r
- else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && \r
- (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))\r
- {\r
- /* Switching from Master to not and divider is 1, set source, so we don't */\r
- /* lock when we clear SSS. */\r
- SD_IntClock_MOD_SRC =\r
- (SD_IntClock_MOD_SRC & (uint8)(~SD_IntClock_SRC_SEL_MSK)) | clkSource;\r
- SD_IntClock_MOD_SRC &= (uint8)(~CYCLK_SSS);\r
- }\r
- else\r
- {\r
- SD_IntClock_MOD_SRC =\r
- (SD_IntClock_MOD_SRC & (uint8)(~SD_IntClock_SRC_SEL_MSK)) | clkSource;\r
- }\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_GetSourceRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Gets the input source of the clock.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* The input source of the clock. See SetSourceRegister for details.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_IntClock_GetSourceRegister(void) \r
-{\r
- return SD_IntClock_MOD_SRC & SD_IntClock_SRC_SEL_MSK;\r
-}\r
-\r
-\r
-#if defined(SD_IntClock__CFG3)\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_SetPhaseRegister\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Sets the phase delay of the analog clock. This function is only available\r
-* for analog clocks. The clock must be disabled before changing the phase\r
-* delay to avoid glitches.\r
-*\r
-* Parameters:\r
-* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.\r
-* clkPhase must be from 1 to 11 inclusive. Other values, including 0,\r
-* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 \r
-* produces a 10ns delay.\r
-*\r
-* Returns:\r
-* None\r
-*\r
-*******************************************************************************/\r
-void SD_IntClock_SetPhaseRegister(uint8 clkPhase) \r
-{\r
- SD_IntClock_PHASE = clkPhase & SD_IntClock_PHASE_MASK;\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_IntClock_GetPhase\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Gets the phase delay of the analog clock. This function is only available\r
-* for analog clocks.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* Phase of the analog clock. See SetPhaseRegister for details.\r
-*\r
-*******************************************************************************/\r
-uint8 SD_IntClock_GetPhaseRegister(void) \r
-{\r
- return SD_IntClock_PHASE & SD_IntClock_PHASE_MASK;\r
-}\r
-\r
-#endif /* SD_IntClock__CFG3 */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SD_IntClock.h\r
-* Version 2.0\r
-*\r
-* Description:\r
-* Provides the function and constant definitions for the clock component.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions, \r
-* disclaimers, and limitations in the end user license agreement accompanying \r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_CLOCK_SD_IntClock_H)\r
-#define CY_CLOCK_SD_IntClock_H\r
-\r
-#include <cytypes.h>\r
-#include <cyfitter.h>\r
-\r
-\r
-/***************************************\r
-* Conditional Compilation Parameters\r
-***************************************/\r
-\r
-/* Check to see if required defines such as CY_PSOC5LP are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5LP)\r
- #error Component cy_clock_v2_0 requires cy_boot v3.0 or later\r
-#endif /* (CY_PSOC5LP) */\r
-\r
-\r
-/***************************************\r
-* Function Prototypes\r
-***************************************/\r
-\r
-void SD_IntClock_Start(void) ;\r
-void SD_IntClock_Stop(void) ;\r
-\r
-#if(CY_PSOC3 || CY_PSOC5LP)\r
-void SD_IntClock_StopBlock(void) ;\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
-\r
-void SD_IntClock_StandbyPower(uint8 state) ;\r
-void SD_IntClock_SetDividerRegister(uint16 clkDivider, uint8 restart) \r
- ;\r
-uint16 SD_IntClock_GetDividerRegister(void) ;\r
-void SD_IntClock_SetModeRegister(uint8 modeBitMask) ;\r
-void SD_IntClock_ClearModeRegister(uint8 modeBitMask) ;\r
-uint8 SD_IntClock_GetModeRegister(void) ;\r
-void SD_IntClock_SetSourceRegister(uint8 clkSource) ;\r
-uint8 SD_IntClock_GetSourceRegister(void) ;\r
-#if defined(SD_IntClock__CFG3)\r
-void SD_IntClock_SetPhaseRegister(uint8 clkPhase) ;\r
-uint8 SD_IntClock_GetPhaseRegister(void) ;\r
-#endif /* defined(SD_IntClock__CFG3) */\r
-\r
-#define SD_IntClock_Enable() SD_IntClock_Start()\r
-#define SD_IntClock_Disable() SD_IntClock_Stop()\r
-#define SD_IntClock_SetDivider(clkDivider) SD_IntClock_SetDividerRegister(clkDivider, 1)\r
-#define SD_IntClock_SetDividerValue(clkDivider) SD_IntClock_SetDividerRegister((clkDivider) - 1, 1)\r
-#define SD_IntClock_SetMode(clkMode) SD_IntClock_SetModeRegister(clkMode)\r
-#define SD_IntClock_SetSource(clkSource) SD_IntClock_SetSourceRegister(clkSource)\r
-#if defined(SD_IntClock__CFG3)\r
-#define SD_IntClock_SetPhase(clkPhase) SD_IntClock_SetPhaseRegister(clkPhase)\r
-#define SD_IntClock_SetPhaseValue(clkPhase) SD_IntClock_SetPhaseRegister((clkPhase) + 1)\r
-#endif /* defined(SD_IntClock__CFG3) */\r
-\r
-\r
-/***************************************\r
-* Registers\r
-***************************************/\r
-\r
-/* Register to enable or disable the clock */\r
-#define SD_IntClock_CLKEN (* (reg8 *) SD_IntClock__PM_ACT_CFG)\r
-#define SD_IntClock_CLKEN_PTR ((reg8 *) SD_IntClock__PM_ACT_CFG)\r
-\r
-/* Register to enable or disable the clock */\r
-#define SD_IntClock_CLKSTBY (* (reg8 *) SD_IntClock__PM_STBY_CFG)\r
-#define SD_IntClock_CLKSTBY_PTR ((reg8 *) SD_IntClock__PM_STBY_CFG)\r
-\r
-/* Clock LSB divider configuration register. */\r
-#define SD_IntClock_DIV_LSB (* (reg8 *) SD_IntClock__CFG0)\r
-#define SD_IntClock_DIV_LSB_PTR ((reg8 *) SD_IntClock__CFG0)\r
-#define SD_IntClock_DIV_PTR ((reg16 *) SD_IntClock__CFG0)\r
-\r
-/* Clock MSB divider configuration register. */\r
-#define SD_IntClock_DIV_MSB (* (reg8 *) SD_IntClock__CFG1)\r
-#define SD_IntClock_DIV_MSB_PTR ((reg8 *) SD_IntClock__CFG1)\r
-\r
-/* Mode and source configuration register */\r
-#define SD_IntClock_MOD_SRC (* (reg8 *) SD_IntClock__CFG2)\r
-#define SD_IntClock_MOD_SRC_PTR ((reg8 *) SD_IntClock__CFG2)\r
-\r
-#if defined(SD_IntClock__CFG3)\r
-/* Analog clock phase configuration register */\r
-#define SD_IntClock_PHASE (* (reg8 *) SD_IntClock__CFG3)\r
-#define SD_IntClock_PHASE_PTR ((reg8 *) SD_IntClock__CFG3)\r
-#endif /* defined(SD_IntClock__CFG3) */\r
-\r
-\r
-/**************************************\r
-* Register Constants\r
-**************************************/\r
-\r
-/* Power manager register masks */\r
-#define SD_IntClock_CLKEN_MASK SD_IntClock__PM_ACT_MSK\r
-#define SD_IntClock_CLKSTBY_MASK SD_IntClock__PM_STBY_MSK\r
-\r
-/* CFG2 field masks */\r
-#define SD_IntClock_SRC_SEL_MSK SD_IntClock__CFG2_SRC_SEL_MASK\r
-#define SD_IntClock_MODE_MASK (~(SD_IntClock_SRC_SEL_MSK))\r
-\r
-#if defined(SD_IntClock__CFG3)\r
-/* CFG3 phase mask */\r
-#define SD_IntClock_PHASE_MASK SD_IntClock__CFG3_PHASE_DLY_MASK\r
-#endif /* defined(SD_IntClock__CFG3) */\r
-\r
-#endif /* CY_CLOCK_SD_IntClock_H */\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: SD_PM.c\r
-* Version 2.40\r
-*\r
-* Description:\r
-* This file contains the setup, control and status commands to support\r
-* component operations in low power mode.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#include "SD_PVT.h"\r
-\r
-static SD_BACKUP_STRUCT SD_backup =\r
-{\r
- SD_DISABLED,\r
- SD_BITCTR_INIT,\r
- #if(CY_UDB_V0)\r
- SD_TX_INIT_INTERRUPTS_MASK,\r
- SD_RX_INIT_INTERRUPTS_MASK\r
- #endif /* CY_UDB_V0 */\r
-};\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_SaveConfig\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Saves SPIM configuration.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global Variables:\r
-* SD_backup - modified when non-retention registers are saved.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void SD_SaveConfig(void) \r
-{\r
- /* Store Status Mask registers */\r
- #if(CY_UDB_V0)\r
- SD_backup.cntrPeriod = SD_COUNTER_PERIOD_REG;\r
- SD_backup.saveSrTxIntMask = SD_TX_STATUS_MASK_REG;\r
- SD_backup.saveSrRxIntMask = SD_RX_STATUS_MASK_REG;\r
- #endif /* (CY_UDB_V0) */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_RestoreConfig\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Restores SPIM configuration.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global Variables:\r
-* SD_backup - used when non-retention registers are restored.\r
-*\r
-* Side Effects:\r
-* If this API is called without first calling SaveConfig then in the following\r
-* registers will be default values from Customizer:\r
-* SD_STATUS_MASK_REG and SD_COUNTER_PERIOD_REG.\r
-*\r
-*******************************************************************************/\r
-void SD_RestoreConfig(void) \r
-{\r
- /* Restore the data, saved by SaveConfig() function */\r
- #if(CY_UDB_V0)\r
- SD_COUNTER_PERIOD_REG = SD_backup.cntrPeriod;\r
- SD_TX_STATUS_MASK_REG = ((uint8) SD_backup.saveSrTxIntMask);\r
- SD_RX_STATUS_MASK_REG = ((uint8) SD_backup.saveSrRxIntMask);\r
- #endif /* (CY_UDB_V0) */\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Sleep\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Prepare SPIM Component goes to sleep.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global Variables:\r
-* SD_backup - modified when non-retention registers are saved.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void SD_Sleep(void) \r
-{\r
- /* Save components enable state */\r
- SD_backup.enableState = ((uint8) SD_IS_ENABLED);\r
-\r
- SD_Stop();\r
- SD_SaveConfig();\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: SD_Wakeup\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Prepare SPIM Component to wake up.\r
-*\r
-* Parameters:\r
-* None.\r
-*\r
-* Return:\r
-* None.\r
-*\r
-* Global Variables:\r
-* SD_backup - used when non-retention registers are restored.\r
-* SD_txBufferWrite - modified every function call - resets to\r
-* zero.\r
-* SD_txBufferRead - modified every function call - resets to\r
-* zero.\r
-* SD_rxBufferWrite - modified every function call - resets to\r
-* zero.\r
-* SD_rxBufferRead - modified every function call - resets to\r
-* zero.\r
-*\r
-* Reentrant:\r
-* No.\r
-*\r
-*******************************************************************************/\r
-void SD_Wakeup(void) \r
-{\r
- SD_RestoreConfig();\r
-\r
- #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
- SD_rxBufferFull = 0u;\r
- SD_rxBufferRead = 0u;\r
- SD_rxBufferWrite = 0u;\r
- #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
- #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
- SD_txBufferFull = 0u;\r
- SD_txBufferRead = 0u;\r
- SD_txBufferWrite = 0u;\r
- #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
- /* Clear any data from the RX and TX FIFO */\r
- SD_ClearFIFO();\r
-\r
- /* Restore components block enable state */\r
- if(0u != SD_backup.enableState)\r
- {\r
- SD_Enable();\r
- }\r
-}\r
-\r
-\r
-/* [] END OF FILE */\r
+++ /dev/null
-/*******************************************************************************\r
-* File Name: .h\r
-* Version 2.40\r
-*\r
-* Description:\r
-* This private header file contains internal definitions for the SPIM\r
-* component. Do not use these definitions directly in your application.\r
-*\r
-* Note:\r
-*\r
-********************************************************************************\r
-* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved.\r
-* You may use this file only in accordance with the license, terms, conditions,\r
-* disclaimers, and limitations in the end user license agreement accompanying\r
-* the software package with which this file was provided.\r
-*******************************************************************************/\r
-\r
-#if !defined(CY_SPIM_PVT_SD_H)\r
-#define CY_SPIM_PVT_SD_H\r
-\r
-#include "SD.h"\r
-\r
-\r
-/**********************************\r
-* Functions with external linkage\r
-**********************************/\r
-\r
-\r
-/**********************************\r
-* Variables with external linkage\r
-**********************************/\r
-\r
-extern volatile uint8 SD_swStatusTx;\r
-extern volatile uint8 SD_swStatusRx;\r
-\r
-#if(SD_TX_SOFTWARE_BUF_ENABLED)\r
- extern volatile uint8 SD_txBuffer[SD_TX_BUFFER_SIZE];\r
- extern volatile uint8 SD_txBufferRead;\r
- extern volatile uint8 SD_txBufferWrite;\r
- extern volatile uint8 SD_txBufferFull;\r
-#endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
-\r
-#if(SD_RX_SOFTWARE_BUF_ENABLED)\r
- extern volatile uint8 SD_rxBuffer[SD_RX_BUFFER_SIZE];\r
- extern volatile uint8 SD_rxBufferRead;\r
- extern volatile uint8 SD_rxBufferWrite;\r
- extern volatile uint8 SD_rxBufferFull;\r
-#endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
-\r
-#endif /* CY_SPIM_PVT_SD_H */\r
-\r
-\r
-/* [] END OF FILE */\r
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+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cm3.c\r
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
- * @version V1.30\r
- * @date 30. October 2009\r
- *\r
- * @note\r
- * Copyright (C) 2009 ARM Limited. All rights reserved.\r
- *\r
- * @par\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
- * processor based microcontrollers. This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
- *\r
- ******************************************************************************/\r
-\r
-#include <stdint.h>\r
-\r
-/* define compiler specific symbols */\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
-\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
-\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
-\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
-\r
-#endif\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-__ASM uint32_t __get_PSP(void)\r
-{\r
- mrs r0, psp\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-__ASM void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- msr psp, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-__ASM uint32_t __get_MSP(void)\r
-{\r
- mrs r0, msp\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-__ASM void __set_MSP(uint32_t mainStackPointer)\r
-{\r
- msr msp, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-__ASM uint32_t __REV16(uint16_t value)\r
-{\r
- rev16 r0, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-__ASM int32_t __REVSH(int16_t value)\r
-{\r
- revsh r0, r0\r
- bx lr\r
-}\r
-\r
-\r
-#if (__ARMCC_VERSION < 400000)\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-__ASM void __CLREX(void)\r
-{\r
- clrex\r
-}\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-__ASM uint32_t __get_BASEPRI(void)\r
-{\r
- mrs r0, basepri\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-__ASM void __set_BASEPRI(uint32_t basePri)\r
-{\r
- msr basepri, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-__ASM uint32_t __get_PRIMASK(void)\r
-{\r
- mrs r0, primask\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-__ASM void __set_PRIMASK(uint32_t priMask)\r
-{\r
- msr primask, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-__ASM uint32_t __get_FAULTMASK(void)\r
-{\r
- mrs r0, faultmask\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-__ASM void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- msr faultmask, r0\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-__ASM uint32_t __get_CONTROL(void)\r
-{\r
- mrs r0, control\r
- bx lr\r
-}\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-__ASM void __set_CONTROL(uint32_t control)\r
-{\r
- msr control, r0\r
- bx lr\r
-}\r
-\r
-#endif /* __ARMCC_VERSION */ \r
-\r
-\r
-\r
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-#pragma diag_suppress=Pe940\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-uint32_t __get_PSP(void)\r
-{\r
- __ASM("mrs r0, psp");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- __ASM("msr psp, r0");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-uint32_t __get_MSP(void)\r
-{\r
- __ASM("mrs r0, msp");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- __ASM("msr msp, r0");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-uint32_t __REV16(uint16_t value)\r
-{\r
- __ASM("rev16 r0, r0");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-uint32_t __RBIT(uint32_t value)\r
-{\r
- __ASM("rbit r0, r0");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive (8 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit values)\r
- */\r
-uint8_t __LDREXB(uint8_t *addr)\r
-{\r
- __ASM("ldrexb r0, [r0]");\r
- __ASM("bx lr"); \r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive (16 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-uint16_t __LDREXH(uint16_t *addr)\r
-{\r
- __ASM("ldrexh r0, [r0]");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive (32 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-uint32_t __LDREXW(uint32_t *addr)\r
-{\r
- __ASM("ldrex r0, [r0]");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive (8 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
-{\r
- __ASM("strexb r0, r0, [r1]");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive (16 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
-{\r
- __ASM("strexh r0, r0, [r1]");\r
- __ASM("bx lr");\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive (32 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
-{\r
- __ASM("strex r0, r0, [r1]");\r
- __ASM("bx lr");\r
-}\r
-\r
-#pragma diag_default=Pe940\r
-\r
-\r
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-uint32_t __get_PSP(void) __attribute__( ( naked ) );\r
-uint32_t __get_PSP(void)\r
-{\r
- uint32_t result=0;\r
-\r
- __ASM volatile ("MRS %0, psp\n\t" \r
- "MOV r0, %0 \n\t"\r
- "BX lr \n\t" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );\r
-void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- __ASM volatile ("MSR psp, %0\n\t"\r
- "BX lr \n\t" : : "r" (topOfProcStack) );\r
-}\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-uint32_t __get_MSP(void) __attribute__( ( naked ) );\r
-uint32_t __get_MSP(void)\r
-{\r
- uint32_t result=0;\r
-\r
- __ASM volatile ("MRS %0, msp\n\t" \r
- "MOV r0, %0 \n\t"\r
- "BX lr \n\t" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );\r
-void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- __ASM volatile ("MSR msp, %0\n\t"\r
- "BX lr \n\t" : : "r" (topOfMainStack) );\r
-}\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-uint32_t __get_BASEPRI(void)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-void __set_BASEPRI(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
-}\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-uint32_t __get_PRIMASK(void)\r
-{\r
- uint32_t result=0;\r
-\r
- __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-void __set_PRIMASK(uint32_t priMask)\r
-{\r
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
-}\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-uint32_t __get_FAULTMASK(void)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
-}\r
-\r
-/**\r
- * @brief Return the Control Register value\r
-* \r
-* @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-uint32_t __get_CONTROL(void)\r
-{\r
- uint32_t result=0;\r
-\r
- __ASM volatile ("MRS %0, control" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-void __set_CONTROL(uint32_t control)\r
-{\r
- __ASM volatile ("MSR control, %0" : : "r" (control) );\r
-}\r
-\r
-\r
-/**\r
- * @brief Reverse byte order in integer value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in integer value\r
- */\r
-uint32_t __REV(uint32_t value)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-uint32_t __REV16(uint16_t value)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-int32_t __REVSH(int16_t value)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-uint32_t __RBIT(uint32_t value)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive (8 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit value\r
- */\r
-uint8_t __LDREXB(uint8_t *addr)\r
-{\r
- uint8_t result=0;\r
- \r
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive (16 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-uint16_t __LDREXH(uint16_t *addr)\r
-{\r
- uint16_t result=0;\r
- \r
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief LDR Exclusive (32 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-uint32_t __LDREXW(uint32_t *addr)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive (8 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive (16 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
- return(result);\r
-}\r
-\r
-/**\r
- * @brief STR Exclusive (32 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
-{\r
- uint32_t result=0;\r
- \r
- __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE\r
#define CYDEV_FLS_SECTOR_SIZE 0x00010000u\r
#define CYDEV_FLS_ROW_SIZE 0x00000100u\r
+#define CYDEV_ALLOCATE_EEPROM 0x00000001u\r
#define CYDEV_ECC_SECTOR_SIZE 0x00002000u\r
#define CYDEV_ECC_ROW_SIZE 0x00000020u\r
#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u\r
#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE\r
#define CYDEV_FLS_SECTOR_SIZE 0x00010000u\r
#define CYDEV_FLS_ROW_SIZE 0x00000100u\r
+#define CYDEV_ALLOCATE_EEPROM 0x00000001u\r
#define CYDEV_ECC_SECTOR_SIZE 0x00002000u\r
#define CYDEV_ECC_ROW_SIZE 0x00000020u\r
#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u\r
.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE\r
.set CYDEV_FLS_SECTOR_SIZE, 0x00010000\r
.set CYDEV_FLS_ROW_SIZE, 0x00000100\r
+.set CYDEV_ALLOCATE_EEPROM, 0x00000001\r
.set CYDEV_ECC_SECTOR_SIZE, 0x00002000\r
.set CYDEV_ECC_ROW_SIZE, 0x00000020\r
.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400\r
.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE\r
.set CYDEV_FLS_SECTOR_SIZE, 0x00010000\r
.set CYDEV_FLS_ROW_SIZE, 0x00000100\r
+.set CYDEV_ALLOCATE_EEPROM, 0x00000001\r
.set CYDEV_ECC_SECTOR_SIZE, 0x00002000\r
.set CYDEV_ECC_ROW_SIZE, 0x00000020\r
.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400\r
#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE\r
#define CYDEV_FLS_SECTOR_SIZE 0x00010000\r
#define CYDEV_FLS_ROW_SIZE 0x00000100\r
+#define CYDEV_ALLOCATE_EEPROM 0x00000001\r
#define CYDEV_ECC_SECTOR_SIZE 0x00002000\r
#define CYDEV_ECC_ROW_SIZE 0x00000020\r
#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400\r
#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE\r
#define CYDEV_FLS_SECTOR_SIZE 0x00010000\r
#define CYDEV_FLS_ROW_SIZE 0x00000100\r
+#define CYDEV_ALLOCATE_EEPROM 0x00000001\r
#define CYDEV_ECC_SECTOR_SIZE 0x00002000\r
#define CYDEV_ECC_ROW_SIZE 0x00000020\r
#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400\r
ENDIF\r
IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE\r
CYDEV_FLS_ROW_SIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ALLOCATE_EEPROM\r
+CYDEV_ALLOCATE_EEPROM EQU 0x00000001\r
ENDIF\r
IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE\r
CYDEV_ECC_SECTOR_SIZE EQU 0x00002000\r
ENDIF\r
IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE\r
CYDEV_FLS_ROW_SIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ALLOCATE_EEPROM\r
+CYDEV_ALLOCATE_EEPROM EQU 0x00000001\r
ENDIF\r
IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE\r
CYDEV_ECC_SECTOR_SIZE EQU 0x00002000\r
/* SCSI_ATN_ISR */\r
#define SCSI_ATN_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_ATN_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_ATN_ISR__INTC_MASK 0x01u\r
-#define SCSI_ATN_ISR__INTC_NUMBER 0u\r
+#define SCSI_ATN_ISR__INTC_MASK 0x800u\r
+#define SCSI_ATN_ISR__INTC_NUMBER 11u\r
#define SCSI_ATN_ISR__INTC_PRIOR_NUM 7u\r
-#define SCSI_ATN_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
+#define SCSI_ATN_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_11\r
#define SCSI_ATN_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define SCSI_ATN_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB02_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB02_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB02_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB02_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB02_MSK\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB03_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB03_ST\r
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB07_08_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB07_08_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB07_08_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB07_08_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB07_08_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB07_08_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB07_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB07_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB07_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB07_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB07_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB07_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB07_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB07_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB07_F1\r
+\r
+/* SCSI_CTL_IO */\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__MASK 0x01u\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK\r
+#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
\r
/* SCSI_In_DBx */\r
#define SCSI_In_DBx__0__MASK 0x01u\r
#define SD_Init_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
#define SD_Init_Clk__PM_STBY_MSK 0x02u\r
\r
+/* scsiTarget */\r
+#define scsiTarget_StatusReg__0__MASK 0x01u\r
+#define scsiTarget_StatusReg__0__POS 0\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
+#define scsiTarget_StatusReg__1__MASK 0x02u\r
+#define scsiTarget_StatusReg__1__POS 1\r
+#define scsiTarget_StatusReg__2__MASK 0x04u\r
+#define scsiTarget_StatusReg__2__POS 2\r
+#define scsiTarget_StatusReg__3__MASK 0x08u\r
+#define scsiTarget_StatusReg__3__POS 3\r
+#define scsiTarget_StatusReg__MASK 0x0Fu\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK\r
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB04_MSK\r
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB04_ST\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB04_CTL\r
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB04_CTL\r
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB04_MSK\r
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB04_05_A0\r
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB04_05_A1\r
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB04_05_D0\r
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB04_05_D1\r
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB04_05_F0\r
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB04_05_F1\r
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB04_A0_A1\r
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB04_A0\r
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB04_A1\r
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB04_D0_D1\r
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB04_D0\r
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB04_D1\r
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB04_F0_F1\r
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB04_F0\r
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB04_F1\r
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+\r
/* SD_Clk_Ctl */\r
#define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB07_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB07_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB07_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-\r
-/* PARITY_EN */\r
-#define PARITY_EN__0__MASK 0x10u\r
-#define PARITY_EN__0__PC CYREG_PRT5_PC4\r
-#define PARITY_EN__0__PORT 5u\r
-#define PARITY_EN__0__SHIFT 4\r
-#define PARITY_EN__AG CYREG_PRT5_AG\r
-#define PARITY_EN__AMUX CYREG_PRT5_AMUX\r
-#define PARITY_EN__BIE CYREG_PRT5_BIE\r
-#define PARITY_EN__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define PARITY_EN__BYP CYREG_PRT5_BYP\r
-#define PARITY_EN__CTL CYREG_PRT5_CTL\r
-#define PARITY_EN__DM0 CYREG_PRT5_DM0\r
-#define PARITY_EN__DM1 CYREG_PRT5_DM1\r
-#define PARITY_EN__DM2 CYREG_PRT5_DM2\r
-#define PARITY_EN__DR CYREG_PRT5_DR\r
-#define PARITY_EN__INP_DIS CYREG_PRT5_INP_DIS\r
-#define PARITY_EN__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define PARITY_EN__LCD_EN CYREG_PRT5_LCD_EN\r
-#define PARITY_EN__MASK 0x10u\r
-#define PARITY_EN__PORT 5u\r
-#define PARITY_EN__PRT CYREG_PRT5_PRT\r
-#define PARITY_EN__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define PARITY_EN__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define PARITY_EN__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define PARITY_EN__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define PARITY_EN__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define PARITY_EN__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define PARITY_EN__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define PARITY_EN__PS CYREG_PRT5_PS\r
-#define PARITY_EN__SHIFT 4\r
-#define PARITY_EN__SLW CYREG_PRT5_SLW\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__1__MASK 0x02u\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__1__POS 1\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x03u\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
\r
/* SCSI_ATN */\r
#define SCSI_ATN__0__MASK 0x20u\r
#define SCSI_ATN__DM2 CYREG_PRT12_DM2\r
#define SCSI_ATN__DR CYREG_PRT12_DR\r
#define SCSI_ATN__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_ATN__INTSTAT CYREG_PICU12_INTSTAT\r
#define SCSI_ATN__INT__MASK 0x20u\r
#define SCSI_ATN__INT__PC CYREG_PRT12_PC5\r
#define SCSI_ATN__INT__PORT 12u\r
#define SCSI_ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
#define SCSI_ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
#define SCSI_ATN__SLW CYREG_PRT12_SLW\r
+#define SCSI_ATN__SNAP CYREG_PICU12_SNAP\r
\r
/* SCSI_Out */\r
#define SCSI_Out__0__AG CYREG_PRT4_AG\r
#define SCSI_Out__CD__PS CYREG_PRT6_PS\r
#define SCSI_Out__CD__SHIFT 1\r
#define SCSI_Out__CD__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out__DBP__AG CYREG_PRT4_AG\r
-#define SCSI_Out__DBP__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__DBP__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__DBP__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__DBP__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__DBP__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__DBP__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__DBP__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__DBP__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__DBP__DR CYREG_PRT4_DR\r
-#define SCSI_Out__DBP__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__DBP__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__DBP__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__DBP__MASK 0x04u\r
-#define SCSI_Out__DBP__PC CYREG_PRT4_PC2\r
-#define SCSI_Out__DBP__PORT 4u\r
-#define SCSI_Out__DBP__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__DBP__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__DBP__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__DBP__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__DBP__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__DBP__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__DBP__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__DBP__PS CYREG_PRT4_PS\r
-#define SCSI_Out__DBP__SHIFT 2\r
-#define SCSI_Out__DBP__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__IO__AG CYREG_PRT6_AG\r
-#define SCSI_Out__IO__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out__IO__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out__IO__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out__IO__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out__IO__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out__IO__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out__IO__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out__IO__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out__IO__DR CYREG_PRT6_DR\r
-#define SCSI_Out__IO__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out__IO__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out__IO__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out__IO__MASK 0x08u\r
-#define SCSI_Out__IO__PC CYREG_PRT6_PC3\r
-#define SCSI_Out__IO__PORT 6u\r
-#define SCSI_Out__IO__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out__IO__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out__IO__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out__IO__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out__IO__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out__IO__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out__IO__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out__IO__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out__IO__PS CYREG_PRT6_PS\r
-#define SCSI_Out__IO__SHIFT 3\r
-#define SCSI_Out__IO__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG\r
+#define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__DBP_raw__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__DBP_raw__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__DBP_raw__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__DBP_raw__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__DBP_raw__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__DBP_raw__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__DBP_raw__DR CYREG_PRT4_DR\r
+#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__DBP_raw__MASK 0x04u\r
+#define SCSI_Out__DBP_raw__PC CYREG_PRT4_PC2\r
+#define SCSI_Out__DBP_raw__PORT 4u\r
+#define SCSI_Out__DBP_raw__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__DBP_raw__PS CYREG_PRT4_PS\r
+#define SCSI_Out__DBP_raw__SHIFT 2\r
+#define SCSI_Out__DBP_raw__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__IO_raw__AG CYREG_PRT6_AG\r
+#define SCSI_Out__IO_raw__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out__IO_raw__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out__IO_raw__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out__IO_raw__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out__IO_raw__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out__IO_raw__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out__IO_raw__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out__IO_raw__DR CYREG_PRT6_DR\r
+#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out__IO_raw__MASK 0x08u\r
+#define SCSI_Out__IO_raw__PC CYREG_PRT6_PC3\r
+#define SCSI_Out__IO_raw__PORT 6u\r
+#define SCSI_Out__IO_raw__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out__IO_raw__PS CYREG_PRT6_PS\r
+#define SCSI_Out__IO_raw__SHIFT 3\r
+#define SCSI_Out__IO_raw__SLW CYREG_PRT6_SLW\r
#define SCSI_Out__MSG__AG CYREG_PRT4_AG\r
#define SCSI_Out__MSG__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out__MSG__BIE CYREG_PRT4_BIE\r
#define SCSI_RST__SLW CYREG_PRT6_SLW\r
#define SCSI_RST__SNAP CYREG_PICU6_SNAP\r
\r
-/* SCSI_ID */\r
-#define SCSI_ID__0__MASK 0x80u\r
-#define SCSI_ID__0__PC CYREG_PRT5_PC7\r
-#define SCSI_ID__0__PORT 5u\r
-#define SCSI_ID__0__SHIFT 7\r
-#define SCSI_ID__1__MASK 0x40u\r
-#define SCSI_ID__1__PC CYREG_PRT5_PC6\r
-#define SCSI_ID__1__PORT 5u\r
-#define SCSI_ID__1__SHIFT 6\r
-#define SCSI_ID__2__MASK 0x20u\r
-#define SCSI_ID__2__PC CYREG_PRT5_PC5\r
-#define SCSI_ID__2__PORT 5u\r
-#define SCSI_ID__2__SHIFT 5\r
-#define SCSI_ID__AG CYREG_PRT5_AG\r
-#define SCSI_ID__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_ID__BIE CYREG_PRT5_BIE\r
-#define SCSI_ID__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_ID__BYP CYREG_PRT5_BYP\r
-#define SCSI_ID__CTL CYREG_PRT5_CTL\r
-#define SCSI_ID__DM0 CYREG_PRT5_DM0\r
-#define SCSI_ID__DM1 CYREG_PRT5_DM1\r
-#define SCSI_ID__DM2 CYREG_PRT5_DM2\r
-#define SCSI_ID__DR CYREG_PRT5_DR\r
-#define SCSI_ID__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_ID__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_ID__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_ID__PORT 5u\r
-#define SCSI_ID__PRT CYREG_PRT5_PRT\r
-#define SCSI_ID__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_ID__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_ID__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_ID__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_ID__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_ID__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_ID__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_ID__PS CYREG_PRT5_PS\r
-#define SCSI_ID__SLW CYREG_PRT5_SLW\r
-\r
/* SCSI_In */\r
#define SCSI_In__0__AG CYREG_PRT12_AG\r
#define SCSI_In__0__BIE CYREG_PRT12_BIE\r
#define CYDEV_ECC_ENABLE 0\r
#define CYDEV_HEAP_SIZE 0x1000\r
#define CYDEV_INSTRUCT_CACHE_ENABLED 1\r
-#define CYDEV_INTR_RISING 0x00000001u\r
+#define CYDEV_INTR_RISING 0x00000000u\r
#define CYDEV_PROJ_TYPE 0\r
#define CYDEV_PROJ_TYPE_BOOTLOADER 1\r
#define CYDEV_PROJ_TYPE_LOADABLE 2\r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 22u\r
+#define CY_CFG_BASE_ADDR_COUNT 32u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
} CYPACKED_ATTR cy_cfg_addrvalue_t;\r
\r
#define cy_cfg_addr_table ((const uint32 CYFAR *)0x48000000u)\r
-#define cy_cfg_data_table ((const cy_cfg_addrvalue_t CYFAR *)0x48000058u)\r
+#define cy_cfg_data_table ((const cy_cfg_addrvalue_t CYFAR *)0x48000080u)\r
\r
-/* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */\r
-#define BS_UDB_1_2_1_CONFIG_VAL ((const uint8 CYFAR *)0x48000318u)\r
+/* UDB_1_2_0_CONFIG Address: CYDEV_UCFG_B0_P3_U1_BASE Size (bytes): 128 */\r
+#define BS_UDB_1_2_0_CONFIG_VAL ((const uint8 CYFAR *)0x480007A8u)\r
\r
/* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */\r
-#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x48000398u)\r
+#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x48000828u)\r
\r
/* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */\r
-#define BS_IOPINS0_7_VAL ((const uint8 CYFAR *)0x480003A0u)\r
+#define BS_IOPINS0_7_VAL ((const uint8 CYFAR *)0x48000830u)\r
\r
/* IOPINS1_7 Address: CYREG_PRT12_DR + 0x0000000Bu Size (bytes): 5 */\r
-#define BS_IOPINS1_7_VAL ((const uint8 CYFAR *)0x480003ACu)\r
+#define BS_IOPINS1_7_VAL ((const uint8 CYFAR *)0x4800083Cu)\r
\r
/* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */\r
-#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x480003B4u)\r
+#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x48000844u)\r
\r
/* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */\r
-#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x480003BCu)\r
+#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x4800084Cu)\r
\r
/* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */\r
-#define BS_IOPINS0_4_VAL ((const uint8 CYFAR *)0x480003C8u)\r
+#define BS_IOPINS0_4_VAL ((const uint8 CYFAR *)0x48000858u)\r
\r
-/* IOPINS0_5 Address: CYREG_PRT5_DR Size (bytes): 10 */\r
-#define BS_IOPINS0_5_VAL ((const uint8 CYFAR *)0x480003D0u)\r
+/* IOPINS0_5 Address: CYREG_PRT5_DM0 Size (bytes): 8 */\r
+#define BS_IOPINS0_5_VAL ((const uint8 CYFAR *)0x48000860u)\r
\r
/* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */\r
-#define BS_IOPINS0_6_VAL ((const uint8 CYFAR *)0x480003DCu)\r
+#define BS_IOPINS0_6_VAL ((const uint8 CYFAR *)0x48000868u)\r
\r
\r
/*******************************************************************************\r
/* address, size */\r
{(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
{(void CYFAR *)(CYREG_PRT15_DR), 16u},\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1536u},\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), 2432u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1664u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P3_ROUTE_BASE), 2304u},\r
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P3_U0_BASE), BS_UDB_1_2_1_CONFIG_VAL, 128u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), BS_UDB_1_2_0_CONFIG_VAL, 128u},\r
};\r
\r
uint8 CYDATA i;\r
CYCONFIGCPY((void CYFAR *)(CYREG_PRT2_DM0), (const void CYFAR *)(BS_IOPINS0_2_VAL), 8u);\r
CYCONFIGCPY((void CYFAR *)(CYREG_PRT3_DR), (const void CYFAR *)(BS_IOPINS0_3_VAL), 10u);\r
CYCONFIGCPY((void CYFAR *)(CYREG_PRT4_DM0), (const void CYFAR *)(BS_IOPINS0_4_VAL), 8u);\r
- CYCONFIGCPY((void CYFAR *)(CYREG_PRT5_DR), (const void CYFAR *)(BS_IOPINS0_5_VAL), 10u);\r
+ CYCONFIGCPY((void CYFAR *)(CYREG_PRT5_DM0), (const void CYFAR *)(BS_IOPINS0_5_VAL), 8u);\r
CYCONFIGCPY((void CYFAR *)(CYREG_PRT6_DM0), (const void CYFAR *)(BS_IOPINS0_6_VAL), 8u);\r
\r
/* Switch Boost to the precision bandgap reference from its internal reference */\r
/* SCSI_ATN_ISR */\r
.set SCSI_ATN_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SCSI_ATN_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_ATN_ISR__INTC_MASK, 0x01\r
-.set SCSI_ATN_ISR__INTC_NUMBER, 0\r
+.set SCSI_ATN_ISR__INTC_MASK, 0x800\r
+.set SCSI_ATN_ISR__INTC_NUMBER, 11\r
.set SCSI_ATN_ISR__INTC_PRIOR_NUM, 7\r
-.set SCSI_ATN_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set SCSI_ATN_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_11\r
.set SCSI_ATN_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set SCSI_ATN_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB02_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB02_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB02_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB02_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB02_MSK\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB03_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB03_ST\r
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB07_08_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB07_08_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB07_08_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB07_08_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB07_08_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB07_08_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB07_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB07_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB07_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB07_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB07_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB07_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB07_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB07_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB07_F1\r
+\r
+/* SCSI_CTL_IO */\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__MASK, 0x01\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK\r
+.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
\r
/* SCSI_In_DBx */\r
.set SCSI_In_DBx__0__MASK, 0x01\r
.set SD_Init_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
.set SD_Init_Clk__PM_STBY_MSK, 0x02\r
\r
+/* scsiTarget */\r
+.set scsiTarget_StatusReg__0__MASK, 0x01\r
+.set scsiTarget_StatusReg__0__POS, 0\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
+.set scsiTarget_StatusReg__1__MASK, 0x02\r
+.set scsiTarget_StatusReg__1__POS, 1\r
+.set scsiTarget_StatusReg__2__MASK, 0x04\r
+.set scsiTarget_StatusReg__2__POS, 2\r
+.set scsiTarget_StatusReg__3__MASK, 0x08\r
+.set scsiTarget_StatusReg__3__POS, 3\r
+.set scsiTarget_StatusReg__MASK, 0x0F\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK\r
+.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB04_MSK\r
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB04_ST\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB04_CTL\r
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB04_CTL\r
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB04_MSK\r
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB04_05_A0\r
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB04_05_A1\r
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB04_05_D0\r
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB04_05_D1\r
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB04_05_F0\r
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB04_05_F1\r
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB04_A0_A1\r
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB04_A0\r
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB04_A1\r
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB04_D0_D1\r
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB04_D0\r
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB04_D1\r
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB04_F0_F1\r
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB04_F0\r
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB04_F1\r
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+\r
/* SD_Clk_Ctl */\r
.set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB07_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB07_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB07_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-\r
-/* PARITY_EN */\r
-.set PARITY_EN__0__MASK, 0x10\r
-.set PARITY_EN__0__PC, CYREG_PRT5_PC4\r
-.set PARITY_EN__0__PORT, 5\r
-.set PARITY_EN__0__SHIFT, 4\r
-.set PARITY_EN__AG, CYREG_PRT5_AG\r
-.set PARITY_EN__AMUX, CYREG_PRT5_AMUX\r
-.set PARITY_EN__BIE, CYREG_PRT5_BIE\r
-.set PARITY_EN__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set PARITY_EN__BYP, CYREG_PRT5_BYP\r
-.set PARITY_EN__CTL, CYREG_PRT5_CTL\r
-.set PARITY_EN__DM0, CYREG_PRT5_DM0\r
-.set PARITY_EN__DM1, CYREG_PRT5_DM1\r
-.set PARITY_EN__DM2, CYREG_PRT5_DM2\r
-.set PARITY_EN__DR, CYREG_PRT5_DR\r
-.set PARITY_EN__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set PARITY_EN__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set PARITY_EN__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set PARITY_EN__MASK, 0x10\r
-.set PARITY_EN__PORT, 5\r
-.set PARITY_EN__PRT, CYREG_PRT5_PRT\r
-.set PARITY_EN__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set PARITY_EN__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set PARITY_EN__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set PARITY_EN__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set PARITY_EN__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set PARITY_EN__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set PARITY_EN__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set PARITY_EN__PS, CYREG_PRT5_PS\r
-.set PARITY_EN__SHIFT, 4\r
-.set PARITY_EN__SLW, CYREG_PRT5_SLW\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__1__MASK, 0x02\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__1__POS, 1\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x03\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
\r
/* SCSI_ATN */\r
.set SCSI_ATN__0__MASK, 0x20\r
.set SCSI_ATN__DM2, CYREG_PRT12_DM2\r
.set SCSI_ATN__DR, CYREG_PRT12_DR\r
.set SCSI_ATN__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_ATN__INTSTAT, CYREG_PICU12_INTSTAT\r
.set SCSI_ATN__INT__MASK, 0x20\r
.set SCSI_ATN__INT__PC, CYREG_PRT12_PC5\r
.set SCSI_ATN__INT__PORT, 12\r
.set SCSI_ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
.set SCSI_ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
.set SCSI_ATN__SLW, CYREG_PRT12_SLW\r
+.set SCSI_ATN__SNAP, CYREG_PICU12_SNAP\r
\r
/* SCSI_Out */\r
.set SCSI_Out__0__AG, CYREG_PRT4_AG\r
.set SCSI_Out__CD__PS, CYREG_PRT6_PS\r
.set SCSI_Out__CD__SHIFT, 1\r
.set SCSI_Out__CD__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out__DBP__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__DBP__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__DBP__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__DBP__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__DBP__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__DBP__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__DBP__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__DBP__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__DBP__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__DBP__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__DBP__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__DBP__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__DBP__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__DBP__MASK, 0x04\r
-.set SCSI_Out__DBP__PC, CYREG_PRT4_PC2\r
-.set SCSI_Out__DBP__PORT, 4\r
-.set SCSI_Out__DBP__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__DBP__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__DBP__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__DBP__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__DBP__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__DBP__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__DBP__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__DBP__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__DBP__SHIFT, 2\r
-.set SCSI_Out__DBP__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__IO__AG, CYREG_PRT6_AG\r
-.set SCSI_Out__IO__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out__IO__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out__IO__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out__IO__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out__IO__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out__IO__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out__IO__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out__IO__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out__IO__DR, CYREG_PRT6_DR\r
-.set SCSI_Out__IO__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out__IO__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out__IO__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out__IO__MASK, 0x08\r
-.set SCSI_Out__IO__PC, CYREG_PRT6_PC3\r
-.set SCSI_Out__IO__PORT, 6\r
-.set SCSI_Out__IO__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out__IO__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out__IO__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out__IO__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out__IO__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out__IO__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out__IO__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out__IO__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out__IO__PS, CYREG_PRT6_PS\r
-.set SCSI_Out__IO__SHIFT, 3\r
-.set SCSI_Out__IO__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out__DBP_raw__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__DBP_raw__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__DBP_raw__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__DBP_raw__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__DBP_raw__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__DBP_raw__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__DBP_raw__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__DBP_raw__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__DBP_raw__MASK, 0x04\r
+.set SCSI_Out__DBP_raw__PC, CYREG_PRT4_PC2\r
+.set SCSI_Out__DBP_raw__PORT, 4\r
+.set SCSI_Out__DBP_raw__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__DBP_raw__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__DBP_raw__SHIFT, 2\r
+.set SCSI_Out__DBP_raw__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__IO_raw__AG, CYREG_PRT6_AG\r
+.set SCSI_Out__IO_raw__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out__IO_raw__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out__IO_raw__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out__IO_raw__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out__IO_raw__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out__IO_raw__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out__IO_raw__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out__IO_raw__DR, CYREG_PRT6_DR\r
+.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out__IO_raw__MASK, 0x08\r
+.set SCSI_Out__IO_raw__PC, CYREG_PRT6_PC3\r
+.set SCSI_Out__IO_raw__PORT, 6\r
+.set SCSI_Out__IO_raw__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out__IO_raw__PS, CYREG_PRT6_PS\r
+.set SCSI_Out__IO_raw__SHIFT, 3\r
+.set SCSI_Out__IO_raw__SLW, CYREG_PRT6_SLW\r
.set SCSI_Out__MSG__AG, CYREG_PRT4_AG\r
.set SCSI_Out__MSG__AMUX, CYREG_PRT4_AMUX\r
.set SCSI_Out__MSG__BIE, CYREG_PRT4_BIE\r
.set SCSI_RST__SLW, CYREG_PRT6_SLW\r
.set SCSI_RST__SNAP, CYREG_PICU6_SNAP\r
\r
-/* SCSI_ID */\r
-.set SCSI_ID__0__MASK, 0x80\r
-.set SCSI_ID__0__PC, CYREG_PRT5_PC7\r
-.set SCSI_ID__0__PORT, 5\r
-.set SCSI_ID__0__SHIFT, 7\r
-.set SCSI_ID__1__MASK, 0x40\r
-.set SCSI_ID__1__PC, CYREG_PRT5_PC6\r
-.set SCSI_ID__1__PORT, 5\r
-.set SCSI_ID__1__SHIFT, 6\r
-.set SCSI_ID__2__MASK, 0x20\r
-.set SCSI_ID__2__PC, CYREG_PRT5_PC5\r
-.set SCSI_ID__2__PORT, 5\r
-.set SCSI_ID__2__SHIFT, 5\r
-.set SCSI_ID__AG, CYREG_PRT5_AG\r
-.set SCSI_ID__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_ID__BIE, CYREG_PRT5_BIE\r
-.set SCSI_ID__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_ID__BYP, CYREG_PRT5_BYP\r
-.set SCSI_ID__CTL, CYREG_PRT5_CTL\r
-.set SCSI_ID__DM0, CYREG_PRT5_DM0\r
-.set SCSI_ID__DM1, CYREG_PRT5_DM1\r
-.set SCSI_ID__DM2, CYREG_PRT5_DM2\r
-.set SCSI_ID__DR, CYREG_PRT5_DR\r
-.set SCSI_ID__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_ID__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_ID__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_ID__PORT, 5\r
-.set SCSI_ID__PRT, CYREG_PRT5_PRT\r
-.set SCSI_ID__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_ID__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_ID__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_ID__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_ID__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_ID__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_ID__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_ID__PS, CYREG_PRT5_PS\r
-.set SCSI_ID__SLW, CYREG_PRT5_SLW\r
-\r
/* SCSI_In */\r
.set SCSI_In__0__AG, CYREG_PRT12_AG\r
.set SCSI_In__0__BIE, CYREG_PRT12_BIE\r
.set CYDEV_ECC_ENABLE, 0\r
.set CYDEV_HEAP_SIZE, 0x1000\r
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1\r
-.set CYDEV_INTR_RISING, 0x00000001\r
+.set CYDEV_INTR_RISING, 0x00000000\r
.set CYDEV_PROJ_TYPE, 0\r
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1\r
.set CYDEV_PROJ_TYPE_LOADABLE, 2\r
/* SCSI_ATN_ISR */\r
SCSI_ATN_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_ATN_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_ATN_ISR__INTC_MASK EQU 0x01\r
-SCSI_ATN_ISR__INTC_NUMBER EQU 0\r
+SCSI_ATN_ISR__INTC_MASK EQU 0x800\r
+SCSI_ATN_ISR__INTC_NUMBER EQU 11\r
SCSI_ATN_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_11\r
SCSI_ATN_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SCSI_ATN_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB02_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB02_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB03_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB03_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1\r
+\r
+/* SCSI_CTL_IO */\r
+SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
\r
/* SCSI_In_DBx */\r
SCSI_In_DBx__0__MASK EQU 0x01\r
SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
SD_Init_Clk__PM_STBY_MSK EQU 0x02\r
\r
+/* scsiTarget */\r
+scsiTarget_StatusReg__0__MASK EQU 0x01\r
+scsiTarget_StatusReg__0__POS EQU 0\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+scsiTarget_StatusReg__1__MASK EQU 0x02\r
+scsiTarget_StatusReg__1__POS EQU 1\r
+scsiTarget_StatusReg__2__MASK EQU 0x04\r
+scsiTarget_StatusReg__2__POS EQU 2\r
+scsiTarget_StatusReg__3__MASK EQU 0x08\r
+scsiTarget_StatusReg__3__POS EQU 3\r
+scsiTarget_StatusReg__MASK EQU 0x0F\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL\r
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB04_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB04_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB04_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB04_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB04_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB04_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB04_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+\r
/* SD_Clk_Ctl */\r
SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-\r
-/* PARITY_EN */\r
-PARITY_EN__0__MASK EQU 0x10\r
-PARITY_EN__0__PC EQU CYREG_PRT5_PC4\r
-PARITY_EN__0__PORT EQU 5\r
-PARITY_EN__0__SHIFT EQU 4\r
-PARITY_EN__AG EQU CYREG_PRT5_AG\r
-PARITY_EN__AMUX EQU CYREG_PRT5_AMUX\r
-PARITY_EN__BIE EQU CYREG_PRT5_BIE\r
-PARITY_EN__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-PARITY_EN__BYP EQU CYREG_PRT5_BYP\r
-PARITY_EN__CTL EQU CYREG_PRT5_CTL\r
-PARITY_EN__DM0 EQU CYREG_PRT5_DM0\r
-PARITY_EN__DM1 EQU CYREG_PRT5_DM1\r
-PARITY_EN__DM2 EQU CYREG_PRT5_DM2\r
-PARITY_EN__DR EQU CYREG_PRT5_DR\r
-PARITY_EN__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-PARITY_EN__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-PARITY_EN__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-PARITY_EN__MASK EQU 0x10\r
-PARITY_EN__PORT EQU 5\r
-PARITY_EN__PRT EQU CYREG_PRT5_PRT\r
-PARITY_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-PARITY_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-PARITY_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-PARITY_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-PARITY_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-PARITY_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-PARITY_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-PARITY_EN__PS EQU CYREG_PRT5_PS\r
-PARITY_EN__SHIFT EQU 4\r
-PARITY_EN__SLW EQU CYREG_PRT5_SLW\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SD_Clk_Ctl_Sync_ctrl_reg__1__POS EQU 1\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x03\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
\r
/* SCSI_ATN */\r
SCSI_ATN__0__MASK EQU 0x20\r
SCSI_ATN__DM2 EQU CYREG_PRT12_DM2\r
SCSI_ATN__DR EQU CYREG_PRT12_DR\r
SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_ATN__INTSTAT EQU CYREG_PICU12_INTSTAT\r
SCSI_ATN__INT__MASK EQU 0x20\r
SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5\r
SCSI_ATN__INT__PORT EQU 12\r
SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
SCSI_ATN__SLW EQU CYREG_PRT12_SLW\r
+SCSI_ATN__SNAP EQU CYREG_PICU12_SNAP\r
\r
/* SCSI_Out */\r
SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
SCSI_Out__CD__PS EQU CYREG_PRT6_PS\r
SCSI_Out__CD__SHIFT EQU 1\r
SCSI_Out__CD__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out__DBP__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__DBP__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__DBP__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__DBP__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__DBP__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__DBP__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__DBP__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__DBP__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__DBP__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__DBP__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__DBP__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__DBP__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__DBP__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__DBP__MASK EQU 0x04\r
-SCSI_Out__DBP__PC EQU CYREG_PRT4_PC2\r
-SCSI_Out__DBP__PORT EQU 4\r
-SCSI_Out__DBP__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__DBP__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__DBP__SHIFT EQU 2\r
-SCSI_Out__DBP__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__IO__AG EQU CYREG_PRT6_AG\r
-SCSI_Out__IO__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out__IO__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out__IO__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out__IO__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out__IO__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out__IO__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out__IO__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out__IO__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out__IO__DR EQU CYREG_PRT6_DR\r
-SCSI_Out__IO__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out__IO__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out__IO__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out__IO__MASK EQU 0x08\r
-SCSI_Out__IO__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out__IO__PORT EQU 6\r
-SCSI_Out__IO__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out__IO__PS EQU CYREG_PRT6_PS\r
-SCSI_Out__IO__SHIFT EQU 3\r
-SCSI_Out__IO__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__DBP_raw__MASK EQU 0x04\r
+SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__DBP_raw__PORT EQU 4\r
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__DBP_raw__SHIFT EQU 2\r
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__IO_raw__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__IO_raw__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__IO_raw__MASK EQU 0x08\r
+SCSI_Out__IO_raw__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out__IO_raw__PORT EQU 6\r
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__IO_raw__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__IO_raw__SHIFT EQU 3\r
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT6_SLW\r
SCSI_Out__MSG__AG EQU CYREG_PRT4_AG\r
SCSI_Out__MSG__AMUX EQU CYREG_PRT4_AMUX\r
SCSI_Out__MSG__BIE EQU CYREG_PRT4_BIE\r
SCSI_RST__SLW EQU CYREG_PRT6_SLW\r
SCSI_RST__SNAP EQU CYREG_PICU6_SNAP\r
\r
-/* SCSI_ID */\r
-SCSI_ID__0__MASK EQU 0x80\r
-SCSI_ID__0__PC EQU CYREG_PRT5_PC7\r
-SCSI_ID__0__PORT EQU 5\r
-SCSI_ID__0__SHIFT EQU 7\r
-SCSI_ID__1__MASK EQU 0x40\r
-SCSI_ID__1__PC EQU CYREG_PRT5_PC6\r
-SCSI_ID__1__PORT EQU 5\r
-SCSI_ID__1__SHIFT EQU 6\r
-SCSI_ID__2__MASK EQU 0x20\r
-SCSI_ID__2__PC EQU CYREG_PRT5_PC5\r
-SCSI_ID__2__PORT EQU 5\r
-SCSI_ID__2__SHIFT EQU 5\r
-SCSI_ID__AG EQU CYREG_PRT5_AG\r
-SCSI_ID__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_ID__BIE EQU CYREG_PRT5_BIE\r
-SCSI_ID__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_ID__BYP EQU CYREG_PRT5_BYP\r
-SCSI_ID__CTL EQU CYREG_PRT5_CTL\r
-SCSI_ID__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_ID__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_ID__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_ID__DR EQU CYREG_PRT5_DR\r
-SCSI_ID__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_ID__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_ID__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_ID__PORT EQU 5\r
-SCSI_ID__PRT EQU CYREG_PRT5_PRT\r
-SCSI_ID__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_ID__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_ID__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_ID__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_ID__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_ID__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_ID__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_ID__PS EQU CYREG_PRT5_PS\r
-SCSI_ID__SLW EQU CYREG_PRT5_SLW\r
-\r
/* SCSI_In */\r
SCSI_In__0__AG EQU CYREG_PRT12_AG\r
SCSI_In__0__BIE EQU CYREG_PRT12_BIE\r
CYDEV_ECC_ENABLE EQU 0\r
CYDEV_HEAP_SIZE EQU 0x1000\r
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x00000001\r
+CYDEV_INTR_RISING EQU 0x00000000\r
CYDEV_PROJ_TYPE EQU 0\r
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
; SCSI_ATN_ISR\r
SCSI_ATN_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_ATN_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_ATN_ISR__INTC_MASK EQU 0x01\r
-SCSI_ATN_ISR__INTC_NUMBER EQU 0\r
+SCSI_ATN_ISR__INTC_MASK EQU 0x800\r
+SCSI_ATN_ISR__INTC_NUMBER EQU 11\r
SCSI_ATN_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_11\r
SCSI_ATN_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SCSI_ATN_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB02_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB02_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB03_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB03_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1\r
+\r
+; SCSI_CTL_IO\r
+SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
+SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK\r
+SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
\r
; SCSI_In_DBx\r
SCSI_In_DBx__0__MASK EQU 0x01\r
SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
SD_Init_Clk__PM_STBY_MSK EQU 0x02\r
\r
+; scsiTarget\r
+scsiTarget_StatusReg__0__MASK EQU 0x01\r
+scsiTarget_StatusReg__0__POS EQU 0\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+scsiTarget_StatusReg__1__MASK EQU 0x02\r
+scsiTarget_StatusReg__1__POS EQU 1\r
+scsiTarget_StatusReg__2__MASK EQU 0x04\r
+scsiTarget_StatusReg__2__POS EQU 2\r
+scsiTarget_StatusReg__3__MASK EQU 0x08\r
+scsiTarget_StatusReg__3__POS EQU 3\r
+scsiTarget_StatusReg__MASK EQU 0x0F\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL\r
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB04_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB04_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB04_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB04_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB04_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB04_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB04_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+\r
; SD_Clk_Ctl\r
SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-\r
-; PARITY_EN\r
-PARITY_EN__0__MASK EQU 0x10\r
-PARITY_EN__0__PC EQU CYREG_PRT5_PC4\r
-PARITY_EN__0__PORT EQU 5\r
-PARITY_EN__0__SHIFT EQU 4\r
-PARITY_EN__AG EQU CYREG_PRT5_AG\r
-PARITY_EN__AMUX EQU CYREG_PRT5_AMUX\r
-PARITY_EN__BIE EQU CYREG_PRT5_BIE\r
-PARITY_EN__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-PARITY_EN__BYP EQU CYREG_PRT5_BYP\r
-PARITY_EN__CTL EQU CYREG_PRT5_CTL\r
-PARITY_EN__DM0 EQU CYREG_PRT5_DM0\r
-PARITY_EN__DM1 EQU CYREG_PRT5_DM1\r
-PARITY_EN__DM2 EQU CYREG_PRT5_DM2\r
-PARITY_EN__DR EQU CYREG_PRT5_DR\r
-PARITY_EN__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-PARITY_EN__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-PARITY_EN__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-PARITY_EN__MASK EQU 0x10\r
-PARITY_EN__PORT EQU 5\r
-PARITY_EN__PRT EQU CYREG_PRT5_PRT\r
-PARITY_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-PARITY_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-PARITY_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-PARITY_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-PARITY_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-PARITY_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-PARITY_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-PARITY_EN__PS EQU CYREG_PRT5_PS\r
-PARITY_EN__SHIFT EQU 4\r
-PARITY_EN__SLW EQU CYREG_PRT5_SLW\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SD_Clk_Ctl_Sync_ctrl_reg__1__POS EQU 1\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x03\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
\r
; SCSI_ATN\r
SCSI_ATN__0__MASK EQU 0x20\r
SCSI_ATN__DM2 EQU CYREG_PRT12_DM2\r
SCSI_ATN__DR EQU CYREG_PRT12_DR\r
SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_ATN__INTSTAT EQU CYREG_PICU12_INTSTAT\r
SCSI_ATN__INT__MASK EQU 0x20\r
SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5\r
SCSI_ATN__INT__PORT EQU 12\r
SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
SCSI_ATN__SLW EQU CYREG_PRT12_SLW\r
+SCSI_ATN__SNAP EQU CYREG_PICU12_SNAP\r
\r
; SCSI_Out\r
SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
SCSI_Out__CD__PS EQU CYREG_PRT6_PS\r
SCSI_Out__CD__SHIFT EQU 1\r
SCSI_Out__CD__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out__DBP__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__DBP__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__DBP__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__DBP__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__DBP__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__DBP__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__DBP__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__DBP__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__DBP__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__DBP__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__DBP__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__DBP__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__DBP__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__DBP__MASK EQU 0x04\r
-SCSI_Out__DBP__PC EQU CYREG_PRT4_PC2\r
-SCSI_Out__DBP__PORT EQU 4\r
-SCSI_Out__DBP__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__DBP__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__DBP__SHIFT EQU 2\r
-SCSI_Out__DBP__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__IO__AG EQU CYREG_PRT6_AG\r
-SCSI_Out__IO__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out__IO__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out__IO__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out__IO__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out__IO__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out__IO__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out__IO__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out__IO__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out__IO__DR EQU CYREG_PRT6_DR\r
-SCSI_Out__IO__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out__IO__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out__IO__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out__IO__MASK EQU 0x08\r
-SCSI_Out__IO__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out__IO__PORT EQU 6\r
-SCSI_Out__IO__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out__IO__PS EQU CYREG_PRT6_PS\r
-SCSI_Out__IO__SHIFT EQU 3\r
-SCSI_Out__IO__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__DBP_raw__MASK EQU 0x04\r
+SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__DBP_raw__PORT EQU 4\r
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__DBP_raw__SHIFT EQU 2\r
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__IO_raw__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__IO_raw__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__IO_raw__MASK EQU 0x08\r
+SCSI_Out__IO_raw__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out__IO_raw__PORT EQU 6\r
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__IO_raw__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__IO_raw__SHIFT EQU 3\r
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT6_SLW\r
SCSI_Out__MSG__AG EQU CYREG_PRT4_AG\r
SCSI_Out__MSG__AMUX EQU CYREG_PRT4_AMUX\r
SCSI_Out__MSG__BIE EQU CYREG_PRT4_BIE\r
SCSI_RST__SLW EQU CYREG_PRT6_SLW\r
SCSI_RST__SNAP EQU CYREG_PICU6_SNAP\r
\r
-; SCSI_ID\r
-SCSI_ID__0__MASK EQU 0x80\r
-SCSI_ID__0__PC EQU CYREG_PRT5_PC7\r
-SCSI_ID__0__PORT EQU 5\r
-SCSI_ID__0__SHIFT EQU 7\r
-SCSI_ID__1__MASK EQU 0x40\r
-SCSI_ID__1__PC EQU CYREG_PRT5_PC6\r
-SCSI_ID__1__PORT EQU 5\r
-SCSI_ID__1__SHIFT EQU 6\r
-SCSI_ID__2__MASK EQU 0x20\r
-SCSI_ID__2__PC EQU CYREG_PRT5_PC5\r
-SCSI_ID__2__PORT EQU 5\r
-SCSI_ID__2__SHIFT EQU 5\r
-SCSI_ID__AG EQU CYREG_PRT5_AG\r
-SCSI_ID__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_ID__BIE EQU CYREG_PRT5_BIE\r
-SCSI_ID__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_ID__BYP EQU CYREG_PRT5_BYP\r
-SCSI_ID__CTL EQU CYREG_PRT5_CTL\r
-SCSI_ID__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_ID__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_ID__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_ID__DR EQU CYREG_PRT5_DR\r
-SCSI_ID__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_ID__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_ID__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_ID__PORT EQU 5\r
-SCSI_ID__PRT EQU CYREG_PRT5_PRT\r
-SCSI_ID__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_ID__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_ID__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_ID__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_ID__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_ID__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_ID__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_ID__PS EQU CYREG_PRT5_PS\r
-SCSI_ID__SLW EQU CYREG_PRT5_SLW\r
-\r
; SCSI_In\r
SCSI_In__0__AG EQU CYREG_PRT12_AG\r
SCSI_In__0__BIE EQU CYREG_PRT12_BIE\r
CYDEV_ECC_ENABLE EQU 0\r
CYDEV_HEAP_SIZE EQU 0x1000\r
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x00000001\r
+CYDEV_INTR_RISING EQU 0x00000000\r
CYDEV_PROJ_TYPE EQU 0\r
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
#error "Unsupported toolchain"\r
#endif\r
const uint8 cy_meta_configecc[] = {\r
- 0x01u, 0x45u, 0x00u, 0x40u, 0x07u, 0x52u, 0x00u, 0x40u,\r
- 0x01u, 0x64u, 0x00u, 0x40u, 0x02u, 0x03u, 0x01u, 0x40u,\r
- 0x3Fu, 0x04u, 0x01u, 0x40u, 0x2Au, 0x05u, 0x01u, 0x40u,\r
- 0x03u, 0x06u, 0x01u, 0x40u, 0x41u, 0x07u, 0x01u, 0x40u,\r
- 0x01u, 0x0Du, 0x01u, 0x40u, 0x09u, 0x15u, 0x01u, 0x40u,\r
- 0x43u, 0x16u, 0x01u, 0x40u, 0x3Au, 0x17u, 0x01u, 0x40u,\r
- 0x02u, 0x40u, 0x01u, 0x40u, 0x01u, 0x41u, 0x01u, 0x40u,\r
- 0x01u, 0x42u, 0x01u, 0x40u, 0x02u, 0x43u, 0x01u, 0x40u,\r
- 0x02u, 0x44u, 0x01u, 0x40u, 0x02u, 0x45u, 0x01u, 0x40u,\r
- 0x04u, 0x48u, 0x01u, 0x40u, 0x0Eu, 0x49u, 0x01u, 0x40u,\r
- 0x04u, 0x50u, 0x01u, 0x40u, 0x01u, 0x51u, 0x01u, 0x40u,\r
- 0x36u, 0x02u, 0x14u, 0xFFu, 0x18u, 0x04u, 0x19u, 0x0Cu,\r
- 0x1Cu, 0xE1u, 0x2Cu, 0xFFu, 0x34u, 0xF0u, 0x64u, 0x10u,\r
- 0x86u, 0x0Fu, 0x98u, 0x40u, 0xB0u, 0x40u, 0x00u, 0x01u,\r
- 0x1Du, 0x01u, 0x2Du, 0x01u, 0x30u, 0x01u, 0x31u, 0x01u,\r
- 0x39u, 0x02u, 0x3Eu, 0x01u, 0x56u, 0x08u, 0x58u, 0x04u,\r
- 0x59u, 0x0Bu, 0x5Bu, 0x04u, 0x5Cu, 0x90u, 0x5Du, 0x90u,\r
- 0x5Fu, 0x01u, 0x80u, 0x6Cu, 0x81u, 0x41u, 0x84u, 0x68u,\r
- 0x86u, 0x04u, 0x88u, 0x6Cu, 0x89u, 0x81u, 0x8Bu, 0x40u,\r
- 0x8Du, 0x41u, 0x91u, 0x04u, 0x92u, 0x02u, 0x94u, 0x10u,\r
- 0x95u, 0xE2u, 0x96u, 0x68u, 0x97u, 0x08u, 0x98u, 0x10u,\r
- 0x99u, 0x88u, 0x9Au, 0xC5u, 0x9Bu, 0x61u, 0x9Cu, 0x6Cu,\r
- 0x9Du, 0x47u, 0x9Fu, 0x98u, 0xA0u, 0x6Cu, 0xA1u, 0x10u,\r
- 0xA4u, 0x04u, 0xA5u, 0x41u, 0xA8u, 0x93u, 0xA9u, 0x40u,\r
- 0xAAu, 0x20u, 0xACu, 0x0Fu, 0xADu, 0x01u, 0xAEu, 0x90u,\r
- 0xAFu, 0x40u, 0xB2u, 0x78u, 0xB4u, 0x07u, 0xB5u, 0xC0u,\r
- 0xB6u, 0x80u, 0xB7u, 0x3Fu, 0xB9u, 0x80u, 0xBAu, 0x38u,\r
- 0xBBu, 0x20u, 0xBEu, 0x40u, 0xBFu, 0x40u, 0xD4u, 0x09u,\r
+ 0x02u, 0x45u, 0x00u, 0x40u, 0x08u, 0x52u, 0x00u, 0x40u,\r
+ 0x02u, 0x64u, 0x00u, 0x40u, 0x45u, 0x00u, 0x01u, 0x40u,\r
+ 0x32u, 0x01u, 0x01u, 0x40u, 0x44u, 0x02u, 0x01u, 0x40u,\r
+ 0x54u, 0x03u, 0x01u, 0x40u, 0x3Du, 0x04u, 0x01u, 0x40u,\r
+ 0x5Bu, 0x05u, 0x01u, 0x40u, 0x0Bu, 0x06u, 0x01u, 0x40u,\r
+ 0x4Eu, 0x07u, 0x01u, 0x40u, 0x10u, 0x09u, 0x01u, 0x40u,\r
+ 0x3Cu, 0x0Au, 0x01u, 0x40u, 0x3Fu, 0x0Bu, 0x01u, 0x40u,\r
+ 0x0Au, 0x0Du, 0x01u, 0x40u, 0x02u, 0x0Fu, 0x01u, 0x40u,\r
+ 0x03u, 0x15u, 0x01u, 0x40u, 0x48u, 0x16u, 0x01u, 0x40u,\r
+ 0x43u, 0x17u, 0x01u, 0x40u, 0x03u, 0x19u, 0x01u, 0x40u,\r
+ 0x02u, 0x1Bu, 0x01u, 0x40u, 0x07u, 0x40u, 0x01u, 0x40u,\r
+ 0x10u, 0x41u, 0x01u, 0x40u, 0x08u, 0x42u, 0x01u, 0x40u,\r
+ 0x05u, 0x43u, 0x01u, 0x40u, 0x08u, 0x44u, 0x01u, 0x40u,\r
+ 0x13u, 0x45u, 0x01u, 0x40u, 0x06u, 0x46u, 0x01u, 0x40u,\r
+ 0x01u, 0x47u, 0x01u, 0x40u, 0x08u, 0x48u, 0x01u, 0x40u,\r
+ 0x09u, 0x49u, 0x01u, 0x40u, 0x06u, 0x50u, 0x01u, 0x40u,\r
+ 0x36u, 0x02u, 0x65u, 0x02u, 0x00u, 0xC9u, 0x01u, 0x9Cu,\r
+ 0x18u, 0x08u, 0x19u, 0x04u, 0x1Cu, 0xE1u, 0x21u, 0x04u,\r
+ 0x30u, 0x04u, 0x31u, 0x08u, 0x34u, 0x03u, 0x82u, 0x0Fu,\r
+ 0x01u, 0x40u, 0x06u, 0x0Cu, 0x07u, 0x18u, 0x0Au, 0x60u,\r
+ 0x0Cu, 0x02u, 0x0Fu, 0x20u, 0x10u, 0x90u, 0x12u, 0x48u,\r
+ 0x14u, 0x90u, 0x16u, 0x24u, 0x17u, 0x24u, 0x19u, 0x24u,\r
+ 0x1Au, 0x10u, 0x1Bu, 0x09u, 0x1Fu, 0x03u, 0x23u, 0x04u,\r
+ 0x26u, 0x80u, 0x2Au, 0x90u, 0x2Cu, 0x01u, 0x2Du, 0x24u,\r
+ 0x2Fu, 0x12u, 0x30u, 0x01u, 0x31u, 0x40u, 0x32u, 0x1Cu,\r
+ 0x33u, 0x38u, 0x34u, 0xE0u, 0x36u, 0x02u, 0x37u, 0x07u,\r
+ 0x3Eu, 0x41u, 0x3Fu, 0x01u, 0x58u, 0x04u, 0x59u, 0x04u,\r
+ 0x5Bu, 0x04u, 0x5Cu, 0x99u, 0x5Fu, 0x01u, 0x85u, 0x01u,\r
+ 0x87u, 0x2Cu, 0x88u, 0x08u, 0x89u, 0x32u, 0x8Bu, 0x01u,\r
+ 0x8Fu, 0x08u, 0x90u, 0x04u, 0x92u, 0x02u, 0x96u, 0x03u,\r
+ 0x97u, 0x40u, 0x98u, 0x04u, 0x99u, 0x06u, 0x9Au, 0x01u,\r
+ 0x9Eu, 0x04u, 0xA0u, 0x08u, 0xA4u, 0x08u, 0xA5u, 0x01u,\r
+ 0xA7u, 0x1Au, 0xAAu, 0x04u, 0xABu, 0x40u, 0xACu, 0x08u,\r
+ 0xB2u, 0x07u, 0xB3u, 0x07u, 0xB4u, 0x08u, 0xB5u, 0x40u,\r
+ 0xB7u, 0x38u, 0xB8u, 0x20u, 0xB9u, 0x08u, 0xBEu, 0x10u,\r
+ 0xBFu, 0x10u, 0xD8u, 0x04u, 0xD9u, 0x0Bu, 0xDCu, 0x99u,\r
+ 0xDFu, 0x01u, 0x01u, 0x28u, 0x03u, 0x02u, 0x05u, 0x10u,\r
+ 0x0Au, 0x78u, 0x0Cu, 0x80u, 0x0Du, 0x10u, 0x0Eu, 0x60u,\r
+ 0x12u, 0x0Cu, 0x13u, 0x48u, 0x14u, 0x90u, 0x16u, 0x04u,\r
+ 0x17u, 0x40u, 0x18u, 0x40u, 0x19u, 0xA8u, 0x1Bu, 0x20u,\r
+ 0x1Eu, 0x20u, 0x1Fu, 0x14u, 0x21u, 0x84u, 0x22u, 0x01u,\r
+ 0x25u, 0x40u, 0x27u, 0x14u, 0x29u, 0x01u, 0x2Bu, 0x01u,\r
+ 0x2Eu, 0x14u, 0x31u, 0x80u, 0x32u, 0x18u, 0x36u, 0x08u,\r
+ 0x37u, 0x10u, 0x39u, 0x48u, 0x3Au, 0x08u, 0x3Bu, 0x01u,\r
+ 0x3Du, 0x80u, 0x3Fu, 0x14u, 0x69u, 0x80u, 0x6Bu, 0x01u,\r
+ 0x7Eu, 0x80u, 0x81u, 0x80u, 0x83u, 0x04u, 0x85u, 0x40u,\r
+ 0x8Bu, 0x10u, 0x8Fu, 0x01u, 0xC0u, 0x47u, 0xC2u, 0xFEu,\r
+ 0xC4u, 0xF7u, 0xCAu, 0x69u, 0xCCu, 0x6Eu, 0xCEu, 0x7Bu,\r
+ 0xDEu, 0x80u, 0xE0u, 0x01u, 0xE2u, 0x20u, 0x04u, 0x0Fu,\r
+ 0x05u, 0x55u, 0x06u, 0xF0u, 0x07u, 0xAAu, 0x0Bu, 0xFFu,\r
+ 0x0Eu, 0xFFu, 0x10u, 0xFFu, 0x13u, 0xFFu, 0x15u, 0x0Fu,\r
+ 0x16u, 0xFFu, 0x17u, 0xF0u, 0x1Du, 0x69u, 0x1Fu, 0x96u,\r
+ 0x24u, 0x33u, 0x25u, 0x33u, 0x26u, 0xCCu, 0x27u, 0xCCu,\r
+ 0x28u, 0x55u, 0x2Au, 0xAAu, 0x2Bu, 0xFFu, 0x2Cu, 0x96u,\r
+ 0x2Eu, 0x69u, 0x31u, 0xFFu, 0x34u, 0xFFu, 0x3Eu, 0x10u,\r
+ 0x3Fu, 0x01u, 0x56u, 0x02u, 0x57u, 0x2Cu, 0x58u, 0x04u,\r
+ 0x59u, 0x04u, 0x5Bu, 0x0Bu, 0x5Du, 0x90u, 0x5Fu, 0x01u,\r
+ 0x84u, 0x38u, 0x85u, 0x10u, 0x8Au, 0x45u, 0x8Eu, 0x38u,\r
+ 0x90u, 0x07u, 0x92u, 0x40u, 0x94u, 0x06u, 0x96u, 0x40u,\r
+ 0x98u, 0x08u, 0x9Cu, 0x02u, 0x9Du, 0x03u, 0x9Fu, 0x0Cu,\r
+ 0xA0u, 0x02u, 0xA1u, 0x05u, 0xA3u, 0x0Au, 0xA6u, 0x10u,\r
+ 0xA8u, 0x20u, 0xA9u, 0x06u, 0xABu, 0x09u, 0xACu, 0x01u,\r
+ 0xAEu, 0x02u, 0xB0u, 0x07u, 0xB1u, 0x0Fu, 0xB2u, 0x40u,\r
+ 0xB5u, 0x10u, 0xB6u, 0x38u, 0xBEu, 0x44u, 0xBFu, 0x11u,\r
+ 0xD4u, 0x40u, 0xD8u, 0x04u, 0xD9u, 0x04u, 0xDBu, 0x0Bu,\r
+ 0xDCu, 0x09u, 0xDDu, 0x90u, 0xDFu, 0x01u, 0x02u, 0x0Au,\r
+ 0x03u, 0x10u, 0x05u, 0x08u, 0x07u, 0x01u, 0x0Au, 0x64u,\r
+ 0x0Bu, 0x02u, 0x0Cu, 0x02u, 0x0Eu, 0x20u, 0x10u, 0x01u,\r
+ 0x12u, 0x40u, 0x13u, 0x14u, 0x15u, 0x04u, 0x16u, 0x08u,\r
+ 0x17u, 0x80u, 0x1Au, 0x50u, 0x1Bu, 0x41u, 0x1Du, 0x10u,\r
+ 0x20u, 0x04u, 0x23u, 0x80u, 0x27u, 0x40u, 0x28u, 0x40u,\r
+ 0x29u, 0x20u, 0x2Du, 0x04u, 0x2Fu, 0x24u, 0x31u, 0x80u,\r
+ 0x35u, 0x08u, 0x37u, 0x81u, 0x3Au, 0x04u, 0x3Cu, 0x20u,\r
+ 0x3Eu, 0x08u, 0x61u, 0x20u, 0x63u, 0x21u, 0x67u, 0x80u,\r
+ 0x6Cu, 0x20u, 0x6Du, 0x91u, 0x6Fu, 0x02u, 0x76u, 0x02u,\r
+ 0x77u, 0x02u, 0x78u, 0x02u, 0x7Au, 0x03u, 0x7Eu, 0x80u,\r
+ 0x81u, 0x20u, 0x82u, 0x04u, 0x83u, 0x40u, 0x84u, 0x80u,\r
+ 0x86u, 0x10u, 0x88u, 0x10u, 0x8Eu, 0x40u, 0x90u, 0x40u,\r
+ 0x91u, 0x80u, 0x92u, 0x02u, 0x93u, 0x08u, 0x95u, 0x60u,\r
+ 0x96u, 0x6Cu, 0x97u, 0x14u, 0x98u, 0x01u, 0x99u, 0x88u,\r
+ 0x9Au, 0x08u, 0x9Bu, 0x11u, 0x9Cu, 0x90u, 0x9Du, 0x11u,\r
+ 0x9Fu, 0x48u, 0xA1u, 0x80u, 0xA2u, 0x10u, 0xA3u, 0x20u,\r
+ 0xA4u, 0x80u, 0xA6u, 0x88u, 0xA7u, 0x01u, 0xAFu, 0x01u,\r
+ 0xB0u, 0x01u, 0xB3u, 0x40u, 0xB7u, 0x02u, 0xC0u, 0xA7u,\r
+ 0xC2u, 0x3Fu, 0xC4u, 0xEFu, 0xCAu, 0x65u, 0xCCu, 0xD8u,\r
+ 0xCEu, 0x62u, 0xD8u, 0x8Eu, 0xDEu, 0x81u, 0xE2u, 0x01u,\r
+ 0xE4u, 0x08u, 0xE6u, 0x03u, 0xE8u, 0x02u, 0x00u, 0x03u,\r
+ 0x0Au, 0x01u, 0x0Fu, 0x08u, 0x15u, 0x28u, 0x17u, 0x44u,\r
+ 0x19u, 0x2Cu, 0x1Bu, 0x81u, 0x1Eu, 0x03u, 0x1Fu, 0x03u,\r
+ 0x20u, 0x03u, 0x24u, 0x03u, 0x27u, 0x80u, 0x28u, 0x03u,\r
+ 0x2Bu, 0x04u, 0x2Du, 0xD4u, 0x2Fu, 0x22u, 0x30u, 0x02u,\r
+ 0x33u, 0xE0u, 0x34u, 0x01u, 0x35u, 0x18u, 0x36u, 0x02u,\r
+ 0x37u, 0x07u, 0x3Bu, 0x30u, 0x3Eu, 0x51u, 0x40u, 0x64u,\r
+ 0x41u, 0x02u, 0x42u, 0x30u, 0x45u, 0xE2u, 0x46u, 0x0Du,\r
+ 0x47u, 0xCFu, 0x48u, 0x37u, 0x49u, 0xFFu, 0x4Au, 0xFFu,\r
+ 0x4Bu, 0xFFu, 0x4Fu, 0x2Cu, 0x56u, 0x01u, 0x58u, 0x04u,\r
+ 0x59u, 0x04u, 0x5Au, 0x04u, 0x5Bu, 0x04u, 0x5Cu, 0x90u,\r
+ 0x5Du, 0x09u, 0x5Fu, 0x01u, 0x62u, 0xC0u, 0x66u, 0x80u,\r
+ 0x68u, 0x40u, 0x69u, 0x40u, 0x6Eu, 0x08u, 0x88u, 0x01u,\r
+ 0x8Au, 0x06u, 0x94u, 0x05u, 0x96u, 0x02u, 0x98u, 0x03u,\r
+ 0x9Au, 0x04u, 0x9Cu, 0x04u, 0x9Eu, 0x03u, 0xB6u, 0x07u,\r
+ 0xBAu, 0x80u, 0xD8u, 0x0Bu, 0xDCu, 0x09u, 0xDFu, 0x01u,\r
+ 0x01u, 0x01u, 0x02u, 0x04u, 0x05u, 0x10u, 0x09u, 0x40u,\r
+ 0x0Eu, 0x01u, 0x0Fu, 0x14u, 0x10u, 0x20u, 0x11u, 0x10u,\r
+ 0x13u, 0x02u, 0x19u, 0x42u, 0x1Bu, 0x10u, 0x1Eu, 0x01u,\r
+ 0x1Fu, 0x40u, 0x21u, 0x10u, 0x22u, 0x58u, 0x23u, 0x20u,\r
+ 0x29u, 0x04u, 0x2Au, 0x20u, 0x2Bu, 0x01u, 0x30u, 0x40u,\r
+ 0x32u, 0x58u, 0x39u, 0x80u, 0x41u, 0x10u, 0x42u, 0x50u,\r
+ 0x48u, 0x40u, 0x49u, 0x04u, 0x4Au, 0x08u, 0x51u, 0x08u,\r
+ 0x52u, 0x40u, 0x53u, 0x01u, 0x59u, 0xA8u, 0x5Au, 0x02u,\r
+ 0x60u, 0x64u, 0x61u, 0x80u, 0x69u, 0x40u, 0x6Au, 0x08u,\r
+ 0x6Bu, 0x88u, 0x70u, 0x90u, 0x71u, 0x01u, 0x72u, 0x20u,\r
+ 0x7Eu, 0x80u, 0x81u, 0x08u, 0x83u, 0x01u, 0x85u, 0x80u,\r
+ 0x88u, 0x20u, 0x89u, 0x10u, 0x8Cu, 0x10u, 0x8Eu, 0x40u,\r
+ 0x90u, 0x44u, 0x91u, 0x91u, 0x92u, 0x52u, 0x95u, 0x60u,\r
+ 0x96u, 0x2Cu, 0x97u, 0x97u, 0x99u, 0x80u, 0x9Au, 0x02u,\r
+ 0x9Bu, 0x02u, 0x9Cu, 0x42u, 0x9Du, 0x01u, 0x9Eu, 0x40u,\r
+ 0x9Fu, 0x08u, 0xA0u, 0x20u, 0xA1u, 0x40u, 0xA3u, 0x23u,\r
+ 0xA4u, 0x90u, 0xA5u, 0x20u, 0xA6u, 0x89u, 0xA7u, 0x10u,\r
+ 0xABu, 0x80u, 0xAFu, 0x20u, 0xB0u, 0x12u, 0xB5u, 0x08u,\r
+ 0xB6u, 0x08u, 0xC0u, 0x4Au, 0xC2u, 0xE1u, 0xC4u, 0x0Eu,\r
+ 0xCAu, 0x0Eu, 0xCCu, 0x0Eu, 0xCEu, 0x08u, 0xD0u, 0x07u,\r
+ 0xD2u, 0x04u, 0xD6u, 0x0Fu, 0xD8u, 0x0Fu, 0xDEu, 0x80u,\r
+ 0xE0u, 0x01u, 0xE2u, 0x10u, 0xE4u, 0x04u, 0xE6u, 0x02u,\r
+ 0xE8u, 0x01u, 0xEAu, 0x50u, 0xEEu, 0x80u, 0x10u, 0x04u,\r
+ 0x12u, 0x02u, 0x16u, 0x03u, 0x18u, 0x04u, 0x1Au, 0x01u,\r
+ 0x2Au, 0x04u, 0x2Eu, 0x04u, 0x32u, 0x07u, 0x58u, 0x04u,\r
+ 0x5Cu, 0x09u, 0x5Fu, 0x01u, 0x00u, 0x08u, 0x01u, 0x01u,\r
+ 0x03u, 0x0Au, 0x09u, 0x08u, 0x0Au, 0x84u, 0x0Du, 0x10u,\r
+ 0x0Eu, 0x60u, 0x10u, 0x22u, 0x11u, 0x12u, 0x13u, 0x02u,\r
+ 0x17u, 0xA0u, 0x18u, 0x20u, 0x1Cu, 0x20u, 0x1Eu, 0x20u,\r
+ 0x20u, 0x40u, 0x21u, 0x04u, 0x22u, 0x40u, 0x2Au, 0x82u,\r
+ 0x2Bu, 0x16u, 0x30u, 0x22u, 0x31u, 0x08u, 0x32u, 0x40u,\r
+ 0x38u, 0x60u, 0x39u, 0x01u, 0x3Bu, 0x04u, 0x41u, 0x08u,\r
+ 0x42u, 0x04u, 0x43u, 0x01u, 0x48u, 0x04u, 0x49u, 0x48u,\r
+ 0x50u, 0x42u, 0x51u, 0x20u, 0x52u, 0x45u, 0x58u, 0x80u,\r
+ 0x60u, 0x02u, 0x62u, 0x80u, 0x78u, 0x02u, 0x91u, 0x31u,\r
+ 0x92u, 0x40u, 0x96u, 0x04u, 0x97u, 0x14u, 0x98u, 0x80u,\r
+ 0x99u, 0x42u, 0x9Au, 0x02u, 0x9Bu, 0xA2u, 0x9Cu, 0x02u,\r
+ 0x9Du, 0x10u, 0x9Eu, 0x04u, 0xA0u, 0x20u, 0xA1u, 0x40u,\r
+ 0xA3u, 0x02u, 0xA4u, 0x10u, 0xA5u, 0x20u, 0xA6u, 0x81u,\r
+ 0xA8u, 0x80u, 0xA9u, 0x08u, 0xAAu, 0x04u, 0xABu, 0x01u,\r
+ 0xACu, 0x50u, 0xADu, 0x20u, 0xB2u, 0x40u, 0xB5u, 0x40u,\r
+ 0xB6u, 0x08u, 0xB7u, 0x20u, 0xC0u, 0x0Fu, 0xC2u, 0x7Eu,\r
+ 0xC4u, 0xCFu, 0xCAu, 0x0Fu, 0xCCu, 0x0Fu, 0xCEu, 0x0Fu,\r
+ 0xD0u, 0x07u, 0xD2u, 0x0Cu, 0xD6u, 0x08u, 0xD8u, 0x08u,\r
+ 0xDEu, 0x01u, 0xE4u, 0x40u, 0xE8u, 0x0Au, 0xEEu, 0x07u,\r
+ 0x8Eu, 0x01u, 0x9Eu, 0x41u, 0xA4u, 0x02u, 0xA8u, 0x41u,\r
+ 0xABu, 0x08u, 0xAEu, 0x09u, 0xAFu, 0x82u, 0xB2u, 0x01u,\r
+ 0xB4u, 0x41u, 0xB5u, 0x10u, 0xB6u, 0x20u, 0xB7u, 0x04u,\r
+ 0xE4u, 0x40u, 0xE8u, 0x40u, 0xEAu, 0x01u, 0xECu, 0xD0u,\r
+ 0x00u, 0x01u, 0x01u, 0x33u, 0x03u, 0xCCu, 0x08u, 0x02u,\r
+ 0x0Fu, 0xFFu, 0x11u, 0x96u, 0x13u, 0x69u, 0x17u, 0xFFu,\r
+ 0x1Du, 0x55u, 0x1Fu, 0xAAu, 0x21u, 0xFFu, 0x29u, 0x0Fu,\r
+ 0x2Bu, 0xF0u, 0x34u, 0x01u, 0x35u, 0xFFu, 0x36u, 0x02u,\r
+ 0x3Eu, 0x50u, 0x3Fu, 0x10u, 0x58u, 0x04u, 0x59u, 0x04u,\r
+ 0x5Fu, 0x01u, 0x82u, 0x02u, 0x85u, 0x33u, 0x86u, 0x80u,\r
+ 0x87u, 0xCCu, 0x88u, 0x80u, 0x8Au, 0x40u, 0x8Bu, 0xFFu,\r
+ 0x8Eu, 0x08u, 0x91u, 0xFFu, 0x92u, 0x04u, 0x94u, 0x06u,\r
+ 0x95u, 0x0Fu, 0x96u, 0x08u, 0x97u, 0xF0u, 0x98u, 0x80u,\r
+ 0x9Au, 0x20u, 0x9Du, 0x55u, 0x9Eu, 0x60u, 0x9Fu, 0xAAu,\r
+ 0xA0u, 0x02u, 0xA2u, 0x04u, 0xA4u, 0x10u, 0xA9u, 0x69u,\r
+ 0xAAu, 0x80u, 0xABu, 0x96u, 0xACu, 0x01u, 0xADu, 0xFFu,\r
+ 0xB0u, 0x01u, 0xB2u, 0x0Eu, 0xB4u, 0x10u, 0xB6u, 0xE0u,\r
+ 0xB7u, 0xFFu, 0xBEu, 0x15u, 0xBFu, 0x40u, 0xD8u, 0x04u,\r
+ 0xD9u, 0x04u, 0xDBu, 0x04u, 0xDCu, 0x09u, 0xDFu, 0x01u,\r
+ 0x00u, 0x01u, 0x01u, 0x20u, 0x06u, 0x61u, 0x07u, 0x08u,\r
+ 0x0Cu, 0x02u, 0x0Eu, 0x22u, 0x0Fu, 0x04u, 0x15u, 0x80u,\r
+ 0x16u, 0x10u, 0x17u, 0x11u, 0x1Au, 0x0Au, 0x1Cu, 0x48u,\r
+ 0x1Eu, 0x02u, 0x1Fu, 0x08u, 0x22u, 0x20u, 0x26u, 0x40u,\r
+ 0x28u, 0x08u, 0x29u, 0x02u, 0x2Cu, 0x08u, 0x2Fu, 0x02u,\r
+ 0x31u, 0x02u, 0x32u, 0x08u, 0x33u, 0x40u, 0x34u, 0x08u,\r
+ 0x35u, 0x02u, 0x37u, 0x40u, 0x38u, 0x82u, 0x3Du, 0x20u,\r
+ 0x3Fu, 0x08u, 0x5Du, 0x08u, 0x5Eu, 0x01u, 0x5Fu, 0xA0u,\r
+ 0x6Eu, 0x20u, 0x6Fu, 0x01u, 0x81u, 0x28u, 0x83u, 0x20u,\r
+ 0x84u, 0x04u, 0x8Au, 0x04u, 0x8Bu, 0x04u, 0x8Du, 0x40u,\r
+ 0x8Fu, 0x10u, 0x98u, 0x08u, 0x99u, 0x02u, 0x9Au, 0x10u,\r
+ 0x9Bu, 0x48u, 0xA0u, 0x08u, 0xA1u, 0x02u, 0xA6u, 0x61u,\r
+ 0xA8u, 0x08u, 0xA9u, 0x02u, 0xB4u, 0x08u, 0xB7u, 0x40u,\r
+ 0xC0u, 0xFAu, 0xC2u, 0xF0u, 0xC4u, 0xF0u, 0xCAu, 0x35u,\r
+ 0xCCu, 0xDBu, 0xCEu, 0x69u, 0xD6u, 0xF0u, 0xE2u, 0x80u,\r
+ 0xE4u, 0x60u, 0xE6u, 0x01u, 0xE8u, 0x50u, 0x82u, 0x01u,\r
+ 0x85u, 0x02u, 0x86u, 0x30u, 0x8Au, 0x40u, 0x8Fu, 0x08u,\r
+ 0xE2u, 0x23u, 0xE4u, 0x40u, 0xE8u, 0x02u, 0xEAu, 0x20u,\r
+ 0xEEu, 0x60u, 0xE0u, 0x01u, 0xE6u, 0x10u, 0xA8u, 0x40u,\r
+ 0xABu, 0x20u, 0xECu, 0x80u, 0x00u, 0xD0u, 0x04u, 0x24u,\r
+ 0x06u, 0x43u, 0x08u, 0x11u, 0x0Au, 0x22u, 0x0Cu, 0xD0u,\r
+ 0x10u, 0x20u, 0x12u, 0xD0u, 0x14u, 0x28u, 0x16u, 0x83u,\r
+ 0x18u, 0xD0u, 0x1Eu, 0x0Cu, 0x20u, 0xD0u, 0x26u, 0x01u,\r
+ 0x28u, 0xD0u, 0x2Eu, 0x02u, 0x30u, 0xF0u, 0x36u, 0x0Fu,\r
+ 0x3Au, 0x02u, 0x58u, 0x0Bu, 0x5Cu, 0x09u, 0x5Fu, 0x01u,\r
+ 0x80u, 0x38u, 0x81u, 0x46u, 0x84u, 0x43u, 0x85u, 0x39u,\r
+ 0x86u, 0x3Cu, 0x87u, 0x06u, 0x88u, 0x48u, 0x8Au, 0x20u,\r
+ 0x8Bu, 0x46u, 0x8Du, 0x04u, 0x8Fu, 0x20u, 0x90u, 0x38u,\r
+ 0x94u, 0x61u, 0x95u, 0x01u, 0x96u, 0x1Eu, 0x97u, 0x5Eu,\r
+ 0x98u, 0x23u, 0x99u, 0x42u, 0x9Au, 0x44u, 0x9Bu, 0x04u,\r
+ 0x9Cu, 0x18u, 0x9Eu, 0x20u, 0xA0u, 0x10u, 0xA1u, 0x46u,\r
+ 0xA4u, 0x28u, 0xA5u, 0x42u, 0xA6u, 0x10u, 0xA8u, 0x20u,\r
+ 0xA9u, 0x77u, 0xAAu, 0x18u, 0xABu, 0x08u, 0xADu, 0x46u,\r
+ 0xB1u, 0x08u, 0xB2u, 0x60u, 0xB3u, 0x70u, 0xB4u, 0x1Eu,\r
+ 0xB5u, 0x0Fu, 0xB6u, 0x01u, 0xB9u, 0x20u, 0xBAu, 0x08u,\r
+ 0xBBu, 0x0Cu, 0xBEu, 0x40u, 0xBFu, 0x01u, 0xD4u, 0x09u,\r
0xD8u, 0x0Bu, 0xD9u, 0x0Bu, 0xDBu, 0x0Bu, 0xDCu, 0x99u,\r
- 0xDDu, 0x90u, 0xDFu, 0x01u, 0x00u, 0x01u, 0x04u, 0x28u,\r
- 0x06u, 0x80u, 0x0Cu, 0x02u, 0x0Du, 0x01u, 0x0Eu, 0x29u,\r
- 0x17u, 0x69u, 0x1Au, 0x80u, 0x1Du, 0x30u, 0x1Eu, 0x28u,\r
- 0x1Fu, 0x40u, 0x21u, 0x02u, 0x22u, 0x02u, 0x25u, 0x90u,\r
- 0x27u, 0x08u, 0x29u, 0x40u, 0x2Fu, 0xAAu, 0x31u, 0x80u,\r
- 0x36u, 0x06u, 0x37u, 0x60u, 0x3Cu, 0x80u, 0x3Du, 0x20u,\r
- 0x3Eu, 0x81u, 0x4Bu, 0xC0u, 0x58u, 0x40u, 0x5Du, 0x24u,\r
- 0x5Eu, 0x02u, 0x5Fu, 0x40u, 0x60u, 0x01u, 0x66u, 0x40u,\r
- 0x78u, 0x02u, 0x7Cu, 0x02u, 0x98u, 0x40u, 0xC0u, 0x78u,\r
- 0xC2u, 0xF0u, 0xC4u, 0xF0u, 0xCAu, 0xF8u, 0xCCu, 0xF8u,\r
- 0xCEu, 0xB0u, 0xD6u, 0xF8u, 0xD8u, 0x18u, 0xDEu, 0x81u,\r
- 0xD6u, 0x08u, 0xDBu, 0x04u, 0xDDu, 0x90u, 0x00u, 0x01u,\r
- 0x02u, 0x40u, 0x05u, 0x10u, 0x07u, 0x61u, 0x0Du, 0x02u,\r
- 0x0Eu, 0x21u, 0x0Fu, 0x08u, 0x17u, 0x1Au, 0x1Du, 0x40u,\r
- 0x24u, 0x01u, 0x25u, 0x0Cu, 0x26u, 0x02u, 0x27u, 0x60u,\r
- 0x2Au, 0x02u, 0x2Bu, 0x80u, 0x2Cu, 0x02u, 0x2Eu, 0x01u,\r
- 0x2Fu, 0x28u, 0x36u, 0x46u, 0x3Cu, 0x80u, 0x3Du, 0x28u,\r
- 0x44u, 0x80u, 0x45u, 0xA8u, 0x4Cu, 0x80u, 0x4Du, 0x04u,\r
- 0x4Eu, 0x02u, 0x54u, 0x02u, 0x56u, 0x10u, 0x57u, 0x84u,\r
- 0x59u, 0x80u, 0x60u, 0x02u, 0x66u, 0x20u, 0x6Cu, 0x14u,\r
- 0x6Eu, 0xA1u, 0x6Fu, 0x3Bu, 0x74u, 0x40u, 0x77u, 0x02u,\r
- 0x7Cu, 0x02u, 0x94u, 0x28u, 0x95u, 0x04u, 0x96u, 0x01u,\r
- 0x99u, 0x10u, 0x9Bu, 0x08u, 0x9Cu, 0x02u, 0x9Du, 0x40u,\r
- 0x9Eu, 0x40u, 0x9Fu, 0x61u, 0xA1u, 0x32u, 0xA2u, 0x04u,\r
- 0xA4u, 0x42u, 0xA6u, 0x01u, 0xA7u, 0xAAu, 0xAAu, 0x40u,\r
- 0xADu, 0x21u, 0xC0u, 0xF0u, 0xC2u, 0xF0u, 0xC4u, 0x70u,\r
- 0xCAu, 0xF0u, 0xCCu, 0xD0u, 0xCEu, 0x70u, 0xD0u, 0xF0u,\r
- 0xD2u, 0x10u, 0xD6u, 0x08u, 0xD8u, 0x28u, 0xDEu, 0x80u,\r
- 0xEAu, 0x80u, 0x84u, 0x80u, 0x89u, 0x40u, 0x9Cu, 0x80u,\r
- 0xA1u, 0x40u, 0xAAu, 0x40u, 0xADu, 0x01u, 0xB0u, 0x85u,\r
- 0xB2u, 0x10u, 0xE6u, 0x20u, 0x00u, 0x04u, 0x02u, 0x08u,\r
- 0x04u, 0x10u, 0x05u, 0x18u, 0x06u, 0x0Cu, 0x07u, 0x25u,\r
- 0x08u, 0x20u, 0x09u, 0x20u, 0x0Au, 0x0Cu, 0x0Bu, 0x18u,\r
- 0x0Eu, 0x03u, 0x0Fu, 0x01u, 0x11u, 0x08u, 0x12u, 0x04u,\r
- 0x13u, 0x33u, 0x14u, 0x03u, 0x19u, 0x2Eu, 0x1Au, 0x30u,\r
- 0x1Bu, 0x10u, 0x1Cu, 0x03u, 0x20u, 0x03u, 0x26u, 0x01u,\r
- 0x28u, 0x03u, 0x2Eu, 0x48u, 0x30u, 0x40u, 0x32u, 0x01u,\r
- 0x34u, 0x3Cu, 0x35u, 0x38u, 0x36u, 0x02u, 0x37u, 0x07u,\r
- 0x3Bu, 0x20u, 0x3Eu, 0x44u, 0x54u, 0x40u, 0x58u, 0x0Bu,\r
- 0x59u, 0x0Bu, 0x5Bu, 0x0Bu, 0x5Cu, 0x99u, 0x5Du, 0x90u,\r
- 0x5Fu, 0x01u, 0x80u, 0x01u, 0x82u, 0x02u, 0x88u, 0x06u,\r
- 0x8Bu, 0x07u, 0x8Eu, 0x10u, 0x91u, 0x01u, 0x92u, 0x08u,\r
- 0x97u, 0x02u, 0x98u, 0x02u, 0x9Au, 0x01u, 0xA1u, 0x07u,\r
- 0xA8u, 0x01u, 0xA9u, 0x04u, 0xAAu, 0x04u, 0xACu, 0x08u,\r
- 0xAEu, 0x10u, 0xB0u, 0x07u, 0xB1u, 0x07u, 0xB2u, 0x07u,\r
- 0xB6u, 0x18u, 0xB8u, 0x0Au, 0xBEu, 0x40u, 0xBFu, 0x01u,\r
- 0xD8u, 0x0Bu, 0xD9u, 0x04u, 0xDBu, 0x04u, 0xDCu, 0x09u,\r
- 0xDFu, 0x01u, 0x00u, 0x10u, 0x01u, 0x40u, 0x03u, 0x40u,\r
- 0x05u, 0x10u, 0x07u, 0x61u, 0x09u, 0x20u, 0x0Au, 0x80u,\r
- 0x0Eu, 0x69u, 0x10u, 0x02u, 0x12u, 0x08u, 0x13u, 0x20u,\r
- 0x16u, 0x12u, 0x17u, 0x12u, 0x18u, 0x10u, 0x19u, 0x81u,\r
- 0x1Du, 0x84u, 0x1Eu, 0x4Au, 0x1Fu, 0x10u, 0x21u, 0x01u,\r
- 0x25u, 0x40u, 0x27u, 0x08u, 0x29u, 0x11u, 0x32u, 0x0Au,\r
- 0x35u, 0x10u, 0x36u, 0x02u, 0x3Bu, 0x20u, 0x3Du, 0x88u,\r
- 0x3Eu, 0x20u, 0x46u, 0x20u, 0x47u, 0x08u, 0x64u, 0x05u,\r
- 0x65u, 0x04u, 0x68u, 0x02u, 0x78u, 0x02u, 0x7Cu, 0x02u,\r
- 0x8Du, 0x40u, 0x92u, 0x01u, 0x98u, 0x02u, 0x99u, 0x10u,\r
- 0x9Au, 0x12u, 0x9Bu, 0x73u, 0x9Cu, 0x80u, 0x9Du, 0x80u,\r
- 0x9Eu, 0x20u, 0xA0u, 0x80u, 0xA1u, 0x24u, 0xA2u, 0x12u,\r
- 0xA5u, 0x80u, 0xA6u, 0x01u, 0xC0u, 0xFBu, 0xC2u, 0xFAu,\r
- 0xC4u, 0xF3u, 0xCAu, 0x05u, 0xCCu, 0xA3u, 0xCEu, 0x74u,\r
- 0xD8u, 0x70u, 0xDEu, 0x81u, 0xE0u, 0x40u, 0x33u, 0x40u,\r
- 0xCCu, 0x10u, 0x9Fu, 0x40u, 0x9Fu, 0x40u, 0xABu, 0x40u,\r
- 0xEEu, 0x80u, 0x14u, 0x40u, 0xC4u, 0x04u, 0xB0u, 0x40u,\r
- 0xEAu, 0x01u, 0x20u, 0x10u, 0x26u, 0x80u, 0x8Eu, 0x80u,\r
- 0xC8u, 0x60u, 0x08u, 0x02u, 0x5Bu, 0x20u, 0x5Fu, 0x40u,\r
- 0x84u, 0x02u, 0x8Bu, 0x20u, 0x93u, 0x40u, 0xA8u, 0x10u,\r
- 0xAFu, 0x40u, 0xC2u, 0x10u, 0xD4u, 0x80u, 0xD6u, 0x20u,\r
- 0xE4u, 0x40u, 0xECu, 0x80u, 0xEEu, 0x40u, 0x01u, 0x01u,\r
- 0x0Bu, 0x01u, 0x11u, 0x01u, 0x1Bu, 0x01u, 0x00u, 0x03u,\r
- 0x1Fu, 0x00u, 0x20u, 0x00u, 0x00u, 0x91u, 0xFFu, 0x6Eu,\r
- 0x7Fu, 0x24u, 0x80u, 0x00u, 0x90u, 0x6Cu, 0x40u, 0x00u,\r
- 0x00u, 0x71u, 0x60u, 0x82u, 0xC0u, 0x10u, 0x08u, 0xEFu,\r
- 0x00u, 0x00u, 0x9Fu, 0x00u, 0xC0u, 0x6Cu, 0x02u, 0x00u,\r
- 0xC0u, 0x6Cu, 0x01u, 0x00u, 0x80u, 0x24u, 0x00u, 0x48u,\r
- 0xC0u, 0x00u, 0x04u, 0x6Cu, 0x00u, 0x48u, 0x00u, 0x00u,\r
- 0x00u, 0x0Fu, 0x00u, 0xF0u, 0x00u, 0x00u, 0xFFu, 0x10u,\r
- 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x40u,\r
- 0x32u, 0x05u, 0x10u, 0x00u, 0x04u, 0xFEu, 0xDBu, 0xCBu,\r
- 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,\r
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u,\r
- 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u,\r
+ 0xDDu, 0x90u, 0xDFu, 0x01u, 0x00u, 0x08u, 0x01u, 0x01u,\r
+ 0x03u, 0x08u, 0x04u, 0x04u, 0x05u, 0x10u, 0x06u, 0x80u,\r
+ 0x07u, 0x02u, 0x09u, 0x49u, 0x0Au, 0x04u, 0x0Cu, 0x20u,\r
+ 0x0Eu, 0x42u, 0x0Fu, 0x10u, 0x10u, 0x20u, 0x11u, 0x10u,\r
+ 0x12u, 0x40u, 0x15u, 0x19u, 0x16u, 0x01u, 0x19u, 0x54u,\r
+ 0x1Au, 0x04u, 0x1Bu, 0x1Cu, 0x1Eu, 0x42u, 0x20u, 0x0Cu,\r
+ 0x21u, 0x08u, 0x23u, 0x94u, 0x29u, 0x14u, 0x2Au, 0x02u,\r
+ 0x2Bu, 0x02u, 0x30u, 0x20u, 0x31u, 0x08u, 0x38u, 0x80u,\r
+ 0x39u, 0x11u, 0x3Bu, 0x04u, 0x59u, 0x0Au, 0x5Bu, 0xA0u,\r
+ 0x61u, 0x40u, 0x78u, 0x02u, 0x7Eu, 0x80u, 0x8Bu, 0x01u,\r
+ 0x90u, 0x80u, 0x91u, 0x19u, 0x96u, 0x04u, 0x97u, 0x14u,\r
+ 0x98u, 0x02u, 0x99u, 0x0Au, 0x9Au, 0xC3u, 0x9Bu, 0x02u,\r
+ 0x9Du, 0x10u, 0x9Fu, 0x01u, 0xA0u, 0x20u, 0xA1u, 0x41u,\r
+ 0xA2u, 0x80u, 0xA3u, 0x02u, 0xA4u, 0x04u, 0xA5u, 0x08u,\r
+ 0xA6u, 0x01u, 0xA7u, 0x1Cu, 0xC0u, 0xFEu, 0xC2u, 0xFFu,\r
+ 0xC4u, 0xFEu, 0xCAu, 0x0Fu, 0xCCu, 0x06u, 0xCEu, 0x0Fu,\r
+ 0xD6u, 0x0Fu, 0xD8u, 0x08u, 0xDEu, 0x81u, 0xE4u, 0x20u,\r
+ 0xECu, 0x80u, 0xA4u, 0x02u, 0xB2u, 0x40u, 0xECu, 0x80u,\r
+ 0xB0u, 0x02u, 0xECu, 0x80u, 0x58u, 0x10u, 0x80u, 0x80u,\r
+ 0x86u, 0x80u, 0x88u, 0x10u, 0xD4u, 0x80u, 0xE2u, 0x40u,\r
+ 0xE6u, 0x80u, 0x53u, 0x81u, 0x57u, 0x0Au, 0x59u, 0x04u,\r
+ 0x5Cu, 0x02u, 0x60u, 0x08u, 0x64u, 0x80u, 0x81u, 0x04u,\r
+ 0x82u, 0x40u, 0x84u, 0x08u, 0x98u, 0x80u, 0x9Au, 0x80u,\r
+ 0xD4u, 0xE0u, 0xD6u, 0xE0u, 0xD8u, 0xC0u, 0xE2u, 0x20u,\r
+ 0xE6u, 0x90u, 0x8Cu, 0x02u, 0x92u, 0x40u, 0x9Au, 0x80u,\r
+ 0x9Cu, 0x02u, 0xAFu, 0x80u, 0xB3u, 0x02u, 0xB7u, 0x09u,\r
+ 0xEEu, 0x10u, 0x23u, 0x08u, 0x8Fu, 0x08u, 0x92u, 0x40u,\r
+ 0x9Au, 0x80u, 0xC8u, 0x10u, 0x0Cu, 0x01u, 0x51u, 0x02u,\r
+ 0x54u, 0x20u, 0x80u, 0x20u, 0x8Cu, 0x40u, 0xC2u, 0x04u,\r
+ 0xD4u, 0x03u, 0xE6u, 0x08u, 0x02u, 0x04u, 0x03u, 0x10u,\r
+ 0x04u, 0x80u, 0x07u, 0x40u, 0x09u, 0x02u, 0x0Bu, 0x01u,\r
+ 0x0Cu, 0x18u, 0x80u, 0x08u, 0x85u, 0x02u, 0x94u, 0x80u,\r
+ 0x9Cu, 0x10u, 0x9Fu, 0x10u, 0xADu, 0x02u, 0xB0u, 0x11u,\r
+ 0xB7u, 0x10u, 0xC0u, 0x0Fu, 0xC2u, 0x0Fu, 0xEAu, 0x04u,\r
+ 0xEEu, 0x06u, 0x83u, 0x40u, 0x8Eu, 0x04u, 0x93u, 0x01u,\r
+ 0x9Au, 0x04u, 0x9Bu, 0x40u, 0xE6u, 0x08u, 0xABu, 0x01u,\r
+ 0x23u, 0x10u, 0x27u, 0x08u, 0x88u, 0x01u, 0x92u, 0x40u,\r
+ 0x97u, 0x10u, 0x9Au, 0x80u, 0xB3u, 0x10u, 0xC8u, 0x60u,\r
+ 0x08u, 0x01u, 0x56u, 0x80u, 0x5Au, 0x40u, 0x92u, 0x40u,\r
+ 0x9Au, 0x80u, 0x9Cu, 0x01u, 0xB3u, 0x08u, 0xC2u, 0x10u,\r
+ 0xD4u, 0xC0u, 0x01u, 0x01u, 0x09u, 0x01u, 0x0Bu, 0x01u,\r
+ 0x0Du, 0x01u, 0x11u, 0x01u, 0x1Bu, 0x01u, 0x00u, 0x00u,\r
+ 0xC0u, 0x01u, 0x02u, 0x00u, 0x00u, 0x08u, 0xFFu, 0x21u,\r
+ 0x80u, 0x40u, 0x00u, 0x00u, 0x90u, 0x40u, 0x40u, 0x00u,\r
+ 0x00u, 0x10u, 0x60u, 0x80u, 0x7Fu, 0x22u, 0x80u, 0x08u,\r
+ 0x1Fu, 0x01u, 0x20u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u,\r
+ 0xC0u, 0x01u, 0x01u, 0x00u, 0xC0u, 0x07u, 0x04u, 0x18u,\r
+ 0xC0u, 0x01u, 0x08u, 0x00u, 0x00u, 0x01u, 0x9Fu, 0x00u,\r
+ 0x00u, 0x3Fu, 0xFFu, 0x80u, 0x00u, 0x00u, 0x00u, 0x40u,\r
+ 0x00u, 0x82u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x01u,\r
+ 0x63u, 0x02u, 0x50u, 0x00u, 0x04u, 0x0Eu, 0xFCu, 0xBDu,\r
+ 0x3Du, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,\r
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u,\r
+ 0x04u, 0x0Bu, 0x0Bu, 0x04u, 0x90u, 0x99u, 0x00u, 0x01u,\r
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u,\r
0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0x00u, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0xFFu, 0xFFu, 0x00u, 0xFFu, 0x00u, 0x00u, 0x00u,\r
0x08u, 0x00u, 0x30u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x10u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x01u, 0x02u, 0x00u, 0xF1u, 0x0Eu,\r
0x0Eu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0x00u, 0xFCu, 0xFCu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0xF0u, 0x00u, 0x0Fu, 0xF0u, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0x00u, 0x01u, 0x00u, 0x00u, 0xF0u, 0x0Fu, 0x0Fu, 0x00u,\r
- 0x00u, 0x00u, 0x00u, 0x01u\r
+ 0x00u, 0xFCu, 0xFCu, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u,\r
+ 0x0Fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u,\r
+ 0xF0u, 0x0Fu, 0x0Fu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x01u\r
};\r
\r
#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
0xBCu, 0x90u, 0xACu, 0xAFu\r
};\r
\r
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
+__attribute__ ((__section__(".cyeeprom"), used))\r
+#elif defined(__ICCARM__)\r
+#pragma location=".cyeeprom"\r
+#else\r
+#error "Unsupported toolchain"\r
+#endif\r
+const uint8 cy_eeprom[] = {\r
+ 0x00u, 0x20u, 0x63u, 0x6Fu, 0x64u, 0x65u, 0x73u, 0x72u,\r
+ 0x63u, 0x20u, 0x20u, 0x20u, 0x20u, 0x20u, 0x20u, 0x20u,\r
+ 0x20u, 0x20u, 0x53u, 0x43u, 0x53u, 0x49u, 0x32u, 0x53u,\r
+ 0x44u, 0x32u, 0x2Eu, 0x30u, 0x61u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x63u, 0x6Fu, 0x64u, 0x65u, 0x73u, 0x72u, 0x63u, 0x5Fu,\r
+ 0x30u, 0x30u, 0x30u, 0x30u, 0x30u, 0x30u, 0x30u, 0x31u,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu,\r
+ 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu, 0xFFu\r
+};\r
+\r
#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
__attribute__ ((__section__(".cyflashprotect"), used))\r
#elif defined(__ICCARM__)\r
+:400000000020636F646573726320202020202020202053435349325344322E30610000000000000000000000000000000000000000000000000000000000000000000000B1\r
+:40004000636F64657372635F3030303030303031FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFED\r
+:40008000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF80\r
+:4000C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF40\r
+:40010000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF\r
+:40014000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBF\r
+:40018000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7F\r
+:4001C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3F\r
+:40020000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE\r
+:40024000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBE\r
+:40028000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7E\r
+:4002C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3E\r
+:40030000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFD\r
+:40034000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBD\r
+:40038000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7D\r
+:4003C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3D\r
+:40040000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC\r
+:40044000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBC\r
+:40048000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7C\r
+:4004C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3C\r
+:40050000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB\r
+:40054000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBB\r
+:40058000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7B\r
+:4005C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3B\r
+:40060000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA\r
+:40064000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFBA\r
+:40068000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF7A\r
+:4006C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF3A\r
+:40070000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF9\r
+:40074000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB9\r
+:40078000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF79\r
+:4007C000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF39\r
+:00000001FF\r
+++ /dev/null
-@REM This script allows a 3rd party IDE to use CyHexTool to perform\r
-@REM any post processing that is necessary to convert the raw flash\r
-@REM image into a complete hex file to use in programming the PSoC.\r
-@REM USAGE: post_link.bat\r
-@REM arg1: Persistant path back to the directory containing the app project.\r
-@REM arg2: Path (relative to arg1) of the directory where the hex files go.\r
-@REM arg3: Name of the project.\r
-@REM NOTE: This script is auto generated. Do not modify.\r
-\r
-"C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\bin\cyvalidateide.exe" -dev CY8C5268AXI-LP047 -ide "%~1\%~3" -flsAddr 0x0 -flsSize 0x40000 -sramAddr 0x1FFF8000 -sramSize 0x10000\r
-@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% \r
-move "%~1\%~2\%~n3.hex" "%~1\%~2\%~n3.ihx"\r
-@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% \r
-"C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\bin\cyhextool" -o "%~1\%~2\%~n3.hex" -f "%~1\%~2\%~n3.ihx" -prot "%~dp0protect.hex" -id 2E12F069 -a EEPROM=90200000:800,PROGRAM=00000000:40000,CONFIG=80000000:8000,PROTECT=90400000:100 -meta 0001 -cunv 00004005 -wonv BC90ACAF -ecc "%~dp0config.hex" \r
-@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% \r
-CD /D "C:\Keil\UV4"\r
-@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% \r
-IF NOT EXIST "Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\SCSI2SD.svd" rem "Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\SCSI2SD.sfr"\r
-@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% \r
#include <SCSI_In_DBx.h>\r
#include <SCSI_Out_DBx_aliases.h>\r
#include <SCSI_Out_DBx.h>\r
-#include <SDCard.h>\r
-#include <SDCard_PVT.h>\r
-#include <SD_MISO_aliases.h>\r
-#include <SD_MISO.h>\r
-#include <SD_MOSI_aliases.h>\r
-#include <SD_MOSI.h>\r
-#include <SD_SCK_aliases.h>\r
-#include <SD_SCK.h>\r
-#include <SD_CS_aliases.h>\r
-#include <SD_CS.h>\r
-#include <SD_DAT1_aliases.h>\r
-#include <SD_DAT1.h>\r
-#include <SD_DAT2_aliases.h>\r
-#include <SD_DAT2.h>\r
-#include <SD_WP_aliases.h>\r
-#include <SD_WP.h>\r
+#include <SD_Clk_Ctl.h>\r
+#include <SD_Data_Clk.h>\r
+#include <SD_Init_Clk.h>\r
#include <SD_CD_aliases.h>\r
#include <SD_CD.h>\r
-#include <SCSI_ID_aliases.h>\r
-#include <PARITY_EN_aliases.h>\r
-#include <PARITY_EN.h>\r
+#include <SD_WP_aliases.h>\r
+#include <SD_WP.h>\r
+#include <SD_DAT2_aliases.h>\r
+#include <SD_DAT2.h>\r
+#include <SD_DAT1_aliases.h>\r
+#include <SD_DAT1.h>\r
+#include <SCSI_CTL_IO.h>\r
#include <SCSI_In_aliases.h>\r
#include <SCSI_Out_aliases.h>\r
-#include <LED1_aliases.h>\r
-#include <LED1.h>\r
-#include <SD_Init_Clk.h>\r
-#include <SD_Data_Clk.h>\r
-#include <SD_Clk_Ctl.h>\r
+#include <CFG_EEPROM.h>\r
+#include <SD_CS_aliases.h>\r
+#include <SD_CS.h>\r
+#include <SD_SCK_aliases.h>\r
+#include <SD_SCK.h>\r
+#include <SD_MOSI_aliases.h>\r
+#include <SD_MOSI.h>\r
#include <SCSI_RST_aliases.h>\r
#include <SCSI_RST.h>\r
#include <SCSI_ATN_aliases.h>\r
#include <SCSI_ATN.h>\r
#include <SCSI_RST_ISR.h>\r
#include <SCSI_ATN_ISR.h>\r
+#include <LED1_aliases.h>\r
+#include <LED1.h>\r
+#include <SDCard.h>\r
+#include <SDCard_PVT.h>\r
+#include <SD_MISO_aliases.h>\r
+#include <SD_MISO.h>\r
#include <core_cm3_psoc5.h>\r
#include <core_cm3.h>\r
#include <CyDmac.h>\r
+++ /dev/null
-<?xml version="1.0" encoding="utf-8"?>\r
-<!--DO NOT EDIT. This document is generated by PSoC Creator design builds.-->\r
-<PSoCCreatorIdeExport Version="1">\r
- <Device Part="CY8C5268AXI-LP047" Processor="CortexM3" DeviceID="2E12F069" />\r
- <Toolchains>\r
- <Toolchain Name="ARM GCC" Selected="True">\r
- <Tool Name="prebuild" Command="" Options="" />\r
- <Tool Name="assembler" Command="arm-none-eabi-as.exe" Options="-I. -I./Generated_Source/PSoC5 -mcpu=cortex-m3 -mthumb -g -alh=${OutputDir}/${CompileFile}.lst " />\r
- <Tool Name="compiler" Command="arm-none-eabi-gcc.exe" Options="-I. -I./Generated_Source/PSoC5 -Wno-main -mcpu=cortex-m3 -mthumb -Wall -g -D NDEBUG -Wa,-alh=${OutputDir}\${CompileFile}.lst -Os -ffunction-sections " />\r
- <Tool Name="linker" Command="arm-none-eabi-gcc.exe" Options="-mthumb -march=armv7-m -mfix-cortex-m3-ldrd -T .\Generated_Source\PSoC5\cm3gcc.ld -g -Wl,-Map,${OutputDir}\${ProjectShortName}.map -specs=nano.specs -Wl,--gc-sections " />\r
- <Tool Name="postbuild" Command="" Options="" />\r
- </Toolchain>\r
- <Toolchain Name="ARM Keil MDK" Selected="False">\r
- <Tool Name="prebuild" Command="" Options="" />\r
- <Tool Name="assembler" Command="armasm.exe" Options="-i. -iGenerated_Source/PSoC5 --diag_style=gnu --thumb --cpu=Cortex-M3 -g --list=${OutputDir}/${CompileFile}.lst " />\r
- <Tool Name="compiler" Command="armcc.exe" Options="-I. -I./Generated_Source/PSoC5 --diag_suppress=951 --diag_style=gnu --cpu=Cortex-M3 -g -D NDEBUG --signed_chars --list -Ospace --split_sections " />\r
- <Tool Name="linker" Command="armlink.exe" Options="--diag_style=gnu --no_startup --cpu=Cortex-M3 --scatter .\Generated_Source\PSoC5\Cm3RealView.scat --map --list ${OutputDir}\${ProjectShortName}.map " />\r
- <Tool Name="postbuild" Command="" Options="" />\r
- </Toolchain>\r
- </Toolchains>\r
- <Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" Version="4.0" Type="Normal">\r
- <CMSIS_SVD_File>SCSI2SD.svd</CMSIS_SVD_File>\r
- <Datasheet>SCSI2SD_datasheet.pdf</Datasheet>\r
- <LinkerFiles>\r
- <LinkerFile Toolchain="ARM GCC">.\Generated_Source\PSoC5\cm3gcc.ld</LinkerFile>\r
- <LinkerFile Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\Cm3RealView.scat</LinkerFile>\r
- <LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile>\r
- </LinkerFiles>\r
- <Folders>\r
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--- /dev/null
+\r
+//`#start header` -- edit after this line, do not edit this line\r
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+`include "cypress.v"\r
+//`#end` -- edit above this line, do not edit this line\r
+// Generated on 10/15/2013 at 22:01\r
+// Component: OddParityGen\r
+module OddParityGen (\r
+ output DBP,\r
+ input [7:0] DBx,\r
+ input EN\r
+);\r
+\r
+//`#start body` -- edit after this line, do not edit this line\r
+\r
+ // For some reason the "simple" implementation uses up about 34% of all\r
+ // PLD resources on a PSoC 5LP\r
+ // 1 ^ DBx[0] ^ DBx[1] ^ DBx[2] ^ DBx[3] ^ DBx[4] ^ DBx[5] ^ DBx[6] ^ DBx[7]\r
+\r
+ // Breaking the expression up into parts seems to use much less resources.\r
+ wire tmp = 1 ^ DBx[0];\r
+ wire tmpa = DBx[1] ^ DBx[2];\r
+ wire tmpb = DBx[3] ^ DBx[4];\r
+ wire tmpc = DBx[5] ^ DBx[6] ^ DBx[7];\r
+ assign DBP = EN ? tmp ^ tmpa ^ tmpb ^ tmpc : 0;\r
+//`#end` -- edit above this line, do not edit this line\r
+endmodule\r
+//`#start footer` -- edit after this line, do not edit this line\r
+//`#end` -- edit above this line, do not edit this line\r
--- /dev/null
+<?xml version="1.0" encoding="utf-8"?>\r
+<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
+ <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ </block>\r
+ <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_ATN_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_Init_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SD_Clk_Ctl_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />\r
+ </block>\r
+ <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_Overclock" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_CTL_IO" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_CTL_IO_CONTROL_REG" address="0x40006470" bitWidth="8" desc="" />\r
+ </block>\r
+ <block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_WP" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+</blockRegMap>
\ No newline at end of file
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</CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52>\r
</CyGuid_d8451a8e-a4ea-4e21-aba8-966eaa7ea07d>\r
+<CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtComponent" version="1">\r
+<CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtPhyFolder" version="1">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="OddParityGen" persistent=".\OddParityGen">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
+<dependencies>\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="OddParityGen.cysym" persistent=".\OddParityGen\OddParityGen.cysym">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="NONE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="OddParityGen.v" persistent=".\OddParityGen\OddParityGen.v">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="NONE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</dependencies>\r
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
+<filters />\r
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
+</CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52>\r
+</CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e>\r
+<CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtComponent" version="1">\r
+<CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtPhyFolder" version="1">\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="scsiTarget" persistent=".\scsiTarget">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
+<dependencies>\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="scsiTarget.cysym" persistent=".\scsiTarget\scsiTarget.cysym">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="NONE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="scsiTarget.v" persistent=".\scsiTarget\scsiTarget.v">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="NONE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</dependencies>\r
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
+<filters />\r
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
+</CyGuid_813b8d13-518a-4dc8-91ba-cda6042dfb52>\r
+</CyGuid_4429d4ed-fe84-42d0-9e9f-19aee0ff4e7e>\r
</dependencies>\r
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
</CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>\r
<boot_component v="cy_boot_v4_0" />\r
<BootloaderTag hexFile="" elfFile="" />\r
-<current_generation v="0" />\r
+<current_generation v="2" />\r
</CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>\r
</CyXmlSerializer>
\ No newline at end of file
--- /dev/null
+<?xml version="1.0" encoding="utf-8"?>\r
+<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">\r
+ <name>CY8C5268AXI_LP047</name>\r
+ <version>0.1</version>\r
+ <description>CY8C52LP</description>\r
+ <addressUnitBits>8</addressUnitBits>\r
+ <width>32</width>\r
+ <peripherals>\r
+ <peripheral>\r
+ <name>SD_Clk_Ctl</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x4000647B</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x1</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SD_Clk_Ctl_CONTROL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
+ <peripheral>\r
+ <name>SCSI_CTL_IO</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x40006470</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x1</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_CTL_IO_CONTROL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
+ </peripherals>\r
+</device>
\ No newline at end of file
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+\r
+#include "device.h"\r
+#include "config.h"\r
+\r
+#include <string.h>\r
+\r
+// CYDEV_EEPROM_ROW_SIZE == 16.\r
+static char magic[CYDEV_EEPROM_ROW_SIZE] = "codesrc_00000001";\r
+\r
+// Config shadow RAM (copy of EEPROM)\r
+static Config shadow =\r
+{\r
+ 0, // SCSI ID\r
+ " codesrc", // vendor (68k Apple Drive Setup: Set to " SEAGATE")\r
+ " SCSI2SD", //prodId (68k Apple Drive Setup: Set to " ST225N")\r
+ "2.0a", // revision (68k Apple Drive Setup: Set to "1.0 ")\r
+ 1, // enable parity\r
+ 0, // disable unit attention,\r
+ 0, // overclock SPI\r
+ 0, // Max blocks (0 == disabled)\r
+ "" // reserved\r
+};\r
+\r
+// Global\r
+Config* config = NULL;\r
+\r
+void configInit()\r
+{\r
+ // We could map cfgPtr directly into the EEPROM memory,\r
+ // but that would waste power. Copy it to RAM then turn off\r
+ // the EEPROM. \r
+ CFG_EEPROM_Start();\r
+ CyDelayUs(5); // 5us to start per datasheet.\r
+ \r
+ // Check magic\r
+ int shadowRows = (sizeof(shadow) / CYDEV_EEPROM_ROW_SIZE) + 1;\r
+ int shadowBytes = CYDEV_EEPROM_ROW_SIZE * shadowRows;\r
+ uint8* eeprom = (uint8*)CYDEV_EE_BASE; \r
+ if (memcmp(eeprom + shadowBytes, magic, sizeof(magic))) \r
+ {\r
+ CySetTemp();\r
+ int row;\r
+ int status = CYRET_SUCCESS;\r
+ for (row = 0; (row < shadowRows) && (status == CYRET_SUCCESS); ++row)\r
+ {\r
+ CFG_EEPROM_Write(((uint8*)&shadow) + (row * CYDEV_EEPROM_ROW_SIZE), row);\r
+ }\r
+ if (status == CYRET_SUCCESS)\r
+ {\r
+ CFG_EEPROM_Write((uint8*)magic, row);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ memcpy(&shadow, eeprom, sizeof(shadow));\r
+ }\r
+ config = &shadow;\r
+ CFG_EEPROM_Stop();\r
+}
\ No newline at end of file
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+#ifndef Config_H\r
+#define Config_H\r
+\r
+#include "device.h"\r
+\r
+typedef struct\r
+{\r
+ uint8 scsiId;\r
+ char vendor[8];\r
+ char prodId[16];\r
+ char revision[4];\r
+ uint8 enableParity;\r
+ uint8 enableUnitAttention;\r
+ uint8 overclockSPI;\r
+ uint32 maxBlocks;\r
+\r
+ // Pad to 64 bytes, which is what we can fit into a USB HID packet.\r
+ char reserved[28]; \r
+} Config;\r
+\r
+extern Config* config;\r
+\r
+void configInit();\r
+\r
+#endif\r
\r
#include "device.h"\r
#include "scsi.h"\r
+#include "config.h"\r
#include "disk.h"\r
#include "sd.h"\r
\r
{\r
blockDev.state = blockDev.state | DISK_INITIALISED;\r
\r
- // TODO artificially limit this value according to EEPROM config.\r
- blockDev.capacity = sdDev.capacity;\r
+ // artificially limit this value according to EEPROM config.\r
+ blockDev.capacity =\r
+ (config->maxBlocks && (sdDev.capacity > config->maxBlocks))\r
+ ? config->maxBlocks : sdDev.capacity;\r
}\r
return result;\r
}\r
\r
#include "device.h"\r
#include "scsi.h"\r
+#include "config.h"\r
#include "inquiry.h"\r
\r
#include <string.h>\r
\r
-static const uint8 StandardResponse[] =\r
+static uint8 StandardResponse[] =\r
{\r
0x00, // "Direct-access device". AKA standard hard disk\r
0x00, // device type qualifier\r
0x02, // SCSI-2 Inquiry response\r
31, // standard length\r
0, 0, //Reserved\r
-0, // We don't support anything at all\r
-/* TODO testing Apple Drive Setup. Make configurable!\r
-'c','o','d','e','s','r','c',' ',\r
-'S','C','S','I','2','S','D',' ',' ',' ',' ',' ',' ',' ',' ',' ',\r
-'2','.','0','a'\r
-*/\r
-' ','S','E','A','G','A','T','E',\r
-' ',' ',' ',' ',' ',' ',' ',' ',' ',' ','S','T','2','2','5','N',\r
-'1','.','0',' '\r
+0 // We don't support anything at all\r
};\r
+// Vendor set by config 'c','o','d','e','s','r','c',' ',\r
+// prodId set by config'S','C','S','I','2','S','D',' ',' ',' ',' ',' ',' ',' ',' ',' ',\r
+// Revision set by config'2','.','0','a'\r
\r
static const uint8 SupportedVitalPages[] =\r
{\r
else\r
{\r
memcpy(scsiDev.data, StandardResponse, sizeof(StandardResponse));\r
- scsiDev.dataLen = sizeof(StandardResponse);\r
+ uint8* out = scsiDev.data + sizeof(StandardResponse);\r
+ memcpy(out, config->vendor, sizeof(config->vendor));\r
+ out += sizeof(config->vendor);\r
+ memcpy(out, config->prodId, sizeof(config->prodId));\r
+ out += sizeof(config->prodId);\r
+ memcpy(out, config->revision, sizeof(config->revision));\r
+ out += sizeof(config->revision); \r
+ scsiDev.dataLen = out - scsiDev.data;\r
scsiDev.phase = DATA_IN;\r
\r
if (!lun) scsiDev.unitAttention = 0;\r
#include "loopback.h"\r
#include "scsi.h"\r
#include "scsiPhy.h"\r
+#include "config.h"\r
#include "disk.h"\r
#include "led.h"\r
\r
// Will not return if uncommented.\r
// scsi2sd_test_loopback();\r
\r
+ configInit();\r
+ \r
scsiInit(0, 1); // ID 0 is mac boot disk\r
scsiDiskInit();\r
\r
#include "device.h"\r
#include "scsi.h"\r
#include "scsiPhy.h"\r
+#include "config.h"\r
#include "bits.h"\r
#include "diagnostic.h"\r
#include "disk.h"\r
static void process_MessageIn()\r
{\r
scsiEnterPhase(MESSAGE_IN);\r
- scsiWrite(scsiDev.msgIn);\r
+ scsiWriteByte(scsiDev.msgIn);\r
\r
if (scsiDev.atnFlag)\r
{\r
else\r
{\r
// MESSAGE_REJECT. Go back to command phase\r
+ // TODO MESSAGE_REJECT moved to messageReject method.\r
scsiDev.phase = COMMAND;\r
}\r
}\r
\r
+static void messageReject()\r
+{\r
+ scsiEnterPhase(MESSAGE_IN);\r
+ scsiWriteByte(MSG_REJECT);\r
+}\r
+\r
static void enter_Status(uint8 status)\r
{\r
scsiDev.status = status;\r
static void process_Status()\r
{\r
scsiEnterPhase(STATUS);\r
- scsiWrite(scsiDev.status);\r
+ scsiWriteByte(scsiDev.status);\r
\r
// Command Complete occurs AFTER a valid status has been\r
// sent. then we go bus-free.\r
}\r
\r
scsiEnterPhase(DATA_IN);\r
- while ((scsiDev.dataPtr < scsiDev.dataLen) &&\r
- !scsiDev.resetFlag &&\r
- !scsiDev.atnFlag)\r
- {\r
- scsiWrite(scsiDev.data[scsiDev.dataPtr]);\r
- ++scsiDev.dataPtr;\r
- }\r
+\r
+ uint32 len = scsiDev.dataLen - scsiDev.dataPtr;\r
+ scsiWrite(scsiDev.data + scsiDev.dataPtr, len);\r
+ scsiDev.dataPtr += len;\r
+\r
\r
if ((scsiDev.dataPtr >= scsiDev.dataLen) &&\r
(transfer.currentBlock == transfer.blocks))\r
}\r
\r
scsiEnterPhase(DATA_OUT);\r
- while ((scsiDev.dataPtr < scsiDev.dataLen) &&\r
- !scsiDev.resetFlag &&\r
- !scsiDev.atnFlag)\r
- {\r
- scsiDev.parityError = 0;\r
- scsiDev.data[scsiDev.dataPtr] = scsiRead();\r
\r
- if (scsiDev.parityError)\r
- {\r
- scsiDev.sense.code = ABORTED_COMMAND;\r
- scsiDev.sense.asc = SCSI_PARITY_ERROR;\r
- enter_Status(CHECK_CONDITION);\r
- break;\r
- }\r
- ++scsiDev.dataPtr;\r
+ scsiDev.parityError = 0;\r
+ uint32 len = scsiDev.dataLen - scsiDev.dataPtr;\r
+ scsiRead(scsiDev.data + scsiDev.dataPtr, len);\r
+ scsiDev.dataPtr += len;\r
+\r
+ // TODO re-implement parity checking\r
+ if (0 && scsiDev.parityError && config->enableParity)\r
+ {\r
+ scsiDev.sense.code = ABORTED_COMMAND;\r
+ scsiDev.sense.asc = SCSI_PARITY_ERROR;\r
+ enter_Status(CHECK_CONDITION);\r
}\r
\r
if ((scsiDev.dataPtr >= scsiDev.dataLen) &&\r
scsiDev.parityError = 0;\r
\r
memset(scsiDev.cdb, 0, sizeof(scsiDev.cdb));\r
- scsiDev.cdb[0] = scsiRead();\r
+ scsiDev.cdb[0] = scsiReadByte();\r
\r
int group = scsiDev.cdb[0] >> 5;\r
int cmdSize = CmdGroupBytes[group];\r
- int i;\r
- for (i = 1; i < cmdSize; ++i)\r
- {\r
- scsiDev.cdb[i] = scsiRead();\r
- }\r
+ scsiRead(scsiDev.cdb + 1, cmdSize - 1);\r
\r
uint8 command = scsiDev.cdb[0];\r
uint8 lun = scsiDev.cdb[1] >> 5;\r
}\r
// Some old SCSI drivers do NOT properly support\r
// unitAttention. OTOH, Linux seems to require it\r
- // TODO MAKE CONFIGURABLE.\r
- /* confirmed LCIII with unknown scsi driver fials here.\r
- else if (scsiDev.unitAttention)\r
+ // confirmed LCIII with unknown scsi driver fials here.\r
+ else if (scsiDev.unitAttention && config->enableUnitAttention)\r
{\r
scsiDev.sense.code = UNIT_ATTENTION;\r
scsiDev.sense.asc = scsiDev.unitAttention;\r
enter_Status(CHECK_CONDITION);\r
- }*/\r
+ }\r
else if (lun)\r
{\r
scsiDev.sense.code = ILLEGAL_REQUEST;\r
static void scsiReset()\r
{\r
ledOff();\r
- SCSI_Out_DBx_Write(0);\r
- SCSI_ClearPin(SCSI_Out_DBP);\r
+ // done in verilog SCSI_Out_DBx_Write(0);\r
+ SCSI_CTL_IO_Write(0);\r
SCSI_ClearPin(SCSI_Out_ATN);\r
SCSI_ClearPin(SCSI_Out_BSY);\r
SCSI_ClearPin(SCSI_Out_ACK);\r
SCSI_ClearPin(SCSI_Out_REQ);\r
SCSI_ClearPin(SCSI_Out_MSG);\r
SCSI_ClearPin(SCSI_Out_CD);\r
- SCSI_ClearPin(SCSI_Out_IO);\r
\r
scsiDev.parityError = 0;\r
scsiDev.phase = BUS_FREE;\r
- \r
+\r
if (scsiDev.unitAttention != POWER_ON_RESET)\r
{\r
scsiDev.unitAttention = SCSI_BUS_RESET;\r
CyDelay(10); // 10ms.\r
reset = SCSI_ReadPin(SCSI_RST_INT);\r
} while (reset);\r
- \r
+\r
scsiDev.resetFlag = 0;\r
- scsiDev.atnFlag = 0; \r
+ scsiDev.atnFlag = 0;\r
}\r
\r
static void enter_SelectionPhase()\r
// Wait until the end of the selection phase.\r
while (!scsiDev.resetFlag)\r
{\r
+ scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
if (!SCSI_ReadPin(SCSI_In_SEL))\r
{\r
break;\r
\r
scsiDev.atnFlag = 0;\r
scsiDev.parityError = 0;\r
- scsiDev.msgOut = scsiRead();\r
+ scsiDev.msgOut = scsiReadByte();\r
\r
if (scsiDev.parityError)\r
{\r
// same set of messages.\r
while (SCSI_ReadPin(SCSI_ATN_INT) && !scsiDev.resetFlag)\r
{\r
- scsiRead();\r
+ scsiReadByte();\r
}\r
\r
// Go-back and try the message again.\r
else if (scsiDev.msgOut >= 0x20 && scsiDev.msgOut <= 0x2F)\r
{\r
// Two byte message. We don't support these. read and discard.\r
- scsiRead();\r
+ scsiReadByte();\r
}\r
else if (scsiDev.msgOut == 0x01)\r
{\r
// Extended message.\r
- int msgLen = scsiRead();\r
+ int msgLen = scsiReadByte();\r
if (msgLen == 0) msgLen = 256;\r
int i;\r
for (i = 0; i < msgLen && !scsiDev.resetFlag; ++i)\r
{\r
// Discard bytes.\r
- scsiRead();\r
+ scsiReadByte();\r
}\r
\r
// We don't support ANY extended messages.\r
// We don't support any 2-byte messages either.\r
// And we don't support any optional 1-byte messages.\r
// In each case, the correct response is MESSAGE REJECT.\r
- enter_MessageIn(MSG_REJECT);\r
+ messageReject();\r
}\r
else\r
{\r
- enter_MessageIn(MSG_REJECT);\r
+ messageReject();\r
}\r
\r
// Re-check the ATN flag. We won't get another interrupt if\r
// it stays asserted.\r
+ CyDelayUs(2); // DODGY HACK\r
scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
}\r
\r
// This is a hack until I work out why the ATN ISR isn't\r
// running when it should.\r
static int atnErrCount = 0;\r
+static int atnHitCount = 0;\r
static void checkATN()\r
{\r
int atn = SCSI_ReadPin(SCSI_ATN_INT);\r
atnErrCount++;\r
scsiDev.atnFlag = 1;\r
}\r
+ else if (atn && scsiDev.atnFlag)\r
+ {\r
+ atnHitCount++;\r
+ }\r
}\r
\r
void scsiPoll(void)\r
}\r
}\r
\r
-void scsiInit(int scsiId, int enableParity)\r
+void scsiInit()\r
{\r
- scsiDev.scsiIdMask = 1 << scsiId;\r
- scsiDev.enableParity = enableParity;\r
+ scsiDev.scsiIdMask = 1 << (config->scsiId);\r
\r
scsiDev.atnFlag = 0;\r
scsiDev.resetFlag = 1;\r
typedef struct
{
uint8_t scsiIdMask;
- int enableParity;
// Set to true (1) if the ATN flag was set, and we need to
// enter the MESSAGE_OUT phase.
extern ScsiDevice scsiDev;
-void scsiInit(int scsiId, int enableParity);
+void scsiInit();
void scsiPoll(void);
CY_ISR(scsiAttentionISR)\r
{\r
scsiDev.atnFlag = 1;\r
- // Not needed when using pin value for interrupt SCSI_ATN_ClearInterrupt();\r
+ SCSI_ATN_ClearInterrupt();\r
}\r
\r
-// Spins until the SCSI pin is true, or the reset flag is set.\r
-static inline void waitForPinTrue(int pin)\r
+uint8 scsiReadByte(void)\r
{\r
- int finished = SCSI_ReadPin(pin);\r
- while (!finished && !scsiDev.resetFlag)\r
- {\r
- finished = SCSI_ReadPin(pin);\r
- }\r
+ while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1)) {}\r
+ CY_SET_REG8(scsiTarget_datapath__F0_REG, 0);\r
+ while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2)) {}\r
+ uint8 value = CY_GET_REG8(scsiTarget_datapath__F1_REG);\r
+ return value;\r
}\r
\r
-// Spins until the SCSI pin is true, or the reset flag is set.\r
-static inline void waitForPinFalse(int pin)\r
+void scsiRead(uint8* data, uint32 count)\r
{\r
- int finished = !SCSI_ReadPin(pin);\r
- while (!finished && !scsiDev.resetFlag)\r
+ int prep = 0;\r
+ int i = 0;\r
+\r
+ while (i < count)\r
{\r
- finished = !SCSI_ReadPin(pin);\r
+ if (prep < count && (CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1))\r
+ {\r
+ CY_SET_REG8(scsiTarget_datapath__F0_REG, 0);\r
+ ++prep;\r
+ }\r
+ if ((CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2))\r
+ {\r
+ data[i] = CY_GET_REG8(scsiTarget_datapath__F1_REG);\r
+ ++i;\r
+ }\r
}\r
}\r
\r
-static inline void deskewDelay(void)\r
+void scsiWriteByte(uint8 value)\r
{\r
- // Delay for deskew + cable skew. total 55 nanoseconds.\r
- // Assumes 66MHz.\r
- CyDelayCycles(4);\r
-}\r
-\r
-uint8 scsiRead(void)\r
-{\r
- SCSI_SetPin(SCSI_Out_REQ);\r
- waitForPinTrue(SCSI_In_ACK);\r
- deskewDelay();\r
-\r
- uint8 value = ~SCSI_In_DBx_Read();\r
- scsiDev.parityError = scsiDev.parityError ||\r
- (Lookup_OddParity[value] != SCSI_ReadPin(SCSI_In_DBP));\r
+ while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1)) {}\r
+ CY_SET_REG8(scsiTarget_datapath__F0_REG, value);\r
\r
- SCSI_ClearPin(SCSI_Out_REQ);\r
- waitForPinFalse(SCSI_In_ACK);\r
- return value;\r
+ // TODO maybe move this TX EMPTY check to scsiEnterPhase ?\r
+ //while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 4)) {}\r
+ while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2)) {}\r
+ value = CY_GET_REG8(scsiTarget_datapath__F1_REG); \r
}\r
\r
-void scsiWrite(uint8 value)\r
+void scsiWrite(uint8* data, uint32 count)\r
{\r
- SCSI_Out_DBx_Write(value);\r
- if (Lookup_OddParity[value])\r
+ int prep = 0;\r
+ int i = 0;\r
+\r
+ while (i < count)\r
{\r
- SCSI_SetPin(SCSI_Out_DBP);\r
+ if (prep < count && (CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1))\r
+ {\r
+ CY_SET_REG8(scsiTarget_datapath__F0_REG, data[prep]);\r
+ ++prep;\r
+ }\r
+ if ((CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2))\r
+ {\r
+ CY_GET_REG8(scsiTarget_datapath__F1_REG);\r
+ ++i;\r
+ }\r
}\r
- deskewDelay();\r
-\r
- SCSI_SetPin(SCSI_Out_REQ);\r
-\r
- // Initiator reads data here.\r
-\r
- waitForPinTrue(SCSI_In_ACK);\r
-\r
- SCSI_ClearPin(SCSI_Out_DBP);\r
- SCSI_Out_DBx_Write(0);\r
- SCSI_ClearPin(SCSI_Out_REQ);\r
-\r
- // Wait for ACK to clear.\r
- waitForPinFalse(SCSI_In_ACK);\r
}\r
\r
static void busSettleDelay(void)\r
SCSI_ClearPin(SCSI_Out_CD);\r
}\r
\r
- if (phase & __scsiphase_io)\r
- {\r
- SCSI_SetPin(SCSI_Out_IO);\r
- }\r
- else\r
- {\r
- SCSI_ClearPin(SCSI_Out_IO);\r
- }\r
+ SCSI_CTL_IO_Write(phase & __scsiphase_io ? 1 : 0);\r
}\r
else\r
{\r
SCSI_ClearPin(SCSI_Out_MSG);\r
SCSI_ClearPin(SCSI_Out_CD);\r
- SCSI_ClearPin(SCSI_Out_IO);\r
+ SCSI_CTL_IO_Write(0);\r
}\r
busSettleDelay();\r
}\r
{\r
SCSI_RST_ISR_StartEx(scsiResetISR);\r
SCSI_ATN_ISR_StartEx(scsiAttentionISR);\r
- \r
+\r
// Interrupts may have already been directed to the (empty)\r
// standard ISR generated by PSoC Creator.\r
SCSI_RST_ClearInterrupt();\r
- // Not needed for pin level interrupt SCSI_ATN_ClearInterrupt(); \r
-}
\ No newline at end of file
+ SCSI_ATN_ClearInterrupt();\r
+}\r
extern const uint8 Lookup_OddParity[256];
void scsiPhyInit();
-uint8 scsiRead(void);
-void scsiWrite(uint8 value);
-
-// Returns true if the ATN flag becomes set, indicating a parity error.
-int scsiWriteMsg(uint8 msg);
+uint8 scsiReadByte(void);
+void scsiRead(uint8* data, uint32 count);
+void scsiWriteByte(uint8 value);
+void scsiWrite(uint8* data, uint32 count);
void scsiEnterPhase(int phase);
--- /dev/null
+\r
+//`#start header` -- edit after this line, do not edit this line\r
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+`include "cypress.v"\r
+//`#end` -- edit above this line, do not edit this line\r
+// Generated on 10/16/2013 at 00:01\r
+// Component: scsiTarget\r
+module scsiTarget (\r
+ output [7:0] DBx_out, // Active High, connected to SCSI bus via inverter\r
+ output REQ, // Active High, connected to SCSI bus via inverter\r
+ input nACK, // Active LOW, connected directly to SCSI bus.\r
+ input [7:0] nDBx_in, // Active LOW, connected directly to SCSI bus.\r
+ input IO, // Active High, set by CPU via status register.\r
+ input nRST, // Active LOW, connected directly to SCSI bus.\r
+ input clk\r
+);\r
+\r
+\r
+//`#start body` -- edit after this line, do not edit this line\r
+\r
+/////////////////////////////////////////////////////////////////////////////\r
+// Force Clock Sync\r
+/////////////////////////////////////////////////////////////////////////////\r
+// The udb_clock_enable primitive component is used to indicate that the input\r
+// clock must always be synchronous and if not implement synchronizers to make\r
+// it synchronous.\r
+wire op_clk;\r
+cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE)) ClkSync\r
+(\r
+ .clock_in(clk),\r
+ .enable(1'b1),\r
+ .clock_out(op_clk)\r
+);\r
+\r
+/////////////////////////////////////////////////////////////////////////////\r
+// FIFO Status Register\r
+/////////////////////////////////////////////////////////////////////////////\r
+// Status Register: scsiTarget_StatusReg__STATUS_REG\r
+// Bit 0: Tx FIFO not full\r
+// Bit 1: Rx FIFO not empty\r
+// Bit 2: Tx FIFO empty\r
+// Bit 3: Rx FIFO full\r
+//\r
+// TX FIFO Register: scsiTarget_scsiTarget_u0__F0_REG\r
+// RX FIFO Register: scsiTarget_scsiTarget_u0__F1_REG\r
+// Use with CY_GET_REG8 and CY_SET_REG8\r
+wire f0_bus_stat; // Tx FIFO not full\r
+wire f0_blk_stat; // Tx FIFO empty\r
+wire f1_bus_stat; // Rx FIFO not empty\r
+wire f1_blk_stat; // Rx FIFO full\r
+cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg\r
+(\r
+ /* input */ .clock(op_clk),\r
+ /* input [04:00] */ .status({4'b0, f1_blk_stat, f0_blk_stat, f1_bus_stat, f0_bus_stat})\r
+);\r
+\r
+/////////////////////////////////////////////////////////////////////////////\r
+// CONSTANTS\r
+/////////////////////////////////////////////////////////////////////////////\r
+localparam IO_WRITE = 1'b1;\r
+localparam IO_READ = 1'b0;\r
+\r
+/////////////////////////////////////////////////////////////////////////////\r
+// STATE MACHINE\r
+/////////////////////////////////////////////////////////////////////////////\r
+// TX States:\r
+// IDLE\r
+// Wait for an entry in the FIFO, and for the SCSI Initiator to be ready\r
+// FIFOLOAD\r
+// Load F0 into A0. Feed (old) A0 into the ALU SRCA.\r
+// TX\r
+// Load data register from PO. PO is fed by A0 going into the ALU via SRCA\r
+// A0 must remain unchanged.\r
+// DESKEW_INIT\r
+// DBx output signals will be output in this state\r
+// Load deskew clock count into A0 from D0\r
+// DESKEW\r
+// DBx output signals will be output in this state\r
+// Wait for the SCSI deskew time of 55ms. (DEC A0).\r
+// A1 must be fed into SRCA, so PO is now useless.\r
+// READY\r
+// REQ and DBx output signals will be output in this state\r
+// Wait for acknowledgement from the SCSI initiator.\r
+// RX\r
+// Dummy state for flow control.\r
+// REQ signal will be output in this state\r
+// PI enabled for input into ALU "PASS" operation, storing into F1.\r
+//\r
+// RX States:\r
+// IDLE\r
+// Wait for a dummy "enabling" entry in the input FIFO, and wait for space\r
+// in output the FIFO, and for the SCSI Initiator to be ready\r
+// FIFOLOAD\r
+// Load F0 into A0.\r
+// The input FIFO is used to control the number of bytes we attempt to\r
+// read from the SCSI bus.\r
+// READY\r
+// REQ signal will be output in this state\r
+// Wait for the initiator to send a byte on the SCSI bus.\r
+// RX\r
+// REQ signal will be output in this state\r
+// PI enabled for input into ALU "PASS" operation, storing into F1.\r
+\r
+\r
+localparam STATE_IDLE = 3'b000;\r
+localparam STATE_FIFOLOAD = 3'b001;\r
+localparam STATE_TX = 3'b010;\r
+localparam STATE_DESKEW_INIT = 3'b011;\r
+localparam STATE_DESKEW = 3'b100;\r
+// This state intentionally not used.\r
+localparam STATE_READY = 3'b110;\r
+localparam STATE_RX = 3'b111;\r
+\r
+// state selects the datapath register.\r
+reg[2:0] state;\r
+\r
+// Data being read/written from/to the SCSI bus\r
+reg[7:0] data;\r
+\r
+// Set by the datapath zero detector (z1). High when A1 counts down to zero.\r
+// D1 set to constant by .d1_init_a(4) (55ns at 66MHz)\r
+wire deskewComplete;\r
+\r
+// Parallel input to the datapath SRCA.\r
+// Selected for input through to the ALU if CFB EN bit set for the datapath\r
+// state and enabled by PI DYN bit in CFG15-14\r
+wire[7:0] pi;\r
+\r
+// Parallel output from the selected SRCA value (A0 or A1) to the ALU.\r
+wire[7:0] po;\r
+\r
+// Set true to trigger storing A1 into F1.\r
+wire fifoStore;\r
+\r
+// Set Output Pins\r
+assign REQ = state[1] & state[2]; // STATE_READY & STATE_RX\r
+assign DBx_out[7:0] = data;\r
+assign pi[7:0] = ~nDBx_in[7:0]; // Invert active low scsi bus\r
+assign fifoStore = (state == STATE_RX) ? 1'b1 : 1'b0;\r
+\r
+always @(posedge op_clk) begin\r
+ case (state)\r
+ STATE_IDLE:\r
+ begin\r
+ // Check that SCSI initiator is ready, and input FIFO is not empty,\r
+ // and output FIFO is not full.\r
+ // Note that output FIFO is unused in TX mode.\r
+ if (nACK & !f0_blk_stat && !f1_blk_stat)\r
+ state <= STATE_FIFOLOAD;\r
+ else\r
+ state <= STATE_IDLE;\r
+\r
+ // Clear our output pins\r
+ data <= 8'b0;\r
+ end\r
+\r
+ STATE_FIFOLOAD:\r
+ state <= IO == IO_WRITE ? STATE_TX : STATE_READY;\r
+\r
+ STATE_TX:\r
+ begin\r
+ state <= STATE_DESKEW_INIT;\r
+ data <= po;\r
+ end\r
+\r
+ STATE_DESKEW_INIT: state <= STATE_DESKEW;\r
+\r
+ STATE_DESKEW:\r
+ if(deskewComplete) state <= STATE_READY;\r
+ else state <= STATE_DESKEW;\r
+\r
+ STATE_READY:\r
+ //if ((IO == IO_WRITE) & ~nACK) state <= STATE_IDLE;\r
+ //else if ((IO == IO_READ) & ~nACK) state <= STATE_RX;\r
+ if (~nACK) state <= STATE_RX;\r
+ else state <= STATE_READY;\r
+\r
+ STATE_RX: state <= STATE_IDLE;\r
+\r
+ default: state <= STATE_IDLE;\r
+ endcase\r
+end\r
+\r
+cy_psoc3_dp #(.d1_init(3), \r
+.cy_dpconfig(\r
+{\r
+ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
+ `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\r
+ `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE*/\r
+ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
+ `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE,\r
+ `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM1: FIFO Load*/\r
+ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
+ `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\r
+ `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM2: TX*/\r
+ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
+ `CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE,\r
+ `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM3: DESKEW INIT*/\r
+ `CS_ALU_OP__DEC, `CS_SRCA_A0, `CS_SRCB_D0,\r
+ `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,\r
+ `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM4: DESKEW*/\r
+ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
+ `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\r
+ `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM5: Not used*/\r
+ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
+ `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\r
+ `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM6: READY*/\r
+ `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,\r
+ `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,\r
+ `CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,\r
+ `CS_CMP_SEL_CFGA, /*CFGRAM7: RX*/\r
+ 8'hFF, 8'h00, /*CFG9: */\r
+ 8'hFF, 8'hFF, /*CFG11-10: */\r
+ `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,\r
+ `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,\r
+ `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,\r
+ `SC_SI_A_DEFSI, /*CFG13-12: */\r
+ `SC_A0_SRC_ACC, `SC_SHIFT_SL, `SC_PI_DYN_EN,\r
+ 1'h0, `SC_FIFO1_ALU, `SC_FIFO0_BUS,\r
+ `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN,\r
+ `SC_FB_NOCHN, `SC_CMP1_NOCHN,\r
+ `SC_CMP0_NOCHN, /*CFG15-14: */\r
+ 10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,\r
+ `SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,\r
+ `SC_WRK16CAT_DSBL /*CFG17-16: */\r
+}\r
+)) datapath(\r
+ /* input */ .reset(1'b0),\r
+ /* input */ .clk(op_clk),\r
+ /* input [02:00] */ .cs_addr(state),\r
+ /* input */ .route_si(1'b0),\r
+ /* input */ .route_ci(1'b0),\r
+ /* input */ .f0_load(1'b0),\r
+ /* input */ .f1_load(fifoStore),\r
+ /* input */ .d0_load(1'b0),\r
+ /* input */ .d1_load(1'b0),\r
+ /* output */ .ce0(),\r
+ /* output */ .cl0(),\r
+ /* output */ .z0(deskewComplete),\r
+ /* output */ .ff0(),\r
+ /* output */ .ce1(),\r
+ /* output */ .cl1(),\r
+ /* output */ .z1(),\r
+ /* output */ .ff1(),\r
+ /* output */ .ov_msb(),\r
+ /* output */ .co_msb(),\r
+ /* output */ .cmsb(),\r
+ /* output */ .so(),\r
+ /* output */ .f0_bus_stat(f0_bus_stat),\r
+ /* output */ .f0_blk_stat(f0_blk_stat),\r
+ /* output */ .f1_bus_stat(f1_bus_stat),\r
+ /* output */ .f1_blk_stat(f1_blk_stat),\r
+ \r
+ /* input */ .ci(1'b0), // Carry in from previous stage\r
+ /* output */ .co(), // Carry out to next stage\r
+ /* input */ .sir(1'b0), // Shift in from right side\r
+ /* output */ .sor(), // Shift out to right side\r
+ /* input */ .sil(1'b0), // Shift in from left side\r
+ /* output */ .sol(), // Shift out to left side\r
+ /* input */ .msbi(1'b0), // MSB chain in\r
+ /* output */ .msbo(), // MSB chain out\r
+ /* input [01:00] */ .cei(2'b0), // Compare equal in from prev stage\r
+ /* output [01:00] */ .ceo(), // Compare equal out to next stage\r
+ /* input [01:00] */ .cli(2'b0), // Compare less than in from prv stage\r
+ /* output [01:00] */ .clo(), // Compare less than out to next stage\r
+ /* input [01:00] */ .zi(2'b0), // Zero detect in from previous stage\r
+ /* output [01:00] */ .zo(), // Zero detect out to next stage\r
+ /* input [01:00] */ .fi(2'b0), // 0xFF detect in from previous stage\r
+ /* output [01:00] */ .fo(), // 0xFF detect out to next stage\r
+ /* input [01:00] */ .capi(2'b0), // Software capture from previous stage\r
+ /* output [01:00] */ .capo(), // Software capture to next stage\r
+ /* input */ .cfbi(1'b0), // CRC Feedback in from previous stage\r
+ /* output */ .cfbo(), // CRC Feedback out to next stage\r
+ /* input [07:00] */ .pi(pi), // Parallel data port\r
+ /* output [07:00] */ .po(po) // Parallel data port\r
+);\r
+//`#end` -- edit above this line, do not edit this line\r
+endmodule\r
+//`#start footer` -- edit after this line, do not edit this line\r
+//`#end` -- edit above this line, do not edit this line\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
\r
#include "device.h"\r
#include "scsi.h"\r
+#include "config.h"\r
#include "disk.h"\r
#include "sd.h"\r
\r
\r
void sdReadSector()\r
{\r
- // We have a spi FIFO of 4 bytes. use it.\r
- // This is much better, byut after 4 bytes we're still\r
- // blocking a bit.\r
- int i;\r
- for (i = 0; i < SCSI_BLOCK_SIZE; i+=4)\r
+ int prep = 0;\r
+ int i = 0;\r
+ while (i < SCSI_BLOCK_SIZE)\r
{\r
- SDCard_WriteTxData(0xFF);\r
- SDCard_WriteTxData(0xFF);\r
- SDCard_WriteTxData(0xFF);\r
- SDCard_WriteTxData(0xFF);\r
-\r
- while(!(SDCard_ReadTxStatus() & SDCard_STS_SPI_DONE))\r
- {}\r
- scsiDev.data[i] = SDCard_ReadRxData();\r
- scsiDev.data[i+1] = SDCard_ReadRxData();\r
- scsiDev.data[i+2] = SDCard_ReadRxData();\r
- scsiDev.data[i+3] = SDCard_ReadRxData();\r
+ if (prep < SCSI_BLOCK_SIZE && (SDCard_ReadTxStatus() & SDCard_STS_TX_FIFO_NOT_FULL))\r
+ {\r
+ SDCard_WriteTxData(0xFF);\r
+ prep++;\r
+ }\r
\r
+ if(SDCard_ReadRxStatus() & SDCard_STS_RX_FIFO_NOT_EMPTY)\r
+ {\r
+ scsiDev.data[i] = SDCard_ReadRxData();\r
+ i++;\r
+ }\r
}\r
\r
\r
\r
sdSpiByte(0xFC); // MULTIPLE byte start token\r
int i;\r
- for (i = 0; i < SCSI_BLOCK_SIZE; i+=4)\r
+ for (i = 0; i < SCSI_BLOCK_SIZE; i++)\r
{\r
- SDCard_WriteTxData(scsiDev.data[i]);\r
- SDCard_WriteTxData(scsiDev.data[i+1]);\r
- SDCard_WriteTxData(scsiDev.data[i+2]);\r
- SDCard_WriteTxData(scsiDev.data[i+3]);\r
-\r
- while(!(SDCard_ReadTxStatus() & SDCard_STS_SPI_DONE))\r
+ while(!(SDCard_ReadTxStatus() & SDCard_STS_TX_FIFO_NOT_FULL))\r
{}\r
+ SDCard_WriteTxData(scsiDev.data[i]);\r
}\r
- \r
- SDCard_ReadRxData();\r
- SDCard_ReadRxData();\r
- SDCard_ReadRxData();\r
- SDCard_ReadRxData();\r
+ while(!(SDCard_ReadTxStatus() & SDCard_STS_SPI_DONE))\r
+ {}\r
+ SDCard_ReadRxData();\r
+ SDCard_ReadRxData();\r
+ SDCard_ReadRxData();\r
+ SDCard_ReadRxData();\r
\r
sdSpiByte(0x00); // CRC\r
sdSpiByte(0x00); // CRC\r
\r
// now set the sd card up for full speed\r
SD_Data_Clk_Start(); // Turn on the fast clock\r
- SD_Clk_Ctl_Write(1); // Select the fast clock source.\r
+ SD_Clk_Ctl_Write(config->overclockSPI ? 2 : 1); // Select the fast clock source.\r
SD_Init_Clk_Stop(); // Stop the slow clock.\r
\r
if (!sdReadCSD()) goto bad;\r
\r
}\r
\r
-\r
void sdPrepareWrite()\r
{\r
// Set the number of blocks to pre-erase by the multiple block write command\r
{
int version; // SDHC = version 2.
int ccs; // Card Capacity Status. 1 = SDHC or SDXC
- int capacity; // in 512 byte blocks
+ uint32 capacity; // in 512 byte blocks
} SdDevice;
extern SdDevice sdDev;
projects / SCSI2SD.git / commitdiff