Fix sync timings to split read and write period times

diff --git a/CHANGELOG b/CHANGELOG
index 57009708007dc3b5b5d632b28dfaace9e40c0580..19c4ab24089c9ea1a5accb971fff2b9b362ac54a 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,3 +1,6 @@
+20180131               6.1.3
+       - Fix bug that caused stability issues with 10MB/s transfers.
+
 20171128               6.1.2
        - Fix synchronous negotiation bugs
 

diff --git a/STM32CubeMX/SCSI2SD-V6/Src/fsmc.c b/STM32CubeMX/SCSI2SD-V6/Src/fsmc.c
index 1e200f7ce64b24d02f6401103d76187ecc32eb72..5261aa928eff03424a2ae8ec29b017b0be323b2a 100755 (executable)
--- a/STM32CubeMX/SCSI2SD-V6/Src/fsmc.c
+++ b/STM32CubeMX/SCSI2SD-V6/Src/fsmc.c
@@ -81,10 +81,10 @@ void MX_FSMC_Init(void)
   //   1 to write back to fsmc bus.
   Timing.DataSetupTime = 4;
 
-  // Allow a clock for us to release signals, plus 3 for the synchroniser to
-  // realise the cycle has ended. Need to avoid both devices acting as outputs
+  // Allow a clock for us to release signals
+  // Need to avoid both devices acting as outputs
   // on the multiplexed lines at the same time.
-  Timing.BusTurnAroundDuration = 4;
+  Timing.BusTurnAroundDuration = 1;
 
   Timing.CLKDivision = 16; // Ignored for async
   Timing.DataLatency = 17; // Ignored for async

diff --git a/rtl/fpga_bitmap.o b/rtl/fpga_bitmap.o
index aa8447bf1e496a1cf2d12df11701fc359736f2f9..046632cac655dd07f3545bcd0a4d0f066f19b422 100644 (file)
Binary files a/rtl/fpga_bitmap.o and b/rtl/fpga_bitmap.o differ

diff --git a/src/firmware/config.c b/src/firmware/config.c
index 06baee27967680b51cb6f42cec0a0762a7a7e950..dc2fe1a3356ddf24e286dc8752d3ab85baf31093 100755 (executable)
--- a/src/firmware/config.c
+++ b/src/firmware/config.c
@@ -38,7 +38,7 @@
 \r
 #include <string.h>\r
 \r
-static const uint16_t FIRMWARE_VERSION = 0x0612;\r
+static const uint16_t FIRMWARE_VERSION = 0x0613;\r
 \r
 // 1 flash row\r
 static const uint8_t DEFAULT_CONFIG[128] =\r

diff --git a/src/firmware/disk.c b/src/firmware/disk.c
index e7c097fc240d6de55033db9451baf5ff42bb22f8..5b1140090eb6c557375c0275f4557dbe9ec574b6 100755 (executable)
--- a/src/firmware/disk.c
+++ b/src/firmware/disk.c
@@ -718,8 +718,11 @@ void scsiDiskPoll()
                                process_MessageIn(); // Will go to BUS_FREE state\r
 \r
                                // Try and prevent anyone else using the SCSI bus while we're not ready.\r
-                               *SCSI_CTRL_BSY = 1;\r
-                               clearBSY = 1;\r
+                               if (*SCSI_CTRL_BSY == 0) // Could be busy for a linked command\r
+                               {\r
+                                       *SCSI_CTRL_BSY = 1;\r
+                                       clearBSY = 1;\r
+                               }\r
                        }\r
 \r
 \r

diff --git a/src/firmware/scsi.c b/src/firmware/scsi.c
index e5528bfc30c0b4bd988317cc4917f25fe9288567..81af617f68507ec67195db336cc50e31b7a08ef0 100755 (executable)
--- a/src/firmware/scsi.c
+++ b/src/firmware/scsi.c
@@ -815,13 +815,14 @@ static void process_MessageOut()
                                // After 80 we start to run out of bits in the fpga timing\r
                                // register.\r
                                (transferPeriod == 0) ||\r
+                               (offset == 0) ||\r
                                ((scsiDev.boardCfg.scsiSpeed != S2S_CFG_SPEED_NoLimit) &&\r
                                        (scsiDev.boardCfg.scsiSpeed <= S2S_CFG_SPEED_ASYNC_50)))\r
                        {\r
                                scsiDev.target->syncOffset = 0;\r
                                scsiDev.target->syncPeriod = 0;\r
                        } else {\r
-                               scsiDev.target->syncOffset = offset < 63 ? offset : 63;\r
+                               scsiDev.target->syncOffset = offset <= 15 ? offset : 15;\r
                                // FAST20 / 50ns / 20MHz is disabled for now due to\r
                                // data corruption while reading data. We can count the\r
                                // ACK's correctly, but can't save the data to a register\r

diff --git a/src/firmware/scsiPhy.c b/src/firmware/scsiPhy.c
index fadddcb341d0fc8c40f3541e616b5fa52ca2cba2..b2bb258fd50952954e532d0296e790698945c908 100755 (executable)
--- a/src/firmware/scsiPhy.c
+++ b/src/firmware/scsiPhy.c
@@ -31,7 +31,7 @@
 static uint8_t asyncTimings[][4] =\r
 {\r
 /* Speed,    Assert,    Deskew,    Hold,    Glitch */\r
-{/*1.5MB/s*/ 28,        18,        13,      13},\r
+{/*1.5MB/s*/ 28,        18,        13,      15},\r
 {/*3.3MB/s*/ 13,        6,         6,       13},\r
 {/*5MB/s*/   9,         6,         6,       6}, // 80ns\r
 {/*safe*/    3,         6,         6,       6}, // Probably safe\r
@@ -58,7 +58,13 @@ static uint8_t asyncTimings[][4] =
 \r
 #define SCSI_FAST10_DESKEW 2 // 25ns\r
 #define SCSI_FAST10_HOLD 3 // 33ns\r
-#define SCSI_FAST10_ASSERT 3 // 30ns\r
+#define SCSI_FAST10_WRITE_ASSERT 3 // 30ns. Overall clocks only works if fpga overhead is 3.\r
+\r
+// Slow down the cycle to be valid. 2x assert period is TOO FAST when\r
+// reading data. It's ok when writing due to the deskew.\r
+// 50ns. ie. 100ns / 2. Rounded down because there's likely a few extra cycles\r
+// here and there.\r
+#define SCSI_FAST10_READ_ASSERT 5\r
 \r
 // Fastest possible timing, probably not 20MB/s\r
 #define SCSI_FAST20_DESKEW 1\r
@@ -74,12 +80,17 @@ static uint8_t asyncTimings[][4] =
        : SCSI_FAST5_HOLD)\r
 \r
 \r
+// Number of overhead cycles per period.\r
+#define FPGA_OVERHEAD 2\r
+#define FPGA_CYCLES_PER_NS 9\r
+#define SCSI_PERIOD_CLKS(period) ((((int)period * 4) + (FPGA_CYCLES_PER_NS/2)) / FPGA_CYCLES_PER_NS)\r
+\r
 // 3.125MB/s (80 period) to < 10MB/s sync\r
 // Assumes a 108MHz fpga clock. (9 ns)\r
-// (((period * 4) / 2) * 0.8) / 9\r
-// Done using 3 fixed point math.\r
 // 3:0 Assertion count, variable\r
-#define syncAssertion(period) ((((((int)period) * 177) + 750)/1000) & 0xF)\r
+#define syncAssertionWrite(period,deskew) ((SCSI_PERIOD_CLKS(period) - deskew - FPGA_OVERHEAD + 1) / 2)\r
+#define syncAssertionRead(period) syncAssertionWrite(period,0)\r
+\r
 \r
 // Time until we consider ourselves selected\r
 // 400ns at 108MHz\r
@@ -481,13 +492,12 @@ scsiSetDefaultTiming()
                asyncTiming[3]);\r
 }\r
 \r
-void scsiEnterPhase(int phase)\r
+void scsiEnterPhase(int newPhase)\r
 {\r
        // ANSI INCITS 362-2002 SPI-3 10.7.1:\r
        // Phase changes are not allowed while REQ or ACK is asserted.\r
        while (likely(!scsiDev.resetFlag) && scsiStatusACK()) {}\r
 \r
-       int newPhase = phase > 0 ? phase : 0;\r
        int oldPhase = *SCSI_CTRL_PHASE;\r
 \r
        if (!scsiDev.resetFlag && (!scsiPhyFifoEmpty() || !scsiPhyFifoAltEmpty())) {\r
@@ -505,7 +515,14 @@ void scsiEnterPhase(int phase)
                        }\r
                        else if (scsiDev.target->syncPeriod <= 25)\r
                        {\r
-                               scsiSetTiming(SCSI_FAST10_ASSERT, SCSI_FAST10_DESKEW, SCSI_FAST10_HOLD, 1);\r
+                               if (newPhase == DATA_IN)\r
+                               {\r
+                                       scsiSetTiming(SCSI_FAST10_WRITE_ASSERT, SCSI_FAST10_DESKEW, SCSI_FAST10_HOLD, 1);\r
+                               }\r
+                               else\r
+                               {\r
+                                       scsiSetTiming(SCSI_FAST10_READ_ASSERT, SCSI_FAST10_DESKEW, SCSI_FAST10_HOLD, 1);\r
+                               }\r
                        }\r
                        else\r
                        {\r
@@ -514,26 +531,26 @@ void scsiEnterPhase(int phase)
                                int glitch =\r
                                        scsiDev.target->syncPeriod < 35 ? 1 :\r
                                                (scsiDev.target->syncPeriod < 45 ? 2 : 5);\r
+                               int deskew = syncDeskew(scsiDev.target->syncPeriod);\r
+                               int assertion;\r
+                               if (newPhase == DATA_IN)\r
+                               {\r
+                                       assertion = syncAssertionWrite(scsiDev.target->syncPeriod, deskew);\r
+                               }\r
+                               else\r
+                               {\r
+                                       assertion = syncAssertionRead(scsiDev.target->syncPeriod);\r
+                               }\r
                                scsiSetTiming(\r
-                                       syncAssertion(scsiDev.target->syncPeriod),\r
-                                       syncDeskew(scsiDev.target->syncPeriod),\r
+                                       assertion,\r
+                                       deskew,\r
                                        syncHold(scsiDev.target->syncPeriod),\r
                                        glitch);\r
                        }\r
 \r
-                       // See note 26 in SCSI 2 standard: SCSI 1 implementations may assume\r
-                       // "leading edge of the first REQ pulse beyond the REQ/ACK offset\r
-                       // agreement would not occur until after the trailing edge of the\r
-                       // last ACK pulse within the agreement."\r
-                       // We simply subtract 1 from the offset to meet this requirement.\r
-                       if (scsiDev.target->syncOffset >= 2)\r
-                       {\r
-                               *SCSI_CTRL_SYNC_OFFSET = scsiDev.target->syncOffset - 1;\r
-                       } else {\r
-                               *SCSI_CTRL_SYNC_OFFSET = scsiDev.target->syncOffset;\r
-                       }\r
+                       *SCSI_CTRL_SYNC_OFFSET = scsiDev.target->syncOffset;\r
                }\r
-               else\r
+               else if (newPhase >= 0)\r
                {\r
 \r
                        *SCSI_CTRL_SYNC_OFFSET = 0;\r
@@ -564,14 +581,20 @@ void scsiEnterPhase(int phase)
                                asyncTiming[3]);\r
                }\r
 \r
-               *SCSI_CTRL_PHASE = newPhase;\r
-               busSettleDelay();\r
+               if (newPhase >= 0)\r
+               {\r
+                       *SCSI_CTRL_PHASE = newPhase;\r
+                       busSettleDelay();\r
 \r
-               if (scsiDev.compatMode < COMPAT_SCSI2)\r
+                       if (scsiDev.compatMode < COMPAT_SCSI2)\r
+                       {\r
+                               s2s_delay_us(100);\r
+                       }\r
+               }\r
+               else\r
                {\r
-                       s2s_delay_us(100);\r
+                       *SCSI_CTRL_PHASE = 0;\r
                }\r
-\r
        }\r
 }\r
 \r
@@ -587,10 +610,10 @@ void scsiPhyReset()
                dmaInProgress = 0;\r
        }\r
 \r
-       *SCSI_CTRL_PHASE = 0x00;\r
-       *SCSI_CTRL_BSY = 0x00;\r
        s2s_fpgaReset(); // Clears fifos etc.\r
 \r
+       *SCSI_CTRL_PHASE = 0x00;\r
+       *SCSI_CTRL_BSY = 0x00;\r
        scsiPhyFifoSel = 0;\r
        *SCSI_FIFO_SEL = 0;\r
        *SCSI_CTRL_DBX = 0;\r