int i = 0;\r
int scsiActive = 0;\r
int sdActive = 0;\r
+ \r
+ int isSDDevice = scsiDev.target->cfg->storageDevice == CONFIG_STOREDEVICE_SD;\r
+ \r
while ((i < totalSDSectors) &&\r
likely(scsiDev.phase == DATA_IN) &&\r
likely(!scsiDev.resetFlag))\r
CyExitCriticalSection(intr);\r
}\r
\r
- if (sdActive && !sdBusy && sdReadSectorDMAPoll())\r
- {\r
- sdActive = 0;\r
- prep++;\r
- }\r
+ if (isSDDevice)\r
+ {\r
+ if (sdActive && !sdBusy && sdReadSectorDMAPoll())\r
+ {\r
+ sdActive = 0;\r
+ prep++;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ S2S_Device* device = scsiDev.target->device;\r
+ if (sdActive && device->readAsyncPoll(device))\r
+ {\r
+ sdActive = 0;\r
+ prep++;\r
+ }\r
+ }\r
\r
// Usually SD is slower than the SCSI interface.\r
// Prioritise starting the read of the next sector over starting a\r
(prep - i < buffers) &&\r
(prep < totalSDSectors))\r
{\r
- if (scsiDev.target->cfg->storageDevice == CONFIG_STOREDEVICE_SD)\r
+ if (isSDDevice)\r
{\r
// Start an SD transfer if we have space.\r
if (transfer.multiBlock)\r
{\r
// Sync Read onboard flash\r
S2S_Device* device = scsiDev.target->device;\r
- device->read(device, sdLBA + prep, 1, &scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]);\r
- prep++;\r
+ device->readAsync(device, sdLBA + prep, 1, &scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]);\r
+ sdActive = 1;\r
}\r
}\r
\r
scsiDev.phase = STATUS;\r
}\r
scsiDiskReset();\r
+ \r
+ // Wait for current DMA transfer done then deselect (if reset encountered)\r
+ if (!isSDDevice)\r
+ {\r
+ S2S_Device* device = scsiDev.target->device;\r
+ while (!device->readAsyncPoll(device))\r
+ {\r
+ }\r
+ }\r
}\r
else if (scsiDev.phase == DATA_OUT &&\r
transfer.currentBlock != transfer.blocks)\r
static void spiFlash_pollMediaBusy(S2S_Device* dev);
static void spiFlash_erase(S2S_Device* dev, uint32_t sectorNumber, uint32_t count);
static void spiFlash_read(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);
+static void spiFlash_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);
+static int spiFlash_readAsyncPoll(S2S_Device* dev);
static void spiFlash_write(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);
SpiFlash spiFlash = {
spiFlash_pollMediaBusy,
spiFlash_erase,
spiFlash_read,
+ spiFlash_readAsync,
+ spiFlash_readAsyncPoll,
spiFlash_write,
0, // initial mediaState
CONFIG_STOREDEVICE_FLASH
S2S_Device* spiFlashDevice = &(spiFlash.dev);
+// Private DMA variables.
+static uint8 spiFlashDMARxChan = CY_DMA_INVALID_CHANNEL;
+static uint8 spiFlashDMATxChan = CY_DMA_INVALID_CHANNEL;
+static uint8_t spiFlashDmaRxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };
+static uint8_t spiFlashDmaTxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };
+
+// Source of dummy SPI bytes for DMA
+static uint8_t dummyBuffer[2] __attribute__((aligned(4))) = {0xFF, 0xFF};
+// Dummy location for DMA to sink usless data to
+static uint8 discardBuffer[2] __attribute__((aligned(4)));
+
+
+volatile uint8_t spiFlashRxDMAComplete = 1;
+volatile uint8_t spiFlashTxDMAComplete = 1;
+
+CY_ISR_PROTO(spiFlashRxISR);
+CY_ISR(spiFlashRxISR)
+{
+ spiFlashRxDMAComplete = 1;
+}
+CY_ISR_PROTO(spiFlashTxISR);
+CY_ISR(spiFlashTxISR)
+{
+ spiFlashTxDMAComplete = 1;
+}
+
// Read and write 1 byte.
static uint8_t spiFlashByte(uint8_t value)
{
// Don't require the host to send us a START STOP UNIT command
spiFlash->dev.mediaState = MEDIA_STARTED;
+
+ // DMA stuff
+ spiFlashDMATxChan =
+ NOR_TX_DMA_DmaInitialize(
+ 2, // Bytes per burst
+ 1, // request per burst
+ HI16(CYDEV_SRAM_BASE),
+ HI16(CYDEV_PERIPH_BASE)
+ );
+
+ spiFlashDMARxChan =
+ NOR_RX_DMA_DmaInitialize(
+ 1, // Bytes per burst
+ 1, // request per burst
+ HI16(CYDEV_PERIPH_BASE),
+ HI16(CYDEV_SRAM_BASE)
+ );
+
+ CyDmaChDisable(spiFlashDMATxChan);
+ CyDmaChDisable(spiFlashDMARxChan);
+
+ NOR_RX_DMA_COMPLETE_StartEx(spiFlashRxISR);
+ NOR_TX_DMA_COMPLETE_StartEx(spiFlashTxISR);
+
+ spiFlashDmaRxTd[0] = CyDmaTdAllocate();
+ spiFlashDmaRxTd[1] = CyDmaTdAllocate();
+
+ spiFlashDmaTxTd[0] = CyDmaTdAllocate();
+ spiFlashDmaTxTd[1] = CyDmaTdAllocate();
}
static void spiFlash_init(S2S_Device* dev)
spiFlashByte(linearAddress >> 16);
spiFlashByte(linearAddress >> 8);
spiFlashByte(linearAddress);
-
+
// There's no harm in reading -extra- data, so keep the FIFO
// one step ahead.
NOR_SPI_WriteTxData(0xFF);
while (!(NOR_SPI_ReadRxStatus() & NOR_SPI_STS_RX_FIFO_NOT_EMPTY)) {}
NOR_SPI_ReadRxData();
}
-
+
nNOR_CS_Write(1); // Deselect
}
+static void spiFlash_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer)
+{
+ // SpiFlash* spiFlash = (SpiFlash*)dev;
+
+ nNOR_CS_Write(0); // Select
+ spiFlashByte(0x13);
+
+ uint32_t linearAddress = sectorNumber * 512;
+
+ // DMA implementation
+ // send is static as the address must remain consistent for the static
+ // DMA descriptors to work.
+ // Size must be divisible by 2 to suit 2-byte-burst TX DMA channel.
+ static uint8_t send[4] __attribute__((aligned(4)));
+ send[0] = linearAddress >> 24;
+ send[1] = linearAddress >> 16;
+ send[2] = linearAddress >> 8;
+ send[3] = linearAddress;
+
+ // Prepare DMA transfer
+ CyDmaTdSetConfiguration(spiFlashDmaTxTd[0], sizeof(send), spiFlashDmaTxTd[1], TD_INC_SRC_ADR);
+ CyDmaTdSetAddress(spiFlashDmaTxTd[0], LO16((uint32)&send), LO16((uint32)NOR_SPI_TXDATA_PTR));
+
+ CyDmaTdSetConfiguration(
+ spiFlashDmaTxTd[1],
+ count * 512,
+ CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes
+ NOR_TX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete
+ );
+ CyDmaTdSetAddress(
+ spiFlashDmaTxTd[1],
+ LO16((uint32)&dummyBuffer),
+ LO16((uint32)NOR_SPI_TXDATA_PTR));
+
+ CyDmaTdSetConfiguration(spiFlashDmaRxTd[0], sizeof(send), spiFlashDmaRxTd[1], 0);
+ CyDmaTdSetAddress(spiFlashDmaRxTd[0], LO16((uint32)NOR_SPI_RXDATA_PTR), LO16((uint32)&discardBuffer));
+
+ CyDmaTdSetConfiguration(
+ spiFlashDmaRxTd[1],
+ count * 512,
+ CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes
+ TD_INC_DST_ADR |
+ NOR_RX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete
+ );
+
+ CyDmaTdSetAddress(
+ spiFlashDmaRxTd[1],
+ LO16((uint32)NOR_SPI_RXDATA_PTR),
+ LO16((uint32)buffer)
+ );
+
+ CyDmaChSetInitialTd(spiFlashDMATxChan, spiFlashDmaTxTd[0]);
+ CyDmaChSetInitialTd(spiFlashDMARxChan, spiFlashDmaRxTd[0]);
+
+ // The DMA controller is a bit trigger-happy. It will retain
+ // a drq request that was triggered while the channel was
+ // disabled.
+ CyDmaChSetRequest(spiFlashDMATxChan, CY_DMA_CPU_REQ);
+ CyDmaClearPendingDrq(spiFlashDMARxChan);
+
+ spiFlashTxDMAComplete = 0;
+ spiFlashRxDMAComplete = 0;
+
+ CyDmaChEnable(spiFlashDMARxChan, 1);
+ CyDmaChEnable(spiFlashDMATxChan, 1);
+}
+
+static int spiFlash_readAsyncPoll(S2S_Device* dev)
+{
+ // SpiFlash* spiFlash = (SpiFlash*)dev;
+
+ int allComplete = 0;
+ uint8_t intr = CyEnterCriticalSection();
+ allComplete = spiFlashTxDMAComplete && spiFlashRxDMAComplete;
+ CyExitCriticalSection(intr);
+
+ if (allComplete)
+ {
+ nNOR_CS_Write(1); // Deselect
+ }
+
+ return allComplete;
+}
\ No newline at end of file
static void sd_pollMediaBusy(S2S_Device* dev);\r
static void sd_erase(S2S_Device* dev, uint32_t sectorNumber, uint32_t count);\r
static void sd_read(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);\r
+static void sd_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);\r
+static int sd_readAsyncPoll(S2S_Device* dev);\r
static void sd_write(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);\r
\r
\r
sd_pollMediaBusy,\r
sd_erase,\r
sd_read,\r
+ sd_readAsync,\r
+ sd_readAsyncPoll,\r
sd_write,\r
0, // initial mediaState\r
CONFIG_STOREDEVICE_SD\r
// TODO\r
}\r
\r
+static void sd_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer)\r
+{\r
+ // TODO\r
+}\r
+\r
+\r
+static int sd_readAsyncPoll(S2S_Device* dev)\r
+{\r
+ return 1;\r
+}\r
+\r
+\r
static void sd_write(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer)\r
{\r
// TODO\r
void (*erase)(S2S_Device* dev, uint32_t sectorNumber, uint32_t count);
void (*read)(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);
+ void (*readAsync)(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);
+ int (*readAsyncPoll)(S2S_Device* dev);
void (*write)(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);
MEDIA_STATE mediaState;
***************************************/
#define NOR_SPI_INT_ON_SPI_DONE ((uint8) (0u << NOR_SPI_STS_SPI_DONE_SHIFT))
-#define NOR_SPI_INT_ON_TX_EMPTY ((uint8) (0u << NOR_SPI_STS_TX_FIFO_EMPTY_SHIFT))
+#define NOR_SPI_INT_ON_TX_EMPTY ((uint8) (1u << NOR_SPI_STS_TX_FIFO_EMPTY_SHIFT))
#define NOR_SPI_INT_ON_TX_NOT_FULL ((uint8) (0u << \
NOR_SPI_STS_TX_FIFO_NOT_FULL_SHIFT))
#define NOR_SPI_INT_ON_BYTE_COMP ((uint8) (0u << NOR_SPI_STS_BYTE_COMPLETE_SHIFT))
#define NOR_SPI_INT_ON_RX_FULL ((uint8) (0u << \
NOR_SPI_STS_RX_FIFO_FULL_SHIFT))
-#define NOR_SPI_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \
+#define NOR_SPI_INT_ON_RX_NOT_EMPTY ((uint8) (1u << \
NOR_SPI_STS_RX_FIFO_NOT_EMPTY_SHIFT))
#define NOR_SPI_INT_ON_RX_OVER ((uint8) (0u << \
NOR_SPI_STS_RX_FIFO_OVERRUN_SHIFT))
#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_1__INTC_MASK 0x80u
-#define USBFS_ep_1__INTC_NUMBER 7u
+#define USBFS_ep_1__INTC_MASK 0x200u
+#define USBFS_ep_1__INTC_NUMBER 9u
#define USBFS_ep_1__INTC_PRIOR_NUM 7u
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_9
#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_2__INTC_MASK 0x100u
-#define USBFS_ep_2__INTC_NUMBER 8u
+#define USBFS_ep_2__INTC_MASK 0x400u
+#define USBFS_ep_2__INTC_NUMBER 10u
#define USBFS_ep_2__INTC_PRIOR_NUM 7u
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_10
#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_3__INTC_MASK 0x200u
-#define USBFS_ep_3__INTC_NUMBER 9u
+#define USBFS_ep_3__INTC_MASK 0x800u
+#define USBFS_ep_3__INTC_NUMBER 11u
#define USBFS_ep_3__INTC_PRIOR_NUM 7u
-#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9
+#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_11
#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_4__INTC_MASK 0x400u
-#define USBFS_ep_4__INTC_NUMBER 10u
+#define USBFS_ep_4__INTC_MASK 0x2000u
+#define USBFS_ep_4__INTC_NUMBER 13u
#define USBFS_ep_4__INTC_PRIOR_NUM 7u
-#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10
+#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_13
#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define NOR_SO__SLW CYREG_PRT15_SLW
/* SDCard */
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB04_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB04_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB04_MSK
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB04_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB04_ST
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
#define SDCard_BSPIM_TxStsReg__2__POS 2
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB11_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB11_ST
/* SD_SCK */
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE1
#define NOR_SCK__SLW CYREG_PRT3_SLW
/* NOR_SPI */
-#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
-#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
-#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
-#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
-#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
-#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
-#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
-#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
-#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
-#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
-#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB04_CTL
-#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
-#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB04_CTL
-#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
-#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
-#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
-#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB04_MSK
-#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
-#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
-#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB04_MSK
-#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
-#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
-#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
-#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL
-#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL
-#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB04_ST
-#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
+#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK
+#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK
+#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK
+#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK
+#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL
+#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL
+#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL
+#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL
+#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK
+#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
+#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK
+#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL
+#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL
+#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST
+#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define NOR_SPI_BSPIM_RxStsReg__4__MASK 0x10u
#define NOR_SPI_BSPIM_RxStsReg__4__POS 4
#define NOR_SPI_BSPIM_RxStsReg__5__MASK 0x20u
#define NOR_SPI_BSPIM_RxStsReg__6__MASK 0x40u
#define NOR_SPI_BSPIM_RxStsReg__6__POS 6
#define NOR_SPI_BSPIM_RxStsReg__MASK 0x70u
-#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB11_MSK
-#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB11_ST
+#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK
+#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1
#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0
#define NOR_SPI_BSPIM_TxStsReg__0__POS 0
#define NOR_SPI_BSPIM_TxStsReg__1__MASK 0x02u
#define NOR_SPI_BSPIM_TxStsReg__1__POS 1
-#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
-#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
+#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
+#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
#define NOR_SPI_BSPIM_TxStsReg__2__MASK 0x04u
#define NOR_SPI_BSPIM_TxStsReg__2__POS 2
#define NOR_SPI_BSPIM_TxStsReg__3__MASK 0x08u
#define NOR_SPI_BSPIM_TxStsReg__4__MASK 0x10u
#define NOR_SPI_BSPIM_TxStsReg__4__POS 4
#define NOR_SPI_BSPIM_TxStsReg__MASK 0x1Fu
-#define NOR_SPI_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB03_MSK
-#define NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
-#define NOR_SPI_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB03_ST
+#define NOR_SPI_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK
+#define NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
+#define NOR_SPI_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST
/* SCSI_In */
#define SCSI_In__0__INTTYPE CYREG_PICU6_INTTYPE1
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB10_11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB10_11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB10_11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB10_11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB10_11_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB10_11_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB10_11_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB10_11_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB10_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB10_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB10_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB10_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB10_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB09_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB09_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB10_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB09_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
#define NOR_Clock__PM_STBY_MSK 0x01u
/* SD_RX_DMA */
-#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SD_RX_DMA__DRQ_NUMBER 2u
+#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL1
+#define SD_RX_DMA__DRQ_NUMBER 4u
#define SD_RX_DMA__NUMBEROF_TDS 0u
#define SD_RX_DMA__PRIORITY 0u
#define SD_RX_DMA__TERMIN_EN 0u
#define SD_RX_DMA__TERMIN_SEL 0u
#define SD_RX_DMA__TERMOUT0_EN 1u
-#define SD_RX_DMA__TERMOUT0_SEL 2u
+#define SD_RX_DMA__TERMOUT0_SEL 4u
#define SD_RX_DMA__TERMOUT1_EN 0u
#define SD_RX_DMA__TERMOUT1_SEL 0u
#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u
-#define SD_RX_DMA_COMPLETE__INTC_NUMBER 5u
+#define SD_RX_DMA_COMPLETE__INTC_MASK 0x80u
+#define SD_RX_DMA_COMPLETE__INTC_NUMBER 7u
#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_7
#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SD_TX_DMA */
-#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SD_TX_DMA__DRQ_NUMBER 3u
+#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL1
+#define SD_TX_DMA__DRQ_NUMBER 5u
#define SD_TX_DMA__NUMBEROF_TDS 0u
#define SD_TX_DMA__PRIORITY 1u
#define SD_TX_DMA__TERMIN_EN 0u
#define SD_TX_DMA__TERMIN_SEL 0u
#define SD_TX_DMA__TERMOUT0_EN 1u
-#define SD_TX_DMA__TERMOUT0_SEL 3u
+#define SD_TX_DMA__TERMOUT0_SEL 5u
#define SD_TX_DMA__TERMOUT1_EN 0u
#define SD_TX_DMA__TERMOUT1_SEL 0u
#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u
-#define SD_TX_DMA_COMPLETE__INTC_NUMBER 6u
+#define SD_TX_DMA_COMPLETE__INTC_MASK 0x100u
+#define SD_TX_DMA_COMPLETE__INTC_NUMBER 8u
#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_8
#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define nNOR_HOLD__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define nNOR_HOLD__SLW CYREG_PRT12_SLW
+/* NOR_RX_DMA */
+#define NOR_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define NOR_RX_DMA__DRQ_NUMBER 0u
+#define NOR_RX_DMA__NUMBEROF_TDS 0u
+#define NOR_RX_DMA__PRIORITY 2u
+#define NOR_RX_DMA__TERMIN_EN 0u
+#define NOR_RX_DMA__TERMIN_SEL 0u
+#define NOR_RX_DMA__TERMOUT0_EN 1u
+#define NOR_RX_DMA__TERMOUT0_SEL 0u
+#define NOR_RX_DMA__TERMOUT1_EN 0u
+#define NOR_RX_DMA__TERMOUT1_SEL 0u
+#define NOR_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define NOR_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define NOR_RX_DMA_COMPLETE__INTC_MASK 0x02u
+#define NOR_RX_DMA_COMPLETE__INTC_NUMBER 1u
+#define NOR_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define NOR_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_1
+#define NOR_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define NOR_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* NOR_TX_DMA */
+#define NOR_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define NOR_TX_DMA__DRQ_NUMBER 1u
+#define NOR_TX_DMA__NUMBEROF_TDS 0u
+#define NOR_TX_DMA__PRIORITY 2u
+#define NOR_TX_DMA__TERMIN_EN 0u
+#define NOR_TX_DMA__TERMIN_SEL 0u
+#define NOR_TX_DMA__TERMOUT0_EN 1u
+#define NOR_TX_DMA__TERMOUT0_SEL 1u
+#define NOR_TX_DMA__TERMOUT1_EN 0u
+#define NOR_TX_DMA__TERMOUT1_SEL 0u
+#define NOR_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define NOR_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define NOR_TX_DMA_COMPLETE__INTC_MASK 0x04u
+#define NOR_TX_DMA_COMPLETE__INTC_NUMBER 2u
+#define NOR_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define NOR_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2
+#define NOR_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define NOR_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
/* SCSI_Noise */
#define SCSI_Noise__0__AG CYREG_PRT4_AG
#define SCSI_Noise__0__AMUX CYREG_PRT4_AMUX
#define scsiTarget_StatusReg__0__POS 0
#define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
#define scsiTarget_StatusReg__2__MASK 0x04u
#define scsiTarget_StatusReg__2__POS 2
#define scsiTarget_StatusReg__3__MASK 0x08u
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK
-#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
-#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
-#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB15_ST_CTL
-#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB15_ST_CTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST
/* Debug_Timer */
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
/* SCSI_RX_DMA */
#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SCSI_RX_DMA__DRQ_NUMBER 0u
+#define SCSI_RX_DMA__DRQ_NUMBER 2u
#define SCSI_RX_DMA__NUMBEROF_TDS 0u
#define SCSI_RX_DMA__PRIORITY 2u
#define SCSI_RX_DMA__TERMIN_EN 0u
#define SCSI_RX_DMA__TERMIN_SEL 0u
#define SCSI_RX_DMA__TERMOUT0_EN 1u
-#define SCSI_RX_DMA__TERMOUT0_SEL 0u
+#define SCSI_RX_DMA__TERMOUT0_SEL 2u
#define SCSI_RX_DMA__TERMOUT1_EN 0u
#define SCSI_RX_DMA__TERMOUT1_SEL 0u
#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x04u
-#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 2u
+#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x10u
+#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 4u
#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SCSI_TX_DMA */
#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SCSI_TX_DMA__DRQ_NUMBER 1u
+#define SCSI_TX_DMA__DRQ_NUMBER 3u
#define SCSI_TX_DMA__NUMBEROF_TDS 0u
#define SCSI_TX_DMA__PRIORITY 2u
#define SCSI_TX_DMA__TERMIN_EN 0u
#define SCSI_TX_DMA__TERMIN_SEL 0u
#define SCSI_TX_DMA__TERMOUT0_EN 1u
-#define SCSI_TX_DMA__TERMOUT0_SEL 1u
+#define SCSI_TX_DMA__TERMOUT0_SEL 3u
#define SCSI_TX_DMA__TERMOUT1_EN 0u
#define SCSI_TX_DMA__TERMOUT1_SEL 0u
#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u
-#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u
+#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x40u
+#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 6u
#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6
#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SCSI_RST_ISR */
#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_RST_ISR__INTC_MASK 0x02u
-#define SCSI_RST_ISR__INTC_NUMBER 1u
+#define SCSI_RST_ISR__INTC_MASK 0x08u
+#define SCSI_RST_ISR__INTC_NUMBER 3u
#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u
-#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_1
+#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3
#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SCSI_SEL_ISR */
#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_SEL_ISR__INTC_MASK 0x08u
-#define SCSI_SEL_ISR__INTC_NUMBER 3u
+#define SCSI_SEL_ISR__INTC_MASK 0x20u
+#define SCSI_SEL_ISR__INTC_NUMBER 5u
#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u
-#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3
+#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_5
#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
#define SCSI_Filtered_sts_sts_reg__0__POS 0
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
#define SCSI_Filtered_sts_sts_reg__1__POS 1
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
#define SCSI_Filtered_sts_sts_reg__2__POS 2
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
#define SCSI_Filtered_sts_sts_reg__4__POS 4
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B1_UDB08_MSK
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B1_UDB08_ST
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK
+#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
/* SCSI_Glitch_Ctl */
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB09_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB09_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB09_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB12_MSK
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB12_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB09_MSK
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB09_ST
/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 50000000U
#define CYDEV_ECC_ENABLE 0
#define CYDEV_HEAP_SIZE 0x0400
#define CYDEV_INSTRUCT_CACHE_ENABLED 1
-#define CYDEV_INTR_RISING 0x0000007Fu
+#define CYDEV_INTR_RISING 0x000001FFu
#define CYDEV_IS_EXPORTING_CODE 0
#define CYDEV_IS_IMPORTING_CODE 0
#define CYDEV_PROJ_TYPE 2
#define CYIPBLOCK_S8_SAR_VERSION 0
#define CYIPBLOCK_S8_SIO_VERSION 0
#define CYIPBLOCK_S8_UDB_VERSION 0
-#define DMA_CHANNELS_USED__MASK0 0x0000000Fu
+#define DMA_CHANNELS_USED__MASK0 0x0000003Fu
#define CYDEV_BOOTLOADER_ENABLE 0
#endif /* INCLUDED_CYFITTER_H */
static const uint8 CYCODE BS_PHUB_CFGMEM3_VAL[] = {
0x00u, 0x03u, 0x00u, 0x00u};
+ /* PHUB_CFGMEM4 Address: CYREG_PHUB_CFGMEM4_CFG0 Size (bytes): 4 */
+ static const uint8 CYCODE BS_PHUB_CFGMEM4_VAL[] = {
+ 0x00u, 0x04u, 0x00u, 0x00u};
+
+ /* PHUB_CFGMEM5 Address: CYREG_PHUB_CFGMEM5_CFG0 Size (bytes): 4 */
+ static const uint8 CYCODE BS_PHUB_CFGMEM5_VAL[] = {
+ 0x00u, 0x05u, 0x00u, 0x00u};
+
#ifdef CYGlobalIntDisable
/* Disable interrupts by default. Let user enable if/when they want. */
CYGlobalIntDisable
0x4000520Cu, /* Base address: 0x40005200 Count: 12 */
0x40006402u, /* Base address: 0x40006400 Count: 2 */
0x40006501u, /* Base address: 0x40006500 Count: 1 */
- 0x40010041u, /* Base address: 0x40010000 Count: 65 */
+ 0x4001003Du, /* Base address: 0x40010000 Count: 61 */
0x4001013Fu, /* Base address: 0x40010100 Count: 63 */
- 0x4001024Du, /* Base address: 0x40010200 Count: 77 */
- 0x40010348u, /* Base address: 0x40010300 Count: 72 */
- 0x40010418u, /* Base address: 0x40010400 Count: 24 */
+ 0x4001025Au, /* Base address: 0x40010200 Count: 90 */
+ 0x40010354u, /* Base address: 0x40010300 Count: 84 */
+ 0x40010419u, /* Base address: 0x40010400 Count: 25 */
0x40010556u, /* Base address: 0x40010500 Count: 86 */
- 0x4001064Fu, /* Base address: 0x40010600 Count: 79 */
- 0x40010751u, /* Base address: 0x40010700 Count: 81 */
- 0x40010848u, /* Base address: 0x40010800 Count: 72 */
- 0x40010955u, /* Base address: 0x40010900 Count: 85 */
- 0x40010A5Fu, /* Base address: 0x40010A00 Count: 95 */
- 0x40010B56u, /* Base address: 0x40010B00 Count: 86 */
- 0x40010C50u, /* Base address: 0x40010C00 Count: 80 */
- 0x40010D55u, /* Base address: 0x40010D00 Count: 85 */
- 0x40010E49u, /* Base address: 0x40010E00 Count: 73 */
- 0x40010F37u, /* Base address: 0x40010F00 Count: 55 */
- 0x4001141Au, /* Base address: 0x40011400 Count: 26 */
- 0x40011553u, /* Base address: 0x40011500 Count: 83 */
- 0x40011656u, /* Base address: 0x40011600 Count: 86 */
- 0x40011753u, /* Base address: 0x40011700 Count: 83 */
- 0x4001184Bu, /* Base address: 0x40011800 Count: 75 */
+ 0x40010653u, /* Base address: 0x40010600 Count: 83 */
+ 0x40010759u, /* Base address: 0x40010700 Count: 89 */
+ 0x4001084Eu, /* Base address: 0x40010800 Count: 78 */
+ 0x4001095Eu, /* Base address: 0x40010900 Count: 94 */
+ 0x40010A41u, /* Base address: 0x40010A00 Count: 65 */
+ 0x40010B5Cu, /* Base address: 0x40010B00 Count: 92 */
+ 0x40010C4Fu, /* Base address: 0x40010C00 Count: 79 */
+ 0x40010D61u, /* Base address: 0x40010D00 Count: 97 */
+ 0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */
+ 0x40010F41u, /* Base address: 0x40010F00 Count: 65 */
+ 0x40011411u, /* Base address: 0x40011400 Count: 17 */
+ 0x40011550u, /* Base address: 0x40011500 Count: 80 */
+ 0x40011650u, /* Base address: 0x40011600 Count: 80 */
+ 0x40011754u, /* Base address: 0x40011700 Count: 84 */
+ 0x40011848u, /* Base address: 0x40011800 Count: 72 */
0x40011954u, /* Base address: 0x40011900 Count: 84 */
- 0x40011A47u, /* Base address: 0x40011A00 Count: 71 */
- 0x40011B52u, /* Base address: 0x40011B00 Count: 82 */
- 0x4001401Au, /* Base address: 0x40014000 Count: 26 */
- 0x40014125u, /* Base address: 0x40014100 Count: 37 */
- 0x40014212u, /* Base address: 0x40014200 Count: 18 */
- 0x4001430Cu, /* Base address: 0x40014300 Count: 12 */
- 0x4001440Fu, /* Base address: 0x40014400 Count: 15 */
- 0x4001451Du, /* Base address: 0x40014500 Count: 29 */
- 0x40014611u, /* Base address: 0x40014600 Count: 17 */
- 0x40014716u, /* Base address: 0x40014700 Count: 22 */
- 0x4001480Fu, /* Base address: 0x40014800 Count: 15 */
- 0x4001491Au, /* Base address: 0x40014900 Count: 26 */
- 0x40014C03u, /* Base address: 0x40014C00 Count: 3 */
- 0x40014D05u, /* Base address: 0x40014D00 Count: 5 */
- 0x40015005u, /* Base address: 0x40015000 Count: 5 */
- 0x40015104u, /* Base address: 0x40015100 Count: 4 */
+ 0x40011A4Eu, /* Base address: 0x40011A00 Count: 78 */
+ 0x40011B48u, /* Base address: 0x40011B00 Count: 72 */
+ 0x4001401Cu, /* Base address: 0x40014000 Count: 28 */
+ 0x4001411Fu, /* Base address: 0x40014100 Count: 31 */
+ 0x40014218u, /* Base address: 0x40014200 Count: 24 */
+ 0x40014312u, /* Base address: 0x40014300 Count: 18 */
+ 0x40014412u, /* Base address: 0x40014400 Count: 18 */
+ 0x40014515u, /* Base address: 0x40014500 Count: 21 */
+ 0x4001460Du, /* Base address: 0x40014600 Count: 13 */
+ 0x4001470Eu, /* Base address: 0x40014700 Count: 14 */
+ 0x40014817u, /* Base address: 0x40014800 Count: 23 */
+ 0x40014914u, /* Base address: 0x40014900 Count: 20 */
+ 0x40014C04u, /* Base address: 0x40014C00 Count: 4 */
+ 0x40014D07u, /* Base address: 0x40014D00 Count: 7 */
+ 0x40015006u, /* Base address: 0x40015000 Count: 6 */
+ 0x40015102u, /* Base address: 0x40015100 Count: 2 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x7Eu, 0x02u},
{0x01u, 0x30u},
{0x0Au, 0x36u},
- {0x01u, 0x22u},
- {0x10u, 0xA8u},
- {0x11u, 0x2Au},
- {0x18u, 0x84u},
- {0x19u, 0x82u},
+ {0x00u, 0x22u},
+ {0x10u, 0x0Au},
+ {0x11u, 0x88u},
+ {0x18u, 0xC2u},
+ {0x19u, 0x44u},
{0x1Cu, 0x08u},
- {0x20u, 0x02u},
- {0x21u, 0x03u},
- {0x30u, 0x84u},
- {0x60u, 0x02u},
+ {0x20u, 0x01u},
+ {0x31u, 0x84u},
+ {0x60u, 0x20u},
+ {0x61u, 0x22u},
{0x78u, 0x20u},
{0x7Cu, 0x40u},
{0x20u, 0x01u},
{0x84u, 0x0Fu},
{0x84u, 0x0Fu},
- {0x01u, 0x6Du},
- {0x02u, 0x20u},
- {0x05u, 0x12u},
- {0x06u, 0x03u},
- {0x07u, 0xE8u},
- {0x09u, 0x0Du},
- {0x0Bu, 0x60u},
- {0x0Du, 0x6Du},
- {0x11u, 0x71u},
- {0x12u, 0x24u},
- {0x13u, 0x82u},
- {0x14u, 0x24u},
- {0x15u, 0x02u},
- {0x16u, 0x09u},
- {0x17u, 0x0Du},
- {0x19u, 0x92u},
- {0x1Bu, 0x64u},
- {0x1Du, 0x20u},
- {0x1Eu, 0x18u},
- {0x21u, 0x40u},
- {0x22u, 0x04u},
- {0x24u, 0x24u},
- {0x26u, 0x12u},
- {0x28u, 0x40u},
- {0x29u, 0x2Du},
- {0x2Bu, 0x40u},
- {0x2Du, 0x6Du},
- {0x30u, 0x40u},
- {0x33u, 0x0Fu},
- {0x34u, 0x07u},
- {0x35u, 0xF0u},
- {0x36u, 0x38u},
- {0x39u, 0x20u},
- {0x3Bu, 0x08u},
- {0x3Eu, 0x01u},
- {0x40u, 0x13u},
+ {0x01u, 0x06u},
+ {0x02u, 0x03u},
+ {0x05u, 0x02u},
+ {0x06u, 0x04u},
+ {0x07u, 0x01u},
+ {0x0Du, 0x01u},
+ {0x0Eu, 0x24u},
+ {0x0Fu, 0x04u},
+ {0x10u, 0x24u},
+ {0x11u, 0x08u},
+ {0x12u, 0x09u},
+ {0x19u, 0x08u},
+ {0x1Au, 0x18u},
+ {0x28u, 0x24u},
+ {0x29u, 0x10u},
+ {0x2Au, 0x12u},
+ {0x2Du, 0x01u},
+ {0x2Eu, 0x20u},
+ {0x2Fu, 0x02u},
+ {0x30u, 0x07u},
+ {0x31u, 0x07u},
+ {0x33u, 0x10u},
+ {0x34u, 0x38u},
+ {0x35u, 0x08u},
+ {0x39u, 0x22u},
+ {0x3Fu, 0x04u},
+ {0x40u, 0x46u},
{0x41u, 0x02u},
- {0x42u, 0x60u},
- {0x45u, 0x2Cu},
- {0x46u, 0xFDu},
+ {0x42u, 0x50u},
+ {0x45u, 0xDCu},
+ {0x46u, 0x2Fu},
{0x47u, 0x0Eu},
{0x48u, 0x1Fu},
{0x49u, 0xFFu},
{0x68u, 0x40u},
{0x69u, 0x40u},
{0x6Eu, 0x08u},
- {0xADu, 0x01u},
+ {0x96u, 0x01u},
+ {0x97u, 0x01u},
+ {0xAAu, 0x02u},
+ {0xB2u, 0x01u},
{0xB3u, 0x01u},
- {0xBFu, 0x04u},
+ {0xB4u, 0x02u},
+ {0xD8u, 0x04u},
{0xD9u, 0x04u},
+ {0xDCu, 0x22u},
{0xDFu, 0x01u},
- {0x00u, 0x06u},
- {0x08u, 0x0Au},
- {0x0Au, 0x01u},
- {0x10u, 0x80u},
- {0x11u, 0x28u},
- {0x18u, 0x04u},
- {0x1Au, 0x01u},
- {0x1Bu, 0x81u},
- {0x20u, 0x08u},
- {0x21u, 0x20u},
- {0x22u, 0x14u},
- {0x23u, 0x04u},
- {0x24u, 0x20u},
- {0x29u, 0x42u},
- {0x2Au, 0x10u},
- {0x2Fu, 0x02u},
+ {0x01u, 0x06u},
+ {0x03u, 0x02u},
+ {0x08u, 0x20u},
+ {0x0Au, 0x44u},
+ {0x0Eu, 0x20u},
+ {0x11u, 0x40u},
+ {0x12u, 0x08u},
+ {0x17u, 0x10u},
+ {0x19u, 0x02u},
+ {0x1Au, 0x04u},
+ {0x1Eu, 0x10u},
+ {0x1Fu, 0x10u},
+ {0x21u, 0x11u},
+ {0x22u, 0x02u},
+ {0x23u, 0x20u},
+ {0x25u, 0x04u},
+ {0x27u, 0x10u},
+ {0x29u, 0x20u},
+ {0x2Bu, 0x01u},
{0x31u, 0x22u},
- {0x32u, 0x44u},
- {0x39u, 0x61u},
- {0x3Au, 0x04u},
- {0x40u, 0x0Au},
- {0x41u, 0x04u},
- {0x49u, 0x20u},
- {0x4Au, 0x90u},
- {0x4Bu, 0x02u},
- {0x51u, 0x80u},
- {0x52u, 0x48u},
- {0x53u, 0x20u},
- {0x58u, 0x04u},
- {0x59u, 0x01u},
- {0x5Au, 0x40u},
- {0x5Bu, 0x10u},
- {0x61u, 0x18u},
- {0x62u, 0x02u},
- {0x63u, 0x01u},
- {0x68u, 0x01u},
- {0x69u, 0x14u},
- {0x6Bu, 0x80u},
- {0x70u, 0x80u},
- {0x72u, 0x04u},
- {0x73u, 0x50u},
- {0x81u, 0x90u},
- {0x82u, 0x08u},
- {0x83u, 0x80u},
- {0x86u, 0x02u},
- {0x87u, 0x22u},
- {0x8Au, 0x10u},
- {0x8Du, 0x14u},
- {0x8Eu, 0x01u},
- {0xC0u, 0x0Cu},
- {0xC2u, 0x0Du},
- {0xC4u, 0x0Eu},
- {0xCAu, 0x1Du},
- {0xCCu, 0x0Fu},
- {0xCEu, 0x0Fu},
- {0xD0u, 0x0Eu},
- {0xD2u, 0x04u},
+ {0x36u, 0x04u},
+ {0x39u, 0x02u},
+ {0x3Bu, 0x44u},
+ {0x40u, 0x04u},
+ {0x43u, 0x02u},
+ {0x48u, 0x04u},
+ {0x49u, 0x84u},
+ {0x4Au, 0x88u},
+ {0x52u, 0x10u},
+ {0x53u, 0x68u},
+ {0x58u, 0x12u},
+ {0x59u, 0x08u},
+ {0x5Au, 0x80u},
+ {0x60u, 0x80u},
+ {0x62u, 0x20u},
+ {0x63u, 0x21u},
+ {0x68u, 0x80u},
+ {0x69u, 0x44u},
+ {0x6Bu, 0x08u},
+ {0x70u, 0x08u},
+ {0x72u, 0x0Au},
+ {0x73u, 0x80u},
+ {0x81u, 0x04u},
+ {0x84u, 0x02u},
+ {0x86u, 0x88u},
+ {0x87u, 0x80u},
+ {0x8Au, 0x02u},
+ {0x8Bu, 0x40u},
+ {0x8Fu, 0x01u},
+ {0xC0u, 0x0Du},
+ {0xC2u, 0x2Au},
+ {0xC4u, 0x43u},
+ {0xCAu, 0x0Cu},
+ {0xCCu, 0x45u},
+ {0xCEu, 0x0Bu},
+ {0xD0u, 0x05u},
+ {0xD2u, 0x0Cu},
{0xD6u, 0x0Fu},
{0xD8u, 0x0Fu},
- {0xE0u, 0x05u},
- {0xE2u, 0x0Au},
+ {0xE0u, 0x02u},
+ {0xE2u, 0x08u},
{0xE4u, 0x09u},
- {0xE6u, 0x04u},
- {0x05u, 0x02u},
- {0x0Fu, 0x02u},
+ {0xE6u, 0x82u},
+ {0x01u, 0x1Cu},
+ {0x04u, 0x01u},
+ {0x05u, 0x14u},
+ {0x06u, 0x02u},
+ {0x07u, 0x08u},
+ {0x08u, 0x02u},
+ {0x09u, 0x24u},
+ {0x0Au, 0x01u},
+ {0x0Bu, 0x10u},
+ {0x0Du, 0x30u},
+ {0x0Fu, 0x0Fu},
+ {0x11u, 0x0Cu},
+ {0x13u, 0x10u},
{0x14u, 0x02u},
- {0x16u, 0x05u},
- {0x17u, 0x02u},
- {0x18u, 0x02u},
- {0x1Au, 0x09u},
+ {0x15u, 0x21u},
+ {0x16u, 0x01u},
+ {0x17u, 0x1Eu},
+ {0x19u, 0x11u},
+ {0x1Bu, 0x22u},
{0x1Cu, 0x02u},
- {0x1Eu, 0x01u},
+ {0x1Eu, 0x05u},
{0x20u, 0x02u},
- {0x22u, 0x11u},
- {0x2Cu, 0x01u},
- {0x2Du, 0x01u},
- {0x2Eu, 0x02u},
- {0x30u, 0x03u},
- {0x31u, 0x02u},
- {0x32u, 0x10u},
- {0x34u, 0x04u},
+ {0x21u, 0x1Cu},
+ {0x22u, 0x09u},
+ {0x29u, 0x10u},
+ {0x2Bu, 0x0Cu},
+ {0x2Du, 0x08u},
+ {0x32u, 0x04u},
+ {0x33u, 0x0Fu},
+ {0x34u, 0x03u},
+ {0x35u, 0x30u},
{0x36u, 0x08u},
- {0x37u, 0x01u},
- {0x3Au, 0x02u},
- {0x3Fu, 0x01u},
+ {0x3Au, 0x20u},
+ {0x3Bu, 0x20u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x92u},
+ {0x5Cu, 0x12u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x81u, 0x28u},
- {0x85u, 0x28u},
- {0x86u, 0xFFu},
- {0x88u, 0xC0u},
- {0x89u, 0x28u},
- {0x8Au, 0x08u},
- {0x8Cu, 0x1Fu},
- {0x8Eu, 0x20u},
- {0x8Fu, 0x28u},
- {0x90u, 0x80u},
- {0x93u, 0x20u},
- {0x95u, 0x05u},
- {0x96u, 0x9Fu},
- {0x97u, 0x02u},
- {0x99u, 0x03u},
- {0x9Au, 0x60u},
+ {0x81u, 0xC0u},
+ {0x83u, 0x02u},
+ {0x85u, 0x7Fu},
+ {0x87u, 0x80u},
+ {0x88u, 0x50u},
+ {0x8Au, 0x0Cu},
+ {0x8Bu, 0x60u},
+ {0x8Cu, 0x5Cu},
+ {0x8Fu, 0xFFu},
+ {0x90u, 0x21u},
+ {0x91u, 0x90u},
+ {0x92u, 0x1Eu},
+ {0x93u, 0x40u},
+ {0x94u, 0x24u},
+ {0x95u, 0xC0u},
+ {0x96u, 0x10u},
+ {0x97u, 0x08u},
+ {0x98u, 0x30u},
+ {0x99u, 0xC0u},
+ {0x9Au, 0x0Fu},
{0x9Bu, 0x04u},
- {0x9Cu, 0xC0u},
- {0x9Du, 0x04u},
- {0x9Eu, 0x01u},
- {0x9Fu, 0x03u},
- {0xA0u, 0xC0u},
- {0xA1u, 0x28u},
- {0xA2u, 0x02u},
- {0xA4u, 0xC0u},
- {0xA5u, 0x10u},
- {0xA6u, 0x04u},
- {0xA8u, 0x7Fu},
- {0xA9u, 0x10u},
- {0xAAu, 0x80u},
- {0xACu, 0x90u},
- {0xADu, 0x01u},
- {0xAEu, 0x40u},
- {0xAFu, 0x06u},
- {0xB1u, 0x08u},
- {0xB2u, 0xFFu},
- {0xB3u, 0x20u},
- {0xB5u, 0x10u},
- {0xB7u, 0x07u},
- {0xB9u, 0x20u},
- {0xBBu, 0x80u},
- {0xBEu, 0x04u},
- {0xBFu, 0x05u},
- {0xD4u, 0x09u},
+ {0x9Cu, 0x5Cu},
+ {0x9Du, 0xC0u},
+ {0x9Fu, 0x01u},
+ {0xA0u, 0x11u},
+ {0xA2u, 0x22u},
+ {0xA3u, 0x9Fu},
+ {0xA4u, 0x54u},
+ {0xA5u, 0x80u},
+ {0xA6u, 0x08u},
+ {0xA8u, 0x08u},
+ {0xACu, 0x0Cu},
+ {0xADu, 0x1Fu},
+ {0xAEu, 0x50u},
+ {0xAFu, 0x20u},
+ {0xB0u, 0x0Fu},
+ {0xB2u, 0x30u},
+ {0xB4u, 0x40u},
+ {0xB5u, 0xFFu},
+ {0xB6u, 0x40u},
+ {0xBAu, 0x08u},
+ {0xBEu, 0x50u},
+ {0xBFu, 0x10u},
+ {0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
+ {0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x88u},
+ {0x00u, 0x80u},
{0x03u, 0x04u},
- {0x09u, 0x20u},
- {0x0Au, 0x81u},
- {0x0Bu, 0x20u},
- {0x0Eu, 0x2Au},
- {0x10u, 0x20u},
- {0x11u, 0x41u},
- {0x12u, 0x18u},
- {0x14u, 0x01u},
+ {0x04u, 0x14u},
+ {0x06u, 0x20u},
+ {0x09u, 0x80u},
+ {0x0Au, 0x20u},
+ {0x0Bu, 0x44u},
+ {0x0Eu, 0x12u},
+ {0x10u, 0x22u},
+ {0x12u, 0x44u},
{0x16u, 0x80u},
- {0x1Bu, 0x04u},
- {0x1Eu, 0x2Au},
- {0x1Fu, 0x02u},
- {0x20u, 0x20u},
+ {0x18u, 0x40u},
+ {0x19u, 0x14u},
+ {0x1Au, 0x22u},
+ {0x1Bu, 0x05u},
+ {0x1Cu, 0x14u},
+ {0x1Eu, 0x22u},
{0x21u, 0x20u},
- {0x22u, 0x83u},
- {0x27u, 0x41u},
- {0x29u, 0x80u},
- {0x2Au, 0x02u},
- {0x2Bu, 0x14u},
- {0x2Cu, 0x01u},
- {0x2Fu, 0x02u},
- {0x30u, 0x02u},
- {0x32u, 0x98u},
- {0x36u, 0x08u},
- {0x39u, 0x69u},
- {0x3Cu, 0x80u},
- {0x3Fu, 0x04u},
- {0x59u, 0x14u},
- {0x5Au, 0x02u},
- {0x5Bu, 0x40u},
- {0x5Cu, 0x80u},
- {0x61u, 0x80u},
+ {0x24u, 0x08u},
+ {0x25u, 0x18u},
+ {0x27u, 0x20u},
+ {0x29u, 0x05u},
+ {0x2Au, 0x40u},
+ {0x2Bu, 0x01u},
+ {0x2Du, 0x11u},
+ {0x2Fu, 0x01u},
+ {0x30u, 0x22u},
+ {0x31u, 0x80u},
+ {0x33u, 0x04u},
+ {0x34u, 0x04u},
+ {0x37u, 0x21u},
+ {0x39u, 0x22u},
+ {0x3Bu, 0x44u},
+ {0x3Du, 0x20u},
+ {0x3Eu, 0x46u},
+ {0x58u, 0x40u},
+ {0x5Du, 0x40u},
+ {0x60u, 0x02u},
{0x66u, 0x80u},
- {0x83u, 0x01u},
- {0x87u, 0x01u},
- {0x8Bu, 0x01u},
- {0x8Cu, 0x04u},
- {0x90u, 0x04u},
- {0x91u, 0x14u},
- {0x92u, 0x24u},
- {0x93u, 0x06u},
- {0x95u, 0x61u},
- {0x96u, 0xC0u},
- {0x97u, 0x01u},
- {0x9Au, 0x41u},
- {0x9Cu, 0x0Eu},
- {0x9Du, 0x63u},
- {0x9Eu, 0x14u},
- {0x9Fu, 0x10u},
- {0xA0u, 0x04u},
+ {0x82u, 0x20u},
+ {0x89u, 0x02u},
+ {0x8Bu, 0x08u},
+ {0x8Cu, 0x02u},
+ {0x8Eu, 0x08u},
+ {0x8Fu, 0x02u},
+ {0x91u, 0x20u},
+ {0x92u, 0x10u},
+ {0x93u, 0xA0u},
+ {0x96u, 0x80u},
+ {0x97u, 0x44u},
+ {0x98u, 0x61u},
+ {0x99u, 0x02u},
+ {0x9Au, 0x18u},
+ {0x9Du, 0xA0u},
+ {0xA0u, 0x84u},
{0xA1u, 0x04u},
- {0xA3u, 0x81u},
- {0xA5u, 0x0Au},
- {0xA8u, 0x10u},
- {0xADu, 0x04u},
- {0xB2u, 0x80u},
- {0xB3u, 0x50u},
- {0xB5u, 0x20u},
- {0xB7u, 0x20u},
- {0xC0u, 0x07u},
- {0xC2u, 0xEFu},
- {0xC4u, 0x9Fu},
- {0xCAu, 0x1Fu},
- {0xCCu, 0x4Fu},
- {0xCEu, 0x5Fu},
- {0xD6u, 0x1Fu},
+ {0xA2u, 0x80u},
+ {0xA3u, 0x08u},
+ {0xA5u, 0x22u},
+ {0xA6u, 0x34u},
+ {0xA7u, 0x13u},
+ {0xA8u, 0x80u},
+ {0xA9u, 0x08u},
+ {0xABu, 0x20u},
+ {0xACu, 0x08u},
+ {0xAFu, 0x08u},
+ {0xB0u, 0x51u},
+ {0xB2u, 0x02u},
+ {0xB4u, 0x04u},
+ {0xB6u, 0x40u},
+ {0xB7u, 0x28u},
+ {0xC0u, 0x63u},
+ {0xC2u, 0xAFu},
+ {0xC4u, 0x1Fu},
+ {0xCAu, 0xBBu},
+ {0xCCu, 0xEFu},
+ {0xCEu, 0xFFu},
+ {0xD6u, 0x18u},
{0xD8u, 0x18u},
- {0xE2u, 0x85u},
- {0xE6u, 0x20u},
- {0xEAu, 0x48u},
- {0x80u, 0x04u},
- {0x82u, 0x02u},
- {0x94u, 0x04u},
- {0x96u, 0x0Au},
- {0x98u, 0x04u},
- {0x99u, 0x01u},
- {0x9Au, 0x12u},
- {0x9Cu, 0x02u},
- {0x9Eu, 0x04u},
- {0xA0u, 0x04u},
- {0xA2u, 0x03u},
- {0xB0u, 0x10u},
- {0xB2u, 0x01u},
- {0xB4u, 0x08u},
- {0xB6u, 0x06u},
- {0xB7u, 0x01u},
- {0xBAu, 0x80u},
+ {0xE0u, 0x04u},
+ {0xE4u, 0x04u},
+ {0xE8u, 0x0Au},
+ {0xEAu, 0x10u},
+ {0xEEu, 0x05u},
+ {0x85u, 0x02u},
+ {0x87u, 0x01u},
+ {0x8Du, 0x01u},
+ {0x8Fu, 0x02u},
+ {0x95u, 0x02u},
+ {0x97u, 0x01u},
+ {0xA2u, 0x02u},
+ {0xA5u, 0x02u},
+ {0xA7u, 0x01u},
+ {0xACu, 0x01u},
+ {0xADu, 0x02u},
+ {0xAFu, 0x05u},
+ {0xB0u, 0x01u},
+ {0xB2u, 0x02u},
+ {0xB3u, 0x04u},
+ {0xB7u, 0x03u},
+ {0xBBu, 0x80u},
+ {0xBEu, 0x01u},
{0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x92u},
+ {0xDCu, 0x22u},
{0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x98u},
- {0x01u, 0x80u},
- {0x05u, 0x01u},
- {0x09u, 0x20u},
- {0x0Au, 0x81u},
- {0x0Bu, 0x20u},
- {0x0Eu, 0x2Au},
- {0x10u, 0x20u},
- {0x11u, 0x41u},
- {0x12u, 0x0Cu},
- {0x16u, 0x80u},
- {0x18u, 0x10u},
- {0x1Bu, 0x10u},
- {0x1Du, 0x01u},
- {0x1Eu, 0x2Au},
- {0x22u, 0x14u},
- {0x27u, 0x02u},
- {0x28u, 0x08u},
- {0x32u, 0x14u},
- {0x37u, 0x20u},
- {0x39u, 0x14u},
- {0x3Au, 0x01u},
- {0x3Bu, 0x40u},
- {0x40u, 0x04u},
- {0x41u, 0x02u},
- {0x43u, 0x08u},
- {0x48u, 0x04u},
- {0x49u, 0x06u},
- {0x4Au, 0x02u},
- {0x50u, 0x02u},
- {0x53u, 0x52u},
+ {0x00u, 0x0Au},
+ {0x01u, 0xA0u},
+ {0x08u, 0x42u},
+ {0x0Bu, 0x08u},
+ {0x12u, 0x99u},
+ {0x14u, 0x01u},
+ {0x17u, 0x02u},
+ {0x19u, 0xA0u},
+ {0x1Au, 0x80u},
+ {0x1Eu, 0x80u},
+ {0x1Fu, 0x08u},
+ {0x20u, 0x20u},
+ {0x21u, 0x04u},
+ {0x22u, 0x20u},
+ {0x25u, 0x40u},
+ {0x26u, 0x04u},
+ {0x28u, 0x04u},
+ {0x2Eu, 0x80u},
+ {0x2Fu, 0x10u},
+ {0x30u, 0x40u},
+ {0x31u, 0x08u},
+ {0x32u, 0x60u},
+ {0x36u, 0x04u},
+ {0x38u, 0x80u},
+ {0x39u, 0x08u},
+ {0x3Du, 0x88u},
+ {0x40u, 0x44u},
+ {0x42u, 0x20u},
+ {0x49u, 0x15u},
+ {0x4Bu, 0x40u},
+ {0x50u, 0x01u},
+ {0x51u, 0x20u},
+ {0x52u, 0x04u},
+ {0x53u, 0x80u},
{0x5Cu, 0x80u},
- {0x62u, 0x80u},
+ {0x62u, 0x20u},
{0x66u, 0x80u},
- {0x68u, 0x20u},
- {0x69u, 0x69u},
- {0x6Bu, 0x04u},
- {0x71u, 0x40u},
+ {0x69u, 0x51u},
+ {0x6Au, 0x04u},
+ {0x6Bu, 0x51u},
{0x72u, 0x03u},
- {0x80u, 0x10u},
- {0x83u, 0x10u},
- {0x84u, 0x04u},
- {0x88u, 0x80u},
- {0x8Eu, 0x10u},
- {0x8Fu, 0x02u},
- {0x91u, 0x14u},
- {0x93u, 0x46u},
- {0x95u, 0x69u},
- {0x96u, 0xC1u},
- {0x97u, 0x20u},
- {0x98u, 0x01u},
- {0x9Au, 0x41u},
- {0x9Cu, 0x0Cu},
- {0x9Du, 0xE6u},
+ {0x73u, 0x01u},
+ {0x8Au, 0x60u},
+ {0x8Cu, 0x01u},
+ {0x90u, 0x48u},
+ {0x91u, 0x20u},
+ {0x92u, 0x02u},
+ {0x93u, 0xB0u},
+ {0x95u, 0x13u},
+ {0x96u, 0xC4u},
+ {0x97u, 0x46u},
+ {0x98u, 0x23u},
+ {0x99u, 0x12u},
+ {0x9Au, 0x10u},
+ {0x9Bu, 0x20u},
+ {0x9Cu, 0x04u},
+ {0x9Du, 0xA1u},
{0x9Eu, 0x06u},
- {0x9Fu, 0x14u},
- {0xA0u, 0x04u},
- {0xA1u, 0x24u},
- {0xA2u, 0x82u},
+ {0x9Fu, 0x05u},
+ {0xA0u, 0x84u},
+ {0xA1u, 0x0Cu},
+ {0xA2u, 0x88u},
+ {0xA3u, 0x05u},
{0xA4u, 0x62u},
- {0xA5u, 0x0Au},
- {0xA6u, 0x28u},
+ {0xA5u, 0x82u},
+ {0xA6u, 0x04u},
{0xA7u, 0x10u},
- {0xA9u, 0x93u},
- {0xAAu, 0x20u},
- {0xACu, 0x02u},
- {0xAFu, 0x40u},
- {0xB0u, 0x10u},
- {0xB2u, 0x04u},
- {0xB3u, 0x80u},
- {0xB4u, 0x80u},
- {0xC0u, 0x17u},
- {0xC2u, 0xEFu},
- {0xC4u, 0x1Fu},
- {0xCAu, 0x04u},
- {0xCCu, 0x26u},
- {0xCEu, 0x0Fu},
+ {0xAEu, 0x20u},
+ {0xAFu, 0x10u},
+ {0xB5u, 0x40u},
+ {0xB6u, 0x08u},
+ {0xB7u, 0x20u},
+ {0xC0u, 0x0Fu},
+ {0xC2u, 0x0Bu},
+ {0xC4u, 0x9Fu},
+ {0xCAu, 0x54u},
+ {0xCCu, 0x46u},
+ {0xCEu, 0x5Au},
{0xD0u, 0x07u},
{0xD2u, 0x0Cu},
{0xD6u, 0x10u},
- {0xD8u, 0x18u},
- {0xE0u, 0x20u},
- {0xE2u, 0x1Cu},
- {0xE8u, 0x10u},
- {0xEAu, 0x04u},
- {0xEEu, 0x42u},
- {0x04u, 0x0Du},
- {0x08u, 0x02u},
- {0x09u, 0x02u},
- {0x0Au, 0x08u},
- {0x0Bu, 0x01u},
- {0x0Cu, 0x01u},
+ {0xD8u, 0x14u},
+ {0xE2u, 0x21u},
+ {0xE4u, 0x80u},
+ {0xE8u, 0x40u},
+ {0xEEu, 0x02u},
+ {0x00u, 0x04u},
+ {0x02u, 0x02u},
{0x0Du, 0x02u},
- {0x0Eu, 0x02u},
- {0x0Fu, 0x05u},
- {0x10u, 0x0Du},
+ {0x0Fu, 0x01u},
{0x11u, 0x02u},
{0x13u, 0x09u},
+ {0x14u, 0x02u},
{0x15u, 0x02u},
+ {0x16u, 0x04u},
{0x17u, 0x01u},
- {0x18u, 0x02u},
+ {0x18u, 0x04u},
{0x19u, 0x01u},
- {0x1Au, 0x0Du},
+ {0x1Au, 0x0Au},
{0x1Bu, 0x02u},
- {0x1Cu, 0x02u},
- {0x1Eu, 0x04u},
- {0x20u, 0x0Du},
- {0x28u, 0x0Du},
- {0x2Cu, 0x0Du},
- {0x33u, 0x03u},
- {0x34u, 0x0Fu},
- {0x35u, 0x04u},
+ {0x1Cu, 0x04u},
+ {0x1Eu, 0x03u},
+ {0x24u, 0x04u},
+ {0x26u, 0x12u},
+ {0x29u, 0x02u},
+ {0x2Bu, 0x05u},
+ {0x30u, 0x01u},
+ {0x32u, 0x06u},
+ {0x33u, 0x04u},
+ {0x34u, 0x10u},
+ {0x35u, 0x03u},
+ {0x36u, 0x08u},
{0x37u, 0x08u},
- {0x3Au, 0x20u},
- {0x3Bu, 0x08u},
+ {0x3Au, 0x08u},
+ {0x3Bu, 0x20u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x21u},
+ {0x5Cu, 0x22u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x80u, 0x02u},
- {0x85u, 0x18u},
- {0x8Cu, 0x10u},
- {0x8Du, 0x05u},
- {0x8Eu, 0x20u},
- {0x8Fu, 0x28u},
- {0x90u, 0x10u},
- {0x91u, 0x02u},
- {0x92u, 0x20u},
- {0x94u, 0x34u},
- {0x95u, 0x02u},
- {0x98u, 0x03u},
- {0x99u, 0x09u},
- {0x9Au, 0x0Cu},
- {0x9Bu, 0x24u},
- {0x9Eu, 0x01u},
- {0xA0u, 0x08u},
- {0xA2u, 0x37u},
- {0xA4u, 0x3Du},
- {0xA6u, 0x02u},
- {0xA9u, 0x02u},
- {0xAAu, 0x37u},
- {0xACu, 0x0Bu},
- {0xADu, 0x25u},
- {0xAEu, 0x34u},
- {0xAFu, 0x10u},
- {0xB0u, 0x30u},
- {0xB1u, 0x20u},
- {0xB3u, 0x1Cu},
+ {0x80u, 0xC6u},
+ {0x81u, 0x10u},
+ {0x84u, 0x42u},
+ {0x85u, 0x22u},
+ {0x87u, 0x08u},
+ {0x88u, 0x39u},
+ {0x89u, 0x04u},
+ {0x8Au, 0x06u},
+ {0x8Cu, 0x01u},
+ {0x8Du, 0x08u},
+ {0x8Eu, 0x5Eu},
+ {0x8Fu, 0x21u},
+ {0x91u, 0x01u},
+ {0x94u, 0x77u},
+ {0x96u, 0x08u},
+ {0x98u, 0xC2u},
+ {0x99u, 0x01u},
+ {0x9Au, 0x04u},
+ {0x9Cu, 0x04u},
+ {0x9Du, 0x01u},
+ {0x9Eu, 0x20u},
+ {0xA0u, 0xC6u},
+ {0xA1u, 0x01u},
+ {0xA8u, 0x80u},
+ {0xA9u, 0x01u},
+ {0xAAu, 0x46u},
+ {0xACu, 0x46u},
+ {0xADu, 0x07u},
+ {0xAEu, 0x80u},
+ {0xAFu, 0x18u},
+ {0xB0u, 0x70u},
+ {0xB1u, 0x3Fu},
{0xB4u, 0x0Fu},
- {0xB5u, 0x02u},
- {0xB7u, 0x01u},
- {0xB9u, 0x08u},
- {0xBAu, 0x22u},
- {0xBFu, 0x51u},
+ {0xB6u, 0x80u},
+ {0xB7u, 0x08u},
+ {0xB8u, 0x20u},
+ {0xB9u, 0x02u},
+ {0xBAu, 0x03u},
+ {0xBEu, 0x40u},
+ {0xBFu, 0x41u},
{0xD4u, 0x09u},
{0xD6u, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x12u},
- {0xDDu, 0x10u},
+ {0xDCu, 0x01u},
{0xDFu, 0x01u},
- {0x01u, 0x80u},
- {0x02u, 0x40u},
- {0x04u, 0x80u},
- {0x05u, 0x10u},
- {0x06u, 0x20u},
- {0x08u, 0x08u},
- {0x0Au, 0x44u},
+ {0x00u, 0x40u},
+ {0x01u, 0x20u},
+ {0x02u, 0x10u},
+ {0x03u, 0x40u},
+ {0x04u, 0x08u},
+ {0x05u, 0x01u},
+ {0x06u, 0x10u},
+ {0x09u, 0x08u},
+ {0x0Au, 0x04u},
{0x0Bu, 0x02u},
- {0x0Du, 0x01u},
- {0x0Eu, 0x08u},
- {0x0Fu, 0x02u},
- {0x10u, 0x40u},
- {0x11u, 0x08u},
- {0x13u, 0x60u},
- {0x16u, 0x0Au},
- {0x17u, 0x01u},
- {0x1Au, 0x44u},
- {0x1Eu, 0x08u},
- {0x21u, 0x04u},
- {0x22u, 0xA0u},
- {0x23u, 0x90u},
- {0x24u, 0x20u},
- {0x25u, 0x50u},
- {0x27u, 0x20u},
- {0x2Au, 0x10u},
- {0x2Bu, 0x01u},
- {0x31u, 0x12u},
- {0x32u, 0x08u},
+ {0x0Eu, 0x2Au},
+ {0x11u, 0x50u},
+ {0x13u, 0x01u},
+ {0x16u, 0x20u},
+ {0x18u, 0xC0u},
+ {0x19u, 0x60u},
+ {0x1Au, 0x48u},
+ {0x1Du, 0x01u},
+ {0x1Eu, 0x2Au},
+ {0x1Fu, 0x04u},
+ {0x21u, 0x02u},
+ {0x22u, 0x40u},
+ {0x25u, 0x40u},
+ {0x26u, 0x28u},
+ {0x27u, 0x0Au},
+ {0x28u, 0x10u},
+ {0x2Au, 0x44u},
+ {0x2Bu, 0x47u},
+ {0x2Fu, 0x08u},
+ {0x30u, 0x26u},
+ {0x31u, 0x80u},
+ {0x32u, 0x04u},
{0x34u, 0x02u},
- {0x37u, 0x24u},
- {0x38u, 0x80u},
- {0x39u, 0x08u},
- {0x3Du, 0xA0u},
+ {0x36u, 0x28u},
+ {0x38u, 0x02u},
+ {0x39u, 0x20u},
+ {0x3Bu, 0x44u},
+ {0x3Du, 0x80u},
+ {0x58u, 0x10u},
{0x59u, 0x04u},
- {0x5Au, 0x12u},
- {0x5Bu, 0x80u},
- {0x5Eu, 0x80u},
- {0x62u, 0x81u},
+ {0x5Au, 0x82u},
+ {0x5Du, 0x80u},
+ {0x5Fu, 0x10u},
+ {0x60u, 0x80u},
+ {0x62u, 0x80u},
{0x64u, 0x02u},
- {0x7Eu, 0x08u},
- {0x7Fu, 0x08u},
- {0x81u, 0x80u},
- {0x86u, 0x40u},
- {0x8Au, 0x04u},
- {0x8Cu, 0x04u},
- {0x91u, 0x61u},
- {0x92u, 0x28u},
- {0x93u, 0x46u},
- {0x94u, 0x24u},
- {0x96u, 0xC0u},
- {0x98u, 0x41u},
- {0x99u, 0x42u},
- {0x9Au, 0x40u},
- {0x9Fu, 0x20u},
- {0xA0u, 0x20u},
- {0xA1u, 0x04u},
- {0xA2u, 0x01u},
- {0xA4u, 0x40u},
- {0xA5u, 0x02u},
- {0xA6u, 0x28u},
- {0xA7u, 0x08u},
- {0xA8u, 0x10u},
- {0xA9u, 0x20u},
- {0xAFu, 0x50u},
- {0xB0u, 0x48u},
- {0xB1u, 0x08u},
- {0xB3u, 0x02u},
- {0xC0u, 0xE9u},
- {0xC2u, 0xDFu},
- {0xC4u, 0xDFu},
- {0xCAu, 0x0Cu},
- {0xCCu, 0xE7u},
- {0xCEu, 0x3Au},
- {0xD6u, 0x1Fu},
- {0xD8u, 0x19u},
+ {0x66u, 0x20u},
+ {0x84u, 0x80u},
+ {0x85u, 0x40u},
+ {0x90u, 0x0Au},
+ {0x91u, 0x70u},
+ {0x92u, 0x07u},
+ {0x93u, 0x11u},
+ {0x94u, 0x84u},
+ {0x95u, 0x02u},
+ {0x96u, 0x40u},
+ {0x97u, 0x4Eu},
+ {0x98u, 0x20u},
+ {0x99u, 0x06u},
+ {0x9Au, 0x06u},
+ {0x9Bu, 0x71u},
+ {0x9Cu, 0x04u},
+ {0x9Fu, 0x06u},
+ {0xA0u, 0x10u},
+ {0xA1u, 0x28u},
+ {0xA3u, 0x8Du},
+ {0xA4u, 0x62u},
+ {0xA5u, 0x82u},
+ {0xAAu, 0x01u},
+ {0xABu, 0x10u},
+ {0xACu, 0x81u},
+ {0xAFu, 0x40u},
+ {0xB1u, 0x40u},
+ {0xB3u, 0x01u},
+ {0xB4u, 0x80u},
+ {0xC0u, 0x1Fu},
+ {0xC2u, 0xE7u},
+ {0xC4u, 0x2Bu},
+ {0xCAu, 0x2Du},
+ {0xCCu, 0xEDu},
+ {0xCEu, 0x1Fu},
+ {0xD6u, 0x3Fu},
+ {0xD8u, 0x39u},
{0xE2u, 0x04u},
- {0xE4u, 0x40u},
- {0xE8u, 0x0Cu},
- {0xEAu, 0x01u},
- {0xECu, 0x02u},
- {0xEEu, 0x01u},
- {0x00u, 0x11u},
- {0x02u, 0x22u},
- {0x03u, 0x0Cu},
- {0x06u, 0xFFu},
- {0x07u, 0x10u},
- {0x08u, 0x0Fu},
- {0x09u, 0x01u},
- {0x0Au, 0xF0u},
- {0x0Cu, 0x21u},
- {0x0Eu, 0x12u},
- {0x0Fu, 0x10u},
- {0x12u, 0xFFu},
+ {0xE4u, 0x08u},
+ {0xE6u, 0x04u},
+ {0xE8u, 0x08u},
+ {0xEAu, 0x05u},
+ {0xEEu, 0x09u},
+ {0x00u, 0x04u},
+ {0x01u, 0x01u},
+ {0x03u, 0x02u},
+ {0x05u, 0x04u},
+ {0x06u, 0x20u},
+ {0x07u, 0x08u},
+ {0x09u, 0x10u},
+ {0x0Au, 0x07u},
+ {0x0Bu, 0x8Fu},
+ {0x0Cu, 0x01u},
+ {0x0Du, 0x0Fu},
+ {0x0Fu, 0x80u},
+ {0x11u, 0x01u},
{0x13u, 0x02u},
- {0x14u, 0x84u},
- {0x15u, 0x10u},
- {0x16u, 0x48u},
- {0x17u, 0x08u},
- {0x18u, 0xFFu},
- {0x19u, 0x01u},
- {0x20u, 0x33u},
- {0x22u, 0xCCu},
- {0x24u, 0x44u},
- {0x25u, 0x01u},
- {0x26u, 0x88u},
- {0x29u, 0x10u},
- {0x2Bu, 0x04u},
- {0x2Du, 0x01u},
- {0x31u, 0x1Cu},
- {0x32u, 0xFFu},
- {0x33u, 0x02u},
- {0x35u, 0x01u},
- {0x3Eu, 0x04u},
- {0x3Fu, 0x10u},
+ {0x15u, 0x20u},
+ {0x16u, 0x18u},
+ {0x17u, 0x0Fu},
+ {0x18u, 0x07u},
+ {0x19u, 0x04u},
+ {0x1Bu, 0x08u},
+ {0x1Eu, 0x20u},
+ {0x20u, 0x20u},
+ {0x21u, 0x4Fu},
+ {0x22u, 0x10u},
+ {0x23u, 0x80u},
+ {0x26u, 0x02u},
+ {0x27u, 0x10u},
+ {0x28u, 0x20u},
+ {0x29u, 0x50u},
+ {0x2Au, 0x08u},
+ {0x2Bu, 0x8Fu},
+ {0x31u, 0x03u},
+ {0x32u, 0x38u},
+ {0x33u, 0xF0u},
+ {0x34u, 0x07u},
+ {0x35u, 0x0Cu},
+ {0x39u, 0x08u},
+ {0x3Bu, 0x22u},
+ {0x3Eu, 0x10u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x20u},
+ {0x5Cu, 0x22u},
{0x5Fu, 0x01u},
- {0x80u, 0x01u},
- {0x82u, 0x02u},
- {0x84u, 0x04u},
- {0x86u, 0x09u},
- {0x89u, 0x01u},
- {0x8Cu, 0x08u},
- {0x8Du, 0x01u},
- {0x8Eu, 0x04u},
- {0x8Fu, 0x02u},
- {0x91u, 0x02u},
- {0x98u, 0x08u},
- {0x9Au, 0x04u},
- {0x9Cu, 0x08u},
- {0x9Eu, 0x04u},
- {0xA0u, 0x08u},
- {0xA2u, 0x16u},
- {0xA3u, 0x04u},
- {0xAFu, 0x08u},
- {0xB0u, 0x10u},
- {0xB1u, 0x08u},
- {0xB3u, 0x04u},
- {0xB4u, 0x0Cu},
- {0xB6u, 0x03u},
- {0xB7u, 0x03u},
- {0xBAu, 0x20u},
- {0xBEu, 0x40u},
- {0xBFu, 0x40u},
- {0xD6u, 0x08u},
- {0xD8u, 0x04u},
- {0xD9u, 0x04u},
- {0xDBu, 0x04u},
- {0xDCu, 0x22u},
- {0xDDu, 0x90u},
- {0xDFu, 0x01u},
- {0x00u, 0x02u},
- {0x03u, 0x22u},
- {0x04u, 0x02u},
- {0x05u, 0x28u},
- {0x06u, 0x02u},
- {0x08u, 0x40u},
- {0x0Au, 0x0Au},
- {0x0Eu, 0x80u},
- {0x0Fu, 0x28u},
- {0x13u, 0x01u},
- {0x15u, 0x04u},
- {0x17u, 0x01u},
- {0x1Au, 0x01u},
- {0x1Bu, 0xA3u},
- {0x1Cu, 0x20u},
- {0x22u, 0x85u},
- {0x25u, 0x01u},
- {0x27u, 0x14u},
- {0x28u, 0x40u},
- {0x2Bu, 0x01u},
- {0x2Eu, 0x40u},
- {0x2Fu, 0x14u},
- {0x30u, 0x02u},
- {0x36u, 0x09u},
- {0x37u, 0x20u},
- {0x39u, 0x50u},
- {0x3Cu, 0x28u},
- {0x3Du, 0x82u},
- {0x58u, 0x24u},
- {0x5Au, 0x80u},
- {0x5Bu, 0x02u},
- {0x5Du, 0x08u},
- {0x5Eu, 0x08u},
- {0x60u, 0x84u},
- {0x61u, 0x04u},
- {0x62u, 0x01u},
- {0x63u, 0x11u},
- {0x68u, 0x01u},
- {0x6Du, 0x40u},
- {0x6Fu, 0x01u},
- {0x80u, 0x04u},
- {0x83u, 0x04u},
- {0x84u, 0x04u},
- {0x86u, 0x80u},
- {0x8Au, 0x02u},
- {0x8Bu, 0x02u},
- {0x8Cu, 0x20u},
+ {0x80u, 0x05u},
+ {0x82u, 0x0Au},
+ {0x85u, 0x08u},
+ {0x88u, 0x06u},
+ {0x89u, 0x20u},
+ {0x8Au, 0x09u},
+ {0x8Cu, 0x0Fu},
+ {0x8Eu, 0xF0u},
+ {0x90u, 0x30u},
{0x91u, 0x10u},
- {0x93u, 0x28u},
- {0x94u, 0x20u},
- {0x95u, 0x4Eu},
- {0x96u, 0x01u},
- {0x98u, 0x12u},
- {0x99u, 0x20u},
- {0x9Au, 0x40u},
- {0x9Cu, 0x80u},
- {0x9Du, 0x55u},
- {0x9Eu, 0x0Eu},
- {0xA0u, 0x0Cu},
- {0xA1u, 0x40u},
- {0xA2u, 0x2Cu},
- {0xA3u, 0x44u},
- {0xA4u, 0x80u},
- {0xA5u, 0x2Bu},
- {0xA7u, 0x90u},
- {0xAAu, 0x40u},
- {0xABu, 0x42u},
- {0xACu, 0x14u},
- {0xB1u, 0x80u},
- {0xB2u, 0x04u},
- {0xB3u, 0x05u},
- {0xC0u, 0xFDu},
- {0xC2u, 0x73u},
- {0xC4u, 0x38u},
- {0xCAu, 0x79u},
- {0xCCu, 0xE1u},
- {0xCEu, 0xFCu},
- {0xD6u, 0x0Fu},
- {0xD8u, 0x0Fu},
- {0xE0u, 0x81u},
- {0xE2u, 0x08u},
- {0xE4u, 0x08u},
- {0xEAu, 0x81u},
- {0xECu, 0x80u},
- {0xEEu, 0x20u},
- {0x03u, 0x4Cu},
- {0x05u, 0x01u},
- {0x07u, 0x30u},
- {0x08u, 0x05u},
- {0x09u, 0x40u},
- {0x0Au, 0x0Au},
- {0x0Bu, 0x1Cu},
- {0x0Du, 0x04u},
- {0x0Fu, 0x08u},
- {0x10u, 0x30u},
- {0x12u, 0xC0u},
- {0x13u, 0x0Cu},
- {0x14u, 0x50u},
- {0x15u, 0x4Cu},
- {0x16u, 0xA0u},
- {0x17u, 0x20u},
- {0x18u, 0x60u},
- {0x19u, 0x02u},
- {0x1Au, 0x90u},
- {0x1Du, 0x0Cu},
- {0x20u, 0x03u},
- {0x21u, 0x01u},
- {0x22u, 0x0Cu},
- {0x23u, 0x02u},
- {0x24u, 0x06u},
- {0x26u, 0x09u},
- {0x2Bu, 0x40u},
- {0x2Cu, 0x0Fu},
- {0x2Du, 0x04u},
- {0x2Eu, 0xF0u},
- {0x2Fu, 0x08u},
- {0x31u, 0x0Cu},
- {0x34u, 0xFFu},
- {0x35u, 0x70u},
- {0x37u, 0x03u},
- {0x3Bu, 0x02u},
- {0x3Eu, 0x10u},
- {0x3Fu, 0x40u},
- {0x58u, 0x04u},
- {0x59u, 0x04u},
- {0x5Cu, 0x20u},
- {0x5Fu, 0x01u},
- {0x80u, 0x01u},
- {0x81u, 0x01u},
- {0x82u, 0xF8u},
- {0x83u, 0x02u},
- {0x84u, 0x40u},
- {0x85u, 0x01u},
- {0x86u, 0x80u},
- {0x87u, 0x02u},
- {0x88u, 0x10u},
- {0x89u, 0x04u},
- {0x8Au, 0x20u},
- {0x8Bu, 0x08u},
- {0x8Cu, 0x10u},
- {0x8Du, 0x20u},
- {0x8Eu, 0x20u},
- {0x8Fu, 0x1Fu},
- {0x90u, 0x02u},
- {0x92u, 0xF0u},
- {0x94u, 0x05u},
+ {0x92u, 0xC0u},
+ {0x94u, 0x03u},
{0x95u, 0x04u},
- {0x96u, 0xF8u},
- {0x97u, 0x08u},
- {0x99u, 0x0Fu},
- {0x9Au, 0x01u},
- {0x9Bu, 0x10u},
- {0x9Cu, 0xF0u},
- {0x9Du, 0x10u},
- {0x9Eu, 0x08u},
- {0x9Fu, 0x20u},
- {0xA0u, 0x40u},
- {0xA1u, 0x0Fu},
- {0xA2u, 0x80u},
- {0xA3u, 0x10u},
- {0xA8u, 0xF4u},
- {0xA9u, 0x20u},
- {0xAAu, 0x08u},
- {0xABu, 0x1Fu},
- {0xAFu, 0x1Fu},
+ {0x96u, 0x0Cu},
+ {0x9Du, 0x01u},
+ {0xA4u, 0x60u},
+ {0xA6u, 0x90u},
+ {0xA8u, 0x50u},
+ {0xA9u, 0x02u},
+ {0xAAu, 0xA0u},
+ {0xADu, 0x15u},
+ {0xAFu, 0x2Au},
{0xB1u, 0x30u},
- {0xB2u, 0x0Fu},
- {0xB3u, 0x03u},
- {0xB4u, 0x30u},
- {0xB5u, 0x0Cu},
- {0xB6u, 0xC0u},
- {0xB8u, 0x08u},
- {0xBAu, 0xA0u},
- {0xBBu, 0x2Au},
- {0xD4u, 0x40u},
+ {0xB3u, 0x0Cu},
+ {0xB5u, 0x03u},
+ {0xB6u, 0xFFu},
+ {0xBEu, 0x40u},
+ {0xBFu, 0x15u},
+ {0xD4u, 0x01u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x22u},
+ {0xDDu, 0x20u},
{0xDFu, 0x01u},
- {0x03u, 0x04u},
- {0x04u, 0x02u},
+ {0x00u, 0x02u},
+ {0x02u, 0x80u},
+ {0x03u, 0x0Au},
{0x05u, 0x10u},
- {0x06u, 0x20u},
- {0x07u, 0x01u},
- {0x08u, 0x01u},
- {0x09u, 0x2Au},
- {0x0Eu, 0x69u},
- {0x11u, 0x43u},
- {0x12u, 0x01u},
- {0x13u, 0x04u},
- {0x14u, 0x80u},
- {0x15u, 0x20u},
- {0x18u, 0x08u},
- {0x19u, 0x20u},
- {0x1Cu, 0x30u},
- {0x1Eu, 0x24u},
- {0x1Fu, 0x44u},
- {0x20u, 0x82u},
- {0x23u, 0x44u},
- {0x25u, 0x14u},
- {0x27u, 0x48u},
- {0x29u, 0x40u},
- {0x2Au, 0x11u},
- {0x2Fu, 0x86u},
- {0x31u, 0x20u},
- {0x32u, 0x08u},
- {0x33u, 0x82u},
- {0x34u, 0x20u},
- {0x35u, 0x04u},
- {0x37u, 0x40u},
- {0x38u, 0x12u},
- {0x3Bu, 0x44u},
- {0x3Du, 0xA8u},
- {0x3Fu, 0x01u},
- {0x64u, 0x04u},
- {0x65u, 0x80u},
- {0x67u, 0x10u},
- {0x78u, 0x20u},
- {0x79u, 0x20u},
- {0x7Au, 0x08u},
- {0x81u, 0x04u},
- {0x84u, 0x01u},
- {0x86u, 0x20u},
- {0x87u, 0x40u},
+ {0x06u, 0xA2u},
+ {0x0Au, 0x20u},
+ {0x0Bu, 0x40u},
+ {0x0Du, 0x10u},
+ {0x0Eu, 0x22u},
+ {0x10u, 0x04u},
+ {0x13u, 0x14u},
+ {0x14u, 0x20u},
+ {0x15u, 0x01u},
+ {0x17u, 0x10u},
+ {0x1Bu, 0x80u},
+ {0x1Eu, 0x20u},
+ {0x1Fu, 0x18u},
+ {0x20u, 0x08u},
+ {0x21u, 0x06u},
+ {0x24u, 0x20u},
+ {0x26u, 0x2Au},
+ {0x27u, 0x10u},
+ {0x28u, 0x04u},
+ {0x2Bu, 0x02u},
+ {0x2Cu, 0x28u},
+ {0x2Du, 0x01u},
+ {0x2Fu, 0x20u},
+ {0x32u, 0x81u},
+ {0x33u, 0x08u},
+ {0x34u, 0x08u},
+ {0x36u, 0x22u},
+ {0x39u, 0x10u},
+ {0x3Bu, 0x04u},
+ {0x3Du, 0x80u},
+ {0x3Eu, 0x20u},
+ {0x3Fu, 0x0Au},
+ {0x44u, 0x08u},
+ {0x46u, 0x04u},
+ {0x48u, 0x08u},
+ {0x4Au, 0x08u},
+ {0x58u, 0x60u},
+ {0x59u, 0x20u},
+ {0x5Cu, 0x04u},
+ {0x5Eu, 0x40u},
+ {0x5Fu, 0x21u},
+ {0x64u, 0x40u},
+ {0x65u, 0x81u},
+ {0x6Fu, 0x02u},
+ {0x85u, 0x02u},
+ {0x89u, 0x02u},
+ {0x8Eu, 0x04u},
{0x8Fu, 0x01u},
- {0x90u, 0x02u},
- {0x91u, 0x10u},
- {0x93u, 0x31u},
- {0x94u, 0x28u},
- {0x95u, 0x4Fu},
- {0x97u, 0x02u},
- {0x98u, 0x02u},
- {0x9Au, 0x50u},
- {0x9Bu, 0x04u},
- {0x9Cu, 0x21u},
- {0x9Du, 0x01u},
- {0x9Eu, 0x0Eu},
- {0x9Fu, 0x08u},
- {0xA0u, 0x0Cu},
+ {0x91u, 0xA1u},
+ {0x92u, 0x62u},
+ {0x93u, 0x08u},
+ {0x94u, 0xA8u},
+ {0x95u, 0x1Cu},
+ {0x97u, 0x40u},
+ {0x98u, 0x80u},
+ {0x99u, 0x01u},
+ {0x9Au, 0x32u},
+ {0x9Bu, 0x28u},
+ {0x9Du, 0x08u},
+ {0x9Eu, 0x04u},
+ {0xA0u, 0x23u},
{0xA1u, 0x40u},
- {0xA2u, 0x2Cu},
- {0xA3u, 0x44u},
- {0xA4u, 0xD0u},
- {0xA5u, 0x08u},
- {0xA6u, 0x10u},
- {0xA7u, 0x92u},
- {0xABu, 0x08u},
- {0xAEu, 0x40u},
- {0xAFu, 0x20u},
- {0xB1u, 0x10u},
- {0xB2u, 0x10u},
- {0xB3u, 0x10u},
- {0xB5u, 0x30u},
- {0xC0u, 0xF2u},
- {0xC2u, 0xFEu},
- {0xC4u, 0x5Du},
- {0xCAu, 0xBDu},
- {0xCCu, 0x7Fu},
- {0xCEu, 0xFFu},
- {0xD8u, 0x70u},
- {0xE0u, 0x40u},
- {0xE4u, 0x08u},
+ {0xA2u, 0x05u},
+ {0xA3u, 0x45u},
+ {0xA4u, 0x54u},
+ {0xA5u, 0x01u},
+ {0xA6u, 0x2Au},
+ {0xA7u, 0x82u},
+ {0xAAu, 0x28u},
+ {0xACu, 0x10u},
+ {0xADu, 0x08u},
+ {0xAEu, 0x80u},
+ {0xAFu, 0x10u},
+ {0xB2u, 0x02u},
+ {0xB3u, 0x20u},
+ {0xB7u, 0x40u},
+ {0xC0u, 0xFBu},
+ {0xC2u, 0xECu},
+ {0xC4u, 0x76u},
+ {0xCAu, 0xECu},
+ {0xCCu, 0xEBu},
+ {0xCEu, 0xF6u},
+ {0xD6u, 0xF8u},
+ {0xD8u, 0x10u},
+ {0xE2u, 0x04u},
+ {0xE6u, 0x04u},
{0xE8u, 0x82u},
- {0xECu, 0xA0u},
- {0xEEu, 0x40u},
- {0x00u, 0x03u},
- {0x01u, 0x20u},
- {0x02u, 0x0Cu},
- {0x03u, 0x40u},
- {0x06u, 0x80u},
- {0x08u, 0x06u},
- {0x09u, 0x01u},
- {0x0Au, 0x09u},
- {0x0Bu, 0x6Eu},
- {0x0Du, 0x03u},
- {0x0Eu, 0x70u},
- {0x0Fu, 0x74u},
- {0x10u, 0xC0u},
- {0x11u, 0x20u},
- {0x12u, 0x1Fu},
- {0x13u, 0x40u},
- {0x14u, 0x90u},
- {0x15u, 0x78u},
- {0x16u, 0x2Fu},
- {0x17u, 0x03u},
- {0x18u, 0x0Fu},
- {0x19u, 0x02u},
- {0x20u, 0x05u},
- {0x21u, 0x64u},
- {0x22u, 0x0Au},
- {0x24u, 0xA0u},
- {0x25u, 0x80u},
- {0x26u, 0x4Fu},
- {0x27u, 0x01u},
- {0x2Bu, 0x08u},
- {0x2Fu, 0x7Fu},
- {0x30u, 0x7Fu},
- {0x31u, 0x60u},
- {0x35u, 0x80u},
- {0x36u, 0x80u},
- {0x37u, 0x1Fu},
- {0x3Bu, 0x02u},
- {0x3Eu, 0x40u},
- {0x3Fu, 0x10u},
- {0x54u, 0x01u},
+ {0xEAu, 0x01u},
+ {0xECu, 0x60u},
+ {0xEEu, 0x02u},
+ {0x01u, 0x04u},
+ {0x02u, 0x40u},
+ {0x03u, 0x02u},
+ {0x06u, 0x30u},
+ {0x0Bu, 0x04u},
+ {0x0Du, 0x10u},
+ {0x10u, 0x48u},
+ {0x11u, 0x08u},
+ {0x12u, 0x24u},
+ {0x13u, 0x10u},
+ {0x16u, 0x48u},
+ {0x17u, 0x04u},
+ {0x19u, 0x08u},
+ {0x1Au, 0x01u},
+ {0x1Bu, 0x03u},
+ {0x1Eu, 0x06u},
+ {0x22u, 0x08u},
+ {0x28u, 0x48u},
+ {0x29u, 0x04u},
+ {0x2Au, 0x12u},
+ {0x2Bu, 0x01u},
+ {0x30u, 0x01u},
+ {0x33u, 0x18u},
+ {0x34u, 0x70u},
+ {0x35u, 0x07u},
+ {0x36u, 0x0Eu},
+ {0x3Fu, 0x04u},
+ {0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
{0x5Cu, 0x22u},
- {0x5Du, 0x20u},
+ {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x81u, 0x10u},
- {0x88u, 0x40u},
- {0x8Cu, 0x53u},
- {0x8Du, 0x01u},
- {0x8Eu, 0xACu},
- {0x90u, 0x02u},
- {0x91u, 0x15u},
- {0x92u, 0x01u},
- {0x93u, 0x2Au},
- {0x94u, 0x80u},
- {0x9Du, 0x02u},
- {0xA0u, 0x08u},
- {0xA1u, 0x04u},
- {0xA2u, 0x04u},
- {0xA5u, 0x08u},
- {0xA8u, 0x24u},
- {0xAAu, 0x08u},
- {0xACu, 0x11u},
- {0xADu, 0x20u},
- {0xAEu, 0x02u},
- {0xB0u, 0xC0u},
- {0xB1u, 0x0Cu},
- {0xB2u, 0x0Fu},
- {0xB3u, 0x30u},
- {0xB4u, 0x30u},
- {0xB5u, 0x03u},
- {0xBEu, 0x15u},
- {0xBFu, 0x15u},
- {0xD6u, 0x08u},
+ {0x82u, 0x70u},
+ {0x84u, 0xC0u},
+ {0x86u, 0x1Fu},
+ {0x88u, 0x90u},
+ {0x8Au, 0x2Fu},
+ {0x8Cu, 0x06u},
+ {0x8Eu, 0x09u},
+ {0x8Fu, 0x04u},
+ {0x94u, 0x03u},
+ {0x96u, 0x0Cu},
+ {0x97u, 0x02u},
+ {0x98u, 0x0Fu},
+ {0x9Cu, 0xA0u},
+ {0x9Eu, 0x4Fu},
+ {0xA0u, 0x05u},
+ {0xA2u, 0x0Au},
+ {0xA6u, 0x80u},
+ {0xA9u, 0x01u},
+ {0xADu, 0x02u},
+ {0xAFu, 0x04u},
+ {0xB0u, 0x7Fu},
+ {0xB5u, 0x01u},
+ {0xB6u, 0x80u},
+ {0xB7u, 0x06u},
+ {0xBEu, 0x40u},
+ {0xBFu, 0x50u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDDu, 0x90u},
+ {0xDCu, 0x02u},
{0xDFu, 0x01u},
- {0x01u, 0x40u},
- {0x03u, 0x05u},
- {0x04u, 0x60u},
- {0x05u, 0x09u},
- {0x09u, 0x08u},
- {0x0Au, 0x80u},
- {0x0Bu, 0x40u},
- {0x0Eu, 0xA8u},
+ {0x00u, 0x04u},
+ {0x01u, 0x02u},
+ {0x02u, 0x10u},
+ {0x04u, 0xA0u},
+ {0x05u, 0x01u},
+ {0x06u, 0x20u},
+ {0x09u, 0x04u},
+ {0x0Au, 0x0Au},
+ {0x0Bu, 0x80u},
+ {0x0Cu, 0x60u},
+ {0x0Eu, 0x20u},
{0x10u, 0x80u},
- {0x12u, 0x05u},
- {0x14u, 0x20u},
+ {0x12u, 0x08u},
{0x15u, 0x02u},
- {0x18u, 0x80u},
- {0x1Bu, 0x24u},
- {0x1Cu, 0x40u},
- {0x1Du, 0x40u},
- {0x22u, 0x01u},
- {0x23u, 0x24u},
- {0x24u, 0x02u},
- {0x25u, 0x61u},
- {0x26u, 0x42u},
- {0x28u, 0x01u},
- {0x2Au, 0x02u},
- {0x2Bu, 0x10u},
- {0x2Cu, 0x20u},
- {0x2Fu, 0x86u},
- {0x30u, 0x80u},
- {0x33u, 0x01u},
- {0x34u, 0x02u},
- {0x35u, 0x20u},
- {0x36u, 0x08u},
+ {0x17u, 0x04u},
+ {0x18u, 0x04u},
+ {0x1Au, 0x82u},
+ {0x1Du, 0x41u},
+ {0x21u, 0x08u},
+ {0x22u, 0x10u},
+ {0x25u, 0x50u},
+ {0x26u, 0x80u},
+ {0x27u, 0x01u},
+ {0x29u, 0x10u},
+ {0x2Cu, 0x40u},
+ {0x2Du, 0x41u},
+ {0x2Fu, 0x08u},
+ {0x30u, 0x08u},
+ {0x32u, 0x10u},
+ {0x33u, 0x02u},
+ {0x37u, 0x08u},
{0x39u, 0x01u},
+ {0x3Au, 0x20u},
{0x3Bu, 0x40u},
- {0x3Cu, 0x20u},
- {0x3Du, 0x82u},
- {0x59u, 0x10u},
- {0x5Bu, 0x40u},
- {0x5Cu, 0x40u},
- {0x62u, 0x60u},
- {0x63u, 0x01u},
- {0x82u, 0x02u},
- {0x86u, 0x01u},
- {0x87u, 0x24u},
- {0x8Cu, 0x40u},
- {0x8Eu, 0x01u},
- {0x92u, 0x80u},
- {0x93u, 0x28u},
- {0x94u, 0x08u},
- {0x95u, 0x4Cu},
- {0x97u, 0x02u},
- {0x98u, 0x02u},
- {0x99u, 0x28u},
- {0x9Bu, 0x44u},
- {0x9Du, 0x40u},
- {0x9Eu, 0x0Au},
- {0xA0u, 0x2Cu},
- {0xA2u, 0x0Cu},
- {0xA3u, 0x40u},
- {0xA4u, 0x50u},
- {0xA5u, 0x40u},
- {0xA6u, 0x20u},
- {0xA7u, 0x96u},
- {0xAAu, 0x40u},
- {0xABu, 0x40u},
- {0xAEu, 0x09u},
- {0xAFu, 0x01u},
- {0xB0u, 0x04u},
- {0xB3u, 0x0Cu},
- {0xB7u, 0x40u},
- {0xC0u, 0xF3u},
- {0xC2u, 0x7Cu},
- {0xC4u, 0x3Bu},
- {0xCAu, 0xFBu},
- {0xCCu, 0xE9u},
- {0xCEu, 0xB9u},
- {0xD6u, 0x1Cu},
- {0xD8u, 0x0Cu},
- {0xE0u, 0x02u},
- {0xE2u, 0x04u},
- {0xE4u, 0x4Au},
- {0xE6u, 0x20u},
- {0xE8u, 0xA0u},
+ {0x3Eu, 0x80u},
+ {0x49u, 0x10u},
+ {0x4Au, 0x08u},
+ {0x58u, 0x18u},
+ {0x59u, 0x80u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x08u},
+ {0x5Eu, 0x81u},
+ {0x5Fu, 0x10u},
+ {0x63u, 0x0Au},
+ {0x65u, 0x40u},
+ {0x69u, 0x40u},
+ {0x6Cu, 0x22u},
+ {0x6Fu, 0x18u},
+ {0x80u, 0x04u},
+ {0x81u, 0x10u},
+ {0x84u, 0x04u},
+ {0x85u, 0x04u},
+ {0x8Eu, 0x04u},
+ {0x91u, 0xA3u},
+ {0x92u, 0x49u},
+ {0x93u, 0x88u},
+ {0x94u, 0x20u},
+ {0x95u, 0x14u},
+ {0x96u, 0x82u},
+ {0x98u, 0x80u},
+ {0x99u, 0x82u},
+ {0x9Au, 0xA0u},
+ {0x9Bu, 0x0Cu},
+ {0x9Du, 0x08u},
+ {0x9Eu, 0x04u},
+ {0x9Fu, 0x11u},
+ {0xA0u, 0x89u},
+ {0xA1u, 0x04u},
+ {0xA2u, 0x51u},
+ {0xA4u, 0x70u},
+ {0xA5u, 0x01u},
+ {0xA6u, 0x0Au},
+ {0xA7u, 0x83u},
+ {0xA8u, 0x82u},
+ {0xADu, 0x60u},
+ {0xAFu, 0x02u},
+ {0xB5u, 0x41u},
+ {0xB6u, 0x09u},
+ {0xC0u, 0xFCu},
+ {0xC2u, 0xEFu},
+ {0xC4u, 0x3Au},
+ {0xCAu, 0x34u},
+ {0xCCu, 0x47u},
+ {0xCEu, 0x1Du},
+ {0xD6u, 0xFCu},
+ {0xD8u, 0x1Cu},
+ {0xE0u, 0x48u},
+ {0xE4u, 0x03u},
+ {0xE8u, 0x10u},
{0xEAu, 0x04u},
- {0xECu, 0xC2u},
+ {0xECu, 0x10u},
{0xEEu, 0x09u},
- {0x04u, 0x80u},
- {0x05u, 0x02u},
- {0x07u, 0x01u},
- {0x08u, 0x24u},
- {0x0Au, 0x09u},
- {0x0Cu, 0x40u},
- {0x0Eu, 0x80u},
- {0x12u, 0x18u},
- {0x15u, 0x06u},
- {0x1Au, 0x03u},
- {0x1Cu, 0x40u},
- {0x21u, 0x01u},
- {0x22u, 0x20u},
- {0x23u, 0x04u},
- {0x25u, 0x01u},
- {0x26u, 0x04u},
- {0x27u, 0x02u},
- {0x28u, 0x24u},
- {0x2Au, 0x12u},
- {0x2Eu, 0x24u},
- {0x30u, 0x38u},
- {0x33u, 0x07u},
- {0x34u, 0x07u},
- {0x36u, 0xC0u},
- {0x39u, 0x08u},
- {0x3Eu, 0x40u},
+ {0x01u, 0x02u},
+ {0x02u, 0xFFu},
+ {0x05u, 0x20u},
+ {0x06u, 0xFFu},
+ {0x07u, 0x40u},
+ {0x08u, 0x0Fu},
+ {0x09u, 0x01u},
+ {0x0Au, 0xF0u},
+ {0x0Bu, 0x6Eu},
+ {0x11u, 0x64u},
+ {0x14u, 0x33u},
+ {0x15u, 0x03u},
+ {0x16u, 0xCCu},
+ {0x17u, 0x74u},
+ {0x1Bu, 0x01u},
+ {0x1Cu, 0xFFu},
+ {0x20u, 0xFFu},
+ {0x21u, 0x78u},
+ {0x23u, 0x03u},
+ {0x26u, 0xFFu},
+ {0x27u, 0x7Fu},
+ {0x28u, 0x69u},
+ {0x29u, 0x20u},
+ {0x2Au, 0x96u},
+ {0x2Bu, 0x40u},
+ {0x2Cu, 0x55u},
+ {0x2Eu, 0xAAu},
+ {0x2Fu, 0x08u},
+ {0x32u, 0xFFu},
+ {0x33u, 0x1Fu},
+ {0x37u, 0x60u},
+ {0x3Au, 0x08u},
+ {0x3Bu, 0x80u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x02u},
+ {0x5Cu, 0x22u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x81u, 0x40u},
- {0x83u, 0x80u},
- {0x84u, 0x0Fu},
- {0x85u, 0xCAu},
- {0x86u, 0xF0u},
- {0x87u, 0x15u},
- {0x89u, 0x0Bu},
- {0x8Au, 0xFFu},
- {0x8Bu, 0xF4u},
- {0x8Cu, 0x21u},
- {0x8Du, 0x11u},
- {0x8Eu, 0x12u},
- {0x8Fu, 0xECu},
- {0x94u, 0x84u},
- {0x95u, 0x01u},
- {0x96u, 0x48u},
- {0x99u, 0x40u},
- {0x9Au, 0xFFu},
- {0x9Bu, 0x80u},
- {0x9Cu, 0xFFu},
- {0xA0u, 0x11u},
- {0xA1u, 0xE0u},
- {0xA2u, 0x22u},
- {0xA4u, 0x44u},
- {0xA5u, 0x06u},
- {0xA6u, 0x88u},
- {0xABu, 0x10u},
- {0xACu, 0x33u},
- {0xAEu, 0xCCu},
- {0xAFu, 0xFFu},
- {0xB3u, 0x3Fu},
+ {0x80u, 0x0Fu},
+ {0x81u, 0x0Fu},
+ {0x82u, 0xF0u},
+ {0x83u, 0xF0u},
+ {0x84u, 0x44u},
+ {0x86u, 0x88u},
+ {0x8Bu, 0xFFu},
+ {0x8Cu, 0x33u},
+ {0x8Du, 0x33u},
+ {0x8Eu, 0xCCu},
+ {0x8Fu, 0xCCu},
+ {0x91u, 0xFFu},
+ {0x92u, 0xFFu},
+ {0x96u, 0xFFu},
+ {0x97u, 0xFFu},
+ {0x98u, 0x11u},
+ {0x9Au, 0x22u},
+ {0x9Cu, 0x21u},
+ {0x9Du, 0xFFu},
+ {0x9Eu, 0x12u},
+ {0xA7u, 0xFFu},
+ {0xA8u, 0x84u},
+ {0xA9u, 0x69u},
+ {0xAAu, 0x48u},
+ {0xABu, 0x96u},
+ {0xACu, 0xFFu},
+ {0xADu, 0x55u},
+ {0xAFu, 0xAAu},
+ {0xB1u, 0xFFu},
{0xB4u, 0xFFu},
- {0xB7u, 0xC0u},
- {0xBBu, 0x80u},
+ {0xBBu, 0x02u},
{0xBEu, 0x10u},
+ {0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
{0xDCu, 0x20u},
+ {0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x20u},
- {0x01u, 0x44u},
- {0x04u, 0x28u},
- {0x06u, 0x02u},
- {0x08u, 0x40u},
- {0x0Au, 0x84u},
- {0x0Bu, 0x02u},
- {0x0Fu, 0x2Au},
- {0x11u, 0x80u},
- {0x12u, 0x08u},
- {0x13u, 0x09u},
- {0x14u, 0x40u},
- {0x15u, 0x44u},
- {0x1Au, 0x86u},
- {0x1Fu, 0x10u},
- {0x21u, 0x08u},
- {0x24u, 0x03u},
+ {0x01u, 0x04u},
+ {0x03u, 0x82u},
+ {0x04u, 0x10u},
+ {0x05u, 0x05u},
+ {0x08u, 0x28u},
+ {0x09u, 0x01u},
+ {0x0Au, 0x02u},
+ {0x0Du, 0x80u},
+ {0x0Fu, 0x20u},
+ {0x10u, 0x02u},
+ {0x11u, 0x10u},
+ {0x14u, 0x06u},
+ {0x16u, 0x20u},
+ {0x17u, 0x01u},
+ {0x1Au, 0x04u},
+ {0x1Cu, 0x10u},
+ {0x1Eu, 0x20u},
+ {0x21u, 0x01u},
{0x25u, 0x04u},
- {0x26u, 0x08u},
- {0x2Au, 0x08u},
- {0x2Bu, 0x40u},
- {0x2Du, 0x28u},
- {0x2Fu, 0xA2u},
- {0x30u, 0x08u},
- {0x31u, 0x08u},
- {0x36u, 0x24u},
- {0x39u, 0x08u},
- {0x3Cu, 0x21u},
- {0x3Du, 0x88u},
- {0x5Au, 0x44u},
- {0x5Bu, 0x04u},
- {0x5Du, 0x88u},
- {0x5Eu, 0x20u},
- {0x5Fu, 0x02u},
- {0x60u, 0x02u},
- {0x65u, 0x40u},
- {0x6Cu, 0x32u},
- {0x6Eu, 0x18u},
- {0x80u, 0x01u},
- {0x81u, 0xA0u},
- {0x83u, 0x03u},
- {0x84u, 0x42u},
- {0x86u, 0x10u},
+ {0x26u, 0x04u},
+ {0x27u, 0x02u},
+ {0x29u, 0x04u},
+ {0x2Au, 0x0Cu},
+ {0x2Bu, 0x05u},
+ {0x2Du, 0x60u},
+ {0x2Eu, 0x08u},
+ {0x2Fu, 0x40u},
+ {0x31u, 0x80u},
+ {0x32u, 0x08u},
+ {0x33u, 0x01u},
+ {0x36u, 0x04u},
+ {0x37u, 0x11u},
+ {0x39u, 0x02u},
+ {0x3Au, 0x60u},
+ {0x3Eu, 0x03u},
+ {0x3Fu, 0x18u},
+ {0x40u, 0x08u},
+ {0x43u, 0x10u},
+ {0x4Au, 0x08u},
+ {0x4Bu, 0x10u},
+ {0x59u, 0x40u},
+ {0x5Au, 0x20u},
+ {0x5Cu, 0x40u},
+ {0x5Eu, 0x10u},
+ {0x62u, 0x40u},
+ {0x63u, 0x08u},
+ {0x66u, 0x80u},
+ {0x67u, 0x08u},
+ {0x80u, 0x40u},
+ {0x82u, 0x50u},
+ {0x88u, 0x20u},
+ {0x89u, 0x80u},
+ {0x8Au, 0x40u},
+ {0x8Du, 0x04u},
+ {0x8Eu, 0x31u},
+ {0x8Fu, 0x10u},
+ {0x91u, 0x61u},
+ {0x92u, 0x08u},
+ {0x93u, 0x80u},
+ {0x94u, 0x20u},
+ {0x96u, 0x84u},
+ {0x97u, 0x08u},
+ {0x98u, 0x06u},
+ {0x99u, 0x02u},
+ {0x9Au, 0x02u},
+ {0x9Bu, 0x0Cu},
+ {0x9Du, 0x08u},
+ {0x9Eu, 0xC5u},
+ {0x9Fu, 0x01u},
+ {0xA0u, 0x89u},
+ {0xA1u, 0x80u},
+ {0xA4u, 0x70u},
+ {0xA5u, 0x04u},
+ {0xA6u, 0x02u},
+ {0xAAu, 0x24u},
+ {0xACu, 0x80u},
+ {0xADu, 0x08u},
+ {0xB1u, 0x10u},
+ {0xB2u, 0x40u},
+ {0xB4u, 0x12u},
+ {0xB5u, 0x40u},
+ {0xB7u, 0x40u},
+ {0xC0u, 0x7Du},
+ {0xC2u, 0xAFu},
+ {0xC4u, 0xF3u},
+ {0xCAu, 0xFEu},
+ {0xCCu, 0xEBu},
+ {0xCEu, 0xEDu},
+ {0xD6u, 0x3Cu},
+ {0xD8u, 0x3Cu},
+ {0xE0u, 0xB0u},
+ {0xE2u, 0x01u},
+ {0xE6u, 0x40u},
+ {0xE8u, 0x40u},
+ {0xEAu, 0xA0u},
+ {0xECu, 0x20u},
+ {0xEEu, 0x40u},
+ {0x01u, 0x20u},
+ {0x03u, 0x10u},
+ {0x04u, 0x02u},
+ {0x08u, 0x02u},
+ {0x09u, 0x04u},
+ {0x0Bu, 0x02u},
+ {0x0Cu, 0x02u},
+ {0x0Fu, 0x18u},
+ {0x11u, 0x20u},
+ {0x12u, 0x01u},
+ {0x13u, 0x08u},
+ {0x17u, 0x20u},
+ {0x18u, 0x02u},
+ {0x19u, 0x02u},
+ {0x1Bu, 0x04u},
+ {0x1Du, 0x04u},
+ {0x1Fu, 0x02u},
+ {0x23u, 0x20u},
+ {0x29u, 0x04u},
+ {0x2Bu, 0x02u},
+ {0x2Du, 0x04u},
+ {0x2Fu, 0x03u},
+ {0x32u, 0x02u},
+ {0x33u, 0x01u},
+ {0x34u, 0x01u},
+ {0x35u, 0x06u},
+ {0x37u, 0x38u},
+ {0x3Bu, 0x20u},
+ {0x3Eu, 0x04u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Cu, 0x22u},
+ {0x5Fu, 0x01u},
+ {0x80u, 0x40u},
+ {0x82u, 0x80u},
+ {0x84u, 0x40u},
+ {0x86u, 0x80u},
+ {0x87u, 0x3Fu},
+ {0x88u, 0x06u},
+ {0x89u, 0x10u},
{0x8Bu, 0x20u},
- {0x8Eu, 0x18u},
- {0xC0u, 0xE7u},
- {0xC2u, 0xEBu},
- {0xC4u, 0xBFu},
- {0xCAu, 0xF3u},
- {0xCCu, 0x62u},
- {0xCEu, 0xF2u},
- {0xD6u, 0xF8u},
- {0xD8u, 0x18u},
- {0xE0u, 0x80u},
- {0xE6u, 0x50u},
- {0x80u, 0x10u},
- {0x84u, 0x01u},
- {0x88u, 0xA2u},
- {0x8Au, 0x08u},
- {0x8Cu, 0x07u},
- {0x8Eu, 0xD8u},
- {0x90u, 0x01u},
- {0x96u, 0x40u},
+ {0x8Eu, 0x10u},
+ {0x8Fu, 0x3Fu},
+ {0x90u, 0x0Bu},
+ {0x91u, 0x3Fu},
+ {0x92u, 0xF4u},
+ {0x95u, 0x01u},
+ {0x97u, 0x02u},
+ {0x98u, 0x01u},
{0x99u, 0x01u},
- {0x9Cu, 0x08u},
- {0x9Eu, 0x61u},
- {0xA0u, 0x01u},
- {0xA4u, 0x01u},
- {0xA5u, 0x01u},
- {0xA8u, 0x04u},
- {0xACu, 0x01u},
- {0xB2u, 0xE0u},
- {0xB3u, 0x01u},
- {0xB4u, 0x3Fu},
- {0xB8u, 0x20u},
- {0xB9u, 0x08u},
- {0xBEu, 0x10u},
+ {0x9Bu, 0x02u},
+ {0x9Cu, 0xCAu},
+ {0x9Du, 0x04u},
+ {0x9Eu, 0x15u},
+ {0x9Fu, 0x08u},
+ {0xA0u, 0xE0u},
+ {0xA1u, 0x3Fu},
+ {0xA7u, 0x3Fu},
+ {0xA9u, 0x10u},
+ {0xAAu, 0xFFu},
+ {0xABu, 0x20u},
+ {0xACu, 0x11u},
+ {0xADu, 0x04u},
+ {0xAEu, 0xECu},
+ {0xAFu, 0x08u},
+ {0xB3u, 0x03u},
+ {0xB4u, 0xC0u},
+ {0xB5u, 0x30u},
+ {0xB6u, 0x3Fu},
+ {0xB7u, 0x0Cu},
+ {0xBAu, 0x20u},
+ {0xBBu, 0xA8u},
+ {0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
- {0xDCu, 0x11u},
+ {0xDBu, 0x04u},
+ {0xDCu, 0x22u},
+ {0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x04u},
- {0x01u, 0x01u},
- {0x03u, 0x01u},
- {0x04u, 0x88u},
- {0x05u, 0x11u},
- {0x07u, 0x20u},
- {0x08u, 0x08u},
+ {0x00u, 0xA0u},
+ {0x01u, 0x08u},
+ {0x04u, 0x04u},
+ {0x05u, 0x20u},
+ {0x06u, 0x42u},
+ {0x07u, 0x04u},
{0x0Au, 0x84u},
- {0x0Bu, 0x01u},
- {0x0Du, 0x41u},
- {0x0Eu, 0x10u},
- {0x0Fu, 0x02u},
- {0x12u, 0x01u},
- {0x13u, 0x28u},
- {0x15u, 0x08u},
- {0x16u, 0x02u},
- {0x17u, 0x11u},
- {0x18u, 0xC8u},
- {0x1Au, 0x82u},
- {0x1Bu, 0x08u},
- {0x1Eu, 0x10u},
- {0x1Fu, 0x10u},
- {0x21u, 0x02u},
+ {0x0Cu, 0x20u},
+ {0x0Du, 0x80u},
+ {0x0Fu, 0x80u},
+ {0x16u, 0x0Du},
+ {0x17u, 0x01u},
+ {0x19u, 0x10u},
+ {0x1Au, 0x20u},
+ {0x1Cu, 0x04u},
+ {0x1Du, 0x80u},
+ {0x1Fu, 0x50u},
+ {0x20u, 0x12u},
+ {0x21u, 0x60u},
+ {0x22u, 0x04u},
+ {0x23u, 0x08u},
+ {0x25u, 0x10u},
+ {0x26u, 0x64u},
{0x27u, 0x10u},
+ {0x29u, 0x10u},
+ {0x2Au, 0x81u},
+ {0x2Cu, 0x01u},
+ {0x2Eu, 0x08u},
+ {0x2Fu, 0x44u},
+ {0x30u, 0x02u},
+ {0x31u, 0x28u},
+ {0x32u, 0x40u},
+ {0x34u, 0x04u},
+ {0x36u, 0x40u},
+ {0x37u, 0x11u},
+ {0x38u, 0x10u},
+ {0x39u, 0x81u},
+ {0x3Du, 0x28u},
+ {0x3Fu, 0x80u},
+ {0x5Cu, 0x40u},
+ {0x5Fu, 0x20u},
+ {0x64u, 0x07u},
+ {0x7Du, 0x01u},
+ {0x7Fu, 0x40u},
+ {0x81u, 0x20u},
+ {0x82u, 0x10u},
+ {0x83u, 0x20u},
+ {0x84u, 0x08u},
+ {0x86u, 0x02u},
+ {0x87u, 0x50u},
+ {0x89u, 0x02u},
+ {0x8Cu, 0x40u},
+ {0x8Eu, 0x02u},
+ {0xC0u, 0xF7u},
+ {0xC2u, 0xDAu},
+ {0xC4u, 0xD0u},
+ {0xCAu, 0xFDu},
+ {0xCCu, 0xFFu},
+ {0xCEu, 0x7Du},
+ {0xD6u, 0x30u},
+ {0xD8u, 0x30u},
+ {0xE0u, 0x80u},
+ {0xE2u, 0x01u},
+ {0xE4u, 0x04u},
+ {0xE6u, 0x10u},
+ {0x89u, 0x07u},
+ {0x97u, 0x07u},
+ {0x98u, 0x01u},
+ {0x99u, 0x01u},
+ {0x9Bu, 0x18u},
+ {0x9Fu, 0x08u},
+ {0xABu, 0x2Au},
+ {0xADu, 0x34u},
+ {0xB0u, 0x01u},
+ {0xB5u, 0x07u},
+ {0xB7u, 0x38u},
+ {0xBEu, 0x01u},
+ {0xBFu, 0x10u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDCu, 0x10u},
+ {0xDFu, 0x01u},
+ {0x01u, 0xA0u},
+ {0x03u, 0x50u},
+ {0x0Au, 0x41u},
+ {0x0Bu, 0x14u},
+ {0x0Cu, 0x03u},
+ {0x0Fu, 0x08u},
+ {0x11u, 0x40u},
+ {0x12u, 0x60u},
+ {0x13u, 0x20u},
+ {0x19u, 0x80u},
+ {0x1Bu, 0x01u},
+ {0x1Fu, 0x02u},
+ {0x23u, 0x10u},
+ {0x26u, 0x40u},
+ {0x27u, 0x08u},
+ {0x29u, 0x24u},
+ {0x2Au, 0x42u},
{0x2Bu, 0x01u},
- {0x2Fu, 0x10u},
- {0x31u, 0x02u},
- {0x36u, 0x10u},
- {0x38u, 0x44u},
- {0x40u, 0x40u},
- {0x41u, 0x40u},
- {0x43u, 0x08u},
- {0x48u, 0x01u},
- {0x49u, 0x15u},
- {0x4Au, 0x80u},
- {0x51u, 0x28u},
- {0x52u, 0x01u},
- {0x61u, 0x02u},
- {0x68u, 0x80u},
- {0x69u, 0x0Bu},
- {0x6Au, 0x4Cu},
- {0x6Bu, 0x09u},
- {0x72u, 0x02u},
- {0x73u, 0x01u},
- {0x80u, 0x40u},
- {0x84u, 0x01u},
- {0x8Au, 0x80u},
- {0x8Bu, 0x10u},
- {0x8Eu, 0x10u},
- {0x90u, 0x04u},
- {0x93u, 0x10u},
- {0x94u, 0xC8u},
+ {0x2Du, 0x20u},
+ {0x2Eu, 0x40u},
+ {0x31u, 0x08u},
+ {0x33u, 0x51u},
+ {0x36u, 0x48u},
+ {0x37u, 0x20u},
+ {0x38u, 0x88u},
+ {0x39u, 0x10u},
+ {0x3Bu, 0x04u},
+ {0x3Cu, 0x20u},
+ {0x41u, 0x08u},
+ {0x42u, 0x44u},
+ {0x49u, 0x64u},
+ {0x4Au, 0xA0u},
+ {0x4Bu, 0x02u},
+ {0x51u, 0x04u},
+ {0x52u, 0x12u},
+ {0x61u, 0x10u},
+ {0x68u, 0x62u},
+ {0x69u, 0x02u},
+ {0x6Au, 0x20u},
+ {0x6Bu, 0x04u},
+ {0x71u, 0x80u},
+ {0x79u, 0x02u},
+ {0x7Bu, 0x40u},
+ {0x83u, 0x0Cu},
+ {0x86u, 0x44u},
+ {0x8Au, 0xAAu},
+ {0x8Fu, 0x02u},
+ {0x90u, 0x88u},
+ {0x91u, 0x50u},
+ {0x92u, 0x41u},
{0x95u, 0x0Au},
- {0x96u, 0x4Au},
- {0x97u, 0x01u},
- {0x98u, 0x08u},
- {0x99u, 0x10u},
- {0x9Du, 0x05u},
- {0x9Eu, 0x03u},
- {0x9Fu, 0x19u},
- {0xA2u, 0x10u},
- {0xA3u, 0x01u},
- {0xA4u, 0x80u},
- {0xA5u, 0x28u},
- {0xA9u, 0x05u},
- {0xACu, 0x80u},
- {0xB0u, 0x08u},
- {0xB1u, 0x10u},
- {0xB2u, 0x08u},
- {0xB3u, 0x41u},
- {0xB6u, 0x01u},
- {0xC0u, 0xFDu},
- {0xC2u, 0xBFu},
- {0xC4u, 0xF7u},
- {0xCAu, 0x48u},
- {0xCCu, 0x21u},
- {0xCEu, 0x0Au},
- {0xD0u, 0x0Bu},
+ {0x96u, 0x20u},
+ {0x97u, 0x02u},
+ {0x99u, 0x70u},
+ {0x9Au, 0x02u},
+ {0x9Bu, 0x71u},
+ {0x9Cu, 0x01u},
+ {0x9Eu, 0x10u},
+ {0x9Fu, 0x04u},
+ {0xA0u, 0x10u},
+ {0xA1u, 0x08u},
+ {0xA4u, 0x62u},
+ {0xA5u, 0x80u},
+ {0xA7u, 0x40u},
+ {0xACu, 0x20u},
+ {0xADu, 0x84u},
+ {0xB3u, 0x44u},
+ {0xB6u, 0x20u},
+ {0xC0u, 0x0Fu},
+ {0xC2u, 0x4Fu},
+ {0xC4u, 0x0Fu},
+ {0xCAu, 0x3Fu},
+ {0xCCu, 0x7Fu},
+ {0xCEu, 0x2Eu},
+ {0xD0u, 0x07u},
{0xD2u, 0x0Cu},
- {0xD8u, 0x01u},
- {0xE0u, 0x05u},
- {0xE2u, 0x10u},
- {0xE6u, 0x50u},
- {0x02u, 0x9Fu},
- {0x04u, 0x80u},
- {0x05u, 0x02u},
- {0x08u, 0xC0u},
- {0x0Au, 0x08u},
- {0x0Bu, 0x01u},
- {0x0Cu, 0x1Fu},
- {0x0Eu, 0x20u},
- {0x10u, 0xC0u},
- {0x12u, 0x02u},
- {0x14u, 0x7Fu},
- {0x16u, 0x80u},
- {0x1Du, 0x04u},
- {0x1Eu, 0xFFu},
- {0x20u, 0x90u},
- {0x22u, 0x40u},
- {0x24u, 0xC0u},
- {0x26u, 0x04u},
- {0x2Au, 0x60u},
- {0x2Cu, 0xC0u},
- {0x2Eu, 0x01u},
- {0x32u, 0xFFu},
- {0x33u, 0x04u},
+ {0xD8u, 0x04u},
+ {0xE6u, 0x44u},
+ {0xEAu, 0x10u},
+ {0xECu, 0x08u},
+ {0x00u, 0x1Du},
+ {0x04u, 0x1Du},
+ {0x08u, 0x02u},
+ {0x0Au, 0x04u},
+ {0x10u, 0x02u},
+ {0x12u, 0x08u},
+ {0x14u, 0x02u},
+ {0x15u, 0x02u},
+ {0x16u, 0x0Du},
+ {0x18u, 0x01u},
+ {0x1Au, 0x02u},
+ {0x20u, 0x0Du},
+ {0x22u, 0x10u},
+ {0x26u, 0x10u},
+ {0x28u, 0x1Du},
+ {0x29u, 0x01u},
+ {0x2Cu, 0x1Du},
+ {0x31u, 0x02u},
+ {0x32u, 0x0Fu},
+ {0x34u, 0x10u},
{0x35u, 0x01u},
- {0x37u, 0x02u},
- {0x39u, 0x02u},
- {0x3Eu, 0x04u},
- {0x3Fu, 0x45u},
+ {0x3Au, 0x08u},
+ {0x3Eu, 0x10u},
+ {0x54u, 0x40u},
+ {0x56u, 0x04u},
{0x58u, 0x04u},
{0x59u, 0x04u},
- {0x5Cu, 0x20u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x91u},
+ {0x5Du, 0x10u},
{0x5Fu, 0x01u},
- {0x81u, 0x9Cu},
- {0x84u, 0x01u},
- {0x85u, 0x61u},
- {0x86u, 0x5Eu},
- {0x87u, 0x1Eu},
- {0x88u, 0x39u},
- {0x89u, 0x10u},
- {0x8Au, 0x06u},
- {0x8Bu, 0x8Cu},
- {0x8Cu, 0x77u},
- {0x8Du, 0x8Cu},
- {0x8Eu, 0x08u},
- {0x8Fu, 0x10u},
- {0x90u, 0x46u},
- {0x91u, 0xD1u},
- {0x92u, 0x80u},
- {0x93u, 0x22u},
- {0x95u, 0x30u},
- {0x96u, 0x80u},
- {0x97u, 0x8Fu},
- {0x98u, 0xC2u},
- {0x99u, 0x94u},
- {0x9Au, 0x04u},
- {0x9Bu, 0x08u},
- {0x9Cu, 0xC6u},
- {0x9Du, 0xA4u},
- {0x9Fu, 0x10u},
- {0xA0u, 0xC6u},
- {0xA1u, 0x08u},
- {0xA3u, 0x40u},
- {0xA4u, 0x80u},
- {0xA6u, 0x46u},
- {0xA8u, 0x42u},
- {0xACu, 0x04u},
- {0xADu, 0x9Cu},
- {0xAEu, 0x20u},
+ {0x80u, 0x11u},
+ {0x81u, 0xC6u},
+ {0x82u, 0x62u},
+ {0x84u, 0x52u},
+ {0x85u, 0x01u},
+ {0x86u, 0x28u},
+ {0x87u, 0x5Eu},
+ {0x8Cu, 0x02u},
+ {0x8Du, 0x39u},
+ {0x8Eu, 0x0Du},
+ {0x8Fu, 0x06u},
+ {0x90u, 0x0Du},
+ {0x91u, 0x77u},
+ {0x93u, 0x08u},
+ {0x94u, 0x0Du},
+ {0x95u, 0x80u},
+ {0x97u, 0x46u},
+ {0x98u, 0x40u},
+ {0x99u, 0xC2u},
+ {0x9Au, 0x30u},
+ {0x9Bu, 0x04u},
+ {0x9Cu, 0x0Du},
+ {0x9Du, 0xC6u},
+ {0xA0u, 0x0Du},
+ {0xA3u, 0x80u},
+ {0xA4u, 0x0Du},
+ {0xA5u, 0x04u},
+ {0xA7u, 0x20u},
+ {0xA9u, 0x42u},
+ {0xACu, 0x32u},
+ {0xADu, 0x46u},
+ {0xAEu, 0x44u},
+ {0xAFu, 0x80u},
{0xB0u, 0x0Fu},
{0xB1u, 0x0Fu},
- {0xB2u, 0x80u},
- {0xB3u, 0xC1u},
+ {0xB3u, 0x80u},
{0xB4u, 0x70u},
- {0xB7u, 0x30u},
- {0xB8u, 0x02u},
- {0xBAu, 0x30u},
- {0xBBu, 0x8Cu},
- {0xBEu, 0x04u},
+ {0xB5u, 0x70u},
+ {0xB7u, 0x01u},
+ {0xB9u, 0x02u},
+ {0xBAu, 0x22u},
+ {0xBBu, 0x30u},
+ {0xBFu, 0x44u},
{0xD4u, 0x40u},
{0xD6u, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x01u},
- {0xDDu, 0x10u},
{0xDFu, 0x01u},
{0x00u, 0x44u},
- {0x01u, 0x10u},
- {0x04u, 0x88u},
- {0x05u, 0x01u},
- {0x06u, 0x08u},
- {0x07u, 0x28u},
- {0x08u, 0x04u},
- {0x09u, 0x08u},
- {0x0Au, 0x48u},
- {0x0Bu, 0x01u},
- {0x0Du, 0x01u},
- {0x0Fu, 0x22u},
- {0x10u, 0x80u},
- {0x12u, 0x03u},
- {0x13u, 0x28u},
- {0x15u, 0x08u},
- {0x16u, 0x22u},
- {0x17u, 0x11u},
- {0x18u, 0x14u},
+ {0x02u, 0x40u},
+ {0x05u, 0x20u},
+ {0x07u, 0x50u},
+ {0x08u, 0x01u},
+ {0x09u, 0x80u},
+ {0x0Au, 0x28u},
+ {0x0Cu, 0x10u},
+ {0x0Eu, 0x60u},
+ {0x10u, 0x20u},
+ {0x11u, 0x01u},
+ {0x13u, 0x40u},
+ {0x15u, 0x18u},
+ {0x16u, 0x02u},
+ {0x17u, 0x01u},
+ {0x18u, 0x40u},
{0x19u, 0x10u},
- {0x1Bu, 0x11u},
+ {0x1Au, 0x08u},
{0x1Eu, 0x20u},
- {0x20u, 0x80u},
- {0x21u, 0x02u},
- {0x22u, 0x48u},
- {0x23u, 0x40u},
- {0x25u, 0x05u},
- {0x26u, 0x40u},
- {0x27u, 0x04u},
- {0x29u, 0x42u},
+ {0x1Fu, 0x10u},
+ {0x20u, 0x04u},
+ {0x22u, 0x88u},
+ {0x23u, 0x44u},
+ {0x26u, 0x21u},
+ {0x28u, 0x01u},
+ {0x2Au, 0x04u},
+ {0x2Bu, 0x84u},
+ {0x2Fu, 0x04u},
{0x30u, 0x20u},
- {0x31u, 0x02u},
- {0x32u, 0x48u},
- {0x37u, 0x80u},
- {0x39u, 0x61u},
- {0x3Bu, 0x04u},
- {0x3Du, 0x20u},
- {0x3Eu, 0x04u},
- {0x60u, 0x90u},
+ {0x31u, 0x80u},
+ {0x33u, 0x06u},
+ {0x37u, 0x08u},
+ {0x38u, 0x04u},
+ {0x39u, 0x03u},
+ {0x3Bu, 0x40u},
+ {0x40u, 0x02u},
+ {0x43u, 0x80u},
+ {0x44u, 0x10u},
+ {0x45u, 0x08u},
+ {0x60u, 0x02u},
{0x61u, 0x20u},
- {0x62u, 0x40u},
- {0x83u, 0x80u},
- {0x84u, 0x05u},
- {0x86u, 0x40u},
- {0x8Au, 0x40u},
- {0x8Cu, 0x10u},
- {0x8Eu, 0x10u},
- {0x8Fu, 0x10u},
- {0x90u, 0x20u},
- {0x91u, 0x61u},
- {0x92u, 0x24u},
- {0x93u, 0x14u},
- {0x94u, 0x80u},
+ {0x62u, 0x0Au},
+ {0x65u, 0x81u},
+ {0x66u, 0x10u},
+ {0x67u, 0x20u},
+ {0x81u, 0x03u},
+ {0x82u, 0x01u},
+ {0x86u, 0x02u},
+ {0x90u, 0x88u},
+ {0x91u, 0x50u},
+ {0x92u, 0x41u},
+ {0x93u, 0x08u},
+ {0x94u, 0x04u},
{0x95u, 0x02u},
- {0x96u, 0x82u},
- {0x98u, 0x01u},
- {0x99u, 0x42u},
- {0x9Du, 0x14u},
- {0x9Eu, 0x2Au},
- {0x9Fu, 0x05u},
- {0xA0u, 0x20u},
- {0xA1u, 0x10u},
- {0xA2u, 0x01u},
- {0xA4u, 0x40u},
- {0xA5u, 0x02u},
- {0xA6u, 0x0Au},
- {0xA7u, 0x01u},
- {0xA8u, 0x08u},
- {0xAAu, 0x12u},
- {0xAEu, 0x10u},
- {0xAFu, 0x04u},
- {0xB6u, 0x01u},
- {0xC0u, 0xF7u},
- {0xC2u, 0xBFu},
- {0xC4u, 0xFFu},
- {0xCAu, 0x09u},
- {0xCCu, 0x1Fu},
- {0xCEu, 0x6Fu},
- {0xD8u, 0x0Fu},
- {0xE0u, 0x02u},
- {0xE2u, 0x21u},
- {0xECu, 0x01u},
- {0xEEu, 0x4Cu},
- {0x00u, 0x11u},
- {0x02u, 0x22u},
- {0x07u, 0xFFu},
- {0x08u, 0x0Fu},
- {0x09u, 0x48u},
- {0x0Au, 0xF0u},
- {0x0Bu, 0x84u},
- {0x0Cu, 0x12u},
- {0x0Du, 0x11u},
- {0x0Eu, 0x21u},
- {0x0Fu, 0x22u},
- {0x10u, 0xFFu},
- {0x11u, 0x33u},
- {0x13u, 0xCCu},
- {0x14u, 0x48u},
- {0x16u, 0x84u},
+ {0x97u, 0x46u},
+ {0x98u, 0x20u},
+ {0x99u, 0x62u},
+ {0x9Au, 0x46u},
+ {0x9Bu, 0x79u},
+ {0x9Fu, 0x04u},
+ {0xA0u, 0x10u},
+ {0xA1u, 0x28u},
+ {0xA3u, 0x86u},
+ {0xA4u, 0x62u},
+ {0xA5u, 0x80u},
+ {0xA6u, 0x80u},
+ {0xA7u, 0x40u},
+ {0xB1u, 0xA0u},
+ {0xB3u, 0x04u},
+ {0xB4u, 0x40u},
+ {0xB7u, 0x08u},
+ {0xC0u, 0x7Du},
+ {0xC2u, 0x7Fu},
+ {0xC4u, 0xFDu},
+ {0xCAu, 0x2Fu},
+ {0xCCu, 0x4Fu},
+ {0xCEu, 0x0Bu},
+ {0xD8u, 0xFFu},
+ {0xE2u, 0x01u},
+ {0xE4u, 0x04u},
+ {0xE6u, 0x32u},
+ {0xEAu, 0x08u},
+ {0xECu, 0x80u},
+ {0xEEu, 0x02u},
+ {0x01u, 0x96u},
+ {0x03u, 0x69u},
+ {0x05u, 0x33u},
+ {0x06u, 0x0Cu},
+ {0x07u, 0xCCu},
+ {0x08u, 0x04u},
+ {0x0Au, 0xA3u},
+ {0x0Bu, 0xFFu},
+ {0x0Du, 0xFFu},
+ {0x16u, 0x20u},
{0x17u, 0xFFu},
- {0x18u, 0xFFu},
- {0x1Fu, 0xFFu},
- {0x20u, 0x33u},
- {0x21u, 0x12u},
- {0x22u, 0xCCu},
- {0x23u, 0x21u},
- {0x24u, 0x44u},
- {0x25u, 0x44u},
- {0x26u, 0x88u},
- {0x27u, 0x88u},
- {0x29u, 0x0Fu},
- {0x2Au, 0xFFu},
- {0x2Bu, 0xF0u},
- {0x30u, 0xFFu},
- {0x33u, 0xFFu},
- {0x3Eu, 0x01u},
- {0x3Fu, 0x04u},
+ {0x1Au, 0x12u},
+ {0x1Bu, 0xFFu},
+ {0x1Du, 0x0Fu},
+ {0x1Eu, 0x01u},
+ {0x1Fu, 0xF0u},
+ {0x21u, 0xFFu},
+ {0x28u, 0xC8u},
+ {0x29u, 0x55u},
+ {0x2Au, 0x03u},
+ {0x2Bu, 0xAAu},
+ {0x2Cu, 0x01u},
+ {0x2Eu, 0x62u},
+ {0x31u, 0xFFu},
+ {0x32u, 0xE0u},
+ {0x34u, 0x0Fu},
+ {0x36u, 0x10u},
+ {0x3Bu, 0x02u},
{0x58u, 0x04u},
{0x59u, 0x04u},
- {0x5Bu, 0x04u},
+ {0x5Cu, 0x20u},
{0x5Fu, 0x01u},
- {0x80u, 0x55u},
- {0x81u, 0x0Fu},
- {0x82u, 0xAAu},
- {0x83u, 0xF0u},
- {0x84u, 0x33u},
- {0x86u, 0xCCu},
- {0x87u, 0xFFu},
- {0x89u, 0x33u},
- {0x8Bu, 0xCCu},
- {0x8Eu, 0xFFu},
- {0x90u, 0x0Fu},
- {0x92u, 0xF0u},
- {0x93u, 0xFFu},
- {0x95u, 0xFFu},
- {0x99u, 0x69u},
- {0x9Au, 0xFFu},
- {0x9Bu, 0x96u},
- {0x9Cu, 0xFFu},
+ {0x84u, 0x80u},
+ {0x85u, 0x44u},
+ {0x87u, 0x88u},
+ {0x89u, 0x48u},
+ {0x8Bu, 0x84u},
+ {0x8Cu, 0x4Du},
+ {0x8Du, 0x33u},
+ {0x8Eu, 0xB2u},
+ {0x8Fu, 0xCCu},
+ {0x91u, 0x12u},
+ {0x93u, 0x21u},
+ {0x98u, 0x40u},
+ {0x99u, 0x11u},
+ {0x9Bu, 0x22u},
+ {0x9Cu, 0x20u},
{0x9Du, 0xFFu},
- {0xA6u, 0xFFu},
- {0xA8u, 0xFFu},
- {0xABu, 0xFFu},
- {0xACu, 0x69u},
- {0xADu, 0x55u},
- {0xAEu, 0x96u},
- {0xAFu, 0xAAu},
- {0xB0u, 0xFFu},
- {0xB1u, 0xFFu},
- {0xBAu, 0x02u},
- {0xBBu, 0x02u},
+ {0x9Eu, 0x10u},
+ {0xA0u, 0x12u},
+ {0xA1u, 0x0Fu},
+ {0xA2u, 0x20u},
+ {0xA3u, 0xF0u},
+ {0xA4u, 0x05u},
+ {0xA6u, 0x08u},
+ {0xA7u, 0xFFu},
+ {0xA8u, 0x08u},
+ {0xAAu, 0x04u},
+ {0xADu, 0xFFu},
+ {0xB0u, 0x3Cu},
+ {0xB2u, 0xC0u},
+ {0xB3u, 0xFFu},
+ {0xB4u, 0x03u},
+ {0xB9u, 0x02u},
+ {0xBEu, 0x15u},
+ {0xBFu, 0x05u},
{0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x22u},
{0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x04u},
- {0x02u, 0x40u},
+ {0x01u, 0x44u},
{0x03u, 0x02u},
- {0x04u, 0x02u},
- {0x05u, 0x22u},
- {0x06u, 0x02u},
- {0x0Au, 0x81u},
- {0x0Bu, 0x08u},
- {0x0Eu, 0x80u},
- {0x0Fu, 0x28u},
- {0x12u, 0x19u},
- {0x14u, 0x04u},
- {0x15u, 0x04u},
- {0x17u, 0x01u},
- {0x19u, 0x01u},
+ {0x04u, 0x04u},
+ {0x05u, 0x20u},
+ {0x08u, 0x20u},
+ {0x0Au, 0x01u},
+ {0x0Du, 0x80u},
+ {0x0Eu, 0x18u},
+ {0x12u, 0x10u},
+ {0x13u, 0x21u},
+ {0x15u, 0x20u},
+ {0x16u, 0x02u},
+ {0x18u, 0x08u},
{0x1Au, 0x80u},
- {0x1Eu, 0x40u},
- {0x21u, 0x01u},
- {0x27u, 0x20u},
- {0x28u, 0x02u},
- {0x2Au, 0x10u},
- {0x2Du, 0x24u},
- {0x2Eu, 0x02u},
- {0x32u, 0x28u},
- {0x33u, 0x82u},
- {0x34u, 0x04u},
- {0x36u, 0xC4u},
- {0x37u, 0x01u},
- {0x39u, 0x02u},
- {0x3Bu, 0x18u},
- {0x3Cu, 0x40u},
- {0x3Du, 0x10u},
- {0x3Fu, 0x28u},
- {0x49u, 0x40u},
- {0x4Bu, 0x80u},
- {0x58u, 0x20u},
- {0x5Bu, 0x40u},
- {0x5Cu, 0x80u},
- {0x5Du, 0x01u},
- {0x5Eu, 0x24u},
- {0x60u, 0x08u},
- {0x61u, 0x50u},
- {0x67u, 0x02u},
- {0x80u, 0x08u},
- {0x86u, 0x04u},
- {0x8Cu, 0x40u},
- {0x8Du, 0x06u},
- {0x8Fu, 0x02u},
- {0x90u, 0x04u},
- {0x92u, 0x01u},
- {0x93u, 0x1Au},
- {0x94u, 0x22u},
- {0x95u, 0x0Eu},
- {0x96u, 0x40u},
- {0x98u, 0x12u},
- {0x99u, 0x20u},
- {0x9Au, 0x53u},
- {0x9Bu, 0x11u},
- {0x9Du, 0x51u},
- {0x9Eu, 0x0Cu},
- {0x9Fu, 0x20u},
- {0xA0u, 0x08u},
- {0xA2u, 0xACu},
- {0xA3u, 0xC4u},
- {0xA4u, 0x82u},
- {0xA5u, 0x2Au},
- {0xA6u, 0x41u},
- {0xA7u, 0x10u},
- {0xAAu, 0x40u},
- {0xABu, 0x80u},
- {0xB1u, 0x40u},
- {0xB2u, 0x10u},
- {0xB7u, 0x21u},
- {0xC0u, 0xDDu},
- {0xC2u, 0x7Bu},
- {0xC4u, 0x77u},
- {0xCAu, 0xECu},
- {0xCCu, 0xDFu},
- {0xCEu, 0x77u},
- {0xD6u, 0xFCu},
- {0xD8u, 0x1Cu},
- {0xE0u, 0x50u},
- {0xE4u, 0x40u},
- {0xEEu, 0x08u},
- {0x00u, 0x96u},
- {0x02u, 0x69u},
- {0x05u, 0x88u},
- {0x07u, 0x03u},
- {0x08u, 0x0Fu},
- {0x09u, 0x21u},
- {0x0Au, 0xF0u},
- {0x0Bu, 0x02u},
- {0x0Eu, 0xFFu},
- {0x10u, 0x55u},
- {0x12u, 0xAAu},
- {0x13u, 0x01u},
- {0x14u, 0x33u},
- {0x15u, 0xE0u},
- {0x16u, 0xCCu},
- {0x1Au, 0xFFu},
- {0x1Bu, 0xECu},
- {0x1Cu, 0xFFu},
- {0x21u, 0x04u},
- {0x23u, 0x43u},
- {0x26u, 0xFFu},
- {0x27u, 0x12u},
- {0x28u, 0xFFu},
- {0x31u, 0x10u},
+ {0x1Bu, 0x08u},
+ {0x1Cu, 0x04u},
+ {0x1Du, 0x90u},
+ {0x1Eu, 0x10u},
+ {0x20u, 0x20u},
+ {0x22u, 0x02u},
+ {0x24u, 0x80u},
+ {0x27u, 0x80u},
+ {0x29u, 0x80u},
+ {0x2Bu, 0xA0u},
+ {0x2Du, 0x01u},
+ {0x2Fu, 0x04u},
+ {0x32u, 0x51u},
+ {0x34u, 0x08u},
+ {0x37u, 0x90u},
+ {0x39u, 0x54u},
+ {0x3Du, 0x80u},
+ {0x3Eu, 0x20u},
+ {0x3Fu, 0x0Au},
+ {0x48u, 0x04u},
+ {0x4Au, 0x08u},
+ {0x58u, 0x80u},
+ {0x63u, 0x02u},
+ {0x69u, 0x14u},
+ {0x6Au, 0x01u},
+ {0x6Bu, 0x01u},
+ {0x73u, 0x55u},
+ {0x80u, 0x20u},
+ {0x81u, 0x87u},
+ {0x82u, 0x50u},
+ {0x87u, 0x10u},
+ {0x8Au, 0x02u},
+ {0x8Eu, 0x10u},
+ {0x91u, 0x81u},
+ {0x92u, 0x02u},
+ {0x93u, 0x28u},
+ {0x94u, 0x88u},
+ {0x95u, 0x14u},
+ {0x97u, 0xD4u},
+ {0x98u, 0x98u},
+ {0x99u, 0x02u},
+ {0x9Au, 0x32u},
+ {0x9Bu, 0x14u},
+ {0x9Du, 0x38u},
+ {0x9Eu, 0x80u},
+ {0xA0u, 0x02u},
+ {0xA1u, 0x40u},
+ {0xA2u, 0x0Cu},
+ {0xA3u, 0xE6u},
+ {0xA4u, 0x50u},
+ {0xA5u, 0x01u},
+ {0xA9u, 0x80u},
+ {0xABu, 0x08u},
+ {0xAFu, 0x40u},
+ {0xB0u, 0x18u},
+ {0xB4u, 0x04u},
+ {0xB7u, 0x04u},
+ {0xC0u, 0x65u},
+ {0xC2u, 0xE3u},
+ {0xC4u, 0xCEu},
+ {0xCAu, 0xABu},
+ {0xCCu, 0x7Du},
+ {0xCEu, 0xFEu},
+ {0xD6u, 0x08u},
+ {0xD8u, 0x08u},
+ {0xE0u, 0x04u},
+ {0xE6u, 0x30u},
+ {0xE8u, 0xA0u},
+ {0xECu, 0x50u},
+ {0xEEu, 0x02u},
+ {0x00u, 0x0Fu},
+ {0x02u, 0xF0u},
+ {0x05u, 0x44u},
+ {0x06u, 0xFFu},
+ {0x07u, 0x88u},
+ {0x09u, 0x84u},
+ {0x0Bu, 0x48u},
+ {0x0Cu, 0x33u},
+ {0x0Eu, 0xCCu},
+ {0x11u, 0x21u},
+ {0x12u, 0xFFu},
+ {0x13u, 0x12u},
+ {0x16u, 0xFFu},
+ {0x17u, 0xFFu},
+ {0x18u, 0x11u},
+ {0x1Au, 0x22u},
+ {0x1Bu, 0xFFu},
+ {0x1Cu, 0x12u},
+ {0x1Du, 0xFFu},
+ {0x1Eu, 0x21u},
+ {0x21u, 0x0Fu},
+ {0x23u, 0xF0u},
+ {0x24u, 0x44u},
+ {0x25u, 0x11u},
+ {0x26u, 0x88u},
+ {0x27u, 0x22u},
+ {0x28u, 0x48u},
+ {0x2Au, 0x84u},
+ {0x2Du, 0x33u},
+ {0x2Fu, 0xCCu},
+ {0x31u, 0xFFu},
{0x32u, 0xFFu},
- {0x35u, 0x0Fu},
- {0x37u, 0xE0u},
- {0x3Au, 0x08u},
- {0x3Fu, 0x40u},
- {0x56u, 0x08u},
+ {0x3Eu, 0x04u},
+ {0x3Fu, 0x01u},
{0x58u, 0x04u},
{0x59u, 0x04u},
- {0x5Bu, 0x04u},
- {0x5Cu, 0x02u},
- {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x84u, 0x02u},
- {0x86u, 0x09u},
+ {0x81u, 0x10u},
+ {0x85u, 0x04u},
{0x87u, 0x01u},
- {0x89u, 0xE0u},
- {0x8Cu, 0x02u},
- {0x8Eu, 0x05u},
- {0x93u, 0xECu},
- {0x94u, 0x01u},
- {0x95u, 0x88u},
- {0x96u, 0x02u},
- {0x97u, 0x03u},
- {0x98u, 0x02u},
+ {0x88u, 0x18u},
+ {0x8Au, 0x23u},
+ {0x8Bu, 0x04u},
+ {0x8Fu, 0x04u},
+ {0x91u, 0x40u},
+ {0x95u, 0x28u},
+ {0x96u, 0x0Cu},
+ {0x97u, 0x50u},
+ {0x99u, 0x08u},
{0x9Au, 0x01u},
- {0x9Cu, 0x02u},
- {0x9Eu, 0x01u},
- {0xA3u, 0x12u},
- {0xA5u, 0x04u},
- {0xA7u, 0x43u},
- {0xA9u, 0x21u},
- {0xABu, 0x02u},
- {0xB2u, 0x03u},
- {0xB3u, 0xE0u},
- {0xB4u, 0x08u},
- {0xB5u, 0x10u},
- {0xB6u, 0x04u},
- {0xB7u, 0x0Fu},
- {0xBAu, 0x08u},
- {0xBFu, 0x04u},
- {0xD6u, 0x08u},
+ {0x9Bu, 0x03u},
+ {0x9Cu, 0x11u},
+ {0x9Du, 0x20u},
+ {0x9Eu, 0x22u},
+ {0xA1u, 0x04u},
+ {0xA2u, 0x42u},
+ {0xA3u, 0x02u},
+ {0xA4u, 0x34u},
+ {0xA6u, 0x03u},
+ {0xADu, 0x80u},
+ {0xB0u, 0x20u},
+ {0xB1u, 0x80u},
+ {0xB2u, 0x0Fu},
+ {0xB3u, 0x60u},
+ {0xB4u, 0x40u},
+ {0xB5u, 0x07u},
+ {0xB6u, 0x10u},
+ {0xB7u, 0x18u},
+ {0xBEu, 0x41u},
+ {0xBFu, 0x45u},
+ {0xD4u, 0x09u},
+ {0xD6u, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x12u},
- {0xDDu, 0x90u},
+ {0xDCu, 0x21u},
+ {0xDDu, 0x10u},
{0xDFu, 0x01u},
- {0x00u, 0x01u},
- {0x03u, 0x0Au},
- {0x05u, 0x80u},
- {0x07u, 0x10u},
- {0x08u, 0x08u},
- {0x0Au, 0x01u},
- {0x0Bu, 0x88u},
- {0x0Eu, 0x2Au},
- {0x12u, 0x18u},
- {0x18u, 0x20u},
- {0x1Bu, 0x08u},
- {0x1Eu, 0x2Au},
- {0x22u, 0x11u},
- {0x23u, 0x02u},
- {0x24u, 0x04u},
- {0x25u, 0x04u},
- {0x27u, 0x01u},
- {0x28u, 0x10u},
- {0x2Bu, 0x40u},
- {0x2Du, 0x08u},
- {0x2Eu, 0x10u},
- {0x2Fu, 0x80u},
- {0x30u, 0x08u},
- {0x32u, 0x11u},
- {0x35u, 0x04u},
- {0x37u, 0x01u},
- {0x39u, 0x08u},
- {0x3Bu, 0x20u},
- {0x3Cu, 0x24u},
- {0x58u, 0x40u},
- {0x5Eu, 0x40u},
- {0x60u, 0x01u},
- {0x65u, 0x80u},
- {0x68u, 0x82u},
- {0x69u, 0x14u},
- {0x71u, 0x2Au},
- {0x73u, 0x01u},
- {0x82u, 0x50u},
- {0x84u, 0x40u},
+ {0x03u, 0xA2u},
+ {0x07u, 0x04u},
+ {0x08u, 0x20u},
+ {0x09u, 0x04u},
+ {0x0Au, 0x82u},
+ {0x0Du, 0x40u},
+ {0x0Eu, 0x18u},
+ {0x11u, 0x14u},
+ {0x14u, 0x10u},
+ {0x15u, 0x02u},
+ {0x19u, 0x08u},
+ {0x1Cu, 0x20u},
+ {0x1Du, 0x40u},
+ {0x1Eu, 0x58u},
+ {0x20u, 0x80u},
+ {0x24u, 0x02u},
+ {0x25u, 0x0Eu},
+ {0x26u, 0x20u},
+ {0x28u, 0x20u},
+ {0x2Bu, 0x82u},
+ {0x2Cu, 0x02u},
+ {0x2Du, 0x01u},
+ {0x31u, 0x08u},
+ {0x32u, 0x41u},
+ {0x33u, 0x20u},
+ {0x36u, 0xA8u},
+ {0x37u, 0x21u},
+ {0x39u, 0x14u},
+ {0x3Cu, 0x08u},
+ {0x3Eu, 0x21u},
+ {0x3Fu, 0x80u},
+ {0x5Du, 0x02u},
+ {0x5Eu, 0x64u},
+ {0x65u, 0x40u},
+ {0x67u, 0x80u},
+ {0x82u, 0x08u},
+ {0x83u, 0x22u},
{0x88u, 0x10u},
- {0x8Bu, 0x80u},
- {0x8Du, 0x04u},
- {0x8Eu, 0x04u},
- {0x8Fu, 0x03u},
- {0x91u, 0x08u},
- {0x92u, 0x01u},
- {0x93u, 0xA8u},
- {0x94u, 0x20u},
- {0x95u, 0x14u},
- {0x98u, 0x18u},
- {0x99u, 0x0Cu},
- {0x9Au, 0x10u},
- {0x9Bu, 0x10u},
- {0x9Eu, 0x04u},
- {0xA0u, 0x08u},
- {0xA2u, 0x08u},
- {0xA3u, 0x42u},
- {0xA4u, 0x82u},
- {0xA5u, 0x2Au},
- {0xA6u, 0x11u},
- {0xABu, 0x40u},
- {0xADu, 0x01u},
- {0xAFu, 0x02u},
- {0xB1u, 0x0Cu},
- {0xB2u, 0x08u},
- {0xB3u, 0x10u},
- {0xB4u, 0xA0u},
- {0xC0u, 0xABu},
+ {0x89u, 0x01u},
+ {0x8Au, 0x14u},
+ {0x8Cu, 0x01u},
+ {0x91u, 0x95u},
+ {0x92u, 0x83u},
+ {0x97u, 0x80u},
+ {0x98u, 0x30u},
+ {0x99u, 0x02u},
+ {0x9Au, 0x20u},
+ {0x9Bu, 0x05u},
+ {0x9Du, 0x08u},
+ {0x9Fu, 0x20u},
+ {0xA0u, 0x06u},
+ {0xA2u, 0x80u},
+ {0xA3u, 0xE2u},
+ {0xA4u, 0x40u},
+ {0xA5u, 0x06u},
+ {0xAEu, 0x80u},
+ {0xAFu, 0x08u},
+ {0xB1u, 0x30u},
+ {0xB2u, 0x80u},
+ {0xC0u, 0x4Du},
{0xC2u, 0xEFu},
- {0xC4u, 0x06u},
- {0xCAu, 0xE3u},
- {0xCCu, 0xC7u},
- {0xCEu, 0x66u},
- {0xD6u, 0x18u},
- {0xD8u, 0x18u},
- {0xE0u, 0x80u},
- {0xE2u, 0x10u},
- {0xE4u, 0x80u},
- {0xE6u, 0x48u},
- {0xE8u, 0xB0u},
- {0xECu, 0x80u},
- {0xEEu, 0x01u},
- {0x06u, 0x08u},
- {0x0Cu, 0x10u},
- {0x0Eu, 0x40u},
- {0x11u, 0x10u},
- {0x13u, 0x08u},
- {0x16u, 0x80u},
- {0x17u, 0x40u},
- {0x30u, 0x40u},
+ {0xC4u, 0x36u},
+ {0xCAu, 0x9Bu},
+ {0xCCu, 0xFFu},
+ {0xCEu, 0xF6u},
+ {0xD6u, 0xF0u},
+ {0xD8u, 0x90u},
+ {0xE0u, 0xA0u},
+ {0xE4u, 0x20u},
+ {0xE6u, 0x80u},
+ {0xE8u, 0x20u},
+ {0xECu, 0x22u},
+ {0x04u, 0x40u},
+ {0x0Eu, 0x08u},
+ {0x0Fu, 0x40u},
+ {0x12u, 0x20u},
+ {0x13u, 0x10u},
+ {0x17u, 0x81u},
+ {0x19u, 0x01u},
+ {0x1Du, 0x04u},
+ {0x30u, 0x10u},
{0x33u, 0x01u},
- {0x36u, 0x22u},
- {0x3Au, 0x81u},
- {0x3Du, 0x44u},
- {0x40u, 0x04u},
- {0x53u, 0x02u},
- {0x5Fu, 0x40u},
- {0x6Bu, 0x09u},
- {0x82u, 0x01u},
+ {0x36u, 0x20u},
+ {0x37u, 0x02u},
+ {0x39u, 0x04u},
+ {0x3Bu, 0x10u},
+ {0x3Du, 0x01u},
+ {0x3Eu, 0x80u},
+ {0x42u, 0x08u},
+ {0x50u, 0x20u},
+ {0x56u, 0x20u},
+ {0x89u, 0x01u},
{0xC0u, 0x80u},
{0xC2u, 0xA0u},
{0xC4u, 0xF0u},
+ {0xC6u, 0x30u},
{0xCCu, 0xF0u},
{0xCEu, 0xF0u},
{0xD0u, 0x10u},
- {0xD4u, 0x80u},
- {0xD6u, 0x20u},
- {0xE2u, 0x20u},
- {0x00u, 0x10u},
- {0x0Au, 0x02u},
- {0x30u, 0x08u},
- {0x33u, 0x20u},
- {0x36u, 0x08u},
- {0x37u, 0x40u},
- {0x39u, 0x80u},
- {0x59u, 0x40u},
- {0x61u, 0x20u},
- {0x82u, 0x08u},
- {0x85u, 0x10u},
- {0x86u, 0x02u},
- {0x87u, 0x20u},
- {0x88u, 0x08u},
- {0x89u, 0x40u},
- {0x91u, 0x10u},
- {0x92u, 0x40u},
- {0x94u, 0x04u},
+ {0xD4u, 0x60u},
+ {0x03u, 0x02u},
+ {0x0Au, 0x01u},
+ {0x31u, 0x01u},
+ {0x32u, 0x40u},
+ {0x35u, 0x04u},
+ {0x37u, 0x80u},
+ {0x39u, 0x08u},
+ {0x3Bu, 0x20u},
+ {0x3Fu, 0x80u},
+ {0x54u, 0x08u},
+ {0x5Fu, 0x01u},
+ {0x80u, 0x40u},
+ {0x90u, 0x40u},
+ {0x93u, 0x40u},
{0x95u, 0x04u},
- {0x97u, 0x40u},
- {0x98u, 0x10u},
- {0x9Au, 0x08u},
- {0x9Bu, 0x40u},
- {0x9Cu, 0x40u},
- {0xA1u, 0x20u},
- {0xA6u, 0x22u},
- {0xA7u, 0x02u},
- {0xA9u, 0x20u},
- {0xB5u, 0x40u},
+ {0x99u, 0x05u},
+ {0x9Bu, 0x80u},
+ {0x9Cu, 0x10u},
+ {0x9Eu, 0xA0u},
+ {0x9Fu, 0x02u},
+ {0xA2u, 0x04u},
+ {0xA8u, 0x20u},
+ {0xB6u, 0x08u},
{0xC0u, 0x40u},
{0xC2u, 0x40u},
{0xCCu, 0xF0u},
- {0xCEu, 0x10u},
- {0xD4u, 0x80u},
- {0xD8u, 0x40u},
- {0xE2u, 0x60u},
- {0xEAu, 0x20u},
- {0x10u, 0x40u},
- {0x33u, 0x80u},
- {0x81u, 0x20u},
- {0x88u, 0x10u},
- {0x8Eu, 0x20u},
- {0x92u, 0x42u},
- {0x94u, 0x04u},
- {0x95u, 0x84u},
- {0x97u, 0x40u},
- {0x98u, 0x10u},
- {0x9Au, 0x08u},
- {0x9Cu, 0x40u},
- {0xA6u, 0x20u},
- {0xB4u, 0x10u},
- {0xB7u, 0x02u},
+ {0xCEu, 0x70u},
+ {0xD4u, 0x40u},
+ {0xD6u, 0x80u},
+ {0xE4u, 0x20u},
+ {0xEAu, 0x80u},
+ {0x10u, 0x10u},
+ {0x33u, 0x10u},
+ {0x34u, 0x08u},
+ {0x37u, 0x80u},
+ {0x52u, 0x20u},
+ {0x80u, 0x08u},
+ {0x8Au, 0x28u},
+ {0x93u, 0x40u},
+ {0x95u, 0x0Cu},
+ {0x96u, 0x80u},
+ {0x97u, 0x21u},
+ {0x9Cu, 0x10u},
+ {0x9Eu, 0xA0u},
+ {0x9Fu, 0x02u},
+ {0xA3u, 0x02u},
+ {0xA4u, 0x08u},
+ {0xA7u, 0x40u},
+ {0xAEu, 0x01u},
+ {0xB6u, 0x04u},
{0xC4u, 0x10u},
- {0xCCu, 0x10u},
- {0xE6u, 0x80u},
- {0x86u, 0x01u},
- {0x8Du, 0x80u},
- {0x92u, 0x42u},
- {0x94u, 0x04u},
- {0x95u, 0x04u},
- {0x97u, 0x40u},
- {0x99u, 0x20u},
- {0x9Au, 0x08u},
- {0xA7u, 0x80u},
- {0xA9u, 0x40u},
- {0xE4u, 0x40u},
+ {0xCCu, 0xB0u},
+ {0xD4u, 0x20u},
+ {0xE2u, 0x80u},
+ {0xE8u, 0x10u},
+ {0x80u, 0x08u},
+ {0x83u, 0x10u},
+ {0x85u, 0x04u},
+ {0x95u, 0x0Cu},
+ {0x96u, 0x80u},
+ {0x97u, 0x21u},
+ {0x9Cu, 0x08u},
+ {0x9Eu, 0xA0u},
+ {0x9Fu, 0x12u},
+ {0xA3u, 0x02u},
+ {0xA6u, 0x08u},
+ {0xA7u, 0x40u},
+ {0xABu, 0x80u},
+ {0xAFu, 0x40u},
+ {0xE2u, 0x20u},
+ {0xE6u, 0x60u},
{0xEAu, 0x80u},
- {0x05u, 0x08u},
- {0x06u, 0x08u},
- {0x09u, 0x01u},
- {0x0Bu, 0x02u},
- {0x11u, 0x04u},
- {0x56u, 0x04u},
- {0x5Bu, 0x02u},
- {0x65u, 0x40u},
- {0x78u, 0x80u},
+ {0xECu, 0x40u},
+ {0x04u, 0x80u},
+ {0x05u, 0x04u},
+ {0x08u, 0x40u},
+ {0x0Au, 0x20u},
+ {0x10u, 0x20u},
+ {0x53u, 0x01u},
+ {0x58u, 0x01u},
+ {0x60u, 0x04u},
+ {0x80u, 0x20u},
+ {0x83u, 0x01u},
+ {0x8Eu, 0x10u},
{0xC0u, 0x05u},
{0xC2u, 0x0Au},
{0xC4u, 0x08u},
- {0xD4u, 0x02u},
- {0xD6u, 0x03u},
- {0xDCu, 0x01u},
- {0x01u, 0x42u},
- {0x09u, 0x04u},
- {0x0Au, 0x01u},
- {0x52u, 0x02u},
- {0x57u, 0x01u},
- {0x66u, 0x82u},
- {0x80u, 0x02u},
- {0x86u, 0x82u},
- {0x87u, 0x02u},
- {0x89u, 0x08u},
- {0x8Eu, 0x02u},
- {0x91u, 0x04u},
- {0x93u, 0x02u},
- {0x99u, 0x08u},
- {0x9Au, 0x08u},
- {0x9Du, 0x40u},
- {0x9Eu, 0x04u},
- {0x9Fu, 0x02u},
- {0xA5u, 0x04u},
- {0xA9u, 0x05u},
- {0xACu, 0x80u},
- {0xADu, 0x40u},
+ {0xD4u, 0x01u},
+ {0xD6u, 0x02u},
+ {0xD8u, 0x02u},
+ {0xE2u, 0x02u},
+ {0x00u, 0x48u},
+ {0x08u, 0x40u},
+ {0x0Bu, 0x10u},
+ {0x57u, 0x0Au},
+ {0x61u, 0x90u},
+ {0x80u, 0x40u},
+ {0x8Bu, 0x10u},
+ {0x8Cu, 0x40u},
+ {0x90u, 0x80u},
+ {0x94u, 0x04u},
+ {0x99u, 0x04u},
+ {0x9Cu, 0x01u},
+ {0xB0u, 0x40u},
{0xC0u, 0x0Au},
{0xC2u, 0x0Au},
- {0xD4u, 0x01u},
- {0xD6u, 0x05u},
- {0xD8u, 0x01u},
- {0xE4u, 0x08u},
- {0xE6u, 0x04u},
- {0x54u, 0x20u},
- {0x87u, 0x01u},
- {0x91u, 0x04u},
- {0x92u, 0x01u},
- {0x93u, 0x02u},
- {0x99u, 0x0Au},
- {0x9Au, 0x08u},
- {0x9Du, 0x40u},
- {0x9Eu, 0x04u},
- {0xA0u, 0x20u},
- {0xA4u, 0x02u},
- {0xA5u, 0x08u},
- {0xA7u, 0x01u},
- {0xACu, 0x20u},
- {0xB5u, 0x40u},
{0xD4u, 0x02u},
- {0xEAu, 0x02u},
- {0x09u, 0x08u},
- {0x0Bu, 0x01u},
- {0x0Cu, 0x02u},
- {0x0Fu, 0x02u},
- {0x82u, 0x04u},
- {0x85u, 0x40u},
- {0x86u, 0x01u},
- {0x89u, 0x04u},
- {0x8Fu, 0x01u},
- {0x91u, 0x04u},
- {0x92u, 0x01u},
- {0x93u, 0x02u},
- {0x97u, 0x01u},
- {0x99u, 0x0Au},
- {0x9Au, 0x08u},
- {0x9Du, 0x40u},
- {0x9Eu, 0x04u},
- {0xA4u, 0x02u},
- {0xA5u, 0x08u},
- {0xABu, 0x01u},
+ {0xD6u, 0x06u},
+ {0xD8u, 0x02u},
+ {0xE2u, 0x02u},
+ {0xE6u, 0x01u},
+ {0xEAu, 0x01u},
+ {0x56u, 0x80u},
+ {0x81u, 0x80u},
+ {0x87u, 0x0Au},
+ {0x94u, 0x04u},
+ {0x9Cu, 0x01u},
+ {0x9Du, 0x10u},
+ {0xA0u, 0x04u},
+ {0xA5u, 0x80u},
+ {0xA7u, 0x0Au},
+ {0xA8u, 0x04u},
+ {0xA9u, 0x04u},
+ {0xACu, 0x40u},
+ {0xD4u, 0x02u},
+ {0x09u, 0x10u},
+ {0x0Bu, 0x40u},
+ {0x0Fu, 0x88u},
+ {0x83u, 0x44u},
+ {0x88u, 0x01u},
+ {0x94u, 0x04u},
+ {0x9Cu, 0x01u},
+ {0x9Du, 0x10u},
+ {0xA5u, 0x10u},
+ {0xA9u, 0x10u},
+ {0xACu, 0x04u},
+ {0xAEu, 0x80u},
{0xC2u, 0x0Fu},
- {0xE2u, 0x06u},
- {0x01u, 0x80u},
- {0x65u, 0x04u},
- {0x8Bu, 0x40u},
- {0x92u, 0x40u},
- {0x95u, 0x04u},
- {0x97u, 0x40u},
- {0x99u, 0x20u},
- {0x9Du, 0x80u},
- {0xAAu, 0x08u},
- {0xAFu, 0x80u},
- {0xB4u, 0x04u},
+ {0xE4u, 0x04u},
+ {0x02u, 0x08u},
+ {0x66u, 0x10u},
+ {0x82u, 0x40u},
+ {0x83u, 0x41u},
+ {0x86u, 0x80u},
+ {0x87u, 0x10u},
+ {0x8Au, 0x10u},
+ {0x8Cu, 0x01u},
+ {0x96u, 0x80u},
+ {0x97u, 0x01u},
+ {0x9Eu, 0xA0u},
+ {0x9Fu, 0x02u},
+ {0xA6u, 0x08u},
+ {0xA7u, 0x40u},
+ {0xADu, 0x04u},
+ {0xAFu, 0x10u},
+ {0xB3u, 0x02u},
{0xC0u, 0x40u},
{0xD8u, 0x80u},
- {0xECu, 0x80u},
- {0xEEu, 0x10u},
- {0x03u, 0x20u},
- {0x51u, 0x02u},
- {0x56u, 0x20u},
- {0x5Bu, 0x02u},
- {0x65u, 0x20u},
- {0x77u, 0x10u},
+ {0xE2u, 0xE0u},
+ {0xE6u, 0xC0u},
+ {0xEAu, 0x10u},
+ {0xEEu, 0x40u},
+ {0x02u, 0x10u},
+ {0x57u, 0x08u},
+ {0x5Au, 0x40u},
+ {0x5Cu, 0x01u},
+ {0x67u, 0x20u},
{0x82u, 0x40u},
- {0x87u, 0x20u},
- {0x8Du, 0x02u},
+ {0x86u, 0x10u},
+ {0x87u, 0x08u},
{0x8Eu, 0x20u},
- {0x8Fu, 0x02u},
- {0x92u, 0x40u},
- {0x99u, 0x20u},
- {0x9Bu, 0x10u},
- {0xA9u, 0x04u},
- {0xABu, 0x10u},
- {0xADu, 0x04u},
+ {0x90u, 0x01u},
+ {0x93u, 0x20u},
+ {0x9Eu, 0x20u},
+ {0xB7u, 0x02u},
{0xC0u, 0x10u},
{0xD4u, 0xC0u},
- {0xD6u, 0x40u},
+ {0xD6u, 0x80u},
{0xD8u, 0x80u},
- {0xDEu, 0x20u},
- {0xE0u, 0x20u},
- {0xE4u, 0x10u},
- {0xEAu, 0x20u},
- {0xEEu, 0xC0u},
- {0x99u, 0x0Au},
- {0x9Au, 0x08u},
- {0xAFu, 0x01u},
- {0x85u, 0x08u},
- {0x99u, 0x08u},
- {0xAAu, 0x08u},
- {0xB5u, 0x02u},
- {0xEAu, 0x02u},
+ {0xE0u, 0x40u},
+ {0xE2u, 0x20u},
+ {0xE6u, 0x40u},
+ {0x80u, 0x04u},
+ {0x94u, 0x04u},
+ {0x9Du, 0x10u},
+ {0xAFu, 0x40u},
+ {0x74u, 0x04u},
+ {0x8Du, 0x10u},
+ {0x9Du, 0x10u},
+ {0xA0u, 0x04u},
+ {0xACu, 0x04u},
+ {0xDEu, 0x04u},
+ {0xE0u, 0x02u},
{0x10u, 0x07u},
{0x11u, 0x01u},
- {0x1Au, 0x07u},
+ {0x1Au, 0x03u},
+ {0x1Bu, 0x01u},
{0x1Cu, 0x07u},
{0x1Du, 0x01u},
- {0x00u, 0xFFu},
- {0x01u, 0xBFu},
- {0x02u, 0x2Au},
- {0x10u, 0x95u},
+ {0x10u, 0x59u},
+ {0x11u, 0x09u},
};
{(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},
};
+ /* IDMUX_IRQ Address: CYREG_IDMUX_IRQ_CTL0 Size (bytes): 8 */
+ static const uint8 CYCODE BS_IDMUX_IRQ_VAL[] = {
+ 0xFFu, 0xFFu, 0xABu, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u};
+
/* UDB_1_3_0_CONFIG Address: CYDEV_UCFG_B0_P2_U0_BASE Size (bytes): 128 */
static const uint8 CYCODE BS_UDB_1_3_0_CONFIG_VAL[] = {
- 0x00u, 0x24u, 0x00u, 0x12u, 0x08u, 0x00u, 0x61u, 0x20u, 0x00u, 0x00u, 0x40u, 0x04u, 0x07u, 0x00u, 0xD8u, 0x24u,
- 0x01u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0x03u, 0x04u, 0x00u, 0x00u, 0x18u, 0x01u, 0x00u, 0x00u, 0x00u,
- 0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0xA2u, 0x24u, 0x08u, 0x09u, 0x01u, 0x00u, 0x00u, 0x00u,
- 0x00u, 0x00u, 0xE0u, 0x07u, 0x3Fu, 0x38u, 0x00u, 0x00u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u,
- 0x63u, 0x04u, 0x50u, 0x00u, 0x02u, 0xCEu, 0xBFu, 0xD0u, 0x2Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x04u, 0x04u, 0x04u, 0x20u, 0x00u, 0x00u, 0x01u,
+ 0x34u, 0x00u, 0x40u, 0x00u, 0x3Du, 0x30u, 0x42u, 0x00u, 0x03u, 0x00u, 0x0Cu, 0x00u, 0x40u, 0x15u, 0x80u, 0x0Au,
+ 0x10u, 0x00u, 0x20u, 0x00u, 0x00u, 0x09u, 0x00u, 0x16u, 0x00u, 0x04u, 0x77u, 0x03u, 0x10u, 0x00u, 0x20u, 0x00u,
+ 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x8Bu, 0x0Bu, 0x74u, 0x24u, 0x88u, 0x00u, 0x77u, 0x00u,
+ 0x30u, 0x00u, 0x00u, 0x38u, 0x0Fu, 0x07u, 0xC0u, 0x00u, 0x00u, 0x08u, 0xA2u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x52u, 0x04u, 0x60u, 0x00u, 0x03u, 0xBEu, 0xFDu, 0xBCu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x04u, 0x04u, 0x04u, 0x12u, 0x10u, 0x00u, 0x01u,
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
/* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */
static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {
- 0x5Cu, 0x00u, 0x00u, 0x00u, 0x30u, 0x05u, 0x0Fu, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x01u, 0x50u, 0x06u,
- 0x11u, 0x04u, 0x22u, 0x03u, 0x21u, 0x00u, 0x1Eu, 0x00u, 0x54u, 0x00u, 0x08u, 0x00u, 0x5Cu, 0x00u, 0x00u, 0x00u,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x00u, 0x0Cu, 0x00u, 0x24u, 0x00u, 0x10u, 0x00u, 0x08u, 0x03u, 0x00u, 0x04u,
- 0x0Fu, 0x07u, 0x40u, 0x00u, 0x30u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x20u, 0x02u, 0x00u, 0x00u, 0x44u, 0x00u,
- 0x16u, 0x04u, 0x30u, 0x00u, 0x05u, 0xBEu, 0xF0u, 0xCDu, 0x3Bu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x2Cu, 0x04u, 0x04u, 0x04u, 0x04u, 0x11u, 0x11u, 0x00u, 0x01u,
+ 0x02u, 0x00u, 0x00u, 0x00u, 0x02u, 0x80u, 0x00u, 0x00u, 0x10u, 0xC0u, 0x42u, 0x08u, 0x01u, 0x7Fu, 0x00u, 0x80u,
+ 0x44u, 0x90u, 0x10u, 0x40u, 0x01u, 0x1Fu, 0x00u, 0x20u, 0x02u, 0xC0u, 0x00u, 0x04u, 0x02u, 0xC0u, 0x00u, 0x02u,
+ 0x08u, 0xC0u, 0x00u, 0x01u, 0x20u, 0x00u, 0x00u, 0x9Fu, 0x0Eu, 0x00u, 0x30u, 0xFFu, 0x02u, 0x00u, 0x00u, 0x60u,
+ 0x01u, 0x00u, 0x00u, 0xFFu, 0x00u, 0x00u, 0x7Eu, 0x00u, 0x82u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x04u,
+ 0x64u, 0x03u, 0x50u, 0x00u, 0x02u, 0xCBu, 0xF0u, 0xEDu, 0x3Bu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x04u, 0x04u, 0x04u, 0x01u, 0x01u, 0x00u, 0x01u,
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {
- 0x07u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x05u, 0x01u, 0x07u, 0x01u, 0x05u, 0x01u, 0x05u, 0x01u};
+ 0x07u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x07u, 0x01u, 0x07u, 0x01u, 0x04u, 0x01u, 0x04u, 0x01u};
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
+ {(void CYFAR *)(CYREG_IDMUX_IRQ_CTL0), BS_IDMUX_IRQ_VAL, 8u},
{(void CYFAR *)(CYDEV_UCFG_B0_P2_U0_BASE), BS_UDB_1_3_0_CONFIG_VAL, 128u},
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u},
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM1_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM1_VAL), 4u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM2_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM2_VAL), 4u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM3_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM3_VAL), 4u);
+ CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM4_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM4_VAL), 4u);
+ CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM5_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM5_VAL), 4u);
/* Enable digital routing */
CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u);
.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_1__INTC_MASK, 0x80
-.set USBFS_ep_1__INTC_NUMBER, 7
+.set USBFS_ep_1__INTC_MASK, 0x200
+.set USBFS_ep_1__INTC_NUMBER, 9
.set USBFS_ep_1__INTC_PRIOR_NUM, 7
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_9
.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_2__INTC_MASK, 0x100
-.set USBFS_ep_2__INTC_NUMBER, 8
+.set USBFS_ep_2__INTC_MASK, 0x400
+.set USBFS_ep_2__INTC_NUMBER, 10
.set USBFS_ep_2__INTC_PRIOR_NUM, 7
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_10
.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_3__INTC_MASK, 0x200
-.set USBFS_ep_3__INTC_NUMBER, 9
+.set USBFS_ep_3__INTC_MASK, 0x800
+.set USBFS_ep_3__INTC_NUMBER, 11
.set USBFS_ep_3__INTC_PRIOR_NUM, 7
-.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9
+.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_11
.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_4__INTC_MASK, 0x400
-.set USBFS_ep_4__INTC_NUMBER, 10
+.set USBFS_ep_4__INTC_MASK, 0x2000
+.set USBFS_ep_4__INTC_NUMBER, 13
.set USBFS_ep_4__INTC_PRIOR_NUM, 7
-.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10
+.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_13
.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set NOR_SO__SLW, CYREG_PRT15_SLW
/* SDCard */
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB04_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB04_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB04_MSK
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB04_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB04_ST
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
.set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
.set SDCard_BSPIM_TxStsReg__2__POS, 2
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB11_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB11_ST
/* SD_SCK */
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE1
.set NOR_SCK__SLW, CYREG_PRT3_SLW
/* NOR_SPI */
-.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
-.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
-.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
-.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
-.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
-.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
-.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
-.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
-.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
-.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
-.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB04_CTL
-.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
-.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB04_CTL
-.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
-.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
-.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
-.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB04_MSK
-.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
-.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
-.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB04_MSK
-.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
-.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
-.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
-.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL
-.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL
-.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB04_ST
-.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
+.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL
+.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL
+.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL
+.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL
+.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK
+.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK
+.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK
+.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK
+.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL
+.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL
+.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL
+.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL
+.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK
+.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
+.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK
+.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL
+.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL
+.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST
+.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set NOR_SPI_BSPIM_RxStsReg__4__MASK, 0x10
.set NOR_SPI_BSPIM_RxStsReg__4__POS, 4
.set NOR_SPI_BSPIM_RxStsReg__5__MASK, 0x20
.set NOR_SPI_BSPIM_RxStsReg__6__MASK, 0x40
.set NOR_SPI_BSPIM_RxStsReg__6__POS, 6
.set NOR_SPI_BSPIM_RxStsReg__MASK, 0x70
-.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB11_MSK
-.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB11_ST
+.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
+.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1
.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0
.set NOR_SPI_BSPIM_TxStsReg__0__POS, 0
.set NOR_SPI_BSPIM_TxStsReg__1__MASK, 0x02
.set NOR_SPI_BSPIM_TxStsReg__1__POS, 1
-.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
-.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
+.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
+.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
.set NOR_SPI_BSPIM_TxStsReg__2__MASK, 0x04
.set NOR_SPI_BSPIM_TxStsReg__2__POS, 2
.set NOR_SPI_BSPIM_TxStsReg__3__MASK, 0x08
.set NOR_SPI_BSPIM_TxStsReg__4__MASK, 0x10
.set NOR_SPI_BSPIM_TxStsReg__4__POS, 4
.set NOR_SPI_BSPIM_TxStsReg__MASK, 0x1F
-.set NOR_SPI_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB03_MSK
-.set NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
-.set NOR_SPI_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB03_ST
+.set NOR_SPI_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
+.set NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
+.set NOR_SPI_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
/* SCSI_In */
.set SCSI_In__0__INTTYPE, CYREG_PICU6_INTTYPE1
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB10_11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB10_11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB10_11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB10_11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB10_11_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB10_11_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB10_11_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB10_11_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB09_10_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB09_10_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB09_10_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB09_10_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB09_10_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB09_10_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB09_10_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB09_10_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB10_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB10_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB10_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB10_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB09_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB09_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB09_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB09_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB10_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB09_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
.set NOR_Clock__PM_STBY_MSK, 0x01
/* SD_RX_DMA */
-.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SD_RX_DMA__DRQ_NUMBER, 2
+.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL1
+.set SD_RX_DMA__DRQ_NUMBER, 4
.set SD_RX_DMA__NUMBEROF_TDS, 0
.set SD_RX_DMA__PRIORITY, 0
.set SD_RX_DMA__TERMIN_EN, 0
.set SD_RX_DMA__TERMIN_SEL, 0
.set SD_RX_DMA__TERMOUT0_EN, 1
-.set SD_RX_DMA__TERMOUT0_SEL, 2
+.set SD_RX_DMA__TERMOUT0_SEL, 4
.set SD_RX_DMA__TERMOUT1_EN, 0
.set SD_RX_DMA__TERMOUT1_SEL, 0
.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20
-.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 5
+.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x80
+.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 7
.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_7
.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SD_TX_DMA */
-.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SD_TX_DMA__DRQ_NUMBER, 3
+.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL1
+.set SD_TX_DMA__DRQ_NUMBER, 5
.set SD_TX_DMA__NUMBEROF_TDS, 0
.set SD_TX_DMA__PRIORITY, 1
.set SD_TX_DMA__TERMIN_EN, 0
.set SD_TX_DMA__TERMIN_SEL, 0
.set SD_TX_DMA__TERMOUT0_EN, 1
-.set SD_TX_DMA__TERMOUT0_SEL, 3
+.set SD_TX_DMA__TERMOUT0_SEL, 5
.set SD_TX_DMA__TERMOUT1_EN, 0
.set SD_TX_DMA__TERMOUT1_SEL, 0
.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40
-.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 6
+.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x100
+.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 8
.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_8
.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
.set nNOR_HOLD__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
.set nNOR_HOLD__SLW, CYREG_PRT12_SLW
+/* NOR_RX_DMA */
+.set NOR_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set NOR_RX_DMA__DRQ_NUMBER, 0
+.set NOR_RX_DMA__NUMBEROF_TDS, 0
+.set NOR_RX_DMA__PRIORITY, 2
+.set NOR_RX_DMA__TERMIN_EN, 0
+.set NOR_RX_DMA__TERMIN_SEL, 0
+.set NOR_RX_DMA__TERMOUT0_EN, 1
+.set NOR_RX_DMA__TERMOUT0_SEL, 0
+.set NOR_RX_DMA__TERMOUT1_EN, 0
+.set NOR_RX_DMA__TERMOUT1_SEL, 0
+.set NOR_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set NOR_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set NOR_RX_DMA_COMPLETE__INTC_MASK, 0x02
+.set NOR_RX_DMA_COMPLETE__INTC_NUMBER, 1
+.set NOR_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set NOR_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
+.set NOR_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set NOR_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* NOR_TX_DMA */
+.set NOR_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set NOR_TX_DMA__DRQ_NUMBER, 1
+.set NOR_TX_DMA__NUMBEROF_TDS, 0
+.set NOR_TX_DMA__PRIORITY, 2
+.set NOR_TX_DMA__TERMIN_EN, 0
+.set NOR_TX_DMA__TERMIN_SEL, 0
+.set NOR_TX_DMA__TERMOUT0_EN, 1
+.set NOR_TX_DMA__TERMOUT0_SEL, 1
+.set NOR_TX_DMA__TERMOUT1_EN, 0
+.set NOR_TX_DMA__TERMOUT1_SEL, 0
+.set NOR_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set NOR_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set NOR_TX_DMA_COMPLETE__INTC_MASK, 0x04
+.set NOR_TX_DMA_COMPLETE__INTC_NUMBER, 2
+.set NOR_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set NOR_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2
+.set NOR_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set NOR_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
/* SCSI_Noise */
.set SCSI_Noise__0__AG, CYREG_PRT4_AG
.set SCSI_Noise__0__AMUX, CYREG_PRT4_AMUX
.set scsiTarget_StatusReg__0__POS, 0
.set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
.set scsiTarget_StatusReg__2__MASK, 0x04
.set scsiTarget_StatusReg__2__POS, 2
.set scsiTarget_StatusReg__3__MASK, 0x08
.set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK
-.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
-.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
-.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB15_ST_CTL
-.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB15_ST_CTL
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK
+.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST
/* Debug_Timer */
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
/* SCSI_RX_DMA */
.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SCSI_RX_DMA__DRQ_NUMBER, 0
+.set SCSI_RX_DMA__DRQ_NUMBER, 2
.set SCSI_RX_DMA__NUMBEROF_TDS, 0
.set SCSI_RX_DMA__PRIORITY, 2
.set SCSI_RX_DMA__TERMIN_EN, 0
.set SCSI_RX_DMA__TERMIN_SEL, 0
.set SCSI_RX_DMA__TERMOUT0_EN, 1
-.set SCSI_RX_DMA__TERMOUT0_SEL, 0
+.set SCSI_RX_DMA__TERMOUT0_SEL, 2
.set SCSI_RX_DMA__TERMOUT1_EN, 0
.set SCSI_RX_DMA__TERMOUT1_SEL, 0
.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x04
-.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 2
+.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x10
+.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 4
.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4
.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SCSI_TX_DMA */
.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SCSI_TX_DMA__DRQ_NUMBER, 1
+.set SCSI_TX_DMA__DRQ_NUMBER, 3
.set SCSI_TX_DMA__NUMBEROF_TDS, 0
.set SCSI_TX_DMA__PRIORITY, 2
.set SCSI_TX_DMA__TERMIN_EN, 0
.set SCSI_TX_DMA__TERMIN_SEL, 0
.set SCSI_TX_DMA__TERMOUT0_EN, 1
-.set SCSI_TX_DMA__TERMOUT0_SEL, 1
+.set SCSI_TX_DMA__TERMOUT0_SEL, 3
.set SCSI_TX_DMA__TERMOUT1_EN, 0
.set SCSI_TX_DMA__TERMOUT1_SEL, 0
.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10
-.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4
+.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x40
+.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 6
.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6
.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SCSI_RST_ISR */
.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_RST_ISR__INTC_MASK, 0x02
-.set SCSI_RST_ISR__INTC_NUMBER, 1
+.set SCSI_RST_ISR__INTC_MASK, 0x08
+.set SCSI_RST_ISR__INTC_NUMBER, 3
.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7
-.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
+.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3
.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SCSI_SEL_ISR */
.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_SEL_ISR__INTC_MASK, 0x08
-.set SCSI_SEL_ISR__INTC_NUMBER, 3
+.set SCSI_SEL_ISR__INTC_MASK, 0x20
+.set SCSI_SEL_ISR__INTC_NUMBER, 5
.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7
-.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3
+.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_5
.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
.set SCSI_Filtered_sts_sts_reg__0__POS, 0
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
.set SCSI_Filtered_sts_sts_reg__1__POS, 1
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
.set SCSI_Filtered_sts_sts_reg__2__POS, 2
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
.set SCSI_Filtered_sts_sts_reg__4__POS, 4
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B1_UDB08_MSK
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B1_UDB08_ST
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK
+.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
/* SCSI_Glitch_Ctl */
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB09_10_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB09_10_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB09_10_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB09_10_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB09_10_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB09_10_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB09_10_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB09_10_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB09_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB09_ST_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB09_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB09_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB09_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB12_MSK
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB12_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB09_MSK
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB09_ST
/* Miscellaneous */
.set BCLK__BUS_CLK__HZ, 50000000
.set CYDEV_ECC_ENABLE, 0
.set CYDEV_HEAP_SIZE, 0x0400
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1
-.set CYDEV_INTR_RISING, 0x0000007F
+.set CYDEV_INTR_RISING, 0x000001FF
.set CYDEV_IS_EXPORTING_CODE, 0
.set CYDEV_IS_IMPORTING_CODE, 0
.set CYDEV_PROJ_TYPE, 2
.set CYIPBLOCK_S8_SAR_VERSION, 0
.set CYIPBLOCK_S8_SIO_VERSION, 0
.set CYIPBLOCK_S8_UDB_VERSION, 0
-.set DMA_CHANNELS_USED__MASK0, 0x0000000F
+.set DMA_CHANNELS_USED__MASK0, 0x0000003F
.set CYDEV_BOOTLOADER_ENABLE, 0
.endif
USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x80
-USBFS_ep_1__INTC_NUMBER EQU 7
+USBFS_ep_1__INTC_MASK EQU 0x200
+USBFS_ep_1__INTC_NUMBER EQU 9
USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x100
-USBFS_ep_2__INTC_NUMBER EQU 8
+USBFS_ep_2__INTC_MASK EQU 0x400
+USBFS_ep_2__INTC_NUMBER EQU 10
USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_3__INTC_MASK EQU 0x200
-USBFS_ep_3__INTC_NUMBER EQU 9
+USBFS_ep_3__INTC_MASK EQU 0x800
+USBFS_ep_3__INTC_NUMBER EQU 11
USBFS_ep_3__INTC_PRIOR_NUM EQU 7
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_11
USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_4__INTC_MASK EQU 0x400
-USBFS_ep_4__INTC_NUMBER EQU 10
+USBFS_ep_4__INTC_MASK EQU 0x2000
+USBFS_ep_4__INTC_NUMBER EQU 13
USBFS_ep_4__INTC_PRIOR_NUM EQU 7
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_13
USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
NOR_SO__SLW EQU CYREG_PRT15_SLW
/* SDCard */
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB04_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB04_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB04_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB04_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB04_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
/* SD_SCK */
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1
NOR_SCK__SLW EQU CYREG_PRT3_SLW
/* NOR_SPI */
-NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB04_CTL
-NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB04_CTL
-NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB04_MSK
-NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
-NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB04_MSK
-NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
-NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
-NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB04_ST
-NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
+NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
+NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
+NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
+NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
+NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
+NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
+NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
+NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10
NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4
NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20
NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40
NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6
NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70
-NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK
-NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST
+NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0
NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02
NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1
-NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
+NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04
NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2
NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08
NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10
NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4
NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F
-NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB03_MSK
-NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB03_ST
+NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
+NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
/* SCSI_In */
SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
NOR_Clock__PM_STBY_MSK EQU 0x01
/* SD_RX_DMA */
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_RX_DMA__DRQ_NUMBER EQU 2
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL1
+SD_RX_DMA__DRQ_NUMBER EQU 4
SD_RX_DMA__NUMBEROF_TDS EQU 0
SD_RX_DMA__PRIORITY EQU 0
SD_RX_DMA__TERMIN_EN EQU 0
SD_RX_DMA__TERMIN_SEL EQU 0
SD_RX_DMA__TERMOUT0_EN EQU 1
-SD_RX_DMA__TERMOUT0_SEL EQU 2
+SD_RX_DMA__TERMOUT0_SEL EQU 4
SD_RX_DMA__TERMOUT1_EN EQU 0
SD_RX_DMA__TERMOUT1_SEL EQU 0
SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x80
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 7
SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SD_TX_DMA */
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_TX_DMA__DRQ_NUMBER EQU 3
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL1
+SD_TX_DMA__DRQ_NUMBER EQU 5
SD_TX_DMA__NUMBEROF_TDS EQU 0
SD_TX_DMA__PRIORITY EQU 1
SD_TX_DMA__TERMIN_EN EQU 0
SD_TX_DMA__TERMIN_SEL EQU 0
SD_TX_DMA__TERMOUT0_EN EQU 1
-SD_TX_DMA__TERMOUT0_SEL EQU 3
+SD_TX_DMA__TERMOUT0_SEL EQU 5
SD_TX_DMA__TERMOUT1_EN EQU 0
SD_TX_DMA__TERMOUT1_SEL EQU 0
SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x100
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 8
SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
nNOR_HOLD__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
nNOR_HOLD__SLW EQU CYREG_PRT12_SLW
+/* NOR_RX_DMA */
+NOR_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+NOR_RX_DMA__DRQ_NUMBER EQU 0
+NOR_RX_DMA__NUMBEROF_TDS EQU 0
+NOR_RX_DMA__PRIORITY EQU 2
+NOR_RX_DMA__TERMIN_EN EQU 0
+NOR_RX_DMA__TERMIN_SEL EQU 0
+NOR_RX_DMA__TERMOUT0_EN EQU 1
+NOR_RX_DMA__TERMOUT0_SEL EQU 0
+NOR_RX_DMA__TERMOUT1_EN EQU 0
+NOR_RX_DMA__TERMOUT1_SEL EQU 0
+NOR_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+NOR_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+NOR_RX_DMA_COMPLETE__INTC_MASK EQU 0x02
+NOR_RX_DMA_COMPLETE__INTC_NUMBER EQU 1
+NOR_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+NOR_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+NOR_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+NOR_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* NOR_TX_DMA */
+NOR_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+NOR_TX_DMA__DRQ_NUMBER EQU 1
+NOR_TX_DMA__NUMBEROF_TDS EQU 0
+NOR_TX_DMA__PRIORITY EQU 2
+NOR_TX_DMA__TERMIN_EN EQU 0
+NOR_TX_DMA__TERMIN_SEL EQU 0
+NOR_TX_DMA__TERMOUT0_EN EQU 1
+NOR_TX_DMA__TERMOUT0_SEL EQU 1
+NOR_TX_DMA__TERMOUT1_EN EQU 0
+NOR_TX_DMA__TERMOUT1_SEL EQU 0
+NOR_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+NOR_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+NOR_TX_DMA_COMPLETE__INTC_MASK EQU 0x04
+NOR_TX_DMA_COMPLETE__INTC_NUMBER EQU 2
+NOR_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+NOR_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
+NOR_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+NOR_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
/* SCSI_Noise */
SCSI_Noise__0__AG EQU CYREG_PRT4_AG
SCSI_Noise__0__AMUX EQU CYREG_PRT4_AMUX
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST
/* Debug_Timer */
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
/* SCSI_RX_DMA */
SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_RX_DMA__DRQ_NUMBER EQU 0
+SCSI_RX_DMA__DRQ_NUMBER EQU 2
SCSI_RX_DMA__NUMBEROF_TDS EQU 0
SCSI_RX_DMA__PRIORITY EQU 2
SCSI_RX_DMA__TERMIN_EN EQU 0
SCSI_RX_DMA__TERMIN_SEL EQU 0
SCSI_RX_DMA__TERMOUT0_EN EQU 1
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0
+SCSI_RX_DMA__TERMOUT0_SEL EQU 2
SCSI_RX_DMA__TERMOUT1_EN EQU 0
SCSI_RX_DMA__TERMOUT1_SEL EQU 0
SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SCSI_TX_DMA */
SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_TX_DMA__DRQ_NUMBER EQU 1
+SCSI_TX_DMA__DRQ_NUMBER EQU 3
SCSI_TX_DMA__NUMBEROF_TDS EQU 0
SCSI_TX_DMA__PRIORITY EQU 2
SCSI_TX_DMA__TERMIN_EN EQU 0
SCSI_TX_DMA__TERMIN_SEL EQU 0
SCSI_TX_DMA__TERMOUT0_EN EQU 1
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1
+SCSI_TX_DMA__TERMOUT0_SEL EQU 3
SCSI_TX_DMA__TERMOUT1_EN EQU 0
SCSI_TX_DMA__TERMOUT1_SEL EQU 0
SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x40
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 6
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SCSI_RST_ISR */
SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RST_ISR__INTC_MASK EQU 0x02
-SCSI_RST_ISR__INTC_NUMBER EQU 1
+SCSI_RST_ISR__INTC_MASK EQU 0x08
+SCSI_RST_ISR__INTC_NUMBER EQU 3
SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SCSI_SEL_ISR */
SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_SEL_ISR__INTC_MASK EQU 0x08
-SCSI_SEL_ISR__INTC_NUMBER EQU 3
+SCSI_SEL_ISR__INTC_MASK EQU 0x20
+SCSI_SEL_ISR__INTC_NUMBER EQU 5
SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
+SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
/* SCSI_Glitch_Ctl */
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST
/* Miscellaneous */
BCLK__BUS_CLK__HZ EQU 50000000
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x0400
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
-CYDEV_INTR_RISING EQU 0x0000007F
+CYDEV_INTR_RISING EQU 0x000001FF
CYDEV_IS_EXPORTING_CODE EQU 0
CYDEV_IS_IMPORTING_CODE EQU 0
CYDEV_PROJ_TYPE EQU 2
CYIPBLOCK_S8_SAR_VERSION EQU 0
CYIPBLOCK_S8_SIO_VERSION EQU 0
CYIPBLOCK_S8_UDB_VERSION EQU 0
-DMA_CHANNELS_USED__MASK0 EQU 0x0000000F
+DMA_CHANNELS_USED__MASK0 EQU 0x0000003F
CYDEV_BOOTLOADER_ENABLE EQU 0
#endif /* INCLUDED_CYFITTERIAR_INC */
USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x80
-USBFS_ep_1__INTC_NUMBER EQU 7
+USBFS_ep_1__INTC_MASK EQU 0x200
+USBFS_ep_1__INTC_NUMBER EQU 9
USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x100
-USBFS_ep_2__INTC_NUMBER EQU 8
+USBFS_ep_2__INTC_MASK EQU 0x400
+USBFS_ep_2__INTC_NUMBER EQU 10
USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10
USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_3__INTC_MASK EQU 0x200
-USBFS_ep_3__INTC_NUMBER EQU 9
+USBFS_ep_3__INTC_MASK EQU 0x800
+USBFS_ep_3__INTC_NUMBER EQU 11
USBFS_ep_3__INTC_PRIOR_NUM EQU 7
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_11
USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_4__INTC_MASK EQU 0x400
-USBFS_ep_4__INTC_NUMBER EQU 10
+USBFS_ep_4__INTC_MASK EQU 0x2000
+USBFS_ep_4__INTC_NUMBER EQU 13
USBFS_ep_4__INTC_PRIOR_NUM EQU 7
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_13
USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
NOR_SO__SLW EQU CYREG_PRT15_SLW
; SDCard
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB04_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB04_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB04_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB04_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB04_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
; SD_SCK
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1
NOR_SCK__SLW EQU CYREG_PRT3_SLW
; NOR_SPI
-NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB04_CTL
-NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB04_CTL
-NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB04_MSK
-NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
-NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB04_MSK
-NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
-NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
-NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB04_ST
-NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
+NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
+NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
+NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
+NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
+NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
+NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
+NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
+NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10
NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4
NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20
NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40
NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6
NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70
-NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK
-NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST
+NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0
NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02
NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1
-NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
+NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04
NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2
NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08
NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10
NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4
NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F
-NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB03_MSK
-NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB03_ST
+NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
+NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
; SCSI_In
SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
NOR_Clock__PM_STBY_MSK EQU 0x01
; SD_RX_DMA
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_RX_DMA__DRQ_NUMBER EQU 2
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL1
+SD_RX_DMA__DRQ_NUMBER EQU 4
SD_RX_DMA__NUMBEROF_TDS EQU 0
SD_RX_DMA__PRIORITY EQU 0
SD_RX_DMA__TERMIN_EN EQU 0
SD_RX_DMA__TERMIN_SEL EQU 0
SD_RX_DMA__TERMOUT0_EN EQU 1
-SD_RX_DMA__TERMOUT0_SEL EQU 2
+SD_RX_DMA__TERMOUT0_SEL EQU 4
SD_RX_DMA__TERMOUT1_EN EQU 0
SD_RX_DMA__TERMOUT1_SEL EQU 0
SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x80
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 7
SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SD_TX_DMA
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_TX_DMA__DRQ_NUMBER EQU 3
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL1
+SD_TX_DMA__DRQ_NUMBER EQU 5
SD_TX_DMA__NUMBEROF_TDS EQU 0
SD_TX_DMA__PRIORITY EQU 1
SD_TX_DMA__TERMIN_EN EQU 0
SD_TX_DMA__TERMIN_SEL EQU 0
SD_TX_DMA__TERMOUT0_EN EQU 1
-SD_TX_DMA__TERMOUT0_SEL EQU 3
+SD_TX_DMA__TERMOUT0_SEL EQU 5
SD_TX_DMA__TERMOUT1_EN EQU 0
SD_TX_DMA__TERMOUT1_SEL EQU 0
SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x100
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 8
SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
nNOR_HOLD__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
nNOR_HOLD__SLW EQU CYREG_PRT12_SLW
+; NOR_RX_DMA
+NOR_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+NOR_RX_DMA__DRQ_NUMBER EQU 0
+NOR_RX_DMA__NUMBEROF_TDS EQU 0
+NOR_RX_DMA__PRIORITY EQU 2
+NOR_RX_DMA__TERMIN_EN EQU 0
+NOR_RX_DMA__TERMIN_SEL EQU 0
+NOR_RX_DMA__TERMOUT0_EN EQU 1
+NOR_RX_DMA__TERMOUT0_SEL EQU 0
+NOR_RX_DMA__TERMOUT1_EN EQU 0
+NOR_RX_DMA__TERMOUT1_SEL EQU 0
+NOR_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+NOR_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+NOR_RX_DMA_COMPLETE__INTC_MASK EQU 0x02
+NOR_RX_DMA_COMPLETE__INTC_NUMBER EQU 1
+NOR_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+NOR_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+NOR_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+NOR_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; NOR_TX_DMA
+NOR_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+NOR_TX_DMA__DRQ_NUMBER EQU 1
+NOR_TX_DMA__NUMBEROF_TDS EQU 0
+NOR_TX_DMA__PRIORITY EQU 2
+NOR_TX_DMA__TERMIN_EN EQU 0
+NOR_TX_DMA__TERMIN_SEL EQU 0
+NOR_TX_DMA__TERMOUT0_EN EQU 1
+NOR_TX_DMA__TERMOUT0_SEL EQU 1
+NOR_TX_DMA__TERMOUT1_EN EQU 0
+NOR_TX_DMA__TERMOUT1_SEL EQU 0
+NOR_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+NOR_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+NOR_TX_DMA_COMPLETE__INTC_MASK EQU 0x04
+NOR_TX_DMA_COMPLETE__INTC_NUMBER EQU 2
+NOR_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+NOR_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
+NOR_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+NOR_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
; SCSI_Noise
SCSI_Noise__0__AG EQU CYREG_PRT4_AG
SCSI_Noise__0__AMUX EQU CYREG_PRT4_AMUX
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST
; Debug_Timer
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
; SCSI_RX_DMA
SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_RX_DMA__DRQ_NUMBER EQU 0
+SCSI_RX_DMA__DRQ_NUMBER EQU 2
SCSI_RX_DMA__NUMBEROF_TDS EQU 0
SCSI_RX_DMA__PRIORITY EQU 2
SCSI_RX_DMA__TERMIN_EN EQU 0
SCSI_RX_DMA__TERMIN_SEL EQU 0
SCSI_RX_DMA__TERMOUT0_EN EQU 1
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0
+SCSI_RX_DMA__TERMOUT0_SEL EQU 2
SCSI_RX_DMA__TERMOUT1_EN EQU 0
SCSI_RX_DMA__TERMOUT1_SEL EQU 0
SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SCSI_TX_DMA
SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_TX_DMA__DRQ_NUMBER EQU 1
+SCSI_TX_DMA__DRQ_NUMBER EQU 3
SCSI_TX_DMA__NUMBEROF_TDS EQU 0
SCSI_TX_DMA__PRIORITY EQU 2
SCSI_TX_DMA__TERMIN_EN EQU 0
SCSI_TX_DMA__TERMIN_SEL EQU 0
SCSI_TX_DMA__TERMOUT0_EN EQU 1
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1
+SCSI_TX_DMA__TERMOUT0_SEL EQU 3
SCSI_TX_DMA__TERMOUT1_EN EQU 0
SCSI_TX_DMA__TERMOUT1_SEL EQU 0
SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x40
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 6
SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SCSI_RST_ISR
SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RST_ISR__INTC_MASK EQU 0x02
-SCSI_RST_ISR__INTC_NUMBER EQU 1
+SCSI_RST_ISR__INTC_MASK EQU 0x08
+SCSI_RST_ISR__INTC_NUMBER EQU 3
SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SCSI_SEL_ISR
SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_SEL_ISR__INTC_MASK EQU 0x08
-SCSI_SEL_ISR__INTC_NUMBER EQU 3
+SCSI_SEL_ISR__INTC_MASK EQU 0x20
+SCSI_SEL_ISR__INTC_NUMBER EQU 5
SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
+SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
; SCSI_Glitch_Ctl
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST
; Miscellaneous
BCLK__BUS_CLK__HZ EQU 50000000
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x0400
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
-CYDEV_INTR_RISING EQU 0x0000007F
+CYDEV_INTR_RISING EQU 0x000001FF
CYDEV_IS_EXPORTING_CODE EQU 0
CYDEV_IS_IMPORTING_CODE EQU 0
CYDEV_PROJ_TYPE EQU 2
CYIPBLOCK_S8_SAR_VERSION EQU 0
CYIPBLOCK_S8_SIO_VERSION EQU 0
CYIPBLOCK_S8_UDB_VERSION EQU 0
-DMA_CHANNELS_USED__MASK0 EQU 0x0000000F
+DMA_CHANNELS_USED__MASK0 EQU 0x0000003F
CYDEV_BOOTLOADER_ENABLE EQU 0
ENDIF
END
#include "nNOR_CS.h"
#include "nNOR_WP_aliases.h"
#include "nNOR_WP.h"
+#include "NOR_RX_DMA_dma.h"
+#include "NOR_TX_DMA_dma.h"
+#include "NOR_RX_DMA_COMPLETE.h"
+#include "NOR_TX_DMA_COMPLETE.h"
#include "USBFS_Dm_aliases.h"
#include "USBFS_Dm.h"
#include "USBFS_Dp_aliases.h"
<?xml version="1.0" encoding="utf-8"?>
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
- <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
- <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006479" bitWidth="8" desc="" hidden="false" />
+ <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" hidden="false" />
</block>
- <block name="TERM_EN" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646C" bitWidth="8" desc="" hidden="false" />
- <register name="SCSI_Parity_Error_MASK_REG" address="0x4000648C" bitWidth="8" desc="" hidden="false" />
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649C" bitWidth="8" desc="" hidden="false">
+ <block name="not_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="not_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="TERM_EN" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="not_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
+ <register name="SCSI_Filtered_STATUS_REG" address="0x40006468" bitWidth="8" desc="" hidden="false" />
+ <register name="SCSI_Filtered_MASK_REG" address="0x40006488" bitWidth="8" desc="" hidden="false" />
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006498" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</field>
</register>
</block>
- <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
- <register name="SCSI_Filtered_STATUS_REG" address="0x40006568" bitWidth="8" desc="" hidden="false" />
- <register name="SCSI_Filtered_MASK_REG" address="0x40006588" bitWidth="8" desc="" hidden="false" />
- <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006598" bitWidth="8" desc="" hidden="false">
+ <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006469" bitWidth="8" desc="" hidden="false" />
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x40006489" bitWidth="8" desc="" hidden="false" />
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006499" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</field>
</register>
</block>
- <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="not_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="NOR_SI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="nNOR_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="NOR_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="nNOR_HOLD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="Em_EEPROM_Dynamic" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="not_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="NOR_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="NOR_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="nNOR_WP" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_9" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="not_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="not_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="not_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="not_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="Em_EEPROM_Dynamic" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="NOR_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="NOR_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="nNOR_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="NOR_Clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="NOR_SO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="not_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="not_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="nNOR_HOLD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="NOR_SI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="NOR_SPI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
</block>
- <block name="not_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="NOR_Clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="NOR_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647F" bitWidth="8" desc="" hidden="false" />
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ </block>
+ <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true" hidden="false">
<block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />
</register>
</block>
- <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
- <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- </block>
- <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" hidden="false" />
- </block>
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
</block>
- <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000657A" bitWidth="8" desc="" hidden="false" />
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006579" bitWidth="8" desc="" hidden="false" />
+ </block>
+ <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" hidden="false" />
</block>
</blockRegMap>
\ No newline at end of file
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<filters />
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolderSerialize" version="3">
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<register>
<name>SCSI_Glitch_Ctl_CONTROL_REG</name>
<description>No description available</description>
- <addressOffset>0x40006479</addressOffset>
+ <addressOffset>0x4000647A</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
</registers>
</peripheral>
<peripheral>
- <name>SCSI_Parity_Error</name>
+ <name>SCSI_Filtered</name>
<description>No description available</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
</addressBlock>
<registers>
<register>
- <name>SCSI_Parity_Error_STATUS_REG</name>
+ <name>SCSI_Filtered_STATUS_REG</name>
<description>No description available</description>
- <addressOffset>0x4000646C</addressOffset>
+ <addressOffset>0x40006468</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
- <name>SCSI_Parity_Error_MASK_REG</name>
+ <name>SCSI_Filtered_MASK_REG</name>
<description>No description available</description>
- <addressOffset>0x4000648C</addressOffset>
+ <addressOffset>0x40006488</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
- <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
+ <name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>
<description>No description available</description>
- <addressOffset>0x4000649C</addressOffset>
+ <addressOffset>0x40006498</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
</registers>
</peripheral>
<peripheral>
- <name>SCSI_Filtered</name>
+ <name>SCSI_Parity_Error</name>
<description>No description available</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
</addressBlock>
<registers>
<register>
- <name>SCSI_Filtered_STATUS_REG</name>
+ <name>SCSI_Parity_Error_STATUS_REG</name>
<description>No description available</description>
- <addressOffset>0x40006568</addressOffset>
+ <addressOffset>0x40006469</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
- <name>SCSI_Filtered_MASK_REG</name>
+ <name>SCSI_Parity_Error_MASK_REG</name>
<description>No description available</description>
- <addressOffset>0x40006588</addressOffset>
+ <addressOffset>0x40006489</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
<register>
- <name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>
+ <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
<description>No description available</description>
- <addressOffset>0x40006598</addressOffset>
+ <addressOffset>0x40006499</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>SCSI_CTL_PHASE_CONTROL_REG</name>
<description>No description available</description>
- <addressOffset>0x4000647F</addressOffset>
+ <addressOffset>0x4000647B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
</register>
</registers>
</peripheral>
- <peripheral>
- <name>SCSI_Out_Ctl</name>
- <description>No description available</description>
- <baseAddress>0x0</baseAddress>
- <addressBlock>
- <offset>0</offset>
- <size>0x0</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>SCSI_Out_Ctl_CONTROL_REG</name>
- <description>No description available</description>
- <addressOffset>0x40006478</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- </registers>
- </peripheral>
<peripheral>
<name>Debug_Timer</name>
<description>No description available</description>
<register>
<name>SCSI_Out_Bits_CONTROL_REG</name>
<description>No description available</description>
- <addressOffset>0x4000657A</addressOffset>
+ <addressOffset>0x40006579</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>SCSI_Out_Ctl</name>
+ <description>No description available</description>
+ <baseAddress>0x0</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x0</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>SCSI_Out_Ctl_CONTROL_REG</name>
+ <description>No description available</description>
+ <addressOffset>0x40006478</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
projects / SCSI2SD.git / commitdiff