- Multi-sector SD card writes supported.
- Updated to PSoC Creator 3.0
- Partity checking is on
- Unit Attention Condition is off
-- Write performance is not adequate
- - Multi-sector SD commands are not yet supported.
- - DMA is not used for SPI transfers
+- DMA is not used for SPI transfers
Performance
As currently implemented:
-Sequential read: 250kb/sec Sequential write: 50kb/sec
-These numbers are dreadful. I am working on updating the slow polling SD card
-communication to use DMA. I expect the performance to reach 1.8Mb/sec.
+Sequential read: 250kb/sec Sequential write: 240kb/sec
+
+Tested with a 16GB class 10 SD card, via the commands:
+
+ # WRITE TEST
+ sudo dd bs=8192 count=100 if=/dev/zero of=/dev/sdX oflag=dsync
+
+ # READ TEST
+ sudo dd bs=8192 count=100 if=/dev/sdX of=/dev/null
+
+I am working on updating the slow polling SD card communication to use DMA. I expect the performance to reach 1Mb/sec.
Compatibility
--- /dev/null
+/*###ICF### Section handled by ICF editor, don't touch! ****/\r
+/*-Editor annotation file-*/\r
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */\r
+/*-Specials-*/\r
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;\r
+/*-Memory Regions-*/\r
+define symbol __ICFEDIT_region_ROM_start__ = 0x0;\r
+define symbol __ICFEDIT_region_ROM_end__ = 262144 - 1;\r
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (65536 / 2);\r
+define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + (65536 / 2) - 1;\r
+/*-Sizes-*/\r
+define symbol __ICFEDIT_size_cstack__ = 0x4000;\r
+define symbol __ICFEDIT_size_heap__ = 0x1000;\r
+/**** End of ICF editor section. ###ICF###*/\r
+\r
+\r
+/******** Definitions ********/\r
+define symbol CY_APPL_LOADABLE = 0;\r
+define symbol CY_APPL_LOADER = 0;\r
+define symbol CY_APPL_NUM = 1;\r
+define symbol CY_APPL_MAX = 1;\r
+define symbol CY_METADATA_SIZE = 64;\r
+define symbol CY_EE_IN_BTLDR = 0x0;\r
+define symbol CY_EE_SIZE = 2048;\r
+\r
+if (!CY_APPL_LOADABLE) {\r
+ define symbol CYDEV_BTLDR_SIZE = 0;\r
+}\r
+\r
+define symbol CY_FLASH_SIZE = 262144;\r
+define symbol CY_APPL_ORIGIN = 0; \r
+define symbol CY_FLASH_ROW_SIZE = 256;\r
+define symbol CY_ECC_ROW_SIZE = 32;\r
+\r
+define memory mem with size = 4G;\r
+define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];\r
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];\r
+\r
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };\r
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
+define block HSTACK {block HEAP, last block CSTACK};\r
+\r
+define block LOADER { readonly section .cybootloader };\r
+define block APPL with fixed order {readonly section .romvectors, readonly};\r
+\r
+/* The address of Flash row next after Bootloader image */\r
+define symbol CY_BTLDR_END = CYDEV_BTLDR_SIZE +\r
+ ((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ?\r
+ (CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0);\r
+\r
+/* The start address of Standard/Loader/Loadable#1 image */\r
+define symbol CY_APPL1_START = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : CY_BTLDR_END;\r
+\r
+/* The number of metadata records located at the end of Flash */\r
+define symbol CY_METADATA_CNT = (CY_APPL_NUM == 2) ? 2 : ((CY_APPL_LOADER || CY_APPL_LOADABLE) ? 1 : 0);\r
+\r
+/* The application area size measured in rows */\r
+define symbol CY_APPL_ROW_CNT = ((CY_FLASH_SIZE - CY_APPL1_START) / CY_FLASH_ROW_SIZE) - CY_METADATA_CNT;\r
+\r
+/* The start address of Loadable#2 image if any */\r
+define symbol CY_APPL2_START = CY_APPL1_START + (CY_APPL_ROW_CNT / 2 + CY_APPL_ROW_CNT % 2) * CY_FLASH_ROW_SIZE;\r
+\r
+/* The current image (Standard/Loader/Loadable) start address */\r
+define symbol CY_APPL_START = (CY_APPL_NUM == 1) ? CY_APPL1_START : CY_APPL2_START;\r
+\r
+/* The ECC data placement address */\r
+define exported symbol CY_ECC_OFFSET = (CY_APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE;\r
+\r
+/* The EEPROM offset and size that can be used by current application (Standard/Loader/Loadable) */\r
+define symbol CY_EE_OFFSET = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0;\r
+define symbol CY_EE_IN_USE = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE;\r
+\r
+/* Define EEPROM region */\r
+define region EEPROM_region = mem:[from (0x90200000 + CY_EE_OFFSET) size CY_EE_IN_USE];\r
+\r
+/* Define APPL region that will limit application size */\r
+define region APPL_region = mem:[from CY_APPL_START size CY_APPL_ROW_CNT * CY_FLASH_ROW_SIZE];\r
+\r
+\r
+/****** Initializations ******/\r
+initialize by copy { readwrite };\r
+do not initialize { section .noinit };\r
+do not initialize { readwrite section .ramvectors };\r
+\r
+/******** Placements *********/\r
+".cybootloader" : place at start of ROM_region {block LOADER};\r
+"APPL" : place at start of APPL_region {block APPL};\r
+\r
+"RAMVEC" : place at start of RAM_region { readwrite section .ramvectors };\r
+"readwrite" : place in RAM_region { readwrite };\r
+"HSTACK" : place at end of RAM_region { block HSTACK};\r
+\r
+keep { section .cybootloader, \r
+ section .cyloadermeta, \r
+ section .cyloadablemeta,\r
+ section .cyconfigecc, \r
+ section .cycustnvl, \r
+ section .cywolatch,\r
+ section .cyeeprom, \r
+ section .cyflashprotect,\r
+ section .cymeta };\r
+\r
+".cyloadermeta" : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };\r
+".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };\r
+".cyconfigecc" : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };\r
+".cycustnvl" : place at address mem : 0x90000000 { readonly section .cycustnvl };\r
+".cywolatch" : place at address mem : 0x90100000 { readonly section .cywolatch };\r
+".cyeeprom" : place in EEPROM_region { readonly section .cyeeprom };\r
+".cyflashprotect" : place at address mem : 0x90400000 { readonly section .cyflashprotect };\r
+".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };\r
+\r
+\r
+/* EOF */\r
+#! armcc -E\r
+; The first line specifies a preprocessor command that the linker invokes \r
+; to pass a scatter file through a C preprocessor.\r
+\r
;********************************************************************************\r
;* File Name: Cm3RealView.scat\r
-;* Version 3.40\r
+;* Version 4.0\r
;*\r
;* Description:\r
;* This Linker Descriptor file describes the memory layout of the PSoC5\r
;* disclaimers, and limitations in the end user license agreement accompanying\r
;* the software package with which this file was provided.\r
;********************************************************************************/\r
+#include "cyfitter.h"\r
+\r
+#define CY_FLASH_SIZE 262144\r
+#define CY_APPL_ORIGIN 0\r
+#define CY_FLASH_ROW_SIZE 256\r
+#define CY_ECC_ROW_SIZE 32\r
+#define CY_EE_SIZE 2048\r
+#define CY_METADATA_SIZE 64\r
+\r
+\r
+; Define application base address\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)\r
+ #define CY_APPL_NUM 1\r
+ #define CY_APPL_MAX 1\r
+ #define CY_EE_IN_BTLDR \r
+\r
+ #if CY_APPL_ORIGIN\r
+ #define APPL1_START CY_APPL_ORIGIN\r
+ #else\r
+ #define APPL1_START AlignExpr(ImageLimit(CYBOOTLOADER), CY_FLASH_ROW_SIZE)\r
+ #endif\r
+\r
+ #define APPL_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ) * (CY_APPL_NUM - 1), CY_FLASH_ROW_SIZE))\r
+ #define ECC_OFFSET ((APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE)\r
+ #define EE_OFFSET (CY_EE_IN_BTLDR ? 0 : (CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1))\r
+ #define EE_SIZE (CY_EE_IN_BTLDR ? CY_EE_SIZE : (CY_EE_SIZE / CY_APPL_MAX))\r
+\r
+#else\r
+\r
+ #define APPL_START 0\r
+ #define ECC_OFFSET 0\r
+ #define EE_OFFSET 0\r
+ #define EE_SIZE CY_EE_SIZE\r
+\r
+#endif\r
+\r
+\r
+; Place Bootloader at the beginning of Flash\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)\r
+\r
+ CYBOOTLOADER 0\r
+ {\r
+ .cybootloader +0\r
+ {\r
+ * (.cybootloader)\r
+ }\r
+ }\r
\r
-LOAD_ROM 0 (262144 - 0)\r
+ #if CY_APPL_ORIGIN\r
+ ScatterAssert(APPL_START > LoadLimit(CYBOOTLOADER))\r
+ #endif\r
+\r
+#endif\r
+\r
+\r
+APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START)\r
{\r
VECTORS +0\r
{\r
\r
DATA +0\r
{\r
- * (+RW, +ZI)\r
+ .ANY (+RW, +ZI)\r
}\r
\r
ARM_LIB_HEAP (0x20000000 + (65536 / 2) - 0x1000 - 0x4000) EMPTY 0x1000\r
{\r
}\r
}\r
+\r
+\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER)\r
+\r
+ CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE)\r
+ {\r
+ .cyloadermeta +0 { * (.cyloadermeta) }\r
+ }\r
+\r
+#else\r
+\r
+ #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)\r
+\r
+ CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE)\r
+ {\r
+ .cyloadablemeta +0 { * (.cyloadablemeta) }\r
+ }\r
+ \r
+ #endif\r
+\r
+#endif\r
+\r
+#if (CYDEV_ECC_ENABLE == 0)\r
+\r
+ CYCONFIGECC (0x80000000 + ECC_OFFSET)\r
+ {\r
+ .cyconfigecc +0 { * (.cyconfigecc) }\r
+ }\r
+\r
+#endif\r
+\r
+CYCUSTNVL 0x90000000\r
+{\r
+ .cycustnvl +0 { * (.cycustnvl) }\r
+}\r
+\r
+CYWOLATCH 0x90100000\r
+{\r
+ .cywolatch +0 { * (.cywolatch) }\r
+}\r
+\r
+#if defined(CYDEV_ALLOCATE_EEPROM)\r
+\r
+ CYEEPROM 0x90200000 + EE_OFFSET (EE_SIZE)\r
+ {\r
+ .cyeeprom +0 { * (.cyeeprom) }\r
+ }\r
+\r
+#endif\r
+\r
+CYFLASHPROTECT 0x90400000\r
+{\r
+ .cyflashprotect +0 { * (.cyflashprotect) }\r
+}\r
+\r
+CYMETA 0x90500000\r
+{\r
+ .cymeta +0 { * (.cymeta) }\r
+}\r
+\r
+#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)\r
+\r
+ CYLOADERMETA +0\r
+ {\r
+ .cyloadermeta +0 { * (.cyloadermeta) }\r
+ }\r
+\r
+#endif\r
/*******************************************************************************\r
* File Name: Cm3Start.c\r
-* Version 3.40\r
+* Version 4.0\r
*\r
* Description:\r
* Startup code for the ARM CM3.\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
+#include <limits.h>\r
#include "cydevice_trm.h"\r
#include "cytypes.h"\r
#include "cyfitter_cfg.h"\r
#include "CyDmac.h"\r
#include "cyfitter.h"\r
\r
-#define NUM_INTERRUPTS 32u\r
-#define NUM_VECTORS (CYINT_IRQ_BASE+NUM_INTERRUPTS)\r
-#define NUM_ROM_VECTORS 4u\r
-#define NVIC_APINT ((reg32 *) CYREG_NVIC_APPLN_INTR)\r
-#define NVIC_CFG_CTRL ((reg32 *) CYREG_NVIC_CFG_CONTROL)\r
-#define NVIC_APINT_PRIGROUP_3_5 0x00000400u /* Priority group 3.5 split */\r
-#define NVIC_APINT_VECTKEY 0x05FA0000u /* This key is required in order to write the NVIC_APINT register */\r
-#define NVIC_CFG_STACKALIGN 0x00000200u /* This specifies that the exception stack must be 8 byte aligned */\r
+#define CY_NUM_INTERRUPTS (32u)\r
+#define CY_NUM_VECTORS (CYINT_IRQ_BASE + CY_NUM_INTERRUPTS)\r
+#define CY_NUM_ROM_VECTORS (4u)\r
+#define CY_NVIC_APINT_PTR ((reg32 *) CYREG_NVIC_APPLN_INTR)\r
+#define CY_NVIC_CFG_CTRL_PTR ((reg32 *) CYREG_NVIC_CFG_CONTROL)\r
+#define CY_NVIC_APINT_PRIGROUP_3_5 (0x00000400u) /* Priority group 3.5 split */\r
+#define CY_NVIC_APINT_VECTKEY (0x05FA0000u) /* This key is required in order to write the NVIC_APINT register */\r
+#define CY_NVIC_CFG_STACKALIGN (0x00000200u) /* This specifies that the exception stack must be 8 byte aligned */\r
+\r
\r
/* Extern functions */\r
extern void CyBtldr_CheckLaunch(void);\r
CY_ISR(IntDefaultHandler);\r
\r
#if defined(__ARMCC_VERSION)\r
- #define INITIAL_STACK_POINTER (cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit\r
+ #define INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit)\r
#elif defined (__GNUC__)\r
- #define INITIAL_STACK_POINTER __cs3_stack\r
+ #define INITIAL_STACK_POINTER (&__cy_stack)\r
+#elif defined (__ICCARM__)\r
+ #pragma language=extended\r
+ #pragma segment="CSTACK"\r
+ #define INITIAL_STACK_POINTER { .__ptr = __sfe( "CSTACK" ) }\r
+\r
+ extern void __iar_program_start( void );\r
+ extern void __iar_data_init3 (void);\r
#endif /* (__ARMCC_VERSION) */\r
\r
/* Global variables */\r
-CY_NOINIT static uint32 cySysNoInitDataValid;\r
+#if !defined (__ICCARM__)\r
+ CY_NOINIT static uint32 cySysNoInitDataValid;\r
+#endif /* !defined (__ICCARM__) */\r
\r
\r
/*******************************************************************************\r
* Default Ram Interrupt Vector table storage area. Must be 256-byte aligned.\r
*******************************************************************************/\r
-\r
-__attribute__ ((section(".ramvectors")))\r
-#if defined(__ARMCC_VERSION)\r
-__align(256)\r
-#elif defined (__GNUC__)\r
-__attribute__ ((aligned(256)))\r
-#endif\r
-cyisraddress CyRamVectors[NUM_VECTORS];\r
+#if defined (__ICCARM__)\r
+ #pragma location=".ramvectors"\r
+ #pragma data_alignment=256\r
+#else\r
+ CY_SECTION(".ramvectors")\r
+ CY_ALIGN(256)\r
+#endif /* defined (__ICCARM__) */\r
+cyisraddress CyRamVectors[CY_NUM_VECTORS];\r
\r
\r
/*******************************************************************************\r
* None\r
*\r
*******************************************************************************/\r
-__asm void Reset(void)\r
+void Reset(void)\r
{\r
- PRESERVE8\r
- EXTERN __main\r
- EXTERN CyResetStatus\r
-\r
- #if(CYDEV_BOOTLOADER_ENABLE)\r
- EXTERN CyBtldr_CheckLaunch\r
- #endif /* (CYDEV_BOOTLOADER_ENABLE) */\r
-\r
-\r
#if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)\r
- #if(CYDEV_DEBUGGING_ENABLE)\r
- ldr r3, =0x400046e8 /* CYDEV_DEBUG_ENABLE_REGISTER */\r
- ldrb r4, [r3, #0]\r
- orr r4, r4, #01\r
- strb r4, [r3, #0]\r
-debugEnabled\r
- #endif /* (CYDEV_DEBUGGING_ENABLE) */\r
\r
- ldr r3, =0x400046fa /* CYREG_RESET_SR0 */\r
- ldrb r2, [r3, #0]\r
+ /* For PSoC 5LP, debugging is enabled by default */\r
+ #if(CYDEV_DEBUGGING_ENABLE == 0)\r
+ *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;\r
+ #endif /* (CYDEV_DEBUGGING_ENABLE) */\r
\r
- #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */\r
+ /* Reset Status Register has Read-to-clear SW access mode.\r
+ * Preserve current RESET_SR0 state to make it available for next reading.\r
+ */\r
+ *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);\r
\r
- ldr r3, =0x400076BC /* CYREG_PHUB_CFGMEM23_CFG1 */\r
- strb r2, [r3, #0]\r
+ #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */\r
\r
#if(CYDEV_BOOTLOADER_ENABLE)\r
- bl CyBtldr_CheckLaunch\r
+ CyBtldr_CheckLaunch();\r
#endif /* (CYDEV_BOOTLOADER_ENABLE) */\r
\r
- /* Let RealView setup the libraries. */\r
- bl __main\r
-\r
- ALIGN\r
+ __main();\r
}\r
\r
\r
/* Call original main */\r
$Super$$main();\r
\r
- /* If main returns it is undefined what we should do. */\r
- while (1);\r
+ while (1)\r
+ {\r
+ /* If main returns it is undefined what we should do. */\r
+ }\r
}\r
\r
#elif defined(__GNUC__)\r
\r
-extern void __cs3_stack(void);\r
-extern void __cs3_start_c(void);\r
+void Start_c(void);\r
+\r
+/* Stack Base address */\r
+extern void __cy_stack(void);\r
+\r
+/* Application entry point. */\r
+extern int main(void);\r
+\r
+/* The static objects constructors initializer */\r
+extern void __libc_init_array(void);\r
+\r
+typedef unsigned char __cy_byte_align8 __attribute ((aligned (8)));\r
+\r
+struct __cy_region\r
+{\r
+ __cy_byte_align8 *init; /* Initial contents of this region. */\r
+ __cy_byte_align8 *data; /* Start address of region. */\r
+ size_t init_size; /* Size of initial data. */\r
+ size_t zero_size; /* Additional size to be zeroed. */\r
+};\r
+\r
+extern const struct __cy_region __cy_regions[];\r
+extern const char __cy_region_num __attribute__((weak));\r
+#define __cy_region_num ((size_t)&__cy_region_num)\r
\r
\r
/*******************************************************************************\r
********************************************************************************\r
*\r
* Summary:\r
-* This function handles the reset interrupt for the GCC toolchain. This is the\r
+* This function handles the reset interrupt for the GCC toolchain. This is the\r
* first bit of code that is executed at startup.\r
*\r
* Parameters:\r
* None\r
*\r
*******************************************************************************/\r
-__attribute__ ((naked))\r
void Reset(void)\r
{\r
- __asm volatile(\r
-#if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)\r
-\r
- #if(CYDEV_DEBUGGING_ENABLE)\r
- " ldr r3, =%0\n"\r
- " ldrb r4, [r3, #0]\n"\r
- " orr r4, r4, #01\n"\r
- " strb r4, [r3, #0]\n"\r
- "debugEnabled:\n"\r
- #endif /* (CYDEV_DEBUGGING_ENABLE) */\r
-\r
- " ldr r3, =%1\n"\r
- " ldrb r2, [r3, #0]\n"\r
- " uxtb r2, r2\n"\r
-#endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */\r
-\r
- " ldr r3, =%2\n"\r
- " strb r2, [r3, #0]\n"\r
-\r
-#if(CYDEV_BOOTLOADER_ENABLE)\r
- " bl CyBtldr_CheckLaunch\n"\r
-#endif /* (CYDEV_BOOTLOADER_ENABLE) */\r
-\r
- /* Switch to C initialization phase */\r
- " bl __cs3_start_c\n" : : "i" (CYDEV_DEBUG_ENABLE_REGISTER), "i" (CYREG_RESET_SR0), "i" (CYREG_PHUB_CFGMEM23_CFG1));\r
+ #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)\r
+\r
+ /* For PSoC 5LP, debugging is enabled by default */\r
+ #if(CYDEV_DEBUGGING_ENABLE == 0)\r
+ *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;\r
+ #endif /* (CYDEV_DEBUGGING_ENABLE) */\r
+\r
+ /* Reset Status Register has Read-to-clear SW access mode.\r
+ * Preserve current RESET_SR0 state to make it available for next reading.\r
+ */\r
+ *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);\r
+\r
+ #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */\r
+\r
+ #if(CYDEV_BOOTLOADER_ENABLE)\r
+ CyBtldr_CheckLaunch();\r
+ #endif /* (CYDEV_BOOTLOADER_ENABLE) */\r
+\r
+ Start_c();\r
+}\r
+\r
+__attribute__((weak))\r
+void _exit(int status)\r
+{\r
+ /* Cause a divide by 0 exception */\r
+ int x = status / INT_MAX;\r
+ x = 4 / x;\r
+\r
+ while(1)\r
+ {\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name: Start_c\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* This function handles initializing the .data and .bss sections in\r
+* preperation for running standard C code. Once initialization is complete\r
+* it will call main(). This function will never return.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void Start_c(void) __attribute__ ((noreturn));\r
+void Start_c(void)\r
+{\r
+ unsigned regions = __cy_region_num;\r
+ const struct __cy_region *rptr = __cy_regions;\r
+\r
+ /* Initialize memory */\r
+ for (regions = __cy_region_num, rptr = __cy_regions; regions--; rptr++)\r
+ {\r
+ uint32 *src = (uint32 *)rptr->init;\r
+ uint32 *dst = (uint32 *)rptr->data;\r
+ unsigned limit = rptr->init_size;\r
+ unsigned count;\r
+\r
+ for (count = 0u; count != limit; count += sizeof (uint32))\r
+ {\r
+ *dst++ = *src++;\r
+ }\r
+ limit = rptr->zero_size;\r
+ for (count = 0u; count != limit; count += sizeof (uint32))\r
+ {\r
+ *dst++ = 0u;\r
+ }\r
+ }\r
+\r
+ /* Invoke static objects constructors */\r
+ __libc_init_array();\r
+ (void) main();\r
+\r
+ while (1)\r
+ {\r
+ /* If main returns, make sure we don't return. */\r
+ }\r
+}\r
+\r
+\r
+#elif defined (__ICCARM__)\r
+\r
+/*******************************************************************************\r
+* Function Name: __low_level_init\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* This function perform early initializations for the IAR Embedded\r
+* Workbench IDE. It is executed in the context of reset interrupt handler\r
+* before the data sections are initialized.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* The value that determines whether or not data sections should be initialized\r
+* by the system startup code:\r
+* 0 - skip data sections initialization;\r
+* 1 - initialize data sections;\r
+*\r
+*******************************************************************************/\r
+int __low_level_init(void)\r
+{\r
+ #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)\r
+\r
+ /* For PSoC 5LP, debugging is enabled by default */\r
+ #if(CYDEV_DEBUGGING_ENABLE == 0)\r
+ *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;\r
+ #endif /* (CYDEV_DEBUGGING_ENABLE) */\r
+\r
+ /* Reset Status Register has Read-to-clear SW access mode.\r
+ * Preserve current RESET_SR0 state to make it available for next reading.\r
+ */\r
+ *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);\r
+\r
+ #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */\r
+\r
+ #if (CYDEV_BOOTLOADER_ENABLE)\r
+ CyBtldr_CheckLaunch();\r
+ #endif /* CYDEV_BOOTLOADER_ENABLE */\r
+\r
+ /* Initialize data sections */\r
+ __iar_data_init3();\r
+\r
+ initialize_psoc();\r
+\r
+ return 0;\r
}\r
\r
#endif /* __GNUC__ */\r
*\r
*******************************************************************************/\r
#if defined(__ARMCC_VERSION)\r
+ /* Suppress diagnostic message 1296-D: extended constant initialiser used */\r
#pragma diag_suppress 1296\r
-#endif\r
-__attribute__ ((section(".romvectors")))\r
-const cyisraddress RomVectors[NUM_ROM_VECTORS] =\r
+#endif /* defined(__ARMCC_VERSION) */\r
+\r
+#if defined (__ICCARM__)\r
+ #pragma location=".romvectors"\r
+ const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] =\r
+#else\r
+ CY_SECTION(".romvectors")\r
+ const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =\r
+#endif /* defined (__ICCARM__) */\r
{\r
- #if defined(__ARMCC_VERSION)\r
- INITIAL_STACK_POINTER, /* The initial stack pointer 0 */\r
- #elif defined (__GNUC__)\r
- &INITIAL_STACK_POINTER, /* The initial stack pointer 0 */\r
- #endif /* (__ARMCC_VERSION) */\r
- (cyisraddress)&Reset, /* The reset handler 1 */\r
+ INITIAL_STACK_POINTER, /* The initial stack pointer 0 */\r
+ #if defined (__ICCARM__) /* The reset handler 1 */\r
+ __iar_program_start,\r
+ #else\r
+ (cyisraddress)&Reset,\r
+ #endif /* defined (__ICCARM__) */\r
&IntDefaultHandler, /* The NMI handler 2 */\r
&IntDefaultHandler, /* The hard fault handler 3 */\r
};\r
\r
+#if defined(__ARMCC_VERSION)\r
+ #pragma diag_default 1296\r
+#endif /* defined(__ARMCC_VERSION) */\r
+\r
\r
/*******************************************************************************\r
* Function Name: initialize_psoc\r
#if (defined(__GNUC__) && !defined(__ARMCC_VERSION))\r
__attribute__ ((constructor(101)))\r
#endif\r
-\r
void initialize_psoc(void)\r
{\r
uint32 i;\r
/* Set Priority group 5. */\r
\r
/* Writes to NVIC_APINT register require the VECTKEY in the upper half */\r
- *NVIC_APINT = NVIC_APINT_VECTKEY | NVIC_APINT_PRIGROUP_3_5;\r
- *NVIC_CFG_CTRL |= NVIC_CFG_STACKALIGN;\r
+ *CY_NVIC_APINT_PTR = CY_NVIC_APINT_VECTKEY | CY_NVIC_APINT_PRIGROUP_3_5;\r
+ *CY_NVIC_CFG_CTRL_PTR |= CY_NVIC_CFG_STACKALIGN;\r
\r
/* Set Ram interrupt vectors to default functions. */\r
- for(i = 0u; i < NUM_VECTORS; i++)\r
+ for (i = 0u; i < CY_NUM_VECTORS; i++)\r
{\r
- CyRamVectors[i] = (i < NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler;\r
+ #if defined (__ICCARM__)\r
+ CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? __vector_table[i].__fun : &IntDefaultHandler;\r
+ #else\r
+ CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler;\r
+ #endif /* defined (__ICCARM__) */\r
}\r
\r
/* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */\r
CyDmacConfigure();\r
\r
#endif /* (0u != DMA_CHANNELS_USED__MASK0) */\r
- \r
- /* Actually, no need to clean this variable, just to make compiler happy. */\r
- cySysNoInitDataValid = 0u;\r
+\r
+ #if !defined (__ICCARM__)\r
+ /* Actually, no need to clean this variable, just to make compiler happy. */\r
+ cySysNoInitDataValid = 0u;\r
+ #endif /* !defined (__ICCARM__) */\r
}\r
\r
\r
/*******************************************************************************\r
* File Name: CyBootAsmGnu.s\r
-* Version 3.40\r
+* Version 4.0\r
*\r
* Description:\r
* Assembly routines for GNU as.\r
* the software package with which this file was provided.\r
*******************************************************************************/\r
\r
+.include "cyfittergnu.inc"\r
+\r
.syntax unified\r
.text\r
.thumb\r
.type CyDelayCycles, %function\r
.thumb_func\r
CyDelayCycles: /* cycles bytes */\r
- ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */\r
- LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */\r
- BEQ CyDelayCycles_done /* 2 2 Skip if 0 */\r
- NOP /* 1 2 Loop alignment padding */\r
+/* If ICache is enabled */\r
+.ifeq CYDEV_INSTRUCT_CACHE_ENABLED - 1\r
+\r
+ ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */\r
+ LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */\r
+ BEQ CyDelayCycles_done /* 2 2 Skip if 0 */\r
+ NOP /* 1 2 Loop alignment padding */\r
+\r
+CyDelayCycles_loop:\r
+ SUBS r0, r0, #1 /* 1 2 */\r
+ MOV r0, r0 /* 1 2 Pad loop to power of two cycles */\r
+ BNE CyDelayCycles_loop /* 2 2 */\r
+\r
+CyDelayCycles_done:\r
+ BX lr /* 3 2 */\r
+\r
+.else\r
+\r
+ CMP r0, #20 /* 1 2 If delay is short - jump to cycle */\r
+ BLS CyDelayCycles_short /* 1 2 */\r
+ PUSH {r1} /* 2 2 PUSH r1 to stack */\r
+ MOVS r1, #1 /* 1 2 */\r
+\r
+ SUBS r0, r0, #20 /* 1 2 Subtract overhead */\r
+ LDR r1,=CYREG_CACHE_CC_CTL/* 2 2 Load flash wait cycles value */\r
+ LDRB r1, [r1, #0] /* 2 2 */\r
+ ANDS r1, #0xC0 /* 1 2 */\r
+\r
+ LSRS r1, r1, #6 /* 1 2 */\r
+ PUSH {r2} /* 1 2 PUSH r2 to stack */\r
+ LDR r2, =cy_flash_cycles /* 2 2 */\r
+ LDRB r1, [r2, r1] /* 2 2 */\r
+\r
+ POP {r2} /* 2 2 POP r2 from stack */\r
+ NOP /* 1 2 Alignment padding */\r
+ NOP /* 1 2 Alignment padding */\r
+ NOP /* 1 2 Alignment padding */\r
+\r
CyDelayCycles_loop:\r
- SUBS r0, r0, #1 /* 1 2 */\r
- MOV r0, r0 /* 1 2 Pad loop to power of two cycles */\r
- BNE CyDelayCycles_loop /* 2 2 */\r
+ SBCS r0, r0, r1 /* 1 2 */\r
+ BPL CyDelayCycles_loop /* 3 2 */\r
+ NOP /* 1 2 Loop alignment padding */\r
+ NOP /* 1 2 Loop alignment padding */\r
+\r
+ POP {r1} /* 2 2 POP r1 from stack */\r
CyDelayCycles_done:\r
- BX lr /* 3 2 */\r
+ BX lr /* 3 2 */\r
+ NOP /* 1 2 Alignment padding */\r
+ NOP /* 1 2 Alignment padding */\r
+\r
+CyDelayCycles_short:\r
+ SBCS r0, r0, #4 /* 1 2 */\r
+ BPL CyDelayCycles_short /* 3 2 */\r
+ BX lr /* 3 2 */\r
+\r
+cy_flash_cycles:\r
+.byte 0x0B\r
+.byte 0x05\r
+.byte 0x07\r
+.byte 0x09\r
+.endif\r
+\r
.endfunc\r
\r
\r
.type CyEnterCriticalSection, %function\r
.thumb_func\r
CyEnterCriticalSection:\r
- MRS r0, PRIMASK /* Save and return interrupt state */\r
- CPSID I /* Disable interrupts */\r
- BX lr\r
+ MRS r0, PRIMASK /* Save and return interrupt state */\r
+ CPSID I /* Disable interrupts */\r
+ BX lr\r
.endfunc\r
\r
\r
.type CyExitCriticalSection, %function\r
.thumb_func\r
CyExitCriticalSection:\r
- MSR PRIMASK, r0 /* Restore interrupt state */\r
- BX lr\r
+ MSR PRIMASK, r0 /* Restore interrupt state */\r
+ BX lr\r
.endfunc\r
\r
.end\r
--- /dev/null
+;-------------------------------------------------------------------------------\r
+; FILENAME: CyBootAsmIar.s\r
+; Version 4.0\r
+;\r
+; DESCRIPTION:\r
+; Assembly routines for IAR Embedded Workbench IDE.\r
+;\r
+;-------------------------------------------------------------------------------\r
+; Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; You may use this file only in accordance with the license, terms, conditions,\r
+; disclaimers, and limitations in the end user license agreement accompanying\r
+; the software package with which this file was provided.\r
+;-------------------------------------------------------------------------------\r
+\r
+ SECTION .text:CODE:ROOT(4)\r
+ PUBLIC CyDelayCycles\r
+ PUBLIC CyEnterCriticalSection\r
+ PUBLIC CyExitCriticalSection\r
+ INCLUDE cyfitteriar.inc\r
+ THUMB\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Function Name: CyEnterCriticalSection\r
+;-------------------------------------------------------------------------------\r
+;\r
+; Summary:\r
+; CyEnterCriticalSection disables interrupts and returns a value indicating\r
+; whether interrupts were previously enabled.\r
+;\r
+; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit\r
+; with interrupts still enabled. The test and set of the interrupt bits is not\r
+; atomic. Therefore, to avoid corrupting processor state, it must be the policy \r
+; that all interrupt routines restore the interrupt enable bits as they were \r
+; found on entry.\r
+;\r
+; Parameters:\r
+; None\r
+;\r
+; Return:\r
+; uint8\r
+; Returns 0 if interrupts were previously enabled or 1 if interrupts\r
+; were previously disabled.\r
+;\r
+;-------------------------------------------------------------------------------\r
+; uint8 CyEnterCriticalSection(void)\r
+\r
+CyEnterCriticalSection:\r
+ MRS r0, PRIMASK ; Save and return interrupt state\r
+ CPSID I ; Disable interrupts\r
+ BX lr\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Function Name: CyExitCriticalSection\r
+;-------------------------------------------------------------------------------\r
+;\r
+; Summary:\r
+; CyExitCriticalSection re-enables interrupts if they were enabled before\r
+; CyEnterCriticalSection was called. The argument should be the value returned\r
+; from CyEnterCriticalSection.\r
+;\r
+; Parameters:\r
+; uint8 savedIntrStatus:\r
+; Saved interrupt status returned by the CyEnterCriticalSection function.\r
+;\r
+; Return:\r
+; None\r
+;\r
+;-------------------------------------------------------------------------------\r
+; void CyExitCriticalSection(uint8 savedIntrStatus)\r
+\r
+CyExitCriticalSection:\r
+ MSR PRIMASK, r0 ; Restore interrupt state\r
+ BX lr\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Function Name: CyDelayCycles\r
+;-------------------------------------------------------------------------------\r
+;\r
+; Summary:\r
+; Delays for the specified number of cycles.\r
+;\r
+; Parameters:\r
+; uint32 cycles: number of cycles to delay.\r
+;\r
+; Return:\r
+; None\r
+;\r
+;-------------------------------------------------------------------------------\r
+; void CyDelayCycles(uint32 cycles)\r
+\r
+CyDelayCycles: \r
+ IF CYDEV_INSTRUCT_CACHE_ENABLED == 1\r
+ ; cycles bytes\r
+ ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4\r
+ LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags\r
+ BEQ CyDelayCycles_done ; 2 2 Skip if 0\r
+ NOP ; 1 2 Loop alignment padding\r
+CyDelayCycles_loop:\r
+ SUBS r0, r0, #1 ; 1 2\r
+ MOV r0, r0 ; 1 2 Pad loop to power of two cycles\r
+ BNE CyDelayCycles_loop ; 2 2\r
+CyDelayCycles_done:\r
+ BX lr ; 3 2\r
+ \r
+ ELSE\r
+ \r
+ CMP r0, #20 ; 1 2 If delay is short - jump to cycle\r
+ BLS CyDelayCycles_short ; 1 2\r
+ PUSH {r1} ; 2 2 PUSH r1 to stack\r
+ MOVS r1, #1 ; 1 2\r
+\r
+ SUBS r0, r0, #20 ; 1 2 Subtract overhead\r
+ LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value\r
+ LDRB r1, [r1, #0] ; 2 2\r
+ ANDS r1, r1, #0xC0 ; 1 2\r
+\r
+ LSRS r1, r1, #6 ; 1 2\r
+ PUSH {r2} ; 1 2 PUSH r2 to stack\r
+ LDR r2, =cy_flash_cycles ; 2 2\r
+ LDRB r1, [r2, r1] ; 2 2\r
+\r
+ POP {r2} ; 2 2 POP r2 from stack\r
+ NOP ; 1 2 Alignment padding\r
+ NOP ; 1 2 Alignment padding\r
+ NOP ; 1 2 Alignment padding\r
+\r
+CyDelayCycles_loop:\r
+ SBCS r0, r0, r1 ; 1 2\r
+ BPL CyDelayCycles_loop ; 3 2\r
+ NOP ; 1 2 Loop alignment padding\r
+ NOP ; 1 2 Loop alignment padding\r
+\r
+ POP {r1} ; 2 2 POP r1 from stack\r
+CyDelayCycles_done:\r
+ BX lr ; 3 2\r
+ NOP ; 1 2 Alignment padding\r
+ NOP ; 1 2 Alignment padding\r
+CyDelayCycles_short:\r
+ SBCS r0, r0, #4 ; 1 2\r
+ BPL CyDelayCycles_short ; 3 2\r
+ BX lr ; 3 2\r
+ NOP ; 1 2 Loop alignment padding\r
+\r
+ DATA\r
+cy_flash_cycles:\r
+byte_1 DCB 0x0B\r
+byte_2 DCB 0x05\r
+byte_3 DCB 0x07\r
+byte_4 DCB 0x09\r
+\r
+ ENDIF\r
+\r
+ END\r
;-------------------------------------------------------------------------------\r
; FILENAME: CyBootAsmRv.s\r
-; Version 3.40\r
+; Version 4.0\r
;\r
; DESCRIPTION:\r
; Assembly routines for RealView.\r
; the software package with which this file was provided.\r
;-------------------------------------------------------------------------------\r
\r
- AREA |.text|,CODE,ALIGN=3\r
- THUMB\r
- EXTERN Reset\r
+ AREA |.text|,CODE,ALIGN=3\r
+ THUMB\r
+ EXTERN Reset\r
+\r
+ GET cyfitterrv.inc\r
\r
;-------------------------------------------------------------------------------\r
; Function Name: CyDelayCycles\r
;\r
;-------------------------------------------------------------------------------\r
; void CyDelayCycles(uint32 cycles)\r
- ALIGN 8\r
+ ALIGN 8\r
CyDelayCycles FUNCTION\r
- EXPORT CyDelayCycles\r
- ; cycles bytes\r
- ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4\r
- LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags\r
- BEQ CyDelayCycles_done ; 2 2 Skip if 0\r
- NOP ; 1 2 Loop alignment padding\r
+ EXPORT CyDelayCycles\r
+ IF CYDEV_INSTRUCT_CACHE_ENABLED == 1\r
+ ; cycles bytes\r
+ ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4\r
+ LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags\r
+ BEQ CyDelayCycles_done ; 2 2 Skip if 0\r
+ NOP ; 1 2 Loop alignment padding\r
CyDelayCycles_loop\r
- SUBS r0, r0, #1 ; 1 2\r
- MOV r0, r0 ; 1 2 Pad loop to power of two cycles\r
- BNE CyDelayCycles_loop ; 2 2\r
+ SUBS r0, r0, #1 ; 1 2\r
+ MOV r0, r0 ; 1 2 Pad loop to power of two cycles\r
+ BNE CyDelayCycles_loop ; 2 2\r
+ NOP ; 1 2 Loop alignment padding\r
CyDelayCycles_done\r
- BX lr ; 3 2\r
- ENDFUNC\r
+ BX lr ; 3 2\r
+\r
+ ELSE\r
+\r
+ CMP r0, #20 ; 1 2 If delay is short - jump to cycle\r
+ BLS CyDelayCycles_short ; 1 2\r
+ PUSH {r1} ; 2 2 PUSH r1 to stack\r
+ MOVS r1, #1 ; 1 2\r
+\r
+ SUBS r0, r0, #20 ; 1 2 Subtract overhead\r
+ LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value\r
+ LDRB r1, [r1, #0] ; 2 2\r
+ ANDS r1, #0xC0 ; 1 2\r
+\r
+ LSRS r1, r1, #6 ; 1 2\r
+ PUSH {r2} ; 1 2 PUSH r2 to stack\r
+ LDR r2, =cy_flash_cycles ; 2 2\r
+ LDRB r1, [r2, r1] ; 2 2\r
+\r
+ POP {r2} ; 2 2 POP r2 from stack\r
+ NOP ; 1 2 Alignment padding\r
+ NOP ; 1 2 Alignment padding\r
+ NOP ; 1 2 Alignment padding\r
+\r
+CyDelayCycles_loop\r
+ SBCS r0, r0, r1 ; 1 2\r
+ BPL CyDelayCycles_loop ; 3 2\r
+ NOP ; 1 2 Loop alignment padding\r
+ NOP ; 1 2 Loop alignment padding\r
+\r
+ POP {r1} ; 2 2 POP r1 from stack\r
+CyDelayCycles_done\r
+ BX lr ; 3 2\r
+ NOP ; 1 2 Alignment padding\r
+ NOP ; 1 2 Alignment padding\r
+\r
+CyDelayCycles_short\r
+ SBCS r0, r0, #4 ; 1 2\r
+ BPL CyDelayCycles_short ; 3 2\r
+ BX lr ; 3 2\r
+\r
+cy_flash_cycles\r
+byte_1 DCB 0x0B\r
+byte_2 DCB 0x05\r
+byte_3 DCB 0x07\r
+byte_4 DCB 0x09\r
+\r
+ ENDIF\r
+ ENDFUNC\r
\r
\r
;-------------------------------------------------------------------------------\r
;-------------------------------------------------------------------------------\r
; uint8 CyEnterCriticalSection(void)\r
CyEnterCriticalSection FUNCTION\r
- EXPORT CyEnterCriticalSection\r
- MRS r0, PRIMASK ; Save and return interrupt state\r
- CPSID I ; Disable interrupts\r
- BX lr\r
- ENDFUNC\r
+ EXPORT CyEnterCriticalSection\r
+ MRS r0, PRIMASK ; Save and return interrupt state\r
+ CPSID I ; Disable interrupts\r
+ BX lr\r
+ ENDFUNC\r
\r
\r
;-------------------------------------------------------------------------------\r
;-------------------------------------------------------------------------------\r
; void CyExitCriticalSection(uint8 savedIntrStatus)\r
CyExitCriticalSection FUNCTION\r
- EXPORT CyExitCriticalSection\r
- MSR PRIMASK, r0 ; Restore interrupt state\r
- BX lr\r
- ENDFUNC\r
+ EXPORT CyExitCriticalSection\r
+ MSR PRIMASK, r0 ; Restore interrupt state\r
+ BX lr\r
+ ENDFUNC\r
\r
- END\r
+ END\r
\r
; [] END OF FILE\r
/*******************************************************************************\r
* File Name: CyDmac.c\r
-* Version 3.40\r
+* Version 4.0\r
*\r
* Description:\r
* Provides an API for the DMAC component. The API includes functions for the\r
\r
#include "CyDmac.h"\r
\r
-static uint8 CyDmaTdCurrentNumber; /* Current Number of free elements in the list */\r
-static uint8 CyDmaTdFreeIndex; /* Index of the first available TD */\r
-static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0; /* Bit map of DMA channel ownership */\r
+\r
+/*******************************************************************************\r
+* The following variables are initialized from CyDmacConfigure() function that\r
+* is executed from initialize_psoc() at the early initialization stage.\r
+* In case of IAR EW IDE, initialize_psoc() is executed before the data sections\r
+* are initialized. To avoid zeroing, these variables should be initialized\r
+* properly during segments initialization as well.\r
+*******************************************************************************/\r
+static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free elements in the list */\r
+static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of the first available TD */\r
+static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0; /* Bit map of DMA channel ownership */\r
\r
\r
/*******************************************************************************\r
uint8 dmaIndex;\r
\r
/* Set TD list variables. */\r
- CyDmaTdFreeIndex = ((uint8) (CY_DMA_NUMBEROF_TDS - 1u));\r
+ CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u);\r
CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;\r
\r
/* Make TD free list. */\r
- for(dmaIndex = ((uint8)(CY_DMA_NUMBEROF_TDS - 1u)); dmaIndex != 0u; dmaIndex--)\r
+ for(dmaIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); dmaIndex != 0u; dmaIndex--)\r
{\r
- CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = ((uint8)(dmaIndex - 1u));\r
+ CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u);\r
}\r
\r
/* Make the last one point to zero. */\r
\r
if(chHandle < CY_DMA_NUMBEROF_CHANNELS)\r
{\r
- CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] =\r
- (CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~0x20u))) | ((0u != preserveTds) ? 0x21u : 0x01u);\r
+ if (0u != preserveTds)\r
+ {\r
+ /* Store the intermediate TD states separately in CHn_SEP_TD0/1 to\r
+ * preserve the original TD chain\r
+ */\r
+ CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP;\r
+ }\r
+ else\r
+ {\r
+ /* Store the intermediate and final TD states on top of the original TD chain */\r
+ CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP);\r
+ }\r
+\r
+ /* Enable channel */\r
+ CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_EN;\r
+\r
status = CYRET_SUCCESS;\r
}\r
\r
\r
if(chHandle < CY_DMA_NUMBEROF_CHANNELS)\r
{\r
- CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~0x21u));\r
+ /***********************************************************************\r
+ * Should not change configuration information of a DMA channel when it\r
+ * is active (or vulnerable to becoming active).\r
+ ***********************************************************************/\r
+\r
+ /* Disable channel */\r
+ CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN));\r
+\r
+ /* Store the intermediate and final TD states on top of the original TD chain */\r
+ CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP));\r
status = CYRET_SUCCESS;\r
}\r
\r
\r
{\r
cystatus status = CYRET_BAD_PARAM;\r
+ reg16 *convert;\r
\r
#if(CY_PSOC5)\r
\r
if(chHandle < CY_DMA_NUMBEROF_CHANNELS)\r
{\r
/* Set source address */\r
- reg16 *convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[0];\r
+ convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[0];\r
CY_SET_REG16(convert, source);\r
\r
/* Set destination address */\r
- CY_SET_REG16((reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[2], destination);\r
+ convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[2u];\r
+ CY_SET_REG16(convert, destination);\r
status = CYRET_SUCCESS;\r
}\r
\r
\r
if(chHandle < CY_DMA_NUMBEROF_CHANNELS)\r
{\r
- status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] & \r
+ status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] &\r
(uint32)(CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN));\r
}\r
\r
cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) \r
{\r
cystatus status = CYRET_BAD_PARAM;\r
+ reg16 *convert;\r
\r
if(tdHandle < CY_DMA_NUMBEROF_TDS)\r
{\r
/* Set source address */\r
- reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0];\r
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u];\r
CY_SET_REG16(convert, source);\r
\r
/* Set destination address */\r
- CY_SET_REG16((reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2], destination);\r
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u];\r
+ CY_SET_REG16(convert, destination);\r
\r
status = CYRET_SUCCESS;\r
}\r
cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) \r
{\r
cystatus status = CYRET_BAD_PARAM;\r
+ reg16 *convert;\r
\r
if(tdHandle < CY_DMA_NUMBEROF_TDS)\r
{\r
if(NULL != source)\r
{\r
/* Get source address */\r
- reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0];\r
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u];\r
*source = CY_GET_REG16(convert);\r
}\r
\r
if(NULL != destination)\r
{\r
/* Get Destination address. */\r
- *destination = CY_GET_REG16((reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2]);\r
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u];\r
+ *destination = CY_GET_REG16(convert);\r
}\r
\r
status = CYRET_SUCCESS;\r
\r
if(chHandle < CY_DMA_NUMBEROF_CHANNELS)\r
{\r
- CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] =\r
- (CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~CY_DMA_ROUND_ROBIN_ENABLE))) |\r
- ((0u != enableRR) ? CY_DMA_ROUND_ROBIN_ENABLE : ((uint8)(~CY_DMA_ROUND_ROBIN_ENABLE)));\r
+ if (0u != enableRR)\r
+ {\r
+ CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= (uint8)CY_DMA_ROUND_ROBIN_ENABLE;\r
+ }\r
+ else\r
+ {\r
+ CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_ROUND_ROBIN_ENABLE);\r
+ }\r
\r
status = CYRET_SUCCESS;\r
}\r
/*******************************************************************************\r
* File Name: CyDmac.h\r
-* Version 3.40\r
+* Version 4.0\r
*\r
* Description:\r
* Provides the function definitions for the DMA Controller.\r
cystatus CyDmaChDisable(uint8 chHandle) ;\r
cystatus CyDmaClearPendingDrq(uint8 chHandle) ;\r
cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) ;\r
-cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination);\r
+cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination)\\r
+;\r
cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) ;\r
cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) ;\r
cystatus CyDmaChGetRequest(uint8 chHandle) ;\r
cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) ;\r
-cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0, uint8 tdDone1, uint8 tdStop) ;\r
+cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0,\r
+ uint8 tdDone1, uint8 tdStop) ;\r
cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) ;\r
\r
/* Transfer Descriptor functions. */\r
uint8 CyDmaTdAllocate(void) ;\r
void CyDmaTdFree(uint8 tdHandle) ;\r
uint8 CyDmaTdFreeCount(void) ;\r
-cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration) ;\r
-cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration) ;\r
+cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration)\\r
+;\r
+cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration)\\r
+;\r
cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) ;\r
cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) ;\r
\r
#define CY_DMA_INVALID_CHANNEL 0xFFu /* Invalid Channel ID */\r
#define CY_DMA_INVALID_TD 0xFFu /* Invalid TD */\r
#define CY_DMA_END_CHAIN_TD 0xFFu /* End of chain TD */\r
-\r
-#if(CY_PSOC3 || CY_PSOC5LP)\r
- #define CY_DMA_DISABLE_TD 0xFEu\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+#define CY_DMA_DISABLE_TD 0xFEu\r
\r
#define CY_DMA_TD_SIZE 0x08u\r
\r
#define CY_DMA_ROUND_ROBIN_ENABLE ((uint8)(1u << 4u))\r
\r
\r
+/*******************************************************************************\r
+* CyDmaChEnable() / CyDmaChDisable() API constants\r
+*******************************************************************************/\r
+#define CY_DMA_CH_BASIC_CFG_EN (0x01u)\r
+#define CY_DMA_CH_BASIC_CFG_WORK_SEP (0x20u)\r
+\r
+\r
/***************************************\r
* Registers\r
***************************************/\r
#define DMAC_UNPOP_ACC (CY_DMA_UNPOP_ACC)\r
#define DMAC_PERIPH_ERR (CY_DMA_PERIPH_ERR)\r
#define ROUND_ROBIN_ENABLE (CY_DMA_ROUND_ROBIN_ENABLE)\r
-#if(CY_PSOC3 || CY_PSOC5LP)\r
- #define DMA_DISABLE_TD (CY_DMA_DISABLE_TD)\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+#define DMA_DISABLE_TD (CY_DMA_DISABLE_TD)\r
\r
#define DMAC_CFG (CY_DMA_CFG_PTR)\r
#define DMAC_ERR (CY_DMA_ERR_PTR)\r
/*******************************************************************************\r
* File Name: CyFlash.c\r
-* Version 3.40\r
+* Version 4.0\r
*\r
* Description:\r
* Provides an API for the FLASH/EEPROM.\r
********************************************************************************\r
*\r
* Summary:\r
-* Enable the EEPROM/Flash.\r
-*\r
-* Note: For PSoC 5, this will enable both Flash and EEPROM. For PSoC 3 and\r
-* PSOC 5LP this will enable only Flash.\r
+* Enable the Flash.\r
*\r
* Parameters:\r
* None\r
*******************************************************************************/\r
void CyFlash_Start(void) \r
{\r
- #if(CY_PSOC5A)\r
-\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_EE_MASK;\r
-\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_EE_MASK;\r
-\r
- #endif /* (CY_PSOC5A) */\r
-\r
- #if(CY_PSOC3 || CY_PSOC5LP)\r
+ /* Active Power Mode */\r
+ *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;\r
\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;\r
-\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;\r
-\r
- #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+ /* Standby Power Mode */\r
+ *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;\r
\r
CyDelayUs(CY_FLASH_EE_STARTUP_DELAY);\r
}\r
********************************************************************************\r
*\r
* Summary:\r
-* Disable the EEPROM/Flash.\r
-*\r
-* Note:\r
-* PSoC 5: disable both Flash and EEPROM.\r
-* PSoC 3 and PSOC 5LP: disable only Flash. Use CyEEPROM_Stop() to stop EEPROM.\r
+* Disable the Flash.\r
*\r
* Parameters:\r
* None\r
*******************************************************************************/\r
void CyFlash_Stop(void) \r
{\r
- #if (CY_PSOC5A)\r
+ /* Active Power Mode */\r
+ *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));\r
\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_EE_MASK));\r
-\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_EE_MASK));\r
-\r
- #endif /* (CY_PSOC5A) */\r
-\r
- #if (CY_PSOC3 || CY_PSOC5LP)\r
-\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));\r
-\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));\r
-\r
- #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+ /* Standby Power Mode */\r
+ *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));\r
}\r
\r
\r
if(CySpcLock() == CYRET_SUCCESS)\r
{\r
/* Write the command. */\r
- #if(CY_PSOC5A)\r
- if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES, CY_TEMP_TIMER_PERIOD, CY_TEMP_CLK_DIV_SELECT))\r
- #else\r
- if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES))\r
- #endif /* (CY_PSOC5A) */\r
+ if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES))\r
+ {\r
+ do\r
{\r
- do\r
+ if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE)\r
{\r
- if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE)\r
- {\r
- status = CYRET_SUCCESS;\r
+ status = CYRET_SUCCESS;\r
\r
- while(CY_SPC_BUSY)\r
- {\r
- /* Spin until idle. */\r
- CyDelayUs(1u);\r
- }\r
- break;\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Spin until idle. */\r
+ CyDelayUs(1u);\r
}\r
+ break;\r
+ }\r
\r
- } while(CY_SPC_BUSY);\r
- }\r
+ } while(CY_SPC_BUSY);\r
+ }\r
\r
- CySpcUnlock();\r
+ CySpcUnlock();\r
}\r
else\r
{\r
********************************************************************************\r
*\r
* Summary:\r
- * Sends a command to the SPC to load and program a row of data in flash.\r
+ * Sends a command to the SPC to load and program a row of data in\r
+ * Flash or EEPROM.\r
*\r
* Parameters:\r
- * arrayID:\r
- * ID of the array to write.\r
- * rowAddress:\r
- * rowAddress of flash row to program.\r
- * rowData:\r
- * Array of bytes to write.\r
+ * arrayID: ID of the array to write.\r
+ * The type of write, Flash or EEPROM, is determined from the array ID.\r
+ * The arrays in the part are sequential starting at the first ID for the\r
+ * specific memory type. The array ID for the Flash memory lasts from 0x00 to\r
+ * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.\r
+ * rowAddress: rowAddress of flash row to program.\r
+ * rowData: Array of bytes to write.\r
*\r
* Return:\r
* status:\r
********************************************************************************\r
*\r
* Summary:\r
- * Sends a command to the SPC to load and program a row of data in flash.\r
+ * Sends a command to the SPC to load and program a row of data in\r
+ * Flash or EEPROM.\r
*\r
* Parameters:\r
* arrayID : ID of the array to write.\r
+ * The type of write, Flash or EEPROM, is determined from the array ID.\r
+ * The arrays in the part are sequential starting at the first ID for the\r
+ * specific memory type. The array ID for the Flash memory lasts from 0x00 to\r
+ * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.\r
* rowAddress : rowAddress of flash row to program.\r
* rowData : Array of bytes to write.\r
*\r
uint16 rowSize;\r
cystatus status;\r
\r
- rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? \\r
- CYDEV_EEPROM_ROW_SIZE : \\r
- (CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);\r
-\r
- if(rowSize != CYDEV_EEPROM_ROW_SIZE)\r
+ /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */\r
+ if(NULL != rowBuffer)\r
{\r
- /* Save the ECC area. */\r
- offset = CYDEV_ECC_BASE + ((uint32) arrayId * CYDEV_ECC_SECTOR_SIZE) +\r
- ((uint32) rowAddress * CYDEV_ECC_ROW_SIZE);\r
-\r
- for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)\r
+ if(arrayId > CY_SPC_LAST_FLASH_ARRAYID)\r
{\r
- *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i));\r
+ rowSize = CYDEV_EEPROM_ROW_SIZE;\r
}\r
- }\r
+ else\r
+ {\r
+ rowSize = CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE;\r
\r
- /* Copy the rowdata to the temporary buffer. */\r
+ /* Save the ECC area. */\r
+ offset = CYDEV_ECC_BASE +\r
+ ((uint32)arrayId * CYDEV_ECC_SECTOR_SIZE) +\r
+ ((uint32)rowAddress * CYDEV_ECC_ROW_SIZE);\r
+\r
+ for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)\r
+ {\r
+ *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i));\r
+ }\r
+ }\r
+\r
+ /* Copy the rowdata to the temporary buffer. */\r
#if(CY_PSOC3)\r
(void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE);\r
#else\r
(void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE);\r
#endif /* (CY_PSOC3) */\r
\r
- status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize);\r
+ status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize);\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
\r
return(status);\r
}\r
* This function is only valid for Flash array IDs (not for EEPROM).\r
*\r
* Parameters:\r
- * arrayId:\r
- * ID of the array to write\r
- * rowAddress:\r
- * Address of the sector to erase.\r
- * rowECC:\r
- * Array of bytes to write.\r
+ * arrayId: ID of the array to write\r
+ * The arrays in the part are sequential starting at the first ID for the\r
+ * specific memory type. The array ID for the Flash memory lasts\r
+ * from 0x00 to 0x3F.\r
+ * rowAddress: Address of the sector to erase.\r
+ * rowECC: Array of bytes to write.\r
*\r
* Return:\r
* status:\r
* CYRET_UNKNOWN if there was an SPC error.\r
*\r
*******************************************************************************/\r
- cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) \r
+ cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\\r
+ \r
{\r
uint32 offset;\r
uint16 i;\r
cystatus status;\r
\r
- /* Read the existing flash data. */\r
- offset = ((uint32) arrayId * CYDEV_FLS_SECTOR_SIZE) +\r
- ((uint32) rowAddress * CYDEV_FLS_ROW_SIZE);\r
- \r
- #if (CYDEV_FLS_BASE != 0u)\r
- offset += CYDEV_FLS_BASE;\r
- #endif\r
-\r
- for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)\r
+ /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */\r
+ if(NULL != rowBuffer)\r
{\r
- rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i));\r
- }\r
+ /* Read the existing flash data. */\r
+ offset = ((uint32)arrayId * CYDEV_FLS_SECTOR_SIZE) +\r
+ ((uint32)rowAddress * CYDEV_FLS_ROW_SIZE);\r
\r
- #if(CY_PSOC3)\r
- (void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (void *)((uint32)rowECC), (int16) CYDEV_ECC_ROW_SIZE);\r
- #else\r
- (void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (const void *) rowECC, CYDEV_ECC_ROW_SIZE);\r
- #endif /* (CY_PSOC3) */\r
+ #if (CYDEV_FLS_BASE != 0u)\r
+ offset += CYDEV_FLS_BASE;\r
+ #endif /* (CYDEV_FLS_BASE != 0u) */\r
\r
- status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);\r
+ for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)\r
+ {\r
+ rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i));\r
+ }\r
+\r
+ #if(CY_PSOC3)\r
+ (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],\r
+ (void *)(uint32)rowECC,\r
+ (int16)CYDEV_ECC_ROW_SIZE);\r
+ #else\r
+ (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],\r
+ (const void *)rowECC,\r
+ CYDEV_ECC_ROW_SIZE);\r
+ #endif /* (CY_PSOC3) */\r
+\r
+ status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
\r
return (status);\r
}\r
* Function Name: CyWriteRowFull\r
********************************************************************************\r
* Summary:\r
-* Sends a command to the SPC to load and program a row of data in flash.\r
-* rowData array is expected to contain Flash and ECC data if needed.\r
+* Sends a command to the SPC to load and program a row of data in flash.\r
+* rowData array is expected to contain Flash and ECC data if needed.\r
*\r
* Parameters:\r
-* arrayId: FLASH or EEPROM array id.\r
-* rowData: pointer to a row of data to write.\r
-* rowNumber: Zero based number of the row.\r
-* rowSize: Size of the row.\r
+* arrayId: FLASH or EEPROM array id.\r
+* rowData: Pointer to a row of data to write.\r
+* rowNumber: Zero based number of the row.\r
+* rowSize: Size of the row.\r
*\r
* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_LOCKED if the SPC is already in use.\r
-* CYRET_CANCELED if command not accepted\r
-* CYRET_UNKNOWN if there was an SPC error.\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_LOCKED if the SPC is already in use.\r
+* CYRET_CANCELED if command not accepted\r
+* CYRET_UNKNOWN if there was an SPC error.\r
*\r
*******************************************************************************/\r
cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \\r
#endif /* (CY_PSOC3) */\r
\r
\r
- #if (CY_PSOC5A)\r
+ #if (CY_PSOC5)\r
\r
if (freq <= 16u)\r
{\r
((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
}\r
\r
- #endif /* (CY_PSOC5A) */\r
-\r
-\r
- #if (CY_PSOC5LP)\r
-\r
- if (freq <= 16u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else if (freq <= 33u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else if (freq <= 50u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
-\r
- #endif /* (CY_PSOC5LP) */\r
+ #endif /* (CY_PSOC5) */\r
\r
/* Restore global interrupt enable state */\r
CyExitCriticalSection(interruptState);\r
}\r
\r
\r
-#if (CY_PSOC3 || CY_PSOC5LP)\r
-\r
- /*******************************************************************************\r
- * Function Name: CyEEPROM_Start\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Enable the EEPROM.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- *******************************************************************************/\r
- void CyEEPROM_Start(void) \r
- {\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;\r
-\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;\r
- }\r
+/*******************************************************************************\r
+* Function Name: CyEEPROM_Start\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enable the EEPROM.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyEEPROM_Start(void) \r
+{\r
+ /* Active Power Mode */\r
+ *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;\r
\r
+ /* Standby Power Mode */\r
+ *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;\r
+}\r
\r
- /*******************************************************************************\r
- * Function Name: CyEEPROM_Stop\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Disable the EEPROM.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- *******************************************************************************/\r
- void CyEEPROM_Stop (void) \r
- {\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));\r
\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));\r
- }\r
+/*******************************************************************************\r
+* Function Name: CyEEPROM_Stop\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disable the EEPROM.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyEEPROM_Stop (void) \r
+{\r
+ /* Active Power Mode */\r
+ *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));\r
\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+ /* Standby Power Mode */\r
+ *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));\r
+}\r
\r
\r
/*******************************************************************************\r
/*******************************************************************************\r
* File Name: CyFlash.h\r
-* Version 3.40\r
+* Version 4.0\r
*\r
* Description:\r
* Provides the function definitions for the FLASH/EEPROM.\r
void CyFlash_SetWaitCycles(uint8 freq) ;\r
\r
/* EEPROM Functions */\r
-#if (CY_PSOC3 || CY_PSOC5LP)\r
- void CyEEPROM_Start(void) ;\r
- void CyEEPROM_Stop(void) ;\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+void CyEEPROM_Start(void) ;\r
+void CyEEPROM_Stop(void) ;\r
\r
void CyEEPROM_ReadReserve(void) ;\r
void CyEEPROM_ReadRelease(void) ;\r
/***************************************\r
* Registers\r
***************************************/\r
+/* Active Power Mode Configuration Register 12 */\r
+#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12)\r
+#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)\r
\r
-#if (CY_PSOC5A)\r
-\r
- /* Active Power Mode Configuration Register 0 */\r
- #define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG0)\r
- #define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)\r
-\r
- /* Alternate Active Power Mode Configuration Register 0 */\r
- #define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG0)\r
- #define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG0)\r
-\r
-#endif /* (CY_PSOC5A) */\r
-\r
-\r
-#if (CY_PSOC3 || CY_PSOC5LP)\r
-\r
- /* Active Power Mode Configuration Register 12 */\r
- #define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12)\r
- #define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)\r
-\r
- /* Alternate Active Power Mode Configuration Register 12 */\r
- #define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12)\r
- #define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)\r
-\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+/* Alternate Active Power Mode Configuration Register 12 */\r
+#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12)\r
+#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)\r
\r
\r
/* Cache Control Register */\r
***************************************/\r
\r
/* Power Mode Masks */\r
-#if(CY_PSOC5A)\r
-\r
- #define CY_FLASH_PM_FLASH_EE_MASK (0x80u)\r
-\r
-#endif /* (CY_PSOC5A) */\r
-\r
-#if (CY_PSOC3 || CY_PSOC5LP)\r
-\r
- #define CY_FLASH_PM_EE_MASK (0x10u)\r
- #define CY_FLASH_PM_FLASH_MASK (0x01u)\r
-\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
-\r
+#define CY_FLASH_PM_EE_MASK (0x10u)\r
+#define CY_FLASH_PM_FLASH_MASK (0x01u)\r
\r
/* Frequency Constants */\r
#if (CY_PSOC3)\r
\r
#endif /* (CY_PSOC3) */\r
\r
-#if (CY_PSOC5A)\r
-\r
- #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)\r
- #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)\r
- #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)\r
- #define CY_FLASH_GREATER_51MHz (0x00u)\r
-\r
-#endif /* (CY_PSOC5A) */\r
-\r
-#if (CY_PSOC5LP)\r
+#if (CY_PSOC5)\r
\r
#define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)\r
#define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)\r
#define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)\r
#define CY_FLASH_GREATER_51MHz (0x00u)\r
\r
-#endif /* (CY_PSOC5LP) */\r
+#endif /* (CY_PSOC5) */\r
\r
#define CY_FLASH_CYCLES_MASK_SHIFT (0x06u)\r
#define CY_FLASH_CYCLES_MASK ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))\r
#define ECC_ADDR (0x80u)\r
\r
\r
-#if (CY_PSOC5A)\r
-\r
- #define PM_ACT_EEFLASH (CY_FLASH_PM_ACT_EEFLASH_PTR)\r
- #define PM_STBY_EEFLASH (CY_FLASH_PM_ALTACT_EEFLASH_PTR)\r
-\r
-#endif /* (CY_PSOC5A) */\r
-\r
-#if (CY_PSOC3 || CY_PSOC5LP)\r
-\r
- #define PM_ACT_EE_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR)\r
- #define PM_ACT_FLASH_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR)\r
-\r
- #define PM_STBY_EE_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR)\r
- #define PM_STBY_FLASH_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR)\r
-\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
-\r
-\r
-#if(CY_PSOC5A)\r
-\r
- #define PM_FLASH_EE_MASK (CY_FLASH_PM_FLASH_EE_MASK)\r
+#define PM_ACT_EE_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR)\r
+#define PM_ACT_FLASH_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR)\r
\r
-#endif /* (CY_PSOC5A) */\r
-\r
-#if (CY_PSOC3 || CY_PSOC5LP)\r
-\r
- #define PM_EE_MASK (CY_FLASH_PM_EE_MASK)\r
- #define PM_FLASH_MASK (CY_FLASH_PM_FLASH_MASK)\r
-\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+#define PM_STBY_EE_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR)\r
+#define PM_STBY_FLASH_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR)\r
\r
+#define PM_EE_MASK (CY_FLASH_PM_EE_MASK)\r
+#define PM_FLASH_MASK (CY_FLASH_PM_FLASH_MASK)\r
\r
#define FLASH_CYCLES_MASK_SHIFT (CY_FLASH_CYCLES_MASK_SHIFT)\r
#define FLASH_CYCLES_MASK (CY_FLASH_CYCLES_MASK)\r
\r
#endif /* (CY_PSOC3) */\r
\r
-#if (CY_PSOC5A)\r
-\r
- #define LESSER_OR_EQUAL_16MHz (CY_FLASH_LESSER_OR_EQUAL_16MHz)\r
- #define LESSER_OR_EQUAL_33MHz (CY_FLASH_LESSER_OR_EQUAL_33MHz)\r
- #define LESSER_OR_EQUAL_50MHz (CY_FLASH_LESSER_OR_EQUAL_50MHz)\r
- #define GREATER_51MHz (CY_FLASH_GREATER_51MHz)\r
-\r
-#endif /* (CY_PSOC5A) */\r
-\r
-#if (CY_PSOC5LP)\r
+#if (CY_PSOC5)\r
\r
#define LESSER_OR_EQUAL_16MHz (CY_FLASH_LESSER_OR_EQUAL_16MHz)\r
#define LESSER_OR_EQUAL_33MHz (CY_FLASH_LESSER_OR_EQUAL_33MHz)\r
#define GREATER_67MHz (CY_FLASH_GREATER_67MHz)\r
#define GREATER_51MHz (CY_FLASH_GREATER_51MHz)\r
\r
-#endif /* (CY_PSOC5LP) */\r
+#endif /* (CY_PSOC5) */\r
\r
#define AHUB_EE_REQ_ACK_PTR (CY_FLASH_EE_SCR_PTR)\r
\r
/*******************************************************************************\r
* File Name: CyLib.c\r
-* Version 3.40\r
+* Version 4.0\r
*\r
* Description:\r
* Provides system API for the clocking, interrupts and watchdog timer.\r
\r
/*******************************************************************************\r
* The CyResetStatus variable is used to obtain value of RESET_SR0 register after\r
-* a device reset.\r
+* a device reset. It is set from initialize_psoc() at the early initialization\r
+* stage. In case of IAR EW IDE, initialize_psoc() is executed before the data\r
+* sections are initialized. To avoid zeroing, CyResetStatus should be placed\r
+* to the .noinit section.\r
*******************************************************************************/\r
-uint8 CYXDATA CyResetStatus;\r
+CY_NOINIT uint8 CYXDATA CyResetStatus;\r
\r
\r
-#if(!CY_PSOC5A)\r
+/* Variable Vdda */\r
+#if(CYDEV_VARIABLE_VDDA == 1)\r
\r
- /* Variable Vdda */\r
- #if(CYDEV_VARIABLE_VDDA == 1)\r
+ uint8 CyScPumpEnabled = (uint8)(CYDEV_VDDA_MV < 2700);\r
\r
- uint8 CyScPumpEnabled = (uint8)(CYDEV_VDDA_MV < 2700);\r
-\r
- #endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
-\r
-#endif /* (!CY_PSOC5A) */\r
+#endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
\r
\r
/* Do not use these definitions directly in your application */\r
if(wait != 0u)\r
{\r
/* Save 100 KHz ILO, FTW interval, enable and interrupt enable */\r
- iloEnableState = SLOWCLK_ILO_CR0;\r
- pmTwCfg0State = CY_PM_TW_CFG0_REG;\r
- pmTwCfg2State = CY_PM_TW_CFG2_REG;\r
+ iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;\r
+ pmTwCfg0State = CY_LIB_PM_TW_CFG0_REG;\r
+ pmTwCfg2State = CY_LIB_PM_TW_CFG2_REG;\r
\r
CyPmFtwSetInterval(CY_CLK_PLL_FTW_INTERVAL);\r
\r
status = CYRET_TIMEOUT;\r
\r
-\r
- while(CyPmReadStatus(CY_PM_FTW_INT) != CY_PM_FTW_INT)\r
+ while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))\r
{\r
/* Wait for the interrupt status */\r
if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))\r
}\r
}\r
\r
-\r
/* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */\r
- if(0u == (iloEnableState & ILO_CONTROL_100KHZ_ON))\r
+ if(0u == iloEnableState)\r
{\r
CyILO_Stop100K();\r
}\r
- CY_PM_TW_CFG0_REG = pmTwCfg0State;\r
- CY_PM_TW_CFG2_REG = pmTwCfg2State;\r
+\r
+ CY_LIB_PM_TW_CFG0_REG = pmTwCfg0State;\r
+ CY_LIB_PM_TW_CFG2_REG = pmTwCfg2State;\r
}\r
\r
return(status);\r
*\r
* Parameters:\r
* source: One of the three available PLL clock sources\r
-* 0 : IMO\r
-* 1 : MHz Crystal\r
-* 2 : DSI\r
+* CY_PLL_SOURCE_IMO : IMO\r
+* CY_PLL_SOURCE_XTAL : MHz Crystal\r
+* CY_PLL_SOURCE_DSI : DSI\r
*\r
* Return:\r
* None\r
{\r
uint8 pmFtwCfg2Reg;\r
uint8 pmFtwCfg0Reg;\r
- uint8 iloControlReg;\r
+ uint8 ilo100KhzEnable;\r
+\r
\r
- /* Set the bit to enable the clock. */\r
- PM_ACT_CFG0 |= IMO_PM_ENABLE;\r
+ CY_LIB_PM_ACT_CFG0_REG |= CY_LIB_PM_ACT_CFG0_IMO_EN;\r
+ CY_LIB_PM_STBY_CFG0_REG |= CY_LIB_PM_STBY_CFG0_IMO_EN;\r
\r
- /* Wait for 6 us */\r
if(0u != wait)\r
{\r
/* Need to turn on the 100KHz ILO if it happens to not already be running.*/\r
- iloControlReg = SLOWCLK_ILO_CR0;\r
-\r
- if(0u == (iloControlReg & ILO_CONTROL_100KHZ_ON))\r
- {\r
- CyILO_Start100K();\r
- }\r
-\r
- /* Use ILO 100 KHz */\r
- pmFtwCfg2Reg = PM_TW_CFG2;\r
- pmFtwCfg0Reg = PM_TW_CFG0;\r
-\r
- /* FTW_EN (bit 0) must be clear to change the period*/\r
- PM_TW_CFG2 &= FTW_CLEAR_FTW_BITS;\r
-\r
- /* Set the FTW interval of 1 100KHz ILO clocks\r
- Should result in status getting set at a (100/1)KHz rate*/\r
- PM_TW_CFG0 = 0u;\r
+ ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;\r
+ pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG;\r
+ pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG;\r
\r
- /* Enable FTW, but not the interrupt */\r
- PM_TW_CFG2 = FTW_ENABLE;\r
+ CyPmFtwSetInterval(CY_LIB_CLK_IMO_FTW_TIMEOUT);\r
\r
- /* Read FTW value */\r
- while (CyPmReadStatus(CY_PM_FTW_INT) == 0u)\r
+ while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))\r
{\r
/* Wait for the interrupt status */\r
}\r
\r
- /* Reset the clock */\r
- if(0u == (iloControlReg & ILO_CONTROL_100KHZ_ON))\r
+ if(0u == ilo100KhzEnable)\r
{\r
CyILO_Stop100K();\r
}\r
\r
- /* Restore the FTW */\r
- PM_TW_CFG0 = pmFtwCfg0Reg;\r
- PM_TW_CFG2 = pmFtwCfg2Reg;\r
+ CY_LIB_PM_TW_CFG0_REG = pmFtwCfg0Reg;\r
+ CY_LIB_PM_TW_CFG2_REG = pmFtwCfg2Reg;\r
}\r
}\r
\r
*******************************************************************************/\r
void CyIMO_Stop(void) \r
{\r
- /* Clear the bit to disable the clock. */\r
- PM_ACT_CFG0 &= ((uint8)(~IMO_PM_ENABLE));\r
+ CY_LIB_PM_ACT_CFG0_REG &= ((uint8) (~CY_LIB_PM_ACT_CFG0_IMO_EN));\r
+ CY_LIB_PM_STBY_CFG0_REG &= ((uint8) (~CY_LIB_PM_STBY_CFG0_IMO_EN));\r
}\r
\r
\r
\r
/* Check whether device is in Active or AltActiv and if USB is powered on */\r
if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) &&\r
- (0u != (CY_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) ||\r
+ (0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) ||\r
(((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) &&\r
- (0u != (CY_PM_STBY_CFG5_REG & CY_ALT_ACT_USB_ENABLED))))\r
+ (0u != (CY_LIB_PM_STBY_CFG5_REG & CY_ALT_ACT_USB_ENABLED))))\r
{\r
poweredOn = 1u;\r
}\r
*******************************************************************************/\r
static void CyIMO_SetTrimValue(uint8 freq) \r
{\r
- uint8 usb_power_on = CyUSB_PowerOnCheck();\r
+ uint8 usbPowerOn = CyUSB_PowerOnCheck();\r
\r
/* If USB is powered */\r
- if(usb_power_on == 1u)\r
+ if(usbPowerOn == 1u)\r
{\r
/* Unlock USB write */\r
- CY_USB_CR1 &= ((uint8)(~CLOCK_USB_ENABLE));\r
+ CY_LIB_USB_CR1_REG &= ((uint8)(~CY_LIB_USB_CLK_EN));\r
}\r
switch(freq)\r
{\r
case CY_IMO_FREQ_3MHZ:\r
- IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_3MHZ_PTR);\r
+ CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_3MHZ_PTR);\r
break;\r
\r
case CY_IMO_FREQ_6MHZ:\r
- IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_6MHZ_PTR);\r
+ CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_6MHZ_PTR);\r
break;\r
\r
case CY_IMO_FREQ_12MHZ:\r
- IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_12MHZ_PTR);\r
+ CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_12MHZ_PTR);\r
break;\r
\r
case CY_IMO_FREQ_24MHZ:\r
- IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_24MHZ_PTR);\r
+ CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_24MHZ_PTR);\r
break;\r
\r
case CY_IMO_FREQ_48MHZ:\r
- IMO_TR1 = CY_GET_XTND_REG8(FLSHID_MFG_CFG_IMO_TR1_PTR);\r
+ CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_TR1_PTR);\r
break;\r
\r
- /* The IMO frequencies above 48 MHz are not supported by PSoC5 */\r
- #if(!CY_PSOC5A)\r
-\r
- case CY_IMO_FREQ_62MHZ:\r
- IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_67MHZ_PTR);\r
- break;\r
+ case CY_IMO_FREQ_62MHZ:\r
+ CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_67MHZ_PTR);\r
+ break;\r
\r
- #endif /* (!CY_PSOC5A) */\r
+#if(CY_PSOC5)\r
+ case CY_IMO_FREQ_74MHZ:\r
+ CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_80MHZ_PTR);\r
+ break;\r
+#endif /* (CY_PSOC5) */\r
\r
case CY_IMO_FREQ_USB:\r
- IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_USB_PTR);\r
+ CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_USB_PTR);\r
\r
/* If USB is powered */\r
- if(usb_power_on == 1u)\r
+ if(usbPowerOn == 1u)\r
{\r
/* Lock the USB Oscillator */\r
- CY_USB_CR1 |= CLOCK_USB_ENABLE;\r
+ CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN;\r
}\r
break;\r
\r
* CY_IMO_FREQ_12MHZ to set 12 MHz\r
* CY_IMO_FREQ_24MHZ to set 24 MHz\r
* CY_IMO_FREQ_48MHZ to set 48 MHz\r
-* CY_IMO_FREQ_62MHZ to set 62 MHz (unsupported by PSoC 5)\r
+* CY_IMO_FREQ_62MHZ to set 62.6 MHz\r
+* CY_IMO_FREQ_74MHZ to set 74.7 MHz (not applicable for PSoC 3)\r
* CY_IMO_FREQ_USB to set 24 MHz (Trimmed for USB operation)\r
*\r
* Return:\r
currentFreq = CY_IMO_FREQ_48MHZ;\r
break;\r
\r
- /* The IMO frequencies above 48 MHz are not supported by PSoC5 */\r
- #if(!CY_PSOC5A)\r
-\r
- case 5u:\r
- currentFreq = CY_IMO_FREQ_62MHZ;\r
- break;\r
+ case 5u:\r
+ currentFreq = CY_IMO_FREQ_62MHZ;\r
+ break;\r
\r
- #endif /* (!CY_PSOC5A) */\r
+#if(CY_PSOC5)\r
+ case 6u:\r
+ currentFreq = CY_IMO_FREQ_74MHZ;\r
+ break;\r
+#endif /* (CY_PSOC5) */\r
\r
default:\r
CYASSERT(0u != 0u);\r
{\r
case CY_IMO_FREQ_3MHZ:\r
CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |\r
- CLOCK_IMO_3MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET));\r
+ CY_LIB_IMO_3MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));\r
break;\r
\r
case CY_IMO_FREQ_6MHZ:\r
CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |\r
- CLOCK_IMO_6MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET));\r
+ CY_LIB_IMO_6MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));\r
break;\r
\r
case CY_IMO_FREQ_12MHZ:\r
CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |\r
- CLOCK_IMO_12MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET));\r
+ CY_LIB_IMO_12MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));\r
break;\r
\r
case CY_IMO_FREQ_24MHZ:\r
CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |\r
- CLOCK_IMO_24MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET));\r
+ CY_LIB_IMO_24MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));\r
break;\r
\r
case CY_IMO_FREQ_48MHZ:\r
CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |\r
- CLOCK_IMO_48MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET));\r
+ CY_LIB_IMO_48MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));\r
break;\r
\r
- /* The IMO frequencies above 48 MHz are not supported by PSoC5 */\r
- #if(!CY_PSOC5A)\r
-\r
case CY_IMO_FREQ_62MHZ:\r
CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |\r
- CLOCK_IMO_62MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET));\r
+ CY_LIB_IMO_62MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));\r
break;\r
\r
- #endif /* (!CY_PSOC5A) */\r
+#if(CY_PSOC5)\r
+ case CY_IMO_FREQ_74MHZ:\r
+ CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |\r
+ CY_LIB_IMO_74MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET));\r
+ break;\r
+#endif /* (CY_PSOC5) */\r
\r
case CY_IMO_FREQ_USB:\r
CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |\r
- CLOCK_IMO_24MHZ_VALUE) | FASTCLK_IMO_USBCLK_ON_SET;\r
+ CY_LIB_IMO_24MHZ_VALUE) | CY_LIB_IMO_USBCLK_ON_SET;\r
break;\r
\r
default:\r
* Crystal or a DSI input can be the source of the IMO output instead.\r
*\r
* Parameters:\r
-* source, CY_IMO_SOURCE_DSI to set the DSI as source.\r
+* source: CY_IMO_SOURCE_DSI to set the DSI as source.\r
* CY_IMO_SOURCE_XTAL to set the MHz as source.\r
* CY_IMO_SOURCE_IMO to set the IMO itself.\r
*\r
*******************************************************************************/\r
void CyMasterClk_SetSource(uint8 source) \r
{\r
- #if(CY_PSOC5A)\r
-\r
- uint8 masterReg0;\r
-\r
- /* Read the current setting */\r
- masterReg0 = CY_LIB_CLKDIST_MSTR0_REG;\r
-\r
- /* Write a non-zero period to the master mux clock divider */\r
- if (masterReg0 == 0x00u)\r
- {\r
- CY_LIB_CLKDIST_MSTR0_REG = 3u;\r
- }\r
-\r
- #endif /* (CY_PSOC5A) */\r
-\r
CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & MASTER_CLK_SRC_CLEAR) |\r
(source & ((uint8)(~MASTER_CLK_SRC_CLEAR)));\r
-\r
- #if(CY_PSOC5A)\r
-\r
- /* Restore zero period (if desired) to the master mux clock divider */\r
- if (masterReg0 == 0x00u)\r
- {\r
- CY_LIB_CLKDIST_MSTR0_REG = 0u;\r
- }\r
-\r
- #endif /* (CY_PSOC5A) */\r
}\r
\r
\r
interruptState = CyEnterCriticalSection();\r
\r
/* Work around to set the bus clock divider value */\r
- busClkDiv = ((uint16)(((uint16)(CY_LIB_CLKDIST_BCFG_MSB_REG)) << 8u)) | CY_LIB_CLKDIST_BCFG_LSB_REG;\r
+ busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u);\r
+ busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG;\r
\r
if ((divider == 0u) || (busClkDiv == 0u))\r
{\r
*******************************************************************************/\r
void CyCpuClk_SetDivider(uint8 divider) \r
{\r
- CLKDIST_MSTR1 = (CLKDIST_MSTR1 & CLKDIST_MSTR1_DIV_CLEAR) |\r
- ((uint8)(divider << CLKDIST_DIV_POSITION));\r
+ CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & CY_LIB_CLKDIST_MSTR1_DIV_MASK) |\r
+ ((uint8)(divider << CY_LIB_CLKDIST_DIV_POSITION));\r
}\r
\r
#endif /* (CY_PSOC3) */\r
*\r
* Parameters:\r
* source: One of the four available USB clock sources\r
-* USB_CLK_IMO2X - IMO 2x\r
-* USB_CLK_IMO - IMO\r
-* USB_CLK_PLL - PLL\r
-* USB_CLK_DSI - DSI\r
+* CY_LIB_USB_CLK_IMO2X - IMO 2x\r
+* CY_LIB_USB_CLK_IMO - IMO\r
+* CY_LIB_USB_CLK_PLL - PLL\r
+* CY_LIB_USB_CLK_DSI - DSI\r
*\r
* Return:\r
* None\r
*******************************************************************************/\r
void CyUsbClk_SetSource(uint8 source) \r
{\r
- CLKDIST_UCFG = (CLKDIST_UCFG & ((uint8)(~USB_CLKDIST_CONFIG_MASK))) |\r
- (USB_CLKDIST_CONFIG_MASK & source);\r
+ CY_LIB_CLKDIST_UCFG_REG = (CY_LIB_CLKDIST_UCFG_REG & ((uint8)(~CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK))) |\r
+ (CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK & source);\r
}\r
\r
\r
void CyILO_Start1K(void) \r
{\r
/* Set the bit 1 of ILO RS */\r
- SLOWCLK_ILO_CR0 |= ILO_CONTROL_1KHZ_ON;\r
+ CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ;\r
}\r
\r
\r
void CyILO_Stop1K(void) \r
{\r
/* Clear the bit 1 of ILO RS */\r
- SLOWCLK_ILO_CR0 &= ((uint8)(~ILO_CONTROL_1KHZ_ON));\r
+ CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ));\r
}\r
\r
\r
*******************************************************************************/\r
void CyILO_Start100K(void) \r
{\r
- /* Set the bit 2 of ILO RS */\r
- SLOWCLK_ILO_CR0 |= ILO_CONTROL_100KHZ_ON;\r
+ CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;\r
}\r
\r
\r
*******************************************************************************/\r
void CyILO_Stop100K(void) \r
{\r
- /* Clear the bit 2 of ILO RS */\r
- SLOWCLK_ILO_CR0 &= ((uint8)(~ILO_CONTROL_100KHZ_ON));\r
+ CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ));\r
}\r
\r
\r
void CyILO_Enable33K(void) \r
{\r
/* Set the bit 5 of ILO RS */\r
- SLOWCLK_ILO_CR0 |= ILO_CONTROL_33KHZ_ON;\r
+ CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ;\r
}\r
\r
\r
*******************************************************************************/\r
void CyILO_Disable33K(void) \r
{\r
- /* Clear the bit 5 of ILO RS */\r
- SLOWCLK_ILO_CR0 &= ((uint8)(~ILO_CONTROL_33KHZ_ON));\r
+ CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ));\r
}\r
\r
\r
*******************************************************************************/\r
void CyILO_SetSource(uint8 source) \r
{\r
- CLKDIST_CR = (CLKDIST_CR & CY_ILO_SOURCE_BITS_CLEAR) |\r
+ CY_LIB_CLKDIST_CR_REG = (CY_LIB_CLKDIST_CR_REG & CY_ILO_SOURCE_BITS_CLEAR) |\r
(((uint8) (source << 2u)) & ((uint8)(~CY_ILO_SOURCE_BITS_CLEAR)));\r
}\r
\r
uint8 state;\r
\r
/* Get current state. */\r
- state = SLOWCLK_ILO_CR0;\r
+ state = CY_LIB_SLOWCLK_ILO_CR0_REG;\r
\r
/* Set the the oscillator power mode. */\r
if(mode != CY_ILO_FAST_START)\r
{\r
- SLOWCLK_ILO_CR0 = (state | ILO_CONTROL_PD_MODE);\r
+ CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE);\r
}\r
else\r
{\r
- SLOWCLK_ILO_CR0 = (state & ((uint8)(~ILO_CONTROL_PD_MODE)));\r
+ CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE)));\r
}\r
\r
/* Return the old mode. */\r
- return ((state & ILO_CONTROL_PD_MODE) >> ILO_CONTROL_PD_POSITION);\r
+ return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION);\r
}\r
\r
\r
{\r
CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT;\r
CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_POWERDOWN;\r
- CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | CY_CLK_XTAL32_CFG_LP_DEFAULT;\r
+ CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) |\r
+ CY_CLK_XTAL32_CFG_LP_DEFAULT;\r
CY_CLK_XTAL32_CR_REG &= ((uint8)(~(CY_CLK_XTAL32_CR_EN | CY_CLK_XTAL32_CR_LPM)));\r
\r
#if(CY_PSOC3)\r
/* Low power mode during Sleep */\r
CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_LOW_POWER;\r
CyDelayUs(10u);\r
- CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | CY_CLK_XTAL32_CFG_LP_LOWPOWER;\r
+ CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) |\r
+ CY_CLK_XTAL32_CFG_LP_LOWPOWER;\r
CyDelayUs(20u);\r
CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_LPM;\r
}\r
/* High power mode */\r
CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_HIGH_POWER;\r
CyDelayUs(10u);\r
- CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | CY_CLK_XTAL32_CFG_LP_DEFAULT;\r
+ CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) |\r
+ CY_CLK_XTAL32_CFG_LP_DEFAULT;\r
CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_LPM));\r
}\r
\r
* Summary:\r
* Enables the megahertz crystal.\r
*\r
-* PSoC3:\r
+* PSoC 3:\r
* Waits until the XERR bit is low (no error) for a millisecond or until the\r
* number of milliseconds specified by the wait parameter has expired.\r
*\r
-* PSoC5:\r
-* Waits for CY_CLK_XMHZ_MIN_TIMEOUT milliseconds (or number of milliseconds\r
-* specified by parameter if it is greater than CY_CLK_XMHZ_MIN_TIMEOUT. The\r
-* XERR bit status is not checked.\r
-*\r
* Parameters:\r
* wait: Valid range [0-255].\r
* This is the timeout value in milliseconds.\r
cystatus CyXTAL_Start(uint8 wait) \r
{\r
cystatus status = CYRET_SUCCESS;\r
-\r
- #if(CY_PSOC5A)\r
- volatile uint8 timeout = (wait < CY_CLK_XMHZ_MIN_TIMEOUT) ? CY_CLK_XMHZ_MIN_TIMEOUT : wait;\r
- #else\r
- volatile uint8 timeout = wait;\r
- #endif /* (CY_PSOC5A) */\r
-\r
+ volatile uint8 timeout = wait;\r
volatile uint8 count;\r
uint8 iloEnableState;\r
uint8 pmTwCfg0Tmp;\r
if(wait > 0u)\r
{\r
/* Save 100 KHz ILO, FTW interval, enable and interrupt enable */\r
- iloEnableState = SLOWCLK_ILO_CR0;\r
- pmTwCfg0Tmp = CY_PM_TW_CFG0_REG;\r
- pmTwCfg2Tmp = CY_PM_TW_CFG2_REG;\r
+ iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG;\r
+ pmTwCfg0Tmp = CY_LIB_PM_TW_CFG0_REG;\r
+ pmTwCfg2Tmp = CY_LIB_PM_TW_CFG2_REG;\r
\r
/* Set 250 us interval */\r
CyPmFtwSetInterval(CY_CLK_XMHZ_FTW_INTERVAL);\r
\r
for( ; timeout > 0u; timeout--)\r
{\r
- #if(!CY_PSOC5A)\r
-\r
- /* Read XERR bit to clear it */\r
- (void) CY_CLK_XMHZ_CSR_REG;\r
-\r
- #endif /* (!CY_PSOC5A) */\r
-\r
+ /* Read XERR bit to clear it */\r
+ (void) CY_CLK_XMHZ_CSR_REG;\r
\r
/* Wait for a millisecond - 4 x 250 us */\r
for(count = 4u; count > 0u; count--)\r
{\r
- while(!(CY_PM_FTW_INT == CyPmReadStatus(CY_PM_FTW_INT)))\r
+ while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))\r
{\r
/* Wait for the FTW interrupt event */\r
}\r
}\r
\r
\r
- #if(!CY_PSOC5A)\r
-\r
- /*******************************************************************\r
- * High output indicates oscillator failure.\r
- * Only can be used after start-up interval (1 ms) is completed.\r
- *******************************************************************/\r
- if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR))\r
- {\r
- status = CYRET_SUCCESS;\r
- break;\r
- }\r
-\r
- #endif /* (!CY_PSOC5A) */\r
+ /*******************************************************************\r
+ * High output indicates oscillator failure.\r
+ * Only can be used after start-up interval (1 ms) is completed.\r
+ *******************************************************************/\r
+ if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR))\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ break;\r
+ }\r
}\r
\r
\r
/* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */\r
- if(0u == (iloEnableState & ILO_CONTROL_100KHZ_ON))\r
+ if(0u == (iloEnableState & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ))\r
{\r
CyILO_Stop100K();\r
}\r
- CY_PM_TW_CFG0_REG = pmTwCfg0Tmp;\r
- CY_PM_TW_CFG2_REG = pmTwCfg2Tmp;\r
+ CY_LIB_PM_TW_CFG0_REG = pmTwCfg0Tmp;\r
+ CY_LIB_PM_TW_CFG2_REG = pmTwCfg2Tmp;\r
}\r
\r
return(status);\r
}\r
\r
\r
-#if(!CY_PSOC5A)\r
-\r
- /*******************************************************************************\r
- * Function Name: CyXTAL_EnableErrStatus\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Enables the generation of the XERR status bit for the megahertz crystal.\r
- * This function is not available for PSoC5.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- *******************************************************************************/\r
- void CyXTAL_EnableErrStatus(void) \r
- {\r
- /* If oscillator has insufficient amplitude, XERR bit will be high. */\r
- CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XFB));\r
- }\r
+/*******************************************************************************\r
+* Function Name: CyXTAL_EnableErrStatus\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables the generation of the XERR status bit for the megahertz crystal.\r
+* This function is not available for PSoC5.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyXTAL_EnableErrStatus(void) \r
+{\r
+ /* If oscillator has insufficient amplitude, XERR bit will be high. */\r
+ CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XFB));\r
+}\r
\r
\r
- /*******************************************************************************\r
- * Function Name: CyXTAL_DisableErrStatus\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Disables the generation of the XERR status bit for the megahertz crystal.\r
- * This function is not available for PSoC5.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- *******************************************************************************/\r
- void CyXTAL_DisableErrStatus(void) \r
- {\r
- /* If oscillator has insufficient amplitude, XERR bit will be high. */\r
- CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XFB;\r
- }\r
+/*******************************************************************************\r
+* Function Name: CyXTAL_DisableErrStatus\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables the generation of the XERR status bit for the megahertz crystal.\r
+* This function is not available for PSoC5.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyXTAL_DisableErrStatus(void) \r
+{\r
+ /* If oscillator has insufficient amplitude, XERR bit will be high. */\r
+ CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XFB;\r
+}\r
\r
\r
- /*******************************************************************************\r
- * Function Name: CyXTAL_ReadStatus\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Reads the XERR status bit for the megahertz crystal. This status bit is a\r
- * sticky clear on read value. This function is not available for PSoC5.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * Status\r
- * 0: No error\r
- * 1: Error\r
- *\r
- *******************************************************************************/\r
- uint8 CyXTAL_ReadStatus(void) \r
- {\r
- /***************************************************************************\r
- * High output indicates oscillator failure. Only use this after start-up\r
- * interval is completed. This can be used for status and failure recovery.\r
- ***************************************************************************/\r
- return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u);\r
- }\r
+/*******************************************************************************\r
+* Function Name: CyXTAL_ReadStatus\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Reads the XERR status bit for the megahertz crystal. This status bit is a\r
+* sticky clear on read value. This function is not available for PSoC5.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* Status\r
+* 0: No error\r
+* 1: Error\r
+*\r
+*******************************************************************************/\r
+uint8 CyXTAL_ReadStatus(void) \r
+{\r
+ /***************************************************************************\r
+ * High output indicates oscillator failure. Only use this after start-up\r
+ * interval is completed. This can be used for status and failure recovery.\r
+ ***************************************************************************/\r
+ return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u);\r
+}\r
\r
\r
- /*******************************************************************************\r
- * Function Name: CyXTAL_EnableFaultRecovery\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Enables the fault recovery circuit which will switch to the IMO in the case\r
- * of a fault in the megahertz crystal circuit. The crystal must be up and\r
- * running with the XERR bit at 0, before calling this function to prevent\r
- * immediate fault switchover. This function is not available for PSoC5.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- *******************************************************************************/\r
- void CyXTAL_EnableFaultRecovery(void) \r
- {\r
- CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XPROT;\r
- }\r
+/*******************************************************************************\r
+* Function Name: CyXTAL_EnableFaultRecovery\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables the fault recovery circuit which will switch to the IMO in the case\r
+* of a fault in the megahertz crystal circuit. The crystal must be up and\r
+* running with the XERR bit at 0, before calling this function to prevent\r
+* immediate fault switchover. This function is not available for PSoC5.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyXTAL_EnableFaultRecovery(void) \r
+{\r
+ CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XPROT;\r
+}\r
\r
\r
- /*******************************************************************************\r
- * Function Name: CyXTAL_DisableFaultRecovery\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Disables the fault recovery circuit which will switch to the IMO in the case\r
- * of a fault in the megahertz crystal circuit. This function is not available\r
- * for PSoC5.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- *******************************************************************************/\r
- void CyXTAL_DisableFaultRecovery(void) \r
- {\r
- CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XPROT));\r
- }\r
+/*******************************************************************************\r
+* Function Name: CyXTAL_DisableFaultRecovery\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables the fault recovery circuit which will switch to the IMO in the case\r
+* of a fault in the megahertz crystal circuit. This function is not available\r
+* for PSoC5.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyXTAL_DisableFaultRecovery(void) \r
+{\r
+ CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XPROT));\r
+}\r
\r
-#endif /* (!CY_PSOC5A) */\r
\r
/*******************************************************************************\r
* Function Name: CyXTAL_SetStartup\r
}\r
\r
\r
-#if(CY_PSOC3 || CY_PSOC5LP)\r
- /*******************************************************************************\r
- * Function Name: CyXTAL_SetFbVoltage\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Sets the feedback reference voltage to use for the crystal circuit.\r
- * This function is only available for PSoC3 and PSoC 5LP.\r
- *\r
- * Parameters:\r
- * setting: Valid range [0-15].\r
- * Refer to the device TRM and datasheet for more information.\r
- *\r
- * Return:\r
- * None\r
- *\r
- *******************************************************************************/\r
- void CyXTAL_SetFbVoltage(uint8 setting) \r
- {\r
- CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_FB_MASK))) |\r
- (setting & CY_CLK_XMHZ_CFG1_VREF_FB_MASK));\r
- }\r
\r
+/*******************************************************************************\r
+* Function Name: CyXTAL_SetFbVoltage\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the feedback reference voltage to use for the crystal circuit.\r
+* This function is only available for PSoC3 and PSoC 5LP.\r
+*\r
+* Parameters:\r
+* setting: Valid range [0-15].\r
+* Refer to the device TRM and datasheet for more information.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyXTAL_SetFbVoltage(uint8 setting) \r
+{\r
+ CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_FB_MASK))) |\r
+ (setting & CY_CLK_XMHZ_CFG1_VREF_FB_MASK));\r
+}\r
\r
- /*******************************************************************************\r
- * Function Name: CyXTAL_SetWdVoltage\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Sets the reference voltage used by the watchdog to detect a failure in the\r
- * crystal circuit. This function is only available for PSoC3 and PSoC 5LP.\r
- *\r
- * Parameters:\r
- * setting: Valid range [0-7].\r
- * Refer to the device TRM and datasheet for more information.\r
- *\r
- * Return:\r
- * None\r
- *\r
- *******************************************************************************/\r
- void CyXTAL_SetWdVoltage(uint8 setting) \r
- {\r
- CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_WD_MASK))) |\r
- (((uint8)(setting << 4u)) & CY_CLK_XMHZ_CFG1_VREF_WD_MASK));\r
- }\r
\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+/*******************************************************************************\r
+* Function Name: CyXTAL_SetWdVoltage\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the reference voltage used by the watchdog to detect a failure in the\r
+* crystal circuit. This function is only available for PSoC3 and PSoC 5LP.\r
+*\r
+* Parameters:\r
+* setting: Valid range [0-7].\r
+* Refer to the device TRM and datasheet for more information.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyXTAL_SetWdVoltage(uint8 setting) \r
+{\r
+ CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_WD_MASK))) |\r
+ (((uint8)(setting << 4u)) & CY_CLK_XMHZ_CFG1_VREF_WD_MASK));\r
+}\r
\r
\r
/*******************************************************************************\r
\r
#if defined (__ARMCC_VERSION)\r
__breakpoint(0x0);\r
- #elif defined(__GNUC__)\r
+ #elif defined(__GNUC__) || defined (__ICCARM__)\r
__asm(" bkpt 1");\r
#elif defined(__C51__)\r
CYDEV_HALT_CPU;\r
*******************************************************************************/\r
void CySoftwareReset(void) \r
{\r
- /* Perform software reset */\r
- *RESET_CR2 = 0x1u;\r
+ CY_LIB_RESET_CR2_REG |= CY_LIB_RESET_CR2_RESET;\r
}\r
\r
\r
*******************************************************************************/\r
void CyWdtStart(uint8 ticks, uint8 lpMode) \r
{\r
- #if(CY_PSOC5A)\r
- CyILO_Start1K();\r
- #endif /* (CY_PSOC5A) */\r
-\r
/* Set WDT interval */\r
CY_WDT_CFG_REG = (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_INTERVAL_MASK))) | (ticks & CY_WDT_CFG_INTERVAL_MASK);\r
\r
CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET;\r
CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET));\r
\r
- #if(!CY_PSOC5A)\r
-\r
- /* Setting the low power mode */\r
- CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) |\r
- (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK)));\r
- #else\r
-\r
- if(0u != lpMode)\r
- {\r
- /* To remove unreferenced local variable warning */\r
- }\r
-\r
- #endif /* (!CY_PSOC5A) */\r
+ /* Setting the low power mode */\r
+ CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) |\r
+ (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK)));\r
\r
/* Enables the watchdog reset */\r
CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN;\r
*******************************************************************************/\r
void CyWdtClear(void) \r
{\r
- #if(CY_PSOC5A)\r
-\r
- /* PSoC5 ES1 watchdog time clear requires workaround */\r
- uint8 wdtCfg = CY_WDT_CFG_REG;\r
- CY_WDT_CR_REG = CY_WDT_CR_FEED;\r
- CY_WDT_CFG_REG = CY_WDT_CFG_CLEAR_ALL;\r
- CY_WDT_CFG_REG = wdtCfg;\r
-\r
- #else\r
-\r
- CY_WDT_CR_REG = CY_WDT_CR_FEED;\r
-\r
- #endif /* (CY_PSOC5A) */\r
+ CY_WDT_CR_REG = CY_WDT_CR_FEED;\r
}\r
\r
\r
* reset: Option to reset device at a specified Vddd threshold:\r
* 0 - Device is not reset.\r
* 1 - Device is reset.\r
-* This option is applicable for PSoC 3/PSoC 5LP devices only.\r
*\r
* threshold: Sets the trip level for the voltage monitor.\r
-* Values from 1.70 V to 5.45 V(for PSoC 3/PSoC 5LP) and from 2.45 V to 5.45 V\r
-* (for PSoC 5TM) are accepted with the approximately 250 mV interval.\r
+* Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV\r
+* interval.\r
*\r
* Return:\r
* None\r
{\r
*CY_INT_CLEAR_PTR = 0x01u;\r
\r
- #if(!CY_PSOC5A)\r
- CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));\r
- #endif /*(!CY_PSOC5A)*/\r
+ CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));\r
\r
CY_VD_LVI_TRIP_REG = (threshold & CY_VD_LVI_TRIP_LVID_MASK) |\r
(CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK)));\r
/* Timeout to eliminate glitches on the LVI/HVI when enabling */\r
CyDelayUs(1u);\r
\r
- (void)CY_VD_PERSISTENT_STATUS_REG;\r
+ (void)CY_VD_PERSISTENT_STATUS_REG;\r
\r
- #if(!CY_PSOC5A)\r
- if(0u != reset)\r
- {\r
- CY_VD_PRES_CONTROL_REG |= CY_VD_PRESD_EN;\r
- }\r
- else\r
- {\r
- CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));\r
- }\r
- #else\r
-\r
- if(0u != reset)\r
- {\r
- /* To remove unreferenced local variable warning */\r
- }\r
-\r
- #endif /*(!CY_PSOC5A)*/\r
+ if(0u != reset)\r
+ {\r
+ CY_VD_PRES_CONTROL_REG |= CY_VD_PRESD_EN;\r
+ }\r
+ else\r
+ {\r
+ CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));\r
+ }\r
\r
*CY_INT_CLR_PEND_PTR = 0x01u;\r
*CY_INT_ENABLE_PTR = 0x01u;\r
* reset: Option to reset device at a specified Vdda threshold:\r
* 0 - Device is not reset.\r
* 1 - Device is reset.\r
-* This option is applicable for PSoC 3/PSoC 5LP devices only.\r
*\r
* threshold: Sets the trip level for the voltage monitor.\r
-* Values from 1.70 V to 5.45 V(for PSoC 3/PSoC 5LP) and from 2.45 V to 5.45 V\r
-* (for PSoC 5TM) are accepted with the approximately 250 mV interval.\r
+* Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV\r
+* interval.\r
*\r
* Return:\r
* None\r
{\r
*CY_INT_CLEAR_PTR = 0x01u;\r
\r
- #if(!CY_PSOC5A)\r
- CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
- #endif /*(!CY_PSOC5A)*/\r
+ CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
\r
CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu);\r
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN;\r
/* Timeout to eliminate glitches on the LVI/HVI when enabling */\r
CyDelayUs(1u);\r
\r
- (void)CY_VD_PERSISTENT_STATUS_REG;\r
-\r
- #if(!CY_PSOC5A)\r
- if(0u != reset)\r
- {\r
- CY_VD_PRES_CONTROL_REG |= CY_VD_PRESA_EN;\r
- }\r
- else\r
- {\r
- CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
- }\r
- #else\r
-\r
- if(0u != reset)\r
- {\r
- /* To remove unreferenced local variable warning */\r
- }\r
+ (void)CY_VD_PERSISTENT_STATUS_REG;\r
\r
- #endif /*(!CY_PSOC5A)*/\r
+ if(0u != reset)\r
+ {\r
+ CY_VD_PRES_CONTROL_REG |= CY_VD_PRESA_EN;\r
+ }\r
+ else\r
+ {\r
+ CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
+ }\r
\r
*CY_INT_CLR_PEND_PTR = 0x01u;\r
*CY_INT_ENABLE_PTR = 0x01u;\r
{\r
CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVID_EN));\r
\r
- #if(!CY_PSOC5A)\r
- CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));\r
- #endif /*(!CY_PSOC5A)*/\r
+ CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));\r
\r
while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u))\r
{\r
********************************************************************************\r
*\r
* Summary:\r
-* Disables the analog low voltage monitor\r
-* (interrupt and device reset are disabled).\r
+* Disables the analog low voltage monitor (interrupt and device reset are\r
+* disabled).\r
*\r
* Parameters:\r
* None\r
{\r
CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVIA_EN));\r
\r
- #if(!CY_PSOC5A)\r
- CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
- #endif /*(!CY_PSOC5A)*/\r
+ CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
\r
while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u))\r
{\r
{\r
*CY_INT_CLEAR_PTR = 0x01u;\r
\r
- #if(!CY_PSOC5A)\r
- CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
- #endif /*(!CY_PSOC5A)*/\r
+ CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
\r
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_HVIA_EN;\r
\r
/* Timeout to eliminate glitches on the LVI/HVI when enabling */\r
CyDelayUs(1u);\r
\r
- (void) CY_VD_PERSISTENT_STATUS_REG;\r
+ (void) CY_VD_PERSISTENT_STATUS_REG;\r
\r
*CY_INT_CLR_PEND_PTR = 0x01u;\r
*CY_INT_ENABLE_PTR = 0x01u;\r
*\r
* Parameters:\r
* mask: Bits in the shadow register to clear.\r
-* Value Define Bit To Clear\r
-* 0x01 CY_VD_LVID LVID\r
-* 0x02 CY_VD_LVIA LVIA\r
-* 0x04 CY_VD_HVIA HVIA\r
+* Define Definition\r
+* CY_VD_LVID Persistent status of digital LVI.\r
+* CY_VD_LVIA Persistent status of analog LVI.\r
+* CY_VD_HVIA Persistent status of analog HVI.\r
*\r
* Return:\r
* Status. Same enumerated bit values as used for the mask parameter.\r
* None\r
*\r
* Return:\r
-* Status. Same enumerated bit values as used for the mask parameter.\r
+* Status:\r
+* Define Definition\r
+* CY_VD_LVID Persistent status of digital LVI.\r
+* CY_VD_LVIA Persistent status of analog LVI.\r
+* CY_VD_HVIA Persistent status of analog HVI.\r
*\r
*******************************************************************************/\r
uint8 CyVdRealTimeStatus(void) \r
#endif /* (CY_PSOC5) */\r
\r
\r
-#if(!CY_PSOC5A)\r
-\r
- #if(CYDEV_VARIABLE_VDDA == 1)\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: CySetScPumps\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * If 1 is passed as a parameter:\r
- * - if any of the SC blocks are used - enable pumps for the SC blocks and\r
- * start boost clock.\r
- * - For the each enabled SC block set boost clock index and enable boost clock.\r
- *\r
- * If non-1 value is passed as a parameter:\r
- * - If all SC blocks are not used - disable pumps for the SC blocks and\r
- * stop boost clock.\r
- * - For the each enabled SC block clear boost clock index and disable boost\r
- * clock.\r
- *\r
- * The global variable CyScPumpEnabled is updated to be equal to passed\r
- * parameter.\r
- *\r
- * Parameters:\r
- * uint8 enable: Enable/disable SC pumps and boost clock for enabled SC block.\r
- * 1 - Enable\r
- * 0 - Disable\r
- *\r
- * Return:\r
- * None\r
- *\r
- *******************************************************************************/\r
- void CySetScPumps(uint8 enable) \r
- {\r
+#if(CYDEV_VARIABLE_VDDA == 1)\r
\r
- if(1u == enable)\r
+ /*******************************************************************************\r
+ * Function Name: CySetScPumps\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * If 1 is passed as a parameter:\r
+ * - if any of the SC blocks are used - enable pumps for the SC blocks and\r
+ * start boost clock.\r
+ * - For the each enabled SC block set boost clock index and enable boost\r
+ * clock.\r
+ *\r
+ * If non-1 value is passed as a parameter:\r
+ * - If all SC blocks are not used - disable pumps for the SC blocks and\r
+ * stop boost clock.\r
+ * - For the each enabled SC block clear boost clock index and disable boost\r
+ * clock.\r
+ *\r
+ * The global variable CyScPumpEnabled is updated to be equal to passed\r
+ * parameter.\r
+ *\r
+ * Parameters:\r
+ * uint8 enable: Enable/disable SC pumps and boost clock for enabled SC block.\r
+ * 1 - Enable\r
+ * 0 - Disable\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CySetScPumps(uint8 enable) \r
+ {\r
+ if(1u == enable)\r
+ {\r
+ /* The SC pumps should be enabled */\r
+ CyScPumpEnabled = 1u;\r
+ /* Enable pumps if any of SC blocks are used */\r
+ if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAPS_MASK))\r
{\r
- /* The SC pumps should be enabled */\r
- CyScPumpEnabled = 1u;\r
-\r
-\r
- /* Enable pumps if any of SC blocks are used */\r
- if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAPS_MASK))\r
- {\r
-\r
- CY_LIB_SC_MISC_REG |= CY_LIB_SC_MISC_PUMP_FORCE;\r
-\r
- CyScBoostClk_Start();\r
- }\r
-\r
-\r
- /* Set positive pump for each enabled SC block: set clock index and enable it */\r
- if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP0_EN))\r
- {\r
- CY_LIB_SC0_BST_REG = (CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;\r
- CY_LIB_SC0_BST_REG |= CY_LIB_SC_BST_CLK_EN;\r
- }\r
-\r
- if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP1_EN))\r
- {\r
- CY_LIB_SC1_BST_REG = (CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;\r
- CY_LIB_SC1_BST_REG |= CY_LIB_SC_BST_CLK_EN;\r
- }\r
-\r
- if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP2_EN))\r
- {\r
- CY_LIB_SC2_BST_REG = (CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;\r
- CY_LIB_SC2_BST_REG |= CY_LIB_SC_BST_CLK_EN;\r
- }\r
-\r
- if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP3_EN))\r
- {\r
- CY_LIB_SC3_BST_REG = (CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;\r
- CY_LIB_SC3_BST_REG |= CY_LIB_SC_BST_CLK_EN;\r
- }\r
+ CY_LIB_SC_MISC_REG |= CY_LIB_SC_MISC_PUMP_FORCE;\r
+ CyScBoostClk_Start();\r
}\r
- else\r
+ /* Set positive pump for each enabled SC block: set clock index and enable it */\r
+ if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP0_EN))\r
{\r
- /* The SC pumps should be disabled */\r
- CyScPumpEnabled = 0u;\r
-\r
- /* Disable pumps for all SC blocks and stop boost clock */\r
- CY_LIB_SC_MISC_REG &= ((uint8)(~CY_LIB_SC_MISC_PUMP_FORCE));\r
- CyScBoostClk_Stop();\r
-\r
- /* Disable boost clock and clear clock index for each SC block */\r
- CY_LIB_SC0_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));\r
- CY_LIB_SC0_BST_REG = CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;\r
-\r
- CY_LIB_SC1_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));\r
- CY_LIB_SC1_BST_REG = CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;\r
-\r
- CY_LIB_SC2_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));\r
- CY_LIB_SC2_BST_REG = CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;\r
-\r
- CY_LIB_SC3_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));\r
- CY_LIB_SC3_BST_REG = CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;\r
+ CY_LIB_SC0_BST_REG = (CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;\r
+ CY_LIB_SC0_BST_REG |= CY_LIB_SC_BST_CLK_EN;\r
+ }\r
+ if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP1_EN))\r
+ {\r
+ CY_LIB_SC1_BST_REG = (CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;\r
+ CY_LIB_SC1_BST_REG |= CY_LIB_SC_BST_CLK_EN;\r
+ }\r
+ if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP2_EN))\r
+ {\r
+ CY_LIB_SC2_BST_REG = (CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;\r
+ CY_LIB_SC2_BST_REG |= CY_LIB_SC_BST_CLK_EN;\r
+ }\r
+ if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP3_EN))\r
+ {\r
+ CY_LIB_SC3_BST_REG = (CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;\r
+ CY_LIB_SC3_BST_REG |= CY_LIB_SC_BST_CLK_EN;\r
}\r
}\r
+ else\r
+ {\r
+ /* The SC pumps should be disabled */\r
+ CyScPumpEnabled = 0u;\r
+ /* Disable pumps for all SC blocks and stop boost clock */\r
+ CY_LIB_SC_MISC_REG &= ((uint8)(~CY_LIB_SC_MISC_PUMP_FORCE));\r
+ CyScBoostClk_Stop();\r
+ /* Disable boost clock and clear clock index for each SC block */\r
+ CY_LIB_SC0_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));\r
+ CY_LIB_SC0_BST_REG = CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;\r
+ CY_LIB_SC1_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));\r
+ CY_LIB_SC1_BST_REG = CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;\r
+ CY_LIB_SC2_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));\r
+ CY_LIB_SC2_BST_REG = CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;\r
+ CY_LIB_SC3_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));\r
+ CY_LIB_SC3_BST_REG = CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;\r
+ }\r
+ }\r
\r
- #endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
-\r
-#endif /* (!CY_PSOC5A) */\r
+#endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: CyLib.h\r
-* Version 3.40\r
+* Version 4.0\r
*\r
* Description:\r
* Provides the function definitions for the system, clocking, interrupts and\r
#endif /* (CY_PSOC3) */\r
\r
\r
-#if(!CY_PSOC5A)\r
+#if(CYDEV_VARIABLE_VDDA == 1)\r
\r
- #if(CYDEV_VARIABLE_VDDA == 1)\r
+ #include "CyScBoostClk.h"\r
\r
- #include "CyScBoostClk.h"\r
-\r
- #endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
-\r
-#endif /* (!CY_PSOC5A) */\r
+#endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
\r
\r
/* Global variable with preserved reset status */\r
extern uint8 CYXDATA CyResetStatus;\r
\r
\r
-#if(!CY_PSOC5A)\r
-\r
- /* Variable Vdda */\r
- #if(CYDEV_VARIABLE_VDDA == 1)\r
-\r
- extern uint8 CyScPumpEnabled;\r
+/* Variable Vdda */\r
+#if(CYDEV_VARIABLE_VDDA == 1)\r
\r
- #endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
+ extern uint8 CyScPumpEnabled;\r
\r
-#endif /* (!CY_PSOC5A) */\r
+#endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
\r
\r
/* Do not use these definitions directly in your application */\r
cystatus CyXTAL_Start(uint8 wait) ;\r
void CyXTAL_Stop(void) ;\r
void CyXTAL_SetStartup(uint8 setting) ;\r
-#if(!CY_PSOC5A)\r
- void CyXTAL_EnableErrStatus(void) ;\r
- void CyXTAL_DisableErrStatus(void) ;\r
- uint8 CyXTAL_ReadStatus(void) ;\r
- void CyXTAL_EnableFaultRecovery(void) ;\r
- void CyXTAL_DisableFaultRecovery(void) ;\r
-#endif /* (!CY_PSOC5A) */\r
-\r
-#if(CY_PSOC3 || CY_PSOC5LP)\r
- void CyXTAL_SetFbVoltage(uint8 setting) ;\r
- void CyXTAL_SetWdVoltage(uint8 setting) ;\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+void CyXTAL_EnableErrStatus(void) ;\r
+void CyXTAL_DisableErrStatus(void) ;\r
+uint8 CyXTAL_ReadStatus(void) ;\r
+void CyXTAL_EnableFaultRecovery(void) ;\r
+void CyXTAL_DisableFaultRecovery(void) ;\r
+\r
+void CyXTAL_SetFbVoltage(uint8 setting) ;\r
+void CyXTAL_SetWdVoltage(uint8 setting) ;\r
\r
void CyWdtStart(uint8 ticks, uint8 lpMode) ;\r
void CyWdtClear(void) ;\r
uint8 CyVdStickyStatus(uint8 mask) ;\r
uint8 CyVdRealTimeStatus(void) ;\r
\r
-#if(!CY_PSOC5A)\r
-\r
- void CySetScPumps(uint8 enable) ;\r
-\r
-#endif /* (!CY_PSOC5A) */\r
+void CySetScPumps(uint8 enable) ;\r
\r
\r
/***************************************\r
*******************************************************************************/\r
#define CY_XTAL32K_ANA_STAT (0x20u)\r
\r
-\r
#define CY_CLK_XTAL32_CR_LPM (0x02u)\r
#define CY_CLK_XTAL32_CR_EN (0x01u)\r
#if(CY_PSOC3)\r
\r
\r
/*******************************************************************************\r
-* Variable VDDA\r
+* Variable VDDA API Constants\r
*******************************************************************************/\r
-#if(!CY_PSOC5A)\r
-\r
- #if(CYDEV_VARIABLE_VDDA == 1)\r
+#if(CYDEV_VARIABLE_VDDA == 1)\r
\r
- /* Active Power Mode Configuration Register 9 */\r
- #define CY_LIB_ACT_CFG9_SWCAP0_EN (0x01u)\r
- #define CY_LIB_ACT_CFG9_SWCAP1_EN (0x02u)\r
- #define CY_LIB_ACT_CFG9_SWCAP2_EN (0x04u)\r
- #define CY_LIB_ACT_CFG9_SWCAP3_EN (0x08u)\r
- #define CY_LIB_ACT_CFG9_SWCAPS_MASK (0x0Fu)\r
+ /* Active Power Mode Configuration Register 9 */\r
+ #define CY_LIB_ACT_CFG9_SWCAP0_EN (0x01u)\r
+ #define CY_LIB_ACT_CFG9_SWCAP1_EN (0x02u)\r
+ #define CY_LIB_ACT_CFG9_SWCAP2_EN (0x04u)\r
+ #define CY_LIB_ACT_CFG9_SWCAP3_EN (0x08u)\r
+ #define CY_LIB_ACT_CFG9_SWCAPS_MASK (0x0Fu)\r
\r
- /* Switched Cap Miscellaneous Control Register */\r
- #define CY_LIB_SC_MISC_PUMP_FORCE (0x20u)\r
+ /* Switched Cap Miscellaneous Control Register */\r
+ #define CY_LIB_SC_MISC_PUMP_FORCE (0x20u)\r
\r
- /* Switched Capacitor 0 Boost Clock Selection Register */\r
- #define CY_LIB_SC_BST_CLK_EN (0x08u)\r
- #define CY_LIB_SC_BST_CLK_INDEX_MASK (0xF8u)\r
+ /* Switched Capacitor 0 Boost Clock Selection Register */\r
+ #define CY_LIB_SC_BST_CLK_EN (0x08u)\r
+ #define CY_LIB_SC_BST_CLK_INDEX_MASK (0xF8u)\r
\r
- #endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
-\r
-#endif /* (!CY_PSOC5A) */\r
+#endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
\r
\r
/*******************************************************************************\r
-* Clock Distribution Constants\r
+* Clock Distribution API Constants\r
*******************************************************************************/\r
#define CY_LIB_CLKDIST_AMASK_MASK (0xF0u)\r
#define CY_LIB_CLKDIST_DMASK_MASK (0x00u)\r
#define CY_LIB_CLKDIST_LD_LOAD (0x01u)\r
-#define CY_LIB_CLKDIST_BCFG2_MASK (0x80u) /* Enable shadow loads */\r
+#define CY_LIB_CLKDIST_BCFG2_MASK (0x80u)\r
#define CY_LIB_CLKDIST_MASTERCLK_DIV (7u)\r
-#define CY_LIB_CLKDIST_BCFG2_SSS (0x40u) /* Sync source is same frequency */\r
+#define CY_LIB_CLKDIST_BCFG2_SSS (0x40u)\r
#define CY_LIB_CLKDIST_MSTR1_SRC_MASK (0xFCu)\r
#define CY_LIB_FASTCLK_IMO_DOUBLER (0x10u)\r
#define CY_LIB_FASTCLK_IMO_IMO (0x20u)\r
#define CY_LIB_CLKDIST_CR_IMO2X (0x40u)\r
#define CY_LIB_FASTCLK_IMO_CR_RANGE_MASK (0xF8u)\r
\r
-#define CY_LIB_CLKDIST_CR_PLL_SCR_MASK (0xFCu)\r
+#define CY_LIB_CLKDIST_CR_PLL_SCR_MASK (0xFCu)\r
\r
-#define ILO_CONTROL_PD_MODE (0x10u)\r
+\r
+/* CyILO_SetPowerMode() */\r
+#define CY_ILO_CONTROL_PD_MODE (0x10u)\r
+#define CY_ILO_CONTROL_PD_POSITION (4u)\r
\r
#define CY_ILO_SOURCE_100K (0u)\r
#define CY_ILO_SOURCE_33K (1u)\r
#define CY_ILO_SOURCE_33K_SET (0x04u)\r
#define CY_ILO_SOURCE_100K_SET (0x00u)\r
\r
-\r
#define CY_MASTER_SOURCE_IMO (0u)\r
#define CY_MASTER_SOURCE_PLL (1u)\r
#define CY_MASTER_SOURCE_XTAL (2u)\r
#define CY_IMO_SOURCE_IMO (0u)\r
#define CY_IMO_SOURCE_XTAL (1u)\r
#define CY_IMO_SOURCE_DSI (2u)\r
-#define IMO_PM_ENABLE (0x10u) /* Enable IMO clock source. */\r
-#define FASTCLK_IMO_USBCLK_ON_SET (0x40u)\r
\r
-#define CLOCK_IMO_3MHZ_VALUE (0x03u)\r
-#define CLOCK_IMO_6MHZ_VALUE (0x01u)\r
-#define CLOCK_IMO_12MHZ_VALUE (0x00u)\r
-#define CLOCK_IMO_24MHZ_VALUE (0x02u)\r
-#define CLOCK_IMO_48MHZ_VALUE (0x04u)\r
-#define CLOCK_IMO_62MHZ_VALUE (0x05u)\r
-#define CLOCK_IMO_74MHZ_VALUE (0x06u)\r
+\r
+/* CyIMO_Start() */\r
+#define CY_LIB_PM_ACT_CFG0_IMO_EN (0x10u)\r
+#define CY_LIB_PM_STBY_CFG0_IMO_EN (0x10u)\r
+#define CY_LIB_CLK_IMO_FTW_TIMEOUT (0x00u)\r
+\r
+#define CY_LIB_IMO_3MHZ_VALUE (0x03u)\r
+#define CY_LIB_IMO_6MHZ_VALUE (0x01u)\r
+#define CY_LIB_IMO_12MHZ_VALUE (0x00u)\r
+#define CY_LIB_IMO_24MHZ_VALUE (0x02u)\r
+#define CY_LIB_IMO_48MHZ_VALUE (0x04u)\r
+#define CY_LIB_IMO_62MHZ_VALUE (0x05u)\r
+#define CY_LIB_IMO_74MHZ_VALUE (0x06u)\r
+\r
\r
/* CyIMO_SetFreq() */\r
#define CY_IMO_FREQ_3MHZ (0u)\r
#define CY_IMO_FREQ_12MHZ (2u)\r
#define CY_IMO_FREQ_24MHZ (3u)\r
#define CY_IMO_FREQ_48MHZ (4u)\r
-#if(!CY_PSOC5A)\r
- #define CY_IMO_FREQ_62MHZ (5u)\r
-#endif /* (!CY_PSOC5A) */\r
+#define CY_IMO_FREQ_62MHZ (5u)\r
+#if(CY_PSOC5)\r
+ #define CY_IMO_FREQ_74MHZ (6u)\r
+#endif /* (CY_PSOC5) */\r
#define CY_IMO_FREQ_USB (8u)\r
\r
+#define CY_LIB_IMO_USBCLK_ON_SET (0x40u)\r
\r
-#define SFR_USER_CPUCLK_DIV_MASK (0x0Fu)\r
-#define CLKDIST_DIV_POSITION (4u)\r
-#define CLKDIST_MSTR1_DIV_CLEAR (0x0Fu)\r
-#define CLOCK_USB_ENABLE (0x02u)\r
-#define CLOCK_IMO_OUT_X2 (0x10u)\r
-#define CLOCK_IMO_OUT_X1 ((uint8)(~CLOCK_IMO_OUT_X2))\r
+\r
+/* CyCpuClk_SetDivider() */\r
+#define CY_LIB_CLKDIST_DIV_POSITION (4u)\r
+#define CY_LIB_CLKDIST_MSTR1_DIV_MASK (0x0Fu)\r
+\r
+\r
+/* CyIMO_SetTrimValue() */\r
+#define CY_LIB_USB_CLK_EN (0x02u)\r
+\r
+\r
+/* CyPLL_OUT_SetSource() - parameters */\r
#define CY_PLL_SOURCE_IMO (0u)\r
#define CY_PLL_SOURCE_XTAL (1u)\r
#define CY_PLL_SOURCE_DSI (2u)\r
\r
-#define CLOCK_IMO2X_ECO ((uint8)(~CLOCK_IMO2X_DSI))\r
\r
-#define ILO_CONTROL_PD_POSITION (4u)\r
-#define ILO_CONTROL_1KHZ_ON (0x02u)\r
-#define ILO_CONTROL_100KHZ_ON (0x04u)\r
-#define ILO_CONTROL_33KHZ_ON (0x20u)\r
+/* CyILO_[Start|Stop][1|100K](), CyILO_[Enable|Disable]33K() */\r
+#define CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ (0x02u)\r
+#define CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ (0x20u)\r
+#define CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ (0x04u)\r
\r
-#define USB_CLKDIST_CONFIG_MASK (0x03u)\r
-#define USB_CLK_IMO2X (0x00u)\r
-#define USB_CLK_IMO (0x01u)\r
-#define USB_CLK_PLL (0x02u)\r
-#define USB_CLK_DSI (0x03u)\r
-#define USB_CLK_DIV2_ON (0x04u)\r
-#define USB_CLK_STOP_FLAG (0x00u)\r
-#define USB_CLK_START_FLAG (0x01u)\r
\r
-#define FTW_CLEAR_ALL_BITS (0x00u) /* To clear all bits of PM_TW_CFG2 */\r
-#define FTW_CLEAR_FTW_BITS (0xFCu) /* To clear FTW bits of PM_TW_CFG2 */\r
-#define FTW_ENABLE (0x01u) /* To enable FTW, no interrupt */\r
+/* CyUsbClk_SetSource() */\r
+#define CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK (0x03u)\r
+\r
\r
+/* CyUsbClk_SetSource() - parameters */\r
+#define CY_LIB_USB_CLK_IMO2X (0x00u)\r
+#define CY_LIB_USB_CLK_IMO (0x01u)\r
+#define CY_LIB_USB_CLK_PLL (0x02u)\r
+#define CY_LIB_USB_CLK_DSI (0x03u)\r
+\r
+\r
+/* CyUSB_PowerOnCheck() */\r
#define CY_ACT_USB_ENABLED (0x01u)\r
#define CY_ALT_ACT_USB_ENABLED (0x01u)\r
\r
***************************************/\r
\r
\r
+/*******************************************************************************\r
+* System Registers\r
+*******************************************************************************/\r
+\r
+/* Software Reset Control Register */\r
+#define CY_LIB_RESET_CR2_REG (* (reg8 *) CYREG_RESET_CR2)\r
+#define CY_LIB_RESET_CR2_PTR ( (reg8 *) CYREG_RESET_CR2)\r
+\r
+/* Timewheel Configuration Register 0 */\r
+#define CY_LIB_PM_TW_CFG0_REG (*(reg8 *) CYREG_PM_TW_CFG0)\r
+#define CY_LIB_PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0)\r
+\r
+/* Timewheel Configuration Register 2 */\r
+#define CY_LIB_PM_TW_CFG2_REG (*(reg8 *) CYREG_PM_TW_CFG2)\r
+#define CY_LIB_PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2)\r
+\r
+/* USB Configuration Register */\r
+#define CY_LIB_CLKDIST_UCFG_REG (*(reg8 *) CYREG_CLKDIST_UCFG)\r
+#define CY_LIB_CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG)\r
+\r
+/* Internal Main Oscillator Trim Register 1 */\r
+#define CY_LIB_IMO_TR1_REG (*(reg8 *) CYREG_IMO_TR1)\r
+#define CY_LIB_IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1)\r
+\r
+/* USB control 1 Register */\r
+#define CY_LIB_USB_CR1_REG (*(reg8 *) CYREG_USB_CR1 )\r
+#define CY_LIB_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 )\r
+\r
+/* Active Power Mode Configuration Register 0 */\r
+#define CY_LIB_PM_ACT_CFG0_REG (*(reg8 *) CYREG_PM_ACT_CFG0)\r
+#define CY_LIB_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)\r
+\r
+/* Standby Power Mode Configuration Register 0 */\r
+#define CY_LIB_PM_STBY_CFG0_REG (*(reg8 *) CYREG_PM_STBY_CFG0)\r
+#define CY_LIB_PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0)\r
+\r
+/* Active Power Mode Configuration Register 5 */\r
+#define CY_LIB_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 )\r
+#define CY_LIB_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 )\r
+\r
+/* Standby Power Mode Configuration Register 5 */\r
+#define CY_LIB_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 )\r
+#define CY_LIB_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 )\r
+\r
+/* CyIMO_SetTrimValue() */\r
+#if(CY_PSOC3)\r
+ #define CY_LIB_TRIM_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)\r
+ #define CY_LIB_TRIM_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)\r
+ #define CY_LIB_TRIM_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)\r
+ #define CY_LIB_TRIM_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)\r
+ #define CY_LIB_TRIM_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)\r
+ #define CY_LIB_TRIM_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)\r
+ #define CY_LIB_TRIM_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB)\r
+ #define CY_LIB_TRIM_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))\r
+ #else\r
+ #define CY_LIB_TRIM_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)\r
+ #define CY_LIB_TRIM_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)\r
+ #define CY_LIB_TRIM_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)\r
+ #define CY_LIB_TRIM_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)\r
+ #define CY_LIB_TRIM_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)\r
+ #define CY_LIB_TRIM_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)\r
+ #define CY_LIB_TRIM_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB)\r
+ #define CY_LIB_TRIM_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
/*******************************************************************************\r
* PLL Registers\r
*******************************************************************************/\r
*******************************************************************************/\r
\r
/* External MHz Crystal Oscillator Status and Control Register */\r
-#define CY_CLK_XMHZ_CSR_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CSR)\r
-#define CY_CLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR)\r
+#define CY_CLK_XMHZ_CSR_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CSR)\r
+#define CY_CLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR)\r
\r
/* External MHz Crystal Oscillator Configuration Register 0 */\r
-#define CY_CLK_XMHZ_CFG0_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG0)\r
-#define CY_CLK_XMHZ_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG0)\r
+#define CY_CLK_XMHZ_CFG0_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG0)\r
+#define CY_CLK_XMHZ_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG0)\r
\r
/* External MHz Crystal Oscillator Configuration Register 1 */\r
-#define CY_CLK_XMHZ_CFG1_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG1)\r
-#define CY_CLK_XMHZ_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG1)\r
+#define CY_CLK_XMHZ_CFG1_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG1)\r
+#define CY_CLK_XMHZ_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG1)\r
\r
\r
/*******************************************************************************\r
*******************************************************************************/\r
\r
/* 32 kHz Watch Crystal Oscillator Trim Register */\r
-#define CY_CLK_XTAL32_TR_REG (*(reg8 *) CYREG_X32_TR)\r
-#define CY_CLK_XTAL32_TR_PTR ( (reg8 *) CYREG_X32_TR)\r
+#define CY_CLK_XTAL32_TR_REG (*(reg8 *) CYREG_X32_TR)\r
+#define CY_CLK_XTAL32_TR_PTR ( (reg8 *) CYREG_X32_TR)\r
\r
/* External 32kHz Crystal Oscillator Test Register */\r
-#define CY_CLK_XTAL32_TST_REG (*(reg8 *) CYREG_SLOWCLK_X32_TST)\r
-#define CY_CLK_XTAL32_TST_PTR ( (reg8 *) CYREG_SLOWCLK_X32_TST)\r
+#define CY_CLK_XTAL32_TST_REG (*(reg8 *) CYREG_SLOWCLK_X32_TST)\r
+#define CY_CLK_XTAL32_TST_PTR ( (reg8 *) CYREG_SLOWCLK_X32_TST)\r
\r
/* External 32kHz Crystal Oscillator Control Register */\r
-#define CY_CLK_XTAL32_CR_REG (*(reg8 *) CYREG_SLOWCLK_X32_CR)\r
-#define CY_CLK_XTAL32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR)\r
+#define CY_CLK_XTAL32_CR_REG (*(reg8 *) CYREG_SLOWCLK_X32_CR)\r
+#define CY_CLK_XTAL32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR)\r
\r
/* External 32kHz Crystal Oscillator Configuration Register */\r
-#define CY_CLK_XTAL32_CFG_REG (*(reg8 *) CYREG_SLOWCLK_X32_CFG)\r
-#define CY_CLK_XTAL32_CFG_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CFG)\r
+#define CY_CLK_XTAL32_CFG_REG (*(reg8 *) CYREG_SLOWCLK_X32_CFG)\r
+#define CY_CLK_XTAL32_CFG_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CFG)\r
\r
\r
/*******************************************************************************\r
* LVI/HVI Registers\r
*******************************************************************************/\r
\r
-#define CY_VD_LVI_TRIP_REG (* (reg8 *) CYDEV_RESET_CR0)\r
-#define CY_VD_LVI_TRIP_PTR ( (reg8 *) CYDEV_RESET_CR0)\r
+#define CY_VD_LVI_TRIP_REG (* (reg8 *) CYREG_RESET_CR0)\r
+#define CY_VD_LVI_TRIP_PTR ( (reg8 *) CYREG_RESET_CR0)\r
\r
-#define CY_VD_LVI_HVI_CONTROL_REG (* (reg8 *) CYDEV_RESET_CR1)\r
-#define CY_VD_LVI_HVI_CONTROL_PTR ( (reg8 *) CYDEV_RESET_CR1)\r
+#define CY_VD_LVI_HVI_CONTROL_REG (* (reg8 *) CYREG_RESET_CR1)\r
+#define CY_VD_LVI_HVI_CONTROL_PTR ( (reg8 *) CYREG_RESET_CR1)\r
\r
-#define CY_VD_PRES_CONTROL_REG (* (reg8 *) CYDEV_RESET_CR3)\r
-#define CY_VD_PRES_CONTROL_PTR ( (reg8 *) CYDEV_RESET_CR3)\r
+#define CY_VD_PRES_CONTROL_REG (* (reg8 *) CYREG_RESET_CR3)\r
+#define CY_VD_PRES_CONTROL_PTR ( (reg8 *) CYREG_RESET_CR3)\r
\r
-#define CY_VD_PERSISTENT_STATUS_REG (* (reg8 *) CYDEV_RESET_SR0)\r
-#define CY_VD_PERSISTENT_STATUS_PTR ( (reg8 *) CYDEV_RESET_SR0)\r
+#define CY_VD_PERSISTENT_STATUS_REG (* (reg8 *) CYREG_RESET_SR0)\r
+#define CY_VD_PERSISTENT_STATUS_PTR ( (reg8 *) CYREG_RESET_SR0)\r
\r
-#define CY_VD_RT_STATUS_REG (* (reg8 *) CYDEV_RESET_SR2)\r
-#define CY_VD_RT_STATUS_PTR ( (reg8 *) CYDEV_RESET_SR2)\r
+#define CY_VD_RT_STATUS_REG (* (reg8 *) CYREG_RESET_SR2)\r
+#define CY_VD_RT_STATUS_PTR ( (reg8 *) CYREG_RESET_SR2)\r
\r
\r
/*******************************************************************************\r
* Variable VDDA\r
*******************************************************************************/\r
-#if(!CY_PSOC5A)\r
-\r
- #if(CYDEV_VARIABLE_VDDA == 1)\r
-\r
- /* Active Power Mode Configuration Register 9 */\r
- #define CY_LIB_ACT_CFG9_REG (* (reg8 *) CYREG_PM_ACT_CFG9 )\r
- #define CY_LIB_ACT_CFG9_PTR ( (reg8 *) CYREG_PM_ACT_CFG9 )\r
+#if(CYDEV_VARIABLE_VDDA == 1)\r
\r
- /* Switched Capacitor 0 Boost Clock Selection Register */\r
- #define CY_LIB_SC0_BST_REG (* (reg8 *) CYREG_SC0_BST )\r
- #define CY_LIB_SC0_BST_PTR ( (reg8 *) CYREG_SC0_BST )\r
+ /* Active Power Mode Configuration Register 9 */\r
+ #define CY_LIB_ACT_CFG9_REG (* (reg8 *) CYREG_PM_ACT_CFG9 )\r
+ #define CY_LIB_ACT_CFG9_PTR ( (reg8 *) CYREG_PM_ACT_CFG9 )\r
\r
- /* Switched Capacitor 1 Boost Clock Selection Register */\r
- #define CY_LIB_SC1_BST_REG (* (reg8 *) CYREG_SC1_BST )\r
- #define CY_LIB_SC1_BST_PTR ( (reg8 *) CYREG_SC1_BST )\r
+ /* Switched Capacitor 0 Boost Clock Selection Register */\r
+ #define CY_LIB_SC0_BST_REG (* (reg8 *) CYREG_SC0_BST )\r
+ #define CY_LIB_SC0_BST_PTR ( (reg8 *) CYREG_SC0_BST )\r
\r
- /* Switched Capacitor 2 Boost Clock Selection Register */\r
- #define CY_LIB_SC2_BST_REG (* (reg8 *) CYREG_SC2_BST )\r
- #define CY_LIB_SC2_BST_PTR ( (reg8 *) CYREG_SC2_BST )\r
+ /* Switched Capacitor 1 Boost Clock Selection Register */\r
+ #define CY_LIB_SC1_BST_REG (* (reg8 *) CYREG_SC1_BST )\r
+ #define CY_LIB_SC1_BST_PTR ( (reg8 *) CYREG_SC1_BST )\r
\r
- /* Switched Capacitor 3 Boost Clock Selection Register */\r
- #define CY_LIB_SC3_BST_REG (* (reg8 *) CYREG_SC3_BST )\r
- #define CY_LIB_SC3_BST_PTR ( (reg8 *) CYREG_SC3_BST )\r
+ /* Switched Capacitor 2 Boost Clock Selection Register */\r
+ #define CY_LIB_SC2_BST_REG (* (reg8 *) CYREG_SC2_BST )\r
+ #define CY_LIB_SC2_BST_PTR ( (reg8 *) CYREG_SC2_BST )\r
\r
- /* Switched Cap Miscellaneous Control Register */\r
- #define CY_LIB_SC_MISC_REG (* (reg8 *) CYREG_SC_MISC )\r
- #define CY_LIB_SC_MISC_PTR ( (reg8 *) CYREG_SC_MISC )\r
+ /* Switched Capacitor 3 Boost Clock Selection Register */\r
+ #define CY_LIB_SC3_BST_REG (* (reg8 *) CYREG_SC3_BST )\r
+ #define CY_LIB_SC3_BST_PTR ( (reg8 *) CYREG_SC3_BST )\r
\r
- #endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
+ /* Switched Cap Miscellaneous Control Register */\r
+ #define CY_LIB_SC_MISC_REG (* (reg8 *) CYREG_SC_MISC )\r
+ #define CY_LIB_SC_MISC_PTR ( (reg8 *) CYREG_SC_MISC )\r
\r
-#endif /* (!CY_PSOC5A) */\r
+#endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
\r
\r
/*******************************************************************************\r
#define CY_LIB_CLKDIST_CR_REG (*(reg8 *) CYREG_CLKDIST_CR)\r
#define CY_LIB_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR)\r
\r
-\r
-#define SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0)\r
-#define SLOWCLK_ILO_CR0 (*(reg8 *) CYREG_SLOWCLK_ILO_CR0)\r
-#define CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG)\r
-#define CLKDIST_UCFG (*(reg8 *) CYREG_CLKDIST_UCFG)\r
-\r
-#define PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0)\r
-#define PM_TW_CFG0 (*(reg8 *) CYREG_PM_TW_CFG0)\r
-\r
-#define PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2)\r
-#define PM_TW_CFG2 (*(reg8 *) CYREG_PM_TW_CFG2)\r
-\r
-#define CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1)\r
-#define CLKDIST_MSTR1 (*(reg8 *) CYREG_CLKDIST_MSTR1)\r
-\r
-\r
-\r
-#define SFR_USER_CPUCLK_DIV_PTR ((void far *) CYREG_SFR_USER_CPUCLK_DIV)\r
-\r
-#define CLOCK_CONTROL ( (reg8 *) CYREG_CLKDIST_CR)\r
-#define IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1)\r
-#define IMO_TR1 (*(reg8 *) CYREG_IMO_TR1)\r
-#define CY_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 )\r
-#define CY_USB_CR1 (*(reg8 *) CYREG_USB_CR1 )\r
-\r
-#define PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)\r
-#define PM_ACT_CFG0 (*(reg8 *) CYREG_PM_ACT_CFG0)\r
-#define PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0)\r
-#define PM_STBY_CFG0 (*(reg8 *) CYREG_PM_STBY_CFG0)\r
-#define PM_AVAIL_CR2_PTR ( (reg8 *) CYREG_PM_AVAIL_CR2)\r
-#define PM_AVAIL_CR2 (*(reg8 *) CYREG_PM_AVAIL_CR2)\r
-\r
-\r
-/* Active Power Mode Configuration Register 5 */\r
-#define CY_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 )\r
-#define CY_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 )\r
-\r
-/* Standby Power Mode Configuration Register 5 */\r
-#define CY_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 )\r
-#define CY_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 )\r
-\r
-\r
-#if(CY_PSOC3)\r
- #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)\r
- #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)\r
- #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)\r
- #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)\r
- #define FLSHID_MFG_CFG_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))\r
- #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)\r
- #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)\r
- #define FLSHID_CUST_TABLES_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB)\r
- #else\r
- #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)\r
- #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)\r
- #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)\r
- #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)\r
- #define FLSHID_MFG_CFG_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))\r
- #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)\r
- #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)\r
- #define FLSHID_CUST_TABLES_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB)\r
-#endif /* (CY_PSOC3) */\r
-\r
-\r
-#define USB_CLKDIST_CONFIG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG)\r
-#define USB_CLKDIST_CONFIG (*(reg8 *) CYREG_CLKDIST_UCFG)\r
+/* Internal Low-speed Oscillator Control Register 0 */\r
+#define CY_LIB_SLOWCLK_ILO_CR0_REG (*(reg8 *) CYREG_SLOWCLK_ILO_CR0)\r
+#define CY_LIB_SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0)\r
\r
\r
/*******************************************************************************\r
#define CY_INT_ENABLE_REG (* (reg8 *) CYREG_INTC_SET_EN0)\r
#define CY_INT_ENABLE_PTR ( (reg8 *) CYREG_INTC_SET_EN0)\r
\r
- #define CY_INT_SET_EN0_REG (* (reg8 *) CYREG_INTC_SET_EN0)\r
- #define CY_INT_SET_EN0_PTR ( (reg8 *) CYREG_INTC_SET_EN0)\r
+ #define CY_INT_SET_EN0_REG (* (reg8 *) CYREG_INTC_SET_EN0)\r
+ #define CY_INT_SET_EN0_PTR ( (reg8 *) CYREG_INTC_SET_EN0)\r
\r
- #define CY_INT_SET_EN1_REG (* (reg8 *) CYREG_INTC_SET_EN1)\r
- #define CY_INT_SET_EN1_PTR ( (reg8 *) CYREG_INTC_SET_EN1)\r
+ #define CY_INT_SET_EN1_REG (* (reg8 *) CYREG_INTC_SET_EN1)\r
+ #define CY_INT_SET_EN1_PTR ( (reg8 *) CYREG_INTC_SET_EN1)\r
\r
- #define CY_INT_SET_EN2_REG (* (reg8 *) CYREG_INTC_SET_EN2)\r
- #define CY_INT_SET_EN2_PTR ( (reg8 *) CYREG_INTC_SET_EN2)\r
+ #define CY_INT_SET_EN2_REG (* (reg8 *) CYREG_INTC_SET_EN2)\r
+ #define CY_INT_SET_EN2_PTR ( (reg8 *) CYREG_INTC_SET_EN2)\r
\r
- #define CY_INT_SET_EN3_REG (* (reg8 *) CYREG_INTC_SET_EN3)\r
- #define CY_INT_SET_EN3_PTR ( (reg8 *) CYREG_INTC_SET_EN3)\r
+ #define CY_INT_SET_EN3_REG (* (reg8 *) CYREG_INTC_SET_EN3)\r
+ #define CY_INT_SET_EN3_PTR ( (reg8 *) CYREG_INTC_SET_EN3)\r
\r
/* Interrrupt Controller Clear Enable Registers */\r
#define CY_INT_CLEAR_REG (* (reg8 *) CYREG_INTC_CLR_EN0)\r
#define CY_INT_CLEAR_PTR ( (reg8 *) CYREG_INTC_CLR_EN0)\r
\r
- #define CY_INT_CLR_EN0_REG (* (reg8 *) CYREG_INTC_CLR_EN0)\r
- #define CY_INT_CLR_EN0_PTR ( (reg8 *) CYREG_INTC_CLR_EN0)\r
+ #define CY_INT_CLR_EN0_REG (* (reg8 *) CYREG_INTC_CLR_EN0)\r
+ #define CY_INT_CLR_EN0_PTR ( (reg8 *) CYREG_INTC_CLR_EN0)\r
\r
- #define CY_INT_CLR_EN1_REG (* (reg8 *) CYREG_INTC_CLR_EN1)\r
- #define CY_INT_CLR_EN1_PTR ( (reg8 *) CYREG_INTC_CLR_EN1)\r
+ #define CY_INT_CLR_EN1_REG (* (reg8 *) CYREG_INTC_CLR_EN1)\r
+ #define CY_INT_CLR_EN1_PTR ( (reg8 *) CYREG_INTC_CLR_EN1)\r
\r
- #define CY_INT_CLR_EN2_REG (* (reg8 *) CYREG_INTC_CLR_EN2)\r
- #define CY_INT_CLR_EN2_PTR ( (reg8 *) CYREG_INTC_CLR_EN2)\r
+ #define CY_INT_CLR_EN2_REG (* (reg8 *) CYREG_INTC_CLR_EN2)\r
+ #define CY_INT_CLR_EN2_PTR ( (reg8 *) CYREG_INTC_CLR_EN2)\r
\r
- #define CY_INT_CLR_EN3_REG (* (reg8 *) CYREG_INTC_CLR_EN3)\r
- #define CY_INT_CLR_EN3_PTR ( (reg8 *) CYREG_INTC_CLR_EN3)\r
+ #define CY_INT_CLR_EN3_REG (* (reg8 *) CYREG_INTC_CLR_EN3)\r
+ #define CY_INT_CLR_EN3_PTR ( (reg8 *) CYREG_INTC_CLR_EN3)\r
\r
\r
/* Interrrupt Controller Set Pend Registers */\r
#if defined(__ARMCC_VERSION)\r
#define CyGlobalIntEnable {__enable_irq();}\r
#define CyGlobalIntDisable {__disable_irq();}\r
-#elif defined(__GNUC__)\r
+#elif defined(__GNUC__) || defined (__ICCARM__)\r
#define CyGlobalIntEnable {__asm("CPSIE i");}\r
#define CyGlobalIntDisable {__asm("CPSID i");}\r
#elif defined(__C51__)\r
CY_NOP; \\r
EA = 0u;\\r
}\r
+#else\r
+ #error No compiler toolchain defined\r
+ #define CyGlobalIntEnable\r
+ #define CyGlobalIntDisable\r
#endif /* (__ARMCC_VERSION) */\r
\r
\r
#define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID))\r
#endif /* (CYREG_MLOGIC_REV_ID_REV_ID) */\r
\r
-#define RESET_CR2 ((reg8 *) CYREG_RESET_CR2)\r
-\r
\r
/*******************************************************************************\r
* System API constants\r
*******************************************************************************/\r
#define CY_CACHE_CONTROL_FLUSH (0x0004u)\r
+#define CY_LIB_RESET_CR2_RESET (0x01u)\r
\r
\r
/*******************************************************************************\r
#define X32_CONTROL_LPM (CY_CLK_XTAL32_CR_LPM)\r
#define X32_CONTROL_LPM_POSITION (1u)\r
#define X32_CONTROL_X32EN (CY_CLK_XTAL32_CR_EN)\r
-#if(CY_PSOC3 || CY_PSOC5LP)\r
- #define X32_CONTROL_PDBEN (CY_CLK_XTAL32_CR_PDBEN)\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+#define X32_CONTROL_PDBEN (CY_CLK_XTAL32_CR_PDBEN)\r
#define X32_TR_DPMODE (CY_CLK_XTAL32_TR_STARTUP)\r
#define X32_TR_CLEAR (CY_CLK_XTAL32_TR_POWERDOWN)\r
#define X32_TR_HPMODE (CY_CLK_XTAL32_TR_HIGH_POWER)\r
#define CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR)\r
#define CLKDIST_CR (*(reg8 *) CYREG_CLKDIST_CR)\r
\r
+\r
+/*******************************************************************************\r
+* Following code are OBSOLETE and must not be used starting from cy_boot 3.50\r
+*******************************************************************************/\r
+#define IMO_PM_ENABLE (0x10u)\r
+#define PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)\r
+#define PM_ACT_CFG0 (*(reg8 *) CYREG_PM_ACT_CFG0)\r
+#define SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0)\r
+#define SLOWCLK_ILO_CR0 (*(reg8 *) CYREG_SLOWCLK_ILO_CR0)\r
+#define ILO_CONTROL_PD_MODE (0x10u)\r
+#define ILO_CONTROL_PD_POSITION (4u)\r
+#define ILO_CONTROL_1KHZ_ON (0x02u)\r
+#define ILO_CONTROL_100KHZ_ON (0x04u)\r
+#define ILO_CONTROL_33KHZ_ON (0x20u)\r
+#define PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0)\r
+#define PM_TW_CFG0 (*(reg8 *) CYREG_PM_TW_CFG0)\r
+#define PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2)\r
+#define PM_TW_CFG2 (*(reg8 *) CYREG_PM_TW_CFG2)\r
+#define RESET_CR2 ((reg8 *) CYREG_RESET_CR2)\r
+#define FASTCLK_IMO_USBCLK_ON_SET (0x40u)\r
+#define CLOCK_IMO_3MHZ_VALUE (0x03u)\r
+#define CLOCK_IMO_6MHZ_VALUE (0x01u)\r
+#define CLOCK_IMO_12MHZ_VALUE (0x00u)\r
+#define CLOCK_IMO_24MHZ_VALUE (0x02u)\r
+#define CLOCK_IMO_48MHZ_VALUE (0x04u)\r
+#define CLOCK_IMO_62MHZ_VALUE (0x05u)\r
+#define CLOCK_IMO_74MHZ_VALUE (0x06u)\r
+#define CLKDIST_DIV_POSITION (4u)\r
+#define CLKDIST_MSTR1_DIV_CLEAR (0x0Fu)\r
+#define SFR_USER_CPUCLK_DIV_MASK (0x0Fu)\r
+#define CLOCK_USB_ENABLE (0x02u)\r
+#define CLOCK_IMO_OUT_X2 (0x10u)\r
+#define CLOCK_IMO_OUT_X1 ((uint8)(~CLOCK_IMO_OUT_X2))\r
+#define CLOCK_IMO2X_ECO ((uint8)(~CLOCK_IMO2X_DSI))\r
+#define USB_CLKDIST_CONFIG_MASK (0x03u)\r
+#define USB_CLK_IMO2X (0x00u)\r
+#define USB_CLK_IMO (0x01u)\r
+#define USB_CLK_PLL (0x02u)\r
+#define USB_CLK_DSI (0x03u)\r
+#define USB_CLK_DIV2_ON (0x04u)\r
+#define USB_CLK_STOP_FLAG (0x00u)\r
+#define USB_CLK_START_FLAG (0x01u)\r
+#define FTW_CLEAR_ALL_BITS (0x00u)\r
+#define FTW_CLEAR_FTW_BITS (0xFCu)\r
+#define FTW_ENABLE (0x01u)\r
+#define PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0)\r
+#define PM_STBY_CFG0 (*(reg8 *) CYREG_PM_STBY_CFG0)\r
+#define PM_AVAIL_CR2_PTR ( (reg8 *) CYREG_PM_AVAIL_CR2)\r
+#define PM_AVAIL_CR2 (*(reg8 *) CYREG_PM_AVAIL_CR2)\r
+#define CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG)\r
+#define CLKDIST_UCFG (*(reg8 *) CYREG_CLKDIST_UCFG)\r
+#define CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1)\r
+#define CLKDIST_MSTR1 (*(reg8 *) CYREG_CLKDIST_MSTR1)\r
+#define SFR_USER_CPUCLK_DIV_PTR ((void far *) CYREG_SFR_USER_CPUCLK_DIV)\r
+#define IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1)\r
+#define IMO_TR1 (*(reg8 *) CYREG_IMO_TR1)\r
+#define CLOCK_CONTROL ( (reg8 *) CYREG_CLKDIST_CR)\r
+#define CY_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 )\r
+#define CY_USB_CR1 (*(reg8 *) CYREG_USB_CR1 )\r
+#define USB_CLKDIST_CONFIG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG)\r
+#define USB_CLKDIST_CONFIG (*(reg8 *) CYREG_CLKDIST_UCFG)\r
+#define CY_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 )\r
+#define CY_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 )\r
+#define CY_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 )\r
+#define CY_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 )\r
+#if(CY_PSOC3)\r
+ #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB)\r
+ #define FLSHID_MFG_CFG_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))\r
+ #else\r
+ #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB)\r
+ #define FLSHID_MFG_CFG_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
#endif /* (CY_BOOT_CYLIB_H) */\r
\r
\r
/*******************************************************************************\r
* File Name: CySpc.c\r
-* Version 3.40\r
+* Version 4.0\r
*\r
* Description:\r
* Provides an API for the System Performance Component.\r
uint8 SpcLockState = CY_SPC_UNLOCKED;\r
\r
\r
-#if(CY_PSOC5LP)\r
+#if(CY_PSOC5)\r
\r
/***************************************************************************\r
* The wait-state pipeline must be enabled prior to accessing the SPC\r
* function, which must be called after SPC transaction, restores original\r
* state.\r
***************************************************************************/\r
- static uint8 spcWaitPipeBypass = 0u;\r
+ static uint32 spcWaitPipeBypass = 0u;\r
\r
-#endif /* (CY_PSOC5LP) */\r
+#endif /* (CY_PSOC5) */\r
\r
\r
/*******************************************************************************\r
* CYRET_BAD_PARAM\r
*\r
*******************************************************************************/\r
-cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size) \r
+cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\\r
+\r
{\r
cystatus status = CYRET_STARTED;\r
uint8 i;\r
* CYRET_LOCKED\r
*\r
*******************************************************************************/\r
-cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\r
+cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\\r
+\r
{\r
cystatus status = CYRET_STARTED;\r
\r
* CYRET_LOCKED\r
*\r
*******************************************************************************/\r
-#if(CY_PSOC5A)\r
-cystatus CySpcGetTemp(uint8 numSamples, uint16 timerPeriod, uint8 clkDivSelect)\r
-#else\r
cystatus CySpcGetTemp(uint8 numSamples)\r
-#endif /* (CY_PSOC5A) */\r
{\r
cystatus status = CYRET_STARTED;\r
\r
if(CY_SPC_BUSY)\r
{\r
CY_SPC_CPU_DATA_REG = numSamples;\r
-\r
- #if(CY_PSOC5A)\r
- CY_SPC_CPU_DATA_REG = HI8(timerPeriod);\r
- CY_SPC_CPU_DATA_REG = LO8(timerPeriod);\r
- CY_SPC_CPU_DATA_REG = clkDivSelect;\r
- #endif /* (CY_PSOC5A) */\r
}\r
else\r
{\r
SpcLockState = CY_SPC_LOCKED;\r
status = CYRET_SUCCESS;\r
\r
- #if(CY_PSOC5LP)\r
+ #if(CY_PSOC5)\r
\r
if(0u != (CY_SPC_CPU_WAITPIPE_REG & CY_SPC_CPU_WAITPIPE_BYPASS))\r
{\r
spcWaitPipeBypass = CY_SPC_CPU_WAITPIPE_BYPASS;\r
}\r
\r
- #endif /* (CY_PSOC5LP) */\r
+ #endif /* (CY_PSOC5) */\r
}\r
\r
/* Exit critical section */\r
/* Release the SPC object */\r
SpcLockState = CY_SPC_UNLOCKED;\r
\r
- #if(CY_PSOC5LP)\r
+ #if(CY_PSOC5)\r
\r
if(CY_SPC_CPU_WAITPIPE_BYPASS == spcWaitPipeBypass)\r
{\r
spcWaitPipeBypass = 0u;\r
}\r
\r
- #endif /* (CY_PSOC5LP) */\r
+ #endif /* (CY_PSOC5) */\r
\r
/* Exit critical section */\r
CyExitCriticalSection(interruptState);\r
/*******************************************************************************\r
* File Name: CySpc.c\r
-* Version 3.40\r
+* Version 4.0\r
*\r
* Description:\r
* Provides definitions for the System Performance Component API.\r
void CySpcStart(void);\r
void CySpcStop(void);\r
uint8 CySpcReadData(uint8 buffer[], uint8 size);\r
-cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size) ;\r
+cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\\r
+;\r
cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size);\r
-cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude) ;\r
+cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\\r
+;\r
cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber);\r
-\r
-#if(CY_PSOC5A)\r
- cystatus CySpcGetTemp(uint8 numSamples, uint16 timerPeriod, uint8 clkDivSelect);\r
-#else\r
- cystatus CySpcGetTemp(uint8 numSamples);\r
-#endif /* (CY_PSOC5A) */\r
-\r
-\r
+cystatus CySpcGetTemp(uint8 numSamples);\r
cystatus CySpcLock(void);\r
void CySpcUnlock(void);\r
\r
#define CY_SPC_STATUS_TADC_INPUT (0x0Du) /* Invalid input value for Get Temp & Get ADC commands */\r
#define CY_SPC_STATUS_BUSY (0xFFu) /* SPC is busy */\r
\r
-#if(CY_PSOC5LP)\r
+#if(CY_PSOC5)\r
\r
/* Wait-state pipeline */\r
#define CY_SPC_CPU_WAITPIPE_BYPASS ((uint32)0x01u)\r
\r
-#endif /* (CY_PSOC5LP) */\r
+#endif /* (CY_PSOC5) */\r
\r
\r
/***************************************\r
#define CY_SPC_PM_STBY_REG (* (reg8 *) CYREG_PM_STBY_CFG0 )\r
#define CY_SPC_PM_STBY_PTR ( (reg8 *) CYREG_PM_STBY_CFG0 )\r
\r
-#if(CY_PSOC5LP)\r
+#if(CY_PSOC5)\r
\r
/* Wait State Pipeline */\r
#define CY_SPC_CPU_WAITPIPE_REG (* (reg32 *) CYREG_PANTHER_WAITPIPE )\r
#define CY_SPC_CPU_WAITPIPE_PTR ( (reg32 *) CYREG_PANTHER_WAITPIPE )\r
\r
-#endif /* (CY_PSOC5LP) */\r
+#endif /* (CY_PSOC5) */\r
\r
\r
/***************************************\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_ATN.c \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file contains API to enable firmware control of a Pins component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "cytypes.h"\r
+#include "SCSI_ATN.h"\r
+\r
+/* APIs are not generated for P15[7:6] on PSoC 5 */\r
+#if !(CY_PSOC5A &&\\r
+ SCSI_ATN__PORT == 15 && ((SCSI_ATN__MASK & 0xC0) != 0))\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_ATN_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Assign a new value to the digital port's data output register. \r
+*\r
+* Parameters: \r
+* prtValue: The value to be assigned to the Digital Port. \r
+*\r
+* Return: \r
+* None\r
+* \r
+*******************************************************************************/\r
+void SCSI_ATN_Write(uint8 value) \r
+{\r
+ uint8 staticBits = (SCSI_ATN_DR & (uint8)(~SCSI_ATN_MASK));\r
+ SCSI_ATN_DR = staticBits | ((uint8)(value << SCSI_ATN_SHIFT) & SCSI_ATN_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_ATN_SetDriveMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Change the drive mode on the pins of the port.\r
+* \r
+* Parameters: \r
+* mode: Change the pins to this drive mode.\r
+*\r
+* Return: \r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_ATN_SetDriveMode(uint8 mode) \r
+{\r
+ CyPins_SetPinDriveMode(SCSI_ATN_0, mode);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_ATN_Read\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value on the pins of the Digital Port in right justified \r
+* form.\r
+*\r
+* Parameters: \r
+* None\r
+*\r
+* Return: \r
+* Returns the current value of the Digital Port as a right justified number\r
+* \r
+* Note:\r
+* Macro SCSI_ATN_ReadPS calls this function. \r
+* \r
+*******************************************************************************/\r
+uint8 SCSI_ATN_Read(void) \r
+{\r
+ return (SCSI_ATN_PS & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_ATN_ReadDataReg\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value assigned to a Digital Port's data output register\r
+*\r
+* Parameters: \r
+* None \r
+*\r
+* Return: \r
+* Returns the current value assigned to the Digital Port's data output register\r
+* \r
+*******************************************************************************/\r
+uint8 SCSI_ATN_ReadDataReg(void) \r
+{\r
+ return (SCSI_ATN_DR & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT;\r
+}\r
+\r
+\r
+/* If Interrupts Are Enabled for this Pins component */ \r
+#if defined(SCSI_ATN_INTSTAT) \r
+\r
+ /*******************************************************************************\r
+ * Function Name: SCSI_ATN_ClearInterrupt\r
+ ********************************************************************************\r
+ * Summary:\r
+ * Clears any active interrupts attached to port and returns the value of the \r
+ * interrupt status register.\r
+ *\r
+ * Parameters: \r
+ * None \r
+ *\r
+ * Return: \r
+ * Returns the value of the interrupt status register\r
+ * \r
+ *******************************************************************************/\r
+ uint8 SCSI_ATN_ClearInterrupt(void) \r
+ {\r
+ return (SCSI_ATN_INTSTAT & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT;\r
+ }\r
+\r
+#endif /* If Interrupts Are Enabled for this Pins component */ \r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+ \r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_ATN.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SCSI_ATN_H) /* Pins SCSI_ATN_H */\r
+#define CY_PINS_SCSI_ATN_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "cypins.h"\r
+#include "SCSI_ATN_aliases.h"\r
+\r
+/* Check to see if required defines such as CY_PSOC5A are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5A)\r
+ #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* APIs are not generated for P15[7:6] */\r
+#if !(CY_PSOC5A &&\\r
+ SCSI_ATN__PORT == 15 && ((SCSI_ATN__MASK & 0xC0) != 0))\r
+\r
+\r
+/***************************************\r
+* Function Prototypes \r
+***************************************/ \r
+\r
+void SCSI_ATN_Write(uint8 value) ;\r
+void SCSI_ATN_SetDriveMode(uint8 mode) ;\r
+uint8 SCSI_ATN_ReadDataReg(void) ;\r
+uint8 SCSI_ATN_Read(void) ;\r
+uint8 SCSI_ATN_ClearInterrupt(void) ;\r
+\r
+\r
+/***************************************\r
+* API Constants \r
+***************************************/\r
+\r
+/* Drive Modes */\r
+#define SCSI_ATN_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+#define SCSI_ATN_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+#define SCSI_ATN_DM_RES_UP PIN_DM_RES_UP\r
+#define SCSI_ATN_DM_RES_DWN PIN_DM_RES_DWN\r
+#define SCSI_ATN_DM_OD_LO PIN_DM_OD_LO\r
+#define SCSI_ATN_DM_OD_HI PIN_DM_OD_HI\r
+#define SCSI_ATN_DM_STRONG PIN_DM_STRONG\r
+#define SCSI_ATN_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+\r
+/* Digital Port Constants */\r
+#define SCSI_ATN_MASK SCSI_ATN__MASK\r
+#define SCSI_ATN_SHIFT SCSI_ATN__SHIFT\r
+#define SCSI_ATN_WIDTH 1u\r
+\r
+\r
+/***************************************\r
+* Registers \r
+***************************************/\r
+\r
+/* Main Port Registers */\r
+/* Pin State */\r
+#define SCSI_ATN_PS (* (reg8 *) SCSI_ATN__PS)\r
+/* Data Register */\r
+#define SCSI_ATN_DR (* (reg8 *) SCSI_ATN__DR)\r
+/* Port Number */\r
+#define SCSI_ATN_PRT_NUM (* (reg8 *) SCSI_ATN__PRT) \r
+/* Connect to Analog Globals */ \r
+#define SCSI_ATN_AG (* (reg8 *) SCSI_ATN__AG) \r
+/* Analog MUX bux enable */\r
+#define SCSI_ATN_AMUX (* (reg8 *) SCSI_ATN__AMUX) \r
+/* Bidirectional Enable */ \r
+#define SCSI_ATN_BIE (* (reg8 *) SCSI_ATN__BIE)\r
+/* Bit-mask for Aliased Register Access */\r
+#define SCSI_ATN_BIT_MASK (* (reg8 *) SCSI_ATN__BIT_MASK)\r
+/* Bypass Enable */\r
+#define SCSI_ATN_BYP (* (reg8 *) SCSI_ATN__BYP)\r
+/* Port wide control signals */ \r
+#define SCSI_ATN_CTL (* (reg8 *) SCSI_ATN__CTL)\r
+/* Drive Modes */\r
+#define SCSI_ATN_DM0 (* (reg8 *) SCSI_ATN__DM0) \r
+#define SCSI_ATN_DM1 (* (reg8 *) SCSI_ATN__DM1)\r
+#define SCSI_ATN_DM2 (* (reg8 *) SCSI_ATN__DM2) \r
+/* Input Buffer Disable Override */\r
+#define SCSI_ATN_INP_DIS (* (reg8 *) SCSI_ATN__INP_DIS)\r
+/* LCD Common or Segment Drive */\r
+#define SCSI_ATN_LCD_COM_SEG (* (reg8 *) SCSI_ATN__LCD_COM_SEG)\r
+/* Enable Segment LCD */\r
+#define SCSI_ATN_LCD_EN (* (reg8 *) SCSI_ATN__LCD_EN)\r
+/* Slew Rate Control */\r
+#define SCSI_ATN_SLW (* (reg8 *) SCSI_ATN__SLW)\r
+\r
+/* DSI Port Registers */\r
+/* Global DSI Select Register */\r
+#define SCSI_ATN_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_ATN__PRTDSI__CAPS_SEL) \r
+/* Double Sync Enable */\r
+#define SCSI_ATN_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_ATN__PRTDSI__DBL_SYNC_IN) \r
+/* Output Enable Select Drive Strength */\r
+#define SCSI_ATN_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_ATN__PRTDSI__OE_SEL0) \r
+#define SCSI_ATN_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_ATN__PRTDSI__OE_SEL1) \r
+/* Port Pin Output Select Registers */\r
+#define SCSI_ATN_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_ATN__PRTDSI__OUT_SEL0) \r
+#define SCSI_ATN_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_ATN__PRTDSI__OUT_SEL1) \r
+/* Sync Output Enable Registers */\r
+#define SCSI_ATN_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_ATN__PRTDSI__SYNC_OUT) \r
+\r
+\r
+#if defined(SCSI_ATN__INTSTAT) /* Interrupt Registers */\r
+\r
+ #define SCSI_ATN_INTSTAT (* (reg8 *) SCSI_ATN__INTSTAT)\r
+ #define SCSI_ATN_SNAP (* (reg8 *) SCSI_ATN__SNAP)\r
+\r
+#endif /* Interrupt Registers */\r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+#endif /* CY_PINS_SCSI_ATN_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_ATN_ISR.c \r
+* Version 1.70\r
+*\r
+* Description:\r
+* API for controlling the state of an interrupt.\r
+*\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+\r
+#include <cydevice_trm.h>\r
+#include <CyLib.h>\r
+#include <SCSI_ATN_ISR.h>\r
+\r
+#if !defined(SCSI_ATN_ISR__REMOVED) /* Check for removal by optimization */\r
+\r
+/*******************************************************************************\r
+* Place your includes, defines and code here \r
+********************************************************************************/\r
+/* `#START SCSI_ATN_ISR_intc` */\r
+\r
+/* `#END` */\r
+\r
+#ifndef CYINT_IRQ_BASE\r
+#define CYINT_IRQ_BASE 16\r
+#endif /* CYINT_IRQ_BASE */\r
+#ifndef CYINT_VECT_TABLE\r
+#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)\r
+#endif /* CYINT_VECT_TABLE */\r
+\r
+/* Declared in startup, used to set unused interrupts to. */\r
+CY_ISR_PROTO(IntDefaultHandler);\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_ATN_ISR_Start\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Set up the interrupt and enable it.\r
+*\r
+* Parameters: \r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_ATN_ISR_Start(void)\r
+{\r
+ /* For all we know the interrupt is active. */\r
+ SCSI_ATN_ISR_Disable();\r
+\r
+ /* Set the ISR to point to the SCSI_ATN_ISR Interrupt. */\r
+ SCSI_ATN_ISR_SetVector(&SCSI_ATN_ISR_Interrupt);\r
+\r
+ /* Set the priority. */\r
+ SCSI_ATN_ISR_SetPriority((uint8)SCSI_ATN_ISR_INTC_PRIOR_NUMBER);\r
+\r
+ /* Enable it. */\r
+ SCSI_ATN_ISR_Enable();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_ATN_ISR_StartEx\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Set up the interrupt and enable it.\r
+*\r
+* Parameters: \r
+* address: Address of the ISR to set in the interrupt vector table.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_ATN_ISR_StartEx(cyisraddress address)\r
+{\r
+ /* For all we know the interrupt is active. */\r
+ SCSI_ATN_ISR_Disable();\r
+\r
+ /* Set the ISR to point to the SCSI_ATN_ISR Interrupt. */\r
+ SCSI_ATN_ISR_SetVector(address);\r
+\r
+ /* Set the priority. */\r
+ SCSI_ATN_ISR_SetPriority((uint8)SCSI_ATN_ISR_INTC_PRIOR_NUMBER);\r
+\r
+ /* Enable it. */\r
+ SCSI_ATN_ISR_Enable();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_ATN_ISR_Stop\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables and removes the interrupt.\r
+*\r
+* Parameters: \r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_ATN_ISR_Stop(void)\r
+{\r
+ /* Disable this interrupt. */\r
+ SCSI_ATN_ISR_Disable();\r
+\r
+ /* Set the ISR to point to the passive one. */\r
+ SCSI_ATN_ISR_SetVector(&IntDefaultHandler);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_ATN_ISR_Interrupt\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* The default Interrupt Service Routine for SCSI_ATN_ISR.\r
+*\r
+* Add custom code between the coments to keep the next version of this file\r
+* from over writting your code.\r
+*\r
+* Parameters: \r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+CY_ISR(SCSI_ATN_ISR_Interrupt)\r
+{\r
+ /* Place your Interrupt code here. */\r
+ /* `#START SCSI_ATN_ISR_Interrupt` */\r
+\r
+ /* `#END` */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_ATN_ISR_SetVector\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Change the ISR vector for the Interrupt. Note calling SCSI_ATN_ISR_Start\r
+* will override any effect this method would have had. To set the vector \r
+* before the component has been started use SCSI_ATN_ISR_StartEx instead.\r
+*\r
+* Parameters:\r
+* address: Address of the ISR to set in the interrupt vector table.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_ATN_ISR_SetVector(cyisraddress address)\r
+{\r
+ cyisraddress * ramVectorTable;\r
+\r
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;\r
+\r
+ ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_ATN_ISR__INTC_NUMBER] = address;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_ATN_ISR_GetVector\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the "address" of the current ISR vector for the Interrupt.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* Address of the ISR in the interrupt vector table.\r
+*\r
+*******************************************************************************/\r
+cyisraddress SCSI_ATN_ISR_GetVector(void)\r
+{\r
+ cyisraddress * ramVectorTable;\r
+\r
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;\r
+\r
+ return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_ATN_ISR__INTC_NUMBER];\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_ATN_ISR_SetPriority\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the Priority of the Interrupt. Note calling SCSI_ATN_ISR_Start\r
+* or SCSI_ATN_ISR_StartEx will override any effect this method \r
+* would have had. This method should only be called after \r
+* SCSI_ATN_ISR_Start or SCSI_ATN_ISR_StartEx has been called. To set \r
+* the initial priority for the component use the cydwr file in the tool.\r
+*\r
+* Parameters:\r
+* priority: Priority of the interrupt. 0 - 7, 0 being the highest.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_ATN_ISR_SetPriority(uint8 priority)\r
+{\r
+ *SCSI_ATN_ISR_INTC_PRIOR = priority << 5;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_ATN_ISR_GetPriority\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the Priority of the Interrupt.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* Priority of the interrupt. 0 - 7, 0 being the highest.\r
+*\r
+*******************************************************************************/\r
+uint8 SCSI_ATN_ISR_GetPriority(void)\r
+{\r
+ uint8 priority;\r
+\r
+\r
+ priority = *SCSI_ATN_ISR_INTC_PRIOR >> 5;\r
+\r
+ return priority;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_ATN_ISR_Enable\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables the interrupt.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_ATN_ISR_Enable(void)\r
+{\r
+ /* Enable the general interrupt. */\r
+ *SCSI_ATN_ISR_INTC_SET_EN = SCSI_ATN_ISR__INTC_MASK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_ATN_ISR_GetState\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the state (enabled, disabled) of the Interrupt.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* 1 if enabled, 0 if disabled.\r
+*\r
+*******************************************************************************/\r
+uint8 SCSI_ATN_ISR_GetState(void)\r
+{\r
+ /* Get the state of the general interrupt. */\r
+ return ((*SCSI_ATN_ISR_INTC_SET_EN & (uint32)SCSI_ATN_ISR__INTC_MASK) != 0u) ? 1u:0u;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_ATN_ISR_Disable\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables the Interrupt.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_ATN_ISR_Disable(void)\r
+{\r
+ /* Disable the general interrupt. */\r
+ *SCSI_ATN_ISR_INTC_CLR_EN = SCSI_ATN_ISR__INTC_MASK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_ATN_ISR_SetPending\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Causes the Interrupt to enter the pending state, a software method of\r
+* generating the interrupt.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_ATN_ISR_SetPending(void)\r
+{\r
+ *SCSI_ATN_ISR_INTC_SET_PD = SCSI_ATN_ISR__INTC_MASK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_ATN_ISR_ClearPending\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Clears a pending interrupt.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_ATN_ISR_ClearPending(void)\r
+{\r
+ *SCSI_ATN_ISR_INTC_CLR_PD = SCSI_ATN_ISR__INTC_MASK;\r
+}\r
+\r
+#endif /* End check for removal by optimization */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_ATN_ISR.h\r
+* Version 1.70\r
+*\r
+* Description:\r
+* Provides the function definitions for the Interrupt Controller.\r
+*\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+#if !defined(CY_ISR_SCSI_ATN_ISR_H)\r
+#define CY_ISR_SCSI_ATN_ISR_H\r
+\r
+\r
+#include <cytypes.h>\r
+#include <cyfitter.h>\r
+\r
+/* Interrupt Controller API. */\r
+void SCSI_ATN_ISR_Start(void);\r
+void SCSI_ATN_ISR_StartEx(cyisraddress address);\r
+void SCSI_ATN_ISR_Stop(void);\r
+\r
+CY_ISR_PROTO(SCSI_ATN_ISR_Interrupt);\r
+\r
+void SCSI_ATN_ISR_SetVector(cyisraddress address);\r
+cyisraddress SCSI_ATN_ISR_GetVector(void);\r
+\r
+void SCSI_ATN_ISR_SetPriority(uint8 priority);\r
+uint8 SCSI_ATN_ISR_GetPriority(void);\r
+\r
+void SCSI_ATN_ISR_Enable(void);\r
+uint8 SCSI_ATN_ISR_GetState(void);\r
+void SCSI_ATN_ISR_Disable(void);\r
+\r
+void SCSI_ATN_ISR_SetPending(void);\r
+void SCSI_ATN_ISR_ClearPending(void);\r
+\r
+\r
+/* Interrupt Controller Constants */\r
+\r
+/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_ATN_ISR ISR. */\r
+#define SCSI_ATN_ISR_INTC_VECTOR ((reg32 *) SCSI_ATN_ISR__INTC_VECT)\r
+\r
+/* Address of the SCSI_ATN_ISR ISR priority. */\r
+#define SCSI_ATN_ISR_INTC_PRIOR ((reg8 *) SCSI_ATN_ISR__INTC_PRIOR_REG)\r
+\r
+/* Priority of the SCSI_ATN_ISR interrupt. */\r
+#define SCSI_ATN_ISR_INTC_PRIOR_NUMBER SCSI_ATN_ISR__INTC_PRIOR_NUM\r
+\r
+/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_ATN_ISR interrupt. */\r
+#define SCSI_ATN_ISR_INTC_SET_EN ((reg32 *) SCSI_ATN_ISR__INTC_SET_EN_REG)\r
+\r
+/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_ATN_ISR interrupt. */\r
+#define SCSI_ATN_ISR_INTC_CLR_EN ((reg32 *) SCSI_ATN_ISR__INTC_CLR_EN_REG)\r
+\r
+/* Address of the INTC.SET_PD[x] register to set the SCSI_ATN_ISR interrupt state to pending. */\r
+#define SCSI_ATN_ISR_INTC_SET_PD ((reg32 *) SCSI_ATN_ISR__INTC_SET_PD_REG)\r
+\r
+/* Address of the INTC.CLR_PD[x] register to clear the SCSI_ATN_ISR interrupt. */\r
+#define SCSI_ATN_ISR_INTC_CLR_PD ((reg32 *) SCSI_ATN_ISR__INTC_CLR_PD_REG)\r
+\r
+\r
+#endif /* CY_ISR_SCSI_ATN_ISR_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_ATN.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SCSI_ATN_ALIASES_H) /* Pins SCSI_ATN_ALIASES_H */\r
+#define CY_PINS_SCSI_ATN_ALIASES_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Constants \r
+***************************************/\r
+#define SCSI_ATN_0 SCSI_ATN__0__PC\r
+\r
+#define SCSI_ATN_INT SCSI_ATN__INT__PC\r
+\r
+#endif /* End Pins SCSI_ATN_ALIASES_H */\r
+\r
+/* [] END OF FILE */\r
#define SCSI_In_DBx_6 SCSI_In_DBx__6__PC\r
#define SCSI_In_DBx_7 SCSI_In_DBx__7__PC\r
\r
-#define SCSI_In_DBx_SCSI_Out_DB0 SCSI_In_DBx__SCSI_Out_DB0__PC\r
-#define SCSI_In_DBx_SCSI_Out_DB1 SCSI_In_DBx__SCSI_Out_DB1__PC\r
-#define SCSI_In_DBx_SCSI_Out_DB2 SCSI_In_DBx__SCSI_Out_DB2__PC\r
-#define SCSI_In_DBx_SCSI_Out_DB3 SCSI_In_DBx__SCSI_Out_DB3__PC\r
-#define SCSI_In_DBx_SCSI_Out_DB4 SCSI_In_DBx__SCSI_Out_DB4__PC\r
-#define SCSI_In_DBx_SCSI_Out_DB5 SCSI_In_DBx__SCSI_Out_DB5__PC\r
-#define SCSI_In_DBx_SCSI_Out_DB6 SCSI_In_DBx__SCSI_Out_DB6__PC\r
-#define SCSI_In_DBx_SCSI_Out_DB7 SCSI_In_DBx__SCSI_Out_DB7__PC\r
+#define SCSI_In_DBx_DB0 SCSI_In_DBx__DB0__PC\r
+#define SCSI_In_DBx_DB1 SCSI_In_DBx__DB1__PC\r
+#define SCSI_In_DBx_DB2 SCSI_In_DBx__DB2__PC\r
+#define SCSI_In_DBx_DB3 SCSI_In_DBx__DB3__PC\r
+#define SCSI_In_DBx_DB4 SCSI_In_DBx__DB4__PC\r
+#define SCSI_In_DBx_DB5 SCSI_In_DBx__DB5__PC\r
+#define SCSI_In_DBx_DB6 SCSI_In_DBx__DB6__PC\r
+#define SCSI_In_DBx_DB7 SCSI_In_DBx__DB7__PC\r
\r
#endif /* End Pins SCSI_In_DBx_ALIASES_H */\r
\r
#define SCSI_In_5 SCSI_In__5__PC\r
#define SCSI_In_6 SCSI_In__6__PC\r
#define SCSI_In_7 SCSI_In__7__PC\r
-#define SCSI_In_8 SCSI_In__8__PC\r
-#define SCSI_In_9 SCSI_In__9__PC\r
\r
#define SCSI_In_DBP SCSI_In__DBP__PC\r
-#define SCSI_In_ATN SCSI_In__ATN__PC\r
#define SCSI_In_BSY SCSI_In__BSY__PC\r
#define SCSI_In_ACK SCSI_In__ACK__PC\r
-#define SCSI_In_RST SCSI_In__RST__PC\r
#define SCSI_In_MSG SCSI_In__MSG__PC\r
#define SCSI_In_SEL SCSI_In__SEL__PC\r
#define SCSI_In_CD SCSI_In__CD__PC\r
#define SCSI_Out_DBx_6 SCSI_Out_DBx__6__PC\r
#define SCSI_Out_DBx_7 SCSI_Out_DBx__7__PC\r
\r
-#define SCSI_Out_DBx_SCSI_Out_DB0 SCSI_Out_DBx__SCSI_Out_DB0__PC\r
-#define SCSI_Out_DBx_SCSI_Out_DB1 SCSI_Out_DBx__SCSI_Out_DB1__PC\r
-#define SCSI_Out_DBx_SCSI_Out_DB2 SCSI_Out_DBx__SCSI_Out_DB2__PC\r
-#define SCSI_Out_DBx_SCSI_Out_DB3 SCSI_Out_DBx__SCSI_Out_DB3__PC\r
-#define SCSI_Out_DBx_SCSI_Out_DB4 SCSI_Out_DBx__SCSI_Out_DB4__PC\r
-#define SCSI_Out_DBx_SCSI_Out_DB5 SCSI_Out_DBx__SCSI_Out_DB5__PC\r
-#define SCSI_Out_DBx_SCSI_Out_DB6 SCSI_Out_DBx__SCSI_Out_DB6__PC\r
-#define SCSI_Out_DBx_SCSI_Out_DB7 SCSI_Out_DBx__SCSI_Out_DB7__PC\r
+#define SCSI_Out_DBx_DB0 SCSI_Out_DBx__DB0__PC\r
+#define SCSI_Out_DBx_DB1 SCSI_Out_DBx__DB1__PC\r
+#define SCSI_Out_DBx_DB2 SCSI_Out_DBx__DB2__PC\r
+#define SCSI_Out_DBx_DB3 SCSI_Out_DBx__DB3__PC\r
+#define SCSI_Out_DBx_DB4 SCSI_Out_DBx__DB4__PC\r
+#define SCSI_Out_DBx_DB5 SCSI_Out_DBx__DB5__PC\r
+#define SCSI_Out_DBx_DB6 SCSI_Out_DBx__DB6__PC\r
+#define SCSI_Out_DBx_DB7 SCSI_Out_DBx__DB7__PC\r
\r
#endif /* End Pins SCSI_Out_DBx_ALIASES_H */\r
\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_RST.c \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file contains API to enable firmware control of a Pins component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "cytypes.h"\r
+#include "SCSI_RST.h"\r
+\r
+/* APIs are not generated for P15[7:6] on PSoC 5 */\r
+#if !(CY_PSOC5A &&\\r
+ SCSI_RST__PORT == 15 && ((SCSI_RST__MASK & 0xC0) != 0))\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_RST_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Assign a new value to the digital port's data output register. \r
+*\r
+* Parameters: \r
+* prtValue: The value to be assigned to the Digital Port. \r
+*\r
+* Return: \r
+* None\r
+* \r
+*******************************************************************************/\r
+void SCSI_RST_Write(uint8 value) \r
+{\r
+ uint8 staticBits = (SCSI_RST_DR & (uint8)(~SCSI_RST_MASK));\r
+ SCSI_RST_DR = staticBits | ((uint8)(value << SCSI_RST_SHIFT) & SCSI_RST_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_RST_SetDriveMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Change the drive mode on the pins of the port.\r
+* \r
+* Parameters: \r
+* mode: Change the pins to this drive mode.\r
+*\r
+* Return: \r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_RST_SetDriveMode(uint8 mode) \r
+{\r
+ CyPins_SetPinDriveMode(SCSI_RST_0, mode);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_RST_Read\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value on the pins of the Digital Port in right justified \r
+* form.\r
+*\r
+* Parameters: \r
+* None\r
+*\r
+* Return: \r
+* Returns the current value of the Digital Port as a right justified number\r
+* \r
+* Note:\r
+* Macro SCSI_RST_ReadPS calls this function. \r
+* \r
+*******************************************************************************/\r
+uint8 SCSI_RST_Read(void) \r
+{\r
+ return (SCSI_RST_PS & SCSI_RST_MASK) >> SCSI_RST_SHIFT;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_RST_ReadDataReg\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value assigned to a Digital Port's data output register\r
+*\r
+* Parameters: \r
+* None \r
+*\r
+* Return: \r
+* Returns the current value assigned to the Digital Port's data output register\r
+* \r
+*******************************************************************************/\r
+uint8 SCSI_RST_ReadDataReg(void) \r
+{\r
+ return (SCSI_RST_DR & SCSI_RST_MASK) >> SCSI_RST_SHIFT;\r
+}\r
+\r
+\r
+/* If Interrupts Are Enabled for this Pins component */ \r
+#if defined(SCSI_RST_INTSTAT) \r
+\r
+ /*******************************************************************************\r
+ * Function Name: SCSI_RST_ClearInterrupt\r
+ ********************************************************************************\r
+ * Summary:\r
+ * Clears any active interrupts attached to port and returns the value of the \r
+ * interrupt status register.\r
+ *\r
+ * Parameters: \r
+ * None \r
+ *\r
+ * Return: \r
+ * Returns the value of the interrupt status register\r
+ * \r
+ *******************************************************************************/\r
+ uint8 SCSI_RST_ClearInterrupt(void) \r
+ {\r
+ return (SCSI_RST_INTSTAT & SCSI_RST_MASK) >> SCSI_RST_SHIFT;\r
+ }\r
+\r
+#endif /* If Interrupts Are Enabled for this Pins component */ \r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+ \r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_RST.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SCSI_RST_H) /* Pins SCSI_RST_H */\r
+#define CY_PINS_SCSI_RST_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "cypins.h"\r
+#include "SCSI_RST_aliases.h"\r
+\r
+/* Check to see if required defines such as CY_PSOC5A are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5A)\r
+ #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* APIs are not generated for P15[7:6] */\r
+#if !(CY_PSOC5A &&\\r
+ SCSI_RST__PORT == 15 && ((SCSI_RST__MASK & 0xC0) != 0))\r
+\r
+\r
+/***************************************\r
+* Function Prototypes \r
+***************************************/ \r
+\r
+void SCSI_RST_Write(uint8 value) ;\r
+void SCSI_RST_SetDriveMode(uint8 mode) ;\r
+uint8 SCSI_RST_ReadDataReg(void) ;\r
+uint8 SCSI_RST_Read(void) ;\r
+uint8 SCSI_RST_ClearInterrupt(void) ;\r
+\r
+\r
+/***************************************\r
+* API Constants \r
+***************************************/\r
+\r
+/* Drive Modes */\r
+#define SCSI_RST_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+#define SCSI_RST_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+#define SCSI_RST_DM_RES_UP PIN_DM_RES_UP\r
+#define SCSI_RST_DM_RES_DWN PIN_DM_RES_DWN\r
+#define SCSI_RST_DM_OD_LO PIN_DM_OD_LO\r
+#define SCSI_RST_DM_OD_HI PIN_DM_OD_HI\r
+#define SCSI_RST_DM_STRONG PIN_DM_STRONG\r
+#define SCSI_RST_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+\r
+/* Digital Port Constants */\r
+#define SCSI_RST_MASK SCSI_RST__MASK\r
+#define SCSI_RST_SHIFT SCSI_RST__SHIFT\r
+#define SCSI_RST_WIDTH 1u\r
+\r
+\r
+/***************************************\r
+* Registers \r
+***************************************/\r
+\r
+/* Main Port Registers */\r
+/* Pin State */\r
+#define SCSI_RST_PS (* (reg8 *) SCSI_RST__PS)\r
+/* Data Register */\r
+#define SCSI_RST_DR (* (reg8 *) SCSI_RST__DR)\r
+/* Port Number */\r
+#define SCSI_RST_PRT_NUM (* (reg8 *) SCSI_RST__PRT) \r
+/* Connect to Analog Globals */ \r
+#define SCSI_RST_AG (* (reg8 *) SCSI_RST__AG) \r
+/* Analog MUX bux enable */\r
+#define SCSI_RST_AMUX (* (reg8 *) SCSI_RST__AMUX) \r
+/* Bidirectional Enable */ \r
+#define SCSI_RST_BIE (* (reg8 *) SCSI_RST__BIE)\r
+/* Bit-mask for Aliased Register Access */\r
+#define SCSI_RST_BIT_MASK (* (reg8 *) SCSI_RST__BIT_MASK)\r
+/* Bypass Enable */\r
+#define SCSI_RST_BYP (* (reg8 *) SCSI_RST__BYP)\r
+/* Port wide control signals */ \r
+#define SCSI_RST_CTL (* (reg8 *) SCSI_RST__CTL)\r
+/* Drive Modes */\r
+#define SCSI_RST_DM0 (* (reg8 *) SCSI_RST__DM0) \r
+#define SCSI_RST_DM1 (* (reg8 *) SCSI_RST__DM1)\r
+#define SCSI_RST_DM2 (* (reg8 *) SCSI_RST__DM2) \r
+/* Input Buffer Disable Override */\r
+#define SCSI_RST_INP_DIS (* (reg8 *) SCSI_RST__INP_DIS)\r
+/* LCD Common or Segment Drive */\r
+#define SCSI_RST_LCD_COM_SEG (* (reg8 *) SCSI_RST__LCD_COM_SEG)\r
+/* Enable Segment LCD */\r
+#define SCSI_RST_LCD_EN (* (reg8 *) SCSI_RST__LCD_EN)\r
+/* Slew Rate Control */\r
+#define SCSI_RST_SLW (* (reg8 *) SCSI_RST__SLW)\r
+\r
+/* DSI Port Registers */\r
+/* Global DSI Select Register */\r
+#define SCSI_RST_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_RST__PRTDSI__CAPS_SEL) \r
+/* Double Sync Enable */\r
+#define SCSI_RST_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_RST__PRTDSI__DBL_SYNC_IN) \r
+/* Output Enable Select Drive Strength */\r
+#define SCSI_RST_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_RST__PRTDSI__OE_SEL0) \r
+#define SCSI_RST_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_RST__PRTDSI__OE_SEL1) \r
+/* Port Pin Output Select Registers */\r
+#define SCSI_RST_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_RST__PRTDSI__OUT_SEL0) \r
+#define SCSI_RST_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_RST__PRTDSI__OUT_SEL1) \r
+/* Sync Output Enable Registers */\r
+#define SCSI_RST_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_RST__PRTDSI__SYNC_OUT) \r
+\r
+\r
+#if defined(SCSI_RST__INTSTAT) /* Interrupt Registers */\r
+\r
+ #define SCSI_RST_INTSTAT (* (reg8 *) SCSI_RST__INTSTAT)\r
+ #define SCSI_RST_SNAP (* (reg8 *) SCSI_RST__SNAP)\r
+\r
+#endif /* Interrupt Registers */\r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+#endif /* CY_PINS_SCSI_RST_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_RST_ISR.c \r
+* Version 1.70\r
+*\r
+* Description:\r
+* API for controlling the state of an interrupt.\r
+*\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+\r
+#include <cydevice_trm.h>\r
+#include <CyLib.h>\r
+#include <SCSI_RST_ISR.h>\r
+\r
+#if !defined(SCSI_RST_ISR__REMOVED) /* Check for removal by optimization */\r
+\r
+/*******************************************************************************\r
+* Place your includes, defines and code here \r
+********************************************************************************/\r
+/* `#START SCSI_RST_ISR_intc` */\r
+\r
+/* `#END` */\r
+\r
+#ifndef CYINT_IRQ_BASE\r
+#define CYINT_IRQ_BASE 16\r
+#endif /* CYINT_IRQ_BASE */\r
+#ifndef CYINT_VECT_TABLE\r
+#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)\r
+#endif /* CYINT_VECT_TABLE */\r
+\r
+/* Declared in startup, used to set unused interrupts to. */\r
+CY_ISR_PROTO(IntDefaultHandler);\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_RST_ISR_Start\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Set up the interrupt and enable it.\r
+*\r
+* Parameters: \r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_RST_ISR_Start(void)\r
+{\r
+ /* For all we know the interrupt is active. */\r
+ SCSI_RST_ISR_Disable();\r
+\r
+ /* Set the ISR to point to the SCSI_RST_ISR Interrupt. */\r
+ SCSI_RST_ISR_SetVector(&SCSI_RST_ISR_Interrupt);\r
+\r
+ /* Set the priority. */\r
+ SCSI_RST_ISR_SetPriority((uint8)SCSI_RST_ISR_INTC_PRIOR_NUMBER);\r
+\r
+ /* Enable it. */\r
+ SCSI_RST_ISR_Enable();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_RST_ISR_StartEx\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Set up the interrupt and enable it.\r
+*\r
+* Parameters: \r
+* address: Address of the ISR to set in the interrupt vector table.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_RST_ISR_StartEx(cyisraddress address)\r
+{\r
+ /* For all we know the interrupt is active. */\r
+ SCSI_RST_ISR_Disable();\r
+\r
+ /* Set the ISR to point to the SCSI_RST_ISR Interrupt. */\r
+ SCSI_RST_ISR_SetVector(address);\r
+\r
+ /* Set the priority. */\r
+ SCSI_RST_ISR_SetPriority((uint8)SCSI_RST_ISR_INTC_PRIOR_NUMBER);\r
+\r
+ /* Enable it. */\r
+ SCSI_RST_ISR_Enable();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_RST_ISR_Stop\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables and removes the interrupt.\r
+*\r
+* Parameters: \r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_RST_ISR_Stop(void)\r
+{\r
+ /* Disable this interrupt. */\r
+ SCSI_RST_ISR_Disable();\r
+\r
+ /* Set the ISR to point to the passive one. */\r
+ SCSI_RST_ISR_SetVector(&IntDefaultHandler);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_RST_ISR_Interrupt\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* The default Interrupt Service Routine for SCSI_RST_ISR.\r
+*\r
+* Add custom code between the coments to keep the next version of this file\r
+* from over writting your code.\r
+*\r
+* Parameters: \r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+CY_ISR(SCSI_RST_ISR_Interrupt)\r
+{\r
+ /* Place your Interrupt code here. */\r
+ /* `#START SCSI_RST_ISR_Interrupt` */\r
+\r
+ /* `#END` */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_RST_ISR_SetVector\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Change the ISR vector for the Interrupt. Note calling SCSI_RST_ISR_Start\r
+* will override any effect this method would have had. To set the vector \r
+* before the component has been started use SCSI_RST_ISR_StartEx instead.\r
+*\r
+* Parameters:\r
+* address: Address of the ISR to set in the interrupt vector table.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_RST_ISR_SetVector(cyisraddress address)\r
+{\r
+ cyisraddress * ramVectorTable;\r
+\r
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;\r
+\r
+ ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RST_ISR__INTC_NUMBER] = address;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_RST_ISR_GetVector\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the "address" of the current ISR vector for the Interrupt.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* Address of the ISR in the interrupt vector table.\r
+*\r
+*******************************************************************************/\r
+cyisraddress SCSI_RST_ISR_GetVector(void)\r
+{\r
+ cyisraddress * ramVectorTable;\r
+\r
+ ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;\r
+\r
+ return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RST_ISR__INTC_NUMBER];\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_RST_ISR_SetPriority\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the Priority of the Interrupt. Note calling SCSI_RST_ISR_Start\r
+* or SCSI_RST_ISR_StartEx will override any effect this method \r
+* would have had. This method should only be called after \r
+* SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called. To set \r
+* the initial priority for the component use the cydwr file in the tool.\r
+*\r
+* Parameters:\r
+* priority: Priority of the interrupt. 0 - 7, 0 being the highest.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_RST_ISR_SetPriority(uint8 priority)\r
+{\r
+ *SCSI_RST_ISR_INTC_PRIOR = priority << 5;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_RST_ISR_GetPriority\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the Priority of the Interrupt.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* Priority of the interrupt. 0 - 7, 0 being the highest.\r
+*\r
+*******************************************************************************/\r
+uint8 SCSI_RST_ISR_GetPriority(void)\r
+{\r
+ uint8 priority;\r
+\r
+\r
+ priority = *SCSI_RST_ISR_INTC_PRIOR >> 5;\r
+\r
+ return priority;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_RST_ISR_Enable\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables the interrupt.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_RST_ISR_Enable(void)\r
+{\r
+ /* Enable the general interrupt. */\r
+ *SCSI_RST_ISR_INTC_SET_EN = SCSI_RST_ISR__INTC_MASK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_RST_ISR_GetState\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the state (enabled, disabled) of the Interrupt.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* 1 if enabled, 0 if disabled.\r
+*\r
+*******************************************************************************/\r
+uint8 SCSI_RST_ISR_GetState(void)\r
+{\r
+ /* Get the state of the general interrupt. */\r
+ return ((*SCSI_RST_ISR_INTC_SET_EN & (uint32)SCSI_RST_ISR__INTC_MASK) != 0u) ? 1u:0u;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_RST_ISR_Disable\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables the Interrupt.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_RST_ISR_Disable(void)\r
+{\r
+ /* Disable the general interrupt. */\r
+ *SCSI_RST_ISR_INTC_CLR_EN = SCSI_RST_ISR__INTC_MASK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_RST_ISR_SetPending\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Causes the Interrupt to enter the pending state, a software method of\r
+* generating the interrupt.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_RST_ISR_SetPending(void)\r
+{\r
+ *SCSI_RST_ISR_INTC_SET_PD = SCSI_RST_ISR__INTC_MASK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_RST_ISR_ClearPending\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Clears a pending interrupt.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_RST_ISR_ClearPending(void)\r
+{\r
+ *SCSI_RST_ISR_INTC_CLR_PD = SCSI_RST_ISR__INTC_MASK;\r
+}\r
+\r
+#endif /* End check for removal by optimization */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_RST_ISR.h\r
+* Version 1.70\r
+*\r
+* Description:\r
+* Provides the function definitions for the Interrupt Controller.\r
+*\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+#if !defined(CY_ISR_SCSI_RST_ISR_H)\r
+#define CY_ISR_SCSI_RST_ISR_H\r
+\r
+\r
+#include <cytypes.h>\r
+#include <cyfitter.h>\r
+\r
+/* Interrupt Controller API. */\r
+void SCSI_RST_ISR_Start(void);\r
+void SCSI_RST_ISR_StartEx(cyisraddress address);\r
+void SCSI_RST_ISR_Stop(void);\r
+\r
+CY_ISR_PROTO(SCSI_RST_ISR_Interrupt);\r
+\r
+void SCSI_RST_ISR_SetVector(cyisraddress address);\r
+cyisraddress SCSI_RST_ISR_GetVector(void);\r
+\r
+void SCSI_RST_ISR_SetPriority(uint8 priority);\r
+uint8 SCSI_RST_ISR_GetPriority(void);\r
+\r
+void SCSI_RST_ISR_Enable(void);\r
+uint8 SCSI_RST_ISR_GetState(void);\r
+void SCSI_RST_ISR_Disable(void);\r
+\r
+void SCSI_RST_ISR_SetPending(void);\r
+void SCSI_RST_ISR_ClearPending(void);\r
+\r
+\r
+/* Interrupt Controller Constants */\r
+\r
+/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_RST_ISR ISR. */\r
+#define SCSI_RST_ISR_INTC_VECTOR ((reg32 *) SCSI_RST_ISR__INTC_VECT)\r
+\r
+/* Address of the SCSI_RST_ISR ISR priority. */\r
+#define SCSI_RST_ISR_INTC_PRIOR ((reg8 *) SCSI_RST_ISR__INTC_PRIOR_REG)\r
+\r
+/* Priority of the SCSI_RST_ISR interrupt. */\r
+#define SCSI_RST_ISR_INTC_PRIOR_NUMBER SCSI_RST_ISR__INTC_PRIOR_NUM\r
+\r
+/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_RST_ISR interrupt. */\r
+#define SCSI_RST_ISR_INTC_SET_EN ((reg32 *) SCSI_RST_ISR__INTC_SET_EN_REG)\r
+\r
+/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_RST_ISR interrupt. */\r
+#define SCSI_RST_ISR_INTC_CLR_EN ((reg32 *) SCSI_RST_ISR__INTC_CLR_EN_REG)\r
+\r
+/* Address of the INTC.SET_PD[x] register to set the SCSI_RST_ISR interrupt state to pending. */\r
+#define SCSI_RST_ISR_INTC_SET_PD ((reg32 *) SCSI_RST_ISR__INTC_SET_PD_REG)\r
+\r
+/* Address of the INTC.CLR_PD[x] register to clear the SCSI_RST_ISR interrupt. */\r
+#define SCSI_RST_ISR_INTC_CLR_PD ((reg32 *) SCSI_RST_ISR__INTC_CLR_PD_REG)\r
+\r
+\r
+#endif /* CY_ISR_SCSI_RST_ISR_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_RST.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SCSI_RST_ALIASES_H) /* Pins SCSI_RST_ALIASES_H */\r
+#define CY_PINS_SCSI_RST_ALIASES_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Constants \r
+***************************************/\r
+#define SCSI_RST_0 SCSI_RST__0__PC\r
+\r
+#define SCSI_RST_INT SCSI_RST__INT__PC\r
+\r
+#endif /* End Pins SCSI_RST_ALIASES_H */\r
+\r
+/* [] END OF FILE */\r
/* Internal interrupt handling */\r
#define SDCard_TX_BUFFER_SIZE (4u)\r
#define SDCard_RX_BUFFER_SIZE (4u)\r
-#define SDCard_INTERNAL_TX_INT_ENABLED (1u)\r
-#define SDCard_INTERNAL_RX_INT_ENABLED (1u)\r
+#define SDCard_INTERNAL_TX_INT_ENABLED (0u)\r
+#define SDCard_INTERNAL_RX_INT_ENABLED (0u)\r
\r
#define SDCard_SINGLE_REG_SIZE (8u)\r
#define SDCard_USE_SECOND_DATAPATH (SDCard_DATA_WIDTH > SDCard_SINGLE_REG_SIZE)\r
/*******************************************************************************\r
* File Name: SD_Data_Clk.c\r
-* Version 2.0\r
+* Version 2.10\r
*\r
* Description:\r
* This file provides the source code to the API for the clock component.\r
/*******************************************************************************\r
* File Name: SD_Data_Clk.h\r
-* Version 2.0\r
+* Version 2.10\r
*\r
* Description:\r
* Provides the function and constant definitions for the clock component.\r
/* Check to see if required defines such as CY_PSOC5LP are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5LP)\r
- #error Component cy_clock_v2_0 requires cy_boot v3.0 or later\r
+ #error Component cy_clock_v2_10 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5LP) */\r
\r
\r
\r
#define SD_Data_Clk_Enable() SD_Data_Clk_Start()\r
#define SD_Data_Clk_Disable() SD_Data_Clk_Stop()\r
-#define SD_Data_Clk_SetDivider(clkDivider) SD_Data_Clk_SetDividerRegister(clkDivider, 1)\r
-#define SD_Data_Clk_SetDividerValue(clkDivider) SD_Data_Clk_SetDividerRegister((clkDivider) - 1, 1)\r
+#define SD_Data_Clk_SetDivider(clkDivider) SD_Data_Clk_SetDividerRegister(clkDivider, 1u)\r
+#define SD_Data_Clk_SetDividerValue(clkDivider) SD_Data_Clk_SetDividerRegister((clkDivider) - 1u, 1u)\r
#define SD_Data_Clk_SetMode(clkMode) SD_Data_Clk_SetModeRegister(clkMode)\r
#define SD_Data_Clk_SetSource(clkSource) SD_Data_Clk_SetSourceRegister(clkSource)\r
#if defined(SD_Data_Clk__CFG3)\r
#define SD_Data_Clk_SetPhase(clkPhase) SD_Data_Clk_SetPhaseRegister(clkPhase)\r
-#define SD_Data_Clk_SetPhaseValue(clkPhase) SD_Data_Clk_SetPhaseRegister((clkPhase) + 1)\r
+#define SD_Data_Clk_SetPhaseValue(clkPhase) SD_Data_Clk_SetPhaseRegister((clkPhase) + 1u)\r
#endif /* defined(SD_Data_Clk__CFG3) */\r
\r
\r
/*******************************************************************************\r
* File Name: SD_Init_Clk.c\r
-* Version 2.0\r
+* Version 2.10\r
*\r
* Description:\r
* This file provides the source code to the API for the clock component.\r
/*******************************************************************************\r
* File Name: SD_Init_Clk.h\r
-* Version 2.0\r
+* Version 2.10\r
*\r
* Description:\r
* Provides the function and constant definitions for the clock component.\r
/* Check to see if required defines such as CY_PSOC5LP are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5LP)\r
- #error Component cy_clock_v2_0 requires cy_boot v3.0 or later\r
+ #error Component cy_clock_v2_10 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5LP) */\r
\r
\r
\r
#define SD_Init_Clk_Enable() SD_Init_Clk_Start()\r
#define SD_Init_Clk_Disable() SD_Init_Clk_Stop()\r
-#define SD_Init_Clk_SetDivider(clkDivider) SD_Init_Clk_SetDividerRegister(clkDivider, 1)\r
-#define SD_Init_Clk_SetDividerValue(clkDivider) SD_Init_Clk_SetDividerRegister((clkDivider) - 1, 1)\r
+#define SD_Init_Clk_SetDivider(clkDivider) SD_Init_Clk_SetDividerRegister(clkDivider, 1u)\r
+#define SD_Init_Clk_SetDividerValue(clkDivider) SD_Init_Clk_SetDividerRegister((clkDivider) - 1u, 1u)\r
#define SD_Init_Clk_SetMode(clkMode) SD_Init_Clk_SetModeRegister(clkMode)\r
#define SD_Init_Clk_SetSource(clkSource) SD_Init_Clk_SetSourceRegister(clkSource)\r
#if defined(SD_Init_Clk__CFG3)\r
#define SD_Init_Clk_SetPhase(clkPhase) SD_Init_Clk_SetPhaseRegister(clkPhase)\r
-#define SD_Init_Clk_SetPhaseValue(clkPhase) SD_Init_Clk_SetPhaseRegister((clkPhase) + 1)\r
+#define SD_Init_Clk_SetPhaseValue(clkPhase) SD_Init_Clk_SetPhaseRegister((clkPhase) + 1u)\r
#endif /* defined(SD_Init_Clk__CFG3) */\r
\r
\r
* they apply.\r
*/\r
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")\r
-ENTRY(__cs3_reset)\r
+ENTRY(__cy_reset)\r
SEARCH_DIR(.)\r
-GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro)\r
+GROUP(-lgcc -lc -lnosys)\r
+\r
\r
MEMORY\r
{\r
- rom (rx) : ORIGIN = 0, LENGTH = (262144 - 0)\r
- ram (rwx) : ORIGIN = 0x20000000 - (65536 / 2), LENGTH = (65536 - 0x4000 - 0x1000)\r
+ rom (rx) : ORIGIN = 0x0, LENGTH = 262144\r
+ ram (rwx) : ORIGIN = 0x20000000 - (65536 / 2), LENGTH = 65536\r
}\r
\r
+\r
+CY_APPL_ORIGIN = 0; \r
+CY_FLASH_ROW_SIZE = 256;\r
+CY_ECC_ROW_SIZE = 32;\r
+CY_EE_IN_BTLDR = 0x0;\r
+CY_APPL_LOADABLE = 0;\r
+CY_EE_SIZE = 2048;\r
+CY_APPL_NUM = 1;\r
+CY_APPL_MAX = 1;\r
+CY_METADATA_SIZE = 64;\r
+\r
+\r
/* These force the linker to search for particular symbols from\r
* the start of the link process and thus ensure the user's\r
* overrides are picked up\r
*/\r
-EXTERN(__cs3_reset Reset)\r
-EXTERN(__cs3_start_asm __cs3_start_asm_generic_m)\r
+EXTERN(Reset)\r
+\r
/* Bring in the interrupt routines & vector */\r
-INCLUDE micro-names.inc\r
-EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)\r
+EXTERN(main)\r
+\r
+/* Bring in the meta data */\r
+EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader)\r
+EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata)\r
\r
/* Provide fall-back values */\r
-PROVIDE(__cs3_heap_start = _end);\r
-PROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) / 20);\r
-PROVIDE(__cs3_stack = 0x20000000 + (65536 / 2));\r
-PROVIDE(__cs3_heap_end = __cs3_stack - 0x4000);\r
+PROVIDE(__cy_heap_start = _end);\r
+PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16);\r
+PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram));\r
+PROVIDE(__cy_heap_end = __cy_stack - 0x4000);\r
\r
\r
SECTIONS\r
{\r
+ /* The bootloader location */\r
+ .cybootloader 0x0 : { KEEP(*(.cybootloader)) } >rom\r
\r
- .text :\r
+ /* Calculate where the loadables should start */\r
+ appl1_start = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : ALIGN(CY_FLASH_ROW_SIZE);\r
+ appl2_start = appl1_start + ALIGN((LENGTH(rom) - appl1_start - 2 * CY_FLASH_ROW_SIZE) / 2, CY_FLASH_ROW_SIZE);\r
+ appl_start = (CY_APPL_NUM == 1) ? appl1_start : appl2_start;\r
+ ecc_offset = (appl_start / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE;\r
+ ee_offset = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0;\r
+ ee_size = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE;\r
+ PROVIDE(CY_ECC_OFFSET = ecc_offset);\r
+ \r
+ .text appl_start :\r
{\r
CREATE_OBJECT_SYMBOLS\r
- PROVIDE(__cs3_interrupt_vector = RomVectors);\r
+ PROVIDE(__cy_interrupt_vector = RomVectors);\r
+\r
*(.romvectors)\r
- *(.cs3.interrupt_vector)\r
+\r
/* Make sure we pulled in an interrupt vector. */\r
- ASSERT (. != __cs3_interrupt_vector, "No interrupt vector");\r
+ ASSERT (. != __cy_interrupt_vector, "No interrupt vector");\r
+\r
+ ASSERT (CY_APPL_ORIGIN ? (SIZEOF(.cybootloader) <= CY_APPL_ORIGIN) : 1, "Wrong image location");\r
\r
- PROVIDE(__cs3_reset = Reset);\r
- *(.cs3.reset)\r
+ PROVIDE(__cy_reset = Reset);\r
+ *(.text.Reset)\r
/* Make sure we pulled in some reset code. */\r
- ASSERT (. != __cs3_reset, "No reset code");\r
+ ASSERT (. != __cy_reset, "No reset code");\r
\r
/* Place the DMA initialization before text to ensure it gets placed in first 64K of flash */\r
*(.dma_init)\r
- ASSERT(0 + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");\r
+ ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");\r
\r
- *(.text.cs3.init)\r
*(.text .text.* .gnu.linkonce.t.*)\r
*(.plt)\r
*(.gnu.warning)\r
KEEP (*crtend.o(.dtors))\r
\r
. = ALIGN(4);\r
- __cs3_regions = .;\r
- LONG (0)\r
- LONG (__cs3_region_init_ram)\r
- LONG (__cs3_region_start_data)\r
- LONG (__cs3_region_init_size_ram)\r
- LONG (__cs3_region_zero_size_ram)\r
- __cs3_regions_end = .;\r
+ __cy_regions = .;\r
+ LONG (__cy_region_init_ram)\r
+ LONG (__cy_region_start_data)\r
+ LONG (__cy_region_init_size_ram)\r
+ LONG (__cy_region_zero_size_ram)\r
+ __cy_regions_end = .;\r
\r
. = ALIGN (8);\r
_etext = .;\r
\r
.ramvectors (NOLOAD) : ALIGN(8)\r
{\r
- __cs3_region_start_ram = .;\r
- *(.cs3.region-head.ram)\r
- ASSERT (. == __cs3_region_start_ram, ".cs3.region-head.ram not permitted");\r
+ __cy_region_start_ram = .;\r
KEEP(*(.ramvectors))\r
}\r
\r
\r
.data : ALIGN(8)\r
{\r
- __cs3_region_start_data = .;\r
+ __cy_region_start_data = .;\r
\r
KEEP(*(.jcr))\r
*(.got.plt) *(.got)\r
} >ram AT>rom\r
.bss : ALIGN(8)\r
{\r
+ PROVIDE(__bss_start__ = .);\r
*(.shbss)\r
*(.bss .bss.* .gnu.linkonce.b.*)\r
*(COMMON)\r
_end = .;\r
__end = .;\r
} >ram AT>rom\r
+ PROVIDE(end = .);\r
+ PROVIDE(__bss_end__ = .);\r
+ \r
+ __cy_region_init_ram = LOADADDR (.data);\r
+ __cy_region_init_size_ram = _edata - ADDR (.data);\r
+ __cy_region_zero_size_ram = _end - _edata;\r
+ \r
+ /* The .stack and .heap sections don't contain any symbols. \r
+ * They are only used for linker to calculate RAM utilization.\r
+ */\r
+ .heap (NOLOAD) :\r
+ {\r
+ . = _end;\r
+ . += 0x1000;\r
+ __cy_heap_limit = .;\r
+ } >ram\r
+\r
+ .stack (__cy_stack - 0x4000) (NOLOAD) :\r
+ {\r
+ __cy_stack_limit = .;\r
+ . += 0x4000;\r
+ } >ram\r
\r
- __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);\r
- __cs3_region_size_ram = LENGTH(ram);\r
- __cs3_region_init_ram = LOADADDR (.data);\r
- __cs3_region_init_size_ram = _edata - ADDR (.data);\r
- __cs3_region_zero_size_ram = _end - _edata;\r
+ /* Check if data + heap + stack exceeds RAM limit */\r
+ ASSERT(__cy_stack_limit >= __cy_heap_limit, "region RAM overflowed with stack")\r
+\r
+ .cyloadermeta ((appl_start == 0) ? (LENGTH(rom) - CY_METADATA_SIZE) : 0xF0000000) :\r
+ {\r
+ KEEP(*(.cyloadermeta))\r
+ } :NONE\r
+\r
+ .cyloadablemeta (LENGTH(rom) - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) :\r
+ {\r
+ KEEP(*(.cyloadablemeta))\r
+ } >rom\r
+\r
+ .cyconfigecc (0x80000000 + ecc_offset) : \r
+ {\r
+ KEEP(*(.cyconfigecc))\r
+ } :NONE \r
+\r
+ .cycustnvl 0x90000000 : { KEEP(*(.cycustnvl)) } :NONE \r
+ .cywolatch 0x90100000 : { KEEP(*(.cywolatch)) } :NONE \r
+\r
+ .cyeeprom (0x90200000 + ee_offset) : \r
+ {\r
+ KEEP(*(.cyeeprom))\r
+ ASSERT(. <= (0x90200000 + ee_offset + ee_size), ".cyeeprom data will not fit in EEPROM");\r
+ } :NONE \r
\r
+ .cyflashprotect 0x90400000 : { KEEP(*(.cyflashprotect)) } :NONE \r
+ .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE \r
\r
.stab 0 (NOLOAD) : { *(.stab) }\r
.stabstr 0 (NOLOAD) : { *(.stabstr) }\r
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+:200280001D841E4A1F102101254027082911320A351036023B203D883E20462047086405E1\r
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+:200360003FFFFFFF2200F0080400000000000224040B0B0B909900010000C000400110118C\r
+:20038000C0010011400140010000000000000000000000000000000000FFFF00000000000B\r
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+:2003C0000E000C000000000000FCFC0000000000F0000FF00000000000010000F00F0F000D\r
+:2003E0000000000100000000000000000000000000000000000000000000000000000000FC\r
:00000001FF\r
/**************************************************************************//**\r
* @file core_cm3.h\r
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
- * @version V1.30\r
- * @date 30. October 2009\r
+ * @version V3.20\r
+ * @date 25. February 2013\r
*\r
* @note\r
- * Copyright (C) 2009 ARM Limited. All rights reserved.\r
- *\r
- * @par\r
- * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
- * processor based microcontrollers. This file can be freely distributed \r
- * within development tools that are supporting such ARM based processors. \r
- *\r
- * @par\r
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
*\r
******************************************************************************/\r
+/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#endif\r
\r
-#ifndef __CM3_CORE_H__\r
-#define __CM3_CORE_H__\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
\r
-/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration\r
- *\r
- * List of Lint messages which will be suppressed and not shown:\r
- * - Error 10: \n\r
- * register uint32_t __regBasePri __asm("basepri"); \n\r
- * Error 10: Expecting ';'\r
- * .\r
- * - Error 530: \n\r
- * return(__regBasePri); \n\r
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized\r
- * . \r
- * - Error 550: \n\r
- * __regBasePri = (basePri & 0x1ff); \n\r
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed\r
- * .\r
- * - Error 754: \n\r
- * uint32_t RESERVED0[24]; \n\r
- * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced\r
- * .\r
- * - Error 750: \n\r
- * #define __CM3_CORE_H__ \n\r
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced\r
- * .\r
- * - Error 528: \n\r
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced\r
- * .\r
- * - Error 751: \n\r
- * } InterruptType_Type; \n\r
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced\r
- * .\r
- * Note: To re-enable a Message, insert a space before 'lint' *\r
- *\r
+#ifndef __CORE_CM3_H_GENERIC\r
+#define __CORE_CM3_H_GENERIC\r
+\r
+/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
*/\r
\r
-/*lint -save */\r
-/*lint -e10 */\r
-/*lint -e530 */\r
-/*lint -e550 */\r
-/*lint -e754 */\r
-/*lint -e750 */\r
-/*lint -e528 */\r
-/*lint -e751 */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions\r
- This file defines all structures and symbols for CMSIS core:\r
- - CMSIS version number\r
- - Cortex-M core registers and bitfields\r
- - Cortex-M core peripheral base address\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/** \ingroup Cortex_M3\r
@{\r
*/\r
\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif \r
+/* CMSIS CM3 definitions */\r
+#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \\r
+ __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x03) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
\r
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
-#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
\r
-#define __CORTEX_M (0x03) /*!< Cortex core */\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
\r
-#include <stdint.h> /* Include standard types */\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
\r
-#if defined (__ICCARM__)\r
- #include <intrinsics.h> /* IAR Intrinsics */\r
#endif\r
\r
+/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all\r
+*/\r
+#define __FPU_USED 0\r
+\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
\r
-#ifndef __NVIC_PRIO_BITS\r
- #define __NVIC_PRIO_BITS 3 /*!< standard definition for NVIC Priority Bits */\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI__VFP_SUPPORT____\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #endif\r
#endif\r
\r
+#include <stdint.h> /* standard types definitions */\r
+#include <core_cmInstr.h> /* Core Instruction Access */\r
+#include <core_cmFunc.h> /* Core Function Access */\r
+\r
+#endif /* __CORE_CM3_H_GENERIC */\r
\r
+#ifndef __CMSIS_GENERIC\r
\r
+#ifndef __CORE_CM3_H_DEPENDANT\r
+#define __CORE_CM3_H_DEPENDANT\r
\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM3_REV\r
+ #define __CM3_REV 0x0200\r
+ #warning "__CM3_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 4\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
/**\r
- * IO definitions\r
- *\r
- * define access restrictions to peripheral registers\r
- */\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
#ifdef __cplusplus\r
- #define __I volatile /*!< defines 'read only' permissions */\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
#else\r
- #define __I volatile const /*!< defines 'read only' permissions */\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
#endif\r
-#define __O volatile /*!< defines 'write only' permissions */\r
-#define __IO volatile /*!< defines 'read / write' permissions */\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/*@} end of group Cortex_M3 */\r
\r
\r
\r
/*******************************************************************************\r
* Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
******************************************************************************/\r
-/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register\r
- @{\r
+/** \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
*/\r
\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/** \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */\r
+#else\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+#endif\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+#if (__CORTEX_M != 0x04)\r
+ uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */\r
+#else\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+#endif\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+\r
+/** \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
\r
-/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC\r
- memory mapped structure for Nested Vectored Interrupt Controller (NVIC)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
@{\r
*/\r
+\r
+/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
typedef struct\r
{\r
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */\r
- uint32_t RESERVED0[24]; \r
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */\r
- uint32_t RSERVED1[24]; \r
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */\r
- uint32_t RESERVED2[24]; \r
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */\r
- uint32_t RESERVED3[24]; \r
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */\r
- uint32_t RESERVED4[56]; \r
- __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */\r
- uint32_t RESERVED5[644]; \r
- __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */\r
-} NVIC_Type; \r
-/*@}*/ /* end of group CMSIS_CM3_NVIC */\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB\r
- memory mapped structure for System Control Block (SCB)\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24];\r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24];\r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24];\r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24];\r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56];\r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644];\r
+ __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
@{\r
*/\r
+\r
+/** \brief Structure type to access the System Control Block (SCB).\r
+ */\r
typedef struct\r
{\r
- __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */\r
- __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */\r
- __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */\r
- __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */\r
- __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */\r
- __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */\r
- __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
- __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */\r
- __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */\r
- __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */\r
- __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */\r
- __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */\r
- __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */\r
- __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */\r
- __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */\r
- __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */\r
- __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */\r
- __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */\r
- __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */\r
-} SCB_Type; \r
+ __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[5];\r
+ __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+} SCB_Type;\r
\r
/* SCB CPUID Register Definitions */\r
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
\r
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
-#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
\r
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
-#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
\r
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
-#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
\r
/* SCB Interrupt Control State Register Definitions */\r
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
-#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
\r
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
-#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
\r
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
-#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
\r
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
-#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
\r
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
-#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
\r
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
-#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
\r
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
-#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
\r
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
\r
#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
-#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
\r
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
\r
-/* SCB Interrupt Control State Register Definitions */\r
+/* SCB Vector Table Offset Register Definitions */\r
+#if (__CM3_REV < 0x0201) /* core r2p1 */\r
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
-#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
\r
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#else\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+#endif\r
\r
/* SCB Application Interrupt and Reset Control Register Definitions */\r
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
\r
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
\r
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
-#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
\r
#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
-#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
\r
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
-#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
\r
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
\r
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
-#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
\r
/* SCB System Control Register Definitions */\r
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
-#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
\r
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
-#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
\r
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
-#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
\r
/* SCB Configuration Control Register Definitions */\r
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
-#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
\r
#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
-#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
\r
#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
-#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
\r
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
-#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
\r
#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
-#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
\r
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
-#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
\r
/* SCB System Handler Control and State Register Definitions */\r
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
-#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
\r
#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
-#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
\r
#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
-#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
\r
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
-#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
\r
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
\r
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
\r
#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
\r
#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
-#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
\r
#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
-#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
\r
#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
-#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
\r
#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
-#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
- \r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
-#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
\r
#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
-#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
\r
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
-#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
\r
/* SCB Configurable Fault Status Registers Definitions */\r
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
\r
#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
\r
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
\r
/* SCB Hard Fault Status Registers Definitions */\r
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
-#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
\r
#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
-#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
\r
#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
-#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
\r
/* SCB Debug Fault Status Register Definitions */\r
#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
-#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
\r
#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
-#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
\r
#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
-#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
\r
#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
-#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
\r
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
-#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_SCB */\r
+#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1];\r
+ __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1[1];\r
+#endif\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */\r
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */\r
\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */\r
\r
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
- memory mapped structure for SysTick\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
@{\r
*/\r
+\r
+/** \brief Structure type to access the System Timer (SysTick).\r
+ */\r
typedef struct\r
{\r
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */\r
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */\r
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */\r
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
} SysTick_Type;\r
\r
/* SysTick Control / Status Register Definitions */\r
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
\r
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
\r
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
\r
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
\r
/* SysTick Reload Register Definitions */\r
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
\r
/* SysTick Current Register Definitions */\r
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
\r
/* SysTick Calibration Register Definitions */\r
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
\r
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
\r
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_SysTick */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
\r
+/*@} end of group CMSIS_SysTick */\r
\r
-/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM\r
- memory mapped structure for Instrumentation Trace Macrocell (ITM)\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
@{\r
*/\r
+\r
+/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
typedef struct\r
{\r
- __O union \r
+ __O union\r
{\r
- __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */\r
- __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */\r
- __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */\r
- } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */\r
- uint32_t RESERVED0[864]; \r
- __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */\r
- uint32_t RESERVED1[15]; \r
- __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */\r
- uint32_t RESERVED2[15]; \r
- __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */\r
- uint32_t RESERVED3[29]; \r
- __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */\r
- __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */\r
- __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */\r
- uint32_t RESERVED4[43]; \r
- __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */\r
- __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */\r
- uint32_t RESERVED5[6]; \r
- __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */\r
- __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */\r
- __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */\r
- __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */\r
- __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */\r
- __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */\r
- __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */\r
- __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */\r
- __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */\r
- __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */\r
- __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */\r
- __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */\r
-} ITM_Type; \r
+ __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864];\r
+ __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15];\r
+ __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15];\r
+ __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29];\r
+ __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43];\r
+ __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6];\r
+ __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
\r
/* ITM Trace Privilege Register Definitions */\r
#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
-#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
\r
/* ITM Trace Control Register Definitions */\r
#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
-#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
\r
-#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */\r
-#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */\r
+#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
\r
#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
-#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
\r
#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
-#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
\r
#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
-#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
\r
#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
-#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
\r
#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
-#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
\r
#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
-#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
\r
/* ITM Integration Write Register Definitions */\r
#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
-#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
\r
/* ITM Integration Read Register Definitions */\r
#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
-#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
\r
/* ITM Integration Mode Control Register Definitions */\r
#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
-#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
\r
/* ITM Lock Status Register Definitions */\r
#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
-#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
\r
#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
-#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
\r
#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
-#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_ITM */\r
+#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
\r
+/*@}*/ /* end of group CMSIS_ITM */\r
\r
-/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type\r
- memory mapped structure for Interrupt Type\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
@{\r
*/\r
+\r
+/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
typedef struct\r
{\r
- uint32_t RESERVED0;\r
- __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */\r
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
- __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */\r
-#else\r
- uint32_t RESERVED1;\r
-#endif\r
-} InterruptType_Type;\r
+ __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1];\r
+ __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1];\r
+ __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1];\r
+ __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+} DWT_Type;\r
\r
-/* Interrupt Controller Type Register Definitions */\r
-#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */\r
-#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
\r
-/* Auxiliary Control Register Definitions */\r
-#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */\r
-#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */\r
+#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */\r
\r
-#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */\r
-#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */\r
\r
-#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */\r
-#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_InterruptType */\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */\r
\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
-/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU\r
- memory mapped structure for Memory Protection Unit (MPU)\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/** \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55];\r
+ __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131];\r
+ __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759];\r
+ __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1];\r
+ __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39];\r
+ __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8];\r
+ __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if (__MPU_PRESENT == 1)\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
@{\r
*/\r
+\r
+/** \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
typedef struct\r
{\r
- __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */\r
- __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */\r
- __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */\r
- __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */\r
- __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */\r
- __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */\r
- __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */\r
- __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */\r
- __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */\r
-} MPU_Type; \r
+ __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
\r
/* MPU Type Register */\r
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
-#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
\r
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
-#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
\r
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
-#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
\r
/* MPU Control Register */\r
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
-#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
\r
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
-#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
\r
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
-#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
\r
/* MPU Region Number Register */\r
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
-#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
\r
/* MPU Region Base Address Register */\r
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
\r
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
-#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
\r
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
-#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
\r
/* MPU Region Attribute and Size Register */\r
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */\r
-#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */\r
+#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
\r
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */\r
-#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
\r
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */\r
-#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
\r
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */\r
-#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
\r
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */\r
-#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
\r
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */\r
-#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
\r
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
-#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
\r
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
-#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
\r
-#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
-#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
\r
-/*@}*/ /* end of group CMSIS_CM3_MPU */\r
+/*@} end of group CMSIS_MPU */\r
#endif\r
\r
\r
-/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug\r
- memory mapped structure for Core Debug Register\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
@{\r
*/\r
+\r
+/** \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
typedef struct\r
{\r
- __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */\r
- __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */\r
- __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */\r
- __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
} CoreDebug_Type;\r
\r
/* Debug Halting Control and Status Register */\r
#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
\r
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
\r
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
\r
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
\r
#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
\r
#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
-#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
\r
#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
\r
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
\r
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
\r
#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
-#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
\r
#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
-#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
\r
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
\r
/* Debug Core Register Selector Register */\r
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
-#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
\r
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
\r
/* Debug Exception and Monitor Control Register */\r
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
-#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
\r
#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
-#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
\r
#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
-#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
\r
#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
-#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
\r
#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
-#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
\r
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
\r
#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
\r
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
\r
#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
\r
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
\r
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
\r
#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
\r
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
-/*@}*/ /* end of group CMSIS_CM3_CoreDebug */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
\r
\r
+/** \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
/* Memory mapping of Cortex-M3 Hardware */\r
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
-\r
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
-\r
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
#endif\r
\r
-/*@}*/ /* end of group CMSIS_CM3_core_register */\r
+/*@} */\r
+\r
\r
\r
/*******************************************************************************\r
* Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
******************************************************************************/\r
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
\r
-#if defined ( __CC_ARM )\r
- #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
\r
-#elif defined ( __ICCARM__ )\r
- #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
\r
-#elif defined ( __GNUC__ )\r
- #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
- #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+/* ########################## NVIC functions #################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
\r
-#elif defined ( __TASKING__ )\r
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+/** \brief Set Priority Grouping\r
\r
-#endif\r
+ The function sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */\r
\r
-/* ################### Compiler specific Intrinsics ########################### */\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
\r
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
-/* ARM armcc specific functions */\r
\r
-#define __enable_fault_irq __enable_fiq\r
-#define __disable_fault_irq __disable_fiq\r
+/** \brief Get Priority Grouping\r
\r
-#define __NOP __nop\r
-#define __WFI __wfi\r
-#define __WFE __wfe\r
-#define __SEV __sev\r
-#define __ISB() __isb(0)\r
-#define __DSB() __dsb(0)\r
-#define __DMB() __dmb(0)\r
-#define __REV __rev\r
-#define __RBIT __rbit\r
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
-#define __STREXB(value, ptr) __strex(value, ptr)\r
-#define __STREXH(value, ptr) __strex(value, ptr)\r
-#define __STREXW(value, ptr) __strex(value, ptr)\r
+ The function reads the priority grouping field from the NVIC Interrupt Controller.\r
\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
\r
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
-/* intrinsic void __enable_irq(); */\r
-/* intrinsic void __disable_irq(); */\r
\r
+/** \brief Enable External Interrupt\r
\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
+ The function enables a device-specific interrupt in the NVIC interrupt controller.\r
\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
*/\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
+/** \brief Disable External Interrupt\r
\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
+ The function disables a device-specific interrupt in the NVIC interrupt controller.\r
\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
*/\r
-extern int32_t __REVSH(int16_t value);\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
\r
\r
-#if (__ARMCC_VERSION < 400000)\r
+/** \brief Get Pending Interrupt\r
\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-extern void __CLREX(void);\r
+ The function reads the pending register in the NVIC and returns the pending bit\r
+ for the specified interrupt.\r
\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
+ \param [in] IRQn Interrupt number.\r
\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-#else /* (__ARMCC_VERSION >= 400000) */\r
-\r
-/**\r
- * @brief Remove the exclusive lock created by ldrex\r
- *\r
- * Removes the exclusive lock which is created by ldrex.\r
- */\r
-#define __CLREX __clrex\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
*/\r
-static __INLINE uint32_t __get_BASEPRI(void)\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- return(__regBasePri);\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
}\r
\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-static __INLINE void __set_BASEPRI(uint32_t basePri)\r
-{\r
- register uint32_t __regBasePri __ASM("basepri");\r
- __regBasePri = (basePri & 0xff);\r
-}\r
\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-static __INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- return(__regPriMask);\r
-}\r
+/** \brief Set Pending Interrupt\r
\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-static __INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- register uint32_t __regPriMask __ASM("primask");\r
- __regPriMask = (priMask);\r
-}\r
+ The function sets the pending bit of an external interrupt.\r
\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
*/\r
-static __INLINE uint32_t __get_FAULTMASK(void)\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- return(__regFaultMask);\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
}\r
\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- register uint32_t __regFaultMask __ASM("faultmask");\r
- __regFaultMask = (faultMask & 1);\r
-}\r
\r
-/**\r
- * @brief Return the Control Register value\r
- * \r
- * @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-static __INLINE uint32_t __get_CONTROL(void)\r
-{\r
- register uint32_t __regControl __ASM("control");\r
- return(__regControl);\r
-}\r
+/** \brief Clear Pending Interrupt\r
\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
+ The function clears the pending bit of an external interrupt.\r
+\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
*/\r
-static __INLINE void __set_CONTROL(uint32_t control)\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
{\r
- register uint32_t __regControl __ASM("control");\r
- __regControl = control;\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
}\r
\r
-#endif /* __ARMCC_VERSION */ \r
-\r
-\r
-\r
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
-/* IAR iccarm specific functions */\r
-\r
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
-\r
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
-\r
-#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ \r
-static __INLINE void __WFI() { __ASM ("wfi"); }\r
-static __INLINE void __WFE() { __ASM ("wfe"); }\r
-static __INLINE void __SEV() { __ASM ("sev"); }\r
-static __INLINE void __CLREX() { __ASM ("clrex"); }\r
-\r
-/* intrinsic void __ISB(void) */\r
-/* intrinsic void __DSB(void) */\r
-/* intrinsic void __DMB(void) */\r
-/* intrinsic void __set_PRIMASK(); */\r
-/* intrinsic void __get_PRIMASK(); */\r
-/* intrinsic void __set_FAULTMASK(); */\r
-/* intrinsic void __get_FAULTMASK(); */\r
-/* intrinsic uint32_t __REV(uint32_t value); */\r
-/* intrinsic uint32_t __REVSH(uint32_t value); */\r
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
-/* intrinsic unsigned long __LDREX(unsigned long *); */\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
- */\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive (8 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit values)\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (16 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (32 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (8 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (16 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
\r
-/**\r
- * @brief STR Exclusive (32 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-\r
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
-/* GNU gcc specific functions */\r
+/** \brief Get Active Interrupt\r
\r
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }\r
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }\r
+ The function reads the active register in NVIC and returns the active bit.\r
\r
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }\r
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }\r
+ \param [in] IRQn Interrupt number.\r
\r
-static __INLINE void __NOP() { __ASM volatile ("nop"); }\r
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }\r
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }\r
-static __INLINE void __SEV() { __ASM volatile ("sev"); }\r
-static __INLINE void __ISB() { __ASM volatile ("isb"); }\r
-static __INLINE void __DSB() { __ASM volatile ("dsb"); }\r
-static __INLINE void __DMB() { __ASM volatile ("dmb"); }\r
-static __INLINE void __CLREX() { __ASM volatile ("clrex"); }\r
-\r
-\r
-/**\r
- * @brief Return the Process Stack Pointer\r
- *\r
- * @return ProcessStackPointer\r
- *\r
- * Return the actual process stack pointer\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
*/\r
-extern uint32_t __get_PSP(void);\r
-\r
-/**\r
- * @brief Set the Process Stack Pointer\r
- *\r
- * @param topOfProcStack Process Stack Pointer\r
- *\r
- * Assign the value ProcessStackPointer to the MSP \r
- * (process stack pointer) Cortex processor register\r
- */\r
-extern void __set_PSP(uint32_t topOfProcStack);\r
-\r
-/**\r
- * @brief Return the Main Stack Pointer\r
- *\r
- * @return Main Stack Pointer\r
- *\r
- * Return the current value of the MSP (main stack pointer)\r
- * Cortex processor register\r
- */\r
-extern uint32_t __get_MSP(void);\r
-\r
-/**\r
- * @brief Set the Main Stack Pointer\r
- *\r
- * @param topOfMainStack Main Stack Pointer\r
- *\r
- * Assign the value mainStackPointer to the MSP \r
- * (main stack pointer) Cortex processor register\r
- */\r
-extern void __set_MSP(uint32_t topOfMainStack);\r
-\r
-/**\r
- * @brief Return the Base Priority value\r
- *\r
- * @return BasePriority\r
- *\r
- * Return the content of the base priority register\r
- */\r
-extern uint32_t __get_BASEPRI(void);\r
-\r
-/**\r
- * @brief Set the Base Priority value\r
- *\r
- * @param basePri BasePriority\r
- *\r
- * Set the base priority register\r
- */\r
-extern void __set_BASEPRI(uint32_t basePri);\r
-\r
-/**\r
- * @brief Return the Priority Mask value\r
- *\r
- * @return PriMask\r
- *\r
- * Return state of the priority mask bit from the priority mask register\r
- */\r
-extern uint32_t __get_PRIMASK(void);\r
-\r
-/**\r
- * @brief Set the Priority Mask value\r
- *\r
- * @param priMask PriMask\r
- *\r
- * Set the priority mask bit in the priority mask register\r
- */\r
-extern void __set_PRIMASK(uint32_t priMask);\r
-\r
-/**\r
- * @brief Return the Fault Mask value\r
- *\r
- * @return FaultMask\r
- *\r
- * Return the content of the fault mask register\r
- */\r
-extern uint32_t __get_FAULTMASK(void);\r
-\r
-/**\r
- * @brief Set the Fault Mask value\r
- *\r
- * @param faultMask faultMask value\r
- *\r
- * Set the fault mask register\r
- */\r
-extern void __set_FAULTMASK(uint32_t faultMask);\r
-\r
-/**\r
- * @brief Return the Control Register value\r
-* \r
-* @return Control value\r
- *\r
- * Return the content of the control register\r
- */\r
-extern uint32_t __get_CONTROL(void);\r
-\r
-/**\r
- * @brief Set the Control Register value\r
- *\r
- * @param control Control value\r
- *\r
- * Set the control register\r
- */\r
-extern void __set_CONTROL(uint32_t control);\r
-\r
-/**\r
- * @brief Reverse byte order in integer value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in integer value\r
- */\r
-extern uint32_t __REV(uint32_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in unsigned short value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in unsigned short value\r
- */\r
-extern uint32_t __REV16(uint16_t value);\r
-\r
-/**\r
- * @brief Reverse byte order in signed short value with sign extension to integer\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse byte order in signed short value with sign extension to integer\r
- */\r
-extern int32_t __REVSH(int16_t value);\r
-\r
-/**\r
- * @brief Reverse bit order of value\r
- *\r
- * @param value value to reverse\r
- * @return reversed value\r
- *\r
- * Reverse bit order of value\r
- */\r
-extern uint32_t __RBIT(uint32_t value);\r
-\r
-/**\r
- * @brief LDR Exclusive (8 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 8 bit value\r
- */\r
-extern uint8_t __LDREXB(uint8_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (16 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 16 bit values\r
- */\r
-extern uint16_t __LDREXH(uint16_t *addr);\r
-\r
-/**\r
- * @brief LDR Exclusive (32 bit)\r
- *\r
- * @param *addr address pointer\r
- * @return value of (*address)\r
- *\r
- * Exclusive LDR command for 32 bit values\r
- */\r
-extern uint32_t __LDREXW(uint32_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (8 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 8 bit values\r
- */\r
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (16 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 16 bit values\r
- */\r
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
-\r
-/**\r
- * @brief STR Exclusive (32 bit)\r
- *\r
- * @param value value to store\r
- * @param *addr address pointer\r
- * @return successful / failed\r
- *\r
- * Exclusive STR command for 32 bit values\r
- */\r
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
-\r
-\r
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
-/* TASKING carm specific functions */\r
-\r
-/*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all instrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-#endif\r
-\r
-\r
-/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface\r
- Core Function Interface containing:\r
- - Core NVIC Functions\r
- - Core SysTick Functions\r
- - Core Reset Functions\r
-*/\r
-/*@{*/\r
-\r
-/* ########################## NVIC functions #################################### */\r
-\r
-/**\r
- * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
- *\r
- * @param PriorityGroup is priority grouping field\r
- *\r
- * Set the priority grouping field using the required unlock sequence.\r
- * The parameter priority_grouping is assigned to the field \r
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
- */\r
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
{\r
- uint32_t reg_value;\r
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
- \r
- reg_value = SCB->AIRCR; /* read old register configuration */\r
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
- reg_value = (reg_value |\r
- (0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
- SCB->AIRCR = reg_value;\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
}\r
\r
-/**\r
- * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
- *\r
- * @return priority grouping field \r
- *\r
- * Get the priority grouping from NVIC Interrupt Controller.\r
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
- */\r
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
-{\r
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
-}\r
\r
-/**\r
- * @brief Enable Interrupt in NVIC Interrupt Controller\r
- *\r
- * @param IRQn The positive number of the external interrupt to enable\r
- *\r
- * Enable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
-}\r
+/** \brief Set Interrupt Priority\r
\r
-/**\r
- * @brief Disable the interrupt line for external interrupt specified\r
- * \r
- * @param IRQn The positive number of the external interrupt to disable\r
- * \r
- * Disable a device specific interupt in the NVIC interrupt controller.\r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
-}\r
+ The function sets the priority of an interrupt.\r
\r
-/**\r
- * @brief Read the interrupt pending bit for a device specific interrupt source\r
- * \r
- * @param IRQn The number of the device specifc interrupt\r
- * @return 1 = interrupt pending, 0 = interrupt not pending\r
- *\r
- * Read the pending register in NVIC and return 1 if its status is pending, \r
- * otherwise it returns 0\r
- */\r
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
-}\r
+ \note The priority cannot be set for every core interrupt.\r
\r
-/**\r
- * @brief Set the pending bit for an external interrupt\r
- * \r
- * @param IRQn The number of the interrupt for set pending\r
- *\r
- * Set the pending bit for the specified interrupt.\r
- * The interrupt number cannot be a negative value.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
*/\r
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
-}\r
-\r
-/**\r
- * @brief Clear the pending bit for an external interrupt\r
- *\r
- * @param IRQn The number of the interrupt for clear pending\r
- *\r
- * Clear the pending bit for the specified interrupt. \r
- * The interrupt number cannot be a negative value.\r
- */\r
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
-{\r
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
-}\r
-\r
-/**\r
- * @brief Read the active bit for an external interrupt\r
- *\r
- * @param IRQn The number of the interrupt for read active bit\r
- * @return 1 = interrupt active, 0 = interrupt not active\r
- *\r
- * Read the active register in NVIC and returns 1 if its status is active, \r
- * otherwise it returns 0.\r
- */\r
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
-{\r
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
-}\r
-\r
-/**\r
- * @brief Set the priority for an interrupt\r
- *\r
- * @param IRQn The number of the interrupt for set priority\r
- * @param priority The priority to set\r
- *\r
- * Set the priority for the specified interrupt. The interrupt \r
- * number can be positive to specify an external (device specific) \r
- * interrupt, or negative to specify an internal (core) interrupt.\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
- */\r
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
{\r
if(IRQn < 0) {\r
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */\r
else {\r
NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
}\r
\r
-/**\r
- * @brief Read the priority for an interrupt\r
- *\r
- * @param IRQn The number of the interrupt for get priority\r
- * @return The priority for the interrupt\r
- *\r
- * Read the priority for the specified interrupt. The interrupt \r
- * number can be positive to specify an external (device specific) \r
- * interrupt, or negative to specify an internal (core) interrupt.\r
- *\r
- * The returned priority value is automatically aligned to the implemented\r
- * priority bits of the microcontroller.\r
- *\r
- * Note: The priority cannot be set for every core interrupt.\r
+\r
+/** \brief Get Interrupt Priority\r
+\r
+ The function reads the priority of an interrupt. The interrupt\r
+ number can be positive to specify an external (device specific)\r
+ interrupt, or negative to specify an internal (core) interrupt.\r
+\r
+\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority. Value is aligned automatically to the implemented\r
+ priority bits of the microcontroller.\r
*/\r
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
{\r
\r
if(IRQn < 0) {\r
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */\r
else {\r
return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
}\r
\r
\r
-/**\r
- * @brief Encode the priority for an interrupt\r
- *\r
- * @param PriorityGroup The used priority group\r
- * @param PreemptPriority The preemptive priority value (starting from 0)\r
- * @param SubPriority The sub priority value (starting from 0)\r
- * @return The encoded priority for the interrupt\r
- *\r
- * Encode the priority for an interrupt with the given priority group,\r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The returned priority value can be used for NVIC_SetPriority(...) function\r
+/** \brief Encode Priority\r
+\r
+ The function encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.\r
+\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
*/\r
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
{\r
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
uint32_t PreemptPriorityBits;\r
\r
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
- \r
+\r
return (\r
((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
}\r
\r
\r
-/**\r
- * @brief Decode the priority of an interrupt\r
- *\r
- * @param Priority The priority for the interrupt\r
- * @param PriorityGroup The used priority group\r
- * @param pPreemptPriority The preemptive priority value (starting from 0)\r
- * @param pSubPriority The sub priority value (starting from 0)\r
- *\r
- * Decode an interrupt priority value with the given priority group to \r
- * preemptive priority value and sub priority value.\r
- * In case of a conflict between priority grouping and available\r
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
- *\r
- * The priority value can be retrieved with NVIC_GetPriority(...) function\r
+/** \brief Decode Priority\r
+\r
+ The function decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
*/\r
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
{\r
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
uint32_t PreemptPriorityBits;\r
\r
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
- \r
+\r
*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
}\r
\r
\r
+/** \brief System Reset\r
\r
-/* ################################## SysTick function ############################################ */\r
+ The function initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+ while(1); /* wait until reset */\r
+}\r
\r
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
\r
-/**\r
- * @brief Initialize and start the SysTick counter and its interrupt.\r
- *\r
- * @param ticks number of ticks between two interrupts\r
- * @return 1 = failed, 0 = successful\r
- *\r
- * Initialise the system tick timer and its interrupt and start the\r
- * system tick timer / counter in free running mode to generate \r
- * periodical interrupts.\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
*/\r
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
-{ \r
- if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
- \r
- SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
- SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | \r
- SysTick_CTRL_TICKINT_Msk | \r
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
- return (0); /* Function successful */\r
-}\r
\r
-#endif\r
+#if (__Vendor_SysTickConfig == 0)\r
\r
+/** \brief System Tick Configuration\r
\r
+ The function initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
\r
+ \param [in] ticks Number of ticks between two interrupts.\r
\r
-/* ################################## Reset function ############################################ */\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
\r
-/**\r
- * @brief Initiate a system reset request.\r
- *\r
- * Initiate a system reset request to reset the MCU\r
*/\r
-static __INLINE void NVIC_SystemReset(void)\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
{\r
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | \r
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
- __DSB(); /* Ensure completion of memory access */ \r
- while(1); /* wait until reset */\r
+ if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+\r
+ SysTick->LOAD = ticks - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
}\r
\r
-/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
\r
\r
\r
/* ##################################### Debug In/Output function ########################################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
\r
-/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface\r
- Core Debug Interface containing:\r
- - Core Debug Receive / Transmit Functions\r
- - Core Debug Defines\r
- - Core Debug Variables\r
-*/\r
-/*@{*/\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
\r
-extern volatile int ITM_RxBuffer; /*!< variable to receive characters */\r
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
\r
+/** \brief ITM Send Character\r
\r
-/**\r
- * @brief Outputs a character via the ITM channel 0\r
- *\r
- * @param ch character to output\r
- * @return character to output\r
- *\r
- * The function outputs a character via the ITM channel 0. \r
- * The function returns when no debugger is connected that has booked the output. \r
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ The function transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+\r
+ \param [in] ch Character to transmit.\r
+\r
+ \returns Character to transmit.\r
*/\r
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
{\r
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
- (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */\r
+ if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */\r
{\r
while (ITM->PORT[0].u32 == 0);\r
ITM->PORT[0].u8 = (uint8_t) ch;\r
- } \r
+ }\r
return (ch);\r
}\r
\r
\r
-/**\r
- * @brief Inputs a character via variable ITM_RxBuffer\r
- *\r
- * @return received character, -1 = no character received\r
- *\r
- * The function inputs a character via variable ITM_RxBuffer. \r
- * The function returns when no debugger is connected that has booked the output. \r
- * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+/** \brief ITM Receive Character\r
+\r
+ The function inputs a character via the external variable \ref ITM_RxBuffer.\r
+\r
+ \return Received character.\r
+ \return -1 No character pending.\r
*/\r
-static __INLINE int ITM_ReceiveChar (void) {\r
- int ch = -1; /* no character available */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void) {\r
+ int32_t ch = -1; /* no character available */\r
\r
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
ch = ITM_RxBuffer;\r
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
}\r
- \r
- return (ch); \r
+\r
+ return (ch);\r
}\r
\r
\r
-/**\r
- * @brief Check if a character via variable ITM_RxBuffer is available\r
- *\r
- * @return 1 = character available, 0 = no character available\r
- *\r
- * The function checks variable ITM_RxBuffer whether a character is available or not. \r
- * The function returns '1' if a character is available and '0' if no character is available. \r
+/** \brief ITM Check Character\r
+\r
+ The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
*/\r
-static __INLINE int ITM_CheckChar (void) {\r
+__STATIC_INLINE int32_t ITM_CheckChar (void) {\r
\r
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
return (0); /* no character available */\r
}\r
}\r
\r
-/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+#endif /* __CORE_CM3_H_DEPENDANT */\r
\r
+#endif /* __CMSIS_GENERIC */\r
\r
#ifdef __cplusplus\r
}\r
#endif\r
-\r
-/*@}*/ /* end of group CMSIS_CM3_core_definitions */\r
-\r
-#endif /* __CM3_CORE_H__ */\r
-\r
-/*lint -restore */\r
/*******************************************************************************\r
* File Name: core_cm3_psoc5.h\r
-* Version 3.40\r
+* Version 4.0\r
*\r
* Description:\r
* Provides important type information for the PSoC5. This includes types\r
/* Not relevant. All peripheral interrupts are defined by the user */\r
} IRQn_Type;\r
\r
+#include <cytypes.h>\r
+\r
+#define __CHECK_DEVICE_DEFINES\r
+\r
+#define __CM3_REV 0x0201\r
+\r
+#define __MPU_PRESENT 0\r
+#define __NVIC_PRIO_BITS 3\r
+#define __Vendor_SysTickConfig 0\r
+\r
#include <core_cm3.h>\r
\r
+\r
#endif /* __CORE_CM3_PSOC5_H__ */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V3.20\r
+ * @date 25. February 2013\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ register uint32_t __regIPSR __ASM("ipsr");\r
+ return(__regIPSR);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ register uint32_t __regAPSR __ASM("apsr");\r
+ return(__regAPSR);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ register uint32_t __regXPSR __ASM("xpsr");\r
+ return(__regXPSR);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ return(__regProcessStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ register uint32_t __regProcessStackPointer __ASM("psp");\r
+ __regProcessStackPointer = topOfProcStack;\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ return(__regMainStackPointer);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ register uint32_t __regMainStackPointer __ASM("msp");\r
+ __regMainStackPointer = topOfMainStack;\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __enable_fault_irq __enable_fiq\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & (uint32_t)1);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ return(__regfpscr);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ register uint32_t __regfpscr __ASM("fpscr");\r
+ __regfpscr = (fpscr);\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/** \brief Enable IRQ Interrupts\r
+\r
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Disable IRQ Interrupts\r
+\r
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Control Register\r
+\r
+ This function returns the content of the Control Register.\r
+\r
+ \return Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Control Register\r
+\r
+ This function writes the given value to the Control Register.\r
+\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+/** \brief Get IPSR Register\r
+\r
+ This function returns the content of the IPSR Register.\r
+\r
+ \return IPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get APSR Register\r
+\r
+ This function returns the content of the APSR Register.\r
+\r
+ \return APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get xPSR Register\r
+\r
+ This function returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Get Process Stack Pointer\r
+\r
+ This function returns the current value of the Process Stack Pointer (PSP).\r
+\r
+ \return PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Process Stack Pointer\r
+\r
+ This function assigns the given value to the Process Stack Pointer (PSP).\r
+\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");\r
+}\r
+\r
+\r
+/** \brief Get Main Stack Pointer\r
+\r
+ This function returns the current value of the Main Stack Pointer (MSP).\r
+\r
+ \return MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Main Stack Pointer\r
+\r
+ This function assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");\r
+}\r
+\r
+\r
+/** \brief Get Priority Mask\r
+\r
+ This function returns the current state of the priority mask bit from the Priority Mask Register.\r
+\r
+ \return Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Priority Mask\r
+\r
+ This function assigns the given value to the Priority Mask Register.\r
+\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Enable FIQ\r
+\r
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Disable FIQ\r
+\r
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Base Priority\r
+\r
+ This function returns the current value of the Base Priority register.\r
+\r
+ \return Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Base Priority\r
+\r
+ This function assigns the given value to the Base Priority register.\r
+\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/** \brief Get Fault Mask\r
+\r
+ This function returns the current value of the Fault Mask register.\r
+\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Set Fault Mask\r
+\r
+ This function assigns the given value to the Fault Mask register.\r
+\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04)\r
+\r
+/** \brief Get FPSCR\r
+\r
+ This function returns the current value of the Floating Point Status/Control register.\r
+\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ uint32_t result;\r
+\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ __ASM volatile ("");\r
+ return(result);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Set FPSCR\r
+\r
+ This function assigns the given value to the Floating Point Status/Control register.\r
+\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
+ __ASM volatile ("");\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04) */\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V3.20\r
+ * @date 05. March 2013\r
+ *\r
+ * @note\r
+ *\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2013 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#if (__ARMCC_VERSION < 400677)\r
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"\r
+#endif\r
+\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+#define __NOP __nop\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+#define __WFI __wfi\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+#define __WFE __wfe\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+#define __SEV __sev\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+#define __ISB() __isb(0xF)\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+#define __DSB() __dsb(0xF)\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+#define __DMB() __dmb(0xF)\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __REV __rev\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#ifndef __NO_EMBEDDED_ASM\r
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+#endif\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+#define __ROR __ror\r
+\r
+\r
+/** \brief Breakpoint\r
+\r
+ This function causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __breakpoint(value)\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+#define __RBIT __rbit\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+#define __CLREX __clrex\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT __ssat\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT __usat\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __clz\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#include <cmsis_iar.h>\r
+\r
+\r
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/\r
+/* TI CCS specific functions */\r
+\r
+#include <cmsis_ccs.h>\r
+\r
+\r
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constrant "l"\r
+ * Otherwise, use general registers, specified by constrant "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/** \brief No Operation\r
+\r
+ No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/** \brief Wait For Interrupt\r
+\r
+ Wait For Interrupt is a hint instruction that suspends execution\r
+ until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/** \brief Wait For Event\r
+\r
+ Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/** \brief Send Event\r
+\r
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/** \brief Instruction Synchronization Barrier\r
+\r
+ Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or\r
+ memory, after the instruction has been completed.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb");\r
+}\r
+\r
+\r
+/** \brief Data Synchronization Barrier\r
+\r
+ This function acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb");\r
+}\r
+\r
+\r
+/** \brief Data Memory Barrier\r
+\r
+ This function ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb");\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (32 bit)\r
+\r
+ This function reverses the byte order in integer value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
+ return __builtin_bswap32(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Reverse byte order (16 bit)\r
+\r
+ This function reverses the byte order in two unsigned short values.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Reverse byte order in signed short value\r
+\r
+ This function reverses the byte order in a signed short value with sign extension to integer.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ return (short)__builtin_bswap16(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/** \brief Rotate Right in unsigned value (32 bit)\r
+\r
+ This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ return (op1 >> op2) | (op1 << (32 - op2));\r
+}\r
+\r
+\r
+/** \brief Breakpoint\r
+\r
+ This function causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+#if (__CORTEX_M >= 0x03)\r
+\r
+/** \brief Reverse bit order of value\r
+\r
+ This function reverses the bit order of the given value.\r
+\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive LDR command for 8 bit value.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive LDR command for 16 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief LDR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive LDR command for 32 bit values.\r
+\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (8 bit)\r
+\r
+ This function performs a exclusive STR command for 8 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (16 bit)\r
+\r
+ This function performs a exclusive STR command for 16 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief STR Exclusive (32 bit)\r
+\r
+ This function performs a exclusive STR command for 32 bit values.\r
+\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/** \brief Remove the exclusive lock\r
+\r
+ This function removes the exclusive lock which is created by LDREX.\r
+\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex" ::: "memory");\r
+}\r
+\r
+\r
+/** \brief Signed Saturate\r
+\r
+ This function saturates a signed value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Unsigned Saturate\r
+\r
+ This function saturates an unsigned value.\r
+\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/** \brief Count leading zeros\r
+\r
+ This function counts the number of leading zeros of a data value.\r
+\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03) */\r
+\r
+\r
+\r
+\r
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
/*******************************************************************************\r
* File Name: cyPm.c\r
-* Version 3.40\r
+* Version 4.0\r
*\r
* Description:\r
* Provides an API for the power management.\r
static void CyPmHibSaveSet(void);\r
static void CyPmHibRestore(void) ;\r
\r
-static void CyPmSlpSaveSet(void) ;\r
-static void CyPmSlpRestore(void) ;\r
-\r
static void CyPmHibSlpSaveSet(void) ;\r
static void CyPmHibSlpRestore(void) ;\r
\r
static void CyPmHviLviSaveDisable(void) ;\r
static void CyPmHviLviRestore(void) ;\r
\r
-#if(CY_PSOC5A)\r
-\r
- /***************************************************************************\r
- * The PICU interupt event is not allowed to act as wakeup source for PSoC 5.\r
- * To prevent accidental wakeup all the PICU interrupts are disabled before\r
- * Sleep and Hibernate low power modes entry. In case of Sleep mode registers\r
- * values must be restored on wakeup, but in case of Hibernate low power mode\r
- * there is no sense in saving/restoring registers values as the only wakeup\r
- * source for this mode is external reset (XRES). For more information refer\r
- * to the PSoC 5 device TRM.\r
- ***************************************************************************/\r
-\r
- static void CyPmSavePicuInterrupts(void);\r
- static void CyPmDisablePicuInterrupts(void) ;\r
- static void CyPmRestorePicuInterrupts(void) ;\r
-\r
-#endif /* (CY_PSOC5A) */\r
-\r
\r
/*******************************************************************************\r
* Function Name: CyPmSaveClocks\r
} /* Need to change nothing if master clock source is IMO */\r
\r
/* Bus clock - save divider and set it, if needed, to divide-by-one */\r
- cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u) | CY_PM_CLK_BUS_LSB_DIV_REG;\r
+ cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u);\r
+ cyPmClockBackup.clkBusDiv |= CY_PM_CLK_BUS_LSB_DIV_REG;\r
if(CY_PM_BUS_CLK_DIV_BY_ONE != cyPmClockBackup.clkBusDiv)\r
{\r
CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE);\r
*******************************************************************************/\r
void CyPmRestoreClocks(void) \r
{\r
- #if (!CY_PSOC5A)\r
-\r
- cystatus status = CYRET_TIMEOUT;\r
- uint16 i;\r
-\r
- #endif /* (!CY_PSOC5A) */\r
+ cystatus status = CYRET_TIMEOUT;\r
+ uint16 i;\r
+ uint16 clkBusDivTmp;\r
\r
\r
/* Convertion table between CyIMO_SetFreq() parameters and register's value */\r
/* Enable XMHZ XTAL with no wait */\r
(void) CyXTAL_Start(CY_PM_XTAL_MHZ_NO_WAIT);\r
\r
- #if(CY_PSOC5A)\r
+ /* Read XERR bit to clear it */\r
+ (void) CY_PM_FASTCLK_XMHZ_CSR_REG;\r
\r
- /* Make a 130 milliseconds delay */\r
- CyDelayCycles((uint32)CY_PM_WAIT_200_US * CY_PM_GET_CPU_FREQ_MHZ * CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US);\r
-\r
- #else\r
-\r
- /* Read XERR bit to clear it */\r
- (void) CY_PM_FASTCLK_XMHZ_CSR_REG;\r
-\r
- /* Wait */\r
- for(i = CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US; i > 0u; i--)\r
- {\r
- /* Make a 200 microseconds delay */\r
- CyDelayCycles((uint32)CY_PM_WAIT_200_US * CY_PM_GET_CPU_FREQ_MHZ);\r
-\r
- /* High output indicates oscillator failure */\r
- if(0u == (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_XERR))\r
- {\r
- status = CYRET_SUCCESS;\r
- break;\r
- }\r
- }\r
+ /* Wait */\r
+ for(i = CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US; i > 0u; i--)\r
+ {\r
+ /* Make a 200 microseconds delay */\r
+ CyDelayCycles((uint32)CY_PM_WAIT_200_US * CY_PM_GET_CPU_FREQ_MHZ);\r
\r
- if(CYRET_TIMEOUT == status)\r
+ /* High output indicates oscillator failure */\r
+ if(0u == (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_XERR))\r
{\r
- /*******************************************************************\r
- * Process the situation when megahertz crystal is not ready.\r
- * Time to stabialize value is crystal specific.\r
- *******************************************************************/\r
-\r
- /* `#START_MHZ_ECO_TIMEOUT` */\r
-\r
- /* `#END` */\r
+ status = CYRET_SUCCESS;\r
+ break;\r
}\r
+ }\r
\r
- #endif /* (CY_PSOC5A) */\r
+ if(CYRET_TIMEOUT == status)\r
+ {\r
+ /*******************************************************************\r
+ * Process the situation when megahertz crystal is not ready.\r
+ * Time to stabialize value is crystal specific.\r
+ *******************************************************************/\r
+ /* `#START_MHZ_ECO_TIMEOUT` */\r
\r
+ /* `#END` */\r
+ }\r
} /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */\r
\r
\r
}\r
\r
/* Bus clock - restore divider, if needed */\r
- if(cyPmClockBackup.clkBusDiv != ((uint16)((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u) | CY_PM_CLK_BUS_LSB_DIV_REG))\r
+ clkBusDivTmp = (uint16) ((uint16)CY_PM_CLK_BUS_MSB_DIV_REG << 8u);\r
+ clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG;\r
+ if(cyPmClockBackup.clkBusDiv != clkBusDivTmp)\r
{\r
CyBusClk_SetDivider(cyPmClockBackup.clkBusDiv);\r
}\r
* then specify NONE for the wakeupTime and include the appropriate source for\r
* wakeupSource.\r
*\r
-* PSoC 5:\r
-* This function is used to both enter the Alternate Active mode and halt the\r
-* processor. For PSoC 3 these two actions must be paired together. With\r
-* PSoC 5 the processor can be halted independently with the __WFI() function\r
-* from the CMSIS library that is included in Creator. This function should be\r
-* used instead when the action required is just to halt the processor until an\r
-* enabled interrupt occurs.\r
-*\r
-* Neither of the parameters to the CyPmAltAct() function are used. The\r
-* parameters must be set to 0 (PM_ALT_ACT_TIME_NONE and PM_ALT_ACT_SRC_NONE).\r
-* The wake up time configuration can be done by a separate component: the CTW\r
-* wakeup interval should be configured with the Sleep Timer component and one\r
-* second interval should be configured with the RTC component.\r
-*\r
-* Upon function execution the device will be switched from Active to Alternate\r
-* Active mode and the CPU will be halted. When an enabled interrupt occurs the\r
-* device will be switched to Active mode and the CPU will be started. Note that\r
-* if a wakeup event occurs and the associated interrupt is not enabled, then\r
-* the device will switch to Active mode with the CPU still halted. The CPU will\r
-* remain halted until an enabled interrupt occurs.\r
-*\r
* PSoC 5LP:\r
* This function is used to both enter the Alternate Active mode and halt the\r
* processor. For PSoC 3 these two actions must be paired together. With PSoC\r
*\r
* Parameters:\r
* wakeupTime: Specifies a timer wakeup source and the frequency of that\r
-* source. For PSoC 5 and PSoC 5LP this parameter is ignored.\r
+* source. For PSoC 5LP this parameter is ignored.\r
*\r
* Define Time\r
* PM_ALT_ACT_TIME_NONE None\r
*\r
* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if\r
* a wakeupTime has been specified the associated timer will be\r
-* included as a wakeup source. For PSoC 5 this parameter is\r
-* ignored.\r
+* included as a wakeup source.\r
*\r
* Define Source\r
* PM_ALT_ACT_SRC_NONE None\r
/* Arguments expected to be 0 */\r
CYASSERT(PM_ALT_ACT_TIME_NONE == wakeupTime);\r
\r
- #if(CY_PSOC5A)\r
-\r
- /* The wakeupSource argument expected to be 0 */\r
- CYASSERT(PM_ALT_ACT_SRC_NONE == wakeupSource);\r
-\r
- if(0u != wakeupSource)\r
- {\r
- /* To remove unreferenced local variable warning */\r
- }\r
-\r
- #endif /* (CY_PSOC5A) */\r
-\r
if(0u != wakeupTime)\r
{\r
/* To remove unreferenced local variable warning */\r
#endif /* (CY_PSOC3) */\r
\r
\r
- #if(CY_PSOC3 || CY_PSOC5LP)\r
-\r
- /* Save and set new wake up configuration */\r
-\r
- /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */\r
- cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG;\r
- CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u);\r
+ /* Save and set new wake up configuration */\r
\r
- /* Comparators */\r
- cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG;\r
- CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK);\r
+ /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */\r
+ cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG;\r
+ CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u);\r
\r
- /* LCD */\r
- cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG;\r
- CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u));\r
+ /* Comparators */\r
+ cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG;\r
+ CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK);\r
\r
- #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+ /* LCD */\r
+ cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG;\r
+ CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u));\r
\r
\r
/* Switch to the Alternate Active mode */\r
\r
/* Point of return from Alternate Active Mode */\r
\r
- #if(CY_PSOC3 || CY_PSOC5LP)\r
-\r
- /* Restore wake up configuration */\r
- CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0;\r
- CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1;\r
- CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2;\r
-\r
- #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+ /* Restore wake up configuration */\r
+ CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0;\r
+ CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1;\r
+ CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2;\r
}\r
\r
\r
* then specify NONE for the wakeupTime and include the appropriate source for\r
* wakeupSource.\r
*\r
-* PSoC 5:\r
-* Neither parameter to this function is used for PSoC 5. The parameters must be\r
-* set to 0 (PM_SLEEP_TIME_NONE and PM_SLEEP_SRC_NONE). The device will go\r
-* into Sleep mode until it is woken by an interrupt from the Central Time Wheel\r
-* (CTW). The CTW must already be configured to generate an interrupt. It is\r
-* configured using the SleepTimer component. Only the CTW can be used to wake\r
-* the device from sleep mode. The other wakeup sources, Once per second or\r
-* Port Interrupt Controller (PICU), cannot be used reliably with PSoC 5. This\r
-* function automatically disables these interrupt sources and then restores\r
-* them after the devices is woken by the CTW.\r
-*\r
-* The duration of sleep needs to be controlled so that the device doesn't wake\r
-* up too soon after going to sleep or remain asleep for too long. Reliable\r
-* sleep times of between 1 ms and 128 ms can be supported. This requirement is\r
-* satisfied with CTW settings of 4, 8, 16, 32, 64, 128 or 256 ms. To control\r
-* the sleep time the CTW is reset automatically just before putting the device\r
-* to sleep. The resulting wakeup time is half the duration programmed into the\r
-* CTW with an uncertainty of 1 ms due to the arrival time of the first ILO\r
-* clock edge. For example, the setting of 4 ms will result in a sleep time\r
-* between 1 ms and 2 ms.\r
-*\r
* PSoC 5LP:\r
* The wakeupTime parameter is not used and the only NONE can be specified.\r
* The wakeup time must be configured with the component, SleepTimer for CTW\r
*\r
* Parameters:\r
* wakeupTime: Specifies a timer wakeup source and the frequency of that\r
-* source. For PSoC 5 and PSoC 5LP, this parameter is ignored.\r
+* source. For PSoC 5LP, this parameter is ignored.\r
*\r
* Define Time\r
* PM_SLEEP_TIME_NONE None\r
*\r
* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if\r
* a wakeupTime has been specified the associated timer will be\r
-* included as a wakeup source. For PSoC 5 this parameter is\r
-* ignored.\r
+* included as a wakeup source.\r
*\r
* Define Source\r
* PM_SLEEP_SRC_NONE None\r
* PM_SLEEP_SRC_LCD LCD\r
*\r
* *Note: CTW and One PPS wakeup signals are in the same mask bit.\r
-* For PSoC 5, these are in a different bit (value 1024).\r
*\r
* When specifying a Comparator as the wakeupSource an instance specific define\r
* should be used that will track with the specific comparator that the instance\r
* No\r
*\r
* Side Effects and Restrictions:\r
-* For PSoC 5 silicon the wakeup source is not selectable. In this case the\r
-* wakeupSource argument is ignored and any of the available wakeup sources will\r
-* wake the device.\r
-*\r
* If a wakeupTime other than NONE is specified, then upon exit the state of the\r
* specified timer will be left as specified by wakeupTime with the timer\r
* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is\r
interruptState = CyEnterCriticalSection();\r
\r
\r
- #if(CY_PSOC3 || CY_PSOC5LP)\r
-\r
- /***********************************************************************\r
- * The Hibernate/Sleep regulator has a settling time after a reset.\r
- * During this time, the system ignores requests to enter Sleep and\r
- * Hibernate modes. The holdoff delay is measured using rising edges of\r
- * the 1 kHz ILO.\r
- ***********************************************************************/\r
- if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q))\r
- {\r
- /* Disable hold off - no action on restore */\r
- CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK;\r
- }\r
- else\r
- {\r
- /* Abort, device is not ready for low power mode entry */\r
-\r
- /* Restore global interrupt enable state */\r
- CyExitCriticalSection(interruptState);\r
+ /***********************************************************************\r
+ * The Hibernate/Sleep regulator has a settling time after a reset.\r
+ * During this time, the system ignores requests to enter Sleep and\r
+ * Hibernate modes. The holdoff delay is measured using rising edges of\r
+ * the 1 kHz ILO.\r
+ ***********************************************************************/\r
+ if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q))\r
+ {\r
+ /* Disable hold off - no action on restore */\r
+ CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK;\r
+ }\r
+ else\r
+ {\r
+ /* Abort, device is not ready for low power mode entry */\r
\r
- return;\r
- }\r
+ /* Restore global interrupt enable state */\r
+ CyExitCriticalSection(interruptState);\r
\r
- #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+ return;\r
+ }\r
\r
\r
+ /***********************************************************************\r
+ * PSoC3 < TO6:\r
+ * - Hardware buzz must be disabled before sleep mode entry.\r
+ * - Voltage supervision (HVI/LVI) requires hardware buzz, so they must\r
+ * be aslo disabled.\r
+ *\r
+ * PSoC3 >= TO6:\r
+ * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware buzz must be\r
+ * enabled before sleep mode entry and restored on wakeup.\r
+ ***********************************************************************/\r
#if(CY_PSOC3)\r
\r
/* Silicon Revision ID is below TO6 */\r
{\r
/* Hardware buzz expected to be disabled in Sleep mode */\r
CYASSERT(0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ));\r
+ }\r
+\r
\r
- /* LVI/HVI requires hardware buzz to be enabled */\r
- if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN |\r
- CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN)))\r
+ if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN |\r
+ CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN)))\r
+ {\r
+ if(CYDEV_CHIP_REV_ACTUAL < 5u)\r
{\r
+ /* LVI/HVI requires hardware buzz to be enabled */\r
CYASSERT(0u != 0u);\r
}\r
+ else\r
+ {\r
+ if (0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ))\r
+ {\r
+ cyPmBackup.hardwareBuzz = CY_PM_DISABLED;\r
+ CY_PM_PWRSYS_WAKE_TR2_REG |= CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ;\r
+ }\r
+ else\r
+ {\r
+ cyPmBackup.hardwareBuzz = CY_PM_ENABLED;\r
+ }\r
+ }\r
}\r
\r
#endif /* (CY_PSOC3) */\r
/* Arguments expected to be 0 */\r
CYASSERT(PM_SLEEP_TIME_NONE == wakeupTime);\r
\r
- #if(CY_PSOC5A)\r
-\r
- /* The wakeupSource argument expected to be 0 */\r
- CYASSERT(PM_SLEEP_SRC_NONE == wakeupSource);\r
-\r
- if(0u != wakeupSource)\r
- {\r
- /* To remove unreferenced local variable warning */\r
- }\r
-\r
- #endif /* (CY_PSOC5A) */\r
-\r
if(0u != wakeupTime)\r
{\r
/* To remove unreferenced local variable warning */\r
#endif /* (CY_PSOC5) */\r
\r
\r
- /* Prepare hardware for Sleep mode */\r
- CyPmSlpSaveSet();\r
+ CyPmHibSlpSaveSet();\r
\r
\r
#if(CY_PSOC3)\r
#endif /* (CY_PSOC3) */\r
\r
\r
- #if(!CY_PSOC5A)\r
-\r
- /* Save and set new wake up configuration */\r
+ /* Save and set new wake up configuration */\r
\r
- /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */\r
- cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG;\r
- CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u);\r
+ /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */\r
+ cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG;\r
+ CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u);\r
\r
- /* Comparators */\r
- cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG;\r
- CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK);\r
+ /* Comparators */\r
+ cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG;\r
+ CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK);\r
\r
- /* LCD */\r
- cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG;\r
- CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u));\r
-\r
- #endif /* (!CY_PSOC5A) */\r
+ /* LCD */\r
+ cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG;\r
+ CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u));\r
\r
\r
/*******************************************************************\r
\r
\r
/* Restore hardware configuration */\r
- CyPmSlpRestore();\r
+ CyPmHibSlpRestore();\r
\r
\r
- #if(!CY_PSOC5A)\r
+ /* Disable hardware buzz, if it was previously enabled */\r
+ #if(CY_PSOC3)\r
\r
- /* Restore current wake up configuration */\r
- CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0;\r
- CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1;\r
- CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2;\r
+ if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN |\r
+ CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN)))\r
+ {\r
+ if(CYDEV_CHIP_REV_ACTUAL >= 5u)\r
+ {\r
+ if (CY_PM_DISABLED == cyPmBackup.hardwareBuzz)\r
+ {\r
+ CY_PM_PWRSYS_WAKE_TR2_REG &= (uint8)(~CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ);\r
+ }\r
+ }\r
+ }\r
+\r
+ #endif /* (CY_PSOC3) */\r
\r
- #endif /* (!CY_PSOC5A) */\r
+\r
+ /* Restore current wake up configuration */\r
+ CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0;\r
+ CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1;\r
+ CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2;\r
\r
/* Restore global interrupt enable state */\r
CyExitCriticalSection(interruptState);\r
* option. Once the wakeup occurs, the PICU wakeup source bit is restored and\r
* the PSoC returns to the Active state.\r
*\r
-* PSoC 5:\r
-* The only method supported for waking up from the Hibernate state is a\r
-* hardware reset of the device. The PICU wakeup source cannot be used\r
-* reliably, so the PICU interrupt sources are automatically disabled by this\r
-* function before putting the device into the Hibernate state.\r
-*\r
* Parameters:\r
* None\r
*\r
/* Save current global interrupt enable and disable it */\r
interruptState = CyEnterCriticalSection();\r
\r
- #if(CY_PSOC3 || CY_PSOC5LP)\r
-\r
/***********************************************************************\r
* The Hibernate/Sleep regulator has a settling time after a reset.\r
* During this time, the system ignores requests to enter Sleep and\r
return;\r
}\r
\r
- #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
-\r
- /* Prepare device for proper Hibernate mode entry */\r
CyPmHibSaveSet();\r
\r
\r
- #if(!CY_PSOC5A)\r
-\r
- /* Save and enable only wakeup on PICU */\r
- cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG;\r
- CY_PM_WAKEUP_CFG0_REG = CY_PM_WAKEUP_PICU;\r
+ /* Save and enable only wakeup on PICU */\r
+ cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG;\r
+ CY_PM_WAKEUP_CFG0_REG = CY_PM_WAKEUP_PICU;\r
\r
- cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG;\r
- CY_PM_WAKEUP_CFG1_REG = 0x00u;\r
+ cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG;\r
+ CY_PM_WAKEUP_CFG1_REG = 0x00u;\r
\r
- cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG;\r
- CY_PM_WAKEUP_CFG2_REG = 0x00u;\r
-\r
- #endif /* (!CY_PSOC5A) */\r
+ cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG;\r
+ CY_PM_WAKEUP_CFG2_REG = 0x00u;\r
\r
\r
/* Last moment IMO frequency change */\r
/* Execute WFI instruction (for ARM-based devices only) */\r
CY_PM_WFI;\r
\r
+\r
/* Point of return from Hibernate mode */\r
\r
\r
/* Restore device for proper Hibernate mode exit*/\r
CyPmHibRestore();\r
\r
-\r
- #if(!CY_PSOC5A)\r
-\r
- /* Restore current wake up configuration */\r
- CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0;\r
- CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1;\r
- CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2;\r
-\r
- #endif /* (!CY_PSOC5A) */\r
+ /* Restore current wake up configuration */\r
+ CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0;\r
+ CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1;\r
+ CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2;\r
\r
/* Restore global interrupt enable state */\r
CyExitCriticalSection(interruptState);\r
* Summary:\r
* Prepare device for proper Hibernate low power mode entry:\r
* - Disables I2C backup regulator\r
-* - Save state of I2C backup regulator (PSoC 5)\r
-* - Saves ILO power down mode state and enable it (all but PSoC 5)\r
-* - Saves state of 1 kHz and 100 kHz ILO and disable them (all but PSoC 5)\r
-* - Disables sleep regulator and shorts vccd to vpwrsleep (all but PSoC 5)\r
+* - Saves ILO power down mode state and enable it\r
+* - Saves state of 1 kHz and 100 kHz ILO and disable them\r
+* - Disables sleep regulator and shorts vccd to vpwrsleep\r
* - Save LVI/HVI configuration and disable them - CyPmHviLviSaveDisable()\r
* - CyPmHibSlpSaveSet() function is called\r
*\r
* to restore I2C registers based on this. If this regulator will be\r
* disabled and then enabled, I2C API will suppose that I2C block\r
* registers preserved their values, while this is not true. So, the\r
- * backup regulator is disabled. And its value is restored only for\r
- * and PSoC 5 devices. The I2C sleep APIs is responsible for restoration.\r
+ * backup regulator is disabled. The I2C sleep APIs is responsible for\r
+ * restoration.\r
***********************************************************************/\r
\r
- #if(CY_PSOC5A)\r
-\r
- cyPmBackup.i2cRegBackup = CY_PM_ENABLED;\r
-\r
- #endif /* (CY_PSOC5A) */\r
-\r
/* Disable I2C backup register */\r
CY_PM_PWRSYS_CR1_REG &= ((uint8)(~CY_PM_PWRSYS_CR1_I2CREG_BACKUP));\r
}\r
- else\r
- {\r
- #if(CY_PSOC5A)\r
-\r
- /* Save disabled state of the I2C backup regulator */\r
- cyPmBackup.i2cRegBackup = CY_PM_DISABLED;\r
-\r
- #endif /* (CY_PSOC5A) */\r
- }\r
-\r
-\r
- #if(!CY_PSOC5A)\r
-\r
- /* Save current ILO power mode and ensure low power mode */\r
- cyPmBackup.iloPowerMode = CyILO_SetPowerMode(CY_PM_POWERDOWN_MODE);\r
-\r
- /* Save current 1kHz ILO enable state. Disabled automatically. */\r
- cyPmBackup.ilo1kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_1K)) ?\r
- CY_PM_DISABLED : CY_PM_ENABLED;\r
\r
- /* Save current 100kHz ILO enable state. Disabled automatically. */\r
- cyPmBackup.ilo100kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_100K)) ?\r
- CY_PM_DISABLED : CY_PM_ENABLED;\r
\r
+ /* Save current ILO power mode and ensure low power mode */\r
+ cyPmBackup.iloPowerMode = CyILO_SetPowerMode(CY_PM_POWERDOWN_MODE);\r
\r
- /* Disable the sleep regulator and shorts vccd to vpwrsleep */\r
- if(0u == (CY_PM_PWRSYS_SLP_TR_REG & CY_PM_PWRSYS_SLP_TR_BYPASS))\r
- {\r
- /* Save current bypass state */\r
- cyPmBackup.slpTrBypass = CY_PM_DISABLED;\r
- CY_PM_PWRSYS_SLP_TR_REG |= CY_PM_PWRSYS_SLP_TR_BYPASS;\r
- }\r
- else\r
- {\r
- cyPmBackup.slpTrBypass = CY_PM_ENABLED;\r
- }\r
+ /* Save current 1kHz ILO enable state. Disabled automatically. */\r
+ cyPmBackup.ilo1kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_1K)) ?\r
+ CY_PM_DISABLED : CY_PM_ENABLED;\r
\r
- /* LPCOMPs are always enabled (even when BOTH ext_vccd=1 and ext_vcca=1)*/\r
+ /* Save current 100kHz ILO enable state. Disabled automatically. */\r
+ cyPmBackup.ilo100kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_100K)) ?\r
+ CY_PM_DISABLED : CY_PM_ENABLED;\r
\r
- #endif /* (!CY_PSOC5A) */\r
\r
+ /* Disable the sleep regulator and shorts vccd to vpwrsleep */\r
+ if(0u == (CY_PM_PWRSYS_SLP_TR_REG & CY_PM_PWRSYS_SLP_TR_BYPASS))\r
+ {\r
+ /* Save current bypass state */\r
+ cyPmBackup.slpTrBypass = CY_PM_DISABLED;\r
+ CY_PM_PWRSYS_SLP_TR_REG |= CY_PM_PWRSYS_SLP_TR_BYPASS;\r
+ }\r
+ else\r
+ {\r
+ cyPmBackup.slpTrBypass = CY_PM_ENABLED;\r
+ }\r
\r
- /* Device is PSoC 5 and the revision is ES1 or earlier. */\r
- #if(CY_PSOC5A)\r
-\r
- /* Disable all the PICU interrupts */\r
- CyPmDisablePicuInterrupts();\r
-\r
- #endif /* (CY_PSOC5A) */\r
+ /* LPCOMPs are always enabled (even when BOTH ext_vccd=1 and ext_vcca=1)*/\r
\r
\r
/***************************************************************************\r
/***************************************************************************\r
* Save and set power mode wakeup trim registers\r
***************************************************************************/\r
- #if(CY_PSOC3 || CY_PSOC5LP)\r
-\r
- cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG;\r
- cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG;\r
-\r
- CY_PM_PWRSYS_WAKE_TR0_REG = CY_PM_PWRSYS_WAKE_TR0;\r
- CY_PM_PWRSYS_WAKE_TR1_REG = CY_PM_PWRSYS_WAKE_TR1;\r
-\r
- #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+ cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG;\r
+ cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG;\r
\r
+ CY_PM_PWRSYS_WAKE_TR0_REG = CY_PM_PWRSYS_WAKE_TR0;\r
+ CY_PM_PWRSYS_WAKE_TR1_REG = CY_PM_PWRSYS_WAKE_TR1;\r
}\r
\r
\r
* Restore device for proper Hibernate mode exit:\r
* - Restore LVI/HVI configuration - call CyPmHviLviRestore()\r
* - CyPmHibSlpSaveRestore() function is called\r
-* - Restores state of I2C backup regulator (PSoC 5)\r
-* - Restores ILO power down mode state and enable it (all but PSoC 5)\r
-* - Restores state of 1 kHz and 100 kHz ILO and disable them (all but PSoC 5)\r
-* - Restores sleep regulator settings (all but PSoC 5)\r
+* - Restores ILO power down mode state and enable it\r
+* - Restores state of 1 kHz and 100 kHz ILO and disable them\r
+* - Restores sleep regulator settings\r
*\r
* Parameters:\r
* None\r
/* Restore the same configuration for Hibernate and Sleep modes */\r
CyPmHibSlpRestore();\r
\r
- #if(CY_PSOC5A)\r
-\r
- /* Restore I2C backup regulator configuration */\r
- if(CY_PM_ENABLED == cyPmBackup.i2cRegBackup)\r
- {\r
- /* Enable I2C backup regulator state */\r
- CY_PM_PWRSYS_CR1_REG |= CY_PM_PWRSYS_CR1_I2CREG_BACKUP;\r
- }\r
-\r
- #endif /* (CY_PSOC5A) */\r
-\r
-\r
- #if(!CY_PSOC5A)\r
-\r
- /* Restore 1kHz ILO enable state */\r
- if(CY_PM_ENABLED == cyPmBackup.ilo1kEnable)\r
- {\r
- /* Enable 1kHz ILO */\r
- CyILO_Start1K();\r
- }\r
-\r
- /* Restore 100kHz ILO enable state */\r
- if(CY_PM_ENABLED == cyPmBackup.ilo100kEnable)\r
- {\r
- /* Enable 100kHz ILO */\r
- CyILO_Start100K();\r
- }\r
+ /* Restore 1kHz ILO enable state */\r
+ if(CY_PM_ENABLED == cyPmBackup.ilo1kEnable)\r
+ {\r
+ /* Enable 1kHz ILO */\r
+ CyILO_Start1K();\r
+ }\r
\r
- /* Restore ILO power mode */\r
- (void) CyILO_SetPowerMode(cyPmBackup.iloPowerMode);\r
+ /* Restore 100kHz ILO enable state */\r
+ if(CY_PM_ENABLED == cyPmBackup.ilo100kEnable)\r
+ {\r
+ /* Enable 100kHz ILO */\r
+ CyILO_Start100K();\r
+ }\r
\r
+ /* Restore ILO power mode */\r
+ (void) CyILO_SetPowerMode(cyPmBackup.iloPowerMode);\r
\r
- if(CY_PM_DISABLED == cyPmBackup.slpTrBypass)\r
- {\r
- /* Enable the sleep regulator */\r
- CY_PM_PWRSYS_SLP_TR_REG &= ((uint8)(~CY_PM_PWRSYS_SLP_TR_BYPASS));\r
- }\r
\r
- #endif /* (!CY_PSOC5A) */\r
+ if(CY_PM_DISABLED == cyPmBackup.slpTrBypass)\r
+ {\r
+ /* Enable the sleep regulator */\r
+ CY_PM_PWRSYS_SLP_TR_REG &= ((uint8)(~CY_PM_PWRSYS_SLP_TR_BYPASS));\r
+ }\r
\r
\r
/***************************************************************************\r
* Restore power mode wakeup trim registers\r
***************************************************************************/\r
- #if(CY_PSOC3 || CY_PSOC5LP)\r
-\r
- CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0;\r
- CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1;\r
-\r
- #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+ CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0;\r
+ CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1;\r
}\r
\r
\r
}\r
\r
\r
-#if(CY_PSOC5A)\r
-\r
- /*******************************************************************************\r
- * Function Name: CyPmSavePicuInterrupts\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Saves PICU interrupt type registers to the backup structure.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- * Reentrant:\r
- * No\r
- *\r
- *******************************************************************************/\r
- static void CyPmSavePicuInterrupts(void) \r
- {\r
- /* Save all the PICU interrupt type */\r
- (void) memcpy((void *) &cyPmBackup.picuIntType[0u],\r
- (void *) CY_PM_PICU_0_6_INT_BASE,\r
- CY_PM_PICU_0_6_INT_SIZE);\r
-\r
- (void) memcpy((void *) &cyPmBackup.picuIntType[CY_PM_PICU_0_6_INT_SIZE],\r
- (void *) CY_PM_PICU_12_INT_BASE,\r
- CY_PM_PICU_12_INT_SIZE);\r
-\r
- (void) memcpy((void *) &cyPmBackup.picuIntType[CY_PM_PICU_0_6_INT_SIZE + CY_PM_PICU_12_INT_SIZE],\r
- (void *) CY_PM_PICU_15_INT_BASE,\r
- CY_PM_PICU_15_INT_SIZE);\r
-\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: CyPmDisablePicuInterrupts\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Disableds PICU interrupts.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- *******************************************************************************/\r
- static void CyPmDisablePicuInterrupts(void) \r
- {\r
- /* Disable all the PICU interrupts */\r
- (void) memset((void *) CY_PM_PICU_0_6_INT_BASE, 0, CY_PM_PICU_0_6_INT_SIZE);\r
- (void) memset((void *) CY_PM_PICU_12_INT_BASE, 0, CY_PM_PICU_12_INT_SIZE );\r
- (void) memset((void *) CY_PM_PICU_15_INT_BASE, 0, CY_PM_PICU_15_INT_SIZE );\r
- }\r
-\r
-\r
- /*******************************************************************************\r
- * Function Name: CyPmRestorePicuInterrupts\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Restores PICU interrupt type registers from the backup structure.\r
- *\r
- * Parameters:\r
- * None\r
- *\r
- * Return:\r
- * None\r
- *\r
- *******************************************************************************/\r
- static void CyPmRestorePicuInterrupts(void) \r
- {\r
- /* Save all the PICU interrupt type */\r
- (void) memcpy((void *) CY_PM_PICU_0_6_INT_BASE,\r
- (void *) &cyPmBackup.picuIntType[0u],\r
- CY_PM_PICU_0_6_INT_SIZE);\r
-\r
- (void) memcpy((void *) CY_PM_PICU_12_INT_BASE,\r
- (void *) &cyPmBackup.picuIntType[CY_PM_PICU_0_6_INT_SIZE],\r
- CY_PM_PICU_12_INT_SIZE);\r
-\r
- (void) memcpy((void *) CY_PM_PICU_15_INT_BASE,\r
- (void *) &cyPmBackup.picuIntType[CY_PM_PICU_0_6_INT_SIZE + CY_PM_PICU_12_INT_SIZE],\r
- CY_PM_PICU_15_INT_SIZE);\r
-\r
- }\r
-\r
-#endif /* (CY_PSOC5A) */\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: CyPmSlpSaveSet\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Prepare device for proper Sleep low power mode entry:\r
-* - Prepare CTW for Sleep mode entry (PSoC 5)\r
-* * Save timewheels configuration\r
-* * Disable FTW and 1PPS (enable and interrupt)\r
-* * Reset CTW\r
-* * Save and disable PICU interrupts\r
-* * Save and disable PRES-A and PRES-D\r
-* - Save and disable LVI/HVI configuration (PSoC 5)\r
-* - Save and set to max buzz interval (PSoC 5)\r
-* - CyPmHibSlpSaveSet() function is called\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
-* Reentrant:\r
-* No\r
-*\r
-*******************************************************************************/\r
-static void CyPmSlpSaveSet(void) \r
-{\r
- #if(CY_PSOC5A)\r
-\r
- /* Preserve the Timewheel Configuration Register 2 */\r
- cyPmBackup.pmTwCfg2 = CY_PM_TW_CFG2_REG;\r
-\r
- /* Clear the enable and interrupt enables for the FTW and ONEPPS */\r
- CY_PM_TW_CFG2_REG &= ((uint8)(~(CY_PM_FTW_IE | CY_PM_FTW_EN | CY_PM_1PPS_EN | CY_PM_1PPS_IE)));\r
-\r
- /* Reset free-running CTW counter to 0 and held it there */\r
- CY_PM_WDT_CFG_REG |= CY_PM_WDT_CFG_CTW_RESET;\r
-\r
- /* Exit CTW counter reset state */\r
- CY_PM_WDT_CFG_REG &= ((uint8)(~CY_PM_WDT_CFG_CTW_RESET));\r
-\r
- /* Save and disable PICU interrupts */\r
- CyPmSavePicuInterrupts();\r
- CyPmDisablePicuInterrupts();\r
-\r
- /* Save and disable PRES-A and PRES-D */\r
- cyPmBackup.pres1 = CY_PM_RESET_CR1_REG & CY_PM_RESET_CR1_DIS_PRES1;\r
- cyPmBackup.pres2 = CY_PM_RESET_CR3_REG & CY_PM_RESET_CR3_DIS_PRES2;\r
- CY_PM_RESET_CR1_REG &= ((uint8)(~CY_PM_RESET_CR1_DIS_PRES1));\r
- CY_PM_RESET_CR3_REG &= ((uint8)(~CY_PM_RESET_CR3_DIS_PRES2));\r
-\r
- #endif /* (CY_PSOC5A) */\r
-\r
-\r
- #if(CY_PSOC5A)\r
-\r
- /***************************************************************************\r
- * LVI/HVI must be disabled as it doesn't work during buzzing.\r
- *\r
- * Using hardware buzz in conjunction with other device wakeup sources\r
- * can cause the device to lockup, halting further code execution. The\r
- * hardware buzz provides power supply supervising capability in sleep.\r
- * It is enabled by default and there is no way to disable it. So the buzz\r
- * interval is set to maximum (512 ms). The CTW must be configured to wake up\r
- * at a rate less than hardware buzz interval.\r
- ***************************************************************************/\r
-\r
- /* Save and disable LVI/HVI */\r
- CyPmHviLviSaveDisable();\r
-\r
- /* Save buzz trim value */\r
- cyPmBackup.buzzSleepTrim = CY_PM_PWRSYS_BUZZ_TR_REG & ((uint8)(~CY_PM_PWRSYS_BUZZ_TR_MASK));\r
-\r
- /* Set buzz interval to maximum */\r
- CY_PM_PWRSYS_BUZZ_TR_REG = CY_PM_PWRSYS_BUZZ_TR_512_TICKS |\r
- (CY_PM_PWRSYS_BUZZ_TR_REG & CY_PM_PWRSYS_BUZZ_TR_MASK);\r
-\r
- #endif /* (CY_PSOC5A) */\r
-\r
-\r
- /* Apply configuration that are same for Sleep and Hibernate */\r
- CyPmHibSlpSaveSet();\r
-}\r
-\r
-\r
-/*******************************************************************************\r
-* Function Name: CyPmSlpRestore\r
-********************************************************************************\r
-*\r
-* Summary:\r
-* Restore device for proper Sleep mode exit:\r
-* - Restore timewheel configuration (PSoC 5)\r
-* - Restore PRES-A and PRES-D (PSoC 5)\r
-* - Restore PICU interrupts (PSoC 5)\r
-* - Restore buzz sleep trim value (PSoC 5)\r
-* - Call to CyPmHibSlpSaveRestore()\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Return:\r
-* None\r
-*\r
-*******************************************************************************/\r
-static void CyPmSlpRestore(void) \r
-{\r
- #if(CY_PSOC5A)\r
-\r
- /* Restore the Timewheel Configuration Register 2 */\r
- CY_PM_TW_CFG2_REG = cyPmBackup.pmTwCfg2;\r
-\r
- /* Restore PICU interrupts */\r
- CyPmRestorePicuInterrupts();\r
-\r
- /* Restore PRES-A and PRES-D (assumed they were disabled) */\r
- CY_PM_RESET_CR1_REG |= cyPmBackup.pres1;\r
- CY_PM_RESET_CR3_REG |= cyPmBackup.pres2;\r
-\r
- #endif /* (CY_PSOC5A) */\r
-\r
-\r
- #if(CY_PSOC5A)\r
-\r
- /* Restore LVI/HVI configuration */\r
- CyPmHviLviRestore();\r
-\r
- /* Restore buzz sleep trim value */\r
- CY_PM_PWRSYS_BUZZ_TR_REG = cyPmBackup.buzzSleepTrim |\r
- (CY_PM_PWRSYS_BUZZ_TR_REG & CY_PM_PWRSYS_BUZZ_TR_MASK);\r
-\r
- #endif /* (CY_PSOC5A) */\r
-\r
-\r
- /* Restore configuration that are same for Sleep and Hibernate */\r
- CyPmHibSlpRestore();\r
-}\r
-\r
-\r
/*******************************************************************************\r
* Function Name: CyPmHibSlpSaveSet\r
********************************************************************************\r
*******************************************************************************/\r
static void CyPmHibSlpSaveSet(void) \r
{\r
- #if(CY_PSOC5A)\r
-\r
- /* Save CMP routing registers */\r
- cyPmBackup.cmpData[0u] = CY_GET_REG8(CYREG_CMP0_SW0);\r
- cyPmBackup.cmpData[1u] = CY_GET_REG8(CYREG_CMP0_SW2);\r
- cyPmBackup.cmpData[2u] = CY_GET_REG8(CYREG_CMP0_SW3);\r
- cyPmBackup.cmpData[3u] = CY_GET_REG8(CYREG_CMP0_SW4);\r
- cyPmBackup.cmpData[4u] = CY_GET_REG8(CYREG_CMP0_SW6);\r
-\r
- cyPmBackup.cmpData[5u] = CY_GET_REG8(CYREG_CMP1_SW0);\r
- cyPmBackup.cmpData[6u] = CY_GET_REG8(CYREG_CMP1_SW2);\r
- cyPmBackup.cmpData[7u] = CY_GET_REG8(CYREG_CMP1_SW3);\r
- cyPmBackup.cmpData[8u] = CY_GET_REG8(CYREG_CMP1_SW4);\r
- cyPmBackup.cmpData[9u] = CY_GET_REG8(CYREG_CMP1_SW6);\r
-\r
- cyPmBackup.cmpData[10u] = CY_GET_REG8(CYREG_CMP2_SW0);\r
- cyPmBackup.cmpData[11u] = CY_GET_REG8(CYREG_CMP2_SW2);\r
- cyPmBackup.cmpData[12u] = CY_GET_REG8(CYREG_CMP2_SW3);\r
- cyPmBackup.cmpData[13u] = CY_GET_REG8(CYREG_CMP2_SW4);\r
- cyPmBackup.cmpData[14u] = CY_GET_REG8(CYREG_CMP2_SW6);\r
-\r
- cyPmBackup.cmpData[15u] = CY_GET_REG8(CYREG_CMP3_SW0);\r
- cyPmBackup.cmpData[16u] = CY_GET_REG8(CYREG_CMP3_SW2);\r
- cyPmBackup.cmpData[17u] = CY_GET_REG8(CYREG_CMP3_SW3);\r
- cyPmBackup.cmpData[18u] = CY_GET_REG8(CYREG_CMP3_SW4);\r
- cyPmBackup.cmpData[19u] = CY_GET_REG8(CYREG_CMP3_SW6);\r
-\r
-\r
- /* Clear CMP routing registers */\r
- CY_SET_REG8(CYREG_CMP0_SW0 , 0u);\r
- CY_SET_REG8(CYREG_CMP0_SW2 , 0u);\r
- CY_SET_REG8(CYREG_CMP0_SW3 , 0u);\r
- CY_SET_REG8(CYREG_CMP0_SW4 , 0u);\r
- CY_SET_REG8(CYREG_CMP0_SW6 , 0u);\r
-\r
- CY_SET_REG8(CYREG_CMP1_SW0 , 0u);\r
- CY_SET_REG8(CYREG_CMP1_SW2 , 0u);\r
- CY_SET_REG8(CYREG_CMP1_SW3 , 0u);\r
- CY_SET_REG8(CYREG_CMP1_SW4 , 0u);\r
- CY_SET_REG8(CYREG_CMP1_SW6 , 0u);\r
-\r
- CY_SET_REG8(CYREG_CMP2_SW0 , 0u);\r
- CY_SET_REG8(CYREG_CMP2_SW2 , 0u);\r
- CY_SET_REG8(CYREG_CMP2_SW3 , 0u);\r
- CY_SET_REG8(CYREG_CMP2_SW4 , 0u);\r
- CY_SET_REG8(CYREG_CMP2_SW6 , 0u);\r
-\r
- CY_SET_REG8(CYREG_CMP3_SW0 , 0u);\r
- CY_SET_REG8(CYREG_CMP3_SW2 , 0u);\r
- CY_SET_REG8(CYREG_CMP3_SW3 , 0u);\r
- CY_SET_REG8(CYREG_CMP3_SW4 , 0u);\r
- CY_SET_REG8(CYREG_CMP3_SW6 , 0u);\r
-\r
-\r
- /* Save DAC routing registers */\r
- cyPmBackup.dacData[0u] = CY_GET_REG8(CYREG_DAC0_SW0);\r
- cyPmBackup.dacData[1u] = CY_GET_REG8(CYREG_DAC0_SW2);\r
- cyPmBackup.dacData[2u] = CY_GET_REG8(CYREG_DAC0_SW3);\r
- cyPmBackup.dacData[3u] = CY_GET_REG8(CYREG_DAC0_SW4);\r
-\r
- cyPmBackup.dacData[4u] = CY_GET_REG8(CYREG_DAC1_SW0);\r
- cyPmBackup.dacData[5u] = CY_GET_REG8(CYREG_DAC1_SW2);\r
- cyPmBackup.dacData[6u] = CY_GET_REG8(CYREG_DAC1_SW3);\r
- cyPmBackup.dacData[7u] = CY_GET_REG8(CYREG_DAC1_SW4);\r
-\r
- cyPmBackup.dacData[8u] = CY_GET_REG8(CYREG_DAC2_SW0);\r
- cyPmBackup.dacData[9u] = CY_GET_REG8(CYREG_DAC2_SW2);\r
- cyPmBackup.dacData[10u] = CY_GET_REG8(CYREG_DAC2_SW3);\r
- cyPmBackup.dacData[11u] = CY_GET_REG8(CYREG_DAC2_SW4);\r
-\r
- cyPmBackup.dacData[12u] = CY_GET_REG8(CYREG_DAC3_SW0);\r
- cyPmBackup.dacData[13u] = CY_GET_REG8(CYREG_DAC3_SW2);\r
- cyPmBackup.dacData[14u] = CY_GET_REG8(CYREG_DAC3_SW3);\r
- cyPmBackup.dacData[15u] = CY_GET_REG8(CYREG_DAC3_SW4);\r
-\r
- /* Clear DAC routing registers */\r
- CY_SET_REG8(CYREG_DAC0_SW0 , 0u);\r
- CY_SET_REG8(CYREG_DAC0_SW2 , 0u);\r
- CY_SET_REG8(CYREG_DAC0_SW3 , 0u);\r
- CY_SET_REG8(CYREG_DAC0_SW4 , 0u);\r
-\r
- CY_SET_REG8(CYREG_DAC1_SW0 , 0u);\r
- CY_SET_REG8(CYREG_DAC1_SW2 , 0u);\r
- CY_SET_REG8(CYREG_DAC1_SW3 , 0u);\r
- CY_SET_REG8(CYREG_DAC1_SW4 , 0u);\r
-\r
- CY_SET_REG8(CYREG_DAC2_SW0 , 0u);\r
- CY_SET_REG8(CYREG_DAC2_SW2 , 0u);\r
- CY_SET_REG8(CYREG_DAC2_SW3 , 0u);\r
- CY_SET_REG8(CYREG_DAC2_SW4 , 0u);\r
-\r
- CY_SET_REG8(CYREG_DAC3_SW0 , 0u);\r
- CY_SET_REG8(CYREG_DAC3_SW2 , 0u);\r
- CY_SET_REG8(CYREG_DAC3_SW3 , 0u);\r
- CY_SET_REG8(CYREG_DAC3_SW4 , 0u);\r
-\r
-\r
- /* Save DSM routing registers */\r
- cyPmBackup.dsmData[0u] = CY_GET_REG8(CYREG_DSM0_SW0);\r
- cyPmBackup.dsmData[1u] = CY_GET_REG8(CYREG_DSM0_SW2);\r
- cyPmBackup.dsmData[2u] = CY_GET_REG8(CYREG_DSM0_SW3);\r
- cyPmBackup.dsmData[3u] = CY_GET_REG8(CYREG_DSM0_SW4);\r
- cyPmBackup.dsmData[4u] = CY_GET_REG8(CYREG_DSM0_SW6);\r
-\r
- /* Clear DSM routing registers */\r
- CY_SET_REG8(CYREG_DSM0_SW0 , 0u);\r
- CY_SET_REG8(CYREG_DSM0_SW2 , 0u);\r
- CY_SET_REG8(CYREG_DSM0_SW3 , 0u);\r
- CY_SET_REG8(CYREG_DSM0_SW4 , 0u);\r
- CY_SET_REG8(CYREG_DSM0_SW6 , 0u);\r
-\r
-\r
- /* Save SAR routing registers */\r
- cyPmBackup.sarData[0u] = CY_GET_REG8(CYREG_SAR0_SW0);\r
- cyPmBackup.sarData[1u] = CY_GET_REG8(CYREG_SAR0_SW2);\r
- cyPmBackup.sarData[2u] = CY_GET_REG8(CYREG_SAR0_SW3);\r
- cyPmBackup.sarData[3u] = CY_GET_REG8(CYREG_SAR0_SW4);\r
- cyPmBackup.sarData[4u] = CY_GET_REG8(CYREG_SAR0_SW6);\r
-\r
- cyPmBackup.sarData[5u] = CY_GET_REG8(CYREG_SAR1_SW0);\r
- cyPmBackup.sarData[6u] = CY_GET_REG8(CYREG_SAR1_SW2);\r
- cyPmBackup.sarData[7u] = CY_GET_REG8(CYREG_SAR1_SW3);\r
- cyPmBackup.sarData[8u] = CY_GET_REG8(CYREG_SAR1_SW4);\r
- cyPmBackup.sarData[9u] = CY_GET_REG8(CYREG_SAR1_SW6);\r
-\r
-\r
- /* Clear SAR routing registers */\r
- CY_SET_REG8(CYREG_SAR0_SW0 , 0u);\r
- CY_SET_REG8(CYREG_SAR0_SW2 , 0u);\r
- CY_SET_REG8(CYREG_SAR0_SW3 , 0u);\r
- CY_SET_REG8(CYREG_SAR0_SW4 , 0u);\r
- CY_SET_REG8(CYREG_SAR0_SW6 , 0u);\r
-\r
- CY_SET_REG8(CYREG_SAR1_SW0 , 0u);\r
- CY_SET_REG8(CYREG_SAR1_SW2 , 0u);\r
- CY_SET_REG8(CYREG_SAR1_SW3 , 0u);\r
- CY_SET_REG8(CYREG_SAR1_SW4 , 0u);\r
- CY_SET_REG8(CYREG_SAR1_SW6 , 0u);\r
-\r
- #endif /* (CY_PSOC5A) */\r
-\r
-\r
- #if(CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP)\r
-\r
- /* Save SC/CT routing registers */\r
- cyPmBackup.scctData[0u] = CY_GET_REG8(CYREG_SC0_SW0 );\r
- cyPmBackup.scctData[1u] = CY_GET_REG8(CYREG_SC0_SW2 );\r
- cyPmBackup.scctData[2u] = CY_GET_REG8(CYREG_SC0_SW3 );\r
- cyPmBackup.scctData[3u] = CY_GET_REG8(CYREG_SC0_SW4 );\r
- cyPmBackup.scctData[4u] = CY_GET_REG8(CYREG_SC0_SW6 );\r
- cyPmBackup.scctData[5u] = CY_GET_REG8(CYREG_SC0_SW8 );\r
- cyPmBackup.scctData[6u] = CY_GET_REG8(CYREG_SC0_SW10);\r
-\r
- cyPmBackup.scctData[7u] = CY_GET_REG8(CYREG_SC1_SW0 );\r
- cyPmBackup.scctData[8u] = CY_GET_REG8(CYREG_SC1_SW2 );\r
- cyPmBackup.scctData[9u] = CY_GET_REG8(CYREG_SC1_SW3 );\r
- cyPmBackup.scctData[10u] = CY_GET_REG8(CYREG_SC1_SW4 );\r
- cyPmBackup.scctData[11u] = CY_GET_REG8(CYREG_SC1_SW6 );\r
- cyPmBackup.scctData[12u] = CY_GET_REG8(CYREG_SC1_SW8 );\r
- cyPmBackup.scctData[13u] = CY_GET_REG8(CYREG_SC1_SW10);\r
-\r
- cyPmBackup.scctData[14u] = CY_GET_REG8(CYREG_SC2_SW0 );\r
- cyPmBackup.scctData[15u] = CY_GET_REG8(CYREG_SC2_SW2 );\r
- cyPmBackup.scctData[16u] = CY_GET_REG8(CYREG_SC2_SW3 );\r
- cyPmBackup.scctData[17u] = CY_GET_REG8(CYREG_SC2_SW4 );\r
- cyPmBackup.scctData[18u] = CY_GET_REG8(CYREG_SC2_SW6 );\r
- cyPmBackup.scctData[19u] = CY_GET_REG8(CYREG_SC2_SW8 );\r
- cyPmBackup.scctData[20u] = CY_GET_REG8(CYREG_SC2_SW10);\r
-\r
- cyPmBackup.scctData[21u] = CY_GET_REG8(CYREG_SC3_SW0 );\r
- cyPmBackup.scctData[22u] = CY_GET_REG8(CYREG_SC3_SW2 );\r
- cyPmBackup.scctData[23u] = CY_GET_REG8(CYREG_SC3_SW3 );\r
- cyPmBackup.scctData[24u] = CY_GET_REG8(CYREG_SC3_SW4 );\r
- cyPmBackup.scctData[25u] = CY_GET_REG8(CYREG_SC3_SW6 );\r
- cyPmBackup.scctData[26u] = CY_GET_REG8(CYREG_SC3_SW8 );\r
- cyPmBackup.scctData[27u] = CY_GET_REG8(CYREG_SC3_SW10);\r
-\r
- CY_SET_REG8(CYREG_SC0_SW0 , 0u);\r
- CY_SET_REG8(CYREG_SC0_SW2 , 0u);\r
- CY_SET_REG8(CYREG_SC0_SW3 , 0u);\r
- CY_SET_REG8(CYREG_SC0_SW4 , 0u);\r
- CY_SET_REG8(CYREG_SC0_SW6 , 0u);\r
- CY_SET_REG8(CYREG_SC0_SW8 , 0u);\r
- CY_SET_REG8(CYREG_SC0_SW10, 0u);\r
-\r
- CY_SET_REG8(CYREG_SC1_SW0 , 0u);\r
- CY_SET_REG8(CYREG_SC1_SW2 , 0u);\r
- CY_SET_REG8(CYREG_SC1_SW3 , 0u);\r
- CY_SET_REG8(CYREG_SC1_SW4 , 0u);\r
- CY_SET_REG8(CYREG_SC1_SW6 , 0u);\r
- CY_SET_REG8(CYREG_SC1_SW8 , 0u);\r
- CY_SET_REG8(CYREG_SC1_SW10, 0u);\r
-\r
- CY_SET_REG8(CYREG_SC2_SW0 , 0u);\r
- CY_SET_REG8(CYREG_SC2_SW2 , 0u);\r
- CY_SET_REG8(CYREG_SC2_SW3 , 0u);\r
- CY_SET_REG8(CYREG_SC2_SW4 , 0u);\r
- CY_SET_REG8(CYREG_SC2_SW6 , 0u);\r
- CY_SET_REG8(CYREG_SC2_SW8 , 0u);\r
- CY_SET_REG8(CYREG_SC2_SW10, 0u);\r
-\r
- CY_SET_REG8(CYREG_SC3_SW0 , 0u);\r
- CY_SET_REG8(CYREG_SC3_SW2 , 0u);\r
- CY_SET_REG8(CYREG_SC3_SW3 , 0u);\r
- CY_SET_REG8(CYREG_SC3_SW4 , 0u);\r
- CY_SET_REG8(CYREG_SC3_SW6 , 0u);\r
- CY_SET_REG8(CYREG_SC3_SW8 , 0u);\r
- CY_SET_REG8(CYREG_SC3_SW10, 0u);\r
-\r
- #endif /* (CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP) */\r
+ /* Save SC/CT routing registers */\r
+ cyPmBackup.scctData[0u] = CY_GET_REG8(CYREG_SC0_SW0 );\r
+ cyPmBackup.scctData[1u] = CY_GET_REG8(CYREG_SC0_SW2 );\r
+ cyPmBackup.scctData[2u] = CY_GET_REG8(CYREG_SC0_SW3 );\r
+ cyPmBackup.scctData[3u] = CY_GET_REG8(CYREG_SC0_SW4 );\r
+ cyPmBackup.scctData[4u] = CY_GET_REG8(CYREG_SC0_SW6 );\r
+ cyPmBackup.scctData[5u] = CY_GET_REG8(CYREG_SC0_SW8 );\r
+ cyPmBackup.scctData[6u] = CY_GET_REG8(CYREG_SC0_SW10);\r
+\r
+ cyPmBackup.scctData[7u] = CY_GET_REG8(CYREG_SC1_SW0 );\r
+ cyPmBackup.scctData[8u] = CY_GET_REG8(CYREG_SC1_SW2 );\r
+ cyPmBackup.scctData[9u] = CY_GET_REG8(CYREG_SC1_SW3 );\r
+ cyPmBackup.scctData[10u] = CY_GET_REG8(CYREG_SC1_SW4 );\r
+ cyPmBackup.scctData[11u] = CY_GET_REG8(CYREG_SC1_SW6 );\r
+ cyPmBackup.scctData[12u] = CY_GET_REG8(CYREG_SC1_SW8 );\r
+ cyPmBackup.scctData[13u] = CY_GET_REG8(CYREG_SC1_SW10);\r
+\r
+ cyPmBackup.scctData[14u] = CY_GET_REG8(CYREG_SC2_SW0 );\r
+ cyPmBackup.scctData[15u] = CY_GET_REG8(CYREG_SC2_SW2 );\r
+ cyPmBackup.scctData[16u] = CY_GET_REG8(CYREG_SC2_SW3 );\r
+ cyPmBackup.scctData[17u] = CY_GET_REG8(CYREG_SC2_SW4 );\r
+ cyPmBackup.scctData[18u] = CY_GET_REG8(CYREG_SC2_SW6 );\r
+ cyPmBackup.scctData[19u] = CY_GET_REG8(CYREG_SC2_SW8 );\r
+ cyPmBackup.scctData[20u] = CY_GET_REG8(CYREG_SC2_SW10);\r
+\r
+ cyPmBackup.scctData[21u] = CY_GET_REG8(CYREG_SC3_SW0 );\r
+ cyPmBackup.scctData[22u] = CY_GET_REG8(CYREG_SC3_SW2 );\r
+ cyPmBackup.scctData[23u] = CY_GET_REG8(CYREG_SC3_SW3 );\r
+ cyPmBackup.scctData[24u] = CY_GET_REG8(CYREG_SC3_SW4 );\r
+ cyPmBackup.scctData[25u] = CY_GET_REG8(CYREG_SC3_SW6 );\r
+ cyPmBackup.scctData[26u] = CY_GET_REG8(CYREG_SC3_SW8 );\r
+ cyPmBackup.scctData[27u] = CY_GET_REG8(CYREG_SC3_SW10);\r
+\r
+ CY_SET_REG8(CYREG_SC0_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_SC0_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_SC0_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_SC0_SW4 , 0u);\r
+ CY_SET_REG8(CYREG_SC0_SW6 , 0u);\r
+ CY_SET_REG8(CYREG_SC0_SW8 , 0u);\r
+ CY_SET_REG8(CYREG_SC0_SW10, 0u);\r
+\r
+ CY_SET_REG8(CYREG_SC1_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_SC1_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_SC1_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_SC1_SW4 , 0u);\r
+ CY_SET_REG8(CYREG_SC1_SW6 , 0u);\r
+ CY_SET_REG8(CYREG_SC1_SW8 , 0u);\r
+ CY_SET_REG8(CYREG_SC1_SW10, 0u);\r
+\r
+ CY_SET_REG8(CYREG_SC2_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_SC2_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_SC2_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_SC2_SW4 , 0u);\r
+ CY_SET_REG8(CYREG_SC2_SW6 , 0u);\r
+ CY_SET_REG8(CYREG_SC2_SW8 , 0u);\r
+ CY_SET_REG8(CYREG_SC2_SW10, 0u);\r
+\r
+ CY_SET_REG8(CYREG_SC3_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_SC3_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_SC3_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_SC3_SW4 , 0u);\r
+ CY_SET_REG8(CYREG_SC3_SW6 , 0u);\r
+ CY_SET_REG8(CYREG_SC3_SW8 , 0u);\r
+ CY_SET_REG8(CYREG_SC3_SW10, 0u);\r
\r
\r
#if(CY_PSOC3)\r
* Summary:\r
* This API is used for restoring device configurations after wakeup from Sleep\r
* and Hibernate low power modes:\r
-* - Restores COMP, VIDAC, DSM and SAR routing connections (PSoC 5)\r
-* - Restores SC/CT routing connections (PSoC 3/5/5LP)\r
+* - Restores SC/CT routing connections\r
* - Restores enable state of Serial Wire Viewer (SWV) (PSoC 3)\r
-* - Restores initial buzz rate (PSoC 5)\r
* - Restore boost reference selection\r
*\r
* Parameters:\r
*******************************************************************************/\r
static void CyPmHibSlpRestore(void) \r
{\r
- #if(CY_PSOC5A)\r
-\r
- /* Restore COMP routing registers */\r
- CY_SET_REG8(CYREG_CMP0_SW0 , cyPmBackup.cmpData[0u] );\r
- CY_SET_REG8(CYREG_CMP0_SW2 , cyPmBackup.cmpData[1u] );\r
- CY_SET_REG8(CYREG_CMP0_SW3 , cyPmBackup.cmpData[2u] );\r
- CY_SET_REG8(CYREG_CMP0_SW4 , cyPmBackup.cmpData[3u] );\r
- CY_SET_REG8(CYREG_CMP0_SW6 , cyPmBackup.cmpData[4u] );\r
-\r
- CY_SET_REG8(CYREG_CMP1_SW0 , cyPmBackup.cmpData[5u] );\r
- CY_SET_REG8(CYREG_CMP1_SW2 , cyPmBackup.cmpData[6u] );\r
- CY_SET_REG8(CYREG_CMP1_SW3 , cyPmBackup.cmpData[7u] );\r
- CY_SET_REG8(CYREG_CMP1_SW4 , cyPmBackup.cmpData[8u] );\r
- CY_SET_REG8(CYREG_CMP1_SW6 , cyPmBackup.cmpData[9u] );\r
-\r
- CY_SET_REG8(CYREG_CMP2_SW0 , cyPmBackup.cmpData[10u]);\r
- CY_SET_REG8(CYREG_CMP2_SW2 , cyPmBackup.cmpData[11u]);\r
- CY_SET_REG8(CYREG_CMP2_SW3 , cyPmBackup.cmpData[12u]);\r
- CY_SET_REG8(CYREG_CMP2_SW4 , cyPmBackup.cmpData[13u]);\r
- CY_SET_REG8(CYREG_CMP2_SW6 , cyPmBackup.cmpData[14u]);\r
-\r
- CY_SET_REG8(CYREG_CMP3_SW0 , cyPmBackup.cmpData[15u]);\r
- CY_SET_REG8(CYREG_CMP3_SW2 , cyPmBackup.cmpData[16u]);\r
- CY_SET_REG8(CYREG_CMP3_SW3 , cyPmBackup.cmpData[17u]);\r
- CY_SET_REG8(CYREG_CMP3_SW4 , cyPmBackup.cmpData[18u]);\r
- CY_SET_REG8(CYREG_CMP3_SW6 , cyPmBackup.cmpData[19u]);\r
-\r
- /* Restore DAC routing registers */\r
- CY_SET_REG8(CYREG_DAC0_SW0 , cyPmBackup.dacData[0u] );\r
- CY_SET_REG8(CYREG_DAC0_SW2 , cyPmBackup.dacData[1u] );\r
- CY_SET_REG8(CYREG_DAC0_SW3 , cyPmBackup.dacData[2u] );\r
- CY_SET_REG8(CYREG_DAC0_SW4 , cyPmBackup.dacData[3u] );\r
-\r
- CY_SET_REG8(CYREG_DAC1_SW0 , cyPmBackup.dacData[4u] );\r
- CY_SET_REG8(CYREG_DAC1_SW2 , cyPmBackup.dacData[5u] );\r
- CY_SET_REG8(CYREG_DAC1_SW3 , cyPmBackup.dacData[6u] );\r
- CY_SET_REG8(CYREG_DAC1_SW4 , cyPmBackup.dacData[7u] );\r
-\r
- CY_SET_REG8(CYREG_DAC2_SW0 , cyPmBackup.dacData[8u] );\r
- CY_SET_REG8(CYREG_DAC2_SW2 , cyPmBackup.dacData[9u] );\r
- CY_SET_REG8(CYREG_DAC2_SW3 , cyPmBackup.dacData[10u]);\r
- CY_SET_REG8(CYREG_DAC2_SW4 , cyPmBackup.dacData[11u]);\r
-\r
- CY_SET_REG8(CYREG_DAC3_SW0 , cyPmBackup.dacData[12u]);\r
- CY_SET_REG8(CYREG_DAC3_SW2 , cyPmBackup.dacData[13u]);\r
- CY_SET_REG8(CYREG_DAC3_SW3 , cyPmBackup.dacData[14u]);\r
- CY_SET_REG8(CYREG_DAC3_SW4 , cyPmBackup.dacData[15u]);\r
-\r
-\r
- /* Restore DSM routing registers */\r
- CY_SET_REG8(CYREG_DSM0_SW0 , cyPmBackup.dsmData[0u]);\r
- CY_SET_REG8(CYREG_DSM0_SW2 , cyPmBackup.dsmData[1u]);\r
- CY_SET_REG8(CYREG_DSM0_SW3 , cyPmBackup.dsmData[2u]);\r
- CY_SET_REG8(CYREG_DSM0_SW4 , cyPmBackup.dsmData[3u]);\r
- CY_SET_REG8(CYREG_DSM0_SW6 , cyPmBackup.dsmData[4u]);\r
-\r
-\r
- /* Restore SAR routing registers */\r
- CY_SET_REG8(CYREG_SAR0_SW0 , cyPmBackup.sarData[0u]);\r
- CY_SET_REG8(CYREG_SAR0_SW2 , cyPmBackup.sarData[1u]);\r
- CY_SET_REG8(CYREG_SAR0_SW3 , cyPmBackup.sarData[2u]);\r
- CY_SET_REG8(CYREG_SAR0_SW4 , cyPmBackup.sarData[3u]);\r
- CY_SET_REG8(CYREG_SAR0_SW6 , cyPmBackup.sarData[4u]);\r
-\r
- CY_SET_REG8(CYREG_SAR1_SW0 , cyPmBackup.sarData[5u]);\r
- CY_SET_REG8(CYREG_SAR1_SW2 , cyPmBackup.sarData[6u]);\r
- CY_SET_REG8(CYREG_SAR1_SW3 , cyPmBackup.sarData[7u]);\r
- CY_SET_REG8(CYREG_SAR1_SW4 , cyPmBackup.sarData[8u]);\r
- CY_SET_REG8(CYREG_SAR1_SW6 , cyPmBackup.sarData[9u]);\r
-\r
- #endif /* (CY_PSOC5A) */\r
-\r
- #if(CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP)\r
-\r
- /* Restore SC/CT routing registers */\r
- CY_SET_REG8(CYREG_SC0_SW0 , cyPmBackup.scctData[0u] );\r
- CY_SET_REG8(CYREG_SC0_SW2 , cyPmBackup.scctData[1u] );\r
- CY_SET_REG8(CYREG_SC0_SW3 , cyPmBackup.scctData[2u] );\r
- CY_SET_REG8(CYREG_SC0_SW4 , cyPmBackup.scctData[3u] );\r
- CY_SET_REG8(CYREG_SC0_SW6 , cyPmBackup.scctData[4u] );\r
- CY_SET_REG8(CYREG_SC0_SW8 , cyPmBackup.scctData[5u] );\r
- CY_SET_REG8(CYREG_SC0_SW10, cyPmBackup.scctData[6u] );\r
-\r
- CY_SET_REG8(CYREG_SC1_SW0 , cyPmBackup.scctData[7u] );\r
- CY_SET_REG8(CYREG_SC1_SW2 , cyPmBackup.scctData[8u] );\r
- CY_SET_REG8(CYREG_SC1_SW3 , cyPmBackup.scctData[9u] );\r
- CY_SET_REG8(CYREG_SC1_SW4 , cyPmBackup.scctData[10u]);\r
- CY_SET_REG8(CYREG_SC1_SW6 , cyPmBackup.scctData[11u]);\r
- CY_SET_REG8(CYREG_SC1_SW8 , cyPmBackup.scctData[12u]);\r
- CY_SET_REG8(CYREG_SC1_SW10, cyPmBackup.scctData[13u]);\r
-\r
- CY_SET_REG8(CYREG_SC2_SW0 , cyPmBackup.scctData[14u]);\r
- CY_SET_REG8(CYREG_SC2_SW2 , cyPmBackup.scctData[15u]);\r
- CY_SET_REG8(CYREG_SC2_SW3 , cyPmBackup.scctData[16u]);\r
- CY_SET_REG8(CYREG_SC2_SW4 , cyPmBackup.scctData[17u]);\r
- CY_SET_REG8(CYREG_SC2_SW6 , cyPmBackup.scctData[18u]);\r
- CY_SET_REG8(CYREG_SC2_SW8 , cyPmBackup.scctData[19u]);\r
- CY_SET_REG8(CYREG_SC2_SW10, cyPmBackup.scctData[20u]);\r
-\r
- CY_SET_REG8(CYREG_SC3_SW0 , cyPmBackup.scctData[21u]);\r
- CY_SET_REG8(CYREG_SC3_SW2 , cyPmBackup.scctData[22u]);\r
- CY_SET_REG8(CYREG_SC3_SW3 , cyPmBackup.scctData[23u]);\r
- CY_SET_REG8(CYREG_SC3_SW4 , cyPmBackup.scctData[24u]);\r
- CY_SET_REG8(CYREG_SC3_SW6 , cyPmBackup.scctData[25u]);\r
- CY_SET_REG8(CYREG_SC3_SW8 , cyPmBackup.scctData[26u]);\r
- CY_SET_REG8(CYREG_SC3_SW10, cyPmBackup.scctData[27u]);\r
-\r
- #endif /* (CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP) */\r
+ /* Restore SC/CT routing registers */\r
+ CY_SET_REG8(CYREG_SC0_SW0 , cyPmBackup.scctData[0u] );\r
+ CY_SET_REG8(CYREG_SC0_SW2 , cyPmBackup.scctData[1u] );\r
+ CY_SET_REG8(CYREG_SC0_SW3 , cyPmBackup.scctData[2u] );\r
+ CY_SET_REG8(CYREG_SC0_SW4 , cyPmBackup.scctData[3u] );\r
+ CY_SET_REG8(CYREG_SC0_SW6 , cyPmBackup.scctData[4u] );\r
+ CY_SET_REG8(CYREG_SC0_SW8 , cyPmBackup.scctData[5u] );\r
+ CY_SET_REG8(CYREG_SC0_SW10, cyPmBackup.scctData[6u] );\r
+\r
+ CY_SET_REG8(CYREG_SC1_SW0 , cyPmBackup.scctData[7u] );\r
+ CY_SET_REG8(CYREG_SC1_SW2 , cyPmBackup.scctData[8u] );\r
+ CY_SET_REG8(CYREG_SC1_SW3 , cyPmBackup.scctData[9u] );\r
+ CY_SET_REG8(CYREG_SC1_SW4 , cyPmBackup.scctData[10u]);\r
+ CY_SET_REG8(CYREG_SC1_SW6 , cyPmBackup.scctData[11u]);\r
+ CY_SET_REG8(CYREG_SC1_SW8 , cyPmBackup.scctData[12u]);\r
+ CY_SET_REG8(CYREG_SC1_SW10, cyPmBackup.scctData[13u]);\r
+\r
+ CY_SET_REG8(CYREG_SC2_SW0 , cyPmBackup.scctData[14u]);\r
+ CY_SET_REG8(CYREG_SC2_SW2 , cyPmBackup.scctData[15u]);\r
+ CY_SET_REG8(CYREG_SC2_SW3 , cyPmBackup.scctData[16u]);\r
+ CY_SET_REG8(CYREG_SC2_SW4 , cyPmBackup.scctData[17u]);\r
+ CY_SET_REG8(CYREG_SC2_SW6 , cyPmBackup.scctData[18u]);\r
+ CY_SET_REG8(CYREG_SC2_SW8 , cyPmBackup.scctData[19u]);\r
+ CY_SET_REG8(CYREG_SC2_SW10, cyPmBackup.scctData[20u]);\r
+\r
+ CY_SET_REG8(CYREG_SC3_SW0 , cyPmBackup.scctData[21u]);\r
+ CY_SET_REG8(CYREG_SC3_SW2 , cyPmBackup.scctData[22u]);\r
+ CY_SET_REG8(CYREG_SC3_SW3 , cyPmBackup.scctData[23u]);\r
+ CY_SET_REG8(CYREG_SC3_SW4 , cyPmBackup.scctData[24u]);\r
+ CY_SET_REG8(CYREG_SC3_SW6 , cyPmBackup.scctData[25u]);\r
+ CY_SET_REG8(CYREG_SC3_SW8 , cyPmBackup.scctData[26u]);\r
+ CY_SET_REG8(CYREG_SC3_SW10, cyPmBackup.scctData[27u]);\r
\r
\r
#if(CY_PSOC3)\r
#endif /* (CY_PSOC3) */\r
\r
\r
- #if(CY_PSOC5A)\r
-\r
- /* Restore buzz sleep trim value */\r
- CY_PM_PWRSYS_BUZZ_TR_REG = cyPmBackup.buzzSleepTrim | \\r
- (CY_PM_PWRSYS_BUZZ_TR_REG & CY_PM_PWRSYS_BUZZ_TR_MASK);\r
-\r
- #endif /* (CY_PSOC5A) */\r
-\r
-\r
/* Restore boost reference */\r
if(CY_PM_ENABLED == cyPmBackup.boostRefExt)\r
{\r
cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK;\r
\r
/* Save state of reset device at a specified Vddd threshold */\r
- #if(CY_PSOC5A)\r
-\r
- /* Not applicable PSoC 5 */\r
- cyPmBackup.lvidRst = CY_PM_DISABLED;\r
-\r
- #else\r
-\r
- cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \\r
- CY_PM_DISABLED : CY_PM_ENABLED;\r
-\r
- #endif /* (CY_PSOC5A) */\r
+ cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \\r
+ CY_PM_DISABLED : CY_PM_ENABLED;\r
\r
CyVdLvDigitDisable();\r
}\r
cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u;\r
\r
/* Save state of reset device at a specified Vdda threshold */\r
- #if(CY_PSOC5A)\r
-\r
- /* Not applicable PSoC 5 */\r
- cyPmBackup.lviaRst = CY_PM_DISABLED;\r
-\r
- #else\r
-\r
- cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \\r
- CY_PM_DISABLED : CY_PM_ENABLED;\r
-\r
- #endif /* (CY_PSOC5A) */\r
+ cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \\r
+ CY_PM_DISABLED : CY_PM_ENABLED;\r
\r
CyVdLvAnalogDisable();\r
}\r
/*******************************************************************************\r
* File Name: cyPm.h\r
-* Version 3.40\r
+* Version 4.0\r
*\r
* Description:\r
* Provides the function definitions for the power management API.\r
#endif /* (CY_PSOC3) */\r
\r
\r
-#if(CY_PSOC3 || CY_PSOC5LP)\r
-\r
- /* Wake up sources for the Sleep mode */\r
- #define PM_SLEEP_SRC_COMPARATOR0 (0x0001u)\r
- #define PM_SLEEP_SRC_COMPARATOR1 (0x0002u)\r
- #define PM_SLEEP_SRC_COMPARATOR2 (0x0004u)\r
- #define PM_SLEEP_SRC_COMPARATOR3 (0x0008u)\r
- #define PM_SLEEP_SRC_PICU (0x0040u)\r
- #define PM_SLEEP_SRC_I2C (0x0080u)\r
- #define PM_SLEEP_SRC_BOOSTCONVERTER (0x0200u)\r
- #define PM_SLEEP_SRC_VD (0x0400u)\r
- #define PM_SLEEP_SRC_CTW (0x0800u)\r
- #define PM_SLEEP_SRC_ONE_PPS (0x0800u)\r
- #define PM_SLEEP_SRC_LCD (0x1000u)\r
-\r
- /* Wake up sources for the Alternate Active mode */\r
- #define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u)\r
- #define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u)\r
- #define PM_ALT_ACT_SRC_COMPARATOR2 (0x0004u)\r
- #define PM_ALT_ACT_SRC_COMPARATOR3 (0x0008u)\r
- #define PM_ALT_ACT_SRC_INTERRUPT (0x0010u)\r
- #define PM_ALT_ACT_SRC_PICU (0x0040u)\r
- #define PM_ALT_ACT_SRC_I2C (0x0080u)\r
- #define PM_ALT_ACT_SRC_BOOSTCONVERTER (0x0200u)\r
- #define PM_ALT_ACT_SRC_FTW (0x0400u)\r
- #define PM_ALT_ACT_SRC_VD (0x0400u)\r
- #define PM_ALT_ACT_SRC_CTW (0x0800u)\r
- #define PM_ALT_ACT_SRC_ONE_PPS (0x0800u)\r
- #define PM_ALT_ACT_SRC_LCD (0x1000u)\r
-\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+/* Wake up sources for the Sleep mode */\r
+#define PM_SLEEP_SRC_COMPARATOR0 (0x0001u)\r
+#define PM_SLEEP_SRC_COMPARATOR1 (0x0002u)\r
+#define PM_SLEEP_SRC_COMPARATOR2 (0x0004u)\r
+#define PM_SLEEP_SRC_COMPARATOR3 (0x0008u)\r
+#define PM_SLEEP_SRC_PICU (0x0040u)\r
+#define PM_SLEEP_SRC_I2C (0x0080u)\r
+#define PM_SLEEP_SRC_BOOSTCONVERTER (0x0200u)\r
+#define PM_SLEEP_SRC_VD (0x0400u)\r
+#define PM_SLEEP_SRC_CTW (0x0800u)\r
+#define PM_SLEEP_SRC_ONE_PPS (0x0800u)\r
+#define PM_SLEEP_SRC_LCD (0x1000u)\r
+\r
+/* Wake up sources for the Alternate Active mode */\r
+#define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u)\r
+#define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u)\r
+#define PM_ALT_ACT_SRC_COMPARATOR2 (0x0004u)\r
+#define PM_ALT_ACT_SRC_COMPARATOR3 (0x0008u)\r
+#define PM_ALT_ACT_SRC_INTERRUPT (0x0010u)\r
+#define PM_ALT_ACT_SRC_PICU (0x0040u)\r
+#define PM_ALT_ACT_SRC_I2C (0x0080u)\r
+#define PM_ALT_ACT_SRC_BOOSTCONVERTER (0x0200u)\r
+#define PM_ALT_ACT_SRC_FTW (0x0400u)\r
+#define PM_ALT_ACT_SRC_VD (0x0400u)\r
+#define PM_ALT_ACT_SRC_CTW (0x0800u)\r
+#define PM_ALT_ACT_SRC_ONE_PPS (0x0800u)\r
+#define PM_ALT_ACT_SRC_LCD (0x1000u)\r
\r
\r
#define CY_PM_WAKEUP_PICU (0x04u)\r
#define CY_PM_FREQ_48MHZ (48u)\r
\r
\r
-#if(CY_PSOC5A)\r
- #define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (650u)\r
-#else\r
- #define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (5u)\r
-#endif /* (CY_PSOC5A) */\r
+#define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (5u)\r
\r
\r
/* Delay line bandgap current settling time starting from a wakeup event */\r
#define CY_PM_MAX_FLASH_WAIT_CYCLES (45u)\r
#endif /* (CY_PSOC3) */\r
\r
-#if(CY_PSOC5A)\r
- #define CY_PM_MAX_FLASH_WAIT_CYCLES (55u)\r
-#endif /* (CY_PSOC5A) */\r
-\r
-#if(CY_PSOC5LP)\r
+#if(CY_PSOC5)\r
#define CY_PM_MAX_FLASH_WAIT_CYCLES (55u)\r
-#endif /* (CY_PSOC5LP) */\r
+#endif /* (CY_PSOC5) */\r
\r
\r
/*******************************************************************************\r
* bitfield.\r
*******************************************************************************/\r
#if(CY_PSOC3)\r
- #define CY_PM_GET_CPU_FREQ_MHZ ((uint32)(cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) / \\r
- ((uint8)(((CY_PM_CLKDIST_MSTR1_REG & CY_PM_CLKDIST_CPU_DIV_MASK) >> 4u) + 1u)))\r
+ #define CY_PM_GET_CPU_FREQ_MHZ \\r
+ ((uint32)(cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) / \\r
+ ((uint8)(((CY_PM_CLKDIST_MSTR1_REG & CY_PM_CLKDIST_CPU_DIV_MASK) >> 4u) + 1u)))\r
#endif /* (CY_PSOC3) */\r
\r
#if(CY_PSOC5)\r
\r
#if defined(__ARMCC_VERSION) /* Instristic for Keil compilers */\r
#define CY_PM_WFI __wfi()\r
- #else /* ASM for GCC */\r
+ #else /* ASM for GCC & IAR */\r
#define CY_PM_WFI asm volatile ("WFI \n")\r
#endif /* (__ARMCC_VERSION) */\r
\r
\r
typedef struct cyPmBackupStruct\r
{\r
- #if(!CY_PSOC5A)\r
-\r
- uint8 iloPowerMode; /* ILO power mode */\r
- uint8 ilo1kEnable; /* ILO 1K enable state */\r
- uint8 ilo100kEnable; /* ILO 100K enable state */\r
-\r
- uint8 slpTrBypass; /* Sleep Trim Bypass */\r
-\r
- #endif /* (!CY_PSOC5A) */\r
-\r
-\r
- #if(CY_PSOC5A)\r
-\r
- /* State of the I2C regulator backup */\r
- uint8 i2cRegBackup;\r
-\r
- #endif /* (CY_PSOC5A) */\r
-\r
-\r
- #if(CY_PSOC5A)\r
- uint8 buzzSleepTrim;\r
- #endif /* (CY_PSOC5A) */\r
+ uint8 iloPowerMode; /* ILO power mode */\r
+ uint8 ilo1kEnable; /* ILO 1K enable state */\r
+ uint8 ilo100kEnable; /* ILO 100K enable state */\r
\r
+ uint8 slpTrBypass; /* Sleep Trim Bypass */\r
\r
#if(CY_PSOC3)\r
\r
uint8 swvClkEnabled; /* SWV clock enable state */\r
uint8 prt1Dm; /* Ports drive mode configuration */\r
+ uint8 hardwareBuzz;\r
\r
#endif /* (CY_PSOC3) */\r
\r
- #if(CY_PSOC3 || CY_PSOC5LP)\r
-\r
- uint8 wakeupCfg0; /* Wake up configuration 0 */\r
- uint8 wakeupCfg1; /* Wake up configuration 1 */\r
- uint8 wakeupCfg2; /* Wake up configuration 2 */\r
-\r
- #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
-\r
+ uint8 wakeupCfg0; /* Wake up configuration 0 */\r
+ uint8 wakeupCfg1; /* Wake up configuration 1 */\r
+ uint8 wakeupCfg2; /* Wake up configuration 2 */\r
\r
- #if(CY_PSOC3 || CY_PSOC5LP)\r
-\r
- uint8 wakeupTrim0;\r
- uint8 wakeupTrim1;\r
-\r
- #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
-\r
-\r
- #if(CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP)\r
-\r
- uint8 scctData[28u]; /* SC/CT routing registers */\r
-\r
- #endif /* (CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP) */\r
-\r
- #if(CY_PSOC5A)\r
-\r
- uint8 cmpData[20u];\r
- uint8 dacData[16u];\r
- uint8 dsmData[5u];\r
- uint8 sarData[10u];\r
-\r
- uint8 pmTwCfg2;\r
- uint8 picuIntType[72u];\r
-\r
- uint8 pres1;\r
- uint8 pres2;\r
-\r
- #endif /* (CY_PSOC5A) */\r
+ uint8 wakeupTrim0;\r
+ uint8 wakeupTrim1;\r
\r
+ uint8 scctData[28u]; /* SC/CT routing registers */\r
\r
/* CyPmHviLviSaveDisable()/CyPmHviLviRestore() */\r
uint8 lvidEn;\r
#endif /* (CY_PSOC3) */\r
\r
\r
-#if(!CY_PSOC5A)\r
+/* Sleep Regulator Trim Register */\r
+#define CY_PM_PWRSYS_SLP_TR_REG (* (reg8 *) CYREG_PWRSYS_SLP_TR )\r
+#define CY_PM_PWRSYS_SLP_TR_PTR ( (reg8 *) CYREG_PWRSYS_SLP_TR )\r
\r
- /* Sleep Regulator Trim Register */\r
- #define CY_PM_PWRSYS_SLP_TR_REG (* (reg8 *) CYREG_PWRSYS_SLP_TR )\r
- #define CY_PM_PWRSYS_SLP_TR_PTR ( (reg8 *) CYREG_PWRSYS_SLP_TR )\r
-\r
-#endif /* (CY_PSOC3) */\r
\r
/* Reset System Control Register */\r
#define CY_PM_RESET_CR1_REG (* (reg8 *) CYREG_RESET_CR1 )\r
#define CY_PM_RESET_CR1_PTR ( (reg8 *) CYREG_RESET_CR1 )\r
\r
-#if(CY_PSOC5A)\r
-\r
- /* LVD/POR Test Mode Control Register */\r
- #define CY_PM_RESET_CR3_REG (* (reg8 *) CYREG_RESET_CR3 )\r
- #define CY_PM_RESET_CR3_PTR ( (reg8 *) CYREG_RESET_CR3 )\r
-\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* Power Mode Wakeup Trim Register 0 */\r
#define CY_PM_PWRSYS_WAKE_TR0_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR0 )\r
#define CY_PM_PWRSYS_WAKE_TR0_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR0 )\r
\r
#endif /* (CY_PSOC3) */\r
\r
-#if(CY_PSOC5A)\r
-\r
- /* Power Mode Buzz Trim Register */\r
- #define CY_PM_PWRSYS_BUZZ_TR_REG (* (reg8 *) CYREG_PWRSYS_BUZZ_TR )\r
- #define CY_PM_PWRSYS_BUZZ_TR_PTR ( (reg8 *) CYREG_PWRSYS_BUZZ_TR )\r
-\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* Power Manager Interrupt Status Register */\r
#define CY_PM_INT_SR_REG (* (reg8 *) CYREG_PM_INT_SR )\r
#define CY_PM_INT_SR_PTR ( (reg8 *) CYREG_PM_INT_SR )\r
#endif /* (CY_PSOC3) */\r
\r
\r
-#if(CY_PSOC3 || CY_PSOC5LP)\r
-\r
- /* Power Mode Wakeup Mask Configuration Register 0 */\r
- #define CY_PM_WAKEUP_CFG0_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG0 )\r
- #define CY_PM_WAKEUP_CFG0_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG0 )\r
-\r
- /* Power Mode Wakeup Mask Configuration Register 1 */\r
- #define CY_PM_WAKEUP_CFG1_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG1 )\r
- #define CY_PM_WAKEUP_CFG1_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG1 )\r
-\r
- /* Power Mode Wakeup Mask Configuration Register 2 */\r
- #define CY_PM_WAKEUP_CFG2_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG2 )\r
- #define CY_PM_WAKEUP_CFG2_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG2 )\r
-\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
-\r
-\r
-#if(CY_PSOC5A)\r
-\r
- /* Watchdog Timer Configuration Register */\r
- #define CY_PM_WDT_CFG_REG (* (reg8 *) CYREG_PM_WDT_CFG )\r
- #define CY_PM_WDT_CFG_PTR ( (reg8 *) CYREG_PM_WDT_CFG )\r
+/* Power Mode Wakeup Mask Configuration Register 0 */\r
+#define CY_PM_WAKEUP_CFG0_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG0 )\r
+#define CY_PM_WAKEUP_CFG0_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG0 )\r
\r
-#endif /* (CY_PSOC5A) */\r
+/* Power Mode Wakeup Mask Configuration Register 1 */\r
+#define CY_PM_WAKEUP_CFG1_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG1 )\r
+#define CY_PM_WAKEUP_CFG1_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG1 )\r
\r
+/* Power Mode Wakeup Mask Configuration Register 2 */\r
+#define CY_PM_WAKEUP_CFG2_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG2 )\r
+#define CY_PM_WAKEUP_CFG2_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG2 )\r
\r
/* Boost Control 2 */\r
#define CY_PM_BOOST_CR2_REG (* (reg8 *) CYREG_BOOST_CR2 )\r
/* The low-voltage-interrupt feature on the external digital supply */\r
#define CY_PM_RESET_CR1_LVID_EN (0x01u)\r
\r
-#if(CY_PSOC5A)\r
-\r
- /* Partly disables PRES-A and PRES-D circuits */\r
- #define CY_PM_RESET_CR1_DIS_PRES1 (0x10u)\r
-\r
- /* Partly disables PRES-A and PRES-D circuits */\r
- #define CY_PM_RESET_CR3_DIS_PRES2 (0x08u)\r
-\r
-#endif /* (CY_PSOC5A) */\r
-\r
/* Allows the system to program delays on clk_sync_d */\r
#define CY_PM_CLKDIST_DELAY_EN (0x04u)\r
\r
\r
-#if(CY_PSOC3 || CY_PSOC5LP)\r
-\r
- #define CY_PM_WAKEUP_SRC_CMPS_MASK (0x000Fu)\r
-\r
- /* Holdoff mask sleep trim */\r
- #define CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK (0x1Fu)\r
-\r
-#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+#define CY_PM_WAKEUP_SRC_CMPS_MASK (0x000Fu)\r
\r
+/* Holdoff mask sleep trim */\r
+#define CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK (0x1Fu)\r
\r
#if(CY_PSOC3)\r
\r
#endif /* (CY_PSOC3) */\r
\r
\r
-#if(!CY_PSOC5A)\r
-\r
- /* Disable the sleep regulator and shorts vccd to vpwrsleep */\r
- #define CY_PM_PWRSYS_SLP_TR_BYPASS (0x10u)\r
-\r
-#endif /* (!CY_PSOC5A) */\r
-\r
-\r
-#if(CY_PSOC5A)\r
-\r
- #define CY_PM_PWRSYS_BUZZ_TR_512_TICKS (0x08u)\r
- #define CY_PM_PWRSYS_BUZZ_TR_MASK (0xF0u)\r
-\r
-#endif /* (CY_PSOC5A) */\r
-\r
-\r
-#if(CY_PSOC5A)\r
-\r
- /* Watchdog Timer Configuration Register */\r
- #define CY_PM_WDT_CFG_CTW_RESET (0x80u)\r
-\r
- /***************************************************************************\r
- * The PICU interrupt type registers are divided into three sections where\r
- * the registers addresses are consecutive.\r
- ***************************************************************************/\r
- #define CY_PM_PICU_0_6_INT_BASE (CYDEV_PICU_INTTYPE_PICU0_BASE )\r
- #define CY_PM_PICU_12_INT_BASE (CYDEV_PICU_INTTYPE_PICU12_BASE)\r
- #define CY_PM_PICU_15_INT_BASE (CYDEV_PICU_INTTYPE_PICU15_BASE)\r
-\r
- #define CY_PM_PICU_0_6_INT_SIZE (CYDEV_PICU_INTTYPE_PICU0_SIZE + CYDEV_PICU_INTTYPE_PICU1_SIZE + \\r
- CYDEV_PICU_INTTYPE_PICU2_SIZE + CYDEV_PICU_INTTYPE_PICU3_SIZE + \\r
- CYDEV_PICU_INTTYPE_PICU4_SIZE + CYDEV_PICU_INTTYPE_PICU5_SIZE + \\r
- CYDEV_PICU_INTTYPE_PICU6_SIZE)\r
- #define CY_PM_PICU_12_INT_SIZE (CYDEV_PICU_INTTYPE_PICU12_SIZE)\r
- #define CY_PM_PICU_15_INT_SIZE (CYDEV_PICU_INTTYPE_PICU15_SIZE)\r
-\r
-#endif /* (CY_PSOC5A) */\r
+/* Disable the sleep regulator and shorts vccd to vpwrsleep */\r
+#define CY_PM_PWRSYS_SLP_TR_BYPASS (0x10u)\r
\r
/* Boost Control 2: Select external precision reference */\r
#define CY_PM_BOOST_CR2_EREFSEL_EXT (0x08u)\r
\r
-\r
-\r
#if(CY_PSOC3)\r
\r
#define CY_PM_PWRSYS_WAKE_TR0 (0xFFu)\r
\r
#endif /* (CY_PSOC3) */\r
\r
-\r
-#if(CY_PSOC5LP)\r
+#if(CY_PSOC5)\r
\r
#define CY_PM_PWRSYS_WAKE_TR0 (0xFFu)\r
#define CY_PM_PWRSYS_WAKE_TR1 (0xB0u)\r
\r
-#endif /* (CY_PSOC5LP) */\r
+#endif /* (CY_PSOC5) */\r
\r
\r
/*******************************************************************************\r
/*******************************************************************************\r
* FILENAME: cydevice.h\r
* OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator 2.2 Component Pack 6\r
+* PSoC Creator 3.0\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
+* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
/*******************************************************************************\r
* FILENAME: cydevice_trm.h\r
* \r
-* PSoC Creator 2.2 Component Pack 6\r
+* PSoC Creator 3.0\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
+* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
/*******************************************************************************\r
* FILENAME: cydevicegnu.inc\r
* OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator 2.2 Component Pack 6\r
+* PSoC Creator 3.0\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
+* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
/*******************************************************************************\r
* FILENAME: cydevicegnu_trm.inc\r
* \r
-* PSoC Creator 2.2 Component Pack 6\r
+* PSoC Creator 3.0\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
+* This file is automatically generated by PSoC Creator.\r
*\r
********************************************************************************\r
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
--- /dev/null
+;\r
+; FILENAME: cydeviceiar.inc\r
+; OBSOLETE: Do not use this file. Use the _trm version instead.\r
+; PSoC Creator 3.0\r
+;\r
+; DESCRIPTION:\r
+; This file provides all of the address values for the entire PSoC device.\r
+;\r
+;-------------------------------------------------------------------------------\r
+; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; You may use this file only in accordance with the license, terms, conditions, \r
+; disclaimers, and limitations in the end user license agreement accompanying \r
+; the software package with which this file was provided.\r
+;-------------------------------------------------------------------------------\r
+\r
+#define CYDEV_FLASH_BASE 0x00000000\r
+#define CYDEV_FLASH_SIZE 0x00040000\r
+#define CYDEV_FLASH_DATA_MBASE 0x00000000\r
+#define CYDEV_FLASH_DATA_MSIZE 0x00040000\r
+#define CYDEV_SRAM_BASE 0x1fff8000\r
+#define CYDEV_SRAM_SIZE 0x00010000\r
+#define CYDEV_SRAM_CODE64K_MBASE 0x1fff8000\r
+#define CYDEV_SRAM_CODE64K_MSIZE 0x00004000\r
+#define CYDEV_SRAM_CODE32K_MBASE 0x1fffc000\r
+#define CYDEV_SRAM_CODE32K_MSIZE 0x00002000\r
+#define CYDEV_SRAM_CODE16K_MBASE 0x1fffe000\r
+#define CYDEV_SRAM_CODE16K_MSIZE 0x00001000\r
+#define CYDEV_SRAM_CODE_MBASE 0x1fff8000\r
+#define CYDEV_SRAM_CODE_MSIZE 0x00008000\r
+#define CYDEV_SRAM_DATA_MBASE 0x20000000\r
+#define CYDEV_SRAM_DATA_MSIZE 0x00008000\r
+#define CYDEV_SRAM_DATA16K_MBASE 0x20001000\r
+#define CYDEV_SRAM_DATA16K_MSIZE 0x00001000\r
+#define CYDEV_SRAM_DATA32K_MBASE 0x20002000\r
+#define CYDEV_SRAM_DATA32K_MSIZE 0x00002000\r
+#define CYDEV_SRAM_DATA64K_MBASE 0x20004000\r
+#define CYDEV_SRAM_DATA64K_MSIZE 0x00004000\r
+#define CYDEV_DMA_BASE 0x20008000\r
+#define CYDEV_DMA_SIZE 0x00008000\r
+#define CYDEV_DMA_SRAM64K_MBASE 0x20008000\r
+#define CYDEV_DMA_SRAM64K_MSIZE 0x00004000\r
+#define CYDEV_DMA_SRAM32K_MBASE 0x2000c000\r
+#define CYDEV_DMA_SRAM32K_MSIZE 0x00002000\r
+#define CYDEV_DMA_SRAM16K_MBASE 0x2000e000\r
+#define CYDEV_DMA_SRAM16K_MSIZE 0x00001000\r
+#define CYDEV_DMA_SRAM_MBASE 0x2000f000\r
+#define CYDEV_DMA_SRAM_MSIZE 0x00001000\r
+#define CYDEV_CLKDIST_BASE 0x40004000\r
+#define CYDEV_CLKDIST_SIZE 0x00000110\r
+#define CYDEV_CLKDIST_CR 0x40004000\r
+#define CYDEV_CLKDIST_LD 0x40004001\r
+#define CYDEV_CLKDIST_WRK0 0x40004002\r
+#define CYDEV_CLKDIST_WRK1 0x40004003\r
+#define CYDEV_CLKDIST_MSTR0 0x40004004\r
+#define CYDEV_CLKDIST_MSTR1 0x40004005\r
+#define CYDEV_CLKDIST_BCFG0 0x40004006\r
+#define CYDEV_CLKDIST_BCFG1 0x40004007\r
+#define CYDEV_CLKDIST_BCFG2 0x40004008\r
+#define CYDEV_CLKDIST_UCFG 0x40004009\r
+#define CYDEV_CLKDIST_DLY0 0x4000400a\r
+#define CYDEV_CLKDIST_DLY1 0x4000400b\r
+#define CYDEV_CLKDIST_DMASK 0x40004010\r
+#define CYDEV_CLKDIST_AMASK 0x40004014\r
+#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080\r
+#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003\r
+#define CYDEV_CLKDIST_DCFG0_CFG0 0x40004080\r
+#define CYDEV_CLKDIST_DCFG0_CFG1 0x40004081\r
+#define CYDEV_CLKDIST_DCFG0_CFG2 0x40004082\r
+#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084\r
+#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003\r
+#define CYDEV_CLKDIST_DCFG1_CFG0 0x40004084\r
+#define CYDEV_CLKDIST_DCFG1_CFG1 0x40004085\r
+#define CYDEV_CLKDIST_DCFG1_CFG2 0x40004086\r
+#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088\r
+#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003\r
+#define CYDEV_CLKDIST_DCFG2_CFG0 0x40004088\r
+#define CYDEV_CLKDIST_DCFG2_CFG1 0x40004089\r
+#define CYDEV_CLKDIST_DCFG2_CFG2 0x4000408a\r
+#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408c\r
+#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003\r
+#define CYDEV_CLKDIST_DCFG3_CFG0 0x4000408c\r
+#define CYDEV_CLKDIST_DCFG3_CFG1 0x4000408d\r
+#define CYDEV_CLKDIST_DCFG3_CFG2 0x4000408e\r
+#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090\r
+#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003\r
+#define CYDEV_CLKDIST_DCFG4_CFG0 0x40004090\r
+#define CYDEV_CLKDIST_DCFG4_CFG1 0x40004091\r
+#define CYDEV_CLKDIST_DCFG4_CFG2 0x40004092\r
+#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094\r
+#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003\r
+#define CYDEV_CLKDIST_DCFG5_CFG0 0x40004094\r
+#define CYDEV_CLKDIST_DCFG5_CFG1 0x40004095\r
+#define CYDEV_CLKDIST_DCFG5_CFG2 0x40004096\r
+#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098\r
+#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003\r
+#define CYDEV_CLKDIST_DCFG6_CFG0 0x40004098\r
+#define CYDEV_CLKDIST_DCFG6_CFG1 0x40004099\r
+#define CYDEV_CLKDIST_DCFG6_CFG2 0x4000409a\r
+#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409c\r
+#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003\r
+#define CYDEV_CLKDIST_DCFG7_CFG0 0x4000409c\r
+#define CYDEV_CLKDIST_DCFG7_CFG1 0x4000409d\r
+#define CYDEV_CLKDIST_DCFG7_CFG2 0x4000409e\r
+#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100\r
+#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004\r
+#define CYDEV_CLKDIST_ACFG0_CFG0 0x40004100\r
+#define CYDEV_CLKDIST_ACFG0_CFG1 0x40004101\r
+#define CYDEV_CLKDIST_ACFG0_CFG2 0x40004102\r
+#define CYDEV_CLKDIST_ACFG0_CFG3 0x40004103\r
+#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104\r
+#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004\r
+#define CYDEV_CLKDIST_ACFG1_CFG0 0x40004104\r
+#define CYDEV_CLKDIST_ACFG1_CFG1 0x40004105\r
+#define CYDEV_CLKDIST_ACFG1_CFG2 0x40004106\r
+#define CYDEV_CLKDIST_ACFG1_CFG3 0x40004107\r
+#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108\r
+#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004\r
+#define CYDEV_CLKDIST_ACFG2_CFG0 0x40004108\r
+#define CYDEV_CLKDIST_ACFG2_CFG1 0x40004109\r
+#define CYDEV_CLKDIST_ACFG2_CFG2 0x4000410a\r
+#define CYDEV_CLKDIST_ACFG2_CFG3 0x4000410b\r
+#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410c\r
+#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004\r
+#define CYDEV_CLKDIST_ACFG3_CFG0 0x4000410c\r
+#define CYDEV_CLKDIST_ACFG3_CFG1 0x4000410d\r
+#define CYDEV_CLKDIST_ACFG3_CFG2 0x4000410e\r
+#define CYDEV_CLKDIST_ACFG3_CFG3 0x4000410f\r
+#define CYDEV_FASTCLK_BASE 0x40004200\r
+#define CYDEV_FASTCLK_SIZE 0x00000026\r
+#define CYDEV_FASTCLK_IMO_BASE 0x40004200\r
+#define CYDEV_FASTCLK_IMO_SIZE 0x00000001\r
+#define CYDEV_FASTCLK_IMO_CR 0x40004200\r
+#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210\r
+#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004\r
+#define CYDEV_FASTCLK_XMHZ_CSR 0x40004210\r
+#define CYDEV_FASTCLK_XMHZ_CFG0 0x40004212\r
+#define CYDEV_FASTCLK_XMHZ_CFG1 0x40004213\r
+#define CYDEV_FASTCLK_PLL_BASE 0x40004220\r
+#define CYDEV_FASTCLK_PLL_SIZE 0x00000006\r
+#define CYDEV_FASTCLK_PLL_CFG0 0x40004220\r
+#define CYDEV_FASTCLK_PLL_CFG1 0x40004221\r
+#define CYDEV_FASTCLK_PLL_P 0x40004222\r
+#define CYDEV_FASTCLK_PLL_Q 0x40004223\r
+#define CYDEV_FASTCLK_PLL_SR 0x40004225\r
+#define CYDEV_SLOWCLK_BASE 0x40004300\r
+#define CYDEV_SLOWCLK_SIZE 0x0000000b\r
+#define CYDEV_SLOWCLK_ILO_BASE 0x40004300\r
+#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002\r
+#define CYDEV_SLOWCLK_ILO_CR0 0x40004300\r
+#define CYDEV_SLOWCLK_ILO_CR1 0x40004301\r
+#define CYDEV_SLOWCLK_X32_BASE 0x40004308\r
+#define CYDEV_SLOWCLK_X32_SIZE 0x00000003\r
+#define CYDEV_SLOWCLK_X32_CR 0x40004308\r
+#define CYDEV_SLOWCLK_X32_CFG 0x40004309\r
+#define CYDEV_SLOWCLK_X32_TST 0x4000430a\r
+#define CYDEV_BOOST_BASE 0x40004320\r
+#define CYDEV_BOOST_SIZE 0x00000007\r
+#define CYDEV_BOOST_CR0 0x40004320\r
+#define CYDEV_BOOST_CR1 0x40004321\r
+#define CYDEV_BOOST_CR2 0x40004322\r
+#define CYDEV_BOOST_CR3 0x40004323\r
+#define CYDEV_BOOST_SR 0x40004324\r
+#define CYDEV_BOOST_CR4 0x40004325\r
+#define CYDEV_BOOST_SR2 0x40004326\r
+#define CYDEV_PWRSYS_BASE 0x40004330\r
+#define CYDEV_PWRSYS_SIZE 0x00000002\r
+#define CYDEV_PWRSYS_CR0 0x40004330\r
+#define CYDEV_PWRSYS_CR1 0x40004331\r
+#define CYDEV_PM_BASE 0x40004380\r
+#define CYDEV_PM_SIZE 0x00000057\r
+#define CYDEV_PM_TW_CFG0 0x40004380\r
+#define CYDEV_PM_TW_CFG1 0x40004381\r
+#define CYDEV_PM_TW_CFG2 0x40004382\r
+#define CYDEV_PM_WDT_CFG 0x40004383\r
+#define CYDEV_PM_WDT_CR 0x40004384\r
+#define CYDEV_PM_INT_SR 0x40004390\r
+#define CYDEV_PM_MODE_CFG0 0x40004391\r
+#define CYDEV_PM_MODE_CFG1 0x40004392\r
+#define CYDEV_PM_MODE_CSR 0x40004393\r
+#define CYDEV_PM_USB_CR0 0x40004394\r
+#define CYDEV_PM_WAKEUP_CFG0 0x40004398\r
+#define CYDEV_PM_WAKEUP_CFG1 0x40004399\r
+#define CYDEV_PM_WAKEUP_CFG2 0x4000439a\r
+#define CYDEV_PM_ACT_BASE 0x400043a0\r
+#define CYDEV_PM_ACT_SIZE 0x0000000e\r
+#define CYDEV_PM_ACT_CFG0 0x400043a0\r
+#define CYDEV_PM_ACT_CFG1 0x400043a1\r
+#define CYDEV_PM_ACT_CFG2 0x400043a2\r
+#define CYDEV_PM_ACT_CFG3 0x400043a3\r
+#define CYDEV_PM_ACT_CFG4 0x400043a4\r
+#define CYDEV_PM_ACT_CFG5 0x400043a5\r
+#define CYDEV_PM_ACT_CFG6 0x400043a6\r
+#define CYDEV_PM_ACT_CFG7 0x400043a7\r
+#define CYDEV_PM_ACT_CFG8 0x400043a8\r
+#define CYDEV_PM_ACT_CFG9 0x400043a9\r
+#define CYDEV_PM_ACT_CFG10 0x400043aa\r
+#define CYDEV_PM_ACT_CFG11 0x400043ab\r
+#define CYDEV_PM_ACT_CFG12 0x400043ac\r
+#define CYDEV_PM_ACT_CFG13 0x400043ad\r
+#define CYDEV_PM_STBY_BASE 0x400043b0\r
+#define CYDEV_PM_STBY_SIZE 0x0000000e\r
+#define CYDEV_PM_STBY_CFG0 0x400043b0\r
+#define CYDEV_PM_STBY_CFG1 0x400043b1\r
+#define CYDEV_PM_STBY_CFG2 0x400043b2\r
+#define CYDEV_PM_STBY_CFG3 0x400043b3\r
+#define CYDEV_PM_STBY_CFG4 0x400043b4\r
+#define CYDEV_PM_STBY_CFG5 0x400043b5\r
+#define CYDEV_PM_STBY_CFG6 0x400043b6\r
+#define CYDEV_PM_STBY_CFG7 0x400043b7\r
+#define CYDEV_PM_STBY_CFG8 0x400043b8\r
+#define CYDEV_PM_STBY_CFG9 0x400043b9\r
+#define CYDEV_PM_STBY_CFG10 0x400043ba\r
+#define CYDEV_PM_STBY_CFG11 0x400043bb\r
+#define CYDEV_PM_STBY_CFG12 0x400043bc\r
+#define CYDEV_PM_STBY_CFG13 0x400043bd\r
+#define CYDEV_PM_AVAIL_BASE 0x400043c0\r
+#define CYDEV_PM_AVAIL_SIZE 0x00000017\r
+#define CYDEV_PM_AVAIL_CR0 0x400043c0\r
+#define CYDEV_PM_AVAIL_CR1 0x400043c1\r
+#define CYDEV_PM_AVAIL_CR2 0x400043c2\r
+#define CYDEV_PM_AVAIL_CR3 0x400043c3\r
+#define CYDEV_PM_AVAIL_CR4 0x400043c4\r
+#define CYDEV_PM_AVAIL_CR5 0x400043c5\r
+#define CYDEV_PM_AVAIL_CR6 0x400043c6\r
+#define CYDEV_PM_AVAIL_SR0 0x400043d0\r
+#define CYDEV_PM_AVAIL_SR1 0x400043d1\r
+#define CYDEV_PM_AVAIL_SR2 0x400043d2\r
+#define CYDEV_PM_AVAIL_SR3 0x400043d3\r
+#define CYDEV_PM_AVAIL_SR4 0x400043d4\r
+#define CYDEV_PM_AVAIL_SR5 0x400043d5\r
+#define CYDEV_PM_AVAIL_SR6 0x400043d6\r
+#define CYDEV_PICU_BASE 0x40004500\r
+#define CYDEV_PICU_SIZE 0x000000b0\r
+#define CYDEV_PICU_INTTYPE_BASE 0x40004500\r
+#define CYDEV_PICU_INTTYPE_SIZE 0x00000080\r
+#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500\r
+#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008\r
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 0x40004500\r
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 0x40004501\r
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 0x40004502\r
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 0x40004503\r
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 0x40004504\r
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 0x40004505\r
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 0x40004506\r
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 0x40004507\r
+#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508\r
+#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008\r
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 0x40004508\r
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 0x40004509\r
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 0x4000450a\r
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 0x4000450b\r
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 0x4000450c\r
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 0x4000450d\r
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 0x4000450e\r
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 0x4000450f\r
+#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510\r
+#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008\r
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 0x40004510\r
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 0x40004511\r
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 0x40004512\r
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 0x40004513\r
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 0x40004514\r
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 0x40004515\r
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 0x40004516\r
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 0x40004517\r
+#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518\r
+#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008\r
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 0x40004518\r
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 0x40004519\r
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 0x4000451a\r
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 0x4000451b\r
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 0x4000451c\r
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 0x4000451d\r
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 0x4000451e\r
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 0x4000451f\r
+#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520\r
+#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008\r
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 0x40004520\r
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 0x40004521\r
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 0x40004522\r
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 0x40004523\r
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 0x40004524\r
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 0x40004525\r
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 0x40004526\r
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 0x40004527\r
+#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528\r
+#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008\r
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 0x40004528\r
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 0x40004529\r
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 0x4000452a\r
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 0x4000452b\r
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 0x4000452c\r
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 0x4000452d\r
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 0x4000452e\r
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 0x4000452f\r
+#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530\r
+#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008\r
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 0x40004530\r
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 0x40004531\r
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 0x40004532\r
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 0x40004533\r
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 0x40004534\r
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 0x40004535\r
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 0x40004536\r
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 0x40004537\r
+#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560\r
+#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008\r
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 0x40004560\r
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 0x40004561\r
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 0x40004562\r
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 0x40004563\r
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 0x40004564\r
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 0x40004565\r
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 0x40004566\r
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 0x40004567\r
+#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578\r
+#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008\r
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 0x40004578\r
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 0x40004579\r
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 0x4000457a\r
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 0x4000457b\r
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 0x4000457c\r
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 0x4000457d\r
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 0x4000457e\r
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 0x4000457f\r
+#define CYDEV_PICU_STAT_BASE 0x40004580\r
+#define CYDEV_PICU_STAT_SIZE 0x00000010\r
+#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580\r
+#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001\r
+#define CYDEV_PICU_STAT_PICU0_INTSTAT 0x40004580\r
+#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581\r
+#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001\r
+#define CYDEV_PICU_STAT_PICU1_INTSTAT 0x40004581\r
+#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582\r
+#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001\r
+#define CYDEV_PICU_STAT_PICU2_INTSTAT 0x40004582\r
+#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583\r
+#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001\r
+#define CYDEV_PICU_STAT_PICU3_INTSTAT 0x40004583\r
+#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584\r
+#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001\r
+#define CYDEV_PICU_STAT_PICU4_INTSTAT 0x40004584\r
+#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585\r
+#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001\r
+#define CYDEV_PICU_STAT_PICU5_INTSTAT 0x40004585\r
+#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586\r
+#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001\r
+#define CYDEV_PICU_STAT_PICU6_INTSTAT 0x40004586\r
+#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458c\r
+#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001\r
+#define CYDEV_PICU_STAT_PICU12_INTSTAT 0x4000458c\r
+#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458f\r
+#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001\r
+#define CYDEV_PICU_STAT_PICU15_INTSTAT 0x4000458f\r
+#define CYDEV_PICU_SNAP_BASE 0x40004590\r
+#define CYDEV_PICU_SNAP_SIZE 0x00000010\r
+#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590\r
+#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001\r
+#define CYDEV_PICU_SNAP_PICU0_SNAP 0x40004590\r
+#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591\r
+#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001\r
+#define CYDEV_PICU_SNAP_PICU1_SNAP 0x40004591\r
+#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592\r
+#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001\r
+#define CYDEV_PICU_SNAP_PICU2_SNAP 0x40004592\r
+#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593\r
+#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001\r
+#define CYDEV_PICU_SNAP_PICU3_SNAP 0x40004593\r
+#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594\r
+#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001\r
+#define CYDEV_PICU_SNAP_PICU4_SNAP 0x40004594\r
+#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595\r
+#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001\r
+#define CYDEV_PICU_SNAP_PICU5_SNAP 0x40004595\r
+#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596\r
+#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001\r
+#define CYDEV_PICU_SNAP_PICU6_SNAP 0x40004596\r
+#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459c\r
+#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001\r
+#define CYDEV_PICU_SNAP_PICU12_SNAP 0x4000459c\r
+#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459f\r
+#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001\r
+#define CYDEV_PICU_SNAP_PICU_15_SNAP_15 0x4000459f\r
+#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0\r
+#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010\r
+#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0\r
+#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001\r
+#define CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR 0x400045a0\r
+#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1\r
+#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001\r
+#define CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR 0x400045a1\r
+#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2\r
+#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001\r
+#define CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR 0x400045a2\r
+#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3\r
+#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001\r
+#define CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR 0x400045a3\r
+#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4\r
+#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001\r
+#define CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR 0x400045a4\r
+#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5\r
+#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001\r
+#define CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR 0x400045a5\r
+#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6\r
+#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001\r
+#define CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR 0x400045a6\r
+#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045ac\r
+#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001\r
+#define CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR 0x400045ac\r
+#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045af\r
+#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001\r
+#define CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR 0x400045af\r
+#define CYDEV_MFGCFG_BASE 0x40004600\r
+#define CYDEV_MFGCFG_SIZE 0x000000ed\r
+#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600\r
+#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038\r
+#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608\r
+#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001\r
+#define CYDEV_MFGCFG_ANAIF_DAC0_TR 0x40004608\r
+#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609\r
+#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001\r
+#define CYDEV_MFGCFG_ANAIF_DAC1_TR 0x40004609\r
+#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460a\r
+#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001\r
+#define CYDEV_MFGCFG_ANAIF_DAC2_TR 0x4000460a\r
+#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460b\r
+#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001\r
+#define CYDEV_MFGCFG_ANAIF_DAC3_TR 0x4000460b\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 0x40004610\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 0x40004611\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 0x40004612\r
+#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614\r
+#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001\r
+#define CYDEV_MFGCFG_ANAIF_SAR0_TR0 0x40004614\r
+#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616\r
+#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001\r
+#define CYDEV_MFGCFG_ANAIF_SAR1_TR0 0x40004616\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 0x40004620\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 0x40004621\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 0x40004622\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 0x40004623\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 0x40004624\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 0x40004625\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 0x40004626\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 0x40004627\r
+#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630\r
+#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002\r
+#define CYDEV_MFGCFG_ANAIF_CMP0_TR0 0x40004630\r
+#define CYDEV_MFGCFG_ANAIF_CMP0_TR1 0x40004631\r
+#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632\r
+#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002\r
+#define CYDEV_MFGCFG_ANAIF_CMP1_TR0 0x40004632\r
+#define CYDEV_MFGCFG_ANAIF_CMP1_TR1 0x40004633\r
+#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634\r
+#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002\r
+#define CYDEV_MFGCFG_ANAIF_CMP2_TR0 0x40004634\r
+#define CYDEV_MFGCFG_ANAIF_CMP2_TR1 0x40004635\r
+#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636\r
+#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002\r
+#define CYDEV_MFGCFG_ANAIF_CMP3_TR0 0x40004636\r
+#define CYDEV_MFGCFG_ANAIF_CMP3_TR1 0x40004637\r
+#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680\r
+#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000b\r
+#define CYDEV_MFGCFG_PWRSYS_HIB_TR0 0x40004680\r
+#define CYDEV_MFGCFG_PWRSYS_HIB_TR1 0x40004681\r
+#define CYDEV_MFGCFG_PWRSYS_I2C_TR 0x40004682\r
+#define CYDEV_MFGCFG_PWRSYS_SLP_TR 0x40004683\r
+#define CYDEV_MFGCFG_PWRSYS_BUZZ_TR 0x40004684\r
+#define CYDEV_MFGCFG_PWRSYS_WAKE_TR0 0x40004685\r
+#define CYDEV_MFGCFG_PWRSYS_WAKE_TR1 0x40004686\r
+#define CYDEV_MFGCFG_PWRSYS_BREF_TR 0x40004687\r
+#define CYDEV_MFGCFG_PWRSYS_BG_TR 0x40004688\r
+#define CYDEV_MFGCFG_PWRSYS_WAKE_TR2 0x40004689\r
+#define CYDEV_MFGCFG_PWRSYS_WAKE_TR3 0x4000468a\r
+#define CYDEV_MFGCFG_ILO_BASE 0x40004690\r
+#define CYDEV_MFGCFG_ILO_SIZE 0x00000002\r
+#define CYDEV_MFGCFG_ILO_TR0 0x40004690\r
+#define CYDEV_MFGCFG_ILO_TR1 0x40004691\r
+#define CYDEV_MFGCFG_X32_BASE 0x40004698\r
+#define CYDEV_MFGCFG_X32_SIZE 0x00000001\r
+#define CYDEV_MFGCFG_X32_TR 0x40004698\r
+#define CYDEV_MFGCFG_IMO_BASE 0x400046a0\r
+#define CYDEV_MFGCFG_IMO_SIZE 0x00000005\r
+#define CYDEV_MFGCFG_IMO_TR0 0x400046a0\r
+#define CYDEV_MFGCFG_IMO_TR1 0x400046a1\r
+#define CYDEV_MFGCFG_IMO_GAIN 0x400046a2\r
+#define CYDEV_MFGCFG_IMO_C36M 0x400046a3\r
+#define CYDEV_MFGCFG_IMO_TR2 0x400046a4\r
+#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8\r
+#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001\r
+#define CYDEV_MFGCFG_XMHZ_TR 0x400046a8\r
+#define CYDEV_MFGCFG_DLY 0x400046c0\r
+#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0\r
+#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000d\r
+#define CYDEV_MFGCFG_MLOGIC_DMPSTR 0x400046e2\r
+#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4\r
+#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002\r
+#define CYDEV_MFGCFG_MLOGIC_SEG_CR 0x400046e4\r
+#define CYDEV_MFGCFG_MLOGIC_SEG_CFG0 0x400046e5\r
+#define CYDEV_MFGCFG_MLOGIC_DEBUG 0x400046e8\r
+#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046ea\r
+#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001\r
+#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR 0x400046ea\r
+#define CYDEV_MFGCFG_MLOGIC_REV_ID 0x400046ec\r
+#define CYDEV_RESET_BASE 0x400046f0\r
+#define CYDEV_RESET_SIZE 0x0000000f\r
+#define CYDEV_RESET_IPOR_CR0 0x400046f0\r
+#define CYDEV_RESET_IPOR_CR1 0x400046f1\r
+#define CYDEV_RESET_IPOR_CR2 0x400046f2\r
+#define CYDEV_RESET_IPOR_CR3 0x400046f3\r
+#define CYDEV_RESET_CR0 0x400046f4\r
+#define CYDEV_RESET_CR1 0x400046f5\r
+#define CYDEV_RESET_CR2 0x400046f6\r
+#define CYDEV_RESET_CR3 0x400046f7\r
+#define CYDEV_RESET_CR4 0x400046f8\r
+#define CYDEV_RESET_CR5 0x400046f9\r
+#define CYDEV_RESET_SR0 0x400046fa\r
+#define CYDEV_RESET_SR1 0x400046fb\r
+#define CYDEV_RESET_SR2 0x400046fc\r
+#define CYDEV_RESET_SR3 0x400046fd\r
+#define CYDEV_RESET_TR 0x400046fe\r
+#define CYDEV_SPC_BASE 0x40004700\r
+#define CYDEV_SPC_SIZE 0x00000100\r
+#define CYDEV_SPC_FM_EE_CR 0x40004700\r
+#define CYDEV_SPC_FM_EE_WAKE_CNT 0x40004701\r
+#define CYDEV_SPC_EE_SCR 0x40004702\r
+#define CYDEV_SPC_EE_ERR 0x40004703\r
+#define CYDEV_SPC_CPU_DATA 0x40004720\r
+#define CYDEV_SPC_DMA_DATA 0x40004721\r
+#define CYDEV_SPC_SR 0x40004722\r
+#define CYDEV_SPC_CR 0x40004723\r
+#define CYDEV_SPC_DMM_MAP_BASE 0x40004780\r
+#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080\r
+#define CYDEV_SPC_DMM_MAP_SRAM_MBASE 0x40004780\r
+#define CYDEV_SPC_DMM_MAP_SRAM_MSIZE 0x00000080\r
+#define CYDEV_CACHE_BASE 0x40004800\r
+#define CYDEV_CACHE_SIZE 0x0000009c\r
+#define CYDEV_CACHE_CC_CTL 0x40004800\r
+#define CYDEV_CACHE_ECC_CORR 0x40004880\r
+#define CYDEV_CACHE_ECC_ERR 0x40004888\r
+#define CYDEV_CACHE_FLASH_ERR 0x40004890\r
+#define CYDEV_CACHE_HITMISS 0x40004898\r
+#define CYDEV_I2C_BASE 0x40004900\r
+#define CYDEV_I2C_SIZE 0x000000e1\r
+#define CYDEV_I2C_XCFG 0x400049c8\r
+#define CYDEV_I2C_ADR 0x400049ca\r
+#define CYDEV_I2C_CFG 0x400049d6\r
+#define CYDEV_I2C_CSR 0x400049d7\r
+#define CYDEV_I2C_D 0x400049d8\r
+#define CYDEV_I2C_MCSR 0x400049d9\r
+#define CYDEV_I2C_CLK_DIV1 0x400049db\r
+#define CYDEV_I2C_CLK_DIV2 0x400049dc\r
+#define CYDEV_I2C_TMOUT_CSR 0x400049dd\r
+#define CYDEV_I2C_TMOUT_SR 0x400049de\r
+#define CYDEV_I2C_TMOUT_CFG0 0x400049df\r
+#define CYDEV_I2C_TMOUT_CFG1 0x400049e0\r
+#define CYDEV_DEC_BASE 0x40004e00\r
+#define CYDEV_DEC_SIZE 0x00000015\r
+#define CYDEV_DEC_CR 0x40004e00\r
+#define CYDEV_DEC_SR 0x40004e01\r
+#define CYDEV_DEC_SHIFT1 0x40004e02\r
+#define CYDEV_DEC_SHIFT2 0x40004e03\r
+#define CYDEV_DEC_DR2 0x40004e04\r
+#define CYDEV_DEC_DR2H 0x40004e05\r
+#define CYDEV_DEC_DR1 0x40004e06\r
+#define CYDEV_DEC_OCOR 0x40004e08\r
+#define CYDEV_DEC_OCORM 0x40004e09\r
+#define CYDEV_DEC_OCORH 0x40004e0a\r
+#define CYDEV_DEC_GCOR 0x40004e0c\r
+#define CYDEV_DEC_GCORH 0x40004e0d\r
+#define CYDEV_DEC_GVAL 0x40004e0e\r
+#define CYDEV_DEC_OUTSAMP 0x40004e10\r
+#define CYDEV_DEC_OUTSAMPM 0x40004e11\r
+#define CYDEV_DEC_OUTSAMPH 0x40004e12\r
+#define CYDEV_DEC_OUTSAMPS 0x40004e13\r
+#define CYDEV_DEC_COHER 0x40004e14\r
+#define CYDEV_TMR0_BASE 0x40004f00\r
+#define CYDEV_TMR0_SIZE 0x0000000c\r
+#define CYDEV_TMR0_CFG0 0x40004f00\r
+#define CYDEV_TMR0_CFG1 0x40004f01\r
+#define CYDEV_TMR0_CFG2 0x40004f02\r
+#define CYDEV_TMR0_SR0 0x40004f03\r
+#define CYDEV_TMR0_PER0 0x40004f04\r
+#define CYDEV_TMR0_PER1 0x40004f05\r
+#define CYDEV_TMR0_CNT_CMP0 0x40004f06\r
+#define CYDEV_TMR0_CNT_CMP1 0x40004f07\r
+#define CYDEV_TMR0_CAP0 0x40004f08\r
+#define CYDEV_TMR0_CAP1 0x40004f09\r
+#define CYDEV_TMR0_RT0 0x40004f0a\r
+#define CYDEV_TMR0_RT1 0x40004f0b\r
+#define CYDEV_TMR1_BASE 0x40004f0c\r
+#define CYDEV_TMR1_SIZE 0x0000000c\r
+#define CYDEV_TMR1_CFG0 0x40004f0c\r
+#define CYDEV_TMR1_CFG1 0x40004f0d\r
+#define CYDEV_TMR1_CFG2 0x40004f0e\r
+#define CYDEV_TMR1_SR0 0x40004f0f\r
+#define CYDEV_TMR1_PER0 0x40004f10\r
+#define CYDEV_TMR1_PER1 0x40004f11\r
+#define CYDEV_TMR1_CNT_CMP0 0x40004f12\r
+#define CYDEV_TMR1_CNT_CMP1 0x40004f13\r
+#define CYDEV_TMR1_CAP0 0x40004f14\r
+#define CYDEV_TMR1_CAP1 0x40004f15\r
+#define CYDEV_TMR1_RT0 0x40004f16\r
+#define CYDEV_TMR1_RT1 0x40004f17\r
+#define CYDEV_TMR2_BASE 0x40004f18\r
+#define CYDEV_TMR2_SIZE 0x0000000c\r
+#define CYDEV_TMR2_CFG0 0x40004f18\r
+#define CYDEV_TMR2_CFG1 0x40004f19\r
+#define CYDEV_TMR2_CFG2 0x40004f1a\r
+#define CYDEV_TMR2_SR0 0x40004f1b\r
+#define CYDEV_TMR2_PER0 0x40004f1c\r
+#define CYDEV_TMR2_PER1 0x40004f1d\r
+#define CYDEV_TMR2_CNT_CMP0 0x40004f1e\r
+#define CYDEV_TMR2_CNT_CMP1 0x40004f1f\r
+#define CYDEV_TMR2_CAP0 0x40004f20\r
+#define CYDEV_TMR2_CAP1 0x40004f21\r
+#define CYDEV_TMR2_RT0 0x40004f22\r
+#define CYDEV_TMR2_RT1 0x40004f23\r
+#define CYDEV_TMR3_BASE 0x40004f24\r
+#define CYDEV_TMR3_SIZE 0x0000000c\r
+#define CYDEV_TMR3_CFG0 0x40004f24\r
+#define CYDEV_TMR3_CFG1 0x40004f25\r
+#define CYDEV_TMR3_CFG2 0x40004f26\r
+#define CYDEV_TMR3_SR0 0x40004f27\r
+#define CYDEV_TMR3_PER0 0x40004f28\r
+#define CYDEV_TMR3_PER1 0x40004f29\r
+#define CYDEV_TMR3_CNT_CMP0 0x40004f2a\r
+#define CYDEV_TMR3_CNT_CMP1 0x40004f2b\r
+#define CYDEV_TMR3_CAP0 0x40004f2c\r
+#define CYDEV_TMR3_CAP1 0x40004f2d\r
+#define CYDEV_TMR3_RT0 0x40004f2e\r
+#define CYDEV_TMR3_RT1 0x40004f2f\r
+#define CYDEV_IO_BASE 0x40005000\r
+#define CYDEV_IO_SIZE 0x00000200\r
+#define CYDEV_IO_PC_BASE 0x40005000\r
+#define CYDEV_IO_PC_SIZE 0x00000080\r
+#define CYDEV_IO_PC_PRT0_BASE 0x40005000\r
+#define CYDEV_IO_PC_PRT0_SIZE 0x00000008\r
+#define CYDEV_IO_PC_PRT0_PC0 0x40005000\r
+#define CYDEV_IO_PC_PRT0_PC1 0x40005001\r
+#define CYDEV_IO_PC_PRT0_PC2 0x40005002\r
+#define CYDEV_IO_PC_PRT0_PC3 0x40005003\r
+#define CYDEV_IO_PC_PRT0_PC4 0x40005004\r
+#define CYDEV_IO_PC_PRT0_PC5 0x40005005\r
+#define CYDEV_IO_PC_PRT0_PC6 0x40005006\r
+#define CYDEV_IO_PC_PRT0_PC7 0x40005007\r
+#define CYDEV_IO_PC_PRT1_BASE 0x40005008\r
+#define CYDEV_IO_PC_PRT1_SIZE 0x00000008\r
+#define CYDEV_IO_PC_PRT1_PC0 0x40005008\r
+#define CYDEV_IO_PC_PRT1_PC1 0x40005009\r
+#define CYDEV_IO_PC_PRT1_PC2 0x4000500a\r
+#define CYDEV_IO_PC_PRT1_PC3 0x4000500b\r
+#define CYDEV_IO_PC_PRT1_PC4 0x4000500c\r
+#define CYDEV_IO_PC_PRT1_PC5 0x4000500d\r
+#define CYDEV_IO_PC_PRT1_PC6 0x4000500e\r
+#define CYDEV_IO_PC_PRT1_PC7 0x4000500f\r
+#define CYDEV_IO_PC_PRT2_BASE 0x40005010\r
+#define CYDEV_IO_PC_PRT2_SIZE 0x00000008\r
+#define CYDEV_IO_PC_PRT2_PC0 0x40005010\r
+#define CYDEV_IO_PC_PRT2_PC1 0x40005011\r
+#define CYDEV_IO_PC_PRT2_PC2 0x40005012\r
+#define CYDEV_IO_PC_PRT2_PC3 0x40005013\r
+#define CYDEV_IO_PC_PRT2_PC4 0x40005014\r
+#define CYDEV_IO_PC_PRT2_PC5 0x40005015\r
+#define CYDEV_IO_PC_PRT2_PC6 0x40005016\r
+#define CYDEV_IO_PC_PRT2_PC7 0x40005017\r
+#define CYDEV_IO_PC_PRT3_BASE 0x40005018\r
+#define CYDEV_IO_PC_PRT3_SIZE 0x00000008\r
+#define CYDEV_IO_PC_PRT3_PC0 0x40005018\r
+#define CYDEV_IO_PC_PRT3_PC1 0x40005019\r
+#define CYDEV_IO_PC_PRT3_PC2 0x4000501a\r
+#define CYDEV_IO_PC_PRT3_PC3 0x4000501b\r
+#define CYDEV_IO_PC_PRT3_PC4 0x4000501c\r
+#define CYDEV_IO_PC_PRT3_PC5 0x4000501d\r
+#define CYDEV_IO_PC_PRT3_PC6 0x4000501e\r
+#define CYDEV_IO_PC_PRT3_PC7 0x4000501f\r
+#define CYDEV_IO_PC_PRT4_BASE 0x40005020\r
+#define CYDEV_IO_PC_PRT4_SIZE 0x00000008\r
+#define CYDEV_IO_PC_PRT4_PC0 0x40005020\r
+#define CYDEV_IO_PC_PRT4_PC1 0x40005021\r
+#define CYDEV_IO_PC_PRT4_PC2 0x40005022\r
+#define CYDEV_IO_PC_PRT4_PC3 0x40005023\r
+#define CYDEV_IO_PC_PRT4_PC4 0x40005024\r
+#define CYDEV_IO_PC_PRT4_PC5 0x40005025\r
+#define CYDEV_IO_PC_PRT4_PC6 0x40005026\r
+#define CYDEV_IO_PC_PRT4_PC7 0x40005027\r
+#define CYDEV_IO_PC_PRT5_BASE 0x40005028\r
+#define CYDEV_IO_PC_PRT5_SIZE 0x00000008\r
+#define CYDEV_IO_PC_PRT5_PC0 0x40005028\r
+#define CYDEV_IO_PC_PRT5_PC1 0x40005029\r
+#define CYDEV_IO_PC_PRT5_PC2 0x4000502a\r
+#define CYDEV_IO_PC_PRT5_PC3 0x4000502b\r
+#define CYDEV_IO_PC_PRT5_PC4 0x4000502c\r
+#define CYDEV_IO_PC_PRT5_PC5 0x4000502d\r
+#define CYDEV_IO_PC_PRT5_PC6 0x4000502e\r
+#define CYDEV_IO_PC_PRT5_PC7 0x4000502f\r
+#define CYDEV_IO_PC_PRT6_BASE 0x40005030\r
+#define CYDEV_IO_PC_PRT6_SIZE 0x00000008\r
+#define CYDEV_IO_PC_PRT6_PC0 0x40005030\r
+#define CYDEV_IO_PC_PRT6_PC1 0x40005031\r
+#define CYDEV_IO_PC_PRT6_PC2 0x40005032\r
+#define CYDEV_IO_PC_PRT6_PC3 0x40005033\r
+#define CYDEV_IO_PC_PRT6_PC4 0x40005034\r
+#define CYDEV_IO_PC_PRT6_PC5 0x40005035\r
+#define CYDEV_IO_PC_PRT6_PC6 0x40005036\r
+#define CYDEV_IO_PC_PRT6_PC7 0x40005037\r
+#define CYDEV_IO_PC_PRT12_BASE 0x40005060\r
+#define CYDEV_IO_PC_PRT12_SIZE 0x00000008\r
+#define CYDEV_IO_PC_PRT12_PC0 0x40005060\r
+#define CYDEV_IO_PC_PRT12_PC1 0x40005061\r
+#define CYDEV_IO_PC_PRT12_PC2 0x40005062\r
+#define CYDEV_IO_PC_PRT12_PC3 0x40005063\r
+#define CYDEV_IO_PC_PRT12_PC4 0x40005064\r
+#define CYDEV_IO_PC_PRT12_PC5 0x40005065\r
+#define CYDEV_IO_PC_PRT12_PC6 0x40005066\r
+#define CYDEV_IO_PC_PRT12_PC7 0x40005067\r
+#define CYDEV_IO_PC_PRT15_BASE 0x40005078\r
+#define CYDEV_IO_PC_PRT15_SIZE 0x00000006\r
+#define CYDEV_IO_PC_PRT15_PC0 0x40005078\r
+#define CYDEV_IO_PC_PRT15_PC1 0x40005079\r
+#define CYDEV_IO_PC_PRT15_PC2 0x4000507a\r
+#define CYDEV_IO_PC_PRT15_PC3 0x4000507b\r
+#define CYDEV_IO_PC_PRT15_PC4 0x4000507c\r
+#define CYDEV_IO_PC_PRT15_PC5 0x4000507d\r
+#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507e\r
+#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002\r
+#define CYDEV_IO_PC_PRT15_7_6_PC0 0x4000507e\r
+#define CYDEV_IO_PC_PRT15_7_6_PC1 0x4000507f\r
+#define CYDEV_IO_DR_BASE 0x40005080\r
+#define CYDEV_IO_DR_SIZE 0x00000010\r
+#define CYDEV_IO_DR_PRT0_BASE 0x40005080\r
+#define CYDEV_IO_DR_PRT0_SIZE 0x00000001\r
+#define CYDEV_IO_DR_PRT0_DR_ALIAS 0x40005080\r
+#define CYDEV_IO_DR_PRT1_BASE 0x40005081\r
+#define CYDEV_IO_DR_PRT1_SIZE 0x00000001\r
+#define CYDEV_IO_DR_PRT1_DR_ALIAS 0x40005081\r
+#define CYDEV_IO_DR_PRT2_BASE 0x40005082\r
+#define CYDEV_IO_DR_PRT2_SIZE 0x00000001\r
+#define CYDEV_IO_DR_PRT2_DR_ALIAS 0x40005082\r
+#define CYDEV_IO_DR_PRT3_BASE 0x40005083\r
+#define CYDEV_IO_DR_PRT3_SIZE 0x00000001\r
+#define CYDEV_IO_DR_PRT3_DR_ALIAS 0x40005083\r
+#define CYDEV_IO_DR_PRT4_BASE 0x40005084\r
+#define CYDEV_IO_DR_PRT4_SIZE 0x00000001\r
+#define CYDEV_IO_DR_PRT4_DR_ALIAS 0x40005084\r
+#define CYDEV_IO_DR_PRT5_BASE 0x40005085\r
+#define CYDEV_IO_DR_PRT5_SIZE 0x00000001\r
+#define CYDEV_IO_DR_PRT5_DR_ALIAS 0x40005085\r
+#define CYDEV_IO_DR_PRT6_BASE 0x40005086\r
+#define CYDEV_IO_DR_PRT6_SIZE 0x00000001\r
+#define CYDEV_IO_DR_PRT6_DR_ALIAS 0x40005086\r
+#define CYDEV_IO_DR_PRT12_BASE 0x4000508c\r
+#define CYDEV_IO_DR_PRT12_SIZE 0x00000001\r
+#define CYDEV_IO_DR_PRT12_DR_ALIAS 0x4000508c\r
+#define CYDEV_IO_DR_PRT15_BASE 0x4000508f\r
+#define CYDEV_IO_DR_PRT15_SIZE 0x00000001\r
+#define CYDEV_IO_DR_PRT15_DR_15_ALIAS 0x4000508f\r
+#define CYDEV_IO_PS_BASE 0x40005090\r
+#define CYDEV_IO_PS_SIZE 0x00000010\r
+#define CYDEV_IO_PS_PRT0_BASE 0x40005090\r
+#define CYDEV_IO_PS_PRT0_SIZE 0x00000001\r
+#define CYDEV_IO_PS_PRT0_PS_ALIAS 0x40005090\r
+#define CYDEV_IO_PS_PRT1_BASE 0x40005091\r
+#define CYDEV_IO_PS_PRT1_SIZE 0x00000001\r
+#define CYDEV_IO_PS_PRT1_PS_ALIAS 0x40005091\r
+#define CYDEV_IO_PS_PRT2_BASE 0x40005092\r
+#define CYDEV_IO_PS_PRT2_SIZE 0x00000001\r
+#define CYDEV_IO_PS_PRT2_PS_ALIAS 0x40005092\r
+#define CYDEV_IO_PS_PRT3_BASE 0x40005093\r
+#define CYDEV_IO_PS_PRT3_SIZE 0x00000001\r
+#define CYDEV_IO_PS_PRT3_PS_ALIAS 0x40005093\r
+#define CYDEV_IO_PS_PRT4_BASE 0x40005094\r
+#define CYDEV_IO_PS_PRT4_SIZE 0x00000001\r
+#define CYDEV_IO_PS_PRT4_PS_ALIAS 0x40005094\r
+#define CYDEV_IO_PS_PRT5_BASE 0x40005095\r
+#define CYDEV_IO_PS_PRT5_SIZE 0x00000001\r
+#define CYDEV_IO_PS_PRT5_PS_ALIAS 0x40005095\r
+#define CYDEV_IO_PS_PRT6_BASE 0x40005096\r
+#define CYDEV_IO_PS_PRT6_SIZE 0x00000001\r
+#define CYDEV_IO_PS_PRT6_PS_ALIAS 0x40005096\r
+#define CYDEV_IO_PS_PRT12_BASE 0x4000509c\r
+#define CYDEV_IO_PS_PRT12_SIZE 0x00000001\r
+#define CYDEV_IO_PS_PRT12_PS_ALIAS 0x4000509c\r
+#define CYDEV_IO_PS_PRT15_BASE 0x4000509f\r
+#define CYDEV_IO_PS_PRT15_SIZE 0x00000001\r
+#define CYDEV_IO_PS_PRT15_PS15_ALIAS 0x4000509f\r
+#define CYDEV_IO_PRT_BASE 0x40005100\r
+#define CYDEV_IO_PRT_SIZE 0x00000100\r
+#define CYDEV_IO_PRT_PRT0_BASE 0x40005100\r
+#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010\r
+#define CYDEV_IO_PRT_PRT0_DR 0x40005100\r
+#define CYDEV_IO_PRT_PRT0_PS 0x40005101\r
+#define CYDEV_IO_PRT_PRT0_DM0 0x40005102\r
+#define CYDEV_IO_PRT_PRT0_DM1 0x40005103\r
+#define CYDEV_IO_PRT_PRT0_DM2 0x40005104\r
+#define CYDEV_IO_PRT_PRT0_SLW 0x40005105\r
+#define CYDEV_IO_PRT_PRT0_BYP 0x40005106\r
+#define CYDEV_IO_PRT_PRT0_BIE 0x40005107\r
+#define CYDEV_IO_PRT_PRT0_INP_DIS 0x40005108\r
+#define CYDEV_IO_PRT_PRT0_CTL 0x40005109\r
+#define CYDEV_IO_PRT_PRT0_PRT 0x4000510a\r
+#define CYDEV_IO_PRT_PRT0_BIT_MASK 0x4000510b\r
+#define CYDEV_IO_PRT_PRT0_AMUX 0x4000510c\r
+#define CYDEV_IO_PRT_PRT0_AG 0x4000510d\r
+#define CYDEV_IO_PRT_PRT0_LCD_COM_SEG 0x4000510e\r
+#define CYDEV_IO_PRT_PRT0_LCD_EN 0x4000510f\r
+#define CYDEV_IO_PRT_PRT1_BASE 0x40005110\r
+#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010\r
+#define CYDEV_IO_PRT_PRT1_DR 0x40005110\r
+#define CYDEV_IO_PRT_PRT1_PS 0x40005111\r
+#define CYDEV_IO_PRT_PRT1_DM0 0x40005112\r
+#define CYDEV_IO_PRT_PRT1_DM1 0x40005113\r
+#define CYDEV_IO_PRT_PRT1_DM2 0x40005114\r
+#define CYDEV_IO_PRT_PRT1_SLW 0x40005115\r
+#define CYDEV_IO_PRT_PRT1_BYP 0x40005116\r
+#define CYDEV_IO_PRT_PRT1_BIE 0x40005117\r
+#define CYDEV_IO_PRT_PRT1_INP_DIS 0x40005118\r
+#define CYDEV_IO_PRT_PRT1_CTL 0x40005119\r
+#define CYDEV_IO_PRT_PRT1_PRT 0x4000511a\r
+#define CYDEV_IO_PRT_PRT1_BIT_MASK 0x4000511b\r
+#define CYDEV_IO_PRT_PRT1_AMUX 0x4000511c\r
+#define CYDEV_IO_PRT_PRT1_AG 0x4000511d\r
+#define CYDEV_IO_PRT_PRT1_LCD_COM_SEG 0x4000511e\r
+#define CYDEV_IO_PRT_PRT1_LCD_EN 0x4000511f\r
+#define CYDEV_IO_PRT_PRT2_BASE 0x40005120\r
+#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010\r
+#define CYDEV_IO_PRT_PRT2_DR 0x40005120\r
+#define CYDEV_IO_PRT_PRT2_PS 0x40005121\r
+#define CYDEV_IO_PRT_PRT2_DM0 0x40005122\r
+#define CYDEV_IO_PRT_PRT2_DM1 0x40005123\r
+#define CYDEV_IO_PRT_PRT2_DM2 0x40005124\r
+#define CYDEV_IO_PRT_PRT2_SLW 0x40005125\r
+#define CYDEV_IO_PRT_PRT2_BYP 0x40005126\r
+#define CYDEV_IO_PRT_PRT2_BIE 0x40005127\r
+#define CYDEV_IO_PRT_PRT2_INP_DIS 0x40005128\r
+#define CYDEV_IO_PRT_PRT2_CTL 0x40005129\r
+#define CYDEV_IO_PRT_PRT2_PRT 0x4000512a\r
+#define CYDEV_IO_PRT_PRT2_BIT_MASK 0x4000512b\r
+#define CYDEV_IO_PRT_PRT2_AMUX 0x4000512c\r
+#define CYDEV_IO_PRT_PRT2_AG 0x4000512d\r
+#define CYDEV_IO_PRT_PRT2_LCD_COM_SEG 0x4000512e\r
+#define CYDEV_IO_PRT_PRT2_LCD_EN 0x4000512f\r
+#define CYDEV_IO_PRT_PRT3_BASE 0x40005130\r
+#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010\r
+#define CYDEV_IO_PRT_PRT3_DR 0x40005130\r
+#define CYDEV_IO_PRT_PRT3_PS 0x40005131\r
+#define CYDEV_IO_PRT_PRT3_DM0 0x40005132\r
+#define CYDEV_IO_PRT_PRT3_DM1 0x40005133\r
+#define CYDEV_IO_PRT_PRT3_DM2 0x40005134\r
+#define CYDEV_IO_PRT_PRT3_SLW 0x40005135\r
+#define CYDEV_IO_PRT_PRT3_BYP 0x40005136\r
+#define CYDEV_IO_PRT_PRT3_BIE 0x40005137\r
+#define CYDEV_IO_PRT_PRT3_INP_DIS 0x40005138\r
+#define CYDEV_IO_PRT_PRT3_CTL 0x40005139\r
+#define CYDEV_IO_PRT_PRT3_PRT 0x4000513a\r
+#define CYDEV_IO_PRT_PRT3_BIT_MASK 0x4000513b\r
+#define CYDEV_IO_PRT_PRT3_AMUX 0x4000513c\r
+#define CYDEV_IO_PRT_PRT3_AG 0x4000513d\r
+#define CYDEV_IO_PRT_PRT3_LCD_COM_SEG 0x4000513e\r
+#define CYDEV_IO_PRT_PRT3_LCD_EN 0x4000513f\r
+#define CYDEV_IO_PRT_PRT4_BASE 0x40005140\r
+#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010\r
+#define CYDEV_IO_PRT_PRT4_DR 0x40005140\r
+#define CYDEV_IO_PRT_PRT4_PS 0x40005141\r
+#define CYDEV_IO_PRT_PRT4_DM0 0x40005142\r
+#define CYDEV_IO_PRT_PRT4_DM1 0x40005143\r
+#define CYDEV_IO_PRT_PRT4_DM2 0x40005144\r
+#define CYDEV_IO_PRT_PRT4_SLW 0x40005145\r
+#define CYDEV_IO_PRT_PRT4_BYP 0x40005146\r
+#define CYDEV_IO_PRT_PRT4_BIE 0x40005147\r
+#define CYDEV_IO_PRT_PRT4_INP_DIS 0x40005148\r
+#define CYDEV_IO_PRT_PRT4_CTL 0x40005149\r
+#define CYDEV_IO_PRT_PRT4_PRT 0x4000514a\r
+#define CYDEV_IO_PRT_PRT4_BIT_MASK 0x4000514b\r
+#define CYDEV_IO_PRT_PRT4_AMUX 0x4000514c\r
+#define CYDEV_IO_PRT_PRT4_AG 0x4000514d\r
+#define CYDEV_IO_PRT_PRT4_LCD_COM_SEG 0x4000514e\r
+#define CYDEV_IO_PRT_PRT4_LCD_EN 0x4000514f\r
+#define CYDEV_IO_PRT_PRT5_BASE 0x40005150\r
+#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010\r
+#define CYDEV_IO_PRT_PRT5_DR 0x40005150\r
+#define CYDEV_IO_PRT_PRT5_PS 0x40005151\r
+#define CYDEV_IO_PRT_PRT5_DM0 0x40005152\r
+#define CYDEV_IO_PRT_PRT5_DM1 0x40005153\r
+#define CYDEV_IO_PRT_PRT5_DM2 0x40005154\r
+#define CYDEV_IO_PRT_PRT5_SLW 0x40005155\r
+#define CYDEV_IO_PRT_PRT5_BYP 0x40005156\r
+#define CYDEV_IO_PRT_PRT5_BIE 0x40005157\r
+#define CYDEV_IO_PRT_PRT5_INP_DIS 0x40005158\r
+#define CYDEV_IO_PRT_PRT5_CTL 0x40005159\r
+#define CYDEV_IO_PRT_PRT5_PRT 0x4000515a\r
+#define CYDEV_IO_PRT_PRT5_BIT_MASK 0x4000515b\r
+#define CYDEV_IO_PRT_PRT5_AMUX 0x4000515c\r
+#define CYDEV_IO_PRT_PRT5_AG 0x4000515d\r
+#define CYDEV_IO_PRT_PRT5_LCD_COM_SEG 0x4000515e\r
+#define CYDEV_IO_PRT_PRT5_LCD_EN 0x4000515f\r
+#define CYDEV_IO_PRT_PRT6_BASE 0x40005160\r
+#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010\r
+#define CYDEV_IO_PRT_PRT6_DR 0x40005160\r
+#define CYDEV_IO_PRT_PRT6_PS 0x40005161\r
+#define CYDEV_IO_PRT_PRT6_DM0 0x40005162\r
+#define CYDEV_IO_PRT_PRT6_DM1 0x40005163\r
+#define CYDEV_IO_PRT_PRT6_DM2 0x40005164\r
+#define CYDEV_IO_PRT_PRT6_SLW 0x40005165\r
+#define CYDEV_IO_PRT_PRT6_BYP 0x40005166\r
+#define CYDEV_IO_PRT_PRT6_BIE 0x40005167\r
+#define CYDEV_IO_PRT_PRT6_INP_DIS 0x40005168\r
+#define CYDEV_IO_PRT_PRT6_CTL 0x40005169\r
+#define CYDEV_IO_PRT_PRT6_PRT 0x4000516a\r
+#define CYDEV_IO_PRT_PRT6_BIT_MASK 0x4000516b\r
+#define CYDEV_IO_PRT_PRT6_AMUX 0x4000516c\r
+#define CYDEV_IO_PRT_PRT6_AG 0x4000516d\r
+#define CYDEV_IO_PRT_PRT6_LCD_COM_SEG 0x4000516e\r
+#define CYDEV_IO_PRT_PRT6_LCD_EN 0x4000516f\r
+#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0\r
+#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010\r
+#define CYDEV_IO_PRT_PRT12_DR 0x400051c0\r
+#define CYDEV_IO_PRT_PRT12_PS 0x400051c1\r
+#define CYDEV_IO_PRT_PRT12_DM0 0x400051c2\r
+#define CYDEV_IO_PRT_PRT12_DM1 0x400051c3\r
+#define CYDEV_IO_PRT_PRT12_DM2 0x400051c4\r
+#define CYDEV_IO_PRT_PRT12_SLW 0x400051c5\r
+#define CYDEV_IO_PRT_PRT12_BYP 0x400051c6\r
+#define CYDEV_IO_PRT_PRT12_BIE 0x400051c7\r
+#define CYDEV_IO_PRT_PRT12_INP_DIS 0x400051c8\r
+#define CYDEV_IO_PRT_PRT12_SIO_HYST_EN 0x400051c9\r
+#define CYDEV_IO_PRT_PRT12_PRT 0x400051ca\r
+#define CYDEV_IO_PRT_PRT12_BIT_MASK 0x400051cb\r
+#define CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ 0x400051cc\r
+#define CYDEV_IO_PRT_PRT12_AG 0x400051cd\r
+#define CYDEV_IO_PRT_PRT12_SIO_CFG 0x400051ce\r
+#define CYDEV_IO_PRT_PRT12_SIO_DIFF 0x400051cf\r
+#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0\r
+#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010\r
+#define CYDEV_IO_PRT_PRT15_DR 0x400051f0\r
+#define CYDEV_IO_PRT_PRT15_PS 0x400051f1\r
+#define CYDEV_IO_PRT_PRT15_DM0 0x400051f2\r
+#define CYDEV_IO_PRT_PRT15_DM1 0x400051f3\r
+#define CYDEV_IO_PRT_PRT15_DM2 0x400051f4\r
+#define CYDEV_IO_PRT_PRT15_SLW 0x400051f5\r
+#define CYDEV_IO_PRT_PRT15_BYP 0x400051f6\r
+#define CYDEV_IO_PRT_PRT15_BIE 0x400051f7\r
+#define CYDEV_IO_PRT_PRT15_INP_DIS 0x400051f8\r
+#define CYDEV_IO_PRT_PRT15_CTL 0x400051f9\r
+#define CYDEV_IO_PRT_PRT15_PRT 0x400051fa\r
+#define CYDEV_IO_PRT_PRT15_BIT_MASK 0x400051fb\r
+#define CYDEV_IO_PRT_PRT15_AMUX 0x400051fc\r
+#define CYDEV_IO_PRT_PRT15_AG 0x400051fd\r
+#define CYDEV_IO_PRT_PRT15_LCD_COM_SEG 0x400051fe\r
+#define CYDEV_IO_PRT_PRT15_LCD_EN 0x400051ff\r
+#define CYDEV_PRTDSI_BASE 0x40005200\r
+#define CYDEV_PRTDSI_SIZE 0x0000007f\r
+#define CYDEV_PRTDSI_PRT0_BASE 0x40005200\r
+#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007\r
+#define CYDEV_PRTDSI_PRT0_OUT_SEL0 0x40005200\r
+#define CYDEV_PRTDSI_PRT0_OUT_SEL1 0x40005201\r
+#define CYDEV_PRTDSI_PRT0_OE_SEL0 0x40005202\r
+#define CYDEV_PRTDSI_PRT0_OE_SEL1 0x40005203\r
+#define CYDEV_PRTDSI_PRT0_DBL_SYNC_IN 0x40005204\r
+#define CYDEV_PRTDSI_PRT0_SYNC_OUT 0x40005205\r
+#define CYDEV_PRTDSI_PRT0_CAPS_SEL 0x40005206\r
+#define CYDEV_PRTDSI_PRT1_BASE 0x40005208\r
+#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007\r
+#define CYDEV_PRTDSI_PRT1_OUT_SEL0 0x40005208\r
+#define CYDEV_PRTDSI_PRT1_OUT_SEL1 0x40005209\r
+#define CYDEV_PRTDSI_PRT1_OE_SEL0 0x4000520a\r
+#define CYDEV_PRTDSI_PRT1_OE_SEL1 0x4000520b\r
+#define CYDEV_PRTDSI_PRT1_DBL_SYNC_IN 0x4000520c\r
+#define CYDEV_PRTDSI_PRT1_SYNC_OUT 0x4000520d\r
+#define CYDEV_PRTDSI_PRT1_CAPS_SEL 0x4000520e\r
+#define CYDEV_PRTDSI_PRT2_BASE 0x40005210\r
+#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007\r
+#define CYDEV_PRTDSI_PRT2_OUT_SEL0 0x40005210\r
+#define CYDEV_PRTDSI_PRT2_OUT_SEL1 0x40005211\r
+#define CYDEV_PRTDSI_PRT2_OE_SEL0 0x40005212\r
+#define CYDEV_PRTDSI_PRT2_OE_SEL1 0x40005213\r
+#define CYDEV_PRTDSI_PRT2_DBL_SYNC_IN 0x40005214\r
+#define CYDEV_PRTDSI_PRT2_SYNC_OUT 0x40005215\r
+#define CYDEV_PRTDSI_PRT2_CAPS_SEL 0x40005216\r
+#define CYDEV_PRTDSI_PRT3_BASE 0x40005218\r
+#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007\r
+#define CYDEV_PRTDSI_PRT3_OUT_SEL0 0x40005218\r
+#define CYDEV_PRTDSI_PRT3_OUT_SEL1 0x40005219\r
+#define CYDEV_PRTDSI_PRT3_OE_SEL0 0x4000521a\r
+#define CYDEV_PRTDSI_PRT3_OE_SEL1 0x4000521b\r
+#define CYDEV_PRTDSI_PRT3_DBL_SYNC_IN 0x4000521c\r
+#define CYDEV_PRTDSI_PRT3_SYNC_OUT 0x4000521d\r
+#define CYDEV_PRTDSI_PRT3_CAPS_SEL 0x4000521e\r
+#define CYDEV_PRTDSI_PRT4_BASE 0x40005220\r
+#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007\r
+#define CYDEV_PRTDSI_PRT4_OUT_SEL0 0x40005220\r
+#define CYDEV_PRTDSI_PRT4_OUT_SEL1 0x40005221\r
+#define CYDEV_PRTDSI_PRT4_OE_SEL0 0x40005222\r
+#define CYDEV_PRTDSI_PRT4_OE_SEL1 0x40005223\r
+#define CYDEV_PRTDSI_PRT4_DBL_SYNC_IN 0x40005224\r
+#define CYDEV_PRTDSI_PRT4_SYNC_OUT 0x40005225\r
+#define CYDEV_PRTDSI_PRT4_CAPS_SEL 0x40005226\r
+#define CYDEV_PRTDSI_PRT5_BASE 0x40005228\r
+#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007\r
+#define CYDEV_PRTDSI_PRT5_OUT_SEL0 0x40005228\r
+#define CYDEV_PRTDSI_PRT5_OUT_SEL1 0x40005229\r
+#define CYDEV_PRTDSI_PRT5_OE_SEL0 0x4000522a\r
+#define CYDEV_PRTDSI_PRT5_OE_SEL1 0x4000522b\r
+#define CYDEV_PRTDSI_PRT5_DBL_SYNC_IN 0x4000522c\r
+#define CYDEV_PRTDSI_PRT5_SYNC_OUT 0x4000522d\r
+#define CYDEV_PRTDSI_PRT5_CAPS_SEL 0x4000522e\r
+#define CYDEV_PRTDSI_PRT6_BASE 0x40005230\r
+#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007\r
+#define CYDEV_PRTDSI_PRT6_OUT_SEL0 0x40005230\r
+#define CYDEV_PRTDSI_PRT6_OUT_SEL1 0x40005231\r
+#define CYDEV_PRTDSI_PRT6_OE_SEL0 0x40005232\r
+#define CYDEV_PRTDSI_PRT6_OE_SEL1 0x40005233\r
+#define CYDEV_PRTDSI_PRT6_DBL_SYNC_IN 0x40005234\r
+#define CYDEV_PRTDSI_PRT6_SYNC_OUT 0x40005235\r
+#define CYDEV_PRTDSI_PRT6_CAPS_SEL 0x40005236\r
+#define CYDEV_PRTDSI_PRT12_BASE 0x40005260\r
+#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006\r
+#define CYDEV_PRTDSI_PRT12_OUT_SEL0 0x40005260\r
+#define CYDEV_PRTDSI_PRT12_OUT_SEL1 0x40005261\r
+#define CYDEV_PRTDSI_PRT12_OE_SEL0 0x40005262\r
+#define CYDEV_PRTDSI_PRT12_OE_SEL1 0x40005263\r
+#define CYDEV_PRTDSI_PRT12_DBL_SYNC_IN 0x40005264\r
+#define CYDEV_PRTDSI_PRT12_SYNC_OUT 0x40005265\r
+#define CYDEV_PRTDSI_PRT15_BASE 0x40005278\r
+#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007\r
+#define CYDEV_PRTDSI_PRT15_OUT_SEL0 0x40005278\r
+#define CYDEV_PRTDSI_PRT15_OUT_SEL1 0x40005279\r
+#define CYDEV_PRTDSI_PRT15_OE_SEL0 0x4000527a\r
+#define CYDEV_PRTDSI_PRT15_OE_SEL1 0x4000527b\r
+#define CYDEV_PRTDSI_PRT15_DBL_SYNC_IN 0x4000527c\r
+#define CYDEV_PRTDSI_PRT15_SYNC_OUT 0x4000527d\r
+#define CYDEV_PRTDSI_PRT15_CAPS_SEL 0x4000527e\r
+#define CYDEV_EMIF_BASE 0x40005400\r
+#define CYDEV_EMIF_SIZE 0x00000007\r
+#define CYDEV_EMIF_NO_UDB 0x40005400\r
+#define CYDEV_EMIF_RP_WAIT_STATES 0x40005401\r
+#define CYDEV_EMIF_MEM_DWN 0x40005402\r
+#define CYDEV_EMIF_MEMCLK_DIV 0x40005403\r
+#define CYDEV_EMIF_CLOCK_EN 0x40005404\r
+#define CYDEV_EMIF_EM_TYPE 0x40005405\r
+#define CYDEV_EMIF_WP_WAIT_STATES 0x40005406\r
+#define CYDEV_ANAIF_BASE 0x40005800\r
+#define CYDEV_ANAIF_SIZE 0x000003a9\r
+#define CYDEV_ANAIF_CFG_BASE 0x40005800\r
+#define CYDEV_ANAIF_CFG_SIZE 0x0000010f\r
+#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800\r
+#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003\r
+#define CYDEV_ANAIF_CFG_SC0_CR0 0x40005800\r
+#define CYDEV_ANAIF_CFG_SC0_CR1 0x40005801\r
+#define CYDEV_ANAIF_CFG_SC0_CR2 0x40005802\r
+#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804\r
+#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003\r
+#define CYDEV_ANAIF_CFG_SC1_CR0 0x40005804\r
+#define CYDEV_ANAIF_CFG_SC1_CR1 0x40005805\r
+#define CYDEV_ANAIF_CFG_SC1_CR2 0x40005806\r
+#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808\r
+#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003\r
+#define CYDEV_ANAIF_CFG_SC2_CR0 0x40005808\r
+#define CYDEV_ANAIF_CFG_SC2_CR1 0x40005809\r
+#define CYDEV_ANAIF_CFG_SC2_CR2 0x4000580a\r
+#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580c\r
+#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003\r
+#define CYDEV_ANAIF_CFG_SC3_CR0 0x4000580c\r
+#define CYDEV_ANAIF_CFG_SC3_CR1 0x4000580d\r
+#define CYDEV_ANAIF_CFG_SC3_CR2 0x4000580e\r
+#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820\r
+#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003\r
+#define CYDEV_ANAIF_CFG_DAC0_CR0 0x40005820\r
+#define CYDEV_ANAIF_CFG_DAC0_CR1 0x40005821\r
+#define CYDEV_ANAIF_CFG_DAC0_TST 0x40005822\r
+#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824\r
+#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003\r
+#define CYDEV_ANAIF_CFG_DAC1_CR0 0x40005824\r
+#define CYDEV_ANAIF_CFG_DAC1_CR1 0x40005825\r
+#define CYDEV_ANAIF_CFG_DAC1_TST 0x40005826\r
+#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828\r
+#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003\r
+#define CYDEV_ANAIF_CFG_DAC2_CR0 0x40005828\r
+#define CYDEV_ANAIF_CFG_DAC2_CR1 0x40005829\r
+#define CYDEV_ANAIF_CFG_DAC2_TST 0x4000582a\r
+#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582c\r
+#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003\r
+#define CYDEV_ANAIF_CFG_DAC3_CR0 0x4000582c\r
+#define CYDEV_ANAIF_CFG_DAC3_CR1 0x4000582d\r
+#define CYDEV_ANAIF_CFG_DAC3_TST 0x4000582e\r
+#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840\r
+#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001\r
+#define CYDEV_ANAIF_CFG_CMP0_CR 0x40005840\r
+#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841\r
+#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001\r
+#define CYDEV_ANAIF_CFG_CMP1_CR 0x40005841\r
+#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842\r
+#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001\r
+#define CYDEV_ANAIF_CFG_CMP2_CR 0x40005842\r
+#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843\r
+#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001\r
+#define CYDEV_ANAIF_CFG_CMP3_CR 0x40005843\r
+#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848\r
+#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002\r
+#define CYDEV_ANAIF_CFG_LUT0_CR 0x40005848\r
+#define CYDEV_ANAIF_CFG_LUT0_MX 0x40005849\r
+#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584a\r
+#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002\r
+#define CYDEV_ANAIF_CFG_LUT1_CR 0x4000584a\r
+#define CYDEV_ANAIF_CFG_LUT1_MX 0x4000584b\r
+#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584c\r
+#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002\r
+#define CYDEV_ANAIF_CFG_LUT2_CR 0x4000584c\r
+#define CYDEV_ANAIF_CFG_LUT2_MX 0x4000584d\r
+#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584e\r
+#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002\r
+#define CYDEV_ANAIF_CFG_LUT3_CR 0x4000584e\r
+#define CYDEV_ANAIF_CFG_LUT3_MX 0x4000584f\r
+#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858\r
+#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002\r
+#define CYDEV_ANAIF_CFG_OPAMP0_CR 0x40005858\r
+#define CYDEV_ANAIF_CFG_OPAMP0_RSVD 0x40005859\r
+#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585a\r
+#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002\r
+#define CYDEV_ANAIF_CFG_OPAMP1_CR 0x4000585a\r
+#define CYDEV_ANAIF_CFG_OPAMP1_RSVD 0x4000585b\r
+#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585c\r
+#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002\r
+#define CYDEV_ANAIF_CFG_OPAMP2_CR 0x4000585c\r
+#define CYDEV_ANAIF_CFG_OPAMP2_RSVD 0x4000585d\r
+#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585e\r
+#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002\r
+#define CYDEV_ANAIF_CFG_OPAMP3_CR 0x4000585e\r
+#define CYDEV_ANAIF_CFG_OPAMP3_RSVD 0x4000585f\r
+#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868\r
+#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002\r
+#define CYDEV_ANAIF_CFG_LCDDAC_CR0 0x40005868\r
+#define CYDEV_ANAIF_CFG_LCDDAC_CR1 0x40005869\r
+#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586a\r
+#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001\r
+#define CYDEV_ANAIF_CFG_LCDDRV_CR 0x4000586a\r
+#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586b\r
+#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001\r
+#define CYDEV_ANAIF_CFG_LCDTMR_CFG 0x4000586b\r
+#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586c\r
+#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004\r
+#define CYDEV_ANAIF_CFG_BG_CR0 0x4000586c\r
+#define CYDEV_ANAIF_CFG_BG_RSVD 0x4000586d\r
+#define CYDEV_ANAIF_CFG_BG_DFT0 0x4000586e\r
+#define CYDEV_ANAIF_CFG_BG_DFT1 0x4000586f\r
+#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870\r
+#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002\r
+#define CYDEV_ANAIF_CFG_CAPSL_CFG0 0x40005870\r
+#define CYDEV_ANAIF_CFG_CAPSL_CFG1 0x40005871\r
+#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872\r
+#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002\r
+#define CYDEV_ANAIF_CFG_CAPSR_CFG0 0x40005872\r
+#define CYDEV_ANAIF_CFG_CAPSR_CFG1 0x40005873\r
+#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876\r
+#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002\r
+#define CYDEV_ANAIF_CFG_PUMP_CR0 0x40005876\r
+#define CYDEV_ANAIF_CFG_PUMP_CR1 0x40005877\r
+#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878\r
+#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002\r
+#define CYDEV_ANAIF_CFG_LPF0_CR0 0x40005878\r
+#define CYDEV_ANAIF_CFG_LPF0_RSVD 0x40005879\r
+#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587a\r
+#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002\r
+#define CYDEV_ANAIF_CFG_LPF1_CR0 0x4000587a\r
+#define CYDEV_ANAIF_CFG_LPF1_RSVD 0x4000587b\r
+#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587c\r
+#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001\r
+#define CYDEV_ANAIF_CFG_MISC_CR0 0x4000587c\r
+#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880\r
+#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020\r
+#define CYDEV_ANAIF_CFG_DSM0_CR0 0x40005880\r
+#define CYDEV_ANAIF_CFG_DSM0_CR1 0x40005881\r
+#define CYDEV_ANAIF_CFG_DSM0_CR2 0x40005882\r
+#define CYDEV_ANAIF_CFG_DSM0_CR3 0x40005883\r
+#define CYDEV_ANAIF_CFG_DSM0_CR4 0x40005884\r
+#define CYDEV_ANAIF_CFG_DSM0_CR5 0x40005885\r
+#define CYDEV_ANAIF_CFG_DSM0_CR6 0x40005886\r
+#define CYDEV_ANAIF_CFG_DSM0_CR7 0x40005887\r
+#define CYDEV_ANAIF_CFG_DSM0_CR8 0x40005888\r
+#define CYDEV_ANAIF_CFG_DSM0_CR9 0x40005889\r
+#define CYDEV_ANAIF_CFG_DSM0_CR10 0x4000588a\r
+#define CYDEV_ANAIF_CFG_DSM0_CR11 0x4000588b\r
+#define CYDEV_ANAIF_CFG_DSM0_CR12 0x4000588c\r
+#define CYDEV_ANAIF_CFG_DSM0_CR13 0x4000588d\r
+#define CYDEV_ANAIF_CFG_DSM0_CR14 0x4000588e\r
+#define CYDEV_ANAIF_CFG_DSM0_CR15 0x4000588f\r
+#define CYDEV_ANAIF_CFG_DSM0_CR16 0x40005890\r
+#define CYDEV_ANAIF_CFG_DSM0_CR17 0x40005891\r
+#define CYDEV_ANAIF_CFG_DSM0_REF0 0x40005892\r
+#define CYDEV_ANAIF_CFG_DSM0_REF1 0x40005893\r
+#define CYDEV_ANAIF_CFG_DSM0_REF2 0x40005894\r
+#define CYDEV_ANAIF_CFG_DSM0_REF3 0x40005895\r
+#define CYDEV_ANAIF_CFG_DSM0_DEM0 0x40005896\r
+#define CYDEV_ANAIF_CFG_DSM0_DEM1 0x40005897\r
+#define CYDEV_ANAIF_CFG_DSM0_TST0 0x40005898\r
+#define CYDEV_ANAIF_CFG_DSM0_TST1 0x40005899\r
+#define CYDEV_ANAIF_CFG_DSM0_BUF0 0x4000589a\r
+#define CYDEV_ANAIF_CFG_DSM0_BUF1 0x4000589b\r
+#define CYDEV_ANAIF_CFG_DSM0_BUF2 0x4000589c\r
+#define CYDEV_ANAIF_CFG_DSM0_BUF3 0x4000589d\r
+#define CYDEV_ANAIF_CFG_DSM0_MISC 0x4000589e\r
+#define CYDEV_ANAIF_CFG_DSM0_RSVD1 0x4000589f\r
+#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900\r
+#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007\r
+#define CYDEV_ANAIF_CFG_SAR0_CSR0 0x40005900\r
+#define CYDEV_ANAIF_CFG_SAR0_CSR1 0x40005901\r
+#define CYDEV_ANAIF_CFG_SAR0_CSR2 0x40005902\r
+#define CYDEV_ANAIF_CFG_SAR0_CSR3 0x40005903\r
+#define CYDEV_ANAIF_CFG_SAR0_CSR4 0x40005904\r
+#define CYDEV_ANAIF_CFG_SAR0_CSR5 0x40005905\r
+#define CYDEV_ANAIF_CFG_SAR0_CSR6 0x40005906\r
+#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908\r
+#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007\r
+#define CYDEV_ANAIF_CFG_SAR1_CSR0 0x40005908\r
+#define CYDEV_ANAIF_CFG_SAR1_CSR1 0x40005909\r
+#define CYDEV_ANAIF_CFG_SAR1_CSR2 0x4000590a\r
+#define CYDEV_ANAIF_CFG_SAR1_CSR3 0x4000590b\r
+#define CYDEV_ANAIF_CFG_SAR1_CSR4 0x4000590c\r
+#define CYDEV_ANAIF_CFG_SAR1_CSR5 0x4000590d\r
+#define CYDEV_ANAIF_CFG_SAR1_CSR6 0x4000590e\r
+#define CYDEV_ANAIF_RT_BASE 0x40005a00\r
+#define CYDEV_ANAIF_RT_SIZE 0x00000162\r
+#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00\r
+#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000d\r
+#define CYDEV_ANAIF_RT_SC0_SW0 0x40005a00\r
+#define CYDEV_ANAIF_RT_SC0_SW2 0x40005a02\r
+#define CYDEV_ANAIF_RT_SC0_SW3 0x40005a03\r
+#define CYDEV_ANAIF_RT_SC0_SW4 0x40005a04\r
+#define CYDEV_ANAIF_RT_SC0_SW6 0x40005a06\r
+#define CYDEV_ANAIF_RT_SC0_SW7 0x40005a07\r
+#define CYDEV_ANAIF_RT_SC0_SW8 0x40005a08\r
+#define CYDEV_ANAIF_RT_SC0_SW10 0x40005a0a\r
+#define CYDEV_ANAIF_RT_SC0_CLK 0x40005a0b\r
+#define CYDEV_ANAIF_RT_SC0_BST 0x40005a0c\r
+#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10\r
+#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000d\r
+#define CYDEV_ANAIF_RT_SC1_SW0 0x40005a10\r
+#define CYDEV_ANAIF_RT_SC1_SW2 0x40005a12\r
+#define CYDEV_ANAIF_RT_SC1_SW3 0x40005a13\r
+#define CYDEV_ANAIF_RT_SC1_SW4 0x40005a14\r
+#define CYDEV_ANAIF_RT_SC1_SW6 0x40005a16\r
+#define CYDEV_ANAIF_RT_SC1_SW7 0x40005a17\r
+#define CYDEV_ANAIF_RT_SC1_SW8 0x40005a18\r
+#define CYDEV_ANAIF_RT_SC1_SW10 0x40005a1a\r
+#define CYDEV_ANAIF_RT_SC1_CLK 0x40005a1b\r
+#define CYDEV_ANAIF_RT_SC1_BST 0x40005a1c\r
+#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20\r
+#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000d\r
+#define CYDEV_ANAIF_RT_SC2_SW0 0x40005a20\r
+#define CYDEV_ANAIF_RT_SC2_SW2 0x40005a22\r
+#define CYDEV_ANAIF_RT_SC2_SW3 0x40005a23\r
+#define CYDEV_ANAIF_RT_SC2_SW4 0x40005a24\r
+#define CYDEV_ANAIF_RT_SC2_SW6 0x40005a26\r
+#define CYDEV_ANAIF_RT_SC2_SW7 0x40005a27\r
+#define CYDEV_ANAIF_RT_SC2_SW8 0x40005a28\r
+#define CYDEV_ANAIF_RT_SC2_SW10 0x40005a2a\r
+#define CYDEV_ANAIF_RT_SC2_CLK 0x40005a2b\r
+#define CYDEV_ANAIF_RT_SC2_BST 0x40005a2c\r
+#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30\r
+#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000d\r
+#define CYDEV_ANAIF_RT_SC3_SW0 0x40005a30\r
+#define CYDEV_ANAIF_RT_SC3_SW2 0x40005a32\r
+#define CYDEV_ANAIF_RT_SC3_SW3 0x40005a33\r
+#define CYDEV_ANAIF_RT_SC3_SW4 0x40005a34\r
+#define CYDEV_ANAIF_RT_SC3_SW6 0x40005a36\r
+#define CYDEV_ANAIF_RT_SC3_SW7 0x40005a37\r
+#define CYDEV_ANAIF_RT_SC3_SW8 0x40005a38\r
+#define CYDEV_ANAIF_RT_SC3_SW10 0x40005a3a\r
+#define CYDEV_ANAIF_RT_SC3_CLK 0x40005a3b\r
+#define CYDEV_ANAIF_RT_SC3_BST 0x40005a3c\r
+#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80\r
+#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008\r
+#define CYDEV_ANAIF_RT_DAC0_SW0 0x40005a80\r
+#define CYDEV_ANAIF_RT_DAC0_SW2 0x40005a82\r
+#define CYDEV_ANAIF_RT_DAC0_SW3 0x40005a83\r
+#define CYDEV_ANAIF_RT_DAC0_SW4 0x40005a84\r
+#define CYDEV_ANAIF_RT_DAC0_STROBE 0x40005a87\r
+#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88\r
+#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008\r
+#define CYDEV_ANAIF_RT_DAC1_SW0 0x40005a88\r
+#define CYDEV_ANAIF_RT_DAC1_SW2 0x40005a8a\r
+#define CYDEV_ANAIF_RT_DAC1_SW3 0x40005a8b\r
+#define CYDEV_ANAIF_RT_DAC1_SW4 0x40005a8c\r
+#define CYDEV_ANAIF_RT_DAC1_STROBE 0x40005a8f\r
+#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90\r
+#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008\r
+#define CYDEV_ANAIF_RT_DAC2_SW0 0x40005a90\r
+#define CYDEV_ANAIF_RT_DAC2_SW2 0x40005a92\r
+#define CYDEV_ANAIF_RT_DAC2_SW3 0x40005a93\r
+#define CYDEV_ANAIF_RT_DAC2_SW4 0x40005a94\r
+#define CYDEV_ANAIF_RT_DAC2_STROBE 0x40005a97\r
+#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98\r
+#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008\r
+#define CYDEV_ANAIF_RT_DAC3_SW0 0x40005a98\r
+#define CYDEV_ANAIF_RT_DAC3_SW2 0x40005a9a\r
+#define CYDEV_ANAIF_RT_DAC3_SW3 0x40005a9b\r
+#define CYDEV_ANAIF_RT_DAC3_SW4 0x40005a9c\r
+#define CYDEV_ANAIF_RT_DAC3_STROBE 0x40005a9f\r
+#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0\r
+#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008\r
+#define CYDEV_ANAIF_RT_CMP0_SW0 0x40005ac0\r
+#define CYDEV_ANAIF_RT_CMP0_SW2 0x40005ac2\r
+#define CYDEV_ANAIF_RT_CMP0_SW3 0x40005ac3\r
+#define CYDEV_ANAIF_RT_CMP0_SW4 0x40005ac4\r
+#define CYDEV_ANAIF_RT_CMP0_SW6 0x40005ac6\r
+#define CYDEV_ANAIF_RT_CMP0_CLK 0x40005ac7\r
+#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8\r
+#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008\r
+#define CYDEV_ANAIF_RT_CMP1_SW0 0x40005ac8\r
+#define CYDEV_ANAIF_RT_CMP1_SW2 0x40005aca\r
+#define CYDEV_ANAIF_RT_CMP1_SW3 0x40005acb\r
+#define CYDEV_ANAIF_RT_CMP1_SW4 0x40005acc\r
+#define CYDEV_ANAIF_RT_CMP1_SW6 0x40005ace\r
+#define CYDEV_ANAIF_RT_CMP1_CLK 0x40005acf\r
+#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0\r
+#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008\r
+#define CYDEV_ANAIF_RT_CMP2_SW0 0x40005ad0\r
+#define CYDEV_ANAIF_RT_CMP2_SW2 0x40005ad2\r
+#define CYDEV_ANAIF_RT_CMP2_SW3 0x40005ad3\r
+#define CYDEV_ANAIF_RT_CMP2_SW4 0x40005ad4\r
+#define CYDEV_ANAIF_RT_CMP2_SW6 0x40005ad6\r
+#define CYDEV_ANAIF_RT_CMP2_CLK 0x40005ad7\r
+#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8\r
+#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008\r
+#define CYDEV_ANAIF_RT_CMP3_SW0 0x40005ad8\r
+#define CYDEV_ANAIF_RT_CMP3_SW2 0x40005ada\r
+#define CYDEV_ANAIF_RT_CMP3_SW3 0x40005adb\r
+#define CYDEV_ANAIF_RT_CMP3_SW4 0x40005adc\r
+#define CYDEV_ANAIF_RT_CMP3_SW6 0x40005ade\r
+#define CYDEV_ANAIF_RT_CMP3_CLK 0x40005adf\r
+#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00\r
+#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008\r
+#define CYDEV_ANAIF_RT_DSM0_SW0 0x40005b00\r
+#define CYDEV_ANAIF_RT_DSM0_SW2 0x40005b02\r
+#define CYDEV_ANAIF_RT_DSM0_SW3 0x40005b03\r
+#define CYDEV_ANAIF_RT_DSM0_SW4 0x40005b04\r
+#define CYDEV_ANAIF_RT_DSM0_SW6 0x40005b06\r
+#define CYDEV_ANAIF_RT_DSM0_CLK 0x40005b07\r
+#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20\r
+#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008\r
+#define CYDEV_ANAIF_RT_SAR0_SW0 0x40005b20\r
+#define CYDEV_ANAIF_RT_SAR0_SW2 0x40005b22\r
+#define CYDEV_ANAIF_RT_SAR0_SW3 0x40005b23\r
+#define CYDEV_ANAIF_RT_SAR0_SW4 0x40005b24\r
+#define CYDEV_ANAIF_RT_SAR0_SW6 0x40005b26\r
+#define CYDEV_ANAIF_RT_SAR0_CLK 0x40005b27\r
+#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28\r
+#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008\r
+#define CYDEV_ANAIF_RT_SAR1_SW0 0x40005b28\r
+#define CYDEV_ANAIF_RT_SAR1_SW2 0x40005b2a\r
+#define CYDEV_ANAIF_RT_SAR1_SW3 0x40005b2b\r
+#define CYDEV_ANAIF_RT_SAR1_SW4 0x40005b2c\r
+#define CYDEV_ANAIF_RT_SAR1_SW6 0x40005b2e\r
+#define CYDEV_ANAIF_RT_SAR1_CLK 0x40005b2f\r
+#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40\r
+#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002\r
+#define CYDEV_ANAIF_RT_OPAMP0_MX 0x40005b40\r
+#define CYDEV_ANAIF_RT_OPAMP0_SW 0x40005b41\r
+#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42\r
+#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002\r
+#define CYDEV_ANAIF_RT_OPAMP1_MX 0x40005b42\r
+#define CYDEV_ANAIF_RT_OPAMP1_SW 0x40005b43\r
+#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44\r
+#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002\r
+#define CYDEV_ANAIF_RT_OPAMP2_MX 0x40005b44\r
+#define CYDEV_ANAIF_RT_OPAMP2_SW 0x40005b45\r
+#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46\r
+#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002\r
+#define CYDEV_ANAIF_RT_OPAMP3_MX 0x40005b46\r
+#define CYDEV_ANAIF_RT_OPAMP3_SW 0x40005b47\r
+#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50\r
+#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005\r
+#define CYDEV_ANAIF_RT_LCDDAC_SW0 0x40005b50\r
+#define CYDEV_ANAIF_RT_LCDDAC_SW1 0x40005b51\r
+#define CYDEV_ANAIF_RT_LCDDAC_SW2 0x40005b52\r
+#define CYDEV_ANAIF_RT_LCDDAC_SW3 0x40005b53\r
+#define CYDEV_ANAIF_RT_LCDDAC_SW4 0x40005b54\r
+#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56\r
+#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001\r
+#define CYDEV_ANAIF_RT_SC_MISC 0x40005b56\r
+#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58\r
+#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004\r
+#define CYDEV_ANAIF_RT_BUS_SW0 0x40005b58\r
+#define CYDEV_ANAIF_RT_BUS_SW2 0x40005b5a\r
+#define CYDEV_ANAIF_RT_BUS_SW3 0x40005b5b\r
+#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5c\r
+#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006\r
+#define CYDEV_ANAIF_RT_DFT_CR0 0x40005b5c\r
+#define CYDEV_ANAIF_RT_DFT_CR1 0x40005b5d\r
+#define CYDEV_ANAIF_RT_DFT_CR2 0x40005b5e\r
+#define CYDEV_ANAIF_RT_DFT_CR3 0x40005b5f\r
+#define CYDEV_ANAIF_RT_DFT_CR4 0x40005b60\r
+#define CYDEV_ANAIF_RT_DFT_CR5 0x40005b61\r
+#define CYDEV_ANAIF_WRK_BASE 0x40005b80\r
+#define CYDEV_ANAIF_WRK_SIZE 0x00000029\r
+#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80\r
+#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001\r
+#define CYDEV_ANAIF_WRK_DAC0_D 0x40005b80\r
+#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81\r
+#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001\r
+#define CYDEV_ANAIF_WRK_DAC1_D 0x40005b81\r
+#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82\r
+#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001\r
+#define CYDEV_ANAIF_WRK_DAC2_D 0x40005b82\r
+#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83\r
+#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001\r
+#define CYDEV_ANAIF_WRK_DAC3_D 0x40005b83\r
+#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88\r
+#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002\r
+#define CYDEV_ANAIF_WRK_DSM0_OUT0 0x40005b88\r
+#define CYDEV_ANAIF_WRK_DSM0_OUT1 0x40005b89\r
+#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90\r
+#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005\r
+#define CYDEV_ANAIF_WRK_LUT_SR 0x40005b90\r
+#define CYDEV_ANAIF_WRK_LUT_WRK1 0x40005b91\r
+#define CYDEV_ANAIF_WRK_LUT_MSK 0x40005b92\r
+#define CYDEV_ANAIF_WRK_LUT_CLK 0x40005b93\r
+#define CYDEV_ANAIF_WRK_LUT_CPTR 0x40005b94\r
+#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96\r
+#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002\r
+#define CYDEV_ANAIF_WRK_CMP_WRK 0x40005b96\r
+#define CYDEV_ANAIF_WRK_CMP_TST 0x40005b97\r
+#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98\r
+#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005\r
+#define CYDEV_ANAIF_WRK_SC_SR 0x40005b98\r
+#define CYDEV_ANAIF_WRK_SC_WRK1 0x40005b99\r
+#define CYDEV_ANAIF_WRK_SC_MSK 0x40005b9a\r
+#define CYDEV_ANAIF_WRK_SC_CMPINV 0x40005b9b\r
+#define CYDEV_ANAIF_WRK_SC_CPTR 0x40005b9c\r
+#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0\r
+#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002\r
+#define CYDEV_ANAIF_WRK_SAR0_WRK0 0x40005ba0\r
+#define CYDEV_ANAIF_WRK_SAR0_WRK1 0x40005ba1\r
+#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2\r
+#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002\r
+#define CYDEV_ANAIF_WRK_SAR1_WRK0 0x40005ba2\r
+#define CYDEV_ANAIF_WRK_SAR1_WRK1 0x40005ba3\r
+#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8\r
+#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001\r
+#define CYDEV_ANAIF_WRK_SARS_SOF 0x40005ba8\r
+#define CYDEV_USB_BASE 0x40006000\r
+#define CYDEV_USB_SIZE 0x00000300\r
+#define CYDEV_USB_EP0_DR0 0x40006000\r
+#define CYDEV_USB_EP0_DR1 0x40006001\r
+#define CYDEV_USB_EP0_DR2 0x40006002\r
+#define CYDEV_USB_EP0_DR3 0x40006003\r
+#define CYDEV_USB_EP0_DR4 0x40006004\r
+#define CYDEV_USB_EP0_DR5 0x40006005\r
+#define CYDEV_USB_EP0_DR6 0x40006006\r
+#define CYDEV_USB_EP0_DR7 0x40006007\r
+#define CYDEV_USB_CR0 0x40006008\r
+#define CYDEV_USB_CR1 0x40006009\r
+#define CYDEV_USB_SIE_EP_INT_EN 0x4000600a\r
+#define CYDEV_USB_SIE_EP_INT_SR 0x4000600b\r
+#define CYDEV_USB_SIE_EP1_BASE 0x4000600c\r
+#define CYDEV_USB_SIE_EP1_SIZE 0x00000003\r
+#define CYDEV_USB_SIE_EP1_CNT0 0x4000600c\r
+#define CYDEV_USB_SIE_EP1_CNT1 0x4000600d\r
+#define CYDEV_USB_SIE_EP1_CR0 0x4000600e\r
+#define CYDEV_USB_USBIO_CR0 0x40006010\r
+#define CYDEV_USB_USBIO_CR1 0x40006012\r
+#define CYDEV_USB_DYN_RECONFIG 0x40006014\r
+#define CYDEV_USB_SOF0 0x40006018\r
+#define CYDEV_USB_SOF1 0x40006019\r
+#define CYDEV_USB_SIE_EP2_BASE 0x4000601c\r
+#define CYDEV_USB_SIE_EP2_SIZE 0x00000003\r
+#define CYDEV_USB_SIE_EP2_CNT0 0x4000601c\r
+#define CYDEV_USB_SIE_EP2_CNT1 0x4000601d\r
+#define CYDEV_USB_SIE_EP2_CR0 0x4000601e\r
+#define CYDEV_USB_EP0_CR 0x40006028\r
+#define CYDEV_USB_EP0_CNT 0x40006029\r
+#define CYDEV_USB_SIE_EP3_BASE 0x4000602c\r
+#define CYDEV_USB_SIE_EP3_SIZE 0x00000003\r
+#define CYDEV_USB_SIE_EP3_CNT0 0x4000602c\r
+#define CYDEV_USB_SIE_EP3_CNT1 0x4000602d\r
+#define CYDEV_USB_SIE_EP3_CR0 0x4000602e\r
+#define CYDEV_USB_SIE_EP4_BASE 0x4000603c\r
+#define CYDEV_USB_SIE_EP4_SIZE 0x00000003\r
+#define CYDEV_USB_SIE_EP4_CNT0 0x4000603c\r
+#define CYDEV_USB_SIE_EP4_CNT1 0x4000603d\r
+#define CYDEV_USB_SIE_EP4_CR0 0x4000603e\r
+#define CYDEV_USB_SIE_EP5_BASE 0x4000604c\r
+#define CYDEV_USB_SIE_EP5_SIZE 0x00000003\r
+#define CYDEV_USB_SIE_EP5_CNT0 0x4000604c\r
+#define CYDEV_USB_SIE_EP5_CNT1 0x4000604d\r
+#define CYDEV_USB_SIE_EP5_CR0 0x4000604e\r
+#define CYDEV_USB_SIE_EP6_BASE 0x4000605c\r
+#define CYDEV_USB_SIE_EP6_SIZE 0x00000003\r
+#define CYDEV_USB_SIE_EP6_CNT0 0x4000605c\r
+#define CYDEV_USB_SIE_EP6_CNT1 0x4000605d\r
+#define CYDEV_USB_SIE_EP6_CR0 0x4000605e\r
+#define CYDEV_USB_SIE_EP7_BASE 0x4000606c\r
+#define CYDEV_USB_SIE_EP7_SIZE 0x00000003\r
+#define CYDEV_USB_SIE_EP7_CNT0 0x4000606c\r
+#define CYDEV_USB_SIE_EP7_CNT1 0x4000606d\r
+#define CYDEV_USB_SIE_EP7_CR0 0x4000606e\r
+#define CYDEV_USB_SIE_EP8_BASE 0x4000607c\r
+#define CYDEV_USB_SIE_EP8_SIZE 0x00000003\r
+#define CYDEV_USB_SIE_EP8_CNT0 0x4000607c\r
+#define CYDEV_USB_SIE_EP8_CNT1 0x4000607d\r
+#define CYDEV_USB_SIE_EP8_CR0 0x4000607e\r
+#define CYDEV_USB_ARB_EP1_BASE 0x40006080\r
+#define CYDEV_USB_ARB_EP1_SIZE 0x00000003\r
+#define CYDEV_USB_ARB_EP1_CFG 0x40006080\r
+#define CYDEV_USB_ARB_EP1_INT_EN 0x40006081\r
+#define CYDEV_USB_ARB_EP1_SR 0x40006082\r
+#define CYDEV_USB_ARB_RW1_BASE 0x40006084\r
+#define CYDEV_USB_ARB_RW1_SIZE 0x00000005\r
+#define CYDEV_USB_ARB_RW1_WA 0x40006084\r
+#define CYDEV_USB_ARB_RW1_WA_MSB 0x40006085\r
+#define CYDEV_USB_ARB_RW1_RA 0x40006086\r
+#define CYDEV_USB_ARB_RW1_RA_MSB 0x40006087\r
+#define CYDEV_USB_ARB_RW1_DR 0x40006088\r
+#define CYDEV_USB_BUF_SIZE 0x4000608c\r
+#define CYDEV_USB_EP_ACTIVE 0x4000608e\r
+#define CYDEV_USB_EP_TYPE 0x4000608f\r
+#define CYDEV_USB_ARB_EP2_BASE 0x40006090\r
+#define CYDEV_USB_ARB_EP2_SIZE 0x00000003\r
+#define CYDEV_USB_ARB_EP2_CFG 0x40006090\r
+#define CYDEV_USB_ARB_EP2_INT_EN 0x40006091\r
+#define CYDEV_USB_ARB_EP2_SR 0x40006092\r
+#define CYDEV_USB_ARB_RW2_BASE 0x40006094\r
+#define CYDEV_USB_ARB_RW2_SIZE 0x00000005\r
+#define CYDEV_USB_ARB_RW2_WA 0x40006094\r
+#define CYDEV_USB_ARB_RW2_WA_MSB 0x40006095\r
+#define CYDEV_USB_ARB_RW2_RA 0x40006096\r
+#define CYDEV_USB_ARB_RW2_RA_MSB 0x40006097\r
+#define CYDEV_USB_ARB_RW2_DR 0x40006098\r
+#define CYDEV_USB_ARB_CFG 0x4000609c\r
+#define CYDEV_USB_USB_CLK_EN 0x4000609d\r
+#define CYDEV_USB_ARB_INT_EN 0x4000609e\r
+#define CYDEV_USB_ARB_INT_SR 0x4000609f\r
+#define CYDEV_USB_ARB_EP3_BASE 0x400060a0\r
+#define CYDEV_USB_ARB_EP3_SIZE 0x00000003\r
+#define CYDEV_USB_ARB_EP3_CFG 0x400060a0\r
+#define CYDEV_USB_ARB_EP3_INT_EN 0x400060a1\r
+#define CYDEV_USB_ARB_EP3_SR 0x400060a2\r
+#define CYDEV_USB_ARB_RW3_BASE 0x400060a4\r
+#define CYDEV_USB_ARB_RW3_SIZE 0x00000005\r
+#define CYDEV_USB_ARB_RW3_WA 0x400060a4\r
+#define CYDEV_USB_ARB_RW3_WA_MSB 0x400060a5\r
+#define CYDEV_USB_ARB_RW3_RA 0x400060a6\r
+#define CYDEV_USB_ARB_RW3_RA_MSB 0x400060a7\r
+#define CYDEV_USB_ARB_RW3_DR 0x400060a8\r
+#define CYDEV_USB_CWA 0x400060ac\r
+#define CYDEV_USB_CWA_MSB 0x400060ad\r
+#define CYDEV_USB_ARB_EP4_BASE 0x400060b0\r
+#define CYDEV_USB_ARB_EP4_SIZE 0x00000003\r
+#define CYDEV_USB_ARB_EP4_CFG 0x400060b0\r
+#define CYDEV_USB_ARB_EP4_INT_EN 0x400060b1\r
+#define CYDEV_USB_ARB_EP4_SR 0x400060b2\r
+#define CYDEV_USB_ARB_RW4_BASE 0x400060b4\r
+#define CYDEV_USB_ARB_RW4_SIZE 0x00000005\r
+#define CYDEV_USB_ARB_RW4_WA 0x400060b4\r
+#define CYDEV_USB_ARB_RW4_WA_MSB 0x400060b5\r
+#define CYDEV_USB_ARB_RW4_RA 0x400060b6\r
+#define CYDEV_USB_ARB_RW4_RA_MSB 0x400060b7\r
+#define CYDEV_USB_ARB_RW4_DR 0x400060b8\r
+#define CYDEV_USB_DMA_THRES 0x400060bc\r
+#define CYDEV_USB_DMA_THRES_MSB 0x400060bd\r
+#define CYDEV_USB_ARB_EP5_BASE 0x400060c0\r
+#define CYDEV_USB_ARB_EP5_SIZE 0x00000003\r
+#define CYDEV_USB_ARB_EP5_CFG 0x400060c0\r
+#define CYDEV_USB_ARB_EP5_INT_EN 0x400060c1\r
+#define CYDEV_USB_ARB_EP5_SR 0x400060c2\r
+#define CYDEV_USB_ARB_RW5_BASE 0x400060c4\r
+#define CYDEV_USB_ARB_RW5_SIZE 0x00000005\r
+#define CYDEV_USB_ARB_RW5_WA 0x400060c4\r
+#define CYDEV_USB_ARB_RW5_WA_MSB 0x400060c5\r
+#define CYDEV_USB_ARB_RW5_RA 0x400060c6\r
+#define CYDEV_USB_ARB_RW5_RA_MSB 0x400060c7\r
+#define CYDEV_USB_ARB_RW5_DR 0x400060c8\r
+#define CYDEV_USB_BUS_RST_CNT 0x400060cc\r
+#define CYDEV_USB_ARB_EP6_BASE 0x400060d0\r
+#define CYDEV_USB_ARB_EP6_SIZE 0x00000003\r
+#define CYDEV_USB_ARB_EP6_CFG 0x400060d0\r
+#define CYDEV_USB_ARB_EP6_INT_EN 0x400060d1\r
+#define CYDEV_USB_ARB_EP6_SR 0x400060d2\r
+#define CYDEV_USB_ARB_RW6_BASE 0x400060d4\r
+#define CYDEV_USB_ARB_RW6_SIZE 0x00000005\r
+#define CYDEV_USB_ARB_RW6_WA 0x400060d4\r
+#define CYDEV_USB_ARB_RW6_WA_MSB 0x400060d5\r
+#define CYDEV_USB_ARB_RW6_RA 0x400060d6\r
+#define CYDEV_USB_ARB_RW6_RA_MSB 0x400060d7\r
+#define CYDEV_USB_ARB_RW6_DR 0x400060d8\r
+#define CYDEV_USB_ARB_EP7_BASE 0x400060e0\r
+#define CYDEV_USB_ARB_EP7_SIZE 0x00000003\r
+#define CYDEV_USB_ARB_EP7_CFG 0x400060e0\r
+#define CYDEV_USB_ARB_EP7_INT_EN 0x400060e1\r
+#define CYDEV_USB_ARB_EP7_SR 0x400060e2\r
+#define CYDEV_USB_ARB_RW7_BASE 0x400060e4\r
+#define CYDEV_USB_ARB_RW7_SIZE 0x00000005\r
+#define CYDEV_USB_ARB_RW7_WA 0x400060e4\r
+#define CYDEV_USB_ARB_RW7_WA_MSB 0x400060e5\r
+#define CYDEV_USB_ARB_RW7_RA 0x400060e6\r
+#define CYDEV_USB_ARB_RW7_RA_MSB 0x400060e7\r
+#define CYDEV_USB_ARB_RW7_DR 0x400060e8\r
+#define CYDEV_USB_ARB_EP8_BASE 0x400060f0\r
+#define CYDEV_USB_ARB_EP8_SIZE 0x00000003\r
+#define CYDEV_USB_ARB_EP8_CFG 0x400060f0\r
+#define CYDEV_USB_ARB_EP8_INT_EN 0x400060f1\r
+#define CYDEV_USB_ARB_EP8_SR 0x400060f2\r
+#define CYDEV_USB_ARB_RW8_BASE 0x400060f4\r
+#define CYDEV_USB_ARB_RW8_SIZE 0x00000005\r
+#define CYDEV_USB_ARB_RW8_WA 0x400060f4\r
+#define CYDEV_USB_ARB_RW8_WA_MSB 0x400060f5\r
+#define CYDEV_USB_ARB_RW8_RA 0x400060f6\r
+#define CYDEV_USB_ARB_RW8_RA_MSB 0x400060f7\r
+#define CYDEV_USB_ARB_RW8_DR 0x400060f8\r
+#define CYDEV_USB_MEM_BASE 0x40006100\r
+#define CYDEV_USB_MEM_SIZE 0x00000200\r
+#define CYDEV_USB_MEM_DATA_MBASE 0x40006100\r
+#define CYDEV_USB_MEM_DATA_MSIZE 0x00000200\r
+#define CYDEV_UWRK_BASE 0x40006400\r
+#define CYDEV_UWRK_SIZE 0x00000b60\r
+#define CYDEV_UWRK_UWRK8_BASE 0x40006400\r
+#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0\r
+#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400\r
+#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_A0 0x40006400\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_A0 0x40006401\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_A0 0x40006402\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_A0 0x40006403\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_A0 0x40006404\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_A0 0x40006405\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_A0 0x40006406\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_A0 0x40006407\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_A0 0x40006408\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_A0 0x40006409\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_A0 0x4000640a\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_A0 0x4000640b\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_A0 0x4000640c\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_A0 0x4000640d\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_A0 0x4000640e\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_A0 0x4000640f\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_A1 0x40006410\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_A1 0x40006411\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_A1 0x40006412\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_A1 0x40006413\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_A1 0x40006414\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_A1 0x40006415\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_A1 0x40006416\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_A1 0x40006417\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_A1 0x40006418\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_A1 0x40006419\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_A1 0x4000641a\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_A1 0x4000641b\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_A1 0x4000641c\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_A1 0x4000641d\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_A1 0x4000641e\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_A1 0x4000641f\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_D0 0x40006420\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_D0 0x40006421\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_D0 0x40006422\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_D0 0x40006423\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_D0 0x40006424\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_D0 0x40006425\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_D0 0x40006426\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_D0 0x40006427\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_D0 0x40006428\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_D0 0x40006429\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_D0 0x4000642a\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_D0 0x4000642b\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_D0 0x4000642c\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_D0 0x4000642d\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_D0 0x4000642e\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_D0 0x4000642f\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_D1 0x40006430\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_D1 0x40006431\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_D1 0x40006432\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_D1 0x40006433\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_D1 0x40006434\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_D1 0x40006435\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_D1 0x40006436\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_D1 0x40006437\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_D1 0x40006438\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_D1 0x40006439\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_D1 0x4000643a\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_D1 0x4000643b\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_D1 0x4000643c\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_D1 0x4000643d\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_D1 0x4000643e\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_D1 0x4000643f\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_F0 0x40006440\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_F0 0x40006441\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_F0 0x40006442\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_F0 0x40006443\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_F0 0x40006444\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_F0 0x40006445\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_F0 0x40006446\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_F0 0x40006447\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_F0 0x40006448\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_F0 0x40006449\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_F0 0x4000644a\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_F0 0x4000644b\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_F0 0x4000644c\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_F0 0x4000644d\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_F0 0x4000644e\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_F0 0x4000644f\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_F1 0x40006450\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_F1 0x40006451\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_F1 0x40006452\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_F1 0x40006453\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_F1 0x40006454\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_F1 0x40006455\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_F1 0x40006456\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_F1 0x40006457\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_F1 0x40006458\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_F1 0x40006459\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_F1 0x4000645a\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_F1 0x4000645b\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_F1 0x4000645c\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_F1 0x4000645d\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_F1 0x4000645e\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_F1 0x4000645f\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_ST 0x40006460\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_ST 0x40006461\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_ST 0x40006462\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_ST 0x40006463\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_ST 0x40006464\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_ST 0x40006465\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_ST 0x40006466\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_ST 0x40006467\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_ST 0x40006468\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_ST 0x40006469\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_ST 0x4000646a\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_ST 0x4000646b\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_ST 0x4000646c\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_ST 0x4000646d\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_ST 0x4000646e\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_ST 0x4000646f\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_CTL 0x40006470\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_CTL 0x40006471\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_CTL 0x40006472\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_CTL 0x40006473\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_CTL 0x40006474\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_CTL 0x40006475\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_CTL 0x40006476\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_CTL 0x40006477\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_CTL 0x40006478\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_CTL 0x40006479\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_CTL 0x4000647a\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_CTL 0x4000647b\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_CTL 0x4000647c\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_CTL 0x4000647d\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_CTL 0x4000647e\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_CTL 0x4000647f\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_MSK 0x40006480\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_MSK 0x40006481\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_MSK 0x40006482\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_MSK 0x40006483\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_MSK 0x40006484\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_MSK 0x40006485\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_MSK 0x40006486\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_MSK 0x40006487\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_MSK 0x40006488\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_MSK 0x40006489\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_MSK 0x4000648a\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_MSK 0x4000648b\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_MSK 0x4000648c\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_MSK 0x4000648d\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_MSK 0x4000648e\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_MSK 0x4000648f\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_ACTL 0x40006490\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_ACTL 0x40006491\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_ACTL 0x40006492\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_ACTL 0x40006493\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_ACTL 0x40006494\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_ACTL 0x40006495\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_ACTL 0x40006496\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_ACTL 0x40006497\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_ACTL 0x40006498\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_ACTL 0x40006499\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_ACTL 0x4000649a\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_ACTL 0x4000649b\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_ACTL 0x4000649c\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_ACTL 0x4000649d\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_ACTL 0x4000649e\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_ACTL 0x4000649f\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_MC 0x400064a0\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_MC 0x400064a1\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_MC 0x400064a2\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_MC 0x400064a3\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_MC 0x400064a4\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_MC 0x400064a5\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_MC 0x400064a6\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_MC 0x400064a7\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_MC 0x400064a8\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_MC 0x400064a9\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_MC 0x400064aa\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_MC 0x400064ab\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_MC 0x400064ac\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_MC 0x400064ad\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_MC 0x400064ae\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_MC 0x400064af\r
+#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500\r
+#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_A0 0x40006504\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_A0 0x40006505\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_A0 0x40006506\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_A0 0x40006507\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_A0 0x40006508\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_A0 0x40006509\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_A0 0x4000650a\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_A0 0x4000650b\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_A1 0x40006514\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_A1 0x40006515\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_A1 0x40006516\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_A1 0x40006517\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_A1 0x40006518\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_A1 0x40006519\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_A1 0x4000651a\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_A1 0x4000651b\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_D0 0x40006524\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_D0 0x40006525\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_D0 0x40006526\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_D0 0x40006527\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_D0 0x40006528\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_D0 0x40006529\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_D0 0x4000652a\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_D0 0x4000652b\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_D1 0x40006534\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_D1 0x40006535\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_D1 0x40006536\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_D1 0x40006537\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_D1 0x40006538\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_D1 0x40006539\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_D1 0x4000653a\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_D1 0x4000653b\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_F0 0x40006544\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_F0 0x40006545\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_F0 0x40006546\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_F0 0x40006547\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_F0 0x40006548\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_F0 0x40006549\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_F0 0x4000654a\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_F0 0x4000654b\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_F1 0x40006554\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_F1 0x40006555\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_F1 0x40006556\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_F1 0x40006557\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_F1 0x40006558\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_F1 0x40006559\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_F1 0x4000655a\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_F1 0x4000655b\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_ST 0x40006564\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_ST 0x40006565\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_ST 0x40006566\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_ST 0x40006567\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_ST 0x40006568\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_ST 0x40006569\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_ST 0x4000656a\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_ST 0x4000656b\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_CTL 0x40006574\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_CTL 0x40006575\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_CTL 0x40006576\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_CTL 0x40006577\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_CTL 0x40006578\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_CTL 0x40006579\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_CTL 0x4000657a\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_CTL 0x4000657b\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_MSK 0x40006584\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_MSK 0x40006585\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_MSK 0x40006586\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_MSK 0x40006587\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_MSK 0x40006588\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_MSK 0x40006589\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_MSK 0x4000658a\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_MSK 0x4000658b\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_ACTL 0x40006594\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_ACTL 0x40006595\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_ACTL 0x40006596\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_ACTL 0x40006597\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_ACTL 0x40006598\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_ACTL 0x40006599\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_ACTL 0x4000659a\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_ACTL 0x4000659b\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_MC 0x400065a4\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_MC 0x400065a5\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_MC 0x400065a6\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_MC 0x400065a7\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_MC 0x400065a8\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_MC 0x400065a9\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_MC 0x400065aa\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_MC 0x400065ab\r
+#define CYDEV_UWRK_UWRK16_BASE 0x40006800\r
+#define CYDEV_UWRK_UWRK16_SIZE 0x00000760\r
+#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800\r
+#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 0x40006800\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 0x40006802\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 0x40006804\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 0x40006806\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 0x40006808\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 0x4000680a\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 0x4000680c\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 0x4000680e\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 0x40006810\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 0x40006812\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 0x40006814\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 0x40006816\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 0x40006818\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 0x4000681a\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 0x4000681c\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 0x4000681e\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 0x40006840\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 0x40006842\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 0x40006844\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 0x40006846\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 0x40006848\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 0x4000684a\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 0x4000684c\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 0x4000684e\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 0x40006850\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 0x40006852\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 0x40006854\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 0x40006856\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 0x40006858\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 0x4000685a\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 0x4000685c\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 0x4000685e\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 0x40006880\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 0x40006882\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 0x40006884\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 0x40006886\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 0x40006888\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 0x4000688a\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 0x4000688c\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 0x4000688e\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 0x40006890\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 0x40006892\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 0x40006894\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 0x40006896\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 0x40006898\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 0x4000689a\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 0x4000689c\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 0x4000689e\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL 0x400068c0\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL 0x400068c2\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL 0x400068c4\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL 0x400068c6\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL 0x400068c8\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL 0x400068ca\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL 0x400068cc\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL 0x400068ce\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL 0x400068d0\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL 0x400068d2\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL 0x400068d4\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL 0x400068d6\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL 0x400068d8\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL 0x400068da\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL 0x400068dc\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL 0x400068de\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL 0x40006900\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL 0x40006902\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL 0x40006904\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL 0x40006906\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL 0x40006908\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL 0x4000690a\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL 0x4000690c\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL 0x4000690e\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL 0x40006910\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL 0x40006912\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL 0x40006914\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL 0x40006916\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL 0x40006918\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL 0x4000691a\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL 0x4000691c\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL 0x4000691e\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 0x40006940\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 0x40006942\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 0x40006944\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 0x40006946\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 0x40006948\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 0x4000694a\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 0x4000694c\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 0x4000694e\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 0x40006950\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 0x40006952\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 0x40006954\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 0x40006956\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 0x40006958\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 0x4000695a\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 0x4000695c\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 0x4000695e\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 0x40006a08\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 0x40006a0a\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 0x40006a0c\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 0x40006a0e\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 0x40006a10\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 0x40006a12\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 0x40006a14\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 0x40006a16\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 0x40006a48\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 0x40006a4a\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 0x40006a4c\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 0x40006a4e\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 0x40006a50\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 0x40006a52\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 0x40006a54\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 0x40006a56\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 0x40006a88\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 0x40006a8a\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 0x40006a8c\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 0x40006a8e\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 0x40006a90\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 0x40006a92\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 0x40006a94\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 0x40006a96\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL 0x40006ac8\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL 0x40006aca\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL 0x40006acc\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL 0x40006ace\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL 0x40006ad0\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL 0x40006ad2\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL 0x40006ad4\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL 0x40006ad6\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL 0x40006b08\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL 0x40006b0a\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL 0x40006b0c\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL 0x40006b0e\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL 0x40006b10\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL 0x40006b12\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL 0x40006b14\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL 0x40006b16\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 0x40006b48\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 0x40006b4a\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 0x40006b4c\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 0x40006b4e\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 0x40006b50\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 0x40006b52\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 0x40006b54\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 0x40006b56\r
+#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800\r
+#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075e\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015e\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 0x40006800\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 0x40006802\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 0x40006804\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 0x40006806\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 0x40006808\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 0x4000680a\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 0x4000680c\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 0x4000680e\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 0x40006810\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 0x40006812\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 0x40006814\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 0x40006816\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 0x40006818\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 0x4000681a\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 0x4000681c\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 0x40006820\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 0x40006822\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 0x40006824\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 0x40006826\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 0x40006828\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 0x4000682a\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 0x4000682c\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 0x4000682e\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 0x40006830\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 0x40006832\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 0x40006834\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 0x40006836\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 0x40006838\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 0x4000683a\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 0x4000683c\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 0x40006840\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 0x40006842\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 0x40006844\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 0x40006846\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 0x40006848\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 0x4000684a\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 0x4000684c\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 0x4000684e\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 0x40006850\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 0x40006852\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 0x40006854\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 0x40006856\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 0x40006858\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 0x4000685a\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 0x4000685c\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 0x40006860\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 0x40006862\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 0x40006864\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 0x40006866\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 0x40006868\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 0x4000686a\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 0x4000686c\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 0x4000686e\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 0x40006870\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 0x40006872\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 0x40006874\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 0x40006876\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 0x40006878\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 0x4000687a\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 0x4000687c\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 0x40006880\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 0x40006882\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 0x40006884\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 0x40006886\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 0x40006888\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 0x4000688a\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 0x4000688c\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 0x4000688e\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 0x40006890\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 0x40006892\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 0x40006894\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 0x40006896\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 0x40006898\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 0x4000689a\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 0x4000689c\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 0x400068a0\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 0x400068a2\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 0x400068a4\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 0x400068a6\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 0x400068a8\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 0x400068aa\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 0x400068ac\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 0x400068ae\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 0x400068b0\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 0x400068b2\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 0x400068b4\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 0x400068b6\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 0x400068b8\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 0x400068ba\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 0x400068bc\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST 0x400068c0\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST 0x400068c2\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST 0x400068c4\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST 0x400068c6\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST 0x400068c8\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST 0x400068ca\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST 0x400068cc\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST 0x400068ce\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST 0x400068d0\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST 0x400068d2\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST 0x400068d4\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST 0x400068d6\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST 0x400068d8\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST 0x400068da\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST 0x400068dc\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL 0x400068e0\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL 0x400068e2\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL 0x400068e4\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL 0x400068e6\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL 0x400068e8\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL 0x400068ea\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL 0x400068ec\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL 0x400068ee\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL 0x400068f0\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL 0x400068f2\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL 0x400068f4\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL 0x400068f6\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL 0x400068f8\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL 0x400068fa\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL 0x400068fc\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK 0x40006900\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK 0x40006902\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK 0x40006904\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK 0x40006906\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK 0x40006908\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK 0x4000690a\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK 0x4000690c\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK 0x4000690e\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK 0x40006910\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK 0x40006912\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK 0x40006914\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK 0x40006916\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK 0x40006918\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK 0x4000691a\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK 0x4000691c\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL 0x40006920\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL 0x40006922\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL 0x40006924\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL 0x40006926\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL 0x40006928\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL 0x4000692a\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL 0x4000692c\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL 0x4000692e\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL 0x40006930\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL 0x40006932\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL 0x40006934\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL 0x40006936\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL 0x40006938\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL 0x4000693a\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL 0x4000693c\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC 0x40006940\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC 0x40006942\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC 0x40006944\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC 0x40006946\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC 0x40006948\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC 0x4000694a\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC 0x4000694c\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC 0x4000694e\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC 0x40006950\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC 0x40006952\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC 0x40006954\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC 0x40006956\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC 0x40006958\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC 0x4000695a\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC 0x4000695c\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015e\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 0x40006a08\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 0x40006a0a\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 0x40006a0c\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 0x40006a0e\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 0x40006a10\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 0x40006a12\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 0x40006a14\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 0x40006a16\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 0x40006a28\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 0x40006a2a\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 0x40006a2c\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 0x40006a2e\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 0x40006a30\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 0x40006a32\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 0x40006a34\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 0x40006a36\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 0x40006a48\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 0x40006a4a\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 0x40006a4c\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 0x40006a4e\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 0x40006a50\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 0x40006a52\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 0x40006a54\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 0x40006a56\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 0x40006a68\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 0x40006a6a\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 0x40006a6c\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 0x40006a6e\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 0x40006a70\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 0x40006a72\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 0x40006a74\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 0x40006a76\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 0x40006a88\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 0x40006a8a\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 0x40006a8c\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 0x40006a8e\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 0x40006a90\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 0x40006a92\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 0x40006a94\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 0x40006a96\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 0x40006aa8\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 0x40006aaa\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 0x40006aac\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 0x40006aae\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 0x40006ab0\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 0x40006ab2\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 0x40006ab4\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 0x40006ab6\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST 0x40006ac8\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST 0x40006aca\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST 0x40006acc\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST 0x40006ace\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST 0x40006ad0\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST 0x40006ad2\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST 0x40006ad4\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST 0x40006ad6\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL 0x40006ae8\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL 0x40006aea\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL 0x40006aec\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL 0x40006aee\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL 0x40006af0\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL 0x40006af2\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL 0x40006af4\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL 0x40006af6\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK 0x40006b08\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK 0x40006b0a\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK 0x40006b0c\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK 0x40006b0e\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK 0x40006b10\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK 0x40006b12\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK 0x40006b14\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK 0x40006b16\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL 0x40006b28\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL 0x40006b2a\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL 0x40006b2c\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL 0x40006b2e\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL 0x40006b30\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL 0x40006b32\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL 0x40006b34\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL 0x40006b36\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC 0x40006b48\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC 0x40006b4a\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC 0x40006b4c\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC 0x40006b4e\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC 0x40006b50\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC 0x40006b52\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC 0x40006b54\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC 0x40006b56\r
+#define CYDEV_PHUB_BASE 0x40007000\r
+#define CYDEV_PHUB_SIZE 0x00000c00\r
+#define CYDEV_PHUB_CFG 0x40007000\r
+#define CYDEV_PHUB_ERR 0x40007004\r
+#define CYDEV_PHUB_ERR_ADR 0x40007008\r
+#define CYDEV_PHUB_CH0_BASE 0x40007010\r
+#define CYDEV_PHUB_CH0_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH0_BASIC_CFG 0x40007010\r
+#define CYDEV_PHUB_CH0_ACTION 0x40007014\r
+#define CYDEV_PHUB_CH0_BASIC_STATUS 0x40007018\r
+#define CYDEV_PHUB_CH1_BASE 0x40007020\r
+#define CYDEV_PHUB_CH1_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH1_BASIC_CFG 0x40007020\r
+#define CYDEV_PHUB_CH1_ACTION 0x40007024\r
+#define CYDEV_PHUB_CH1_BASIC_STATUS 0x40007028\r
+#define CYDEV_PHUB_CH2_BASE 0x40007030\r
+#define CYDEV_PHUB_CH2_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH2_BASIC_CFG 0x40007030\r
+#define CYDEV_PHUB_CH2_ACTION 0x40007034\r
+#define CYDEV_PHUB_CH2_BASIC_STATUS 0x40007038\r
+#define CYDEV_PHUB_CH3_BASE 0x40007040\r
+#define CYDEV_PHUB_CH3_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH3_BASIC_CFG 0x40007040\r
+#define CYDEV_PHUB_CH3_ACTION 0x40007044\r
+#define CYDEV_PHUB_CH3_BASIC_STATUS 0x40007048\r
+#define CYDEV_PHUB_CH4_BASE 0x40007050\r
+#define CYDEV_PHUB_CH4_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH4_BASIC_CFG 0x40007050\r
+#define CYDEV_PHUB_CH4_ACTION 0x40007054\r
+#define CYDEV_PHUB_CH4_BASIC_STATUS 0x40007058\r
+#define CYDEV_PHUB_CH5_BASE 0x40007060\r
+#define CYDEV_PHUB_CH5_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH5_BASIC_CFG 0x40007060\r
+#define CYDEV_PHUB_CH5_ACTION 0x40007064\r
+#define CYDEV_PHUB_CH5_BASIC_STATUS 0x40007068\r
+#define CYDEV_PHUB_CH6_BASE 0x40007070\r
+#define CYDEV_PHUB_CH6_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH6_BASIC_CFG 0x40007070\r
+#define CYDEV_PHUB_CH6_ACTION 0x40007074\r
+#define CYDEV_PHUB_CH6_BASIC_STATUS 0x40007078\r
+#define CYDEV_PHUB_CH7_BASE 0x40007080\r
+#define CYDEV_PHUB_CH7_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH7_BASIC_CFG 0x40007080\r
+#define CYDEV_PHUB_CH7_ACTION 0x40007084\r
+#define CYDEV_PHUB_CH7_BASIC_STATUS 0x40007088\r
+#define CYDEV_PHUB_CH8_BASE 0x40007090\r
+#define CYDEV_PHUB_CH8_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH8_BASIC_CFG 0x40007090\r
+#define CYDEV_PHUB_CH8_ACTION 0x40007094\r
+#define CYDEV_PHUB_CH8_BASIC_STATUS 0x40007098\r
+#define CYDEV_PHUB_CH9_BASE 0x400070a0\r
+#define CYDEV_PHUB_CH9_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH9_BASIC_CFG 0x400070a0\r
+#define CYDEV_PHUB_CH9_ACTION 0x400070a4\r
+#define CYDEV_PHUB_CH9_BASIC_STATUS 0x400070a8\r
+#define CYDEV_PHUB_CH10_BASE 0x400070b0\r
+#define CYDEV_PHUB_CH10_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH10_BASIC_CFG 0x400070b0\r
+#define CYDEV_PHUB_CH10_ACTION 0x400070b4\r
+#define CYDEV_PHUB_CH10_BASIC_STATUS 0x400070b8\r
+#define CYDEV_PHUB_CH11_BASE 0x400070c0\r
+#define CYDEV_PHUB_CH11_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH11_BASIC_CFG 0x400070c0\r
+#define CYDEV_PHUB_CH11_ACTION 0x400070c4\r
+#define CYDEV_PHUB_CH11_BASIC_STATUS 0x400070c8\r
+#define CYDEV_PHUB_CH12_BASE 0x400070d0\r
+#define CYDEV_PHUB_CH12_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH12_BASIC_CFG 0x400070d0\r
+#define CYDEV_PHUB_CH12_ACTION 0x400070d4\r
+#define CYDEV_PHUB_CH12_BASIC_STATUS 0x400070d8\r
+#define CYDEV_PHUB_CH13_BASE 0x400070e0\r
+#define CYDEV_PHUB_CH13_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH13_BASIC_CFG 0x400070e0\r
+#define CYDEV_PHUB_CH13_ACTION 0x400070e4\r
+#define CYDEV_PHUB_CH13_BASIC_STATUS 0x400070e8\r
+#define CYDEV_PHUB_CH14_BASE 0x400070f0\r
+#define CYDEV_PHUB_CH14_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH14_BASIC_CFG 0x400070f0\r
+#define CYDEV_PHUB_CH14_ACTION 0x400070f4\r
+#define CYDEV_PHUB_CH14_BASIC_STATUS 0x400070f8\r
+#define CYDEV_PHUB_CH15_BASE 0x40007100\r
+#define CYDEV_PHUB_CH15_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH15_BASIC_CFG 0x40007100\r
+#define CYDEV_PHUB_CH15_ACTION 0x40007104\r
+#define CYDEV_PHUB_CH15_BASIC_STATUS 0x40007108\r
+#define CYDEV_PHUB_CH16_BASE 0x40007110\r
+#define CYDEV_PHUB_CH16_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH16_BASIC_CFG 0x40007110\r
+#define CYDEV_PHUB_CH16_ACTION 0x40007114\r
+#define CYDEV_PHUB_CH16_BASIC_STATUS 0x40007118\r
+#define CYDEV_PHUB_CH17_BASE 0x40007120\r
+#define CYDEV_PHUB_CH17_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH17_BASIC_CFG 0x40007120\r
+#define CYDEV_PHUB_CH17_ACTION 0x40007124\r
+#define CYDEV_PHUB_CH17_BASIC_STATUS 0x40007128\r
+#define CYDEV_PHUB_CH18_BASE 0x40007130\r
+#define CYDEV_PHUB_CH18_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH18_BASIC_CFG 0x40007130\r
+#define CYDEV_PHUB_CH18_ACTION 0x40007134\r
+#define CYDEV_PHUB_CH18_BASIC_STATUS 0x40007138\r
+#define CYDEV_PHUB_CH19_BASE 0x40007140\r
+#define CYDEV_PHUB_CH19_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH19_BASIC_CFG 0x40007140\r
+#define CYDEV_PHUB_CH19_ACTION 0x40007144\r
+#define CYDEV_PHUB_CH19_BASIC_STATUS 0x40007148\r
+#define CYDEV_PHUB_CH20_BASE 0x40007150\r
+#define CYDEV_PHUB_CH20_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH20_BASIC_CFG 0x40007150\r
+#define CYDEV_PHUB_CH20_ACTION 0x40007154\r
+#define CYDEV_PHUB_CH20_BASIC_STATUS 0x40007158\r
+#define CYDEV_PHUB_CH21_BASE 0x40007160\r
+#define CYDEV_PHUB_CH21_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH21_BASIC_CFG 0x40007160\r
+#define CYDEV_PHUB_CH21_ACTION 0x40007164\r
+#define CYDEV_PHUB_CH21_BASIC_STATUS 0x40007168\r
+#define CYDEV_PHUB_CH22_BASE 0x40007170\r
+#define CYDEV_PHUB_CH22_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH22_BASIC_CFG 0x40007170\r
+#define CYDEV_PHUB_CH22_ACTION 0x40007174\r
+#define CYDEV_PHUB_CH22_BASIC_STATUS 0x40007178\r
+#define CYDEV_PHUB_CH23_BASE 0x40007180\r
+#define CYDEV_PHUB_CH23_SIZE 0x0000000c\r
+#define CYDEV_PHUB_CH23_BASIC_CFG 0x40007180\r
+#define CYDEV_PHUB_CH23_ACTION 0x40007184\r
+#define CYDEV_PHUB_CH23_BASIC_STATUS 0x40007188\r
+#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600\r
+#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM0_CFG0 0x40007600\r
+#define CYDEV_PHUB_CFGMEM0_CFG1 0x40007604\r
+#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608\r
+#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM1_CFG0 0x40007608\r
+#define CYDEV_PHUB_CFGMEM1_CFG1 0x4000760c\r
+#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610\r
+#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM2_CFG0 0x40007610\r
+#define CYDEV_PHUB_CFGMEM2_CFG1 0x40007614\r
+#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618\r
+#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM3_CFG0 0x40007618\r
+#define CYDEV_PHUB_CFGMEM3_CFG1 0x4000761c\r
+#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620\r
+#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM4_CFG0 0x40007620\r
+#define CYDEV_PHUB_CFGMEM4_CFG1 0x40007624\r
+#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628\r
+#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM5_CFG0 0x40007628\r
+#define CYDEV_PHUB_CFGMEM5_CFG1 0x4000762c\r
+#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630\r
+#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM6_CFG0 0x40007630\r
+#define CYDEV_PHUB_CFGMEM6_CFG1 0x40007634\r
+#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638\r
+#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM7_CFG0 0x40007638\r
+#define CYDEV_PHUB_CFGMEM7_CFG1 0x4000763c\r
+#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640\r
+#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM8_CFG0 0x40007640\r
+#define CYDEV_PHUB_CFGMEM8_CFG1 0x40007644\r
+#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648\r
+#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM9_CFG0 0x40007648\r
+#define CYDEV_PHUB_CFGMEM9_CFG1 0x4000764c\r
+#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650\r
+#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM10_CFG0 0x40007650\r
+#define CYDEV_PHUB_CFGMEM10_CFG1 0x40007654\r
+#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658\r
+#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM11_CFG0 0x40007658\r
+#define CYDEV_PHUB_CFGMEM11_CFG1 0x4000765c\r
+#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660\r
+#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM12_CFG0 0x40007660\r
+#define CYDEV_PHUB_CFGMEM12_CFG1 0x40007664\r
+#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668\r
+#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM13_CFG0 0x40007668\r
+#define CYDEV_PHUB_CFGMEM13_CFG1 0x4000766c\r
+#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670\r
+#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM14_CFG0 0x40007670\r
+#define CYDEV_PHUB_CFGMEM14_CFG1 0x40007674\r
+#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678\r
+#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM15_CFG0 0x40007678\r
+#define CYDEV_PHUB_CFGMEM15_CFG1 0x4000767c\r
+#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680\r
+#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM16_CFG0 0x40007680\r
+#define CYDEV_PHUB_CFGMEM16_CFG1 0x40007684\r
+#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688\r
+#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM17_CFG0 0x40007688\r
+#define CYDEV_PHUB_CFGMEM17_CFG1 0x4000768c\r
+#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690\r
+#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM18_CFG0 0x40007690\r
+#define CYDEV_PHUB_CFGMEM18_CFG1 0x40007694\r
+#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698\r
+#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM19_CFG0 0x40007698\r
+#define CYDEV_PHUB_CFGMEM19_CFG1 0x4000769c\r
+#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0\r
+#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM20_CFG0 0x400076a0\r
+#define CYDEV_PHUB_CFGMEM20_CFG1 0x400076a4\r
+#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8\r
+#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM21_CFG0 0x400076a8\r
+#define CYDEV_PHUB_CFGMEM21_CFG1 0x400076ac\r
+#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0\r
+#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM22_CFG0 0x400076b0\r
+#define CYDEV_PHUB_CFGMEM22_CFG1 0x400076b4\r
+#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8\r
+#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008\r
+#define CYDEV_PHUB_CFGMEM23_CFG0 0x400076b8\r
+#define CYDEV_PHUB_CFGMEM23_CFG1 0x400076bc\r
+#define CYDEV_PHUB_TDMEM0_BASE 0x40007800\r
+#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM0_ORIG_TD0 0x40007800\r
+#define CYDEV_PHUB_TDMEM0_ORIG_TD1 0x40007804\r
+#define CYDEV_PHUB_TDMEM1_BASE 0x40007808\r
+#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM1_ORIG_TD0 0x40007808\r
+#define CYDEV_PHUB_TDMEM1_ORIG_TD1 0x4000780c\r
+#define CYDEV_PHUB_TDMEM2_BASE 0x40007810\r
+#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM2_ORIG_TD0 0x40007810\r
+#define CYDEV_PHUB_TDMEM2_ORIG_TD1 0x40007814\r
+#define CYDEV_PHUB_TDMEM3_BASE 0x40007818\r
+#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM3_ORIG_TD0 0x40007818\r
+#define CYDEV_PHUB_TDMEM3_ORIG_TD1 0x4000781c\r
+#define CYDEV_PHUB_TDMEM4_BASE 0x40007820\r
+#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM4_ORIG_TD0 0x40007820\r
+#define CYDEV_PHUB_TDMEM4_ORIG_TD1 0x40007824\r
+#define CYDEV_PHUB_TDMEM5_BASE 0x40007828\r
+#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM5_ORIG_TD0 0x40007828\r
+#define CYDEV_PHUB_TDMEM5_ORIG_TD1 0x4000782c\r
+#define CYDEV_PHUB_TDMEM6_BASE 0x40007830\r
+#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM6_ORIG_TD0 0x40007830\r
+#define CYDEV_PHUB_TDMEM6_ORIG_TD1 0x40007834\r
+#define CYDEV_PHUB_TDMEM7_BASE 0x40007838\r
+#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM7_ORIG_TD0 0x40007838\r
+#define CYDEV_PHUB_TDMEM7_ORIG_TD1 0x4000783c\r
+#define CYDEV_PHUB_TDMEM8_BASE 0x40007840\r
+#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM8_ORIG_TD0 0x40007840\r
+#define CYDEV_PHUB_TDMEM8_ORIG_TD1 0x40007844\r
+#define CYDEV_PHUB_TDMEM9_BASE 0x40007848\r
+#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM9_ORIG_TD0 0x40007848\r
+#define CYDEV_PHUB_TDMEM9_ORIG_TD1 0x4000784c\r
+#define CYDEV_PHUB_TDMEM10_BASE 0x40007850\r
+#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM10_ORIG_TD0 0x40007850\r
+#define CYDEV_PHUB_TDMEM10_ORIG_TD1 0x40007854\r
+#define CYDEV_PHUB_TDMEM11_BASE 0x40007858\r
+#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM11_ORIG_TD0 0x40007858\r
+#define CYDEV_PHUB_TDMEM11_ORIG_TD1 0x4000785c\r
+#define CYDEV_PHUB_TDMEM12_BASE 0x40007860\r
+#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM12_ORIG_TD0 0x40007860\r
+#define CYDEV_PHUB_TDMEM12_ORIG_TD1 0x40007864\r
+#define CYDEV_PHUB_TDMEM13_BASE 0x40007868\r
+#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM13_ORIG_TD0 0x40007868\r
+#define CYDEV_PHUB_TDMEM13_ORIG_TD1 0x4000786c\r
+#define CYDEV_PHUB_TDMEM14_BASE 0x40007870\r
+#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM14_ORIG_TD0 0x40007870\r
+#define CYDEV_PHUB_TDMEM14_ORIG_TD1 0x40007874\r
+#define CYDEV_PHUB_TDMEM15_BASE 0x40007878\r
+#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM15_ORIG_TD0 0x40007878\r
+#define CYDEV_PHUB_TDMEM15_ORIG_TD1 0x4000787c\r
+#define CYDEV_PHUB_TDMEM16_BASE 0x40007880\r
+#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM16_ORIG_TD0 0x40007880\r
+#define CYDEV_PHUB_TDMEM16_ORIG_TD1 0x40007884\r
+#define CYDEV_PHUB_TDMEM17_BASE 0x40007888\r
+#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM17_ORIG_TD0 0x40007888\r
+#define CYDEV_PHUB_TDMEM17_ORIG_TD1 0x4000788c\r
+#define CYDEV_PHUB_TDMEM18_BASE 0x40007890\r
+#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM18_ORIG_TD0 0x40007890\r
+#define CYDEV_PHUB_TDMEM18_ORIG_TD1 0x40007894\r
+#define CYDEV_PHUB_TDMEM19_BASE 0x40007898\r
+#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM19_ORIG_TD0 0x40007898\r
+#define CYDEV_PHUB_TDMEM19_ORIG_TD1 0x4000789c\r
+#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0\r
+#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM20_ORIG_TD0 0x400078a0\r
+#define CYDEV_PHUB_TDMEM20_ORIG_TD1 0x400078a4\r
+#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8\r
+#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM21_ORIG_TD0 0x400078a8\r
+#define CYDEV_PHUB_TDMEM21_ORIG_TD1 0x400078ac\r
+#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0\r
+#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM22_ORIG_TD0 0x400078b0\r
+#define CYDEV_PHUB_TDMEM22_ORIG_TD1 0x400078b4\r
+#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8\r
+#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM23_ORIG_TD0 0x400078b8\r
+#define CYDEV_PHUB_TDMEM23_ORIG_TD1 0x400078bc\r
+#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0\r
+#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM24_ORIG_TD0 0x400078c0\r
+#define CYDEV_PHUB_TDMEM24_ORIG_TD1 0x400078c4\r
+#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8\r
+#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM25_ORIG_TD0 0x400078c8\r
+#define CYDEV_PHUB_TDMEM25_ORIG_TD1 0x400078cc\r
+#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0\r
+#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM26_ORIG_TD0 0x400078d0\r
+#define CYDEV_PHUB_TDMEM26_ORIG_TD1 0x400078d4\r
+#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8\r
+#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM27_ORIG_TD0 0x400078d8\r
+#define CYDEV_PHUB_TDMEM27_ORIG_TD1 0x400078dc\r
+#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0\r
+#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM28_ORIG_TD0 0x400078e0\r
+#define CYDEV_PHUB_TDMEM28_ORIG_TD1 0x400078e4\r
+#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8\r
+#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM29_ORIG_TD0 0x400078e8\r
+#define CYDEV_PHUB_TDMEM29_ORIG_TD1 0x400078ec\r
+#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0\r
+#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM30_ORIG_TD0 0x400078f0\r
+#define CYDEV_PHUB_TDMEM30_ORIG_TD1 0x400078f4\r
+#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8\r
+#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM31_ORIG_TD0 0x400078f8\r
+#define CYDEV_PHUB_TDMEM31_ORIG_TD1 0x400078fc\r
+#define CYDEV_PHUB_TDMEM32_BASE 0x40007900\r
+#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM32_ORIG_TD0 0x40007900\r
+#define CYDEV_PHUB_TDMEM32_ORIG_TD1 0x40007904\r
+#define CYDEV_PHUB_TDMEM33_BASE 0x40007908\r
+#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM33_ORIG_TD0 0x40007908\r
+#define CYDEV_PHUB_TDMEM33_ORIG_TD1 0x4000790c\r
+#define CYDEV_PHUB_TDMEM34_BASE 0x40007910\r
+#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM34_ORIG_TD0 0x40007910\r
+#define CYDEV_PHUB_TDMEM34_ORIG_TD1 0x40007914\r
+#define CYDEV_PHUB_TDMEM35_BASE 0x40007918\r
+#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM35_ORIG_TD0 0x40007918\r
+#define CYDEV_PHUB_TDMEM35_ORIG_TD1 0x4000791c\r
+#define CYDEV_PHUB_TDMEM36_BASE 0x40007920\r
+#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM36_ORIG_TD0 0x40007920\r
+#define CYDEV_PHUB_TDMEM36_ORIG_TD1 0x40007924\r
+#define CYDEV_PHUB_TDMEM37_BASE 0x40007928\r
+#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM37_ORIG_TD0 0x40007928\r
+#define CYDEV_PHUB_TDMEM37_ORIG_TD1 0x4000792c\r
+#define CYDEV_PHUB_TDMEM38_BASE 0x40007930\r
+#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM38_ORIG_TD0 0x40007930\r
+#define CYDEV_PHUB_TDMEM38_ORIG_TD1 0x40007934\r
+#define CYDEV_PHUB_TDMEM39_BASE 0x40007938\r
+#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM39_ORIG_TD0 0x40007938\r
+#define CYDEV_PHUB_TDMEM39_ORIG_TD1 0x4000793c\r
+#define CYDEV_PHUB_TDMEM40_BASE 0x40007940\r
+#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM40_ORIG_TD0 0x40007940\r
+#define CYDEV_PHUB_TDMEM40_ORIG_TD1 0x40007944\r
+#define CYDEV_PHUB_TDMEM41_BASE 0x40007948\r
+#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM41_ORIG_TD0 0x40007948\r
+#define CYDEV_PHUB_TDMEM41_ORIG_TD1 0x4000794c\r
+#define CYDEV_PHUB_TDMEM42_BASE 0x40007950\r
+#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM42_ORIG_TD0 0x40007950\r
+#define CYDEV_PHUB_TDMEM42_ORIG_TD1 0x40007954\r
+#define CYDEV_PHUB_TDMEM43_BASE 0x40007958\r
+#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM43_ORIG_TD0 0x40007958\r
+#define CYDEV_PHUB_TDMEM43_ORIG_TD1 0x4000795c\r
+#define CYDEV_PHUB_TDMEM44_BASE 0x40007960\r
+#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM44_ORIG_TD0 0x40007960\r
+#define CYDEV_PHUB_TDMEM44_ORIG_TD1 0x40007964\r
+#define CYDEV_PHUB_TDMEM45_BASE 0x40007968\r
+#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM45_ORIG_TD0 0x40007968\r
+#define CYDEV_PHUB_TDMEM45_ORIG_TD1 0x4000796c\r
+#define CYDEV_PHUB_TDMEM46_BASE 0x40007970\r
+#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM46_ORIG_TD0 0x40007970\r
+#define CYDEV_PHUB_TDMEM46_ORIG_TD1 0x40007974\r
+#define CYDEV_PHUB_TDMEM47_BASE 0x40007978\r
+#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM47_ORIG_TD0 0x40007978\r
+#define CYDEV_PHUB_TDMEM47_ORIG_TD1 0x4000797c\r
+#define CYDEV_PHUB_TDMEM48_BASE 0x40007980\r
+#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM48_ORIG_TD0 0x40007980\r
+#define CYDEV_PHUB_TDMEM48_ORIG_TD1 0x40007984\r
+#define CYDEV_PHUB_TDMEM49_BASE 0x40007988\r
+#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM49_ORIG_TD0 0x40007988\r
+#define CYDEV_PHUB_TDMEM49_ORIG_TD1 0x4000798c\r
+#define CYDEV_PHUB_TDMEM50_BASE 0x40007990\r
+#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM50_ORIG_TD0 0x40007990\r
+#define CYDEV_PHUB_TDMEM50_ORIG_TD1 0x40007994\r
+#define CYDEV_PHUB_TDMEM51_BASE 0x40007998\r
+#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM51_ORIG_TD0 0x40007998\r
+#define CYDEV_PHUB_TDMEM51_ORIG_TD1 0x4000799c\r
+#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0\r
+#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM52_ORIG_TD0 0x400079a0\r
+#define CYDEV_PHUB_TDMEM52_ORIG_TD1 0x400079a4\r
+#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8\r
+#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM53_ORIG_TD0 0x400079a8\r
+#define CYDEV_PHUB_TDMEM53_ORIG_TD1 0x400079ac\r
+#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0\r
+#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM54_ORIG_TD0 0x400079b0\r
+#define CYDEV_PHUB_TDMEM54_ORIG_TD1 0x400079b4\r
+#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8\r
+#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM55_ORIG_TD0 0x400079b8\r
+#define CYDEV_PHUB_TDMEM55_ORIG_TD1 0x400079bc\r
+#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0\r
+#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM56_ORIG_TD0 0x400079c0\r
+#define CYDEV_PHUB_TDMEM56_ORIG_TD1 0x400079c4\r
+#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8\r
+#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM57_ORIG_TD0 0x400079c8\r
+#define CYDEV_PHUB_TDMEM57_ORIG_TD1 0x400079cc\r
+#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0\r
+#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM58_ORIG_TD0 0x400079d0\r
+#define CYDEV_PHUB_TDMEM58_ORIG_TD1 0x400079d4\r
+#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8\r
+#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM59_ORIG_TD0 0x400079d8\r
+#define CYDEV_PHUB_TDMEM59_ORIG_TD1 0x400079dc\r
+#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0\r
+#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM60_ORIG_TD0 0x400079e0\r
+#define CYDEV_PHUB_TDMEM60_ORIG_TD1 0x400079e4\r
+#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8\r
+#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM61_ORIG_TD0 0x400079e8\r
+#define CYDEV_PHUB_TDMEM61_ORIG_TD1 0x400079ec\r
+#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0\r
+#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM62_ORIG_TD0 0x400079f0\r
+#define CYDEV_PHUB_TDMEM62_ORIG_TD1 0x400079f4\r
+#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8\r
+#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM63_ORIG_TD0 0x400079f8\r
+#define CYDEV_PHUB_TDMEM63_ORIG_TD1 0x400079fc\r
+#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00\r
+#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM64_ORIG_TD0 0x40007a00\r
+#define CYDEV_PHUB_TDMEM64_ORIG_TD1 0x40007a04\r
+#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08\r
+#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM65_ORIG_TD0 0x40007a08\r
+#define CYDEV_PHUB_TDMEM65_ORIG_TD1 0x40007a0c\r
+#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10\r
+#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM66_ORIG_TD0 0x40007a10\r
+#define CYDEV_PHUB_TDMEM66_ORIG_TD1 0x40007a14\r
+#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18\r
+#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM67_ORIG_TD0 0x40007a18\r
+#define CYDEV_PHUB_TDMEM67_ORIG_TD1 0x40007a1c\r
+#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20\r
+#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM68_ORIG_TD0 0x40007a20\r
+#define CYDEV_PHUB_TDMEM68_ORIG_TD1 0x40007a24\r
+#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28\r
+#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM69_ORIG_TD0 0x40007a28\r
+#define CYDEV_PHUB_TDMEM69_ORIG_TD1 0x40007a2c\r
+#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30\r
+#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM70_ORIG_TD0 0x40007a30\r
+#define CYDEV_PHUB_TDMEM70_ORIG_TD1 0x40007a34\r
+#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38\r
+#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM71_ORIG_TD0 0x40007a38\r
+#define CYDEV_PHUB_TDMEM71_ORIG_TD1 0x40007a3c\r
+#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40\r
+#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM72_ORIG_TD0 0x40007a40\r
+#define CYDEV_PHUB_TDMEM72_ORIG_TD1 0x40007a44\r
+#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48\r
+#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM73_ORIG_TD0 0x40007a48\r
+#define CYDEV_PHUB_TDMEM73_ORIG_TD1 0x40007a4c\r
+#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50\r
+#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM74_ORIG_TD0 0x40007a50\r
+#define CYDEV_PHUB_TDMEM74_ORIG_TD1 0x40007a54\r
+#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58\r
+#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM75_ORIG_TD0 0x40007a58\r
+#define CYDEV_PHUB_TDMEM75_ORIG_TD1 0x40007a5c\r
+#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60\r
+#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM76_ORIG_TD0 0x40007a60\r
+#define CYDEV_PHUB_TDMEM76_ORIG_TD1 0x40007a64\r
+#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68\r
+#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM77_ORIG_TD0 0x40007a68\r
+#define CYDEV_PHUB_TDMEM77_ORIG_TD1 0x40007a6c\r
+#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70\r
+#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM78_ORIG_TD0 0x40007a70\r
+#define CYDEV_PHUB_TDMEM78_ORIG_TD1 0x40007a74\r
+#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78\r
+#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM79_ORIG_TD0 0x40007a78\r
+#define CYDEV_PHUB_TDMEM79_ORIG_TD1 0x40007a7c\r
+#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80\r
+#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM80_ORIG_TD0 0x40007a80\r
+#define CYDEV_PHUB_TDMEM80_ORIG_TD1 0x40007a84\r
+#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88\r
+#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM81_ORIG_TD0 0x40007a88\r
+#define CYDEV_PHUB_TDMEM81_ORIG_TD1 0x40007a8c\r
+#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90\r
+#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM82_ORIG_TD0 0x40007a90\r
+#define CYDEV_PHUB_TDMEM82_ORIG_TD1 0x40007a94\r
+#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98\r
+#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM83_ORIG_TD0 0x40007a98\r
+#define CYDEV_PHUB_TDMEM83_ORIG_TD1 0x40007a9c\r
+#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0\r
+#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM84_ORIG_TD0 0x40007aa0\r
+#define CYDEV_PHUB_TDMEM84_ORIG_TD1 0x40007aa4\r
+#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8\r
+#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM85_ORIG_TD0 0x40007aa8\r
+#define CYDEV_PHUB_TDMEM85_ORIG_TD1 0x40007aac\r
+#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0\r
+#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM86_ORIG_TD0 0x40007ab0\r
+#define CYDEV_PHUB_TDMEM86_ORIG_TD1 0x40007ab4\r
+#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8\r
+#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM87_ORIG_TD0 0x40007ab8\r
+#define CYDEV_PHUB_TDMEM87_ORIG_TD1 0x40007abc\r
+#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0\r
+#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM88_ORIG_TD0 0x40007ac0\r
+#define CYDEV_PHUB_TDMEM88_ORIG_TD1 0x40007ac4\r
+#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8\r
+#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM89_ORIG_TD0 0x40007ac8\r
+#define CYDEV_PHUB_TDMEM89_ORIG_TD1 0x40007acc\r
+#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0\r
+#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM90_ORIG_TD0 0x40007ad0\r
+#define CYDEV_PHUB_TDMEM90_ORIG_TD1 0x40007ad4\r
+#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8\r
+#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM91_ORIG_TD0 0x40007ad8\r
+#define CYDEV_PHUB_TDMEM91_ORIG_TD1 0x40007adc\r
+#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0\r
+#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM92_ORIG_TD0 0x40007ae0\r
+#define CYDEV_PHUB_TDMEM92_ORIG_TD1 0x40007ae4\r
+#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8\r
+#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM93_ORIG_TD0 0x40007ae8\r
+#define CYDEV_PHUB_TDMEM93_ORIG_TD1 0x40007aec\r
+#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0\r
+#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM94_ORIG_TD0 0x40007af0\r
+#define CYDEV_PHUB_TDMEM94_ORIG_TD1 0x40007af4\r
+#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8\r
+#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM95_ORIG_TD0 0x40007af8\r
+#define CYDEV_PHUB_TDMEM95_ORIG_TD1 0x40007afc\r
+#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00\r
+#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM96_ORIG_TD0 0x40007b00\r
+#define CYDEV_PHUB_TDMEM96_ORIG_TD1 0x40007b04\r
+#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08\r
+#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM97_ORIG_TD0 0x40007b08\r
+#define CYDEV_PHUB_TDMEM97_ORIG_TD1 0x40007b0c\r
+#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10\r
+#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM98_ORIG_TD0 0x40007b10\r
+#define CYDEV_PHUB_TDMEM98_ORIG_TD1 0x40007b14\r
+#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18\r
+#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM99_ORIG_TD0 0x40007b18\r
+#define CYDEV_PHUB_TDMEM99_ORIG_TD1 0x40007b1c\r
+#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20\r
+#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM100_ORIG_TD0 0x40007b20\r
+#define CYDEV_PHUB_TDMEM100_ORIG_TD1 0x40007b24\r
+#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28\r
+#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM101_ORIG_TD0 0x40007b28\r
+#define CYDEV_PHUB_TDMEM101_ORIG_TD1 0x40007b2c\r
+#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30\r
+#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM102_ORIG_TD0 0x40007b30\r
+#define CYDEV_PHUB_TDMEM102_ORIG_TD1 0x40007b34\r
+#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38\r
+#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM103_ORIG_TD0 0x40007b38\r
+#define CYDEV_PHUB_TDMEM103_ORIG_TD1 0x40007b3c\r
+#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40\r
+#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM104_ORIG_TD0 0x40007b40\r
+#define CYDEV_PHUB_TDMEM104_ORIG_TD1 0x40007b44\r
+#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48\r
+#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM105_ORIG_TD0 0x40007b48\r
+#define CYDEV_PHUB_TDMEM105_ORIG_TD1 0x40007b4c\r
+#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50\r
+#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM106_ORIG_TD0 0x40007b50\r
+#define CYDEV_PHUB_TDMEM106_ORIG_TD1 0x40007b54\r
+#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58\r
+#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM107_ORIG_TD0 0x40007b58\r
+#define CYDEV_PHUB_TDMEM107_ORIG_TD1 0x40007b5c\r
+#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60\r
+#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM108_ORIG_TD0 0x40007b60\r
+#define CYDEV_PHUB_TDMEM108_ORIG_TD1 0x40007b64\r
+#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68\r
+#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM109_ORIG_TD0 0x40007b68\r
+#define CYDEV_PHUB_TDMEM109_ORIG_TD1 0x40007b6c\r
+#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70\r
+#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM110_ORIG_TD0 0x40007b70\r
+#define CYDEV_PHUB_TDMEM110_ORIG_TD1 0x40007b74\r
+#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78\r
+#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM111_ORIG_TD0 0x40007b78\r
+#define CYDEV_PHUB_TDMEM111_ORIG_TD1 0x40007b7c\r
+#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80\r
+#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM112_ORIG_TD0 0x40007b80\r
+#define CYDEV_PHUB_TDMEM112_ORIG_TD1 0x40007b84\r
+#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88\r
+#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM113_ORIG_TD0 0x40007b88\r
+#define CYDEV_PHUB_TDMEM113_ORIG_TD1 0x40007b8c\r
+#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90\r
+#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM114_ORIG_TD0 0x40007b90\r
+#define CYDEV_PHUB_TDMEM114_ORIG_TD1 0x40007b94\r
+#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98\r
+#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM115_ORIG_TD0 0x40007b98\r
+#define CYDEV_PHUB_TDMEM115_ORIG_TD1 0x40007b9c\r
+#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0\r
+#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM116_ORIG_TD0 0x40007ba0\r
+#define CYDEV_PHUB_TDMEM116_ORIG_TD1 0x40007ba4\r
+#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8\r
+#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM117_ORIG_TD0 0x40007ba8\r
+#define CYDEV_PHUB_TDMEM117_ORIG_TD1 0x40007bac\r
+#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0\r
+#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM118_ORIG_TD0 0x40007bb0\r
+#define CYDEV_PHUB_TDMEM118_ORIG_TD1 0x40007bb4\r
+#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8\r
+#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM119_ORIG_TD0 0x40007bb8\r
+#define CYDEV_PHUB_TDMEM119_ORIG_TD1 0x40007bbc\r
+#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0\r
+#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM120_ORIG_TD0 0x40007bc0\r
+#define CYDEV_PHUB_TDMEM120_ORIG_TD1 0x40007bc4\r
+#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8\r
+#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM121_ORIG_TD0 0x40007bc8\r
+#define CYDEV_PHUB_TDMEM121_ORIG_TD1 0x40007bcc\r
+#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0\r
+#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM122_ORIG_TD0 0x40007bd0\r
+#define CYDEV_PHUB_TDMEM122_ORIG_TD1 0x40007bd4\r
+#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8\r
+#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM123_ORIG_TD0 0x40007bd8\r
+#define CYDEV_PHUB_TDMEM123_ORIG_TD1 0x40007bdc\r
+#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0\r
+#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM124_ORIG_TD0 0x40007be0\r
+#define CYDEV_PHUB_TDMEM124_ORIG_TD1 0x40007be4\r
+#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8\r
+#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM125_ORIG_TD0 0x40007be8\r
+#define CYDEV_PHUB_TDMEM125_ORIG_TD1 0x40007bec\r
+#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0\r
+#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM126_ORIG_TD0 0x40007bf0\r
+#define CYDEV_PHUB_TDMEM126_ORIG_TD1 0x40007bf4\r
+#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8\r
+#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008\r
+#define CYDEV_PHUB_TDMEM127_ORIG_TD0 0x40007bf8\r
+#define CYDEV_PHUB_TDMEM127_ORIG_TD1 0x40007bfc\r
+#define CYDEV_EE_BASE 0x40008000\r
+#define CYDEV_EE_SIZE 0x00000800\r
+#define CYDEV_EE_DATA_MBASE 0x40008000\r
+#define CYDEV_EE_DATA_MSIZE 0x00000800\r
+#define CYDEV_CAN0_BASE 0x4000a000\r
+#define CYDEV_CAN0_SIZE 0x000002a0\r
+#define CYDEV_CAN0_CSR_BASE 0x4000a000\r
+#define CYDEV_CAN0_CSR_SIZE 0x00000018\r
+#define CYDEV_CAN0_CSR_INT_SR 0x4000a000\r
+#define CYDEV_CAN0_CSR_INT_EN 0x4000a004\r
+#define CYDEV_CAN0_CSR_BUF_SR 0x4000a008\r
+#define CYDEV_CAN0_CSR_ERR_SR 0x4000a00c\r
+#define CYDEV_CAN0_CSR_CMD 0x4000a010\r
+#define CYDEV_CAN0_CSR_CFG 0x4000a014\r
+#define CYDEV_CAN0_TX0_BASE 0x4000a020\r
+#define CYDEV_CAN0_TX0_SIZE 0x00000010\r
+#define CYDEV_CAN0_TX0_CMD 0x4000a020\r
+#define CYDEV_CAN0_TX0_ID 0x4000a024\r
+#define CYDEV_CAN0_TX0_DH 0x4000a028\r
+#define CYDEV_CAN0_TX0_DL 0x4000a02c\r
+#define CYDEV_CAN0_TX1_BASE 0x4000a030\r
+#define CYDEV_CAN0_TX1_SIZE 0x00000010\r
+#define CYDEV_CAN0_TX1_CMD 0x4000a030\r
+#define CYDEV_CAN0_TX1_ID 0x4000a034\r
+#define CYDEV_CAN0_TX1_DH 0x4000a038\r
+#define CYDEV_CAN0_TX1_DL 0x4000a03c\r
+#define CYDEV_CAN0_TX2_BASE 0x4000a040\r
+#define CYDEV_CAN0_TX2_SIZE 0x00000010\r
+#define CYDEV_CAN0_TX2_CMD 0x4000a040\r
+#define CYDEV_CAN0_TX2_ID 0x4000a044\r
+#define CYDEV_CAN0_TX2_DH 0x4000a048\r
+#define CYDEV_CAN0_TX2_DL 0x4000a04c\r
+#define CYDEV_CAN0_TX3_BASE 0x4000a050\r
+#define CYDEV_CAN0_TX3_SIZE 0x00000010\r
+#define CYDEV_CAN0_TX3_CMD 0x4000a050\r
+#define CYDEV_CAN0_TX3_ID 0x4000a054\r
+#define CYDEV_CAN0_TX3_DH 0x4000a058\r
+#define CYDEV_CAN0_TX3_DL 0x4000a05c\r
+#define CYDEV_CAN0_TX4_BASE 0x4000a060\r
+#define CYDEV_CAN0_TX4_SIZE 0x00000010\r
+#define CYDEV_CAN0_TX4_CMD 0x4000a060\r
+#define CYDEV_CAN0_TX4_ID 0x4000a064\r
+#define CYDEV_CAN0_TX4_DH 0x4000a068\r
+#define CYDEV_CAN0_TX4_DL 0x4000a06c\r
+#define CYDEV_CAN0_TX5_BASE 0x4000a070\r
+#define CYDEV_CAN0_TX5_SIZE 0x00000010\r
+#define CYDEV_CAN0_TX5_CMD 0x4000a070\r
+#define CYDEV_CAN0_TX5_ID 0x4000a074\r
+#define CYDEV_CAN0_TX5_DH 0x4000a078\r
+#define CYDEV_CAN0_TX5_DL 0x4000a07c\r
+#define CYDEV_CAN0_TX6_BASE 0x4000a080\r
+#define CYDEV_CAN0_TX6_SIZE 0x00000010\r
+#define CYDEV_CAN0_TX6_CMD 0x4000a080\r
+#define CYDEV_CAN0_TX6_ID 0x4000a084\r
+#define CYDEV_CAN0_TX6_DH 0x4000a088\r
+#define CYDEV_CAN0_TX6_DL 0x4000a08c\r
+#define CYDEV_CAN0_TX7_BASE 0x4000a090\r
+#define CYDEV_CAN0_TX7_SIZE 0x00000010\r
+#define CYDEV_CAN0_TX7_CMD 0x4000a090\r
+#define CYDEV_CAN0_TX7_ID 0x4000a094\r
+#define CYDEV_CAN0_TX7_DH 0x4000a098\r
+#define CYDEV_CAN0_TX7_DL 0x4000a09c\r
+#define CYDEV_CAN0_RX0_BASE 0x4000a0a0\r
+#define CYDEV_CAN0_RX0_SIZE 0x00000020\r
+#define CYDEV_CAN0_RX0_CMD 0x4000a0a0\r
+#define CYDEV_CAN0_RX0_ID 0x4000a0a4\r
+#define CYDEV_CAN0_RX0_DH 0x4000a0a8\r
+#define CYDEV_CAN0_RX0_DL 0x4000a0ac\r
+#define CYDEV_CAN0_RX0_AMR 0x4000a0b0\r
+#define CYDEV_CAN0_RX0_ACR 0x4000a0b4\r
+#define CYDEV_CAN0_RX0_AMRD 0x4000a0b8\r
+#define CYDEV_CAN0_RX0_ACRD 0x4000a0bc\r
+#define CYDEV_CAN0_RX1_BASE 0x4000a0c0\r
+#define CYDEV_CAN0_RX1_SIZE 0x00000020\r
+#define CYDEV_CAN0_RX1_CMD 0x4000a0c0\r
+#define CYDEV_CAN0_RX1_ID 0x4000a0c4\r
+#define CYDEV_CAN0_RX1_DH 0x4000a0c8\r
+#define CYDEV_CAN0_RX1_DL 0x4000a0cc\r
+#define CYDEV_CAN0_RX1_AMR 0x4000a0d0\r
+#define CYDEV_CAN0_RX1_ACR 0x4000a0d4\r
+#define CYDEV_CAN0_RX1_AMRD 0x4000a0d8\r
+#define CYDEV_CAN0_RX1_ACRD 0x4000a0dc\r
+#define CYDEV_CAN0_RX2_BASE 0x4000a0e0\r
+#define CYDEV_CAN0_RX2_SIZE 0x00000020\r
+#define CYDEV_CAN0_RX2_CMD 0x4000a0e0\r
+#define CYDEV_CAN0_RX2_ID 0x4000a0e4\r
+#define CYDEV_CAN0_RX2_DH 0x4000a0e8\r
+#define CYDEV_CAN0_RX2_DL 0x4000a0ec\r
+#define CYDEV_CAN0_RX2_AMR 0x4000a0f0\r
+#define CYDEV_CAN0_RX2_ACR 0x4000a0f4\r
+#define CYDEV_CAN0_RX2_AMRD 0x4000a0f8\r
+#define CYDEV_CAN0_RX2_ACRD 0x4000a0fc\r
+#define CYDEV_CAN0_RX3_BASE 0x4000a100\r
+#define CYDEV_CAN0_RX3_SIZE 0x00000020\r
+#define CYDEV_CAN0_RX3_CMD 0x4000a100\r
+#define CYDEV_CAN0_RX3_ID 0x4000a104\r
+#define CYDEV_CAN0_RX3_DH 0x4000a108\r
+#define CYDEV_CAN0_RX3_DL 0x4000a10c\r
+#define CYDEV_CAN0_RX3_AMR 0x4000a110\r
+#define CYDEV_CAN0_RX3_ACR 0x4000a114\r
+#define CYDEV_CAN0_RX3_AMRD 0x4000a118\r
+#define CYDEV_CAN0_RX3_ACRD 0x4000a11c\r
+#define CYDEV_CAN0_RX4_BASE 0x4000a120\r
+#define CYDEV_CAN0_RX4_SIZE 0x00000020\r
+#define CYDEV_CAN0_RX4_CMD 0x4000a120\r
+#define CYDEV_CAN0_RX4_ID 0x4000a124\r
+#define CYDEV_CAN0_RX4_DH 0x4000a128\r
+#define CYDEV_CAN0_RX4_DL 0x4000a12c\r
+#define CYDEV_CAN0_RX4_AMR 0x4000a130\r
+#define CYDEV_CAN0_RX4_ACR 0x4000a134\r
+#define CYDEV_CAN0_RX4_AMRD 0x4000a138\r
+#define CYDEV_CAN0_RX4_ACRD 0x4000a13c\r
+#define CYDEV_CAN0_RX5_BASE 0x4000a140\r
+#define CYDEV_CAN0_RX5_SIZE 0x00000020\r
+#define CYDEV_CAN0_RX5_CMD 0x4000a140\r
+#define CYDEV_CAN0_RX5_ID 0x4000a144\r
+#define CYDEV_CAN0_RX5_DH 0x4000a148\r
+#define CYDEV_CAN0_RX5_DL 0x4000a14c\r
+#define CYDEV_CAN0_RX5_AMR 0x4000a150\r
+#define CYDEV_CAN0_RX5_ACR 0x4000a154\r
+#define CYDEV_CAN0_RX5_AMRD 0x4000a158\r
+#define CYDEV_CAN0_RX5_ACRD 0x4000a15c\r
+#define CYDEV_CAN0_RX6_BASE 0x4000a160\r
+#define CYDEV_CAN0_RX6_SIZE 0x00000020\r
+#define CYDEV_CAN0_RX6_CMD 0x4000a160\r
+#define CYDEV_CAN0_RX6_ID 0x4000a164\r
+#define CYDEV_CAN0_RX6_DH 0x4000a168\r
+#define CYDEV_CAN0_RX6_DL 0x4000a16c\r
+#define CYDEV_CAN0_RX6_AMR 0x4000a170\r
+#define CYDEV_CAN0_RX6_ACR 0x4000a174\r
+#define CYDEV_CAN0_RX6_AMRD 0x4000a178\r
+#define CYDEV_CAN0_RX6_ACRD 0x4000a17c\r
+#define CYDEV_CAN0_RX7_BASE 0x4000a180\r
+#define CYDEV_CAN0_RX7_SIZE 0x00000020\r
+#define CYDEV_CAN0_RX7_CMD 0x4000a180\r
+#define CYDEV_CAN0_RX7_ID 0x4000a184\r
+#define CYDEV_CAN0_RX7_DH 0x4000a188\r
+#define CYDEV_CAN0_RX7_DL 0x4000a18c\r
+#define CYDEV_CAN0_RX7_AMR 0x4000a190\r
+#define CYDEV_CAN0_RX7_ACR 0x4000a194\r
+#define CYDEV_CAN0_RX7_AMRD 0x4000a198\r
+#define CYDEV_CAN0_RX7_ACRD 0x4000a19c\r
+#define CYDEV_CAN0_RX8_BASE 0x4000a1a0\r
+#define CYDEV_CAN0_RX8_SIZE 0x00000020\r
+#define CYDEV_CAN0_RX8_CMD 0x4000a1a0\r
+#define CYDEV_CAN0_RX8_ID 0x4000a1a4\r
+#define CYDEV_CAN0_RX8_DH 0x4000a1a8\r
+#define CYDEV_CAN0_RX8_DL 0x4000a1ac\r
+#define CYDEV_CAN0_RX8_AMR 0x4000a1b0\r
+#define CYDEV_CAN0_RX8_ACR 0x4000a1b4\r
+#define CYDEV_CAN0_RX8_AMRD 0x4000a1b8\r
+#define CYDEV_CAN0_RX8_ACRD 0x4000a1bc\r
+#define CYDEV_CAN0_RX9_BASE 0x4000a1c0\r
+#define CYDEV_CAN0_RX9_SIZE 0x00000020\r
+#define CYDEV_CAN0_RX9_CMD 0x4000a1c0\r
+#define CYDEV_CAN0_RX9_ID 0x4000a1c4\r
+#define CYDEV_CAN0_RX9_DH 0x4000a1c8\r
+#define CYDEV_CAN0_RX9_DL 0x4000a1cc\r
+#define CYDEV_CAN0_RX9_AMR 0x4000a1d0\r
+#define CYDEV_CAN0_RX9_ACR 0x4000a1d4\r
+#define CYDEV_CAN0_RX9_AMRD 0x4000a1d8\r
+#define CYDEV_CAN0_RX9_ACRD 0x4000a1dc\r
+#define CYDEV_CAN0_RX10_BASE 0x4000a1e0\r
+#define CYDEV_CAN0_RX10_SIZE 0x00000020\r
+#define CYDEV_CAN0_RX10_CMD 0x4000a1e0\r
+#define CYDEV_CAN0_RX10_ID 0x4000a1e4\r
+#define CYDEV_CAN0_RX10_DH 0x4000a1e8\r
+#define CYDEV_CAN0_RX10_DL 0x4000a1ec\r
+#define CYDEV_CAN0_RX10_AMR 0x4000a1f0\r
+#define CYDEV_CAN0_RX10_ACR 0x4000a1f4\r
+#define CYDEV_CAN0_RX10_AMRD 0x4000a1f8\r
+#define CYDEV_CAN0_RX10_ACRD 0x4000a1fc\r
+#define CYDEV_CAN0_RX11_BASE 0x4000a200\r
+#define CYDEV_CAN0_RX11_SIZE 0x00000020\r
+#define CYDEV_CAN0_RX11_CMD 0x4000a200\r
+#define CYDEV_CAN0_RX11_ID 0x4000a204\r
+#define CYDEV_CAN0_RX11_DH 0x4000a208\r
+#define CYDEV_CAN0_RX11_DL 0x4000a20c\r
+#define CYDEV_CAN0_RX11_AMR 0x4000a210\r
+#define CYDEV_CAN0_RX11_ACR 0x4000a214\r
+#define CYDEV_CAN0_RX11_AMRD 0x4000a218\r
+#define CYDEV_CAN0_RX11_ACRD 0x4000a21c\r
+#define CYDEV_CAN0_RX12_BASE 0x4000a220\r
+#define CYDEV_CAN0_RX12_SIZE 0x00000020\r
+#define CYDEV_CAN0_RX12_CMD 0x4000a220\r
+#define CYDEV_CAN0_RX12_ID 0x4000a224\r
+#define CYDEV_CAN0_RX12_DH 0x4000a228\r
+#define CYDEV_CAN0_RX12_DL 0x4000a22c\r
+#define CYDEV_CAN0_RX12_AMR 0x4000a230\r
+#define CYDEV_CAN0_RX12_ACR 0x4000a234\r
+#define CYDEV_CAN0_RX12_AMRD 0x4000a238\r
+#define CYDEV_CAN0_RX12_ACRD 0x4000a23c\r
+#define CYDEV_CAN0_RX13_BASE 0x4000a240\r
+#define CYDEV_CAN0_RX13_SIZE 0x00000020\r
+#define CYDEV_CAN0_RX13_CMD 0x4000a240\r
+#define CYDEV_CAN0_RX13_ID 0x4000a244\r
+#define CYDEV_CAN0_RX13_DH 0x4000a248\r
+#define CYDEV_CAN0_RX13_DL 0x4000a24c\r
+#define CYDEV_CAN0_RX13_AMR 0x4000a250\r
+#define CYDEV_CAN0_RX13_ACR 0x4000a254\r
+#define CYDEV_CAN0_RX13_AMRD 0x4000a258\r
+#define CYDEV_CAN0_RX13_ACRD 0x4000a25c\r
+#define CYDEV_CAN0_RX14_BASE 0x4000a260\r
+#define CYDEV_CAN0_RX14_SIZE 0x00000020\r
+#define CYDEV_CAN0_RX14_CMD 0x4000a260\r
+#define CYDEV_CAN0_RX14_ID 0x4000a264\r
+#define CYDEV_CAN0_RX14_DH 0x4000a268\r
+#define CYDEV_CAN0_RX14_DL 0x4000a26c\r
+#define CYDEV_CAN0_RX14_AMR 0x4000a270\r
+#define CYDEV_CAN0_RX14_ACR 0x4000a274\r
+#define CYDEV_CAN0_RX14_AMRD 0x4000a278\r
+#define CYDEV_CAN0_RX14_ACRD 0x4000a27c\r
+#define CYDEV_CAN0_RX15_BASE 0x4000a280\r
+#define CYDEV_CAN0_RX15_SIZE 0x00000020\r
+#define CYDEV_CAN0_RX15_CMD 0x4000a280\r
+#define CYDEV_CAN0_RX15_ID 0x4000a284\r
+#define CYDEV_CAN0_RX15_DH 0x4000a288\r
+#define CYDEV_CAN0_RX15_DL 0x4000a28c\r
+#define CYDEV_CAN0_RX15_AMR 0x4000a290\r
+#define CYDEV_CAN0_RX15_ACR 0x4000a294\r
+#define CYDEV_CAN0_RX15_AMRD 0x4000a298\r
+#define CYDEV_CAN0_RX15_ACRD 0x4000a29c\r
+#define CYDEV_DFB0_BASE 0x4000c000\r
+#define CYDEV_DFB0_SIZE 0x000007b5\r
+#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000\r
+#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200\r
+#define CYDEV_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000\r
+#define CYDEV_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200\r
+#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200\r
+#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200\r
+#define CYDEV_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200\r
+#define CYDEV_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200\r
+#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400\r
+#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100\r
+#define CYDEV_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400\r
+#define CYDEV_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100\r
+#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500\r
+#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100\r
+#define CYDEV_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500\r
+#define CYDEV_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100\r
+#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600\r
+#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100\r
+#define CYDEV_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600\r
+#define CYDEV_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100\r
+#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700\r
+#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040\r
+#define CYDEV_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700\r
+#define CYDEV_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040\r
+#define CYDEV_DFB0_CR 0x4000c780\r
+#define CYDEV_DFB0_SR 0x4000c784\r
+#define CYDEV_DFB0_RAM_EN 0x4000c788\r
+#define CYDEV_DFB0_RAM_DIR 0x4000c78c\r
+#define CYDEV_DFB0_SEMA 0x4000c790\r
+#define CYDEV_DFB0_DSI_CTRL 0x4000c794\r
+#define CYDEV_DFB0_INT_CTRL 0x4000c798\r
+#define CYDEV_DFB0_DMA_CTRL 0x4000c79c\r
+#define CYDEV_DFB0_STAGEA 0x4000c7a0\r
+#define CYDEV_DFB0_STAGEAM 0x4000c7a1\r
+#define CYDEV_DFB0_STAGEAH 0x4000c7a2\r
+#define CYDEV_DFB0_STAGEB 0x4000c7a4\r
+#define CYDEV_DFB0_STAGEBM 0x4000c7a5\r
+#define CYDEV_DFB0_STAGEBH 0x4000c7a6\r
+#define CYDEV_DFB0_HOLDA 0x4000c7a8\r
+#define CYDEV_DFB0_HOLDAM 0x4000c7a9\r
+#define CYDEV_DFB0_HOLDAH 0x4000c7aa\r
+#define CYDEV_DFB0_HOLDAS 0x4000c7ab\r
+#define CYDEV_DFB0_HOLDB 0x4000c7ac\r
+#define CYDEV_DFB0_HOLDBM 0x4000c7ad\r
+#define CYDEV_DFB0_HOLDBH 0x4000c7ae\r
+#define CYDEV_DFB0_HOLDBS 0x4000c7af\r
+#define CYDEV_DFB0_COHER 0x4000c7b0\r
+#define CYDEV_DFB0_DALIGN 0x4000c7b4\r
+#define CYDEV_UCFG_BASE 0x40010000\r
+#define CYDEV_UCFG_SIZE 0x00005040\r
+#define CYDEV_UCFG_B0_BASE 0x40010000\r
+#define CYDEV_UCFG_B0_SIZE 0x00000fef\r
+#define CYDEV_UCFG_B0_P0_BASE 0x40010000\r
+#define CYDEV_UCFG_B0_P0_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000\r
+#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT0 0x40010000\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT1 0x40010004\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT2 0x40010008\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT3 0x4001000c\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT4 0x40010010\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT5 0x40010014\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT6 0x40010018\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT7 0x4001001c\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT8 0x40010020\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT9 0x40010024\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT10 0x40010028\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT11 0x4001002c\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_ORT0 0x40010030\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_ORT1 0x40010032\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_ORT2 0x40010034\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_ORT3 0x40010036\r
+#define CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038\r
+#define CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB 0x4001003a\r
+#define CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003c\r
+#define CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS 0x4001003e\r
+#define CYDEV_UCFG_B0_P0_U0_CFG0 0x40010040\r
+#define CYDEV_UCFG_B0_P0_U0_CFG1 0x40010041\r
+#define CYDEV_UCFG_B0_P0_U0_CFG2 0x40010042\r
+#define CYDEV_UCFG_B0_P0_U0_CFG3 0x40010043\r
+#define CYDEV_UCFG_B0_P0_U0_CFG4 0x40010044\r
+#define CYDEV_UCFG_B0_P0_U0_CFG5 0x40010045\r
+#define CYDEV_UCFG_B0_P0_U0_CFG6 0x40010046\r
+#define CYDEV_UCFG_B0_P0_U0_CFG7 0x40010047\r
+#define CYDEV_UCFG_B0_P0_U0_CFG8 0x40010048\r
+#define CYDEV_UCFG_B0_P0_U0_CFG9 0x40010049\r
+#define CYDEV_UCFG_B0_P0_U0_CFG10 0x4001004a\r
+#define CYDEV_UCFG_B0_P0_U0_CFG11 0x4001004b\r
+#define CYDEV_UCFG_B0_P0_U0_CFG12 0x4001004c\r
+#define CYDEV_UCFG_B0_P0_U0_CFG13 0x4001004d\r
+#define CYDEV_UCFG_B0_P0_U0_CFG14 0x4001004e\r
+#define CYDEV_UCFG_B0_P0_U0_CFG15 0x4001004f\r
+#define CYDEV_UCFG_B0_P0_U0_CFG16 0x40010050\r
+#define CYDEV_UCFG_B0_P0_U0_CFG17 0x40010051\r
+#define CYDEV_UCFG_B0_P0_U0_CFG18 0x40010052\r
+#define CYDEV_UCFG_B0_P0_U0_CFG19 0x40010053\r
+#define CYDEV_UCFG_B0_P0_U0_CFG20 0x40010054\r
+#define CYDEV_UCFG_B0_P0_U0_CFG21 0x40010055\r
+#define CYDEV_UCFG_B0_P0_U0_CFG22 0x40010056\r
+#define CYDEV_UCFG_B0_P0_U0_CFG23 0x40010057\r
+#define CYDEV_UCFG_B0_P0_U0_CFG24 0x40010058\r
+#define CYDEV_UCFG_B0_P0_U0_CFG25 0x40010059\r
+#define CYDEV_UCFG_B0_P0_U0_CFG26 0x4001005a\r
+#define CYDEV_UCFG_B0_P0_U0_CFG27 0x4001005b\r
+#define CYDEV_UCFG_B0_P0_U0_CFG28 0x4001005c\r
+#define CYDEV_UCFG_B0_P0_U0_CFG29 0x4001005d\r
+#define CYDEV_UCFG_B0_P0_U0_CFG30 0x4001005e\r
+#define CYDEV_UCFG_B0_P0_U0_CFG31 0x4001005f\r
+#define CYDEV_UCFG_B0_P0_U0_DCFG0 0x40010060\r
+#define CYDEV_UCFG_B0_P0_U0_DCFG1 0x40010062\r
+#define CYDEV_UCFG_B0_P0_U0_DCFG2 0x40010064\r
+#define CYDEV_UCFG_B0_P0_U0_DCFG3 0x40010066\r
+#define CYDEV_UCFG_B0_P0_U0_DCFG4 0x40010068\r
+#define CYDEV_UCFG_B0_P0_U0_DCFG5 0x4001006a\r
+#define CYDEV_UCFG_B0_P0_U0_DCFG6 0x4001006c\r
+#define CYDEV_UCFG_B0_P0_U0_DCFG7 0x4001006e\r
+#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080\r
+#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT0 0x40010080\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT1 0x40010084\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT2 0x40010088\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT3 0x4001008c\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT4 0x40010090\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT5 0x40010094\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT6 0x40010098\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT7 0x4001009c\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT8 0x400100a0\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT9 0x400100a4\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT10 0x400100a8\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT11 0x400100ac\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_ORT0 0x400100b0\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_ORT1 0x400100b2\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_ORT2 0x400100b4\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_ORT3 0x400100b6\r
+#define CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8\r
+#define CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB 0x400100ba\r
+#define CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bc\r
+#define CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS 0x400100be\r
+#define CYDEV_UCFG_B0_P0_U1_CFG0 0x400100c0\r
+#define CYDEV_UCFG_B0_P0_U1_CFG1 0x400100c1\r
+#define CYDEV_UCFG_B0_P0_U1_CFG2 0x400100c2\r
+#define CYDEV_UCFG_B0_P0_U1_CFG3 0x400100c3\r
+#define CYDEV_UCFG_B0_P0_U1_CFG4 0x400100c4\r
+#define CYDEV_UCFG_B0_P0_U1_CFG5 0x400100c5\r
+#define CYDEV_UCFG_B0_P0_U1_CFG6 0x400100c6\r
+#define CYDEV_UCFG_B0_P0_U1_CFG7 0x400100c7\r
+#define CYDEV_UCFG_B0_P0_U1_CFG8 0x400100c8\r
+#define CYDEV_UCFG_B0_P0_U1_CFG9 0x400100c9\r
+#define CYDEV_UCFG_B0_P0_U1_CFG10 0x400100ca\r
+#define CYDEV_UCFG_B0_P0_U1_CFG11 0x400100cb\r
+#define CYDEV_UCFG_B0_P0_U1_CFG12 0x400100cc\r
+#define CYDEV_UCFG_B0_P0_U1_CFG13 0x400100cd\r
+#define CYDEV_UCFG_B0_P0_U1_CFG14 0x400100ce\r
+#define CYDEV_UCFG_B0_P0_U1_CFG15 0x400100cf\r
+#define CYDEV_UCFG_B0_P0_U1_CFG16 0x400100d0\r
+#define CYDEV_UCFG_B0_P0_U1_CFG17 0x400100d1\r
+#define CYDEV_UCFG_B0_P0_U1_CFG18 0x400100d2\r
+#define CYDEV_UCFG_B0_P0_U1_CFG19 0x400100d3\r
+#define CYDEV_UCFG_B0_P0_U1_CFG20 0x400100d4\r
+#define CYDEV_UCFG_B0_P0_U1_CFG21 0x400100d5\r
+#define CYDEV_UCFG_B0_P0_U1_CFG22 0x400100d6\r
+#define CYDEV_UCFG_B0_P0_U1_CFG23 0x400100d7\r
+#define CYDEV_UCFG_B0_P0_U1_CFG24 0x400100d8\r
+#define CYDEV_UCFG_B0_P0_U1_CFG25 0x400100d9\r
+#define CYDEV_UCFG_B0_P0_U1_CFG26 0x400100da\r
+#define CYDEV_UCFG_B0_P0_U1_CFG27 0x400100db\r
+#define CYDEV_UCFG_B0_P0_U1_CFG28 0x400100dc\r
+#define CYDEV_UCFG_B0_P0_U1_CFG29 0x400100dd\r
+#define CYDEV_UCFG_B0_P0_U1_CFG30 0x400100de\r
+#define CYDEV_UCFG_B0_P0_U1_CFG31 0x400100df\r
+#define CYDEV_UCFG_B0_P0_U1_DCFG0 0x400100e0\r
+#define CYDEV_UCFG_B0_P0_U1_DCFG1 0x400100e2\r
+#define CYDEV_UCFG_B0_P0_U1_DCFG2 0x400100e4\r
+#define CYDEV_UCFG_B0_P0_U1_DCFG3 0x400100e6\r
+#define CYDEV_UCFG_B0_P0_U1_DCFG4 0x400100e8\r
+#define CYDEV_UCFG_B0_P0_U1_DCFG5 0x400100ea\r
+#define CYDEV_UCFG_B0_P0_U1_DCFG6 0x400100ec\r
+#define CYDEV_UCFG_B0_P0_U1_DCFG7 0x400100ee\r
+#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100\r
+#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B0_P1_BASE 0x40010200\r
+#define CYDEV_UCFG_B0_P1_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200\r
+#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT0 0x40010200\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT1 0x40010204\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT2 0x40010208\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT3 0x4001020c\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT4 0x40010210\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT5 0x40010214\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT6 0x40010218\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT7 0x4001021c\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT8 0x40010220\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT9 0x40010224\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT10 0x40010228\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT11 0x4001022c\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_ORT0 0x40010230\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_ORT1 0x40010232\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_ORT2 0x40010234\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_ORT3 0x40010236\r
+#define CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238\r
+#define CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB 0x4001023a\r
+#define CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023c\r
+#define CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS 0x4001023e\r
+#define CYDEV_UCFG_B0_P1_U0_CFG0 0x40010240\r
+#define CYDEV_UCFG_B0_P1_U0_CFG1 0x40010241\r
+#define CYDEV_UCFG_B0_P1_U0_CFG2 0x40010242\r
+#define CYDEV_UCFG_B0_P1_U0_CFG3 0x40010243\r
+#define CYDEV_UCFG_B0_P1_U0_CFG4 0x40010244\r
+#define CYDEV_UCFG_B0_P1_U0_CFG5 0x40010245\r
+#define CYDEV_UCFG_B0_P1_U0_CFG6 0x40010246\r
+#define CYDEV_UCFG_B0_P1_U0_CFG7 0x40010247\r
+#define CYDEV_UCFG_B0_P1_U0_CFG8 0x40010248\r
+#define CYDEV_UCFG_B0_P1_U0_CFG9 0x40010249\r
+#define CYDEV_UCFG_B0_P1_U0_CFG10 0x4001024a\r
+#define CYDEV_UCFG_B0_P1_U0_CFG11 0x4001024b\r
+#define CYDEV_UCFG_B0_P1_U0_CFG12 0x4001024c\r
+#define CYDEV_UCFG_B0_P1_U0_CFG13 0x4001024d\r
+#define CYDEV_UCFG_B0_P1_U0_CFG14 0x4001024e\r
+#define CYDEV_UCFG_B0_P1_U0_CFG15 0x4001024f\r
+#define CYDEV_UCFG_B0_P1_U0_CFG16 0x40010250\r
+#define CYDEV_UCFG_B0_P1_U0_CFG17 0x40010251\r
+#define CYDEV_UCFG_B0_P1_U0_CFG18 0x40010252\r
+#define CYDEV_UCFG_B0_P1_U0_CFG19 0x40010253\r
+#define CYDEV_UCFG_B0_P1_U0_CFG20 0x40010254\r
+#define CYDEV_UCFG_B0_P1_U0_CFG21 0x40010255\r
+#define CYDEV_UCFG_B0_P1_U0_CFG22 0x40010256\r
+#define CYDEV_UCFG_B0_P1_U0_CFG23 0x40010257\r
+#define CYDEV_UCFG_B0_P1_U0_CFG24 0x40010258\r
+#define CYDEV_UCFG_B0_P1_U0_CFG25 0x40010259\r
+#define CYDEV_UCFG_B0_P1_U0_CFG26 0x4001025a\r
+#define CYDEV_UCFG_B0_P1_U0_CFG27 0x4001025b\r
+#define CYDEV_UCFG_B0_P1_U0_CFG28 0x4001025c\r
+#define CYDEV_UCFG_B0_P1_U0_CFG29 0x4001025d\r
+#define CYDEV_UCFG_B0_P1_U0_CFG30 0x4001025e\r
+#define CYDEV_UCFG_B0_P1_U0_CFG31 0x4001025f\r
+#define CYDEV_UCFG_B0_P1_U0_DCFG0 0x40010260\r
+#define CYDEV_UCFG_B0_P1_U0_DCFG1 0x40010262\r
+#define CYDEV_UCFG_B0_P1_U0_DCFG2 0x40010264\r
+#define CYDEV_UCFG_B0_P1_U0_DCFG3 0x40010266\r
+#define CYDEV_UCFG_B0_P1_U0_DCFG4 0x40010268\r
+#define CYDEV_UCFG_B0_P1_U0_DCFG5 0x4001026a\r
+#define CYDEV_UCFG_B0_P1_U0_DCFG6 0x4001026c\r
+#define CYDEV_UCFG_B0_P1_U0_DCFG7 0x4001026e\r
+#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280\r
+#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT0 0x40010280\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT1 0x40010284\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT2 0x40010288\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT3 0x4001028c\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT4 0x40010290\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT5 0x40010294\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT6 0x40010298\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT7 0x4001029c\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT8 0x400102a0\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT9 0x400102a4\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT10 0x400102a8\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT11 0x400102ac\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_ORT0 0x400102b0\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_ORT1 0x400102b2\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_ORT2 0x400102b4\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_ORT3 0x400102b6\r
+#define CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8\r
+#define CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB 0x400102ba\r
+#define CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bc\r
+#define CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS 0x400102be\r
+#define CYDEV_UCFG_B0_P1_U1_CFG0 0x400102c0\r
+#define CYDEV_UCFG_B0_P1_U1_CFG1 0x400102c1\r
+#define CYDEV_UCFG_B0_P1_U1_CFG2 0x400102c2\r
+#define CYDEV_UCFG_B0_P1_U1_CFG3 0x400102c3\r
+#define CYDEV_UCFG_B0_P1_U1_CFG4 0x400102c4\r
+#define CYDEV_UCFG_B0_P1_U1_CFG5 0x400102c5\r
+#define CYDEV_UCFG_B0_P1_U1_CFG6 0x400102c6\r
+#define CYDEV_UCFG_B0_P1_U1_CFG7 0x400102c7\r
+#define CYDEV_UCFG_B0_P1_U1_CFG8 0x400102c8\r
+#define CYDEV_UCFG_B0_P1_U1_CFG9 0x400102c9\r
+#define CYDEV_UCFG_B0_P1_U1_CFG10 0x400102ca\r
+#define CYDEV_UCFG_B0_P1_U1_CFG11 0x400102cb\r
+#define CYDEV_UCFG_B0_P1_U1_CFG12 0x400102cc\r
+#define CYDEV_UCFG_B0_P1_U1_CFG13 0x400102cd\r
+#define CYDEV_UCFG_B0_P1_U1_CFG14 0x400102ce\r
+#define CYDEV_UCFG_B0_P1_U1_CFG15 0x400102cf\r
+#define CYDEV_UCFG_B0_P1_U1_CFG16 0x400102d0\r
+#define CYDEV_UCFG_B0_P1_U1_CFG17 0x400102d1\r
+#define CYDEV_UCFG_B0_P1_U1_CFG18 0x400102d2\r
+#define CYDEV_UCFG_B0_P1_U1_CFG19 0x400102d3\r
+#define CYDEV_UCFG_B0_P1_U1_CFG20 0x400102d4\r
+#define CYDEV_UCFG_B0_P1_U1_CFG21 0x400102d5\r
+#define CYDEV_UCFG_B0_P1_U1_CFG22 0x400102d6\r
+#define CYDEV_UCFG_B0_P1_U1_CFG23 0x400102d7\r
+#define CYDEV_UCFG_B0_P1_U1_CFG24 0x400102d8\r
+#define CYDEV_UCFG_B0_P1_U1_CFG25 0x400102d9\r
+#define CYDEV_UCFG_B0_P1_U1_CFG26 0x400102da\r
+#define CYDEV_UCFG_B0_P1_U1_CFG27 0x400102db\r
+#define CYDEV_UCFG_B0_P1_U1_CFG28 0x400102dc\r
+#define CYDEV_UCFG_B0_P1_U1_CFG29 0x400102dd\r
+#define CYDEV_UCFG_B0_P1_U1_CFG30 0x400102de\r
+#define CYDEV_UCFG_B0_P1_U1_CFG31 0x400102df\r
+#define CYDEV_UCFG_B0_P1_U1_DCFG0 0x400102e0\r
+#define CYDEV_UCFG_B0_P1_U1_DCFG1 0x400102e2\r
+#define CYDEV_UCFG_B0_P1_U1_DCFG2 0x400102e4\r
+#define CYDEV_UCFG_B0_P1_U1_DCFG3 0x400102e6\r
+#define CYDEV_UCFG_B0_P1_U1_DCFG4 0x400102e8\r
+#define CYDEV_UCFG_B0_P1_U1_DCFG5 0x400102ea\r
+#define CYDEV_UCFG_B0_P1_U1_DCFG6 0x400102ec\r
+#define CYDEV_UCFG_B0_P1_U1_DCFG7 0x400102ee\r
+#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300\r
+#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B0_P2_BASE 0x40010400\r
+#define CYDEV_UCFG_B0_P2_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400\r
+#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT0 0x40010400\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT1 0x40010404\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT2 0x40010408\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT3 0x4001040c\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT4 0x40010410\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT5 0x40010414\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT6 0x40010418\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT7 0x4001041c\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT8 0x40010420\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT9 0x40010424\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT10 0x40010428\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT11 0x4001042c\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_ORT0 0x40010430\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_ORT1 0x40010432\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_ORT2 0x40010434\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_ORT3 0x40010436\r
+#define CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438\r
+#define CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB 0x4001043a\r
+#define CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043c\r
+#define CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS 0x4001043e\r
+#define CYDEV_UCFG_B0_P2_U0_CFG0 0x40010440\r
+#define CYDEV_UCFG_B0_P2_U0_CFG1 0x40010441\r
+#define CYDEV_UCFG_B0_P2_U0_CFG2 0x40010442\r
+#define CYDEV_UCFG_B0_P2_U0_CFG3 0x40010443\r
+#define CYDEV_UCFG_B0_P2_U0_CFG4 0x40010444\r
+#define CYDEV_UCFG_B0_P2_U0_CFG5 0x40010445\r
+#define CYDEV_UCFG_B0_P2_U0_CFG6 0x40010446\r
+#define CYDEV_UCFG_B0_P2_U0_CFG7 0x40010447\r
+#define CYDEV_UCFG_B0_P2_U0_CFG8 0x40010448\r
+#define CYDEV_UCFG_B0_P2_U0_CFG9 0x40010449\r
+#define CYDEV_UCFG_B0_P2_U0_CFG10 0x4001044a\r
+#define CYDEV_UCFG_B0_P2_U0_CFG11 0x4001044b\r
+#define CYDEV_UCFG_B0_P2_U0_CFG12 0x4001044c\r
+#define CYDEV_UCFG_B0_P2_U0_CFG13 0x4001044d\r
+#define CYDEV_UCFG_B0_P2_U0_CFG14 0x4001044e\r
+#define CYDEV_UCFG_B0_P2_U0_CFG15 0x4001044f\r
+#define CYDEV_UCFG_B0_P2_U0_CFG16 0x40010450\r
+#define CYDEV_UCFG_B0_P2_U0_CFG17 0x40010451\r
+#define CYDEV_UCFG_B0_P2_U0_CFG18 0x40010452\r
+#define CYDEV_UCFG_B0_P2_U0_CFG19 0x40010453\r
+#define CYDEV_UCFG_B0_P2_U0_CFG20 0x40010454\r
+#define CYDEV_UCFG_B0_P2_U0_CFG21 0x40010455\r
+#define CYDEV_UCFG_B0_P2_U0_CFG22 0x40010456\r
+#define CYDEV_UCFG_B0_P2_U0_CFG23 0x40010457\r
+#define CYDEV_UCFG_B0_P2_U0_CFG24 0x40010458\r
+#define CYDEV_UCFG_B0_P2_U0_CFG25 0x40010459\r
+#define CYDEV_UCFG_B0_P2_U0_CFG26 0x4001045a\r
+#define CYDEV_UCFG_B0_P2_U0_CFG27 0x4001045b\r
+#define CYDEV_UCFG_B0_P2_U0_CFG28 0x4001045c\r
+#define CYDEV_UCFG_B0_P2_U0_CFG29 0x4001045d\r
+#define CYDEV_UCFG_B0_P2_U0_CFG30 0x4001045e\r
+#define CYDEV_UCFG_B0_P2_U0_CFG31 0x4001045f\r
+#define CYDEV_UCFG_B0_P2_U0_DCFG0 0x40010460\r
+#define CYDEV_UCFG_B0_P2_U0_DCFG1 0x40010462\r
+#define CYDEV_UCFG_B0_P2_U0_DCFG2 0x40010464\r
+#define CYDEV_UCFG_B0_P2_U0_DCFG3 0x40010466\r
+#define CYDEV_UCFG_B0_P2_U0_DCFG4 0x40010468\r
+#define CYDEV_UCFG_B0_P2_U0_DCFG5 0x4001046a\r
+#define CYDEV_UCFG_B0_P2_U0_DCFG6 0x4001046c\r
+#define CYDEV_UCFG_B0_P2_U0_DCFG7 0x4001046e\r
+#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480\r
+#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT0 0x40010480\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT1 0x40010484\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT2 0x40010488\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT3 0x4001048c\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT4 0x40010490\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT5 0x40010494\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT6 0x40010498\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT7 0x4001049c\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT8 0x400104a0\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT9 0x400104a4\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT10 0x400104a8\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT11 0x400104ac\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_ORT0 0x400104b0\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_ORT1 0x400104b2\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_ORT2 0x400104b4\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_ORT3 0x400104b6\r
+#define CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8\r
+#define CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB 0x400104ba\r
+#define CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bc\r
+#define CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS 0x400104be\r
+#define CYDEV_UCFG_B0_P2_U1_CFG0 0x400104c0\r
+#define CYDEV_UCFG_B0_P2_U1_CFG1 0x400104c1\r
+#define CYDEV_UCFG_B0_P2_U1_CFG2 0x400104c2\r
+#define CYDEV_UCFG_B0_P2_U1_CFG3 0x400104c3\r
+#define CYDEV_UCFG_B0_P2_U1_CFG4 0x400104c4\r
+#define CYDEV_UCFG_B0_P2_U1_CFG5 0x400104c5\r
+#define CYDEV_UCFG_B0_P2_U1_CFG6 0x400104c6\r
+#define CYDEV_UCFG_B0_P2_U1_CFG7 0x400104c7\r
+#define CYDEV_UCFG_B0_P2_U1_CFG8 0x400104c8\r
+#define CYDEV_UCFG_B0_P2_U1_CFG9 0x400104c9\r
+#define CYDEV_UCFG_B0_P2_U1_CFG10 0x400104ca\r
+#define CYDEV_UCFG_B0_P2_U1_CFG11 0x400104cb\r
+#define CYDEV_UCFG_B0_P2_U1_CFG12 0x400104cc\r
+#define CYDEV_UCFG_B0_P2_U1_CFG13 0x400104cd\r
+#define CYDEV_UCFG_B0_P2_U1_CFG14 0x400104ce\r
+#define CYDEV_UCFG_B0_P2_U1_CFG15 0x400104cf\r
+#define CYDEV_UCFG_B0_P2_U1_CFG16 0x400104d0\r
+#define CYDEV_UCFG_B0_P2_U1_CFG17 0x400104d1\r
+#define CYDEV_UCFG_B0_P2_U1_CFG18 0x400104d2\r
+#define CYDEV_UCFG_B0_P2_U1_CFG19 0x400104d3\r
+#define CYDEV_UCFG_B0_P2_U1_CFG20 0x400104d4\r
+#define CYDEV_UCFG_B0_P2_U1_CFG21 0x400104d5\r
+#define CYDEV_UCFG_B0_P2_U1_CFG22 0x400104d6\r
+#define CYDEV_UCFG_B0_P2_U1_CFG23 0x400104d7\r
+#define CYDEV_UCFG_B0_P2_U1_CFG24 0x400104d8\r
+#define CYDEV_UCFG_B0_P2_U1_CFG25 0x400104d9\r
+#define CYDEV_UCFG_B0_P2_U1_CFG26 0x400104da\r
+#define CYDEV_UCFG_B0_P2_U1_CFG27 0x400104db\r
+#define CYDEV_UCFG_B0_P2_U1_CFG28 0x400104dc\r
+#define CYDEV_UCFG_B0_P2_U1_CFG29 0x400104dd\r
+#define CYDEV_UCFG_B0_P2_U1_CFG30 0x400104de\r
+#define CYDEV_UCFG_B0_P2_U1_CFG31 0x400104df\r
+#define CYDEV_UCFG_B0_P2_U1_DCFG0 0x400104e0\r
+#define CYDEV_UCFG_B0_P2_U1_DCFG1 0x400104e2\r
+#define CYDEV_UCFG_B0_P2_U1_DCFG2 0x400104e4\r
+#define CYDEV_UCFG_B0_P2_U1_DCFG3 0x400104e6\r
+#define CYDEV_UCFG_B0_P2_U1_DCFG4 0x400104e8\r
+#define CYDEV_UCFG_B0_P2_U1_DCFG5 0x400104ea\r
+#define CYDEV_UCFG_B0_P2_U1_DCFG6 0x400104ec\r
+#define CYDEV_UCFG_B0_P2_U1_DCFG7 0x400104ee\r
+#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500\r
+#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B0_P3_BASE 0x40010600\r
+#define CYDEV_UCFG_B0_P3_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600\r
+#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT0 0x40010600\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT1 0x40010604\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT2 0x40010608\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT3 0x4001060c\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT4 0x40010610\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT5 0x40010614\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT6 0x40010618\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT7 0x4001061c\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT8 0x40010620\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT9 0x40010624\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT10 0x40010628\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT11 0x4001062c\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_ORT0 0x40010630\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_ORT1 0x40010632\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_ORT2 0x40010634\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_ORT3 0x40010636\r
+#define CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638\r
+#define CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB 0x4001063a\r
+#define CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063c\r
+#define CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS 0x4001063e\r
+#define CYDEV_UCFG_B0_P3_U0_CFG0 0x40010640\r
+#define CYDEV_UCFG_B0_P3_U0_CFG1 0x40010641\r
+#define CYDEV_UCFG_B0_P3_U0_CFG2 0x40010642\r
+#define CYDEV_UCFG_B0_P3_U0_CFG3 0x40010643\r
+#define CYDEV_UCFG_B0_P3_U0_CFG4 0x40010644\r
+#define CYDEV_UCFG_B0_P3_U0_CFG5 0x40010645\r
+#define CYDEV_UCFG_B0_P3_U0_CFG6 0x40010646\r
+#define CYDEV_UCFG_B0_P3_U0_CFG7 0x40010647\r
+#define CYDEV_UCFG_B0_P3_U0_CFG8 0x40010648\r
+#define CYDEV_UCFG_B0_P3_U0_CFG9 0x40010649\r
+#define CYDEV_UCFG_B0_P3_U0_CFG10 0x4001064a\r
+#define CYDEV_UCFG_B0_P3_U0_CFG11 0x4001064b\r
+#define CYDEV_UCFG_B0_P3_U0_CFG12 0x4001064c\r
+#define CYDEV_UCFG_B0_P3_U0_CFG13 0x4001064d\r
+#define CYDEV_UCFG_B0_P3_U0_CFG14 0x4001064e\r
+#define CYDEV_UCFG_B0_P3_U0_CFG15 0x4001064f\r
+#define CYDEV_UCFG_B0_P3_U0_CFG16 0x40010650\r
+#define CYDEV_UCFG_B0_P3_U0_CFG17 0x40010651\r
+#define CYDEV_UCFG_B0_P3_U0_CFG18 0x40010652\r
+#define CYDEV_UCFG_B0_P3_U0_CFG19 0x40010653\r
+#define CYDEV_UCFG_B0_P3_U0_CFG20 0x40010654\r
+#define CYDEV_UCFG_B0_P3_U0_CFG21 0x40010655\r
+#define CYDEV_UCFG_B0_P3_U0_CFG22 0x40010656\r
+#define CYDEV_UCFG_B0_P3_U0_CFG23 0x40010657\r
+#define CYDEV_UCFG_B0_P3_U0_CFG24 0x40010658\r
+#define CYDEV_UCFG_B0_P3_U0_CFG25 0x40010659\r
+#define CYDEV_UCFG_B0_P3_U0_CFG26 0x4001065a\r
+#define CYDEV_UCFG_B0_P3_U0_CFG27 0x4001065b\r
+#define CYDEV_UCFG_B0_P3_U0_CFG28 0x4001065c\r
+#define CYDEV_UCFG_B0_P3_U0_CFG29 0x4001065d\r
+#define CYDEV_UCFG_B0_P3_U0_CFG30 0x4001065e\r
+#define CYDEV_UCFG_B0_P3_U0_CFG31 0x4001065f\r
+#define CYDEV_UCFG_B0_P3_U0_DCFG0 0x40010660\r
+#define CYDEV_UCFG_B0_P3_U0_DCFG1 0x40010662\r
+#define CYDEV_UCFG_B0_P3_U0_DCFG2 0x40010664\r
+#define CYDEV_UCFG_B0_P3_U0_DCFG3 0x40010666\r
+#define CYDEV_UCFG_B0_P3_U0_DCFG4 0x40010668\r
+#define CYDEV_UCFG_B0_P3_U0_DCFG5 0x4001066a\r
+#define CYDEV_UCFG_B0_P3_U0_DCFG6 0x4001066c\r
+#define CYDEV_UCFG_B0_P3_U0_DCFG7 0x4001066e\r
+#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680\r
+#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT0 0x40010680\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT1 0x40010684\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT2 0x40010688\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT3 0x4001068c\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT4 0x40010690\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT5 0x40010694\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT6 0x40010698\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT7 0x4001069c\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT8 0x400106a0\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT9 0x400106a4\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT10 0x400106a8\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT11 0x400106ac\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_ORT0 0x400106b0\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_ORT1 0x400106b2\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_ORT2 0x400106b4\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_ORT3 0x400106b6\r
+#define CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8\r
+#define CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB 0x400106ba\r
+#define CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bc\r
+#define CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS 0x400106be\r
+#define CYDEV_UCFG_B0_P3_U1_CFG0 0x400106c0\r
+#define CYDEV_UCFG_B0_P3_U1_CFG1 0x400106c1\r
+#define CYDEV_UCFG_B0_P3_U1_CFG2 0x400106c2\r
+#define CYDEV_UCFG_B0_P3_U1_CFG3 0x400106c3\r
+#define CYDEV_UCFG_B0_P3_U1_CFG4 0x400106c4\r
+#define CYDEV_UCFG_B0_P3_U1_CFG5 0x400106c5\r
+#define CYDEV_UCFG_B0_P3_U1_CFG6 0x400106c6\r
+#define CYDEV_UCFG_B0_P3_U1_CFG7 0x400106c7\r
+#define CYDEV_UCFG_B0_P3_U1_CFG8 0x400106c8\r
+#define CYDEV_UCFG_B0_P3_U1_CFG9 0x400106c9\r
+#define CYDEV_UCFG_B0_P3_U1_CFG10 0x400106ca\r
+#define CYDEV_UCFG_B0_P3_U1_CFG11 0x400106cb\r
+#define CYDEV_UCFG_B0_P3_U1_CFG12 0x400106cc\r
+#define CYDEV_UCFG_B0_P3_U1_CFG13 0x400106cd\r
+#define CYDEV_UCFG_B0_P3_U1_CFG14 0x400106ce\r
+#define CYDEV_UCFG_B0_P3_U1_CFG15 0x400106cf\r
+#define CYDEV_UCFG_B0_P3_U1_CFG16 0x400106d0\r
+#define CYDEV_UCFG_B0_P3_U1_CFG17 0x400106d1\r
+#define CYDEV_UCFG_B0_P3_U1_CFG18 0x400106d2\r
+#define CYDEV_UCFG_B0_P3_U1_CFG19 0x400106d3\r
+#define CYDEV_UCFG_B0_P3_U1_CFG20 0x400106d4\r
+#define CYDEV_UCFG_B0_P3_U1_CFG21 0x400106d5\r
+#define CYDEV_UCFG_B0_P3_U1_CFG22 0x400106d6\r
+#define CYDEV_UCFG_B0_P3_U1_CFG23 0x400106d7\r
+#define CYDEV_UCFG_B0_P3_U1_CFG24 0x400106d8\r
+#define CYDEV_UCFG_B0_P3_U1_CFG25 0x400106d9\r
+#define CYDEV_UCFG_B0_P3_U1_CFG26 0x400106da\r
+#define CYDEV_UCFG_B0_P3_U1_CFG27 0x400106db\r
+#define CYDEV_UCFG_B0_P3_U1_CFG28 0x400106dc\r
+#define CYDEV_UCFG_B0_P3_U1_CFG29 0x400106dd\r
+#define CYDEV_UCFG_B0_P3_U1_CFG30 0x400106de\r
+#define CYDEV_UCFG_B0_P3_U1_CFG31 0x400106df\r
+#define CYDEV_UCFG_B0_P3_U1_DCFG0 0x400106e0\r
+#define CYDEV_UCFG_B0_P3_U1_DCFG1 0x400106e2\r
+#define CYDEV_UCFG_B0_P3_U1_DCFG2 0x400106e4\r
+#define CYDEV_UCFG_B0_P3_U1_DCFG3 0x400106e6\r
+#define CYDEV_UCFG_B0_P3_U1_DCFG4 0x400106e8\r
+#define CYDEV_UCFG_B0_P3_U1_DCFG5 0x400106ea\r
+#define CYDEV_UCFG_B0_P3_U1_DCFG6 0x400106ec\r
+#define CYDEV_UCFG_B0_P3_U1_DCFG7 0x400106ee\r
+#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700\r
+#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B0_P4_BASE 0x40010800\r
+#define CYDEV_UCFG_B0_P4_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800\r
+#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT0 0x40010800\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT1 0x40010804\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT2 0x40010808\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT3 0x4001080c\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT4 0x40010810\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT5 0x40010814\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT6 0x40010818\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT7 0x4001081c\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT8 0x40010820\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT9 0x40010824\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT10 0x40010828\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT11 0x4001082c\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_ORT0 0x40010830\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_ORT1 0x40010832\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_ORT2 0x40010834\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_ORT3 0x40010836\r
+#define CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838\r
+#define CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB 0x4001083a\r
+#define CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083c\r
+#define CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS 0x4001083e\r
+#define CYDEV_UCFG_B0_P4_U0_CFG0 0x40010840\r
+#define CYDEV_UCFG_B0_P4_U0_CFG1 0x40010841\r
+#define CYDEV_UCFG_B0_P4_U0_CFG2 0x40010842\r
+#define CYDEV_UCFG_B0_P4_U0_CFG3 0x40010843\r
+#define CYDEV_UCFG_B0_P4_U0_CFG4 0x40010844\r
+#define CYDEV_UCFG_B0_P4_U0_CFG5 0x40010845\r
+#define CYDEV_UCFG_B0_P4_U0_CFG6 0x40010846\r
+#define CYDEV_UCFG_B0_P4_U0_CFG7 0x40010847\r
+#define CYDEV_UCFG_B0_P4_U0_CFG8 0x40010848\r
+#define CYDEV_UCFG_B0_P4_U0_CFG9 0x40010849\r
+#define CYDEV_UCFG_B0_P4_U0_CFG10 0x4001084a\r
+#define CYDEV_UCFG_B0_P4_U0_CFG11 0x4001084b\r
+#define CYDEV_UCFG_B0_P4_U0_CFG12 0x4001084c\r
+#define CYDEV_UCFG_B0_P4_U0_CFG13 0x4001084d\r
+#define CYDEV_UCFG_B0_P4_U0_CFG14 0x4001084e\r
+#define CYDEV_UCFG_B0_P4_U0_CFG15 0x4001084f\r
+#define CYDEV_UCFG_B0_P4_U0_CFG16 0x40010850\r
+#define CYDEV_UCFG_B0_P4_U0_CFG17 0x40010851\r
+#define CYDEV_UCFG_B0_P4_U0_CFG18 0x40010852\r
+#define CYDEV_UCFG_B0_P4_U0_CFG19 0x40010853\r
+#define CYDEV_UCFG_B0_P4_U0_CFG20 0x40010854\r
+#define CYDEV_UCFG_B0_P4_U0_CFG21 0x40010855\r
+#define CYDEV_UCFG_B0_P4_U0_CFG22 0x40010856\r
+#define CYDEV_UCFG_B0_P4_U0_CFG23 0x40010857\r
+#define CYDEV_UCFG_B0_P4_U0_CFG24 0x40010858\r
+#define CYDEV_UCFG_B0_P4_U0_CFG25 0x40010859\r
+#define CYDEV_UCFG_B0_P4_U0_CFG26 0x4001085a\r
+#define CYDEV_UCFG_B0_P4_U0_CFG27 0x4001085b\r
+#define CYDEV_UCFG_B0_P4_U0_CFG28 0x4001085c\r
+#define CYDEV_UCFG_B0_P4_U0_CFG29 0x4001085d\r
+#define CYDEV_UCFG_B0_P4_U0_CFG30 0x4001085e\r
+#define CYDEV_UCFG_B0_P4_U0_CFG31 0x4001085f\r
+#define CYDEV_UCFG_B0_P4_U0_DCFG0 0x40010860\r
+#define CYDEV_UCFG_B0_P4_U0_DCFG1 0x40010862\r
+#define CYDEV_UCFG_B0_P4_U0_DCFG2 0x40010864\r
+#define CYDEV_UCFG_B0_P4_U0_DCFG3 0x40010866\r
+#define CYDEV_UCFG_B0_P4_U0_DCFG4 0x40010868\r
+#define CYDEV_UCFG_B0_P4_U0_DCFG5 0x4001086a\r
+#define CYDEV_UCFG_B0_P4_U0_DCFG6 0x4001086c\r
+#define CYDEV_UCFG_B0_P4_U0_DCFG7 0x4001086e\r
+#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880\r
+#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT0 0x40010880\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT1 0x40010884\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT2 0x40010888\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT3 0x4001088c\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT4 0x40010890\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT5 0x40010894\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT6 0x40010898\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT7 0x4001089c\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT8 0x400108a0\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT9 0x400108a4\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT10 0x400108a8\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT11 0x400108ac\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_ORT0 0x400108b0\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_ORT1 0x400108b2\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_ORT2 0x400108b4\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_ORT3 0x400108b6\r
+#define CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8\r
+#define CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB 0x400108ba\r
+#define CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bc\r
+#define CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS 0x400108be\r
+#define CYDEV_UCFG_B0_P4_U1_CFG0 0x400108c0\r
+#define CYDEV_UCFG_B0_P4_U1_CFG1 0x400108c1\r
+#define CYDEV_UCFG_B0_P4_U1_CFG2 0x400108c2\r
+#define CYDEV_UCFG_B0_P4_U1_CFG3 0x400108c3\r
+#define CYDEV_UCFG_B0_P4_U1_CFG4 0x400108c4\r
+#define CYDEV_UCFG_B0_P4_U1_CFG5 0x400108c5\r
+#define CYDEV_UCFG_B0_P4_U1_CFG6 0x400108c6\r
+#define CYDEV_UCFG_B0_P4_U1_CFG7 0x400108c7\r
+#define CYDEV_UCFG_B0_P4_U1_CFG8 0x400108c8\r
+#define CYDEV_UCFG_B0_P4_U1_CFG9 0x400108c9\r
+#define CYDEV_UCFG_B0_P4_U1_CFG10 0x400108ca\r
+#define CYDEV_UCFG_B0_P4_U1_CFG11 0x400108cb\r
+#define CYDEV_UCFG_B0_P4_U1_CFG12 0x400108cc\r
+#define CYDEV_UCFG_B0_P4_U1_CFG13 0x400108cd\r
+#define CYDEV_UCFG_B0_P4_U1_CFG14 0x400108ce\r
+#define CYDEV_UCFG_B0_P4_U1_CFG15 0x400108cf\r
+#define CYDEV_UCFG_B0_P4_U1_CFG16 0x400108d0\r
+#define CYDEV_UCFG_B0_P4_U1_CFG17 0x400108d1\r
+#define CYDEV_UCFG_B0_P4_U1_CFG18 0x400108d2\r
+#define CYDEV_UCFG_B0_P4_U1_CFG19 0x400108d3\r
+#define CYDEV_UCFG_B0_P4_U1_CFG20 0x400108d4\r
+#define CYDEV_UCFG_B0_P4_U1_CFG21 0x400108d5\r
+#define CYDEV_UCFG_B0_P4_U1_CFG22 0x400108d6\r
+#define CYDEV_UCFG_B0_P4_U1_CFG23 0x400108d7\r
+#define CYDEV_UCFG_B0_P4_U1_CFG24 0x400108d8\r
+#define CYDEV_UCFG_B0_P4_U1_CFG25 0x400108d9\r
+#define CYDEV_UCFG_B0_P4_U1_CFG26 0x400108da\r
+#define CYDEV_UCFG_B0_P4_U1_CFG27 0x400108db\r
+#define CYDEV_UCFG_B0_P4_U1_CFG28 0x400108dc\r
+#define CYDEV_UCFG_B0_P4_U1_CFG29 0x400108dd\r
+#define CYDEV_UCFG_B0_P4_U1_CFG30 0x400108de\r
+#define CYDEV_UCFG_B0_P4_U1_CFG31 0x400108df\r
+#define CYDEV_UCFG_B0_P4_U1_DCFG0 0x400108e0\r
+#define CYDEV_UCFG_B0_P4_U1_DCFG1 0x400108e2\r
+#define CYDEV_UCFG_B0_P4_U1_DCFG2 0x400108e4\r
+#define CYDEV_UCFG_B0_P4_U1_DCFG3 0x400108e6\r
+#define CYDEV_UCFG_B0_P4_U1_DCFG4 0x400108e8\r
+#define CYDEV_UCFG_B0_P4_U1_DCFG5 0x400108ea\r
+#define CYDEV_UCFG_B0_P4_U1_DCFG6 0x400108ec\r
+#define CYDEV_UCFG_B0_P4_U1_DCFG7 0x400108ee\r
+#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900\r
+#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B0_P5_BASE 0x40010a00\r
+#define CYDEV_UCFG_B0_P5_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00\r
+#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT0 0x40010a00\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT1 0x40010a04\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT2 0x40010a08\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT3 0x40010a0c\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT4 0x40010a10\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT5 0x40010a14\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT6 0x40010a18\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT7 0x40010a1c\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT8 0x40010a20\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT9 0x40010a24\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT10 0x40010a28\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT11 0x40010a2c\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_ORT0 0x40010a30\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_ORT1 0x40010a32\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_ORT2 0x40010a34\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_ORT3 0x40010a36\r
+#define CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38\r
+#define CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB 0x40010a3a\r
+#define CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3c\r
+#define CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3e\r
+#define CYDEV_UCFG_B0_P5_U0_CFG0 0x40010a40\r
+#define CYDEV_UCFG_B0_P5_U0_CFG1 0x40010a41\r
+#define CYDEV_UCFG_B0_P5_U0_CFG2 0x40010a42\r
+#define CYDEV_UCFG_B0_P5_U0_CFG3 0x40010a43\r
+#define CYDEV_UCFG_B0_P5_U0_CFG4 0x40010a44\r
+#define CYDEV_UCFG_B0_P5_U0_CFG5 0x40010a45\r
+#define CYDEV_UCFG_B0_P5_U0_CFG6 0x40010a46\r
+#define CYDEV_UCFG_B0_P5_U0_CFG7 0x40010a47\r
+#define CYDEV_UCFG_B0_P5_U0_CFG8 0x40010a48\r
+#define CYDEV_UCFG_B0_P5_U0_CFG9 0x40010a49\r
+#define CYDEV_UCFG_B0_P5_U0_CFG10 0x40010a4a\r
+#define CYDEV_UCFG_B0_P5_U0_CFG11 0x40010a4b\r
+#define CYDEV_UCFG_B0_P5_U0_CFG12 0x40010a4c\r
+#define CYDEV_UCFG_B0_P5_U0_CFG13 0x40010a4d\r
+#define CYDEV_UCFG_B0_P5_U0_CFG14 0x40010a4e\r
+#define CYDEV_UCFG_B0_P5_U0_CFG15 0x40010a4f\r
+#define CYDEV_UCFG_B0_P5_U0_CFG16 0x40010a50\r
+#define CYDEV_UCFG_B0_P5_U0_CFG17 0x40010a51\r
+#define CYDEV_UCFG_B0_P5_U0_CFG18 0x40010a52\r
+#define CYDEV_UCFG_B0_P5_U0_CFG19 0x40010a53\r
+#define CYDEV_UCFG_B0_P5_U0_CFG20 0x40010a54\r
+#define CYDEV_UCFG_B0_P5_U0_CFG21 0x40010a55\r
+#define CYDEV_UCFG_B0_P5_U0_CFG22 0x40010a56\r
+#define CYDEV_UCFG_B0_P5_U0_CFG23 0x40010a57\r
+#define CYDEV_UCFG_B0_P5_U0_CFG24 0x40010a58\r
+#define CYDEV_UCFG_B0_P5_U0_CFG25 0x40010a59\r
+#define CYDEV_UCFG_B0_P5_U0_CFG26 0x40010a5a\r
+#define CYDEV_UCFG_B0_P5_U0_CFG27 0x40010a5b\r
+#define CYDEV_UCFG_B0_P5_U0_CFG28 0x40010a5c\r
+#define CYDEV_UCFG_B0_P5_U0_CFG29 0x40010a5d\r
+#define CYDEV_UCFG_B0_P5_U0_CFG30 0x40010a5e\r
+#define CYDEV_UCFG_B0_P5_U0_CFG31 0x40010a5f\r
+#define CYDEV_UCFG_B0_P5_U0_DCFG0 0x40010a60\r
+#define CYDEV_UCFG_B0_P5_U0_DCFG1 0x40010a62\r
+#define CYDEV_UCFG_B0_P5_U0_DCFG2 0x40010a64\r
+#define CYDEV_UCFG_B0_P5_U0_DCFG3 0x40010a66\r
+#define CYDEV_UCFG_B0_P5_U0_DCFG4 0x40010a68\r
+#define CYDEV_UCFG_B0_P5_U0_DCFG5 0x40010a6a\r
+#define CYDEV_UCFG_B0_P5_U0_DCFG6 0x40010a6c\r
+#define CYDEV_UCFG_B0_P5_U0_DCFG7 0x40010a6e\r
+#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80\r
+#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT0 0x40010a80\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT1 0x40010a84\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT2 0x40010a88\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT3 0x40010a8c\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT4 0x40010a90\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT5 0x40010a94\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT6 0x40010a98\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT7 0x40010a9c\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT8 0x40010aa0\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT9 0x40010aa4\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT10 0x40010aa8\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT11 0x40010aac\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_ORT0 0x40010ab0\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_ORT1 0x40010ab2\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_ORT2 0x40010ab4\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_ORT3 0x40010ab6\r
+#define CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8\r
+#define CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB 0x40010aba\r
+#define CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abc\r
+#define CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS 0x40010abe\r
+#define CYDEV_UCFG_B0_P5_U1_CFG0 0x40010ac0\r
+#define CYDEV_UCFG_B0_P5_U1_CFG1 0x40010ac1\r
+#define CYDEV_UCFG_B0_P5_U1_CFG2 0x40010ac2\r
+#define CYDEV_UCFG_B0_P5_U1_CFG3 0x40010ac3\r
+#define CYDEV_UCFG_B0_P5_U1_CFG4 0x40010ac4\r
+#define CYDEV_UCFG_B0_P5_U1_CFG5 0x40010ac5\r
+#define CYDEV_UCFG_B0_P5_U1_CFG6 0x40010ac6\r
+#define CYDEV_UCFG_B0_P5_U1_CFG7 0x40010ac7\r
+#define CYDEV_UCFG_B0_P5_U1_CFG8 0x40010ac8\r
+#define CYDEV_UCFG_B0_P5_U1_CFG9 0x40010ac9\r
+#define CYDEV_UCFG_B0_P5_U1_CFG10 0x40010aca\r
+#define CYDEV_UCFG_B0_P5_U1_CFG11 0x40010acb\r
+#define CYDEV_UCFG_B0_P5_U1_CFG12 0x40010acc\r
+#define CYDEV_UCFG_B0_P5_U1_CFG13 0x40010acd\r
+#define CYDEV_UCFG_B0_P5_U1_CFG14 0x40010ace\r
+#define CYDEV_UCFG_B0_P5_U1_CFG15 0x40010acf\r
+#define CYDEV_UCFG_B0_P5_U1_CFG16 0x40010ad0\r
+#define CYDEV_UCFG_B0_P5_U1_CFG17 0x40010ad1\r
+#define CYDEV_UCFG_B0_P5_U1_CFG18 0x40010ad2\r
+#define CYDEV_UCFG_B0_P5_U1_CFG19 0x40010ad3\r
+#define CYDEV_UCFG_B0_P5_U1_CFG20 0x40010ad4\r
+#define CYDEV_UCFG_B0_P5_U1_CFG21 0x40010ad5\r
+#define CYDEV_UCFG_B0_P5_U1_CFG22 0x40010ad6\r
+#define CYDEV_UCFG_B0_P5_U1_CFG23 0x40010ad7\r
+#define CYDEV_UCFG_B0_P5_U1_CFG24 0x40010ad8\r
+#define CYDEV_UCFG_B0_P5_U1_CFG25 0x40010ad9\r
+#define CYDEV_UCFG_B0_P5_U1_CFG26 0x40010ada\r
+#define CYDEV_UCFG_B0_P5_U1_CFG27 0x40010adb\r
+#define CYDEV_UCFG_B0_P5_U1_CFG28 0x40010adc\r
+#define CYDEV_UCFG_B0_P5_U1_CFG29 0x40010add\r
+#define CYDEV_UCFG_B0_P5_U1_CFG30 0x40010ade\r
+#define CYDEV_UCFG_B0_P5_U1_CFG31 0x40010adf\r
+#define CYDEV_UCFG_B0_P5_U1_DCFG0 0x40010ae0\r
+#define CYDEV_UCFG_B0_P5_U1_DCFG1 0x40010ae2\r
+#define CYDEV_UCFG_B0_P5_U1_DCFG2 0x40010ae4\r
+#define CYDEV_UCFG_B0_P5_U1_DCFG3 0x40010ae6\r
+#define CYDEV_UCFG_B0_P5_U1_DCFG4 0x40010ae8\r
+#define CYDEV_UCFG_B0_P5_U1_DCFG5 0x40010aea\r
+#define CYDEV_UCFG_B0_P5_U1_DCFG6 0x40010aec\r
+#define CYDEV_UCFG_B0_P5_U1_DCFG7 0x40010aee\r
+#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00\r
+#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B0_P6_BASE 0x40010c00\r
+#define CYDEV_UCFG_B0_P6_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00\r
+#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT0 0x40010c00\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT1 0x40010c04\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT2 0x40010c08\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT3 0x40010c0c\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT4 0x40010c10\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT5 0x40010c14\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT6 0x40010c18\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT7 0x40010c1c\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT8 0x40010c20\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT9 0x40010c24\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT10 0x40010c28\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT11 0x40010c2c\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_ORT0 0x40010c30\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_ORT1 0x40010c32\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_ORT2 0x40010c34\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_ORT3 0x40010c36\r
+#define CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38\r
+#define CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB 0x40010c3a\r
+#define CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3c\r
+#define CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3e\r
+#define CYDEV_UCFG_B0_P6_U0_CFG0 0x40010c40\r
+#define CYDEV_UCFG_B0_P6_U0_CFG1 0x40010c41\r
+#define CYDEV_UCFG_B0_P6_U0_CFG2 0x40010c42\r
+#define CYDEV_UCFG_B0_P6_U0_CFG3 0x40010c43\r
+#define CYDEV_UCFG_B0_P6_U0_CFG4 0x40010c44\r
+#define CYDEV_UCFG_B0_P6_U0_CFG5 0x40010c45\r
+#define CYDEV_UCFG_B0_P6_U0_CFG6 0x40010c46\r
+#define CYDEV_UCFG_B0_P6_U0_CFG7 0x40010c47\r
+#define CYDEV_UCFG_B0_P6_U0_CFG8 0x40010c48\r
+#define CYDEV_UCFG_B0_P6_U0_CFG9 0x40010c49\r
+#define CYDEV_UCFG_B0_P6_U0_CFG10 0x40010c4a\r
+#define CYDEV_UCFG_B0_P6_U0_CFG11 0x40010c4b\r
+#define CYDEV_UCFG_B0_P6_U0_CFG12 0x40010c4c\r
+#define CYDEV_UCFG_B0_P6_U0_CFG13 0x40010c4d\r
+#define CYDEV_UCFG_B0_P6_U0_CFG14 0x40010c4e\r
+#define CYDEV_UCFG_B0_P6_U0_CFG15 0x40010c4f\r
+#define CYDEV_UCFG_B0_P6_U0_CFG16 0x40010c50\r
+#define CYDEV_UCFG_B0_P6_U0_CFG17 0x40010c51\r
+#define CYDEV_UCFG_B0_P6_U0_CFG18 0x40010c52\r
+#define CYDEV_UCFG_B0_P6_U0_CFG19 0x40010c53\r
+#define CYDEV_UCFG_B0_P6_U0_CFG20 0x40010c54\r
+#define CYDEV_UCFG_B0_P6_U0_CFG21 0x40010c55\r
+#define CYDEV_UCFG_B0_P6_U0_CFG22 0x40010c56\r
+#define CYDEV_UCFG_B0_P6_U0_CFG23 0x40010c57\r
+#define CYDEV_UCFG_B0_P6_U0_CFG24 0x40010c58\r
+#define CYDEV_UCFG_B0_P6_U0_CFG25 0x40010c59\r
+#define CYDEV_UCFG_B0_P6_U0_CFG26 0x40010c5a\r
+#define CYDEV_UCFG_B0_P6_U0_CFG27 0x40010c5b\r
+#define CYDEV_UCFG_B0_P6_U0_CFG28 0x40010c5c\r
+#define CYDEV_UCFG_B0_P6_U0_CFG29 0x40010c5d\r
+#define CYDEV_UCFG_B0_P6_U0_CFG30 0x40010c5e\r
+#define CYDEV_UCFG_B0_P6_U0_CFG31 0x40010c5f\r
+#define CYDEV_UCFG_B0_P6_U0_DCFG0 0x40010c60\r
+#define CYDEV_UCFG_B0_P6_U0_DCFG1 0x40010c62\r
+#define CYDEV_UCFG_B0_P6_U0_DCFG2 0x40010c64\r
+#define CYDEV_UCFG_B0_P6_U0_DCFG3 0x40010c66\r
+#define CYDEV_UCFG_B0_P6_U0_DCFG4 0x40010c68\r
+#define CYDEV_UCFG_B0_P6_U0_DCFG5 0x40010c6a\r
+#define CYDEV_UCFG_B0_P6_U0_DCFG6 0x40010c6c\r
+#define CYDEV_UCFG_B0_P6_U0_DCFG7 0x40010c6e\r
+#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80\r
+#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT0 0x40010c80\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT1 0x40010c84\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT2 0x40010c88\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT3 0x40010c8c\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT4 0x40010c90\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT5 0x40010c94\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT6 0x40010c98\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT7 0x40010c9c\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT8 0x40010ca0\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT9 0x40010ca4\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT10 0x40010ca8\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT11 0x40010cac\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_ORT0 0x40010cb0\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_ORT1 0x40010cb2\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_ORT2 0x40010cb4\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_ORT3 0x40010cb6\r
+#define CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8\r
+#define CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB 0x40010cba\r
+#define CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbc\r
+#define CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbe\r
+#define CYDEV_UCFG_B0_P6_U1_CFG0 0x40010cc0\r
+#define CYDEV_UCFG_B0_P6_U1_CFG1 0x40010cc1\r
+#define CYDEV_UCFG_B0_P6_U1_CFG2 0x40010cc2\r
+#define CYDEV_UCFG_B0_P6_U1_CFG3 0x40010cc3\r
+#define CYDEV_UCFG_B0_P6_U1_CFG4 0x40010cc4\r
+#define CYDEV_UCFG_B0_P6_U1_CFG5 0x40010cc5\r
+#define CYDEV_UCFG_B0_P6_U1_CFG6 0x40010cc6\r
+#define CYDEV_UCFG_B0_P6_U1_CFG7 0x40010cc7\r
+#define CYDEV_UCFG_B0_P6_U1_CFG8 0x40010cc8\r
+#define CYDEV_UCFG_B0_P6_U1_CFG9 0x40010cc9\r
+#define CYDEV_UCFG_B0_P6_U1_CFG10 0x40010cca\r
+#define CYDEV_UCFG_B0_P6_U1_CFG11 0x40010ccb\r
+#define CYDEV_UCFG_B0_P6_U1_CFG12 0x40010ccc\r
+#define CYDEV_UCFG_B0_P6_U1_CFG13 0x40010ccd\r
+#define CYDEV_UCFG_B0_P6_U1_CFG14 0x40010cce\r
+#define CYDEV_UCFG_B0_P6_U1_CFG15 0x40010ccf\r
+#define CYDEV_UCFG_B0_P6_U1_CFG16 0x40010cd0\r
+#define CYDEV_UCFG_B0_P6_U1_CFG17 0x40010cd1\r
+#define CYDEV_UCFG_B0_P6_U1_CFG18 0x40010cd2\r
+#define CYDEV_UCFG_B0_P6_U1_CFG19 0x40010cd3\r
+#define CYDEV_UCFG_B0_P6_U1_CFG20 0x40010cd4\r
+#define CYDEV_UCFG_B0_P6_U1_CFG21 0x40010cd5\r
+#define CYDEV_UCFG_B0_P6_U1_CFG22 0x40010cd6\r
+#define CYDEV_UCFG_B0_P6_U1_CFG23 0x40010cd7\r
+#define CYDEV_UCFG_B0_P6_U1_CFG24 0x40010cd8\r
+#define CYDEV_UCFG_B0_P6_U1_CFG25 0x40010cd9\r
+#define CYDEV_UCFG_B0_P6_U1_CFG26 0x40010cda\r
+#define CYDEV_UCFG_B0_P6_U1_CFG27 0x40010cdb\r
+#define CYDEV_UCFG_B0_P6_U1_CFG28 0x40010cdc\r
+#define CYDEV_UCFG_B0_P6_U1_CFG29 0x40010cdd\r
+#define CYDEV_UCFG_B0_P6_U1_CFG30 0x40010cde\r
+#define CYDEV_UCFG_B0_P6_U1_CFG31 0x40010cdf\r
+#define CYDEV_UCFG_B0_P6_U1_DCFG0 0x40010ce0\r
+#define CYDEV_UCFG_B0_P6_U1_DCFG1 0x40010ce2\r
+#define CYDEV_UCFG_B0_P6_U1_DCFG2 0x40010ce4\r
+#define CYDEV_UCFG_B0_P6_U1_DCFG3 0x40010ce6\r
+#define CYDEV_UCFG_B0_P6_U1_DCFG4 0x40010ce8\r
+#define CYDEV_UCFG_B0_P6_U1_DCFG5 0x40010cea\r
+#define CYDEV_UCFG_B0_P6_U1_DCFG6 0x40010cec\r
+#define CYDEV_UCFG_B0_P6_U1_DCFG7 0x40010cee\r
+#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00\r
+#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B0_P7_BASE 0x40010e00\r
+#define CYDEV_UCFG_B0_P7_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00\r
+#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT0 0x40010e00\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT1 0x40010e04\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT2 0x40010e08\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT3 0x40010e0c\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT4 0x40010e10\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT5 0x40010e14\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT6 0x40010e18\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT7 0x40010e1c\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT8 0x40010e20\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT9 0x40010e24\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT10 0x40010e28\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT11 0x40010e2c\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_ORT0 0x40010e30\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_ORT1 0x40010e32\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_ORT2 0x40010e34\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_ORT3 0x40010e36\r
+#define CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38\r
+#define CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB 0x40010e3a\r
+#define CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3c\r
+#define CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3e\r
+#define CYDEV_UCFG_B0_P7_U0_CFG0 0x40010e40\r
+#define CYDEV_UCFG_B0_P7_U0_CFG1 0x40010e41\r
+#define CYDEV_UCFG_B0_P7_U0_CFG2 0x40010e42\r
+#define CYDEV_UCFG_B0_P7_U0_CFG3 0x40010e43\r
+#define CYDEV_UCFG_B0_P7_U0_CFG4 0x40010e44\r
+#define CYDEV_UCFG_B0_P7_U0_CFG5 0x40010e45\r
+#define CYDEV_UCFG_B0_P7_U0_CFG6 0x40010e46\r
+#define CYDEV_UCFG_B0_P7_U0_CFG7 0x40010e47\r
+#define CYDEV_UCFG_B0_P7_U0_CFG8 0x40010e48\r
+#define CYDEV_UCFG_B0_P7_U0_CFG9 0x40010e49\r
+#define CYDEV_UCFG_B0_P7_U0_CFG10 0x40010e4a\r
+#define CYDEV_UCFG_B0_P7_U0_CFG11 0x40010e4b\r
+#define CYDEV_UCFG_B0_P7_U0_CFG12 0x40010e4c\r
+#define CYDEV_UCFG_B0_P7_U0_CFG13 0x40010e4d\r
+#define CYDEV_UCFG_B0_P7_U0_CFG14 0x40010e4e\r
+#define CYDEV_UCFG_B0_P7_U0_CFG15 0x40010e4f\r
+#define CYDEV_UCFG_B0_P7_U0_CFG16 0x40010e50\r
+#define CYDEV_UCFG_B0_P7_U0_CFG17 0x40010e51\r
+#define CYDEV_UCFG_B0_P7_U0_CFG18 0x40010e52\r
+#define CYDEV_UCFG_B0_P7_U0_CFG19 0x40010e53\r
+#define CYDEV_UCFG_B0_P7_U0_CFG20 0x40010e54\r
+#define CYDEV_UCFG_B0_P7_U0_CFG21 0x40010e55\r
+#define CYDEV_UCFG_B0_P7_U0_CFG22 0x40010e56\r
+#define CYDEV_UCFG_B0_P7_U0_CFG23 0x40010e57\r
+#define CYDEV_UCFG_B0_P7_U0_CFG24 0x40010e58\r
+#define CYDEV_UCFG_B0_P7_U0_CFG25 0x40010e59\r
+#define CYDEV_UCFG_B0_P7_U0_CFG26 0x40010e5a\r
+#define CYDEV_UCFG_B0_P7_U0_CFG27 0x40010e5b\r
+#define CYDEV_UCFG_B0_P7_U0_CFG28 0x40010e5c\r
+#define CYDEV_UCFG_B0_P7_U0_CFG29 0x40010e5d\r
+#define CYDEV_UCFG_B0_P7_U0_CFG30 0x40010e5e\r
+#define CYDEV_UCFG_B0_P7_U0_CFG31 0x40010e5f\r
+#define CYDEV_UCFG_B0_P7_U0_DCFG0 0x40010e60\r
+#define CYDEV_UCFG_B0_P7_U0_DCFG1 0x40010e62\r
+#define CYDEV_UCFG_B0_P7_U0_DCFG2 0x40010e64\r
+#define CYDEV_UCFG_B0_P7_U0_DCFG3 0x40010e66\r
+#define CYDEV_UCFG_B0_P7_U0_DCFG4 0x40010e68\r
+#define CYDEV_UCFG_B0_P7_U0_DCFG5 0x40010e6a\r
+#define CYDEV_UCFG_B0_P7_U0_DCFG6 0x40010e6c\r
+#define CYDEV_UCFG_B0_P7_U0_DCFG7 0x40010e6e\r
+#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80\r
+#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT0 0x40010e80\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT1 0x40010e84\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT2 0x40010e88\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT3 0x40010e8c\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT4 0x40010e90\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT5 0x40010e94\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT6 0x40010e98\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT7 0x40010e9c\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT8 0x40010ea0\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT9 0x40010ea4\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT10 0x40010ea8\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT11 0x40010eac\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_ORT0 0x40010eb0\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_ORT1 0x40010eb2\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_ORT2 0x40010eb4\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_ORT3 0x40010eb6\r
+#define CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8\r
+#define CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB 0x40010eba\r
+#define CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebc\r
+#define CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebe\r
+#define CYDEV_UCFG_B0_P7_U1_CFG0 0x40010ec0\r
+#define CYDEV_UCFG_B0_P7_U1_CFG1 0x40010ec1\r
+#define CYDEV_UCFG_B0_P7_U1_CFG2 0x40010ec2\r
+#define CYDEV_UCFG_B0_P7_U1_CFG3 0x40010ec3\r
+#define CYDEV_UCFG_B0_P7_U1_CFG4 0x40010ec4\r
+#define CYDEV_UCFG_B0_P7_U1_CFG5 0x40010ec5\r
+#define CYDEV_UCFG_B0_P7_U1_CFG6 0x40010ec6\r
+#define CYDEV_UCFG_B0_P7_U1_CFG7 0x40010ec7\r
+#define CYDEV_UCFG_B0_P7_U1_CFG8 0x40010ec8\r
+#define CYDEV_UCFG_B0_P7_U1_CFG9 0x40010ec9\r
+#define CYDEV_UCFG_B0_P7_U1_CFG10 0x40010eca\r
+#define CYDEV_UCFG_B0_P7_U1_CFG11 0x40010ecb\r
+#define CYDEV_UCFG_B0_P7_U1_CFG12 0x40010ecc\r
+#define CYDEV_UCFG_B0_P7_U1_CFG13 0x40010ecd\r
+#define CYDEV_UCFG_B0_P7_U1_CFG14 0x40010ece\r
+#define CYDEV_UCFG_B0_P7_U1_CFG15 0x40010ecf\r
+#define CYDEV_UCFG_B0_P7_U1_CFG16 0x40010ed0\r
+#define CYDEV_UCFG_B0_P7_U1_CFG17 0x40010ed1\r
+#define CYDEV_UCFG_B0_P7_U1_CFG18 0x40010ed2\r
+#define CYDEV_UCFG_B0_P7_U1_CFG19 0x40010ed3\r
+#define CYDEV_UCFG_B0_P7_U1_CFG20 0x40010ed4\r
+#define CYDEV_UCFG_B0_P7_U1_CFG21 0x40010ed5\r
+#define CYDEV_UCFG_B0_P7_U1_CFG22 0x40010ed6\r
+#define CYDEV_UCFG_B0_P7_U1_CFG23 0x40010ed7\r
+#define CYDEV_UCFG_B0_P7_U1_CFG24 0x40010ed8\r
+#define CYDEV_UCFG_B0_P7_U1_CFG25 0x40010ed9\r
+#define CYDEV_UCFG_B0_P7_U1_CFG26 0x40010eda\r
+#define CYDEV_UCFG_B0_P7_U1_CFG27 0x40010edb\r
+#define CYDEV_UCFG_B0_P7_U1_CFG28 0x40010edc\r
+#define CYDEV_UCFG_B0_P7_U1_CFG29 0x40010edd\r
+#define CYDEV_UCFG_B0_P7_U1_CFG30 0x40010ede\r
+#define CYDEV_UCFG_B0_P7_U1_CFG31 0x40010edf\r
+#define CYDEV_UCFG_B0_P7_U1_DCFG0 0x40010ee0\r
+#define CYDEV_UCFG_B0_P7_U1_DCFG1 0x40010ee2\r
+#define CYDEV_UCFG_B0_P7_U1_DCFG2 0x40010ee4\r
+#define CYDEV_UCFG_B0_P7_U1_DCFG3 0x40010ee6\r
+#define CYDEV_UCFG_B0_P7_U1_DCFG4 0x40010ee8\r
+#define CYDEV_UCFG_B0_P7_U1_DCFG5 0x40010eea\r
+#define CYDEV_UCFG_B0_P7_U1_DCFG6 0x40010eec\r
+#define CYDEV_UCFG_B0_P7_U1_DCFG7 0x40010eee\r
+#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00\r
+#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B1_BASE 0x40011000\r
+#define CYDEV_UCFG_B1_SIZE 0x00000fef\r
+#define CYDEV_UCFG_B1_P2_BASE 0x40011400\r
+#define CYDEV_UCFG_B1_P2_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400\r
+#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT0 0x40011400\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT1 0x40011404\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT2 0x40011408\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT3 0x4001140c\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT4 0x40011410\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT5 0x40011414\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT6 0x40011418\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT7 0x4001141c\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT8 0x40011420\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT9 0x40011424\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT10 0x40011428\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT11 0x4001142c\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_ORT0 0x40011430\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_ORT1 0x40011432\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_ORT2 0x40011434\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_ORT3 0x40011436\r
+#define CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438\r
+#define CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB 0x4001143a\r
+#define CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143c\r
+#define CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS 0x4001143e\r
+#define CYDEV_UCFG_B1_P2_U0_CFG0 0x40011440\r
+#define CYDEV_UCFG_B1_P2_U0_CFG1 0x40011441\r
+#define CYDEV_UCFG_B1_P2_U0_CFG2 0x40011442\r
+#define CYDEV_UCFG_B1_P2_U0_CFG3 0x40011443\r
+#define CYDEV_UCFG_B1_P2_U0_CFG4 0x40011444\r
+#define CYDEV_UCFG_B1_P2_U0_CFG5 0x40011445\r
+#define CYDEV_UCFG_B1_P2_U0_CFG6 0x40011446\r
+#define CYDEV_UCFG_B1_P2_U0_CFG7 0x40011447\r
+#define CYDEV_UCFG_B1_P2_U0_CFG8 0x40011448\r
+#define CYDEV_UCFG_B1_P2_U0_CFG9 0x40011449\r
+#define CYDEV_UCFG_B1_P2_U0_CFG10 0x4001144a\r
+#define CYDEV_UCFG_B1_P2_U0_CFG11 0x4001144b\r
+#define CYDEV_UCFG_B1_P2_U0_CFG12 0x4001144c\r
+#define CYDEV_UCFG_B1_P2_U0_CFG13 0x4001144d\r
+#define CYDEV_UCFG_B1_P2_U0_CFG14 0x4001144e\r
+#define CYDEV_UCFG_B1_P2_U0_CFG15 0x4001144f\r
+#define CYDEV_UCFG_B1_P2_U0_CFG16 0x40011450\r
+#define CYDEV_UCFG_B1_P2_U0_CFG17 0x40011451\r
+#define CYDEV_UCFG_B1_P2_U0_CFG18 0x40011452\r
+#define CYDEV_UCFG_B1_P2_U0_CFG19 0x40011453\r
+#define CYDEV_UCFG_B1_P2_U0_CFG20 0x40011454\r
+#define CYDEV_UCFG_B1_P2_U0_CFG21 0x40011455\r
+#define CYDEV_UCFG_B1_P2_U0_CFG22 0x40011456\r
+#define CYDEV_UCFG_B1_P2_U0_CFG23 0x40011457\r
+#define CYDEV_UCFG_B1_P2_U0_CFG24 0x40011458\r
+#define CYDEV_UCFG_B1_P2_U0_CFG25 0x40011459\r
+#define CYDEV_UCFG_B1_P2_U0_CFG26 0x4001145a\r
+#define CYDEV_UCFG_B1_P2_U0_CFG27 0x4001145b\r
+#define CYDEV_UCFG_B1_P2_U0_CFG28 0x4001145c\r
+#define CYDEV_UCFG_B1_P2_U0_CFG29 0x4001145d\r
+#define CYDEV_UCFG_B1_P2_U0_CFG30 0x4001145e\r
+#define CYDEV_UCFG_B1_P2_U0_CFG31 0x4001145f\r
+#define CYDEV_UCFG_B1_P2_U0_DCFG0 0x40011460\r
+#define CYDEV_UCFG_B1_P2_U0_DCFG1 0x40011462\r
+#define CYDEV_UCFG_B1_P2_U0_DCFG2 0x40011464\r
+#define CYDEV_UCFG_B1_P2_U0_DCFG3 0x40011466\r
+#define CYDEV_UCFG_B1_P2_U0_DCFG4 0x40011468\r
+#define CYDEV_UCFG_B1_P2_U0_DCFG5 0x4001146a\r
+#define CYDEV_UCFG_B1_P2_U0_DCFG6 0x4001146c\r
+#define CYDEV_UCFG_B1_P2_U0_DCFG7 0x4001146e\r
+#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480\r
+#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT0 0x40011480\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT1 0x40011484\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT2 0x40011488\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT3 0x4001148c\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT4 0x40011490\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT5 0x40011494\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT6 0x40011498\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT7 0x4001149c\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT8 0x400114a0\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT9 0x400114a4\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT10 0x400114a8\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT11 0x400114ac\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_ORT0 0x400114b0\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_ORT1 0x400114b2\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_ORT2 0x400114b4\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_ORT3 0x400114b6\r
+#define CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8\r
+#define CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB 0x400114ba\r
+#define CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bc\r
+#define CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS 0x400114be\r
+#define CYDEV_UCFG_B1_P2_U1_CFG0 0x400114c0\r
+#define CYDEV_UCFG_B1_P2_U1_CFG1 0x400114c1\r
+#define CYDEV_UCFG_B1_P2_U1_CFG2 0x400114c2\r
+#define CYDEV_UCFG_B1_P2_U1_CFG3 0x400114c3\r
+#define CYDEV_UCFG_B1_P2_U1_CFG4 0x400114c4\r
+#define CYDEV_UCFG_B1_P2_U1_CFG5 0x400114c5\r
+#define CYDEV_UCFG_B1_P2_U1_CFG6 0x400114c6\r
+#define CYDEV_UCFG_B1_P2_U1_CFG7 0x400114c7\r
+#define CYDEV_UCFG_B1_P2_U1_CFG8 0x400114c8\r
+#define CYDEV_UCFG_B1_P2_U1_CFG9 0x400114c9\r
+#define CYDEV_UCFG_B1_P2_U1_CFG10 0x400114ca\r
+#define CYDEV_UCFG_B1_P2_U1_CFG11 0x400114cb\r
+#define CYDEV_UCFG_B1_P2_U1_CFG12 0x400114cc\r
+#define CYDEV_UCFG_B1_P2_U1_CFG13 0x400114cd\r
+#define CYDEV_UCFG_B1_P2_U1_CFG14 0x400114ce\r
+#define CYDEV_UCFG_B1_P2_U1_CFG15 0x400114cf\r
+#define CYDEV_UCFG_B1_P2_U1_CFG16 0x400114d0\r
+#define CYDEV_UCFG_B1_P2_U1_CFG17 0x400114d1\r
+#define CYDEV_UCFG_B1_P2_U1_CFG18 0x400114d2\r
+#define CYDEV_UCFG_B1_P2_U1_CFG19 0x400114d3\r
+#define CYDEV_UCFG_B1_P2_U1_CFG20 0x400114d4\r
+#define CYDEV_UCFG_B1_P2_U1_CFG21 0x400114d5\r
+#define CYDEV_UCFG_B1_P2_U1_CFG22 0x400114d6\r
+#define CYDEV_UCFG_B1_P2_U1_CFG23 0x400114d7\r
+#define CYDEV_UCFG_B1_P2_U1_CFG24 0x400114d8\r
+#define CYDEV_UCFG_B1_P2_U1_CFG25 0x400114d9\r
+#define CYDEV_UCFG_B1_P2_U1_CFG26 0x400114da\r
+#define CYDEV_UCFG_B1_P2_U1_CFG27 0x400114db\r
+#define CYDEV_UCFG_B1_P2_U1_CFG28 0x400114dc\r
+#define CYDEV_UCFG_B1_P2_U1_CFG29 0x400114dd\r
+#define CYDEV_UCFG_B1_P2_U1_CFG30 0x400114de\r
+#define CYDEV_UCFG_B1_P2_U1_CFG31 0x400114df\r
+#define CYDEV_UCFG_B1_P2_U1_DCFG0 0x400114e0\r
+#define CYDEV_UCFG_B1_P2_U1_DCFG1 0x400114e2\r
+#define CYDEV_UCFG_B1_P2_U1_DCFG2 0x400114e4\r
+#define CYDEV_UCFG_B1_P2_U1_DCFG3 0x400114e6\r
+#define CYDEV_UCFG_B1_P2_U1_DCFG4 0x400114e8\r
+#define CYDEV_UCFG_B1_P2_U1_DCFG5 0x400114ea\r
+#define CYDEV_UCFG_B1_P2_U1_DCFG6 0x400114ec\r
+#define CYDEV_UCFG_B1_P2_U1_DCFG7 0x400114ee\r
+#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500\r
+#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B1_P3_BASE 0x40011600\r
+#define CYDEV_UCFG_B1_P3_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600\r
+#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT0 0x40011600\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT1 0x40011604\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT2 0x40011608\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT3 0x4001160c\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT4 0x40011610\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT5 0x40011614\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT6 0x40011618\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT7 0x4001161c\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT8 0x40011620\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT9 0x40011624\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT10 0x40011628\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT11 0x4001162c\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_ORT0 0x40011630\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_ORT1 0x40011632\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_ORT2 0x40011634\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_ORT3 0x40011636\r
+#define CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638\r
+#define CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB 0x4001163a\r
+#define CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163c\r
+#define CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS 0x4001163e\r
+#define CYDEV_UCFG_B1_P3_U0_CFG0 0x40011640\r
+#define CYDEV_UCFG_B1_P3_U0_CFG1 0x40011641\r
+#define CYDEV_UCFG_B1_P3_U0_CFG2 0x40011642\r
+#define CYDEV_UCFG_B1_P3_U0_CFG3 0x40011643\r
+#define CYDEV_UCFG_B1_P3_U0_CFG4 0x40011644\r
+#define CYDEV_UCFG_B1_P3_U0_CFG5 0x40011645\r
+#define CYDEV_UCFG_B1_P3_U0_CFG6 0x40011646\r
+#define CYDEV_UCFG_B1_P3_U0_CFG7 0x40011647\r
+#define CYDEV_UCFG_B1_P3_U0_CFG8 0x40011648\r
+#define CYDEV_UCFG_B1_P3_U0_CFG9 0x40011649\r
+#define CYDEV_UCFG_B1_P3_U0_CFG10 0x4001164a\r
+#define CYDEV_UCFG_B1_P3_U0_CFG11 0x4001164b\r
+#define CYDEV_UCFG_B1_P3_U0_CFG12 0x4001164c\r
+#define CYDEV_UCFG_B1_P3_U0_CFG13 0x4001164d\r
+#define CYDEV_UCFG_B1_P3_U0_CFG14 0x4001164e\r
+#define CYDEV_UCFG_B1_P3_U0_CFG15 0x4001164f\r
+#define CYDEV_UCFG_B1_P3_U0_CFG16 0x40011650\r
+#define CYDEV_UCFG_B1_P3_U0_CFG17 0x40011651\r
+#define CYDEV_UCFG_B1_P3_U0_CFG18 0x40011652\r
+#define CYDEV_UCFG_B1_P3_U0_CFG19 0x40011653\r
+#define CYDEV_UCFG_B1_P3_U0_CFG20 0x40011654\r
+#define CYDEV_UCFG_B1_P3_U0_CFG21 0x40011655\r
+#define CYDEV_UCFG_B1_P3_U0_CFG22 0x40011656\r
+#define CYDEV_UCFG_B1_P3_U0_CFG23 0x40011657\r
+#define CYDEV_UCFG_B1_P3_U0_CFG24 0x40011658\r
+#define CYDEV_UCFG_B1_P3_U0_CFG25 0x40011659\r
+#define CYDEV_UCFG_B1_P3_U0_CFG26 0x4001165a\r
+#define CYDEV_UCFG_B1_P3_U0_CFG27 0x4001165b\r
+#define CYDEV_UCFG_B1_P3_U0_CFG28 0x4001165c\r
+#define CYDEV_UCFG_B1_P3_U0_CFG29 0x4001165d\r
+#define CYDEV_UCFG_B1_P3_U0_CFG30 0x4001165e\r
+#define CYDEV_UCFG_B1_P3_U0_CFG31 0x4001165f\r
+#define CYDEV_UCFG_B1_P3_U0_DCFG0 0x40011660\r
+#define CYDEV_UCFG_B1_P3_U0_DCFG1 0x40011662\r
+#define CYDEV_UCFG_B1_P3_U0_DCFG2 0x40011664\r
+#define CYDEV_UCFG_B1_P3_U0_DCFG3 0x40011666\r
+#define CYDEV_UCFG_B1_P3_U0_DCFG4 0x40011668\r
+#define CYDEV_UCFG_B1_P3_U0_DCFG5 0x4001166a\r
+#define CYDEV_UCFG_B1_P3_U0_DCFG6 0x4001166c\r
+#define CYDEV_UCFG_B1_P3_U0_DCFG7 0x4001166e\r
+#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680\r
+#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT0 0x40011680\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT1 0x40011684\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT2 0x40011688\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT3 0x4001168c\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT4 0x40011690\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT5 0x40011694\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT6 0x40011698\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT7 0x4001169c\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT8 0x400116a0\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT9 0x400116a4\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT10 0x400116a8\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT11 0x400116ac\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_ORT0 0x400116b0\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_ORT1 0x400116b2\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_ORT2 0x400116b4\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_ORT3 0x400116b6\r
+#define CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8\r
+#define CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB 0x400116ba\r
+#define CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bc\r
+#define CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS 0x400116be\r
+#define CYDEV_UCFG_B1_P3_U1_CFG0 0x400116c0\r
+#define CYDEV_UCFG_B1_P3_U1_CFG1 0x400116c1\r
+#define CYDEV_UCFG_B1_P3_U1_CFG2 0x400116c2\r
+#define CYDEV_UCFG_B1_P3_U1_CFG3 0x400116c3\r
+#define CYDEV_UCFG_B1_P3_U1_CFG4 0x400116c4\r
+#define CYDEV_UCFG_B1_P3_U1_CFG5 0x400116c5\r
+#define CYDEV_UCFG_B1_P3_U1_CFG6 0x400116c6\r
+#define CYDEV_UCFG_B1_P3_U1_CFG7 0x400116c7\r
+#define CYDEV_UCFG_B1_P3_U1_CFG8 0x400116c8\r
+#define CYDEV_UCFG_B1_P3_U1_CFG9 0x400116c9\r
+#define CYDEV_UCFG_B1_P3_U1_CFG10 0x400116ca\r
+#define CYDEV_UCFG_B1_P3_U1_CFG11 0x400116cb\r
+#define CYDEV_UCFG_B1_P3_U1_CFG12 0x400116cc\r
+#define CYDEV_UCFG_B1_P3_U1_CFG13 0x400116cd\r
+#define CYDEV_UCFG_B1_P3_U1_CFG14 0x400116ce\r
+#define CYDEV_UCFG_B1_P3_U1_CFG15 0x400116cf\r
+#define CYDEV_UCFG_B1_P3_U1_CFG16 0x400116d0\r
+#define CYDEV_UCFG_B1_P3_U1_CFG17 0x400116d1\r
+#define CYDEV_UCFG_B1_P3_U1_CFG18 0x400116d2\r
+#define CYDEV_UCFG_B1_P3_U1_CFG19 0x400116d3\r
+#define CYDEV_UCFG_B1_P3_U1_CFG20 0x400116d4\r
+#define CYDEV_UCFG_B1_P3_U1_CFG21 0x400116d5\r
+#define CYDEV_UCFG_B1_P3_U1_CFG22 0x400116d6\r
+#define CYDEV_UCFG_B1_P3_U1_CFG23 0x400116d7\r
+#define CYDEV_UCFG_B1_P3_U1_CFG24 0x400116d8\r
+#define CYDEV_UCFG_B1_P3_U1_CFG25 0x400116d9\r
+#define CYDEV_UCFG_B1_P3_U1_CFG26 0x400116da\r
+#define CYDEV_UCFG_B1_P3_U1_CFG27 0x400116db\r
+#define CYDEV_UCFG_B1_P3_U1_CFG28 0x400116dc\r
+#define CYDEV_UCFG_B1_P3_U1_CFG29 0x400116dd\r
+#define CYDEV_UCFG_B1_P3_U1_CFG30 0x400116de\r
+#define CYDEV_UCFG_B1_P3_U1_CFG31 0x400116df\r
+#define CYDEV_UCFG_B1_P3_U1_DCFG0 0x400116e0\r
+#define CYDEV_UCFG_B1_P3_U1_DCFG1 0x400116e2\r
+#define CYDEV_UCFG_B1_P3_U1_DCFG2 0x400116e4\r
+#define CYDEV_UCFG_B1_P3_U1_DCFG3 0x400116e6\r
+#define CYDEV_UCFG_B1_P3_U1_DCFG4 0x400116e8\r
+#define CYDEV_UCFG_B1_P3_U1_DCFG5 0x400116ea\r
+#define CYDEV_UCFG_B1_P3_U1_DCFG6 0x400116ec\r
+#define CYDEV_UCFG_B1_P3_U1_DCFG7 0x400116ee\r
+#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700\r
+#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B1_P4_BASE 0x40011800\r
+#define CYDEV_UCFG_B1_P4_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800\r
+#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT0 0x40011800\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT1 0x40011804\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT2 0x40011808\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT3 0x4001180c\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT4 0x40011810\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT5 0x40011814\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT6 0x40011818\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT7 0x4001181c\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT8 0x40011820\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT9 0x40011824\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT10 0x40011828\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT11 0x4001182c\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_ORT0 0x40011830\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_ORT1 0x40011832\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_ORT2 0x40011834\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_ORT3 0x40011836\r
+#define CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838\r
+#define CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB 0x4001183a\r
+#define CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183c\r
+#define CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS 0x4001183e\r
+#define CYDEV_UCFG_B1_P4_U0_CFG0 0x40011840\r
+#define CYDEV_UCFG_B1_P4_U0_CFG1 0x40011841\r
+#define CYDEV_UCFG_B1_P4_U0_CFG2 0x40011842\r
+#define CYDEV_UCFG_B1_P4_U0_CFG3 0x40011843\r
+#define CYDEV_UCFG_B1_P4_U0_CFG4 0x40011844\r
+#define CYDEV_UCFG_B1_P4_U0_CFG5 0x40011845\r
+#define CYDEV_UCFG_B1_P4_U0_CFG6 0x40011846\r
+#define CYDEV_UCFG_B1_P4_U0_CFG7 0x40011847\r
+#define CYDEV_UCFG_B1_P4_U0_CFG8 0x40011848\r
+#define CYDEV_UCFG_B1_P4_U0_CFG9 0x40011849\r
+#define CYDEV_UCFG_B1_P4_U0_CFG10 0x4001184a\r
+#define CYDEV_UCFG_B1_P4_U0_CFG11 0x4001184b\r
+#define CYDEV_UCFG_B1_P4_U0_CFG12 0x4001184c\r
+#define CYDEV_UCFG_B1_P4_U0_CFG13 0x4001184d\r
+#define CYDEV_UCFG_B1_P4_U0_CFG14 0x4001184e\r
+#define CYDEV_UCFG_B1_P4_U0_CFG15 0x4001184f\r
+#define CYDEV_UCFG_B1_P4_U0_CFG16 0x40011850\r
+#define CYDEV_UCFG_B1_P4_U0_CFG17 0x40011851\r
+#define CYDEV_UCFG_B1_P4_U0_CFG18 0x40011852\r
+#define CYDEV_UCFG_B1_P4_U0_CFG19 0x40011853\r
+#define CYDEV_UCFG_B1_P4_U0_CFG20 0x40011854\r
+#define CYDEV_UCFG_B1_P4_U0_CFG21 0x40011855\r
+#define CYDEV_UCFG_B1_P4_U0_CFG22 0x40011856\r
+#define CYDEV_UCFG_B1_P4_U0_CFG23 0x40011857\r
+#define CYDEV_UCFG_B1_P4_U0_CFG24 0x40011858\r
+#define CYDEV_UCFG_B1_P4_U0_CFG25 0x40011859\r
+#define CYDEV_UCFG_B1_P4_U0_CFG26 0x4001185a\r
+#define CYDEV_UCFG_B1_P4_U0_CFG27 0x4001185b\r
+#define CYDEV_UCFG_B1_P4_U0_CFG28 0x4001185c\r
+#define CYDEV_UCFG_B1_P4_U0_CFG29 0x4001185d\r
+#define CYDEV_UCFG_B1_P4_U0_CFG30 0x4001185e\r
+#define CYDEV_UCFG_B1_P4_U0_CFG31 0x4001185f\r
+#define CYDEV_UCFG_B1_P4_U0_DCFG0 0x40011860\r
+#define CYDEV_UCFG_B1_P4_U0_DCFG1 0x40011862\r
+#define CYDEV_UCFG_B1_P4_U0_DCFG2 0x40011864\r
+#define CYDEV_UCFG_B1_P4_U0_DCFG3 0x40011866\r
+#define CYDEV_UCFG_B1_P4_U0_DCFG4 0x40011868\r
+#define CYDEV_UCFG_B1_P4_U0_DCFG5 0x4001186a\r
+#define CYDEV_UCFG_B1_P4_U0_DCFG6 0x4001186c\r
+#define CYDEV_UCFG_B1_P4_U0_DCFG7 0x4001186e\r
+#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880\r
+#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT0 0x40011880\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT1 0x40011884\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT2 0x40011888\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT3 0x4001188c\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT4 0x40011890\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT5 0x40011894\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT6 0x40011898\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT7 0x4001189c\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT8 0x400118a0\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT9 0x400118a4\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT10 0x400118a8\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT11 0x400118ac\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_ORT0 0x400118b0\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_ORT1 0x400118b2\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_ORT2 0x400118b4\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_ORT3 0x400118b6\r
+#define CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8\r
+#define CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB 0x400118ba\r
+#define CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bc\r
+#define CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS 0x400118be\r
+#define CYDEV_UCFG_B1_P4_U1_CFG0 0x400118c0\r
+#define CYDEV_UCFG_B1_P4_U1_CFG1 0x400118c1\r
+#define CYDEV_UCFG_B1_P4_U1_CFG2 0x400118c2\r
+#define CYDEV_UCFG_B1_P4_U1_CFG3 0x400118c3\r
+#define CYDEV_UCFG_B1_P4_U1_CFG4 0x400118c4\r
+#define CYDEV_UCFG_B1_P4_U1_CFG5 0x400118c5\r
+#define CYDEV_UCFG_B1_P4_U1_CFG6 0x400118c6\r
+#define CYDEV_UCFG_B1_P4_U1_CFG7 0x400118c7\r
+#define CYDEV_UCFG_B1_P4_U1_CFG8 0x400118c8\r
+#define CYDEV_UCFG_B1_P4_U1_CFG9 0x400118c9\r
+#define CYDEV_UCFG_B1_P4_U1_CFG10 0x400118ca\r
+#define CYDEV_UCFG_B1_P4_U1_CFG11 0x400118cb\r
+#define CYDEV_UCFG_B1_P4_U1_CFG12 0x400118cc\r
+#define CYDEV_UCFG_B1_P4_U1_CFG13 0x400118cd\r
+#define CYDEV_UCFG_B1_P4_U1_CFG14 0x400118ce\r
+#define CYDEV_UCFG_B1_P4_U1_CFG15 0x400118cf\r
+#define CYDEV_UCFG_B1_P4_U1_CFG16 0x400118d0\r
+#define CYDEV_UCFG_B1_P4_U1_CFG17 0x400118d1\r
+#define CYDEV_UCFG_B1_P4_U1_CFG18 0x400118d2\r
+#define CYDEV_UCFG_B1_P4_U1_CFG19 0x400118d3\r
+#define CYDEV_UCFG_B1_P4_U1_CFG20 0x400118d4\r
+#define CYDEV_UCFG_B1_P4_U1_CFG21 0x400118d5\r
+#define CYDEV_UCFG_B1_P4_U1_CFG22 0x400118d6\r
+#define CYDEV_UCFG_B1_P4_U1_CFG23 0x400118d7\r
+#define CYDEV_UCFG_B1_P4_U1_CFG24 0x400118d8\r
+#define CYDEV_UCFG_B1_P4_U1_CFG25 0x400118d9\r
+#define CYDEV_UCFG_B1_P4_U1_CFG26 0x400118da\r
+#define CYDEV_UCFG_B1_P4_U1_CFG27 0x400118db\r
+#define CYDEV_UCFG_B1_P4_U1_CFG28 0x400118dc\r
+#define CYDEV_UCFG_B1_P4_U1_CFG29 0x400118dd\r
+#define CYDEV_UCFG_B1_P4_U1_CFG30 0x400118de\r
+#define CYDEV_UCFG_B1_P4_U1_CFG31 0x400118df\r
+#define CYDEV_UCFG_B1_P4_U1_DCFG0 0x400118e0\r
+#define CYDEV_UCFG_B1_P4_U1_DCFG1 0x400118e2\r
+#define CYDEV_UCFG_B1_P4_U1_DCFG2 0x400118e4\r
+#define CYDEV_UCFG_B1_P4_U1_DCFG3 0x400118e6\r
+#define CYDEV_UCFG_B1_P4_U1_DCFG4 0x400118e8\r
+#define CYDEV_UCFG_B1_P4_U1_DCFG5 0x400118ea\r
+#define CYDEV_UCFG_B1_P4_U1_DCFG6 0x400118ec\r
+#define CYDEV_UCFG_B1_P4_U1_DCFG7 0x400118ee\r
+#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900\r
+#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B1_P5_BASE 0x40011a00\r
+#define CYDEV_UCFG_B1_P5_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00\r
+#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT0 0x40011a00\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT1 0x40011a04\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT2 0x40011a08\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT3 0x40011a0c\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT4 0x40011a10\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT5 0x40011a14\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT6 0x40011a18\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT7 0x40011a1c\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT8 0x40011a20\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT9 0x40011a24\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT10 0x40011a28\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT11 0x40011a2c\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_ORT0 0x40011a30\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_ORT1 0x40011a32\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_ORT2 0x40011a34\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_ORT3 0x40011a36\r
+#define CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38\r
+#define CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB 0x40011a3a\r
+#define CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3c\r
+#define CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3e\r
+#define CYDEV_UCFG_B1_P5_U0_CFG0 0x40011a40\r
+#define CYDEV_UCFG_B1_P5_U0_CFG1 0x40011a41\r
+#define CYDEV_UCFG_B1_P5_U0_CFG2 0x40011a42\r
+#define CYDEV_UCFG_B1_P5_U0_CFG3 0x40011a43\r
+#define CYDEV_UCFG_B1_P5_U0_CFG4 0x40011a44\r
+#define CYDEV_UCFG_B1_P5_U0_CFG5 0x40011a45\r
+#define CYDEV_UCFG_B1_P5_U0_CFG6 0x40011a46\r
+#define CYDEV_UCFG_B1_P5_U0_CFG7 0x40011a47\r
+#define CYDEV_UCFG_B1_P5_U0_CFG8 0x40011a48\r
+#define CYDEV_UCFG_B1_P5_U0_CFG9 0x40011a49\r
+#define CYDEV_UCFG_B1_P5_U0_CFG10 0x40011a4a\r
+#define CYDEV_UCFG_B1_P5_U0_CFG11 0x40011a4b\r
+#define CYDEV_UCFG_B1_P5_U0_CFG12 0x40011a4c\r
+#define CYDEV_UCFG_B1_P5_U0_CFG13 0x40011a4d\r
+#define CYDEV_UCFG_B1_P5_U0_CFG14 0x40011a4e\r
+#define CYDEV_UCFG_B1_P5_U0_CFG15 0x40011a4f\r
+#define CYDEV_UCFG_B1_P5_U0_CFG16 0x40011a50\r
+#define CYDEV_UCFG_B1_P5_U0_CFG17 0x40011a51\r
+#define CYDEV_UCFG_B1_P5_U0_CFG18 0x40011a52\r
+#define CYDEV_UCFG_B1_P5_U0_CFG19 0x40011a53\r
+#define CYDEV_UCFG_B1_P5_U0_CFG20 0x40011a54\r
+#define CYDEV_UCFG_B1_P5_U0_CFG21 0x40011a55\r
+#define CYDEV_UCFG_B1_P5_U0_CFG22 0x40011a56\r
+#define CYDEV_UCFG_B1_P5_U0_CFG23 0x40011a57\r
+#define CYDEV_UCFG_B1_P5_U0_CFG24 0x40011a58\r
+#define CYDEV_UCFG_B1_P5_U0_CFG25 0x40011a59\r
+#define CYDEV_UCFG_B1_P5_U0_CFG26 0x40011a5a\r
+#define CYDEV_UCFG_B1_P5_U0_CFG27 0x40011a5b\r
+#define CYDEV_UCFG_B1_P5_U0_CFG28 0x40011a5c\r
+#define CYDEV_UCFG_B1_P5_U0_CFG29 0x40011a5d\r
+#define CYDEV_UCFG_B1_P5_U0_CFG30 0x40011a5e\r
+#define CYDEV_UCFG_B1_P5_U0_CFG31 0x40011a5f\r
+#define CYDEV_UCFG_B1_P5_U0_DCFG0 0x40011a60\r
+#define CYDEV_UCFG_B1_P5_U0_DCFG1 0x40011a62\r
+#define CYDEV_UCFG_B1_P5_U0_DCFG2 0x40011a64\r
+#define CYDEV_UCFG_B1_P5_U0_DCFG3 0x40011a66\r
+#define CYDEV_UCFG_B1_P5_U0_DCFG4 0x40011a68\r
+#define CYDEV_UCFG_B1_P5_U0_DCFG5 0x40011a6a\r
+#define CYDEV_UCFG_B1_P5_U0_DCFG6 0x40011a6c\r
+#define CYDEV_UCFG_B1_P5_U0_DCFG7 0x40011a6e\r
+#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80\r
+#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT0 0x40011a80\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT1 0x40011a84\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT2 0x40011a88\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT3 0x40011a8c\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT4 0x40011a90\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT5 0x40011a94\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT6 0x40011a98\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT7 0x40011a9c\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT8 0x40011aa0\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT9 0x40011aa4\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT10 0x40011aa8\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT11 0x40011aac\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_ORT0 0x40011ab0\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_ORT1 0x40011ab2\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_ORT2 0x40011ab4\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_ORT3 0x40011ab6\r
+#define CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8\r
+#define CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB 0x40011aba\r
+#define CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abc\r
+#define CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS 0x40011abe\r
+#define CYDEV_UCFG_B1_P5_U1_CFG0 0x40011ac0\r
+#define CYDEV_UCFG_B1_P5_U1_CFG1 0x40011ac1\r
+#define CYDEV_UCFG_B1_P5_U1_CFG2 0x40011ac2\r
+#define CYDEV_UCFG_B1_P5_U1_CFG3 0x40011ac3\r
+#define CYDEV_UCFG_B1_P5_U1_CFG4 0x40011ac4\r
+#define CYDEV_UCFG_B1_P5_U1_CFG5 0x40011ac5\r
+#define CYDEV_UCFG_B1_P5_U1_CFG6 0x40011ac6\r
+#define CYDEV_UCFG_B1_P5_U1_CFG7 0x40011ac7\r
+#define CYDEV_UCFG_B1_P5_U1_CFG8 0x40011ac8\r
+#define CYDEV_UCFG_B1_P5_U1_CFG9 0x40011ac9\r
+#define CYDEV_UCFG_B1_P5_U1_CFG10 0x40011aca\r
+#define CYDEV_UCFG_B1_P5_U1_CFG11 0x40011acb\r
+#define CYDEV_UCFG_B1_P5_U1_CFG12 0x40011acc\r
+#define CYDEV_UCFG_B1_P5_U1_CFG13 0x40011acd\r
+#define CYDEV_UCFG_B1_P5_U1_CFG14 0x40011ace\r
+#define CYDEV_UCFG_B1_P5_U1_CFG15 0x40011acf\r
+#define CYDEV_UCFG_B1_P5_U1_CFG16 0x40011ad0\r
+#define CYDEV_UCFG_B1_P5_U1_CFG17 0x40011ad1\r
+#define CYDEV_UCFG_B1_P5_U1_CFG18 0x40011ad2\r
+#define CYDEV_UCFG_B1_P5_U1_CFG19 0x40011ad3\r
+#define CYDEV_UCFG_B1_P5_U1_CFG20 0x40011ad4\r
+#define CYDEV_UCFG_B1_P5_U1_CFG21 0x40011ad5\r
+#define CYDEV_UCFG_B1_P5_U1_CFG22 0x40011ad6\r
+#define CYDEV_UCFG_B1_P5_U1_CFG23 0x40011ad7\r
+#define CYDEV_UCFG_B1_P5_U1_CFG24 0x40011ad8\r
+#define CYDEV_UCFG_B1_P5_U1_CFG25 0x40011ad9\r
+#define CYDEV_UCFG_B1_P5_U1_CFG26 0x40011ada\r
+#define CYDEV_UCFG_B1_P5_U1_CFG27 0x40011adb\r
+#define CYDEV_UCFG_B1_P5_U1_CFG28 0x40011adc\r
+#define CYDEV_UCFG_B1_P5_U1_CFG29 0x40011add\r
+#define CYDEV_UCFG_B1_P5_U1_CFG30 0x40011ade\r
+#define CYDEV_UCFG_B1_P5_U1_CFG31 0x40011adf\r
+#define CYDEV_UCFG_B1_P5_U1_DCFG0 0x40011ae0\r
+#define CYDEV_UCFG_B1_P5_U1_DCFG1 0x40011ae2\r
+#define CYDEV_UCFG_B1_P5_U1_DCFG2 0x40011ae4\r
+#define CYDEV_UCFG_B1_P5_U1_DCFG3 0x40011ae6\r
+#define CYDEV_UCFG_B1_P5_U1_DCFG4 0x40011ae8\r
+#define CYDEV_UCFG_B1_P5_U1_DCFG5 0x40011aea\r
+#define CYDEV_UCFG_B1_P5_U1_DCFG6 0x40011aec\r
+#define CYDEV_UCFG_B1_P5_U1_DCFG7 0x40011aee\r
+#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00\r
+#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI0_BASE 0x40014000\r
+#define CYDEV_UCFG_DSI0_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI1_BASE 0x40014100\r
+#define CYDEV_UCFG_DSI1_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI2_BASE 0x40014200\r
+#define CYDEV_UCFG_DSI2_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI3_BASE 0x40014300\r
+#define CYDEV_UCFG_DSI3_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI4_BASE 0x40014400\r
+#define CYDEV_UCFG_DSI4_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI5_BASE 0x40014500\r
+#define CYDEV_UCFG_DSI5_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI6_BASE 0x40014600\r
+#define CYDEV_UCFG_DSI6_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI7_BASE 0x40014700\r
+#define CYDEV_UCFG_DSI7_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI8_BASE 0x40014800\r
+#define CYDEV_UCFG_DSI8_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI9_BASE 0x40014900\r
+#define CYDEV_UCFG_DSI9_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI12_BASE 0x40014c00\r
+#define CYDEV_UCFG_DSI12_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI13_BASE 0x40014d00\r
+#define CYDEV_UCFG_DSI13_SIZE 0x000000ef\r
+#define CYDEV_UCFG_BCTL0_BASE 0x40015000\r
+#define CYDEV_UCFG_BCTL0_SIZE 0x00000010\r
+#define CYDEV_UCFG_BCTL0_MDCLK_EN 0x40015000\r
+#define CYDEV_UCFG_BCTL0_MBCLK_EN 0x40015001\r
+#define CYDEV_UCFG_BCTL0_WAIT_CFG 0x40015002\r
+#define CYDEV_UCFG_BCTL0_BANK_CTL 0x40015003\r
+#define CYDEV_UCFG_BCTL0_UDB_TEST_3 0x40015007\r
+#define CYDEV_UCFG_BCTL0_DCLK_EN0 0x40015008\r
+#define CYDEV_UCFG_BCTL0_BCLK_EN0 0x40015009\r
+#define CYDEV_UCFG_BCTL0_DCLK_EN1 0x4001500a\r
+#define CYDEV_UCFG_BCTL0_BCLK_EN1 0x4001500b\r
+#define CYDEV_UCFG_BCTL0_DCLK_EN2 0x4001500c\r
+#define CYDEV_UCFG_BCTL0_BCLK_EN2 0x4001500d\r
+#define CYDEV_UCFG_BCTL0_DCLK_EN3 0x4001500e\r
+#define CYDEV_UCFG_BCTL0_BCLK_EN3 0x4001500f\r
+#define CYDEV_UCFG_BCTL1_BASE 0x40015010\r
+#define CYDEV_UCFG_BCTL1_SIZE 0x00000010\r
+#define CYDEV_UCFG_BCTL1_MDCLK_EN 0x40015010\r
+#define CYDEV_UCFG_BCTL1_MBCLK_EN 0x40015011\r
+#define CYDEV_UCFG_BCTL1_WAIT_CFG 0x40015012\r
+#define CYDEV_UCFG_BCTL1_BANK_CTL 0x40015013\r
+#define CYDEV_UCFG_BCTL1_UDB_TEST_3 0x40015017\r
+#define CYDEV_UCFG_BCTL1_DCLK_EN0 0x40015018\r
+#define CYDEV_UCFG_BCTL1_BCLK_EN0 0x40015019\r
+#define CYDEV_UCFG_BCTL1_DCLK_EN1 0x4001501a\r
+#define CYDEV_UCFG_BCTL1_BCLK_EN1 0x4001501b\r
+#define CYDEV_UCFG_BCTL1_DCLK_EN2 0x4001501c\r
+#define CYDEV_UCFG_BCTL1_BCLK_EN2 0x4001501d\r
+#define CYDEV_UCFG_BCTL1_DCLK_EN3 0x4001501e\r
+#define CYDEV_UCFG_BCTL1_BCLK_EN3 0x4001501f\r
+#define CYDEV_IDMUX_BASE 0x40015100\r
+#define CYDEV_IDMUX_SIZE 0x00000016\r
+#define CYDEV_IDMUX_IRQ_CTL0 0x40015100\r
+#define CYDEV_IDMUX_IRQ_CTL1 0x40015101\r
+#define CYDEV_IDMUX_IRQ_CTL2 0x40015102\r
+#define CYDEV_IDMUX_IRQ_CTL3 0x40015103\r
+#define CYDEV_IDMUX_IRQ_CTL4 0x40015104\r
+#define CYDEV_IDMUX_IRQ_CTL5 0x40015105\r
+#define CYDEV_IDMUX_IRQ_CTL6 0x40015106\r
+#define CYDEV_IDMUX_IRQ_CTL7 0x40015107\r
+#define CYDEV_IDMUX_DRQ_CTL0 0x40015110\r
+#define CYDEV_IDMUX_DRQ_CTL1 0x40015111\r
+#define CYDEV_IDMUX_DRQ_CTL2 0x40015112\r
+#define CYDEV_IDMUX_DRQ_CTL3 0x40015113\r
+#define CYDEV_IDMUX_DRQ_CTL4 0x40015114\r
+#define CYDEV_IDMUX_DRQ_CTL5 0x40015115\r
+#define CYDEV_CACHERAM_BASE 0x40030000\r
+#define CYDEV_CACHERAM_SIZE 0x00000400\r
+#define CYDEV_CACHERAM_DATA_MBASE 0x40030000\r
+#define CYDEV_CACHERAM_DATA_MSIZE 0x00000400\r
+#define CYDEV_SFR_BASE 0x40050100\r
+#define CYDEV_SFR_SIZE 0x000000fb\r
+#define CYDEV_SFR_GPIO0 0x40050180\r
+#define CYDEV_SFR_GPIRD0 0x40050189\r
+#define CYDEV_SFR_GPIO0_SEL 0x4005018a\r
+#define CYDEV_SFR_GPIO1 0x40050190\r
+#define CYDEV_SFR_GPIRD1 0x40050191\r
+#define CYDEV_SFR_GPIO2 0x40050198\r
+#define CYDEV_SFR_GPIRD2 0x40050199\r
+#define CYDEV_SFR_GPIO2_SEL 0x4005019a\r
+#define CYDEV_SFR_GPIO1_SEL 0x400501a2\r
+#define CYDEV_SFR_GPIO3 0x400501b0\r
+#define CYDEV_SFR_GPIRD3 0x400501b1\r
+#define CYDEV_SFR_GPIO3_SEL 0x400501b2\r
+#define CYDEV_SFR_GPIO4 0x400501c0\r
+#define CYDEV_SFR_GPIRD4 0x400501c1\r
+#define CYDEV_SFR_GPIO4_SEL 0x400501c2\r
+#define CYDEV_SFR_GPIO5 0x400501c8\r
+#define CYDEV_SFR_GPIRD5 0x400501c9\r
+#define CYDEV_SFR_GPIO5_SEL 0x400501ca\r
+#define CYDEV_SFR_GPIO6 0x400501d8\r
+#define CYDEV_SFR_GPIRD6 0x400501d9\r
+#define CYDEV_SFR_GPIO6_SEL 0x400501da\r
+#define CYDEV_SFR_GPIO12 0x400501e8\r
+#define CYDEV_SFR_GPIRD12 0x400501e9\r
+#define CYDEV_SFR_GPIO12_SEL 0x400501f2\r
+#define CYDEV_SFR_GPIO15 0x400501f8\r
+#define CYDEV_SFR_GPIRD15 0x400501f9\r
+#define CYDEV_SFR_GPIO15_SEL 0x400501fa\r
+#define CYDEV_P3BA_BASE 0x40050300\r
+#define CYDEV_P3BA_SIZE 0x0000002b\r
+#define CYDEV_P3BA_Y_START 0x40050300\r
+#define CYDEV_P3BA_YROLL 0x40050301\r
+#define CYDEV_P3BA_YCFG 0x40050302\r
+#define CYDEV_P3BA_X_START1 0x40050303\r
+#define CYDEV_P3BA_X_START2 0x40050304\r
+#define CYDEV_P3BA_XROLL1 0x40050305\r
+#define CYDEV_P3BA_XROLL2 0x40050306\r
+#define CYDEV_P3BA_XINC 0x40050307\r
+#define CYDEV_P3BA_XCFG 0x40050308\r
+#define CYDEV_P3BA_OFFSETADDR1 0x40050309\r
+#define CYDEV_P3BA_OFFSETADDR2 0x4005030a\r
+#define CYDEV_P3BA_OFFSETADDR3 0x4005030b\r
+#define CYDEV_P3BA_ABSADDR1 0x4005030c\r
+#define CYDEV_P3BA_ABSADDR2 0x4005030d\r
+#define CYDEV_P3BA_ABSADDR3 0x4005030e\r
+#define CYDEV_P3BA_ABSADDR4 0x4005030f\r
+#define CYDEV_P3BA_DATCFG1 0x40050310\r
+#define CYDEV_P3BA_DATCFG2 0x40050311\r
+#define CYDEV_P3BA_CMP_RSLT1 0x40050314\r
+#define CYDEV_P3BA_CMP_RSLT2 0x40050315\r
+#define CYDEV_P3BA_CMP_RSLT3 0x40050316\r
+#define CYDEV_P3BA_CMP_RSLT4 0x40050317\r
+#define CYDEV_P3BA_DATA_REG1 0x40050318\r
+#define CYDEV_P3BA_DATA_REG2 0x40050319\r
+#define CYDEV_P3BA_DATA_REG3 0x4005031a\r
+#define CYDEV_P3BA_DATA_REG4 0x4005031b\r
+#define CYDEV_P3BA_EXP_DATA1 0x4005031c\r
+#define CYDEV_P3BA_EXP_DATA2 0x4005031d\r
+#define CYDEV_P3BA_EXP_DATA3 0x4005031e\r
+#define CYDEV_P3BA_EXP_DATA4 0x4005031f\r
+#define CYDEV_P3BA_MSTR_HRDATA1 0x40050320\r
+#define CYDEV_P3BA_MSTR_HRDATA2 0x40050321\r
+#define CYDEV_P3BA_MSTR_HRDATA3 0x40050322\r
+#define CYDEV_P3BA_MSTR_HRDATA4 0x40050323\r
+#define CYDEV_P3BA_BIST_EN 0x40050324\r
+#define CYDEV_P3BA_PHUB_MASTER_SSR 0x40050325\r
+#define CYDEV_P3BA_SEQCFG1 0x40050326\r
+#define CYDEV_P3BA_SEQCFG2 0x40050327\r
+#define CYDEV_P3BA_Y_CURR 0x40050328\r
+#define CYDEV_P3BA_X_CURR1 0x40050329\r
+#define CYDEV_P3BA_X_CURR2 0x4005032a\r
+#define CYDEV_PANTHER_BASE 0x40080000\r
+#define CYDEV_PANTHER_SIZE 0x00000020\r
+#define CYDEV_PANTHER_STCALIB_CFG 0x40080000\r
+#define CYDEV_PANTHER_WAITPIPE 0x40080004\r
+#define CYDEV_PANTHER_TRACE_CFG 0x40080008\r
+#define CYDEV_PANTHER_DBG_CFG 0x4008000c\r
+#define CYDEV_PANTHER_CM3_LCKRST_STAT 0x40080018\r
+#define CYDEV_PANTHER_DEVICE_ID 0x4008001c\r
+#define CYDEV_FLSECC_BASE 0x48000000\r
+#define CYDEV_FLSECC_SIZE 0x00008000\r
+#define CYDEV_FLSECC_DATA_MBASE 0x48000000\r
+#define CYDEV_FLSECC_DATA_MSIZE 0x00008000\r
+#define CYDEV_FLSHID_BASE 0x49000000\r
+#define CYDEV_FLSHID_SIZE 0x00000200\r
+#define CYDEV_FLSHID_RSVD_MBASE 0x49000000\r
+#define CYDEV_FLSHID_RSVD_MSIZE 0x00000080\r
+#define CYDEV_FLSHID_CUST_MDATA_MBASE 0x49000080\r
+#define CYDEV_FLSHID_CUST_MDATA_MSIZE 0x00000080\r
+#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100\r
+#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040\r
+#define CYDEV_FLSHID_CUST_TABLES_Y_LOC 0x49000100\r
+#define CYDEV_FLSHID_CUST_TABLES_X_LOC 0x49000101\r
+#define CYDEV_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102\r
+#define CYDEV_FLSHID_CUST_TABLES_LOT_LSB 0x49000103\r
+#define CYDEV_FLSHID_CUST_TABLES_LOT_MSB 0x49000104\r
+#define CYDEV_FLSHID_CUST_TABLES_WRK_WK 0x49000105\r
+#define CYDEV_FLSHID_CUST_TABLES_FAB_YR 0x49000106\r
+#define CYDEV_FLSHID_CUST_TABLES_MINOR 0x49000107\r
+#define CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108\r
+#define CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109\r
+#define CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010a\r
+#define CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010b\r
+#define CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010c\r
+#define CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010d\r
+#define CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010e\r
+#define CYDEV_FLSHID_CUST_TABLES_IMO_USB 0x4900010f\r
+#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110\r
+#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111\r
+#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112\r
+#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113\r
+#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114\r
+#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115\r
+#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116\r
+#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117\r
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M1 0x49000118\r
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M2 0x49000119\r
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M3 0x4900011a\r
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M4 0x4900011b\r
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M5 0x4900011c\r
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M6 0x4900011d\r
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M7 0x4900011e\r
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M8 0x4900011f\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M1 0x49000120\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M2 0x49000121\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M3 0x49000122\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M4 0x49000123\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M5 0x49000124\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M6 0x49000125\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M7 0x49000126\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M8 0x49000127\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M1 0x49000128\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M2 0x49000129\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M3 0x4900012a\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M4 0x4900012b\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M5 0x4900012c\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M6 0x4900012d\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M7 0x4900012e\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M8 0x4900012f\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M1 0x49000130\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M2 0x49000131\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M3 0x49000132\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M4 0x49000133\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M5 0x49000134\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M6 0x49000135\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M7 0x49000136\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M8 0x49000137\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M1 0x49000138\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M2 0x49000139\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M3 0x4900013a\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M4 0x4900013b\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M5 0x4900013c\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M6 0x4900013d\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M7 0x4900013e\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M8 0x4900013f\r
+#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180\r
+#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080\r
+#define CYDEV_FLSHID_MFG_CFG_IMO_TR1 0x49000188\r
+#define CYDEV_FLSHID_MFG_CFG_CMP0_TR0 0x490001ac\r
+#define CYDEV_FLSHID_MFG_CFG_CMP1_TR0 0x490001ae\r
+#define CYDEV_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0\r
+#define CYDEV_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2\r
+#define CYDEV_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4\r
+#define CYDEV_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6\r
+#define CYDEV_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8\r
+#define CYDEV_FLSHID_MFG_CFG_CMP3_TR1 0x490001ba\r
+#define CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ce\r
+#define CYDEV_EXTMEM_BASE 0x60000000\r
+#define CYDEV_EXTMEM_SIZE 0x00800000\r
+#define CYDEV_EXTMEM_DATA_MBASE 0x60000000\r
+#define CYDEV_EXTMEM_DATA_MSIZE 0x00800000\r
+#define CYDEV_ITM_BASE 0xe0000000\r
+#define CYDEV_ITM_SIZE 0x00001000\r
+#define CYDEV_ITM_TRACE_EN 0xe0000e00\r
+#define CYDEV_ITM_TRACE_PRIVILEGE 0xe0000e40\r
+#define CYDEV_ITM_TRACE_CTRL 0xe0000e80\r
+#define CYDEV_ITM_LOCK_ACCESS 0xe0000fb0\r
+#define CYDEV_ITM_LOCK_STATUS 0xe0000fb4\r
+#define CYDEV_ITM_PID4 0xe0000fd0\r
+#define CYDEV_ITM_PID5 0xe0000fd4\r
+#define CYDEV_ITM_PID6 0xe0000fd8\r
+#define CYDEV_ITM_PID7 0xe0000fdc\r
+#define CYDEV_ITM_PID0 0xe0000fe0\r
+#define CYDEV_ITM_PID1 0xe0000fe4\r
+#define CYDEV_ITM_PID2 0xe0000fe8\r
+#define CYDEV_ITM_PID3 0xe0000fec\r
+#define CYDEV_ITM_CID0 0xe0000ff0\r
+#define CYDEV_ITM_CID1 0xe0000ff4\r
+#define CYDEV_ITM_CID2 0xe0000ff8\r
+#define CYDEV_ITM_CID3 0xe0000ffc\r
+#define CYDEV_DWT_BASE 0xe0001000\r
+#define CYDEV_DWT_SIZE 0x0000005c\r
+#define CYDEV_DWT_CTRL 0xe0001000\r
+#define CYDEV_DWT_CYCLE_COUNT 0xe0001004\r
+#define CYDEV_DWT_CPI_COUNT 0xe0001008\r
+#define CYDEV_DWT_EXC_OVHD_COUNT 0xe000100c\r
+#define CYDEV_DWT_SLEEP_COUNT 0xe0001010\r
+#define CYDEV_DWT_LSU_COUNT 0xe0001014\r
+#define CYDEV_DWT_FOLD_COUNT 0xe0001018\r
+#define CYDEV_DWT_PC_SAMPLE 0xe000101c\r
+#define CYDEV_DWT_COMP_0 0xe0001020\r
+#define CYDEV_DWT_MASK_0 0xe0001024\r
+#define CYDEV_DWT_FUNCTION_0 0xe0001028\r
+#define CYDEV_DWT_COMP_1 0xe0001030\r
+#define CYDEV_DWT_MASK_1 0xe0001034\r
+#define CYDEV_DWT_FUNCTION_1 0xe0001038\r
+#define CYDEV_DWT_COMP_2 0xe0001040\r
+#define CYDEV_DWT_MASK_2 0xe0001044\r
+#define CYDEV_DWT_FUNCTION_2 0xe0001048\r
+#define CYDEV_DWT_COMP_3 0xe0001050\r
+#define CYDEV_DWT_MASK_3 0xe0001054\r
+#define CYDEV_DWT_FUNCTION_3 0xe0001058\r
+#define CYDEV_FPB_BASE 0xe0002000\r
+#define CYDEV_FPB_SIZE 0x00001000\r
+#define CYDEV_FPB_CTRL 0xe0002000\r
+#define CYDEV_FPB_REMAP 0xe0002004\r
+#define CYDEV_FPB_FP_COMP_0 0xe0002008\r
+#define CYDEV_FPB_FP_COMP_1 0xe000200c\r
+#define CYDEV_FPB_FP_COMP_2 0xe0002010\r
+#define CYDEV_FPB_FP_COMP_3 0xe0002014\r
+#define CYDEV_FPB_FP_COMP_4 0xe0002018\r
+#define CYDEV_FPB_FP_COMP_5 0xe000201c\r
+#define CYDEV_FPB_FP_COMP_6 0xe0002020\r
+#define CYDEV_FPB_FP_COMP_7 0xe0002024\r
+#define CYDEV_FPB_PID4 0xe0002fd0\r
+#define CYDEV_FPB_PID5 0xe0002fd4\r
+#define CYDEV_FPB_PID6 0xe0002fd8\r
+#define CYDEV_FPB_PID7 0xe0002fdc\r
+#define CYDEV_FPB_PID0 0xe0002fe0\r
+#define CYDEV_FPB_PID1 0xe0002fe4\r
+#define CYDEV_FPB_PID2 0xe0002fe8\r
+#define CYDEV_FPB_PID3 0xe0002fec\r
+#define CYDEV_FPB_CID0 0xe0002ff0\r
+#define CYDEV_FPB_CID1 0xe0002ff4\r
+#define CYDEV_FPB_CID2 0xe0002ff8\r
+#define CYDEV_FPB_CID3 0xe0002ffc\r
+#define CYDEV_NVIC_BASE 0xe000e000\r
+#define CYDEV_NVIC_SIZE 0x00000d3c\r
+#define CYDEV_NVIC_INT_CTL_TYPE 0xe000e004\r
+#define CYDEV_NVIC_SYSTICK_CTL 0xe000e010\r
+#define CYDEV_NVIC_SYSTICK_RELOAD 0xe000e014\r
+#define CYDEV_NVIC_SYSTICK_CURRENT 0xe000e018\r
+#define CYDEV_NVIC_SYSTICK_CAL 0xe000e01c\r
+#define CYDEV_NVIC_SETENA0 0xe000e100\r
+#define CYDEV_NVIC_CLRENA0 0xe000e180\r
+#define CYDEV_NVIC_SETPEND0 0xe000e200\r
+#define CYDEV_NVIC_CLRPEND0 0xe000e280\r
+#define CYDEV_NVIC_ACTIVE0 0xe000e300\r
+#define CYDEV_NVIC_PRI_0 0xe000e400\r
+#define CYDEV_NVIC_PRI_1 0xe000e401\r
+#define CYDEV_NVIC_PRI_2 0xe000e402\r
+#define CYDEV_NVIC_PRI_3 0xe000e403\r
+#define CYDEV_NVIC_PRI_4 0xe000e404\r
+#define CYDEV_NVIC_PRI_5 0xe000e405\r
+#define CYDEV_NVIC_PRI_6 0xe000e406\r
+#define CYDEV_NVIC_PRI_7 0xe000e407\r
+#define CYDEV_NVIC_PRI_8 0xe000e408\r
+#define CYDEV_NVIC_PRI_9 0xe000e409\r
+#define CYDEV_NVIC_PRI_10 0xe000e40a\r
+#define CYDEV_NVIC_PRI_11 0xe000e40b\r
+#define CYDEV_NVIC_PRI_12 0xe000e40c\r
+#define CYDEV_NVIC_PRI_13 0xe000e40d\r
+#define CYDEV_NVIC_PRI_14 0xe000e40e\r
+#define CYDEV_NVIC_PRI_15 0xe000e40f\r
+#define CYDEV_NVIC_PRI_16 0xe000e410\r
+#define CYDEV_NVIC_PRI_17 0xe000e411\r
+#define CYDEV_NVIC_PRI_18 0xe000e412\r
+#define CYDEV_NVIC_PRI_19 0xe000e413\r
+#define CYDEV_NVIC_PRI_20 0xe000e414\r
+#define CYDEV_NVIC_PRI_21 0xe000e415\r
+#define CYDEV_NVIC_PRI_22 0xe000e416\r
+#define CYDEV_NVIC_PRI_23 0xe000e417\r
+#define CYDEV_NVIC_PRI_24 0xe000e418\r
+#define CYDEV_NVIC_PRI_25 0xe000e419\r
+#define CYDEV_NVIC_PRI_26 0xe000e41a\r
+#define CYDEV_NVIC_PRI_27 0xe000e41b\r
+#define CYDEV_NVIC_PRI_28 0xe000e41c\r
+#define CYDEV_NVIC_PRI_29 0xe000e41d\r
+#define CYDEV_NVIC_PRI_30 0xe000e41e\r
+#define CYDEV_NVIC_PRI_31 0xe000e41f\r
+#define CYDEV_NVIC_CPUID_BASE 0xe000ed00\r
+#define CYDEV_NVIC_INTR_CTRL_STATE 0xe000ed04\r
+#define CYDEV_NVIC_VECT_OFFSET 0xe000ed08\r
+#define CYDEV_NVIC_APPLN_INTR 0xe000ed0c\r
+#define CYDEV_NVIC_SYSTEM_CONTROL 0xe000ed10\r
+#define CYDEV_NVIC_CFG_CONTROL 0xe000ed14\r
+#define CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18\r
+#define CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1c\r
+#define CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20\r
+#define CYDEV_NVIC_SYS_HANDLER_CSR 0xe000ed24\r
+#define CYDEV_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28\r
+#define CYDEV_NVIC_BUS_FAULT_STATUS 0xe000ed29\r
+#define CYDEV_NVIC_USAGE_FAULT_STATUS 0xe000ed2a\r
+#define CYDEV_NVIC_HARD_FAULT_STATUS 0xe000ed2c\r
+#define CYDEV_NVIC_DEBUG_FAULT_STATUS 0xe000ed30\r
+#define CYDEV_NVIC_MEMMAN_FAULT_ADD 0xe000ed34\r
+#define CYDEV_NVIC_BUS_FAULT_ADD 0xe000ed38\r
+#define CYDEV_CORE_DBG_BASE 0xe000edf0\r
+#define CYDEV_CORE_DBG_SIZE 0x00000010\r
+#define CYDEV_CORE_DBG_DBG_HLT_CS 0xe000edf0\r
+#define CYDEV_CORE_DBG_DBG_REG_SEL 0xe000edf4\r
+#define CYDEV_CORE_DBG_DBG_REG_DATA 0xe000edf8\r
+#define CYDEV_CORE_DBG_EXC_MON_CTL 0xe000edfc\r
+#define CYDEV_TPIU_BASE 0xe0040000\r
+#define CYDEV_TPIU_SIZE 0x00001000\r
+#define CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000\r
+#define CYDEV_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004\r
+#define CYDEV_TPIU_ASYNC_CLK_PRESCALER 0xe0040010\r
+#define CYDEV_TPIU_PROTOCOL 0xe00400f0\r
+#define CYDEV_TPIU_FORM_FLUSH_STAT 0xe0040300\r
+#define CYDEV_TPIU_FORM_FLUSH_CTRL 0xe0040304\r
+#define CYDEV_TPIU_TRIGGER 0xe0040ee8\r
+#define CYDEV_TPIU_ITETMDATA 0xe0040eec\r
+#define CYDEV_TPIU_ITATBCTR2 0xe0040ef0\r
+#define CYDEV_TPIU_ITATBCTR0 0xe0040ef8\r
+#define CYDEV_TPIU_ITITMDATA 0xe0040efc\r
+#define CYDEV_TPIU_ITCTRL 0xe0040f00\r
+#define CYDEV_TPIU_DEVID 0xe0040fc8\r
+#define CYDEV_TPIU_DEVTYPE 0xe0040fcc\r
+#define CYDEV_TPIU_PID4 0xe0040fd0\r
+#define CYDEV_TPIU_PID5 0xe0040fd4\r
+#define CYDEV_TPIU_PID6 0xe0040fd8\r
+#define CYDEV_TPIU_PID7 0xe0040fdc\r
+#define CYDEV_TPIU_PID0 0xe0040fe0\r
+#define CYDEV_TPIU_PID1 0xe0040fe4\r
+#define CYDEV_TPIU_PID2 0xe0040fe8\r
+#define CYDEV_TPIU_PID3 0xe0040fec\r
+#define CYDEV_TPIU_CID0 0xe0040ff0\r
+#define CYDEV_TPIU_CID1 0xe0040ff4\r
+#define CYDEV_TPIU_CID2 0xe0040ff8\r
+#define CYDEV_TPIU_CID3 0xe0040ffc\r
+#define CYDEV_ETM_BASE 0xe0041000\r
+#define CYDEV_ETM_SIZE 0x00001000\r
+#define CYDEV_ETM_CTL 0xe0041000\r
+#define CYDEV_ETM_CFG_CODE 0xe0041004\r
+#define CYDEV_ETM_TRIG_EVENT 0xe0041008\r
+#define CYDEV_ETM_STATUS 0xe0041010\r
+#define CYDEV_ETM_SYS_CFG 0xe0041014\r
+#define CYDEV_ETM_TRACE_ENB_EVENT 0xe0041020\r
+#define CYDEV_ETM_TRACE_EN_CTRL1 0xe0041024\r
+#define CYDEV_ETM_FIFOFULL_LEVEL 0xe004102c\r
+#define CYDEV_ETM_SYNC_FREQ 0xe00411e0\r
+#define CYDEV_ETM_ETM_ID 0xe00411e4\r
+#define CYDEV_ETM_CFG_CODE_EXT 0xe00411e8\r
+#define CYDEV_ETM_TR_SS_EMBICE_CTRL 0xe00411f0\r
+#define CYDEV_ETM_CS_TRACE_ID 0xe0041200\r
+#define CYDEV_ETM_OS_LOCK_ACCESS 0xe0041300\r
+#define CYDEV_ETM_OS_LOCK_STATUS 0xe0041304\r
+#define CYDEV_ETM_PDSR 0xe0041314\r
+#define CYDEV_ETM_ITMISCIN 0xe0041ee0\r
+#define CYDEV_ETM_ITTRIGOUT 0xe0041ee8\r
+#define CYDEV_ETM_ITATBCTR2 0xe0041ef0\r
+#define CYDEV_ETM_ITATBCTR0 0xe0041ef8\r
+#define CYDEV_ETM_INT_MODE_CTRL 0xe0041f00\r
+#define CYDEV_ETM_CLM_TAG_SET 0xe0041fa0\r
+#define CYDEV_ETM_CLM_TAG_CLR 0xe0041fa4\r
+#define CYDEV_ETM_LOCK_ACCESS 0xe0041fb0\r
+#define CYDEV_ETM_LOCK_STATUS 0xe0041fb4\r
+#define CYDEV_ETM_AUTH_STATUS 0xe0041fb8\r
+#define CYDEV_ETM_DEV_TYPE 0xe0041fcc\r
+#define CYDEV_ETM_PID4 0xe0041fd0\r
+#define CYDEV_ETM_PID5 0xe0041fd4\r
+#define CYDEV_ETM_PID6 0xe0041fd8\r
+#define CYDEV_ETM_PID7 0xe0041fdc\r
+#define CYDEV_ETM_PID0 0xe0041fe0\r
+#define CYDEV_ETM_PID1 0xe0041fe4\r
+#define CYDEV_ETM_PID2 0xe0041fe8\r
+#define CYDEV_ETM_PID3 0xe0041fec\r
+#define CYDEV_ETM_CID0 0xe0041ff0\r
+#define CYDEV_ETM_CID1 0xe0041ff4\r
+#define CYDEV_ETM_CID2 0xe0041ff8\r
+#define CYDEV_ETM_CID3 0xe0041ffc\r
+#define CYDEV_ROM_TABLE_BASE 0xe00ff000\r
+#define CYDEV_ROM_TABLE_SIZE 0x00001000\r
+#define CYDEV_ROM_TABLE_NVIC 0xe00ff000\r
+#define CYDEV_ROM_TABLE_DWT 0xe00ff004\r
+#define CYDEV_ROM_TABLE_FPB 0xe00ff008\r
+#define CYDEV_ROM_TABLE_ITM 0xe00ff00c\r
+#define CYDEV_ROM_TABLE_TPIU 0xe00ff010\r
+#define CYDEV_ROM_TABLE_ETM 0xe00ff014\r
+#define CYDEV_ROM_TABLE_END 0xe00ff018\r
+#define CYDEV_ROM_TABLE_MEMTYPE 0xe00fffcc\r
+#define CYDEV_ROM_TABLE_PID4 0xe00fffd0\r
+#define CYDEV_ROM_TABLE_PID5 0xe00fffd4\r
+#define CYDEV_ROM_TABLE_PID6 0xe00fffd8\r
+#define CYDEV_ROM_TABLE_PID7 0xe00fffdc\r
+#define CYDEV_ROM_TABLE_PID0 0xe00fffe0\r
+#define CYDEV_ROM_TABLE_PID1 0xe00fffe4\r
+#define CYDEV_ROM_TABLE_PID2 0xe00fffe8\r
+#define CYDEV_ROM_TABLE_PID3 0xe00fffec\r
+#define CYDEV_ROM_TABLE_CID0 0xe00ffff0\r
+#define CYDEV_ROM_TABLE_CID1 0xe00ffff4\r
+#define CYDEV_ROM_TABLE_CID2 0xe00ffff8\r
+#define CYDEV_ROM_TABLE_CID3 0xe00ffffc\r
+#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE\r
+#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE\r
+#define CYDEV_FLS_SECTOR_SIZE 0x00010000\r
+#define CYDEV_FLS_ROW_SIZE 0x00000100\r
+#define CYDEV_ECC_SECTOR_SIZE 0x00002000\r
+#define CYDEV_ECC_ROW_SIZE 0x00000020\r
+#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400\r
+#define CYDEV_EEPROM_ROW_SIZE 0x00000010\r
+#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE\r
+#define CYCLK_LD_DISABLE 0x00000004\r
+#define CYCLK_LD_SYNC_EN 0x00000002\r
+#define CYCLK_LD_LOAD 0x00000001\r
+#define CYCLK_PIPE 0x00000080\r
+#define CYCLK_SSS 0x00000040\r
+#define CYCLK_EARLY 0x00000020\r
+#define CYCLK_DUTY 0x00000010\r
+#define CYCLK_SYNC 0x00000008\r
+#define CYCLK_SRC_SEL_CLK_SYNC_D 0\r
+#define CYCLK_SRC_SEL_SYNC_DIG 0\r
+#define CYCLK_SRC_SEL_IMO 1\r
+#define CYCLK_SRC_SEL_XTAL_MHZ 2\r
+#define CYCLK_SRC_SEL_XTALM 2\r
+#define CYCLK_SRC_SEL_ILO 3\r
+#define CYCLK_SRC_SEL_PLL 4\r
+#define CYCLK_SRC_SEL_XTAL_KHZ 5\r
+#define CYCLK_SRC_SEL_XTALK 5\r
+#define CYCLK_SRC_SEL_DSI_G 6\r
+#define CYCLK_SRC_SEL_DSI_D 7\r
+#define CYCLK_SRC_SEL_CLK_SYNC_A 0\r
+#define CYCLK_SRC_SEL_DSI_A 7\r
--- /dev/null
+;\r
+; FILENAME: cydeviceiar_trm.inc\r
+; \r
+; PSoC Creator 3.0\r
+;\r
+; DESCRIPTION:\r
+; This file provides all of the address values for the entire PSoC device.\r
+;\r
+;-------------------------------------------------------------------------------\r
+; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; You may use this file only in accordance with the license, terms, conditions, \r
+; disclaimers, and limitations in the end user license agreement accompanying \r
+; the software package with which this file was provided.\r
+;-------------------------------------------------------------------------------\r
+\r
+#define CYDEV_FLASH_BASE 0x00000000\r
+#define CYDEV_FLASH_SIZE 0x00040000\r
+#define CYREG_FLASH_DATA_MBASE 0x00000000\r
+#define CYREG_FLASH_DATA_MSIZE 0x00040000\r
+#define CYDEV_SRAM_BASE 0x1fff8000\r
+#define CYDEV_SRAM_SIZE 0x00010000\r
+#define CYREG_SRAM_CODE64K_MBASE 0x1fff8000\r
+#define CYREG_SRAM_CODE64K_MSIZE 0x00004000\r
+#define CYREG_SRAM_CODE32K_MBASE 0x1fffc000\r
+#define CYREG_SRAM_CODE32K_MSIZE 0x00002000\r
+#define CYREG_SRAM_CODE16K_MBASE 0x1fffe000\r
+#define CYREG_SRAM_CODE16K_MSIZE 0x00001000\r
+#define CYREG_SRAM_CODE_MBASE 0x1fff8000\r
+#define CYREG_SRAM_CODE_MSIZE 0x00008000\r
+#define CYREG_SRAM_DATA_MBASE 0x20000000\r
+#define CYREG_SRAM_DATA_MSIZE 0x00008000\r
+#define CYREG_SRAM_DATA16K_MBASE 0x20001000\r
+#define CYREG_SRAM_DATA16K_MSIZE 0x00001000\r
+#define CYREG_SRAM_DATA32K_MBASE 0x20002000\r
+#define CYREG_SRAM_DATA32K_MSIZE 0x00002000\r
+#define CYREG_SRAM_DATA64K_MBASE 0x20004000\r
+#define CYREG_SRAM_DATA64K_MSIZE 0x00004000\r
+#define CYDEV_DMA_BASE 0x20008000\r
+#define CYDEV_DMA_SIZE 0x00008000\r
+#define CYREG_DMA_SRAM64K_MBASE 0x20008000\r
+#define CYREG_DMA_SRAM64K_MSIZE 0x00004000\r
+#define CYREG_DMA_SRAM32K_MBASE 0x2000c000\r
+#define CYREG_DMA_SRAM32K_MSIZE 0x00002000\r
+#define CYREG_DMA_SRAM16K_MBASE 0x2000e000\r
+#define CYREG_DMA_SRAM16K_MSIZE 0x00001000\r
+#define CYREG_DMA_SRAM_MBASE 0x2000f000\r
+#define CYREG_DMA_SRAM_MSIZE 0x00001000\r
+#define CYDEV_CLKDIST_BASE 0x40004000\r
+#define CYDEV_CLKDIST_SIZE 0x00000110\r
+#define CYREG_CLKDIST_CR 0x40004000\r
+#define CYREG_CLKDIST_LD 0x40004001\r
+#define CYREG_CLKDIST_WRK0 0x40004002\r
+#define CYREG_CLKDIST_WRK1 0x40004003\r
+#define CYREG_CLKDIST_MSTR0 0x40004004\r
+#define CYREG_CLKDIST_MSTR1 0x40004005\r
+#define CYREG_CLKDIST_BCFG0 0x40004006\r
+#define CYREG_CLKDIST_BCFG1 0x40004007\r
+#define CYREG_CLKDIST_BCFG2 0x40004008\r
+#define CYREG_CLKDIST_UCFG 0x40004009\r
+#define CYREG_CLKDIST_DLY0 0x4000400a\r
+#define CYREG_CLKDIST_DLY1 0x4000400b\r
+#define CYREG_CLKDIST_DMASK 0x40004010\r
+#define CYREG_CLKDIST_AMASK 0x40004014\r
+#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080\r
+#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003\r
+#define CYREG_CLKDIST_DCFG0_CFG0 0x40004080\r
+#define CYREG_CLKDIST_DCFG0_CFG1 0x40004081\r
+#define CYREG_CLKDIST_DCFG0_CFG2 0x40004082\r
+#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084\r
+#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003\r
+#define CYREG_CLKDIST_DCFG1_CFG0 0x40004084\r
+#define CYREG_CLKDIST_DCFG1_CFG1 0x40004085\r
+#define CYREG_CLKDIST_DCFG1_CFG2 0x40004086\r
+#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088\r
+#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003\r
+#define CYREG_CLKDIST_DCFG2_CFG0 0x40004088\r
+#define CYREG_CLKDIST_DCFG2_CFG1 0x40004089\r
+#define CYREG_CLKDIST_DCFG2_CFG2 0x4000408a\r
+#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408c\r
+#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003\r
+#define CYREG_CLKDIST_DCFG3_CFG0 0x4000408c\r
+#define CYREG_CLKDIST_DCFG3_CFG1 0x4000408d\r
+#define CYREG_CLKDIST_DCFG3_CFG2 0x4000408e\r
+#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090\r
+#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003\r
+#define CYREG_CLKDIST_DCFG4_CFG0 0x40004090\r
+#define CYREG_CLKDIST_DCFG4_CFG1 0x40004091\r
+#define CYREG_CLKDIST_DCFG4_CFG2 0x40004092\r
+#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094\r
+#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003\r
+#define CYREG_CLKDIST_DCFG5_CFG0 0x40004094\r
+#define CYREG_CLKDIST_DCFG5_CFG1 0x40004095\r
+#define CYREG_CLKDIST_DCFG5_CFG2 0x40004096\r
+#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098\r
+#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003\r
+#define CYREG_CLKDIST_DCFG6_CFG0 0x40004098\r
+#define CYREG_CLKDIST_DCFG6_CFG1 0x40004099\r
+#define CYREG_CLKDIST_DCFG6_CFG2 0x4000409a\r
+#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409c\r
+#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003\r
+#define CYREG_CLKDIST_DCFG7_CFG0 0x4000409c\r
+#define CYREG_CLKDIST_DCFG7_CFG1 0x4000409d\r
+#define CYREG_CLKDIST_DCFG7_CFG2 0x4000409e\r
+#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100\r
+#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004\r
+#define CYREG_CLKDIST_ACFG0_CFG0 0x40004100\r
+#define CYREG_CLKDIST_ACFG0_CFG1 0x40004101\r
+#define CYREG_CLKDIST_ACFG0_CFG2 0x40004102\r
+#define CYREG_CLKDIST_ACFG0_CFG3 0x40004103\r
+#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104\r
+#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004\r
+#define CYREG_CLKDIST_ACFG1_CFG0 0x40004104\r
+#define CYREG_CLKDIST_ACFG1_CFG1 0x40004105\r
+#define CYREG_CLKDIST_ACFG1_CFG2 0x40004106\r
+#define CYREG_CLKDIST_ACFG1_CFG3 0x40004107\r
+#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108\r
+#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004\r
+#define CYREG_CLKDIST_ACFG2_CFG0 0x40004108\r
+#define CYREG_CLKDIST_ACFG2_CFG1 0x40004109\r
+#define CYREG_CLKDIST_ACFG2_CFG2 0x4000410a\r
+#define CYREG_CLKDIST_ACFG2_CFG3 0x4000410b\r
+#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410c\r
+#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004\r
+#define CYREG_CLKDIST_ACFG3_CFG0 0x4000410c\r
+#define CYREG_CLKDIST_ACFG3_CFG1 0x4000410d\r
+#define CYREG_CLKDIST_ACFG3_CFG2 0x4000410e\r
+#define CYREG_CLKDIST_ACFG3_CFG3 0x4000410f\r
+#define CYDEV_FASTCLK_BASE 0x40004200\r
+#define CYDEV_FASTCLK_SIZE 0x00000026\r
+#define CYDEV_FASTCLK_IMO_BASE 0x40004200\r
+#define CYDEV_FASTCLK_IMO_SIZE 0x00000001\r
+#define CYREG_FASTCLK_IMO_CR 0x40004200\r
+#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210\r
+#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004\r
+#define CYREG_FASTCLK_XMHZ_CSR 0x40004210\r
+#define CYREG_FASTCLK_XMHZ_CFG0 0x40004212\r
+#define CYREG_FASTCLK_XMHZ_CFG1 0x40004213\r
+#define CYDEV_FASTCLK_PLL_BASE 0x40004220\r
+#define CYDEV_FASTCLK_PLL_SIZE 0x00000006\r
+#define CYREG_FASTCLK_PLL_CFG0 0x40004220\r
+#define CYREG_FASTCLK_PLL_CFG1 0x40004221\r
+#define CYREG_FASTCLK_PLL_P 0x40004222\r
+#define CYREG_FASTCLK_PLL_Q 0x40004223\r
+#define CYREG_FASTCLK_PLL_SR 0x40004225\r
+#define CYDEV_SLOWCLK_BASE 0x40004300\r
+#define CYDEV_SLOWCLK_SIZE 0x0000000b\r
+#define CYDEV_SLOWCLK_ILO_BASE 0x40004300\r
+#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002\r
+#define CYREG_SLOWCLK_ILO_CR0 0x40004300\r
+#define CYREG_SLOWCLK_ILO_CR1 0x40004301\r
+#define CYDEV_SLOWCLK_X32_BASE 0x40004308\r
+#define CYDEV_SLOWCLK_X32_SIZE 0x00000003\r
+#define CYREG_SLOWCLK_X32_CR 0x40004308\r
+#define CYREG_SLOWCLK_X32_CFG 0x40004309\r
+#define CYREG_SLOWCLK_X32_TST 0x4000430a\r
+#define CYDEV_BOOST_BASE 0x40004320\r
+#define CYDEV_BOOST_SIZE 0x00000007\r
+#define CYREG_BOOST_CR0 0x40004320\r
+#define CYREG_BOOST_CR1 0x40004321\r
+#define CYREG_BOOST_CR2 0x40004322\r
+#define CYREG_BOOST_CR3 0x40004323\r
+#define CYREG_BOOST_SR 0x40004324\r
+#define CYREG_BOOST_CR4 0x40004325\r
+#define CYREG_BOOST_SR2 0x40004326\r
+#define CYDEV_PWRSYS_BASE 0x40004330\r
+#define CYDEV_PWRSYS_SIZE 0x00000002\r
+#define CYREG_PWRSYS_CR0 0x40004330\r
+#define CYREG_PWRSYS_CR1 0x40004331\r
+#define CYDEV_PM_BASE 0x40004380\r
+#define CYDEV_PM_SIZE 0x00000057\r
+#define CYREG_PM_TW_CFG0 0x40004380\r
+#define CYREG_PM_TW_CFG1 0x40004381\r
+#define CYREG_PM_TW_CFG2 0x40004382\r
+#define CYREG_PM_WDT_CFG 0x40004383\r
+#define CYREG_PM_WDT_CR 0x40004384\r
+#define CYREG_PM_INT_SR 0x40004390\r
+#define CYREG_PM_MODE_CFG0 0x40004391\r
+#define CYREG_PM_MODE_CFG1 0x40004392\r
+#define CYREG_PM_MODE_CSR 0x40004393\r
+#define CYREG_PM_USB_CR0 0x40004394\r
+#define CYREG_PM_WAKEUP_CFG0 0x40004398\r
+#define CYREG_PM_WAKEUP_CFG1 0x40004399\r
+#define CYREG_PM_WAKEUP_CFG2 0x4000439a\r
+#define CYDEV_PM_ACT_BASE 0x400043a0\r
+#define CYDEV_PM_ACT_SIZE 0x0000000e\r
+#define CYREG_PM_ACT_CFG0 0x400043a0\r
+#define CYREG_PM_ACT_CFG1 0x400043a1\r
+#define CYREG_PM_ACT_CFG2 0x400043a2\r
+#define CYREG_PM_ACT_CFG3 0x400043a3\r
+#define CYREG_PM_ACT_CFG4 0x400043a4\r
+#define CYREG_PM_ACT_CFG5 0x400043a5\r
+#define CYREG_PM_ACT_CFG6 0x400043a6\r
+#define CYREG_PM_ACT_CFG7 0x400043a7\r
+#define CYREG_PM_ACT_CFG8 0x400043a8\r
+#define CYREG_PM_ACT_CFG9 0x400043a9\r
+#define CYREG_PM_ACT_CFG10 0x400043aa\r
+#define CYREG_PM_ACT_CFG11 0x400043ab\r
+#define CYREG_PM_ACT_CFG12 0x400043ac\r
+#define CYREG_PM_ACT_CFG13 0x400043ad\r
+#define CYDEV_PM_STBY_BASE 0x400043b0\r
+#define CYDEV_PM_STBY_SIZE 0x0000000e\r
+#define CYREG_PM_STBY_CFG0 0x400043b0\r
+#define CYREG_PM_STBY_CFG1 0x400043b1\r
+#define CYREG_PM_STBY_CFG2 0x400043b2\r
+#define CYREG_PM_STBY_CFG3 0x400043b3\r
+#define CYREG_PM_STBY_CFG4 0x400043b4\r
+#define CYREG_PM_STBY_CFG5 0x400043b5\r
+#define CYREG_PM_STBY_CFG6 0x400043b6\r
+#define CYREG_PM_STBY_CFG7 0x400043b7\r
+#define CYREG_PM_STBY_CFG8 0x400043b8\r
+#define CYREG_PM_STBY_CFG9 0x400043b9\r
+#define CYREG_PM_STBY_CFG10 0x400043ba\r
+#define CYREG_PM_STBY_CFG11 0x400043bb\r
+#define CYREG_PM_STBY_CFG12 0x400043bc\r
+#define CYREG_PM_STBY_CFG13 0x400043bd\r
+#define CYDEV_PM_AVAIL_BASE 0x400043c0\r
+#define CYDEV_PM_AVAIL_SIZE 0x00000017\r
+#define CYREG_PM_AVAIL_CR0 0x400043c0\r
+#define CYREG_PM_AVAIL_CR1 0x400043c1\r
+#define CYREG_PM_AVAIL_CR2 0x400043c2\r
+#define CYREG_PM_AVAIL_CR3 0x400043c3\r
+#define CYREG_PM_AVAIL_CR4 0x400043c4\r
+#define CYREG_PM_AVAIL_CR5 0x400043c5\r
+#define CYREG_PM_AVAIL_CR6 0x400043c6\r
+#define CYREG_PM_AVAIL_SR0 0x400043d0\r
+#define CYREG_PM_AVAIL_SR1 0x400043d1\r
+#define CYREG_PM_AVAIL_SR2 0x400043d2\r
+#define CYREG_PM_AVAIL_SR3 0x400043d3\r
+#define CYREG_PM_AVAIL_SR4 0x400043d4\r
+#define CYREG_PM_AVAIL_SR5 0x400043d5\r
+#define CYREG_PM_AVAIL_SR6 0x400043d6\r
+#define CYDEV_PICU_BASE 0x40004500\r
+#define CYDEV_PICU_SIZE 0x000000b0\r
+#define CYDEV_PICU_INTTYPE_BASE 0x40004500\r
+#define CYDEV_PICU_INTTYPE_SIZE 0x00000080\r
+#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500\r
+#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008\r
+#define CYREG_PICU0_INTTYPE0 0x40004500\r
+#define CYREG_PICU0_INTTYPE1 0x40004501\r
+#define CYREG_PICU0_INTTYPE2 0x40004502\r
+#define CYREG_PICU0_INTTYPE3 0x40004503\r
+#define CYREG_PICU0_INTTYPE4 0x40004504\r
+#define CYREG_PICU0_INTTYPE5 0x40004505\r
+#define CYREG_PICU0_INTTYPE6 0x40004506\r
+#define CYREG_PICU0_INTTYPE7 0x40004507\r
+#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508\r
+#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008\r
+#define CYREG_PICU1_INTTYPE0 0x40004508\r
+#define CYREG_PICU1_INTTYPE1 0x40004509\r
+#define CYREG_PICU1_INTTYPE2 0x4000450a\r
+#define CYREG_PICU1_INTTYPE3 0x4000450b\r
+#define CYREG_PICU1_INTTYPE4 0x4000450c\r
+#define CYREG_PICU1_INTTYPE5 0x4000450d\r
+#define CYREG_PICU1_INTTYPE6 0x4000450e\r
+#define CYREG_PICU1_INTTYPE7 0x4000450f\r
+#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510\r
+#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008\r
+#define CYREG_PICU2_INTTYPE0 0x40004510\r
+#define CYREG_PICU2_INTTYPE1 0x40004511\r
+#define CYREG_PICU2_INTTYPE2 0x40004512\r
+#define CYREG_PICU2_INTTYPE3 0x40004513\r
+#define CYREG_PICU2_INTTYPE4 0x40004514\r
+#define CYREG_PICU2_INTTYPE5 0x40004515\r
+#define CYREG_PICU2_INTTYPE6 0x40004516\r
+#define CYREG_PICU2_INTTYPE7 0x40004517\r
+#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518\r
+#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008\r
+#define CYREG_PICU3_INTTYPE0 0x40004518\r
+#define CYREG_PICU3_INTTYPE1 0x40004519\r
+#define CYREG_PICU3_INTTYPE2 0x4000451a\r
+#define CYREG_PICU3_INTTYPE3 0x4000451b\r
+#define CYREG_PICU3_INTTYPE4 0x4000451c\r
+#define CYREG_PICU3_INTTYPE5 0x4000451d\r
+#define CYREG_PICU3_INTTYPE6 0x4000451e\r
+#define CYREG_PICU3_INTTYPE7 0x4000451f\r
+#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520\r
+#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008\r
+#define CYREG_PICU4_INTTYPE0 0x40004520\r
+#define CYREG_PICU4_INTTYPE1 0x40004521\r
+#define CYREG_PICU4_INTTYPE2 0x40004522\r
+#define CYREG_PICU4_INTTYPE3 0x40004523\r
+#define CYREG_PICU4_INTTYPE4 0x40004524\r
+#define CYREG_PICU4_INTTYPE5 0x40004525\r
+#define CYREG_PICU4_INTTYPE6 0x40004526\r
+#define CYREG_PICU4_INTTYPE7 0x40004527\r
+#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528\r
+#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008\r
+#define CYREG_PICU5_INTTYPE0 0x40004528\r
+#define CYREG_PICU5_INTTYPE1 0x40004529\r
+#define CYREG_PICU5_INTTYPE2 0x4000452a\r
+#define CYREG_PICU5_INTTYPE3 0x4000452b\r
+#define CYREG_PICU5_INTTYPE4 0x4000452c\r
+#define CYREG_PICU5_INTTYPE5 0x4000452d\r
+#define CYREG_PICU5_INTTYPE6 0x4000452e\r
+#define CYREG_PICU5_INTTYPE7 0x4000452f\r
+#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530\r
+#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008\r
+#define CYREG_PICU6_INTTYPE0 0x40004530\r
+#define CYREG_PICU6_INTTYPE1 0x40004531\r
+#define CYREG_PICU6_INTTYPE2 0x40004532\r
+#define CYREG_PICU6_INTTYPE3 0x40004533\r
+#define CYREG_PICU6_INTTYPE4 0x40004534\r
+#define CYREG_PICU6_INTTYPE5 0x40004535\r
+#define CYREG_PICU6_INTTYPE6 0x40004536\r
+#define CYREG_PICU6_INTTYPE7 0x40004537\r
+#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560\r
+#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008\r
+#define CYREG_PICU12_INTTYPE0 0x40004560\r
+#define CYREG_PICU12_INTTYPE1 0x40004561\r
+#define CYREG_PICU12_INTTYPE2 0x40004562\r
+#define CYREG_PICU12_INTTYPE3 0x40004563\r
+#define CYREG_PICU12_INTTYPE4 0x40004564\r
+#define CYREG_PICU12_INTTYPE5 0x40004565\r
+#define CYREG_PICU12_INTTYPE6 0x40004566\r
+#define CYREG_PICU12_INTTYPE7 0x40004567\r
+#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578\r
+#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008\r
+#define CYREG_PICU15_INTTYPE0 0x40004578\r
+#define CYREG_PICU15_INTTYPE1 0x40004579\r
+#define CYREG_PICU15_INTTYPE2 0x4000457a\r
+#define CYREG_PICU15_INTTYPE3 0x4000457b\r
+#define CYREG_PICU15_INTTYPE4 0x4000457c\r
+#define CYREG_PICU15_INTTYPE5 0x4000457d\r
+#define CYREG_PICU15_INTTYPE6 0x4000457e\r
+#define CYREG_PICU15_INTTYPE7 0x4000457f\r
+#define CYDEV_PICU_STAT_BASE 0x40004580\r
+#define CYDEV_PICU_STAT_SIZE 0x00000010\r
+#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580\r
+#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001\r
+#define CYREG_PICU0_INTSTAT 0x40004580\r
+#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581\r
+#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001\r
+#define CYREG_PICU1_INTSTAT 0x40004581\r
+#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582\r
+#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001\r
+#define CYREG_PICU2_INTSTAT 0x40004582\r
+#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583\r
+#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001\r
+#define CYREG_PICU3_INTSTAT 0x40004583\r
+#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584\r
+#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001\r
+#define CYREG_PICU4_INTSTAT 0x40004584\r
+#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585\r
+#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001\r
+#define CYREG_PICU5_INTSTAT 0x40004585\r
+#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586\r
+#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001\r
+#define CYREG_PICU6_INTSTAT 0x40004586\r
+#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458c\r
+#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001\r
+#define CYREG_PICU12_INTSTAT 0x4000458c\r
+#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458f\r
+#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001\r
+#define CYREG_PICU15_INTSTAT 0x4000458f\r
+#define CYDEV_PICU_SNAP_BASE 0x40004590\r
+#define CYDEV_PICU_SNAP_SIZE 0x00000010\r
+#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590\r
+#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001\r
+#define CYREG_PICU0_SNAP 0x40004590\r
+#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591\r
+#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001\r
+#define CYREG_PICU1_SNAP 0x40004591\r
+#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592\r
+#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001\r
+#define CYREG_PICU2_SNAP 0x40004592\r
+#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593\r
+#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001\r
+#define CYREG_PICU3_SNAP 0x40004593\r
+#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594\r
+#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001\r
+#define CYREG_PICU4_SNAP 0x40004594\r
+#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595\r
+#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001\r
+#define CYREG_PICU5_SNAP 0x40004595\r
+#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596\r
+#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001\r
+#define CYREG_PICU6_SNAP 0x40004596\r
+#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459c\r
+#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001\r
+#define CYREG_PICU12_SNAP 0x4000459c\r
+#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459f\r
+#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001\r
+#define CYREG_PICU_15_SNAP_15 0x4000459f\r
+#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0\r
+#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010\r
+#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0\r
+#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001\r
+#define CYREG_PICU0_DISABLE_COR 0x400045a0\r
+#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1\r
+#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001\r
+#define CYREG_PICU1_DISABLE_COR 0x400045a1\r
+#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2\r
+#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001\r
+#define CYREG_PICU2_DISABLE_COR 0x400045a2\r
+#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3\r
+#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001\r
+#define CYREG_PICU3_DISABLE_COR 0x400045a3\r
+#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4\r
+#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001\r
+#define CYREG_PICU4_DISABLE_COR 0x400045a4\r
+#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5\r
+#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001\r
+#define CYREG_PICU5_DISABLE_COR 0x400045a5\r
+#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6\r
+#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001\r
+#define CYREG_PICU6_DISABLE_COR 0x400045a6\r
+#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045ac\r
+#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001\r
+#define CYREG_PICU12_DISABLE_COR 0x400045ac\r
+#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045af\r
+#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001\r
+#define CYREG_PICU15_DISABLE_COR 0x400045af\r
+#define CYDEV_MFGCFG_BASE 0x40004600\r
+#define CYDEV_MFGCFG_SIZE 0x000000ed\r
+#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600\r
+#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038\r
+#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608\r
+#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001\r
+#define CYREG_DAC0_TR 0x40004608\r
+#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609\r
+#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001\r
+#define CYREG_DAC1_TR 0x40004609\r
+#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460a\r
+#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001\r
+#define CYREG_DAC2_TR 0x4000460a\r
+#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460b\r
+#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001\r
+#define CYREG_DAC3_TR 0x4000460b\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001\r
+#define CYREG_NPUMP_DSM_TR0 0x40004610\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001\r
+#define CYREG_NPUMP_SC_TR0 0x40004611\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001\r
+#define CYREG_NPUMP_OPAMP_TR0 0x40004612\r
+#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614\r
+#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001\r
+#define CYREG_SAR0_TR0 0x40004614\r
+#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616\r
+#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001\r
+#define CYREG_SAR1_TR0 0x40004616\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002\r
+#define CYREG_OPAMP0_TR0 0x40004620\r
+#define CYREG_OPAMP0_TR1 0x40004621\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002\r
+#define CYREG_OPAMP1_TR0 0x40004622\r
+#define CYREG_OPAMP1_TR1 0x40004623\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002\r
+#define CYREG_OPAMP2_TR0 0x40004624\r
+#define CYREG_OPAMP2_TR1 0x40004625\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002\r
+#define CYREG_OPAMP3_TR0 0x40004626\r
+#define CYREG_OPAMP3_TR1 0x40004627\r
+#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630\r
+#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002\r
+#define CYREG_CMP0_TR0 0x40004630\r
+#define CYREG_CMP0_TR1 0x40004631\r
+#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632\r
+#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002\r
+#define CYREG_CMP1_TR0 0x40004632\r
+#define CYREG_CMP1_TR1 0x40004633\r
+#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634\r
+#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002\r
+#define CYREG_CMP2_TR0 0x40004634\r
+#define CYREG_CMP2_TR1 0x40004635\r
+#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636\r
+#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002\r
+#define CYREG_CMP3_TR0 0x40004636\r
+#define CYREG_CMP3_TR1 0x40004637\r
+#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680\r
+#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000b\r
+#define CYREG_PWRSYS_HIB_TR0 0x40004680\r
+#define CYREG_PWRSYS_HIB_TR1 0x40004681\r
+#define CYREG_PWRSYS_I2C_TR 0x40004682\r
+#define CYREG_PWRSYS_SLP_TR 0x40004683\r
+#define CYREG_PWRSYS_BUZZ_TR 0x40004684\r
+#define CYREG_PWRSYS_WAKE_TR0 0x40004685\r
+#define CYREG_PWRSYS_WAKE_TR1 0x40004686\r
+#define CYREG_PWRSYS_BREF_TR 0x40004687\r
+#define CYREG_PWRSYS_BG_TR 0x40004688\r
+#define CYREG_PWRSYS_WAKE_TR2 0x40004689\r
+#define CYREG_PWRSYS_WAKE_TR3 0x4000468a\r
+#define CYDEV_MFGCFG_ILO_BASE 0x40004690\r
+#define CYDEV_MFGCFG_ILO_SIZE 0x00000002\r
+#define CYREG_ILO_TR0 0x40004690\r
+#define CYREG_ILO_TR1 0x40004691\r
+#define CYDEV_MFGCFG_X32_BASE 0x40004698\r
+#define CYDEV_MFGCFG_X32_SIZE 0x00000001\r
+#define CYREG_X32_TR 0x40004698\r
+#define CYDEV_MFGCFG_IMO_BASE 0x400046a0\r
+#define CYDEV_MFGCFG_IMO_SIZE 0x00000005\r
+#define CYREG_IMO_TR0 0x400046a0\r
+#define CYREG_IMO_TR1 0x400046a1\r
+#define CYREG_IMO_GAIN 0x400046a2\r
+#define CYREG_IMO_C36M 0x400046a3\r
+#define CYREG_IMO_TR2 0x400046a4\r
+#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8\r
+#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001\r
+#define CYREG_XMHZ_TR 0x400046a8\r
+#define CYREG_MFGCFG_DLY 0x400046c0\r
+#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0\r
+#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000d\r
+#define CYREG_MLOGIC_DMPSTR 0x400046e2\r
+#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4\r
+#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002\r
+#define CYREG_MLOGIC_SEG_CR 0x400046e4\r
+#define CYREG_MLOGIC_SEG_CFG0 0x400046e5\r
+#define CYREG_MLOGIC_DEBUG 0x400046e8\r
+#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046ea\r
+#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001\r
+#define CYREG_MLOGIC_CPU_SCR_CPU_SCR 0x400046ea\r
+#define CYREG_MLOGIC_REV_ID 0x400046ec\r
+#define CYDEV_RESET_BASE 0x400046f0\r
+#define CYDEV_RESET_SIZE 0x0000000f\r
+#define CYREG_RESET_IPOR_CR0 0x400046f0\r
+#define CYREG_RESET_IPOR_CR1 0x400046f1\r
+#define CYREG_RESET_IPOR_CR2 0x400046f2\r
+#define CYREG_RESET_IPOR_CR3 0x400046f3\r
+#define CYREG_RESET_CR0 0x400046f4\r
+#define CYREG_RESET_CR1 0x400046f5\r
+#define CYREG_RESET_CR2 0x400046f6\r
+#define CYREG_RESET_CR3 0x400046f7\r
+#define CYREG_RESET_CR4 0x400046f8\r
+#define CYREG_RESET_CR5 0x400046f9\r
+#define CYREG_RESET_SR0 0x400046fa\r
+#define CYREG_RESET_SR1 0x400046fb\r
+#define CYREG_RESET_SR2 0x400046fc\r
+#define CYREG_RESET_SR3 0x400046fd\r
+#define CYREG_RESET_TR 0x400046fe\r
+#define CYDEV_SPC_BASE 0x40004700\r
+#define CYDEV_SPC_SIZE 0x00000100\r
+#define CYREG_SPC_FM_EE_CR 0x40004700\r
+#define CYREG_SPC_FM_EE_WAKE_CNT 0x40004701\r
+#define CYREG_SPC_EE_SCR 0x40004702\r
+#define CYREG_SPC_EE_ERR 0x40004703\r
+#define CYREG_SPC_CPU_DATA 0x40004720\r
+#define CYREG_SPC_DMA_DATA 0x40004721\r
+#define CYREG_SPC_SR 0x40004722\r
+#define CYREG_SPC_CR 0x40004723\r
+#define CYDEV_SPC_DMM_MAP_BASE 0x40004780\r
+#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080\r
+#define CYREG_SPC_DMM_MAP_SRAM_MBASE 0x40004780\r
+#define CYREG_SPC_DMM_MAP_SRAM_MSIZE 0x00000080\r
+#define CYDEV_CACHE_BASE 0x40004800\r
+#define CYDEV_CACHE_SIZE 0x0000009c\r
+#define CYREG_CACHE_CC_CTL 0x40004800\r
+#define CYREG_CACHE_ECC_CORR 0x40004880\r
+#define CYREG_CACHE_ECC_ERR 0x40004888\r
+#define CYREG_CACHE_FLASH_ERR 0x40004890\r
+#define CYREG_CACHE_HITMISS 0x40004898\r
+#define CYDEV_I2C_BASE 0x40004900\r
+#define CYDEV_I2C_SIZE 0x000000e1\r
+#define CYREG_I2C_XCFG 0x400049c8\r
+#define CYREG_I2C_ADR 0x400049ca\r
+#define CYREG_I2C_CFG 0x400049d6\r
+#define CYREG_I2C_CSR 0x400049d7\r
+#define CYREG_I2C_D 0x400049d8\r
+#define CYREG_I2C_MCSR 0x400049d9\r
+#define CYREG_I2C_CLK_DIV1 0x400049db\r
+#define CYREG_I2C_CLK_DIV2 0x400049dc\r
+#define CYREG_I2C_TMOUT_CSR 0x400049dd\r
+#define CYREG_I2C_TMOUT_SR 0x400049de\r
+#define CYREG_I2C_TMOUT_CFG0 0x400049df\r
+#define CYREG_I2C_TMOUT_CFG1 0x400049e0\r
+#define CYDEV_DEC_BASE 0x40004e00\r
+#define CYDEV_DEC_SIZE 0x00000015\r
+#define CYREG_DEC_CR 0x40004e00\r
+#define CYREG_DEC_SR 0x40004e01\r
+#define CYREG_DEC_SHIFT1 0x40004e02\r
+#define CYREG_DEC_SHIFT2 0x40004e03\r
+#define CYREG_DEC_DR2 0x40004e04\r
+#define CYREG_DEC_DR2H 0x40004e05\r
+#define CYREG_DEC_DR1 0x40004e06\r
+#define CYREG_DEC_OCOR 0x40004e08\r
+#define CYREG_DEC_OCORM 0x40004e09\r
+#define CYREG_DEC_OCORH 0x40004e0a\r
+#define CYREG_DEC_GCOR 0x40004e0c\r
+#define CYREG_DEC_GCORH 0x40004e0d\r
+#define CYREG_DEC_GVAL 0x40004e0e\r
+#define CYREG_DEC_OUTSAMP 0x40004e10\r
+#define CYREG_DEC_OUTSAMPM 0x40004e11\r
+#define CYREG_DEC_OUTSAMPH 0x40004e12\r
+#define CYREG_DEC_OUTSAMPS 0x40004e13\r
+#define CYREG_DEC_COHER 0x40004e14\r
+#define CYDEV_TMR0_BASE 0x40004f00\r
+#define CYDEV_TMR0_SIZE 0x0000000c\r
+#define CYREG_TMR0_CFG0 0x40004f00\r
+#define CYREG_TMR0_CFG1 0x40004f01\r
+#define CYREG_TMR0_CFG2 0x40004f02\r
+#define CYREG_TMR0_SR0 0x40004f03\r
+#define CYREG_TMR0_PER0 0x40004f04\r
+#define CYREG_TMR0_PER1 0x40004f05\r
+#define CYREG_TMR0_CNT_CMP0 0x40004f06\r
+#define CYREG_TMR0_CNT_CMP1 0x40004f07\r
+#define CYREG_TMR0_CAP0 0x40004f08\r
+#define CYREG_TMR0_CAP1 0x40004f09\r
+#define CYREG_TMR0_RT0 0x40004f0a\r
+#define CYREG_TMR0_RT1 0x40004f0b\r
+#define CYDEV_TMR1_BASE 0x40004f0c\r
+#define CYDEV_TMR1_SIZE 0x0000000c\r
+#define CYREG_TMR1_CFG0 0x40004f0c\r
+#define CYREG_TMR1_CFG1 0x40004f0d\r
+#define CYREG_TMR1_CFG2 0x40004f0e\r
+#define CYREG_TMR1_SR0 0x40004f0f\r
+#define CYREG_TMR1_PER0 0x40004f10\r
+#define CYREG_TMR1_PER1 0x40004f11\r
+#define CYREG_TMR1_CNT_CMP0 0x40004f12\r
+#define CYREG_TMR1_CNT_CMP1 0x40004f13\r
+#define CYREG_TMR1_CAP0 0x40004f14\r
+#define CYREG_TMR1_CAP1 0x40004f15\r
+#define CYREG_TMR1_RT0 0x40004f16\r
+#define CYREG_TMR1_RT1 0x40004f17\r
+#define CYDEV_TMR2_BASE 0x40004f18\r
+#define CYDEV_TMR2_SIZE 0x0000000c\r
+#define CYREG_TMR2_CFG0 0x40004f18\r
+#define CYREG_TMR2_CFG1 0x40004f19\r
+#define CYREG_TMR2_CFG2 0x40004f1a\r
+#define CYREG_TMR2_SR0 0x40004f1b\r
+#define CYREG_TMR2_PER0 0x40004f1c\r
+#define CYREG_TMR2_PER1 0x40004f1d\r
+#define CYREG_TMR2_CNT_CMP0 0x40004f1e\r
+#define CYREG_TMR2_CNT_CMP1 0x40004f1f\r
+#define CYREG_TMR2_CAP0 0x40004f20\r
+#define CYREG_TMR2_CAP1 0x40004f21\r
+#define CYREG_TMR2_RT0 0x40004f22\r
+#define CYREG_TMR2_RT1 0x40004f23\r
+#define CYDEV_TMR3_BASE 0x40004f24\r
+#define CYDEV_TMR3_SIZE 0x0000000c\r
+#define CYREG_TMR3_CFG0 0x40004f24\r
+#define CYREG_TMR3_CFG1 0x40004f25\r
+#define CYREG_TMR3_CFG2 0x40004f26\r
+#define CYREG_TMR3_SR0 0x40004f27\r
+#define CYREG_TMR3_PER0 0x40004f28\r
+#define CYREG_TMR3_PER1 0x40004f29\r
+#define CYREG_TMR3_CNT_CMP0 0x40004f2a\r
+#define CYREG_TMR3_CNT_CMP1 0x40004f2b\r
+#define CYREG_TMR3_CAP0 0x40004f2c\r
+#define CYREG_TMR3_CAP1 0x40004f2d\r
+#define CYREG_TMR3_RT0 0x40004f2e\r
+#define CYREG_TMR3_RT1 0x40004f2f\r
+#define CYDEV_IO_BASE 0x40005000\r
+#define CYDEV_IO_SIZE 0x00000200\r
+#define CYDEV_IO_PC_BASE 0x40005000\r
+#define CYDEV_IO_PC_SIZE 0x00000080\r
+#define CYDEV_IO_PC_PRT0_BASE 0x40005000\r
+#define CYDEV_IO_PC_PRT0_SIZE 0x00000008\r
+#define CYREG_PRT0_PC0 0x40005000\r
+#define CYREG_PRT0_PC1 0x40005001\r
+#define CYREG_PRT0_PC2 0x40005002\r
+#define CYREG_PRT0_PC3 0x40005003\r
+#define CYREG_PRT0_PC4 0x40005004\r
+#define CYREG_PRT0_PC5 0x40005005\r
+#define CYREG_PRT0_PC6 0x40005006\r
+#define CYREG_PRT0_PC7 0x40005007\r
+#define CYDEV_IO_PC_PRT1_BASE 0x40005008\r
+#define CYDEV_IO_PC_PRT1_SIZE 0x00000008\r
+#define CYREG_PRT1_PC0 0x40005008\r
+#define CYREG_PRT1_PC1 0x40005009\r
+#define CYREG_PRT1_PC2 0x4000500a\r
+#define CYREG_PRT1_PC3 0x4000500b\r
+#define CYREG_PRT1_PC4 0x4000500c\r
+#define CYREG_PRT1_PC5 0x4000500d\r
+#define CYREG_PRT1_PC6 0x4000500e\r
+#define CYREG_PRT1_PC7 0x4000500f\r
+#define CYDEV_IO_PC_PRT2_BASE 0x40005010\r
+#define CYDEV_IO_PC_PRT2_SIZE 0x00000008\r
+#define CYREG_PRT2_PC0 0x40005010\r
+#define CYREG_PRT2_PC1 0x40005011\r
+#define CYREG_PRT2_PC2 0x40005012\r
+#define CYREG_PRT2_PC3 0x40005013\r
+#define CYREG_PRT2_PC4 0x40005014\r
+#define CYREG_PRT2_PC5 0x40005015\r
+#define CYREG_PRT2_PC6 0x40005016\r
+#define CYREG_PRT2_PC7 0x40005017\r
+#define CYDEV_IO_PC_PRT3_BASE 0x40005018\r
+#define CYDEV_IO_PC_PRT3_SIZE 0x00000008\r
+#define CYREG_PRT3_PC0 0x40005018\r
+#define CYREG_PRT3_PC1 0x40005019\r
+#define CYREG_PRT3_PC2 0x4000501a\r
+#define CYREG_PRT3_PC3 0x4000501b\r
+#define CYREG_PRT3_PC4 0x4000501c\r
+#define CYREG_PRT3_PC5 0x4000501d\r
+#define CYREG_PRT3_PC6 0x4000501e\r
+#define CYREG_PRT3_PC7 0x4000501f\r
+#define CYDEV_IO_PC_PRT4_BASE 0x40005020\r
+#define CYDEV_IO_PC_PRT4_SIZE 0x00000008\r
+#define CYREG_PRT4_PC0 0x40005020\r
+#define CYREG_PRT4_PC1 0x40005021\r
+#define CYREG_PRT4_PC2 0x40005022\r
+#define CYREG_PRT4_PC3 0x40005023\r
+#define CYREG_PRT4_PC4 0x40005024\r
+#define CYREG_PRT4_PC5 0x40005025\r
+#define CYREG_PRT4_PC6 0x40005026\r
+#define CYREG_PRT4_PC7 0x40005027\r
+#define CYDEV_IO_PC_PRT5_BASE 0x40005028\r
+#define CYDEV_IO_PC_PRT5_SIZE 0x00000008\r
+#define CYREG_PRT5_PC0 0x40005028\r
+#define CYREG_PRT5_PC1 0x40005029\r
+#define CYREG_PRT5_PC2 0x4000502a\r
+#define CYREG_PRT5_PC3 0x4000502b\r
+#define CYREG_PRT5_PC4 0x4000502c\r
+#define CYREG_PRT5_PC5 0x4000502d\r
+#define CYREG_PRT5_PC6 0x4000502e\r
+#define CYREG_PRT5_PC7 0x4000502f\r
+#define CYDEV_IO_PC_PRT6_BASE 0x40005030\r
+#define CYDEV_IO_PC_PRT6_SIZE 0x00000008\r
+#define CYREG_PRT6_PC0 0x40005030\r
+#define CYREG_PRT6_PC1 0x40005031\r
+#define CYREG_PRT6_PC2 0x40005032\r
+#define CYREG_PRT6_PC3 0x40005033\r
+#define CYREG_PRT6_PC4 0x40005034\r
+#define CYREG_PRT6_PC5 0x40005035\r
+#define CYREG_PRT6_PC6 0x40005036\r
+#define CYREG_PRT6_PC7 0x40005037\r
+#define CYDEV_IO_PC_PRT12_BASE 0x40005060\r
+#define CYDEV_IO_PC_PRT12_SIZE 0x00000008\r
+#define CYREG_PRT12_PC0 0x40005060\r
+#define CYREG_PRT12_PC1 0x40005061\r
+#define CYREG_PRT12_PC2 0x40005062\r
+#define CYREG_PRT12_PC3 0x40005063\r
+#define CYREG_PRT12_PC4 0x40005064\r
+#define CYREG_PRT12_PC5 0x40005065\r
+#define CYREG_PRT12_PC6 0x40005066\r
+#define CYREG_PRT12_PC7 0x40005067\r
+#define CYDEV_IO_PC_PRT15_BASE 0x40005078\r
+#define CYDEV_IO_PC_PRT15_SIZE 0x00000006\r
+#define CYREG_IO_PC_PRT15_PC0 0x40005078\r
+#define CYREG_IO_PC_PRT15_PC1 0x40005079\r
+#define CYREG_IO_PC_PRT15_PC2 0x4000507a\r
+#define CYREG_IO_PC_PRT15_PC3 0x4000507b\r
+#define CYREG_IO_PC_PRT15_PC4 0x4000507c\r
+#define CYREG_IO_PC_PRT15_PC5 0x4000507d\r
+#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507e\r
+#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002\r
+#define CYREG_IO_PC_PRT15_7_6_PC0 0x4000507e\r
+#define CYREG_IO_PC_PRT15_7_6_PC1 0x4000507f\r
+#define CYDEV_IO_DR_BASE 0x40005080\r
+#define CYDEV_IO_DR_SIZE 0x00000010\r
+#define CYDEV_IO_DR_PRT0_BASE 0x40005080\r
+#define CYDEV_IO_DR_PRT0_SIZE 0x00000001\r
+#define CYREG_PRT0_DR_ALIAS 0x40005080\r
+#define CYDEV_IO_DR_PRT1_BASE 0x40005081\r
+#define CYDEV_IO_DR_PRT1_SIZE 0x00000001\r
+#define CYREG_PRT1_DR_ALIAS 0x40005081\r
+#define CYDEV_IO_DR_PRT2_BASE 0x40005082\r
+#define CYDEV_IO_DR_PRT2_SIZE 0x00000001\r
+#define CYREG_PRT2_DR_ALIAS 0x40005082\r
+#define CYDEV_IO_DR_PRT3_BASE 0x40005083\r
+#define CYDEV_IO_DR_PRT3_SIZE 0x00000001\r
+#define CYREG_PRT3_DR_ALIAS 0x40005083\r
+#define CYDEV_IO_DR_PRT4_BASE 0x40005084\r
+#define CYDEV_IO_DR_PRT4_SIZE 0x00000001\r
+#define CYREG_PRT4_DR_ALIAS 0x40005084\r
+#define CYDEV_IO_DR_PRT5_BASE 0x40005085\r
+#define CYDEV_IO_DR_PRT5_SIZE 0x00000001\r
+#define CYREG_PRT5_DR_ALIAS 0x40005085\r
+#define CYDEV_IO_DR_PRT6_BASE 0x40005086\r
+#define CYDEV_IO_DR_PRT6_SIZE 0x00000001\r
+#define CYREG_PRT6_DR_ALIAS 0x40005086\r
+#define CYDEV_IO_DR_PRT12_BASE 0x4000508c\r
+#define CYDEV_IO_DR_PRT12_SIZE 0x00000001\r
+#define CYREG_PRT12_DR_ALIAS 0x4000508c\r
+#define CYDEV_IO_DR_PRT15_BASE 0x4000508f\r
+#define CYDEV_IO_DR_PRT15_SIZE 0x00000001\r
+#define CYREG_PRT15_DR_15_ALIAS 0x4000508f\r
+#define CYDEV_IO_PS_BASE 0x40005090\r
+#define CYDEV_IO_PS_SIZE 0x00000010\r
+#define CYDEV_IO_PS_PRT0_BASE 0x40005090\r
+#define CYDEV_IO_PS_PRT0_SIZE 0x00000001\r
+#define CYREG_PRT0_PS_ALIAS 0x40005090\r
+#define CYDEV_IO_PS_PRT1_BASE 0x40005091\r
+#define CYDEV_IO_PS_PRT1_SIZE 0x00000001\r
+#define CYREG_PRT1_PS_ALIAS 0x40005091\r
+#define CYDEV_IO_PS_PRT2_BASE 0x40005092\r
+#define CYDEV_IO_PS_PRT2_SIZE 0x00000001\r
+#define CYREG_PRT2_PS_ALIAS 0x40005092\r
+#define CYDEV_IO_PS_PRT3_BASE 0x40005093\r
+#define CYDEV_IO_PS_PRT3_SIZE 0x00000001\r
+#define CYREG_PRT3_PS_ALIAS 0x40005093\r
+#define CYDEV_IO_PS_PRT4_BASE 0x40005094\r
+#define CYDEV_IO_PS_PRT4_SIZE 0x00000001\r
+#define CYREG_PRT4_PS_ALIAS 0x40005094\r
+#define CYDEV_IO_PS_PRT5_BASE 0x40005095\r
+#define CYDEV_IO_PS_PRT5_SIZE 0x00000001\r
+#define CYREG_PRT5_PS_ALIAS 0x40005095\r
+#define CYDEV_IO_PS_PRT6_BASE 0x40005096\r
+#define CYDEV_IO_PS_PRT6_SIZE 0x00000001\r
+#define CYREG_PRT6_PS_ALIAS 0x40005096\r
+#define CYDEV_IO_PS_PRT12_BASE 0x4000509c\r
+#define CYDEV_IO_PS_PRT12_SIZE 0x00000001\r
+#define CYREG_PRT12_PS_ALIAS 0x4000509c\r
+#define CYDEV_IO_PS_PRT15_BASE 0x4000509f\r
+#define CYDEV_IO_PS_PRT15_SIZE 0x00000001\r
+#define CYREG_PRT15_PS15_ALIAS 0x4000509f\r
+#define CYDEV_IO_PRT_BASE 0x40005100\r
+#define CYDEV_IO_PRT_SIZE 0x00000100\r
+#define CYDEV_IO_PRT_PRT0_BASE 0x40005100\r
+#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010\r
+#define CYREG_PRT0_DR 0x40005100\r
+#define CYREG_PRT0_PS 0x40005101\r
+#define CYREG_PRT0_DM0 0x40005102\r
+#define CYREG_PRT0_DM1 0x40005103\r
+#define CYREG_PRT0_DM2 0x40005104\r
+#define CYREG_PRT0_SLW 0x40005105\r
+#define CYREG_PRT0_BYP 0x40005106\r
+#define CYREG_PRT0_BIE 0x40005107\r
+#define CYREG_PRT0_INP_DIS 0x40005108\r
+#define CYREG_PRT0_CTL 0x40005109\r
+#define CYREG_PRT0_PRT 0x4000510a\r
+#define CYREG_PRT0_BIT_MASK 0x4000510b\r
+#define CYREG_PRT0_AMUX 0x4000510c\r
+#define CYREG_PRT0_AG 0x4000510d\r
+#define CYREG_PRT0_LCD_COM_SEG 0x4000510e\r
+#define CYREG_PRT0_LCD_EN 0x4000510f\r
+#define CYDEV_IO_PRT_PRT1_BASE 0x40005110\r
+#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010\r
+#define CYREG_PRT1_DR 0x40005110\r
+#define CYREG_PRT1_PS 0x40005111\r
+#define CYREG_PRT1_DM0 0x40005112\r
+#define CYREG_PRT1_DM1 0x40005113\r
+#define CYREG_PRT1_DM2 0x40005114\r
+#define CYREG_PRT1_SLW 0x40005115\r
+#define CYREG_PRT1_BYP 0x40005116\r
+#define CYREG_PRT1_BIE 0x40005117\r
+#define CYREG_PRT1_INP_DIS 0x40005118\r
+#define CYREG_PRT1_CTL 0x40005119\r
+#define CYREG_PRT1_PRT 0x4000511a\r
+#define CYREG_PRT1_BIT_MASK 0x4000511b\r
+#define CYREG_PRT1_AMUX 0x4000511c\r
+#define CYREG_PRT1_AG 0x4000511d\r
+#define CYREG_PRT1_LCD_COM_SEG 0x4000511e\r
+#define CYREG_PRT1_LCD_EN 0x4000511f\r
+#define CYDEV_IO_PRT_PRT2_BASE 0x40005120\r
+#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010\r
+#define CYREG_PRT2_DR 0x40005120\r
+#define CYREG_PRT2_PS 0x40005121\r
+#define CYREG_PRT2_DM0 0x40005122\r
+#define CYREG_PRT2_DM1 0x40005123\r
+#define CYREG_PRT2_DM2 0x40005124\r
+#define CYREG_PRT2_SLW 0x40005125\r
+#define CYREG_PRT2_BYP 0x40005126\r
+#define CYREG_PRT2_BIE 0x40005127\r
+#define CYREG_PRT2_INP_DIS 0x40005128\r
+#define CYREG_PRT2_CTL 0x40005129\r
+#define CYREG_PRT2_PRT 0x4000512a\r
+#define CYREG_PRT2_BIT_MASK 0x4000512b\r
+#define CYREG_PRT2_AMUX 0x4000512c\r
+#define CYREG_PRT2_AG 0x4000512d\r
+#define CYREG_PRT2_LCD_COM_SEG 0x4000512e\r
+#define CYREG_PRT2_LCD_EN 0x4000512f\r
+#define CYDEV_IO_PRT_PRT3_BASE 0x40005130\r
+#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010\r
+#define CYREG_PRT3_DR 0x40005130\r
+#define CYREG_PRT3_PS 0x40005131\r
+#define CYREG_PRT3_DM0 0x40005132\r
+#define CYREG_PRT3_DM1 0x40005133\r
+#define CYREG_PRT3_DM2 0x40005134\r
+#define CYREG_PRT3_SLW 0x40005135\r
+#define CYREG_PRT3_BYP 0x40005136\r
+#define CYREG_PRT3_BIE 0x40005137\r
+#define CYREG_PRT3_INP_DIS 0x40005138\r
+#define CYREG_PRT3_CTL 0x40005139\r
+#define CYREG_PRT3_PRT 0x4000513a\r
+#define CYREG_PRT3_BIT_MASK 0x4000513b\r
+#define CYREG_PRT3_AMUX 0x4000513c\r
+#define CYREG_PRT3_AG 0x4000513d\r
+#define CYREG_PRT3_LCD_COM_SEG 0x4000513e\r
+#define CYREG_PRT3_LCD_EN 0x4000513f\r
+#define CYDEV_IO_PRT_PRT4_BASE 0x40005140\r
+#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010\r
+#define CYREG_PRT4_DR 0x40005140\r
+#define CYREG_PRT4_PS 0x40005141\r
+#define CYREG_PRT4_DM0 0x40005142\r
+#define CYREG_PRT4_DM1 0x40005143\r
+#define CYREG_PRT4_DM2 0x40005144\r
+#define CYREG_PRT4_SLW 0x40005145\r
+#define CYREG_PRT4_BYP 0x40005146\r
+#define CYREG_PRT4_BIE 0x40005147\r
+#define CYREG_PRT4_INP_DIS 0x40005148\r
+#define CYREG_PRT4_CTL 0x40005149\r
+#define CYREG_PRT4_PRT 0x4000514a\r
+#define CYREG_PRT4_BIT_MASK 0x4000514b\r
+#define CYREG_PRT4_AMUX 0x4000514c\r
+#define CYREG_PRT4_AG 0x4000514d\r
+#define CYREG_PRT4_LCD_COM_SEG 0x4000514e\r
+#define CYREG_PRT4_LCD_EN 0x4000514f\r
+#define CYDEV_IO_PRT_PRT5_BASE 0x40005150\r
+#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010\r
+#define CYREG_PRT5_DR 0x40005150\r
+#define CYREG_PRT5_PS 0x40005151\r
+#define CYREG_PRT5_DM0 0x40005152\r
+#define CYREG_PRT5_DM1 0x40005153\r
+#define CYREG_PRT5_DM2 0x40005154\r
+#define CYREG_PRT5_SLW 0x40005155\r
+#define CYREG_PRT5_BYP 0x40005156\r
+#define CYREG_PRT5_BIE 0x40005157\r
+#define CYREG_PRT5_INP_DIS 0x40005158\r
+#define CYREG_PRT5_CTL 0x40005159\r
+#define CYREG_PRT5_PRT 0x4000515a\r
+#define CYREG_PRT5_BIT_MASK 0x4000515b\r
+#define CYREG_PRT5_AMUX 0x4000515c\r
+#define CYREG_PRT5_AG 0x4000515d\r
+#define CYREG_PRT5_LCD_COM_SEG 0x4000515e\r
+#define CYREG_PRT5_LCD_EN 0x4000515f\r
+#define CYDEV_IO_PRT_PRT6_BASE 0x40005160\r
+#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010\r
+#define CYREG_PRT6_DR 0x40005160\r
+#define CYREG_PRT6_PS 0x40005161\r
+#define CYREG_PRT6_DM0 0x40005162\r
+#define CYREG_PRT6_DM1 0x40005163\r
+#define CYREG_PRT6_DM2 0x40005164\r
+#define CYREG_PRT6_SLW 0x40005165\r
+#define CYREG_PRT6_BYP 0x40005166\r
+#define CYREG_PRT6_BIE 0x40005167\r
+#define CYREG_PRT6_INP_DIS 0x40005168\r
+#define CYREG_PRT6_CTL 0x40005169\r
+#define CYREG_PRT6_PRT 0x4000516a\r
+#define CYREG_PRT6_BIT_MASK 0x4000516b\r
+#define CYREG_PRT6_AMUX 0x4000516c\r
+#define CYREG_PRT6_AG 0x4000516d\r
+#define CYREG_PRT6_LCD_COM_SEG 0x4000516e\r
+#define CYREG_PRT6_LCD_EN 0x4000516f\r
+#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0\r
+#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010\r
+#define CYREG_PRT12_DR 0x400051c0\r
+#define CYREG_PRT12_PS 0x400051c1\r
+#define CYREG_PRT12_DM0 0x400051c2\r
+#define CYREG_PRT12_DM1 0x400051c3\r
+#define CYREG_PRT12_DM2 0x400051c4\r
+#define CYREG_PRT12_SLW 0x400051c5\r
+#define CYREG_PRT12_BYP 0x400051c6\r
+#define CYREG_PRT12_BIE 0x400051c7\r
+#define CYREG_PRT12_INP_DIS 0x400051c8\r
+#define CYREG_PRT12_SIO_HYST_EN 0x400051c9\r
+#define CYREG_PRT12_PRT 0x400051ca\r
+#define CYREG_PRT12_BIT_MASK 0x400051cb\r
+#define CYREG_PRT12_SIO_REG_HIFREQ 0x400051cc\r
+#define CYREG_PRT12_AG 0x400051cd\r
+#define CYREG_PRT12_SIO_CFG 0x400051ce\r
+#define CYREG_PRT12_SIO_DIFF 0x400051cf\r
+#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0\r
+#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010\r
+#define CYREG_PRT15_DR 0x400051f0\r
+#define CYREG_PRT15_PS 0x400051f1\r
+#define CYREG_PRT15_DM0 0x400051f2\r
+#define CYREG_PRT15_DM1 0x400051f3\r
+#define CYREG_PRT15_DM2 0x400051f4\r
+#define CYREG_PRT15_SLW 0x400051f5\r
+#define CYREG_PRT15_BYP 0x400051f6\r
+#define CYREG_PRT15_BIE 0x400051f7\r
+#define CYREG_PRT15_INP_DIS 0x400051f8\r
+#define CYREG_PRT15_CTL 0x400051f9\r
+#define CYREG_PRT15_PRT 0x400051fa\r
+#define CYREG_PRT15_BIT_MASK 0x400051fb\r
+#define CYREG_PRT15_AMUX 0x400051fc\r
+#define CYREG_PRT15_AG 0x400051fd\r
+#define CYREG_PRT15_LCD_COM_SEG 0x400051fe\r
+#define CYREG_PRT15_LCD_EN 0x400051ff\r
+#define CYDEV_PRTDSI_BASE 0x40005200\r
+#define CYDEV_PRTDSI_SIZE 0x0000007f\r
+#define CYDEV_PRTDSI_PRT0_BASE 0x40005200\r
+#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007\r
+#define CYREG_PRT0_OUT_SEL0 0x40005200\r
+#define CYREG_PRT0_OUT_SEL1 0x40005201\r
+#define CYREG_PRT0_OE_SEL0 0x40005202\r
+#define CYREG_PRT0_OE_SEL1 0x40005203\r
+#define CYREG_PRT0_DBL_SYNC_IN 0x40005204\r
+#define CYREG_PRT0_SYNC_OUT 0x40005205\r
+#define CYREG_PRT0_CAPS_SEL 0x40005206\r
+#define CYDEV_PRTDSI_PRT1_BASE 0x40005208\r
+#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007\r
+#define CYREG_PRT1_OUT_SEL0 0x40005208\r
+#define CYREG_PRT1_OUT_SEL1 0x40005209\r
+#define CYREG_PRT1_OE_SEL0 0x4000520a\r
+#define CYREG_PRT1_OE_SEL1 0x4000520b\r
+#define CYREG_PRT1_DBL_SYNC_IN 0x4000520c\r
+#define CYREG_PRT1_SYNC_OUT 0x4000520d\r
+#define CYREG_PRT1_CAPS_SEL 0x4000520e\r
+#define CYDEV_PRTDSI_PRT2_BASE 0x40005210\r
+#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007\r
+#define CYREG_PRT2_OUT_SEL0 0x40005210\r
+#define CYREG_PRT2_OUT_SEL1 0x40005211\r
+#define CYREG_PRT2_OE_SEL0 0x40005212\r
+#define CYREG_PRT2_OE_SEL1 0x40005213\r
+#define CYREG_PRT2_DBL_SYNC_IN 0x40005214\r
+#define CYREG_PRT2_SYNC_OUT 0x40005215\r
+#define CYREG_PRT2_CAPS_SEL 0x40005216\r
+#define CYDEV_PRTDSI_PRT3_BASE 0x40005218\r
+#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007\r
+#define CYREG_PRT3_OUT_SEL0 0x40005218\r
+#define CYREG_PRT3_OUT_SEL1 0x40005219\r
+#define CYREG_PRT3_OE_SEL0 0x4000521a\r
+#define CYREG_PRT3_OE_SEL1 0x4000521b\r
+#define CYREG_PRT3_DBL_SYNC_IN 0x4000521c\r
+#define CYREG_PRT3_SYNC_OUT 0x4000521d\r
+#define CYREG_PRT3_CAPS_SEL 0x4000521e\r
+#define CYDEV_PRTDSI_PRT4_BASE 0x40005220\r
+#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007\r
+#define CYREG_PRT4_OUT_SEL0 0x40005220\r
+#define CYREG_PRT4_OUT_SEL1 0x40005221\r
+#define CYREG_PRT4_OE_SEL0 0x40005222\r
+#define CYREG_PRT4_OE_SEL1 0x40005223\r
+#define CYREG_PRT4_DBL_SYNC_IN 0x40005224\r
+#define CYREG_PRT4_SYNC_OUT 0x40005225\r
+#define CYREG_PRT4_CAPS_SEL 0x40005226\r
+#define CYDEV_PRTDSI_PRT5_BASE 0x40005228\r
+#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007\r
+#define CYREG_PRT5_OUT_SEL0 0x40005228\r
+#define CYREG_PRT5_OUT_SEL1 0x40005229\r
+#define CYREG_PRT5_OE_SEL0 0x4000522a\r
+#define CYREG_PRT5_OE_SEL1 0x4000522b\r
+#define CYREG_PRT5_DBL_SYNC_IN 0x4000522c\r
+#define CYREG_PRT5_SYNC_OUT 0x4000522d\r
+#define CYREG_PRT5_CAPS_SEL 0x4000522e\r
+#define CYDEV_PRTDSI_PRT6_BASE 0x40005230\r
+#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007\r
+#define CYREG_PRT6_OUT_SEL0 0x40005230\r
+#define CYREG_PRT6_OUT_SEL1 0x40005231\r
+#define CYREG_PRT6_OE_SEL0 0x40005232\r
+#define CYREG_PRT6_OE_SEL1 0x40005233\r
+#define CYREG_PRT6_DBL_SYNC_IN 0x40005234\r
+#define CYREG_PRT6_SYNC_OUT 0x40005235\r
+#define CYREG_PRT6_CAPS_SEL 0x40005236\r
+#define CYDEV_PRTDSI_PRT12_BASE 0x40005260\r
+#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006\r
+#define CYREG_PRT12_OUT_SEL0 0x40005260\r
+#define CYREG_PRT12_OUT_SEL1 0x40005261\r
+#define CYREG_PRT12_OE_SEL0 0x40005262\r
+#define CYREG_PRT12_OE_SEL1 0x40005263\r
+#define CYREG_PRT12_DBL_SYNC_IN 0x40005264\r
+#define CYREG_PRT12_SYNC_OUT 0x40005265\r
+#define CYDEV_PRTDSI_PRT15_BASE 0x40005278\r
+#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007\r
+#define CYREG_PRT15_OUT_SEL0 0x40005278\r
+#define CYREG_PRT15_OUT_SEL1 0x40005279\r
+#define CYREG_PRT15_OE_SEL0 0x4000527a\r
+#define CYREG_PRT15_OE_SEL1 0x4000527b\r
+#define CYREG_PRT15_DBL_SYNC_IN 0x4000527c\r
+#define CYREG_PRT15_SYNC_OUT 0x4000527d\r
+#define CYREG_PRT15_CAPS_SEL 0x4000527e\r
+#define CYDEV_EMIF_BASE 0x40005400\r
+#define CYDEV_EMIF_SIZE 0x00000007\r
+#define CYREG_EMIF_NO_UDB 0x40005400\r
+#define CYREG_EMIF_RP_WAIT_STATES 0x40005401\r
+#define CYREG_EMIF_MEM_DWN 0x40005402\r
+#define CYREG_EMIF_MEMCLK_DIV 0x40005403\r
+#define CYREG_EMIF_CLOCK_EN 0x40005404\r
+#define CYREG_EMIF_EM_TYPE 0x40005405\r
+#define CYREG_EMIF_WP_WAIT_STATES 0x40005406\r
+#define CYDEV_ANAIF_BASE 0x40005800\r
+#define CYDEV_ANAIF_SIZE 0x000003a9\r
+#define CYDEV_ANAIF_CFG_BASE 0x40005800\r
+#define CYDEV_ANAIF_CFG_SIZE 0x0000010f\r
+#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800\r
+#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003\r
+#define CYREG_SC0_CR0 0x40005800\r
+#define CYREG_SC0_CR1 0x40005801\r
+#define CYREG_SC0_CR2 0x40005802\r
+#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804\r
+#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003\r
+#define CYREG_SC1_CR0 0x40005804\r
+#define CYREG_SC1_CR1 0x40005805\r
+#define CYREG_SC1_CR2 0x40005806\r
+#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808\r
+#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003\r
+#define CYREG_SC2_CR0 0x40005808\r
+#define CYREG_SC2_CR1 0x40005809\r
+#define CYREG_SC2_CR2 0x4000580a\r
+#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580c\r
+#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003\r
+#define CYREG_SC3_CR0 0x4000580c\r
+#define CYREG_SC3_CR1 0x4000580d\r
+#define CYREG_SC3_CR2 0x4000580e\r
+#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820\r
+#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003\r
+#define CYREG_DAC0_CR0 0x40005820\r
+#define CYREG_DAC0_CR1 0x40005821\r
+#define CYREG_DAC0_TST 0x40005822\r
+#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824\r
+#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003\r
+#define CYREG_DAC1_CR0 0x40005824\r
+#define CYREG_DAC1_CR1 0x40005825\r
+#define CYREG_DAC1_TST 0x40005826\r
+#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828\r
+#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003\r
+#define CYREG_DAC2_CR0 0x40005828\r
+#define CYREG_DAC2_CR1 0x40005829\r
+#define CYREG_DAC2_TST 0x4000582a\r
+#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582c\r
+#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003\r
+#define CYREG_DAC3_CR0 0x4000582c\r
+#define CYREG_DAC3_CR1 0x4000582d\r
+#define CYREG_DAC3_TST 0x4000582e\r
+#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840\r
+#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001\r
+#define CYREG_CMP0_CR 0x40005840\r
+#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841\r
+#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001\r
+#define CYREG_CMP1_CR 0x40005841\r
+#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842\r
+#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001\r
+#define CYREG_CMP2_CR 0x40005842\r
+#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843\r
+#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001\r
+#define CYREG_CMP3_CR 0x40005843\r
+#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848\r
+#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002\r
+#define CYREG_LUT0_CR 0x40005848\r
+#define CYREG_LUT0_MX 0x40005849\r
+#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584a\r
+#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002\r
+#define CYREG_LUT1_CR 0x4000584a\r
+#define CYREG_LUT1_MX 0x4000584b\r
+#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584c\r
+#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002\r
+#define CYREG_LUT2_CR 0x4000584c\r
+#define CYREG_LUT2_MX 0x4000584d\r
+#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584e\r
+#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002\r
+#define CYREG_LUT3_CR 0x4000584e\r
+#define CYREG_LUT3_MX 0x4000584f\r
+#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858\r
+#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002\r
+#define CYREG_OPAMP0_CR 0x40005858\r
+#define CYREG_OPAMP0_RSVD 0x40005859\r
+#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585a\r
+#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002\r
+#define CYREG_OPAMP1_CR 0x4000585a\r
+#define CYREG_OPAMP1_RSVD 0x4000585b\r
+#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585c\r
+#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002\r
+#define CYREG_OPAMP2_CR 0x4000585c\r
+#define CYREG_OPAMP2_RSVD 0x4000585d\r
+#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585e\r
+#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002\r
+#define CYREG_OPAMP3_CR 0x4000585e\r
+#define CYREG_OPAMP3_RSVD 0x4000585f\r
+#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868\r
+#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002\r
+#define CYREG_LCDDAC_CR0 0x40005868\r
+#define CYREG_LCDDAC_CR1 0x40005869\r
+#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586a\r
+#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001\r
+#define CYREG_LCDDRV_CR 0x4000586a\r
+#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586b\r
+#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001\r
+#define CYREG_LCDTMR_CFG 0x4000586b\r
+#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586c\r
+#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004\r
+#define CYREG_BG_CR0 0x4000586c\r
+#define CYREG_BG_RSVD 0x4000586d\r
+#define CYREG_BG_DFT0 0x4000586e\r
+#define CYREG_BG_DFT1 0x4000586f\r
+#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870\r
+#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002\r
+#define CYREG_CAPSL_CFG0 0x40005870\r
+#define CYREG_CAPSL_CFG1 0x40005871\r
+#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872\r
+#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002\r
+#define CYREG_CAPSR_CFG0 0x40005872\r
+#define CYREG_CAPSR_CFG1 0x40005873\r
+#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876\r
+#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002\r
+#define CYREG_PUMP_CR0 0x40005876\r
+#define CYREG_PUMP_CR1 0x40005877\r
+#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878\r
+#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002\r
+#define CYREG_LPF0_CR0 0x40005878\r
+#define CYREG_LPF0_RSVD 0x40005879\r
+#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587a\r
+#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002\r
+#define CYREG_LPF1_CR0 0x4000587a\r
+#define CYREG_LPF1_RSVD 0x4000587b\r
+#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587c\r
+#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001\r
+#define CYREG_ANAIF_CFG_MISC_CR0 0x4000587c\r
+#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880\r
+#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020\r
+#define CYREG_DSM0_CR0 0x40005880\r
+#define CYREG_DSM0_CR1 0x40005881\r
+#define CYREG_DSM0_CR2 0x40005882\r
+#define CYREG_DSM0_CR3 0x40005883\r
+#define CYREG_DSM0_CR4 0x40005884\r
+#define CYREG_DSM0_CR5 0x40005885\r
+#define CYREG_DSM0_CR6 0x40005886\r
+#define CYREG_DSM0_CR7 0x40005887\r
+#define CYREG_DSM0_CR8 0x40005888\r
+#define CYREG_DSM0_CR9 0x40005889\r
+#define CYREG_DSM0_CR10 0x4000588a\r
+#define CYREG_DSM0_CR11 0x4000588b\r
+#define CYREG_DSM0_CR12 0x4000588c\r
+#define CYREG_DSM0_CR13 0x4000588d\r
+#define CYREG_DSM0_CR14 0x4000588e\r
+#define CYREG_DSM0_CR15 0x4000588f\r
+#define CYREG_DSM0_CR16 0x40005890\r
+#define CYREG_DSM0_CR17 0x40005891\r
+#define CYREG_DSM0_REF0 0x40005892\r
+#define CYREG_DSM0_REF1 0x40005893\r
+#define CYREG_DSM0_REF2 0x40005894\r
+#define CYREG_DSM0_REF3 0x40005895\r
+#define CYREG_DSM0_DEM0 0x40005896\r
+#define CYREG_DSM0_DEM1 0x40005897\r
+#define CYREG_DSM0_TST0 0x40005898\r
+#define CYREG_DSM0_TST1 0x40005899\r
+#define CYREG_DSM0_BUF0 0x4000589a\r
+#define CYREG_DSM0_BUF1 0x4000589b\r
+#define CYREG_DSM0_BUF2 0x4000589c\r
+#define CYREG_DSM0_BUF3 0x4000589d\r
+#define CYREG_DSM0_MISC 0x4000589e\r
+#define CYREG_DSM0_RSVD1 0x4000589f\r
+#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900\r
+#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007\r
+#define CYREG_SAR0_CSR0 0x40005900\r
+#define CYREG_SAR0_CSR1 0x40005901\r
+#define CYREG_SAR0_CSR2 0x40005902\r
+#define CYREG_SAR0_CSR3 0x40005903\r
+#define CYREG_SAR0_CSR4 0x40005904\r
+#define CYREG_SAR0_CSR5 0x40005905\r
+#define CYREG_SAR0_CSR6 0x40005906\r
+#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908\r
+#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007\r
+#define CYREG_SAR1_CSR0 0x40005908\r
+#define CYREG_SAR1_CSR1 0x40005909\r
+#define CYREG_SAR1_CSR2 0x4000590a\r
+#define CYREG_SAR1_CSR3 0x4000590b\r
+#define CYREG_SAR1_CSR4 0x4000590c\r
+#define CYREG_SAR1_CSR5 0x4000590d\r
+#define CYREG_SAR1_CSR6 0x4000590e\r
+#define CYDEV_ANAIF_RT_BASE 0x40005a00\r
+#define CYDEV_ANAIF_RT_SIZE 0x00000162\r
+#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00\r
+#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000d\r
+#define CYREG_SC0_SW0 0x40005a00\r
+#define CYREG_SC0_SW2 0x40005a02\r
+#define CYREG_SC0_SW3 0x40005a03\r
+#define CYREG_SC0_SW4 0x40005a04\r
+#define CYREG_SC0_SW6 0x40005a06\r
+#define CYREG_SC0_SW7 0x40005a07\r
+#define CYREG_SC0_SW8 0x40005a08\r
+#define CYREG_SC0_SW10 0x40005a0a\r
+#define CYREG_SC0_CLK 0x40005a0b\r
+#define CYREG_SC0_BST 0x40005a0c\r
+#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10\r
+#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000d\r
+#define CYREG_SC1_SW0 0x40005a10\r
+#define CYREG_SC1_SW2 0x40005a12\r
+#define CYREG_SC1_SW3 0x40005a13\r
+#define CYREG_SC1_SW4 0x40005a14\r
+#define CYREG_SC1_SW6 0x40005a16\r
+#define CYREG_SC1_SW7 0x40005a17\r
+#define CYREG_SC1_SW8 0x40005a18\r
+#define CYREG_SC1_SW10 0x40005a1a\r
+#define CYREG_SC1_CLK 0x40005a1b\r
+#define CYREG_SC1_BST 0x40005a1c\r
+#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20\r
+#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000d\r
+#define CYREG_SC2_SW0 0x40005a20\r
+#define CYREG_SC2_SW2 0x40005a22\r
+#define CYREG_SC2_SW3 0x40005a23\r
+#define CYREG_SC2_SW4 0x40005a24\r
+#define CYREG_SC2_SW6 0x40005a26\r
+#define CYREG_SC2_SW7 0x40005a27\r
+#define CYREG_SC2_SW8 0x40005a28\r
+#define CYREG_SC2_SW10 0x40005a2a\r
+#define CYREG_SC2_CLK 0x40005a2b\r
+#define CYREG_SC2_BST 0x40005a2c\r
+#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30\r
+#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000d\r
+#define CYREG_SC3_SW0 0x40005a30\r
+#define CYREG_SC3_SW2 0x40005a32\r
+#define CYREG_SC3_SW3 0x40005a33\r
+#define CYREG_SC3_SW4 0x40005a34\r
+#define CYREG_SC3_SW6 0x40005a36\r
+#define CYREG_SC3_SW7 0x40005a37\r
+#define CYREG_SC3_SW8 0x40005a38\r
+#define CYREG_SC3_SW10 0x40005a3a\r
+#define CYREG_SC3_CLK 0x40005a3b\r
+#define CYREG_SC3_BST 0x40005a3c\r
+#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80\r
+#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008\r
+#define CYREG_DAC0_SW0 0x40005a80\r
+#define CYREG_DAC0_SW2 0x40005a82\r
+#define CYREG_DAC0_SW3 0x40005a83\r
+#define CYREG_DAC0_SW4 0x40005a84\r
+#define CYREG_DAC0_STROBE 0x40005a87\r
+#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88\r
+#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008\r
+#define CYREG_DAC1_SW0 0x40005a88\r
+#define CYREG_DAC1_SW2 0x40005a8a\r
+#define CYREG_DAC1_SW3 0x40005a8b\r
+#define CYREG_DAC1_SW4 0x40005a8c\r
+#define CYREG_DAC1_STROBE 0x40005a8f\r
+#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90\r
+#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008\r
+#define CYREG_DAC2_SW0 0x40005a90\r
+#define CYREG_DAC2_SW2 0x40005a92\r
+#define CYREG_DAC2_SW3 0x40005a93\r
+#define CYREG_DAC2_SW4 0x40005a94\r
+#define CYREG_DAC2_STROBE 0x40005a97\r
+#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98\r
+#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008\r
+#define CYREG_DAC3_SW0 0x40005a98\r
+#define CYREG_DAC3_SW2 0x40005a9a\r
+#define CYREG_DAC3_SW3 0x40005a9b\r
+#define CYREG_DAC3_SW4 0x40005a9c\r
+#define CYREG_DAC3_STROBE 0x40005a9f\r
+#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0\r
+#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008\r
+#define CYREG_CMP0_SW0 0x40005ac0\r
+#define CYREG_CMP0_SW2 0x40005ac2\r
+#define CYREG_CMP0_SW3 0x40005ac3\r
+#define CYREG_CMP0_SW4 0x40005ac4\r
+#define CYREG_CMP0_SW6 0x40005ac6\r
+#define CYREG_CMP0_CLK 0x40005ac7\r
+#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8\r
+#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008\r
+#define CYREG_CMP1_SW0 0x40005ac8\r
+#define CYREG_CMP1_SW2 0x40005aca\r
+#define CYREG_CMP1_SW3 0x40005acb\r
+#define CYREG_CMP1_SW4 0x40005acc\r
+#define CYREG_CMP1_SW6 0x40005ace\r
+#define CYREG_CMP1_CLK 0x40005acf\r
+#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0\r
+#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008\r
+#define CYREG_CMP2_SW0 0x40005ad0\r
+#define CYREG_CMP2_SW2 0x40005ad2\r
+#define CYREG_CMP2_SW3 0x40005ad3\r
+#define CYREG_CMP2_SW4 0x40005ad4\r
+#define CYREG_CMP2_SW6 0x40005ad6\r
+#define CYREG_CMP2_CLK 0x40005ad7\r
+#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8\r
+#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008\r
+#define CYREG_CMP3_SW0 0x40005ad8\r
+#define CYREG_CMP3_SW2 0x40005ada\r
+#define CYREG_CMP3_SW3 0x40005adb\r
+#define CYREG_CMP3_SW4 0x40005adc\r
+#define CYREG_CMP3_SW6 0x40005ade\r
+#define CYREG_CMP3_CLK 0x40005adf\r
+#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00\r
+#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008\r
+#define CYREG_DSM0_SW0 0x40005b00\r
+#define CYREG_DSM0_SW2 0x40005b02\r
+#define CYREG_DSM0_SW3 0x40005b03\r
+#define CYREG_DSM0_SW4 0x40005b04\r
+#define CYREG_DSM0_SW6 0x40005b06\r
+#define CYREG_DSM0_CLK 0x40005b07\r
+#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20\r
+#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008\r
+#define CYREG_SAR0_SW0 0x40005b20\r
+#define CYREG_SAR0_SW2 0x40005b22\r
+#define CYREG_SAR0_SW3 0x40005b23\r
+#define CYREG_SAR0_SW4 0x40005b24\r
+#define CYREG_SAR0_SW6 0x40005b26\r
+#define CYREG_SAR0_CLK 0x40005b27\r
+#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28\r
+#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008\r
+#define CYREG_SAR1_SW0 0x40005b28\r
+#define CYREG_SAR1_SW2 0x40005b2a\r
+#define CYREG_SAR1_SW3 0x40005b2b\r
+#define CYREG_SAR1_SW4 0x40005b2c\r
+#define CYREG_SAR1_SW6 0x40005b2e\r
+#define CYREG_SAR1_CLK 0x40005b2f\r
+#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40\r
+#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002\r
+#define CYREG_OPAMP0_MX 0x40005b40\r
+#define CYREG_OPAMP0_SW 0x40005b41\r
+#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42\r
+#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002\r
+#define CYREG_OPAMP1_MX 0x40005b42\r
+#define CYREG_OPAMP1_SW 0x40005b43\r
+#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44\r
+#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002\r
+#define CYREG_OPAMP2_MX 0x40005b44\r
+#define CYREG_OPAMP2_SW 0x40005b45\r
+#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46\r
+#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002\r
+#define CYREG_OPAMP3_MX 0x40005b46\r
+#define CYREG_OPAMP3_SW 0x40005b47\r
+#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50\r
+#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005\r
+#define CYREG_LCDDAC_SW0 0x40005b50\r
+#define CYREG_LCDDAC_SW1 0x40005b51\r
+#define CYREG_LCDDAC_SW2 0x40005b52\r
+#define CYREG_LCDDAC_SW3 0x40005b53\r
+#define CYREG_LCDDAC_SW4 0x40005b54\r
+#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56\r
+#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001\r
+#define CYREG_SC_MISC 0x40005b56\r
+#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58\r
+#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004\r
+#define CYREG_BUS_SW0 0x40005b58\r
+#define CYREG_BUS_SW2 0x40005b5a\r
+#define CYREG_BUS_SW3 0x40005b5b\r
+#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5c\r
+#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006\r
+#define CYREG_DFT_CR0 0x40005b5c\r
+#define CYREG_DFT_CR1 0x40005b5d\r
+#define CYREG_DFT_CR2 0x40005b5e\r
+#define CYREG_DFT_CR3 0x40005b5f\r
+#define CYREG_DFT_CR4 0x40005b60\r
+#define CYREG_DFT_CR5 0x40005b61\r
+#define CYDEV_ANAIF_WRK_BASE 0x40005b80\r
+#define CYDEV_ANAIF_WRK_SIZE 0x00000029\r
+#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80\r
+#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001\r
+#define CYREG_DAC0_D 0x40005b80\r
+#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81\r
+#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001\r
+#define CYREG_DAC1_D 0x40005b81\r
+#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82\r
+#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001\r
+#define CYREG_DAC2_D 0x40005b82\r
+#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83\r
+#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001\r
+#define CYREG_DAC3_D 0x40005b83\r
+#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88\r
+#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002\r
+#define CYREG_DSM0_OUT0 0x40005b88\r
+#define CYREG_DSM0_OUT1 0x40005b89\r
+#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90\r
+#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005\r
+#define CYREG_LUT_SR 0x40005b90\r
+#define CYREG_LUT_WRK1 0x40005b91\r
+#define CYREG_LUT_MSK 0x40005b92\r
+#define CYREG_LUT_CLK 0x40005b93\r
+#define CYREG_LUT_CPTR 0x40005b94\r
+#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96\r
+#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002\r
+#define CYREG_CMP_WRK 0x40005b96\r
+#define CYREG_CMP_TST 0x40005b97\r
+#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98\r
+#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005\r
+#define CYREG_SC_SR 0x40005b98\r
+#define CYREG_SC_WRK1 0x40005b99\r
+#define CYREG_SC_MSK 0x40005b9a\r
+#define CYREG_SC_CMPINV 0x40005b9b\r
+#define CYREG_SC_CPTR 0x40005b9c\r
+#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0\r
+#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002\r
+#define CYREG_SAR0_WRK0 0x40005ba0\r
+#define CYREG_SAR0_WRK1 0x40005ba1\r
+#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2\r
+#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002\r
+#define CYREG_SAR1_WRK0 0x40005ba2\r
+#define CYREG_SAR1_WRK1 0x40005ba3\r
+#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8\r
+#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001\r
+#define CYREG_ANAIF_WRK_SARS_SOF 0x40005ba8\r
+#define CYDEV_USB_BASE 0x40006000\r
+#define CYDEV_USB_SIZE 0x00000300\r
+#define CYREG_USB_EP0_DR0 0x40006000\r
+#define CYREG_USB_EP0_DR1 0x40006001\r
+#define CYREG_USB_EP0_DR2 0x40006002\r
+#define CYREG_USB_EP0_DR3 0x40006003\r
+#define CYREG_USB_EP0_DR4 0x40006004\r
+#define CYREG_USB_EP0_DR5 0x40006005\r
+#define CYREG_USB_EP0_DR6 0x40006006\r
+#define CYREG_USB_EP0_DR7 0x40006007\r
+#define CYREG_USB_CR0 0x40006008\r
+#define CYREG_USB_CR1 0x40006009\r
+#define CYREG_USB_SIE_EP_INT_EN 0x4000600a\r
+#define CYREG_USB_SIE_EP_INT_SR 0x4000600b\r
+#define CYDEV_USB_SIE_EP1_BASE 0x4000600c\r
+#define CYDEV_USB_SIE_EP1_SIZE 0x00000003\r
+#define CYREG_USB_SIE_EP1_CNT0 0x4000600c\r
+#define CYREG_USB_SIE_EP1_CNT1 0x4000600d\r
+#define CYREG_USB_SIE_EP1_CR0 0x4000600e\r
+#define CYREG_USB_USBIO_CR0 0x40006010\r
+#define CYREG_USB_USBIO_CR1 0x40006012\r
+#define CYREG_USB_DYN_RECONFIG 0x40006014\r
+#define CYREG_USB_SOF0 0x40006018\r
+#define CYREG_USB_SOF1 0x40006019\r
+#define CYDEV_USB_SIE_EP2_BASE 0x4000601c\r
+#define CYDEV_USB_SIE_EP2_SIZE 0x00000003\r
+#define CYREG_USB_SIE_EP2_CNT0 0x4000601c\r
+#define CYREG_USB_SIE_EP2_CNT1 0x4000601d\r
+#define CYREG_USB_SIE_EP2_CR0 0x4000601e\r
+#define CYREG_USB_EP0_CR 0x40006028\r
+#define CYREG_USB_EP0_CNT 0x40006029\r
+#define CYDEV_USB_SIE_EP3_BASE 0x4000602c\r
+#define CYDEV_USB_SIE_EP3_SIZE 0x00000003\r
+#define CYREG_USB_SIE_EP3_CNT0 0x4000602c\r
+#define CYREG_USB_SIE_EP3_CNT1 0x4000602d\r
+#define CYREG_USB_SIE_EP3_CR0 0x4000602e\r
+#define CYDEV_USB_SIE_EP4_BASE 0x4000603c\r
+#define CYDEV_USB_SIE_EP4_SIZE 0x00000003\r
+#define CYREG_USB_SIE_EP4_CNT0 0x4000603c\r
+#define CYREG_USB_SIE_EP4_CNT1 0x4000603d\r
+#define CYREG_USB_SIE_EP4_CR0 0x4000603e\r
+#define CYDEV_USB_SIE_EP5_BASE 0x4000604c\r
+#define CYDEV_USB_SIE_EP5_SIZE 0x00000003\r
+#define CYREG_USB_SIE_EP5_CNT0 0x4000604c\r
+#define CYREG_USB_SIE_EP5_CNT1 0x4000604d\r
+#define CYREG_USB_SIE_EP5_CR0 0x4000604e\r
+#define CYDEV_USB_SIE_EP6_BASE 0x4000605c\r
+#define CYDEV_USB_SIE_EP6_SIZE 0x00000003\r
+#define CYREG_USB_SIE_EP6_CNT0 0x4000605c\r
+#define CYREG_USB_SIE_EP6_CNT1 0x4000605d\r
+#define CYREG_USB_SIE_EP6_CR0 0x4000605e\r
+#define CYDEV_USB_SIE_EP7_BASE 0x4000606c\r
+#define CYDEV_USB_SIE_EP7_SIZE 0x00000003\r
+#define CYREG_USB_SIE_EP7_CNT0 0x4000606c\r
+#define CYREG_USB_SIE_EP7_CNT1 0x4000606d\r
+#define CYREG_USB_SIE_EP7_CR0 0x4000606e\r
+#define CYDEV_USB_SIE_EP8_BASE 0x4000607c\r
+#define CYDEV_USB_SIE_EP8_SIZE 0x00000003\r
+#define CYREG_USB_SIE_EP8_CNT0 0x4000607c\r
+#define CYREG_USB_SIE_EP8_CNT1 0x4000607d\r
+#define CYREG_USB_SIE_EP8_CR0 0x4000607e\r
+#define CYDEV_USB_ARB_EP1_BASE 0x40006080\r
+#define CYDEV_USB_ARB_EP1_SIZE 0x00000003\r
+#define CYREG_USB_ARB_EP1_CFG 0x40006080\r
+#define CYREG_USB_ARB_EP1_INT_EN 0x40006081\r
+#define CYREG_USB_ARB_EP1_SR 0x40006082\r
+#define CYDEV_USB_ARB_RW1_BASE 0x40006084\r
+#define CYDEV_USB_ARB_RW1_SIZE 0x00000005\r
+#define CYREG_USB_ARB_RW1_WA 0x40006084\r
+#define CYREG_USB_ARB_RW1_WA_MSB 0x40006085\r
+#define CYREG_USB_ARB_RW1_RA 0x40006086\r
+#define CYREG_USB_ARB_RW1_RA_MSB 0x40006087\r
+#define CYREG_USB_ARB_RW1_DR 0x40006088\r
+#define CYREG_USB_BUF_SIZE 0x4000608c\r
+#define CYREG_USB_EP_ACTIVE 0x4000608e\r
+#define CYREG_USB_EP_TYPE 0x4000608f\r
+#define CYDEV_USB_ARB_EP2_BASE 0x40006090\r
+#define CYDEV_USB_ARB_EP2_SIZE 0x00000003\r
+#define CYREG_USB_ARB_EP2_CFG 0x40006090\r
+#define CYREG_USB_ARB_EP2_INT_EN 0x40006091\r
+#define CYREG_USB_ARB_EP2_SR 0x40006092\r
+#define CYDEV_USB_ARB_RW2_BASE 0x40006094\r
+#define CYDEV_USB_ARB_RW2_SIZE 0x00000005\r
+#define CYREG_USB_ARB_RW2_WA 0x40006094\r
+#define CYREG_USB_ARB_RW2_WA_MSB 0x40006095\r
+#define CYREG_USB_ARB_RW2_RA 0x40006096\r
+#define CYREG_USB_ARB_RW2_RA_MSB 0x40006097\r
+#define CYREG_USB_ARB_RW2_DR 0x40006098\r
+#define CYREG_USB_ARB_CFG 0x4000609c\r
+#define CYREG_USB_USB_CLK_EN 0x4000609d\r
+#define CYREG_USB_ARB_INT_EN 0x4000609e\r
+#define CYREG_USB_ARB_INT_SR 0x4000609f\r
+#define CYDEV_USB_ARB_EP3_BASE 0x400060a0\r
+#define CYDEV_USB_ARB_EP3_SIZE 0x00000003\r
+#define CYREG_USB_ARB_EP3_CFG 0x400060a0\r
+#define CYREG_USB_ARB_EP3_INT_EN 0x400060a1\r
+#define CYREG_USB_ARB_EP3_SR 0x400060a2\r
+#define CYDEV_USB_ARB_RW3_BASE 0x400060a4\r
+#define CYDEV_USB_ARB_RW3_SIZE 0x00000005\r
+#define CYREG_USB_ARB_RW3_WA 0x400060a4\r
+#define CYREG_USB_ARB_RW3_WA_MSB 0x400060a5\r
+#define CYREG_USB_ARB_RW3_RA 0x400060a6\r
+#define CYREG_USB_ARB_RW3_RA_MSB 0x400060a7\r
+#define CYREG_USB_ARB_RW3_DR 0x400060a8\r
+#define CYREG_USB_CWA 0x400060ac\r
+#define CYREG_USB_CWA_MSB 0x400060ad\r
+#define CYDEV_USB_ARB_EP4_BASE 0x400060b0\r
+#define CYDEV_USB_ARB_EP4_SIZE 0x00000003\r
+#define CYREG_USB_ARB_EP4_CFG 0x400060b0\r
+#define CYREG_USB_ARB_EP4_INT_EN 0x400060b1\r
+#define CYREG_USB_ARB_EP4_SR 0x400060b2\r
+#define CYDEV_USB_ARB_RW4_BASE 0x400060b4\r
+#define CYDEV_USB_ARB_RW4_SIZE 0x00000005\r
+#define CYREG_USB_ARB_RW4_WA 0x400060b4\r
+#define CYREG_USB_ARB_RW4_WA_MSB 0x400060b5\r
+#define CYREG_USB_ARB_RW4_RA 0x400060b6\r
+#define CYREG_USB_ARB_RW4_RA_MSB 0x400060b7\r
+#define CYREG_USB_ARB_RW4_DR 0x400060b8\r
+#define CYREG_USB_DMA_THRES 0x400060bc\r
+#define CYREG_USB_DMA_THRES_MSB 0x400060bd\r
+#define CYDEV_USB_ARB_EP5_BASE 0x400060c0\r
+#define CYDEV_USB_ARB_EP5_SIZE 0x00000003\r
+#define CYREG_USB_ARB_EP5_CFG 0x400060c0\r
+#define CYREG_USB_ARB_EP5_INT_EN 0x400060c1\r
+#define CYREG_USB_ARB_EP5_SR 0x400060c2\r
+#define CYDEV_USB_ARB_RW5_BASE 0x400060c4\r
+#define CYDEV_USB_ARB_RW5_SIZE 0x00000005\r
+#define CYREG_USB_ARB_RW5_WA 0x400060c4\r
+#define CYREG_USB_ARB_RW5_WA_MSB 0x400060c5\r
+#define CYREG_USB_ARB_RW5_RA 0x400060c6\r
+#define CYREG_USB_ARB_RW5_RA_MSB 0x400060c7\r
+#define CYREG_USB_ARB_RW5_DR 0x400060c8\r
+#define CYREG_USB_BUS_RST_CNT 0x400060cc\r
+#define CYDEV_USB_ARB_EP6_BASE 0x400060d0\r
+#define CYDEV_USB_ARB_EP6_SIZE 0x00000003\r
+#define CYREG_USB_ARB_EP6_CFG 0x400060d0\r
+#define CYREG_USB_ARB_EP6_INT_EN 0x400060d1\r
+#define CYREG_USB_ARB_EP6_SR 0x400060d2\r
+#define CYDEV_USB_ARB_RW6_BASE 0x400060d4\r
+#define CYDEV_USB_ARB_RW6_SIZE 0x00000005\r
+#define CYREG_USB_ARB_RW6_WA 0x400060d4\r
+#define CYREG_USB_ARB_RW6_WA_MSB 0x400060d5\r
+#define CYREG_USB_ARB_RW6_RA 0x400060d6\r
+#define CYREG_USB_ARB_RW6_RA_MSB 0x400060d7\r
+#define CYREG_USB_ARB_RW6_DR 0x400060d8\r
+#define CYDEV_USB_ARB_EP7_BASE 0x400060e0\r
+#define CYDEV_USB_ARB_EP7_SIZE 0x00000003\r
+#define CYREG_USB_ARB_EP7_CFG 0x400060e0\r
+#define CYREG_USB_ARB_EP7_INT_EN 0x400060e1\r
+#define CYREG_USB_ARB_EP7_SR 0x400060e2\r
+#define CYDEV_USB_ARB_RW7_BASE 0x400060e4\r
+#define CYDEV_USB_ARB_RW7_SIZE 0x00000005\r
+#define CYREG_USB_ARB_RW7_WA 0x400060e4\r
+#define CYREG_USB_ARB_RW7_WA_MSB 0x400060e5\r
+#define CYREG_USB_ARB_RW7_RA 0x400060e6\r
+#define CYREG_USB_ARB_RW7_RA_MSB 0x400060e7\r
+#define CYREG_USB_ARB_RW7_DR 0x400060e8\r
+#define CYDEV_USB_ARB_EP8_BASE 0x400060f0\r
+#define CYDEV_USB_ARB_EP8_SIZE 0x00000003\r
+#define CYREG_USB_ARB_EP8_CFG 0x400060f0\r
+#define CYREG_USB_ARB_EP8_INT_EN 0x400060f1\r
+#define CYREG_USB_ARB_EP8_SR 0x400060f2\r
+#define CYDEV_USB_ARB_RW8_BASE 0x400060f4\r
+#define CYDEV_USB_ARB_RW8_SIZE 0x00000005\r
+#define CYREG_USB_ARB_RW8_WA 0x400060f4\r
+#define CYREG_USB_ARB_RW8_WA_MSB 0x400060f5\r
+#define CYREG_USB_ARB_RW8_RA 0x400060f6\r
+#define CYREG_USB_ARB_RW8_RA_MSB 0x400060f7\r
+#define CYREG_USB_ARB_RW8_DR 0x400060f8\r
+#define CYDEV_USB_MEM_BASE 0x40006100\r
+#define CYDEV_USB_MEM_SIZE 0x00000200\r
+#define CYREG_USB_MEM_DATA_MBASE 0x40006100\r
+#define CYREG_USB_MEM_DATA_MSIZE 0x00000200\r
+#define CYDEV_UWRK_BASE 0x40006400\r
+#define CYDEV_UWRK_SIZE 0x00000b60\r
+#define CYDEV_UWRK_UWRK8_BASE 0x40006400\r
+#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0\r
+#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400\r
+#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0\r
+#define CYREG_B0_UDB00_A0 0x40006400\r
+#define CYREG_B0_UDB01_A0 0x40006401\r
+#define CYREG_B0_UDB02_A0 0x40006402\r
+#define CYREG_B0_UDB03_A0 0x40006403\r
+#define CYREG_B0_UDB04_A0 0x40006404\r
+#define CYREG_B0_UDB05_A0 0x40006405\r
+#define CYREG_B0_UDB06_A0 0x40006406\r
+#define CYREG_B0_UDB07_A0 0x40006407\r
+#define CYREG_B0_UDB08_A0 0x40006408\r
+#define CYREG_B0_UDB09_A0 0x40006409\r
+#define CYREG_B0_UDB10_A0 0x4000640a\r
+#define CYREG_B0_UDB11_A0 0x4000640b\r
+#define CYREG_B0_UDB12_A0 0x4000640c\r
+#define CYREG_B0_UDB13_A0 0x4000640d\r
+#define CYREG_B0_UDB14_A0 0x4000640e\r
+#define CYREG_B0_UDB15_A0 0x4000640f\r
+#define CYREG_B0_UDB00_A1 0x40006410\r
+#define CYREG_B0_UDB01_A1 0x40006411\r
+#define CYREG_B0_UDB02_A1 0x40006412\r
+#define CYREG_B0_UDB03_A1 0x40006413\r
+#define CYREG_B0_UDB04_A1 0x40006414\r
+#define CYREG_B0_UDB05_A1 0x40006415\r
+#define CYREG_B0_UDB06_A1 0x40006416\r
+#define CYREG_B0_UDB07_A1 0x40006417\r
+#define CYREG_B0_UDB08_A1 0x40006418\r
+#define CYREG_B0_UDB09_A1 0x40006419\r
+#define CYREG_B0_UDB10_A1 0x4000641a\r
+#define CYREG_B0_UDB11_A1 0x4000641b\r
+#define CYREG_B0_UDB12_A1 0x4000641c\r
+#define CYREG_B0_UDB13_A1 0x4000641d\r
+#define CYREG_B0_UDB14_A1 0x4000641e\r
+#define CYREG_B0_UDB15_A1 0x4000641f\r
+#define CYREG_B0_UDB00_D0 0x40006420\r
+#define CYREG_B0_UDB01_D0 0x40006421\r
+#define CYREG_B0_UDB02_D0 0x40006422\r
+#define CYREG_B0_UDB03_D0 0x40006423\r
+#define CYREG_B0_UDB04_D0 0x40006424\r
+#define CYREG_B0_UDB05_D0 0x40006425\r
+#define CYREG_B0_UDB06_D0 0x40006426\r
+#define CYREG_B0_UDB07_D0 0x40006427\r
+#define CYREG_B0_UDB08_D0 0x40006428\r
+#define CYREG_B0_UDB09_D0 0x40006429\r
+#define CYREG_B0_UDB10_D0 0x4000642a\r
+#define CYREG_B0_UDB11_D0 0x4000642b\r
+#define CYREG_B0_UDB12_D0 0x4000642c\r
+#define CYREG_B0_UDB13_D0 0x4000642d\r
+#define CYREG_B0_UDB14_D0 0x4000642e\r
+#define CYREG_B0_UDB15_D0 0x4000642f\r
+#define CYREG_B0_UDB00_D1 0x40006430\r
+#define CYREG_B0_UDB01_D1 0x40006431\r
+#define CYREG_B0_UDB02_D1 0x40006432\r
+#define CYREG_B0_UDB03_D1 0x40006433\r
+#define CYREG_B0_UDB04_D1 0x40006434\r
+#define CYREG_B0_UDB05_D1 0x40006435\r
+#define CYREG_B0_UDB06_D1 0x40006436\r
+#define CYREG_B0_UDB07_D1 0x40006437\r
+#define CYREG_B0_UDB08_D1 0x40006438\r
+#define CYREG_B0_UDB09_D1 0x40006439\r
+#define CYREG_B0_UDB10_D1 0x4000643a\r
+#define CYREG_B0_UDB11_D1 0x4000643b\r
+#define CYREG_B0_UDB12_D1 0x4000643c\r
+#define CYREG_B0_UDB13_D1 0x4000643d\r
+#define CYREG_B0_UDB14_D1 0x4000643e\r
+#define CYREG_B0_UDB15_D1 0x4000643f\r
+#define CYREG_B0_UDB00_F0 0x40006440\r
+#define CYREG_B0_UDB01_F0 0x40006441\r
+#define CYREG_B0_UDB02_F0 0x40006442\r
+#define CYREG_B0_UDB03_F0 0x40006443\r
+#define CYREG_B0_UDB04_F0 0x40006444\r
+#define CYREG_B0_UDB05_F0 0x40006445\r
+#define CYREG_B0_UDB06_F0 0x40006446\r
+#define CYREG_B0_UDB07_F0 0x40006447\r
+#define CYREG_B0_UDB08_F0 0x40006448\r
+#define CYREG_B0_UDB09_F0 0x40006449\r
+#define CYREG_B0_UDB10_F0 0x4000644a\r
+#define CYREG_B0_UDB11_F0 0x4000644b\r
+#define CYREG_B0_UDB12_F0 0x4000644c\r
+#define CYREG_B0_UDB13_F0 0x4000644d\r
+#define CYREG_B0_UDB14_F0 0x4000644e\r
+#define CYREG_B0_UDB15_F0 0x4000644f\r
+#define CYREG_B0_UDB00_F1 0x40006450\r
+#define CYREG_B0_UDB01_F1 0x40006451\r
+#define CYREG_B0_UDB02_F1 0x40006452\r
+#define CYREG_B0_UDB03_F1 0x40006453\r
+#define CYREG_B0_UDB04_F1 0x40006454\r
+#define CYREG_B0_UDB05_F1 0x40006455\r
+#define CYREG_B0_UDB06_F1 0x40006456\r
+#define CYREG_B0_UDB07_F1 0x40006457\r
+#define CYREG_B0_UDB08_F1 0x40006458\r
+#define CYREG_B0_UDB09_F1 0x40006459\r
+#define CYREG_B0_UDB10_F1 0x4000645a\r
+#define CYREG_B0_UDB11_F1 0x4000645b\r
+#define CYREG_B0_UDB12_F1 0x4000645c\r
+#define CYREG_B0_UDB13_F1 0x4000645d\r
+#define CYREG_B0_UDB14_F1 0x4000645e\r
+#define CYREG_B0_UDB15_F1 0x4000645f\r
+#define CYREG_B0_UDB00_ST 0x40006460\r
+#define CYREG_B0_UDB01_ST 0x40006461\r
+#define CYREG_B0_UDB02_ST 0x40006462\r
+#define CYREG_B0_UDB03_ST 0x40006463\r
+#define CYREG_B0_UDB04_ST 0x40006464\r
+#define CYREG_B0_UDB05_ST 0x40006465\r
+#define CYREG_B0_UDB06_ST 0x40006466\r
+#define CYREG_B0_UDB07_ST 0x40006467\r
+#define CYREG_B0_UDB08_ST 0x40006468\r
+#define CYREG_B0_UDB09_ST 0x40006469\r
+#define CYREG_B0_UDB10_ST 0x4000646a\r
+#define CYREG_B0_UDB11_ST 0x4000646b\r
+#define CYREG_B0_UDB12_ST 0x4000646c\r
+#define CYREG_B0_UDB13_ST 0x4000646d\r
+#define CYREG_B0_UDB14_ST 0x4000646e\r
+#define CYREG_B0_UDB15_ST 0x4000646f\r
+#define CYREG_B0_UDB00_CTL 0x40006470\r
+#define CYREG_B0_UDB01_CTL 0x40006471\r
+#define CYREG_B0_UDB02_CTL 0x40006472\r
+#define CYREG_B0_UDB03_CTL 0x40006473\r
+#define CYREG_B0_UDB04_CTL 0x40006474\r
+#define CYREG_B0_UDB05_CTL 0x40006475\r
+#define CYREG_B0_UDB06_CTL 0x40006476\r
+#define CYREG_B0_UDB07_CTL 0x40006477\r
+#define CYREG_B0_UDB08_CTL 0x40006478\r
+#define CYREG_B0_UDB09_CTL 0x40006479\r
+#define CYREG_B0_UDB10_CTL 0x4000647a\r
+#define CYREG_B0_UDB11_CTL 0x4000647b\r
+#define CYREG_B0_UDB12_CTL 0x4000647c\r
+#define CYREG_B0_UDB13_CTL 0x4000647d\r
+#define CYREG_B0_UDB14_CTL 0x4000647e\r
+#define CYREG_B0_UDB15_CTL 0x4000647f\r
+#define CYREG_B0_UDB00_MSK 0x40006480\r
+#define CYREG_B0_UDB01_MSK 0x40006481\r
+#define CYREG_B0_UDB02_MSK 0x40006482\r
+#define CYREG_B0_UDB03_MSK 0x40006483\r
+#define CYREG_B0_UDB04_MSK 0x40006484\r
+#define CYREG_B0_UDB05_MSK 0x40006485\r
+#define CYREG_B0_UDB06_MSK 0x40006486\r
+#define CYREG_B0_UDB07_MSK 0x40006487\r
+#define CYREG_B0_UDB08_MSK 0x40006488\r
+#define CYREG_B0_UDB09_MSK 0x40006489\r
+#define CYREG_B0_UDB10_MSK 0x4000648a\r
+#define CYREG_B0_UDB11_MSK 0x4000648b\r
+#define CYREG_B0_UDB12_MSK 0x4000648c\r
+#define CYREG_B0_UDB13_MSK 0x4000648d\r
+#define CYREG_B0_UDB14_MSK 0x4000648e\r
+#define CYREG_B0_UDB15_MSK 0x4000648f\r
+#define CYREG_B0_UDB00_ACTL 0x40006490\r
+#define CYREG_B0_UDB01_ACTL 0x40006491\r
+#define CYREG_B0_UDB02_ACTL 0x40006492\r
+#define CYREG_B0_UDB03_ACTL 0x40006493\r
+#define CYREG_B0_UDB04_ACTL 0x40006494\r
+#define CYREG_B0_UDB05_ACTL 0x40006495\r
+#define CYREG_B0_UDB06_ACTL 0x40006496\r
+#define CYREG_B0_UDB07_ACTL 0x40006497\r
+#define CYREG_B0_UDB08_ACTL 0x40006498\r
+#define CYREG_B0_UDB09_ACTL 0x40006499\r
+#define CYREG_B0_UDB10_ACTL 0x4000649a\r
+#define CYREG_B0_UDB11_ACTL 0x4000649b\r
+#define CYREG_B0_UDB12_ACTL 0x4000649c\r
+#define CYREG_B0_UDB13_ACTL 0x4000649d\r
+#define CYREG_B0_UDB14_ACTL 0x4000649e\r
+#define CYREG_B0_UDB15_ACTL 0x4000649f\r
+#define CYREG_B0_UDB00_MC 0x400064a0\r
+#define CYREG_B0_UDB01_MC 0x400064a1\r
+#define CYREG_B0_UDB02_MC 0x400064a2\r
+#define CYREG_B0_UDB03_MC 0x400064a3\r
+#define CYREG_B0_UDB04_MC 0x400064a4\r
+#define CYREG_B0_UDB05_MC 0x400064a5\r
+#define CYREG_B0_UDB06_MC 0x400064a6\r
+#define CYREG_B0_UDB07_MC 0x400064a7\r
+#define CYREG_B0_UDB08_MC 0x400064a8\r
+#define CYREG_B0_UDB09_MC 0x400064a9\r
+#define CYREG_B0_UDB10_MC 0x400064aa\r
+#define CYREG_B0_UDB11_MC 0x400064ab\r
+#define CYREG_B0_UDB12_MC 0x400064ac\r
+#define CYREG_B0_UDB13_MC 0x400064ad\r
+#define CYREG_B0_UDB14_MC 0x400064ae\r
+#define CYREG_B0_UDB15_MC 0x400064af\r
+#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500\r
+#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0\r
+#define CYREG_B1_UDB04_A0 0x40006504\r
+#define CYREG_B1_UDB05_A0 0x40006505\r
+#define CYREG_B1_UDB06_A0 0x40006506\r
+#define CYREG_B1_UDB07_A0 0x40006507\r
+#define CYREG_B1_UDB08_A0 0x40006508\r
+#define CYREG_B1_UDB09_A0 0x40006509\r
+#define CYREG_B1_UDB10_A0 0x4000650a\r
+#define CYREG_B1_UDB11_A0 0x4000650b\r
+#define CYREG_B1_UDB04_A1 0x40006514\r
+#define CYREG_B1_UDB05_A1 0x40006515\r
+#define CYREG_B1_UDB06_A1 0x40006516\r
+#define CYREG_B1_UDB07_A1 0x40006517\r
+#define CYREG_B1_UDB08_A1 0x40006518\r
+#define CYREG_B1_UDB09_A1 0x40006519\r
+#define CYREG_B1_UDB10_A1 0x4000651a\r
+#define CYREG_B1_UDB11_A1 0x4000651b\r
+#define CYREG_B1_UDB04_D0 0x40006524\r
+#define CYREG_B1_UDB05_D0 0x40006525\r
+#define CYREG_B1_UDB06_D0 0x40006526\r
+#define CYREG_B1_UDB07_D0 0x40006527\r
+#define CYREG_B1_UDB08_D0 0x40006528\r
+#define CYREG_B1_UDB09_D0 0x40006529\r
+#define CYREG_B1_UDB10_D0 0x4000652a\r
+#define CYREG_B1_UDB11_D0 0x4000652b\r
+#define CYREG_B1_UDB04_D1 0x40006534\r
+#define CYREG_B1_UDB05_D1 0x40006535\r
+#define CYREG_B1_UDB06_D1 0x40006536\r
+#define CYREG_B1_UDB07_D1 0x40006537\r
+#define CYREG_B1_UDB08_D1 0x40006538\r
+#define CYREG_B1_UDB09_D1 0x40006539\r
+#define CYREG_B1_UDB10_D1 0x4000653a\r
+#define CYREG_B1_UDB11_D1 0x4000653b\r
+#define CYREG_B1_UDB04_F0 0x40006544\r
+#define CYREG_B1_UDB05_F0 0x40006545\r
+#define CYREG_B1_UDB06_F0 0x40006546\r
+#define CYREG_B1_UDB07_F0 0x40006547\r
+#define CYREG_B1_UDB08_F0 0x40006548\r
+#define CYREG_B1_UDB09_F0 0x40006549\r
+#define CYREG_B1_UDB10_F0 0x4000654a\r
+#define CYREG_B1_UDB11_F0 0x4000654b\r
+#define CYREG_B1_UDB04_F1 0x40006554\r
+#define CYREG_B1_UDB05_F1 0x40006555\r
+#define CYREG_B1_UDB06_F1 0x40006556\r
+#define CYREG_B1_UDB07_F1 0x40006557\r
+#define CYREG_B1_UDB08_F1 0x40006558\r
+#define CYREG_B1_UDB09_F1 0x40006559\r
+#define CYREG_B1_UDB10_F1 0x4000655a\r
+#define CYREG_B1_UDB11_F1 0x4000655b\r
+#define CYREG_B1_UDB04_ST 0x40006564\r
+#define CYREG_B1_UDB05_ST 0x40006565\r
+#define CYREG_B1_UDB06_ST 0x40006566\r
+#define CYREG_B1_UDB07_ST 0x40006567\r
+#define CYREG_B1_UDB08_ST 0x40006568\r
+#define CYREG_B1_UDB09_ST 0x40006569\r
+#define CYREG_B1_UDB10_ST 0x4000656a\r
+#define CYREG_B1_UDB11_ST 0x4000656b\r
+#define CYREG_B1_UDB04_CTL 0x40006574\r
+#define CYREG_B1_UDB05_CTL 0x40006575\r
+#define CYREG_B1_UDB06_CTL 0x40006576\r
+#define CYREG_B1_UDB07_CTL 0x40006577\r
+#define CYREG_B1_UDB08_CTL 0x40006578\r
+#define CYREG_B1_UDB09_CTL 0x40006579\r
+#define CYREG_B1_UDB10_CTL 0x4000657a\r
+#define CYREG_B1_UDB11_CTL 0x4000657b\r
+#define CYREG_B1_UDB04_MSK 0x40006584\r
+#define CYREG_B1_UDB05_MSK 0x40006585\r
+#define CYREG_B1_UDB06_MSK 0x40006586\r
+#define CYREG_B1_UDB07_MSK 0x40006587\r
+#define CYREG_B1_UDB08_MSK 0x40006588\r
+#define CYREG_B1_UDB09_MSK 0x40006589\r
+#define CYREG_B1_UDB10_MSK 0x4000658a\r
+#define CYREG_B1_UDB11_MSK 0x4000658b\r
+#define CYREG_B1_UDB04_ACTL 0x40006594\r
+#define CYREG_B1_UDB05_ACTL 0x40006595\r
+#define CYREG_B1_UDB06_ACTL 0x40006596\r
+#define CYREG_B1_UDB07_ACTL 0x40006597\r
+#define CYREG_B1_UDB08_ACTL 0x40006598\r
+#define CYREG_B1_UDB09_ACTL 0x40006599\r
+#define CYREG_B1_UDB10_ACTL 0x4000659a\r
+#define CYREG_B1_UDB11_ACTL 0x4000659b\r
+#define CYREG_B1_UDB04_MC 0x400065a4\r
+#define CYREG_B1_UDB05_MC 0x400065a5\r
+#define CYREG_B1_UDB06_MC 0x400065a6\r
+#define CYREG_B1_UDB07_MC 0x400065a7\r
+#define CYREG_B1_UDB08_MC 0x400065a8\r
+#define CYREG_B1_UDB09_MC 0x400065a9\r
+#define CYREG_B1_UDB10_MC 0x400065aa\r
+#define CYREG_B1_UDB11_MC 0x400065ab\r
+#define CYDEV_UWRK_UWRK16_BASE 0x40006800\r
+#define CYDEV_UWRK_UWRK16_SIZE 0x00000760\r
+#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800\r
+#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160\r
+#define CYREG_B0_UDB00_A0_A1 0x40006800\r
+#define CYREG_B0_UDB01_A0_A1 0x40006802\r
+#define CYREG_B0_UDB02_A0_A1 0x40006804\r
+#define CYREG_B0_UDB03_A0_A1 0x40006806\r
+#define CYREG_B0_UDB04_A0_A1 0x40006808\r
+#define CYREG_B0_UDB05_A0_A1 0x4000680a\r
+#define CYREG_B0_UDB06_A0_A1 0x4000680c\r
+#define CYREG_B0_UDB07_A0_A1 0x4000680e\r
+#define CYREG_B0_UDB08_A0_A1 0x40006810\r
+#define CYREG_B0_UDB09_A0_A1 0x40006812\r
+#define CYREG_B0_UDB10_A0_A1 0x40006814\r
+#define CYREG_B0_UDB11_A0_A1 0x40006816\r
+#define CYREG_B0_UDB12_A0_A1 0x40006818\r
+#define CYREG_B0_UDB13_A0_A1 0x4000681a\r
+#define CYREG_B0_UDB14_A0_A1 0x4000681c\r
+#define CYREG_B0_UDB15_A0_A1 0x4000681e\r
+#define CYREG_B0_UDB00_D0_D1 0x40006840\r
+#define CYREG_B0_UDB01_D0_D1 0x40006842\r
+#define CYREG_B0_UDB02_D0_D1 0x40006844\r
+#define CYREG_B0_UDB03_D0_D1 0x40006846\r
+#define CYREG_B0_UDB04_D0_D1 0x40006848\r
+#define CYREG_B0_UDB05_D0_D1 0x4000684a\r
+#define CYREG_B0_UDB06_D0_D1 0x4000684c\r
+#define CYREG_B0_UDB07_D0_D1 0x4000684e\r
+#define CYREG_B0_UDB08_D0_D1 0x40006850\r
+#define CYREG_B0_UDB09_D0_D1 0x40006852\r
+#define CYREG_B0_UDB10_D0_D1 0x40006854\r
+#define CYREG_B0_UDB11_D0_D1 0x40006856\r
+#define CYREG_B0_UDB12_D0_D1 0x40006858\r
+#define CYREG_B0_UDB13_D0_D1 0x4000685a\r
+#define CYREG_B0_UDB14_D0_D1 0x4000685c\r
+#define CYREG_B0_UDB15_D0_D1 0x4000685e\r
+#define CYREG_B0_UDB00_F0_F1 0x40006880\r
+#define CYREG_B0_UDB01_F0_F1 0x40006882\r
+#define CYREG_B0_UDB02_F0_F1 0x40006884\r
+#define CYREG_B0_UDB03_F0_F1 0x40006886\r
+#define CYREG_B0_UDB04_F0_F1 0x40006888\r
+#define CYREG_B0_UDB05_F0_F1 0x4000688a\r
+#define CYREG_B0_UDB06_F0_F1 0x4000688c\r
+#define CYREG_B0_UDB07_F0_F1 0x4000688e\r
+#define CYREG_B0_UDB08_F0_F1 0x40006890\r
+#define CYREG_B0_UDB09_F0_F1 0x40006892\r
+#define CYREG_B0_UDB10_F0_F1 0x40006894\r
+#define CYREG_B0_UDB11_F0_F1 0x40006896\r
+#define CYREG_B0_UDB12_F0_F1 0x40006898\r
+#define CYREG_B0_UDB13_F0_F1 0x4000689a\r
+#define CYREG_B0_UDB14_F0_F1 0x4000689c\r
+#define CYREG_B0_UDB15_F0_F1 0x4000689e\r
+#define CYREG_B0_UDB00_ST_CTL 0x400068c0\r
+#define CYREG_B0_UDB01_ST_CTL 0x400068c2\r
+#define CYREG_B0_UDB02_ST_CTL 0x400068c4\r
+#define CYREG_B0_UDB03_ST_CTL 0x400068c6\r
+#define CYREG_B0_UDB04_ST_CTL 0x400068c8\r
+#define CYREG_B0_UDB05_ST_CTL 0x400068ca\r
+#define CYREG_B0_UDB06_ST_CTL 0x400068cc\r
+#define CYREG_B0_UDB07_ST_CTL 0x400068ce\r
+#define CYREG_B0_UDB08_ST_CTL 0x400068d0\r
+#define CYREG_B0_UDB09_ST_CTL 0x400068d2\r
+#define CYREG_B0_UDB10_ST_CTL 0x400068d4\r
+#define CYREG_B0_UDB11_ST_CTL 0x400068d6\r
+#define CYREG_B0_UDB12_ST_CTL 0x400068d8\r
+#define CYREG_B0_UDB13_ST_CTL 0x400068da\r
+#define CYREG_B0_UDB14_ST_CTL 0x400068dc\r
+#define CYREG_B0_UDB15_ST_CTL 0x400068de\r
+#define CYREG_B0_UDB00_MSK_ACTL 0x40006900\r
+#define CYREG_B0_UDB01_MSK_ACTL 0x40006902\r
+#define CYREG_B0_UDB02_MSK_ACTL 0x40006904\r
+#define CYREG_B0_UDB03_MSK_ACTL 0x40006906\r
+#define CYREG_B0_UDB04_MSK_ACTL 0x40006908\r
+#define CYREG_B0_UDB05_MSK_ACTL 0x4000690a\r
+#define CYREG_B0_UDB06_MSK_ACTL 0x4000690c\r
+#define CYREG_B0_UDB07_MSK_ACTL 0x4000690e\r
+#define CYREG_B0_UDB08_MSK_ACTL 0x40006910\r
+#define CYREG_B0_UDB09_MSK_ACTL 0x40006912\r
+#define CYREG_B0_UDB10_MSK_ACTL 0x40006914\r
+#define CYREG_B0_UDB11_MSK_ACTL 0x40006916\r
+#define CYREG_B0_UDB12_MSK_ACTL 0x40006918\r
+#define CYREG_B0_UDB13_MSK_ACTL 0x4000691a\r
+#define CYREG_B0_UDB14_MSK_ACTL 0x4000691c\r
+#define CYREG_B0_UDB15_MSK_ACTL 0x4000691e\r
+#define CYREG_B0_UDB00_MC_00 0x40006940\r
+#define CYREG_B0_UDB01_MC_00 0x40006942\r
+#define CYREG_B0_UDB02_MC_00 0x40006944\r
+#define CYREG_B0_UDB03_MC_00 0x40006946\r
+#define CYREG_B0_UDB04_MC_00 0x40006948\r
+#define CYREG_B0_UDB05_MC_00 0x4000694a\r
+#define CYREG_B0_UDB06_MC_00 0x4000694c\r
+#define CYREG_B0_UDB07_MC_00 0x4000694e\r
+#define CYREG_B0_UDB08_MC_00 0x40006950\r
+#define CYREG_B0_UDB09_MC_00 0x40006952\r
+#define CYREG_B0_UDB10_MC_00 0x40006954\r
+#define CYREG_B0_UDB11_MC_00 0x40006956\r
+#define CYREG_B0_UDB12_MC_00 0x40006958\r
+#define CYREG_B0_UDB13_MC_00 0x4000695a\r
+#define CYREG_B0_UDB14_MC_00 0x4000695c\r
+#define CYREG_B0_UDB15_MC_00 0x4000695e\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160\r
+#define CYREG_B1_UDB04_A0_A1 0x40006a08\r
+#define CYREG_B1_UDB05_A0_A1 0x40006a0a\r
+#define CYREG_B1_UDB06_A0_A1 0x40006a0c\r
+#define CYREG_B1_UDB07_A0_A1 0x40006a0e\r
+#define CYREG_B1_UDB08_A0_A1 0x40006a10\r
+#define CYREG_B1_UDB09_A0_A1 0x40006a12\r
+#define CYREG_B1_UDB10_A0_A1 0x40006a14\r
+#define CYREG_B1_UDB11_A0_A1 0x40006a16\r
+#define CYREG_B1_UDB04_D0_D1 0x40006a48\r
+#define CYREG_B1_UDB05_D0_D1 0x40006a4a\r
+#define CYREG_B1_UDB06_D0_D1 0x40006a4c\r
+#define CYREG_B1_UDB07_D0_D1 0x40006a4e\r
+#define CYREG_B1_UDB08_D0_D1 0x40006a50\r
+#define CYREG_B1_UDB09_D0_D1 0x40006a52\r
+#define CYREG_B1_UDB10_D0_D1 0x40006a54\r
+#define CYREG_B1_UDB11_D0_D1 0x40006a56\r
+#define CYREG_B1_UDB04_F0_F1 0x40006a88\r
+#define CYREG_B1_UDB05_F0_F1 0x40006a8a\r
+#define CYREG_B1_UDB06_F0_F1 0x40006a8c\r
+#define CYREG_B1_UDB07_F0_F1 0x40006a8e\r
+#define CYREG_B1_UDB08_F0_F1 0x40006a90\r
+#define CYREG_B1_UDB09_F0_F1 0x40006a92\r
+#define CYREG_B1_UDB10_F0_F1 0x40006a94\r
+#define CYREG_B1_UDB11_F0_F1 0x40006a96\r
+#define CYREG_B1_UDB04_ST_CTL 0x40006ac8\r
+#define CYREG_B1_UDB05_ST_CTL 0x40006aca\r
+#define CYREG_B1_UDB06_ST_CTL 0x40006acc\r
+#define CYREG_B1_UDB07_ST_CTL 0x40006ace\r
+#define CYREG_B1_UDB08_ST_CTL 0x40006ad0\r
+#define CYREG_B1_UDB09_ST_CTL 0x40006ad2\r
+#define CYREG_B1_UDB10_ST_CTL 0x40006ad4\r
+#define CYREG_B1_UDB11_ST_CTL 0x40006ad6\r
+#define CYREG_B1_UDB04_MSK_ACTL 0x40006b08\r
+#define CYREG_B1_UDB05_MSK_ACTL 0x40006b0a\r
+#define CYREG_B1_UDB06_MSK_ACTL 0x40006b0c\r
+#define CYREG_B1_UDB07_MSK_ACTL 0x40006b0e\r
+#define CYREG_B1_UDB08_MSK_ACTL 0x40006b10\r
+#define CYREG_B1_UDB09_MSK_ACTL 0x40006b12\r
+#define CYREG_B1_UDB10_MSK_ACTL 0x40006b14\r
+#define CYREG_B1_UDB11_MSK_ACTL 0x40006b16\r
+#define CYREG_B1_UDB04_MC_00 0x40006b48\r
+#define CYREG_B1_UDB05_MC_00 0x40006b4a\r
+#define CYREG_B1_UDB06_MC_00 0x40006b4c\r
+#define CYREG_B1_UDB07_MC_00 0x40006b4e\r
+#define CYREG_B1_UDB08_MC_00 0x40006b50\r
+#define CYREG_B1_UDB09_MC_00 0x40006b52\r
+#define CYREG_B1_UDB10_MC_00 0x40006b54\r
+#define CYREG_B1_UDB11_MC_00 0x40006b56\r
+#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800\r
+#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075e\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015e\r
+#define CYREG_B0_UDB00_01_A0 0x40006800\r
+#define CYREG_B0_UDB01_02_A0 0x40006802\r
+#define CYREG_B0_UDB02_03_A0 0x40006804\r
+#define CYREG_B0_UDB03_04_A0 0x40006806\r
+#define CYREG_B0_UDB04_05_A0 0x40006808\r
+#define CYREG_B0_UDB05_06_A0 0x4000680a\r
+#define CYREG_B0_UDB06_07_A0 0x4000680c\r
+#define CYREG_B0_UDB07_08_A0 0x4000680e\r
+#define CYREG_B0_UDB08_09_A0 0x40006810\r
+#define CYREG_B0_UDB09_10_A0 0x40006812\r
+#define CYREG_B0_UDB10_11_A0 0x40006814\r
+#define CYREG_B0_UDB11_12_A0 0x40006816\r
+#define CYREG_B0_UDB12_13_A0 0x40006818\r
+#define CYREG_B0_UDB13_14_A0 0x4000681a\r
+#define CYREG_B0_UDB14_15_A0 0x4000681c\r
+#define CYREG_B0_UDB00_01_A1 0x40006820\r
+#define CYREG_B0_UDB01_02_A1 0x40006822\r
+#define CYREG_B0_UDB02_03_A1 0x40006824\r
+#define CYREG_B0_UDB03_04_A1 0x40006826\r
+#define CYREG_B0_UDB04_05_A1 0x40006828\r
+#define CYREG_B0_UDB05_06_A1 0x4000682a\r
+#define CYREG_B0_UDB06_07_A1 0x4000682c\r
+#define CYREG_B0_UDB07_08_A1 0x4000682e\r
+#define CYREG_B0_UDB08_09_A1 0x40006830\r
+#define CYREG_B0_UDB09_10_A1 0x40006832\r
+#define CYREG_B0_UDB10_11_A1 0x40006834\r
+#define CYREG_B0_UDB11_12_A1 0x40006836\r
+#define CYREG_B0_UDB12_13_A1 0x40006838\r
+#define CYREG_B0_UDB13_14_A1 0x4000683a\r
+#define CYREG_B0_UDB14_15_A1 0x4000683c\r
+#define CYREG_B0_UDB00_01_D0 0x40006840\r
+#define CYREG_B0_UDB01_02_D0 0x40006842\r
+#define CYREG_B0_UDB02_03_D0 0x40006844\r
+#define CYREG_B0_UDB03_04_D0 0x40006846\r
+#define CYREG_B0_UDB04_05_D0 0x40006848\r
+#define CYREG_B0_UDB05_06_D0 0x4000684a\r
+#define CYREG_B0_UDB06_07_D0 0x4000684c\r
+#define CYREG_B0_UDB07_08_D0 0x4000684e\r
+#define CYREG_B0_UDB08_09_D0 0x40006850\r
+#define CYREG_B0_UDB09_10_D0 0x40006852\r
+#define CYREG_B0_UDB10_11_D0 0x40006854\r
+#define CYREG_B0_UDB11_12_D0 0x40006856\r
+#define CYREG_B0_UDB12_13_D0 0x40006858\r
+#define CYREG_B0_UDB13_14_D0 0x4000685a\r
+#define CYREG_B0_UDB14_15_D0 0x4000685c\r
+#define CYREG_B0_UDB00_01_D1 0x40006860\r
+#define CYREG_B0_UDB01_02_D1 0x40006862\r
+#define CYREG_B0_UDB02_03_D1 0x40006864\r
+#define CYREG_B0_UDB03_04_D1 0x40006866\r
+#define CYREG_B0_UDB04_05_D1 0x40006868\r
+#define CYREG_B0_UDB05_06_D1 0x4000686a\r
+#define CYREG_B0_UDB06_07_D1 0x4000686c\r
+#define CYREG_B0_UDB07_08_D1 0x4000686e\r
+#define CYREG_B0_UDB08_09_D1 0x40006870\r
+#define CYREG_B0_UDB09_10_D1 0x40006872\r
+#define CYREG_B0_UDB10_11_D1 0x40006874\r
+#define CYREG_B0_UDB11_12_D1 0x40006876\r
+#define CYREG_B0_UDB12_13_D1 0x40006878\r
+#define CYREG_B0_UDB13_14_D1 0x4000687a\r
+#define CYREG_B0_UDB14_15_D1 0x4000687c\r
+#define CYREG_B0_UDB00_01_F0 0x40006880\r
+#define CYREG_B0_UDB01_02_F0 0x40006882\r
+#define CYREG_B0_UDB02_03_F0 0x40006884\r
+#define CYREG_B0_UDB03_04_F0 0x40006886\r
+#define CYREG_B0_UDB04_05_F0 0x40006888\r
+#define CYREG_B0_UDB05_06_F0 0x4000688a\r
+#define CYREG_B0_UDB06_07_F0 0x4000688c\r
+#define CYREG_B0_UDB07_08_F0 0x4000688e\r
+#define CYREG_B0_UDB08_09_F0 0x40006890\r
+#define CYREG_B0_UDB09_10_F0 0x40006892\r
+#define CYREG_B0_UDB10_11_F0 0x40006894\r
+#define CYREG_B0_UDB11_12_F0 0x40006896\r
+#define CYREG_B0_UDB12_13_F0 0x40006898\r
+#define CYREG_B0_UDB13_14_F0 0x4000689a\r
+#define CYREG_B0_UDB14_15_F0 0x4000689c\r
+#define CYREG_B0_UDB00_01_F1 0x400068a0\r
+#define CYREG_B0_UDB01_02_F1 0x400068a2\r
+#define CYREG_B0_UDB02_03_F1 0x400068a4\r
+#define CYREG_B0_UDB03_04_F1 0x400068a6\r
+#define CYREG_B0_UDB04_05_F1 0x400068a8\r
+#define CYREG_B0_UDB05_06_F1 0x400068aa\r
+#define CYREG_B0_UDB06_07_F1 0x400068ac\r
+#define CYREG_B0_UDB07_08_F1 0x400068ae\r
+#define CYREG_B0_UDB08_09_F1 0x400068b0\r
+#define CYREG_B0_UDB09_10_F1 0x400068b2\r
+#define CYREG_B0_UDB10_11_F1 0x400068b4\r
+#define CYREG_B0_UDB11_12_F1 0x400068b6\r
+#define CYREG_B0_UDB12_13_F1 0x400068b8\r
+#define CYREG_B0_UDB13_14_F1 0x400068ba\r
+#define CYREG_B0_UDB14_15_F1 0x400068bc\r
+#define CYREG_B0_UDB00_01_ST 0x400068c0\r
+#define CYREG_B0_UDB01_02_ST 0x400068c2\r
+#define CYREG_B0_UDB02_03_ST 0x400068c4\r
+#define CYREG_B0_UDB03_04_ST 0x400068c6\r
+#define CYREG_B0_UDB04_05_ST 0x400068c8\r
+#define CYREG_B0_UDB05_06_ST 0x400068ca\r
+#define CYREG_B0_UDB06_07_ST 0x400068cc\r
+#define CYREG_B0_UDB07_08_ST 0x400068ce\r
+#define CYREG_B0_UDB08_09_ST 0x400068d0\r
+#define CYREG_B0_UDB09_10_ST 0x400068d2\r
+#define CYREG_B0_UDB10_11_ST 0x400068d4\r
+#define CYREG_B0_UDB11_12_ST 0x400068d6\r
+#define CYREG_B0_UDB12_13_ST 0x400068d8\r
+#define CYREG_B0_UDB13_14_ST 0x400068da\r
+#define CYREG_B0_UDB14_15_ST 0x400068dc\r
+#define CYREG_B0_UDB00_01_CTL 0x400068e0\r
+#define CYREG_B0_UDB01_02_CTL 0x400068e2\r
+#define CYREG_B0_UDB02_03_CTL 0x400068e4\r
+#define CYREG_B0_UDB03_04_CTL 0x400068e6\r
+#define CYREG_B0_UDB04_05_CTL 0x400068e8\r
+#define CYREG_B0_UDB05_06_CTL 0x400068ea\r
+#define CYREG_B0_UDB06_07_CTL 0x400068ec\r
+#define CYREG_B0_UDB07_08_CTL 0x400068ee\r
+#define CYREG_B0_UDB08_09_CTL 0x400068f0\r
+#define CYREG_B0_UDB09_10_CTL 0x400068f2\r
+#define CYREG_B0_UDB10_11_CTL 0x400068f4\r
+#define CYREG_B0_UDB11_12_CTL 0x400068f6\r
+#define CYREG_B0_UDB12_13_CTL 0x400068f8\r
+#define CYREG_B0_UDB13_14_CTL 0x400068fa\r
+#define CYREG_B0_UDB14_15_CTL 0x400068fc\r
+#define CYREG_B0_UDB00_01_MSK 0x40006900\r
+#define CYREG_B0_UDB01_02_MSK 0x40006902\r
+#define CYREG_B0_UDB02_03_MSK 0x40006904\r
+#define CYREG_B0_UDB03_04_MSK 0x40006906\r
+#define CYREG_B0_UDB04_05_MSK 0x40006908\r
+#define CYREG_B0_UDB05_06_MSK 0x4000690a\r
+#define CYREG_B0_UDB06_07_MSK 0x4000690c\r
+#define CYREG_B0_UDB07_08_MSK 0x4000690e\r
+#define CYREG_B0_UDB08_09_MSK 0x40006910\r
+#define CYREG_B0_UDB09_10_MSK 0x40006912\r
+#define CYREG_B0_UDB10_11_MSK 0x40006914\r
+#define CYREG_B0_UDB11_12_MSK 0x40006916\r
+#define CYREG_B0_UDB12_13_MSK 0x40006918\r
+#define CYREG_B0_UDB13_14_MSK 0x4000691a\r
+#define CYREG_B0_UDB14_15_MSK 0x4000691c\r
+#define CYREG_B0_UDB00_01_ACTL 0x40006920\r
+#define CYREG_B0_UDB01_02_ACTL 0x40006922\r
+#define CYREG_B0_UDB02_03_ACTL 0x40006924\r
+#define CYREG_B0_UDB03_04_ACTL 0x40006926\r
+#define CYREG_B0_UDB04_05_ACTL 0x40006928\r
+#define CYREG_B0_UDB05_06_ACTL 0x4000692a\r
+#define CYREG_B0_UDB06_07_ACTL 0x4000692c\r
+#define CYREG_B0_UDB07_08_ACTL 0x4000692e\r
+#define CYREG_B0_UDB08_09_ACTL 0x40006930\r
+#define CYREG_B0_UDB09_10_ACTL 0x40006932\r
+#define CYREG_B0_UDB10_11_ACTL 0x40006934\r
+#define CYREG_B0_UDB11_12_ACTL 0x40006936\r
+#define CYREG_B0_UDB12_13_ACTL 0x40006938\r
+#define CYREG_B0_UDB13_14_ACTL 0x4000693a\r
+#define CYREG_B0_UDB14_15_ACTL 0x4000693c\r
+#define CYREG_B0_UDB00_01_MC 0x40006940\r
+#define CYREG_B0_UDB01_02_MC 0x40006942\r
+#define CYREG_B0_UDB02_03_MC 0x40006944\r
+#define CYREG_B0_UDB03_04_MC 0x40006946\r
+#define CYREG_B0_UDB04_05_MC 0x40006948\r
+#define CYREG_B0_UDB05_06_MC 0x4000694a\r
+#define CYREG_B0_UDB06_07_MC 0x4000694c\r
+#define CYREG_B0_UDB07_08_MC 0x4000694e\r
+#define CYREG_B0_UDB08_09_MC 0x40006950\r
+#define CYREG_B0_UDB09_10_MC 0x40006952\r
+#define CYREG_B0_UDB10_11_MC 0x40006954\r
+#define CYREG_B0_UDB11_12_MC 0x40006956\r
+#define CYREG_B0_UDB12_13_MC 0x40006958\r
+#define CYREG_B0_UDB13_14_MC 0x4000695a\r
+#define CYREG_B0_UDB14_15_MC 0x4000695c\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015e\r
+#define CYREG_B1_UDB04_05_A0 0x40006a08\r
+#define CYREG_B1_UDB05_06_A0 0x40006a0a\r
+#define CYREG_B1_UDB06_07_A0 0x40006a0c\r
+#define CYREG_B1_UDB07_08_A0 0x40006a0e\r
+#define CYREG_B1_UDB08_09_A0 0x40006a10\r
+#define CYREG_B1_UDB09_10_A0 0x40006a12\r
+#define CYREG_B1_UDB10_11_A0 0x40006a14\r
+#define CYREG_B1_UDB11_12_A0 0x40006a16\r
+#define CYREG_B1_UDB04_05_A1 0x40006a28\r
+#define CYREG_B1_UDB05_06_A1 0x40006a2a\r
+#define CYREG_B1_UDB06_07_A1 0x40006a2c\r
+#define CYREG_B1_UDB07_08_A1 0x40006a2e\r
+#define CYREG_B1_UDB08_09_A1 0x40006a30\r
+#define CYREG_B1_UDB09_10_A1 0x40006a32\r
+#define CYREG_B1_UDB10_11_A1 0x40006a34\r
+#define CYREG_B1_UDB11_12_A1 0x40006a36\r
+#define CYREG_B1_UDB04_05_D0 0x40006a48\r
+#define CYREG_B1_UDB05_06_D0 0x40006a4a\r
+#define CYREG_B1_UDB06_07_D0 0x40006a4c\r
+#define CYREG_B1_UDB07_08_D0 0x40006a4e\r
+#define CYREG_B1_UDB08_09_D0 0x40006a50\r
+#define CYREG_B1_UDB09_10_D0 0x40006a52\r
+#define CYREG_B1_UDB10_11_D0 0x40006a54\r
+#define CYREG_B1_UDB11_12_D0 0x40006a56\r
+#define CYREG_B1_UDB04_05_D1 0x40006a68\r
+#define CYREG_B1_UDB05_06_D1 0x40006a6a\r
+#define CYREG_B1_UDB06_07_D1 0x40006a6c\r
+#define CYREG_B1_UDB07_08_D1 0x40006a6e\r
+#define CYREG_B1_UDB08_09_D1 0x40006a70\r
+#define CYREG_B1_UDB09_10_D1 0x40006a72\r
+#define CYREG_B1_UDB10_11_D1 0x40006a74\r
+#define CYREG_B1_UDB11_12_D1 0x40006a76\r
+#define CYREG_B1_UDB04_05_F0 0x40006a88\r
+#define CYREG_B1_UDB05_06_F0 0x40006a8a\r
+#define CYREG_B1_UDB06_07_F0 0x40006a8c\r
+#define CYREG_B1_UDB07_08_F0 0x40006a8e\r
+#define CYREG_B1_UDB08_09_F0 0x40006a90\r
+#define CYREG_B1_UDB09_10_F0 0x40006a92\r
+#define CYREG_B1_UDB10_11_F0 0x40006a94\r
+#define CYREG_B1_UDB11_12_F0 0x40006a96\r
+#define CYREG_B1_UDB04_05_F1 0x40006aa8\r
+#define CYREG_B1_UDB05_06_F1 0x40006aaa\r
+#define CYREG_B1_UDB06_07_F1 0x40006aac\r
+#define CYREG_B1_UDB07_08_F1 0x40006aae\r
+#define CYREG_B1_UDB08_09_F1 0x40006ab0\r
+#define CYREG_B1_UDB09_10_F1 0x40006ab2\r
+#define CYREG_B1_UDB10_11_F1 0x40006ab4\r
+#define CYREG_B1_UDB11_12_F1 0x40006ab6\r
+#define CYREG_B1_UDB04_05_ST 0x40006ac8\r
+#define CYREG_B1_UDB05_06_ST 0x40006aca\r
+#define CYREG_B1_UDB06_07_ST 0x40006acc\r
+#define CYREG_B1_UDB07_08_ST 0x40006ace\r
+#define CYREG_B1_UDB08_09_ST 0x40006ad0\r
+#define CYREG_B1_UDB09_10_ST 0x40006ad2\r
+#define CYREG_B1_UDB10_11_ST 0x40006ad4\r
+#define CYREG_B1_UDB11_12_ST 0x40006ad6\r
+#define CYREG_B1_UDB04_05_CTL 0x40006ae8\r
+#define CYREG_B1_UDB05_06_CTL 0x40006aea\r
+#define CYREG_B1_UDB06_07_CTL 0x40006aec\r
+#define CYREG_B1_UDB07_08_CTL 0x40006aee\r
+#define CYREG_B1_UDB08_09_CTL 0x40006af0\r
+#define CYREG_B1_UDB09_10_CTL 0x40006af2\r
+#define CYREG_B1_UDB10_11_CTL 0x40006af4\r
+#define CYREG_B1_UDB11_12_CTL 0x40006af6\r
+#define CYREG_B1_UDB04_05_MSK 0x40006b08\r
+#define CYREG_B1_UDB05_06_MSK 0x40006b0a\r
+#define CYREG_B1_UDB06_07_MSK 0x40006b0c\r
+#define CYREG_B1_UDB07_08_MSK 0x40006b0e\r
+#define CYREG_B1_UDB08_09_MSK 0x40006b10\r
+#define CYREG_B1_UDB09_10_MSK 0x40006b12\r
+#define CYREG_B1_UDB10_11_MSK 0x40006b14\r
+#define CYREG_B1_UDB11_12_MSK 0x40006b16\r
+#define CYREG_B1_UDB04_05_ACTL 0x40006b28\r
+#define CYREG_B1_UDB05_06_ACTL 0x40006b2a\r
+#define CYREG_B1_UDB06_07_ACTL 0x40006b2c\r
+#define CYREG_B1_UDB07_08_ACTL 0x40006b2e\r
+#define CYREG_B1_UDB08_09_ACTL 0x40006b30\r
+#define CYREG_B1_UDB09_10_ACTL 0x40006b32\r
+#define CYREG_B1_UDB10_11_ACTL 0x40006b34\r
+#define CYREG_B1_UDB11_12_ACTL 0x40006b36\r
+#define CYREG_B1_UDB04_05_MC 0x40006b48\r
+#define CYREG_B1_UDB05_06_MC 0x40006b4a\r
+#define CYREG_B1_UDB06_07_MC 0x40006b4c\r
+#define CYREG_B1_UDB07_08_MC 0x40006b4e\r
+#define CYREG_B1_UDB08_09_MC 0x40006b50\r
+#define CYREG_B1_UDB09_10_MC 0x40006b52\r
+#define CYREG_B1_UDB10_11_MC 0x40006b54\r
+#define CYREG_B1_UDB11_12_MC 0x40006b56\r
+#define CYDEV_PHUB_BASE 0x40007000\r
+#define CYDEV_PHUB_SIZE 0x00000c00\r
+#define CYREG_PHUB_CFG 0x40007000\r
+#define CYREG_PHUB_ERR 0x40007004\r
+#define CYREG_PHUB_ERR_ADR 0x40007008\r
+#define CYDEV_PHUB_CH0_BASE 0x40007010\r
+#define CYDEV_PHUB_CH0_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH0_BASIC_CFG 0x40007010\r
+#define CYREG_PHUB_CH0_ACTION 0x40007014\r
+#define CYREG_PHUB_CH0_BASIC_STATUS 0x40007018\r
+#define CYDEV_PHUB_CH1_BASE 0x40007020\r
+#define CYDEV_PHUB_CH1_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH1_BASIC_CFG 0x40007020\r
+#define CYREG_PHUB_CH1_ACTION 0x40007024\r
+#define CYREG_PHUB_CH1_BASIC_STATUS 0x40007028\r
+#define CYDEV_PHUB_CH2_BASE 0x40007030\r
+#define CYDEV_PHUB_CH2_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH2_BASIC_CFG 0x40007030\r
+#define CYREG_PHUB_CH2_ACTION 0x40007034\r
+#define CYREG_PHUB_CH2_BASIC_STATUS 0x40007038\r
+#define CYDEV_PHUB_CH3_BASE 0x40007040\r
+#define CYDEV_PHUB_CH3_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH3_BASIC_CFG 0x40007040\r
+#define CYREG_PHUB_CH3_ACTION 0x40007044\r
+#define CYREG_PHUB_CH3_BASIC_STATUS 0x40007048\r
+#define CYDEV_PHUB_CH4_BASE 0x40007050\r
+#define CYDEV_PHUB_CH4_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH4_BASIC_CFG 0x40007050\r
+#define CYREG_PHUB_CH4_ACTION 0x40007054\r
+#define CYREG_PHUB_CH4_BASIC_STATUS 0x40007058\r
+#define CYDEV_PHUB_CH5_BASE 0x40007060\r
+#define CYDEV_PHUB_CH5_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH5_BASIC_CFG 0x40007060\r
+#define CYREG_PHUB_CH5_ACTION 0x40007064\r
+#define CYREG_PHUB_CH5_BASIC_STATUS 0x40007068\r
+#define CYDEV_PHUB_CH6_BASE 0x40007070\r
+#define CYDEV_PHUB_CH6_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH6_BASIC_CFG 0x40007070\r
+#define CYREG_PHUB_CH6_ACTION 0x40007074\r
+#define CYREG_PHUB_CH6_BASIC_STATUS 0x40007078\r
+#define CYDEV_PHUB_CH7_BASE 0x40007080\r
+#define CYDEV_PHUB_CH7_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH7_BASIC_CFG 0x40007080\r
+#define CYREG_PHUB_CH7_ACTION 0x40007084\r
+#define CYREG_PHUB_CH7_BASIC_STATUS 0x40007088\r
+#define CYDEV_PHUB_CH8_BASE 0x40007090\r
+#define CYDEV_PHUB_CH8_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH8_BASIC_CFG 0x40007090\r
+#define CYREG_PHUB_CH8_ACTION 0x40007094\r
+#define CYREG_PHUB_CH8_BASIC_STATUS 0x40007098\r
+#define CYDEV_PHUB_CH9_BASE 0x400070a0\r
+#define CYDEV_PHUB_CH9_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH9_BASIC_CFG 0x400070a0\r
+#define CYREG_PHUB_CH9_ACTION 0x400070a4\r
+#define CYREG_PHUB_CH9_BASIC_STATUS 0x400070a8\r
+#define CYDEV_PHUB_CH10_BASE 0x400070b0\r
+#define CYDEV_PHUB_CH10_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH10_BASIC_CFG 0x400070b0\r
+#define CYREG_PHUB_CH10_ACTION 0x400070b4\r
+#define CYREG_PHUB_CH10_BASIC_STATUS 0x400070b8\r
+#define CYDEV_PHUB_CH11_BASE 0x400070c0\r
+#define CYDEV_PHUB_CH11_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH11_BASIC_CFG 0x400070c0\r
+#define CYREG_PHUB_CH11_ACTION 0x400070c4\r
+#define CYREG_PHUB_CH11_BASIC_STATUS 0x400070c8\r
+#define CYDEV_PHUB_CH12_BASE 0x400070d0\r
+#define CYDEV_PHUB_CH12_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH12_BASIC_CFG 0x400070d0\r
+#define CYREG_PHUB_CH12_ACTION 0x400070d4\r
+#define CYREG_PHUB_CH12_BASIC_STATUS 0x400070d8\r
+#define CYDEV_PHUB_CH13_BASE 0x400070e0\r
+#define CYDEV_PHUB_CH13_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH13_BASIC_CFG 0x400070e0\r
+#define CYREG_PHUB_CH13_ACTION 0x400070e4\r
+#define CYREG_PHUB_CH13_BASIC_STATUS 0x400070e8\r
+#define CYDEV_PHUB_CH14_BASE 0x400070f0\r
+#define CYDEV_PHUB_CH14_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH14_BASIC_CFG 0x400070f0\r
+#define CYREG_PHUB_CH14_ACTION 0x400070f4\r
+#define CYREG_PHUB_CH14_BASIC_STATUS 0x400070f8\r
+#define CYDEV_PHUB_CH15_BASE 0x40007100\r
+#define CYDEV_PHUB_CH15_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH15_BASIC_CFG 0x40007100\r
+#define CYREG_PHUB_CH15_ACTION 0x40007104\r
+#define CYREG_PHUB_CH15_BASIC_STATUS 0x40007108\r
+#define CYDEV_PHUB_CH16_BASE 0x40007110\r
+#define CYDEV_PHUB_CH16_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH16_BASIC_CFG 0x40007110\r
+#define CYREG_PHUB_CH16_ACTION 0x40007114\r
+#define CYREG_PHUB_CH16_BASIC_STATUS 0x40007118\r
+#define CYDEV_PHUB_CH17_BASE 0x40007120\r
+#define CYDEV_PHUB_CH17_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH17_BASIC_CFG 0x40007120\r
+#define CYREG_PHUB_CH17_ACTION 0x40007124\r
+#define CYREG_PHUB_CH17_BASIC_STATUS 0x40007128\r
+#define CYDEV_PHUB_CH18_BASE 0x40007130\r
+#define CYDEV_PHUB_CH18_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH18_BASIC_CFG 0x40007130\r
+#define CYREG_PHUB_CH18_ACTION 0x40007134\r
+#define CYREG_PHUB_CH18_BASIC_STATUS 0x40007138\r
+#define CYDEV_PHUB_CH19_BASE 0x40007140\r
+#define CYDEV_PHUB_CH19_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH19_BASIC_CFG 0x40007140\r
+#define CYREG_PHUB_CH19_ACTION 0x40007144\r
+#define CYREG_PHUB_CH19_BASIC_STATUS 0x40007148\r
+#define CYDEV_PHUB_CH20_BASE 0x40007150\r
+#define CYDEV_PHUB_CH20_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH20_BASIC_CFG 0x40007150\r
+#define CYREG_PHUB_CH20_ACTION 0x40007154\r
+#define CYREG_PHUB_CH20_BASIC_STATUS 0x40007158\r
+#define CYDEV_PHUB_CH21_BASE 0x40007160\r
+#define CYDEV_PHUB_CH21_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH21_BASIC_CFG 0x40007160\r
+#define CYREG_PHUB_CH21_ACTION 0x40007164\r
+#define CYREG_PHUB_CH21_BASIC_STATUS 0x40007168\r
+#define CYDEV_PHUB_CH22_BASE 0x40007170\r
+#define CYDEV_PHUB_CH22_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH22_BASIC_CFG 0x40007170\r
+#define CYREG_PHUB_CH22_ACTION 0x40007174\r
+#define CYREG_PHUB_CH22_BASIC_STATUS 0x40007178\r
+#define CYDEV_PHUB_CH23_BASE 0x40007180\r
+#define CYDEV_PHUB_CH23_SIZE 0x0000000c\r
+#define CYREG_PHUB_CH23_BASIC_CFG 0x40007180\r
+#define CYREG_PHUB_CH23_ACTION 0x40007184\r
+#define CYREG_PHUB_CH23_BASIC_STATUS 0x40007188\r
+#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600\r
+#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM0_CFG0 0x40007600\r
+#define CYREG_PHUB_CFGMEM0_CFG1 0x40007604\r
+#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608\r
+#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM1_CFG0 0x40007608\r
+#define CYREG_PHUB_CFGMEM1_CFG1 0x4000760c\r
+#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610\r
+#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM2_CFG0 0x40007610\r
+#define CYREG_PHUB_CFGMEM2_CFG1 0x40007614\r
+#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618\r
+#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM3_CFG0 0x40007618\r
+#define CYREG_PHUB_CFGMEM3_CFG1 0x4000761c\r
+#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620\r
+#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM4_CFG0 0x40007620\r
+#define CYREG_PHUB_CFGMEM4_CFG1 0x40007624\r
+#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628\r
+#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM5_CFG0 0x40007628\r
+#define CYREG_PHUB_CFGMEM5_CFG1 0x4000762c\r
+#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630\r
+#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM6_CFG0 0x40007630\r
+#define CYREG_PHUB_CFGMEM6_CFG1 0x40007634\r
+#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638\r
+#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM7_CFG0 0x40007638\r
+#define CYREG_PHUB_CFGMEM7_CFG1 0x4000763c\r
+#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640\r
+#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM8_CFG0 0x40007640\r
+#define CYREG_PHUB_CFGMEM8_CFG1 0x40007644\r
+#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648\r
+#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM9_CFG0 0x40007648\r
+#define CYREG_PHUB_CFGMEM9_CFG1 0x4000764c\r
+#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650\r
+#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM10_CFG0 0x40007650\r
+#define CYREG_PHUB_CFGMEM10_CFG1 0x40007654\r
+#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658\r
+#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM11_CFG0 0x40007658\r
+#define CYREG_PHUB_CFGMEM11_CFG1 0x4000765c\r
+#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660\r
+#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM12_CFG0 0x40007660\r
+#define CYREG_PHUB_CFGMEM12_CFG1 0x40007664\r
+#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668\r
+#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM13_CFG0 0x40007668\r
+#define CYREG_PHUB_CFGMEM13_CFG1 0x4000766c\r
+#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670\r
+#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM14_CFG0 0x40007670\r
+#define CYREG_PHUB_CFGMEM14_CFG1 0x40007674\r
+#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678\r
+#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM15_CFG0 0x40007678\r
+#define CYREG_PHUB_CFGMEM15_CFG1 0x4000767c\r
+#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680\r
+#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM16_CFG0 0x40007680\r
+#define CYREG_PHUB_CFGMEM16_CFG1 0x40007684\r
+#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688\r
+#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM17_CFG0 0x40007688\r
+#define CYREG_PHUB_CFGMEM17_CFG1 0x4000768c\r
+#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690\r
+#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM18_CFG0 0x40007690\r
+#define CYREG_PHUB_CFGMEM18_CFG1 0x40007694\r
+#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698\r
+#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM19_CFG0 0x40007698\r
+#define CYREG_PHUB_CFGMEM19_CFG1 0x4000769c\r
+#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0\r
+#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM20_CFG0 0x400076a0\r
+#define CYREG_PHUB_CFGMEM20_CFG1 0x400076a4\r
+#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8\r
+#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM21_CFG0 0x400076a8\r
+#define CYREG_PHUB_CFGMEM21_CFG1 0x400076ac\r
+#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0\r
+#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM22_CFG0 0x400076b0\r
+#define CYREG_PHUB_CFGMEM22_CFG1 0x400076b4\r
+#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8\r
+#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008\r
+#define CYREG_PHUB_CFGMEM23_CFG0 0x400076b8\r
+#define CYREG_PHUB_CFGMEM23_CFG1 0x400076bc\r
+#define CYDEV_PHUB_TDMEM0_BASE 0x40007800\r
+#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM0_ORIG_TD0 0x40007800\r
+#define CYREG_PHUB_TDMEM0_ORIG_TD1 0x40007804\r
+#define CYDEV_PHUB_TDMEM1_BASE 0x40007808\r
+#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM1_ORIG_TD0 0x40007808\r
+#define CYREG_PHUB_TDMEM1_ORIG_TD1 0x4000780c\r
+#define CYDEV_PHUB_TDMEM2_BASE 0x40007810\r
+#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM2_ORIG_TD0 0x40007810\r
+#define CYREG_PHUB_TDMEM2_ORIG_TD1 0x40007814\r
+#define CYDEV_PHUB_TDMEM3_BASE 0x40007818\r
+#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM3_ORIG_TD0 0x40007818\r
+#define CYREG_PHUB_TDMEM3_ORIG_TD1 0x4000781c\r
+#define CYDEV_PHUB_TDMEM4_BASE 0x40007820\r
+#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM4_ORIG_TD0 0x40007820\r
+#define CYREG_PHUB_TDMEM4_ORIG_TD1 0x40007824\r
+#define CYDEV_PHUB_TDMEM5_BASE 0x40007828\r
+#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM5_ORIG_TD0 0x40007828\r
+#define CYREG_PHUB_TDMEM5_ORIG_TD1 0x4000782c\r
+#define CYDEV_PHUB_TDMEM6_BASE 0x40007830\r
+#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM6_ORIG_TD0 0x40007830\r
+#define CYREG_PHUB_TDMEM6_ORIG_TD1 0x40007834\r
+#define CYDEV_PHUB_TDMEM7_BASE 0x40007838\r
+#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM7_ORIG_TD0 0x40007838\r
+#define CYREG_PHUB_TDMEM7_ORIG_TD1 0x4000783c\r
+#define CYDEV_PHUB_TDMEM8_BASE 0x40007840\r
+#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM8_ORIG_TD0 0x40007840\r
+#define CYREG_PHUB_TDMEM8_ORIG_TD1 0x40007844\r
+#define CYDEV_PHUB_TDMEM9_BASE 0x40007848\r
+#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM9_ORIG_TD0 0x40007848\r
+#define CYREG_PHUB_TDMEM9_ORIG_TD1 0x4000784c\r
+#define CYDEV_PHUB_TDMEM10_BASE 0x40007850\r
+#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM10_ORIG_TD0 0x40007850\r
+#define CYREG_PHUB_TDMEM10_ORIG_TD1 0x40007854\r
+#define CYDEV_PHUB_TDMEM11_BASE 0x40007858\r
+#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM11_ORIG_TD0 0x40007858\r
+#define CYREG_PHUB_TDMEM11_ORIG_TD1 0x4000785c\r
+#define CYDEV_PHUB_TDMEM12_BASE 0x40007860\r
+#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM12_ORIG_TD0 0x40007860\r
+#define CYREG_PHUB_TDMEM12_ORIG_TD1 0x40007864\r
+#define CYDEV_PHUB_TDMEM13_BASE 0x40007868\r
+#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM13_ORIG_TD0 0x40007868\r
+#define CYREG_PHUB_TDMEM13_ORIG_TD1 0x4000786c\r
+#define CYDEV_PHUB_TDMEM14_BASE 0x40007870\r
+#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM14_ORIG_TD0 0x40007870\r
+#define CYREG_PHUB_TDMEM14_ORIG_TD1 0x40007874\r
+#define CYDEV_PHUB_TDMEM15_BASE 0x40007878\r
+#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM15_ORIG_TD0 0x40007878\r
+#define CYREG_PHUB_TDMEM15_ORIG_TD1 0x4000787c\r
+#define CYDEV_PHUB_TDMEM16_BASE 0x40007880\r
+#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM16_ORIG_TD0 0x40007880\r
+#define CYREG_PHUB_TDMEM16_ORIG_TD1 0x40007884\r
+#define CYDEV_PHUB_TDMEM17_BASE 0x40007888\r
+#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM17_ORIG_TD0 0x40007888\r
+#define CYREG_PHUB_TDMEM17_ORIG_TD1 0x4000788c\r
+#define CYDEV_PHUB_TDMEM18_BASE 0x40007890\r
+#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM18_ORIG_TD0 0x40007890\r
+#define CYREG_PHUB_TDMEM18_ORIG_TD1 0x40007894\r
+#define CYDEV_PHUB_TDMEM19_BASE 0x40007898\r
+#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM19_ORIG_TD0 0x40007898\r
+#define CYREG_PHUB_TDMEM19_ORIG_TD1 0x4000789c\r
+#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0\r
+#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM20_ORIG_TD0 0x400078a0\r
+#define CYREG_PHUB_TDMEM20_ORIG_TD1 0x400078a4\r
+#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8\r
+#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM21_ORIG_TD0 0x400078a8\r
+#define CYREG_PHUB_TDMEM21_ORIG_TD1 0x400078ac\r
+#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0\r
+#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM22_ORIG_TD0 0x400078b0\r
+#define CYREG_PHUB_TDMEM22_ORIG_TD1 0x400078b4\r
+#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8\r
+#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM23_ORIG_TD0 0x400078b8\r
+#define CYREG_PHUB_TDMEM23_ORIG_TD1 0x400078bc\r
+#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0\r
+#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM24_ORIG_TD0 0x400078c0\r
+#define CYREG_PHUB_TDMEM24_ORIG_TD1 0x400078c4\r
+#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8\r
+#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM25_ORIG_TD0 0x400078c8\r
+#define CYREG_PHUB_TDMEM25_ORIG_TD1 0x400078cc\r
+#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0\r
+#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM26_ORIG_TD0 0x400078d0\r
+#define CYREG_PHUB_TDMEM26_ORIG_TD1 0x400078d4\r
+#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8\r
+#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM27_ORIG_TD0 0x400078d8\r
+#define CYREG_PHUB_TDMEM27_ORIG_TD1 0x400078dc\r
+#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0\r
+#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM28_ORIG_TD0 0x400078e0\r
+#define CYREG_PHUB_TDMEM28_ORIG_TD1 0x400078e4\r
+#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8\r
+#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM29_ORIG_TD0 0x400078e8\r
+#define CYREG_PHUB_TDMEM29_ORIG_TD1 0x400078ec\r
+#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0\r
+#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM30_ORIG_TD0 0x400078f0\r
+#define CYREG_PHUB_TDMEM30_ORIG_TD1 0x400078f4\r
+#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8\r
+#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM31_ORIG_TD0 0x400078f8\r
+#define CYREG_PHUB_TDMEM31_ORIG_TD1 0x400078fc\r
+#define CYDEV_PHUB_TDMEM32_BASE 0x40007900\r
+#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM32_ORIG_TD0 0x40007900\r
+#define CYREG_PHUB_TDMEM32_ORIG_TD1 0x40007904\r
+#define CYDEV_PHUB_TDMEM33_BASE 0x40007908\r
+#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM33_ORIG_TD0 0x40007908\r
+#define CYREG_PHUB_TDMEM33_ORIG_TD1 0x4000790c\r
+#define CYDEV_PHUB_TDMEM34_BASE 0x40007910\r
+#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM34_ORIG_TD0 0x40007910\r
+#define CYREG_PHUB_TDMEM34_ORIG_TD1 0x40007914\r
+#define CYDEV_PHUB_TDMEM35_BASE 0x40007918\r
+#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM35_ORIG_TD0 0x40007918\r
+#define CYREG_PHUB_TDMEM35_ORIG_TD1 0x4000791c\r
+#define CYDEV_PHUB_TDMEM36_BASE 0x40007920\r
+#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM36_ORIG_TD0 0x40007920\r
+#define CYREG_PHUB_TDMEM36_ORIG_TD1 0x40007924\r
+#define CYDEV_PHUB_TDMEM37_BASE 0x40007928\r
+#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM37_ORIG_TD0 0x40007928\r
+#define CYREG_PHUB_TDMEM37_ORIG_TD1 0x4000792c\r
+#define CYDEV_PHUB_TDMEM38_BASE 0x40007930\r
+#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM38_ORIG_TD0 0x40007930\r
+#define CYREG_PHUB_TDMEM38_ORIG_TD1 0x40007934\r
+#define CYDEV_PHUB_TDMEM39_BASE 0x40007938\r
+#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM39_ORIG_TD0 0x40007938\r
+#define CYREG_PHUB_TDMEM39_ORIG_TD1 0x4000793c\r
+#define CYDEV_PHUB_TDMEM40_BASE 0x40007940\r
+#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM40_ORIG_TD0 0x40007940\r
+#define CYREG_PHUB_TDMEM40_ORIG_TD1 0x40007944\r
+#define CYDEV_PHUB_TDMEM41_BASE 0x40007948\r
+#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM41_ORIG_TD0 0x40007948\r
+#define CYREG_PHUB_TDMEM41_ORIG_TD1 0x4000794c\r
+#define CYDEV_PHUB_TDMEM42_BASE 0x40007950\r
+#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM42_ORIG_TD0 0x40007950\r
+#define CYREG_PHUB_TDMEM42_ORIG_TD1 0x40007954\r
+#define CYDEV_PHUB_TDMEM43_BASE 0x40007958\r
+#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM43_ORIG_TD0 0x40007958\r
+#define CYREG_PHUB_TDMEM43_ORIG_TD1 0x4000795c\r
+#define CYDEV_PHUB_TDMEM44_BASE 0x40007960\r
+#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM44_ORIG_TD0 0x40007960\r
+#define CYREG_PHUB_TDMEM44_ORIG_TD1 0x40007964\r
+#define CYDEV_PHUB_TDMEM45_BASE 0x40007968\r
+#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM45_ORIG_TD0 0x40007968\r
+#define CYREG_PHUB_TDMEM45_ORIG_TD1 0x4000796c\r
+#define CYDEV_PHUB_TDMEM46_BASE 0x40007970\r
+#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM46_ORIG_TD0 0x40007970\r
+#define CYREG_PHUB_TDMEM46_ORIG_TD1 0x40007974\r
+#define CYDEV_PHUB_TDMEM47_BASE 0x40007978\r
+#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM47_ORIG_TD0 0x40007978\r
+#define CYREG_PHUB_TDMEM47_ORIG_TD1 0x4000797c\r
+#define CYDEV_PHUB_TDMEM48_BASE 0x40007980\r
+#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM48_ORIG_TD0 0x40007980\r
+#define CYREG_PHUB_TDMEM48_ORIG_TD1 0x40007984\r
+#define CYDEV_PHUB_TDMEM49_BASE 0x40007988\r
+#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM49_ORIG_TD0 0x40007988\r
+#define CYREG_PHUB_TDMEM49_ORIG_TD1 0x4000798c\r
+#define CYDEV_PHUB_TDMEM50_BASE 0x40007990\r
+#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM50_ORIG_TD0 0x40007990\r
+#define CYREG_PHUB_TDMEM50_ORIG_TD1 0x40007994\r
+#define CYDEV_PHUB_TDMEM51_BASE 0x40007998\r
+#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM51_ORIG_TD0 0x40007998\r
+#define CYREG_PHUB_TDMEM51_ORIG_TD1 0x4000799c\r
+#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0\r
+#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM52_ORIG_TD0 0x400079a0\r
+#define CYREG_PHUB_TDMEM52_ORIG_TD1 0x400079a4\r
+#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8\r
+#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM53_ORIG_TD0 0x400079a8\r
+#define CYREG_PHUB_TDMEM53_ORIG_TD1 0x400079ac\r
+#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0\r
+#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM54_ORIG_TD0 0x400079b0\r
+#define CYREG_PHUB_TDMEM54_ORIG_TD1 0x400079b4\r
+#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8\r
+#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM55_ORIG_TD0 0x400079b8\r
+#define CYREG_PHUB_TDMEM55_ORIG_TD1 0x400079bc\r
+#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0\r
+#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM56_ORIG_TD0 0x400079c0\r
+#define CYREG_PHUB_TDMEM56_ORIG_TD1 0x400079c4\r
+#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8\r
+#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM57_ORIG_TD0 0x400079c8\r
+#define CYREG_PHUB_TDMEM57_ORIG_TD1 0x400079cc\r
+#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0\r
+#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM58_ORIG_TD0 0x400079d0\r
+#define CYREG_PHUB_TDMEM58_ORIG_TD1 0x400079d4\r
+#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8\r
+#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM59_ORIG_TD0 0x400079d8\r
+#define CYREG_PHUB_TDMEM59_ORIG_TD1 0x400079dc\r
+#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0\r
+#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM60_ORIG_TD0 0x400079e0\r
+#define CYREG_PHUB_TDMEM60_ORIG_TD1 0x400079e4\r
+#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8\r
+#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM61_ORIG_TD0 0x400079e8\r
+#define CYREG_PHUB_TDMEM61_ORIG_TD1 0x400079ec\r
+#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0\r
+#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM62_ORIG_TD0 0x400079f0\r
+#define CYREG_PHUB_TDMEM62_ORIG_TD1 0x400079f4\r
+#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8\r
+#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM63_ORIG_TD0 0x400079f8\r
+#define CYREG_PHUB_TDMEM63_ORIG_TD1 0x400079fc\r
+#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00\r
+#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM64_ORIG_TD0 0x40007a00\r
+#define CYREG_PHUB_TDMEM64_ORIG_TD1 0x40007a04\r
+#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08\r
+#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM65_ORIG_TD0 0x40007a08\r
+#define CYREG_PHUB_TDMEM65_ORIG_TD1 0x40007a0c\r
+#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10\r
+#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM66_ORIG_TD0 0x40007a10\r
+#define CYREG_PHUB_TDMEM66_ORIG_TD1 0x40007a14\r
+#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18\r
+#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM67_ORIG_TD0 0x40007a18\r
+#define CYREG_PHUB_TDMEM67_ORIG_TD1 0x40007a1c\r
+#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20\r
+#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM68_ORIG_TD0 0x40007a20\r
+#define CYREG_PHUB_TDMEM68_ORIG_TD1 0x40007a24\r
+#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28\r
+#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM69_ORIG_TD0 0x40007a28\r
+#define CYREG_PHUB_TDMEM69_ORIG_TD1 0x40007a2c\r
+#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30\r
+#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM70_ORIG_TD0 0x40007a30\r
+#define CYREG_PHUB_TDMEM70_ORIG_TD1 0x40007a34\r
+#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38\r
+#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM71_ORIG_TD0 0x40007a38\r
+#define CYREG_PHUB_TDMEM71_ORIG_TD1 0x40007a3c\r
+#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40\r
+#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM72_ORIG_TD0 0x40007a40\r
+#define CYREG_PHUB_TDMEM72_ORIG_TD1 0x40007a44\r
+#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48\r
+#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM73_ORIG_TD0 0x40007a48\r
+#define CYREG_PHUB_TDMEM73_ORIG_TD1 0x40007a4c\r
+#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50\r
+#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM74_ORIG_TD0 0x40007a50\r
+#define CYREG_PHUB_TDMEM74_ORIG_TD1 0x40007a54\r
+#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58\r
+#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM75_ORIG_TD0 0x40007a58\r
+#define CYREG_PHUB_TDMEM75_ORIG_TD1 0x40007a5c\r
+#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60\r
+#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM76_ORIG_TD0 0x40007a60\r
+#define CYREG_PHUB_TDMEM76_ORIG_TD1 0x40007a64\r
+#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68\r
+#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM77_ORIG_TD0 0x40007a68\r
+#define CYREG_PHUB_TDMEM77_ORIG_TD1 0x40007a6c\r
+#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70\r
+#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM78_ORIG_TD0 0x40007a70\r
+#define CYREG_PHUB_TDMEM78_ORIG_TD1 0x40007a74\r
+#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78\r
+#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM79_ORIG_TD0 0x40007a78\r
+#define CYREG_PHUB_TDMEM79_ORIG_TD1 0x40007a7c\r
+#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80\r
+#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM80_ORIG_TD0 0x40007a80\r
+#define CYREG_PHUB_TDMEM80_ORIG_TD1 0x40007a84\r
+#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88\r
+#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM81_ORIG_TD0 0x40007a88\r
+#define CYREG_PHUB_TDMEM81_ORIG_TD1 0x40007a8c\r
+#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90\r
+#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM82_ORIG_TD0 0x40007a90\r
+#define CYREG_PHUB_TDMEM82_ORIG_TD1 0x40007a94\r
+#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98\r
+#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM83_ORIG_TD0 0x40007a98\r
+#define CYREG_PHUB_TDMEM83_ORIG_TD1 0x40007a9c\r
+#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0\r
+#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM84_ORIG_TD0 0x40007aa0\r
+#define CYREG_PHUB_TDMEM84_ORIG_TD1 0x40007aa4\r
+#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8\r
+#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM85_ORIG_TD0 0x40007aa8\r
+#define CYREG_PHUB_TDMEM85_ORIG_TD1 0x40007aac\r
+#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0\r
+#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM86_ORIG_TD0 0x40007ab0\r
+#define CYREG_PHUB_TDMEM86_ORIG_TD1 0x40007ab4\r
+#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8\r
+#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM87_ORIG_TD0 0x40007ab8\r
+#define CYREG_PHUB_TDMEM87_ORIG_TD1 0x40007abc\r
+#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0\r
+#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM88_ORIG_TD0 0x40007ac0\r
+#define CYREG_PHUB_TDMEM88_ORIG_TD1 0x40007ac4\r
+#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8\r
+#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM89_ORIG_TD0 0x40007ac8\r
+#define CYREG_PHUB_TDMEM89_ORIG_TD1 0x40007acc\r
+#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0\r
+#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM90_ORIG_TD0 0x40007ad0\r
+#define CYREG_PHUB_TDMEM90_ORIG_TD1 0x40007ad4\r
+#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8\r
+#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM91_ORIG_TD0 0x40007ad8\r
+#define CYREG_PHUB_TDMEM91_ORIG_TD1 0x40007adc\r
+#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0\r
+#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM92_ORIG_TD0 0x40007ae0\r
+#define CYREG_PHUB_TDMEM92_ORIG_TD1 0x40007ae4\r
+#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8\r
+#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM93_ORIG_TD0 0x40007ae8\r
+#define CYREG_PHUB_TDMEM93_ORIG_TD1 0x40007aec\r
+#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0\r
+#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM94_ORIG_TD0 0x40007af0\r
+#define CYREG_PHUB_TDMEM94_ORIG_TD1 0x40007af4\r
+#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8\r
+#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM95_ORIG_TD0 0x40007af8\r
+#define CYREG_PHUB_TDMEM95_ORIG_TD1 0x40007afc\r
+#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00\r
+#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM96_ORIG_TD0 0x40007b00\r
+#define CYREG_PHUB_TDMEM96_ORIG_TD1 0x40007b04\r
+#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08\r
+#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM97_ORIG_TD0 0x40007b08\r
+#define CYREG_PHUB_TDMEM97_ORIG_TD1 0x40007b0c\r
+#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10\r
+#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM98_ORIG_TD0 0x40007b10\r
+#define CYREG_PHUB_TDMEM98_ORIG_TD1 0x40007b14\r
+#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18\r
+#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM99_ORIG_TD0 0x40007b18\r
+#define CYREG_PHUB_TDMEM99_ORIG_TD1 0x40007b1c\r
+#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20\r
+#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM100_ORIG_TD0 0x40007b20\r
+#define CYREG_PHUB_TDMEM100_ORIG_TD1 0x40007b24\r
+#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28\r
+#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM101_ORIG_TD0 0x40007b28\r
+#define CYREG_PHUB_TDMEM101_ORIG_TD1 0x40007b2c\r
+#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30\r
+#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM102_ORIG_TD0 0x40007b30\r
+#define CYREG_PHUB_TDMEM102_ORIG_TD1 0x40007b34\r
+#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38\r
+#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM103_ORIG_TD0 0x40007b38\r
+#define CYREG_PHUB_TDMEM103_ORIG_TD1 0x40007b3c\r
+#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40\r
+#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM104_ORIG_TD0 0x40007b40\r
+#define CYREG_PHUB_TDMEM104_ORIG_TD1 0x40007b44\r
+#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48\r
+#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM105_ORIG_TD0 0x40007b48\r
+#define CYREG_PHUB_TDMEM105_ORIG_TD1 0x40007b4c\r
+#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50\r
+#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM106_ORIG_TD0 0x40007b50\r
+#define CYREG_PHUB_TDMEM106_ORIG_TD1 0x40007b54\r
+#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58\r
+#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM107_ORIG_TD0 0x40007b58\r
+#define CYREG_PHUB_TDMEM107_ORIG_TD1 0x40007b5c\r
+#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60\r
+#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM108_ORIG_TD0 0x40007b60\r
+#define CYREG_PHUB_TDMEM108_ORIG_TD1 0x40007b64\r
+#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68\r
+#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM109_ORIG_TD0 0x40007b68\r
+#define CYREG_PHUB_TDMEM109_ORIG_TD1 0x40007b6c\r
+#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70\r
+#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM110_ORIG_TD0 0x40007b70\r
+#define CYREG_PHUB_TDMEM110_ORIG_TD1 0x40007b74\r
+#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78\r
+#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM111_ORIG_TD0 0x40007b78\r
+#define CYREG_PHUB_TDMEM111_ORIG_TD1 0x40007b7c\r
+#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80\r
+#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM112_ORIG_TD0 0x40007b80\r
+#define CYREG_PHUB_TDMEM112_ORIG_TD1 0x40007b84\r
+#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88\r
+#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM113_ORIG_TD0 0x40007b88\r
+#define CYREG_PHUB_TDMEM113_ORIG_TD1 0x40007b8c\r
+#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90\r
+#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM114_ORIG_TD0 0x40007b90\r
+#define CYREG_PHUB_TDMEM114_ORIG_TD1 0x40007b94\r
+#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98\r
+#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM115_ORIG_TD0 0x40007b98\r
+#define CYREG_PHUB_TDMEM115_ORIG_TD1 0x40007b9c\r
+#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0\r
+#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM116_ORIG_TD0 0x40007ba0\r
+#define CYREG_PHUB_TDMEM116_ORIG_TD1 0x40007ba4\r
+#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8\r
+#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM117_ORIG_TD0 0x40007ba8\r
+#define CYREG_PHUB_TDMEM117_ORIG_TD1 0x40007bac\r
+#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0\r
+#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM118_ORIG_TD0 0x40007bb0\r
+#define CYREG_PHUB_TDMEM118_ORIG_TD1 0x40007bb4\r
+#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8\r
+#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM119_ORIG_TD0 0x40007bb8\r
+#define CYREG_PHUB_TDMEM119_ORIG_TD1 0x40007bbc\r
+#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0\r
+#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM120_ORIG_TD0 0x40007bc0\r
+#define CYREG_PHUB_TDMEM120_ORIG_TD1 0x40007bc4\r
+#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8\r
+#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM121_ORIG_TD0 0x40007bc8\r
+#define CYREG_PHUB_TDMEM121_ORIG_TD1 0x40007bcc\r
+#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0\r
+#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM122_ORIG_TD0 0x40007bd0\r
+#define CYREG_PHUB_TDMEM122_ORIG_TD1 0x40007bd4\r
+#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8\r
+#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM123_ORIG_TD0 0x40007bd8\r
+#define CYREG_PHUB_TDMEM123_ORIG_TD1 0x40007bdc\r
+#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0\r
+#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM124_ORIG_TD0 0x40007be0\r
+#define CYREG_PHUB_TDMEM124_ORIG_TD1 0x40007be4\r
+#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8\r
+#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM125_ORIG_TD0 0x40007be8\r
+#define CYREG_PHUB_TDMEM125_ORIG_TD1 0x40007bec\r
+#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0\r
+#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM126_ORIG_TD0 0x40007bf0\r
+#define CYREG_PHUB_TDMEM126_ORIG_TD1 0x40007bf4\r
+#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8\r
+#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008\r
+#define CYREG_PHUB_TDMEM127_ORIG_TD0 0x40007bf8\r
+#define CYREG_PHUB_TDMEM127_ORIG_TD1 0x40007bfc\r
+#define CYDEV_EE_BASE 0x40008000\r
+#define CYDEV_EE_SIZE 0x00000800\r
+#define CYREG_EE_DATA_MBASE 0x40008000\r
+#define CYREG_EE_DATA_MSIZE 0x00000800\r
+#define CYDEV_CAN0_BASE 0x4000a000\r
+#define CYDEV_CAN0_SIZE 0x000002a0\r
+#define CYDEV_CAN0_CSR_BASE 0x4000a000\r
+#define CYDEV_CAN0_CSR_SIZE 0x00000018\r
+#define CYREG_CAN0_CSR_INT_SR 0x4000a000\r
+#define CYREG_CAN0_CSR_INT_EN 0x4000a004\r
+#define CYREG_CAN0_CSR_BUF_SR 0x4000a008\r
+#define CYREG_CAN0_CSR_ERR_SR 0x4000a00c\r
+#define CYREG_CAN0_CSR_CMD 0x4000a010\r
+#define CYREG_CAN0_CSR_CFG 0x4000a014\r
+#define CYDEV_CAN0_TX0_BASE 0x4000a020\r
+#define CYDEV_CAN0_TX0_SIZE 0x00000010\r
+#define CYREG_CAN0_TX0_CMD 0x4000a020\r
+#define CYREG_CAN0_TX0_ID 0x4000a024\r
+#define CYREG_CAN0_TX0_DH 0x4000a028\r
+#define CYREG_CAN0_TX0_DL 0x4000a02c\r
+#define CYDEV_CAN0_TX1_BASE 0x4000a030\r
+#define CYDEV_CAN0_TX1_SIZE 0x00000010\r
+#define CYREG_CAN0_TX1_CMD 0x4000a030\r
+#define CYREG_CAN0_TX1_ID 0x4000a034\r
+#define CYREG_CAN0_TX1_DH 0x4000a038\r
+#define CYREG_CAN0_TX1_DL 0x4000a03c\r
+#define CYDEV_CAN0_TX2_BASE 0x4000a040\r
+#define CYDEV_CAN0_TX2_SIZE 0x00000010\r
+#define CYREG_CAN0_TX2_CMD 0x4000a040\r
+#define CYREG_CAN0_TX2_ID 0x4000a044\r
+#define CYREG_CAN0_TX2_DH 0x4000a048\r
+#define CYREG_CAN0_TX2_DL 0x4000a04c\r
+#define CYDEV_CAN0_TX3_BASE 0x4000a050\r
+#define CYDEV_CAN0_TX3_SIZE 0x00000010\r
+#define CYREG_CAN0_TX3_CMD 0x4000a050\r
+#define CYREG_CAN0_TX3_ID 0x4000a054\r
+#define CYREG_CAN0_TX3_DH 0x4000a058\r
+#define CYREG_CAN0_TX3_DL 0x4000a05c\r
+#define CYDEV_CAN0_TX4_BASE 0x4000a060\r
+#define CYDEV_CAN0_TX4_SIZE 0x00000010\r
+#define CYREG_CAN0_TX4_CMD 0x4000a060\r
+#define CYREG_CAN0_TX4_ID 0x4000a064\r
+#define CYREG_CAN0_TX4_DH 0x4000a068\r
+#define CYREG_CAN0_TX4_DL 0x4000a06c\r
+#define CYDEV_CAN0_TX5_BASE 0x4000a070\r
+#define CYDEV_CAN0_TX5_SIZE 0x00000010\r
+#define CYREG_CAN0_TX5_CMD 0x4000a070\r
+#define CYREG_CAN0_TX5_ID 0x4000a074\r
+#define CYREG_CAN0_TX5_DH 0x4000a078\r
+#define CYREG_CAN0_TX5_DL 0x4000a07c\r
+#define CYDEV_CAN0_TX6_BASE 0x4000a080\r
+#define CYDEV_CAN0_TX6_SIZE 0x00000010\r
+#define CYREG_CAN0_TX6_CMD 0x4000a080\r
+#define CYREG_CAN0_TX6_ID 0x4000a084\r
+#define CYREG_CAN0_TX6_DH 0x4000a088\r
+#define CYREG_CAN0_TX6_DL 0x4000a08c\r
+#define CYDEV_CAN0_TX7_BASE 0x4000a090\r
+#define CYDEV_CAN0_TX7_SIZE 0x00000010\r
+#define CYREG_CAN0_TX7_CMD 0x4000a090\r
+#define CYREG_CAN0_TX7_ID 0x4000a094\r
+#define CYREG_CAN0_TX7_DH 0x4000a098\r
+#define CYREG_CAN0_TX7_DL 0x4000a09c\r
+#define CYDEV_CAN0_RX0_BASE 0x4000a0a0\r
+#define CYDEV_CAN0_RX0_SIZE 0x00000020\r
+#define CYREG_CAN0_RX0_CMD 0x4000a0a0\r
+#define CYREG_CAN0_RX0_ID 0x4000a0a4\r
+#define CYREG_CAN0_RX0_DH 0x4000a0a8\r
+#define CYREG_CAN0_RX0_DL 0x4000a0ac\r
+#define CYREG_CAN0_RX0_AMR 0x4000a0b0\r
+#define CYREG_CAN0_RX0_ACR 0x4000a0b4\r
+#define CYREG_CAN0_RX0_AMRD 0x4000a0b8\r
+#define CYREG_CAN0_RX0_ACRD 0x4000a0bc\r
+#define CYDEV_CAN0_RX1_BASE 0x4000a0c0\r
+#define CYDEV_CAN0_RX1_SIZE 0x00000020\r
+#define CYREG_CAN0_RX1_CMD 0x4000a0c0\r
+#define CYREG_CAN0_RX1_ID 0x4000a0c4\r
+#define CYREG_CAN0_RX1_DH 0x4000a0c8\r
+#define CYREG_CAN0_RX1_DL 0x4000a0cc\r
+#define CYREG_CAN0_RX1_AMR 0x4000a0d0\r
+#define CYREG_CAN0_RX1_ACR 0x4000a0d4\r
+#define CYREG_CAN0_RX1_AMRD 0x4000a0d8\r
+#define CYREG_CAN0_RX1_ACRD 0x4000a0dc\r
+#define CYDEV_CAN0_RX2_BASE 0x4000a0e0\r
+#define CYDEV_CAN0_RX2_SIZE 0x00000020\r
+#define CYREG_CAN0_RX2_CMD 0x4000a0e0\r
+#define CYREG_CAN0_RX2_ID 0x4000a0e4\r
+#define CYREG_CAN0_RX2_DH 0x4000a0e8\r
+#define CYREG_CAN0_RX2_DL 0x4000a0ec\r
+#define CYREG_CAN0_RX2_AMR 0x4000a0f0\r
+#define CYREG_CAN0_RX2_ACR 0x4000a0f4\r
+#define CYREG_CAN0_RX2_AMRD 0x4000a0f8\r
+#define CYREG_CAN0_RX2_ACRD 0x4000a0fc\r
+#define CYDEV_CAN0_RX3_BASE 0x4000a100\r
+#define CYDEV_CAN0_RX3_SIZE 0x00000020\r
+#define CYREG_CAN0_RX3_CMD 0x4000a100\r
+#define CYREG_CAN0_RX3_ID 0x4000a104\r
+#define CYREG_CAN0_RX3_DH 0x4000a108\r
+#define CYREG_CAN0_RX3_DL 0x4000a10c\r
+#define CYREG_CAN0_RX3_AMR 0x4000a110\r
+#define CYREG_CAN0_RX3_ACR 0x4000a114\r
+#define CYREG_CAN0_RX3_AMRD 0x4000a118\r
+#define CYREG_CAN0_RX3_ACRD 0x4000a11c\r
+#define CYDEV_CAN0_RX4_BASE 0x4000a120\r
+#define CYDEV_CAN0_RX4_SIZE 0x00000020\r
+#define CYREG_CAN0_RX4_CMD 0x4000a120\r
+#define CYREG_CAN0_RX4_ID 0x4000a124\r
+#define CYREG_CAN0_RX4_DH 0x4000a128\r
+#define CYREG_CAN0_RX4_DL 0x4000a12c\r
+#define CYREG_CAN0_RX4_AMR 0x4000a130\r
+#define CYREG_CAN0_RX4_ACR 0x4000a134\r
+#define CYREG_CAN0_RX4_AMRD 0x4000a138\r
+#define CYREG_CAN0_RX4_ACRD 0x4000a13c\r
+#define CYDEV_CAN0_RX5_BASE 0x4000a140\r
+#define CYDEV_CAN0_RX5_SIZE 0x00000020\r
+#define CYREG_CAN0_RX5_CMD 0x4000a140\r
+#define CYREG_CAN0_RX5_ID 0x4000a144\r
+#define CYREG_CAN0_RX5_DH 0x4000a148\r
+#define CYREG_CAN0_RX5_DL 0x4000a14c\r
+#define CYREG_CAN0_RX5_AMR 0x4000a150\r
+#define CYREG_CAN0_RX5_ACR 0x4000a154\r
+#define CYREG_CAN0_RX5_AMRD 0x4000a158\r
+#define CYREG_CAN0_RX5_ACRD 0x4000a15c\r
+#define CYDEV_CAN0_RX6_BASE 0x4000a160\r
+#define CYDEV_CAN0_RX6_SIZE 0x00000020\r
+#define CYREG_CAN0_RX6_CMD 0x4000a160\r
+#define CYREG_CAN0_RX6_ID 0x4000a164\r
+#define CYREG_CAN0_RX6_DH 0x4000a168\r
+#define CYREG_CAN0_RX6_DL 0x4000a16c\r
+#define CYREG_CAN0_RX6_AMR 0x4000a170\r
+#define CYREG_CAN0_RX6_ACR 0x4000a174\r
+#define CYREG_CAN0_RX6_AMRD 0x4000a178\r
+#define CYREG_CAN0_RX6_ACRD 0x4000a17c\r
+#define CYDEV_CAN0_RX7_BASE 0x4000a180\r
+#define CYDEV_CAN0_RX7_SIZE 0x00000020\r
+#define CYREG_CAN0_RX7_CMD 0x4000a180\r
+#define CYREG_CAN0_RX7_ID 0x4000a184\r
+#define CYREG_CAN0_RX7_DH 0x4000a188\r
+#define CYREG_CAN0_RX7_DL 0x4000a18c\r
+#define CYREG_CAN0_RX7_AMR 0x4000a190\r
+#define CYREG_CAN0_RX7_ACR 0x4000a194\r
+#define CYREG_CAN0_RX7_AMRD 0x4000a198\r
+#define CYREG_CAN0_RX7_ACRD 0x4000a19c\r
+#define CYDEV_CAN0_RX8_BASE 0x4000a1a0\r
+#define CYDEV_CAN0_RX8_SIZE 0x00000020\r
+#define CYREG_CAN0_RX8_CMD 0x4000a1a0\r
+#define CYREG_CAN0_RX8_ID 0x4000a1a4\r
+#define CYREG_CAN0_RX8_DH 0x4000a1a8\r
+#define CYREG_CAN0_RX8_DL 0x4000a1ac\r
+#define CYREG_CAN0_RX8_AMR 0x4000a1b0\r
+#define CYREG_CAN0_RX8_ACR 0x4000a1b4\r
+#define CYREG_CAN0_RX8_AMRD 0x4000a1b8\r
+#define CYREG_CAN0_RX8_ACRD 0x4000a1bc\r
+#define CYDEV_CAN0_RX9_BASE 0x4000a1c0\r
+#define CYDEV_CAN0_RX9_SIZE 0x00000020\r
+#define CYREG_CAN0_RX9_CMD 0x4000a1c0\r
+#define CYREG_CAN0_RX9_ID 0x4000a1c4\r
+#define CYREG_CAN0_RX9_DH 0x4000a1c8\r
+#define CYREG_CAN0_RX9_DL 0x4000a1cc\r
+#define CYREG_CAN0_RX9_AMR 0x4000a1d0\r
+#define CYREG_CAN0_RX9_ACR 0x4000a1d4\r
+#define CYREG_CAN0_RX9_AMRD 0x4000a1d8\r
+#define CYREG_CAN0_RX9_ACRD 0x4000a1dc\r
+#define CYDEV_CAN0_RX10_BASE 0x4000a1e0\r
+#define CYDEV_CAN0_RX10_SIZE 0x00000020\r
+#define CYREG_CAN0_RX10_CMD 0x4000a1e0\r
+#define CYREG_CAN0_RX10_ID 0x4000a1e4\r
+#define CYREG_CAN0_RX10_DH 0x4000a1e8\r
+#define CYREG_CAN0_RX10_DL 0x4000a1ec\r
+#define CYREG_CAN0_RX10_AMR 0x4000a1f0\r
+#define CYREG_CAN0_RX10_ACR 0x4000a1f4\r
+#define CYREG_CAN0_RX10_AMRD 0x4000a1f8\r
+#define CYREG_CAN0_RX10_ACRD 0x4000a1fc\r
+#define CYDEV_CAN0_RX11_BASE 0x4000a200\r
+#define CYDEV_CAN0_RX11_SIZE 0x00000020\r
+#define CYREG_CAN0_RX11_CMD 0x4000a200\r
+#define CYREG_CAN0_RX11_ID 0x4000a204\r
+#define CYREG_CAN0_RX11_DH 0x4000a208\r
+#define CYREG_CAN0_RX11_DL 0x4000a20c\r
+#define CYREG_CAN0_RX11_AMR 0x4000a210\r
+#define CYREG_CAN0_RX11_ACR 0x4000a214\r
+#define CYREG_CAN0_RX11_AMRD 0x4000a218\r
+#define CYREG_CAN0_RX11_ACRD 0x4000a21c\r
+#define CYDEV_CAN0_RX12_BASE 0x4000a220\r
+#define CYDEV_CAN0_RX12_SIZE 0x00000020\r
+#define CYREG_CAN0_RX12_CMD 0x4000a220\r
+#define CYREG_CAN0_RX12_ID 0x4000a224\r
+#define CYREG_CAN0_RX12_DH 0x4000a228\r
+#define CYREG_CAN0_RX12_DL 0x4000a22c\r
+#define CYREG_CAN0_RX12_AMR 0x4000a230\r
+#define CYREG_CAN0_RX12_ACR 0x4000a234\r
+#define CYREG_CAN0_RX12_AMRD 0x4000a238\r
+#define CYREG_CAN0_RX12_ACRD 0x4000a23c\r
+#define CYDEV_CAN0_RX13_BASE 0x4000a240\r
+#define CYDEV_CAN0_RX13_SIZE 0x00000020\r
+#define CYREG_CAN0_RX13_CMD 0x4000a240\r
+#define CYREG_CAN0_RX13_ID 0x4000a244\r
+#define CYREG_CAN0_RX13_DH 0x4000a248\r
+#define CYREG_CAN0_RX13_DL 0x4000a24c\r
+#define CYREG_CAN0_RX13_AMR 0x4000a250\r
+#define CYREG_CAN0_RX13_ACR 0x4000a254\r
+#define CYREG_CAN0_RX13_AMRD 0x4000a258\r
+#define CYREG_CAN0_RX13_ACRD 0x4000a25c\r
+#define CYDEV_CAN0_RX14_BASE 0x4000a260\r
+#define CYDEV_CAN0_RX14_SIZE 0x00000020\r
+#define CYREG_CAN0_RX14_CMD 0x4000a260\r
+#define CYREG_CAN0_RX14_ID 0x4000a264\r
+#define CYREG_CAN0_RX14_DH 0x4000a268\r
+#define CYREG_CAN0_RX14_DL 0x4000a26c\r
+#define CYREG_CAN0_RX14_AMR 0x4000a270\r
+#define CYREG_CAN0_RX14_ACR 0x4000a274\r
+#define CYREG_CAN0_RX14_AMRD 0x4000a278\r
+#define CYREG_CAN0_RX14_ACRD 0x4000a27c\r
+#define CYDEV_CAN0_RX15_BASE 0x4000a280\r
+#define CYDEV_CAN0_RX15_SIZE 0x00000020\r
+#define CYREG_CAN0_RX15_CMD 0x4000a280\r
+#define CYREG_CAN0_RX15_ID 0x4000a284\r
+#define CYREG_CAN0_RX15_DH 0x4000a288\r
+#define CYREG_CAN0_RX15_DL 0x4000a28c\r
+#define CYREG_CAN0_RX15_AMR 0x4000a290\r
+#define CYREG_CAN0_RX15_ACR 0x4000a294\r
+#define CYREG_CAN0_RX15_AMRD 0x4000a298\r
+#define CYREG_CAN0_RX15_ACRD 0x4000a29c\r
+#define CYDEV_DFB0_BASE 0x4000c000\r
+#define CYDEV_DFB0_SIZE 0x000007b5\r
+#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000\r
+#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200\r
+#define CYREG_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000\r
+#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200\r
+#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200\r
+#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200\r
+#define CYREG_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200\r
+#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200\r
+#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400\r
+#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100\r
+#define CYREG_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400\r
+#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100\r
+#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500\r
+#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100\r
+#define CYREG_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500\r
+#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100\r
+#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600\r
+#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100\r
+#define CYREG_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600\r
+#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100\r
+#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700\r
+#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040\r
+#define CYREG_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700\r
+#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040\r
+#define CYREG_DFB0_CR 0x4000c780\r
+#define CYREG_DFB0_SR 0x4000c784\r
+#define CYREG_DFB0_RAM_EN 0x4000c788\r
+#define CYREG_DFB0_RAM_DIR 0x4000c78c\r
+#define CYREG_DFB0_SEMA 0x4000c790\r
+#define CYREG_DFB0_DSI_CTRL 0x4000c794\r
+#define CYREG_DFB0_INT_CTRL 0x4000c798\r
+#define CYREG_DFB0_DMA_CTRL 0x4000c79c\r
+#define CYREG_DFB0_STAGEA 0x4000c7a0\r
+#define CYREG_DFB0_STAGEAM 0x4000c7a1\r
+#define CYREG_DFB0_STAGEAH 0x4000c7a2\r
+#define CYREG_DFB0_STAGEB 0x4000c7a4\r
+#define CYREG_DFB0_STAGEBM 0x4000c7a5\r
+#define CYREG_DFB0_STAGEBH 0x4000c7a6\r
+#define CYREG_DFB0_HOLDA 0x4000c7a8\r
+#define CYREG_DFB0_HOLDAM 0x4000c7a9\r
+#define CYREG_DFB0_HOLDAH 0x4000c7aa\r
+#define CYREG_DFB0_HOLDAS 0x4000c7ab\r
+#define CYREG_DFB0_HOLDB 0x4000c7ac\r
+#define CYREG_DFB0_HOLDBM 0x4000c7ad\r
+#define CYREG_DFB0_HOLDBH 0x4000c7ae\r
+#define CYREG_DFB0_HOLDBS 0x4000c7af\r
+#define CYREG_DFB0_COHER 0x4000c7b0\r
+#define CYREG_DFB0_DALIGN 0x4000c7b4\r
+#define CYDEV_UCFG_BASE 0x40010000\r
+#define CYDEV_UCFG_SIZE 0x00005040\r
+#define CYDEV_UCFG_B0_BASE 0x40010000\r
+#define CYDEV_UCFG_B0_SIZE 0x00000fef\r
+#define CYDEV_UCFG_B0_P0_BASE 0x40010000\r
+#define CYDEV_UCFG_B0_P0_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000\r
+#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070\r
+#define CYREG_B0_P0_U0_PLD_IT0 0x40010000\r
+#define CYREG_B0_P0_U0_PLD_IT1 0x40010004\r
+#define CYREG_B0_P0_U0_PLD_IT2 0x40010008\r
+#define CYREG_B0_P0_U0_PLD_IT3 0x4001000c\r
+#define CYREG_B0_P0_U0_PLD_IT4 0x40010010\r
+#define CYREG_B0_P0_U0_PLD_IT5 0x40010014\r
+#define CYREG_B0_P0_U0_PLD_IT6 0x40010018\r
+#define CYREG_B0_P0_U0_PLD_IT7 0x4001001c\r
+#define CYREG_B0_P0_U0_PLD_IT8 0x40010020\r
+#define CYREG_B0_P0_U0_PLD_IT9 0x40010024\r
+#define CYREG_B0_P0_U0_PLD_IT10 0x40010028\r
+#define CYREG_B0_P0_U0_PLD_IT11 0x4001002c\r
+#define CYREG_B0_P0_U0_PLD_ORT0 0x40010030\r
+#define CYREG_B0_P0_U0_PLD_ORT1 0x40010032\r
+#define CYREG_B0_P0_U0_PLD_ORT2 0x40010034\r
+#define CYREG_B0_P0_U0_PLD_ORT3 0x40010036\r
+#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038\r
+#define CYREG_B0_P0_U0_MC_CFG_XORFB 0x4001003a\r
+#define CYREG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003c\r
+#define CYREG_B0_P0_U0_MC_CFG_BYPASS 0x4001003e\r
+#define CYREG_B0_P0_U0_CFG0 0x40010040\r
+#define CYREG_B0_P0_U0_CFG1 0x40010041\r
+#define CYREG_B0_P0_U0_CFG2 0x40010042\r
+#define CYREG_B0_P0_U0_CFG3 0x40010043\r
+#define CYREG_B0_P0_U0_CFG4 0x40010044\r
+#define CYREG_B0_P0_U0_CFG5 0x40010045\r
+#define CYREG_B0_P0_U0_CFG6 0x40010046\r
+#define CYREG_B0_P0_U0_CFG7 0x40010047\r
+#define CYREG_B0_P0_U0_CFG8 0x40010048\r
+#define CYREG_B0_P0_U0_CFG9 0x40010049\r
+#define CYREG_B0_P0_U0_CFG10 0x4001004a\r
+#define CYREG_B0_P0_U0_CFG11 0x4001004b\r
+#define CYREG_B0_P0_U0_CFG12 0x4001004c\r
+#define CYREG_B0_P0_U0_CFG13 0x4001004d\r
+#define CYREG_B0_P0_U0_CFG14 0x4001004e\r
+#define CYREG_B0_P0_U0_CFG15 0x4001004f\r
+#define CYREG_B0_P0_U0_CFG16 0x40010050\r
+#define CYREG_B0_P0_U0_CFG17 0x40010051\r
+#define CYREG_B0_P0_U0_CFG18 0x40010052\r
+#define CYREG_B0_P0_U0_CFG19 0x40010053\r
+#define CYREG_B0_P0_U0_CFG20 0x40010054\r
+#define CYREG_B0_P0_U0_CFG21 0x40010055\r
+#define CYREG_B0_P0_U0_CFG22 0x40010056\r
+#define CYREG_B0_P0_U0_CFG23 0x40010057\r
+#define CYREG_B0_P0_U0_CFG24 0x40010058\r
+#define CYREG_B0_P0_U0_CFG25 0x40010059\r
+#define CYREG_B0_P0_U0_CFG26 0x4001005a\r
+#define CYREG_B0_P0_U0_CFG27 0x4001005b\r
+#define CYREG_B0_P0_U0_CFG28 0x4001005c\r
+#define CYREG_B0_P0_U0_CFG29 0x4001005d\r
+#define CYREG_B0_P0_U0_CFG30 0x4001005e\r
+#define CYREG_B0_P0_U0_CFG31 0x4001005f\r
+#define CYREG_B0_P0_U0_DCFG0 0x40010060\r
+#define CYREG_B0_P0_U0_DCFG1 0x40010062\r
+#define CYREG_B0_P0_U0_DCFG2 0x40010064\r
+#define CYREG_B0_P0_U0_DCFG3 0x40010066\r
+#define CYREG_B0_P0_U0_DCFG4 0x40010068\r
+#define CYREG_B0_P0_U0_DCFG5 0x4001006a\r
+#define CYREG_B0_P0_U0_DCFG6 0x4001006c\r
+#define CYREG_B0_P0_U0_DCFG7 0x4001006e\r
+#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080\r
+#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070\r
+#define CYREG_B0_P0_U1_PLD_IT0 0x40010080\r
+#define CYREG_B0_P0_U1_PLD_IT1 0x40010084\r
+#define CYREG_B0_P0_U1_PLD_IT2 0x40010088\r
+#define CYREG_B0_P0_U1_PLD_IT3 0x4001008c\r
+#define CYREG_B0_P0_U1_PLD_IT4 0x40010090\r
+#define CYREG_B0_P0_U1_PLD_IT5 0x40010094\r
+#define CYREG_B0_P0_U1_PLD_IT6 0x40010098\r
+#define CYREG_B0_P0_U1_PLD_IT7 0x4001009c\r
+#define CYREG_B0_P0_U1_PLD_IT8 0x400100a0\r
+#define CYREG_B0_P0_U1_PLD_IT9 0x400100a4\r
+#define CYREG_B0_P0_U1_PLD_IT10 0x400100a8\r
+#define CYREG_B0_P0_U1_PLD_IT11 0x400100ac\r
+#define CYREG_B0_P0_U1_PLD_ORT0 0x400100b0\r
+#define CYREG_B0_P0_U1_PLD_ORT1 0x400100b2\r
+#define CYREG_B0_P0_U1_PLD_ORT2 0x400100b4\r
+#define CYREG_B0_P0_U1_PLD_ORT3 0x400100b6\r
+#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8\r
+#define CYREG_B0_P0_U1_MC_CFG_XORFB 0x400100ba\r
+#define CYREG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bc\r
+#define CYREG_B0_P0_U1_MC_CFG_BYPASS 0x400100be\r
+#define CYREG_B0_P0_U1_CFG0 0x400100c0\r
+#define CYREG_B0_P0_U1_CFG1 0x400100c1\r
+#define CYREG_B0_P0_U1_CFG2 0x400100c2\r
+#define CYREG_B0_P0_U1_CFG3 0x400100c3\r
+#define CYREG_B0_P0_U1_CFG4 0x400100c4\r
+#define CYREG_B0_P0_U1_CFG5 0x400100c5\r
+#define CYREG_B0_P0_U1_CFG6 0x400100c6\r
+#define CYREG_B0_P0_U1_CFG7 0x400100c7\r
+#define CYREG_B0_P0_U1_CFG8 0x400100c8\r
+#define CYREG_B0_P0_U1_CFG9 0x400100c9\r
+#define CYREG_B0_P0_U1_CFG10 0x400100ca\r
+#define CYREG_B0_P0_U1_CFG11 0x400100cb\r
+#define CYREG_B0_P0_U1_CFG12 0x400100cc\r
+#define CYREG_B0_P0_U1_CFG13 0x400100cd\r
+#define CYREG_B0_P0_U1_CFG14 0x400100ce\r
+#define CYREG_B0_P0_U1_CFG15 0x400100cf\r
+#define CYREG_B0_P0_U1_CFG16 0x400100d0\r
+#define CYREG_B0_P0_U1_CFG17 0x400100d1\r
+#define CYREG_B0_P0_U1_CFG18 0x400100d2\r
+#define CYREG_B0_P0_U1_CFG19 0x400100d3\r
+#define CYREG_B0_P0_U1_CFG20 0x400100d4\r
+#define CYREG_B0_P0_U1_CFG21 0x400100d5\r
+#define CYREG_B0_P0_U1_CFG22 0x400100d6\r
+#define CYREG_B0_P0_U1_CFG23 0x400100d7\r
+#define CYREG_B0_P0_U1_CFG24 0x400100d8\r
+#define CYREG_B0_P0_U1_CFG25 0x400100d9\r
+#define CYREG_B0_P0_U1_CFG26 0x400100da\r
+#define CYREG_B0_P0_U1_CFG27 0x400100db\r
+#define CYREG_B0_P0_U1_CFG28 0x400100dc\r
+#define CYREG_B0_P0_U1_CFG29 0x400100dd\r
+#define CYREG_B0_P0_U1_CFG30 0x400100de\r
+#define CYREG_B0_P0_U1_CFG31 0x400100df\r
+#define CYREG_B0_P0_U1_DCFG0 0x400100e0\r
+#define CYREG_B0_P0_U1_DCFG1 0x400100e2\r
+#define CYREG_B0_P0_U1_DCFG2 0x400100e4\r
+#define CYREG_B0_P0_U1_DCFG3 0x400100e6\r
+#define CYREG_B0_P0_U1_DCFG4 0x400100e8\r
+#define CYREG_B0_P0_U1_DCFG5 0x400100ea\r
+#define CYREG_B0_P0_U1_DCFG6 0x400100ec\r
+#define CYREG_B0_P0_U1_DCFG7 0x400100ee\r
+#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100\r
+#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B0_P1_BASE 0x40010200\r
+#define CYDEV_UCFG_B0_P1_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200\r
+#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070\r
+#define CYREG_B0_P1_U0_PLD_IT0 0x40010200\r
+#define CYREG_B0_P1_U0_PLD_IT1 0x40010204\r
+#define CYREG_B0_P1_U0_PLD_IT2 0x40010208\r
+#define CYREG_B0_P1_U0_PLD_IT3 0x4001020c\r
+#define CYREG_B0_P1_U0_PLD_IT4 0x40010210\r
+#define CYREG_B0_P1_U0_PLD_IT5 0x40010214\r
+#define CYREG_B0_P1_U0_PLD_IT6 0x40010218\r
+#define CYREG_B0_P1_U0_PLD_IT7 0x4001021c\r
+#define CYREG_B0_P1_U0_PLD_IT8 0x40010220\r
+#define CYREG_B0_P1_U0_PLD_IT9 0x40010224\r
+#define CYREG_B0_P1_U0_PLD_IT10 0x40010228\r
+#define CYREG_B0_P1_U0_PLD_IT11 0x4001022c\r
+#define CYREG_B0_P1_U0_PLD_ORT0 0x40010230\r
+#define CYREG_B0_P1_U0_PLD_ORT1 0x40010232\r
+#define CYREG_B0_P1_U0_PLD_ORT2 0x40010234\r
+#define CYREG_B0_P1_U0_PLD_ORT3 0x40010236\r
+#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238\r
+#define CYREG_B0_P1_U0_MC_CFG_XORFB 0x4001023a\r
+#define CYREG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023c\r
+#define CYREG_B0_P1_U0_MC_CFG_BYPASS 0x4001023e\r
+#define CYREG_B0_P1_U0_CFG0 0x40010240\r
+#define CYREG_B0_P1_U0_CFG1 0x40010241\r
+#define CYREG_B0_P1_U0_CFG2 0x40010242\r
+#define CYREG_B0_P1_U0_CFG3 0x40010243\r
+#define CYREG_B0_P1_U0_CFG4 0x40010244\r
+#define CYREG_B0_P1_U0_CFG5 0x40010245\r
+#define CYREG_B0_P1_U0_CFG6 0x40010246\r
+#define CYREG_B0_P1_U0_CFG7 0x40010247\r
+#define CYREG_B0_P1_U0_CFG8 0x40010248\r
+#define CYREG_B0_P1_U0_CFG9 0x40010249\r
+#define CYREG_B0_P1_U0_CFG10 0x4001024a\r
+#define CYREG_B0_P1_U0_CFG11 0x4001024b\r
+#define CYREG_B0_P1_U0_CFG12 0x4001024c\r
+#define CYREG_B0_P1_U0_CFG13 0x4001024d\r
+#define CYREG_B0_P1_U0_CFG14 0x4001024e\r
+#define CYREG_B0_P1_U0_CFG15 0x4001024f\r
+#define CYREG_B0_P1_U0_CFG16 0x40010250\r
+#define CYREG_B0_P1_U0_CFG17 0x40010251\r
+#define CYREG_B0_P1_U0_CFG18 0x40010252\r
+#define CYREG_B0_P1_U0_CFG19 0x40010253\r
+#define CYREG_B0_P1_U0_CFG20 0x40010254\r
+#define CYREG_B0_P1_U0_CFG21 0x40010255\r
+#define CYREG_B0_P1_U0_CFG22 0x40010256\r
+#define CYREG_B0_P1_U0_CFG23 0x40010257\r
+#define CYREG_B0_P1_U0_CFG24 0x40010258\r
+#define CYREG_B0_P1_U0_CFG25 0x40010259\r
+#define CYREG_B0_P1_U0_CFG26 0x4001025a\r
+#define CYREG_B0_P1_U0_CFG27 0x4001025b\r
+#define CYREG_B0_P1_U0_CFG28 0x4001025c\r
+#define CYREG_B0_P1_U0_CFG29 0x4001025d\r
+#define CYREG_B0_P1_U0_CFG30 0x4001025e\r
+#define CYREG_B0_P1_U0_CFG31 0x4001025f\r
+#define CYREG_B0_P1_U0_DCFG0 0x40010260\r
+#define CYREG_B0_P1_U0_DCFG1 0x40010262\r
+#define CYREG_B0_P1_U0_DCFG2 0x40010264\r
+#define CYREG_B0_P1_U0_DCFG3 0x40010266\r
+#define CYREG_B0_P1_U0_DCFG4 0x40010268\r
+#define CYREG_B0_P1_U0_DCFG5 0x4001026a\r
+#define CYREG_B0_P1_U0_DCFG6 0x4001026c\r
+#define CYREG_B0_P1_U0_DCFG7 0x4001026e\r
+#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280\r
+#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070\r
+#define CYREG_B0_P1_U1_PLD_IT0 0x40010280\r
+#define CYREG_B0_P1_U1_PLD_IT1 0x40010284\r
+#define CYREG_B0_P1_U1_PLD_IT2 0x40010288\r
+#define CYREG_B0_P1_U1_PLD_IT3 0x4001028c\r
+#define CYREG_B0_P1_U1_PLD_IT4 0x40010290\r
+#define CYREG_B0_P1_U1_PLD_IT5 0x40010294\r
+#define CYREG_B0_P1_U1_PLD_IT6 0x40010298\r
+#define CYREG_B0_P1_U1_PLD_IT7 0x4001029c\r
+#define CYREG_B0_P1_U1_PLD_IT8 0x400102a0\r
+#define CYREG_B0_P1_U1_PLD_IT9 0x400102a4\r
+#define CYREG_B0_P1_U1_PLD_IT10 0x400102a8\r
+#define CYREG_B0_P1_U1_PLD_IT11 0x400102ac\r
+#define CYREG_B0_P1_U1_PLD_ORT0 0x400102b0\r
+#define CYREG_B0_P1_U1_PLD_ORT1 0x400102b2\r
+#define CYREG_B0_P1_U1_PLD_ORT2 0x400102b4\r
+#define CYREG_B0_P1_U1_PLD_ORT3 0x400102b6\r
+#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8\r
+#define CYREG_B0_P1_U1_MC_CFG_XORFB 0x400102ba\r
+#define CYREG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bc\r
+#define CYREG_B0_P1_U1_MC_CFG_BYPASS 0x400102be\r
+#define CYREG_B0_P1_U1_CFG0 0x400102c0\r
+#define CYREG_B0_P1_U1_CFG1 0x400102c1\r
+#define CYREG_B0_P1_U1_CFG2 0x400102c2\r
+#define CYREG_B0_P1_U1_CFG3 0x400102c3\r
+#define CYREG_B0_P1_U1_CFG4 0x400102c4\r
+#define CYREG_B0_P1_U1_CFG5 0x400102c5\r
+#define CYREG_B0_P1_U1_CFG6 0x400102c6\r
+#define CYREG_B0_P1_U1_CFG7 0x400102c7\r
+#define CYREG_B0_P1_U1_CFG8 0x400102c8\r
+#define CYREG_B0_P1_U1_CFG9 0x400102c9\r
+#define CYREG_B0_P1_U1_CFG10 0x400102ca\r
+#define CYREG_B0_P1_U1_CFG11 0x400102cb\r
+#define CYREG_B0_P1_U1_CFG12 0x400102cc\r
+#define CYREG_B0_P1_U1_CFG13 0x400102cd\r
+#define CYREG_B0_P1_U1_CFG14 0x400102ce\r
+#define CYREG_B0_P1_U1_CFG15 0x400102cf\r
+#define CYREG_B0_P1_U1_CFG16 0x400102d0\r
+#define CYREG_B0_P1_U1_CFG17 0x400102d1\r
+#define CYREG_B0_P1_U1_CFG18 0x400102d2\r
+#define CYREG_B0_P1_U1_CFG19 0x400102d3\r
+#define CYREG_B0_P1_U1_CFG20 0x400102d4\r
+#define CYREG_B0_P1_U1_CFG21 0x400102d5\r
+#define CYREG_B0_P1_U1_CFG22 0x400102d6\r
+#define CYREG_B0_P1_U1_CFG23 0x400102d7\r
+#define CYREG_B0_P1_U1_CFG24 0x400102d8\r
+#define CYREG_B0_P1_U1_CFG25 0x400102d9\r
+#define CYREG_B0_P1_U1_CFG26 0x400102da\r
+#define CYREG_B0_P1_U1_CFG27 0x400102db\r
+#define CYREG_B0_P1_U1_CFG28 0x400102dc\r
+#define CYREG_B0_P1_U1_CFG29 0x400102dd\r
+#define CYREG_B0_P1_U1_CFG30 0x400102de\r
+#define CYREG_B0_P1_U1_CFG31 0x400102df\r
+#define CYREG_B0_P1_U1_DCFG0 0x400102e0\r
+#define CYREG_B0_P1_U1_DCFG1 0x400102e2\r
+#define CYREG_B0_P1_U1_DCFG2 0x400102e4\r
+#define CYREG_B0_P1_U1_DCFG3 0x400102e6\r
+#define CYREG_B0_P1_U1_DCFG4 0x400102e8\r
+#define CYREG_B0_P1_U1_DCFG5 0x400102ea\r
+#define CYREG_B0_P1_U1_DCFG6 0x400102ec\r
+#define CYREG_B0_P1_U1_DCFG7 0x400102ee\r
+#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300\r
+#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B0_P2_BASE 0x40010400\r
+#define CYDEV_UCFG_B0_P2_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400\r
+#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070\r
+#define CYREG_B0_P2_U0_PLD_IT0 0x40010400\r
+#define CYREG_B0_P2_U0_PLD_IT1 0x40010404\r
+#define CYREG_B0_P2_U0_PLD_IT2 0x40010408\r
+#define CYREG_B0_P2_U0_PLD_IT3 0x4001040c\r
+#define CYREG_B0_P2_U0_PLD_IT4 0x40010410\r
+#define CYREG_B0_P2_U0_PLD_IT5 0x40010414\r
+#define CYREG_B0_P2_U0_PLD_IT6 0x40010418\r
+#define CYREG_B0_P2_U0_PLD_IT7 0x4001041c\r
+#define CYREG_B0_P2_U0_PLD_IT8 0x40010420\r
+#define CYREG_B0_P2_U0_PLD_IT9 0x40010424\r
+#define CYREG_B0_P2_U0_PLD_IT10 0x40010428\r
+#define CYREG_B0_P2_U0_PLD_IT11 0x4001042c\r
+#define CYREG_B0_P2_U0_PLD_ORT0 0x40010430\r
+#define CYREG_B0_P2_U0_PLD_ORT1 0x40010432\r
+#define CYREG_B0_P2_U0_PLD_ORT2 0x40010434\r
+#define CYREG_B0_P2_U0_PLD_ORT3 0x40010436\r
+#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438\r
+#define CYREG_B0_P2_U0_MC_CFG_XORFB 0x4001043a\r
+#define CYREG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043c\r
+#define CYREG_B0_P2_U0_MC_CFG_BYPASS 0x4001043e\r
+#define CYREG_B0_P2_U0_CFG0 0x40010440\r
+#define CYREG_B0_P2_U0_CFG1 0x40010441\r
+#define CYREG_B0_P2_U0_CFG2 0x40010442\r
+#define CYREG_B0_P2_U0_CFG3 0x40010443\r
+#define CYREG_B0_P2_U0_CFG4 0x40010444\r
+#define CYREG_B0_P2_U0_CFG5 0x40010445\r
+#define CYREG_B0_P2_U0_CFG6 0x40010446\r
+#define CYREG_B0_P2_U0_CFG7 0x40010447\r
+#define CYREG_B0_P2_U0_CFG8 0x40010448\r
+#define CYREG_B0_P2_U0_CFG9 0x40010449\r
+#define CYREG_B0_P2_U0_CFG10 0x4001044a\r
+#define CYREG_B0_P2_U0_CFG11 0x4001044b\r
+#define CYREG_B0_P2_U0_CFG12 0x4001044c\r
+#define CYREG_B0_P2_U0_CFG13 0x4001044d\r
+#define CYREG_B0_P2_U0_CFG14 0x4001044e\r
+#define CYREG_B0_P2_U0_CFG15 0x4001044f\r
+#define CYREG_B0_P2_U0_CFG16 0x40010450\r
+#define CYREG_B0_P2_U0_CFG17 0x40010451\r
+#define CYREG_B0_P2_U0_CFG18 0x40010452\r
+#define CYREG_B0_P2_U0_CFG19 0x40010453\r
+#define CYREG_B0_P2_U0_CFG20 0x40010454\r
+#define CYREG_B0_P2_U0_CFG21 0x40010455\r
+#define CYREG_B0_P2_U0_CFG22 0x40010456\r
+#define CYREG_B0_P2_U0_CFG23 0x40010457\r
+#define CYREG_B0_P2_U0_CFG24 0x40010458\r
+#define CYREG_B0_P2_U0_CFG25 0x40010459\r
+#define CYREG_B0_P2_U0_CFG26 0x4001045a\r
+#define CYREG_B0_P2_U0_CFG27 0x4001045b\r
+#define CYREG_B0_P2_U0_CFG28 0x4001045c\r
+#define CYREG_B0_P2_U0_CFG29 0x4001045d\r
+#define CYREG_B0_P2_U0_CFG30 0x4001045e\r
+#define CYREG_B0_P2_U0_CFG31 0x4001045f\r
+#define CYREG_B0_P2_U0_DCFG0 0x40010460\r
+#define CYREG_B0_P2_U0_DCFG1 0x40010462\r
+#define CYREG_B0_P2_U0_DCFG2 0x40010464\r
+#define CYREG_B0_P2_U0_DCFG3 0x40010466\r
+#define CYREG_B0_P2_U0_DCFG4 0x40010468\r
+#define CYREG_B0_P2_U0_DCFG5 0x4001046a\r
+#define CYREG_B0_P2_U0_DCFG6 0x4001046c\r
+#define CYREG_B0_P2_U0_DCFG7 0x4001046e\r
+#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480\r
+#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070\r
+#define CYREG_B0_P2_U1_PLD_IT0 0x40010480\r
+#define CYREG_B0_P2_U1_PLD_IT1 0x40010484\r
+#define CYREG_B0_P2_U1_PLD_IT2 0x40010488\r
+#define CYREG_B0_P2_U1_PLD_IT3 0x4001048c\r
+#define CYREG_B0_P2_U1_PLD_IT4 0x40010490\r
+#define CYREG_B0_P2_U1_PLD_IT5 0x40010494\r
+#define CYREG_B0_P2_U1_PLD_IT6 0x40010498\r
+#define CYREG_B0_P2_U1_PLD_IT7 0x4001049c\r
+#define CYREG_B0_P2_U1_PLD_IT8 0x400104a0\r
+#define CYREG_B0_P2_U1_PLD_IT9 0x400104a4\r
+#define CYREG_B0_P2_U1_PLD_IT10 0x400104a8\r
+#define CYREG_B0_P2_U1_PLD_IT11 0x400104ac\r
+#define CYREG_B0_P2_U1_PLD_ORT0 0x400104b0\r
+#define CYREG_B0_P2_U1_PLD_ORT1 0x400104b2\r
+#define CYREG_B0_P2_U1_PLD_ORT2 0x400104b4\r
+#define CYREG_B0_P2_U1_PLD_ORT3 0x400104b6\r
+#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8\r
+#define CYREG_B0_P2_U1_MC_CFG_XORFB 0x400104ba\r
+#define CYREG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bc\r
+#define CYREG_B0_P2_U1_MC_CFG_BYPASS 0x400104be\r
+#define CYREG_B0_P2_U1_CFG0 0x400104c0\r
+#define CYREG_B0_P2_U1_CFG1 0x400104c1\r
+#define CYREG_B0_P2_U1_CFG2 0x400104c2\r
+#define CYREG_B0_P2_U1_CFG3 0x400104c3\r
+#define CYREG_B0_P2_U1_CFG4 0x400104c4\r
+#define CYREG_B0_P2_U1_CFG5 0x400104c5\r
+#define CYREG_B0_P2_U1_CFG6 0x400104c6\r
+#define CYREG_B0_P2_U1_CFG7 0x400104c7\r
+#define CYREG_B0_P2_U1_CFG8 0x400104c8\r
+#define CYREG_B0_P2_U1_CFG9 0x400104c9\r
+#define CYREG_B0_P2_U1_CFG10 0x400104ca\r
+#define CYREG_B0_P2_U1_CFG11 0x400104cb\r
+#define CYREG_B0_P2_U1_CFG12 0x400104cc\r
+#define CYREG_B0_P2_U1_CFG13 0x400104cd\r
+#define CYREG_B0_P2_U1_CFG14 0x400104ce\r
+#define CYREG_B0_P2_U1_CFG15 0x400104cf\r
+#define CYREG_B0_P2_U1_CFG16 0x400104d0\r
+#define CYREG_B0_P2_U1_CFG17 0x400104d1\r
+#define CYREG_B0_P2_U1_CFG18 0x400104d2\r
+#define CYREG_B0_P2_U1_CFG19 0x400104d3\r
+#define CYREG_B0_P2_U1_CFG20 0x400104d4\r
+#define CYREG_B0_P2_U1_CFG21 0x400104d5\r
+#define CYREG_B0_P2_U1_CFG22 0x400104d6\r
+#define CYREG_B0_P2_U1_CFG23 0x400104d7\r
+#define CYREG_B0_P2_U1_CFG24 0x400104d8\r
+#define CYREG_B0_P2_U1_CFG25 0x400104d9\r
+#define CYREG_B0_P2_U1_CFG26 0x400104da\r
+#define CYREG_B0_P2_U1_CFG27 0x400104db\r
+#define CYREG_B0_P2_U1_CFG28 0x400104dc\r
+#define CYREG_B0_P2_U1_CFG29 0x400104dd\r
+#define CYREG_B0_P2_U1_CFG30 0x400104de\r
+#define CYREG_B0_P2_U1_CFG31 0x400104df\r
+#define CYREG_B0_P2_U1_DCFG0 0x400104e0\r
+#define CYREG_B0_P2_U1_DCFG1 0x400104e2\r
+#define CYREG_B0_P2_U1_DCFG2 0x400104e4\r
+#define CYREG_B0_P2_U1_DCFG3 0x400104e6\r
+#define CYREG_B0_P2_U1_DCFG4 0x400104e8\r
+#define CYREG_B0_P2_U1_DCFG5 0x400104ea\r
+#define CYREG_B0_P2_U1_DCFG6 0x400104ec\r
+#define CYREG_B0_P2_U1_DCFG7 0x400104ee\r
+#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500\r
+#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B0_P3_BASE 0x40010600\r
+#define CYDEV_UCFG_B0_P3_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600\r
+#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070\r
+#define CYREG_B0_P3_U0_PLD_IT0 0x40010600\r
+#define CYREG_B0_P3_U0_PLD_IT1 0x40010604\r
+#define CYREG_B0_P3_U0_PLD_IT2 0x40010608\r
+#define CYREG_B0_P3_U0_PLD_IT3 0x4001060c\r
+#define CYREG_B0_P3_U0_PLD_IT4 0x40010610\r
+#define CYREG_B0_P3_U0_PLD_IT5 0x40010614\r
+#define CYREG_B0_P3_U0_PLD_IT6 0x40010618\r
+#define CYREG_B0_P3_U0_PLD_IT7 0x4001061c\r
+#define CYREG_B0_P3_U0_PLD_IT8 0x40010620\r
+#define CYREG_B0_P3_U0_PLD_IT9 0x40010624\r
+#define CYREG_B0_P3_U0_PLD_IT10 0x40010628\r
+#define CYREG_B0_P3_U0_PLD_IT11 0x4001062c\r
+#define CYREG_B0_P3_U0_PLD_ORT0 0x40010630\r
+#define CYREG_B0_P3_U0_PLD_ORT1 0x40010632\r
+#define CYREG_B0_P3_U0_PLD_ORT2 0x40010634\r
+#define CYREG_B0_P3_U0_PLD_ORT3 0x40010636\r
+#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638\r
+#define CYREG_B0_P3_U0_MC_CFG_XORFB 0x4001063a\r
+#define CYREG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063c\r
+#define CYREG_B0_P3_U0_MC_CFG_BYPASS 0x4001063e\r
+#define CYREG_B0_P3_U0_CFG0 0x40010640\r
+#define CYREG_B0_P3_U0_CFG1 0x40010641\r
+#define CYREG_B0_P3_U0_CFG2 0x40010642\r
+#define CYREG_B0_P3_U0_CFG3 0x40010643\r
+#define CYREG_B0_P3_U0_CFG4 0x40010644\r
+#define CYREG_B0_P3_U0_CFG5 0x40010645\r
+#define CYREG_B0_P3_U0_CFG6 0x40010646\r
+#define CYREG_B0_P3_U0_CFG7 0x40010647\r
+#define CYREG_B0_P3_U0_CFG8 0x40010648\r
+#define CYREG_B0_P3_U0_CFG9 0x40010649\r
+#define CYREG_B0_P3_U0_CFG10 0x4001064a\r
+#define CYREG_B0_P3_U0_CFG11 0x4001064b\r
+#define CYREG_B0_P3_U0_CFG12 0x4001064c\r
+#define CYREG_B0_P3_U0_CFG13 0x4001064d\r
+#define CYREG_B0_P3_U0_CFG14 0x4001064e\r
+#define CYREG_B0_P3_U0_CFG15 0x4001064f\r
+#define CYREG_B0_P3_U0_CFG16 0x40010650\r
+#define CYREG_B0_P3_U0_CFG17 0x40010651\r
+#define CYREG_B0_P3_U0_CFG18 0x40010652\r
+#define CYREG_B0_P3_U0_CFG19 0x40010653\r
+#define CYREG_B0_P3_U0_CFG20 0x40010654\r
+#define CYREG_B0_P3_U0_CFG21 0x40010655\r
+#define CYREG_B0_P3_U0_CFG22 0x40010656\r
+#define CYREG_B0_P3_U0_CFG23 0x40010657\r
+#define CYREG_B0_P3_U0_CFG24 0x40010658\r
+#define CYREG_B0_P3_U0_CFG25 0x40010659\r
+#define CYREG_B0_P3_U0_CFG26 0x4001065a\r
+#define CYREG_B0_P3_U0_CFG27 0x4001065b\r
+#define CYREG_B0_P3_U0_CFG28 0x4001065c\r
+#define CYREG_B0_P3_U0_CFG29 0x4001065d\r
+#define CYREG_B0_P3_U0_CFG30 0x4001065e\r
+#define CYREG_B0_P3_U0_CFG31 0x4001065f\r
+#define CYREG_B0_P3_U0_DCFG0 0x40010660\r
+#define CYREG_B0_P3_U0_DCFG1 0x40010662\r
+#define CYREG_B0_P3_U0_DCFG2 0x40010664\r
+#define CYREG_B0_P3_U0_DCFG3 0x40010666\r
+#define CYREG_B0_P3_U0_DCFG4 0x40010668\r
+#define CYREG_B0_P3_U0_DCFG5 0x4001066a\r
+#define CYREG_B0_P3_U0_DCFG6 0x4001066c\r
+#define CYREG_B0_P3_U0_DCFG7 0x4001066e\r
+#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680\r
+#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070\r
+#define CYREG_B0_P3_U1_PLD_IT0 0x40010680\r
+#define CYREG_B0_P3_U1_PLD_IT1 0x40010684\r
+#define CYREG_B0_P3_U1_PLD_IT2 0x40010688\r
+#define CYREG_B0_P3_U1_PLD_IT3 0x4001068c\r
+#define CYREG_B0_P3_U1_PLD_IT4 0x40010690\r
+#define CYREG_B0_P3_U1_PLD_IT5 0x40010694\r
+#define CYREG_B0_P3_U1_PLD_IT6 0x40010698\r
+#define CYREG_B0_P3_U1_PLD_IT7 0x4001069c\r
+#define CYREG_B0_P3_U1_PLD_IT8 0x400106a0\r
+#define CYREG_B0_P3_U1_PLD_IT9 0x400106a4\r
+#define CYREG_B0_P3_U1_PLD_IT10 0x400106a8\r
+#define CYREG_B0_P3_U1_PLD_IT11 0x400106ac\r
+#define CYREG_B0_P3_U1_PLD_ORT0 0x400106b0\r
+#define CYREG_B0_P3_U1_PLD_ORT1 0x400106b2\r
+#define CYREG_B0_P3_U1_PLD_ORT2 0x400106b4\r
+#define CYREG_B0_P3_U1_PLD_ORT3 0x400106b6\r
+#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8\r
+#define CYREG_B0_P3_U1_MC_CFG_XORFB 0x400106ba\r
+#define CYREG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bc\r
+#define CYREG_B0_P3_U1_MC_CFG_BYPASS 0x400106be\r
+#define CYREG_B0_P3_U1_CFG0 0x400106c0\r
+#define CYREG_B0_P3_U1_CFG1 0x400106c1\r
+#define CYREG_B0_P3_U1_CFG2 0x400106c2\r
+#define CYREG_B0_P3_U1_CFG3 0x400106c3\r
+#define CYREG_B0_P3_U1_CFG4 0x400106c4\r
+#define CYREG_B0_P3_U1_CFG5 0x400106c5\r
+#define CYREG_B0_P3_U1_CFG6 0x400106c6\r
+#define CYREG_B0_P3_U1_CFG7 0x400106c7\r
+#define CYREG_B0_P3_U1_CFG8 0x400106c8\r
+#define CYREG_B0_P3_U1_CFG9 0x400106c9\r
+#define CYREG_B0_P3_U1_CFG10 0x400106ca\r
+#define CYREG_B0_P3_U1_CFG11 0x400106cb\r
+#define CYREG_B0_P3_U1_CFG12 0x400106cc\r
+#define CYREG_B0_P3_U1_CFG13 0x400106cd\r
+#define CYREG_B0_P3_U1_CFG14 0x400106ce\r
+#define CYREG_B0_P3_U1_CFG15 0x400106cf\r
+#define CYREG_B0_P3_U1_CFG16 0x400106d0\r
+#define CYREG_B0_P3_U1_CFG17 0x400106d1\r
+#define CYREG_B0_P3_U1_CFG18 0x400106d2\r
+#define CYREG_B0_P3_U1_CFG19 0x400106d3\r
+#define CYREG_B0_P3_U1_CFG20 0x400106d4\r
+#define CYREG_B0_P3_U1_CFG21 0x400106d5\r
+#define CYREG_B0_P3_U1_CFG22 0x400106d6\r
+#define CYREG_B0_P3_U1_CFG23 0x400106d7\r
+#define CYREG_B0_P3_U1_CFG24 0x400106d8\r
+#define CYREG_B0_P3_U1_CFG25 0x400106d9\r
+#define CYREG_B0_P3_U1_CFG26 0x400106da\r
+#define CYREG_B0_P3_U1_CFG27 0x400106db\r
+#define CYREG_B0_P3_U1_CFG28 0x400106dc\r
+#define CYREG_B0_P3_U1_CFG29 0x400106dd\r
+#define CYREG_B0_P3_U1_CFG30 0x400106de\r
+#define CYREG_B0_P3_U1_CFG31 0x400106df\r
+#define CYREG_B0_P3_U1_DCFG0 0x400106e0\r
+#define CYREG_B0_P3_U1_DCFG1 0x400106e2\r
+#define CYREG_B0_P3_U1_DCFG2 0x400106e4\r
+#define CYREG_B0_P3_U1_DCFG3 0x400106e6\r
+#define CYREG_B0_P3_U1_DCFG4 0x400106e8\r
+#define CYREG_B0_P3_U1_DCFG5 0x400106ea\r
+#define CYREG_B0_P3_U1_DCFG6 0x400106ec\r
+#define CYREG_B0_P3_U1_DCFG7 0x400106ee\r
+#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700\r
+#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B0_P4_BASE 0x40010800\r
+#define CYDEV_UCFG_B0_P4_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800\r
+#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070\r
+#define CYREG_B0_P4_U0_PLD_IT0 0x40010800\r
+#define CYREG_B0_P4_U0_PLD_IT1 0x40010804\r
+#define CYREG_B0_P4_U0_PLD_IT2 0x40010808\r
+#define CYREG_B0_P4_U0_PLD_IT3 0x4001080c\r
+#define CYREG_B0_P4_U0_PLD_IT4 0x40010810\r
+#define CYREG_B0_P4_U0_PLD_IT5 0x40010814\r
+#define CYREG_B0_P4_U0_PLD_IT6 0x40010818\r
+#define CYREG_B0_P4_U0_PLD_IT7 0x4001081c\r
+#define CYREG_B0_P4_U0_PLD_IT8 0x40010820\r
+#define CYREG_B0_P4_U0_PLD_IT9 0x40010824\r
+#define CYREG_B0_P4_U0_PLD_IT10 0x40010828\r
+#define CYREG_B0_P4_U0_PLD_IT11 0x4001082c\r
+#define CYREG_B0_P4_U0_PLD_ORT0 0x40010830\r
+#define CYREG_B0_P4_U0_PLD_ORT1 0x40010832\r
+#define CYREG_B0_P4_U0_PLD_ORT2 0x40010834\r
+#define CYREG_B0_P4_U0_PLD_ORT3 0x40010836\r
+#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838\r
+#define CYREG_B0_P4_U0_MC_CFG_XORFB 0x4001083a\r
+#define CYREG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083c\r
+#define CYREG_B0_P4_U0_MC_CFG_BYPASS 0x4001083e\r
+#define CYREG_B0_P4_U0_CFG0 0x40010840\r
+#define CYREG_B0_P4_U0_CFG1 0x40010841\r
+#define CYREG_B0_P4_U0_CFG2 0x40010842\r
+#define CYREG_B0_P4_U0_CFG3 0x40010843\r
+#define CYREG_B0_P4_U0_CFG4 0x40010844\r
+#define CYREG_B0_P4_U0_CFG5 0x40010845\r
+#define CYREG_B0_P4_U0_CFG6 0x40010846\r
+#define CYREG_B0_P4_U0_CFG7 0x40010847\r
+#define CYREG_B0_P4_U0_CFG8 0x40010848\r
+#define CYREG_B0_P4_U0_CFG9 0x40010849\r
+#define CYREG_B0_P4_U0_CFG10 0x4001084a\r
+#define CYREG_B0_P4_U0_CFG11 0x4001084b\r
+#define CYREG_B0_P4_U0_CFG12 0x4001084c\r
+#define CYREG_B0_P4_U0_CFG13 0x4001084d\r
+#define CYREG_B0_P4_U0_CFG14 0x4001084e\r
+#define CYREG_B0_P4_U0_CFG15 0x4001084f\r
+#define CYREG_B0_P4_U0_CFG16 0x40010850\r
+#define CYREG_B0_P4_U0_CFG17 0x40010851\r
+#define CYREG_B0_P4_U0_CFG18 0x40010852\r
+#define CYREG_B0_P4_U0_CFG19 0x40010853\r
+#define CYREG_B0_P4_U0_CFG20 0x40010854\r
+#define CYREG_B0_P4_U0_CFG21 0x40010855\r
+#define CYREG_B0_P4_U0_CFG22 0x40010856\r
+#define CYREG_B0_P4_U0_CFG23 0x40010857\r
+#define CYREG_B0_P4_U0_CFG24 0x40010858\r
+#define CYREG_B0_P4_U0_CFG25 0x40010859\r
+#define CYREG_B0_P4_U0_CFG26 0x4001085a\r
+#define CYREG_B0_P4_U0_CFG27 0x4001085b\r
+#define CYREG_B0_P4_U0_CFG28 0x4001085c\r
+#define CYREG_B0_P4_U0_CFG29 0x4001085d\r
+#define CYREG_B0_P4_U0_CFG30 0x4001085e\r
+#define CYREG_B0_P4_U0_CFG31 0x4001085f\r
+#define CYREG_B0_P4_U0_DCFG0 0x40010860\r
+#define CYREG_B0_P4_U0_DCFG1 0x40010862\r
+#define CYREG_B0_P4_U0_DCFG2 0x40010864\r
+#define CYREG_B0_P4_U0_DCFG3 0x40010866\r
+#define CYREG_B0_P4_U0_DCFG4 0x40010868\r
+#define CYREG_B0_P4_U0_DCFG5 0x4001086a\r
+#define CYREG_B0_P4_U0_DCFG6 0x4001086c\r
+#define CYREG_B0_P4_U0_DCFG7 0x4001086e\r
+#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880\r
+#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070\r
+#define CYREG_B0_P4_U1_PLD_IT0 0x40010880\r
+#define CYREG_B0_P4_U1_PLD_IT1 0x40010884\r
+#define CYREG_B0_P4_U1_PLD_IT2 0x40010888\r
+#define CYREG_B0_P4_U1_PLD_IT3 0x4001088c\r
+#define CYREG_B0_P4_U1_PLD_IT4 0x40010890\r
+#define CYREG_B0_P4_U1_PLD_IT5 0x40010894\r
+#define CYREG_B0_P4_U1_PLD_IT6 0x40010898\r
+#define CYREG_B0_P4_U1_PLD_IT7 0x4001089c\r
+#define CYREG_B0_P4_U1_PLD_IT8 0x400108a0\r
+#define CYREG_B0_P4_U1_PLD_IT9 0x400108a4\r
+#define CYREG_B0_P4_U1_PLD_IT10 0x400108a8\r
+#define CYREG_B0_P4_U1_PLD_IT11 0x400108ac\r
+#define CYREG_B0_P4_U1_PLD_ORT0 0x400108b0\r
+#define CYREG_B0_P4_U1_PLD_ORT1 0x400108b2\r
+#define CYREG_B0_P4_U1_PLD_ORT2 0x400108b4\r
+#define CYREG_B0_P4_U1_PLD_ORT3 0x400108b6\r
+#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8\r
+#define CYREG_B0_P4_U1_MC_CFG_XORFB 0x400108ba\r
+#define CYREG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bc\r
+#define CYREG_B0_P4_U1_MC_CFG_BYPASS 0x400108be\r
+#define CYREG_B0_P4_U1_CFG0 0x400108c0\r
+#define CYREG_B0_P4_U1_CFG1 0x400108c1\r
+#define CYREG_B0_P4_U1_CFG2 0x400108c2\r
+#define CYREG_B0_P4_U1_CFG3 0x400108c3\r
+#define CYREG_B0_P4_U1_CFG4 0x400108c4\r
+#define CYREG_B0_P4_U1_CFG5 0x400108c5\r
+#define CYREG_B0_P4_U1_CFG6 0x400108c6\r
+#define CYREG_B0_P4_U1_CFG7 0x400108c7\r
+#define CYREG_B0_P4_U1_CFG8 0x400108c8\r
+#define CYREG_B0_P4_U1_CFG9 0x400108c9\r
+#define CYREG_B0_P4_U1_CFG10 0x400108ca\r
+#define CYREG_B0_P4_U1_CFG11 0x400108cb\r
+#define CYREG_B0_P4_U1_CFG12 0x400108cc\r
+#define CYREG_B0_P4_U1_CFG13 0x400108cd\r
+#define CYREG_B0_P4_U1_CFG14 0x400108ce\r
+#define CYREG_B0_P4_U1_CFG15 0x400108cf\r
+#define CYREG_B0_P4_U1_CFG16 0x400108d0\r
+#define CYREG_B0_P4_U1_CFG17 0x400108d1\r
+#define CYREG_B0_P4_U1_CFG18 0x400108d2\r
+#define CYREG_B0_P4_U1_CFG19 0x400108d3\r
+#define CYREG_B0_P4_U1_CFG20 0x400108d4\r
+#define CYREG_B0_P4_U1_CFG21 0x400108d5\r
+#define CYREG_B0_P4_U1_CFG22 0x400108d6\r
+#define CYREG_B0_P4_U1_CFG23 0x400108d7\r
+#define CYREG_B0_P4_U1_CFG24 0x400108d8\r
+#define CYREG_B0_P4_U1_CFG25 0x400108d9\r
+#define CYREG_B0_P4_U1_CFG26 0x400108da\r
+#define CYREG_B0_P4_U1_CFG27 0x400108db\r
+#define CYREG_B0_P4_U1_CFG28 0x400108dc\r
+#define CYREG_B0_P4_U1_CFG29 0x400108dd\r
+#define CYREG_B0_P4_U1_CFG30 0x400108de\r
+#define CYREG_B0_P4_U1_CFG31 0x400108df\r
+#define CYREG_B0_P4_U1_DCFG0 0x400108e0\r
+#define CYREG_B0_P4_U1_DCFG1 0x400108e2\r
+#define CYREG_B0_P4_U1_DCFG2 0x400108e4\r
+#define CYREG_B0_P4_U1_DCFG3 0x400108e6\r
+#define CYREG_B0_P4_U1_DCFG4 0x400108e8\r
+#define CYREG_B0_P4_U1_DCFG5 0x400108ea\r
+#define CYREG_B0_P4_U1_DCFG6 0x400108ec\r
+#define CYREG_B0_P4_U1_DCFG7 0x400108ee\r
+#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900\r
+#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B0_P5_BASE 0x40010a00\r
+#define CYDEV_UCFG_B0_P5_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00\r
+#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070\r
+#define CYREG_B0_P5_U0_PLD_IT0 0x40010a00\r
+#define CYREG_B0_P5_U0_PLD_IT1 0x40010a04\r
+#define CYREG_B0_P5_U0_PLD_IT2 0x40010a08\r
+#define CYREG_B0_P5_U0_PLD_IT3 0x40010a0c\r
+#define CYREG_B0_P5_U0_PLD_IT4 0x40010a10\r
+#define CYREG_B0_P5_U0_PLD_IT5 0x40010a14\r
+#define CYREG_B0_P5_U0_PLD_IT6 0x40010a18\r
+#define CYREG_B0_P5_U0_PLD_IT7 0x40010a1c\r
+#define CYREG_B0_P5_U0_PLD_IT8 0x40010a20\r
+#define CYREG_B0_P5_U0_PLD_IT9 0x40010a24\r
+#define CYREG_B0_P5_U0_PLD_IT10 0x40010a28\r
+#define CYREG_B0_P5_U0_PLD_IT11 0x40010a2c\r
+#define CYREG_B0_P5_U0_PLD_ORT0 0x40010a30\r
+#define CYREG_B0_P5_U0_PLD_ORT1 0x40010a32\r
+#define CYREG_B0_P5_U0_PLD_ORT2 0x40010a34\r
+#define CYREG_B0_P5_U0_PLD_ORT3 0x40010a36\r
+#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38\r
+#define CYREG_B0_P5_U0_MC_CFG_XORFB 0x40010a3a\r
+#define CYREG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3c\r
+#define CYREG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3e\r
+#define CYREG_B0_P5_U0_CFG0 0x40010a40\r
+#define CYREG_B0_P5_U0_CFG1 0x40010a41\r
+#define CYREG_B0_P5_U0_CFG2 0x40010a42\r
+#define CYREG_B0_P5_U0_CFG3 0x40010a43\r
+#define CYREG_B0_P5_U0_CFG4 0x40010a44\r
+#define CYREG_B0_P5_U0_CFG5 0x40010a45\r
+#define CYREG_B0_P5_U0_CFG6 0x40010a46\r
+#define CYREG_B0_P5_U0_CFG7 0x40010a47\r
+#define CYREG_B0_P5_U0_CFG8 0x40010a48\r
+#define CYREG_B0_P5_U0_CFG9 0x40010a49\r
+#define CYREG_B0_P5_U0_CFG10 0x40010a4a\r
+#define CYREG_B0_P5_U0_CFG11 0x40010a4b\r
+#define CYREG_B0_P5_U0_CFG12 0x40010a4c\r
+#define CYREG_B0_P5_U0_CFG13 0x40010a4d\r
+#define CYREG_B0_P5_U0_CFG14 0x40010a4e\r
+#define CYREG_B0_P5_U0_CFG15 0x40010a4f\r
+#define CYREG_B0_P5_U0_CFG16 0x40010a50\r
+#define CYREG_B0_P5_U0_CFG17 0x40010a51\r
+#define CYREG_B0_P5_U0_CFG18 0x40010a52\r
+#define CYREG_B0_P5_U0_CFG19 0x40010a53\r
+#define CYREG_B0_P5_U0_CFG20 0x40010a54\r
+#define CYREG_B0_P5_U0_CFG21 0x40010a55\r
+#define CYREG_B0_P5_U0_CFG22 0x40010a56\r
+#define CYREG_B0_P5_U0_CFG23 0x40010a57\r
+#define CYREG_B0_P5_U0_CFG24 0x40010a58\r
+#define CYREG_B0_P5_U0_CFG25 0x40010a59\r
+#define CYREG_B0_P5_U0_CFG26 0x40010a5a\r
+#define CYREG_B0_P5_U0_CFG27 0x40010a5b\r
+#define CYREG_B0_P5_U0_CFG28 0x40010a5c\r
+#define CYREG_B0_P5_U0_CFG29 0x40010a5d\r
+#define CYREG_B0_P5_U0_CFG30 0x40010a5e\r
+#define CYREG_B0_P5_U0_CFG31 0x40010a5f\r
+#define CYREG_B0_P5_U0_DCFG0 0x40010a60\r
+#define CYREG_B0_P5_U0_DCFG1 0x40010a62\r
+#define CYREG_B0_P5_U0_DCFG2 0x40010a64\r
+#define CYREG_B0_P5_U0_DCFG3 0x40010a66\r
+#define CYREG_B0_P5_U0_DCFG4 0x40010a68\r
+#define CYREG_B0_P5_U0_DCFG5 0x40010a6a\r
+#define CYREG_B0_P5_U0_DCFG6 0x40010a6c\r
+#define CYREG_B0_P5_U0_DCFG7 0x40010a6e\r
+#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80\r
+#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070\r
+#define CYREG_B0_P5_U1_PLD_IT0 0x40010a80\r
+#define CYREG_B0_P5_U1_PLD_IT1 0x40010a84\r
+#define CYREG_B0_P5_U1_PLD_IT2 0x40010a88\r
+#define CYREG_B0_P5_U1_PLD_IT3 0x40010a8c\r
+#define CYREG_B0_P5_U1_PLD_IT4 0x40010a90\r
+#define CYREG_B0_P5_U1_PLD_IT5 0x40010a94\r
+#define CYREG_B0_P5_U1_PLD_IT6 0x40010a98\r
+#define CYREG_B0_P5_U1_PLD_IT7 0x40010a9c\r
+#define CYREG_B0_P5_U1_PLD_IT8 0x40010aa0\r
+#define CYREG_B0_P5_U1_PLD_IT9 0x40010aa4\r
+#define CYREG_B0_P5_U1_PLD_IT10 0x40010aa8\r
+#define CYREG_B0_P5_U1_PLD_IT11 0x40010aac\r
+#define CYREG_B0_P5_U1_PLD_ORT0 0x40010ab0\r
+#define CYREG_B0_P5_U1_PLD_ORT1 0x40010ab2\r
+#define CYREG_B0_P5_U1_PLD_ORT2 0x40010ab4\r
+#define CYREG_B0_P5_U1_PLD_ORT3 0x40010ab6\r
+#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8\r
+#define CYREG_B0_P5_U1_MC_CFG_XORFB 0x40010aba\r
+#define CYREG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abc\r
+#define CYREG_B0_P5_U1_MC_CFG_BYPASS 0x40010abe\r
+#define CYREG_B0_P5_U1_CFG0 0x40010ac0\r
+#define CYREG_B0_P5_U1_CFG1 0x40010ac1\r
+#define CYREG_B0_P5_U1_CFG2 0x40010ac2\r
+#define CYREG_B0_P5_U1_CFG3 0x40010ac3\r
+#define CYREG_B0_P5_U1_CFG4 0x40010ac4\r
+#define CYREG_B0_P5_U1_CFG5 0x40010ac5\r
+#define CYREG_B0_P5_U1_CFG6 0x40010ac6\r
+#define CYREG_B0_P5_U1_CFG7 0x40010ac7\r
+#define CYREG_B0_P5_U1_CFG8 0x40010ac8\r
+#define CYREG_B0_P5_U1_CFG9 0x40010ac9\r
+#define CYREG_B0_P5_U1_CFG10 0x40010aca\r
+#define CYREG_B0_P5_U1_CFG11 0x40010acb\r
+#define CYREG_B0_P5_U1_CFG12 0x40010acc\r
+#define CYREG_B0_P5_U1_CFG13 0x40010acd\r
+#define CYREG_B0_P5_U1_CFG14 0x40010ace\r
+#define CYREG_B0_P5_U1_CFG15 0x40010acf\r
+#define CYREG_B0_P5_U1_CFG16 0x40010ad0\r
+#define CYREG_B0_P5_U1_CFG17 0x40010ad1\r
+#define CYREG_B0_P5_U1_CFG18 0x40010ad2\r
+#define CYREG_B0_P5_U1_CFG19 0x40010ad3\r
+#define CYREG_B0_P5_U1_CFG20 0x40010ad4\r
+#define CYREG_B0_P5_U1_CFG21 0x40010ad5\r
+#define CYREG_B0_P5_U1_CFG22 0x40010ad6\r
+#define CYREG_B0_P5_U1_CFG23 0x40010ad7\r
+#define CYREG_B0_P5_U1_CFG24 0x40010ad8\r
+#define CYREG_B0_P5_U1_CFG25 0x40010ad9\r
+#define CYREG_B0_P5_U1_CFG26 0x40010ada\r
+#define CYREG_B0_P5_U1_CFG27 0x40010adb\r
+#define CYREG_B0_P5_U1_CFG28 0x40010adc\r
+#define CYREG_B0_P5_U1_CFG29 0x40010add\r
+#define CYREG_B0_P5_U1_CFG30 0x40010ade\r
+#define CYREG_B0_P5_U1_CFG31 0x40010adf\r
+#define CYREG_B0_P5_U1_DCFG0 0x40010ae0\r
+#define CYREG_B0_P5_U1_DCFG1 0x40010ae2\r
+#define CYREG_B0_P5_U1_DCFG2 0x40010ae4\r
+#define CYREG_B0_P5_U1_DCFG3 0x40010ae6\r
+#define CYREG_B0_P5_U1_DCFG4 0x40010ae8\r
+#define CYREG_B0_P5_U1_DCFG5 0x40010aea\r
+#define CYREG_B0_P5_U1_DCFG6 0x40010aec\r
+#define CYREG_B0_P5_U1_DCFG7 0x40010aee\r
+#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00\r
+#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B0_P6_BASE 0x40010c00\r
+#define CYDEV_UCFG_B0_P6_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00\r
+#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070\r
+#define CYREG_B0_P6_U0_PLD_IT0 0x40010c00\r
+#define CYREG_B0_P6_U0_PLD_IT1 0x40010c04\r
+#define CYREG_B0_P6_U0_PLD_IT2 0x40010c08\r
+#define CYREG_B0_P6_U0_PLD_IT3 0x40010c0c\r
+#define CYREG_B0_P6_U0_PLD_IT4 0x40010c10\r
+#define CYREG_B0_P6_U0_PLD_IT5 0x40010c14\r
+#define CYREG_B0_P6_U0_PLD_IT6 0x40010c18\r
+#define CYREG_B0_P6_U0_PLD_IT7 0x40010c1c\r
+#define CYREG_B0_P6_U0_PLD_IT8 0x40010c20\r
+#define CYREG_B0_P6_U0_PLD_IT9 0x40010c24\r
+#define CYREG_B0_P6_U0_PLD_IT10 0x40010c28\r
+#define CYREG_B0_P6_U0_PLD_IT11 0x40010c2c\r
+#define CYREG_B0_P6_U0_PLD_ORT0 0x40010c30\r
+#define CYREG_B0_P6_U0_PLD_ORT1 0x40010c32\r
+#define CYREG_B0_P6_U0_PLD_ORT2 0x40010c34\r
+#define CYREG_B0_P6_U0_PLD_ORT3 0x40010c36\r
+#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38\r
+#define CYREG_B0_P6_U0_MC_CFG_XORFB 0x40010c3a\r
+#define CYREG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3c\r
+#define CYREG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3e\r
+#define CYREG_B0_P6_U0_CFG0 0x40010c40\r
+#define CYREG_B0_P6_U0_CFG1 0x40010c41\r
+#define CYREG_B0_P6_U0_CFG2 0x40010c42\r
+#define CYREG_B0_P6_U0_CFG3 0x40010c43\r
+#define CYREG_B0_P6_U0_CFG4 0x40010c44\r
+#define CYREG_B0_P6_U0_CFG5 0x40010c45\r
+#define CYREG_B0_P6_U0_CFG6 0x40010c46\r
+#define CYREG_B0_P6_U0_CFG7 0x40010c47\r
+#define CYREG_B0_P6_U0_CFG8 0x40010c48\r
+#define CYREG_B0_P6_U0_CFG9 0x40010c49\r
+#define CYREG_B0_P6_U0_CFG10 0x40010c4a\r
+#define CYREG_B0_P6_U0_CFG11 0x40010c4b\r
+#define CYREG_B0_P6_U0_CFG12 0x40010c4c\r
+#define CYREG_B0_P6_U0_CFG13 0x40010c4d\r
+#define CYREG_B0_P6_U0_CFG14 0x40010c4e\r
+#define CYREG_B0_P6_U0_CFG15 0x40010c4f\r
+#define CYREG_B0_P6_U0_CFG16 0x40010c50\r
+#define CYREG_B0_P6_U0_CFG17 0x40010c51\r
+#define CYREG_B0_P6_U0_CFG18 0x40010c52\r
+#define CYREG_B0_P6_U0_CFG19 0x40010c53\r
+#define CYREG_B0_P6_U0_CFG20 0x40010c54\r
+#define CYREG_B0_P6_U0_CFG21 0x40010c55\r
+#define CYREG_B0_P6_U0_CFG22 0x40010c56\r
+#define CYREG_B0_P6_U0_CFG23 0x40010c57\r
+#define CYREG_B0_P6_U0_CFG24 0x40010c58\r
+#define CYREG_B0_P6_U0_CFG25 0x40010c59\r
+#define CYREG_B0_P6_U0_CFG26 0x40010c5a\r
+#define CYREG_B0_P6_U0_CFG27 0x40010c5b\r
+#define CYREG_B0_P6_U0_CFG28 0x40010c5c\r
+#define CYREG_B0_P6_U0_CFG29 0x40010c5d\r
+#define CYREG_B0_P6_U0_CFG30 0x40010c5e\r
+#define CYREG_B0_P6_U0_CFG31 0x40010c5f\r
+#define CYREG_B0_P6_U0_DCFG0 0x40010c60\r
+#define CYREG_B0_P6_U0_DCFG1 0x40010c62\r
+#define CYREG_B0_P6_U0_DCFG2 0x40010c64\r
+#define CYREG_B0_P6_U0_DCFG3 0x40010c66\r
+#define CYREG_B0_P6_U0_DCFG4 0x40010c68\r
+#define CYREG_B0_P6_U0_DCFG5 0x40010c6a\r
+#define CYREG_B0_P6_U0_DCFG6 0x40010c6c\r
+#define CYREG_B0_P6_U0_DCFG7 0x40010c6e\r
+#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80\r
+#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070\r
+#define CYREG_B0_P6_U1_PLD_IT0 0x40010c80\r
+#define CYREG_B0_P6_U1_PLD_IT1 0x40010c84\r
+#define CYREG_B0_P6_U1_PLD_IT2 0x40010c88\r
+#define CYREG_B0_P6_U1_PLD_IT3 0x40010c8c\r
+#define CYREG_B0_P6_U1_PLD_IT4 0x40010c90\r
+#define CYREG_B0_P6_U1_PLD_IT5 0x40010c94\r
+#define CYREG_B0_P6_U1_PLD_IT6 0x40010c98\r
+#define CYREG_B0_P6_U1_PLD_IT7 0x40010c9c\r
+#define CYREG_B0_P6_U1_PLD_IT8 0x40010ca0\r
+#define CYREG_B0_P6_U1_PLD_IT9 0x40010ca4\r
+#define CYREG_B0_P6_U1_PLD_IT10 0x40010ca8\r
+#define CYREG_B0_P6_U1_PLD_IT11 0x40010cac\r
+#define CYREG_B0_P6_U1_PLD_ORT0 0x40010cb0\r
+#define CYREG_B0_P6_U1_PLD_ORT1 0x40010cb2\r
+#define CYREG_B0_P6_U1_PLD_ORT2 0x40010cb4\r
+#define CYREG_B0_P6_U1_PLD_ORT3 0x40010cb6\r
+#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8\r
+#define CYREG_B0_P6_U1_MC_CFG_XORFB 0x40010cba\r
+#define CYREG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbc\r
+#define CYREG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbe\r
+#define CYREG_B0_P6_U1_CFG0 0x40010cc0\r
+#define CYREG_B0_P6_U1_CFG1 0x40010cc1\r
+#define CYREG_B0_P6_U1_CFG2 0x40010cc2\r
+#define CYREG_B0_P6_U1_CFG3 0x40010cc3\r
+#define CYREG_B0_P6_U1_CFG4 0x40010cc4\r
+#define CYREG_B0_P6_U1_CFG5 0x40010cc5\r
+#define CYREG_B0_P6_U1_CFG6 0x40010cc6\r
+#define CYREG_B0_P6_U1_CFG7 0x40010cc7\r
+#define CYREG_B0_P6_U1_CFG8 0x40010cc8\r
+#define CYREG_B0_P6_U1_CFG9 0x40010cc9\r
+#define CYREG_B0_P6_U1_CFG10 0x40010cca\r
+#define CYREG_B0_P6_U1_CFG11 0x40010ccb\r
+#define CYREG_B0_P6_U1_CFG12 0x40010ccc\r
+#define CYREG_B0_P6_U1_CFG13 0x40010ccd\r
+#define CYREG_B0_P6_U1_CFG14 0x40010cce\r
+#define CYREG_B0_P6_U1_CFG15 0x40010ccf\r
+#define CYREG_B0_P6_U1_CFG16 0x40010cd0\r
+#define CYREG_B0_P6_U1_CFG17 0x40010cd1\r
+#define CYREG_B0_P6_U1_CFG18 0x40010cd2\r
+#define CYREG_B0_P6_U1_CFG19 0x40010cd3\r
+#define CYREG_B0_P6_U1_CFG20 0x40010cd4\r
+#define CYREG_B0_P6_U1_CFG21 0x40010cd5\r
+#define CYREG_B0_P6_U1_CFG22 0x40010cd6\r
+#define CYREG_B0_P6_U1_CFG23 0x40010cd7\r
+#define CYREG_B0_P6_U1_CFG24 0x40010cd8\r
+#define CYREG_B0_P6_U1_CFG25 0x40010cd9\r
+#define CYREG_B0_P6_U1_CFG26 0x40010cda\r
+#define CYREG_B0_P6_U1_CFG27 0x40010cdb\r
+#define CYREG_B0_P6_U1_CFG28 0x40010cdc\r
+#define CYREG_B0_P6_U1_CFG29 0x40010cdd\r
+#define CYREG_B0_P6_U1_CFG30 0x40010cde\r
+#define CYREG_B0_P6_U1_CFG31 0x40010cdf\r
+#define CYREG_B0_P6_U1_DCFG0 0x40010ce0\r
+#define CYREG_B0_P6_U1_DCFG1 0x40010ce2\r
+#define CYREG_B0_P6_U1_DCFG2 0x40010ce4\r
+#define CYREG_B0_P6_U1_DCFG3 0x40010ce6\r
+#define CYREG_B0_P6_U1_DCFG4 0x40010ce8\r
+#define CYREG_B0_P6_U1_DCFG5 0x40010cea\r
+#define CYREG_B0_P6_U1_DCFG6 0x40010cec\r
+#define CYREG_B0_P6_U1_DCFG7 0x40010cee\r
+#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00\r
+#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B0_P7_BASE 0x40010e00\r
+#define CYDEV_UCFG_B0_P7_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00\r
+#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070\r
+#define CYREG_B0_P7_U0_PLD_IT0 0x40010e00\r
+#define CYREG_B0_P7_U0_PLD_IT1 0x40010e04\r
+#define CYREG_B0_P7_U0_PLD_IT2 0x40010e08\r
+#define CYREG_B0_P7_U0_PLD_IT3 0x40010e0c\r
+#define CYREG_B0_P7_U0_PLD_IT4 0x40010e10\r
+#define CYREG_B0_P7_U0_PLD_IT5 0x40010e14\r
+#define CYREG_B0_P7_U0_PLD_IT6 0x40010e18\r
+#define CYREG_B0_P7_U0_PLD_IT7 0x40010e1c\r
+#define CYREG_B0_P7_U0_PLD_IT8 0x40010e20\r
+#define CYREG_B0_P7_U0_PLD_IT9 0x40010e24\r
+#define CYREG_B0_P7_U0_PLD_IT10 0x40010e28\r
+#define CYREG_B0_P7_U0_PLD_IT11 0x40010e2c\r
+#define CYREG_B0_P7_U0_PLD_ORT0 0x40010e30\r
+#define CYREG_B0_P7_U0_PLD_ORT1 0x40010e32\r
+#define CYREG_B0_P7_U0_PLD_ORT2 0x40010e34\r
+#define CYREG_B0_P7_U0_PLD_ORT3 0x40010e36\r
+#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38\r
+#define CYREG_B0_P7_U0_MC_CFG_XORFB 0x40010e3a\r
+#define CYREG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3c\r
+#define CYREG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3e\r
+#define CYREG_B0_P7_U0_CFG0 0x40010e40\r
+#define CYREG_B0_P7_U0_CFG1 0x40010e41\r
+#define CYREG_B0_P7_U0_CFG2 0x40010e42\r
+#define CYREG_B0_P7_U0_CFG3 0x40010e43\r
+#define CYREG_B0_P7_U0_CFG4 0x40010e44\r
+#define CYREG_B0_P7_U0_CFG5 0x40010e45\r
+#define CYREG_B0_P7_U0_CFG6 0x40010e46\r
+#define CYREG_B0_P7_U0_CFG7 0x40010e47\r
+#define CYREG_B0_P7_U0_CFG8 0x40010e48\r
+#define CYREG_B0_P7_U0_CFG9 0x40010e49\r
+#define CYREG_B0_P7_U0_CFG10 0x40010e4a\r
+#define CYREG_B0_P7_U0_CFG11 0x40010e4b\r
+#define CYREG_B0_P7_U0_CFG12 0x40010e4c\r
+#define CYREG_B0_P7_U0_CFG13 0x40010e4d\r
+#define CYREG_B0_P7_U0_CFG14 0x40010e4e\r
+#define CYREG_B0_P7_U0_CFG15 0x40010e4f\r
+#define CYREG_B0_P7_U0_CFG16 0x40010e50\r
+#define CYREG_B0_P7_U0_CFG17 0x40010e51\r
+#define CYREG_B0_P7_U0_CFG18 0x40010e52\r
+#define CYREG_B0_P7_U0_CFG19 0x40010e53\r
+#define CYREG_B0_P7_U0_CFG20 0x40010e54\r
+#define CYREG_B0_P7_U0_CFG21 0x40010e55\r
+#define CYREG_B0_P7_U0_CFG22 0x40010e56\r
+#define CYREG_B0_P7_U0_CFG23 0x40010e57\r
+#define CYREG_B0_P7_U0_CFG24 0x40010e58\r
+#define CYREG_B0_P7_U0_CFG25 0x40010e59\r
+#define CYREG_B0_P7_U0_CFG26 0x40010e5a\r
+#define CYREG_B0_P7_U0_CFG27 0x40010e5b\r
+#define CYREG_B0_P7_U0_CFG28 0x40010e5c\r
+#define CYREG_B0_P7_U0_CFG29 0x40010e5d\r
+#define CYREG_B0_P7_U0_CFG30 0x40010e5e\r
+#define CYREG_B0_P7_U0_CFG31 0x40010e5f\r
+#define CYREG_B0_P7_U0_DCFG0 0x40010e60\r
+#define CYREG_B0_P7_U0_DCFG1 0x40010e62\r
+#define CYREG_B0_P7_U0_DCFG2 0x40010e64\r
+#define CYREG_B0_P7_U0_DCFG3 0x40010e66\r
+#define CYREG_B0_P7_U0_DCFG4 0x40010e68\r
+#define CYREG_B0_P7_U0_DCFG5 0x40010e6a\r
+#define CYREG_B0_P7_U0_DCFG6 0x40010e6c\r
+#define CYREG_B0_P7_U0_DCFG7 0x40010e6e\r
+#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80\r
+#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070\r
+#define CYREG_B0_P7_U1_PLD_IT0 0x40010e80\r
+#define CYREG_B0_P7_U1_PLD_IT1 0x40010e84\r
+#define CYREG_B0_P7_U1_PLD_IT2 0x40010e88\r
+#define CYREG_B0_P7_U1_PLD_IT3 0x40010e8c\r
+#define CYREG_B0_P7_U1_PLD_IT4 0x40010e90\r
+#define CYREG_B0_P7_U1_PLD_IT5 0x40010e94\r
+#define CYREG_B0_P7_U1_PLD_IT6 0x40010e98\r
+#define CYREG_B0_P7_U1_PLD_IT7 0x40010e9c\r
+#define CYREG_B0_P7_U1_PLD_IT8 0x40010ea0\r
+#define CYREG_B0_P7_U1_PLD_IT9 0x40010ea4\r
+#define CYREG_B0_P7_U1_PLD_IT10 0x40010ea8\r
+#define CYREG_B0_P7_U1_PLD_IT11 0x40010eac\r
+#define CYREG_B0_P7_U1_PLD_ORT0 0x40010eb0\r
+#define CYREG_B0_P7_U1_PLD_ORT1 0x40010eb2\r
+#define CYREG_B0_P7_U1_PLD_ORT2 0x40010eb4\r
+#define CYREG_B0_P7_U1_PLD_ORT3 0x40010eb6\r
+#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8\r
+#define CYREG_B0_P7_U1_MC_CFG_XORFB 0x40010eba\r
+#define CYREG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebc\r
+#define CYREG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebe\r
+#define CYREG_B0_P7_U1_CFG0 0x40010ec0\r
+#define CYREG_B0_P7_U1_CFG1 0x40010ec1\r
+#define CYREG_B0_P7_U1_CFG2 0x40010ec2\r
+#define CYREG_B0_P7_U1_CFG3 0x40010ec3\r
+#define CYREG_B0_P7_U1_CFG4 0x40010ec4\r
+#define CYREG_B0_P7_U1_CFG5 0x40010ec5\r
+#define CYREG_B0_P7_U1_CFG6 0x40010ec6\r
+#define CYREG_B0_P7_U1_CFG7 0x40010ec7\r
+#define CYREG_B0_P7_U1_CFG8 0x40010ec8\r
+#define CYREG_B0_P7_U1_CFG9 0x40010ec9\r
+#define CYREG_B0_P7_U1_CFG10 0x40010eca\r
+#define CYREG_B0_P7_U1_CFG11 0x40010ecb\r
+#define CYREG_B0_P7_U1_CFG12 0x40010ecc\r
+#define CYREG_B0_P7_U1_CFG13 0x40010ecd\r
+#define CYREG_B0_P7_U1_CFG14 0x40010ece\r
+#define CYREG_B0_P7_U1_CFG15 0x40010ecf\r
+#define CYREG_B0_P7_U1_CFG16 0x40010ed0\r
+#define CYREG_B0_P7_U1_CFG17 0x40010ed1\r
+#define CYREG_B0_P7_U1_CFG18 0x40010ed2\r
+#define CYREG_B0_P7_U1_CFG19 0x40010ed3\r
+#define CYREG_B0_P7_U1_CFG20 0x40010ed4\r
+#define CYREG_B0_P7_U1_CFG21 0x40010ed5\r
+#define CYREG_B0_P7_U1_CFG22 0x40010ed6\r
+#define CYREG_B0_P7_U1_CFG23 0x40010ed7\r
+#define CYREG_B0_P7_U1_CFG24 0x40010ed8\r
+#define CYREG_B0_P7_U1_CFG25 0x40010ed9\r
+#define CYREG_B0_P7_U1_CFG26 0x40010eda\r
+#define CYREG_B0_P7_U1_CFG27 0x40010edb\r
+#define CYREG_B0_P7_U1_CFG28 0x40010edc\r
+#define CYREG_B0_P7_U1_CFG29 0x40010edd\r
+#define CYREG_B0_P7_U1_CFG30 0x40010ede\r
+#define CYREG_B0_P7_U1_CFG31 0x40010edf\r
+#define CYREG_B0_P7_U1_DCFG0 0x40010ee0\r
+#define CYREG_B0_P7_U1_DCFG1 0x40010ee2\r
+#define CYREG_B0_P7_U1_DCFG2 0x40010ee4\r
+#define CYREG_B0_P7_U1_DCFG3 0x40010ee6\r
+#define CYREG_B0_P7_U1_DCFG4 0x40010ee8\r
+#define CYREG_B0_P7_U1_DCFG5 0x40010eea\r
+#define CYREG_B0_P7_U1_DCFG6 0x40010eec\r
+#define CYREG_B0_P7_U1_DCFG7 0x40010eee\r
+#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00\r
+#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B1_BASE 0x40011000\r
+#define CYDEV_UCFG_B1_SIZE 0x00000fef\r
+#define CYDEV_UCFG_B1_P2_BASE 0x40011400\r
+#define CYDEV_UCFG_B1_P2_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400\r
+#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070\r
+#define CYREG_B1_P2_U0_PLD_IT0 0x40011400\r
+#define CYREG_B1_P2_U0_PLD_IT1 0x40011404\r
+#define CYREG_B1_P2_U0_PLD_IT2 0x40011408\r
+#define CYREG_B1_P2_U0_PLD_IT3 0x4001140c\r
+#define CYREG_B1_P2_U0_PLD_IT4 0x40011410\r
+#define CYREG_B1_P2_U0_PLD_IT5 0x40011414\r
+#define CYREG_B1_P2_U0_PLD_IT6 0x40011418\r
+#define CYREG_B1_P2_U0_PLD_IT7 0x4001141c\r
+#define CYREG_B1_P2_U0_PLD_IT8 0x40011420\r
+#define CYREG_B1_P2_U0_PLD_IT9 0x40011424\r
+#define CYREG_B1_P2_U0_PLD_IT10 0x40011428\r
+#define CYREG_B1_P2_U0_PLD_IT11 0x4001142c\r
+#define CYREG_B1_P2_U0_PLD_ORT0 0x40011430\r
+#define CYREG_B1_P2_U0_PLD_ORT1 0x40011432\r
+#define CYREG_B1_P2_U0_PLD_ORT2 0x40011434\r
+#define CYREG_B1_P2_U0_PLD_ORT3 0x40011436\r
+#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438\r
+#define CYREG_B1_P2_U0_MC_CFG_XORFB 0x4001143a\r
+#define CYREG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143c\r
+#define CYREG_B1_P2_U0_MC_CFG_BYPASS 0x4001143e\r
+#define CYREG_B1_P2_U0_CFG0 0x40011440\r
+#define CYREG_B1_P2_U0_CFG1 0x40011441\r
+#define CYREG_B1_P2_U0_CFG2 0x40011442\r
+#define CYREG_B1_P2_U0_CFG3 0x40011443\r
+#define CYREG_B1_P2_U0_CFG4 0x40011444\r
+#define CYREG_B1_P2_U0_CFG5 0x40011445\r
+#define CYREG_B1_P2_U0_CFG6 0x40011446\r
+#define CYREG_B1_P2_U0_CFG7 0x40011447\r
+#define CYREG_B1_P2_U0_CFG8 0x40011448\r
+#define CYREG_B1_P2_U0_CFG9 0x40011449\r
+#define CYREG_B1_P2_U0_CFG10 0x4001144a\r
+#define CYREG_B1_P2_U0_CFG11 0x4001144b\r
+#define CYREG_B1_P2_U0_CFG12 0x4001144c\r
+#define CYREG_B1_P2_U0_CFG13 0x4001144d\r
+#define CYREG_B1_P2_U0_CFG14 0x4001144e\r
+#define CYREG_B1_P2_U0_CFG15 0x4001144f\r
+#define CYREG_B1_P2_U0_CFG16 0x40011450\r
+#define CYREG_B1_P2_U0_CFG17 0x40011451\r
+#define CYREG_B1_P2_U0_CFG18 0x40011452\r
+#define CYREG_B1_P2_U0_CFG19 0x40011453\r
+#define CYREG_B1_P2_U0_CFG20 0x40011454\r
+#define CYREG_B1_P2_U0_CFG21 0x40011455\r
+#define CYREG_B1_P2_U0_CFG22 0x40011456\r
+#define CYREG_B1_P2_U0_CFG23 0x40011457\r
+#define CYREG_B1_P2_U0_CFG24 0x40011458\r
+#define CYREG_B1_P2_U0_CFG25 0x40011459\r
+#define CYREG_B1_P2_U0_CFG26 0x4001145a\r
+#define CYREG_B1_P2_U0_CFG27 0x4001145b\r
+#define CYREG_B1_P2_U0_CFG28 0x4001145c\r
+#define CYREG_B1_P2_U0_CFG29 0x4001145d\r
+#define CYREG_B1_P2_U0_CFG30 0x4001145e\r
+#define CYREG_B1_P2_U0_CFG31 0x4001145f\r
+#define CYREG_B1_P2_U0_DCFG0 0x40011460\r
+#define CYREG_B1_P2_U0_DCFG1 0x40011462\r
+#define CYREG_B1_P2_U0_DCFG2 0x40011464\r
+#define CYREG_B1_P2_U0_DCFG3 0x40011466\r
+#define CYREG_B1_P2_U0_DCFG4 0x40011468\r
+#define CYREG_B1_P2_U0_DCFG5 0x4001146a\r
+#define CYREG_B1_P2_U0_DCFG6 0x4001146c\r
+#define CYREG_B1_P2_U0_DCFG7 0x4001146e\r
+#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480\r
+#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070\r
+#define CYREG_B1_P2_U1_PLD_IT0 0x40011480\r
+#define CYREG_B1_P2_U1_PLD_IT1 0x40011484\r
+#define CYREG_B1_P2_U1_PLD_IT2 0x40011488\r
+#define CYREG_B1_P2_U1_PLD_IT3 0x4001148c\r
+#define CYREG_B1_P2_U1_PLD_IT4 0x40011490\r
+#define CYREG_B1_P2_U1_PLD_IT5 0x40011494\r
+#define CYREG_B1_P2_U1_PLD_IT6 0x40011498\r
+#define CYREG_B1_P2_U1_PLD_IT7 0x4001149c\r
+#define CYREG_B1_P2_U1_PLD_IT8 0x400114a0\r
+#define CYREG_B1_P2_U1_PLD_IT9 0x400114a4\r
+#define CYREG_B1_P2_U1_PLD_IT10 0x400114a8\r
+#define CYREG_B1_P2_U1_PLD_IT11 0x400114ac\r
+#define CYREG_B1_P2_U1_PLD_ORT0 0x400114b0\r
+#define CYREG_B1_P2_U1_PLD_ORT1 0x400114b2\r
+#define CYREG_B1_P2_U1_PLD_ORT2 0x400114b4\r
+#define CYREG_B1_P2_U1_PLD_ORT3 0x400114b6\r
+#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8\r
+#define CYREG_B1_P2_U1_MC_CFG_XORFB 0x400114ba\r
+#define CYREG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bc\r
+#define CYREG_B1_P2_U1_MC_CFG_BYPASS 0x400114be\r
+#define CYREG_B1_P2_U1_CFG0 0x400114c0\r
+#define CYREG_B1_P2_U1_CFG1 0x400114c1\r
+#define CYREG_B1_P2_U1_CFG2 0x400114c2\r
+#define CYREG_B1_P2_U1_CFG3 0x400114c3\r
+#define CYREG_B1_P2_U1_CFG4 0x400114c4\r
+#define CYREG_B1_P2_U1_CFG5 0x400114c5\r
+#define CYREG_B1_P2_U1_CFG6 0x400114c6\r
+#define CYREG_B1_P2_U1_CFG7 0x400114c7\r
+#define CYREG_B1_P2_U1_CFG8 0x400114c8\r
+#define CYREG_B1_P2_U1_CFG9 0x400114c9\r
+#define CYREG_B1_P2_U1_CFG10 0x400114ca\r
+#define CYREG_B1_P2_U1_CFG11 0x400114cb\r
+#define CYREG_B1_P2_U1_CFG12 0x400114cc\r
+#define CYREG_B1_P2_U1_CFG13 0x400114cd\r
+#define CYREG_B1_P2_U1_CFG14 0x400114ce\r
+#define CYREG_B1_P2_U1_CFG15 0x400114cf\r
+#define CYREG_B1_P2_U1_CFG16 0x400114d0\r
+#define CYREG_B1_P2_U1_CFG17 0x400114d1\r
+#define CYREG_B1_P2_U1_CFG18 0x400114d2\r
+#define CYREG_B1_P2_U1_CFG19 0x400114d3\r
+#define CYREG_B1_P2_U1_CFG20 0x400114d4\r
+#define CYREG_B1_P2_U1_CFG21 0x400114d5\r
+#define CYREG_B1_P2_U1_CFG22 0x400114d6\r
+#define CYREG_B1_P2_U1_CFG23 0x400114d7\r
+#define CYREG_B1_P2_U1_CFG24 0x400114d8\r
+#define CYREG_B1_P2_U1_CFG25 0x400114d9\r
+#define CYREG_B1_P2_U1_CFG26 0x400114da\r
+#define CYREG_B1_P2_U1_CFG27 0x400114db\r
+#define CYREG_B1_P2_U1_CFG28 0x400114dc\r
+#define CYREG_B1_P2_U1_CFG29 0x400114dd\r
+#define CYREG_B1_P2_U1_CFG30 0x400114de\r
+#define CYREG_B1_P2_U1_CFG31 0x400114df\r
+#define CYREG_B1_P2_U1_DCFG0 0x400114e0\r
+#define CYREG_B1_P2_U1_DCFG1 0x400114e2\r
+#define CYREG_B1_P2_U1_DCFG2 0x400114e4\r
+#define CYREG_B1_P2_U1_DCFG3 0x400114e6\r
+#define CYREG_B1_P2_U1_DCFG4 0x400114e8\r
+#define CYREG_B1_P2_U1_DCFG5 0x400114ea\r
+#define CYREG_B1_P2_U1_DCFG6 0x400114ec\r
+#define CYREG_B1_P2_U1_DCFG7 0x400114ee\r
+#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500\r
+#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B1_P3_BASE 0x40011600\r
+#define CYDEV_UCFG_B1_P3_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600\r
+#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070\r
+#define CYREG_B1_P3_U0_PLD_IT0 0x40011600\r
+#define CYREG_B1_P3_U0_PLD_IT1 0x40011604\r
+#define CYREG_B1_P3_U0_PLD_IT2 0x40011608\r
+#define CYREG_B1_P3_U0_PLD_IT3 0x4001160c\r
+#define CYREG_B1_P3_U0_PLD_IT4 0x40011610\r
+#define CYREG_B1_P3_U0_PLD_IT5 0x40011614\r
+#define CYREG_B1_P3_U0_PLD_IT6 0x40011618\r
+#define CYREG_B1_P3_U0_PLD_IT7 0x4001161c\r
+#define CYREG_B1_P3_U0_PLD_IT8 0x40011620\r
+#define CYREG_B1_P3_U0_PLD_IT9 0x40011624\r
+#define CYREG_B1_P3_U0_PLD_IT10 0x40011628\r
+#define CYREG_B1_P3_U0_PLD_IT11 0x4001162c\r
+#define CYREG_B1_P3_U0_PLD_ORT0 0x40011630\r
+#define CYREG_B1_P3_U0_PLD_ORT1 0x40011632\r
+#define CYREG_B1_P3_U0_PLD_ORT2 0x40011634\r
+#define CYREG_B1_P3_U0_PLD_ORT3 0x40011636\r
+#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638\r
+#define CYREG_B1_P3_U0_MC_CFG_XORFB 0x4001163a\r
+#define CYREG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163c\r
+#define CYREG_B1_P3_U0_MC_CFG_BYPASS 0x4001163e\r
+#define CYREG_B1_P3_U0_CFG0 0x40011640\r
+#define CYREG_B1_P3_U0_CFG1 0x40011641\r
+#define CYREG_B1_P3_U0_CFG2 0x40011642\r
+#define CYREG_B1_P3_U0_CFG3 0x40011643\r
+#define CYREG_B1_P3_U0_CFG4 0x40011644\r
+#define CYREG_B1_P3_U0_CFG5 0x40011645\r
+#define CYREG_B1_P3_U0_CFG6 0x40011646\r
+#define CYREG_B1_P3_U0_CFG7 0x40011647\r
+#define CYREG_B1_P3_U0_CFG8 0x40011648\r
+#define CYREG_B1_P3_U0_CFG9 0x40011649\r
+#define CYREG_B1_P3_U0_CFG10 0x4001164a\r
+#define CYREG_B1_P3_U0_CFG11 0x4001164b\r
+#define CYREG_B1_P3_U0_CFG12 0x4001164c\r
+#define CYREG_B1_P3_U0_CFG13 0x4001164d\r
+#define CYREG_B1_P3_U0_CFG14 0x4001164e\r
+#define CYREG_B1_P3_U0_CFG15 0x4001164f\r
+#define CYREG_B1_P3_U0_CFG16 0x40011650\r
+#define CYREG_B1_P3_U0_CFG17 0x40011651\r
+#define CYREG_B1_P3_U0_CFG18 0x40011652\r
+#define CYREG_B1_P3_U0_CFG19 0x40011653\r
+#define CYREG_B1_P3_U0_CFG20 0x40011654\r
+#define CYREG_B1_P3_U0_CFG21 0x40011655\r
+#define CYREG_B1_P3_U0_CFG22 0x40011656\r
+#define CYREG_B1_P3_U0_CFG23 0x40011657\r
+#define CYREG_B1_P3_U0_CFG24 0x40011658\r
+#define CYREG_B1_P3_U0_CFG25 0x40011659\r
+#define CYREG_B1_P3_U0_CFG26 0x4001165a\r
+#define CYREG_B1_P3_U0_CFG27 0x4001165b\r
+#define CYREG_B1_P3_U0_CFG28 0x4001165c\r
+#define CYREG_B1_P3_U0_CFG29 0x4001165d\r
+#define CYREG_B1_P3_U0_CFG30 0x4001165e\r
+#define CYREG_B1_P3_U0_CFG31 0x4001165f\r
+#define CYREG_B1_P3_U0_DCFG0 0x40011660\r
+#define CYREG_B1_P3_U0_DCFG1 0x40011662\r
+#define CYREG_B1_P3_U0_DCFG2 0x40011664\r
+#define CYREG_B1_P3_U0_DCFG3 0x40011666\r
+#define CYREG_B1_P3_U0_DCFG4 0x40011668\r
+#define CYREG_B1_P3_U0_DCFG5 0x4001166a\r
+#define CYREG_B1_P3_U0_DCFG6 0x4001166c\r
+#define CYREG_B1_P3_U0_DCFG7 0x4001166e\r
+#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680\r
+#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070\r
+#define CYREG_B1_P3_U1_PLD_IT0 0x40011680\r
+#define CYREG_B1_P3_U1_PLD_IT1 0x40011684\r
+#define CYREG_B1_P3_U1_PLD_IT2 0x40011688\r
+#define CYREG_B1_P3_U1_PLD_IT3 0x4001168c\r
+#define CYREG_B1_P3_U1_PLD_IT4 0x40011690\r
+#define CYREG_B1_P3_U1_PLD_IT5 0x40011694\r
+#define CYREG_B1_P3_U1_PLD_IT6 0x40011698\r
+#define CYREG_B1_P3_U1_PLD_IT7 0x4001169c\r
+#define CYREG_B1_P3_U1_PLD_IT8 0x400116a0\r
+#define CYREG_B1_P3_U1_PLD_IT9 0x400116a4\r
+#define CYREG_B1_P3_U1_PLD_IT10 0x400116a8\r
+#define CYREG_B1_P3_U1_PLD_IT11 0x400116ac\r
+#define CYREG_B1_P3_U1_PLD_ORT0 0x400116b0\r
+#define CYREG_B1_P3_U1_PLD_ORT1 0x400116b2\r
+#define CYREG_B1_P3_U1_PLD_ORT2 0x400116b4\r
+#define CYREG_B1_P3_U1_PLD_ORT3 0x400116b6\r
+#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8\r
+#define CYREG_B1_P3_U1_MC_CFG_XORFB 0x400116ba\r
+#define CYREG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bc\r
+#define CYREG_B1_P3_U1_MC_CFG_BYPASS 0x400116be\r
+#define CYREG_B1_P3_U1_CFG0 0x400116c0\r
+#define CYREG_B1_P3_U1_CFG1 0x400116c1\r
+#define CYREG_B1_P3_U1_CFG2 0x400116c2\r
+#define CYREG_B1_P3_U1_CFG3 0x400116c3\r
+#define CYREG_B1_P3_U1_CFG4 0x400116c4\r
+#define CYREG_B1_P3_U1_CFG5 0x400116c5\r
+#define CYREG_B1_P3_U1_CFG6 0x400116c6\r
+#define CYREG_B1_P3_U1_CFG7 0x400116c7\r
+#define CYREG_B1_P3_U1_CFG8 0x400116c8\r
+#define CYREG_B1_P3_U1_CFG9 0x400116c9\r
+#define CYREG_B1_P3_U1_CFG10 0x400116ca\r
+#define CYREG_B1_P3_U1_CFG11 0x400116cb\r
+#define CYREG_B1_P3_U1_CFG12 0x400116cc\r
+#define CYREG_B1_P3_U1_CFG13 0x400116cd\r
+#define CYREG_B1_P3_U1_CFG14 0x400116ce\r
+#define CYREG_B1_P3_U1_CFG15 0x400116cf\r
+#define CYREG_B1_P3_U1_CFG16 0x400116d0\r
+#define CYREG_B1_P3_U1_CFG17 0x400116d1\r
+#define CYREG_B1_P3_U1_CFG18 0x400116d2\r
+#define CYREG_B1_P3_U1_CFG19 0x400116d3\r
+#define CYREG_B1_P3_U1_CFG20 0x400116d4\r
+#define CYREG_B1_P3_U1_CFG21 0x400116d5\r
+#define CYREG_B1_P3_U1_CFG22 0x400116d6\r
+#define CYREG_B1_P3_U1_CFG23 0x400116d7\r
+#define CYREG_B1_P3_U1_CFG24 0x400116d8\r
+#define CYREG_B1_P3_U1_CFG25 0x400116d9\r
+#define CYREG_B1_P3_U1_CFG26 0x400116da\r
+#define CYREG_B1_P3_U1_CFG27 0x400116db\r
+#define CYREG_B1_P3_U1_CFG28 0x400116dc\r
+#define CYREG_B1_P3_U1_CFG29 0x400116dd\r
+#define CYREG_B1_P3_U1_CFG30 0x400116de\r
+#define CYREG_B1_P3_U1_CFG31 0x400116df\r
+#define CYREG_B1_P3_U1_DCFG0 0x400116e0\r
+#define CYREG_B1_P3_U1_DCFG1 0x400116e2\r
+#define CYREG_B1_P3_U1_DCFG2 0x400116e4\r
+#define CYREG_B1_P3_U1_DCFG3 0x400116e6\r
+#define CYREG_B1_P3_U1_DCFG4 0x400116e8\r
+#define CYREG_B1_P3_U1_DCFG5 0x400116ea\r
+#define CYREG_B1_P3_U1_DCFG6 0x400116ec\r
+#define CYREG_B1_P3_U1_DCFG7 0x400116ee\r
+#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700\r
+#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B1_P4_BASE 0x40011800\r
+#define CYDEV_UCFG_B1_P4_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800\r
+#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070\r
+#define CYREG_B1_P4_U0_PLD_IT0 0x40011800\r
+#define CYREG_B1_P4_U0_PLD_IT1 0x40011804\r
+#define CYREG_B1_P4_U0_PLD_IT2 0x40011808\r
+#define CYREG_B1_P4_U0_PLD_IT3 0x4001180c\r
+#define CYREG_B1_P4_U0_PLD_IT4 0x40011810\r
+#define CYREG_B1_P4_U0_PLD_IT5 0x40011814\r
+#define CYREG_B1_P4_U0_PLD_IT6 0x40011818\r
+#define CYREG_B1_P4_U0_PLD_IT7 0x4001181c\r
+#define CYREG_B1_P4_U0_PLD_IT8 0x40011820\r
+#define CYREG_B1_P4_U0_PLD_IT9 0x40011824\r
+#define CYREG_B1_P4_U0_PLD_IT10 0x40011828\r
+#define CYREG_B1_P4_U0_PLD_IT11 0x4001182c\r
+#define CYREG_B1_P4_U0_PLD_ORT0 0x40011830\r
+#define CYREG_B1_P4_U0_PLD_ORT1 0x40011832\r
+#define CYREG_B1_P4_U0_PLD_ORT2 0x40011834\r
+#define CYREG_B1_P4_U0_PLD_ORT3 0x40011836\r
+#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838\r
+#define CYREG_B1_P4_U0_MC_CFG_XORFB 0x4001183a\r
+#define CYREG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183c\r
+#define CYREG_B1_P4_U0_MC_CFG_BYPASS 0x4001183e\r
+#define CYREG_B1_P4_U0_CFG0 0x40011840\r
+#define CYREG_B1_P4_U0_CFG1 0x40011841\r
+#define CYREG_B1_P4_U0_CFG2 0x40011842\r
+#define CYREG_B1_P4_U0_CFG3 0x40011843\r
+#define CYREG_B1_P4_U0_CFG4 0x40011844\r
+#define CYREG_B1_P4_U0_CFG5 0x40011845\r
+#define CYREG_B1_P4_U0_CFG6 0x40011846\r
+#define CYREG_B1_P4_U0_CFG7 0x40011847\r
+#define CYREG_B1_P4_U0_CFG8 0x40011848\r
+#define CYREG_B1_P4_U0_CFG9 0x40011849\r
+#define CYREG_B1_P4_U0_CFG10 0x4001184a\r
+#define CYREG_B1_P4_U0_CFG11 0x4001184b\r
+#define CYREG_B1_P4_U0_CFG12 0x4001184c\r
+#define CYREG_B1_P4_U0_CFG13 0x4001184d\r
+#define CYREG_B1_P4_U0_CFG14 0x4001184e\r
+#define CYREG_B1_P4_U0_CFG15 0x4001184f\r
+#define CYREG_B1_P4_U0_CFG16 0x40011850\r
+#define CYREG_B1_P4_U0_CFG17 0x40011851\r
+#define CYREG_B1_P4_U0_CFG18 0x40011852\r
+#define CYREG_B1_P4_U0_CFG19 0x40011853\r
+#define CYREG_B1_P4_U0_CFG20 0x40011854\r
+#define CYREG_B1_P4_U0_CFG21 0x40011855\r
+#define CYREG_B1_P4_U0_CFG22 0x40011856\r
+#define CYREG_B1_P4_U0_CFG23 0x40011857\r
+#define CYREG_B1_P4_U0_CFG24 0x40011858\r
+#define CYREG_B1_P4_U0_CFG25 0x40011859\r
+#define CYREG_B1_P4_U0_CFG26 0x4001185a\r
+#define CYREG_B1_P4_U0_CFG27 0x4001185b\r
+#define CYREG_B1_P4_U0_CFG28 0x4001185c\r
+#define CYREG_B1_P4_U0_CFG29 0x4001185d\r
+#define CYREG_B1_P4_U0_CFG30 0x4001185e\r
+#define CYREG_B1_P4_U0_CFG31 0x4001185f\r
+#define CYREG_B1_P4_U0_DCFG0 0x40011860\r
+#define CYREG_B1_P4_U0_DCFG1 0x40011862\r
+#define CYREG_B1_P4_U0_DCFG2 0x40011864\r
+#define CYREG_B1_P4_U0_DCFG3 0x40011866\r
+#define CYREG_B1_P4_U0_DCFG4 0x40011868\r
+#define CYREG_B1_P4_U0_DCFG5 0x4001186a\r
+#define CYREG_B1_P4_U0_DCFG6 0x4001186c\r
+#define CYREG_B1_P4_U0_DCFG7 0x4001186e\r
+#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880\r
+#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070\r
+#define CYREG_B1_P4_U1_PLD_IT0 0x40011880\r
+#define CYREG_B1_P4_U1_PLD_IT1 0x40011884\r
+#define CYREG_B1_P4_U1_PLD_IT2 0x40011888\r
+#define CYREG_B1_P4_U1_PLD_IT3 0x4001188c\r
+#define CYREG_B1_P4_U1_PLD_IT4 0x40011890\r
+#define CYREG_B1_P4_U1_PLD_IT5 0x40011894\r
+#define CYREG_B1_P4_U1_PLD_IT6 0x40011898\r
+#define CYREG_B1_P4_U1_PLD_IT7 0x4001189c\r
+#define CYREG_B1_P4_U1_PLD_IT8 0x400118a0\r
+#define CYREG_B1_P4_U1_PLD_IT9 0x400118a4\r
+#define CYREG_B1_P4_U1_PLD_IT10 0x400118a8\r
+#define CYREG_B1_P4_U1_PLD_IT11 0x400118ac\r
+#define CYREG_B1_P4_U1_PLD_ORT0 0x400118b0\r
+#define CYREG_B1_P4_U1_PLD_ORT1 0x400118b2\r
+#define CYREG_B1_P4_U1_PLD_ORT2 0x400118b4\r
+#define CYREG_B1_P4_U1_PLD_ORT3 0x400118b6\r
+#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8\r
+#define CYREG_B1_P4_U1_MC_CFG_XORFB 0x400118ba\r
+#define CYREG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bc\r
+#define CYREG_B1_P4_U1_MC_CFG_BYPASS 0x400118be\r
+#define CYREG_B1_P4_U1_CFG0 0x400118c0\r
+#define CYREG_B1_P4_U1_CFG1 0x400118c1\r
+#define CYREG_B1_P4_U1_CFG2 0x400118c2\r
+#define CYREG_B1_P4_U1_CFG3 0x400118c3\r
+#define CYREG_B1_P4_U1_CFG4 0x400118c4\r
+#define CYREG_B1_P4_U1_CFG5 0x400118c5\r
+#define CYREG_B1_P4_U1_CFG6 0x400118c6\r
+#define CYREG_B1_P4_U1_CFG7 0x400118c7\r
+#define CYREG_B1_P4_U1_CFG8 0x400118c8\r
+#define CYREG_B1_P4_U1_CFG9 0x400118c9\r
+#define CYREG_B1_P4_U1_CFG10 0x400118ca\r
+#define CYREG_B1_P4_U1_CFG11 0x400118cb\r
+#define CYREG_B1_P4_U1_CFG12 0x400118cc\r
+#define CYREG_B1_P4_U1_CFG13 0x400118cd\r
+#define CYREG_B1_P4_U1_CFG14 0x400118ce\r
+#define CYREG_B1_P4_U1_CFG15 0x400118cf\r
+#define CYREG_B1_P4_U1_CFG16 0x400118d0\r
+#define CYREG_B1_P4_U1_CFG17 0x400118d1\r
+#define CYREG_B1_P4_U1_CFG18 0x400118d2\r
+#define CYREG_B1_P4_U1_CFG19 0x400118d3\r
+#define CYREG_B1_P4_U1_CFG20 0x400118d4\r
+#define CYREG_B1_P4_U1_CFG21 0x400118d5\r
+#define CYREG_B1_P4_U1_CFG22 0x400118d6\r
+#define CYREG_B1_P4_U1_CFG23 0x400118d7\r
+#define CYREG_B1_P4_U1_CFG24 0x400118d8\r
+#define CYREG_B1_P4_U1_CFG25 0x400118d9\r
+#define CYREG_B1_P4_U1_CFG26 0x400118da\r
+#define CYREG_B1_P4_U1_CFG27 0x400118db\r
+#define CYREG_B1_P4_U1_CFG28 0x400118dc\r
+#define CYREG_B1_P4_U1_CFG29 0x400118dd\r
+#define CYREG_B1_P4_U1_CFG30 0x400118de\r
+#define CYREG_B1_P4_U1_CFG31 0x400118df\r
+#define CYREG_B1_P4_U1_DCFG0 0x400118e0\r
+#define CYREG_B1_P4_U1_DCFG1 0x400118e2\r
+#define CYREG_B1_P4_U1_DCFG2 0x400118e4\r
+#define CYREG_B1_P4_U1_DCFG3 0x400118e6\r
+#define CYREG_B1_P4_U1_DCFG4 0x400118e8\r
+#define CYREG_B1_P4_U1_DCFG5 0x400118ea\r
+#define CYREG_B1_P4_U1_DCFG6 0x400118ec\r
+#define CYREG_B1_P4_U1_DCFG7 0x400118ee\r
+#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900\r
+#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_B1_P5_BASE 0x40011a00\r
+#define CYDEV_UCFG_B1_P5_SIZE 0x000001ef\r
+#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00\r
+#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070\r
+#define CYREG_B1_P5_U0_PLD_IT0 0x40011a00\r
+#define CYREG_B1_P5_U0_PLD_IT1 0x40011a04\r
+#define CYREG_B1_P5_U0_PLD_IT2 0x40011a08\r
+#define CYREG_B1_P5_U0_PLD_IT3 0x40011a0c\r
+#define CYREG_B1_P5_U0_PLD_IT4 0x40011a10\r
+#define CYREG_B1_P5_U0_PLD_IT5 0x40011a14\r
+#define CYREG_B1_P5_U0_PLD_IT6 0x40011a18\r
+#define CYREG_B1_P5_U0_PLD_IT7 0x40011a1c\r
+#define CYREG_B1_P5_U0_PLD_IT8 0x40011a20\r
+#define CYREG_B1_P5_U0_PLD_IT9 0x40011a24\r
+#define CYREG_B1_P5_U0_PLD_IT10 0x40011a28\r
+#define CYREG_B1_P5_U0_PLD_IT11 0x40011a2c\r
+#define CYREG_B1_P5_U0_PLD_ORT0 0x40011a30\r
+#define CYREG_B1_P5_U0_PLD_ORT1 0x40011a32\r
+#define CYREG_B1_P5_U0_PLD_ORT2 0x40011a34\r
+#define CYREG_B1_P5_U0_PLD_ORT3 0x40011a36\r
+#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38\r
+#define CYREG_B1_P5_U0_MC_CFG_XORFB 0x40011a3a\r
+#define CYREG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3c\r
+#define CYREG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3e\r
+#define CYREG_B1_P5_U0_CFG0 0x40011a40\r
+#define CYREG_B1_P5_U0_CFG1 0x40011a41\r
+#define CYREG_B1_P5_U0_CFG2 0x40011a42\r
+#define CYREG_B1_P5_U0_CFG3 0x40011a43\r
+#define CYREG_B1_P5_U0_CFG4 0x40011a44\r
+#define CYREG_B1_P5_U0_CFG5 0x40011a45\r
+#define CYREG_B1_P5_U0_CFG6 0x40011a46\r
+#define CYREG_B1_P5_U0_CFG7 0x40011a47\r
+#define CYREG_B1_P5_U0_CFG8 0x40011a48\r
+#define CYREG_B1_P5_U0_CFG9 0x40011a49\r
+#define CYREG_B1_P5_U0_CFG10 0x40011a4a\r
+#define CYREG_B1_P5_U0_CFG11 0x40011a4b\r
+#define CYREG_B1_P5_U0_CFG12 0x40011a4c\r
+#define CYREG_B1_P5_U0_CFG13 0x40011a4d\r
+#define CYREG_B1_P5_U0_CFG14 0x40011a4e\r
+#define CYREG_B1_P5_U0_CFG15 0x40011a4f\r
+#define CYREG_B1_P5_U0_CFG16 0x40011a50\r
+#define CYREG_B1_P5_U0_CFG17 0x40011a51\r
+#define CYREG_B1_P5_U0_CFG18 0x40011a52\r
+#define CYREG_B1_P5_U0_CFG19 0x40011a53\r
+#define CYREG_B1_P5_U0_CFG20 0x40011a54\r
+#define CYREG_B1_P5_U0_CFG21 0x40011a55\r
+#define CYREG_B1_P5_U0_CFG22 0x40011a56\r
+#define CYREG_B1_P5_U0_CFG23 0x40011a57\r
+#define CYREG_B1_P5_U0_CFG24 0x40011a58\r
+#define CYREG_B1_P5_U0_CFG25 0x40011a59\r
+#define CYREG_B1_P5_U0_CFG26 0x40011a5a\r
+#define CYREG_B1_P5_U0_CFG27 0x40011a5b\r
+#define CYREG_B1_P5_U0_CFG28 0x40011a5c\r
+#define CYREG_B1_P5_U0_CFG29 0x40011a5d\r
+#define CYREG_B1_P5_U0_CFG30 0x40011a5e\r
+#define CYREG_B1_P5_U0_CFG31 0x40011a5f\r
+#define CYREG_B1_P5_U0_DCFG0 0x40011a60\r
+#define CYREG_B1_P5_U0_DCFG1 0x40011a62\r
+#define CYREG_B1_P5_U0_DCFG2 0x40011a64\r
+#define CYREG_B1_P5_U0_DCFG3 0x40011a66\r
+#define CYREG_B1_P5_U0_DCFG4 0x40011a68\r
+#define CYREG_B1_P5_U0_DCFG5 0x40011a6a\r
+#define CYREG_B1_P5_U0_DCFG6 0x40011a6c\r
+#define CYREG_B1_P5_U0_DCFG7 0x40011a6e\r
+#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80\r
+#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070\r
+#define CYREG_B1_P5_U1_PLD_IT0 0x40011a80\r
+#define CYREG_B1_P5_U1_PLD_IT1 0x40011a84\r
+#define CYREG_B1_P5_U1_PLD_IT2 0x40011a88\r
+#define CYREG_B1_P5_U1_PLD_IT3 0x40011a8c\r
+#define CYREG_B1_P5_U1_PLD_IT4 0x40011a90\r
+#define CYREG_B1_P5_U1_PLD_IT5 0x40011a94\r
+#define CYREG_B1_P5_U1_PLD_IT6 0x40011a98\r
+#define CYREG_B1_P5_U1_PLD_IT7 0x40011a9c\r
+#define CYREG_B1_P5_U1_PLD_IT8 0x40011aa0\r
+#define CYREG_B1_P5_U1_PLD_IT9 0x40011aa4\r
+#define CYREG_B1_P5_U1_PLD_IT10 0x40011aa8\r
+#define CYREG_B1_P5_U1_PLD_IT11 0x40011aac\r
+#define CYREG_B1_P5_U1_PLD_ORT0 0x40011ab0\r
+#define CYREG_B1_P5_U1_PLD_ORT1 0x40011ab2\r
+#define CYREG_B1_P5_U1_PLD_ORT2 0x40011ab4\r
+#define CYREG_B1_P5_U1_PLD_ORT3 0x40011ab6\r
+#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8\r
+#define CYREG_B1_P5_U1_MC_CFG_XORFB 0x40011aba\r
+#define CYREG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abc\r
+#define CYREG_B1_P5_U1_MC_CFG_BYPASS 0x40011abe\r
+#define CYREG_B1_P5_U1_CFG0 0x40011ac0\r
+#define CYREG_B1_P5_U1_CFG1 0x40011ac1\r
+#define CYREG_B1_P5_U1_CFG2 0x40011ac2\r
+#define CYREG_B1_P5_U1_CFG3 0x40011ac3\r
+#define CYREG_B1_P5_U1_CFG4 0x40011ac4\r
+#define CYREG_B1_P5_U1_CFG5 0x40011ac5\r
+#define CYREG_B1_P5_U1_CFG6 0x40011ac6\r
+#define CYREG_B1_P5_U1_CFG7 0x40011ac7\r
+#define CYREG_B1_P5_U1_CFG8 0x40011ac8\r
+#define CYREG_B1_P5_U1_CFG9 0x40011ac9\r
+#define CYREG_B1_P5_U1_CFG10 0x40011aca\r
+#define CYREG_B1_P5_U1_CFG11 0x40011acb\r
+#define CYREG_B1_P5_U1_CFG12 0x40011acc\r
+#define CYREG_B1_P5_U1_CFG13 0x40011acd\r
+#define CYREG_B1_P5_U1_CFG14 0x40011ace\r
+#define CYREG_B1_P5_U1_CFG15 0x40011acf\r
+#define CYREG_B1_P5_U1_CFG16 0x40011ad0\r
+#define CYREG_B1_P5_U1_CFG17 0x40011ad1\r
+#define CYREG_B1_P5_U1_CFG18 0x40011ad2\r
+#define CYREG_B1_P5_U1_CFG19 0x40011ad3\r
+#define CYREG_B1_P5_U1_CFG20 0x40011ad4\r
+#define CYREG_B1_P5_U1_CFG21 0x40011ad5\r
+#define CYREG_B1_P5_U1_CFG22 0x40011ad6\r
+#define CYREG_B1_P5_U1_CFG23 0x40011ad7\r
+#define CYREG_B1_P5_U1_CFG24 0x40011ad8\r
+#define CYREG_B1_P5_U1_CFG25 0x40011ad9\r
+#define CYREG_B1_P5_U1_CFG26 0x40011ada\r
+#define CYREG_B1_P5_U1_CFG27 0x40011adb\r
+#define CYREG_B1_P5_U1_CFG28 0x40011adc\r
+#define CYREG_B1_P5_U1_CFG29 0x40011add\r
+#define CYREG_B1_P5_U1_CFG30 0x40011ade\r
+#define CYREG_B1_P5_U1_CFG31 0x40011adf\r
+#define CYREG_B1_P5_U1_DCFG0 0x40011ae0\r
+#define CYREG_B1_P5_U1_DCFG1 0x40011ae2\r
+#define CYREG_B1_P5_U1_DCFG2 0x40011ae4\r
+#define CYREG_B1_P5_U1_DCFG3 0x40011ae6\r
+#define CYREG_B1_P5_U1_DCFG4 0x40011ae8\r
+#define CYREG_B1_P5_U1_DCFG5 0x40011aea\r
+#define CYREG_B1_P5_U1_DCFG6 0x40011aec\r
+#define CYREG_B1_P5_U1_DCFG7 0x40011aee\r
+#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00\r
+#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI0_BASE 0x40014000\r
+#define CYDEV_UCFG_DSI0_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI1_BASE 0x40014100\r
+#define CYDEV_UCFG_DSI1_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI2_BASE 0x40014200\r
+#define CYDEV_UCFG_DSI2_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI3_BASE 0x40014300\r
+#define CYDEV_UCFG_DSI3_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI4_BASE 0x40014400\r
+#define CYDEV_UCFG_DSI4_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI5_BASE 0x40014500\r
+#define CYDEV_UCFG_DSI5_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI6_BASE 0x40014600\r
+#define CYDEV_UCFG_DSI6_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI7_BASE 0x40014700\r
+#define CYDEV_UCFG_DSI7_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI8_BASE 0x40014800\r
+#define CYDEV_UCFG_DSI8_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI9_BASE 0x40014900\r
+#define CYDEV_UCFG_DSI9_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI12_BASE 0x40014c00\r
+#define CYDEV_UCFG_DSI12_SIZE 0x000000ef\r
+#define CYDEV_UCFG_DSI13_BASE 0x40014d00\r
+#define CYDEV_UCFG_DSI13_SIZE 0x000000ef\r
+#define CYDEV_UCFG_BCTL0_BASE 0x40015000\r
+#define CYDEV_UCFG_BCTL0_SIZE 0x00000010\r
+#define CYREG_BCTL0_MDCLK_EN 0x40015000\r
+#define CYREG_BCTL0_MBCLK_EN 0x40015001\r
+#define CYREG_BCTL0_WAIT_CFG 0x40015002\r
+#define CYREG_BCTL0_BANK_CTL 0x40015003\r
+#define CYREG_BCTL0_UDB_TEST_3 0x40015007\r
+#define CYREG_BCTL0_DCLK_EN0 0x40015008\r
+#define CYREG_BCTL0_BCLK_EN0 0x40015009\r
+#define CYREG_BCTL0_DCLK_EN1 0x4001500a\r
+#define CYREG_BCTL0_BCLK_EN1 0x4001500b\r
+#define CYREG_BCTL0_DCLK_EN2 0x4001500c\r
+#define CYREG_BCTL0_BCLK_EN2 0x4001500d\r
+#define CYREG_BCTL0_DCLK_EN3 0x4001500e\r
+#define CYREG_BCTL0_BCLK_EN3 0x4001500f\r
+#define CYDEV_UCFG_BCTL1_BASE 0x40015010\r
+#define CYDEV_UCFG_BCTL1_SIZE 0x00000010\r
+#define CYREG_BCTL1_MDCLK_EN 0x40015010\r
+#define CYREG_BCTL1_MBCLK_EN 0x40015011\r
+#define CYREG_BCTL1_WAIT_CFG 0x40015012\r
+#define CYREG_BCTL1_BANK_CTL 0x40015013\r
+#define CYREG_BCTL1_UDB_TEST_3 0x40015017\r
+#define CYREG_BCTL1_DCLK_EN0 0x40015018\r
+#define CYREG_BCTL1_BCLK_EN0 0x40015019\r
+#define CYREG_BCTL1_DCLK_EN1 0x4001501a\r
+#define CYREG_BCTL1_BCLK_EN1 0x4001501b\r
+#define CYREG_BCTL1_DCLK_EN2 0x4001501c\r
+#define CYREG_BCTL1_BCLK_EN2 0x4001501d\r
+#define CYREG_BCTL1_DCLK_EN3 0x4001501e\r
+#define CYREG_BCTL1_BCLK_EN3 0x4001501f\r
+#define CYDEV_IDMUX_BASE 0x40015100\r
+#define CYDEV_IDMUX_SIZE 0x00000016\r
+#define CYREG_IDMUX_IRQ_CTL0 0x40015100\r
+#define CYREG_IDMUX_IRQ_CTL1 0x40015101\r
+#define CYREG_IDMUX_IRQ_CTL2 0x40015102\r
+#define CYREG_IDMUX_IRQ_CTL3 0x40015103\r
+#define CYREG_IDMUX_IRQ_CTL4 0x40015104\r
+#define CYREG_IDMUX_IRQ_CTL5 0x40015105\r
+#define CYREG_IDMUX_IRQ_CTL6 0x40015106\r
+#define CYREG_IDMUX_IRQ_CTL7 0x40015107\r
+#define CYREG_IDMUX_DRQ_CTL0 0x40015110\r
+#define CYREG_IDMUX_DRQ_CTL1 0x40015111\r
+#define CYREG_IDMUX_DRQ_CTL2 0x40015112\r
+#define CYREG_IDMUX_DRQ_CTL3 0x40015113\r
+#define CYREG_IDMUX_DRQ_CTL4 0x40015114\r
+#define CYREG_IDMUX_DRQ_CTL5 0x40015115\r
+#define CYDEV_CACHERAM_BASE 0x40030000\r
+#define CYDEV_CACHERAM_SIZE 0x00000400\r
+#define CYREG_CACHERAM_DATA_MBASE 0x40030000\r
+#define CYREG_CACHERAM_DATA_MSIZE 0x00000400\r
+#define CYDEV_SFR_BASE 0x40050100\r
+#define CYDEV_SFR_SIZE 0x000000fb\r
+#define CYREG_SFR_GPIO0 0x40050180\r
+#define CYREG_SFR_GPIRD0 0x40050189\r
+#define CYREG_SFR_GPIO0_SEL 0x4005018a\r
+#define CYREG_SFR_GPIO1 0x40050190\r
+#define CYREG_SFR_GPIRD1 0x40050191\r
+#define CYREG_SFR_GPIO2 0x40050198\r
+#define CYREG_SFR_GPIRD2 0x40050199\r
+#define CYREG_SFR_GPIO2_SEL 0x4005019a\r
+#define CYREG_SFR_GPIO1_SEL 0x400501a2\r
+#define CYREG_SFR_GPIO3 0x400501b0\r
+#define CYREG_SFR_GPIRD3 0x400501b1\r
+#define CYREG_SFR_GPIO3_SEL 0x400501b2\r
+#define CYREG_SFR_GPIO4 0x400501c0\r
+#define CYREG_SFR_GPIRD4 0x400501c1\r
+#define CYREG_SFR_GPIO4_SEL 0x400501c2\r
+#define CYREG_SFR_GPIO5 0x400501c8\r
+#define CYREG_SFR_GPIRD5 0x400501c9\r
+#define CYREG_SFR_GPIO5_SEL 0x400501ca\r
+#define CYREG_SFR_GPIO6 0x400501d8\r
+#define CYREG_SFR_GPIRD6 0x400501d9\r
+#define CYREG_SFR_GPIO6_SEL 0x400501da\r
+#define CYREG_SFR_GPIO12 0x400501e8\r
+#define CYREG_SFR_GPIRD12 0x400501e9\r
+#define CYREG_SFR_GPIO12_SEL 0x400501f2\r
+#define CYREG_SFR_GPIO15 0x400501f8\r
+#define CYREG_SFR_GPIRD15 0x400501f9\r
+#define CYREG_SFR_GPIO15_SEL 0x400501fa\r
+#define CYDEV_P3BA_BASE 0x40050300\r
+#define CYDEV_P3BA_SIZE 0x0000002b\r
+#define CYREG_P3BA_Y_START 0x40050300\r
+#define CYREG_P3BA_YROLL 0x40050301\r
+#define CYREG_P3BA_YCFG 0x40050302\r
+#define CYREG_P3BA_X_START1 0x40050303\r
+#define CYREG_P3BA_X_START2 0x40050304\r
+#define CYREG_P3BA_XROLL1 0x40050305\r
+#define CYREG_P3BA_XROLL2 0x40050306\r
+#define CYREG_P3BA_XINC 0x40050307\r
+#define CYREG_P3BA_XCFG 0x40050308\r
+#define CYREG_P3BA_OFFSETADDR1 0x40050309\r
+#define CYREG_P3BA_OFFSETADDR2 0x4005030a\r
+#define CYREG_P3BA_OFFSETADDR3 0x4005030b\r
+#define CYREG_P3BA_ABSADDR1 0x4005030c\r
+#define CYREG_P3BA_ABSADDR2 0x4005030d\r
+#define CYREG_P3BA_ABSADDR3 0x4005030e\r
+#define CYREG_P3BA_ABSADDR4 0x4005030f\r
+#define CYREG_P3BA_DATCFG1 0x40050310\r
+#define CYREG_P3BA_DATCFG2 0x40050311\r
+#define CYREG_P3BA_CMP_RSLT1 0x40050314\r
+#define CYREG_P3BA_CMP_RSLT2 0x40050315\r
+#define CYREG_P3BA_CMP_RSLT3 0x40050316\r
+#define CYREG_P3BA_CMP_RSLT4 0x40050317\r
+#define CYREG_P3BA_DATA_REG1 0x40050318\r
+#define CYREG_P3BA_DATA_REG2 0x40050319\r
+#define CYREG_P3BA_DATA_REG3 0x4005031a\r
+#define CYREG_P3BA_DATA_REG4 0x4005031b\r
+#define CYREG_P3BA_EXP_DATA1 0x4005031c\r
+#define CYREG_P3BA_EXP_DATA2 0x4005031d\r
+#define CYREG_P3BA_EXP_DATA3 0x4005031e\r
+#define CYREG_P3BA_EXP_DATA4 0x4005031f\r
+#define CYREG_P3BA_MSTR_HRDATA1 0x40050320\r
+#define CYREG_P3BA_MSTR_HRDATA2 0x40050321\r
+#define CYREG_P3BA_MSTR_HRDATA3 0x40050322\r
+#define CYREG_P3BA_MSTR_HRDATA4 0x40050323\r
+#define CYREG_P3BA_BIST_EN 0x40050324\r
+#define CYREG_P3BA_PHUB_MASTER_SSR 0x40050325\r
+#define CYREG_P3BA_SEQCFG1 0x40050326\r
+#define CYREG_P3BA_SEQCFG2 0x40050327\r
+#define CYREG_P3BA_Y_CURR 0x40050328\r
+#define CYREG_P3BA_X_CURR1 0x40050329\r
+#define CYREG_P3BA_X_CURR2 0x4005032a\r
+#define CYDEV_PANTHER_BASE 0x40080000\r
+#define CYDEV_PANTHER_SIZE 0x00000020\r
+#define CYREG_PANTHER_STCALIB_CFG 0x40080000\r
+#define CYREG_PANTHER_WAITPIPE 0x40080004\r
+#define CYREG_PANTHER_TRACE_CFG 0x40080008\r
+#define CYREG_PANTHER_DBG_CFG 0x4008000c\r
+#define CYREG_PANTHER_CM3_LCKRST_STAT 0x40080018\r
+#define CYREG_PANTHER_DEVICE_ID 0x4008001c\r
+#define CYDEV_FLSECC_BASE 0x48000000\r
+#define CYDEV_FLSECC_SIZE 0x00008000\r
+#define CYREG_FLSECC_DATA_MBASE 0x48000000\r
+#define CYREG_FLSECC_DATA_MSIZE 0x00008000\r
+#define CYDEV_FLSHID_BASE 0x49000000\r
+#define CYDEV_FLSHID_SIZE 0x00000200\r
+#define CYREG_FLSHID_RSVD_MBASE 0x49000000\r
+#define CYREG_FLSHID_RSVD_MSIZE 0x00000080\r
+#define CYREG_FLSHID_CUST_MDATA_MBASE 0x49000080\r
+#define CYREG_FLSHID_CUST_MDATA_MSIZE 0x00000080\r
+#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100\r
+#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040\r
+#define CYREG_FLSHID_CUST_TABLES_Y_LOC 0x49000100\r
+#define CYREG_FLSHID_CUST_TABLES_X_LOC 0x49000101\r
+#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102\r
+#define CYREG_FLSHID_CUST_TABLES_LOT_LSB 0x49000103\r
+#define CYREG_FLSHID_CUST_TABLES_LOT_MSB 0x49000104\r
+#define CYREG_FLSHID_CUST_TABLES_WRK_WK 0x49000105\r
+#define CYREG_FLSHID_CUST_TABLES_FAB_YR 0x49000106\r
+#define CYREG_FLSHID_CUST_TABLES_MINOR 0x49000107\r
+#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108\r
+#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109\r
+#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010a\r
+#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010b\r
+#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010c\r
+#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010d\r
+#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010e\r
+#define CYREG_FLSHID_CUST_TABLES_IMO_USB 0x4900010f\r
+#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110\r
+#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111\r
+#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112\r
+#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113\r
+#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114\r
+#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115\r
+#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116\r
+#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117\r
+#define CYREG_FLSHID_CUST_TABLES_DEC_M1 0x49000118\r
+#define CYREG_FLSHID_CUST_TABLES_DEC_M2 0x49000119\r
+#define CYREG_FLSHID_CUST_TABLES_DEC_M3 0x4900011a\r
+#define CYREG_FLSHID_CUST_TABLES_DEC_M4 0x4900011b\r
+#define CYREG_FLSHID_CUST_TABLES_DEC_M5 0x4900011c\r
+#define CYREG_FLSHID_CUST_TABLES_DEC_M6 0x4900011d\r
+#define CYREG_FLSHID_CUST_TABLES_DEC_M7 0x4900011e\r
+#define CYREG_FLSHID_CUST_TABLES_DEC_M8 0x4900011f\r
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M1 0x49000120\r
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M2 0x49000121\r
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M3 0x49000122\r
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M4 0x49000123\r
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M5 0x49000124\r
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M6 0x49000125\r
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M7 0x49000126\r
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M8 0x49000127\r
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M1 0x49000128\r
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M2 0x49000129\r
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M3 0x4900012a\r
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M4 0x4900012b\r
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M5 0x4900012c\r
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M6 0x4900012d\r
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M7 0x4900012e\r
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M8 0x4900012f\r
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M1 0x49000130\r
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M2 0x49000131\r
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M3 0x49000132\r
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M4 0x49000133\r
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M5 0x49000134\r
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M6 0x49000135\r
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M7 0x49000136\r
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M8 0x49000137\r
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M1 0x49000138\r
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M2 0x49000139\r
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M3 0x4900013a\r
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M4 0x4900013b\r
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M5 0x4900013c\r
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M6 0x4900013d\r
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M7 0x4900013e\r
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M8 0x4900013f\r
+#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180\r
+#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080\r
+#define CYREG_FLSHID_MFG_CFG_IMO_TR1 0x49000188\r
+#define CYREG_FLSHID_MFG_CFG_CMP0_TR0 0x490001ac\r
+#define CYREG_FLSHID_MFG_CFG_CMP1_TR0 0x490001ae\r
+#define CYREG_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0\r
+#define CYREG_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2\r
+#define CYREG_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4\r
+#define CYREG_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6\r
+#define CYREG_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8\r
+#define CYREG_FLSHID_MFG_CFG_CMP3_TR1 0x490001ba\r
+#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ce\r
+#define CYDEV_EXTMEM_BASE 0x60000000\r
+#define CYDEV_EXTMEM_SIZE 0x00800000\r
+#define CYREG_EXTMEM_DATA_MBASE 0x60000000\r
+#define CYREG_EXTMEM_DATA_MSIZE 0x00800000\r
+#define CYDEV_ITM_BASE 0xe0000000\r
+#define CYDEV_ITM_SIZE 0x00001000\r
+#define CYREG_ITM_TRACE_EN 0xe0000e00\r
+#define CYREG_ITM_TRACE_PRIVILEGE 0xe0000e40\r
+#define CYREG_ITM_TRACE_CTRL 0xe0000e80\r
+#define CYREG_ITM_LOCK_ACCESS 0xe0000fb0\r
+#define CYREG_ITM_LOCK_STATUS 0xe0000fb4\r
+#define CYREG_ITM_PID4 0xe0000fd0\r
+#define CYREG_ITM_PID5 0xe0000fd4\r
+#define CYREG_ITM_PID6 0xe0000fd8\r
+#define CYREG_ITM_PID7 0xe0000fdc\r
+#define CYREG_ITM_PID0 0xe0000fe0\r
+#define CYREG_ITM_PID1 0xe0000fe4\r
+#define CYREG_ITM_PID2 0xe0000fe8\r
+#define CYREG_ITM_PID3 0xe0000fec\r
+#define CYREG_ITM_CID0 0xe0000ff0\r
+#define CYREG_ITM_CID1 0xe0000ff4\r
+#define CYREG_ITM_CID2 0xe0000ff8\r
+#define CYREG_ITM_CID3 0xe0000ffc\r
+#define CYDEV_DWT_BASE 0xe0001000\r
+#define CYDEV_DWT_SIZE 0x0000005c\r
+#define CYREG_DWT_CTRL 0xe0001000\r
+#define CYREG_DWT_CYCLE_COUNT 0xe0001004\r
+#define CYREG_DWT_CPI_COUNT 0xe0001008\r
+#define CYREG_DWT_EXC_OVHD_COUNT 0xe000100c\r
+#define CYREG_DWT_SLEEP_COUNT 0xe0001010\r
+#define CYREG_DWT_LSU_COUNT 0xe0001014\r
+#define CYREG_DWT_FOLD_COUNT 0xe0001018\r
+#define CYREG_DWT_PC_SAMPLE 0xe000101c\r
+#define CYREG_DWT_COMP_0 0xe0001020\r
+#define CYREG_DWT_MASK_0 0xe0001024\r
+#define CYREG_DWT_FUNCTION_0 0xe0001028\r
+#define CYREG_DWT_COMP_1 0xe0001030\r
+#define CYREG_DWT_MASK_1 0xe0001034\r
+#define CYREG_DWT_FUNCTION_1 0xe0001038\r
+#define CYREG_DWT_COMP_2 0xe0001040\r
+#define CYREG_DWT_MASK_2 0xe0001044\r
+#define CYREG_DWT_FUNCTION_2 0xe0001048\r
+#define CYREG_DWT_COMP_3 0xe0001050\r
+#define CYREG_DWT_MASK_3 0xe0001054\r
+#define CYREG_DWT_FUNCTION_3 0xe0001058\r
+#define CYDEV_FPB_BASE 0xe0002000\r
+#define CYDEV_FPB_SIZE 0x00001000\r
+#define CYREG_FPB_CTRL 0xe0002000\r
+#define CYREG_FPB_REMAP 0xe0002004\r
+#define CYREG_FPB_FP_COMP_0 0xe0002008\r
+#define CYREG_FPB_FP_COMP_1 0xe000200c\r
+#define CYREG_FPB_FP_COMP_2 0xe0002010\r
+#define CYREG_FPB_FP_COMP_3 0xe0002014\r
+#define CYREG_FPB_FP_COMP_4 0xe0002018\r
+#define CYREG_FPB_FP_COMP_5 0xe000201c\r
+#define CYREG_FPB_FP_COMP_6 0xe0002020\r
+#define CYREG_FPB_FP_COMP_7 0xe0002024\r
+#define CYREG_FPB_PID4 0xe0002fd0\r
+#define CYREG_FPB_PID5 0xe0002fd4\r
+#define CYREG_FPB_PID6 0xe0002fd8\r
+#define CYREG_FPB_PID7 0xe0002fdc\r
+#define CYREG_FPB_PID0 0xe0002fe0\r
+#define CYREG_FPB_PID1 0xe0002fe4\r
+#define CYREG_FPB_PID2 0xe0002fe8\r
+#define CYREG_FPB_PID3 0xe0002fec\r
+#define CYREG_FPB_CID0 0xe0002ff0\r
+#define CYREG_FPB_CID1 0xe0002ff4\r
+#define CYREG_FPB_CID2 0xe0002ff8\r
+#define CYREG_FPB_CID3 0xe0002ffc\r
+#define CYDEV_NVIC_BASE 0xe000e000\r
+#define CYDEV_NVIC_SIZE 0x00000d3c\r
+#define CYREG_NVIC_INT_CTL_TYPE 0xe000e004\r
+#define CYREG_NVIC_SYSTICK_CTL 0xe000e010\r
+#define CYREG_NVIC_SYSTICK_RELOAD 0xe000e014\r
+#define CYREG_NVIC_SYSTICK_CURRENT 0xe000e018\r
+#define CYREG_NVIC_SYSTICK_CAL 0xe000e01c\r
+#define CYREG_NVIC_SETENA0 0xe000e100\r
+#define CYREG_NVIC_CLRENA0 0xe000e180\r
+#define CYREG_NVIC_SETPEND0 0xe000e200\r
+#define CYREG_NVIC_CLRPEND0 0xe000e280\r
+#define CYREG_NVIC_ACTIVE0 0xe000e300\r
+#define CYREG_NVIC_PRI_0 0xe000e400\r
+#define CYREG_NVIC_PRI_1 0xe000e401\r
+#define CYREG_NVIC_PRI_2 0xe000e402\r
+#define CYREG_NVIC_PRI_3 0xe000e403\r
+#define CYREG_NVIC_PRI_4 0xe000e404\r
+#define CYREG_NVIC_PRI_5 0xe000e405\r
+#define CYREG_NVIC_PRI_6 0xe000e406\r
+#define CYREG_NVIC_PRI_7 0xe000e407\r
+#define CYREG_NVIC_PRI_8 0xe000e408\r
+#define CYREG_NVIC_PRI_9 0xe000e409\r
+#define CYREG_NVIC_PRI_10 0xe000e40a\r
+#define CYREG_NVIC_PRI_11 0xe000e40b\r
+#define CYREG_NVIC_PRI_12 0xe000e40c\r
+#define CYREG_NVIC_PRI_13 0xe000e40d\r
+#define CYREG_NVIC_PRI_14 0xe000e40e\r
+#define CYREG_NVIC_PRI_15 0xe000e40f\r
+#define CYREG_NVIC_PRI_16 0xe000e410\r
+#define CYREG_NVIC_PRI_17 0xe000e411\r
+#define CYREG_NVIC_PRI_18 0xe000e412\r
+#define CYREG_NVIC_PRI_19 0xe000e413\r
+#define CYREG_NVIC_PRI_20 0xe000e414\r
+#define CYREG_NVIC_PRI_21 0xe000e415\r
+#define CYREG_NVIC_PRI_22 0xe000e416\r
+#define CYREG_NVIC_PRI_23 0xe000e417\r
+#define CYREG_NVIC_PRI_24 0xe000e418\r
+#define CYREG_NVIC_PRI_25 0xe000e419\r
+#define CYREG_NVIC_PRI_26 0xe000e41a\r
+#define CYREG_NVIC_PRI_27 0xe000e41b\r
+#define CYREG_NVIC_PRI_28 0xe000e41c\r
+#define CYREG_NVIC_PRI_29 0xe000e41d\r
+#define CYREG_NVIC_PRI_30 0xe000e41e\r
+#define CYREG_NVIC_PRI_31 0xe000e41f\r
+#define CYREG_NVIC_CPUID_BASE 0xe000ed00\r
+#define CYREG_NVIC_INTR_CTRL_STATE 0xe000ed04\r
+#define CYREG_NVIC_VECT_OFFSET 0xe000ed08\r
+#define CYREG_NVIC_APPLN_INTR 0xe000ed0c\r
+#define CYREG_NVIC_SYSTEM_CONTROL 0xe000ed10\r
+#define CYREG_NVIC_CFG_CONTROL 0xe000ed14\r
+#define CYREG_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18\r
+#define CYREG_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1c\r
+#define CYREG_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20\r
+#define CYREG_NVIC_SYS_HANDLER_CSR 0xe000ed24\r
+#define CYREG_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28\r
+#define CYREG_NVIC_BUS_FAULT_STATUS 0xe000ed29\r
+#define CYREG_NVIC_USAGE_FAULT_STATUS 0xe000ed2a\r
+#define CYREG_NVIC_HARD_FAULT_STATUS 0xe000ed2c\r
+#define CYREG_NVIC_DEBUG_FAULT_STATUS 0xe000ed30\r
+#define CYREG_NVIC_MEMMAN_FAULT_ADD 0xe000ed34\r
+#define CYREG_NVIC_BUS_FAULT_ADD 0xe000ed38\r
+#define CYDEV_CORE_DBG_BASE 0xe000edf0\r
+#define CYDEV_CORE_DBG_SIZE 0x00000010\r
+#define CYREG_CORE_DBG_DBG_HLT_CS 0xe000edf0\r
+#define CYREG_CORE_DBG_DBG_REG_SEL 0xe000edf4\r
+#define CYREG_CORE_DBG_DBG_REG_DATA 0xe000edf8\r
+#define CYREG_CORE_DBG_EXC_MON_CTL 0xe000edfc\r
+#define CYDEV_TPIU_BASE 0xe0040000\r
+#define CYDEV_TPIU_SIZE 0x00001000\r
+#define CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000\r
+#define CYREG_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004\r
+#define CYREG_TPIU_ASYNC_CLK_PRESCALER 0xe0040010\r
+#define CYREG_TPIU_PROTOCOL 0xe00400f0\r
+#define CYREG_TPIU_FORM_FLUSH_STAT 0xe0040300\r
+#define CYREG_TPIU_FORM_FLUSH_CTRL 0xe0040304\r
+#define CYREG_TPIU_TRIGGER 0xe0040ee8\r
+#define CYREG_TPIU_ITETMDATA 0xe0040eec\r
+#define CYREG_TPIU_ITATBCTR2 0xe0040ef0\r
+#define CYREG_TPIU_ITATBCTR0 0xe0040ef8\r
+#define CYREG_TPIU_ITITMDATA 0xe0040efc\r
+#define CYREG_TPIU_ITCTRL 0xe0040f00\r
+#define CYREG_TPIU_DEVID 0xe0040fc8\r
+#define CYREG_TPIU_DEVTYPE 0xe0040fcc\r
+#define CYREG_TPIU_PID4 0xe0040fd0\r
+#define CYREG_TPIU_PID5 0xe0040fd4\r
+#define CYREG_TPIU_PID6 0xe0040fd8\r
+#define CYREG_TPIU_PID7 0xe0040fdc\r
+#define CYREG_TPIU_PID0 0xe0040fe0\r
+#define CYREG_TPIU_PID1 0xe0040fe4\r
+#define CYREG_TPIU_PID2 0xe0040fe8\r
+#define CYREG_TPIU_PID3 0xe0040fec\r
+#define CYREG_TPIU_CID0 0xe0040ff0\r
+#define CYREG_TPIU_CID1 0xe0040ff4\r
+#define CYREG_TPIU_CID2 0xe0040ff8\r
+#define CYREG_TPIU_CID3 0xe0040ffc\r
+#define CYDEV_ETM_BASE 0xe0041000\r
+#define CYDEV_ETM_SIZE 0x00001000\r
+#define CYREG_ETM_CTL 0xe0041000\r
+#define CYREG_ETM_CFG_CODE 0xe0041004\r
+#define CYREG_ETM_TRIG_EVENT 0xe0041008\r
+#define CYREG_ETM_STATUS 0xe0041010\r
+#define CYREG_ETM_SYS_CFG 0xe0041014\r
+#define CYREG_ETM_TRACE_ENB_EVENT 0xe0041020\r
+#define CYREG_ETM_TRACE_EN_CTRL1 0xe0041024\r
+#define CYREG_ETM_FIFOFULL_LEVEL 0xe004102c\r
+#define CYREG_ETM_SYNC_FREQ 0xe00411e0\r
+#define CYREG_ETM_ETM_ID 0xe00411e4\r
+#define CYREG_ETM_CFG_CODE_EXT 0xe00411e8\r
+#define CYREG_ETM_TR_SS_EMBICE_CTRL 0xe00411f0\r
+#define CYREG_ETM_CS_TRACE_ID 0xe0041200\r
+#define CYREG_ETM_OS_LOCK_ACCESS 0xe0041300\r
+#define CYREG_ETM_OS_LOCK_STATUS 0xe0041304\r
+#define CYREG_ETM_PDSR 0xe0041314\r
+#define CYREG_ETM_ITMISCIN 0xe0041ee0\r
+#define CYREG_ETM_ITTRIGOUT 0xe0041ee8\r
+#define CYREG_ETM_ITATBCTR2 0xe0041ef0\r
+#define CYREG_ETM_ITATBCTR0 0xe0041ef8\r
+#define CYREG_ETM_INT_MODE_CTRL 0xe0041f00\r
+#define CYREG_ETM_CLM_TAG_SET 0xe0041fa0\r
+#define CYREG_ETM_CLM_TAG_CLR 0xe0041fa4\r
+#define CYREG_ETM_LOCK_ACCESS 0xe0041fb0\r
+#define CYREG_ETM_LOCK_STATUS 0xe0041fb4\r
+#define CYREG_ETM_AUTH_STATUS 0xe0041fb8\r
+#define CYREG_ETM_DEV_TYPE 0xe0041fcc\r
+#define CYREG_ETM_PID4 0xe0041fd0\r
+#define CYREG_ETM_PID5 0xe0041fd4\r
+#define CYREG_ETM_PID6 0xe0041fd8\r
+#define CYREG_ETM_PID7 0xe0041fdc\r
+#define CYREG_ETM_PID0 0xe0041fe0\r
+#define CYREG_ETM_PID1 0xe0041fe4\r
+#define CYREG_ETM_PID2 0xe0041fe8\r
+#define CYREG_ETM_PID3 0xe0041fec\r
+#define CYREG_ETM_CID0 0xe0041ff0\r
+#define CYREG_ETM_CID1 0xe0041ff4\r
+#define CYREG_ETM_CID2 0xe0041ff8\r
+#define CYREG_ETM_CID3 0xe0041ffc\r
+#define CYDEV_ROM_TABLE_BASE 0xe00ff000\r
+#define CYDEV_ROM_TABLE_SIZE 0x00001000\r
+#define CYREG_ROM_TABLE_NVIC 0xe00ff000\r
+#define CYREG_ROM_TABLE_DWT 0xe00ff004\r
+#define CYREG_ROM_TABLE_FPB 0xe00ff008\r
+#define CYREG_ROM_TABLE_ITM 0xe00ff00c\r
+#define CYREG_ROM_TABLE_TPIU 0xe00ff010\r
+#define CYREG_ROM_TABLE_ETM 0xe00ff014\r
+#define CYREG_ROM_TABLE_END 0xe00ff018\r
+#define CYREG_ROM_TABLE_MEMTYPE 0xe00fffcc\r
+#define CYREG_ROM_TABLE_PID4 0xe00fffd0\r
+#define CYREG_ROM_TABLE_PID5 0xe00fffd4\r
+#define CYREG_ROM_TABLE_PID6 0xe00fffd8\r
+#define CYREG_ROM_TABLE_PID7 0xe00fffdc\r
+#define CYREG_ROM_TABLE_PID0 0xe00fffe0\r
+#define CYREG_ROM_TABLE_PID1 0xe00fffe4\r
+#define CYREG_ROM_TABLE_PID2 0xe00fffe8\r
+#define CYREG_ROM_TABLE_PID3 0xe00fffec\r
+#define CYREG_ROM_TABLE_CID0 0xe00ffff0\r
+#define CYREG_ROM_TABLE_CID1 0xe00ffff4\r
+#define CYREG_ROM_TABLE_CID2 0xe00ffff8\r
+#define CYREG_ROM_TABLE_CID3 0xe00ffffc\r
+#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE\r
+#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE\r
+#define CYDEV_FLS_SECTOR_SIZE 0x00010000\r
+#define CYDEV_FLS_ROW_SIZE 0x00000100\r
+#define CYDEV_ECC_SECTOR_SIZE 0x00002000\r
+#define CYDEV_ECC_ROW_SIZE 0x00000020\r
+#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400\r
+#define CYDEV_EEPROM_ROW_SIZE 0x00000010\r
+#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE\r
+#define CYCLK_LD_DISABLE 0x00000004\r
+#define CYCLK_LD_SYNC_EN 0x00000002\r
+#define CYCLK_LD_LOAD 0x00000001\r
+#define CYCLK_PIPE 0x00000080\r
+#define CYCLK_SSS 0x00000040\r
+#define CYCLK_EARLY 0x00000020\r
+#define CYCLK_DUTY 0x00000010\r
+#define CYCLK_SYNC 0x00000008\r
+#define CYCLK_SRC_SEL_CLK_SYNC_D 0\r
+#define CYCLK_SRC_SEL_SYNC_DIG 0\r
+#define CYCLK_SRC_SEL_IMO 1\r
+#define CYCLK_SRC_SEL_XTAL_MHZ 2\r
+#define CYCLK_SRC_SEL_XTALM 2\r
+#define CYCLK_SRC_SEL_ILO 3\r
+#define CYCLK_SRC_SEL_PLL 4\r
+#define CYCLK_SRC_SEL_XTAL_KHZ 5\r
+#define CYCLK_SRC_SEL_XTALK 5\r
+#define CYCLK_SRC_SEL_DSI_G 6\r
+#define CYCLK_SRC_SEL_DSI_D 7\r
+#define CYCLK_SRC_SEL_CLK_SYNC_A 0\r
+#define CYCLK_SRC_SEL_DSI_A 7\r
;\r
; FILENAME: cydevicerv.inc\r
; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator 2.2 Component Pack 6\r
+; PSoC Creator 3.0\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
; FILENAME: cydevicerv_trm.inc\r
; \r
-; PSoC Creator 2.2 Component Pack 6\r
+; PSoC Creator 3.0\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
--- /dev/null
+#ifndef INCLUDED_CYDISABLEDSHEETS_H\r
+#define INCLUDED_CYDISABLEDSHEETS_H\r
+\r
+\r
+#endif /* INCLUDED_CYDISABLEDSHEETS_H */\r
#include <cydevice.h>\r
#include <cydevice_trm.h>\r
\r
-/* SDCard_RxInternalInterrupt */\r
-#define SDCard_RxInternalInterrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SDCard_RxInternalInterrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SDCard_RxInternalInterrupt__INTC_MASK 0x01u\r
-#define SDCard_RxInternalInterrupt__INTC_NUMBER 0u\r
-#define SDCard_RxInternalInterrupt__INTC_PRIOR_NUM 7u\r
-#define SDCard_RxInternalInterrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
-#define SDCard_RxInternalInterrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SDCard_RxInternalInterrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SDCard_TxInternalInterrupt */\r
-#define SDCard_TxInternalInterrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SDCard_TxInternalInterrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SDCard_TxInternalInterrupt__INTC_MASK 0x02u\r
-#define SDCard_TxInternalInterrupt__INTC_NUMBER 1u\r
-#define SDCard_TxInternalInterrupt__INTC_PRIOR_NUM 7u\r
-#define SDCard_TxInternalInterrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
-#define SDCard_TxInternalInterrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SDCard_TxInternalInterrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+/* SCSI_ATN_ISR */\r
+#define SCSI_ATN_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_ATN_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_ATN_ISR__INTC_MASK 0x01u\r
+#define SCSI_ATN_ISR__INTC_NUMBER 0u\r
+#define SCSI_ATN_ISR__INTC_PRIOR_NUM 7u\r
+#define SCSI_ATN_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
+#define SCSI_ATN_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_ATN_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__MASK 0x01u\r
#define SCSI_Out_DBx__BIT_MASK CYREG_PRT0_BIT_MASK\r
#define SCSI_Out_DBx__BYP CYREG_PRT0_BYP\r
#define SCSI_Out_DBx__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out_DBx__DB0__MASK 0x01u\r
+#define SCSI_Out_DBx__DB0__PC CYREG_PRT0_PC0\r
+#define SCSI_Out_DBx__DB0__PORT 0u\r
+#define SCSI_Out_DBx__DB0__SHIFT 0\r
+#define SCSI_Out_DBx__DB1__MASK 0x02u\r
+#define SCSI_Out_DBx__DB1__PC CYREG_PRT0_PC1\r
+#define SCSI_Out_DBx__DB1__PORT 0u\r
+#define SCSI_Out_DBx__DB1__SHIFT 1\r
+#define SCSI_Out_DBx__DB2__MASK 0x04u\r
+#define SCSI_Out_DBx__DB2__PC CYREG_PRT0_PC2\r
+#define SCSI_Out_DBx__DB2__PORT 0u\r
+#define SCSI_Out_DBx__DB2__SHIFT 2\r
+#define SCSI_Out_DBx__DB3__MASK 0x08u\r
+#define SCSI_Out_DBx__DB3__PC CYREG_PRT0_PC3\r
+#define SCSI_Out_DBx__DB3__PORT 0u\r
+#define SCSI_Out_DBx__DB3__SHIFT 3\r
+#define SCSI_Out_DBx__DB4__MASK 0x10u\r
+#define SCSI_Out_DBx__DB4__PC CYREG_PRT0_PC4\r
+#define SCSI_Out_DBx__DB4__PORT 0u\r
+#define SCSI_Out_DBx__DB4__SHIFT 4\r
+#define SCSI_Out_DBx__DB5__MASK 0x20u\r
+#define SCSI_Out_DBx__DB5__PC CYREG_PRT0_PC5\r
+#define SCSI_Out_DBx__DB5__PORT 0u\r
+#define SCSI_Out_DBx__DB5__SHIFT 5\r
+#define SCSI_Out_DBx__DB6__MASK 0x40u\r
+#define SCSI_Out_DBx__DB6__PC CYREG_PRT0_PC6\r
+#define SCSI_Out_DBx__DB6__PORT 0u\r
+#define SCSI_Out_DBx__DB6__SHIFT 6\r
+#define SCSI_Out_DBx__DB7__MASK 0x80u\r
+#define SCSI_Out_DBx__DB7__PC CYREG_PRT0_PC7\r
+#define SCSI_Out_DBx__DB7__PORT 0u\r
+#define SCSI_Out_DBx__DB7__SHIFT 7\r
#define SCSI_Out_DBx__DM0 CYREG_PRT0_DM0\r
#define SCSI_Out_DBx__DM1 CYREG_PRT0_DM1\r
#define SCSI_Out_DBx__DM2 CYREG_PRT0_DM2\r
#define SCSI_Out_DBx__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
#define SCSI_Out_DBx__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
#define SCSI_Out_DBx__PS CYREG_PRT0_PS\r
-#define SCSI_Out_DBx__SCSI_Out_DB0__MASK 0x01u\r
-#define SCSI_Out_DBx__SCSI_Out_DB0__PC CYREG_PRT0_PC0\r
-#define SCSI_Out_DBx__SCSI_Out_DB0__PORT 0u\r
-#define SCSI_Out_DBx__SCSI_Out_DB0__SHIFT 0\r
-#define SCSI_Out_DBx__SCSI_Out_DB1__MASK 0x02u\r
-#define SCSI_Out_DBx__SCSI_Out_DB1__PC CYREG_PRT0_PC1\r
-#define SCSI_Out_DBx__SCSI_Out_DB1__PORT 0u\r
-#define SCSI_Out_DBx__SCSI_Out_DB1__SHIFT 1\r
-#define SCSI_Out_DBx__SCSI_Out_DB2__MASK 0x04u\r
-#define SCSI_Out_DBx__SCSI_Out_DB2__PC CYREG_PRT0_PC2\r
-#define SCSI_Out_DBx__SCSI_Out_DB2__PORT 0u\r
-#define SCSI_Out_DBx__SCSI_Out_DB2__SHIFT 2\r
-#define SCSI_Out_DBx__SCSI_Out_DB3__MASK 0x08u\r
-#define SCSI_Out_DBx__SCSI_Out_DB3__PC CYREG_PRT0_PC3\r
-#define SCSI_Out_DBx__SCSI_Out_DB3__PORT 0u\r
-#define SCSI_Out_DBx__SCSI_Out_DB3__SHIFT 3\r
-#define SCSI_Out_DBx__SCSI_Out_DB4__MASK 0x10u\r
-#define SCSI_Out_DBx__SCSI_Out_DB4__PC CYREG_PRT0_PC4\r
-#define SCSI_Out_DBx__SCSI_Out_DB4__PORT 0u\r
-#define SCSI_Out_DBx__SCSI_Out_DB4__SHIFT 4\r
-#define SCSI_Out_DBx__SCSI_Out_DB5__MASK 0x20u\r
-#define SCSI_Out_DBx__SCSI_Out_DB5__PC CYREG_PRT0_PC5\r
-#define SCSI_Out_DBx__SCSI_Out_DB5__PORT 0u\r
-#define SCSI_Out_DBx__SCSI_Out_DB5__SHIFT 5\r
-#define SCSI_Out_DBx__SCSI_Out_DB6__MASK 0x40u\r
-#define SCSI_Out_DBx__SCSI_Out_DB6__PC CYREG_PRT0_PC6\r
-#define SCSI_Out_DBx__SCSI_Out_DB6__PORT 0u\r
-#define SCSI_Out_DBx__SCSI_Out_DB6__SHIFT 6\r
-#define SCSI_Out_DBx__SCSI_Out_DB7__MASK 0x80u\r
-#define SCSI_Out_DBx__SCSI_Out_DB7__PC CYREG_PRT0_PC7\r
-#define SCSI_Out_DBx__SCSI_Out_DB7__PORT 0u\r
-#define SCSI_Out_DBx__SCSI_Out_DB7__SHIFT 7\r
#define SCSI_Out_DBx__SHIFT 0\r
#define SCSI_Out_DBx__SLW CYREG_PRT0_SLW\r
\r
+/* SCSI_RST_ISR */\r
+#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_RST_ISR__INTC_MASK 0x400u\r
+#define SCSI_RST_ISR__INTC_NUMBER 10u\r
+#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u\r
+#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_10\r
+#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST\r
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB07_08_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB07_08_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB07_08_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB07_08_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB07_08_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB07_08_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB07_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB07_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB07_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB07_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB07_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB07_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB07_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB07_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB07_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
\r
/* SCSI_In_DBx */\r
#define SCSI_In_DBx__0__MASK 0x01u\r
#define SCSI_In_DBx__BIT_MASK CYREG_PRT2_BIT_MASK\r
#define SCSI_In_DBx__BYP CYREG_PRT2_BYP\r
#define SCSI_In_DBx__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB0__MASK 0x01u\r
+#define SCSI_In_DBx__DB0__PC CYREG_PRT2_PC0\r
+#define SCSI_In_DBx__DB0__PORT 2u\r
+#define SCSI_In_DBx__DB0__SHIFT 0\r
+#define SCSI_In_DBx__DB1__MASK 0x02u\r
+#define SCSI_In_DBx__DB1__PC CYREG_PRT2_PC1\r
+#define SCSI_In_DBx__DB1__PORT 2u\r
+#define SCSI_In_DBx__DB1__SHIFT 1\r
+#define SCSI_In_DBx__DB2__MASK 0x04u\r
+#define SCSI_In_DBx__DB2__PC CYREG_PRT2_PC2\r
+#define SCSI_In_DBx__DB2__PORT 2u\r
+#define SCSI_In_DBx__DB2__SHIFT 2\r
+#define SCSI_In_DBx__DB3__MASK 0x08u\r
+#define SCSI_In_DBx__DB3__PC CYREG_PRT2_PC3\r
+#define SCSI_In_DBx__DB3__PORT 2u\r
+#define SCSI_In_DBx__DB3__SHIFT 3\r
+#define SCSI_In_DBx__DB4__MASK 0x10u\r
+#define SCSI_In_DBx__DB4__PC CYREG_PRT2_PC4\r
+#define SCSI_In_DBx__DB4__PORT 2u\r
+#define SCSI_In_DBx__DB4__SHIFT 4\r
+#define SCSI_In_DBx__DB5__MASK 0x20u\r
+#define SCSI_In_DBx__DB5__PC CYREG_PRT2_PC5\r
+#define SCSI_In_DBx__DB5__PORT 2u\r
+#define SCSI_In_DBx__DB5__SHIFT 5\r
+#define SCSI_In_DBx__DB6__MASK 0x40u\r
+#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC6\r
+#define SCSI_In_DBx__DB6__PORT 2u\r
+#define SCSI_In_DBx__DB6__SHIFT 6\r
+#define SCSI_In_DBx__DB7__MASK 0x80u\r
+#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC7\r
+#define SCSI_In_DBx__DB7__PORT 2u\r
+#define SCSI_In_DBx__DB7__SHIFT 7\r
#define SCSI_In_DBx__DM0 CYREG_PRT2_DM0\r
#define SCSI_In_DBx__DM1 CYREG_PRT2_DM1\r
#define SCSI_In_DBx__DM2 CYREG_PRT2_DM2\r
#define SCSI_In_DBx__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
#define SCSI_In_DBx__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
#define SCSI_In_DBx__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__SCSI_Out_DB0__MASK 0x01u\r
-#define SCSI_In_DBx__SCSI_Out_DB0__PC CYREG_PRT2_PC0\r
-#define SCSI_In_DBx__SCSI_Out_DB0__PORT 2u\r
-#define SCSI_In_DBx__SCSI_Out_DB0__SHIFT 0\r
-#define SCSI_In_DBx__SCSI_Out_DB1__MASK 0x02u\r
-#define SCSI_In_DBx__SCSI_Out_DB1__PC CYREG_PRT2_PC1\r
-#define SCSI_In_DBx__SCSI_Out_DB1__PORT 2u\r
-#define SCSI_In_DBx__SCSI_Out_DB1__SHIFT 1\r
-#define SCSI_In_DBx__SCSI_Out_DB2__MASK 0x04u\r
-#define SCSI_In_DBx__SCSI_Out_DB2__PC CYREG_PRT2_PC2\r
-#define SCSI_In_DBx__SCSI_Out_DB2__PORT 2u\r
-#define SCSI_In_DBx__SCSI_Out_DB2__SHIFT 2\r
-#define SCSI_In_DBx__SCSI_Out_DB3__MASK 0x08u\r
-#define SCSI_In_DBx__SCSI_Out_DB3__PC CYREG_PRT2_PC3\r
-#define SCSI_In_DBx__SCSI_Out_DB3__PORT 2u\r
-#define SCSI_In_DBx__SCSI_Out_DB3__SHIFT 3\r
-#define SCSI_In_DBx__SCSI_Out_DB4__MASK 0x10u\r
-#define SCSI_In_DBx__SCSI_Out_DB4__PC CYREG_PRT2_PC4\r
-#define SCSI_In_DBx__SCSI_Out_DB4__PORT 2u\r
-#define SCSI_In_DBx__SCSI_Out_DB4__SHIFT 4\r
-#define SCSI_In_DBx__SCSI_Out_DB5__MASK 0x20u\r
-#define SCSI_In_DBx__SCSI_Out_DB5__PC CYREG_PRT2_PC5\r
-#define SCSI_In_DBx__SCSI_Out_DB5__PORT 2u\r
-#define SCSI_In_DBx__SCSI_Out_DB5__SHIFT 5\r
-#define SCSI_In_DBx__SCSI_Out_DB6__MASK 0x40u\r
-#define SCSI_In_DBx__SCSI_Out_DB6__PC CYREG_PRT2_PC6\r
-#define SCSI_In_DBx__SCSI_Out_DB6__PORT 2u\r
-#define SCSI_In_DBx__SCSI_Out_DB6__SHIFT 6\r
-#define SCSI_In_DBx__SCSI_Out_DB7__MASK 0x80u\r
-#define SCSI_In_DBx__SCSI_Out_DB7__PC CYREG_PRT2_PC7\r
-#define SCSI_In_DBx__SCSI_Out_DB7__PORT 2u\r
-#define SCSI_In_DBx__SCSI_Out_DB7__SHIFT 7\r
#define SCSI_In_DBx__SHIFT 0\r
#define SCSI_In_DBx__SLW CYREG_PRT2_SLW\r
\r
/* SD_Clk_Ctl */\r
#define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB06_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB06_CTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB07_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB07_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL\r
#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB06_MSK\r
-#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB07_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
\r
/* PARITY_EN */\r
#define PARITY_EN__0__MASK 0x10u\r
#define PARITY_EN__SHIFT 4\r
#define PARITY_EN__SLW CYREG_PRT5_SLW\r
\r
+/* SCSI_ATN */\r
+#define SCSI_ATN__0__MASK 0x20u\r
+#define SCSI_ATN__0__PC CYREG_PRT12_PC5\r
+#define SCSI_ATN__0__PORT 12u\r
+#define SCSI_ATN__0__SHIFT 5\r
+#define SCSI_ATN__AG CYREG_PRT12_AG\r
+#define SCSI_ATN__BIE CYREG_PRT12_BIE\r
+#define SCSI_ATN__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_ATN__BYP CYREG_PRT12_BYP\r
+#define SCSI_ATN__DM0 CYREG_PRT12_DM0\r
+#define SCSI_ATN__DM1 CYREG_PRT12_DM1\r
+#define SCSI_ATN__DM2 CYREG_PRT12_DM2\r
+#define SCSI_ATN__DR CYREG_PRT12_DR\r
+#define SCSI_ATN__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_ATN__INT__MASK 0x20u\r
+#define SCSI_ATN__INT__PC CYREG_PRT12_PC5\r
+#define SCSI_ATN__INT__PORT 12u\r
+#define SCSI_ATN__INT__SHIFT 5\r
+#define SCSI_ATN__MASK 0x20u\r
+#define SCSI_ATN__PORT 12u\r
+#define SCSI_ATN__PRT CYREG_PRT12_PRT\r
+#define SCSI_ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_ATN__PS CYREG_PRT12_PS\r
+#define SCSI_ATN__SHIFT 5\r
+#define SCSI_ATN__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_ATN__SLW CYREG_PRT12_SLW\r
+\r
/* SCSI_Out */\r
#define SCSI_Out__0__AG CYREG_PRT4_AG\r
#define SCSI_Out__0__AMUX CYREG_PRT4_AMUX\r
#define SCSI_Out__SEL__SHIFT 0\r
#define SCSI_Out__SEL__SLW CYREG_PRT6_SLW\r
\r
+/* SCSI_RST */\r
+#define SCSI_RST__0__MASK 0x40u\r
+#define SCSI_RST__0__PC CYREG_PRT6_PC6\r
+#define SCSI_RST__0__PORT 6u\r
+#define SCSI_RST__0__SHIFT 6\r
+#define SCSI_RST__AG CYREG_PRT6_AG\r
+#define SCSI_RST__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_RST__BIE CYREG_PRT6_BIE\r
+#define SCSI_RST__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_RST__BYP CYREG_PRT6_BYP\r
+#define SCSI_RST__CTL CYREG_PRT6_CTL\r
+#define SCSI_RST__DM0 CYREG_PRT6_DM0\r
+#define SCSI_RST__DM1 CYREG_PRT6_DM1\r
+#define SCSI_RST__DM2 CYREG_PRT6_DM2\r
+#define SCSI_RST__DR CYREG_PRT6_DR\r
+#define SCSI_RST__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_RST__INTSTAT CYREG_PICU6_INTSTAT\r
+#define SCSI_RST__INT__MASK 0x40u\r
+#define SCSI_RST__INT__PC CYREG_PRT6_PC6\r
+#define SCSI_RST__INT__PORT 6u\r
+#define SCSI_RST__INT__SHIFT 6\r
+#define SCSI_RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_RST__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_RST__MASK 0x40u\r
+#define SCSI_RST__PORT 6u\r
+#define SCSI_RST__PRT CYREG_PRT6_PRT\r
+#define SCSI_RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_RST__PS CYREG_PRT6_PS\r
+#define SCSI_RST__SHIFT 6\r
+#define SCSI_RST__SLW CYREG_PRT6_SLW\r
+#define SCSI_RST__SNAP CYREG_PICU6_SNAP\r
+\r
/* SCSI_ID */\r
#define SCSI_ID__0__MASK 0x80u\r
#define SCSI_ID__0__PC CYREG_PRT5_PC7\r
#define SCSI_In__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
#define SCSI_In__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
#define SCSI_In__0__SLW CYREG_PRT12_SLW\r
-#define SCSI_In__1__AG CYREG_PRT12_AG\r
-#define SCSI_In__1__BIE CYREG_PRT12_BIE\r
-#define SCSI_In__1__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_In__1__BYP CYREG_PRT12_BYP\r
-#define SCSI_In__1__DM0 CYREG_PRT12_DM0\r
-#define SCSI_In__1__DM1 CYREG_PRT12_DM1\r
-#define SCSI_In__1__DM2 CYREG_PRT12_DM2\r
-#define SCSI_In__1__DR CYREG_PRT12_DR\r
-#define SCSI_In__1__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_In__1__MASK 0x20u\r
-#define SCSI_In__1__PC CYREG_PRT12_PC5\r
-#define SCSI_In__1__PORT 12u\r
-#define SCSI_In__1__PRT CYREG_PRT12_PRT\r
-#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_In__1__PS CYREG_PRT12_PS\r
-#define SCSI_In__1__SHIFT 5\r
-#define SCSI_In__1__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_In__1__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_In__1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_In__1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_In__1__SLW CYREG_PRT12_SLW\r
+#define SCSI_In__1__AG CYREG_PRT6_AG\r
+#define SCSI_In__1__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_In__1__BIE CYREG_PRT6_BIE\r
+#define SCSI_In__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_In__1__BYP CYREG_PRT6_BYP\r
+#define SCSI_In__1__CTL CYREG_PRT6_CTL\r
+#define SCSI_In__1__DM0 CYREG_PRT6_DM0\r
+#define SCSI_In__1__DM1 CYREG_PRT6_DM1\r
+#define SCSI_In__1__DM2 CYREG_PRT6_DM2\r
+#define SCSI_In__1__DR CYREG_PRT6_DR\r
+#define SCSI_In__1__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_In__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_In__1__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_In__1__MASK 0x10u\r
+#define SCSI_In__1__PC CYREG_PRT6_PC4\r
+#define SCSI_In__1__PORT 6u\r
+#define SCSI_In__1__PRT CYREG_PRT6_PRT\r
+#define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_In__1__PS CYREG_PRT6_PS\r
+#define SCSI_In__1__SHIFT 4\r
+#define SCSI_In__1__SLW CYREG_PRT6_SLW\r
#define SCSI_In__2__AG CYREG_PRT6_AG\r
#define SCSI_In__2__AMUX CYREG_PRT6_AMUX\r
#define SCSI_In__2__BIE CYREG_PRT6_BIE\r
#define SCSI_In__2__INP_DIS CYREG_PRT6_INP_DIS\r
#define SCSI_In__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
#define SCSI_In__2__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__2__MASK 0x10u\r
-#define SCSI_In__2__PC CYREG_PRT6_PC4\r
+#define SCSI_In__2__MASK 0x20u\r
+#define SCSI_In__2__PC CYREG_PRT6_PC5\r
#define SCSI_In__2__PORT 6u\r
#define SCSI_In__2__PRT CYREG_PRT6_PRT\r
#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_In__2__PS CYREG_PRT6_PS\r
-#define SCSI_In__2__SHIFT 4\r
+#define SCSI_In__2__SHIFT 5\r
#define SCSI_In__2__SLW CYREG_PRT6_SLW\r
#define SCSI_In__3__AG CYREG_PRT6_AG\r
#define SCSI_In__3__AMUX CYREG_PRT6_AMUX\r
#define SCSI_In__3__INP_DIS CYREG_PRT6_INP_DIS\r
#define SCSI_In__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
#define SCSI_In__3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__3__MASK 0x20u\r
-#define SCSI_In__3__PC CYREG_PRT6_PC5\r
+#define SCSI_In__3__MASK 0x80u\r
+#define SCSI_In__3__PC CYREG_PRT6_PC7\r
#define SCSI_In__3__PORT 6u\r
#define SCSI_In__3__PRT CYREG_PRT6_PRT\r
#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
#define SCSI_In__3__PS CYREG_PRT6_PS\r
-#define SCSI_In__3__SHIFT 5\r
+#define SCSI_In__3__SHIFT 7\r
#define SCSI_In__3__SLW CYREG_PRT6_SLW\r
-#define SCSI_In__4__AG CYREG_PRT6_AG\r
-#define SCSI_In__4__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In__4__BIE CYREG_PRT6_BIE\r
-#define SCSI_In__4__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In__4__BYP CYREG_PRT6_BYP\r
-#define SCSI_In__4__CTL CYREG_PRT6_CTL\r
-#define SCSI_In__4__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In__4__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In__4__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In__4__DR CYREG_PRT6_DR\r
-#define SCSI_In__4__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In__4__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__4__MASK 0x40u\r
-#define SCSI_In__4__PC CYREG_PRT6_PC6\r
-#define SCSI_In__4__PORT 6u\r
-#define SCSI_In__4__PRT CYREG_PRT6_PRT\r
-#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In__4__PS CYREG_PRT6_PS\r
-#define SCSI_In__4__SHIFT 6\r
-#define SCSI_In__4__SLW CYREG_PRT6_SLW\r
-#define SCSI_In__5__AG CYREG_PRT6_AG\r
-#define SCSI_In__5__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In__5__BIE CYREG_PRT6_BIE\r
-#define SCSI_In__5__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In__5__BYP CYREG_PRT6_BYP\r
-#define SCSI_In__5__CTL CYREG_PRT6_CTL\r
-#define SCSI_In__5__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In__5__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In__5__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In__5__DR CYREG_PRT6_DR\r
-#define SCSI_In__5__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In__5__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In__5__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__5__MASK 0x80u\r
-#define SCSI_In__5__PC CYREG_PRT6_PC7\r
-#define SCSI_In__5__PORT 6u\r
-#define SCSI_In__5__PRT CYREG_PRT6_PRT\r
-#define SCSI_In__5__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In__5__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In__5__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In__5__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In__5__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In__5__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In__5__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In__5__PS CYREG_PRT6_PS\r
-#define SCSI_In__5__SHIFT 7\r
-#define SCSI_In__5__SLW CYREG_PRT6_SLW\r
+#define SCSI_In__4__AG CYREG_PRT5_AG\r
+#define SCSI_In__4__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__4__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__4__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__4__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__4__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__4__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__4__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__4__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__4__DR CYREG_PRT5_DR\r
+#define SCSI_In__4__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__4__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__4__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__4__MASK 0x01u\r
+#define SCSI_In__4__PC CYREG_PRT5_PC0\r
+#define SCSI_In__4__PORT 5u\r
+#define SCSI_In__4__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__4__PS CYREG_PRT5_PS\r
+#define SCSI_In__4__SHIFT 0\r
+#define SCSI_In__4__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__5__AG CYREG_PRT5_AG\r
+#define SCSI_In__5__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__5__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__5__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__5__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__5__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__5__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__5__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__5__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__5__DR CYREG_PRT5_DR\r
+#define SCSI_In__5__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__5__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__5__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__5__MASK 0x02u\r
+#define SCSI_In__5__PC CYREG_PRT5_PC1\r
+#define SCSI_In__5__PORT 5u\r
+#define SCSI_In__5__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__5__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__5__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__5__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__5__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__5__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__5__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__5__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__5__PS CYREG_PRT5_PS\r
+#define SCSI_In__5__SHIFT 1\r
+#define SCSI_In__5__SLW CYREG_PRT5_SLW\r
#define SCSI_In__6__AG CYREG_PRT5_AG\r
#define SCSI_In__6__AMUX CYREG_PRT5_AMUX\r
#define SCSI_In__6__BIE CYREG_PRT5_BIE\r
#define SCSI_In__6__INP_DIS CYREG_PRT5_INP_DIS\r
#define SCSI_In__6__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
#define SCSI_In__6__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__6__MASK 0x01u\r
-#define SCSI_In__6__PC CYREG_PRT5_PC0\r
+#define SCSI_In__6__MASK 0x04u\r
+#define SCSI_In__6__PC CYREG_PRT5_PC2\r
#define SCSI_In__6__PORT 5u\r
#define SCSI_In__6__PRT CYREG_PRT5_PRT\r
#define SCSI_In__6__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
#define SCSI_In__6__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_In__6__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_In__6__PS CYREG_PRT5_PS\r
-#define SCSI_In__6__SHIFT 0\r
+#define SCSI_In__6__SHIFT 2\r
#define SCSI_In__6__SLW CYREG_PRT5_SLW\r
#define SCSI_In__7__AG CYREG_PRT5_AG\r
#define SCSI_In__7__AMUX CYREG_PRT5_AMUX\r
#define SCSI_In__7__INP_DIS CYREG_PRT5_INP_DIS\r
#define SCSI_In__7__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
#define SCSI_In__7__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__7__MASK 0x02u\r
-#define SCSI_In__7__PC CYREG_PRT5_PC1\r
+#define SCSI_In__7__MASK 0x08u\r
+#define SCSI_In__7__PC CYREG_PRT5_PC3\r
#define SCSI_In__7__PORT 5u\r
#define SCSI_In__7__PRT CYREG_PRT5_PRT\r
#define SCSI_In__7__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
#define SCSI_In__7__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
#define SCSI_In__7__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
#define SCSI_In__7__PS CYREG_PRT5_PS\r
-#define SCSI_In__7__SHIFT 1\r
+#define SCSI_In__7__SHIFT 3\r
#define SCSI_In__7__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__8__AG CYREG_PRT5_AG\r
-#define SCSI_In__8__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__8__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__8__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__8__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__8__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__8__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__8__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__8__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__8__DR CYREG_PRT5_DR\r
-#define SCSI_In__8__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__8__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__8__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__8__MASK 0x04u\r
-#define SCSI_In__8__PC CYREG_PRT5_PC2\r
-#define SCSI_In__8__PORT 5u\r
-#define SCSI_In__8__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__8__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__8__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__8__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__8__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__8__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__8__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__8__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__8__PS CYREG_PRT5_PS\r
-#define SCSI_In__8__SHIFT 2\r
-#define SCSI_In__8__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__9__AG CYREG_PRT5_AG\r
-#define SCSI_In__9__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_In__9__BIE CYREG_PRT5_BIE\r
-#define SCSI_In__9__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_In__9__BYP CYREG_PRT5_BYP\r
-#define SCSI_In__9__CTL CYREG_PRT5_CTL\r
-#define SCSI_In__9__DM0 CYREG_PRT5_DM0\r
-#define SCSI_In__9__DM1 CYREG_PRT5_DM1\r
-#define SCSI_In__9__DM2 CYREG_PRT5_DM2\r
-#define SCSI_In__9__DR CYREG_PRT5_DR\r
-#define SCSI_In__9__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_In__9__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_In__9__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_In__9__MASK 0x08u\r
-#define SCSI_In__9__PC CYREG_PRT5_PC3\r
-#define SCSI_In__9__PORT 5u\r
-#define SCSI_In__9__PRT CYREG_PRT5_PRT\r
-#define SCSI_In__9__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_In__9__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_In__9__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_In__9__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_In__9__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_In__9__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_In__9__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_In__9__PS CYREG_PRT5_PS\r
-#define SCSI_In__9__SHIFT 3\r
-#define SCSI_In__9__SLW CYREG_PRT5_SLW\r
#define SCSI_In__ACK__AG CYREG_PRT6_AG\r
#define SCSI_In__ACK__AMUX CYREG_PRT6_AMUX\r
#define SCSI_In__ACK__BIE CYREG_PRT6_BIE\r
#define SCSI_In__ACK__PS CYREG_PRT6_PS\r
#define SCSI_In__ACK__SHIFT 5\r
#define SCSI_In__ACK__SLW CYREG_PRT6_SLW\r
-#define SCSI_In__ATN__AG CYREG_PRT12_AG\r
-#define SCSI_In__ATN__BIE CYREG_PRT12_BIE\r
-#define SCSI_In__ATN__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_In__ATN__BYP CYREG_PRT12_BYP\r
-#define SCSI_In__ATN__DM0 CYREG_PRT12_DM0\r
-#define SCSI_In__ATN__DM1 CYREG_PRT12_DM1\r
-#define SCSI_In__ATN__DM2 CYREG_PRT12_DM2\r
-#define SCSI_In__ATN__DR CYREG_PRT12_DR\r
-#define SCSI_In__ATN__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_In__ATN__MASK 0x20u\r
-#define SCSI_In__ATN__PC CYREG_PRT12_PC5\r
-#define SCSI_In__ATN__PORT 12u\r
-#define SCSI_In__ATN__PRT CYREG_PRT12_PRT\r
-#define SCSI_In__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_In__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_In__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_In__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_In__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_In__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_In__ATN__PS CYREG_PRT12_PS\r
-#define SCSI_In__ATN__SHIFT 5\r
-#define SCSI_In__ATN__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_In__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_In__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_In__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_In__ATN__SLW CYREG_PRT12_SLW\r
#define SCSI_In__BSY__AG CYREG_PRT6_AG\r
#define SCSI_In__BSY__AMUX CYREG_PRT6_AMUX\r
#define SCSI_In__BSY__BIE CYREG_PRT6_BIE\r
#define SCSI_In__REQ__PS CYREG_PRT5_PS\r
#define SCSI_In__REQ__SHIFT 2\r
#define SCSI_In__REQ__SLW CYREG_PRT5_SLW\r
-#define SCSI_In__RST__AG CYREG_PRT6_AG\r
-#define SCSI_In__RST__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_In__RST__BIE CYREG_PRT6_BIE\r
-#define SCSI_In__RST__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_In__RST__BYP CYREG_PRT6_BYP\r
-#define SCSI_In__RST__CTL CYREG_PRT6_CTL\r
-#define SCSI_In__RST__DM0 CYREG_PRT6_DM0\r
-#define SCSI_In__RST__DM1 CYREG_PRT6_DM1\r
-#define SCSI_In__RST__DM2 CYREG_PRT6_DM2\r
-#define SCSI_In__RST__DR CYREG_PRT6_DR\r
-#define SCSI_In__RST__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_In__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_In__RST__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_In__RST__MASK 0x40u\r
-#define SCSI_In__RST__PC CYREG_PRT6_PC6\r
-#define SCSI_In__RST__PORT 6u\r
-#define SCSI_In__RST__PRT CYREG_PRT6_PRT\r
-#define SCSI_In__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_In__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_In__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_In__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_In__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_In__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_In__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_In__RST__PS CYREG_PRT6_PS\r
-#define SCSI_In__RST__SHIFT 6\r
-#define SCSI_In__RST__SLW CYREG_PRT6_SLW\r
#define SCSI_In__SEL__AG CYREG_PRT5_AG\r
#define SCSI_In__SEL__AMUX CYREG_PRT5_AMUX\r
#define SCSI_In__SEL__BIE CYREG_PRT5_BIE\r
#define CYDEV_DEBUGGING_DPS_JTAG_5 0\r
#define CYDEV_DEBUGGING_DPS_SWD 2\r
#define CYDEV_DEBUGGING_ENABLE 1\r
-#define CYDEV_DEBUGGING_REQXRES 1\r
#define CYDEV_DEBUGGING_XRES 0\r
#define CYDEV_DEBUG_ENABLE_MASK 0x20u\r
#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG\r
#define CYDEV_ECC_ENABLE 0\r
#define CYDEV_HEAP_SIZE 0x1000\r
#define CYDEV_INSTRUCT_CACHE_ENABLED 1\r
-#define CYDEV_INTR_RISING 0x00000003u\r
+#define CYDEV_INTR_RISING 0x00000001u\r
#define CYDEV_PROJ_TYPE 0\r
#define CYDEV_PROJ_TYPE_BOOTLOADER 1\r
#define CYDEV_PROJ_TYPE_LOADABLE 2\r
/*******************************************************************************\r
* FILENAME: cyfitter_cfg.c\r
-* PSoC Creator 2.2 Component Pack 6\r
+* PSoC Creator 3.0\r
*\r
* Description:\r
* This file is automatically generated by PSoC Creator with device \r
#include <CyLib.h>\r
#include <cyfitter_cfg.h>\r
\r
+#define CY_NEED_CYCLOCKSTARTUPERROR 1\r
+\r
+\r
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
+ #define CYPACKED \r
+ #define CYPACKED_ATTR __attribute__ ((packed))\r
+ #define CYALIGNED __attribute__ ((aligned))\r
+ #define CY_CFG_UNUSED __attribute__ ((unused))\r
+ #define CY_CFG_SECTION __attribute__ ((section(".psocinit")))\r
+ \r
+ #if defined(__ARMCC_VERSION)\r
+ #define CY_CFG_MEMORY_BARRIER() __memory_changed()\r
+ #else\r
+ #define CY_CFG_MEMORY_BARRIER() __sync_synchronize()\r
+ #endif\r
+ \r
+#elif defined(__ICCARM__)\r
+ #include <intrinsics.h>\r
+\r
+ #define CYPACKED __packed\r
+ #define CYPACKED_ATTR \r
+ #define CYALIGNED _Pragma("data_alignment=4")\r
+ #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177")\r
+ #define CY_CFG_SECTION _Pragma("location=\".psocinit\"")\r
+ \r
+ #define CY_CFG_MEMORY_BARRIER() __DMB()\r
+ \r
+#else\r
+ #error Unsupported toolchain\r
+#endif\r
+\r
+\r
+CY_CFG_UNUSED\r
+static void CYMEMZERO(void *s, size_t n);\r
+CY_CFG_UNUSED\r
+static void CYMEMZERO(void *s, size_t n)\r
+{\r
+ (void)memset(s, 0, n);\r
+}\r
+CY_CFG_UNUSED\r
+static void CYCONFIGCPY(void *dest, const void *src, size_t n);\r
+CY_CFG_UNUSED\r
+static void CYCONFIGCPY(void *dest, const void *src, size_t n)\r
+{\r
+ (void)memcpy(dest, src, n);\r
+}\r
+CY_CFG_UNUSED\r
+static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);\r
+CY_CFG_UNUSED\r
+static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)\r
+{\r
+ (void)memcpy(dest, src, n);\r
+}\r
+\r
+\r
+\r
/* Clock startup error codes */\r
#define CYCLOCKSTART_NO_ERROR 0u\r
#define CYCLOCKSTART_XTAL_ERROR 1u\r
* void\r
*\r
*******************************************************************************/\r
-#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
-__attribute__ ((unused))\r
-#endif\r
+CY_CFG_UNUSED\r
static void CyClockStartupError(uint8 errorCode);\r
-#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
-__attribute__ ((unused))\r
-#endif\r
+CY_CFG_UNUSED\r
static void CyClockStartupError(uint8 errorCode)\r
{\r
/* To remove the compiler warning if errorCode not used. */\r
}\r
#endif\r
\r
-\r
-#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
- #define CYPACKED __attribute__ ((packed))\r
- #define CYALIGNED __attribute__ ((aligned))\r
- \r
- #if defined(__ARMCC_VERSION)\r
- #define CY_CFG_MEMORY_BARRIER() __memory_changed()\r
- #else\r
- #define CY_CFG_MEMORY_BARRIER() __sync_synchronize()\r
- #endif\r
- \r
-\r
- __attribute__ ((unused))\r
- static void CYMEMZERO(void *s, size_t n);\r
- __attribute__ ((unused))\r
- static void CYMEMZERO(void *s, size_t n)\r
- {\r
- (void)memset(s, 0, n);\r
- }\r
- __attribute__ ((unused))\r
- static void CYCONFIGCPY(void *dest, const void *src, size_t n);\r
- __attribute__ ((unused))\r
- static void CYCONFIGCPY(void *dest, const void *src, size_t n)\r
- {\r
- (void)memcpy(dest, src, n);\r
- }\r
- __attribute__ ((unused))\r
- static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);\r
- __attribute__ ((unused))\r
- static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)\r
- {\r
- (void)memcpy(dest, src, n);\r
- }\r
-#else\r
- #error Unsupported toolchain\r
-#endif\r
-\r
-#define CY_CFG_BASE_ADDR_COUNT 16u\r
-typedef struct\r
+#define CY_CFG_BASE_ADDR_COUNT 22u\r
+CYPACKED typedef struct\r
{\r
uint8 offset;\r
uint8 value;\r
-} CYPACKED cy_cfg_addrvalue_t;\r
+} CYPACKED_ATTR cy_cfg_addrvalue_t;\r
\r
#define cy_cfg_addr_table ((const uint32 CYFAR *)0x48000000u)\r
-#define cy_cfg_data_table ((const cy_cfg_addrvalue_t CYFAR *)0x48000040u)\r
+#define cy_cfg_data_table ((const cy_cfg_addrvalue_t CYFAR *)0x48000058u)\r
\r
-/* UDB_1_1_0_CONFIG Address: CYDEV_UCFG_B1_P3_U1_BASE Size (bytes): 128 */\r
-#define BS_UDB_1_1_0_CONFIG_VAL ((const uint8 CYFAR *)0x480002D4u)\r
+/* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */\r
+#define BS_UDB_1_2_1_CONFIG_VAL ((const uint8 CYFAR *)0x48000318u)\r
\r
/* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */\r
-#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x48000354u)\r
+#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x48000398u)\r
\r
/* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */\r
-#define BS_IOPINS0_7_VAL ((const uint8 CYFAR *)0x4800035Cu)\r
+#define BS_IOPINS0_7_VAL ((const uint8 CYFAR *)0x480003A0u)\r
\r
/* IOPINS1_7 Address: CYREG_PRT12_DR + 0x0000000Bu Size (bytes): 5 */\r
-#define BS_IOPINS1_7_VAL ((const uint8 CYFAR *)0x48000368u)\r
+#define BS_IOPINS1_7_VAL ((const uint8 CYFAR *)0x480003ACu)\r
\r
/* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */\r
-#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x48000370u)\r
+#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x480003B4u)\r
\r
/* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */\r
-#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x48000378u)\r
+#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x480003BCu)\r
\r
/* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */\r
-#define BS_IOPINS0_4_VAL ((const uint8 CYFAR *)0x48000384u)\r
+#define BS_IOPINS0_4_VAL ((const uint8 CYFAR *)0x480003C8u)\r
\r
/* IOPINS0_5 Address: CYREG_PRT5_DR Size (bytes): 10 */\r
-#define BS_IOPINS0_5_VAL ((const uint8 CYFAR *)0x4800038Cu)\r
+#define BS_IOPINS0_5_VAL ((const uint8 CYFAR *)0x480003D0u)\r
\r
/* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */\r
-#define BS_IOPINS0_6_VAL ((const uint8 CYFAR *)0x48000398u)\r
+#define BS_IOPINS0_6_VAL ((const uint8 CYFAR *)0x480003DCu)\r
\r
\r
/*******************************************************************************\r
\r
/* Configure PLL based on settings from Clock DWR */\r
CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0F15u);\r
- CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1051u);\r
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u);\r
/* Wait up to 250us for the PLL to lock */\r
pllLock = 0u;\r
- for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--) { \r
+ for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--)\r
+ { \r
pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0));\r
CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */\r
}\r
+ /* If we ran out of time the PLL didn't lock so go to the error function */\r
+ if (timeout == 0u)\r
+ {\r
+ CyClockStartupError(CYCLOCKSTART_PLL_ERROR);\r
+ }\r
\r
/* Configure Bus/Master Clock based on settings from Clock DWR */\r
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u);\r
static void AnalogSetDefault(void)\r
{\r
uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u));\r
- CY_SET_XTND_REG8((void CYFAR *)CYREG_BG_DFT0, bg_xover_inl_trim & 0x07u);\r
- CY_SET_XTND_REG8((void CYFAR *)CYREG_BG_DFT1, ((uint8)((uint8)bg_xover_inl_trim >> 4)) & 0x0Fu);\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u));\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu));\r
CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u);\r
}\r
\r
\r
{\r
\r
- typedef struct {\r
+ CYPACKED typedef struct {\r
void CYFAR *address;\r
uint16 size;\r
- } CYPACKED cfg_memset_t;\r
+ } CYPACKED_ATTR cfg_memset_t;\r
\r
\r
- typedef struct {\r
+ CYPACKED typedef struct {\r
void CYFAR *dest;\r
const void CYFAR *src;\r
uint16 size;\r
- } CYPACKED cfg_memcpy_t;\r
+ } CYPACKED_ATTR cfg_memcpy_t;\r
\r
static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
/* address, size */\r
{(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
{(void CYFAR *)(CYREG_PRT15_DR), 16u},\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 640u},\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P3_ROUTE_BASE), 1280u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1536u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), 2432u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P3_U1_BASE), BS_UDB_1_1_0_CONFIG_VAL, 128u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P3_U0_BASE), BS_UDB_1_2_1_CONFIG_VAL, 128u},\r
};\r
\r
uint8 CYDATA i;\r
CYCONFIGCPY((void CYFAR *)(CYREG_PRT6_DM0), (const void CYFAR *)(BS_IOPINS0_6_VAL), 8u);\r
\r
/* Switch Boost to the precision bandgap reference from its internal reference */\r
- CY_SET_REG8((void CYXDATA *)CYDEV_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYDEV_BOOST_CR2) | 0x08u));\r
+ CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));\r
\r
/* Perform basic analog initialization to defaults */\r
AnalogSetDefault();\r
/*******************************************************************************\r
* FILENAME: cyfitter_cfg.h\r
-* PSoC Creator 2.2 Component Pack 6\r
+* PSoC Creator 3.0\r
*\r
* Description:\r
* This file is automatically generated by PSoC Creator.\r
.include "cydevicegnu.inc"\r
.include "cydevicegnu_trm.inc"\r
\r
-/* SDCard_RxInternalInterrupt */\r
-.set SDCard_RxInternalInterrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SDCard_RxInternalInterrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SDCard_RxInternalInterrupt__INTC_MASK, 0x01\r
-.set SDCard_RxInternalInterrupt__INTC_NUMBER, 0\r
-.set SDCard_RxInternalInterrupt__INTC_PRIOR_NUM, 7\r
-.set SDCard_RxInternalInterrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
-.set SDCard_RxInternalInterrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SDCard_RxInternalInterrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SDCard_TxInternalInterrupt */\r
-.set SDCard_TxInternalInterrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SDCard_TxInternalInterrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SDCard_TxInternalInterrupt__INTC_MASK, 0x02\r
-.set SDCard_TxInternalInterrupt__INTC_NUMBER, 1\r
-.set SDCard_TxInternalInterrupt__INTC_PRIOR_NUM, 7\r
-.set SDCard_TxInternalInterrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
-.set SDCard_TxInternalInterrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SDCard_TxInternalInterrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+/* SCSI_ATN_ISR */\r
+.set SCSI_ATN_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_ATN_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_ATN_ISR__INTC_MASK, 0x01\r
+.set SCSI_ATN_ISR__INTC_NUMBER, 0\r
+.set SCSI_ATN_ISR__INTC_PRIOR_NUM, 7\r
+.set SCSI_ATN_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set SCSI_ATN_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_ATN_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* SCSI_Out_DBx */\r
.set SCSI_Out_DBx__0__MASK, 0x01\r
.set SCSI_Out_DBx__BIT_MASK, CYREG_PRT0_BIT_MASK\r
.set SCSI_Out_DBx__BYP, CYREG_PRT0_BYP\r
.set SCSI_Out_DBx__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out_DBx__DB0__MASK, 0x01\r
+.set SCSI_Out_DBx__DB0__PC, CYREG_PRT0_PC0\r
+.set SCSI_Out_DBx__DB0__PORT, 0\r
+.set SCSI_Out_DBx__DB0__SHIFT, 0\r
+.set SCSI_Out_DBx__DB1__MASK, 0x02\r
+.set SCSI_Out_DBx__DB1__PC, CYREG_PRT0_PC1\r
+.set SCSI_Out_DBx__DB1__PORT, 0\r
+.set SCSI_Out_DBx__DB1__SHIFT, 1\r
+.set SCSI_Out_DBx__DB2__MASK, 0x04\r
+.set SCSI_Out_DBx__DB2__PC, CYREG_PRT0_PC2\r
+.set SCSI_Out_DBx__DB2__PORT, 0\r
+.set SCSI_Out_DBx__DB2__SHIFT, 2\r
+.set SCSI_Out_DBx__DB3__MASK, 0x08\r
+.set SCSI_Out_DBx__DB3__PC, CYREG_PRT0_PC3\r
+.set SCSI_Out_DBx__DB3__PORT, 0\r
+.set SCSI_Out_DBx__DB3__SHIFT, 3\r
+.set SCSI_Out_DBx__DB4__MASK, 0x10\r
+.set SCSI_Out_DBx__DB4__PC, CYREG_PRT0_PC4\r
+.set SCSI_Out_DBx__DB4__PORT, 0\r
+.set SCSI_Out_DBx__DB4__SHIFT, 4\r
+.set SCSI_Out_DBx__DB5__MASK, 0x20\r
+.set SCSI_Out_DBx__DB5__PC, CYREG_PRT0_PC5\r
+.set SCSI_Out_DBx__DB5__PORT, 0\r
+.set SCSI_Out_DBx__DB5__SHIFT, 5\r
+.set SCSI_Out_DBx__DB6__MASK, 0x40\r
+.set SCSI_Out_DBx__DB6__PC, CYREG_PRT0_PC6\r
+.set SCSI_Out_DBx__DB6__PORT, 0\r
+.set SCSI_Out_DBx__DB6__SHIFT, 6\r
+.set SCSI_Out_DBx__DB7__MASK, 0x80\r
+.set SCSI_Out_DBx__DB7__PC, CYREG_PRT0_PC7\r
+.set SCSI_Out_DBx__DB7__PORT, 0\r
+.set SCSI_Out_DBx__DB7__SHIFT, 7\r
.set SCSI_Out_DBx__DM0, CYREG_PRT0_DM0\r
.set SCSI_Out_DBx__DM1, CYREG_PRT0_DM1\r
.set SCSI_Out_DBx__DM2, CYREG_PRT0_DM2\r
.set SCSI_Out_DBx__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
.set SCSI_Out_DBx__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
.set SCSI_Out_DBx__PS, CYREG_PRT0_PS\r
-.set SCSI_Out_DBx__SCSI_Out_DB0__MASK, 0x01\r
-.set SCSI_Out_DBx__SCSI_Out_DB0__PC, CYREG_PRT0_PC0\r
-.set SCSI_Out_DBx__SCSI_Out_DB0__PORT, 0\r
-.set SCSI_Out_DBx__SCSI_Out_DB0__SHIFT, 0\r
-.set SCSI_Out_DBx__SCSI_Out_DB1__MASK, 0x02\r
-.set SCSI_Out_DBx__SCSI_Out_DB1__PC, CYREG_PRT0_PC1\r
-.set SCSI_Out_DBx__SCSI_Out_DB1__PORT, 0\r
-.set SCSI_Out_DBx__SCSI_Out_DB1__SHIFT, 1\r
-.set SCSI_Out_DBx__SCSI_Out_DB2__MASK, 0x04\r
-.set SCSI_Out_DBx__SCSI_Out_DB2__PC, CYREG_PRT0_PC2\r
-.set SCSI_Out_DBx__SCSI_Out_DB2__PORT, 0\r
-.set SCSI_Out_DBx__SCSI_Out_DB2__SHIFT, 2\r
-.set SCSI_Out_DBx__SCSI_Out_DB3__MASK, 0x08\r
-.set SCSI_Out_DBx__SCSI_Out_DB3__PC, CYREG_PRT0_PC3\r
-.set SCSI_Out_DBx__SCSI_Out_DB3__PORT, 0\r
-.set SCSI_Out_DBx__SCSI_Out_DB3__SHIFT, 3\r
-.set SCSI_Out_DBx__SCSI_Out_DB4__MASK, 0x10\r
-.set SCSI_Out_DBx__SCSI_Out_DB4__PC, CYREG_PRT0_PC4\r
-.set SCSI_Out_DBx__SCSI_Out_DB4__PORT, 0\r
-.set SCSI_Out_DBx__SCSI_Out_DB4__SHIFT, 4\r
-.set SCSI_Out_DBx__SCSI_Out_DB5__MASK, 0x20\r
-.set SCSI_Out_DBx__SCSI_Out_DB5__PC, CYREG_PRT0_PC5\r
-.set SCSI_Out_DBx__SCSI_Out_DB5__PORT, 0\r
-.set SCSI_Out_DBx__SCSI_Out_DB5__SHIFT, 5\r
-.set SCSI_Out_DBx__SCSI_Out_DB6__MASK, 0x40\r
-.set SCSI_Out_DBx__SCSI_Out_DB6__PC, CYREG_PRT0_PC6\r
-.set SCSI_Out_DBx__SCSI_Out_DB6__PORT, 0\r
-.set SCSI_Out_DBx__SCSI_Out_DB6__SHIFT, 6\r
-.set SCSI_Out_DBx__SCSI_Out_DB7__MASK, 0x80\r
-.set SCSI_Out_DBx__SCSI_Out_DB7__PC, CYREG_PRT0_PC7\r
-.set SCSI_Out_DBx__SCSI_Out_DB7__PORT, 0\r
-.set SCSI_Out_DBx__SCSI_Out_DB7__SHIFT, 7\r
.set SCSI_Out_DBx__SHIFT, 0\r
.set SCSI_Out_DBx__SLW, CYREG_PRT0_SLW\r
\r
+/* SCSI_RST_ISR */\r
+.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_RST_ISR__INTC_MASK, 0x400\r
+.set SCSI_RST_ISR__INTC_NUMBER, 10\r
+.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7\r
+.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_10\r
+.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST\r
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB07_08_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB07_08_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB07_08_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB07_08_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB07_08_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB07_08_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB07_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB07_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB07_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB07_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB07_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB07_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB07_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB07_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB07_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
\r
/* SCSI_In_DBx */\r
.set SCSI_In_DBx__0__MASK, 0x01\r
.set SCSI_In_DBx__BIT_MASK, CYREG_PRT2_BIT_MASK\r
.set SCSI_In_DBx__BYP, CYREG_PRT2_BYP\r
.set SCSI_In_DBx__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB0__MASK, 0x01\r
+.set SCSI_In_DBx__DB0__PC, CYREG_PRT2_PC0\r
+.set SCSI_In_DBx__DB0__PORT, 2\r
+.set SCSI_In_DBx__DB0__SHIFT, 0\r
+.set SCSI_In_DBx__DB1__MASK, 0x02\r
+.set SCSI_In_DBx__DB1__PC, CYREG_PRT2_PC1\r
+.set SCSI_In_DBx__DB1__PORT, 2\r
+.set SCSI_In_DBx__DB1__SHIFT, 1\r
+.set SCSI_In_DBx__DB2__MASK, 0x04\r
+.set SCSI_In_DBx__DB2__PC, CYREG_PRT2_PC2\r
+.set SCSI_In_DBx__DB2__PORT, 2\r
+.set SCSI_In_DBx__DB2__SHIFT, 2\r
+.set SCSI_In_DBx__DB3__MASK, 0x08\r
+.set SCSI_In_DBx__DB3__PC, CYREG_PRT2_PC3\r
+.set SCSI_In_DBx__DB3__PORT, 2\r
+.set SCSI_In_DBx__DB3__SHIFT, 3\r
+.set SCSI_In_DBx__DB4__MASK, 0x10\r
+.set SCSI_In_DBx__DB4__PC, CYREG_PRT2_PC4\r
+.set SCSI_In_DBx__DB4__PORT, 2\r
+.set SCSI_In_DBx__DB4__SHIFT, 4\r
+.set SCSI_In_DBx__DB5__MASK, 0x20\r
+.set SCSI_In_DBx__DB5__PC, CYREG_PRT2_PC5\r
+.set SCSI_In_DBx__DB5__PORT, 2\r
+.set SCSI_In_DBx__DB5__SHIFT, 5\r
+.set SCSI_In_DBx__DB6__MASK, 0x40\r
+.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC6\r
+.set SCSI_In_DBx__DB6__PORT, 2\r
+.set SCSI_In_DBx__DB6__SHIFT, 6\r
+.set SCSI_In_DBx__DB7__MASK, 0x80\r
+.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC7\r
+.set SCSI_In_DBx__DB7__PORT, 2\r
+.set SCSI_In_DBx__DB7__SHIFT, 7\r
.set SCSI_In_DBx__DM0, CYREG_PRT2_DM0\r
.set SCSI_In_DBx__DM1, CYREG_PRT2_DM1\r
.set SCSI_In_DBx__DM2, CYREG_PRT2_DM2\r
.set SCSI_In_DBx__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
.set SCSI_In_DBx__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
.set SCSI_In_DBx__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__SCSI_Out_DB0__MASK, 0x01\r
-.set SCSI_In_DBx__SCSI_Out_DB0__PC, CYREG_PRT2_PC0\r
-.set SCSI_In_DBx__SCSI_Out_DB0__PORT, 2\r
-.set SCSI_In_DBx__SCSI_Out_DB0__SHIFT, 0\r
-.set SCSI_In_DBx__SCSI_Out_DB1__MASK, 0x02\r
-.set SCSI_In_DBx__SCSI_Out_DB1__PC, CYREG_PRT2_PC1\r
-.set SCSI_In_DBx__SCSI_Out_DB1__PORT, 2\r
-.set SCSI_In_DBx__SCSI_Out_DB1__SHIFT, 1\r
-.set SCSI_In_DBx__SCSI_Out_DB2__MASK, 0x04\r
-.set SCSI_In_DBx__SCSI_Out_DB2__PC, CYREG_PRT2_PC2\r
-.set SCSI_In_DBx__SCSI_Out_DB2__PORT, 2\r
-.set SCSI_In_DBx__SCSI_Out_DB2__SHIFT, 2\r
-.set SCSI_In_DBx__SCSI_Out_DB3__MASK, 0x08\r
-.set SCSI_In_DBx__SCSI_Out_DB3__PC, CYREG_PRT2_PC3\r
-.set SCSI_In_DBx__SCSI_Out_DB3__PORT, 2\r
-.set SCSI_In_DBx__SCSI_Out_DB3__SHIFT, 3\r
-.set SCSI_In_DBx__SCSI_Out_DB4__MASK, 0x10\r
-.set SCSI_In_DBx__SCSI_Out_DB4__PC, CYREG_PRT2_PC4\r
-.set SCSI_In_DBx__SCSI_Out_DB4__PORT, 2\r
-.set SCSI_In_DBx__SCSI_Out_DB4__SHIFT, 4\r
-.set SCSI_In_DBx__SCSI_Out_DB5__MASK, 0x20\r
-.set SCSI_In_DBx__SCSI_Out_DB5__PC, CYREG_PRT2_PC5\r
-.set SCSI_In_DBx__SCSI_Out_DB5__PORT, 2\r
-.set SCSI_In_DBx__SCSI_Out_DB5__SHIFT, 5\r
-.set SCSI_In_DBx__SCSI_Out_DB6__MASK, 0x40\r
-.set SCSI_In_DBx__SCSI_Out_DB6__PC, CYREG_PRT2_PC6\r
-.set SCSI_In_DBx__SCSI_Out_DB6__PORT, 2\r
-.set SCSI_In_DBx__SCSI_Out_DB6__SHIFT, 6\r
-.set SCSI_In_DBx__SCSI_Out_DB7__MASK, 0x80\r
-.set SCSI_In_DBx__SCSI_Out_DB7__PC, CYREG_PRT2_PC7\r
-.set SCSI_In_DBx__SCSI_Out_DB7__PORT, 2\r
-.set SCSI_In_DBx__SCSI_Out_DB7__SHIFT, 7\r
.set SCSI_In_DBx__SHIFT, 0\r
.set SCSI_In_DBx__SLW, CYREG_PRT2_SLW\r
\r
/* SD_Clk_Ctl */\r
.set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB06_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB06_CTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB07_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB07_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL\r
.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB06_MSK\r
-.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB07_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
\r
/* PARITY_EN */\r
.set PARITY_EN__0__MASK, 0x10\r
.set PARITY_EN__SHIFT, 4\r
.set PARITY_EN__SLW, CYREG_PRT5_SLW\r
\r
+/* SCSI_ATN */\r
+.set SCSI_ATN__0__MASK, 0x20\r
+.set SCSI_ATN__0__PC, CYREG_PRT12_PC5\r
+.set SCSI_ATN__0__PORT, 12\r
+.set SCSI_ATN__0__SHIFT, 5\r
+.set SCSI_ATN__AG, CYREG_PRT12_AG\r
+.set SCSI_ATN__BIE, CYREG_PRT12_BIE\r
+.set SCSI_ATN__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_ATN__BYP, CYREG_PRT12_BYP\r
+.set SCSI_ATN__DM0, CYREG_PRT12_DM0\r
+.set SCSI_ATN__DM1, CYREG_PRT12_DM1\r
+.set SCSI_ATN__DM2, CYREG_PRT12_DM2\r
+.set SCSI_ATN__DR, CYREG_PRT12_DR\r
+.set SCSI_ATN__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_ATN__INT__MASK, 0x20\r
+.set SCSI_ATN__INT__PC, CYREG_PRT12_PC5\r
+.set SCSI_ATN__INT__PORT, 12\r
+.set SCSI_ATN__INT__SHIFT, 5\r
+.set SCSI_ATN__MASK, 0x20\r
+.set SCSI_ATN__PORT, 12\r
+.set SCSI_ATN__PRT, CYREG_PRT12_PRT\r
+.set SCSI_ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_ATN__PS, CYREG_PRT12_PS\r
+.set SCSI_ATN__SHIFT, 5\r
+.set SCSI_ATN__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_ATN__SLW, CYREG_PRT12_SLW\r
+\r
/* SCSI_Out */\r
.set SCSI_Out__0__AG, CYREG_PRT4_AG\r
.set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX\r
.set SCSI_Out__SEL__SHIFT, 0\r
.set SCSI_Out__SEL__SLW, CYREG_PRT6_SLW\r
\r
+/* SCSI_RST */\r
+.set SCSI_RST__0__MASK, 0x40\r
+.set SCSI_RST__0__PC, CYREG_PRT6_PC6\r
+.set SCSI_RST__0__PORT, 6\r
+.set SCSI_RST__0__SHIFT, 6\r
+.set SCSI_RST__AG, CYREG_PRT6_AG\r
+.set SCSI_RST__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_RST__BIE, CYREG_PRT6_BIE\r
+.set SCSI_RST__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_RST__BYP, CYREG_PRT6_BYP\r
+.set SCSI_RST__CTL, CYREG_PRT6_CTL\r
+.set SCSI_RST__DM0, CYREG_PRT6_DM0\r
+.set SCSI_RST__DM1, CYREG_PRT6_DM1\r
+.set SCSI_RST__DM2, CYREG_PRT6_DM2\r
+.set SCSI_RST__DR, CYREG_PRT6_DR\r
+.set SCSI_RST__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_RST__INTSTAT, CYREG_PICU6_INTSTAT\r
+.set SCSI_RST__INT__MASK, 0x40\r
+.set SCSI_RST__INT__PC, CYREG_PRT6_PC6\r
+.set SCSI_RST__INT__PORT, 6\r
+.set SCSI_RST__INT__SHIFT, 6\r
+.set SCSI_RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_RST__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_RST__MASK, 0x40\r
+.set SCSI_RST__PORT, 6\r
+.set SCSI_RST__PRT, CYREG_PRT6_PRT\r
+.set SCSI_RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_RST__PS, CYREG_PRT6_PS\r
+.set SCSI_RST__SHIFT, 6\r
+.set SCSI_RST__SLW, CYREG_PRT6_SLW\r
+.set SCSI_RST__SNAP, CYREG_PICU6_SNAP\r
+\r
/* SCSI_ID */\r
.set SCSI_ID__0__MASK, 0x80\r
.set SCSI_ID__0__PC, CYREG_PRT5_PC7\r
.set SCSI_In__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
.set SCSI_In__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
.set SCSI_In__0__SLW, CYREG_PRT12_SLW\r
-.set SCSI_In__1__AG, CYREG_PRT12_AG\r
-.set SCSI_In__1__BIE, CYREG_PRT12_BIE\r
-.set SCSI_In__1__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set SCSI_In__1__BYP, CYREG_PRT12_BYP\r
-.set SCSI_In__1__DM0, CYREG_PRT12_DM0\r
-.set SCSI_In__1__DM1, CYREG_PRT12_DM1\r
-.set SCSI_In__1__DM2, CYREG_PRT12_DM2\r
-.set SCSI_In__1__DR, CYREG_PRT12_DR\r
-.set SCSI_In__1__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_In__1__MASK, 0x20\r
-.set SCSI_In__1__PC, CYREG_PRT12_PC5\r
-.set SCSI_In__1__PORT, 12\r
-.set SCSI_In__1__PRT, CYREG_PRT12_PRT\r
-.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set SCSI_In__1__PS, CYREG_PRT12_PS\r
-.set SCSI_In__1__SHIFT, 5\r
-.set SCSI_In__1__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set SCSI_In__1__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set SCSI_In__1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set SCSI_In__1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set SCSI_In__1__SLW, CYREG_PRT12_SLW\r
+.set SCSI_In__1__AG, CYREG_PRT6_AG\r
+.set SCSI_In__1__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_In__1__BIE, CYREG_PRT6_BIE\r
+.set SCSI_In__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_In__1__BYP, CYREG_PRT6_BYP\r
+.set SCSI_In__1__CTL, CYREG_PRT6_CTL\r
+.set SCSI_In__1__DM0, CYREG_PRT6_DM0\r
+.set SCSI_In__1__DM1, CYREG_PRT6_DM1\r
+.set SCSI_In__1__DM2, CYREG_PRT6_DM2\r
+.set SCSI_In__1__DR, CYREG_PRT6_DR\r
+.set SCSI_In__1__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_In__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_In__1__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_In__1__MASK, 0x10\r
+.set SCSI_In__1__PC, CYREG_PRT6_PC4\r
+.set SCSI_In__1__PORT, 6\r
+.set SCSI_In__1__PRT, CYREG_PRT6_PRT\r
+.set SCSI_In__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_In__1__PS, CYREG_PRT6_PS\r
+.set SCSI_In__1__SHIFT, 4\r
+.set SCSI_In__1__SLW, CYREG_PRT6_SLW\r
.set SCSI_In__2__AG, CYREG_PRT6_AG\r
.set SCSI_In__2__AMUX, CYREG_PRT6_AMUX\r
.set SCSI_In__2__BIE, CYREG_PRT6_BIE\r
.set SCSI_In__2__INP_DIS, CYREG_PRT6_INP_DIS\r
.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
.set SCSI_In__2__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In__2__MASK, 0x10\r
-.set SCSI_In__2__PC, CYREG_PRT6_PC4\r
+.set SCSI_In__2__MASK, 0x20\r
+.set SCSI_In__2__PC, CYREG_PRT6_PC5\r
.set SCSI_In__2__PORT, 6\r
.set SCSI_In__2__PRT, CYREG_PRT6_PRT\r
.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
.set SCSI_In__2__PS, CYREG_PRT6_PS\r
-.set SCSI_In__2__SHIFT, 4\r
+.set SCSI_In__2__SHIFT, 5\r
.set SCSI_In__2__SLW, CYREG_PRT6_SLW\r
.set SCSI_In__3__AG, CYREG_PRT6_AG\r
.set SCSI_In__3__AMUX, CYREG_PRT6_AMUX\r
.set SCSI_In__3__INP_DIS, CYREG_PRT6_INP_DIS\r
.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
.set SCSI_In__3__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In__3__MASK, 0x20\r
-.set SCSI_In__3__PC, CYREG_PRT6_PC5\r
+.set SCSI_In__3__MASK, 0x80\r
+.set SCSI_In__3__PC, CYREG_PRT6_PC7\r
.set SCSI_In__3__PORT, 6\r
.set SCSI_In__3__PRT, CYREG_PRT6_PRT\r
.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
.set SCSI_In__3__PS, CYREG_PRT6_PS\r
-.set SCSI_In__3__SHIFT, 5\r
+.set SCSI_In__3__SHIFT, 7\r
.set SCSI_In__3__SLW, CYREG_PRT6_SLW\r
-.set SCSI_In__4__AG, CYREG_PRT6_AG\r
-.set SCSI_In__4__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_In__4__BIE, CYREG_PRT6_BIE\r
-.set SCSI_In__4__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_In__4__BYP, CYREG_PRT6_BYP\r
-.set SCSI_In__4__CTL, CYREG_PRT6_CTL\r
-.set SCSI_In__4__DM0, CYREG_PRT6_DM0\r
-.set SCSI_In__4__DM1, CYREG_PRT6_DM1\r
-.set SCSI_In__4__DM2, CYREG_PRT6_DM2\r
-.set SCSI_In__4__DR, CYREG_PRT6_DR\r
-.set SCSI_In__4__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_In__4__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In__4__MASK, 0x40\r
-.set SCSI_In__4__PC, CYREG_PRT6_PC6\r
-.set SCSI_In__4__PORT, 6\r
-.set SCSI_In__4__PRT, CYREG_PRT6_PRT\r
-.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_In__4__PS, CYREG_PRT6_PS\r
-.set SCSI_In__4__SHIFT, 6\r
-.set SCSI_In__4__SLW, CYREG_PRT6_SLW\r
-.set SCSI_In__5__AG, CYREG_PRT6_AG\r
-.set SCSI_In__5__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_In__5__BIE, CYREG_PRT6_BIE\r
-.set SCSI_In__5__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_In__5__BYP, CYREG_PRT6_BYP\r
-.set SCSI_In__5__CTL, CYREG_PRT6_CTL\r
-.set SCSI_In__5__DM0, CYREG_PRT6_DM0\r
-.set SCSI_In__5__DM1, CYREG_PRT6_DM1\r
-.set SCSI_In__5__DM2, CYREG_PRT6_DM2\r
-.set SCSI_In__5__DR, CYREG_PRT6_DR\r
-.set SCSI_In__5__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_In__5__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_In__5__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In__5__MASK, 0x80\r
-.set SCSI_In__5__PC, CYREG_PRT6_PC7\r
-.set SCSI_In__5__PORT, 6\r
-.set SCSI_In__5__PRT, CYREG_PRT6_PRT\r
-.set SCSI_In__5__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_In__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_In__5__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_In__5__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_In__5__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_In__5__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_In__5__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_In__5__PS, CYREG_PRT6_PS\r
-.set SCSI_In__5__SHIFT, 7\r
-.set SCSI_In__5__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In__4__AG, CYREG_PRT5_AG\r
+.set SCSI_In__4__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__4__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__4__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__4__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__4__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__4__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__4__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__4__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__4__DR, CYREG_PRT5_DR\r
+.set SCSI_In__4__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__4__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__4__MASK, 0x01\r
+.set SCSI_In__4__PC, CYREG_PRT5_PC0\r
+.set SCSI_In__4__PORT, 5\r
+.set SCSI_In__4__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__4__PS, CYREG_PRT5_PS\r
+.set SCSI_In__4__SHIFT, 0\r
+.set SCSI_In__4__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__5__AG, CYREG_PRT5_AG\r
+.set SCSI_In__5__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__5__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__5__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__5__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__5__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__5__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__5__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__5__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__5__DR, CYREG_PRT5_DR\r
+.set SCSI_In__5__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__5__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__5__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__5__MASK, 0x02\r
+.set SCSI_In__5__PC, CYREG_PRT5_PC1\r
+.set SCSI_In__5__PORT, 5\r
+.set SCSI_In__5__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__5__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__5__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__5__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__5__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__5__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__5__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__5__PS, CYREG_PRT5_PS\r
+.set SCSI_In__5__SHIFT, 1\r
+.set SCSI_In__5__SLW, CYREG_PRT5_SLW\r
.set SCSI_In__6__AG, CYREG_PRT5_AG\r
.set SCSI_In__6__AMUX, CYREG_PRT5_AMUX\r
.set SCSI_In__6__BIE, CYREG_PRT5_BIE\r
.set SCSI_In__6__INP_DIS, CYREG_PRT5_INP_DIS\r
.set SCSI_In__6__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
.set SCSI_In__6__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__6__MASK, 0x01\r
-.set SCSI_In__6__PC, CYREG_PRT5_PC0\r
+.set SCSI_In__6__MASK, 0x04\r
+.set SCSI_In__6__PC, CYREG_PRT5_PC2\r
.set SCSI_In__6__PORT, 5\r
.set SCSI_In__6__PRT, CYREG_PRT5_PRT\r
.set SCSI_In__6__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
.set SCSI_In__6__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
.set SCSI_In__6__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
.set SCSI_In__6__PS, CYREG_PRT5_PS\r
-.set SCSI_In__6__SHIFT, 0\r
+.set SCSI_In__6__SHIFT, 2\r
.set SCSI_In__6__SLW, CYREG_PRT5_SLW\r
.set SCSI_In__7__AG, CYREG_PRT5_AG\r
.set SCSI_In__7__AMUX, CYREG_PRT5_AMUX\r
.set SCSI_In__7__INP_DIS, CYREG_PRT5_INP_DIS\r
.set SCSI_In__7__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
.set SCSI_In__7__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__7__MASK, 0x02\r
-.set SCSI_In__7__PC, CYREG_PRT5_PC1\r
+.set SCSI_In__7__MASK, 0x08\r
+.set SCSI_In__7__PC, CYREG_PRT5_PC3\r
.set SCSI_In__7__PORT, 5\r
.set SCSI_In__7__PRT, CYREG_PRT5_PRT\r
.set SCSI_In__7__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
.set SCSI_In__7__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
.set SCSI_In__7__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
.set SCSI_In__7__PS, CYREG_PRT5_PS\r
-.set SCSI_In__7__SHIFT, 1\r
+.set SCSI_In__7__SHIFT, 3\r
.set SCSI_In__7__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__8__AG, CYREG_PRT5_AG\r
-.set SCSI_In__8__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__8__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__8__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__8__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__8__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__8__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__8__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__8__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__8__DR, CYREG_PRT5_DR\r
-.set SCSI_In__8__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__8__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__8__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__8__MASK, 0x04\r
-.set SCSI_In__8__PC, CYREG_PRT5_PC2\r
-.set SCSI_In__8__PORT, 5\r
-.set SCSI_In__8__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__8__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__8__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__8__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__8__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__8__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__8__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__8__PS, CYREG_PRT5_PS\r
-.set SCSI_In__8__SHIFT, 2\r
-.set SCSI_In__8__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__9__AG, CYREG_PRT5_AG\r
-.set SCSI_In__9__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_In__9__BIE, CYREG_PRT5_BIE\r
-.set SCSI_In__9__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_In__9__BYP, CYREG_PRT5_BYP\r
-.set SCSI_In__9__CTL, CYREG_PRT5_CTL\r
-.set SCSI_In__9__DM0, CYREG_PRT5_DM0\r
-.set SCSI_In__9__DM1, CYREG_PRT5_DM1\r
-.set SCSI_In__9__DM2, CYREG_PRT5_DM2\r
-.set SCSI_In__9__DR, CYREG_PRT5_DR\r
-.set SCSI_In__9__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_In__9__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_In__9__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_In__9__MASK, 0x08\r
-.set SCSI_In__9__PC, CYREG_PRT5_PC3\r
-.set SCSI_In__9__PORT, 5\r
-.set SCSI_In__9__PRT, CYREG_PRT5_PRT\r
-.set SCSI_In__9__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_In__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_In__9__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_In__9__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_In__9__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_In__9__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_In__9__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_In__9__PS, CYREG_PRT5_PS\r
-.set SCSI_In__9__SHIFT, 3\r
-.set SCSI_In__9__SLW, CYREG_PRT5_SLW\r
.set SCSI_In__ACK__AG, CYREG_PRT6_AG\r
.set SCSI_In__ACK__AMUX, CYREG_PRT6_AMUX\r
.set SCSI_In__ACK__BIE, CYREG_PRT6_BIE\r
.set SCSI_In__ACK__PS, CYREG_PRT6_PS\r
.set SCSI_In__ACK__SHIFT, 5\r
.set SCSI_In__ACK__SLW, CYREG_PRT6_SLW\r
-.set SCSI_In__ATN__AG, CYREG_PRT12_AG\r
-.set SCSI_In__ATN__BIE, CYREG_PRT12_BIE\r
-.set SCSI_In__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set SCSI_In__ATN__BYP, CYREG_PRT12_BYP\r
-.set SCSI_In__ATN__DM0, CYREG_PRT12_DM0\r
-.set SCSI_In__ATN__DM1, CYREG_PRT12_DM1\r
-.set SCSI_In__ATN__DM2, CYREG_PRT12_DM2\r
-.set SCSI_In__ATN__DR, CYREG_PRT12_DR\r
-.set SCSI_In__ATN__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_In__ATN__MASK, 0x20\r
-.set SCSI_In__ATN__PC, CYREG_PRT12_PC5\r
-.set SCSI_In__ATN__PORT, 12\r
-.set SCSI_In__ATN__PRT, CYREG_PRT12_PRT\r
-.set SCSI_In__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set SCSI_In__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set SCSI_In__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set SCSI_In__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set SCSI_In__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set SCSI_In__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set SCSI_In__ATN__PS, CYREG_PRT12_PS\r
-.set SCSI_In__ATN__SHIFT, 5\r
-.set SCSI_In__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set SCSI_In__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set SCSI_In__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set SCSI_In__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set SCSI_In__ATN__SLW, CYREG_PRT12_SLW\r
.set SCSI_In__BSY__AG, CYREG_PRT6_AG\r
.set SCSI_In__BSY__AMUX, CYREG_PRT6_AMUX\r
.set SCSI_In__BSY__BIE, CYREG_PRT6_BIE\r
.set SCSI_In__REQ__PS, CYREG_PRT5_PS\r
.set SCSI_In__REQ__SHIFT, 2\r
.set SCSI_In__REQ__SLW, CYREG_PRT5_SLW\r
-.set SCSI_In__RST__AG, CYREG_PRT6_AG\r
-.set SCSI_In__RST__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_In__RST__BIE, CYREG_PRT6_BIE\r
-.set SCSI_In__RST__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_In__RST__BYP, CYREG_PRT6_BYP\r
-.set SCSI_In__RST__CTL, CYREG_PRT6_CTL\r
-.set SCSI_In__RST__DM0, CYREG_PRT6_DM0\r
-.set SCSI_In__RST__DM1, CYREG_PRT6_DM1\r
-.set SCSI_In__RST__DM2, CYREG_PRT6_DM2\r
-.set SCSI_In__RST__DR, CYREG_PRT6_DR\r
-.set SCSI_In__RST__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_In__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_In__RST__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_In__RST__MASK, 0x40\r
-.set SCSI_In__RST__PC, CYREG_PRT6_PC6\r
-.set SCSI_In__RST__PORT, 6\r
-.set SCSI_In__RST__PRT, CYREG_PRT6_PRT\r
-.set SCSI_In__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_In__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_In__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_In__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_In__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_In__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_In__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_In__RST__PS, CYREG_PRT6_PS\r
-.set SCSI_In__RST__SHIFT, 6\r
-.set SCSI_In__RST__SLW, CYREG_PRT6_SLW\r
.set SCSI_In__SEL__AG, CYREG_PRT5_AG\r
.set SCSI_In__SEL__AMUX, CYREG_PRT5_AMUX\r
.set SCSI_In__SEL__BIE, CYREG_PRT5_BIE\r
.set CYDEV_DEBUGGING_DPS_JTAG_5, 0\r
.set CYDEV_DEBUGGING_DPS_SWD, 2\r
.set CYDEV_DEBUGGING_ENABLE, 1\r
-.set CYDEV_DEBUGGING_REQXRES, 1\r
.set CYDEV_DEBUGGING_XRES, 0\r
.set CYDEV_DEBUG_ENABLE_MASK, 0x20\r
.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG\r
.set CYDEV_ECC_ENABLE, 0\r
.set CYDEV_HEAP_SIZE, 0x1000\r
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1\r
-.set CYDEV_INTR_RISING, 0x00000003\r
+.set CYDEV_INTR_RISING, 0x00000001\r
.set CYDEV_PROJ_TYPE, 0\r
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1\r
.set CYDEV_PROJ_TYPE_LOADABLE, 2\r
--- /dev/null
+#ifndef INCLUDED_CYFITTERIAR_INC\r
+#define INCLUDED_CYFITTERIAR_INC\r
+ INCLUDE cydeviceiar.inc\r
+ INCLUDE cydeviceiar_trm.inc\r
+\r
+/* SCSI_ATN_ISR */\r
+SCSI_ATN_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_ATN_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_ATN_ISR__INTC_MASK EQU 0x01\r
+SCSI_ATN_ISR__INTC_NUMBER EQU 0\r
+SCSI_ATN_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+SCSI_ATN_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_ATN_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_Out_DBx */\r
+SCSI_Out_DBx__0__MASK EQU 0x01\r
+SCSI_Out_DBx__0__PC EQU CYREG_PRT0_PC0\r
+SCSI_Out_DBx__0__PORT EQU 0\r
+SCSI_Out_DBx__0__SHIFT EQU 0\r
+SCSI_Out_DBx__1__MASK EQU 0x02\r
+SCSI_Out_DBx__1__PC EQU CYREG_PRT0_PC1\r
+SCSI_Out_DBx__1__PORT EQU 0\r
+SCSI_Out_DBx__1__SHIFT EQU 1\r
+SCSI_Out_DBx__2__MASK EQU 0x04\r
+SCSI_Out_DBx__2__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out_DBx__2__PORT EQU 0\r
+SCSI_Out_DBx__2__SHIFT EQU 2\r
+SCSI_Out_DBx__3__MASK EQU 0x08\r
+SCSI_Out_DBx__3__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out_DBx__3__PORT EQU 0\r
+SCSI_Out_DBx__3__SHIFT EQU 3\r
+SCSI_Out_DBx__4__MASK EQU 0x10\r
+SCSI_Out_DBx__4__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out_DBx__4__PORT EQU 0\r
+SCSI_Out_DBx__4__SHIFT EQU 4\r
+SCSI_Out_DBx__5__MASK EQU 0x20\r
+SCSI_Out_DBx__5__PC EQU CYREG_PRT0_PC5\r
+SCSI_Out_DBx__5__PORT EQU 0\r
+SCSI_Out_DBx__5__SHIFT EQU 5\r
+SCSI_Out_DBx__6__MASK EQU 0x40\r
+SCSI_Out_DBx__6__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out_DBx__6__PORT EQU 0\r
+SCSI_Out_DBx__6__SHIFT EQU 6\r
+SCSI_Out_DBx__7__MASK EQU 0x80\r
+SCSI_Out_DBx__7__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out_DBx__7__PORT EQU 0\r
+SCSI_Out_DBx__7__SHIFT EQU 7\r
+SCSI_Out_DBx__AG EQU CYREG_PRT0_AG\r
+SCSI_Out_DBx__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out_DBx__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out_DBx__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out_DBx__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out_DBx__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out_DBx__DB0__MASK EQU 0x01\r
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT0_PC0\r
+SCSI_Out_DBx__DB0__PORT EQU 0\r
+SCSI_Out_DBx__DB0__SHIFT EQU 0\r
+SCSI_Out_DBx__DB1__MASK EQU 0x02\r
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT0_PC1\r
+SCSI_Out_DBx__DB1__PORT EQU 0\r
+SCSI_Out_DBx__DB1__SHIFT EQU 1\r
+SCSI_Out_DBx__DB2__MASK EQU 0x04\r
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out_DBx__DB2__PORT EQU 0\r
+SCSI_Out_DBx__DB2__SHIFT EQU 2\r
+SCSI_Out_DBx__DB3__MASK EQU 0x08\r
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out_DBx__DB3__PORT EQU 0\r
+SCSI_Out_DBx__DB3__SHIFT EQU 3\r
+SCSI_Out_DBx__DB4__MASK EQU 0x10\r
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out_DBx__DB4__PORT EQU 0\r
+SCSI_Out_DBx__DB4__SHIFT EQU 4\r
+SCSI_Out_DBx__DB5__MASK EQU 0x20\r
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT0_PC5\r
+SCSI_Out_DBx__DB5__PORT EQU 0\r
+SCSI_Out_DBx__DB5__SHIFT EQU 5\r
+SCSI_Out_DBx__DB6__MASK EQU 0x40\r
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out_DBx__DB6__PORT EQU 0\r
+SCSI_Out_DBx__DB6__SHIFT EQU 6\r
+SCSI_Out_DBx__DB7__MASK EQU 0x80\r
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out_DBx__DB7__PORT EQU 0\r
+SCSI_Out_DBx__DB7__SHIFT EQU 7\r
+SCSI_Out_DBx__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out_DBx__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out_DBx__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out_DBx__DR EQU CYREG_PRT0_DR\r
+SCSI_Out_DBx__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out_DBx__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out_DBx__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out_DBx__MASK EQU 0xFF\r
+SCSI_Out_DBx__PORT EQU 0\r
+SCSI_Out_DBx__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out_DBx__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out_DBx__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out_DBx__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out_DBx__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out_DBx__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out_DBx__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out_DBx__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out_DBx__PS EQU CYREG_PRT0_PS\r
+SCSI_Out_DBx__SHIFT EQU 0\r
+SCSI_Out_DBx__SLW EQU CYREG_PRT0_SLW\r
+\r
+/* SCSI_RST_ISR */\r
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RST_ISR__INTC_MASK EQU 0x400\r
+SCSI_RST_ISR__INTC_NUMBER EQU 10\r
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10\r
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SDCard_BSPIM */\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
+SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
+SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
+SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
+SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
+SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
+SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+\r
+/* SCSI_In_DBx */\r
+SCSI_In_DBx__0__MASK EQU 0x01\r
+SCSI_In_DBx__0__PC EQU CYREG_PRT2_PC0\r
+SCSI_In_DBx__0__PORT EQU 2\r
+SCSI_In_DBx__0__SHIFT EQU 0\r
+SCSI_In_DBx__1__MASK EQU 0x02\r
+SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC1\r
+SCSI_In_DBx__1__PORT EQU 2\r
+SCSI_In_DBx__1__SHIFT EQU 1\r
+SCSI_In_DBx__2__MASK EQU 0x04\r
+SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC2\r
+SCSI_In_DBx__2__PORT EQU 2\r
+SCSI_In_DBx__2__SHIFT EQU 2\r
+SCSI_In_DBx__3__MASK EQU 0x08\r
+SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC3\r
+SCSI_In_DBx__3__PORT EQU 2\r
+SCSI_In_DBx__3__SHIFT EQU 3\r
+SCSI_In_DBx__4__MASK EQU 0x10\r
+SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__4__PORT EQU 2\r
+SCSI_In_DBx__4__SHIFT EQU 4\r
+SCSI_In_DBx__5__MASK EQU 0x20\r
+SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__5__PORT EQU 2\r
+SCSI_In_DBx__5__SHIFT EQU 5\r
+SCSI_In_DBx__6__MASK EQU 0x40\r
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC6\r
+SCSI_In_DBx__6__PORT EQU 2\r
+SCSI_In_DBx__6__SHIFT EQU 6\r
+SCSI_In_DBx__7__MASK EQU 0x80\r
+SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC7\r
+SCSI_In_DBx__7__PORT EQU 2\r
+SCSI_In_DBx__7__SHIFT EQU 7\r
+SCSI_In_DBx__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB0__MASK EQU 0x01\r
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT2_PC0\r
+SCSI_In_DBx__DB0__PORT EQU 2\r
+SCSI_In_DBx__DB0__SHIFT EQU 0\r
+SCSI_In_DBx__DB1__MASK EQU 0x02\r
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC1\r
+SCSI_In_DBx__DB1__PORT EQU 2\r
+SCSI_In_DBx__DB1__SHIFT EQU 1\r
+SCSI_In_DBx__DB2__MASK EQU 0x04\r
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC2\r
+SCSI_In_DBx__DB2__PORT EQU 2\r
+SCSI_In_DBx__DB2__SHIFT EQU 2\r
+SCSI_In_DBx__DB3__MASK EQU 0x08\r
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC3\r
+SCSI_In_DBx__DB3__PORT EQU 2\r
+SCSI_In_DBx__DB3__SHIFT EQU 3\r
+SCSI_In_DBx__DB4__MASK EQU 0x10\r
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__DB4__PORT EQU 2\r
+SCSI_In_DBx__DB4__SHIFT EQU 4\r
+SCSI_In_DBx__DB5__MASK EQU 0x20\r
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__DB5__PORT EQU 2\r
+SCSI_In_DBx__DB5__SHIFT EQU 5\r
+SCSI_In_DBx__DB6__MASK EQU 0x40\r
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC6\r
+SCSI_In_DBx__DB6__PORT EQU 2\r
+SCSI_In_DBx__DB6__SHIFT EQU 6\r
+SCSI_In_DBx__DB7__MASK EQU 0x80\r
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC7\r
+SCSI_In_DBx__DB7__PORT EQU 2\r
+SCSI_In_DBx__DB7__SHIFT EQU 7\r
+SCSI_In_DBx__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__MASK EQU 0xFF\r
+SCSI_In_DBx__PORT EQU 2\r
+SCSI_In_DBx__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__SHIFT EQU 0\r
+SCSI_In_DBx__SLW EQU CYREG_PRT2_SLW\r
+\r
+/* SD_Data_Clk */\r
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
+SD_Data_Clk__INDEX EQU 0x00\r
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
+\r
+/* SD_Init_Clk */\r
+SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
+SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
+SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
+SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
+SD_Init_Clk__INDEX EQU 0x01\r
+SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SD_Init_Clk__PM_ACT_MSK EQU 0x02\r
+SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SD_Init_Clk__PM_STBY_MSK EQU 0x02\r
+\r
+/* SD_Clk_Ctl */\r
+SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+\r
+/* PARITY_EN */\r
+PARITY_EN__0__MASK EQU 0x10\r
+PARITY_EN__0__PC EQU CYREG_PRT5_PC4\r
+PARITY_EN__0__PORT EQU 5\r
+PARITY_EN__0__SHIFT EQU 4\r
+PARITY_EN__AG EQU CYREG_PRT5_AG\r
+PARITY_EN__AMUX EQU CYREG_PRT5_AMUX\r
+PARITY_EN__BIE EQU CYREG_PRT5_BIE\r
+PARITY_EN__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+PARITY_EN__BYP EQU CYREG_PRT5_BYP\r
+PARITY_EN__CTL EQU CYREG_PRT5_CTL\r
+PARITY_EN__DM0 EQU CYREG_PRT5_DM0\r
+PARITY_EN__DM1 EQU CYREG_PRT5_DM1\r
+PARITY_EN__DM2 EQU CYREG_PRT5_DM2\r
+PARITY_EN__DR EQU CYREG_PRT5_DR\r
+PARITY_EN__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+PARITY_EN__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+PARITY_EN__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+PARITY_EN__MASK EQU 0x10\r
+PARITY_EN__PORT EQU 5\r
+PARITY_EN__PRT EQU CYREG_PRT5_PRT\r
+PARITY_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+PARITY_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+PARITY_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+PARITY_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+PARITY_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+PARITY_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+PARITY_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+PARITY_EN__PS EQU CYREG_PRT5_PS\r
+PARITY_EN__SHIFT EQU 4\r
+PARITY_EN__SLW EQU CYREG_PRT5_SLW\r
+\r
+/* SCSI_ATN */\r
+SCSI_ATN__0__MASK EQU 0x20\r
+SCSI_ATN__0__PC EQU CYREG_PRT12_PC5\r
+SCSI_ATN__0__PORT EQU 12\r
+SCSI_ATN__0__SHIFT EQU 5\r
+SCSI_ATN__AG EQU CYREG_PRT12_AG\r
+SCSI_ATN__BIE EQU CYREG_PRT12_BIE\r
+SCSI_ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_ATN__BYP EQU CYREG_PRT12_BYP\r
+SCSI_ATN__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_ATN__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_ATN__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_ATN__DR EQU CYREG_PRT12_DR\r
+SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_ATN__INT__MASK EQU 0x20\r
+SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5\r
+SCSI_ATN__INT__PORT EQU 12\r
+SCSI_ATN__INT__SHIFT EQU 5\r
+SCSI_ATN__MASK EQU 0x20\r
+SCSI_ATN__PORT EQU 12\r
+SCSI_ATN__PRT EQU CYREG_PRT12_PRT\r
+SCSI_ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_ATN__PS EQU CYREG_PRT12_PS\r
+SCSI_ATN__SHIFT EQU 5\r
+SCSI_ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_ATN__SLW EQU CYREG_PRT12_SLW\r
+\r
+/* SCSI_Out */\r
+SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__0__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__0__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__0__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__0__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__0__MASK EQU 0x04\r
+SCSI_Out__0__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__0__PORT EQU 4\r
+SCSI_Out__0__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__0__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__0__SHIFT EQU 2\r
+SCSI_Out__0__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__1__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__1__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__1__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__1__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__1__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__1__MASK EQU 0x08\r
+SCSI_Out__1__PC EQU CYREG_PRT4_PC3\r
+SCSI_Out__1__PORT EQU 4\r
+SCSI_Out__1__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__1__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__1__SHIFT EQU 3\r
+SCSI_Out__1__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__2__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__2__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__2__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__2__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__2__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__2__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__2__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__2__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__2__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__2__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__2__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__2__MASK EQU 0x10\r
+SCSI_Out__2__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out__2__PORT EQU 4\r
+SCSI_Out__2__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__2__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__2__SHIFT EQU 4\r
+SCSI_Out__2__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__3__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__3__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__3__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__3__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__3__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__3__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__3__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__3__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__3__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__3__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__3__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__3__MASK EQU 0x20\r
+SCSI_Out__3__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out__3__PORT EQU 4\r
+SCSI_Out__3__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__3__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__3__SHIFT EQU 5\r
+SCSI_Out__3__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__4__MASK EQU 0x40\r
+SCSI_Out__4__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out__4__PORT EQU 4\r
+SCSI_Out__4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__4__SHIFT EQU 6\r
+SCSI_Out__4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__5__MASK EQU 0x80\r
+SCSI_Out__5__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out__5__PORT EQU 4\r
+SCSI_Out__5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__5__SHIFT EQU 7\r
+SCSI_Out__5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__6__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__6__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__6__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__6__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__6__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__6__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__6__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__6__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__6__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__6__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__6__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__6__MASK EQU 0x01\r
+SCSI_Out__6__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out__6__PORT EQU 6\r
+SCSI_Out__6__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__6__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__6__SHIFT EQU 0\r
+SCSI_Out__6__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__7__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__7__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__7__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__7__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__7__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__7__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__7__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__7__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__7__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__7__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__7__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__7__MASK EQU 0x02\r
+SCSI_Out__7__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out__7__PORT EQU 6\r
+SCSI_Out__7__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__7__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__7__SHIFT EQU 1\r
+SCSI_Out__7__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__8__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__8__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__8__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__8__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__8__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__8__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__8__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__8__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__8__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__8__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__8__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__8__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__8__MASK EQU 0x04\r
+SCSI_Out__8__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out__8__PORT EQU 6\r
+SCSI_Out__8__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__8__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__8__SHIFT EQU 2\r
+SCSI_Out__8__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__9__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__9__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__9__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__9__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__9__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__9__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__9__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__9__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__9__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__9__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__9__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__9__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__9__MASK EQU 0x08\r
+SCSI_Out__9__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out__9__PORT EQU 6\r
+SCSI_Out__9__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__9__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__9__SHIFT EQU 3\r
+SCSI_Out__9__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__ACK__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__ACK__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__ACK__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__ACK__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__ACK__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__ACK__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__ACK__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__ACK__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__ACK__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__ACK__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__ACK__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__ACK__MASK EQU 0x20\r
+SCSI_Out__ACK__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out__ACK__PORT EQU 4\r
+SCSI_Out__ACK__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__ACK__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__ACK__SHIFT EQU 5\r
+SCSI_Out__ACK__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__ATN__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__ATN__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__ATN__MASK EQU 0x08\r
+SCSI_Out__ATN__PC EQU CYREG_PRT4_PC3\r
+SCSI_Out__ATN__PORT EQU 4\r
+SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__ATN__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__ATN__SHIFT EQU 3\r
+SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__BSY__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__BSY__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__BSY__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__BSY__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__BSY__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__BSY__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__BSY__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__BSY__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__BSY__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__BSY__MASK EQU 0x10\r
+SCSI_Out__BSY__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out__BSY__PORT EQU 4\r
+SCSI_Out__BSY__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__BSY__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__BSY__SHIFT EQU 4\r
+SCSI_Out__BSY__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__CD__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__CD__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__CD__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__CD__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__CD__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__CD__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__CD__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__CD__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__CD__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__CD__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__CD__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__CD__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__CD__MASK EQU 0x02\r
+SCSI_Out__CD__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out__CD__PORT EQU 6\r
+SCSI_Out__CD__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__CD__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__CD__SHIFT EQU 1\r
+SCSI_Out__CD__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__DBP__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__DBP__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__DBP__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__DBP__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__DBP__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__DBP__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__DBP__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__DBP__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__DBP__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__DBP__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__DBP__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__DBP__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__DBP__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__DBP__MASK EQU 0x04\r
+SCSI_Out__DBP__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__DBP__PORT EQU 4\r
+SCSI_Out__DBP__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__DBP__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__DBP__SHIFT EQU 2\r
+SCSI_Out__DBP__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__IO__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__IO__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__IO__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__IO__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__IO__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__IO__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__IO__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__IO__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__IO__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__IO__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__IO__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__IO__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__IO__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__IO__MASK EQU 0x08\r
+SCSI_Out__IO__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out__IO__PORT EQU 6\r
+SCSI_Out__IO__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__IO__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__IO__SHIFT EQU 3\r
+SCSI_Out__IO__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__MSG__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__MSG__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__MSG__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__MSG__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__MSG__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__MSG__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__MSG__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__MSG__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__MSG__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__MSG__MASK EQU 0x80\r
+SCSI_Out__MSG__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out__MSG__PORT EQU 4\r
+SCSI_Out__MSG__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__MSG__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__MSG__SHIFT EQU 7\r
+SCSI_Out__MSG__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__REQ__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__REQ__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__REQ__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__REQ__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__REQ__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__REQ__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__REQ__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__REQ__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__REQ__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__REQ__MASK EQU 0x04\r
+SCSI_Out__REQ__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out__REQ__PORT EQU 6\r
+SCSI_Out__REQ__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__REQ__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__REQ__SHIFT EQU 2\r
+SCSI_Out__REQ__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__RST__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__RST__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__RST__MASK EQU 0x40\r
+SCSI_Out__RST__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out__RST__PORT EQU 4\r
+SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__RST__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__RST__SHIFT EQU 6\r
+SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__SEL__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__SEL__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__SEL__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__SEL__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__SEL__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__SEL__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__SEL__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__SEL__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__SEL__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__SEL__MASK EQU 0x01\r
+SCSI_Out__SEL__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out__SEL__PORT EQU 6\r
+SCSI_Out__SEL__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__SEL__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__SEL__SHIFT EQU 0\r
+SCSI_Out__SEL__SLW EQU CYREG_PRT6_SLW\r
+\r
+/* SCSI_RST */\r
+SCSI_RST__0__MASK EQU 0x40\r
+SCSI_RST__0__PC EQU CYREG_PRT6_PC6\r
+SCSI_RST__0__PORT EQU 6\r
+SCSI_RST__0__SHIFT EQU 6\r
+SCSI_RST__AG EQU CYREG_PRT6_AG\r
+SCSI_RST__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_RST__BIE EQU CYREG_PRT6_BIE\r
+SCSI_RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_RST__BYP EQU CYREG_PRT6_BYP\r
+SCSI_RST__CTL EQU CYREG_PRT6_CTL\r
+SCSI_RST__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_RST__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_RST__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_RST__DR EQU CYREG_PRT6_DR\r
+SCSI_RST__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_RST__INTSTAT EQU CYREG_PICU6_INTSTAT\r
+SCSI_RST__INT__MASK EQU 0x40\r
+SCSI_RST__INT__PC EQU CYREG_PRT6_PC6\r
+SCSI_RST__INT__PORT EQU 6\r
+SCSI_RST__INT__SHIFT EQU 6\r
+SCSI_RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_RST__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_RST__MASK EQU 0x40\r
+SCSI_RST__PORT EQU 6\r
+SCSI_RST__PRT EQU CYREG_PRT6_PRT\r
+SCSI_RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_RST__PS EQU CYREG_PRT6_PS\r
+SCSI_RST__SHIFT EQU 6\r
+SCSI_RST__SLW EQU CYREG_PRT6_SLW\r
+SCSI_RST__SNAP EQU CYREG_PICU6_SNAP\r
+\r
+/* SCSI_ID */\r
+SCSI_ID__0__MASK EQU 0x80\r
+SCSI_ID__0__PC EQU CYREG_PRT5_PC7\r
+SCSI_ID__0__PORT EQU 5\r
+SCSI_ID__0__SHIFT EQU 7\r
+SCSI_ID__1__MASK EQU 0x40\r
+SCSI_ID__1__PC EQU CYREG_PRT5_PC6\r
+SCSI_ID__1__PORT EQU 5\r
+SCSI_ID__1__SHIFT EQU 6\r
+SCSI_ID__2__MASK EQU 0x20\r
+SCSI_ID__2__PC EQU CYREG_PRT5_PC5\r
+SCSI_ID__2__PORT EQU 5\r
+SCSI_ID__2__SHIFT EQU 5\r
+SCSI_ID__AG EQU CYREG_PRT5_AG\r
+SCSI_ID__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_ID__BIE EQU CYREG_PRT5_BIE\r
+SCSI_ID__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_ID__BYP EQU CYREG_PRT5_BYP\r
+SCSI_ID__CTL EQU CYREG_PRT5_CTL\r
+SCSI_ID__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_ID__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_ID__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_ID__DR EQU CYREG_PRT5_DR\r
+SCSI_ID__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_ID__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_ID__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_ID__PORT EQU 5\r
+SCSI_ID__PRT EQU CYREG_PRT5_PRT\r
+SCSI_ID__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_ID__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_ID__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_ID__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_ID__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_ID__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_ID__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_ID__PS EQU CYREG_PRT5_PS\r
+SCSI_ID__SLW EQU CYREG_PRT5_SLW\r
+\r
+/* SCSI_In */\r
+SCSI_In__0__AG EQU CYREG_PRT12_AG\r
+SCSI_In__0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In__0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In__0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In__0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In__0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In__0__DR EQU CYREG_PRT12_DR\r
+SCSI_In__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In__0__MASK EQU 0x10\r
+SCSI_In__0__PC EQU CYREG_PRT12_PC4\r
+SCSI_In__0__PORT EQU 12\r
+SCSI_In__0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In__0__PS EQU CYREG_PRT12_PS\r
+SCSI_In__0__SHIFT EQU 4\r
+SCSI_In__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In__0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In__1__AG EQU CYREG_PRT6_AG\r
+SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__1__DR EQU CYREG_PRT6_DR\r
+SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__1__MASK EQU 0x10\r
+SCSI_In__1__PC EQU CYREG_PRT6_PC4\r
+SCSI_In__1__PORT EQU 6\r
+SCSI_In__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__1__PS EQU CYREG_PRT6_PS\r
+SCSI_In__1__SHIFT EQU 4\r
+SCSI_In__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__2__AG EQU CYREG_PRT6_AG\r
+SCSI_In__2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__2__DR EQU CYREG_PRT6_DR\r
+SCSI_In__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__2__MASK EQU 0x20\r
+SCSI_In__2__PC EQU CYREG_PRT6_PC5\r
+SCSI_In__2__PORT EQU 6\r
+SCSI_In__2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__2__PS EQU CYREG_PRT6_PS\r
+SCSI_In__2__SHIFT EQU 5\r
+SCSI_In__2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__3__AG EQU CYREG_PRT6_AG\r
+SCSI_In__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__3__DR EQU CYREG_PRT6_DR\r
+SCSI_In__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__3__MASK EQU 0x80\r
+SCSI_In__3__PC EQU CYREG_PRT6_PC7\r
+SCSI_In__3__PORT EQU 6\r
+SCSI_In__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__3__PS EQU CYREG_PRT6_PS\r
+SCSI_In__3__SHIFT EQU 7\r
+SCSI_In__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__4__AG EQU CYREG_PRT5_AG\r
+SCSI_In__4__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__4__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__4__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__4__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__4__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__4__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__4__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__4__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__4__DR EQU CYREG_PRT5_DR\r
+SCSI_In__4__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__4__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__4__MASK EQU 0x01\r
+SCSI_In__4__PC EQU CYREG_PRT5_PC0\r
+SCSI_In__4__PORT EQU 5\r
+SCSI_In__4__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__4__PS EQU CYREG_PRT5_PS\r
+SCSI_In__4__SHIFT EQU 0\r
+SCSI_In__4__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__5__AG EQU CYREG_PRT5_AG\r
+SCSI_In__5__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__5__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__5__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__5__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__5__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__5__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__5__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__5__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__5__DR EQU CYREG_PRT5_DR\r
+SCSI_In__5__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__5__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__5__MASK EQU 0x02\r
+SCSI_In__5__PC EQU CYREG_PRT5_PC1\r
+SCSI_In__5__PORT EQU 5\r
+SCSI_In__5__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__5__PS EQU CYREG_PRT5_PS\r
+SCSI_In__5__SHIFT EQU 1\r
+SCSI_In__5__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__6__AG EQU CYREG_PRT5_AG\r
+SCSI_In__6__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__6__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__6__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__6__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__6__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__6__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__6__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__6__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__6__DR EQU CYREG_PRT5_DR\r
+SCSI_In__6__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__6__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__6__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__6__MASK EQU 0x04\r
+SCSI_In__6__PC EQU CYREG_PRT5_PC2\r
+SCSI_In__6__PORT EQU 5\r
+SCSI_In__6__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__6__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__6__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__6__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__6__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__6__PS EQU CYREG_PRT5_PS\r
+SCSI_In__6__SHIFT EQU 2\r
+SCSI_In__6__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__7__AG EQU CYREG_PRT5_AG\r
+SCSI_In__7__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__7__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__7__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__7__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__7__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__7__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__7__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__7__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__7__DR EQU CYREG_PRT5_DR\r
+SCSI_In__7__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__7__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__7__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__7__MASK EQU 0x08\r
+SCSI_In__7__PC EQU CYREG_PRT5_PC3\r
+SCSI_In__7__PORT EQU 5\r
+SCSI_In__7__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__7__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__7__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__7__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__7__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__7__PS EQU CYREG_PRT5_PS\r
+SCSI_In__7__SHIFT EQU 3\r
+SCSI_In__7__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__ACK__AG EQU CYREG_PRT6_AG\r
+SCSI_In__ACK__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__ACK__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__ACK__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__ACK__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__ACK__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__ACK__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__ACK__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__ACK__DR EQU CYREG_PRT6_DR\r
+SCSI_In__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__ACK__MASK EQU 0x20\r
+SCSI_In__ACK__PC EQU CYREG_PRT6_PC5\r
+SCSI_In__ACK__PORT EQU 6\r
+SCSI_In__ACK__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__ACK__PS EQU CYREG_PRT6_PS\r
+SCSI_In__ACK__SHIFT EQU 5\r
+SCSI_In__ACK__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__BSY__AG EQU CYREG_PRT6_AG\r
+SCSI_In__BSY__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__BSY__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__BSY__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__BSY__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__BSY__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__BSY__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__BSY__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__BSY__DR EQU CYREG_PRT6_DR\r
+SCSI_In__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__BSY__MASK EQU 0x10\r
+SCSI_In__BSY__PC EQU CYREG_PRT6_PC4\r
+SCSI_In__BSY__PORT EQU 6\r
+SCSI_In__BSY__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__BSY__PS EQU CYREG_PRT6_PS\r
+SCSI_In__BSY__SHIFT EQU 4\r
+SCSI_In__BSY__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__CD__AG EQU CYREG_PRT5_AG\r
+SCSI_In__CD__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__CD__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__CD__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__CD__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__CD__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__CD__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__CD__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__CD__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__CD__DR EQU CYREG_PRT5_DR\r
+SCSI_In__CD__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__CD__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__CD__MASK EQU 0x02\r
+SCSI_In__CD__PC EQU CYREG_PRT5_PC1\r
+SCSI_In__CD__PORT EQU 5\r
+SCSI_In__CD__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__CD__PS EQU CYREG_PRT5_PS\r
+SCSI_In__CD__SHIFT EQU 1\r
+SCSI_In__CD__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__DBP__AG EQU CYREG_PRT12_AG\r
+SCSI_In__DBP__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In__DBP__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In__DBP__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In__DBP__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In__DBP__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In__DBP__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In__DBP__DR EQU CYREG_PRT12_DR\r
+SCSI_In__DBP__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In__DBP__MASK EQU 0x10\r
+SCSI_In__DBP__PC EQU CYREG_PRT12_PC4\r
+SCSI_In__DBP__PORT EQU 12\r
+SCSI_In__DBP__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In__DBP__PS EQU CYREG_PRT12_PS\r
+SCSI_In__DBP__SHIFT EQU 4\r
+SCSI_In__DBP__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In__DBP__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In__DBP__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In__DBP__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In__DBP__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In__IO__AG EQU CYREG_PRT5_AG\r
+SCSI_In__IO__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__IO__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__IO__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__IO__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__IO__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__IO__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__IO__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__IO__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__IO__DR EQU CYREG_PRT5_DR\r
+SCSI_In__IO__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__IO__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__IO__MASK EQU 0x08\r
+SCSI_In__IO__PC EQU CYREG_PRT5_PC3\r
+SCSI_In__IO__PORT EQU 5\r
+SCSI_In__IO__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__IO__PS EQU CYREG_PRT5_PS\r
+SCSI_In__IO__SHIFT EQU 3\r
+SCSI_In__IO__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__MSG__AG EQU CYREG_PRT6_AG\r
+SCSI_In__MSG__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__MSG__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__MSG__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__MSG__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__MSG__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__MSG__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__MSG__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__MSG__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__MSG__DR EQU CYREG_PRT6_DR\r
+SCSI_In__MSG__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__MSG__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__MSG__MASK EQU 0x80\r
+SCSI_In__MSG__PC EQU CYREG_PRT6_PC7\r
+SCSI_In__MSG__PORT EQU 6\r
+SCSI_In__MSG__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__MSG__PS EQU CYREG_PRT6_PS\r
+SCSI_In__MSG__SHIFT EQU 7\r
+SCSI_In__MSG__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__REQ__AG EQU CYREG_PRT5_AG\r
+SCSI_In__REQ__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__REQ__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__REQ__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__REQ__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__REQ__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__REQ__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__REQ__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__REQ__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__REQ__DR EQU CYREG_PRT5_DR\r
+SCSI_In__REQ__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__REQ__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__REQ__MASK EQU 0x04\r
+SCSI_In__REQ__PC EQU CYREG_PRT5_PC2\r
+SCSI_In__REQ__PORT EQU 5\r
+SCSI_In__REQ__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__REQ__PS EQU CYREG_PRT5_PS\r
+SCSI_In__REQ__SHIFT EQU 2\r
+SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__SEL__AG EQU CYREG_PRT5_AG\r
+SCSI_In__SEL__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__SEL__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__SEL__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__SEL__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__SEL__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__SEL__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__SEL__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__SEL__DR EQU CYREG_PRT5_DR\r
+SCSI_In__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__SEL__MASK EQU 0x01\r
+SCSI_In__SEL__PC EQU CYREG_PRT5_PC0\r
+SCSI_In__SEL__PORT EQU 5\r
+SCSI_In__SEL__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__SEL__PS EQU CYREG_PRT5_PS\r
+SCSI_In__SEL__SHIFT EQU 0\r
+SCSI_In__SEL__SLW EQU CYREG_PRT5_SLW\r
+\r
+/* SD_DAT1 */\r
+SD_DAT1__0__MASK EQU 0x20\r
+SD_DAT1__0__PC EQU CYREG_PRT3_PC5\r
+SD_DAT1__0__PORT EQU 3\r
+SD_DAT1__0__SHIFT EQU 5\r
+SD_DAT1__AG EQU CYREG_PRT3_AG\r
+SD_DAT1__AMUX EQU CYREG_PRT3_AMUX\r
+SD_DAT1__BIE EQU CYREG_PRT3_BIE\r
+SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_DAT1__BYP EQU CYREG_PRT3_BYP\r
+SD_DAT1__CTL EQU CYREG_PRT3_CTL\r
+SD_DAT1__DM0 EQU CYREG_PRT3_DM0\r
+SD_DAT1__DM1 EQU CYREG_PRT3_DM1\r
+SD_DAT1__DM2 EQU CYREG_PRT3_DM2\r
+SD_DAT1__DR EQU CYREG_PRT3_DR\r
+SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_DAT1__MASK EQU 0x20\r
+SD_DAT1__PORT EQU 3\r
+SD_DAT1__PRT EQU CYREG_PRT3_PRT\r
+SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_DAT1__PS EQU CYREG_PRT3_PS\r
+SD_DAT1__SHIFT EQU 5\r
+SD_DAT1__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_DAT2 */\r
+SD_DAT2__0__MASK EQU 0x01\r
+SD_DAT2__0__PC EQU CYREG_PRT3_PC0\r
+SD_DAT2__0__PORT EQU 3\r
+SD_DAT2__0__SHIFT EQU 0\r
+SD_DAT2__AG EQU CYREG_PRT3_AG\r
+SD_DAT2__AMUX EQU CYREG_PRT3_AMUX\r
+SD_DAT2__BIE EQU CYREG_PRT3_BIE\r
+SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_DAT2__BYP EQU CYREG_PRT3_BYP\r
+SD_DAT2__CTL EQU CYREG_PRT3_CTL\r
+SD_DAT2__DM0 EQU CYREG_PRT3_DM0\r
+SD_DAT2__DM1 EQU CYREG_PRT3_DM1\r
+SD_DAT2__DM2 EQU CYREG_PRT3_DM2\r
+SD_DAT2__DR EQU CYREG_PRT3_DR\r
+SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_DAT2__MASK EQU 0x01\r
+SD_DAT2__PORT EQU 3\r
+SD_DAT2__PRT EQU CYREG_PRT3_PRT\r
+SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_DAT2__PS EQU CYREG_PRT3_PS\r
+SD_DAT2__SHIFT EQU 0\r
+SD_DAT2__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_MISO */\r
+SD_MISO__0__MASK EQU 0x10\r
+SD_MISO__0__PC EQU CYREG_PRT3_PC4\r
+SD_MISO__0__PORT EQU 3\r
+SD_MISO__0__SHIFT EQU 4\r
+SD_MISO__AG EQU CYREG_PRT3_AG\r
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MISO__BIE EQU CYREG_PRT3_BIE\r
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MISO__BYP EQU CYREG_PRT3_BYP\r
+SD_MISO__CTL EQU CYREG_PRT3_CTL\r
+SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
+SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
+SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
+SD_MISO__DR EQU CYREG_PRT3_DR\r
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MISO__MASK EQU 0x10\r
+SD_MISO__PORT EQU 3\r
+SD_MISO__PRT EQU CYREG_PRT3_PRT\r
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MISO__PS EQU CYREG_PRT3_PS\r
+SD_MISO__SHIFT EQU 4\r
+SD_MISO__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_MOSI */\r
+SD_MOSI__0__MASK EQU 0x04\r
+SD_MOSI__0__PC EQU CYREG_PRT3_PC2\r
+SD_MOSI__0__PORT EQU 3\r
+SD_MOSI__0__SHIFT EQU 2\r
+SD_MOSI__AG EQU CYREG_PRT3_AG\r
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
+SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
+SD_MOSI__DR EQU CYREG_PRT3_DR\r
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MOSI__MASK EQU 0x04\r
+SD_MOSI__PORT EQU 3\r
+SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MOSI__PS EQU CYREG_PRT3_PS\r
+SD_MOSI__SHIFT EQU 2\r
+SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_SCK */\r
+SD_SCK__0__MASK EQU 0x08\r
+SD_SCK__0__PC EQU CYREG_PRT3_PC3\r
+SD_SCK__0__PORT EQU 3\r
+SD_SCK__0__SHIFT EQU 3\r
+SD_SCK__AG EQU CYREG_PRT3_AG\r
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
+SD_SCK__BIE EQU CYREG_PRT3_BIE\r
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_SCK__BYP EQU CYREG_PRT3_BYP\r
+SD_SCK__CTL EQU CYREG_PRT3_CTL\r
+SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
+SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
+SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
+SD_SCK__DR EQU CYREG_PRT3_DR\r
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_SCK__MASK EQU 0x08\r
+SD_SCK__PORT EQU 3\r
+SD_SCK__PRT EQU CYREG_PRT3_PRT\r
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_SCK__PS EQU CYREG_PRT3_PS\r
+SD_SCK__SHIFT EQU 3\r
+SD_SCK__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_CD */\r
+SD_CD__0__MASK EQU 0x40\r
+SD_CD__0__PC EQU CYREG_PRT3_PC6\r
+SD_CD__0__PORT EQU 3\r
+SD_CD__0__SHIFT EQU 6\r
+SD_CD__AG EQU CYREG_PRT3_AG\r
+SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CD__BIE EQU CYREG_PRT3_BIE\r
+SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CD__BYP EQU CYREG_PRT3_BYP\r
+SD_CD__CTL EQU CYREG_PRT3_CTL\r
+SD_CD__DM0 EQU CYREG_PRT3_DM0\r
+SD_CD__DM1 EQU CYREG_PRT3_DM1\r
+SD_CD__DM2 EQU CYREG_PRT3_DM2\r
+SD_CD__DR EQU CYREG_PRT3_DR\r
+SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CD__MASK EQU 0x40\r
+SD_CD__PORT EQU 3\r
+SD_CD__PRT EQU CYREG_PRT3_PRT\r
+SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CD__PS EQU CYREG_PRT3_PS\r
+SD_CD__SHIFT EQU 6\r
+SD_CD__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_CS */\r
+SD_CS__0__MASK EQU 0x02\r
+SD_CS__0__PC EQU CYREG_PRT3_PC1\r
+SD_CS__0__PORT EQU 3\r
+SD_CS__0__SHIFT EQU 1\r
+SD_CS__AG EQU CYREG_PRT3_AG\r
+SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CS__BIE EQU CYREG_PRT3_BIE\r
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CS__BYP EQU CYREG_PRT3_BYP\r
+SD_CS__CTL EQU CYREG_PRT3_CTL\r
+SD_CS__DM0 EQU CYREG_PRT3_DM0\r
+SD_CS__DM1 EQU CYREG_PRT3_DM1\r
+SD_CS__DM2 EQU CYREG_PRT3_DM2\r
+SD_CS__DR EQU CYREG_PRT3_DR\r
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CS__MASK EQU 0x02\r
+SD_CS__PORT EQU 3\r
+SD_CS__PRT EQU CYREG_PRT3_PRT\r
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CS__PS EQU CYREG_PRT3_PS\r
+SD_CS__SHIFT EQU 1\r
+SD_CS__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_WP */\r
+SD_WP__0__MASK EQU 0x80\r
+SD_WP__0__PC EQU CYREG_PRT3_PC7\r
+SD_WP__0__PORT EQU 3\r
+SD_WP__0__SHIFT EQU 7\r
+SD_WP__AG EQU CYREG_PRT3_AG\r
+SD_WP__AMUX EQU CYREG_PRT3_AMUX\r
+SD_WP__BIE EQU CYREG_PRT3_BIE\r
+SD_WP__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_WP__BYP EQU CYREG_PRT3_BYP\r
+SD_WP__CTL EQU CYREG_PRT3_CTL\r
+SD_WP__DM0 EQU CYREG_PRT3_DM0\r
+SD_WP__DM1 EQU CYREG_PRT3_DM1\r
+SD_WP__DM2 EQU CYREG_PRT3_DM2\r
+SD_WP__DR EQU CYREG_PRT3_DR\r
+SD_WP__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_WP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_WP__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_WP__MASK EQU 0x80\r
+SD_WP__PORT EQU 3\r
+SD_WP__PRT EQU CYREG_PRT3_PRT\r
+SD_WP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_WP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_WP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_WP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_WP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_WP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_WP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_WP__PS EQU CYREG_PRT3_PS\r
+SD_WP__SHIFT EQU 7\r
+SD_WP__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* LED1 */\r
+LED1__0__MASK EQU 0x08\r
+LED1__0__PC EQU CYREG_PRT12_PC3\r
+LED1__0__PORT EQU 12\r
+LED1__0__SHIFT EQU 3\r
+LED1__AG EQU CYREG_PRT12_AG\r
+LED1__BIE EQU CYREG_PRT12_BIE\r
+LED1__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+LED1__BYP EQU CYREG_PRT12_BYP\r
+LED1__DM0 EQU CYREG_PRT12_DM0\r
+LED1__DM1 EQU CYREG_PRT12_DM1\r
+LED1__DM2 EQU CYREG_PRT12_DM2\r
+LED1__DR EQU CYREG_PRT12_DR\r
+LED1__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+LED1__MASK EQU 0x08\r
+LED1__PORT EQU 12\r
+LED1__PRT EQU CYREG_PRT12_PRT\r
+LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+LED1__PS EQU CYREG_PRT12_PS\r
+LED1__SHIFT EQU 3\r
+LED1__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+LED1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+LED1__SLW EQU CYREG_PRT12_SLW\r
+\r
+/* Miscellaneous */\r
+/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */\r
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6\r
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0\r
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0\r
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1\r
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
+CYDEV_CHIP_MEMBER_5B EQU 4\r
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
+CYDEV_CHIP_DIE_PSOC5LP EQU 4\r
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP\r
+BCLK__BUS_CLK__HZ EQU 63000000\r
+BCLK__BUS_CLK__KHZ EQU 63000\r
+BCLK__BUS_CLK__MHZ EQU 63\r
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT\r
+CYDEV_CHIP_DIE_LEOPARD EQU 1\r
+CYDEV_CHIP_DIE_PANTHER EQU 3\r
+CYDEV_CHIP_DIE_PSOC4A EQU 2\r
+CYDEV_CHIP_DIE_UNKNOWN EQU 0\r
+CYDEV_CHIP_FAMILY_PSOC3 EQU 1\r
+CYDEV_CHIP_FAMILY_PSOC4 EQU 2\r
+CYDEV_CHIP_FAMILY_UNKNOWN EQU 0\r
+CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
+CYDEV_CHIP_JTAG_ID EQU 0x2E12F069\r
+CYDEV_CHIP_MEMBER_3A EQU 1\r
+CYDEV_CHIP_MEMBER_4A EQU 2\r
+CYDEV_CHIP_MEMBER_5A EQU 3\r
+CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
+CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
+CYDEV_CHIP_REVISION_3A_ES1 EQU 0\r
+CYDEV_CHIP_REVISION_3A_ES2 EQU 1\r
+CYDEV_CHIP_REVISION_3A_ES3 EQU 3\r
+CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3\r
+CYDEV_CHIP_REVISION_4A_ES0 EQU 17\r
+CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17\r
+CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
+CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
+CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
+CYDEV_CHIP_REVISION_5B_ES0 EQU 0\r
+CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION\r
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION\r
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0\r
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1\r
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3\r
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3\r
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0\r
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1\r
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1\r
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17\r
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17\r
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0\r
+CYDEV_CONFIGURATION_COMPRESSED EQU 1\r
+CYDEV_CONFIGURATION_DMA EQU 0\r
+CYDEV_CONFIGURATION_ECC EQU 1\r
+CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED\r
+CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED\r
+CYDEV_CONFIGURATION_MODE_DMA EQU 2\r
+CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1\r
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1\r
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2\r
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV\r
+CYDEV_DEBUGGING_DPS_Disable EQU 3\r
+CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1\r
+CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0\r
+CYDEV_DEBUGGING_DPS_SWD EQU 2\r
+CYDEV_DEBUGGING_ENABLE EQU 1\r
+CYDEV_DEBUGGING_XRES EQU 0\r
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20\r
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG\r
+CYDEV_DMA_CHANNELS_AVAILABLE EQU 24\r
+CYDEV_ECC_ENABLE EQU 0\r
+CYDEV_HEAP_SIZE EQU 0x1000\r
+CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
+CYDEV_INTR_RISING EQU 0x00000001\r
+CYDEV_PROJ_TYPE EQU 0\r
+CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
+CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
+CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3\r
+CYDEV_PROJ_TYPE_STANDARD EQU 0\r
+CYDEV_PROTECTION_ENABLE EQU 0\r
+CYDEV_STACK_SIZE EQU 0x4000\r
+CYDEV_USE_BUNDLED_CMSIS EQU 1\r
+CYDEV_VARIABLE_VDDA EQU 0\r
+CYDEV_VDDA_MV EQU 5000\r
+CYDEV_VDDD_MV EQU 5000\r
+CYDEV_VDDIO0_MV EQU 5000\r
+CYDEV_VDDIO1_MV EQU 5000\r
+CYDEV_VDDIO2_MV EQU 5000\r
+CYDEV_VDDIO3_MV EQU 3300\r
+CYDEV_VIO0 EQU 5\r
+CYDEV_VIO0_MV EQU 5000\r
+CYDEV_VIO1 EQU 5\r
+CYDEV_VIO1_MV EQU 5000\r
+CYDEV_VIO2 EQU 5\r
+CYDEV_VIO2_MV EQU 5000\r
+CYDEV_VIO3_MV EQU 3300\r
+DMA_CHANNELS_USED__MASK0 EQU 0x00000000\r
+CYDEV_BOOTLOADER_ENABLE EQU 0\r
+\r
+#endif /* INCLUDED_CYFITTERIAR_INC */\r
GET cydevicerv.inc\r
GET cydevicerv_trm.inc\r
\r
-; SDCard_RxInternalInterrupt\r
-SDCard_RxInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SDCard_RxInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SDCard_RxInternalInterrupt__INTC_MASK EQU 0x01\r
-SDCard_RxInternalInterrupt__INTC_NUMBER EQU 0\r
-SDCard_RxInternalInterrupt__INTC_PRIOR_NUM EQU 7\r
-SDCard_RxInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
-SDCard_RxInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SDCard_RxInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SDCard_TxInternalInterrupt\r
-SDCard_TxInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SDCard_TxInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SDCard_TxInternalInterrupt__INTC_MASK EQU 0x02\r
-SDCard_TxInternalInterrupt__INTC_NUMBER EQU 1\r
-SDCard_TxInternalInterrupt__INTC_PRIOR_NUM EQU 7\r
-SDCard_TxInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
-SDCard_TxInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SDCard_TxInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+; SCSI_ATN_ISR\r
+SCSI_ATN_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_ATN_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_ATN_ISR__INTC_MASK EQU 0x01\r
+SCSI_ATN_ISR__INTC_NUMBER EQU 0\r
+SCSI_ATN_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+SCSI_ATN_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_ATN_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; SCSI_Out_DBx\r
SCSI_Out_DBx__0__MASK EQU 0x01\r
SCSI_Out_DBx__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
SCSI_Out_DBx__BYP EQU CYREG_PRT0_BYP\r
SCSI_Out_DBx__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out_DBx__DB0__MASK EQU 0x01\r
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT0_PC0\r
+SCSI_Out_DBx__DB0__PORT EQU 0\r
+SCSI_Out_DBx__DB0__SHIFT EQU 0\r
+SCSI_Out_DBx__DB1__MASK EQU 0x02\r
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT0_PC1\r
+SCSI_Out_DBx__DB1__PORT EQU 0\r
+SCSI_Out_DBx__DB1__SHIFT EQU 1\r
+SCSI_Out_DBx__DB2__MASK EQU 0x04\r
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out_DBx__DB2__PORT EQU 0\r
+SCSI_Out_DBx__DB2__SHIFT EQU 2\r
+SCSI_Out_DBx__DB3__MASK EQU 0x08\r
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out_DBx__DB3__PORT EQU 0\r
+SCSI_Out_DBx__DB3__SHIFT EQU 3\r
+SCSI_Out_DBx__DB4__MASK EQU 0x10\r
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out_DBx__DB4__PORT EQU 0\r
+SCSI_Out_DBx__DB4__SHIFT EQU 4\r
+SCSI_Out_DBx__DB5__MASK EQU 0x20\r
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT0_PC5\r
+SCSI_Out_DBx__DB5__PORT EQU 0\r
+SCSI_Out_DBx__DB5__SHIFT EQU 5\r
+SCSI_Out_DBx__DB6__MASK EQU 0x40\r
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out_DBx__DB6__PORT EQU 0\r
+SCSI_Out_DBx__DB6__SHIFT EQU 6\r
+SCSI_Out_DBx__DB7__MASK EQU 0x80\r
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out_DBx__DB7__PORT EQU 0\r
+SCSI_Out_DBx__DB7__SHIFT EQU 7\r
SCSI_Out_DBx__DM0 EQU CYREG_PRT0_DM0\r
SCSI_Out_DBx__DM1 EQU CYREG_PRT0_DM1\r
SCSI_Out_DBx__DM2 EQU CYREG_PRT0_DM2\r
SCSI_Out_DBx__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
SCSI_Out_DBx__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
SCSI_Out_DBx__PS EQU CYREG_PRT0_PS\r
-SCSI_Out_DBx__SCSI_Out_DB0__MASK EQU 0x01\r
-SCSI_Out_DBx__SCSI_Out_DB0__PC EQU CYREG_PRT0_PC0\r
-SCSI_Out_DBx__SCSI_Out_DB0__PORT EQU 0\r
-SCSI_Out_DBx__SCSI_Out_DB0__SHIFT EQU 0\r
-SCSI_Out_DBx__SCSI_Out_DB1__MASK EQU 0x02\r
-SCSI_Out_DBx__SCSI_Out_DB1__PC EQU CYREG_PRT0_PC1\r
-SCSI_Out_DBx__SCSI_Out_DB1__PORT EQU 0\r
-SCSI_Out_DBx__SCSI_Out_DB1__SHIFT EQU 1\r
-SCSI_Out_DBx__SCSI_Out_DB2__MASK EQU 0x04\r
-SCSI_Out_DBx__SCSI_Out_DB2__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out_DBx__SCSI_Out_DB2__PORT EQU 0\r
-SCSI_Out_DBx__SCSI_Out_DB2__SHIFT EQU 2\r
-SCSI_Out_DBx__SCSI_Out_DB3__MASK EQU 0x08\r
-SCSI_Out_DBx__SCSI_Out_DB3__PC EQU CYREG_PRT0_PC3\r
-SCSI_Out_DBx__SCSI_Out_DB3__PORT EQU 0\r
-SCSI_Out_DBx__SCSI_Out_DB3__SHIFT EQU 3\r
-SCSI_Out_DBx__SCSI_Out_DB4__MASK EQU 0x10\r
-SCSI_Out_DBx__SCSI_Out_DB4__PC EQU CYREG_PRT0_PC4\r
-SCSI_Out_DBx__SCSI_Out_DB4__PORT EQU 0\r
-SCSI_Out_DBx__SCSI_Out_DB4__SHIFT EQU 4\r
-SCSI_Out_DBx__SCSI_Out_DB5__MASK EQU 0x20\r
-SCSI_Out_DBx__SCSI_Out_DB5__PC EQU CYREG_PRT0_PC5\r
-SCSI_Out_DBx__SCSI_Out_DB5__PORT EQU 0\r
-SCSI_Out_DBx__SCSI_Out_DB5__SHIFT EQU 5\r
-SCSI_Out_DBx__SCSI_Out_DB6__MASK EQU 0x40\r
-SCSI_Out_DBx__SCSI_Out_DB6__PC EQU CYREG_PRT0_PC6\r
-SCSI_Out_DBx__SCSI_Out_DB6__PORT EQU 0\r
-SCSI_Out_DBx__SCSI_Out_DB6__SHIFT EQU 6\r
-SCSI_Out_DBx__SCSI_Out_DB7__MASK EQU 0x80\r
-SCSI_Out_DBx__SCSI_Out_DB7__PC EQU CYREG_PRT0_PC7\r
-SCSI_Out_DBx__SCSI_Out_DB7__PORT EQU 0\r
-SCSI_Out_DBx__SCSI_Out_DB7__SHIFT EQU 7\r
SCSI_Out_DBx__SHIFT EQU 0\r
SCSI_Out_DBx__SLW EQU CYREG_PRT0_SLW\r
\r
+; SCSI_RST_ISR\r
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RST_ISR__INTC_MASK EQU 0x400\r
+SCSI_RST_ISR__INTC_NUMBER EQU 10\r
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10\r
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB07_08_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB07_08_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB07_08_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB07_08_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB07_08_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB07_08_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB07_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB07_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB07_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB07_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB07_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB07_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB07_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB07_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB07_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
\r
; SCSI_In_DBx\r
SCSI_In_DBx__0__MASK EQU 0x01\r
SCSI_In_DBx__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
SCSI_In_DBx__BYP EQU CYREG_PRT2_BYP\r
SCSI_In_DBx__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB0__MASK EQU 0x01\r
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT2_PC0\r
+SCSI_In_DBx__DB0__PORT EQU 2\r
+SCSI_In_DBx__DB0__SHIFT EQU 0\r
+SCSI_In_DBx__DB1__MASK EQU 0x02\r
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC1\r
+SCSI_In_DBx__DB1__PORT EQU 2\r
+SCSI_In_DBx__DB1__SHIFT EQU 1\r
+SCSI_In_DBx__DB2__MASK EQU 0x04\r
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC2\r
+SCSI_In_DBx__DB2__PORT EQU 2\r
+SCSI_In_DBx__DB2__SHIFT EQU 2\r
+SCSI_In_DBx__DB3__MASK EQU 0x08\r
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC3\r
+SCSI_In_DBx__DB3__PORT EQU 2\r
+SCSI_In_DBx__DB3__SHIFT EQU 3\r
+SCSI_In_DBx__DB4__MASK EQU 0x10\r
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__DB4__PORT EQU 2\r
+SCSI_In_DBx__DB4__SHIFT EQU 4\r
+SCSI_In_DBx__DB5__MASK EQU 0x20\r
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__DB5__PORT EQU 2\r
+SCSI_In_DBx__DB5__SHIFT EQU 5\r
+SCSI_In_DBx__DB6__MASK EQU 0x40\r
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC6\r
+SCSI_In_DBx__DB6__PORT EQU 2\r
+SCSI_In_DBx__DB6__SHIFT EQU 6\r
+SCSI_In_DBx__DB7__MASK EQU 0x80\r
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC7\r
+SCSI_In_DBx__DB7__PORT EQU 2\r
+SCSI_In_DBx__DB7__SHIFT EQU 7\r
SCSI_In_DBx__DM0 EQU CYREG_PRT2_DM0\r
SCSI_In_DBx__DM1 EQU CYREG_PRT2_DM1\r
SCSI_In_DBx__DM2 EQU CYREG_PRT2_DM2\r
SCSI_In_DBx__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
SCSI_In_DBx__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
SCSI_In_DBx__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__SCSI_Out_DB0__MASK EQU 0x01\r
-SCSI_In_DBx__SCSI_Out_DB0__PC EQU CYREG_PRT2_PC0\r
-SCSI_In_DBx__SCSI_Out_DB0__PORT EQU 2\r
-SCSI_In_DBx__SCSI_Out_DB0__SHIFT EQU 0\r
-SCSI_In_DBx__SCSI_Out_DB1__MASK EQU 0x02\r
-SCSI_In_DBx__SCSI_Out_DB1__PC EQU CYREG_PRT2_PC1\r
-SCSI_In_DBx__SCSI_Out_DB1__PORT EQU 2\r
-SCSI_In_DBx__SCSI_Out_DB1__SHIFT EQU 1\r
-SCSI_In_DBx__SCSI_Out_DB2__MASK EQU 0x04\r
-SCSI_In_DBx__SCSI_Out_DB2__PC EQU CYREG_PRT2_PC2\r
-SCSI_In_DBx__SCSI_Out_DB2__PORT EQU 2\r
-SCSI_In_DBx__SCSI_Out_DB2__SHIFT EQU 2\r
-SCSI_In_DBx__SCSI_Out_DB3__MASK EQU 0x08\r
-SCSI_In_DBx__SCSI_Out_DB3__PC EQU CYREG_PRT2_PC3\r
-SCSI_In_DBx__SCSI_Out_DB3__PORT EQU 2\r
-SCSI_In_DBx__SCSI_Out_DB3__SHIFT EQU 3\r
-SCSI_In_DBx__SCSI_Out_DB4__MASK EQU 0x10\r
-SCSI_In_DBx__SCSI_Out_DB4__PC EQU CYREG_PRT2_PC4\r
-SCSI_In_DBx__SCSI_Out_DB4__PORT EQU 2\r
-SCSI_In_DBx__SCSI_Out_DB4__SHIFT EQU 4\r
-SCSI_In_DBx__SCSI_Out_DB5__MASK EQU 0x20\r
-SCSI_In_DBx__SCSI_Out_DB5__PC EQU CYREG_PRT2_PC5\r
-SCSI_In_DBx__SCSI_Out_DB5__PORT EQU 2\r
-SCSI_In_DBx__SCSI_Out_DB5__SHIFT EQU 5\r
-SCSI_In_DBx__SCSI_Out_DB6__MASK EQU 0x40\r
-SCSI_In_DBx__SCSI_Out_DB6__PC EQU CYREG_PRT2_PC6\r
-SCSI_In_DBx__SCSI_Out_DB6__PORT EQU 2\r
-SCSI_In_DBx__SCSI_Out_DB6__SHIFT EQU 6\r
-SCSI_In_DBx__SCSI_Out_DB7__MASK EQU 0x80\r
-SCSI_In_DBx__SCSI_Out_DB7__PC EQU CYREG_PRT2_PC7\r
-SCSI_In_DBx__SCSI_Out_DB7__PORT EQU 2\r
-SCSI_In_DBx__SCSI_Out_DB7__SHIFT EQU 7\r
SCSI_In_DBx__SHIFT EQU 0\r
SCSI_In_DBx__SLW EQU CYREG_PRT2_SLW\r
\r
; SD_Clk_Ctl\r
SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
-SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
\r
; PARITY_EN\r
PARITY_EN__0__MASK EQU 0x10\r
PARITY_EN__SHIFT EQU 4\r
PARITY_EN__SLW EQU CYREG_PRT5_SLW\r
\r
+; SCSI_ATN\r
+SCSI_ATN__0__MASK EQU 0x20\r
+SCSI_ATN__0__PC EQU CYREG_PRT12_PC5\r
+SCSI_ATN__0__PORT EQU 12\r
+SCSI_ATN__0__SHIFT EQU 5\r
+SCSI_ATN__AG EQU CYREG_PRT12_AG\r
+SCSI_ATN__BIE EQU CYREG_PRT12_BIE\r
+SCSI_ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_ATN__BYP EQU CYREG_PRT12_BYP\r
+SCSI_ATN__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_ATN__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_ATN__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_ATN__DR EQU CYREG_PRT12_DR\r
+SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_ATN__INT__MASK EQU 0x20\r
+SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5\r
+SCSI_ATN__INT__PORT EQU 12\r
+SCSI_ATN__INT__SHIFT EQU 5\r
+SCSI_ATN__MASK EQU 0x20\r
+SCSI_ATN__PORT EQU 12\r
+SCSI_ATN__PRT EQU CYREG_PRT12_PRT\r
+SCSI_ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_ATN__PS EQU CYREG_PRT12_PS\r
+SCSI_ATN__SHIFT EQU 5\r
+SCSI_ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_ATN__SLW EQU CYREG_PRT12_SLW\r
+\r
; SCSI_Out\r
SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX\r
SCSI_Out__SEL__SHIFT EQU 0\r
SCSI_Out__SEL__SLW EQU CYREG_PRT6_SLW\r
\r
+; SCSI_RST\r
+SCSI_RST__0__MASK EQU 0x40\r
+SCSI_RST__0__PC EQU CYREG_PRT6_PC6\r
+SCSI_RST__0__PORT EQU 6\r
+SCSI_RST__0__SHIFT EQU 6\r
+SCSI_RST__AG EQU CYREG_PRT6_AG\r
+SCSI_RST__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_RST__BIE EQU CYREG_PRT6_BIE\r
+SCSI_RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_RST__BYP EQU CYREG_PRT6_BYP\r
+SCSI_RST__CTL EQU CYREG_PRT6_CTL\r
+SCSI_RST__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_RST__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_RST__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_RST__DR EQU CYREG_PRT6_DR\r
+SCSI_RST__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_RST__INTSTAT EQU CYREG_PICU6_INTSTAT\r
+SCSI_RST__INT__MASK EQU 0x40\r
+SCSI_RST__INT__PC EQU CYREG_PRT6_PC6\r
+SCSI_RST__INT__PORT EQU 6\r
+SCSI_RST__INT__SHIFT EQU 6\r
+SCSI_RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_RST__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_RST__MASK EQU 0x40\r
+SCSI_RST__PORT EQU 6\r
+SCSI_RST__PRT EQU CYREG_PRT6_PRT\r
+SCSI_RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_RST__PS EQU CYREG_PRT6_PS\r
+SCSI_RST__SHIFT EQU 6\r
+SCSI_RST__SLW EQU CYREG_PRT6_SLW\r
+SCSI_RST__SNAP EQU CYREG_PICU6_SNAP\r
+\r
; SCSI_ID\r
SCSI_ID__0__MASK EQU 0x80\r
SCSI_ID__0__PC EQU CYREG_PRT5_PC7\r
SCSI_In__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
SCSI_In__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
SCSI_In__0__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In__1__AG EQU CYREG_PRT12_AG\r
-SCSI_In__1__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In__1__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In__1__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In__1__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In__1__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In__1__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In__1__DR EQU CYREG_PRT12_DR\r
-SCSI_In__1__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In__1__MASK EQU 0x20\r
-SCSI_In__1__PC EQU CYREG_PRT12_PC5\r
-SCSI_In__1__PORT EQU 12\r
-SCSI_In__1__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In__1__PS EQU CYREG_PRT12_PS\r
-SCSI_In__1__SHIFT EQU 5\r
-SCSI_In__1__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In__1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In__1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In__1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In__1__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In__1__AG EQU CYREG_PRT6_AG\r
+SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__1__DR EQU CYREG_PRT6_DR\r
+SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__1__MASK EQU 0x10\r
+SCSI_In__1__PC EQU CYREG_PRT6_PC4\r
+SCSI_In__1__PORT EQU 6\r
+SCSI_In__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__1__PS EQU CYREG_PRT6_PS\r
+SCSI_In__1__SHIFT EQU 4\r
+SCSI_In__1__SLW EQU CYREG_PRT6_SLW\r
SCSI_In__2__AG EQU CYREG_PRT6_AG\r
SCSI_In__2__AMUX EQU CYREG_PRT6_AMUX\r
SCSI_In__2__BIE EQU CYREG_PRT6_BIE\r
SCSI_In__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
SCSI_In__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__2__MASK EQU 0x10\r
-SCSI_In__2__PC EQU CYREG_PRT6_PC4\r
+SCSI_In__2__MASK EQU 0x20\r
+SCSI_In__2__PC EQU CYREG_PRT6_PC5\r
SCSI_In__2__PORT EQU 6\r
SCSI_In__2__PRT EQU CYREG_PRT6_PRT\r
SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
SCSI_In__2__PS EQU CYREG_PRT6_PS\r
-SCSI_In__2__SHIFT EQU 4\r
+SCSI_In__2__SHIFT EQU 5\r
SCSI_In__2__SLW EQU CYREG_PRT6_SLW\r
SCSI_In__3__AG EQU CYREG_PRT6_AG\r
SCSI_In__3__AMUX EQU CYREG_PRT6_AMUX\r
SCSI_In__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
SCSI_In__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__3__MASK EQU 0x20\r
-SCSI_In__3__PC EQU CYREG_PRT6_PC5\r
+SCSI_In__3__MASK EQU 0x80\r
+SCSI_In__3__PC EQU CYREG_PRT6_PC7\r
SCSI_In__3__PORT EQU 6\r
SCSI_In__3__PRT EQU CYREG_PRT6_PRT\r
SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
SCSI_In__3__PS EQU CYREG_PRT6_PS\r
-SCSI_In__3__SHIFT EQU 5\r
+SCSI_In__3__SHIFT EQU 7\r
SCSI_In__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In__4__AG EQU CYREG_PRT6_AG\r
-SCSI_In__4__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__4__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__4__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__4__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__4__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__4__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__4__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__4__DR EQU CYREG_PRT6_DR\r
-SCSI_In__4__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__4__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__4__MASK EQU 0x40\r
-SCSI_In__4__PC EQU CYREG_PRT6_PC6\r
-SCSI_In__4__PORT EQU 6\r
-SCSI_In__4__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__4__PS EQU CYREG_PRT6_PS\r
-SCSI_In__4__SHIFT EQU 6\r
-SCSI_In__4__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In__5__AG EQU CYREG_PRT6_AG\r
-SCSI_In__5__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__5__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__5__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__5__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__5__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__5__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__5__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__5__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__5__DR EQU CYREG_PRT6_DR\r
-SCSI_In__5__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__5__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__5__MASK EQU 0x80\r
-SCSI_In__5__PC EQU CYREG_PRT6_PC7\r
-SCSI_In__5__PORT EQU 6\r
-SCSI_In__5__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__5__PS EQU CYREG_PRT6_PS\r
-SCSI_In__5__SHIFT EQU 7\r
-SCSI_In__5__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__4__AG EQU CYREG_PRT5_AG\r
+SCSI_In__4__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__4__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__4__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__4__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__4__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__4__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__4__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__4__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__4__DR EQU CYREG_PRT5_DR\r
+SCSI_In__4__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__4__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__4__MASK EQU 0x01\r
+SCSI_In__4__PC EQU CYREG_PRT5_PC0\r
+SCSI_In__4__PORT EQU 5\r
+SCSI_In__4__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__4__PS EQU CYREG_PRT5_PS\r
+SCSI_In__4__SHIFT EQU 0\r
+SCSI_In__4__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__5__AG EQU CYREG_PRT5_AG\r
+SCSI_In__5__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__5__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__5__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__5__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__5__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__5__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__5__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__5__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__5__DR EQU CYREG_PRT5_DR\r
+SCSI_In__5__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__5__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__5__MASK EQU 0x02\r
+SCSI_In__5__PC EQU CYREG_PRT5_PC1\r
+SCSI_In__5__PORT EQU 5\r
+SCSI_In__5__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__5__PS EQU CYREG_PRT5_PS\r
+SCSI_In__5__SHIFT EQU 1\r
+SCSI_In__5__SLW EQU CYREG_PRT5_SLW\r
SCSI_In__6__AG EQU CYREG_PRT5_AG\r
SCSI_In__6__AMUX EQU CYREG_PRT5_AMUX\r
SCSI_In__6__BIE EQU CYREG_PRT5_BIE\r
SCSI_In__6__INP_DIS EQU CYREG_PRT5_INP_DIS\r
SCSI_In__6__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
SCSI_In__6__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__6__MASK EQU 0x01\r
-SCSI_In__6__PC EQU CYREG_PRT5_PC0\r
+SCSI_In__6__MASK EQU 0x04\r
+SCSI_In__6__PC EQU CYREG_PRT5_PC2\r
SCSI_In__6__PORT EQU 5\r
SCSI_In__6__PRT EQU CYREG_PRT5_PRT\r
SCSI_In__6__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
SCSI_In__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
SCSI_In__6__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
SCSI_In__6__PS EQU CYREG_PRT5_PS\r
-SCSI_In__6__SHIFT EQU 0\r
+SCSI_In__6__SHIFT EQU 2\r
SCSI_In__6__SLW EQU CYREG_PRT5_SLW\r
SCSI_In__7__AG EQU CYREG_PRT5_AG\r
SCSI_In__7__AMUX EQU CYREG_PRT5_AMUX\r
SCSI_In__7__INP_DIS EQU CYREG_PRT5_INP_DIS\r
SCSI_In__7__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
SCSI_In__7__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__7__MASK EQU 0x02\r
-SCSI_In__7__PC EQU CYREG_PRT5_PC1\r
+SCSI_In__7__MASK EQU 0x08\r
+SCSI_In__7__PC EQU CYREG_PRT5_PC3\r
SCSI_In__7__PORT EQU 5\r
SCSI_In__7__PRT EQU CYREG_PRT5_PRT\r
SCSI_In__7__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
SCSI_In__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
SCSI_In__7__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
SCSI_In__7__PS EQU CYREG_PRT5_PS\r
-SCSI_In__7__SHIFT EQU 1\r
+SCSI_In__7__SHIFT EQU 3\r
SCSI_In__7__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__8__AG EQU CYREG_PRT5_AG\r
-SCSI_In__8__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__8__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__8__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__8__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__8__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__8__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__8__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__8__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__8__DR EQU CYREG_PRT5_DR\r
-SCSI_In__8__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__8__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__8__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__8__MASK EQU 0x04\r
-SCSI_In__8__PC EQU CYREG_PRT5_PC2\r
-SCSI_In__8__PORT EQU 5\r
-SCSI_In__8__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__8__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__8__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__8__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__8__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__8__PS EQU CYREG_PRT5_PS\r
-SCSI_In__8__SHIFT EQU 2\r
-SCSI_In__8__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__9__AG EQU CYREG_PRT5_AG\r
-SCSI_In__9__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_In__9__BIE EQU CYREG_PRT5_BIE\r
-SCSI_In__9__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_In__9__BYP EQU CYREG_PRT5_BYP\r
-SCSI_In__9__CTL EQU CYREG_PRT5_CTL\r
-SCSI_In__9__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_In__9__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_In__9__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_In__9__DR EQU CYREG_PRT5_DR\r
-SCSI_In__9__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_In__9__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_In__9__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_In__9__MASK EQU 0x08\r
-SCSI_In__9__PC EQU CYREG_PRT5_PC3\r
-SCSI_In__9__PORT EQU 5\r
-SCSI_In__9__PRT EQU CYREG_PRT5_PRT\r
-SCSI_In__9__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_In__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_In__9__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_In__9__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_In__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_In__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_In__9__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_In__9__PS EQU CYREG_PRT5_PS\r
-SCSI_In__9__SHIFT EQU 3\r
-SCSI_In__9__SLW EQU CYREG_PRT5_SLW\r
SCSI_In__ACK__AG EQU CYREG_PRT6_AG\r
SCSI_In__ACK__AMUX EQU CYREG_PRT6_AMUX\r
SCSI_In__ACK__BIE EQU CYREG_PRT6_BIE\r
SCSI_In__ACK__PS EQU CYREG_PRT6_PS\r
SCSI_In__ACK__SHIFT EQU 5\r
SCSI_In__ACK__SLW EQU CYREG_PRT6_SLW\r
-SCSI_In__ATN__AG EQU CYREG_PRT12_AG\r
-SCSI_In__ATN__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In__ATN__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In__ATN__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In__ATN__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In__ATN__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In__ATN__DR EQU CYREG_PRT12_DR\r
-SCSI_In__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In__ATN__MASK EQU 0x20\r
-SCSI_In__ATN__PC EQU CYREG_PRT12_PC5\r
-SCSI_In__ATN__PORT EQU 12\r
-SCSI_In__ATN__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In__ATN__PS EQU CYREG_PRT12_PS\r
-SCSI_In__ATN__SHIFT EQU 5\r
-SCSI_In__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In__ATN__SLW EQU CYREG_PRT12_SLW\r
SCSI_In__BSY__AG EQU CYREG_PRT6_AG\r
SCSI_In__BSY__AMUX EQU CYREG_PRT6_AMUX\r
SCSI_In__BSY__BIE EQU CYREG_PRT6_BIE\r
SCSI_In__REQ__PS EQU CYREG_PRT5_PS\r
SCSI_In__REQ__SHIFT EQU 2\r
SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW\r
-SCSI_In__RST__AG EQU CYREG_PRT6_AG\r
-SCSI_In__RST__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_In__RST__BIE EQU CYREG_PRT6_BIE\r
-SCSI_In__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_In__RST__BYP EQU CYREG_PRT6_BYP\r
-SCSI_In__RST__CTL EQU CYREG_PRT6_CTL\r
-SCSI_In__RST__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_In__RST__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_In__RST__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_In__RST__DR EQU CYREG_PRT6_DR\r
-SCSI_In__RST__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_In__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_In__RST__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_In__RST__MASK EQU 0x40\r
-SCSI_In__RST__PC EQU CYREG_PRT6_PC6\r
-SCSI_In__RST__PORT EQU 6\r
-SCSI_In__RST__PRT EQU CYREG_PRT6_PRT\r
-SCSI_In__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_In__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_In__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_In__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_In__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_In__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_In__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_In__RST__PS EQU CYREG_PRT6_PS\r
-SCSI_In__RST__SHIFT EQU 6\r
-SCSI_In__RST__SLW EQU CYREG_PRT6_SLW\r
SCSI_In__SEL__AG EQU CYREG_PRT5_AG\r
SCSI_In__SEL__AMUX EQU CYREG_PRT5_AMUX\r
SCSI_In__SEL__BIE EQU CYREG_PRT5_BIE\r
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0\r
CYDEV_DEBUGGING_DPS_SWD EQU 2\r
CYDEV_DEBUGGING_ENABLE EQU 1\r
-CYDEV_DEBUGGING_REQXRES EQU 1\r
CYDEV_DEBUGGING_XRES EQU 0\r
CYDEV_DEBUG_ENABLE_MASK EQU 0x20\r
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG\r
CYDEV_ECC_ENABLE EQU 0\r
CYDEV_HEAP_SIZE EQU 0x1000\r
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
-CYDEV_INTR_RISING EQU 0x00000003\r
+CYDEV_INTR_RISING EQU 0x00000001\r
CYDEV_PROJ_TYPE EQU 0\r
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
--- /dev/null
+/*******************************************************************************\r
+* FILENAME: cymetadata.c\r
+* \r
+* PSoC Creator 3.0\r
+*\r
+* DESCRIPTION:\r
+* This file defines all extra memory spaces that need to be included.\r
+* This file is automatically generated by PSoC Creator.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+********************************************************************************/\r
+\r
+\r
+#include "cytypes.h"\r
+\r
+\r
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
+__attribute__ ((__section__(".cyconfigecc"), used))\r
+#elif defined(__ICCARM__)\r
+#pragma location=".cyconfigecc"\r
+#else\r
+#error "Unsupported toolchain"\r
+#endif\r
+const uint8 cy_meta_configecc[] = {\r
+ 0x01u, 0x45u, 0x00u, 0x40u, 0x07u, 0x52u, 0x00u, 0x40u,\r
+ 0x01u, 0x64u, 0x00u, 0x40u, 0x02u, 0x03u, 0x01u, 0x40u,\r
+ 0x3Fu, 0x04u, 0x01u, 0x40u, 0x2Au, 0x05u, 0x01u, 0x40u,\r
+ 0x03u, 0x06u, 0x01u, 0x40u, 0x41u, 0x07u, 0x01u, 0x40u,\r
+ 0x01u, 0x0Du, 0x01u, 0x40u, 0x09u, 0x15u, 0x01u, 0x40u,\r
+ 0x43u, 0x16u, 0x01u, 0x40u, 0x3Au, 0x17u, 0x01u, 0x40u,\r
+ 0x02u, 0x40u, 0x01u, 0x40u, 0x01u, 0x41u, 0x01u, 0x40u,\r
+ 0x01u, 0x42u, 0x01u, 0x40u, 0x02u, 0x43u, 0x01u, 0x40u,\r
+ 0x02u, 0x44u, 0x01u, 0x40u, 0x02u, 0x45u, 0x01u, 0x40u,\r
+ 0x04u, 0x48u, 0x01u, 0x40u, 0x0Eu, 0x49u, 0x01u, 0x40u,\r
+ 0x04u, 0x50u, 0x01u, 0x40u, 0x01u, 0x51u, 0x01u, 0x40u,\r
+ 0x36u, 0x02u, 0x14u, 0xFFu, 0x18u, 0x04u, 0x19u, 0x0Cu,\r
+ 0x1Cu, 0xE1u, 0x2Cu, 0xFFu, 0x34u, 0xF0u, 0x64u, 0x10u,\r
+ 0x86u, 0x0Fu, 0x98u, 0x40u, 0xB0u, 0x40u, 0x00u, 0x01u,\r
+ 0x1Du, 0x01u, 0x2Du, 0x01u, 0x30u, 0x01u, 0x31u, 0x01u,\r
+ 0x39u, 0x02u, 0x3Eu, 0x01u, 0x56u, 0x08u, 0x58u, 0x04u,\r
+ 0x59u, 0x0Bu, 0x5Bu, 0x04u, 0x5Cu, 0x90u, 0x5Du, 0x90u,\r
+ 0x5Fu, 0x01u, 0x80u, 0x6Cu, 0x81u, 0x41u, 0x84u, 0x68u,\r
+ 0x86u, 0x04u, 0x88u, 0x6Cu, 0x89u, 0x81u, 0x8Bu, 0x40u,\r
+ 0x8Du, 0x41u, 0x91u, 0x04u, 0x92u, 0x02u, 0x94u, 0x10u,\r
+ 0x95u, 0xE2u, 0x96u, 0x68u, 0x97u, 0x08u, 0x98u, 0x10u,\r
+ 0x99u, 0x88u, 0x9Au, 0xC5u, 0x9Bu, 0x61u, 0x9Cu, 0x6Cu,\r
+ 0x9Du, 0x47u, 0x9Fu, 0x98u, 0xA0u, 0x6Cu, 0xA1u, 0x10u,\r
+ 0xA4u, 0x04u, 0xA5u, 0x41u, 0xA8u, 0x93u, 0xA9u, 0x40u,\r
+ 0xAAu, 0x20u, 0xACu, 0x0Fu, 0xADu, 0x01u, 0xAEu, 0x90u,\r
+ 0xAFu, 0x40u, 0xB2u, 0x78u, 0xB4u, 0x07u, 0xB5u, 0xC0u,\r
+ 0xB6u, 0x80u, 0xB7u, 0x3Fu, 0xB9u, 0x80u, 0xBAu, 0x38u,\r
+ 0xBBu, 0x20u, 0xBEu, 0x40u, 0xBFu, 0x40u, 0xD4u, 0x09u,\r
+ 0xD8u, 0x0Bu, 0xD9u, 0x0Bu, 0xDBu, 0x0Bu, 0xDCu, 0x99u,\r
+ 0xDDu, 0x90u, 0xDFu, 0x01u, 0x00u, 0x01u, 0x04u, 0x28u,\r
+ 0x06u, 0x80u, 0x0Cu, 0x02u, 0x0Du, 0x01u, 0x0Eu, 0x29u,\r
+ 0x17u, 0x69u, 0x1Au, 0x80u, 0x1Du, 0x30u, 0x1Eu, 0x28u,\r
+ 0x1Fu, 0x40u, 0x21u, 0x02u, 0x22u, 0x02u, 0x25u, 0x90u,\r
+ 0x27u, 0x08u, 0x29u, 0x40u, 0x2Fu, 0xAAu, 0x31u, 0x80u,\r
+ 0x36u, 0x06u, 0x37u, 0x60u, 0x3Cu, 0x80u, 0x3Du, 0x20u,\r
+ 0x3Eu, 0x81u, 0x4Bu, 0xC0u, 0x58u, 0x40u, 0x5Du, 0x24u,\r
+ 0x5Eu, 0x02u, 0x5Fu, 0x40u, 0x60u, 0x01u, 0x66u, 0x40u,\r
+ 0x78u, 0x02u, 0x7Cu, 0x02u, 0x98u, 0x40u, 0xC0u, 0x78u,\r
+ 0xC2u, 0xF0u, 0xC4u, 0xF0u, 0xCAu, 0xF8u, 0xCCu, 0xF8u,\r
+ 0xCEu, 0xB0u, 0xD6u, 0xF8u, 0xD8u, 0x18u, 0xDEu, 0x81u,\r
+ 0xD6u, 0x08u, 0xDBu, 0x04u, 0xDDu, 0x90u, 0x00u, 0x01u,\r
+ 0x02u, 0x40u, 0x05u, 0x10u, 0x07u, 0x61u, 0x0Du, 0x02u,\r
+ 0x0Eu, 0x21u, 0x0Fu, 0x08u, 0x17u, 0x1Au, 0x1Du, 0x40u,\r
+ 0x24u, 0x01u, 0x25u, 0x0Cu, 0x26u, 0x02u, 0x27u, 0x60u,\r
+ 0x2Au, 0x02u, 0x2Bu, 0x80u, 0x2Cu, 0x02u, 0x2Eu, 0x01u,\r
+ 0x2Fu, 0x28u, 0x36u, 0x46u, 0x3Cu, 0x80u, 0x3Du, 0x28u,\r
+ 0x44u, 0x80u, 0x45u, 0xA8u, 0x4Cu, 0x80u, 0x4Du, 0x04u,\r
+ 0x4Eu, 0x02u, 0x54u, 0x02u, 0x56u, 0x10u, 0x57u, 0x84u,\r
+ 0x59u, 0x80u, 0x60u, 0x02u, 0x66u, 0x20u, 0x6Cu, 0x14u,\r
+ 0x6Eu, 0xA1u, 0x6Fu, 0x3Bu, 0x74u, 0x40u, 0x77u, 0x02u,\r
+ 0x7Cu, 0x02u, 0x94u, 0x28u, 0x95u, 0x04u, 0x96u, 0x01u,\r
+ 0x99u, 0x10u, 0x9Bu, 0x08u, 0x9Cu, 0x02u, 0x9Du, 0x40u,\r
+ 0x9Eu, 0x40u, 0x9Fu, 0x61u, 0xA1u, 0x32u, 0xA2u, 0x04u,\r
+ 0xA4u, 0x42u, 0xA6u, 0x01u, 0xA7u, 0xAAu, 0xAAu, 0x40u,\r
+ 0xADu, 0x21u, 0xC0u, 0xF0u, 0xC2u, 0xF0u, 0xC4u, 0x70u,\r
+ 0xCAu, 0xF0u, 0xCCu, 0xD0u, 0xCEu, 0x70u, 0xD0u, 0xF0u,\r
+ 0xD2u, 0x10u, 0xD6u, 0x08u, 0xD8u, 0x28u, 0xDEu, 0x80u,\r
+ 0xEAu, 0x80u, 0x84u, 0x80u, 0x89u, 0x40u, 0x9Cu, 0x80u,\r
+ 0xA1u, 0x40u, 0xAAu, 0x40u, 0xADu, 0x01u, 0xB0u, 0x85u,\r
+ 0xB2u, 0x10u, 0xE6u, 0x20u, 0x00u, 0x04u, 0x02u, 0x08u,\r
+ 0x04u, 0x10u, 0x05u, 0x18u, 0x06u, 0x0Cu, 0x07u, 0x25u,\r
+ 0x08u, 0x20u, 0x09u, 0x20u, 0x0Au, 0x0Cu, 0x0Bu, 0x18u,\r
+ 0x0Eu, 0x03u, 0x0Fu, 0x01u, 0x11u, 0x08u, 0x12u, 0x04u,\r
+ 0x13u, 0x33u, 0x14u, 0x03u, 0x19u, 0x2Eu, 0x1Au, 0x30u,\r
+ 0x1Bu, 0x10u, 0x1Cu, 0x03u, 0x20u, 0x03u, 0x26u, 0x01u,\r
+ 0x28u, 0x03u, 0x2Eu, 0x48u, 0x30u, 0x40u, 0x32u, 0x01u,\r
+ 0x34u, 0x3Cu, 0x35u, 0x38u, 0x36u, 0x02u, 0x37u, 0x07u,\r
+ 0x3Bu, 0x20u, 0x3Eu, 0x44u, 0x54u, 0x40u, 0x58u, 0x0Bu,\r
+ 0x59u, 0x0Bu, 0x5Bu, 0x0Bu, 0x5Cu, 0x99u, 0x5Du, 0x90u,\r
+ 0x5Fu, 0x01u, 0x80u, 0x01u, 0x82u, 0x02u, 0x88u, 0x06u,\r
+ 0x8Bu, 0x07u, 0x8Eu, 0x10u, 0x91u, 0x01u, 0x92u, 0x08u,\r
+ 0x97u, 0x02u, 0x98u, 0x02u, 0x9Au, 0x01u, 0xA1u, 0x07u,\r
+ 0xA8u, 0x01u, 0xA9u, 0x04u, 0xAAu, 0x04u, 0xACu, 0x08u,\r
+ 0xAEu, 0x10u, 0xB0u, 0x07u, 0xB1u, 0x07u, 0xB2u, 0x07u,\r
+ 0xB6u, 0x18u, 0xB8u, 0x0Au, 0xBEu, 0x40u, 0xBFu, 0x01u,\r
+ 0xD8u, 0x0Bu, 0xD9u, 0x04u, 0xDBu, 0x04u, 0xDCu, 0x09u,\r
+ 0xDFu, 0x01u, 0x00u, 0x10u, 0x01u, 0x40u, 0x03u, 0x40u,\r
+ 0x05u, 0x10u, 0x07u, 0x61u, 0x09u, 0x20u, 0x0Au, 0x80u,\r
+ 0x0Eu, 0x69u, 0x10u, 0x02u, 0x12u, 0x08u, 0x13u, 0x20u,\r
+ 0x16u, 0x12u, 0x17u, 0x12u, 0x18u, 0x10u, 0x19u, 0x81u,\r
+ 0x1Du, 0x84u, 0x1Eu, 0x4Au, 0x1Fu, 0x10u, 0x21u, 0x01u,\r
+ 0x25u, 0x40u, 0x27u, 0x08u, 0x29u, 0x11u, 0x32u, 0x0Au,\r
+ 0x35u, 0x10u, 0x36u, 0x02u, 0x3Bu, 0x20u, 0x3Du, 0x88u,\r
+ 0x3Eu, 0x20u, 0x46u, 0x20u, 0x47u, 0x08u, 0x64u, 0x05u,\r
+ 0x65u, 0x04u, 0x68u, 0x02u, 0x78u, 0x02u, 0x7Cu, 0x02u,\r
+ 0x8Du, 0x40u, 0x92u, 0x01u, 0x98u, 0x02u, 0x99u, 0x10u,\r
+ 0x9Au, 0x12u, 0x9Bu, 0x73u, 0x9Cu, 0x80u, 0x9Du, 0x80u,\r
+ 0x9Eu, 0x20u, 0xA0u, 0x80u, 0xA1u, 0x24u, 0xA2u, 0x12u,\r
+ 0xA5u, 0x80u, 0xA6u, 0x01u, 0xC0u, 0xFBu, 0xC2u, 0xFAu,\r
+ 0xC4u, 0xF3u, 0xCAu, 0x05u, 0xCCu, 0xA3u, 0xCEu, 0x74u,\r
+ 0xD8u, 0x70u, 0xDEu, 0x81u, 0xE0u, 0x40u, 0x33u, 0x40u,\r
+ 0xCCu, 0x10u, 0x9Fu, 0x40u, 0x9Fu, 0x40u, 0xABu, 0x40u,\r
+ 0xEEu, 0x80u, 0x14u, 0x40u, 0xC4u, 0x04u, 0xB0u, 0x40u,\r
+ 0xEAu, 0x01u, 0x20u, 0x10u, 0x26u, 0x80u, 0x8Eu, 0x80u,\r
+ 0xC8u, 0x60u, 0x08u, 0x02u, 0x5Bu, 0x20u, 0x5Fu, 0x40u,\r
+ 0x84u, 0x02u, 0x8Bu, 0x20u, 0x93u, 0x40u, 0xA8u, 0x10u,\r
+ 0xAFu, 0x40u, 0xC2u, 0x10u, 0xD4u, 0x80u, 0xD6u, 0x20u,\r
+ 0xE4u, 0x40u, 0xECu, 0x80u, 0xEEu, 0x40u, 0x01u, 0x01u,\r
+ 0x0Bu, 0x01u, 0x11u, 0x01u, 0x1Bu, 0x01u, 0x00u, 0x03u,\r
+ 0x1Fu, 0x00u, 0x20u, 0x00u, 0x00u, 0x91u, 0xFFu, 0x6Eu,\r
+ 0x7Fu, 0x24u, 0x80u, 0x00u, 0x90u, 0x6Cu, 0x40u, 0x00u,\r
+ 0x00u, 0x71u, 0x60u, 0x82u, 0xC0u, 0x10u, 0x08u, 0xEFu,\r
+ 0x00u, 0x00u, 0x9Fu, 0x00u, 0xC0u, 0x6Cu, 0x02u, 0x00u,\r
+ 0xC0u, 0x6Cu, 0x01u, 0x00u, 0x80u, 0x24u, 0x00u, 0x48u,\r
+ 0xC0u, 0x00u, 0x04u, 0x6Cu, 0x00u, 0x48u, 0x00u, 0x00u,\r
+ 0x00u, 0x0Fu, 0x00u, 0xF0u, 0x00u, 0x00u, 0xFFu, 0x10u,\r
+ 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x40u,\r
+ 0x32u, 0x05u, 0x10u, 0x00u, 0x04u, 0xFEu, 0xDBu, 0xCBu,\r
+ 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,\r
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u,\r
+ 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u,\r
+ 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u,\r
+ 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x08u, 0x00u, 0x30u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x10u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x01u, 0x02u, 0x00u, 0xF1u, 0x0Eu,\r
+ 0x0Eu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0xFCu, 0xFCu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0xF0u, 0x00u, 0x0Fu, 0xF0u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x01u, 0x00u, 0x00u, 0xF0u, 0x0Fu, 0x0Fu, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x01u\r
+};\r
+\r
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
+__attribute__ ((__section__(".cycustnvl"), used))\r
+#elif defined(__ICCARM__)\r
+#pragma location=".cycustnvl"\r
+#else\r
+#error "Unsupported toolchain"\r
+#endif\r
+const uint8 cy_meta_custnvl[] = {\r
+ 0x00u, 0x00u, 0x40u, 0x05u\r
+};\r
+\r
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
+__attribute__ ((__section__(".cywolatch"), used))\r
+#elif defined(__ICCARM__)\r
+#pragma location=".cywolatch"\r
+#else\r
+#error "Unsupported toolchain"\r
+#endif\r
+const uint8 cy_meta_wonvl[] = {\r
+ 0xBCu, 0x90u, 0xACu, 0xAFu\r
+};\r
+\r
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
+__attribute__ ((__section__(".cyflashprotect"), used))\r
+#elif defined(__ICCARM__)\r
+#pragma location=".cyflashprotect"\r
+#else\r
+#error "Unsupported toolchain"\r
+#endif\r
+const uint8 cy_meta_flashprotect[] = {\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u\r
+};\r
+\r
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
+__attribute__ ((__section__(".cymeta"), used))\r
+#elif defined(__ICCARM__)\r
+#pragma location=".cymeta"\r
+#else\r
+#error "Unsupported toolchain"\r
+#endif\r
+const uint8 cy_metadata[] = {\r
+ 0x00u, 0x01u, 0x2Eu, 0x12u, 0xF0u, 0x69u, 0x00u, 0x01u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u\r
+};\r
/*******************************************************************************\r
* File Name: cypins.h\r
-* Version 3.40\r
+* Version 4.0\r
*\r
* Description:\r
* This file contains the function prototypes and constants used for port/pin\r
/*******************************************************************************\r
* FILENAME: cytypes.h\r
-* Version 3.40\r
+* Version 4.0\r
*\r
* Description:\r
* CyTypes provides register access macros and approved types for use in\r
#include "cyfitter.h"\r
\r
\r
+#if defined( __ICCARM__ )\r
+ /* Suppress warning for multiple volatile variables in an expression. */\r
+ /* This is common in component code and the usage is not order dependent. */\r
+ #pragma diag_suppress=Pa082\r
+#endif /* defined( __ICCARM__ ) */\r
+\r
\r
/***************************************\r
* Conditional Compilation Parameters\r
/*******************************************************************************\r
* MEMBER encodes both the family and the detailed architecture\r
*******************************************************************************/\r
+#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)\r
+#ifdef CYDEV_CHIP_MEMBER_4D\r
+ #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)\r
+ #define CY_PSOC4SF (CY_PSOC4D)\r
+#else\r
+ #define CY_PSOC4D (0u != 0u)\r
+ #define CY_PSOC4SF (CY_PSOC4D)\r
+#endif /* CYDEV_CHIP_MEMBER_4D */\r
+\r
#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)\r
#ifdef CYDEV_CHIP_MEMBER_5B\r
- #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)\r
+ #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)\r
#else\r
- #define CY_PSOC5LP 0\r
-#endif\r
+ #define CY_PSOC5LP (0u != 0u)\r
+#endif /* CYDEV_CHIP_MEMBER_5B */\r
\r
\r
/*******************************************************************************\r
* endian conversion. These functions should be called through the\r
* CY_GET_XTND_REGxx and CY_SET_XTND_REGxx macros.\r
***************************************************************************/\r
- extern uint8 cyread8 (volatile void far *addr);\r
+ extern uint8 cyread8 (const volatile void far *addr);\r
extern void cywrite8 (volatile void far *addr, uint8 value);\r
\r
- extern uint16 cyread16 (volatile void far *addr);\r
- extern uint16 cyread16_nodpx(volatile void far *addr);\r
+ extern uint16 cyread16 (const volatile void far *addr);\r
+ extern uint16 cyread16_nodpx(const volatile void far *addr);\r
\r
extern void cywrite16 (volatile void far *addr, uint16 value);\r
extern void cywrite16_nodpx(volatile void far *addr, uint16 value);\r
\r
- extern uint32 cyread24 (volatile void far *addr);\r
- extern uint32 cyread24_nodpx(volatile void far *addr);\r
+ extern uint32 cyread24 (const volatile void far *addr);\r
+ extern uint32 cyread24_nodpx(const volatile void far *addr);\r
\r
extern void cywrite24 (volatile void far *addr, uint32 value);\r
extern void cywrite24_nodpx(volatile void far *addr, uint32 value);\r
\r
- extern uint32 cyread32 (volatile void far *addr);\r
- extern uint32 cyread32_nodpx(volatile void far *addr);\r
+ extern uint32 cyread32 (const volatile void far *addr);\r
+ extern uint32 cyread32_nodpx(const volatile void far *addr);\r
\r
extern void cywrite32 (volatile void far *addr, uint32 value);\r
extern void cywrite32_nodpx(volatile void far *addr, uint32 value);\r
\r
#if(CY_PSOC4)\r
\r
- extern uint32 CyGetReg24(uint32 volatile * addr);\r
+ extern uint32 CyGetReg24(uint32 const volatile * addr);\r
\r
- #endif /*(CY_PSOC4)*/\r
+ #endif /* (CY_PSOC4) */\r
\r
#endif /* (CY_PSOC3) */\r
\r
#define CYSMALL small\r
#define CYXDATA xdata\r
#define XDATA xdata\r
- \r
+\r
#define CY_NOINIT\r
\r
#else\r
#define CYSMALL\r
#define CYXDATA\r
#define XDATA\r
- \r
+\r
#if defined(__ARMCC_VERSION)\r
- #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init))\r
+ #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init))\r
+ #define CY_NORETURN __attribute__ ((noreturn))\r
+ #define CY_SECTION(name) __attribute__ ((section(name)))\r
+ #define CY_ALIGN(align) __align(align)\r
#elif defined (__GNUC__)\r
- #define CY_NOINIT __attribute__ ((section(".noinit")))\r
+ #define CY_NOINIT __attribute__ ((section(".noinit")))\r
+ #define CY_NORETURN __attribute__ ((noreturn))\r
+ #define CY_SECTION(name) __attribute__ ((section(name)))\r
+ #define CY_ALIGN(align) __attribute__ ((aligned(align)))\r
+ #elif defined (__ICCARM__)\r
+ #define CY_NOINIT __no_init\r
+ #define CY_NORETURN __noreturn\r
#endif /* (__ARMCC_VERSION) */\r
\r
-\r
#endif /* (CY_PSOC3) */\r
\r
\r
#define CY_ISR_PROTO(FuncName) void FuncName (void)\r
typedef void (* cyisraddress)(void);\r
\r
+ #if defined (__ICCARM__)\r
+ typedef union { cyisraddress __fun; void * __ptr; } intvec_elem;\r
+ #endif /* defined (__ICCARM__) */\r
+\r
#endif /* (CY_PSOC3) */\r
\r
\r
\r
/* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */\r
\r
- #define CY_GET_REG8(addr) (*((reg8 *)(addr)))\r
+ #define CY_GET_REG8(addr) (*((const reg8 *)(addr)))\r
#define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value))\r
\r
- #define CY_GET_REG16(addr) cyread16_nodpx ((volatile void far *)(reg16 *)(addr))\r
+ #define CY_GET_REG16(addr) cyread16_nodpx ((const volatile void far *)(const reg16 *)(addr))\r
#define CY_SET_REG16(addr, value) cywrite16_nodpx((volatile void far *)(reg16 *)(addr), value)\r
\r
- #define CY_GET_REG24(addr) cyread24_nodpx ((volatile void far *)(reg32 *)(addr))\r
+ #define CY_GET_REG24(addr) cyread24_nodpx ((const volatile void far *)(const reg32 *)(addr))\r
#define CY_SET_REG24(addr, value) cywrite24_nodpx((volatile void far *)(reg32 *)(addr),value)\r
\r
- #define CY_GET_REG32(addr) cyread32_nodpx ((volatile void far *)(reg32 *)(addr))\r
+ #define CY_GET_REG32(addr) cyread32_nodpx ((const volatile void far *)(const reg32 *)(addr))\r
#define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value)\r
\r
/* Access 8, 16, 24 and 32-bit registers, ABOVE THE FIRST 64K OF XDATA */\r
- #define CY_GET_XTND_REG8(addr) cyread8((volatile void far *)(addr))\r
+ #define CY_GET_XTND_REG8(addr) cyread8((const volatile void far *)(addr))\r
#define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value)\r
\r
- #define CY_GET_XTND_REG16(addr) cyread16((volatile void far *)(addr))\r
+ #define CY_GET_XTND_REG16(addr) cyread16((const volatile void far *)(addr))\r
#define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value)\r
\r
- #define CY_GET_XTND_REG24(addr) cyread24((volatile void far *)(addr))\r
+ #define CY_GET_XTND_REG24(addr) cyread24((const volatile void far *)(addr))\r
#define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value)\r
\r
- #define CY_GET_XTND_REG32(addr) cyread32((volatile void far *)(addr))\r
+ #define CY_GET_XTND_REG32(addr) cyread32((const volatile void far *)(addr))\r
#define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value)\r
\r
#else\r
\r
/* 8, 16, 24 and 32-bit register access macros */\r
- #define CY_GET_REG8(addr) (*((reg8 *)(addr)))\r
+ #define CY_GET_REG8(addr) (*((const reg8 *)(addr)))\r
#define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value))\r
\r
- #define CY_GET_REG16(addr) (*((reg16 *)(addr)))\r
+ #define CY_GET_REG16(addr) (*((const reg16 *)(addr)))\r
#define CY_SET_REG16(addr, value) (*((reg16 *)(addr)) = (uint16)(value))\r
\r
\r
#define CY_SET_REG24(addr, value) CySetReg24((reg32 *) (addr), (value))\r
#if(CY_PSOC4)\r
- #define CY_GET_REG24(addr) CyGetReg24((reg32 *) (addr))\r
+ #define CY_GET_REG24(addr) CyGetReg24((const reg32 *) (addr))\r
#else\r
- #define CY_GET_REG24(addr) (*((reg32 *)(addr)) & 0x00FFFFFFu)\r
+ #define CY_GET_REG24(addr) (*((const reg32 *)(addr)) & 0x00FFFFFFu)\r
#endif /* (CY_PSOC4) */\r
\r
\r
- #define CY_GET_REG32(addr) (*((reg32 *)(addr)))\r
+ #define CY_GET_REG32(addr) (*((const reg32 *)(addr)))\r
#define CY_SET_REG32(addr, value) (*((reg32 *)(addr)) = (uint32)(value))\r
\r
\r
*******************************************************************************/\r
\r
/* Get 8 bits of a 16 bit value. */\r
-#define LO8(x) ((uint8) (x))\r
-#define HI8(x) ((uint8) ((x) >> 8))\r
+#define LO8(x) ((uint8) ((x) & 0xFFu))\r
+#define HI8(x) ((uint8) ((uint16)(x) >> 8))\r
\r
/* Get 16 bits of a 32 bit value. */\r
-#define LO16(x) ((uint16) (x))\r
+#define LO16(x) ((uint16) ((x) & 0xFFFFu))\r
#define HI16(x) ((uint16) ((uint32)(x) >> 16))\r
\r
/* Swap the byte ordering of a 32 bit value */\r
/*******************************************************************************\r
* FILENAME: cyutils.c\r
-* Version 3.40\r
+* Version 4.0\r
*\r
* Description:\r
* CyUtils provides function to handle 24-bit value writes.\r
* No\r
*\r
***************************************************************************/\r
- uint32 CyGetReg24(uint32 volatile * addr)\r
+ uint32 CyGetReg24(uint32 const volatile * addr)\r
{\r
- uint8 volatile *tmpAddr;\r
+ uint8 const volatile *tmpAddr;\r
uint32 value;\r
\r
- tmpAddr = (uint8 volatile *) addr;\r
+ tmpAddr = (uint8 const volatile *) addr;\r
\r
value = (uint32) tmpAddr[0u];\r
value |= ((uint32) tmpAddr[1u] << 8u );\r
/*******************************************************************************\r
- * File Name: project.h \r
- * PSoC Creator 2.2 Component Pack 6\r
+ * File Name: project.h\r
+ * PSoC Creator 3.0\r
*\r
* Description:\r
* This file is automatically generated by PSoC Creator and should not \r
#include <cydevice.h>\r
#include <cydevice_trm.h>\r
#include <cyfitter.h>\r
+#include <cydisabledsheets.h>\r
#include <SCSI_In_DBx_aliases.h>\r
#include <SCSI_In_DBx.h>\r
#include <SCSI_Out_DBx_aliases.h>\r
#include <SD_Init_Clk.h>\r
#include <SD_Data_Clk.h>\r
#include <SD_Clk_Ctl.h>\r
+#include <SCSI_RST_aliases.h>\r
+#include <SCSI_RST.h>\r
+#include <SCSI_ATN_aliases.h>\r
+#include <SCSI_ATN.h>\r
+#include <SCSI_RST_ISR.h>\r
+#include <SCSI_ATN_ISR.h>\r
#include <core_cm3_psoc5.h>\r
#include <core_cm3.h>\r
#include <CyDmac.h>\r
#include <cyPm.h>\r
#include <CySpc.h>\r
#include <cytypes.h>\r
+#include <core_cmFunc.h>\r
+#include <core_cmInstr.h>\r
\r
/*[]*/\r
\r
--- /dev/null
+<?xml version="1.0" encoding="utf-8"?>\r
+<!--DO NOT EDIT. This document is generated by PSoC Creator design builds.-->\r
+<PSoCCreatorIdeExport Version="1">\r
+ <Device Part="CY8C5268AXI-LP047" Processor="CortexM3" DeviceID="2E12F069" />\r
+ <Toolchains>\r
+ <Toolchain Name="ARM GCC" Selected="True">\r
+ <Tool Name="prebuild" Command="" Options="" />\r
+ <Tool Name="assembler" Command="arm-none-eabi-as.exe" Options="-I. -I./Generated_Source/PSoC5 -mcpu=cortex-m3 -mthumb -g -alh=${OutputDir}/${CompileFile}.lst " />\r
+ <Tool Name="compiler" Command="arm-none-eabi-gcc.exe" Options="-I. -I./Generated_Source/PSoC5 -Wno-main -mcpu=cortex-m3 -mthumb -Wall -g -D NDEBUG -Wa,-alh=${OutputDir}\${CompileFile}.lst -Os -ffunction-sections " />\r
+ <Tool Name="linker" Command="arm-none-eabi-gcc.exe" Options="-mthumb -march=armv7-m -mfix-cortex-m3-ldrd -T .\Generated_Source\PSoC5\cm3gcc.ld -g -Wl,-Map,${OutputDir}\${ProjectShortName}.map -specs=nano.specs -Wl,--gc-sections " />\r
+ <Tool Name="postbuild" Command="" Options="" />\r
+ </Toolchain>\r
+ <Toolchain Name="ARM Keil MDK" Selected="False">\r
+ <Tool Name="prebuild" Command="" Options="" />\r
+ <Tool Name="assembler" Command="armasm.exe" Options="-i. -iGenerated_Source/PSoC5 --diag_style=gnu --thumb --cpu=Cortex-M3 -g --list=${OutputDir}/${CompileFile}.lst " />\r
+ <Tool Name="compiler" Command="armcc.exe" Options="-I. -I./Generated_Source/PSoC5 --diag_suppress=951 --diag_style=gnu --cpu=Cortex-M3 -g -D NDEBUG --signed_chars --list -Ospace --split_sections " />\r
+ <Tool Name="linker" Command="armlink.exe" Options="--diag_style=gnu --no_startup --cpu=Cortex-M3 --scatter .\Generated_Source\PSoC5\Cm3RealView.scat --map --list ${OutputDir}\${ProjectShortName}.map " />\r
+ <Tool Name="postbuild" Command="" Options="" />\r
+ </Toolchain>\r
+ </Toolchains>\r
+ <Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" Version="4.0" Type="Normal">\r
+ <CMSIS_SVD_File>SCSI2SD.svd</CMSIS_SVD_File>\r
+ <Datasheet>SCSI2SD_datasheet.pdf</Datasheet>\r
+ <LinkerFiles>\r
+ <LinkerFile Toolchain="ARM GCC">.\Generated_Source\PSoC5\cm3gcc.ld</LinkerFile>\r
+ <LinkerFile Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\Cm3RealView.scat</LinkerFile>\r
+ <LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile>\r
+ </LinkerFiles>\r
+ <Folders>\r
+ <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">\r
+ <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">\r
+ <File BuildType="BUILD" Toolchain="">.\main.c</File>\r
+ <File BuildType="BUILD" Toolchain="">.\loopback.c</File>\r
+ <File BuildType="BUILD" Toolchain="">.\blinky.c</File>\r
+ <File BuildType="BUILD" Toolchain="">.\bits.c</File>\r
+ <File BuildType="BUILD" Toolchain="">.\device.h</File>\r
+ <File BuildType="BUILD" Toolchain="">.\blinky.h</File>\r
+ <File BuildType="BUILD" Toolchain="">.\loopback.h</File>\r
+ <File BuildType="BUILD" Toolchain="">.\bits.h</File>\r
+ </Files>\r
+ </Folder>\r
+ <Folder BuildType="BUILD" Path="\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">\r
+ <Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">\r
+ <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\diagnostic.c</File>\r
+ <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\disk.c</File>\r
+ <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\geometry.c</File>\r
+ <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\inquiry.c</File>\r
+ <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\mode.c</File>\r
+ <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\scsi.c</File>\r
+ <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\scsiPhy.c</File>\r
+ <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\sd.c</File>\r
+ <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\diagnostic.h</File>\r
+ <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\disk.h</File>\r
+ <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\geometry.h</File>\r
+ <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\inquiry.h</File>\r
+ <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\led.h</File>\r
+ <File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\mode.h</File>\r
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<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Default Libs" v="True" />\r
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<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Use Default Libs" v="True" />\r
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<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Remove Unused Functions" v="True" />\r
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<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
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+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />\r
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+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Suppress Warnings" v="False" />\r
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+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Additional Link Files" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Additional Libraries" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Additional Library Directories" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Use Debugging Information" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Generate Map File" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Use Nano Lib" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Remove Unused Functions" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Additional Include Directories" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Warnings as Errors" v="False" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Warning Level" v="High" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Pedantic Compilation" v="False" />\r
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+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Create Listing File" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Code Generation@Struct Return Method" v="System Default" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Code Generation@Verbose Asm" v="False" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Command Line@Command Line" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Suppress Warnings" v="False" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Generate Debugging Information" v="True" />\r
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+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@Command Line@Command Line" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Link Files" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Libraries" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Library Directories" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Debugging Information" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Generate Map File" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Default Libs" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Nano Lib" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Remove Unused Functions" v="True" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Custom Linker Script" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Command Line@Command Line" v="" />\r
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
</name>\r
</platform>\r
</platforms>\r
<project_current_processor v="CortexM3" />\r
<component_generation v="PSoC Creator 2.2 Component Pack 6" />\r
<last_selected_tab v="Cypress" />\r
-<component_dependent_projects_generation v="(69eeda1b-ded5-4da3-a74d-3a98f2d5d4ab , CP6) | (b1a3f413-e018-46a5-a51c-20818b2f118e , 2.2SP1) | (cd381074-8dad-4f43-bb88-7719b3e16126 , 2.1) | (29420278-6fcc-46a7-a651-999ec5c253d2 , 2.1) | (e95576e7-780d-474a-b944-018db0492cc9 , 2.1)" />\r
-<WriteAppVersionLastSavedWith v="2.2.0.572" />\r
-<WriteAppMarketingVersionLastSavedWith v=" 2.2 Component Pack 6" />\r
+<component_dependent_projects_generation v="(69eeda1b-ded5-4da3-a74d-3a98f2d5d4ab , 2.1PR) | (b1a3f413-e018-46a5-a51c-20818b2f118e , 3.0) | (cd381074-8dad-4f43-bb88-7719b3e16126 , 2.1) | (29420278-6fcc-46a7-a651-999ec5c253d2 , 2.1) | (e95576e7-780d-474a-b944-018db0492cc9 , 2.1)" />\r
+<WriteAppVersionLastSavedWith v="3.0.0.1539" />\r
+<WriteAppMarketingVersionLastSavedWith v=" 3.0" />\r
<project_id v="6e1f5cbb-a0ca-4f55-a1fa-7b20c5be3a3e" />\r
<custom_data>\r
<CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1">\r
<CyGuid_b0d670ad-d48f-47cb-9d0b-b1642bab195c type_name="CyDesigner.Common.Base.CyExprTypeMgr" version="1" />\r
<ignored_deps />\r
</CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>\r
-<boot_component v="cy_boot_v3_40" />\r
+<boot_component v="cy_boot_v4_0" />\r
<BootloaderTag hexFile="" elfFile="" />\r
+<current_generation v="0" />\r
</CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>\r
</CyXmlSerializer>
\ No newline at end of file
+++ /dev/null
-<?xml version="1.0" encoding="utf-8"?>\r
-<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">\r
- <name>CY8C5268AXI_LP047</name>\r
- <version>0.1</version>\r
- <description>CY8C52LP</description>\r
- <addressUnitBits>8</addressUnitBits>\r
- <width>32</width>\r
- <peripherals>\r
- <peripheral>\r
- <name>SD_Clk_Ctl</name>\r
- <description>No description available</description>\r
- <baseAddress>0x40006476</baseAddress>\r
- <addressBlock>\r
- <offset>0</offset>\r
- <size>0x1</size>\r
- <usage>registers</usage>\r
- </addressBlock>\r
- <registers>\r
- <register>\r
- <name>SD_Clk_Ctl_CONTROL_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- </registers>\r
- </peripheral>\r
- </peripherals>\r
-</device>
\ No newline at end of file
<FileType>5</FileType>
<FilePath>.\Generated_Source\PSoC5\SDCard_PVT.h</FilePath>
</File>
+ <File>
+ <FileName>SCSI_RST_aliases.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_RST_aliases.h</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_RST.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_RST.c</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_RST.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_RST.h</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_ATN_aliases.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_ATN_aliases.h</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_ATN.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_ATN.c</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_ATN.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_ATN.h</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_RST_ISR.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_RST_ISR.c</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_RST_ISR.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_RST_ISR.h</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_ATN_ISR.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_ATN_ISR.c</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_ATN_ISR.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_ATN_ISR.h</FilePath>
+ </File>
</Files>
</Group>
</Groups>
<FileType>5</FileType>
<FilePath>.\Generated_Source\PSoC5\SDCard_PVT.h</FilePath>
</File>
+ <File>
+ <FileName>SCSI_RST_aliases.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_RST_aliases.h</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_RST.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_RST.c</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_RST.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_RST.h</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_ATN_aliases.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_ATN_aliases.h</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_ATN.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_ATN.c</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_ATN.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_ATN.h</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_RST_ISR.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_RST_ISR.c</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_RST_ISR.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_RST_ISR.h</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_ATN_ISR.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_ATN_ISR.c</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_ATN_ISR.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_ATN_ISR.h</FilePath>
+ </File>
</Files>
</Group>
</Groups>
31, // standard length\r
0, 0, //Reserved\r
0, // We don't support anything at all\r
+/* TODO testing Apple Drive Setup. Make configurable!\r
'c','o','d','e','s','r','c',' ',\r
'S','C','S','I','2','S','D',' ',' ',' ',' ',' ',' ',' ',' ',' ',\r
'2','.','0','a'\r
+*/\r
+' ','S','E','A','G','A','T','E',\r
+' ',' ',' ',' ',' ',' ',' ',' ',' ',' ','S','T','2','2','5','N',\r
+'1','.','0',' '\r
};\r
\r
static const uint8 SupportedVitalPages[] =\r
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
\r
#include "loopback.h"\r
+#include "scsi.h"\r
#include "device.h"\r
\r
// Return true if all inputs are un-asserted (1)\r
int result =\r
(dbx == 0xFF) &&\r
CyPins_ReadPin(SCSI_In_DBP) &&\r
- CyPins_ReadPin(SCSI_In_ATN) &&\r
+ CyPins_ReadPin(SCSI_ATN_INT) &&\r
CyPins_ReadPin(SCSI_In_BSY) &&\r
CyPins_ReadPin(SCSI_In_ACK) &&\r
- CyPins_ReadPin(SCSI_In_RST) &&\r
+ CyPins_ReadPin(SCSI_RST_INT) &&\r
CyPins_ReadPin(SCSI_In_MSG) &&\r
CyPins_ReadPin(SCSI_In_SEL) &&\r
CyPins_ReadPin(SCSI_In_CD) &&\r
return result;\r
}\r
\r
+static int test_ATN_interrupt(void)\r
+{\r
+ int result = 1;\r
+ int i;\r
+ \r
+ scsiDev.atnFlag = 0;\r
+ for (i = 0; i < 100 && result; ++i)\r
+ {\r
+ // We write using Active High\r
+ CyPins_SetPin(SCSI_Out_ATN);\r
+ CyDelayCycles(2);\r
+ result &= scsiDev.atnFlag == 1;\r
+ scsiDev.atnFlag = 0;\r
+ CyPins_ClearPin(SCSI_Out_ATN);\r
+ result &= scsiDev.atnFlag == 0;\r
+ }\r
+ return result;\r
+}\r
+\r
static void test_error(void)\r
{\r
// Toggle LED.\r
}\r
void scsi2sd_test_loopback(void)\r
{\r
- if (!test_initial_inputs() || !test_data_lines() || !test_data_10MHz())\r
+ if (!test_initial_inputs() ||\r
+ !test_data_lines() ||\r
+ !test_data_10MHz() ||\r
+ !test_ATN_interrupt())\r
{\r
test_error();\r
}\r
\r
#include "device.h"\r
// #include "blinky.h"\r
-// #include "loopback.h"\r
+#include "loopback.h"\r
#include "scsi.h"\r
+#include "scsiPhy.h"\r
#include "disk.h"\r
#include "led.h"\r
\r
const char* Notice = "Copyright (C) 2013 Michael McMaster <michael@codesrc.com>";\r
\r
-void main()\r
+int main()\r
{\r
// scsi2sd_test_blinky(); // Initial test. Will not return.\r
- // scsi2sd_test_loopback(); // Second test. Will not return.\r
ledOff();\r
\r
- /* Uncomment this line to enable global interrupts. */\r
- // MM: Try to avoid interrupts completely, as it will screw with our\r
- // timing.\r
- CyGlobalIntEnable;\r
- \r
- // TODO insert any initialisation code here.\r
+ // Enable global interrupts.\r
+ // Needed for RST and ATN interrupt handlers.\r
+ CyGlobalIntEnable;\r
+\r
+ // Set interrupt handlers.\r
+ scsiPhyInit();\r
+ \r
+ // Loopback test requires the interrupt handers.\r
+ // Will not return if uncommented.\r
+ // scsi2sd_test_loopback();\r
+ \r
scsiInit(0, 1); // ID 0 is mac boot disk\r
scsiDiskInit();\r
\r
scsiPoll();\r
scsiDiskPoll();\r
}\r
+ return 0;\r
}\r
\r
0x00, 0x00 // AEN holdoff period.\r
};\r
\r
+// Allow Apple 68k Drive Setup to format this drive.\r
+// Code\r
+// TODO make this string configurable.\r
+static const uint8 AppleVendorPage[] =\r
+{\r
+0x30, // Page code\r
+28, // Page length\r
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,\r
+'A','P','P','L','E',' ','C','O','M','P','U','T','E','R',',',' ','I','N','C','.'\r
+};\r
+\r
static void pageIn(int pc, int dataIdx, const uint8* pageData, int pageLen)\r
{\r
memcpy(&scsiDev.data[dataIdx], pageData, pageLen);\r
idx += sizeof(ControlModePage);\r
break;\r
\r
+ case 0x30:\r
+ pageIn(pc, idx, AppleVendorPage, sizeof(AppleVendorPage));\r
+ idx += sizeof(AppleVendorPage);\r
+ break;\r
+ \r
default:\r
// Unknown Page Code\r
pageFound = 0;\r
scsiEnterPhase(MESSAGE_IN);\r
scsiWrite(scsiDev.msgIn);\r
\r
- scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);\r
-\r
-\r
if (scsiDev.atnFlag)\r
{\r
// If there was a parity error, we go\r
{\r
scsiWrite(scsiDev.data[scsiDev.dataPtr]);\r
++scsiDev.dataPtr;\r
-\r
- // scsiWrite will update resetFlag.\r
- scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);\r
}\r
\r
if ((scsiDev.dataPtr >= scsiDev.dataLen) &&\r
break;\r
}\r
++scsiDev.dataPtr;\r
-\r
- // scsiRead will update resetFlag.\r
- scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);\r
}\r
\r
if ((scsiDev.dataPtr >= scsiDev.dataLen) &&\r
{\r
enter_Status(GOOD);\r
}\r
-\r
- scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);\r
}\r
\r
static void doReserveRelease()\r
SCSI_ClearPin(SCSI_Out_CD);\r
SCSI_ClearPin(SCSI_Out_IO);\r
\r
- scsiDev.resetFlag = 0;\r
- scsiDev.atnFlag = 0;\r
scsiDev.parityError = 0;\r
scsiDev.phase = BUS_FREE;\r
\r
do\r
{\r
CyDelay(10); // 10ms.\r
- reset = SCSI_ReadPin(SCSI_In_RST);\r
+ reset = SCSI_ReadPin(SCSI_RST_INT);\r
} while (reset);\r
+ \r
+ scsiDev.resetFlag = 0;\r
+ scsiDev.atnFlag = 0; \r
}\r
\r
static void enter_SelectionPhase()\r
{\r
-\r
- scsiDev.atnFlag = 0;\r
+ // Ignore stale versions of this flag, but ensure we know the\r
+ // current value if the flag is still set.\r
+ scsiDev.atnFlag = SCSI_ReadPin(SCSI_ATN_INT);\r
scsiDev.parityError = 0;\r
scsiDev.dataPtr = 0;\r
scsiDev.savedDataPtr = 0;\r
uint8 mask = ~SCSI_In_DBx_Read();\r
int goodParity = (Lookup_OddParity[mask] == SCSI_ReadPin(SCSI_In_DBP));\r
\r
- scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);\r
int sel = SCSI_ReadPin(SCSI_In_SEL);\r
int bsy = SCSI_ReadPin(SCSI_In_BSY);\r
if (!bsy && sel &&\r
ledOn();\r
\r
// Wait until the end of the selection phase.\r
- // Keep checking the ATN flag, as the initiator may assert it at any\r
- // time before releasing SEL.\r
while (!scsiDev.resetFlag)\r
{\r
- scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);\r
if (!SCSI_ReadPin(SCSI_In_SEL))\r
{\r
break;\r
}\r
- scsiDev.resetFlag = SCSI_ReadPin(SCSI_In_RST);\r
}\r
\r
// Save our initiator now that we're no longer in a time-critical\r
{\r
scsiDev.phase = BUS_BUSY;\r
}\r
-\r
- scsiDev.resetFlag = scsiDev.resetFlag || SCSI_ReadPin(SCSI_In_RST);\r
}\r
\r
static void process_MessageOut()\r
{\r
- scsiDev.atnFlag = 0;\r
scsiEnterPhase(MESSAGE_OUT);\r
\r
+ scsiDev.atnFlag = 0;\r
scsiDev.parityError = 0;\r
scsiDev.msgOut = scsiRead();\r
\r
// Skip the remaining message bytes, and then start the MESSAGE_OUT\r
// phase again from the start. The initiator will re-send the\r
// same set of messages.\r
- while (SCSI_ReadPin(SCSI_In_ATN) && !scsiDev.resetFlag)\r
+ while (SCSI_ReadPin(SCSI_ATN_INT) && !scsiDev.resetFlag)\r
{\r
scsiRead();\r
- scsiDev.resetFlag = scsiDev.resetFlag || SCSI_ReadPin(SCSI_In_RST);\r
}\r
\r
// Go-back and try the message again.\r
{\r
enter_MessageIn(MSG_REJECT);\r
}\r
-\r
- // atnFlag will be forced to 1 if there was a parity error.\r
- scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);\r
+ \r
+ // Re-check the ATN flag. We won't get another interrupt if\r
+ // it stays asserted.\r
+ scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);\r
}\r
\r
\r
+// TODO remove.\r
+// This is a hack until I work out why the ATN ISR isn't\r
+// running when it should.\r
+static int atnErrCount = 0;\r
+static void checkATN()\r
+{\r
+ int atn = SCSI_ReadPin(SCSI_ATN_INT);\r
+ if (atn && !scsiDev.atnFlag)\r
+ {\r
+ atnErrCount++;\r
+ scsiDev.atnFlag = 1;\r
+ }\r
+}\r
+\r
void scsiPoll(void)\r
{\r
- if (scsiDev.resetFlag || SCSI_ReadPin(SCSI_In_RST))\r
+ if (scsiDev.resetFlag)\r
{\r
scsiReset();\r
}\r
break;\r
\r
case COMMAND:\r
+ checkATN();\r
if (scsiDev.atnFlag)\r
{\r
process_MessageOut();\r
break;\r
\r
case DATA_IN:\r
+ checkATN();\r
if (scsiDev.atnFlag)\r
{\r
process_MessageOut();\r
break;\r
\r
case DATA_OUT:\r
+ checkATN();\r
if (scsiDev.atnFlag)\r
{\r
process_MessageOut();\r
else\r
{\r
process_DataOut();\r
- } \r
+ }\r
break;\r
\r
case STATUS:\r
+ checkATN();\r
if (scsiDev.atnFlag)\r
{\r
process_MessageOut();\r
break;\r
\r
case MESSAGE_IN:\r
+ checkATN();\r
if (scsiDev.atnFlag)\r
{\r
process_MessageOut();\r
// Set to true (1) if the ATN flag was set, and we need to
// enter the MESSAGE_OUT phase.
- int atnFlag;
+ volatile int atnFlag;
// Set to true (1) if the RST flag was set.
- int resetFlag;
+ volatile int resetFlag;
// Set to true (1) if a parity error was observed.
int parityError;
#include "scsiPhy.h"\r
#include "bits.h"\r
\r
+CY_ISR_PROTO(scsiResetISR);\r
+CY_ISR(scsiResetISR)\r
+{\r
+ scsiDev.resetFlag = 1;\r
+ SCSI_RST_ClearInterrupt();\r
+}\r
+\r
+CY_ISR_PROTO(scsiAttentionISR);\r
+CY_ISR(scsiAttentionISR)\r
+{\r
+ scsiDev.atnFlag = 1;\r
+ // Not needed when using pin value for interrupt SCSI_ATN_ClearInterrupt();\r
+}\r
+\r
// Spins until the SCSI pin is true, or the reset flag is set.\r
-static void waitForPinTrue(int pin)\r
+static inline void waitForPinTrue(int pin)\r
{\r
- while (!scsiDev.resetFlag)\r
+ int finished = SCSI_ReadPin(pin);\r
+ while (!finished && !scsiDev.resetFlag)\r
{\r
- // TODO put some hardware gates in front of the RST pin, and store\r
- // the state in a register. The minimum "Reset hold time" is 25us, which\r
- // we can easily satisfy within this loop, but perhaps hard to satisfy\r
- // if we don't call this function often.\r
- scsiDev.resetFlag = SCSI_ReadPin(SCSI_In_RST);\r
-\r
- if (SCSI_ReadPin(pin))\r
- {\r
- break;\r
- }\r
+ finished = SCSI_ReadPin(pin);\r
}\r
}\r
\r
// Spins until the SCSI pin is true, or the reset flag is set.\r
-static void waitForPinFalse(int pin)\r
+static inline void waitForPinFalse(int pin)\r
{\r
- while (!scsiDev.resetFlag)\r
+ int finished = !SCSI_ReadPin(pin);\r
+ while (!finished && !scsiDev.resetFlag)\r
{\r
- // TODO put some hardware gates in front of the RST pin, and store\r
- // the state in a register. The minimum "Reset hold time" is 25us, which\r
- // we can easily satisfy within this loop, but perhaps hard to satisfy\r
- // if we don't call this function often.\r
- scsiDev.resetFlag = SCSI_ReadPin(SCSI_In_RST);\r
-\r
- if (!SCSI_ReadPin(pin))\r
- {\r
- break;\r
- }\r
+ finished = !SCSI_ReadPin(pin);\r
}\r
}\r
\r
-static void deskewDelay(void)\r
+static inline void deskewDelay(void)\r
{\r
// Delay for deskew + cable skew. total 55 nanoseconds.\r
// Assumes 66MHz.\r
busSettleDelay();\r
}\r
\r
+void scsiPhyInit()\r
+{\r
+ SCSI_RST_ISR_StartEx(scsiResetISR);\r
+ SCSI_ATN_ISR_StartEx(scsiAttentionISR);\r
+ \r
+ // Interrupts may have already been directed to the (empty)\r
+ // standard ISR generated by PSoC Creator.\r
+ SCSI_RST_ClearInterrupt();\r
+ // Not needed for pin level interrupt SCSI_ATN_ClearInterrupt(); \r
+}
\ No newline at end of file
// Contains the odd-parity flag for a given 8-bit value.
extern const uint8 Lookup_OddParity[256];
+void scsiPhyInit();
uint8 scsiRead(void);
void scsiWrite(uint8 value);
return SDCard_ReadRxData();\r
}\r
\r
-static void sdSendCommand(uint8 cmd, uint32 param)\r
+static void sdSendCRCCommand(uint8 cmd, uint32 param)\r
{\r
uint8 send[6];\r
\r
}\r
}\r
\r
+static void sdSendCommand(uint8 cmd, uint32 param)\r
+{\r
+ uint8 send[6];\r
+\r
+ send[0] = cmd | 0x40;\r
+ send[1] = param >> 24;\r
+ send[2] = param >> 16;\r
+ send[3] = param >> 8;\r
+ send[4] = param;\r
+ send[5] = 0;\r
+\r
+ for(cmd = 0; cmd < sizeof(send); cmd++)\r
+ {\r
+ sdSpiByte(send[cmd]);\r
+ }\r
+}\r
+\r
static uint8 sdReadResp()\r
{\r
uint8 v;\r
return sdReadResp();\r
}\r
\r
+static uint8 sdCRCCommandAndResponse(uint8 cmd, uint32 param)\r
+{\r
+ SDCard_ClearRxBuffer();\r
+ sdSpiByte(0xFF);\r
+ sdSendCRCCommand(cmd, param);\r
+ return sdReadResp();\r
+}\r
+\r
\r
void sdPrepareRead(int nextBlockOffset)\r
{\r
\r
while(!(SDCard_ReadTxStatus() & SDCard_STS_SPI_DONE))\r
{}\r
- \r
+ }\r
+ \r
SDCard_ReadRxData();\r
SDCard_ReadRxData();\r
SDCard_ReadRxData();\r
SDCard_ReadRxData();\r
- }\r
\r
sdSpiByte(0x00); // CRC\r
sdSpiByte(0x00); // CRC\r
\r
do\r
{\r
- uint8 status = sdCommandAndResponse(SD_SEND_IF_COND, 0x000001AA);\r
+ uint8 status = sdCRCCommandAndResponse(SD_SEND_IF_COND, 0x000001AA);\r
\r
if (status == SD_R1_IDLE)\r
{\r
{\r
CyDelay(33); // Spec says to retry for 1 second.\r
\r
- sdCommandAndResponse(SD_APP_CMD, 0);\r
+ sdCRCCommandAndResponse(SD_APP_CMD, 0);\r
// Host Capacity Support = 1 (SDHC/SDXC supported)\r
- status = sdCommandAndResponse(SD_APP_SEND_OP_COND, 0x40000000);\r
+ status = sdCRCCommandAndResponse(SD_APP_SEND_OP_COND, 0x40000000);\r
} while ((status != 0) && (--retries > 0));\r
\r
return retries > 0;\r
\r
static int sdReadOCR()\r
{\r
- uint8 status = sdCommandAndResponse(SD_READ_OCR, 0);\r
+ uint8 status = sdCRCCommandAndResponse(SD_READ_OCR, 0);\r
if(status){goto bad;}\r
\r
uint8 buf[4];\r
\r
static int sdReadCSD()\r
{\r
- uint8 status = sdCommandAndResponse(SD_SEND_CSD, 0);\r
+ uint8 status = sdCRCCommandAndResponse(SD_SEND_CSD, 0);\r
if(status){goto bad;}\r
status = sdWaitResp();\r
if (status != 0xFE) { goto bad; }\r
SD_CS_Write(0); // Set CS active (active low)\r
CyDelayUs(1);\r
\r
- uint8 v = sdCommandAndResponse(SD_GO_IDLE_STATE, 0);\r
+ uint8 v = sdCRCCommandAndResponse(SD_GO_IDLE_STATE, 0);\r
if(v != 1){goto bad;}\r
\r
if (!sendIfCond()) goto bad; // Sets V1 or V2 flag\r
\r
// This command will be ignored if sdDev.ccs is set.\r
// SDHC and SDXC are always 512bytes.\r
- v = sdCommandAndResponse(SD_SET_BLOCKLEN, SCSI_BLOCK_SIZE); //Force sector size\r
+ v = sdCRCCommandAndResponse(SD_SET_BLOCKLEN, SCSI_BLOCK_SIZE); //Force sector size\r
if(v){goto bad;}\r
- v = sdCommandAndResponse(SD_CRC_ON_OFF, 0); //crc off\r
+ v = sdCRCCommandAndResponse(SD_CRC_ON_OFF, 0); //crc off\r
if(v){goto bad;}\r
\r
// now set the sd card up for full speed\r
projects / SCSI2SD.git / commitdiff