-20150x0x 4.5
+20151105 4.5
- Fix bug in SCSI MODE SENSE that returned the wrong mode type
- Fixes CDROM emulation
- Added selection delay parameter. This should be set to 1ms for older
1 spare sector per cylinder
2051459 usable sectors on volume
Apollo 400/425s running DOMAIN/OS
+ Motorola System V/68 R3V7 and R3V8.
+ Since the installation have information about limited number of drives(most of them with custom commands) it requires a pre-installed disk image to be dd-ed on it. Works with MVME167 and MVME177
+ Motorola System V/88 R40V4.0 through R40V4.4
+ It requires to describe the disk into a configuration file. The process is described here - http://m88k.com/howto-001.html
Samplers
May require scsi2sd-config --apple flag
Yamaha A5000, A3000, EX5, EX5R
EMU ESI4000
+ Synclavier 9600.
+ Disable Parity. Max size == 9GB.
+
Other
// Optional bootup delay\r
int delaySeconds = 0;\r
while (delaySeconds < scsiDev.boardCfg.startupDelay) {\r
- CyDelay(1000);\r
+ // Keep the USB connection working, otherwise it's very hard to revert\r
+ // silly extra-long startup delay settings.\r
+ int i;\r
+ for (i = 0; i < 200; i++) {\r
+ CyDelay(5);\r
+ scsiDev.watchdogTick++;\r
+ configPoll();\r
+ }\r
++delaySeconds;\r
}\r
\r
uint32_t lastSDPoll = getTime_ms();\r
sdCheckPresent();\r
\r
-\r
while (1)\r
{\r
scsiDev.watchdogTick++;\r
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB07_ST\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__2__POS 2\r
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB08_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB08_ST\r
\r
/* SD_SCK */\r
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB05_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB05_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL\r
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB05_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK\r
\r
/* SCSI_Out_Ctl */\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK\r
\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
#define scsiTarget_StatusReg__0__POS 0\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__2__POS 2\r
#define scsiTarget_StatusReg__3__MASK 0x08u\r
#define scsiTarget_StatusReg__4__MASK 0x10u\r
#define scsiTarget_StatusReg__4__POS 4\r
#define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB02_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB02_ST\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST\r
\r
/* Debug_Timer_Interrupt */\r
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST\r
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST\r
\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST\r
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB04_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB04_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB09_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB09_ST\r
\r
/* Miscellaneous */\r
#define BCLK__BUS_CLK__HZ 50000000U\r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 41u\r
+#define CY_CFG_BASE_ADDR_COUNT 42u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
0x40004501u, /* Base address: 0x40004500 Count: 1 */\r
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
0x4000520Bu, /* Base address: 0x40005200 Count: 11 */\r
- 0x40006402u, /* Base address: 0x40006400 Count: 2 */\r
- 0x40010037u, /* Base address: 0x40010000 Count: 55 */\r
- 0x4001013Cu, /* Base address: 0x40010100 Count: 60 */\r
- 0x40010245u, /* Base address: 0x40010200 Count: 69 */\r
+ 0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
+ 0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
+ 0x4001003Du, /* Base address: 0x40010000 Count: 61 */\r
+ 0x40010138u, /* Base address: 0x40010100 Count: 56 */\r
+ 0x40010248u, /* Base address: 0x40010200 Count: 72 */\r
0x40010356u, /* Base address: 0x40010300 Count: 86 */\r
- 0x40010455u, /* Base address: 0x40010400 Count: 85 */\r
- 0x40010555u, /* Base address: 0x40010500 Count: 85 */\r
- 0x4001064Bu, /* Base address: 0x40010600 Count: 75 */\r
- 0x40010756u, /* Base address: 0x40010700 Count: 86 */\r
- 0x40010922u, /* Base address: 0x40010900 Count: 34 */\r
- 0x40010A4Eu, /* Base address: 0x40010A00 Count: 78 */\r
- 0x40010B51u, /* Base address: 0x40010B00 Count: 81 */\r
- 0x40010C53u, /* Base address: 0x40010C00 Count: 83 */\r
- 0x40010D59u, /* Base address: 0x40010D00 Count: 89 */\r
- 0x40010E50u, /* Base address: 0x40010E00 Count: 80 */\r
- 0x40010F40u, /* Base address: 0x40010F00 Count: 64 */\r
- 0x40011454u, /* Base address: 0x40011400 Count: 84 */\r
- 0x40011548u, /* Base address: 0x40011500 Count: 72 */\r
- 0x4001164Fu, /* Base address: 0x40011600 Count: 79 */\r
+ 0x40010445u, /* Base address: 0x40010400 Count: 69 */\r
+ 0x4001054Au, /* Base address: 0x40010500 Count: 74 */\r
+ 0x4001064Eu, /* Base address: 0x40010600 Count: 78 */\r
+ 0x4001074Fu, /* Base address: 0x40010700 Count: 79 */\r
+ 0x40010856u, /* Base address: 0x40010800 Count: 86 */\r
+ 0x40010954u, /* Base address: 0x40010900 Count: 84 */\r
+ 0x40010A4Cu, /* Base address: 0x40010A00 Count: 76 */\r
+ 0x40010B4Bu, /* Base address: 0x40010B00 Count: 75 */\r
+ 0x40010C51u, /* Base address: 0x40010C00 Count: 81 */\r
+ 0x40010D56u, /* Base address: 0x40010D00 Count: 86 */\r
+ 0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */\r
+ 0x40010F42u, /* Base address: 0x40010F00 Count: 66 */\r
+ 0x4001145Eu, /* Base address: 0x40011400 Count: 94 */\r
+ 0x4001154Au, /* Base address: 0x40011500 Count: 74 */\r
+ 0x40011650u, /* Base address: 0x40011600 Count: 80 */\r
0x4001174Au, /* Base address: 0x40011700 Count: 74 */\r
- 0x4001184Eu, /* Base address: 0x40011800 Count: 78 */\r
- 0x40011943u, /* Base address: 0x40011900 Count: 67 */\r
- 0x40011A04u, /* Base address: 0x40011A00 Count: 4 */\r
- 0x40011B0Fu, /* Base address: 0x40011B00 Count: 15 */\r
- 0x40014017u, /* Base address: 0x40014000 Count: 23 */\r
- 0x4001411Du, /* Base address: 0x40014100 Count: 29 */\r
- 0x40014215u, /* Base address: 0x40014200 Count: 21 */\r
- 0x4001430Eu, /* Base address: 0x40014300 Count: 14 */\r
+ 0x40011804u, /* Base address: 0x40011800 Count: 4 */\r
+ 0x40011913u, /* Base address: 0x40011900 Count: 19 */\r
+ 0x40011B0Cu, /* Base address: 0x40011B00 Count: 12 */\r
+ 0x4001401Bu, /* Base address: 0x40014000 Count: 27 */\r
+ 0x4001411Au, /* Base address: 0x40014100 Count: 26 */\r
+ 0x40014213u, /* Base address: 0x40014200 Count: 19 */\r
+ 0x4001430Au, /* Base address: 0x40014300 Count: 10 */\r
0x4001440Eu, /* Base address: 0x40014400 Count: 14 */\r
- 0x40014514u, /* Base address: 0x40014500 Count: 20 */\r
- 0x40014610u, /* Base address: 0x40014600 Count: 16 */\r
- 0x40014710u, /* Base address: 0x40014700 Count: 16 */\r
- 0x40014809u, /* Base address: 0x40014800 Count: 9 */\r
- 0x4001490Cu, /* Base address: 0x40014900 Count: 12 */\r
- 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */\r
- 0x40014D05u, /* Base address: 0x40014D00 Count: 5 */\r
- 0x40015006u, /* Base address: 0x40015000 Count: 6 */\r
+ 0x4001451Bu, /* Base address: 0x40014500 Count: 27 */\r
+ 0x4001460Cu, /* Base address: 0x40014600 Count: 12 */\r
+ 0x4001470Fu, /* Base address: 0x40014700 Count: 15 */\r
+ 0x40014807u, /* Base address: 0x40014800 Count: 7 */\r
+ 0x40014909u, /* Base address: 0x40014900 Count: 9 */\r
+ 0x40014C03u, /* Base address: 0x40014C00 Count: 3 */\r
+ 0x40014D03u, /* Base address: 0x40014D00 Count: 3 */\r
+ 0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
{0x0Au, 0x36u},\r
- {0x00u, 0x13u},\r
- {0x01u, 0x06u},\r
+ {0x00u, 0x05u},\r
+ {0x01u, 0x13u},\r
{0x18u, 0x08u},\r
{0x1Cu, 0x71u},\r
- {0x20u, 0xA0u},\r
- {0x21u, 0xC8u},\r
+ {0x20u, 0x50u},\r
+ {0x21u, 0x90u},\r
{0x2Cu, 0x0Eu},\r
- {0x30u, 0x05u},\r
- {0x31u, 0x03u},\r
+ {0x30u, 0x0Cu},\r
+ {0x31u, 0x09u},\r
{0x34u, 0x80u},\r
{0x7Cu, 0x40u},\r
{0x20u, 0x01u},\r
{0x87u, 0x0Fu},\r
- {0x06u, 0x07u},\r
- {0x08u, 0xAAu},\r
- {0x0Au, 0x55u},\r
- {0x0Cu, 0x99u},\r
- {0x0Eu, 0x22u},\r
- {0x10u, 0x44u},\r
- {0x12u, 0x88u},\r
- {0x17u, 0x01u},\r
- {0x1Au, 0x70u},\r
- {0x26u, 0x80u},\r
- {0x2Au, 0x08u},\r
- {0x31u, 0x01u},\r
- {0x32u, 0x0Fu},\r
- {0x34u, 0xF0u},\r
+ {0x00u, 0x20u},\r
+ {0x02u, 0x40u},\r
+ {0x03u, 0x04u},\r
+ {0x04u, 0x01u},\r
+ {0x05u, 0x08u},\r
+ {0x08u, 0x0Au},\r
+ {0x09u, 0x09u},\r
+ {0x0Au, 0x35u},\r
+ {0x0Bu, 0x72u},\r
+ {0x0Cu, 0x48u},\r
+ {0x0Eu, 0x36u},\r
+ {0x10u, 0x07u},\r
+ {0x11u, 0x01u},\r
+ {0x12u, 0x18u},\r
+ {0x13u, 0x66u},\r
+ {0x14u, 0x4Fu},\r
+ {0x16u, 0x30u},\r
+ {0x17u, 0x7Fu},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Du, 0x62u},\r
+ {0x1Eu, 0x02u},\r
+ {0x21u, 0x20u},\r
+ {0x22u, 0x20u},\r
+ {0x23u, 0x40u},\r
+ {0x24u, 0x05u},\r
+ {0x25u, 0x74u},\r
+ {0x27u, 0x09u},\r
+ {0x29u, 0x20u},\r
+ {0x2Au, 0x27u},\r
+ {0x2Bu, 0x40u},\r
+ {0x30u, 0x1Fu},\r
+ {0x31u, 0x60u},\r
+ {0x33u, 0x1Fu},\r
+ {0x36u, 0x60u},\r
+ {0x3Au, 0x82u},\r
+ {0x3Bu, 0x02u},\r
{0x40u, 0x32u},\r
{0x41u, 0x04u},\r
- {0x42u, 0x50u},\r
- {0x45u, 0xEFu},\r
- {0x46u, 0xDCu},\r
- {0x47u, 0x02u},\r
+ {0x42u, 0x10u},\r
+ {0x45u, 0x2Du},\r
+ {0x46u, 0xFCu},\r
+ {0x47u, 0x0Eu},\r
{0x48u, 0x1Fu},\r
{0x49u, 0xFFu},\r
{0x4Au, 0xFFu},\r
{0x59u, 0x04u},\r
{0x5Au, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x91u},\r
+ {0x5Cu, 0x11u},\r
{0x5Du, 0x01u},\r
{0x5Fu, 0x01u},\r
{0x60u, 0x08u},\r
{0x68u, 0x40u},\r
{0x69u, 0x40u},\r
{0x6Eu, 0x08u},\r
- {0x83u, 0x08u},\r
+ {0x02u, 0x04u},\r
+ {0x03u, 0x91u},\r
+ {0x04u, 0x30u},\r
+ {0x0Au, 0x80u},\r
+ {0x0Bu, 0x11u},\r
+ {0x11u, 0x10u},\r
+ {0x12u, 0xA8u},\r
+ {0x1Au, 0x80u},\r
+ {0x1Bu, 0x80u},\r
+ {0x20u, 0x30u},\r
+ {0x23u, 0x90u},\r
+ {0x28u, 0x48u},\r
+ {0x2Au, 0x04u},\r
+ {0x2Bu, 0x10u},\r
+ {0x32u, 0x88u},\r
+ {0x33u, 0x11u},\r
+ {0x38u, 0x10u},\r
+ {0x3Bu, 0x05u},\r
+ {0x40u, 0x10u},\r
+ {0x42u, 0x04u},\r
+ {0x43u, 0x81u},\r
+ {0x4Au, 0x20u},\r
+ {0x4Bu, 0x05u},\r
+ {0x50u, 0x80u},\r
+ {0x53u, 0x28u},\r
+ {0x58u, 0x40u},\r
+ {0x59u, 0x20u},\r
+ {0x5Au, 0x02u},\r
+ {0x5Bu, 0x84u},\r
+ {0x60u, 0x04u},\r
+ {0x61u, 0x49u},\r
+ {0x69u, 0x84u},\r
+ {0x6Au, 0x20u},\r
+ {0x6Bu, 0x40u},\r
+ {0x71u, 0x80u},\r
+ {0x72u, 0x88u},\r
+ {0x73u, 0x20u},\r
+ {0x80u, 0x80u},\r
+ {0x81u, 0xC0u},\r
+ {0x85u, 0x04u},\r
+ {0x8Au, 0x08u},\r
+ {0x8Eu, 0x10u},\r
+ {0x8Fu, 0x22u},\r
+ {0xC0u, 0x0Fu},\r
+ {0xC2u, 0x0Du},\r
+ {0xC4u, 0x0Eu},\r
+ {0xCAu, 0x07u},\r
+ {0xCCu, 0x0Fu},\r
+ {0xCEu, 0x07u},\r
+ {0xD0u, 0x0Fu},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x0Fu},\r
+ {0xE0u, 0x05u},\r
+ {0xE2u, 0x02u},\r
+ {0xE4u, 0x03u},\r
+ {0xE6u, 0x08u},\r
+ {0x00u, 0x96u},\r
+ {0x02u, 0x69u},\r
+ {0x04u, 0x55u},\r
+ {0x05u, 0x33u},\r
+ {0x06u, 0xAAu},\r
+ {0x07u, 0xCCu},\r
+ {0x0Au, 0xFFu},\r
+ {0x0Bu, 0xFFu},\r
+ {0x0Cu, 0x33u},\r
+ {0x0Du, 0x0Fu},\r
+ {0x0Eu, 0xCCu},\r
+ {0x0Fu, 0xF0u},\r
+ {0x13u, 0xFFu},\r
+ {0x14u, 0x0Fu},\r
+ {0x16u, 0xF0u},\r
+ {0x17u, 0xFFu},\r
+ {0x18u, 0xFFu},\r
+ {0x1Du, 0xFFu},\r
+ {0x1Eu, 0xFFu},\r
+ {0x25u, 0xFFu},\r
+ {0x29u, 0x55u},\r
+ {0x2Au, 0xFFu},\r
+ {0x2Bu, 0xAAu},\r
+ {0x2Cu, 0xFFu},\r
+ {0x2Du, 0x69u},\r
+ {0x2Fu, 0x96u},\r
+ {0x32u, 0xFFu},\r
+ {0x37u, 0xFFu},\r
+ {0x3Au, 0x08u},\r
+ {0x3Bu, 0x80u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x11u},\r
+ {0x5Fu, 0x01u},\r
+ {0x80u, 0xE0u},\r
+ {0x84u, 0x40u},\r
+ {0x86u, 0x80u},\r
+ {0x89u, 0x44u},\r
+ {0x8Au, 0xFFu},\r
+ {0x8Bu, 0x88u},\r
+ {0x8Cu, 0x06u},\r
+ {0x8Eu, 0xF8u},\r
{0x8Fu, 0x80u},\r
- {0x93u, 0x70u},\r
+ {0x91u, 0x99u},\r
+ {0x93u, 0x22u},\r
+ {0x94u, 0x01u},\r
{0x97u, 0x07u},\r
+ {0x98u, 0xC6u},\r
+ {0x9Au, 0x19u},\r
+ {0x9Bu, 0x70u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Eu, 0x80u},\r
+ {0x9Fu, 0x08u},\r
+ {0xA0u, 0x14u},\r
{0xA5u, 0xAAu},\r
+ {0xA6u, 0x09u},\r
{0xA7u, 0x55u},\r
- {0xA9u, 0x44u},\r
- {0xABu, 0x88u},\r
- {0xADu, 0x99u},\r
- {0xAFu, 0x22u},\r
+ {0xA8u, 0x09u},\r
+ {0xAAu, 0xF2u},\r
{0xB3u, 0x0Fu},\r
- {0xB7u, 0xF0u},\r
+ {0xB4u, 0x3Fu},\r
+ {0xB5u, 0xF0u},\r
+ {0xB6u, 0xC0u},\r
+ {0xBAu, 0x80u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x10u},\r
+ {0xDCu, 0x11u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x18u},\r
+ {0x01u, 0x10u},\r
+ {0x02u, 0x90u},\r
{0x03u, 0x01u},\r
- {0x08u, 0x01u},\r
- {0x09u, 0x20u},\r
- {0x0Au, 0x08u},\r
- {0x10u, 0x28u},\r
- {0x18u, 0x20u},\r
- {0x19u, 0x08u},\r
- {0x1Au, 0x08u},\r
- {0x20u, 0x40u},\r
- {0x26u, 0x88u},\r
- {0x27u, 0x02u},\r
- {0x2Du, 0x04u},\r
- {0x2Eu, 0x80u},\r
- {0x2Fu, 0x28u},\r
- {0x33u, 0x04u},\r
- {0x35u, 0x04u},\r
- {0x36u, 0x08u},\r
- {0x37u, 0x02u},\r
- {0x3Du, 0x40u},\r
- {0x3Eu, 0x02u},\r
- {0x41u, 0x08u},\r
- {0x42u, 0x80u},\r
- {0x43u, 0x29u},\r
- {0x4Au, 0x50u},\r
- {0x4Bu, 0x80u},\r
- {0x50u, 0x80u},\r
- {0x52u, 0x20u},\r
- {0x53u, 0x04u},\r
- {0x5Au, 0x25u},\r
- {0x5Bu, 0x40u},\r
- {0x5Du, 0x80u},\r
- {0x5Eu, 0x0Au},\r
- {0x5Fu, 0x20u},\r
+ {0x04u, 0x20u},\r
+ {0x05u, 0x04u},\r
+ {0x06u, 0x40u},\r
+ {0x07u, 0x02u},\r
+ {0x09u, 0x04u},\r
+ {0x0Au, 0x06u},\r
+ {0x0Eu, 0x26u},\r
+ {0x10u, 0x80u},\r
+ {0x12u, 0x20u},\r
+ {0x13u, 0x18u},\r
+ {0x15u, 0x90u},\r
+ {0x1Au, 0x06u},\r
+ {0x1Bu, 0x30u},\r
+ {0x1Eu, 0x20u},\r
+ {0x21u, 0x20u},\r
+ {0x22u, 0x04u},\r
+ {0x24u, 0x02u},\r
+ {0x25u, 0x40u},\r
+ {0x2Bu, 0x10u},\r
+ {0x2Eu, 0x20u},\r
+ {0x2Fu, 0x21u},\r
+ {0x31u, 0x20u},\r
+ {0x32u, 0x04u},\r
+ {0x33u, 0x41u},\r
+ {0x36u, 0x89u},\r
+ {0x37u, 0x01u},\r
+ {0x38u, 0x20u},\r
+ {0x3Au, 0x80u},\r
+ {0x3Du, 0x80u},\r
+ {0x3Fu, 0x18u},\r
+ {0x58u, 0x10u},\r
+ {0x5Bu, 0x80u},\r
+ {0x5Cu, 0x50u},\r
+ {0x5Du, 0x09u},\r
{0x60u, 0x08u},\r
- {0x61u, 0x40u},\r
- {0x63u, 0x50u},\r
- {0x64u, 0x02u},\r
- {0x69u, 0x61u},\r
- {0x6Bu, 0x10u},\r
- {0x70u, 0x28u},\r
- {0x72u, 0x42u},\r
- {0x80u, 0x02u},\r
- {0x81u, 0x02u},\r
- {0x84u, 0x08u},\r
- {0x86u, 0x20u},\r
- {0x8Bu, 0x24u},\r
- {0x8Eu, 0x10u},\r
- {0xC0u, 0x07u},\r
- {0xC2u, 0x0Au},\r
- {0xC4u, 0x06u},\r
- {0xCAu, 0x70u},\r
- {0xCCu, 0xC2u},\r
- {0xCEu, 0x90u},\r
- {0xD0u, 0x07u},\r
- {0xD2u, 0x08u},\r
- {0xD6u, 0xFFu},\r
- {0xD8u, 0x1Fu},\r
- {0xE4u, 0x06u},\r
- {0xE6u, 0x09u},\r
- {0x04u, 0x24u},\r
+ {0x62u, 0x40u},\r
+ {0x63u, 0x08u},\r
+ {0x65u, 0x80u},\r
+ {0x81u, 0x08u},\r
+ {0x82u, 0x40u},\r
+ {0x83u, 0x80u},\r
+ {0x85u, 0x20u},\r
+ {0x87u, 0x08u},\r
+ {0x89u, 0x20u},\r
+ {0x8Bu, 0x80u},\r
+ {0x8Cu, 0x40u},\r
+ {0x8Eu, 0x04u},\r
+ {0x90u, 0x20u},\r
+ {0x91u, 0x10u},\r
+ {0x93u, 0x10u},\r
+ {0x94u, 0x04u},\r
+ {0x96u, 0x06u},\r
+ {0x98u, 0x04u},\r
+ {0x9Au, 0x80u},\r
+ {0x9Bu, 0x42u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Du, 0x61u},\r
+ {0x9Fu, 0x15u},\r
+ {0xA0u, 0x80u},\r
+ {0xA2u, 0x28u},\r
+ {0xA3u, 0x08u},\r
+ {0xA5u, 0x08u},\r
+ {0xA6u, 0x80u},\r
+ {0xA7u, 0x10u},\r
+ {0xAAu, 0x40u},\r
+ {0xACu, 0x10u},\r
+ {0xAEu, 0x04u},\r
+ {0xB0u, 0x04u},\r
+ {0xB3u, 0x20u},\r
+ {0xB6u, 0x28u},\r
+ {0xC0u, 0xFFu},\r
+ {0xC2u, 0xE7u},\r
+ {0xC4u, 0xCEu},\r
+ {0xCAu, 0x72u},\r
+ {0xCCu, 0xDFu},\r
+ {0xCEu, 0x7Cu},\r
+ {0xD6u, 0xFCu},\r
+ {0xD8u, 0x1Cu},\r
+ {0xE0u, 0x08u},\r
+ {0xE6u, 0x03u},\r
+ {0xE8u, 0x0Au},\r
+ {0xEAu, 0x10u},\r
+ {0xEEu, 0x06u},\r
+ {0x01u, 0x02u},\r
+ {0x02u, 0x02u},\r
+ {0x03u, 0x01u},\r
{0x05u, 0x01u},\r
- {0x06u, 0x08u},\r
- {0x09u, 0x07u},\r
- {0x0Bu, 0x18u},\r
- {0x0Cu, 0x01u},\r
- {0x0Du, 0x2Fu},\r
- {0x0Eu, 0x02u},\r
- {0x0Fu, 0x10u},\r
- {0x13u, 0x07u},\r
- {0x19u, 0x05u},\r
- {0x1Au, 0x20u},\r
- {0x1Eu, 0x1Du},\r
- {0x23u, 0x20u},\r
- {0x24u, 0x28u},\r
- {0x25u, 0x2Au},\r
- {0x26u, 0x14u},\r
- {0x27u, 0x15u},\r
- {0x2Au, 0x02u},\r
- {0x2Bu, 0x02u},\r
- {0x2Cu, 0x10u},\r
- {0x2Du, 0x28u},\r
- {0x2Eu, 0x20u},\r
- {0x2Fu, 0x16u},\r
+ {0x07u, 0x06u},\r
+ {0x11u, 0x04u},\r
+ {0x13u, 0x08u},\r
+ {0x17u, 0x10u},\r
+ {0x1Eu, 0x01u},\r
+ {0x21u, 0x02u},\r
+ {0x23u, 0x01u},\r
+ {0x29u, 0x02u},\r
+ {0x2Bu, 0x01u},\r
+ {0x2Du, 0x02u},\r
+ {0x2Fu, 0x29u},\r
+ {0x30u, 0x01u},\r
{0x31u, 0x20u},\r
- {0x32u, 0x03u},\r
- {0x35u, 0x1Fu},\r
- {0x36u, 0x3Cu},\r
- {0x3Bu, 0x20u},\r
- {0x3Eu, 0x04u},\r
- {0x3Fu, 0x01u},\r
+ {0x33u, 0x03u},\r
+ {0x34u, 0x02u},\r
+ {0x35u, 0x10u},\r
+ {0x37u, 0x0Cu},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Fu, 0x40u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
{0x5Cu, 0x11u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x83u, 0x80u},\r
- {0x86u, 0x04u},\r
- {0x87u, 0x07u},\r
- {0x89u, 0xAAu},\r
- {0x8Au, 0x08u},\r
- {0x8Bu, 0x55u},\r
- {0x8Cu, 0x2Au},\r
- {0x8Eu, 0x54u},\r
- {0x8Fu, 0x70u},\r
- {0x95u, 0x99u},\r
- {0x96u, 0x02u},\r
- {0x97u, 0x22u},\r
- {0x9Au, 0x20u},\r
- {0x9Bu, 0x08u},\r
- {0x9Eu, 0x10u},\r
- {0xA6u, 0x01u},\r
- {0xAAu, 0x40u},\r
- {0xADu, 0x44u},\r
- {0xAFu, 0x88u},\r
- {0xB0u, 0x18u},\r
- {0xB1u, 0xF0u},\r
- {0xB2u, 0x01u},\r
- {0xB3u, 0x0Fu},\r
- {0xB4u, 0x60u},\r
- {0xB6u, 0x06u},\r
- {0xBEu, 0x51u},\r
+ {0x81u, 0x0Du},\r
+ {0x85u, 0x02u},\r
+ {0x87u, 0x54u},\r
+ {0x8Bu, 0x10u},\r
+ {0x8Cu, 0x02u},\r
+ {0x8Du, 0x02u},\r
+ {0x8Eu, 0x01u},\r
+ {0x8Fu, 0x0Du},\r
+ {0x94u, 0x02u},\r
+ {0x95u, 0x62u},\r
+ {0x96u, 0x09u},\r
+ {0x97u, 0x08u},\r
+ {0x98u, 0x01u},\r
+ {0x99u, 0x01u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Bu, 0x32u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Eu, 0x05u},\r
+ {0xA1u, 0x0Du},\r
+ {0xA5u, 0x0Du},\r
+ {0xA8u, 0x02u},\r
+ {0xA9u, 0x0Du},\r
+ {0xAAu, 0x11u},\r
+ {0xADu, 0x0Du},\r
+ {0xB0u, 0x04u},\r
+ {0xB2u, 0x10u},\r
+ {0xB4u, 0x03u},\r
+ {0xB5u, 0x70u},\r
+ {0xB6u, 0x08u},\r
+ {0xB7u, 0x0Fu},\r
+ {0xBAu, 0x20u},\r
+ {0xBBu, 0x80u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x19u},\r
+ {0xDCu, 0x01u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x20u},\r
- {0x01u, 0x40u},\r
- {0x02u, 0x11u},\r
- {0x06u, 0x01u},\r
- {0x07u, 0x20u},\r
- {0x09u, 0x24u},\r
- {0x0Bu, 0x02u},\r
- {0x0Du, 0x10u},\r
- {0x0Eu, 0x01u},\r
- {0x11u, 0x02u},\r
- {0x12u, 0x04u},\r
- {0x13u, 0x05u},\r
- {0x14u, 0x05u},\r
- {0x15u, 0x04u},\r
- {0x18u, 0x08u},\r
- {0x19u, 0x0Au},\r
- {0x1Bu, 0x80u},\r
- {0x1Eu, 0x11u},\r
- {0x20u, 0x60u},\r
- {0x21u, 0x05u},\r
- {0x25u, 0x11u},\r
- {0x28u, 0x01u},\r
- {0x2Cu, 0x80u},\r
- {0x2Du, 0x04u},\r
- {0x2Eu, 0x80u},\r
- {0x2Fu, 0x04u},\r
- {0x30u, 0x08u},\r
- {0x33u, 0x10u},\r
- {0x36u, 0x23u},\r
- {0x38u, 0x40u},\r
- {0x39u, 0x19u},\r
+ {0x01u, 0x06u},\r
+ {0x03u, 0x20u},\r
+ {0x04u, 0x40u},\r
+ {0x0Au, 0x02u},\r
+ {0x0Eu, 0x1Au},\r
+ {0x14u, 0x08u},\r
+ {0x19u, 0x22u},\r
+ {0x1Cu, 0x40u},\r
+ {0x1Eu, 0x1Au},\r
+ {0x20u, 0x01u},\r
+ {0x21u, 0x45u},\r
+ {0x22u, 0x91u},\r
+ {0x25u, 0x50u},\r
+ {0x28u, 0x02u},\r
+ {0x29u, 0x22u},\r
+ {0x2Cu, 0xA8u},\r
+ {0x2Du, 0x40u},\r
+ {0x30u, 0x02u},\r
+ {0x32u, 0x08u},\r
+ {0x36u, 0x20u},\r
+ {0x37u, 0x08u},\r
+ {0x39u, 0x0Au},\r
+ {0x3Cu, 0x08u},\r
{0x3Du, 0xA0u},\r
- {0x3Fu, 0x08u},\r
- {0x58u, 0x20u},\r
- {0x5Au, 0x80u},\r
- {0x5Cu, 0x06u},\r
- {0x5Eu, 0xA0u},\r
- {0x61u, 0x10u},\r
- {0x62u, 0x40u},\r
- {0x63u, 0x04u},\r
- {0x67u, 0x01u},\r
- {0x80u, 0x04u},\r
- {0x81u, 0x98u},\r
- {0x84u, 0x20u},\r
- {0x86u, 0x20u},\r
- {0x8Au, 0x40u},\r
- {0x8Bu, 0x40u},\r
- {0x8Cu, 0x84u},\r
+ {0x3Eu, 0x02u},\r
+ {0x58u, 0x10u},\r
+ {0x5Au, 0x84u},\r
+ {0x5Eu, 0x40u},\r
+ {0x5Fu, 0x20u},\r
+ {0x60u, 0x02u},\r
+ {0x61u, 0x24u},\r
+ {0x62u, 0x04u},\r
+ {0x64u, 0x08u},\r
+ {0x67u, 0x02u},\r
+ {0x68u, 0x02u},\r
+ {0x6Du, 0x08u},\r
+ {0x6Fu, 0x1Au},\r
+ {0x83u, 0x0Au},\r
+ {0x84u, 0x10u},\r
+ {0x85u, 0x08u},\r
+ {0x86u, 0x04u},\r
+ {0x8Bu, 0x20u},\r
{0x8Du, 0x10u},\r
- {0x8Fu, 0x40u},\r
- {0x90u, 0x20u},\r
- {0x91u, 0x35u},\r
- {0x92u, 0x40u},\r
- {0x93u, 0x08u},\r
- {0x96u, 0x04u},\r
- {0x97u, 0xC0u},\r
- {0x99u, 0x04u},\r
- {0x9Bu, 0x10u},\r
- {0x9Cu, 0x01u},\r
- {0x9Du, 0x82u},\r
- {0x9Eu, 0x80u},\r
- {0x9Fu, 0x04u},\r
- {0xA0u, 0x80u},\r
- {0xA1u, 0x20u},\r
- {0xA2u, 0xF0u},\r
- {0xA5u, 0x08u},\r
- {0xA6u, 0x05u},\r
- {0xADu, 0x40u},\r
- {0xAEu, 0x01u},\r
- {0xB1u, 0x10u},\r
- {0xB3u, 0x30u},\r
- {0xB4u, 0xC0u},\r
- {0xB7u, 0x40u},\r
- {0xC0u, 0xA7u},\r
- {0xC2u, 0xC7u},\r
- {0xC4u, 0xE6u},\r
- {0xCAu, 0xF8u},\r
- {0xCCu, 0xA6u},\r
- {0xCEu, 0x7Fu},\r
- {0xD6u, 0xFCu},\r
- {0xD8u, 0x1Cu},\r
- {0xE2u, 0x0Cu},\r
- {0xE4u, 0x04u},\r
- {0xE6u, 0x2Au},\r
- {0xEAu, 0x08u},\r
- {0xEEu, 0x48u},\r
- {0x00u, 0x40u},\r
- {0x01u, 0x04u},\r
- {0x02u, 0x80u},\r
- {0x05u, 0x30u},\r
- {0x06u, 0x1Cu},\r
- {0x07u, 0x05u},\r
- {0x0Bu, 0x04u},\r
- {0x0Du, 0x04u},\r
- {0x0Eu, 0x43u},\r
- {0x11u, 0x04u},\r
- {0x12u, 0x20u},\r
- {0x14u, 0x03u},\r
- {0x15u, 0x07u},\r
- {0x16u, 0x40u},\r
- {0x17u, 0x18u},\r
- {0x18u, 0x01u},\r
- {0x19u, 0x04u},\r
- {0x1Au, 0x02u},\r
- {0x1Cu, 0x90u},\r
- {0x1Eu, 0x63u},\r
+ {0x90u, 0x22u},\r
+ {0x92u, 0x80u},\r
+ {0x94u, 0x14u},\r
+ {0x95u, 0x89u},\r
+ {0x97u, 0x02u},\r
+ {0x98u, 0x04u},\r
+ {0x9Du, 0x45u},\r
+ {0x9Eu, 0x30u},\r
+ {0x9Fu, 0x15u},\r
+ {0xA2u, 0x10u},\r
+ {0xA3u, 0x20u},\r
+ {0xA5u, 0x0Cu},\r
+ {0xA6u, 0x84u},\r
+ {0xA7u, 0x80u},\r
+ {0xABu, 0x18u},\r
+ {0xACu, 0x10u},\r
+ {0xAEu, 0x04u},\r
+ {0xB1u, 0x84u},\r
+ {0xB3u, 0x01u},\r
+ {0xC0u, 0x88u},\r
+ {0xC2u, 0xE1u},\r
+ {0xC4u, 0x40u},\r
+ {0xCAu, 0xFDu},\r
+ {0xCCu, 0x63u},\r
+ {0xCEu, 0xF3u},\r
+ {0xD6u, 0x3Eu},\r
+ {0xD8u, 0x3Eu},\r
+ {0xE2u, 0x22u},\r
+ {0xE6u, 0x16u},\r
+ {0xECu, 0x09u},\r
+ {0xEEu, 0x06u},\r
+ {0x00u, 0x02u},\r
+ {0x02u, 0x01u},\r
+ {0x05u, 0x34u},\r
+ {0x07u, 0x08u},\r
+ {0x09u, 0x01u},\r
+ {0x0Bu, 0x38u},\r
+ {0x11u, 0x05u},\r
+ {0x13u, 0x38u},\r
+ {0x14u, 0x02u},\r
+ {0x15u, 0x10u},\r
+ {0x16u, 0x01u},\r
+ {0x17u, 0x20u},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Cu, 0x01u},\r
+ {0x1Du, 0x30u},\r
+ {0x1Eu, 0x02u},\r
{0x1Fu, 0x08u},\r
- {0x20u, 0x01u},\r
- {0x22u, 0x02u},\r
- {0x23u, 0x02u},\r
- {0x24u, 0x2Bu},\r
- {0x26u, 0x54u},\r
- {0x28u, 0xA4u},\r
- {0x29u, 0x03u},\r
- {0x2Au, 0x4Bu},\r
- {0x2Bu, 0x28u},\r
- {0x2Du, 0x04u},\r
- {0x30u, 0xC0u},\r
- {0x31u, 0x07u},\r
- {0x32u, 0x3Cu},\r
- {0x34u, 0x03u},\r
- {0x35u, 0x07u},\r
- {0x37u, 0x38u},\r
- {0x3Au, 0x22u},\r
- {0x3Bu, 0x33u},\r
- {0x54u, 0x01u},\r
+ {0x21u, 0x02u},\r
+ {0x23u, 0x30u},\r
+ {0x28u, 0x02u},\r
+ {0x2Au, 0x01u},\r
+ {0x2Bu, 0x40u},\r
+ {0x2Cu, 0x02u},\r
+ {0x2Du, 0x10u},\r
+ {0x2Eu, 0x05u},\r
+ {0x2Fu, 0x20u},\r
+ {0x32u, 0x04u},\r
+ {0x33u, 0x40u},\r
+ {0x35u, 0x30u},\r
+ {0x36u, 0x03u},\r
+ {0x37u, 0x0Fu},\r
+ {0x39u, 0x80u},\r
+ {0x3Au, 0x80u},\r
+ {0x3Bu, 0x20u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x01u},\r
- {0x5Du, 0x10u},\r
+ {0x5Cu, 0x11u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x05u},\r
- {0x82u, 0x80u},\r
- {0x83u, 0x0Au},\r
- {0x84u, 0x01u},\r
- {0x86u, 0x12u},\r
- {0x89u, 0x03u},\r
- {0x8Bu, 0x0Cu},\r
- {0x8Cu, 0x04u},\r
- {0x8Du, 0x0Fu},\r
- {0x8Eu, 0x28u},\r
- {0x8Fu, 0xF0u},\r
- {0x92u, 0x40u},\r
- {0x93u, 0xFFu},\r
- {0x9Bu, 0xFFu},\r
- {0x9Cu, 0x08u},\r
- {0x9Du, 0x09u},\r
- {0x9Eu, 0x04u},\r
- {0x9Fu, 0x06u},\r
- {0xA0u, 0x02u},\r
- {0xA2u, 0x01u},\r
- {0xA3u, 0xFFu},\r
- {0xA5u, 0x30u},\r
- {0xA7u, 0xC0u},\r
- {0xA9u, 0x50u},\r
- {0xABu, 0xA0u},\r
- {0xACu, 0x53u},\r
- {0xADu, 0x90u},\r
- {0xAEu, 0xACu},\r
- {0xAFu, 0x60u},\r
- {0xB0u, 0x0Fu},\r
- {0xB2u, 0x30u},\r
- {0xB4u, 0xC0u},\r
- {0xB5u, 0xFFu},\r
- {0xBEu, 0x15u},\r
- {0xBFu, 0x10u},\r
+ {0x81u, 0x01u},\r
+ {0x82u, 0x3Fu},\r
+ {0x84u, 0x04u},\r
+ {0x86u, 0x08u},\r
+ {0x88u, 0x10u},\r
+ {0x8Au, 0x20u},\r
+ {0x8Cu, 0x10u},\r
+ {0x8Eu, 0x20u},\r
+ {0x8Fu, 0x01u},\r
+ {0x90u, 0x04u},\r
+ {0x92u, 0x08u},\r
+ {0x95u, 0x01u},\r
+ {0x98u, 0x01u},\r
+ {0x99u, 0x01u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Cu, 0x01u},\r
+ {0x9Du, 0x01u},\r
+ {0x9Eu, 0x02u},\r
+ {0xA0u, 0x3Fu},\r
+ {0xA1u, 0x02u},\r
+ {0xA4u, 0x3Fu},\r
+ {0xAAu, 0x3Fu},\r
+ {0xAEu, 0x3Fu},\r
+ {0xB0u, 0x30u},\r
+ {0xB1u, 0x01u},\r
+ {0xB3u, 0x02u},\r
+ {0xB4u, 0x0Cu},\r
+ {0xB6u, 0x03u},\r
+ {0xBAu, 0xA2u},\r
+ {0xBFu, 0x01u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDCu, 0x91u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x0Au},\r
- {0x02u, 0x02u},\r
- {0x05u, 0x04u},\r
- {0x06u, 0x81u},\r
- {0x08u, 0x08u},\r
- {0x09u, 0x40u},\r
- {0x0Au, 0x44u},\r
- {0x0Eu, 0x82u},\r
- {0x11u, 0x04u},\r
- {0x12u, 0x40u},\r
- {0x13u, 0x20u},\r
- {0x15u, 0x42u},\r
- {0x19u, 0x0Au},\r
- {0x1Au, 0x04u},\r
- {0x1Du, 0x19u},\r
- {0x20u, 0x44u},\r
- {0x21u, 0x02u},\r
- {0x22u, 0x50u},\r
- {0x26u, 0x10u},\r
- {0x28u, 0x02u},\r
- {0x29u, 0x20u},\r
- {0x2Bu, 0x80u},\r
- {0x2Cu, 0x04u},\r
- {0x2Eu, 0x82u},\r
- {0x2Fu, 0x2Au},\r
- {0x30u, 0x20u},\r
- {0x32u, 0x44u},\r
- {0x33u, 0x01u},\r
- {0x35u, 0x01u},\r
- {0x36u, 0xE0u},\r
- {0x38u, 0x84u},\r
- {0x39u, 0x11u},\r
- {0x3Cu, 0x20u},\r
- {0x3Du, 0x40u},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x11u},\r
- {0x5Bu, 0x40u},\r
- {0x65u, 0x02u},\r
- {0x67u, 0x80u},\r
- {0x6Du, 0x40u},\r
- {0x80u, 0x02u},\r
- {0x81u, 0x18u},\r
- {0x84u, 0x08u},\r
- {0x8Bu, 0x04u},\r
- {0x8Eu, 0x42u},\r
- {0x8Fu, 0x04u},\r
- {0x90u, 0x20u},\r
- {0x91u, 0x06u},\r
- {0x92u, 0x41u},\r
+ {0x00u, 0x04u},\r
+ {0x01u, 0x01u},\r
+ {0x02u, 0x04u},\r
+ {0x03u, 0x02u},\r
+ {0x07u, 0x40u},\r
+ {0x08u, 0x02u},\r
+ {0x09u, 0x20u},\r
+ {0x0Au, 0x01u},\r
+ {0x0Eu, 0x12u},\r
+ {0x11u, 0x94u},\r
+ {0x12u, 0x80u},\r
+ {0x14u, 0x01u},\r
+ {0x17u, 0x20u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x41u},\r
+ {0x1Au, 0x01u},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Eu, 0x12u},\r
+ {0x1Fu, 0x84u},\r
+ {0x21u, 0x01u},\r
+ {0x22u, 0x04u},\r
+ {0x25u, 0x40u},\r
+ {0x27u, 0x25u},\r
+ {0x2Bu, 0x80u},\r
+ {0x2Du, 0x01u},\r
+ {0x2Fu, 0x09u},\r
+ {0x30u, 0xA8u},\r
+ {0x36u, 0x80u},\r
+ {0x37u, 0x15u},\r
+ {0x38u, 0x20u},\r
+ {0x39u, 0x50u},\r
+ {0x3Au, 0x02u},\r
+ {0x3Du, 0x14u},\r
+ {0x58u, 0x84u},\r
+ {0x59u, 0x20u},\r
+ {0x5Eu, 0x40u},\r
+ {0x60u, 0x02u},\r
+ {0x61u, 0x04u},\r
+ {0x62u, 0x18u},\r
+ {0x64u, 0x01u},\r
+ {0x85u, 0x20u},\r
+ {0x8Bu, 0x01u},\r
+ {0x8Du, 0x04u},\r
+ {0x8Eu, 0x40u},\r
+ {0x90u, 0x23u},\r
+ {0x91u, 0x05u},\r
+ {0x92u, 0x20u},\r
+ {0x93u, 0x02u},\r
+ {0x94u, 0x04u},\r
{0x95u, 0x40u},\r
- {0x96u, 0x04u},\r
- {0x97u, 0x80u},\r
- {0x99u, 0x04u},\r
- {0x9Au, 0x60u},\r
- {0x9Bu, 0x60u},\r
- {0x9Cu, 0x04u},\r
- {0x9Eu, 0x14u},\r
- {0x9Fu, 0x04u},\r
- {0xA0u, 0x10u},\r
- {0xA1u, 0x60u},\r
- {0xA2u, 0x80u},\r
- {0xA6u, 0x06u},\r
- {0xA7u, 0x24u},\r
- {0xA8u, 0x02u},\r
- {0xAAu, 0x30u},\r
- {0xABu, 0x21u},\r
- {0xACu, 0x01u},\r
- {0xADu, 0x48u},\r
- {0xB3u, 0x80u},\r
- {0xB4u, 0x18u},\r
- {0xB5u, 0x04u},\r
- {0xB6u, 0xC0u},\r
+ {0x96u, 0x08u},\r
+ {0x98u, 0x04u},\r
+ {0x9Au, 0x04u},\r
+ {0x9Bu, 0x10u},\r
+ {0x9Du, 0x41u},\r
+ {0x9Eu, 0x12u},\r
+ {0x9Fu, 0x0Du},\r
+ {0xA1u, 0x20u},\r
+ {0xA2u, 0x90u},\r
+ {0xA4u, 0xACu},\r
+ {0xA6u, 0x28u},\r
+ {0xA7u, 0x80u},\r
+ {0xAEu, 0x24u},\r
+ {0xB1u, 0x01u},\r
+ {0xB4u, 0x11u},\r
+ {0xB6u, 0x40u},\r
{0xB7u, 0x20u},\r
- {0xC0u, 0xBDu},\r
- {0xC2u, 0x9Fu},\r
- {0xC4u, 0x9Eu},\r
- {0xCAu, 0xFDu},\r
- {0xCCu, 0xBFu},\r
- {0xCEu, 0xBFu},\r
- {0xD6u, 0x08u},\r
- {0xE2u, 0xD4u},\r
- {0xE4u, 0x04u},\r
- {0xE6u, 0x09u},\r
- {0xE8u, 0x01u},\r
- {0xEAu, 0x82u},\r
- {0x00u, 0xFFu},\r
- {0x07u, 0x02u},\r
- {0x0Au, 0xFFu},\r
+ {0xC0u, 0x1Fu},\r
+ {0xC2u, 0xABu},\r
+ {0xC4u, 0xCFu},\r
+ {0xCAu, 0xB1u},\r
+ {0xCCu, 0xFEu},\r
+ {0xCEu, 0x69u},\r
+ {0xD6u, 0x1Eu},\r
+ {0xD8u, 0x1Eu},\r
+ {0xE2u, 0x01u},\r
+ {0xE6u, 0x03u},\r
+ {0xEAu, 0x0Bu},\r
+ {0xEEu, 0x08u},\r
+ {0x01u, 0x02u},\r
+ {0x03u, 0x01u},\r
+ {0x04u, 0x06u},\r
+ {0x09u, 0x02u},\r
{0x0Bu, 0x01u},\r
- {0x0Du, 0x04u},\r
- {0x0Eu, 0xFFu},\r
- {0x10u, 0x60u},\r
- {0x11u, 0x04u},\r
- {0x12u, 0x90u},\r
- {0x14u, 0x03u},\r
- {0x16u, 0x0Cu},\r
- {0x19u, 0x04u},\r
- {0x1Cu, 0x05u},\r
- {0x1Eu, 0x0Au},\r
- {0x20u, 0x06u},\r
- {0x22u, 0x09u},\r
- {0x24u, 0x50u},\r
- {0x25u, 0x04u},\r
- {0x26u, 0xA0u},\r
- {0x28u, 0x30u},\r
- {0x2Au, 0xC0u},\r
- {0x2Cu, 0x0Fu},\r
- {0x2Eu, 0xF0u},\r
- {0x33u, 0x01u},\r
- {0x34u, 0xFFu},\r
- {0x35u, 0x02u},\r
- {0x37u, 0x04u},\r
- {0x39u, 0x80u},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x40u},\r
+ {0x0Cu, 0x2Au},\r
+ {0x0Eu, 0x11u},\r
+ {0x10u, 0x19u},\r
+ {0x11u, 0x01u},\r
+ {0x12u, 0x24u},\r
+ {0x13u, 0x02u},\r
+ {0x14u, 0x20u},\r
+ {0x15u, 0x02u},\r
+ {0x16u, 0x18u},\r
+ {0x17u, 0x09u},\r
+ {0x18u, 0x09u},\r
+ {0x19u, 0x02u},\r
+ {0x1Au, 0x32u},\r
+ {0x1Bu, 0x05u},\r
+ {0x23u, 0x10u},\r
+ {0x26u, 0x40u},\r
+ {0x2Au, 0x80u},\r
+ {0x2Cu, 0x40u},\r
+ {0x2Eu, 0x80u},\r
+ {0x31u, 0x08u},\r
+ {0x32u, 0x38u},\r
+ {0x33u, 0x04u},\r
+ {0x34u, 0x07u},\r
+ {0x35u, 0x10u},\r
+ {0x36u, 0xC0u},\r
+ {0x37u, 0x03u},\r
+ {0x38u, 0x20u},\r
+ {0x3Au, 0x08u},\r
+ {0x3Bu, 0x80u},\r
+ {0x3Eu, 0x40u},\r
+ {0x54u, 0x09u},\r
+ {0x56u, 0x04u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Cu, 0x90u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x04u},\r
- {0x81u, 0x0Cu},\r
- {0x84u, 0x09u},\r
- {0x85u, 0x40u},\r
- {0x86u, 0x06u},\r
- {0x87u, 0x30u},\r
- {0x8Au, 0x06u},\r
- {0x8Bu, 0x0Cu},\r
- {0x8Cu, 0x06u},\r
- {0x8Du, 0x50u},\r
- {0x8Fu, 0x2Fu},\r
- {0x90u, 0x02u},\r
- {0x91u, 0x0Cu},\r
- {0x94u, 0x01u},\r
- {0x95u, 0x11u},\r
- {0x96u, 0x0Eu},\r
- {0x97u, 0x62u},\r
- {0x99u, 0x04u},\r
- {0x9Bu, 0x08u},\r
- {0x9Cu, 0x06u},\r
- {0x9Du, 0x0Cu},\r
- {0xA0u, 0x06u},\r
- {0xA1u, 0x08u},\r
- {0xA4u, 0x02u},\r
- {0xA6u, 0x04u},\r
- {0xA8u, 0x07u},\r
- {0xA9u, 0x31u},\r
- {0xAAu, 0x08u},\r
- {0xABu, 0x4Eu},\r
- {0xADu, 0x04u},\r
- {0xB3u, 0x0Fu},\r
- {0xB4u, 0x0Fu},\r
- {0xB5u, 0x70u},\r
- {0xB8u, 0x20u},\r
- {0xBBu, 0x20u},\r
- {0xD6u, 0x02u},\r
- {0xD7u, 0x24u},\r
+ {0x84u, 0x06u},\r
+ {0x86u, 0x09u},\r
+ {0x87u, 0xFFu},\r
+ {0x88u, 0x05u},\r
+ {0x89u, 0x50u},\r
+ {0x8Au, 0x0Au},\r
+ {0x8Bu, 0xA0u},\r
+ {0x8Cu, 0x60u},\r
+ {0x8Eu, 0x90u},\r
+ {0x90u, 0x0Fu},\r
+ {0x91u, 0x90u},\r
+ {0x92u, 0xF0u},\r
+ {0x93u, 0x60u},\r
+ {0x94u, 0x50u},\r
+ {0x95u, 0x30u},\r
+ {0x96u, 0xA0u},\r
+ {0x97u, 0xC0u},\r
+ {0x98u, 0x03u},\r
+ {0x99u, 0x09u},\r
+ {0x9Au, 0x0Cu},\r
+ {0x9Bu, 0x06u},\r
+ {0x9Du, 0x0Fu},\r
+ {0x9Fu, 0xF0u},\r
+ {0xA2u, 0xFFu},\r
+ {0xA3u, 0xFFu},\r
+ {0xA4u, 0x30u},\r
+ {0xA5u, 0x03u},\r
+ {0xA6u, 0xC0u},\r
+ {0xA7u, 0x0Cu},\r
+ {0xA8u, 0xFFu},\r
+ {0xA9u, 0x05u},\r
+ {0xABu, 0x0Au},\r
+ {0xAEu, 0xFFu},\r
+ {0xAFu, 0xFFu},\r
+ {0xB3u, 0xFFu},\r
+ {0xB4u, 0xFFu},\r
+ {0xBEu, 0x10u},\r
+ {0xBFu, 0x04u},\r
+ {0xD4u, 0x01u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDDu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x04u},\r
{0x01u, 0x10u},\r
- {0x03u, 0x81u},\r
- {0x05u, 0x11u},\r
- {0x06u, 0x02u},\r
- {0x08u, 0x02u},\r
- {0x0Au, 0x21u},\r
- {0x0Eu, 0x40u},\r
- {0x0Fu, 0x11u},\r
- {0x10u, 0xA0u},\r
- {0x12u, 0x08u},\r
- {0x14u, 0x18u},\r
- {0x15u, 0x40u},\r
- {0x16u, 0x40u},\r
- {0x18u, 0x04u},\r
+ {0x03u, 0x21u},\r
+ {0x04u, 0x04u},\r
+ {0x05u, 0x80u},\r
+ {0x08u, 0x20u},\r
+ {0x0Au, 0x80u},\r
+ {0x0Bu, 0x20u},\r
+ {0x0Cu, 0x10u},\r
+ {0x0Eu, 0x20u},\r
+ {0x0Fu, 0x80u},\r
+ {0x11u, 0x04u},\r
+ {0x12u, 0x45u},\r
+ {0x14u, 0x24u},\r
+ {0x17u, 0x40u},\r
{0x19u, 0x20u},\r
- {0x1Au, 0x04u},\r
- {0x1Fu, 0x10u},\r
- {0x22u, 0x0Cu},\r
- {0x23u, 0x04u},\r
- {0x24u, 0x02u},\r
- {0x25u, 0x14u},\r
- {0x27u, 0x04u},\r
- {0x28u, 0x02u},\r
- {0x29u, 0x20u},\r
- {0x2Bu, 0x80u},\r
- {0x2Eu, 0x40u},\r
- {0x2Fu, 0x12u},\r
- {0x30u, 0xA0u},\r
- {0x32u, 0x04u},\r
- {0x33u, 0x01u},\r
- {0x36u, 0x12u},\r
- {0x38u, 0x40u},\r
- {0x39u, 0x11u},\r
- {0x3Bu, 0x04u},\r
- {0x3Cu, 0x80u},\r
- {0x3Du, 0x08u},\r
- {0x3Eu, 0x20u},\r
- {0x62u, 0xC0u},\r
- {0x63u, 0x04u},\r
- {0x68u, 0x21u},\r
- {0x69u, 0x11u},\r
- {0x6Au, 0x01u},\r
- {0x6Bu, 0x01u},\r
- {0x70u, 0xC0u},\r
- {0x78u, 0x10u},\r
- {0x7Bu, 0x08u},\r
- {0x80u, 0x01u},\r
- {0x86u, 0x01u},\r
- {0x88u, 0x20u},\r
- {0x89u, 0x10u},\r
- {0x8Cu, 0x80u},\r
- {0x90u, 0x60u},\r
- {0x91u, 0x40u},\r
- {0x92u, 0x20u},\r
- {0x93u, 0x11u},\r
- {0x94u, 0x80u},\r
- {0x95u, 0x11u},\r
- {0x96u, 0x08u},\r
- {0x97u, 0x08u},\r
- {0x98u, 0x02u},\r
- {0x99u, 0x09u},\r
- {0x9Au, 0x22u},\r
- {0x9Du, 0x20u},\r
- {0x9Eu, 0x15u},\r
- {0x9Fu, 0x05u},\r
- {0xA1u, 0x22u},\r
- {0xA2u, 0x90u},\r
- {0xA3u, 0x04u},\r
- {0xA4u, 0x20u},\r
- {0xA6u, 0x25u},\r
- {0xA7u, 0xAAu},\r
- {0xADu, 0x01u},\r
- {0xB2u, 0x02u},\r
- {0xB4u, 0x04u},\r
- {0xC0u, 0xDFu},\r
- {0xC2u, 0xBDu},\r
- {0xC4u, 0xFEu},\r
- {0xCAu, 0x4Du},\r
- {0xCCu, 0xAFu},\r
- {0xCEu, 0x7Fu},\r
- {0xD8u, 0x04u},\r
- {0xE0u, 0x08u},\r
- {0xE2u, 0x01u},\r
- {0xEAu, 0x32u},\r
- {0xECu, 0x02u},\r
- {0x81u, 0x40u},\r
- {0x82u, 0x40u},\r
- {0x84u, 0x04u},\r
- {0x85u, 0x01u},\r
- {0x88u, 0x08u},\r
- {0x8Au, 0x16u},\r
- {0x8Eu, 0x01u},\r
- {0x8Fu, 0x40u},\r
- {0x90u, 0x20u},\r
- {0x91u, 0x06u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x01u},\r
- {0x96u, 0x08u},\r
- {0x9Bu, 0x02u},\r
+ {0x1Cu, 0x04u},\r
+ {0x1Eu, 0x22u},\r
+ {0x1Fu, 0x04u},\r
+ {0x20u, 0x10u},\r
+ {0x24u, 0x08u},\r
+ {0x25u, 0x01u},\r
+ {0x26u, 0x08u},\r
+ {0x27u, 0x02u},\r
+ {0x28u, 0x20u},\r
+ {0x29u, 0x04u},\r
+ {0x2Au, 0x41u},\r
+ {0x2Bu, 0x05u},\r
+ {0x2Du, 0x02u},\r
+ {0x30u, 0x04u},\r
+ {0x32u, 0x44u},\r
+ {0x33u, 0x61u},\r
+ {0x35u, 0x10u},\r
+ {0x36u, 0x08u},\r
+ {0x37u, 0x02u},\r
+ {0x39u, 0x28u},\r
+ {0x3Au, 0x04u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Du, 0x02u},\r
+ {0x3Fu, 0x20u},\r
+ {0x59u, 0x40u},\r
+ {0x5Cu, 0x0Au},\r
+ {0x5Eu, 0x90u},\r
+ {0x64u, 0x40u},\r
+ {0x67u, 0x02u},\r
+ {0x8Bu, 0x04u},\r
+ {0x8Fu, 0x10u},\r
+ {0x91u, 0x3Cu},\r
+ {0x92u, 0x88u},\r
+ {0x93u, 0x02u},\r
+ {0x94u, 0x10u},\r
+ {0x97u, 0x80u},\r
+ {0x99u, 0x04u},\r
+ {0x9Bu, 0x01u},\r
{0x9Cu, 0x40u},\r
- {0x9Du, 0x08u},\r
- {0x9Eu, 0x20u},\r
- {0xA0u, 0x02u},\r
- {0xA2u, 0x80u},\r
- {0xA4u, 0x08u},\r
- {0xA5u, 0x08u},\r
- {0xA6u, 0x10u},\r
- {0xA7u, 0x42u},\r
- {0xABu, 0x04u},\r
- {0xADu, 0x04u},\r
- {0xB0u, 0x40u},\r
- {0xB4u, 0x16u},\r
- {0xB5u, 0x40u},\r
- {0xE0u, 0x80u},\r
- {0xE2u, 0x04u},\r
- {0xE4u, 0x60u},\r
- {0xEAu, 0x33u},\r
- {0xECu, 0x40u},\r
- {0xEEu, 0x20u},\r
- {0x00u, 0x08u},\r
- {0x02u, 0x10u},\r
- {0x08u, 0x01u},\r
+ {0x9Du, 0x20u},\r
+ {0x9Eu, 0x01u},\r
+ {0x9Fu, 0x42u},\r
+ {0xA2u, 0x40u},\r
+ {0xA3u, 0x25u},\r
+ {0xA5u, 0x04u},\r
+ {0xA6u, 0x21u},\r
+ {0xA7u, 0x40u},\r
+ {0xAAu, 0x04u},\r
+ {0xABu, 0x05u},\r
+ {0xACu, 0x40u},\r
+ {0xAEu, 0x40u},\r
+ {0xB2u, 0x01u},\r
+ {0xB6u, 0x82u},\r
+ {0xB7u, 0x02u},\r
+ {0xC0u, 0xA7u},\r
+ {0xC2u, 0x7Eu},\r
+ {0xC4u, 0xEFu},\r
+ {0xCAu, 0x8Fu},\r
+ {0xCCu, 0xEFu},\r
+ {0xCEu, 0xA6u},\r
+ {0xD6u, 0xF8u},\r
+ {0xD8u, 0x90u},\r
+ {0xE0u, 0x10u},\r
+ {0xE2u, 0x81u},\r
+ {0xE6u, 0x43u},\r
+ {0xE8u, 0x40u},\r
+ {0xEAu, 0x12u},\r
+ {0xECu, 0x10u},\r
+ {0xEEu, 0xC0u},\r
+ {0x00u, 0x0Fu},\r
+ {0x02u, 0xF0u},\r
+ {0x04u, 0x09u},\r
+ {0x06u, 0x06u},\r
+ {0x07u, 0xFFu},\r
+ {0x08u, 0x05u},\r
+ {0x09u, 0x50u},\r
{0x0Au, 0x0Au},\r
- {0x0Cu, 0x02u},\r
- {0x0Du, 0x01u},\r
- {0x0Eu, 0x01u},\r
- {0x0Fu, 0x02u},\r
- {0x14u, 0x02u},\r
- {0x15u, 0x02u},\r
- {0x16u, 0x01u},\r
- {0x17u, 0x01u},\r
- {0x18u, 0x02u},\r
- {0x1Au, 0x01u},\r
- {0x1Du, 0x02u},\r
- {0x1Fu, 0x01u},\r
- {0x20u, 0x02u},\r
- {0x21u, 0x02u},\r
- {0x22u, 0x11u},\r
- {0x23u, 0x01u},\r
- {0x29u, 0x02u},\r
- {0x2Au, 0x04u},\r
- {0x2Bu, 0x01u},\r
- {0x30u, 0x04u},\r
- {0x31u, 0x03u},\r
- {0x34u, 0x03u},\r
- {0x36u, 0x18u},\r
- {0x3Au, 0x20u},\r
- {0x3Bu, 0x02u},\r
- {0x3Eu, 0x40u},\r
- {0x56u, 0x08u},\r
+ {0x0Bu, 0xA0u},\r
+ {0x0Cu, 0x90u},\r
+ {0x0Eu, 0x60u},\r
+ {0x10u, 0x03u},\r
+ {0x11u, 0x60u},\r
+ {0x12u, 0x0Cu},\r
+ {0x13u, 0x90u},\r
+ {0x15u, 0x30u},\r
+ {0x16u, 0xFFu},\r
+ {0x17u, 0xC0u},\r
+ {0x18u, 0xFFu},\r
+ {0x19u, 0x06u},\r
+ {0x1Bu, 0x09u},\r
+ {0x1Du, 0x0Fu},\r
+ {0x1Fu, 0xF0u},\r
+ {0x23u, 0xFFu},\r
+ {0x24u, 0x30u},\r
+ {0x25u, 0x03u},\r
+ {0x26u, 0xC0u},\r
+ {0x27u, 0x0Cu},\r
+ {0x28u, 0x50u},\r
+ {0x29u, 0x05u},\r
+ {0x2Au, 0xA0u},\r
+ {0x2Bu, 0x0Au},\r
+ {0x2Cu, 0xFFu},\r
+ {0x2Du, 0xFFu},\r
+ {0x31u, 0xFFu},\r
+ {0x32u, 0xFFu},\r
+ {0x3Eu, 0x04u},\r
+ {0x3Fu, 0x01u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x99u},\r
- {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x10u},\r
- {0x81u, 0x35u},\r
- {0x82u, 0x0Cu},\r
- {0x85u, 0x08u},\r
- {0x87u, 0x34u},\r
- {0x89u, 0x0Au},\r
- {0x8Bu, 0x11u},\r
+ {0x81u, 0x02u},\r
+ {0x84u, 0x04u},\r
+ {0x86u, 0x38u},\r
+ {0x88u, 0x10u},\r
+ {0x8Au, 0x20u},\r
{0x8Cu, 0x10u},\r
- {0x8Du, 0x35u},\r
- {0x8Eu, 0x08u},\r
- {0x91u, 0x02u},\r
- {0x93u, 0x01u},\r
- {0x94u, 0x10u},\r
- {0x95u, 0x05u},\r
- {0x96u, 0x0Au},\r
- {0x97u, 0x0Au},\r
- {0x98u, 0x08u},\r
- {0x99u, 0x35u},\r
- {0x9Au, 0x10u},\r
- {0x9Du, 0x34u},\r
- {0x9Fu, 0x01u},\r
- {0xA9u, 0x35u},\r
- {0xACu, 0x10u},\r
- {0xADu, 0x0Bu},\r
- {0xAEu, 0x09u},\r
- {0xAFu, 0x20u},\r
- {0xB0u, 0x04u},\r
- {0xB2u, 0x01u},\r
- {0xB3u, 0x3Cu},\r
- {0xB4u, 0x18u},\r
- {0xB6u, 0x02u},\r
- {0xB7u, 0x03u},\r
+ {0x8Du, 0x05u},\r
+ {0x8Eu, 0x20u},\r
+ {0x96u, 0x07u},\r
+ {0x98u, 0x09u},\r
+ {0x99u, 0x01u},\r
+ {0x9Au, 0x32u},\r
+ {0x9Bu, 0x04u},\r
+ {0x9Eu, 0x30u},\r
+ {0xA0u, 0x30u},\r
+ {0xA1u, 0x01u},\r
+ {0xA3u, 0x04u},\r
+ {0xAAu, 0x08u},\r
+ {0xACu, 0x3Au},\r
+ {0xAEu, 0x05u},\r
+ {0xB2u, 0x0Fu},\r
+ {0xB3u, 0x01u},\r
+ {0xB4u, 0x30u},\r
+ {0xB5u, 0x02u},\r
+ {0xB7u, 0x04u},\r
{0xBAu, 0x20u},\r
- {0xBBu, 0x88u},\r
+ {0xBFu, 0x44u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x09u},\r
+ {0xDCu, 0x91u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x02u},\r
- {0x01u, 0x20u},\r
- {0x03u, 0x02u},\r
- {0x04u, 0x41u},\r
- {0x08u, 0x20u},\r
- {0x09u, 0x08u},\r
+ {0x01u, 0x10u},\r
+ {0x03u, 0x61u},\r
+ {0x05u, 0x90u},\r
+ {0x06u, 0x20u},\r
+ {0x08u, 0x12u},\r
+ {0x09u, 0x04u},\r
{0x0Cu, 0x20u},\r
- {0x0Eu, 0x14u},\r
- {0x10u, 0x04u},\r
- {0x12u, 0x40u},\r
- {0x14u, 0x01u},\r
- {0x18u, 0x02u},\r
- {0x19u, 0xA1u},\r
- {0x1Bu, 0x80u},\r
- {0x1Cu, 0x41u},\r
- {0x1Eu, 0x14u},\r
- {0x20u, 0x80u},\r
+ {0x0Eu, 0x21u},\r
+ {0x10u, 0x09u},\r
+ {0x11u, 0x04u},\r
+ {0x14u, 0x10u},\r
+ {0x15u, 0x08u},\r
+ {0x16u, 0x8Au},\r
+ {0x19u, 0x08u},\r
+ {0x1Du, 0x14u},\r
+ {0x1Eu, 0x24u},\r
{0x21u, 0x01u},\r
- {0x23u, 0x40u},\r
- {0x25u, 0x04u},\r
- {0x27u, 0x02u},\r
- {0x29u, 0x01u},\r
- {0x2Bu, 0x04u},\r
- {0x2Cu, 0x0Au},\r
- {0x30u, 0x04u},\r
- {0x32u, 0x84u},\r
- {0x34u, 0x40u},\r
- {0x35u, 0x08u},\r
- {0x36u, 0x10u},\r
- {0x37u, 0x02u},\r
- {0x3Bu, 0x40u},\r
- {0x3Du, 0x09u},\r
- {0x3Eu, 0x20u},\r
+ {0x26u, 0x44u},\r
+ {0x27u, 0x04u},\r
+ {0x28u, 0x01u},\r
+ {0x29u, 0x04u},\r
+ {0x2Au, 0x01u},\r
+ {0x2Bu, 0x05u},\r
+ {0x2Fu, 0x40u},\r
+ {0x32u, 0x44u},\r
+ {0x33u, 0x21u},\r
+ {0x36u, 0x20u},\r
+ {0x39u, 0x28u},\r
+ {0x3Eu, 0x01u},\r
{0x3Fu, 0x80u},\r
- {0x58u, 0x10u},\r
- {0x5Au, 0x40u},\r
- {0x5Bu, 0x04u},\r
- {0x5Du, 0x40u},\r
- {0x60u, 0x02u},\r
- {0x62u, 0x18u},\r
- {0x64u, 0x01u},\r
- {0x68u, 0x01u},\r
- {0x6Cu, 0x04u},\r
- {0x6Eu, 0x08u},\r
- {0x6Fu, 0x01u},\r
- {0x83u, 0x02u},\r
- {0x87u, 0x80u},\r
- {0x88u, 0x10u},\r
- {0x8Eu, 0x04u},\r
- {0x92u, 0x40u},\r
- {0x94u, 0x06u},\r
- {0x95u, 0x02u},\r
- {0x97u, 0x40u},\r
- {0x98u, 0x20u},\r
- {0x9Au, 0x40u},\r
- {0x9Cu, 0x02u},\r
- {0x9Du, 0xA0u},\r
- {0x9Eu, 0x10u},\r
+ {0x5Cu, 0x80u},\r
+ {0x66u, 0x40u},\r
+ {0x68u, 0x88u},\r
+ {0x69u, 0x24u},\r
+ {0x6Au, 0x08u},\r
+ {0x6Bu, 0x01u},\r
+ {0x71u, 0x60u},\r
+ {0x72u, 0x50u},\r
+ {0x79u, 0x10u},\r
+ {0x7Bu, 0x04u},\r
+ {0x80u, 0x80u},\r
+ {0x86u, 0x04u},\r
+ {0x8Cu, 0x02u},\r
+ {0x8Du, 0x04u},\r
+ {0x91u, 0x08u},\r
+ {0x92u, 0x81u},\r
+ {0x94u, 0x10u},\r
+ {0x95u, 0x22u},\r
+ {0x96u, 0x50u},\r
+ {0x99u, 0x80u},\r
+ {0x9Au, 0x28u},\r
+ {0x9Du, 0x68u},\r
+ {0x9Eu, 0xC2u},\r
{0x9Fu, 0x01u},\r
- {0xA2u, 0x80u},\r
- {0xA3u, 0x04u},\r
- {0xA4u, 0x60u},\r
- {0xA6u, 0x0Cu},\r
- {0xAAu, 0x10u},\r
- {0xAFu, 0x20u},\r
- {0xB0u, 0x04u},\r
- {0xB5u, 0x40u},\r
- {0xB6u, 0x50u},\r
- {0xC0u, 0x9Bu},\r
- {0xC2u, 0x66u},\r
- {0xC4u, 0x8Au},\r
- {0xCAu, 0x35u},\r
- {0xCCu, 0xFAu},\r
- {0xCEu, 0xF8u},\r
- {0xD6u, 0x1Eu},\r
- {0xD8u, 0x1Eu},\r
- {0xE2u, 0x44u},\r
- {0xE4u, 0x04u},\r
- {0xE8u, 0x01u},\r
- {0xEAu, 0x10u},\r
- {0xEEu, 0x14u},\r
- {0x00u, 0xD3u},\r
- {0x01u, 0x53u},\r
- {0x02u, 0x20u},\r
- {0x03u, 0x24u},\r
- {0x05u, 0x20u},\r
- {0x08u, 0x01u},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0x02u},\r
- {0x0Bu, 0x02u},\r
- {0x0Cu, 0xC3u},\r
- {0x0Eu, 0x20u},\r
- {0x0Fu, 0x7Fu},\r
- {0x11u, 0x01u},\r
- {0x13u, 0x02u},\r
- {0x14u, 0x04u},\r
- {0x16u, 0xE3u},\r
- {0x17u, 0x04u},\r
- {0x19u, 0x24u},\r
- {0x1Au, 0x04u},\r
- {0x1Bu, 0x4Bu},\r
- {0x1Cu, 0x40u},\r
- {0x1Eu, 0x80u},\r
- {0x20u, 0x08u},\r
- {0x22u, 0xC3u},\r
- {0x23u, 0x10u},\r
- {0x24u, 0x40u},\r
- {0x26u, 0x80u},\r
- {0x28u, 0x01u},\r
+ {0xA0u, 0x20u},\r
+ {0xA3u, 0x25u},\r
+ {0xA4u, 0x80u},\r
+ {0xA5u, 0x20u},\r
+ {0xA6u, 0x01u},\r
+ {0xA8u, 0x81u},\r
+ {0xAFu, 0x80u},\r
+ {0xB0u, 0x20u},\r
+ {0xB1u, 0x08u},\r
+ {0xC0u, 0xEFu},\r
+ {0xC2u, 0xEEu},\r
+ {0xC4u, 0xD7u},\r
+ {0xCAu, 0x8Fu},\r
+ {0xCCu, 0x2Fu},\r
+ {0xCEu, 0x96u},\r
+ {0xD6u, 0x10u},\r
+ {0xD8u, 0x10u},\r
+ {0xE2u, 0x20u},\r
+ {0xE6u, 0x27u},\r
+ {0xECu, 0x20u},\r
+ {0xEEu, 0x02u},\r
+ {0x00u, 0x03u},\r
+ {0x04u, 0x10u},\r
+ {0x06u, 0x23u},\r
+ {0x0Au, 0x20u},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Cu, 0x2Bu},\r
+ {0x0Du, 0x0Au},\r
+ {0x0Eu, 0x14u},\r
+ {0x0Fu, 0x05u},\r
+ {0x13u, 0x20u},\r
+ {0x14u, 0x24u},\r
+ {0x16u, 0x0Bu},\r
+ {0x1Au, 0x5Cu},\r
+ {0x1Bu, 0x17u},\r
+ {0x1Eu, 0x03u},\r
+ {0x20u, 0x01u},\r
+ {0x22u, 0x02u},\r
+ {0x24u, 0x01u},\r
+ {0x25u, 0x09u},\r
+ {0x26u, 0x02u},\r
+ {0x27u, 0x02u},\r
{0x29u, 0x04u},\r
- {0x2Au, 0x02u},\r
- {0x2Bu, 0x1Bu},\r
- {0x2Cu, 0x14u},\r
- {0x2Du, 0x0Bu},\r
- {0x2Eu, 0xE3u},\r
- {0x32u, 0x3Cu},\r
- {0x33u, 0x7Cu},\r
- {0x34u, 0x03u},\r
+ {0x2Au, 0x80u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Cu, 0x40u},\r
+ {0x2Du, 0x10u},\r
+ {0x2Eu, 0x80u},\r
+ {0x2Fu, 0x20u},\r
+ {0x32u, 0x03u},\r
+ {0x34u, 0x3Cu},\r
+ {0x35u, 0x0Fu},\r
{0x36u, 0xC0u},\r
- {0x37u, 0x03u},\r
- {0x38u, 0x08u},\r
- {0x3Au, 0xA0u},\r
- {0x3Bu, 0x80u},\r
+ {0x37u, 0x30u},\r
+ {0x3Au, 0x08u},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x40u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
{0x5Cu, 0x11u},\r
{0x5Fu, 0x01u},\r
- {0x83u, 0xFFu},\r
- {0x85u, 0x69u},\r
- {0x87u, 0x96u},\r
- {0x88u, 0x55u},\r
- {0x8Au, 0xAAu},\r
- {0x8Cu, 0xFFu},\r
- {0x90u, 0x33u},\r
- {0x91u, 0x0Fu},\r
- {0x92u, 0xCCu},\r
- {0x93u, 0xF0u},\r
- {0x96u, 0xFFu},\r
- {0x97u, 0xFFu},\r
- {0x98u, 0x0Fu},\r
- {0x99u, 0x55u},\r
- {0x9Au, 0xF0u},\r
- {0x9Bu, 0xAAu},\r
- {0xA0u, 0xFFu},\r
- {0xA1u, 0xFFu},\r
- {0xA4u, 0x96u},\r
- {0xA5u, 0x33u},\r
- {0xA6u, 0x69u},\r
- {0xA7u, 0xCCu},\r
- {0xAAu, 0xFFu},\r
- {0xABu, 0xFFu},\r
- {0xADu, 0xFFu},\r
- {0xAEu, 0xFFu},\r
- {0xB1u, 0xFFu},\r
- {0xB4u, 0xFFu},\r
- {0xBAu, 0x20u},\r
- {0xBBu, 0x02u},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
- {0xDDu, 0x90u},\r
- {0xDFu, 0x01u},\r
- {0x01u, 0x90u},\r
- {0x02u, 0x08u},\r
- {0x05u, 0x91u},\r
- {0x08u, 0x02u},\r
- {0x0Au, 0x14u},\r
- {0x0Du, 0x08u},\r
- {0x0Eu, 0x0Au},\r
- {0x10u, 0x40u},\r
- {0x13u, 0x64u},\r
- {0x15u, 0x82u},\r
- {0x16u, 0x14u},\r
- {0x17u, 0x10u},\r
- {0x1Au, 0x04u},\r
- {0x1Du, 0x10u},\r
- {0x1Eu, 0x12u},\r
- {0x1Fu, 0xA8u},\r
- {0x22u, 0x02u},\r
- {0x24u, 0x20u},\r
- {0x25u, 0x0Cu},\r
- {0x27u, 0x22u},\r
- {0x28u, 0x40u},\r
- {0x29u, 0x81u},\r
- {0x2Au, 0x02u},\r
- {0x2Bu, 0x18u},\r
- {0x2Du, 0x82u},\r
- {0x2Fu, 0x08u},\r
- {0x31u, 0x08u},\r
- {0x32u, 0x02u},\r
- {0x33u, 0x10u},\r
- {0x36u, 0x04u},\r
- {0x37u, 0x22u},\r
- {0x39u, 0x0Au},\r
- {0x3Cu, 0x80u},\r
- {0x3Du, 0x10u},\r
- {0x3Eu, 0x0Au},\r
- {0x58u, 0x04u},\r
- {0x5Au, 0x20u},\r
- {0x5Bu, 0x40u},\r
- {0x62u, 0x44u},\r
- {0x63u, 0x04u},\r
- {0x80u, 0x04u},\r
- {0x82u, 0x80u},\r
- {0x83u, 0x40u},\r
- {0x86u, 0x40u},\r
- {0x89u, 0x04u},\r
- {0x8Bu, 0x03u},\r
- {0x8Du, 0x01u},\r
- {0x8Fu, 0x04u},\r
- {0x94u, 0x22u},\r
- {0x95u, 0x02u},\r
- {0x96u, 0x14u},\r
- {0x98u, 0x20u},\r
- {0x99u, 0x02u},\r
- {0x9Au, 0x0Au},\r
- {0x9Cu, 0x02u},\r
- {0x9Du, 0xA0u},\r
+ {0x81u, 0x10u},\r
+ {0x84u, 0x06u},\r
+ {0x85u, 0x01u},\r
+ {0x86u, 0x09u},\r
+ {0x87u, 0x02u},\r
+ {0x89u, 0x10u},\r
+ {0x8Cu, 0x0Fu},\r
+ {0x8Du, 0x23u},\r
+ {0x8Eu, 0xF0u},\r
+ {0x8Fu, 0x4Cu},\r
+ {0x90u, 0x30u},\r
+ {0x92u, 0xC0u},\r
+ {0x93u, 0x40u},\r
+ {0x94u, 0x50u},\r
+ {0x96u, 0xA0u},\r
+ {0x98u, 0x60u},\r
+ {0x9Au, 0x90u},\r
+ {0x9Bu, 0x20u},\r
+ {0x9Du, 0x08u},\r
+ {0x9Fu, 0x04u},\r
+ {0xA1u, 0x02u},\r
+ {0xA3u, 0x01u},\r
+ {0xA4u, 0x03u},\r
+ {0xA5u, 0x10u},\r
+ {0xA6u, 0x0Cu},\r
+ {0xA8u, 0x05u},\r
+ {0xA9u, 0x10u},\r
+ {0xAAu, 0x0Au},\r
+ {0xADu, 0x04u},\r
+ {0xAFu, 0x08u},\r
+ {0xB0u, 0xFFu},\r
+ {0xB1u, 0x10u},\r
+ {0xB3u, 0x0Fu},\r
+ {0xB5u, 0x60u},\r
+ {0xB9u, 0x02u},\r
+ {0xBEu, 0x01u},\r
+ {0xBFu, 0x15u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDFu, 0x01u},\r
+ {0x00u, 0x04u},\r
+ {0x01u, 0x40u},\r
+ {0x05u, 0x10u},\r
+ {0x06u, 0xA2u},\r
+ {0x08u, 0x08u},\r
+ {0x09u, 0x20u},\r
+ {0x0Au, 0x50u},\r
+ {0x0Du, 0x08u},\r
+ {0x0Eu, 0x09u},\r
+ {0x0Fu, 0x08u},\r
+ {0x12u, 0x18u},\r
+ {0x13u, 0x08u},\r
+ {0x14u, 0x10u},\r
+ {0x15u, 0xA0u},\r
+ {0x16u, 0x40u},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Cu, 0x02u},\r
+ {0x1Eu, 0x08u},\r
+ {0x1Fu, 0x08u},\r
+ {0x20u, 0x08u},\r
+ {0x21u, 0x04u},\r
+ {0x22u, 0x01u},\r
+ {0x24u, 0x0Au},\r
+ {0x26u, 0x20u},\r
+ {0x28u, 0x01u},\r
+ {0x29u, 0x68u},\r
+ {0x2Bu, 0x80u},\r
+ {0x2Cu, 0x24u},\r
+ {0x2Du, 0x40u},\r
+ {0x2Eu, 0x20u},\r
+ {0x30u, 0x80u},\r
+ {0x33u, 0x21u},\r
+ {0x34u, 0x01u},\r
+ {0x36u, 0x20u},\r
+ {0x38u, 0x18u},\r
+ {0x39u, 0xC2u},\r
+ {0x3Du, 0x80u},\r
+ {0x3Fu, 0x20u},\r
+ {0x5Cu, 0x80u},\r
+ {0x5Du, 0x05u},\r
+ {0x5Eu, 0x20u},\r
+ {0x64u, 0x02u},\r
+ {0x78u, 0x02u},\r
+ {0x7Au, 0x80u},\r
+ {0x84u, 0x10u},\r
+ {0x85u, 0x01u},\r
+ {0x87u, 0x08u},\r
+ {0x88u, 0x05u},\r
+ {0x8Bu, 0x08u},\r
+ {0x90u, 0x04u},\r
+ {0x91u, 0x84u},\r
+ {0x92u, 0x81u},\r
+ {0x96u, 0x42u},\r
+ {0x98u, 0x04u},\r
+ {0x99u, 0x90u},\r
+ {0x9Au, 0x08u},\r
+ {0x9Cu, 0x08u},\r
{0x9Eu, 0x10u},\r
- {0xA1u, 0x01u},\r
- {0xA3u, 0x10u},\r
- {0xA4u, 0x20u},\r
- {0xA5u, 0x04u},\r
- {0xA6u, 0x06u},\r
- {0xA7u, 0xA0u},\r
- {0xAAu, 0x40u},\r
- {0xABu, 0x04u},\r
- {0xACu, 0x40u},\r
- {0xADu, 0x20u},\r
- {0xAEu, 0x04u},\r
- {0xB2u, 0x02u},\r
- {0xB3u, 0x0Cu},\r
- {0xB4u, 0x20u},\r
- {0xB6u, 0x20u},\r
- {0xB7u, 0x02u},\r
- {0xC0u, 0xD3u},\r
+ {0xA1u, 0x40u},\r
+ {0xA2u, 0x98u},\r
+ {0xA3u, 0x30u},\r
+ {0xA4u, 0xA0u},\r
+ {0xA5u, 0x28u},\r
+ {0xA6u, 0x01u},\r
+ {0xA7u, 0x80u},\r
+ {0xAAu, 0x01u},\r
+ {0xABu, 0x01u},\r
+ {0xACu, 0x04u},\r
+ {0xADu, 0x41u},\r
+ {0xAEu, 0x05u},\r
+ {0xB2u, 0x10u},\r
+ {0xB4u, 0x80u},\r
+ {0xB7u, 0x40u},\r
+ {0xC0u, 0xF5u},\r
{0xC2u, 0xEEu},\r
- {0xC4u, 0xFFu},\r
- {0xCAu, 0xBFu},\r
- {0xCCu, 0xE7u},\r
- {0xCEu, 0xF3u},\r
- {0xD6u, 0x0Eu},\r
- {0xD8u, 0x0Eu},\r
- {0xE0u, 0x40u},\r
- {0xE2u, 0x30u},\r
+ {0xC4u, 0xF6u},\r
+ {0xCAu, 0x7Fu},\r
+ {0xCCu, 0xADu},\r
+ {0xCEu, 0x3Fu},\r
+ {0xD6u, 0xF0u},\r
+ {0xD8u, 0x10u},\r
{0xE4u, 0x80u},\r
- {0xE6u, 0x2Bu},\r
- {0xE8u, 0x40u},\r
- {0xEAu, 0x95u},\r
- {0xECu, 0x40u},\r
- {0xEEu, 0x80u},\r
- {0x01u, 0x3Fu},\r
- {0x04u, 0x69u},\r
- {0x05u, 0x3Fu},\r
- {0x06u, 0x96u},\r
- {0x08u, 0x0Fu},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0xF0u},\r
- {0x0Bu, 0x02u},\r
- {0x0Cu, 0xFFu},\r
- {0x0Fu, 0x3Fu},\r
- {0x14u, 0x55u},\r
- {0x16u, 0xAAu},\r
- {0x17u, 0x3Fu},\r
- {0x18u, 0xFFu},\r
- {0x1Bu, 0x3Fu},\r
- {0x1Cu, 0x33u},\r
- {0x1Du, 0x10u},\r
- {0x1Eu, 0xCCu},\r
- {0x1Fu, 0x20u},\r
- {0x21u, 0x04u},\r
- {0x22u, 0xFFu},\r
+ {0xE6u, 0x21u},\r
+ {0xE8u, 0x80u},\r
+ {0xECu, 0x09u},\r
+ {0xEEu, 0xC0u},\r
+ {0x00u, 0x80u},\r
+ {0x02u, 0x40u},\r
+ {0x06u, 0x1Cu},\r
+ {0x0Cu, 0x80u},\r
+ {0x0Du, 0x0Au},\r
+ {0x0Eu, 0x41u},\r
+ {0x0Fu, 0x14u},\r
+ {0x14u, 0x24u},\r
+ {0x16u, 0x08u},\r
+ {0x18u, 0x80u},\r
+ {0x1Au, 0x40u},\r
+ {0x1Bu, 0x04u},\r
+ {0x1Cu, 0x40u},\r
+ {0x1Eu, 0x80u},\r
+ {0x1Fu, 0x10u},\r
+ {0x20u, 0x80u},\r
+ {0x22u, 0x42u},\r
{0x23u, 0x08u},\r
- {0x25u, 0x10u},\r
- {0x26u, 0xFFu},\r
- {0x27u, 0x20u},\r
- {0x29u, 0x04u},\r
- {0x2Au, 0xFFu},\r
- {0x2Bu, 0x08u},\r
- {0x2Du, 0x01u},\r
- {0x2Fu, 0x02u},\r
- {0x32u, 0xFFu},\r
- {0x33u, 0x0Cu},\r
- {0x35u, 0x03u},\r
- {0x37u, 0x30u},\r
- {0x3Au, 0x08u},\r
- {0x3Bu, 0xA8u},\r
+ {0x26u, 0x20u},\r
+ {0x27u, 0x02u},\r
+ {0x28u, 0x10u},\r
+ {0x2Au, 0x20u},\r
+ {0x2Cu, 0x28u},\r
+ {0x2Eu, 0x14u},\r
+ {0x2Fu, 0x01u},\r
+ {0x30u, 0x01u},\r
+ {0x31u, 0x01u},\r
+ {0x32u, 0x3Cu},\r
+ {0x33u, 0x18u},\r
+ {0x34u, 0x02u},\r
+ {0x36u, 0xC0u},\r
+ {0x37u, 0x06u},\r
+ {0x3Au, 0x80u},\r
+ {0x3Fu, 0x44u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0xE0u},\r
- {0x83u, 0x70u},\r
- {0x84u, 0x14u},\r
- {0x85u, 0x40u},\r
- {0x87u, 0x1Fu},\r
- {0x88u, 0x09u},\r
- {0x89u, 0x10u},\r
- {0x8Au, 0xF2u},\r
- {0x8Bu, 0x2Fu},\r
- {0x91u, 0x03u},\r
- {0x92u, 0x09u},\r
- {0x93u, 0x0Cu},\r
- {0x94u, 0x06u},\r
- {0x95u, 0x0Fu},\r
- {0x96u, 0xF8u},\r
- {0x98u, 0x40u},\r
- {0x99u, 0x20u},\r
- {0x9Au, 0x80u},\r
- {0x9Bu, 0x4Fu},\r
- {0x9Cu, 0x40u},\r
- {0x9Eu, 0x80u},\r
- {0xA2u, 0xFFu},\r
- {0xA5u, 0x06u},\r
- {0xA7u, 0x09u},\r
- {0xA8u, 0x01u},\r
- {0xA9u, 0x05u},\r
- {0xABu, 0x0Au},\r
- {0xACu, 0xC6u},\r
- {0xAEu, 0x19u},\r
- {0xB1u, 0x7Fu},\r
- {0xB2u, 0x3Fu},\r
- {0xB4u, 0xC0u},\r
- {0xBAu, 0x20u},\r
+ {0x81u, 0x44u},\r
+ {0x83u, 0x08u},\r
+ {0x86u, 0x10u},\r
+ {0x87u, 0x17u},\r
+ {0x8Bu, 0x40u},\r
+ {0x8Cu, 0x0Au},\r
+ {0x8Du, 0x4Au},\r
+ {0x8Eu, 0x05u},\r
+ {0x8Fu, 0x05u},\r
+ {0x91u, 0x10u},\r
+ {0x92u, 0x20u},\r
+ {0x93u, 0x20u},\r
+ {0x94u, 0x09u},\r
+ {0x96u, 0x02u},\r
+ {0x97u, 0x20u},\r
+ {0x9Au, 0x07u},\r
+ {0xA0u, 0x04u},\r
+ {0xA2u, 0x08u},\r
+ {0xA5u, 0x49u},\r
+ {0xA7u, 0x02u},\r
+ {0xAAu, 0x08u},\r
+ {0xABu, 0x08u},\r
+ {0xACu, 0x10u},\r
+ {0xAEu, 0x20u},\r
+ {0xB0u, 0x30u},\r
+ {0xB1u, 0x30u},\r
+ {0xB3u, 0x0Fu},\r
+ {0xB4u, 0x0Fu},\r
+ {0xB7u, 0x40u},\r
+ {0xBEu, 0x01u},\r
+ {0xBFu, 0x41u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
{0xDCu, 0x11u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x80u},\r
- {0x02u, 0x10u},\r
- {0x03u, 0x08u},\r
- {0x04u, 0x22u},\r
- {0x05u, 0x10u},\r
- {0x06u, 0x20u},\r
- {0x08u, 0x08u},\r
- {0x0Bu, 0x09u},\r
- {0x0Cu, 0x08u},\r
- {0x0Du, 0x20u},\r
- {0x0Eu, 0x90u},\r
- {0x0Fu, 0x02u},\r
- {0x10u, 0x08u},\r
- {0x11u, 0x08u},\r
- {0x12u, 0x40u},\r
- {0x14u, 0x04u},\r
- {0x15u, 0x02u},\r
- {0x16u, 0x42u},\r
- {0x1Bu, 0x08u},\r
- {0x1Du, 0x20u},\r
- {0x1Eu, 0x20u},\r
- {0x1Fu, 0x04u},\r
- {0x21u, 0x10u},\r
- {0x22u, 0x44u},\r
- {0x23u, 0x0Au},\r
- {0x25u, 0x01u},\r
- {0x28u, 0x4Au},\r
- {0x2Bu, 0x10u},\r
- {0x2Eu, 0x04u},\r
- {0x2Fu, 0x08u},\r
- {0x30u, 0x08u},\r
- {0x31u, 0x10u},\r
- {0x32u, 0x40u},\r
- {0x34u, 0x04u},\r
- {0x36u, 0x16u},\r
- {0x38u, 0x02u},\r
- {0x39u, 0x20u},\r
- {0x3Au, 0x40u},\r
- {0x3Bu, 0x08u},\r
- {0x3Du, 0x0Au},\r
- {0x3Eu, 0x10u},\r
- {0x58u, 0x10u},\r
- {0x5Au, 0x40u},\r
- {0x5Bu, 0x04u},\r
- {0x60u, 0x08u},\r
- {0x63u, 0x23u},\r
- {0x81u, 0x20u},\r
- {0x86u, 0x48u},\r
- {0x87u, 0x80u},\r
- {0x88u, 0x30u},\r
- {0x89u, 0x02u},\r
- {0x8Fu, 0x20u},\r
- {0xC0u, 0x77u},\r
- {0xC2u, 0xF7u},\r
- {0xC4u, 0xDEu},\r
- {0xCAu, 0x6Fu},\r
- {0xCCu, 0xEEu},\r
- {0xCEu, 0xEFu},\r
- {0xD6u, 0x0Eu},\r
- {0xD8u, 0x0Eu},\r
- {0xE0u, 0x80u},\r
- {0xE2u, 0x40u},\r
- {0xE4u, 0x04u},\r
- {0xE6u, 0x20u},\r
- {0x02u, 0x02u},\r
- {0x06u, 0x30u},\r
- {0x08u, 0x04u},\r
+ {0x00u, 0x84u},\r
+ {0x01u, 0x08u},\r
+ {0x02u, 0x40u},\r
+ {0x04u, 0x40u},\r
+ {0x06u, 0x10u},\r
{0x09u, 0x08u},\r
- {0x0Au, 0x08u},\r
- {0x0Bu, 0x22u},\r
- {0x0Cu, 0x01u},\r
- {0x0Eu, 0x02u},\r
- {0x10u, 0x20u},\r
- {0x11u, 0x14u},\r
- {0x12u, 0x0Cu},\r
- {0x13u, 0x08u},\r
- {0x14u, 0x10u},\r
- {0x15u, 0x09u},\r
- {0x16u, 0x0Cu},\r
- {0x17u, 0x10u},\r
- {0x19u, 0x37u},\r
- {0x1Au, 0x01u},\r
- {0x1Eu, 0x04u},\r
- {0x27u, 0x07u},\r
- {0x2Au, 0x48u},\r
- {0x30u, 0x03u},\r
- {0x34u, 0x3Cu},\r
- {0x35u, 0x38u},\r
- {0x36u, 0x40u},\r
- {0x37u, 0x07u},\r
- {0x39u, 0x20u},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x40u},\r
- {0x40u, 0x24u},\r
+ {0x0Au, 0x05u},\r
+ {0x0Du, 0x08u},\r
+ {0x0Eu, 0x48u},\r
+ {0x10u, 0x54u},\r
+ {0x11u, 0x80u},\r
+ {0x15u, 0x85u},\r
+ {0x16u, 0x24u},\r
+ {0x19u, 0x0Au},\r
+ {0x1Au, 0x05u},\r
+ {0x1Bu, 0x40u},\r
+ {0x1Eu, 0x08u},\r
+ {0x1Fu, 0x21u},\r
+ {0x20u, 0x82u},\r
+ {0x22u, 0x04u},\r
+ {0x25u, 0x06u},\r
+ {0x26u, 0x88u},\r
+ {0x29u, 0x08u},\r
+ {0x2Au, 0x40u},\r
+ {0x2Bu, 0x80u},\r
+ {0x2Cu, 0x60u},\r
+ {0x2Du, 0x02u},\r
+ {0x2Eu, 0x10u},\r
+ {0x30u, 0x80u},\r
+ {0x31u, 0x20u},\r
+ {0x34u, 0x08u},\r
+ {0x37u, 0x01u},\r
+ {0x39u, 0x80u},\r
+ {0x3Cu, 0x40u},\r
+ {0x3Du, 0x89u},\r
+ {0x3Eu, 0x20u},\r
+ {0x58u, 0x80u},\r
+ {0x5Du, 0x40u},\r
+ {0x62u, 0x40u},\r
+ {0x64u, 0x02u},\r
+ {0x65u, 0x80u},\r
+ {0x69u, 0x80u},\r
+ {0x6Au, 0x80u},\r
+ {0x6Bu, 0x01u},\r
+ {0x81u, 0x40u},\r
+ {0x82u, 0x24u},\r
+ {0x83u, 0x10u},\r
+ {0x84u, 0x01u},\r
+ {0x85u, 0x02u},\r
+ {0x86u, 0x08u},\r
+ {0x88u, 0x10u},\r
+ {0x8Cu, 0x02u},\r
+ {0x8Du, 0x10u},\r
+ {0x8Eu, 0x10u},\r
+ {0xC0u, 0xADu},\r
+ {0xC2u, 0x77u},\r
+ {0xC4u, 0xDFu},\r
+ {0xCAu, 0x6Bu},\r
+ {0xCCu, 0xCCu},\r
+ {0xCEu, 0xF8u},\r
+ {0xD6u, 0x18u},\r
+ {0xD8u, 0x18u},\r
+ {0xE0u, 0x60u},\r
+ {0xE2u, 0x10u},\r
+ {0xE4u, 0x10u},\r
+ {0xE6u, 0x04u},\r
+ {0x01u, 0x5Cu},\r
+ {0x05u, 0x11u},\r
+ {0x07u, 0x22u},\r
+ {0x09u, 0x50u},\r
+ {0x0Bu, 0x0Cu},\r
+ {0x0Du, 0x0Cu},\r
+ {0x0Fu, 0x50u},\r
+ {0x15u, 0x30u},\r
+ {0x17u, 0x0Fu},\r
+ {0x19u, 0x54u},\r
+ {0x1Bu, 0x08u},\r
+ {0x1Du, 0x5Cu},\r
+ {0x21u, 0x08u},\r
+ {0x27u, 0x40u},\r
+ {0x29u, 0x21u},\r
+ {0x2Bu, 0x1Eu},\r
+ {0x2Du, 0x24u},\r
+ {0x2Fu, 0x10u},\r
+ {0x31u, 0x30u},\r
+ {0x33u, 0x40u},\r
+ {0x35u, 0x0Fu},\r
+ {0x3Bu, 0x02u},\r
+ {0x3Fu, 0x04u},\r
+ {0x40u, 0x23u},\r
{0x41u, 0x06u},\r
- {0x42u, 0x30u},\r
+ {0x42u, 0x40u},\r
{0x44u, 0x01u},\r
- {0x45u, 0xFEu},\r
- {0x46u, 0xDCu},\r
- {0x47u, 0x0Bu},\r
- {0x48u, 0x1Fu},\r
+ {0x45u, 0xBDu},\r
+ {0x46u, 0xF0u},\r
+ {0x47u, 0xCEu},\r
+ {0x48u, 0x3Bu},\r
{0x49u, 0xFFu},\r
{0x4Au, 0xFFu},\r
{0x4Bu, 0xFFu},\r
{0x4Eu, 0xF0u},\r
{0x4Fu, 0x08u},\r
{0x50u, 0x04u},\r
- {0x58u, 0x04u},\r
+ {0x54u, 0x40u},\r
+ {0x56u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Au, 0x04u},\r
+ {0x5Bu, 0x04u},\r
{0x5Fu, 0x01u},\r
{0x62u, 0xC0u},\r
{0x64u, 0x40u},\r
{0x6Du, 0x01u},\r
{0x6Eu, 0x40u},\r
{0x6Fu, 0x01u},\r
- {0x81u, 0x02u},\r
- {0x83u, 0x09u},\r
- {0x8Du, 0x02u},\r
- {0x8Fu, 0x01u},\r
- {0x91u, 0x02u},\r
- {0x93u, 0x11u},\r
- {0x95u, 0x02u},\r
- {0x97u, 0x05u},\r
- {0x99u, 0x01u},\r
- {0x9Bu, 0x02u},\r
- {0xA8u, 0x01u},\r
- {0xB1u, 0x10u},\r
- {0xB2u, 0x01u},\r
- {0xB3u, 0x03u},\r
- {0xB5u, 0x08u},\r
- {0xB7u, 0x04u},\r
- {0xBBu, 0x08u},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x99u},\r
- {0xDDu, 0x90u},\r
- {0xDFu, 0x01u},\r
- {0x00u, 0x04u},\r
- {0x01u, 0x40u},\r
- {0x02u, 0x08u},\r
- {0x03u, 0x40u},\r
- {0x08u, 0x28u},\r
- {0x09u, 0x02u},\r
- {0x0Au, 0x02u},\r
- {0x10u, 0x08u},\r
- {0x17u, 0x20u},\r
- {0x18u, 0x04u},\r
- {0x19u, 0x01u},\r
- {0x1Au, 0x02u},\r
- {0x1Bu, 0x10u},\r
- {0x1Fu, 0x04u},\r
- {0x21u, 0x40u},\r
- {0x22u, 0x10u},\r
- {0x24u, 0x40u},\r
- {0x26u, 0x04u},\r
- {0x27u, 0x2Au},\r
- {0x2Bu, 0x10u},\r
- {0x31u, 0x02u},\r
- {0x32u, 0x18u},\r
- {0x37u, 0x2Au},\r
- {0x39u, 0x20u},\r
- {0x3Cu, 0x40u},\r
- {0x3Fu, 0x01u},\r
- {0x40u, 0x0Au},\r
- {0x41u, 0x12u},\r
- {0x42u, 0x14u},\r
- {0x49u, 0x04u},\r
- {0x4Au, 0x88u},\r
- {0x50u, 0x08u},\r
- {0x53u, 0x90u},\r
- {0x5Cu, 0x80u},\r
- {0x67u, 0x01u},\r
- {0x6Eu, 0x02u},\r
- {0x6Fu, 0x2Au},\r
- {0x76u, 0x25u},\r
- {0x77u, 0x40u},\r
- {0x84u, 0x88u},\r
- {0x8Au, 0x80u},\r
+ {0x80u, 0x20u},\r
+ {0x82u, 0x01u},\r
+ {0x84u, 0x10u},\r
+ {0x85u, 0x04u},\r
+ {0x86u, 0x42u},\r
+ {0x87u, 0x23u},\r
+ {0x89u, 0x48u},\r
+ {0x8Bu, 0x03u},\r
{0x8Cu, 0x02u},\r
- {0x8Du, 0x41u},\r
- {0x91u, 0x40u},\r
- {0x92u, 0x14u},\r
- {0x97u, 0x28u},\r
- {0x98u, 0x20u},\r
- {0x9Du, 0x04u},\r
- {0x9Eu, 0x25u},\r
- {0x9Fu, 0x40u},\r
- {0xA1u, 0x02u},\r
- {0xA2u, 0x08u},\r
- {0xA6u, 0x05u},\r
- {0xA7u, 0xAAu},\r
- {0xAAu, 0x10u},\r
- {0xABu, 0x80u},\r
- {0xB2u, 0x04u},\r
- {0xB5u, 0x08u},\r
- {0xB6u, 0x01u},\r
- {0xC0u, 0x0Fu},\r
- {0xC2u, 0x0Fu},\r
- {0xC4u, 0x42u},\r
- {0xCAu, 0x02u},\r
- {0xCCu, 0xE7u},\r
- {0xCEu, 0x94u},\r
- {0xD0u, 0x0Fu},\r
- {0xD2u, 0x04u},\r
- {0xD6u, 0x10u},\r
- {0xD8u, 0x10u},\r
- {0xE0u, 0x12u},\r
- {0xE6u, 0x52u},\r
- {0xEAu, 0x04u},\r
- {0x00u, 0x0Fu},\r
- {0x01u, 0x05u},\r
- {0x02u, 0xF0u},\r
- {0x03u, 0x0Au},\r
- {0x07u, 0xFFu},\r
- {0x08u, 0xFFu},\r
- {0x09u, 0x03u},\r
- {0x0Bu, 0x0Cu},\r
- {0x0Cu, 0x60u},\r
- {0x0Du, 0x0Fu},\r
- {0x0Eu, 0x90u},\r
- {0x0Fu, 0xF0u},\r
- {0x11u, 0xFFu},\r
- {0x12u, 0xFFu},\r
- {0x14u, 0x03u},\r
- {0x16u, 0x0Cu},\r
- {0x19u, 0xFFu},\r
- {0x1Au, 0xFFu},\r
- {0x1Cu, 0x05u},\r
- {0x1Du, 0x09u},\r
- {0x1Eu, 0x0Au},\r
- {0x1Fu, 0x06u},\r
- {0x20u, 0x06u},\r
- {0x22u, 0x09u},\r
- {0x24u, 0x30u},\r
- {0x25u, 0x30u},\r
- {0x26u, 0xC0u},\r
- {0x27u, 0xC0u},\r
- {0x28u, 0x50u},\r
- {0x29u, 0x50u},\r
- {0x2Au, 0xA0u},\r
- {0x2Bu, 0xA0u},\r
- {0x2Du, 0x90u},\r
- {0x2Fu, 0x60u},\r
- {0x30u, 0xFFu},\r
- {0x31u, 0xFFu},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x01u},\r
- {0x58u, 0x04u},\r
- {0x59u, 0x04u},\r
- {0x5Fu, 0x01u},\r
- {0x82u, 0x0Au},\r
- {0x85u, 0x60u},\r
- {0x87u, 0x90u},\r
- {0x88u, 0x01u},\r
- {0x89u, 0x05u},\r
- {0x8Au, 0x04u},\r
- {0x8Bu, 0x0Au},\r
- {0x8Du, 0x0Fu},\r
- {0x8Fu, 0xF0u},\r
- {0x90u, 0x01u},\r
- {0x92u, 0x04u},\r
- {0x96u, 0x02u},\r
- {0x98u, 0x05u},\r
- {0x99u, 0x06u},\r
- {0x9Bu, 0x09u},\r
- {0x9Cu, 0x0Au},\r
- {0x9Du, 0x30u},\r
- {0x9Fu, 0xC0u},\r
- {0xA0u, 0x0Au},\r
- {0xA4u, 0x0Au},\r
- {0xA5u, 0x03u},\r
- {0xA7u, 0x0Cu},\r
- {0xA8u, 0x0Au},\r
- {0xA9u, 0x50u},\r
- {0xABu, 0xA0u},\r
- {0xB0u, 0x04u},\r
- {0xB2u, 0x08u},\r
- {0xB4u, 0x02u},\r
- {0xB5u, 0xFFu},\r
- {0xB6u, 0x01u},\r
- {0xBEu, 0x55u},\r
- {0xBFu, 0x10u},\r
- {0xD4u, 0x09u},\r
- {0xD6u, 0x04u},\r
+ {0x90u, 0x02u},\r
+ {0x91u, 0x80u},\r
+ {0x94u, 0x44u},\r
+ {0x96u, 0x10u},\r
+ {0x97u, 0x7Cu},\r
+ {0x98u, 0x02u},\r
+ {0x99u, 0x11u},\r
+ {0x9Bu, 0x02u},\r
+ {0x9Cu, 0x02u},\r
+ {0xA0u, 0x08u},\r
+ {0xA3u, 0x02u},\r
+ {0xA5u, 0x80u},\r
+ {0xA8u, 0x0Eu},\r
+ {0xA9u, 0x70u},\r
+ {0xAAu, 0x30u},\r
+ {0xACu, 0x02u},\r
+ {0xAFu, 0x01u},\r
+ {0xB0u, 0x01u},\r
+ {0xB3u, 0x70u},\r
+ {0xB4u, 0x7Eu},\r
+ {0xB5u, 0x0Fu},\r
+ {0xB7u, 0x80u},\r
+ {0xB8u, 0x20u},\r
+ {0xB9u, 0x80u},\r
+ {0xBEu, 0x10u},\r
+ {0xBFu, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x02u},\r
- {0x02u, 0x08u},\r
- {0x05u, 0x90u},\r
- {0x06u, 0x80u},\r
- {0x09u, 0x0Au},\r
- {0x0Au, 0x05u},\r
- {0x0Bu, 0x20u},\r
- {0x0Cu, 0x01u},\r
- {0x0Fu, 0x19u},\r
- {0x10u, 0xA0u},\r
- {0x11u, 0x10u},\r
- {0x14u, 0x44u},\r
- {0x15u, 0x04u},\r
- {0x18u, 0x10u},\r
- {0x19u, 0x40u},\r
- {0x1Au, 0x58u},\r
- {0x1Cu, 0x80u},\r
+ {0x04u, 0x04u},\r
+ {0x05u, 0x02u},\r
+ {0x06u, 0x02u},\r
+ {0x0Cu, 0xA1u},\r
+ {0x0Du, 0x08u},\r
+ {0x0Fu, 0x40u},\r
+ {0x15u, 0x60u},\r
+ {0x17u, 0x02u},\r
+ {0x1Fu, 0x22u},\r
+ {0x20u, 0x18u},\r
+ {0x21u, 0x10u},\r
{0x22u, 0x20u},\r
- {0x26u, 0x02u},\r
- {0x28u, 0x20u},\r
- {0x29u, 0x08u},\r
- {0x2Au, 0x30u},\r
- {0x2Cu, 0x04u},\r
- {0x2Du, 0x84u},\r
- {0x2Fu, 0x2Au},\r
- {0x31u, 0x20u},\r
- {0x33u, 0x40u},\r
- {0x34u, 0x41u},\r
- {0x35u, 0x11u},\r
- {0x36u, 0xA0u},\r
- {0x38u, 0x20u},\r
- {0x39u, 0x40u},\r
- {0x3Au, 0x84u},\r
- {0x3Du, 0x40u},\r
- {0x3Fu, 0x19u},\r
- {0x58u, 0x02u},\r
- {0x59u, 0x04u},\r
- {0x5Au, 0x60u},\r
- {0x61u, 0x40u},\r
- {0x63u, 0x40u},\r
- {0x80u, 0x12u},\r
- {0x87u, 0x40u},\r
- {0x8Du, 0x40u},\r
- {0x90u, 0x20u},\r
- {0x91u, 0x50u},\r
- {0x92u, 0x05u},\r
- {0x93u, 0x11u},\r
- {0x97u, 0x08u},\r
- {0x99u, 0x09u},\r
- {0x9Du, 0x10u},\r
- {0x9Eu, 0x15u},\r
- {0xA0u, 0xA1u},\r
- {0xA1u, 0x22u},\r
- {0xA2u, 0x88u},\r
+ {0x23u, 0x44u},\r
+ {0x26u, 0x84u},\r
+ {0x27u, 0x0Au},\r
+ {0x28u, 0x01u},\r
+ {0x29u, 0x04u},\r
+ {0x2Au, 0x01u},\r
+ {0x2Bu, 0x04u},\r
+ {0x2Du, 0x02u},\r
+ {0x2Eu, 0x20u},\r
+ {0x2Fu, 0x22u},\r
+ {0x30u, 0xA0u},\r
+ {0x31u, 0x08u},\r
+ {0x36u, 0x21u},\r
+ {0x37u, 0x08u},\r
+ {0x39u, 0x50u},\r
+ {0x3Au, 0x02u},\r
+ {0x3Bu, 0x04u},\r
+ {0x3Cu, 0x24u},\r
+ {0x40u, 0x04u},\r
+ {0x41u, 0x09u},\r
+ {0x42u, 0x01u},\r
+ {0x48u, 0x04u},\r
+ {0x49u, 0x06u},\r
+ {0x51u, 0x20u},\r
+ {0x52u, 0x01u},\r
+ {0x53u, 0x04u},\r
+ {0x60u, 0x92u},\r
+ {0x61u, 0x20u},\r
+ {0x82u, 0x20u},\r
+ {0x84u, 0x04u},\r
+ {0x86u, 0x01u},\r
+ {0x8Cu, 0x02u},\r
+ {0x8Du, 0x04u},\r
+ {0x8Eu, 0x04u},\r
+ {0x90u, 0x04u},\r
+ {0x91u, 0x52u},\r
+ {0x97u, 0x48u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Cu, 0x80u},\r
+ {0x9Du, 0x02u},\r
+ {0x9Eu, 0x01u},\r
+ {0xA0u, 0xB0u},\r
+ {0xA1u, 0x08u},\r
+ {0xA2u, 0x01u},\r
{0xA3u, 0x04u},\r
- {0xA4u, 0x40u},\r
- {0xA6u, 0x27u},\r
- {0xA7u, 0xAAu},\r
- {0xA8u, 0x0Cu},\r
- {0xABu, 0x20u},\r
- {0xAEu, 0x04u},\r
- {0xB0u, 0x01u},\r
- {0xB5u, 0x14u},\r
- {0xC0u, 0xDAu},\r
- {0xC2u, 0xFFu},\r
- {0xC4u, 0x7Eu},\r
- {0xCAu, 0x76u},\r
- {0xCCu, 0xBCu},\r
- {0xCEu, 0xFEu},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x09u},\r
- {0xE2u, 0x08u},\r
- {0xE8u, 0x04u},\r
- {0xECu, 0x08u},\r
- {0x00u, 0x10u},\r
+ {0xA6u, 0xA0u},\r
+ {0xABu, 0x01u},\r
+ {0xB2u, 0x08u},\r
+ {0xB3u, 0x20u},\r
+ {0xB4u, 0x04u},\r
+ {0xC0u, 0xB0u},\r
+ {0xC2u, 0xF0u},\r
+ {0xC4u, 0xD0u},\r
+ {0xCAu, 0xFFu},\r
+ {0xCCu, 0xEEu},\r
+ {0xCEu, 0x6Fu},\r
+ {0xD0u, 0x0Fu},\r
+ {0xD2u, 0x04u},\r
+ {0xD8u, 0x0Fu},\r
+ {0xE2u, 0x44u},\r
+ {0xE4u, 0x02u},\r
+ {0xE8u, 0x01u},\r
+ {0x00u, 0x03u},\r
{0x01u, 0xC0u},\r
- {0x03u, 0x08u},\r
- {0x04u, 0x07u},\r
- {0x05u, 0xC0u},\r
- {0x06u, 0x18u},\r
- {0x07u, 0x04u},\r
- {0x08u, 0x22u},\r
- {0x0Au, 0x08u},\r
- {0x0Cu, 0x40u},\r
- {0x0Du, 0xC0u},\r
- {0x0Fu, 0x01u},\r
- {0x10u, 0x40u},\r
- {0x11u, 0x80u},\r
- {0x14u, 0x04u},\r
- {0x17u, 0xFFu},\r
- {0x18u, 0x01u},\r
- {0x1Bu, 0x60u},\r
- {0x1Cu, 0x01u},\r
- {0x1Fu, 0x9Fu},\r
- {0x20u, 0x01u},\r
- {0x21u, 0x1Fu},\r
- {0x23u, 0x20u},\r
- {0x24u, 0x08u},\r
- {0x25u, 0x90u},\r
- {0x26u, 0x21u},\r
- {0x27u, 0x40u},\r
- {0x28u, 0x01u},\r
- {0x29u, 0xC0u},\r
- {0x2Bu, 0x02u},\r
- {0x2Cu, 0x01u},\r
- {0x2Du, 0x7Fu},\r
- {0x2Fu, 0x80u},\r
- {0x30u, 0x3Fu},\r
- {0x32u, 0x40u},\r
- {0x37u, 0xFFu},\r
- {0x38u, 0x0Au},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x40u},\r
- {0x54u, 0x40u},\r
- {0x56u, 0x04u},\r
+ {0x02u, 0x0Cu},\r
+ {0x03u, 0x01u},\r
+ {0x04u, 0x05u},\r
+ {0x06u, 0x0Au},\r
+ {0x07u, 0xFFu},\r
+ {0x08u, 0x40u},\r
+ {0x09u, 0xC0u},\r
+ {0x0Au, 0x1Fu},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Cu, 0x10u},\r
+ {0x0Du, 0x80u},\r
+ {0x0Eu, 0x2Fu},\r
+ {0x13u, 0x9Fu},\r
+ {0x14u, 0x06u},\r
+ {0x15u, 0x7Fu},\r
+ {0x16u, 0x09u},\r
+ {0x17u, 0x80u},\r
+ {0x19u, 0x1Fu},\r
+ {0x1Au, 0x70u},\r
+ {0x1Bu, 0x20u},\r
+ {0x1Fu, 0x60u},\r
+ {0x21u, 0xC0u},\r
+ {0x23u, 0x02u},\r
+ {0x24u, 0x20u},\r
+ {0x25u, 0xC0u},\r
+ {0x26u, 0x4Fu},\r
+ {0x27u, 0x04u},\r
+ {0x28u, 0x0Fu},\r
+ {0x2Du, 0x90u},\r
+ {0x2Fu, 0x40u},\r
+ {0x31u, 0xFFu},\r
+ {0x34u, 0x7Fu},\r
+ {0x3Fu, 0x01u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x01u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x10u},\r
+ {0x80u, 0xFFu},\r
{0x81u, 0x04u},\r
- {0x82u, 0x20u},\r
- {0x84u, 0x01u},\r
- {0x86u, 0x02u},\r
- {0x8Cu, 0x02u},\r
- {0x8Eu, 0x09u},\r
- {0x90u, 0x02u},\r
- {0x92u, 0x05u},\r
- {0x94u, 0x02u},\r
- {0x96u, 0x01u},\r
- {0x9Cu, 0x02u},\r
- {0x9Eu, 0x01u},\r
- {0x9Fu, 0x01u},\r
- {0xA2u, 0x20u},\r
- {0xA6u, 0x10u},\r
- {0xAFu, 0x02u},\r
- {0xB0u, 0x04u},\r
- {0xB1u, 0x02u},\r
- {0xB2u, 0x08u},\r
- {0xB3u, 0x01u},\r
- {0xB4u, 0x03u},\r
- {0xB6u, 0x30u},\r
- {0xB7u, 0x04u},\r
+ {0x83u, 0x20u},\r
+ {0x84u, 0x33u},\r
+ {0x85u, 0x39u},\r
+ {0x86u, 0xCCu},\r
+ {0x87u, 0x06u},\r
+ {0x88u, 0x0Fu},\r
+ {0x8Au, 0xF0u},\r
+ {0x8Bu, 0x46u},\r
+ {0x8Du, 0x46u},\r
+ {0x8Eu, 0xFFu},\r
+ {0x90u, 0x69u},\r
+ {0x92u, 0x96u},\r
+ {0x95u, 0x01u},\r
+ {0x97u, 0x5Eu},\r
+ {0x98u, 0x55u},\r
+ {0x99u, 0x42u},\r
+ {0x9Au, 0xAAu},\r
+ {0x9Bu, 0x04u},\r
+ {0x9Du, 0x46u},\r
+ {0xA1u, 0x46u},\r
+ {0xA2u, 0xFFu},\r
+ {0xA4u, 0xFFu},\r
+ {0xA5u, 0x77u},\r
+ {0xA7u, 0x08u},\r
+ {0xAAu, 0xFFu},\r
+ {0xADu, 0x42u},\r
+ {0xB3u, 0x70u},\r
+ {0xB4u, 0xFFu},\r
+ {0xB5u, 0x0Fu},\r
+ {0xB9u, 0x20u},\r
{0xBAu, 0x20u},\r
- {0xBEu, 0x40u},\r
- {0xD6u, 0x08u},\r
+ {0xBBu, 0x0Cu},\r
+ {0xD6u, 0x02u},\r
+ {0xD7u, 0x20u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x99u},\r
- {0xDDu, 0x90u},\r
- {0xDFu, 0x01u},\r
- {0x00u, 0x44u},\r
- {0x01u, 0x02u},\r
- {0x04u, 0x20u},\r
- {0x05u, 0x08u},\r
- {0x07u, 0x81u},\r
- {0x09u, 0x82u},\r
- {0x0Au, 0x10u},\r
- {0x0Eu, 0xA4u},\r
- {0x0Fu, 0x02u},\r
- {0x11u, 0x06u},\r
- {0x14u, 0x04u},\r
- {0x16u, 0x01u},\r
- {0x17u, 0x0Au},\r
- {0x18u, 0x46u},\r
- {0x1Au, 0x10u},\r
- {0x1Eu, 0xA0u},\r
- {0x21u, 0x42u},\r
- {0x22u, 0x04u},\r
- {0x27u, 0x01u},\r
- {0x29u, 0x40u},\r
- {0x2Cu, 0x06u},\r
- {0x2Fu, 0xA0u},\r
- {0x32u, 0x80u},\r
- {0x36u, 0x10u},\r
- {0x37u, 0x8Au},\r
- {0x39u, 0x02u},\r
- {0x3Eu, 0x06u},\r
- {0x3Fu, 0x80u},\r
- {0x5Au, 0x40u},\r
- {0x61u, 0xC0u},\r
- {0x64u, 0x20u},\r
- {0x66u, 0x80u},\r
- {0x67u, 0x88u},\r
- {0x87u, 0x40u},\r
- {0x8Du, 0x02u},\r
- {0x90u, 0x20u},\r
- {0x91u, 0x06u},\r
- {0x92u, 0x44u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x80u},\r
- {0x96u, 0x08u},\r
- {0x98u, 0x04u},\r
- {0x99u, 0x08u},\r
- {0x9Au, 0x03u},\r
- {0x9Bu, 0x0Au},\r
- {0xA0u, 0x02u},\r
- {0xA2u, 0x80u},\r
- {0xA3u, 0xE1u},\r
- {0xAAu, 0x20u},\r
- {0xABu, 0x08u},\r
- {0xADu, 0x08u},\r
- {0xAFu, 0x80u},\r
- {0xB0u, 0x40u},\r
- {0xB3u, 0x21u},\r
- {0xB5u, 0x08u},\r
- {0xB7u, 0x02u},\r
- {0xC0u, 0xFDu},\r
- {0xC2u, 0xFDu},\r
- {0xC4u, 0xFCu},\r
- {0xCAu, 0xF8u},\r
- {0xCCu, 0xF8u},\r
- {0xCEu, 0xD1u},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0xF8u},\r
- {0xE0u, 0x40u},\r
- {0xE8u, 0x80u},\r
- {0xECu, 0x50u},\r
- {0xB9u, 0x08u},\r
- {0xBFu, 0x04u},\r
- {0xD9u, 0x04u},\r
+ {0xDCu, 0x01u},\r
{0xDFu, 0x01u},\r
- {0x26u, 0x08u},\r
- {0x87u, 0x80u},\r
+ {0x00u, 0x01u},\r
+ {0x01u, 0x20u},\r
+ {0x02u, 0x10u},\r
+ {0x03u, 0x01u},\r
+ {0x04u, 0x2Au},\r
+ {0x06u, 0x04u},\r
+ {0x07u, 0x01u},\r
+ {0x08u, 0x02u},\r
+ {0x09u, 0x20u},\r
+ {0x0Eu, 0x28u},\r
+ {0x11u, 0x05u},\r
+ {0x12u, 0x04u},\r
+ {0x15u, 0x04u},\r
+ {0x17u, 0x10u},\r
+ {0x18u, 0x08u},\r
+ {0x19u, 0x20u},\r
+ {0x1Eu, 0x08u},\r
+ {0x1Fu, 0x20u},\r
+ {0x20u, 0x2Cu},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0x08u},\r
+ {0x26u, 0x01u},\r
+ {0x28u, 0x10u},\r
+ {0x2Au, 0x82u},\r
+ {0x2Cu, 0xA0u},\r
+ {0x2Du, 0x40u},\r
+ {0x30u, 0xA0u},\r
+ {0x31u, 0x08u},\r
+ {0x34u, 0x10u},\r
+ {0x35u, 0x02u},\r
+ {0x36u, 0xA8u},\r
+ {0x37u, 0x08u},\r
+ {0x38u, 0x04u},\r
+ {0x39u, 0x50u},\r
+ {0x3Au, 0x01u},\r
+ {0x3Bu, 0x01u},\r
+ {0x3Cu, 0x04u},\r
+ {0x3Eu, 0x92u},\r
+ {0x3Fu, 0x48u},\r
+ {0x63u, 0x02u},\r
+ {0x68u, 0xA8u},\r
+ {0x69u, 0x50u},\r
+ {0x6Au, 0x10u},\r
+ {0x72u, 0x02u},\r
+ {0x88u, 0x80u},\r
{0x8Bu, 0x04u},\r
- {0x97u, 0x08u},\r
- {0x9Fu, 0x80u},\r
- {0xA6u, 0x08u},\r
- {0xAAu, 0x08u},\r
- {0xB0u, 0x20u},\r
- {0xB4u, 0x01u},\r
- {0xB5u, 0x01u},\r
- {0xB6u, 0x80u},\r
+ {0x90u, 0x23u},\r
+ {0x91u, 0x07u},\r
+ {0x95u, 0x40u},\r
+ {0x98u, 0x02u},\r
+ {0x9Au, 0x10u},\r
+ {0x9Bu, 0x11u},\r
+ {0x9Eu, 0x02u},\r
+ {0x9Fu, 0x08u},\r
+ {0xA1u, 0x20u},\r
+ {0xA2u, 0x10u},\r
+ {0xA3u, 0x01u},\r
+ {0xA4u, 0xACu},\r
+ {0xA6u, 0x20u},\r
+ {0xABu, 0x58u},\r
+ {0xB1u, 0x01u},\r
+ {0xB3u, 0x04u},\r
+ {0xB4u, 0x80u},\r
+ {0xB6u, 0x10u},\r
+ {0xC0u, 0xFFu},\r
+ {0xC2u, 0x6Au},\r
+ {0xC4u, 0x6Eu},\r
+ {0xCAu, 0xDBu},\r
+ {0xCCu, 0xFEu},\r
+ {0xCEu, 0xFFu},\r
+ {0xD8u, 0x08u},\r
+ {0xE2u, 0x28u},\r
+ {0xE8u, 0x04u},\r
+ {0xEEu, 0x01u},\r
+ {0x39u, 0x20u},\r
+ {0x3Fu, 0x10u},\r
+ {0x59u, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x27u, 0x08u},\r
+ {0x87u, 0x08u},\r
+ {0x88u, 0x08u},\r
+ {0x90u, 0x04u},\r
+ {0x96u, 0x10u},\r
+ {0x97u, 0x80u},\r
+ {0x9Cu, 0x18u},\r
+ {0x9Du, 0xC0u},\r
+ {0xA6u, 0x20u},\r
+ {0xA7u, 0x40u},\r
+ {0xA8u, 0x04u},\r
+ {0xA9u, 0x04u},\r
+ {0xAAu, 0x01u},\r
+ {0xB0u, 0x02u},\r
+ {0xB1u, 0x02u},\r
+ {0xB5u, 0x10u},\r
{0xE0u, 0x80u},\r
- {0xE6u, 0x02u},\r
- {0xE8u, 0x90u},\r
- {0xECu, 0x10u},\r
- {0x12u, 0x02u},\r
+ {0xE8u, 0xE0u},\r
+ {0xEAu, 0x10u},\r
+ {0x80u, 0x04u},\r
+ {0x84u, 0x10u},\r
+ {0x86u, 0x20u},\r
+ {0x90u, 0x04u},\r
+ {0x9Cu, 0x10u},\r
+ {0xA6u, 0x20u},\r
+ {0xAAu, 0x10u},\r
+ {0xB1u, 0xC0u},\r
+ {0xB3u, 0x40u},\r
+ {0xB7u, 0x40u},\r
+ {0xE8u, 0x80u},\r
+ {0xECu, 0xC0u},\r
+ {0x12u, 0x08u},\r
{0x16u, 0x80u},\r
- {0x17u, 0x20u},\r
- {0x31u, 0x08u},\r
- {0x34u, 0x18u},\r
+ {0x17u, 0x80u},\r
+ {0x33u, 0x04u},\r
+ {0x35u, 0x08u},\r
+ {0x36u, 0x80u},\r
{0x3Au, 0x81u},\r
- {0x3Eu, 0x01u},\r
+ {0x3Du, 0x04u},\r
{0x3Fu, 0x20u},\r
- {0x42u, 0x08u},\r
- {0x53u, 0x01u},\r
- {0x5Bu, 0x08u},\r
- {0x5Du, 0x02u},\r
- {0x62u, 0x20u},\r
- {0x66u, 0x04u},\r
- {0x77u, 0x10u},\r
- {0x7Eu, 0x02u},\r
+ {0x43u, 0x20u},\r
+ {0x52u, 0x20u},\r
+ {0x5Bu, 0x01u},\r
+ {0x60u, 0x20u},\r
+ {0x64u, 0x08u},\r
+ {0x65u, 0x40u},\r
+ {0x82u, 0x01u},\r
+ {0x85u, 0x40u},\r
+ {0x87u, 0x01u},\r
{0xC4u, 0xE0u},\r
{0xCCu, 0xE0u},\r
{0xCEu, 0xF0u},\r
{0xD0u, 0x10u},\r
- {0xD4u, 0x80u},\r
+ {0xD4u, 0x20u},\r
{0xD6u, 0xC0u},\r
{0xD8u, 0xC0u},\r
- {0x30u, 0x02u},\r
- {0x33u, 0x10u},\r
- {0x34u, 0x02u},\r
- {0x37u, 0x20u},\r
- {0x3Bu, 0x20u},\r
- {0x57u, 0x20u},\r
- {0x5Au, 0x80u},\r
- {0x5Eu, 0x10u},\r
- {0x66u, 0x80u},\r
- {0x82u, 0x30u},\r
- {0x84u, 0x02u},\r
- {0x8Au, 0x80u},\r
- {0x96u, 0x01u},\r
- {0x97u, 0x02u},\r
- {0x9Bu, 0x30u},\r
- {0x9Cu, 0x18u},\r
- {0x9Du, 0x02u},\r
- {0x9Eu, 0x0Cu},\r
- {0x9Fu, 0x08u},\r
- {0xA5u, 0x08u},\r
- {0xA6u, 0x20u},\r
- {0xA7u, 0x10u},\r
- {0xB6u, 0x01u},\r
+ {0xE2u, 0x60u},\r
+ {0xE6u, 0x10u},\r
+ {0x33u, 0x18u},\r
+ {0x35u, 0x04u},\r
+ {0x37u, 0x80u},\r
+ {0x39u, 0x80u},\r
+ {0x54u, 0x02u},\r
+ {0x57u, 0x10u},\r
+ {0x5Bu, 0x40u},\r
+ {0x63u, 0x80u},\r
+ {0x95u, 0x04u},\r
+ {0x9Bu, 0xD0u},\r
+ {0x9Cu, 0x20u},\r
+ {0x9Du, 0x08u},\r
+ {0x9Fu, 0x04u},\r
+ {0xA6u, 0x80u},\r
+ {0xA7u, 0x20u},\r
+ {0xA8u, 0x08u},\r
+ {0xAAu, 0x08u},\r
+ {0xABu, 0x50u},\r
+ {0xAEu, 0x20u},\r
+ {0xB7u, 0x10u},\r
{0xCCu, 0xF0u},\r
{0xCEu, 0x10u},\r
{0xD4u, 0xC0u},\r
- {0xD6u, 0xA0u},\r
- {0xE2u, 0x80u},\r
- {0xE6u, 0xC0u},\r
- {0x10u, 0x10u},\r
- {0x30u, 0x20u},\r
- {0x80u, 0x02u},\r
- {0x82u, 0x04u},\r
- {0x88u, 0x08u},\r
- {0x8Du, 0x80u},\r
- {0x8Fu, 0x20u},\r
- {0x96u, 0x81u},\r
- {0x97u, 0x22u},\r
- {0x9Cu, 0x18u},\r
- {0x9Eu, 0x0Cu},\r
- {0x9Fu, 0x08u},\r
- {0xA4u, 0x02u},\r
- {0xA5u, 0x08u},\r
- {0xA7u, 0x20u},\r
- {0xABu, 0x10u},\r
- {0xB1u, 0x02u},\r
+ {0xD6u, 0x20u},\r
+ {0xD8u, 0x40u},\r
+ {0xEEu, 0xE0u},\r
+ {0x12u, 0x80u},\r
+ {0x32u, 0x10u},\r
+ {0x82u, 0x10u},\r
+ {0x83u, 0x50u},\r
+ {0x85u, 0x08u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Cu, 0x20u},\r
+ {0x95u, 0x84u},\r
+ {0x9Du, 0x0Cu},\r
+ {0x9Fu, 0x04u},\r
+ {0xA6u, 0x80u},\r
+ {0xA7u, 0x78u},\r
+ {0xA8u, 0x22u},\r
{0xC4u, 0x10u},\r
{0xCCu, 0x10u},\r
- {0xE2u, 0xA0u},\r
- {0xEEu, 0x80u},\r
- {0x81u, 0x08u},\r
- {0x83u, 0x01u},\r
- {0x96u, 0x01u},\r
- {0x97u, 0x02u},\r
- {0x9Eu, 0x08u},\r
- {0x9Fu, 0x08u},\r
- {0xA1u, 0x80u},\r
- {0xA5u, 0x08u},\r
- {0xACu, 0x20u},\r
- {0xB3u, 0x10u},\r
- {0xB6u, 0x40u},\r
+ {0xE2u, 0x20u},\r
+ {0xE6u, 0xB0u},\r
+ {0xEAu, 0x20u},\r
+ {0xEEu, 0x20u},\r
+ {0x81u, 0x44u},\r
+ {0x95u, 0x84u},\r
+ {0x9Du, 0x04u},\r
+ {0xA0u, 0x20u},\r
+ {0xABu, 0x04u},\r
+ {0xAFu, 0x20u},\r
{0xE2u, 0x80u},\r
- {0xE6u, 0x20u},\r
- {0xEAu, 0x40u},\r
- {0x08u, 0x28u},\r
+ {0xE6u, 0x80u},\r
+ {0xEAu, 0x80u},\r
+ {0xEEu, 0x10u},\r
+ {0x08u, 0x04u},\r
+ {0x09u, 0x80u},\r
{0x0Fu, 0x20u},\r
- {0x13u, 0x01u},\r
- {0x17u, 0x08u},\r
- {0x53u, 0x21u},\r
- {0x55u, 0x08u},\r
- {0x5Cu, 0x40u},\r
- {0x83u, 0x01u},\r
- {0x8Bu, 0x10u},\r
+ {0x12u, 0x20u},\r
+ {0x17u, 0x01u},\r
+ {0x50u, 0x04u},\r
+ {0x57u, 0x20u},\r
+ {0x58u, 0x20u},\r
+ {0x5Fu, 0x40u},\r
+ {0x80u, 0x40u},\r
{0xC2u, 0x0Eu},\r
{0xC4u, 0x0Cu},\r
{0xD4u, 0x07u},\r
{0xD6u, 0x04u},\r
- {0xE2u, 0x04u},\r
- {0x01u, 0x82u},\r
- {0x06u, 0x08u},\r
+ {0x00u, 0x40u},\r
+ {0x02u, 0x10u},\r
+ {0x05u, 0x20u},\r
{0x07u, 0x20u},\r
- {0x08u, 0x80u},\r
- {0x0Bu, 0x20u},\r
- {0x0Eu, 0x01u},\r
- {0x0Fu, 0x80u},\r
+ {0x08u, 0x02u},\r
+ {0x09u, 0x20u},\r
+ {0x0Du, 0x01u},\r
+ {0x0Eu, 0x02u},\r
{0x83u, 0x10u},\r
- {0x84u, 0x20u},\r
- {0x85u, 0x01u},\r
+ {0x8Au, 0x10u},\r
+ {0x8Bu, 0x60u},\r
{0x94u, 0x40u},\r
- {0x97u, 0x20u},\r
- {0x98u, 0x28u},\r
- {0x9Bu, 0x08u},\r
+ {0x97u, 0x40u},\r
+ {0x9Bu, 0x01u},\r
+ {0xA2u, 0x20u},\r
{0xA3u, 0x10u},\r
- {0xA5u, 0x08u},\r
- {0xA7u, 0x60u},\r
- {0xABu, 0x41u},\r
- {0xC0u, 0x0Fu},\r
- {0xC2u, 0x0Fu},\r
- {0x82u, 0x40u},\r
- {0x83u, 0x20u},\r
- {0x8Au, 0x08u},\r
- {0x94u, 0x40u},\r
- {0x95u, 0x02u},\r
- {0x98u, 0x08u},\r
- {0x9Au, 0x08u},\r
- {0x9Bu, 0x28u},\r
{0xA7u, 0x20u},\r
- {0xA9u, 0x0Au},\r
- {0xB2u, 0x01u},\r
- {0xB4u, 0x80u},\r
+ {0xA8u, 0x04u},\r
+ {0xACu, 0x20u},\r
+ {0xB0u, 0x04u},\r
{0xB5u, 0x80u},\r
- {0xE2u, 0x04u},\r
+ {0xC0u, 0x0Fu},\r
+ {0xC2u, 0x0Fu},\r
+ {0xE0u, 0x05u},\r
+ {0xE6u, 0x04u},\r
{0xEAu, 0x08u},\r
- {0xEEu, 0x03u},\r
- {0x08u, 0x10u},\r
- {0x0Au, 0x40u},\r
- {0x0Du, 0x01u},\r
- {0x0Eu, 0x04u},\r
- {0x83u, 0x08u},\r
- {0x94u, 0x40u},\r
- {0x95u, 0x02u},\r
- {0x96u, 0x44u},\r
- {0x9Bu, 0x08u},\r
- {0x9Cu, 0x10u},\r
- {0xABu, 0x20u},\r
- {0xAEu, 0x04u},\r
- {0xB0u, 0x10u},\r
- {0xB4u, 0x08u},\r
+ {0xEEu, 0x01u},\r
+ {0x82u, 0x05u},\r
+ {0x84u, 0x02u},\r
+ {0x8Bu, 0x11u},\r
+ {0x91u, 0x02u},\r
+ {0x98u, 0x02u},\r
+ {0x99u, 0x20u},\r
+ {0x9Bu, 0x21u},\r
+ {0xA1u, 0x20u},\r
+ {0xA2u, 0x01u},\r
+ {0xAEu, 0x20u},\r
+ {0xE2u, 0x04u},\r
+ {0xE6u, 0x04u},\r
+ {0x0Bu, 0x21u},\r
+ {0x0Eu, 0x08u},\r
+ {0x0Fu, 0x20u},\r
+ {0x83u, 0x11u},\r
+ {0x85u, 0x01u},\r
+ {0x8Cu, 0x04u},\r
+ {0x91u, 0x02u},\r
+ {0x97u, 0x20u},\r
+ {0x99u, 0x20u},\r
+ {0xA6u, 0x04u},\r
+ {0xAFu, 0x20u},\r
+ {0xB5u, 0x20u},\r
{0xC2u, 0x0Fu},\r
- {0xEAu, 0x06u},\r
- {0x65u, 0x01u},\r
- {0x86u, 0x09u},\r
- {0x96u, 0x01u},\r
- {0x9Eu, 0x08u},\r
- {0x9Fu, 0x08u},\r
- {0xA1u, 0x80u},\r
+ {0xE6u, 0x02u},\r
+ {0xEEu, 0x02u},\r
+ {0x67u, 0x80u},\r
+ {0x87u, 0x40u},\r
+ {0x89u, 0x04u},\r
+ {0x95u, 0x04u},\r
+ {0xA0u, 0x20u},\r
{0xD8u, 0x80u},\r
{0xE2u, 0x10u},\r
- {0xE6u, 0x40u},\r
- {0x04u, 0x08u},\r
- {0x51u, 0x80u},\r
- {0x56u, 0x80u},\r
- {0x8Cu, 0x04u},\r
- {0x8Eu, 0x80u},\r
- {0x8Fu, 0x08u},\r
- {0x9Fu, 0x08u},\r
- {0xA1u, 0x80u},\r
- {0xA9u, 0x01u},\r
+ {0x06u, 0x40u},\r
+ {0x50u, 0x20u},\r
+ {0x57u, 0x80u},\r
+ {0x86u, 0x40u},\r
+ {0x8Fu, 0x80u},\r
+ {0xA0u, 0x20u},\r
{0xC0u, 0x20u},\r
{0xD4u, 0x60u},\r
- {0xEAu, 0x20u},\r
- {0x94u, 0x40u},\r
- {0x00u, 0x08u},\r
- {0x84u, 0x04u},\r
- {0xB4u, 0x40u},\r
+ {0xE0u, 0x10u},\r
+ {0x94u, 0x04u},\r
+ {0xB5u, 0x20u},\r
+ {0xEAu, 0x08u},\r
+ {0x00u, 0x04u},\r
+ {0x94u, 0x04u},\r
{0xC0u, 0x08u},\r
- {0xE8u, 0x02u},\r
- {0x10u, 0x01u},\r
- {0x11u, 0x01u},\r
- {0x1Au, 0x01u},\r
- {0x1Bu, 0x01u},\r
- {0x1Cu, 0x01u},\r
- {0x1Du, 0x01u},\r
+ {0x10u, 0x03u},\r
+ {0x1Au, 0x03u},\r
{0x00u, 0xFDu},\r
{0x01u, 0xBFu},\r
{0x02u, 0x2Au},\r
\r
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x01u, 0x01u, 0x02u, 0x01u};\r
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB07_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB07_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB07_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB07_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB07_ST\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST\r
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
.set SDCard_BSPIM_TxStsReg__2__POS, 2\r
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08\r
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB08_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB08_ST\r
\r
/* SD_SCK */\r
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB05_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB05_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL\r
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB05_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK\r
\r
/* SCSI_Out_Ctl */\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK\r
\r
/* SCSI_Out_DBx */\r
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
.set scsiTarget_StatusReg__0__POS, 0\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__2__POS, 2\r
.set scsiTarget_StatusReg__3__MASK, 0x08\r
.set scsiTarget_StatusReg__4__MASK, 0x10\r
.set scsiTarget_StatusReg__4__POS, 4\r
.set scsiTarget_StatusReg__MASK, 0x1F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB02_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB02_ST\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST\r
\r
/* Debug_Timer_Interrupt */\r
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST\r
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST\r
\r
/* SCSI_CTL_PHASE */\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST\r
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB04_MSK\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB04_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB09_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB09_ST\r
\r
/* Miscellaneous */\r
.set BCLK__BUS_CLK__HZ, 50000000\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
\r
/* SD_SCK */\r
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
\r
/* SCSI_Out_Ctl */\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
\r
/* SCSI_Out_DBx */\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
\r
/* Debug_Timer_Interrupt */\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
\r
/* SCSI_CTL_PHASE */\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST\r
\r
/* Miscellaneous */\r
BCLK__BUS_CLK__HZ EQU 50000000\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
\r
; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
\r
; SD_SCK\r
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
\r
; SCSI_Out_Ctl\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
\r
; SCSI_Out_DBx\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
\r
; Debug_Timer_Interrupt\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
\r
; SCSI_CTL_PHASE\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
\r
; SCSI_Glitch_Ctl\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
\r
; SCSI_Parity_Error\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST\r
\r
; Miscellaneous\r
BCLK__BUS_CLK__HZ EQU 50000000\r
<?xml version="1.0" encoding="utf-8"?>\r
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
- <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006464" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_MASK_REG" address="0x40006484" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006494" bitWidth="8" desc="" hidden="false">\r
- <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
- <value name="ENABLED" value="1" desc="Enable counter" />\r
- <value name="DISABLED" value="0" desc="Disable counter" />\r
- </field>\r
- <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">\r
- <value name="ENABLED" value="1" desc="Interrupt enabled" />\r
- <value name="DISABLED" value="0" desc="Interrupt disabled" />\r
- </field>\r
- <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">\r
- <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
- <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
- </field>\r
- <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">\r
- <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
- <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
- </field>\r
- <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">\r
- <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
- <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
- </field>\r
- <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">\r
- <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
- <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
- </field>\r
- </register>\r
- </block>\r
+ <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />\r
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />\r
</block>\r
- <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647E" bitWidth="8" desc="" hidden="false" />\r
+ </block>\r
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
+ <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />\r
+ </block>\r
+ <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Filtered_STATUS_REG" address="0x40006461" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Filtered_MASK_REG" address="0x40006481" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006491" bitWidth="8" desc="" hidden="false">\r
+ <register name="SCSI_Filtered_STATUS_REG" address="0x40006462" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Filtered_MASK_REG" address="0x40006482" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006492" bitWidth="8" desc="" hidden="false">\r
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
</field>\r
</register>\r
</block>\r
- <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" hidden="false" />\r
+ <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006469" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x40006489" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006499" bitWidth="8" desc="" hidden="false">\r
+ <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
+ <value name="ENABLED" value="1" desc="Enable counter" />\r
+ <value name="DISABLED" value="0" desc="Disable counter" />\r
+ </field>\r
+ <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">\r
+ <value name="ENABLED" value="1" desc="Interrupt enabled" />\r
+ <value name="DISABLED" value="0" desc="Interrupt disabled" />\r
+ </field>\r
+ <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">\r
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
+ </field>\r
+ <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">\r
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
+ </field>\r
+ <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">\r
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
+ </field>\r
+ <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">\r
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
+ </field>\r
+ </register>\r
</block>\r
- <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true" hidden="false">\r
<block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" hidden="false" />\r
</block>\r
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" hidden="false" />\r
- </block>\r
- <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006575" bitWidth="8" desc="" hidden="false" />\r
- </block>\r
- <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
</block>\r
- <block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" hidden="false" />\r
+ </block>\r
+ <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
</blockRegMap>
\ No newline at end of file
<addressUnitBits>8</addressUnitBits>\r
<width>32</width>\r
<peripherals>\r
- <peripheral>\r
- <name>SCSI_Parity_Error</name>\r
- <description>No description available</description>\r
- <baseAddress>0x40006464</baseAddress>\r
- <addressBlock>\r
- <offset>0</offset>\r
- <size>0x0</size>\r
- <usage>registers</usage>\r
- </addressBlock>\r
- <registers>\r
- <register>\r
- <name>SCSI_Parity_Error_STATUS_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>SCSI_Parity_Error_MASK_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x20</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x30</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- <fields>\r
- <field>\r
- <name>FIFO0</name>\r
- <description>FIFO0 clear</description>\r
- <lsb>5</lsb>\r
- <msb>5</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>Enable counter</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>Disable counter</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>INTRENBL</name>\r
- <description>Enables or disables the Interrupt</description>\r
- <lsb>4</lsb>\r
- <msb>4</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>Interrupt enabled</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>Interrupt disabled</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>FIFO1LEVEL</name>\r
- <description>FIFO level</description>\r
- <lsb>3</lsb>\r
- <msb>3</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>FIFO0LEVEL</name>\r
- <description>FIFO level</description>\r
- <lsb>2</lsb>\r
- <msb>2</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>FIFO1CLEAR</name>\r
- <description>FIFO clear</description>\r
- <lsb>1</lsb>\r
- <msb>1</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>Clear FIFO state</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>Normal FIFO operation</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>FIFO0CLEAR</name>\r
- <description>FIFO clear</description>\r
- <lsb>0</lsb>\r
- <msb>0</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>ENABLED</name>\r
- <description>Clear FIFO state</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>DISABLED</name>\r
- <description>Normal FIFO operation</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- </fields>\r
- </register>\r
- </registers>\r
- </peripheral>\r
<peripheral>\r
<name>Debug_Timer</name>\r
<description>No description available</description>\r
</register>\r
</registers>\r
</peripheral>\r
+ <peripheral>\r
+ <name>SCSI_Out_Ctl</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x4000647E</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x0</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_Out_Ctl_CONTROL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
+ <peripheral>\r
+ <name>SCSI_Glitch_Ctl</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x40006474</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x0</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_Glitch_Ctl_CONTROL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
<peripheral>\r
<name>SCSI_Filtered</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006461</baseAddress>\r
+ <baseAddress>0x40006462</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
</registers>\r
</peripheral>\r
<peripheral>\r
- <name>SCSI_Glitch_Ctl</name>\r
+ <name>SCSI_Parity_Error</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000647A</baseAddress>\r
+ <baseAddress>0x40006469</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
</addressBlock>\r
<registers>\r
<register>\r
- <name>SCSI_Glitch_Ctl_CONTROL_REG</name>\r
+ <name>SCSI_Parity_Error_STATUS_REG</name>\r
<description>No description available</description>\r
<addressOffset>0x0</addressOffset>\r
<size>8</size>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
+ <register>\r
+ <name>SCSI_Parity_Error_MASK_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x20</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x30</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>FIFO0</name>\r
+ <description>FIFO0 clear</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Enable counter</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Disable counter</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>INTRENBL</name>\r
+ <description>Enables or disables the Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Interrupt enabled</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Interrupt disabled</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO1LEVEL</name>\r
+ <description>FIFO level</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO0LEVEL</name>\r
+ <description>FIFO level</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO1CLEAR</name>\r
+ <description>FIFO clear</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Clear FIFO state</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Normal FIFO operation</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO0CLEAR</name>\r
+ <description>FIFO clear</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Clear FIFO state</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Normal FIFO operation</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ </fields>\r
+ </register>\r
</registers>\r
</peripheral>\r
<peripheral>\r
<name>SCSI_CTL_PHASE</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000647B</baseAddress>\r
+ <baseAddress>0x40006475</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
</register>\r
</registers>\r
</peripheral>\r
- <peripheral>\r
- <name>SCSI_Out_Ctl</name>\r
- <description>No description available</description>\r
- <baseAddress>0x40006475</baseAddress>\r
- <addressBlock>\r
- <offset>0</offset>\r
- <size>0x0</size>\r
- <usage>registers</usage>\r
- </addressBlock>\r
- <registers>\r
- <register>\r
- <name>SCSI_Out_Ctl_CONTROL_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- </registers>\r
- </peripheral>\r
<peripheral>\r
<name>SCSI_Out_Bits</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006575</baseAddress>\r
+ <baseAddress>0x4000647A</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
#define EXTLED__SLW CYREG_PRT0_SLW\r
\r
/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1\r
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0\r
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__2__POS 2\r
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB04_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB04_ST\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
\r
/* SD_SCK */\r
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK\r
\r
/* SCSI_Out_Ctl */\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG\r
#define scsiTarget_StatusReg__0__POS 0\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__2__POS 2\r
#define scsiTarget_StatusReg__3__MASK 0x08u\r
#define scsiTarget_StatusReg__4__MASK 0x10u\r
#define scsiTarget_StatusReg__4__POS 4\r
#define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB04_MSK\r
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB04_ST\r
\r
/* Debug_Timer_Interrupt */\r
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST\r
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK\r
-#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST\r
\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
/* SCSI_Parity_Error */\r
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST\r
\r
/* Miscellaneous */\r
#define BCLK__BUS_CLK__HZ 50000000U\r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 41u\r
+#define CY_CFG_BASE_ADDR_COUNT 42u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
0x4000520Eu, /* Base address: 0x40005200 Count: 14 */\r
0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
- 0x40010042u, /* Base address: 0x40010000 Count: 66 */\r
- 0x40010143u, /* Base address: 0x40010100 Count: 67 */\r
- 0x4001023Fu, /* Base address: 0x40010200 Count: 63 */\r
- 0x40010351u, /* Base address: 0x40010300 Count: 81 */\r
- 0x40010448u, /* Base address: 0x40010400 Count: 72 */\r
- 0x40010550u, /* Base address: 0x40010500 Count: 80 */\r
- 0x40010653u, /* Base address: 0x40010600 Count: 83 */\r
- 0x40010751u, /* Base address: 0x40010700 Count: 81 */\r
- 0x40010911u, /* Base address: 0x40010900 Count: 17 */\r
- 0x40010A4Du, /* Base address: 0x40010A00 Count: 77 */\r
- 0x40010B50u, /* Base address: 0x40010B00 Count: 80 */\r
- 0x40010C4Cu, /* Base address: 0x40010C00 Count: 76 */\r
- 0x40010D57u, /* Base address: 0x40010D00 Count: 87 */\r
- 0x40010E50u, /* Base address: 0x40010E00 Count: 80 */\r
- 0x40010F3Du, /* Base address: 0x40010F00 Count: 61 */\r
- 0x40011420u, /* Base address: 0x40011400 Count: 32 */\r
- 0x40011545u, /* Base address: 0x40011500 Count: 69 */\r
- 0x40011652u, /* Base address: 0x40011600 Count: 82 */\r
- 0x40011748u, /* Base address: 0x40011700 Count: 72 */\r
+ 0x4001003Fu, /* Base address: 0x40010000 Count: 63 */\r
+ 0x4001013Fu, /* Base address: 0x40010100 Count: 63 */\r
+ 0x40010247u, /* Base address: 0x40010200 Count: 71 */\r
+ 0x40010358u, /* Base address: 0x40010300 Count: 88 */\r
+ 0x40010451u, /* Base address: 0x40010400 Count: 81 */\r
+ 0x40010555u, /* Base address: 0x40010500 Count: 85 */\r
+ 0x4001064Cu, /* Base address: 0x40010600 Count: 76 */\r
+ 0x4001074Cu, /* Base address: 0x40010700 Count: 76 */\r
+ 0x4001084Bu, /* Base address: 0x40010800 Count: 75 */\r
+ 0x4001094Bu, /* Base address: 0x40010900 Count: 75 */\r
+ 0x40010A50u, /* Base address: 0x40010A00 Count: 80 */\r
+ 0x40010B56u, /* Base address: 0x40010B00 Count: 86 */\r
+ 0x40010C47u, /* Base address: 0x40010C00 Count: 71 */\r
+ 0x40010D51u, /* Base address: 0x40010D00 Count: 81 */\r
+ 0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */\r
+ 0x40010F45u, /* Base address: 0x40010F00 Count: 69 */\r
+ 0x4001140Eu, /* Base address: 0x40011400 Count: 14 */\r
+ 0x40011547u, /* Base address: 0x40011500 Count: 71 */\r
+ 0x4001164Eu, /* Base address: 0x40011600 Count: 78 */\r
+ 0x40011743u, /* Base address: 0x40011700 Count: 67 */\r
0x40011804u, /* Base address: 0x40011800 Count: 4 */\r
- 0x40011908u, /* Base address: 0x40011900 Count: 8 */\r
- 0x40011B04u, /* Base address: 0x40011B00 Count: 4 */\r
- 0x4001401Au, /* Base address: 0x40014000 Count: 26 */\r
+ 0x40011910u, /* Base address: 0x40011900 Count: 16 */\r
+ 0x40011B09u, /* Base address: 0x40011B00 Count: 9 */\r
+ 0x40014018u, /* Base address: 0x40014000 Count: 24 */\r
0x40014117u, /* Base address: 0x40014100 Count: 23 */\r
- 0x4001420Eu, /* Base address: 0x40014200 Count: 14 */\r
- 0x40014307u, /* Base address: 0x40014300 Count: 7 */\r
+ 0x40014210u, /* Base address: 0x40014200 Count: 16 */\r
+ 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */\r
0x4001440Eu, /* Base address: 0x40014400 Count: 14 */\r
- 0x4001451Bu, /* Base address: 0x40014500 Count: 27 */\r
+ 0x40014519u, /* Base address: 0x40014500 Count: 25 */\r
0x40014612u, /* Base address: 0x40014600 Count: 18 */\r
- 0x4001470Eu, /* Base address: 0x40014700 Count: 14 */\r
- 0x40014807u, /* Base address: 0x40014800 Count: 7 */\r
- 0x40014909u, /* Base address: 0x40014900 Count: 9 */\r
- 0x40014C05u, /* Base address: 0x40014C00 Count: 5 */\r
- 0x40014D0Eu, /* Base address: 0x40014D00 Count: 14 */\r
- 0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
+ 0x40014712u, /* Base address: 0x40014700 Count: 18 */\r
+ 0x40014805u, /* Base address: 0x40014800 Count: 5 */\r
+ 0x4001490Du, /* Base address: 0x40014900 Count: 13 */\r
+ 0x40014C04u, /* Base address: 0x40014C00 Count: 4 */\r
+ 0x40014D0Bu, /* Base address: 0x40014D00 Count: 11 */\r
+ 0x40015004u, /* Base address: 0x40015000 Count: 4 */\r
0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
{0x0Au, 0x36u},\r
- {0x00u, 0x04u},\r
- {0x01u, 0x41u},\r
+ {0x00u, 0x48u},\r
+ {0x01u, 0x04u},\r
{0x04u, 0x31u},\r
- {0x10u, 0x0Cu},\r
+ {0x10u, 0xC8u},\r
{0x11u, 0x44u},\r
+ {0x18u, 0x08u},\r
{0x19u, 0x04u},\r
{0x1Cu, 0x30u},\r
{0x20u, 0x10u},\r
{0x24u, 0x44u},\r
- {0x28u, 0x01u},\r
- {0x29u, 0x03u},\r
+ {0x29u, 0x01u},\r
{0x30u, 0x20u},\r
{0x31u, 0x30u},\r
{0x7Cu, 0x40u},\r
{0x20u, 0x01u},\r
- {0x86u, 0x0Fu},\r
- {0x01u, 0x01u},\r
- {0x03u, 0x02u},\r
- {0x06u, 0x08u},\r
- {0x09u, 0x24u},\r
+ {0x84u, 0x0Fu},\r
+ {0x03u, 0x70u},\r
+ {0x06u, 0xFFu},\r
+ {0x07u, 0x80u},\r
+ {0x08u, 0xFFu},\r
{0x0Bu, 0x08u},\r
- {0x0Cu, 0x99u},\r
- {0x0Eu, 0x22u},\r
- {0x0Fu, 0x1Du},\r
- {0x12u, 0x07u},\r
- {0x13u, 0x20u},\r
- {0x14u, 0xAAu},\r
- {0x15u, 0x10u},\r
- {0x16u, 0x55u},\r
- {0x17u, 0x20u},\r
- {0x1Au, 0x70u},\r
- {0x1Fu, 0x02u},\r
- {0x26u, 0x80u},\r
- {0x28u, 0x44u},\r
- {0x29u, 0x28u},\r
- {0x2Au, 0x88u},\r
- {0x2Bu, 0x14u},\r
- {0x30u, 0x0Fu},\r
- {0x31u, 0x3Cu},\r
- {0x34u, 0xF0u},\r
- {0x35u, 0x03u},\r
- {0x3Fu, 0x10u},\r
- {0x40u, 0x63u},\r
- {0x41u, 0x05u},\r
+ {0x0Eu, 0xFFu},\r
+ {0x10u, 0xFFu},\r
+ {0x17u, 0x07u},\r
+ {0x1Au, 0xFFu},\r
+ {0x1Cu, 0x69u},\r
+ {0x1Eu, 0x96u},\r
+ {0x20u, 0x55u},\r
+ {0x22u, 0xAAu},\r
+ {0x25u, 0x44u},\r
+ {0x27u, 0x88u},\r
+ {0x28u, 0x33u},\r
+ {0x29u, 0xAAu},\r
+ {0x2Au, 0xCCu},\r
+ {0x2Bu, 0x55u},\r
+ {0x2Cu, 0x0Fu},\r
+ {0x2Du, 0x99u},\r
+ {0x2Eu, 0xF0u},\r
+ {0x2Fu, 0x22u},\r
+ {0x30u, 0xFFu},\r
+ {0x31u, 0xF0u},\r
+ {0x33u, 0x0Fu},\r
+ {0x3Au, 0x02u},\r
+ {0x40u, 0x36u},\r
+ {0x41u, 0x04u},\r
{0x42u, 0x10u},\r
- {0x45u, 0xC2u},\r
- {0x46u, 0xEDu},\r
+ {0x45u, 0x2Cu},\r
+ {0x46u, 0xDEu},\r
{0x47u, 0x0Fu},\r
{0x48u, 0x1Fu},\r
{0x49u, 0xFFu},\r
{0x68u, 0x40u},\r
{0x69u, 0x40u},\r
{0x6Eu, 0x08u},\r
- {0x90u, 0x02u},\r
- {0x92u, 0x01u},\r
- {0x94u, 0x01u},\r
- {0x96u, 0x02u},\r
- {0x99u, 0x01u},\r
- {0xA0u, 0x02u},\r
- {0xA2u, 0x01u},\r
- {0xB2u, 0x03u},\r
- {0xB3u, 0x01u},\r
- {0xBAu, 0x08u},\r
+ {0x8Du, 0x01u},\r
+ {0x8Fu, 0x02u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA7u, 0x02u},\r
+ {0xAEu, 0x01u},\r
+ {0xB2u, 0x01u},\r
+ {0xB7u, 0x03u},\r
+ {0xBFu, 0x40u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x99u},\r
{0xDFu, 0x01u},\r
- {0x02u, 0x02u},\r
- {0x03u, 0x10u},\r
- {0x09u, 0x04u},\r
- {0x0Au, 0x44u},\r
- {0x0Cu, 0x01u},\r
- {0x0Eu, 0x20u},\r
+ {0x01u, 0x28u},\r
+ {0x03u, 0x02u},\r
+ {0x04u, 0x80u},\r
+ {0x06u, 0x01u},\r
+ {0x08u, 0x02u},\r
+ {0x09u, 0x50u},\r
{0x10u, 0x08u},\r
- {0x13u, 0x08u},\r
- {0x17u, 0x01u},\r
- {0x19u, 0x22u},\r
- {0x1Au, 0x44u},\r
- {0x1Eu, 0x20u},\r
+ {0x12u, 0x41u},\r
+ {0x15u, 0x80u},\r
+ {0x18u, 0x80u},\r
{0x1Fu, 0x08u},\r
- {0x20u, 0x40u},\r
- {0x21u, 0x20u},\r
- {0x27u, 0x20u},\r
- {0x2Au, 0x20u},\r
- {0x30u, 0x08u},\r
- {0x32u, 0x01u},\r
- {0x33u, 0x40u},\r
- {0x36u, 0x20u},\r
- {0x38u, 0x42u},\r
- {0x3Au, 0x50u},\r
- {0x41u, 0x40u},\r
- {0x42u, 0x20u},\r
- {0x44u, 0x10u},\r
- {0x45u, 0x08u},\r
- {0x48u, 0x08u},\r
- {0x49u, 0x04u},\r
- {0x4Au, 0xC2u},\r
- {0x4Bu, 0x04u},\r
- {0x51u, 0x08u},\r
- {0x53u, 0x50u},\r
- {0x58u, 0x04u},\r
+ {0x21u, 0x01u},\r
+ {0x22u, 0x04u},\r
+ {0x23u, 0x80u},\r
+ {0x26u, 0x40u},\r
+ {0x29u, 0x20u},\r
+ {0x2Bu, 0x12u},\r
+ {0x2Cu, 0x20u},\r
+ {0x30u, 0x04u},\r
+ {0x32u, 0x04u},\r
+ {0x37u, 0x80u},\r
+ {0x39u, 0x16u},\r
+ {0x3Bu, 0x02u},\r
+ {0x3Du, 0x40u},\r
+ {0x40u, 0x10u},\r
+ {0x43u, 0x82u},\r
+ {0x48u, 0x10u},\r
+ {0x49u, 0x26u},\r
+ {0x50u, 0x10u},\r
+ {0x52u, 0x18u},\r
+ {0x53u, 0x60u},\r
+ {0x58u, 0x18u},\r
{0x59u, 0x01u},\r
- {0x5Au, 0x10u},\r
- {0x5Bu, 0x80u},\r
- {0x5Du, 0x03u},\r
- {0x60u, 0x0Au},\r
- {0x61u, 0x02u},\r
- {0x63u, 0x20u},\r
- {0x69u, 0x40u},\r
- {0x6Au, 0x02u},\r
- {0x6Bu, 0x18u},\r
- {0x6Cu, 0x01u},\r
- {0x70u, 0x20u},\r
- {0x72u, 0x80u},\r
- {0x73u, 0x12u},\r
- {0x80u, 0x08u},\r
+ {0x5Bu, 0x40u},\r
+ {0x60u, 0x40u},\r
+ {0x61u, 0x08u},\r
+ {0x62u, 0xA0u},\r
+ {0x69u, 0x14u},\r
+ {0x6Au, 0x82u},\r
+ {0x70u, 0x01u},\r
+ {0x72u, 0x20u},\r
+ {0x73u, 0x06u},\r
+ {0x80u, 0x40u},\r
{0x81u, 0x01u},\r
- {0x84u, 0x02u},\r
- {0x86u, 0x12u},\r
- {0x8Au, 0xC0u},\r
- {0x8Fu, 0x20u},\r
- {0xC0u, 0x05u},\r
- {0xC2u, 0x3Eu},\r
- {0xC4u, 0x16u},\r
- {0xCAu, 0x04u},\r
- {0xCCu, 0x2Bu},\r
- {0xCEu, 0x0Du},\r
- {0xD0u, 0x0Au},\r
- {0xD2u, 0x0Cu},\r
+ {0x82u, 0x20u},\r
+ {0x84u, 0x18u},\r
+ {0x85u, 0x40u},\r
+ {0x88u, 0x08u},\r
+ {0x8Bu, 0x02u},\r
+ {0x8Cu, 0x11u},\r
+ {0xC0u, 0x07u},\r
+ {0xC2u, 0x0Bu},\r
+ {0xC4u, 0x8Bu},\r
+ {0xCAu, 0x4Eu},\r
+ {0xCCu, 0x12u},\r
+ {0xCEu, 0x17u},\r
+ {0xD0u, 0x0Bu},\r
+ {0xD2u, 0x04u},\r
{0xD6u, 0x0Fu},\r
{0xD8u, 0x0Fu},\r
- {0xE0u, 0x50u},\r
- {0xE2u, 0x2Eu},\r
- {0xE6u, 0x16u},\r
- {0x00u, 0x0Fu},\r
- {0x01u, 0x03u},\r
- {0x02u, 0xF0u},\r
- {0x03u, 0x0Cu},\r
- {0x04u, 0xFFu},\r
- {0x05u, 0xFFu},\r
- {0x08u, 0x05u},\r
- {0x09u, 0x06u},\r
- {0x0Au, 0x0Au},\r
- {0x0Bu, 0x09u},\r
- {0x0Cu, 0x90u},\r
- {0x0Eu, 0x60u},\r
- {0x10u, 0xFFu},\r
- {0x11u, 0x0Fu},\r
- {0x13u, 0xF0u},\r
- {0x15u, 0x50u},\r
- {0x17u, 0xA0u},\r
- {0x18u, 0x09u},\r
- {0x19u, 0x05u},\r
- {0x1Au, 0x06u},\r
- {0x1Bu, 0x0Au},\r
- {0x1Eu, 0xFFu},\r
- {0x1Fu, 0xFFu},\r
+ {0xE2u, 0x06u},\r
+ {0xE4u, 0x80u},\r
+ {0xE6u, 0x4Fu},\r
+ {0x04u, 0x09u},\r
+ {0x05u, 0x01u},\r
+ {0x06u, 0x06u},\r
+ {0x08u, 0x50u},\r
+ {0x09u, 0x0Fu},\r
+ {0x0Au, 0xA0u},\r
+ {0x0Bu, 0x10u},\r
+ {0x0Cu, 0xFFu},\r
+ {0x10u, 0x90u},\r
+ {0x12u, 0x60u},\r
+ {0x13u, 0x02u},\r
+ {0x14u, 0x05u},\r
+ {0x16u, 0x0Au},\r
+ {0x17u, 0x07u},\r
+ {0x18u, 0x30u},\r
+ {0x19u, 0x07u},\r
+ {0x1Au, 0xC0u},\r
+ {0x1Bu, 0x18u},\r
{0x20u, 0x03u},\r
- {0x21u, 0x60u},\r
{0x22u, 0x0Cu},\r
- {0x23u, 0x90u},\r
- {0x24u, 0x50u},\r
- {0x25u, 0x30u},\r
- {0x26u, 0xA0u},\r
- {0x27u, 0xC0u},\r
- {0x28u, 0x30u},\r
- {0x2Au, 0xC0u},\r
- {0x2Fu, 0xFFu},\r
- {0x30u, 0xFFu},\r
- {0x31u, 0xFFu},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x01u},\r
+ {0x24u, 0xFFu},\r
+ {0x25u, 0x05u},\r
+ {0x29u, 0x0Au},\r
+ {0x2Au, 0xFFu},\r
+ {0x2Bu, 0x15u},\r
+ {0x2Cu, 0x0Fu},\r
+ {0x2Du, 0x08u},\r
+ {0x2Eu, 0xF0u},\r
+ {0x2Fu, 0x16u},\r
+ {0x33u, 0x1Fu},\r
+ {0x34u, 0xFFu},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Eu, 0x10u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x82u, 0x20u},\r
- {0x86u, 0x07u},\r
- {0x88u, 0x07u},\r
- {0x8Au, 0x18u},\r
- {0x8Cu, 0x28u},\r
- {0x8Eu, 0x16u},\r
- {0x90u, 0x05u},\r
- {0x94u, 0x2Au},\r
- {0x96u, 0x15u},\r
- {0x9Au, 0x02u},\r
- {0x9Cu, 0x01u},\r
- {0xA8u, 0x2Fu},\r
- {0xAAu, 0x10u},\r
+ {0x82u, 0x04u},\r
+ {0x84u, 0x08u},\r
+ {0x88u, 0x34u},\r
+ {0x8Au, 0x09u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Eu, 0x20u},\r
+ {0x90u, 0x02u},\r
+ {0x96u, 0x1Fu},\r
+ {0x97u, 0x70u},\r
+ {0x98u, 0x29u},\r
+ {0x9Au, 0x12u},\r
+ {0x9Bu, 0x07u},\r
+ {0x9Fu, 0x80u},\r
+ {0xA2u, 0x01u},\r
+ {0xA5u, 0x44u},\r
+ {0xA7u, 0x88u},\r
+ {0xA8u, 0x21u},\r
+ {0xA9u, 0xAAu},\r
+ {0xAAu, 0x06u},\r
+ {0xABu, 0x55u},\r
+ {0xADu, 0x99u},\r
+ {0xAFu, 0x22u},\r
{0xB0u, 0x20u},\r
{0xB2u, 0x1Fu},\r
- {0xBAu, 0x08u},\r
+ {0xB3u, 0xF0u},\r
+ {0xB5u, 0x0Fu},\r
{0xBEu, 0x01u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x01u},\r
+ {0xDCu, 0x11u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x02u, 0xA2u},\r
- {0x03u, 0x08u},\r
- {0x04u, 0x06u},\r
- {0x05u, 0x21u},\r
- {0x06u, 0x02u},\r
- {0x07u, 0x01u},\r
- {0x08u, 0x01u},\r
- {0x09u, 0x04u},\r
- {0x0Bu, 0x87u},\r
- {0x0Du, 0x10u},\r
- {0x0Eu, 0x80u},\r
- {0x0Fu, 0x01u},\r
- {0x10u, 0x08u},\r
- {0x15u, 0x01u},\r
- {0x17u, 0x14u},\r
- {0x1Bu, 0x09u},\r
- {0x1Du, 0x02u},\r
- {0x24u, 0x80u},\r
- {0x2Eu, 0x06u},\r
- {0x2Fu, 0x01u},\r
- {0x35u, 0x21u},\r
- {0x36u, 0x40u},\r
- {0x37u, 0x04u},\r
- {0x3Cu, 0x04u},\r
- {0x3Du, 0x11u},\r
- {0x58u, 0x99u},\r
- {0x5Cu, 0x42u},\r
- {0x5Du, 0x04u},\r
- {0x5Eu, 0x20u},\r
- {0x63u, 0x02u},\r
- {0x65u, 0x40u},\r
- {0x6Du, 0x02u},\r
- {0x6Eu, 0x04u},\r
- {0x6Fu, 0x55u},\r
- {0x75u, 0x90u},\r
- {0x76u, 0xB0u},\r
- {0x80u, 0x01u},\r
- {0x82u, 0x80u},\r
- {0x86u, 0x10u},\r
- {0x88u, 0x04u},\r
- {0x8Cu, 0x08u},\r
- {0x8Du, 0x04u},\r
- {0x8Eu, 0x90u},\r
- {0x90u, 0x02u},\r
- {0x91u, 0x45u},\r
- {0x93u, 0xB4u},\r
- {0x95u, 0x80u},\r
- {0x96u, 0x10u},\r
- {0x98u, 0x10u},\r
- {0x99u, 0x24u},\r
- {0x9Au, 0x40u},\r
- {0x9Bu, 0x02u},\r
- {0x9Cu, 0x04u},\r
- {0x9Fu, 0xC0u},\r
- {0xA0u, 0x20u},\r
- {0xA1u, 0x04u},\r
- {0xA2u, 0x82u},\r
- {0xA4u, 0x08u},\r
- {0xA6u, 0x20u},\r
- {0xA9u, 0x06u},\r
- {0xAAu, 0x20u},\r
- {0xABu, 0x10u},\r
- {0xAFu, 0x41u},\r
- {0xB0u, 0x01u},\r
- {0xB1u, 0x24u},\r
- {0xB3u, 0x08u},\r
- {0xC0u, 0xFFu},\r
- {0xC2u, 0xDFu},\r
- {0xC4u, 0x72u},\r
- {0xCAu, 0xD0u},\r
- {0xCCu, 0xF0u},\r
- {0xCEu, 0xE0u},\r
- {0xD6u, 0xFFu},\r
- {0xD8u, 0x18u},\r
- {0xE0u, 0x01u},\r
- {0xE2u, 0x0Au},\r
- {0xE4u, 0x04u},\r
- {0xE6u, 0x0Au},\r
+ {0x01u, 0xA2u},\r
+ {0x02u, 0x10u},\r
+ {0x04u, 0x40u},\r
+ {0x07u, 0x24u},\r
+ {0x08u, 0x02u},\r
+ {0x09u, 0x10u},\r
+ {0x0Au, 0x20u},\r
+ {0x0Cu, 0x24u},\r
+ {0x0Eu, 0x40u},\r
+ {0x13u, 0x12u},\r
+ {0x15u, 0x42u},\r
+ {0x16u, 0x08u},\r
+ {0x17u, 0x08u},\r
+ {0x18u, 0x10u},\r
+ {0x1Bu, 0x05u},\r
+ {0x1Cu, 0x04u},\r
+ {0x20u, 0x20u},\r
+ {0x21u, 0x28u},\r
+ {0x23u, 0x20u},\r
+ {0x27u, 0x10u},\r
+ {0x29u, 0x20u},\r
+ {0x2Bu, 0x12u},\r
+ {0x2Du, 0x20u},\r
+ {0x2Fu, 0x22u},\r
+ {0x31u, 0x28u},\r
+ {0x32u, 0x40u},\r
+ {0x35u, 0x0Au},\r
+ {0x37u, 0x10u},\r
+ {0x3Au, 0x20u},\r
+ {0x3Cu, 0x10u},\r
+ {0x3Du, 0x20u},\r
+ {0x3Eu, 0x08u},\r
+ {0x3Fu, 0x20u},\r
+ {0x49u, 0x10u},\r
+ {0x4Au, 0x08u},\r
+ {0x58u, 0x40u},\r
+ {0x62u, 0x40u},\r
+ {0x68u, 0x24u},\r
+ {0x69u, 0x01u},\r
+ {0x6Au, 0x44u},\r
+ {0x6Bu, 0x05u},\r
+ {0x70u, 0x18u},\r
+ {0x71u, 0x80u},\r
+ {0x72u, 0x80u},\r
+ {0x81u, 0x08u},\r
+ {0x82u, 0x10u},\r
+ {0x89u, 0x81u},\r
+ {0x8Fu, 0x10u},\r
+ {0x90u, 0x80u},\r
+ {0x91u, 0x02u},\r
+ {0x92u, 0x80u},\r
+ {0x93u, 0x86u},\r
+ {0x94u, 0x10u},\r
+ {0x95u, 0xC0u},\r
+ {0x98u, 0x04u},\r
+ {0x99u, 0xA6u},\r
+ {0x9Au, 0x30u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Du, 0x08u},\r
+ {0x9Eu, 0x40u},\r
+ {0x9Fu, 0x40u},\r
+ {0xA2u, 0x08u},\r
+ {0xA3u, 0x28u},\r
+ {0xA4u, 0x20u},\r
+ {0xA5u, 0x10u},\r
+ {0xA6u, 0x80u},\r
+ {0xA7u, 0x92u},\r
+ {0xA9u, 0x20u},\r
+ {0xACu, 0x10u},\r
+ {0xADu, 0x80u},\r
+ {0xAEu, 0x40u},\r
+ {0xB2u, 0x01u},\r
+ {0xB4u, 0x10u},\r
+ {0xB5u, 0x08u},\r
+ {0xC0u, 0xEFu},\r
+ {0xC2u, 0x7Eu},\r
+ {0xC4u, 0xFAu},\r
+ {0xCAu, 0x7Eu},\r
+ {0xCCu, 0xEEu},\r
+ {0xCEu, 0x64u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x08u},\r
+ {0xE2u, 0x08u},\r
+ {0xE6u, 0x64u},\r
{0xE8u, 0x08u},\r
- {0xEAu, 0x07u},\r
+ {0xEAu, 0x04u},\r
+ {0xECu, 0x02u},\r
{0xEEu, 0x01u},\r
- {0x03u, 0x70u},\r
- {0x04u, 0x05u},\r
- {0x06u, 0x0Au},\r
- {0x0Bu, 0x80u},\r
- {0x0Cu, 0x10u},\r
- {0x0Eu, 0x2Fu},\r
- {0x0Fu, 0x08u},\r
- {0x10u, 0x40u},\r
- {0x11u, 0x99u},\r
- {0x12u, 0x1Fu},\r
- {0x13u, 0x22u},\r
- {0x17u, 0x07u},\r
- {0x19u, 0xAAu},\r
- {0x1Au, 0x70u},\r
- {0x1Bu, 0x55u},\r
- {0x1Cu, 0x06u},\r
- {0x1Eu, 0x09u},\r
- {0x20u, 0x0Fu},\r
- {0x24u, 0x20u},\r
- {0x26u, 0x4Fu},\r
- {0x28u, 0x03u},\r
- {0x2Au, 0x0Cu},\r
- {0x2Du, 0x44u},\r
- {0x2Fu, 0x88u},\r
- {0x31u, 0xF0u},\r
- {0x33u, 0x0Fu},\r
- {0x34u, 0x7Fu},\r
- {0x54u, 0x09u},\r
- {0x56u, 0x04u},\r
+ {0x00u, 0xFFu},\r
+ {0x04u, 0x50u},\r
+ {0x05u, 0x05u},\r
+ {0x06u, 0xA0u},\r
+ {0x07u, 0x0Au},\r
+ {0x08u, 0x06u},\r
+ {0x09u, 0x0Fu},\r
+ {0x0Au, 0x09u},\r
+ {0x0Cu, 0x0Fu},\r
+ {0x0Du, 0x03u},\r
+ {0x0Eu, 0xF0u},\r
+ {0x0Fu, 0x0Cu},\r
+ {0x13u, 0x70u},\r
+ {0x14u, 0x05u},\r
+ {0x16u, 0x0Au},\r
+ {0x18u, 0x30u},\r
+ {0x1Au, 0xC0u},\r
+ {0x1Cu, 0x03u},\r
+ {0x1Du, 0x10u},\r
+ {0x1Eu, 0x0Cu},\r
+ {0x1Fu, 0x2Fu},\r
+ {0x20u, 0x60u},\r
+ {0x22u, 0x90u},\r
+ {0x25u, 0x40u},\r
+ {0x26u, 0xFFu},\r
+ {0x27u, 0x1Fu},\r
+ {0x29u, 0x20u},\r
+ {0x2Au, 0xFFu},\r
+ {0x2Bu, 0x4Fu},\r
+ {0x2Du, 0x06u},\r
+ {0x2Fu, 0x09u},\r
+ {0x30u, 0xFFu},\r
+ {0x31u, 0x7Fu},\r
+ {0x3Eu, 0x01u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
+ {0x5Cu, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x02u},\r
- {0x83u, 0x10u},\r
- {0x8Bu, 0x80u},\r
- {0x8Cu, 0x02u},\r
- {0x8Fu, 0x40u},\r
- {0x90u, 0x02u},\r
- {0x93u, 0x02u},\r
- {0x94u, 0x02u},\r
- {0x98u, 0x04u},\r
+ {0x80u, 0x10u},\r
+ {0x84u, 0x10u},\r
+ {0x85u, 0x50u},\r
+ {0x87u, 0xA0u},\r
+ {0x88u, 0x0Au},\r
+ {0x8Au, 0x05u},\r
+ {0x8Bu, 0xFFu},\r
+ {0x8Du, 0x0Fu},\r
+ {0x8Eu, 0x07u},\r
+ {0x8Fu, 0xF0u},\r
+ {0x91u, 0x60u},\r
+ {0x93u, 0x90u},\r
+ {0x94u, 0x10u},\r
+ {0x95u, 0x05u},\r
+ {0x97u, 0x0Au},\r
+ {0x99u, 0xFFu},\r
{0x9Au, 0x08u},\r
- {0x9Bu, 0x08u},\r
- {0x9Cu, 0x08u},\r
- {0x9Eu, 0x04u},\r
- {0xA3u, 0x04u},\r
- {0xA5u, 0x55u},\r
- {0xA7u, 0xAAu},\r
- {0xABu, 0x01u},\r
- {0xACu, 0x08u},\r
- {0xAEu, 0x05u},\r
- {0xAFu, 0x20u},\r
- {0xB1u, 0x30u},\r
- {0xB2u, 0x02u},\r
- {0xB3u, 0xC0u},\r
- {0xB4u, 0x0Cu},\r
- {0xB5u, 0x0Cu},\r
- {0xB6u, 0x01u},\r
- {0xB7u, 0x03u},\r
+ {0x9Fu, 0xFFu},\r
+ {0xA0u, 0x09u},\r
+ {0xA2u, 0x02u},\r
+ {0xA4u, 0x04u},\r
+ {0xA5u, 0x30u},\r
+ {0xA6u, 0x08u},\r
+ {0xA7u, 0xC0u},\r
+ {0xA8u, 0x10u},\r
+ {0xA9u, 0x06u},\r
+ {0xABu, 0x09u},\r
+ {0xADu, 0x03u},\r
+ {0xAFu, 0x0Cu},\r
+ {0xB2u, 0x10u},\r
+ {0xB5u, 0xFFu},\r
+ {0xB6u, 0x0Fu},\r
{0xB8u, 0x08u},\r
- {0xBAu, 0x20u},\r
{0xBEu, 0x04u},\r
- {0xBFu, 0x55u},\r
- {0xD6u, 0x08u},\r
+ {0xBFu, 0x10u},\r
+ {0xD4u, 0x01u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x09u},\r
- {0xDDu, 0x90u},\r
+ {0xDCu, 0x01u},\r
+ {0xDDu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x08u},\r
- {0x02u, 0x02u},\r
- {0x04u, 0x80u},\r
- {0x07u, 0x40u},\r
- {0x08u, 0x01u},\r
- {0x09u, 0x80u},\r
- {0x0Au, 0x04u},\r
- {0x0Du, 0x02u},\r
- {0x0Eu, 0x1Au},\r
- {0x11u, 0x28u},\r
- {0x12u, 0x20u},\r
- {0x13u, 0x01u},\r
- {0x14u, 0x02u},\r
- {0x1Au, 0x04u},\r
- {0x1Cu, 0x20u},\r
- {0x1Eu, 0x0Au},\r
- {0x20u, 0x80u},\r
- {0x21u, 0x01u},\r
- {0x22u, 0x04u},\r
- {0x23u, 0x20u},\r
- {0x24u, 0x20u},\r
- {0x25u, 0x60u},\r
- {0x27u, 0x80u},\r
- {0x28u, 0x01u},\r
- {0x2Du, 0x19u},\r
- {0x2Fu, 0x09u},\r
- {0x32u, 0x26u},\r
- {0x33u, 0x08u},\r
- {0x37u, 0x11u},\r
- {0x39u, 0x42u},\r
- {0x3Au, 0x02u},\r
- {0x3Bu, 0x10u},\r
- {0x3Cu, 0x80u},\r
- {0x3Eu, 0x21u},\r
- {0x58u, 0x10u},\r
- {0x59u, 0x04u},\r
- {0x5Au, 0x42u},\r
- {0x5Cu, 0x80u},\r
- {0x60u, 0x04u},\r
- {0x63u, 0x4Au},\r
- {0x64u, 0x02u},\r
- {0x81u, 0x20u},\r
- {0x87u, 0xC0u},\r
- {0x88u, 0x80u},\r
- {0x8Au, 0x04u},\r
- {0x8Cu, 0x10u},\r
- {0x90u, 0x82u},\r
- {0x91u, 0x41u},\r
- {0x93u, 0x11u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x30u},\r
- {0x99u, 0xB0u},\r
- {0x9Au, 0xF0u},\r
- {0x9Bu, 0x17u},\r
- {0xA0u, 0x20u},\r
- {0xA1u, 0x07u},\r
- {0xA2u, 0x02u},\r
- {0xA6u, 0x44u},\r
+ {0x00u, 0x28u},\r
+ {0x01u, 0x40u},\r
+ {0x02u, 0x80u},\r
+ {0x04u, 0x04u},\r
+ {0x05u, 0x61u},\r
+ {0x06u, 0x02u},\r
+ {0x08u, 0x04u},\r
+ {0x0Au, 0x44u},\r
+ {0x0Bu, 0x82u},\r
+ {0x0Eu, 0x20u},\r
+ {0x0Fu, 0x04u},\r
+ {0x11u, 0x12u},\r
+ {0x13u, 0x08u},\r
+ {0x14u, 0x20u},\r
+ {0x16u, 0x40u},\r
+ {0x17u, 0x20u},\r
+ {0x19u, 0x01u},\r
+ {0x1Du, 0x40u},\r
+ {0x1Fu, 0x04u},\r
+ {0x21u, 0x02u},\r
+ {0x23u, 0x40u},\r
+ {0x26u, 0x10u},\r
+ {0x28u, 0x22u},\r
+ {0x29u, 0x20u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Eu, 0x20u},\r
+ {0x2Fu, 0x01u},\r
+ {0x30u, 0x80u},\r
+ {0x31u, 0x02u},\r
+ {0x34u, 0x04u},\r
+ {0x36u, 0xA0u},\r
+ {0x37u, 0x01u},\r
+ {0x38u, 0x80u},\r
+ {0x39u, 0x10u},\r
+ {0x3Au, 0x08u},\r
+ {0x3Bu, 0x20u},\r
+ {0x3Cu, 0x08u},\r
+ {0x3Du, 0x50u},\r
+ {0x45u, 0x01u},\r
+ {0x47u, 0x01u},\r
+ {0x59u, 0x16u},\r
+ {0x5Au, 0x40u},\r
+ {0x5Fu, 0x40u},\r
+ {0x63u, 0x02u},\r
+ {0x69u, 0x40u},\r
+ {0x83u, 0x40u},\r
+ {0x84u, 0x80u},\r
+ {0x86u, 0x40u},\r
+ {0x87u, 0x12u},\r
+ {0x8Bu, 0x04u},\r
+ {0x8Fu, 0x80u},\r
+ {0x90u, 0xA4u},\r
+ {0x92u, 0x04u},\r
+ {0x93u, 0xA6u},\r
+ {0x95u, 0xC0u},\r
+ {0x97u, 0x10u},\r
+ {0x98u, 0x04u},\r
+ {0x99u, 0x34u},\r
+ {0x9Au, 0x80u},\r
+ {0x9Bu, 0x01u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Fu, 0x48u},\r
+ {0xA0u, 0x3Cu},\r
+ {0xA1u, 0x20u},\r
+ {0xA3u, 0x2Du},\r
+ {0xA7u, 0x82u},\r
{0xA8u, 0x40u},\r
- {0xA9u, 0x40u},\r
- {0xAAu, 0x04u},\r
- {0xABu, 0x08u},\r
{0xACu, 0x02u},\r
- {0xAEu, 0x20u},\r
- {0xAFu, 0x80u},\r
- {0xB0u, 0x88u},\r
- {0xB1u, 0x40u},\r
- {0xB3u, 0x10u},\r
- {0xB7u, 0x01u},\r
- {0xC0u, 0x95u},\r
- {0xC2u, 0xFBu},\r
- {0xC4u, 0x8Eu},\r
- {0xCAu, 0xF8u},\r
- {0xCCu, 0xA7u},\r
- {0xCEu, 0xBDu},\r
+ {0xAEu, 0xC0u},\r
+ {0xB2u, 0x08u},\r
+ {0xB3u, 0x12u},\r
+ {0xB5u, 0x40u},\r
+ {0xC0u, 0xFFu},\r
+ {0xC2u, 0x67u},\r
+ {0xC4u, 0x7Eu},\r
+ {0xCAu, 0x7Eu},\r
+ {0xCCu, 0xF9u},\r
+ {0xCEu, 0x7Eu},\r
{0xD6u, 0x1Fu},\r
- {0xD8u, 0x19u},\r
- {0xE0u, 0x06u},\r
- {0xEAu, 0x03u},\r
- {0xEEu, 0x12u},\r
- {0x00u, 0x0Fu},\r
- {0x01u, 0x03u},\r
- {0x02u, 0xF0u},\r
- {0x03u, 0x0Cu},\r
- {0x04u, 0x30u},\r
- {0x06u, 0xC0u},\r
- {0x07u, 0xFFu},\r
- {0x08u, 0x05u},\r
- {0x0Au, 0x0Au},\r
- {0x0Cu, 0x90u},\r
- {0x0Du, 0x06u},\r
- {0x0Eu, 0x60u},\r
- {0x0Fu, 0x09u},\r
- {0x11u, 0x60u},\r
- {0x12u, 0xFFu},\r
- {0x13u, 0x90u},\r
- {0x15u, 0x50u},\r
- {0x17u, 0xA0u},\r
- {0x19u, 0x30u},\r
- {0x1Au, 0xFFu},\r
- {0x1Bu, 0xC0u},\r
- {0x1Du, 0xFFu},\r
- {0x1Eu, 0xFFu},\r
- {0x20u, 0x03u},\r
- {0x22u, 0x0Cu},\r
- {0x23u, 0xFFu},\r
- {0x24u, 0x50u},\r
- {0x25u, 0x0Fu},\r
- {0x26u, 0xA0u},\r
- {0x27u, 0xF0u},\r
- {0x28u, 0x09u},\r
- {0x29u, 0x05u},\r
- {0x2Au, 0x06u},\r
- {0x2Bu, 0x0Au},\r
- {0x31u, 0xFFu},\r
- {0x32u, 0xFFu},\r
- {0x3Eu, 0x04u},\r
- {0x3Fu, 0x01u},\r
+ {0xD8u, 0x08u},\r
+ {0xE2u, 0x08u},\r
+ {0xE6u, 0x05u},\r
+ {0xE8u, 0x0Cu},\r
+ {0xEAu, 0x20u},\r
+ {0xEEu, 0x1Eu},\r
+ {0x05u, 0x50u},\r
+ {0x07u, 0xA0u},\r
+ {0x0Au, 0x10u},\r
+ {0x0Bu, 0xFFu},\r
+ {0x0Du, 0x0Fu},\r
+ {0x0Eu, 0x08u},\r
+ {0x0Fu, 0xF0u},\r
+ {0x11u, 0x90u},\r
+ {0x13u, 0x60u},\r
+ {0x15u, 0x05u},\r
+ {0x17u, 0x0Au},\r
+ {0x1Au, 0x01u},\r
+ {0x1Bu, 0xFFu},\r
+ {0x1Eu, 0x05u},\r
+ {0x1Fu, 0xFFu},\r
+ {0x22u, 0x03u},\r
+ {0x24u, 0x06u},\r
+ {0x25u, 0x30u},\r
+ {0x27u, 0xC0u},\r
+ {0x29u, 0x09u},\r
+ {0x2Bu, 0x06u},\r
+ {0x2Cu, 0x08u},\r
+ {0x2Du, 0x03u},\r
+ {0x2Eu, 0x10u},\r
+ {0x2Fu, 0x0Cu},\r
+ {0x33u, 0xFFu},\r
+ {0x34u, 0x07u},\r
+ {0x36u, 0x18u},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x04u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x31u},\r
- {0x82u, 0x07u},\r
- {0x83u, 0x02u},\r
- {0x85u, 0xC0u},\r
- {0x87u, 0x2Cu},\r
- {0x89u, 0xE4u},\r
- {0x8Bu, 0x08u},\r
- {0x8Cu, 0x99u},\r
- {0x8Du, 0x24u},\r
- {0x8Eu, 0x22u},\r
- {0x91u, 0x2Cu},\r
- {0x93u, 0xC0u},\r
- {0x94u, 0xAAu},\r
- {0x95u, 0x11u},\r
- {0x96u, 0x55u},\r
- {0x97u, 0x0Eu},\r
- {0x98u, 0x44u},\r
- {0x9Au, 0x88u},\r
- {0x9Bu, 0x2Fu},\r
- {0x9Du, 0xECu},\r
- {0x9Eu, 0x70u},\r
- {0xA2u, 0x08u},\r
- {0xA3u, 0x80u},\r
- {0xA5u, 0x08u},\r
- {0xA6u, 0x80u},\r
- {0xA7u, 0x10u},\r
- {0xADu, 0xECu},\r
- {0xB0u, 0x0Fu},\r
- {0xB1u, 0x40u},\r
- {0xB3u, 0x80u},\r
- {0xB5u, 0x31u},\r
- {0xB6u, 0xF0u},\r
- {0xB7u, 0x0Fu},\r
- {0xBBu, 0x30u},\r
- {0xBFu, 0x05u},\r
- {0xD4u, 0x40u},\r
- {0xD6u, 0x04u},\r
- {0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x01u},\r
- {0xDFu, 0x01u},\r
- {0x01u, 0x02u},\r
- {0x02u, 0x02u},\r
- {0x04u, 0x02u},\r
- {0x05u, 0x20u},\r
- {0x07u, 0x11u},\r
- {0x09u, 0x04u},\r
- {0x0Au, 0x05u},\r
- {0x0Cu, 0x40u},\r
- {0x0Eu, 0x80u},\r
- {0x0Fu, 0x09u},\r
- {0x10u, 0x20u},\r
- {0x13u, 0x02u},\r
- {0x15u, 0x05u},\r
- {0x17u, 0x24u},\r
- {0x19u, 0x02u},\r
- {0x1Au, 0x01u},\r
+ {0x80u, 0x10u},\r
+ {0x84u, 0x01u},\r
+ {0x88u, 0x40u},\r
+ {0x89u, 0x60u},\r
+ {0x8Bu, 0x90u},\r
+ {0x8Cu, 0x87u},\r
+ {0x8Du, 0x0Fu},\r
+ {0x8Eu, 0x18u},\r
+ {0x8Fu, 0xF0u},\r
+ {0x90u, 0x88u},\r
+ {0x92u, 0x21u},\r
+ {0x94u, 0x04u},\r
+ {0x95u, 0x50u},\r
+ {0x97u, 0xA0u},\r
+ {0x98u, 0x40u},\r
+ {0x99u, 0x05u},\r
+ {0x9Bu, 0x0Au},\r
+ {0x9Cu, 0x01u},\r
+ {0xA0u, 0x01u},\r
+ {0xA1u, 0x06u},\r
+ {0xA3u, 0x09u},\r
+ {0xA4u, 0x01u},\r
+ {0xA5u, 0x03u},\r
+ {0xA7u, 0x0Cu},\r
+ {0xA8u, 0xA2u},\r
+ {0xAAu, 0x08u},\r
+ {0xACu, 0x01u},\r
+ {0xADu, 0x30u},\r
+ {0xAFu, 0xC0u},\r
+ {0xB0u, 0x08u},\r
+ {0xB2u, 0x40u},\r
+ {0xB4u, 0x3Fu},\r
+ {0xB5u, 0xFFu},\r
+ {0xB6u, 0x80u},\r
+ {0xB8u, 0x28u},\r
+ {0xBEu, 0x51u},\r
+ {0xBFu, 0x10u},\r
+ {0xD4u, 0x09u},\r
+ {0xD6u, 0x04u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDFu, 0x01u},\r
+ {0x00u, 0xA0u},\r
+ {0x01u, 0x04u},\r
+ {0x02u, 0x40u},\r
+ {0x04u, 0x20u},\r
+ {0x06u, 0x02u},\r
+ {0x0Au, 0xA9u},\r
+ {0x0Eu, 0x04u},\r
+ {0x0Fu, 0x02u},\r
+ {0x10u, 0x02u},\r
+ {0x11u, 0x01u},\r
+ {0x12u, 0x08u},\r
+ {0x13u, 0x04u},\r
+ {0x15u, 0x4Au},\r
+ {0x19u, 0x40u},\r
+ {0x1Au, 0x68u},\r
+ {0x1Bu, 0x04u},\r
+ {0x1Eu, 0x04u},\r
+ {0x1Fu, 0x80u},\r
+ {0x22u, 0x20u},\r
+ {0x23u, 0x08u},\r
+ {0x27u, 0x20u},\r
+ {0x29u, 0x80u},\r
+ {0x2Au, 0x8Au},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Eu, 0x20u},\r
+ {0x2Fu, 0x01u},\r
+ {0x30u, 0x08u},\r
+ {0x31u, 0x20u},\r
+ {0x34u, 0x04u},\r
+ {0x36u, 0xA0u},\r
+ {0x37u, 0x01u},\r
+ {0x38u, 0x20u},\r
+ {0x39u, 0x40u},\r
+ {0x3Cu, 0x08u},\r
+ {0x3Du, 0x50u},\r
+ {0x59u, 0x19u},\r
+ {0x5Au, 0x40u},\r
+ {0x61u, 0x42u},\r
+ {0x81u, 0x02u},\r
+ {0x87u, 0x81u},\r
+ {0x89u, 0x20u},\r
+ {0x90u, 0x20u},\r
+ {0x91u, 0x50u},\r
+ {0x93u, 0x02u},\r
+ {0x95u, 0x80u},\r
+ {0x98u, 0x04u},\r
+ {0x9Au, 0xA2u},\r
+ {0x9Bu, 0x01u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Fu, 0x28u},\r
+ {0xA0u, 0x2Cu},\r
+ {0xA1u, 0x20u},\r
+ {0xA3u, 0x08u},\r
+ {0xA6u, 0xA0u},\r
+ {0xA8u, 0x20u},\r
+ {0xABu, 0x04u},\r
+ {0xACu, 0x10u},\r
+ {0xAEu, 0x28u},\r
+ {0xB1u, 0x02u},\r
+ {0xB3u, 0x20u},\r
+ {0xB4u, 0x02u},\r
+ {0xC0u, 0xCFu},\r
+ {0xC2u, 0xCFu},\r
+ {0xC4u, 0xBFu},\r
+ {0xCAu, 0x7Bu},\r
+ {0xCCu, 0xF6u},\r
+ {0xCEu, 0x7Cu},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x09u},\r
+ {0xE0u, 0x02u},\r
+ {0xE2u, 0x08u},\r
+ {0xE4u, 0x08u},\r
+ {0xE6u, 0x01u},\r
+ {0xEAu, 0x01u},\r
+ {0xECu, 0x04u},\r
+ {0xEEu, 0x02u},\r
+ {0x00u, 0x50u},\r
+ {0x02u, 0xA0u},\r
+ {0x06u, 0x20u},\r
+ {0x0Au, 0x08u},\r
+ {0x0Du, 0x01u},\r
+ {0x0Eu, 0x40u},\r
+ {0x0Fu, 0x02u},\r
+ {0x10u, 0x09u},\r
+ {0x12u, 0x02u},\r
+ {0x13u, 0x02u},\r
+ {0x16u, 0x07u},\r
+ {0x17u, 0x01u},\r
+ {0x18u, 0x04u},\r
+ {0x1Au, 0x08u},\r
{0x1Eu, 0x10u},\r
- {0x20u, 0x05u},\r
+ {0x1Fu, 0x1Cu},\r
+ {0x21u, 0x24u},\r
+ {0x22u, 0x80u},\r
+ {0x23u, 0x08u},\r
+ {0x25u, 0x10u},\r
+ {0x27u, 0x20u},\r
+ {0x28u, 0x0Au},\r
+ {0x29u, 0x28u},\r
+ {0x2Au, 0x05u},\r
+ {0x2Bu, 0x14u},\r
+ {0x2Fu, 0x20u},\r
+ {0x31u, 0x3Cu},\r
+ {0x32u, 0x0Fu},\r
+ {0x34u, 0xC0u},\r
+ {0x35u, 0x03u},\r
+ {0x36u, 0x30u},\r
+ {0x3Eu, 0x50u},\r
+ {0x3Fu, 0x10u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x11u},\r
+ {0x5Fu, 0x01u},\r
+ {0x80u, 0xFFu},\r
+ {0x81u, 0x02u},\r
+ {0x83u, 0x01u},\r
+ {0x86u, 0xFFu},\r
+ {0x88u, 0xFFu},\r
+ {0x8Eu, 0xFFu},\r
+ {0x90u, 0x96u},\r
+ {0x92u, 0x69u},\r
+ {0x94u, 0x0Fu},\r
+ {0x95u, 0x01u},\r
+ {0x96u, 0xF0u},\r
+ {0x97u, 0x02u},\r
+ {0x99u, 0x02u},\r
+ {0x9Bu, 0x05u},\r
+ {0x9Du, 0x02u},\r
+ {0x9Fu, 0x09u},\r
+ {0xA0u, 0x33u},\r
+ {0xA2u, 0xCCu},\r
+ {0xA8u, 0x55u},\r
+ {0xAAu, 0xAAu},\r
+ {0xADu, 0x02u},\r
+ {0xAEu, 0xFFu},\r
+ {0xAFu, 0x11u},\r
+ {0xB1u, 0x08u},\r
+ {0xB3u, 0x03u},\r
+ {0xB4u, 0xFFu},\r
+ {0xB5u, 0x10u},\r
+ {0xB7u, 0x04u},\r
+ {0xBAu, 0x20u},\r
+ {0xBBu, 0x08u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x11u},\r
+ {0xDDu, 0x90u},\r
+ {0xDFu, 0x01u},\r
+ {0x00u, 0x4Au},\r
+ {0x03u, 0x08u},\r
+ {0x04u, 0x80u},\r
+ {0x05u, 0x22u},\r
+ {0x06u, 0x90u},\r
+ {0x08u, 0x02u},\r
+ {0x0Bu, 0x10u},\r
+ {0x0Cu, 0xA2u},\r
+ {0x0Eu, 0x28u},\r
+ {0x10u, 0x02u},\r
+ {0x12u, 0x84u},\r
+ {0x14u, 0x04u},\r
+ {0x16u, 0x40u},\r
+ {0x1Bu, 0x10u},\r
+ {0x1Eu, 0x22u},\r
+ {0x1Fu, 0x10u},\r
{0x21u, 0x09u},\r
- {0x22u, 0x91u},\r
+ {0x22u, 0x50u},\r
+ {0x24u, 0x88u},\r
{0x27u, 0x40u},\r
- {0x28u, 0x10u},\r
{0x29u, 0x40u},\r
- {0x2Au, 0x05u},\r
- {0x2Cu, 0x40u},\r
- {0x2Du, 0x28u},\r
- {0x32u, 0x18u},\r
- {0x33u, 0x82u},\r
- {0x36u, 0x40u},\r
- {0x37u, 0x15u},\r
- {0x38u, 0x69u},\r
- {0x3Cu, 0x80u},\r
- {0x3Du, 0x01u},\r
- {0x3Fu, 0x08u},\r
- {0x45u, 0x80u},\r
- {0x46u, 0x01u},\r
- {0x61u, 0x88u},\r
- {0x62u, 0x20u},\r
- {0x63u, 0x40u},\r
- {0x64u, 0x80u},\r
- {0x65u, 0x02u},\r
- {0x86u, 0x04u},\r
- {0x89u, 0x50u},\r
- {0x8Au, 0x80u},\r
- {0x8Bu, 0x40u},\r
- {0x90u, 0x02u},\r
- {0x91u, 0x01u},\r
- {0x93u, 0x01u},\r
- {0x96u, 0x53u},\r
- {0x99u, 0xB8u},\r
- {0x9Au, 0xD2u},\r
- {0x9Bu, 0x37u},\r
- {0x9Cu, 0x10u},\r
- {0x9Du, 0x04u},\r
- {0x9Fu, 0x40u},\r
- {0xA0u, 0x20u},\r
- {0xA1u, 0x45u},\r
- {0xA2u, 0x02u},\r
- {0xA6u, 0x40u},\r
- {0xA7u, 0x24u},\r
- {0xA8u, 0x01u},\r
- {0xA9u, 0x18u},\r
- {0xACu, 0x14u},\r
- {0xADu, 0x10u},\r
- {0xAFu, 0x20u},\r
- {0xB0u, 0x01u},\r
- {0xB1u, 0x80u},\r
- {0xB3u, 0x21u},\r
- {0xB5u, 0x10u},\r
- {0xB7u, 0x01u},\r
- {0xC0u, 0xF9u},\r
- {0xC2u, 0xD7u},\r
- {0xC4u, 0x7Cu},\r
- {0xCAu, 0xEBu},\r
- {0xCCu, 0xFFu},\r
- {0xCEu, 0xDFu},\r
- {0xD8u, 0x0Fu},\r
- {0xE2u, 0x23u},\r
- {0xE8u, 0x08u},\r
- {0xEAu, 0x01u},\r
- {0xEEu, 0x02u},\r
- {0x80u, 0x02u},\r
- {0x85u, 0x40u},\r
- {0x9Cu, 0x02u},\r
- {0x9Du, 0x08u},\r
- {0xA1u, 0x40u},\r
- {0xA2u, 0x04u},\r
- {0xA9u, 0x40u},\r
+ {0x2Cu, 0x24u},\r
+ {0x2Fu, 0x49u},\r
+ {0x31u, 0x08u},\r
+ {0x32u, 0x50u},\r
+ {0x36u, 0x02u},\r
+ {0x37u, 0x48u},\r
+ {0x39u, 0x02u},\r
+ {0x3Eu, 0x80u},\r
+ {0x4Fu, 0x30u},\r
+ {0x58u, 0x80u},\r
+ {0x5Cu, 0x20u},\r
+ {0x5Eu, 0x44u},\r
+ {0x5Fu, 0x02u},\r
+ {0x60u, 0x02u},\r
+ {0x64u, 0x01u},\r
+ {0x81u, 0x20u},\r
+ {0x82u, 0x40u},\r
+ {0x86u, 0x10u},\r
+ {0x88u, 0x04u},\r
+ {0x8Bu, 0x0Au},\r
+ {0x8Cu, 0x04u},\r
+ {0x90u, 0x42u},\r
+ {0x92u, 0x04u},\r
+ {0x93u, 0x82u},\r
+ {0x95u, 0x10u},\r
+ {0x97u, 0x20u},\r
+ {0x99u, 0x62u},\r
+ {0x9Au, 0x04u},\r
+ {0xA0u, 0x07u},\r
+ {0xA1u, 0x20u},\r
+ {0xA2u, 0x84u},\r
+ {0xA3u, 0x08u},\r
+ {0xA5u, 0x08u},\r
+ {0xA6u, 0x10u},\r
+ {0xA7u, 0x10u},\r
+ {0xA8u, 0x40u},\r
+ {0xAAu, 0x04u},\r
+ {0xACu, 0x44u},\r
{0xAEu, 0x01u},\r
- {0xB1u, 0x01u},\r
- {0xB3u, 0x31u},\r
- {0xB5u, 0x20u},\r
- {0xE2u, 0x01u},\r
- {0xE4u, 0x20u},\r
+ {0xAFu, 0x20u},\r
+ {0xB5u, 0x84u},\r
+ {0xB7u, 0x10u},\r
+ {0xC0u, 0xFFu},\r
+ {0xC2u, 0xFCu},\r
+ {0xC4u, 0x5Bu},\r
+ {0xCAu, 0xF8u},\r
+ {0xCCu, 0xDEu},\r
+ {0xCEu, 0x11u},\r
+ {0xD6u, 0xF8u},\r
+ {0xD8u, 0x18u},\r
+ {0xE2u, 0x08u},\r
+ {0xE4u, 0x88u},\r
{0xE6u, 0x01u},\r
- {0xE8u, 0x08u},\r
- {0xEAu, 0x20u},\r
- {0xEEu, 0x20u},\r
- {0x00u, 0x33u},\r
- {0x02u, 0xCCu},\r
- {0x09u, 0xFFu},\r
- {0x0Au, 0xFFu},\r
- {0x0Cu, 0xFFu},\r
- {0x0Du, 0x0Fu},\r
- {0x0Fu, 0xF0u},\r
- {0x13u, 0xFFu},\r
- {0x14u, 0x69u},\r
- {0x16u, 0x96u},\r
- {0x17u, 0xFFu},\r
- {0x1Au, 0xFFu},\r
- {0x1Bu, 0xFFu},\r
+ {0xEAu, 0x19u},\r
+ {0x00u, 0xFFu},\r
+ {0x06u, 0xFFu},\r
+ {0x08u, 0xFFu},\r
+ {0x09u, 0x02u},\r
+ {0x0Bu, 0x09u},\r
+ {0x0Eu, 0xFFu},\r
+ {0x12u, 0xFFu},\r
+ {0x14u, 0x33u},\r
+ {0x15u, 0x02u},\r
+ {0x16u, 0xCCu},\r
+ {0x17u, 0x01u},\r
+ {0x19u, 0x01u},\r
+ {0x1Bu, 0x02u},\r
{0x1Cu, 0x0Fu},\r
+ {0x1Du, 0x02u},\r
{0x1Eu, 0xF0u},\r
- {0x21u, 0x55u},\r
- {0x23u, 0xAAu},\r
- {0x24u, 0xFFu},\r
- {0x25u, 0x33u},\r
- {0x27u, 0xCCu},\r
+ {0x1Fu, 0x05u},\r
+ {0x24u, 0x69u},\r
+ {0x26u, 0x96u},\r
{0x28u, 0x55u},\r
- {0x29u, 0x69u},\r
{0x2Au, 0xAAu},\r
- {0x2Bu, 0x96u},\r
- {0x2Du, 0xFFu},\r
- {0x2Eu, 0xFFu},\r
+ {0x2Du, 0x02u},\r
+ {0x2Fu, 0x01u},\r
+ {0x33u, 0x04u},\r
+ {0x35u, 0x03u},\r
{0x36u, 0xFFu},\r
- {0x37u, 0xFFu},\r
+ {0x37u, 0x08u},\r
{0x3Au, 0x80u},\r
- {0x3Bu, 0x80u},\r
+ {0x3Bu, 0x20u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0xFFu},\r
- {0x83u, 0x04u},\r
- {0x86u, 0xFFu},\r
- {0x87u, 0x7Fu},\r
- {0x8Cu, 0x96u},\r
- {0x8Du, 0x20u},\r
- {0x8Eu, 0x69u},\r
- {0x8Fu, 0x40u},\r
- {0x90u, 0x0Fu},\r
- {0x91u, 0x09u},\r
- {0x92u, 0xF0u},\r
- {0x93u, 0x72u},\r
- {0x96u, 0xFFu},\r
- {0x99u, 0x74u},\r
- {0x9Au, 0xFFu},\r
- {0x9Bu, 0x09u},\r
- {0x9Du, 0x20u},\r
- {0x9Fu, 0x40u},\r
- {0xA0u, 0x33u},\r
- {0xA1u, 0x08u},\r
- {0xA2u, 0xCCu},\r
- {0xA4u, 0x55u},\r
- {0xA6u, 0xAAu},\r
- {0xA7u, 0x01u},\r
- {0xA8u, 0xFFu},\r
- {0xA9u, 0x01u},\r
- {0xABu, 0x66u},\r
- {0xADu, 0x62u},\r
- {0xB1u, 0x60u},\r
- {0xB4u, 0xFFu},\r
- {0xB7u, 0x1Fu},\r
- {0xBAu, 0x20u},\r
- {0xBBu, 0x02u},\r
- {0xD4u, 0x01u},\r
+ {0x81u, 0x0Fu},\r
+ {0x84u, 0x40u},\r
+ {0x86u, 0x80u},\r
+ {0x87u, 0x0Fu},\r
+ {0x88u, 0x40u},\r
+ {0x89u, 0x04u},\r
+ {0x8Au, 0x80u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Cu, 0x06u},\r
+ {0x8Eu, 0xE1u},\r
+ {0x8Fu, 0x0Fu},\r
+ {0x93u, 0x0Fu},\r
+ {0x94u, 0xD0u},\r
+ {0x95u, 0x01u},\r
+ {0x96u, 0x21u},\r
+ {0x97u, 0x02u},\r
+ {0x99u, 0x04u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Cu, 0x16u},\r
+ {0x9Eu, 0xE1u},\r
+ {0xA0u, 0x01u},\r
+ {0xA2u, 0x02u},\r
+ {0xA3u, 0x10u},\r
+ {0xA4u, 0x08u},\r
+ {0xA6u, 0xC1u},\r
+ {0xA9u, 0x0Fu},\r
+ {0xAAu, 0x04u},\r
+ {0xACu, 0xC0u},\r
+ {0xADu, 0x01u},\r
+ {0xAEu, 0x21u},\r
+ {0xAFu, 0x02u},\r
+ {0xB2u, 0xC0u},\r
+ {0xB3u, 0x03u},\r
+ {0xB4u, 0x03u},\r
+ {0xB5u, 0x0Cu},\r
+ {0xB6u, 0x3Cu},\r
+ {0xB7u, 0x10u},\r
+ {0xB8u, 0x80u},\r
+ {0xBAu, 0x28u},\r
+ {0xBBu, 0x28u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
{0xDCu, 0x11u},\r
- {0xDDu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x80u},\r
- {0x02u, 0x40u},\r
+ {0x00u, 0x4Au},\r
{0x03u, 0x08u},\r
- {0x04u, 0x02u},\r
- {0x05u, 0x40u},\r
- {0x07u, 0x20u},\r
+ {0x04u, 0x50u},\r
+ {0x05u, 0x04u},\r
{0x08u, 0x08u},\r
- {0x0Au, 0x06u},\r
- {0x0Du, 0x09u},\r
- {0x0Eu, 0x04u},\r
- {0x10u, 0x10u},\r
- {0x11u, 0x80u},\r
- {0x12u, 0x04u},\r
- {0x15u, 0x10u},\r
- {0x16u, 0xA0u},\r
+ {0x0Au, 0x02u},\r
+ {0x0Bu, 0x80u},\r
+ {0x0Du, 0x04u},\r
+ {0x0Eu, 0x02u},\r
+ {0x12u, 0x28u},\r
+ {0x14u, 0x40u},\r
+ {0x15u, 0x84u},\r
{0x17u, 0x10u},\r
{0x1Au, 0x02u},\r
- {0x1Fu, 0x10u},\r
- {0x21u, 0x40u},\r
- {0x24u, 0x80u},\r
- {0x25u, 0x40u},\r
- {0x27u, 0x41u},\r
- {0x28u, 0x20u},\r
- {0x29u, 0x80u},\r
- {0x2Bu, 0x44u},\r
- {0x2Cu, 0x20u},\r
- {0x2Du, 0x81u},\r
+ {0x1Du, 0x04u},\r
+ {0x1Eu, 0x02u},\r
+ {0x1Fu, 0x64u},\r
+ {0x21u, 0x20u},\r
+ {0x22u, 0x44u},\r
+ {0x24u, 0x08u},\r
+ {0x25u, 0x14u},\r
+ {0x27u, 0x01u},\r
+ {0x2Au, 0x40u},\r
+ {0x2Du, 0x80u},\r
+ {0x2Eu, 0x01u},\r
{0x2Fu, 0x08u},\r
- {0x31u, 0x28u},\r
- {0x33u, 0x09u},\r
- {0x34u, 0x10u},\r
- {0x37u, 0x51u},\r
- {0x39u, 0x90u},\r
- {0x3Du, 0x02u},\r
- {0x3Eu, 0x04u},\r
- {0x3Fu, 0x80u},\r
- {0x58u, 0x82u},\r
- {0x59u, 0x28u},\r
- {0x5Fu, 0x80u},\r
- {0x60u, 0x20u},\r
+ {0x31u, 0x20u},\r
+ {0x32u, 0x44u},\r
+ {0x34u, 0x08u},\r
+ {0x35u, 0x10u},\r
+ {0x36u, 0x01u},\r
+ {0x39u, 0x20u},\r
+ {0x3Cu, 0x4Au},\r
+ {0x3Du, 0x24u},\r
+ {0x41u, 0x04u},\r
+ {0x43u, 0x08u},\r
+ {0x58u, 0x94u},\r
+ {0x60u, 0x18u},\r
{0x61u, 0x40u},\r
{0x62u, 0x08u},\r
- {0x63u, 0x88u},\r
- {0x80u, 0x80u},\r
- {0x8Bu, 0x80u},\r
+ {0x80u, 0x04u},\r
+ {0x84u, 0x02u},\r
+ {0x87u, 0x50u},\r
+ {0x88u, 0x10u},\r
+ {0x8Fu, 0x20u},\r
{0x90u, 0x02u},\r
- {0x91u, 0x01u},\r
- {0x92u, 0x04u},\r
- {0x94u, 0x80u},\r
- {0x98u, 0x08u},\r
- {0x99u, 0x80u},\r
- {0x9Au, 0xE4u},\r
+ {0x91u, 0xA0u},\r
+ {0x92u, 0x05u},\r
+ {0x93u, 0x02u},\r
+ {0x95u, 0x10u},\r
+ {0x97u, 0x08u},\r
+ {0x98u, 0x80u},\r
+ {0x99u, 0x32u},\r
+ {0x9Au, 0x44u},\r
{0x9Bu, 0x10u},\r
- {0xA0u, 0x20u},\r
- {0xA1u, 0x29u},\r
- {0xA2u, 0x04u},\r
- {0xA5u, 0x40u},\r
- {0xA6u, 0x08u},\r
- {0xA7u, 0x04u},\r
- {0xABu, 0x20u},\r
- {0xAFu, 0x11u},\r
- {0xB0u, 0x80u},\r
- {0xB1u, 0x60u},\r
- {0xB2u, 0x10u},\r
- {0xB3u, 0x60u},\r
- {0xB4u, 0x20u},\r
- {0xC0u, 0xBBu},\r
- {0xC2u, 0x77u},\r
- {0xC4u, 0x77u},\r
- {0xCAu, 0xFFu},\r
- {0xCCu, 0xB7u},\r
- {0xCEu, 0xDCu},\r
- {0xD6u, 0x1Fu},\r
- {0xD8u, 0x0Fu},\r
- {0xE0u, 0x06u},\r
- {0xE2u, 0x20u},\r
- {0xE4u, 0x60u},\r
- {0xE6u, 0x01u},\r
- {0xEAu, 0x80u},\r
- {0xEEu, 0x30u},\r
- {0x01u, 0x10u},\r
- {0x03u, 0x20u},\r
- {0x04u, 0x20u},\r
- {0x05u, 0x10u},\r
- {0x06u, 0x10u},\r
- {0x07u, 0x20u},\r
- {0x08u, 0x04u},\r
- {0x09u, 0x02u},\r
- {0x0Au, 0x08u},\r
- {0x0Bu, 0x3Du},\r
- {0x0Cu, 0x20u},\r
- {0x0Du, 0x3Cu},\r
- {0x0Eu, 0x11u},\r
- {0x0Fu, 0x01u},\r
- {0x11u, 0x04u},\r
- {0x13u, 0x08u},\r
- {0x15u, 0x04u},\r
- {0x17u, 0x08u},\r
- {0x18u, 0x10u},\r
- {0x19u, 0x01u},\r
- {0x1Au, 0x20u},\r
+ {0x9Du, 0x40u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA0u, 0x05u},\r
+ {0xA2u, 0xA0u},\r
+ {0xA3u, 0x08u},\r
+ {0xA5u, 0x0Cu},\r
+ {0xA6u, 0x11u},\r
+ {0xA8u, 0x81u},\r
+ {0xA9u, 0x80u},\r
+ {0xAFu, 0x0Eu},\r
+ {0xB0u, 0x04u},\r
+ {0xB1u, 0x04u},\r
+ {0xB4u, 0x40u},\r
+ {0xB5u, 0x02u},\r
+ {0xB6u, 0x40u},\r
+ {0xB7u, 0x80u},\r
+ {0xC0u, 0xEFu},\r
+ {0xC2u, 0xADu},\r
+ {0xC4u, 0xF6u},\r
+ {0xCAu, 0xB8u},\r
+ {0xCCu, 0xEEu},\r
+ {0xCEu, 0xF4u},\r
+ {0xD6u, 0x0Eu},\r
+ {0xD8u, 0x0Eu},\r
+ {0xE0u, 0x80u},\r
+ {0xE2u, 0x40u},\r
+ {0xE4u, 0x02u},\r
+ {0xE6u, 0x04u},\r
+ {0xE8u, 0x40u},\r
+ {0xEAu, 0x20u},\r
+ {0xEEu, 0x11u},\r
+ {0x00u, 0x08u},\r
+ {0x02u, 0x10u},\r
+ {0x04u, 0x02u},\r
+ {0x05u, 0x01u},\r
+ {0x06u, 0x01u},\r
+ {0x0Du, 0x06u},\r
+ {0x0Fu, 0x18u},\r
+ {0x12u, 0x10u},\r
+ {0x15u, 0x20u},\r
+ {0x16u, 0x08u},\r
+ {0x18u, 0x01u},\r
+ {0x19u, 0x04u},\r
+ {0x1Au, 0x02u},\r
{0x1Bu, 0x02u},\r
+ {0x1Cu, 0x02u},\r
+ {0x1Du, 0x02u},\r
+ {0x1Eu, 0x01u},\r
+ {0x1Fu, 0x04u},\r
{0x20u, 0x02u},\r
- {0x21u, 0x02u},\r
- {0x23u, 0x3Du},\r
- {0x26u, 0x08u},\r
- {0x27u, 0x3Du},\r
- {0x2Au, 0x04u},\r
- {0x2Du, 0x3Cu},\r
- {0x2Fu, 0x01u},\r
- {0x30u, 0x0Cu},\r
- {0x32u, 0x01u},\r
- {0x33u, 0x03u},\r
- {0x34u, 0x30u},\r
- {0x35u, 0x30u},\r
- {0x36u, 0x02u},\r
- {0x37u, 0x0Cu},\r
+ {0x22u, 0x05u},\r
+ {0x25u, 0x08u},\r
+ {0x27u, 0x10u},\r
+ {0x28u, 0x02u},\r
+ {0x2Au, 0x21u},\r
+ {0x2Du, 0x10u},\r
+ {0x2Fu, 0x08u},\r
+ {0x30u, 0x18u},\r
+ {0x31u, 0x20u},\r
+ {0x32u, 0x04u},\r
+ {0x33u, 0x01u},\r
+ {0x34u, 0x03u},\r
+ {0x36u, 0x20u},\r
+ {0x37u, 0x1Eu},\r
{0x3Au, 0x20u},\r
- {0x3Bu, 0xA8u},\r
{0x3Eu, 0x01u},\r
+ {0x3Fu, 0x40u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x19u},\r
+ {0x5Cu, 0x91u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x08u},\r
- {0x82u, 0x04u},\r
{0x84u, 0x04u},\r
- {0x85u, 0x02u},\r
- {0x86u, 0x09u},\r
- {0x87u, 0x05u},\r
- {0x90u, 0x08u},\r
- {0x92u, 0x16u},\r
- {0x99u, 0x02u},\r
- {0x9Bu, 0x01u},\r
- {0x9Du, 0x01u},\r
- {0x9Fu, 0x02u},\r
- {0xACu, 0x01u},\r
- {0xAEu, 0x02u},\r
- {0xB0u, 0x10u},\r
- {0xB4u, 0x0Cu},\r
- {0xB5u, 0x04u},\r
- {0xB6u, 0x03u},\r
- {0xB7u, 0x03u},\r
+ {0x86u, 0x02u},\r
+ {0x8Du, 0x02u},\r
+ {0x8Fu, 0x04u},\r
+ {0x90u, 0x04u},\r
+ {0x92u, 0x03u},\r
+ {0x94u, 0x04u},\r
+ {0x96u, 0x02u},\r
+ {0x97u, 0x02u},\r
+ {0x98u, 0x02u},\r
+ {0x9Au, 0x04u},\r
+ {0x9Cu, 0x04u},\r
+ {0x9Eu, 0x02u},\r
+ {0x9Fu, 0x04u},\r
+ {0xAFu, 0x01u},\r
+ {0xB2u, 0x01u},\r
+ {0xB4u, 0x06u},\r
+ {0xB5u, 0x01u},\r
+ {0xB7u, 0x06u},\r
{0xBAu, 0x20u},\r
- {0xBBu, 0x80u},\r
- {0xBEu, 0x40u},\r
+ {0xBFu, 0x40u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x99u},\r
+ {0xDCu, 0x11u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x02u},\r
- {0x03u, 0x20u},\r
- {0x05u, 0x54u},\r
+ {0x01u, 0x08u},\r
+ {0x05u, 0x06u},\r
{0x08u, 0x02u},\r
- {0x0Eu, 0x04u},\r
- {0x10u, 0x02u},\r
- {0x15u, 0x12u},\r
- {0x17u, 0x04u},\r
- {0x18u, 0x02u},\r
- {0x19u, 0x82u},\r
- {0x1Bu, 0x60u},\r
- {0x1Cu, 0x80u},\r
- {0x1Du, 0x24u},\r
- {0x1Eu, 0x04u},\r
- {0x1Fu, 0x50u},\r
- {0x22u, 0xA0u},\r
- {0x27u, 0x29u},\r
- {0x2Du, 0x80u},\r
- {0x2Eu, 0x02u},\r
+ {0x0Au, 0x26u},\r
+ {0x0Cu, 0x02u},\r
+ {0x0Eu, 0x29u},\r
+ {0x14u, 0x08u},\r
+ {0x17u, 0x01u},\r
+ {0x1Au, 0x24u},\r
+ {0x1Cu, 0x08u},\r
+ {0x1Du, 0x05u},\r
+ {0x1Eu, 0x09u},\r
+ {0x20u, 0x02u},\r
+ {0x21u, 0x50u},\r
+ {0x23u, 0x03u},\r
+ {0x24u, 0x02u},\r
+ {0x26u, 0x08u},\r
+ {0x27u, 0x80u},\r
+ {0x2Au, 0x40u},\r
+ {0x2Cu, 0x02u},\r
{0x2Fu, 0x10u},\r
- {0x32u, 0xA0u},\r
- {0x36u, 0x08u},\r
- {0x37u, 0x21u},\r
- {0x38u, 0x04u},\r
- {0x3Cu, 0x20u},\r
- {0x3Eu, 0x41u},\r
- {0x3Fu, 0x08u},\r
- {0x45u, 0x40u},\r
- {0x46u, 0x02u},\r
- {0x5Au, 0xA8u},\r
- {0x5Du, 0x20u},\r
- {0x5Fu, 0x40u},\r
- {0x60u, 0x0Au},\r
- {0x62u, 0x04u},\r
- {0x66u, 0xA0u},\r
- {0x68u, 0x02u},\r
- {0x6Cu, 0x20u},\r
- {0x6Fu, 0x0Au},\r
- {0x79u, 0x10u},\r
- {0x7Au, 0x04u},\r
- {0x81u, 0x10u},\r
- {0x83u, 0x04u},\r
- {0x86u, 0x80u},\r
- {0x87u, 0x0Au},\r
- {0x88u, 0x40u},\r
- {0x89u, 0x20u},\r
- {0x8Au, 0x01u},\r
- {0x8Bu, 0x08u},\r
- {0x8Cu, 0x40u},\r
- {0x8Du, 0x01u},\r
- {0x8Eu, 0x10u},\r
- {0x90u, 0x04u},\r
- {0x91u, 0x03u},\r
- {0x92u, 0xC8u},\r
- {0x94u, 0x02u},\r
- {0x97u, 0xA0u},\r
- {0x99u, 0x40u},\r
+ {0x31u, 0x48u},\r
+ {0x36u, 0x14u},\r
+ {0x37u, 0x44u},\r
+ {0x39u, 0x40u},\r
+ {0x3Cu, 0x40u},\r
+ {0x3Eu, 0x04u},\r
+ {0x58u, 0x14u},\r
+ {0x5Au, 0x40u},\r
+ {0x5Du, 0x80u},\r
+ {0x5Fu, 0x10u},\r
+ {0x62u, 0xA4u},\r
+ {0x64u, 0x0Au},\r
+ {0x69u, 0x40u},\r
+ {0x6Cu, 0x28u},\r
+ {0x6Du, 0x04u},\r
+ {0x6Fu, 0x12u},\r
+ {0x81u, 0x01u},\r
+ {0x82u, 0x04u},\r
+ {0x84u, 0x10u},\r
+ {0x87u, 0x02u},\r
+ {0x88u, 0x0Au},\r
+ {0x8Bu, 0x10u},\r
+ {0x92u, 0x02u},\r
+ {0x93u, 0x12u},\r
+ {0x95u, 0x90u},\r
+ {0x96u, 0x20u},\r
+ {0x97u, 0x21u},\r
+ {0x99u, 0x38u},\r
{0x9Au, 0x40u},\r
- {0x9Bu, 0x10u},\r
- {0x9Cu, 0x08u},\r
- {0x9Eu, 0xB4u},\r
- {0xA0u, 0x10u},\r
- {0xA1u, 0x08u},\r
- {0xA2u, 0x04u},\r
- {0xA4u, 0xA0u},\r
- {0xA7u, 0x40u},\r
- {0xAAu, 0x78u},\r
- {0xADu, 0x01u},\r
- {0xAFu, 0x04u},\r
- {0xB1u, 0x01u},\r
- {0xB2u, 0x04u},\r
- {0xB5u, 0x80u},\r
- {0xB6u, 0x50u},\r
- {0xC0u, 0xECu},\r
- {0xC2u, 0x48u},\r
- {0xC4u, 0x71u},\r
- {0xCAu, 0xD0u},\r
- {0xCCu, 0xECu},\r
- {0xCEu, 0xF2u},\r
+ {0x9Bu, 0x40u},\r
+ {0x9Du, 0x02u},\r
+ {0x9Eu, 0x04u},\r
+ {0x9Fu, 0x0Cu},\r
+ {0xA3u, 0x08u},\r
+ {0xA4u, 0x20u},\r
+ {0xA5u, 0x04u},\r
+ {0xA6u, 0xA9u},\r
+ {0xA8u, 0x40u},\r
+ {0xAAu, 0x08u},\r
+ {0xABu, 0x08u},\r
+ {0xACu, 0x04u},\r
+ {0xADu, 0x08u},\r
+ {0xB1u, 0x20u},\r
+ {0xB4u, 0x40u},\r
+ {0xB5u, 0x01u},\r
+ {0xB6u, 0x08u},\r
+ {0xC0u, 0x34u},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0x50u},\r
+ {0xCAu, 0x58u},\r
+ {0xCCu, 0x7Au},\r
+ {0xCEu, 0x58u},\r
{0xD6u, 0x3Eu},\r
{0xD8u, 0x3Eu},\r
- {0xE0u, 0x10u},\r
- {0xE2u, 0x02u},\r
- {0xE6u, 0x90u},\r
- {0xE8u, 0x20u},\r
- {0xECu, 0x80u},\r
- {0xEEu, 0x20u},\r
- {0x01u, 0x40u},\r
- {0x03u, 0x80u},\r
- {0x05u, 0xD3u},\r
- {0x07u, 0x20u},\r
- {0x09u, 0x08u},\r
- {0x0Bu, 0xC3u},\r
- {0x0Du, 0x01u},\r
- {0x0Fu, 0x02u},\r
- {0x15u, 0x14u},\r
- {0x17u, 0xE3u},\r
- {0x1Bu, 0x04u},\r
- {0x21u, 0xC3u},\r
- {0x23u, 0x20u},\r
- {0x25u, 0x01u},\r
- {0x26u, 0x01u},\r
- {0x27u, 0x02u},\r
- {0x29u, 0x04u},\r
- {0x2Bu, 0xE3u},\r
- {0x2Du, 0x40u},\r
- {0x2Fu, 0x80u},\r
- {0x33u, 0x3Cu},\r
- {0x34u, 0x01u},\r
- {0x35u, 0xC0u},\r
- {0x37u, 0x03u},\r
- {0x39u, 0x08u},\r
- {0x3Bu, 0xA0u},\r
+ {0xE0u, 0x24u},\r
+ {0xE4u, 0x80u},\r
+ {0xE6u, 0x22u},\r
+ {0xE8u, 0x32u},\r
+ {0xECu, 0x02u},\r
+ {0xEEu, 0x14u},\r
+ {0x02u, 0x6Fu},\r
+ {0x04u, 0x04u},\r
+ {0x06u, 0x08u},\r
+ {0x08u, 0x6Fu},\r
+ {0x0Cu, 0x20u},\r
+ {0x0Eu, 0x40u},\r
+ {0x12u, 0x6Fu},\r
+ {0x16u, 0x10u},\r
+ {0x1Au, 0x6Fu},\r
+ {0x1Cu, 0x6Fu},\r
+ {0x20u, 0x01u},\r
+ {0x22u, 0x02u},\r
+ {0x24u, 0x04u},\r
+ {0x26u, 0x08u},\r
+ {0x27u, 0x01u},\r
+ {0x28u, 0x20u},\r
+ {0x2Au, 0x40u},\r
+ {0x2Cu, 0x01u},\r
+ {0x2Eu, 0x02u},\r
+ {0x30u, 0x03u},\r
+ {0x31u, 0x01u},\r
+ {0x32u, 0x10u},\r
+ {0x34u, 0x0Cu},\r
+ {0x36u, 0x60u},\r
+ {0x3Au, 0xA2u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x19u},\r
+ {0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0xF0u},\r
- {0x83u, 0x09u},\r
- {0x84u, 0x04u},\r
- {0x86u, 0xF8u},\r
- {0x88u, 0xFAu},\r
- {0x89u, 0x40u},\r
- {0x8Au, 0x05u},\r
- {0x8Bu, 0x80u},\r
- {0x8Du, 0xE0u},\r
- {0x91u, 0x06u},\r
- {0x92u, 0x08u},\r
- {0x93u, 0xF8u},\r
- {0x94u, 0x40u},\r
- {0x95u, 0xC6u},\r
- {0x96u, 0x80u},\r
- {0x97u, 0x19u},\r
- {0x99u, 0x09u},\r
- {0x9Au, 0x07u},\r
- {0x9Bu, 0xF2u},\r
- {0x9Eu, 0xF0u},\r
- {0xA0u, 0x09u},\r
- {0xA2u, 0xF2u},\r
- {0xA3u, 0xFFu},\r
- {0xA4u, 0x40u},\r
- {0xA5u, 0x01u},\r
- {0xA6u, 0x80u},\r
- {0xA8u, 0x10u},\r
- {0xA9u, 0x14u},\r
- {0xAAu, 0x20u},\r
- {0xACu, 0x10u},\r
+ {0x80u, 0x06u},\r
+ {0x81u, 0xC0u},\r
+ {0x82u, 0xF8u},\r
+ {0x84u, 0xC6u},\r
+ {0x85u, 0x10u},\r
+ {0x86u, 0x19u},\r
+ {0x87u, 0xE0u},\r
+ {0x88u, 0x40u},\r
+ {0x8Au, 0x80u},\r
+ {0x8Fu, 0x20u},\r
+ {0x91u, 0x24u},\r
+ {0x92u, 0x09u},\r
+ {0x93u, 0xC8u},\r
+ {0x94u, 0x14u},\r
+ {0x97u, 0xC0u},\r
+ {0x98u, 0x01u},\r
+ {0x99u, 0x40u},\r
+ {0x9Bu, 0x80u},\r
+ {0x9Cu, 0xE0u},\r
+ {0x9Fu, 0x1Du},\r
+ {0xA0u, 0x40u},\r
+ {0xA1u, 0x01u},\r
+ {0xA2u, 0x80u},\r
+ {0xA3u, 0x02u},\r
+ {0xA6u, 0xFFu},\r
+ {0xA7u, 0x02u},\r
+ {0xA8u, 0x09u},\r
+ {0xA9u, 0xE8u},\r
+ {0xAAu, 0xF2u},\r
+ {0xABu, 0x14u},\r
{0xADu, 0x40u},\r
- {0xAEu, 0x20u},\r
{0xAFu, 0x80u},\r
- {0xB2u, 0xC0u},\r
- {0xB3u, 0x3Fu},\r
- {0xB4u, 0x0Fu},\r
+ {0xB1u, 0x3Cu},\r
+ {0xB2u, 0x3Fu},\r
+ {0xB3u, 0x03u},\r
+ {0xB4u, 0xC0u},\r
{0xB5u, 0xC0u},\r
- {0xB6u, 0x30u},\r
- {0xBAu, 0x88u},\r
+ {0xBAu, 0x20u},\r
{0xBBu, 0x20u},\r
+ {0xBFu, 0x04u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDCu, 0x11u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x04u, 0x02u},\r
- {0x06u, 0x18u},\r
- {0x0Cu, 0x81u},\r
- {0x0Eu, 0x18u},\r
- {0x13u, 0x04u},\r
- {0x14u, 0x08u},\r
- {0x15u, 0x40u},\r
- {0x16u, 0x20u},\r
- {0x17u, 0x01u},\r
- {0x1Au, 0x04u},\r
- {0x1Eu, 0x18u},\r
- {0x1Fu, 0x80u},\r
- {0x20u, 0x20u},\r
- {0x21u, 0x48u},\r
- {0x23u, 0x2Au},\r
- {0x25u, 0x10u},\r
- {0x26u, 0x28u},\r
- {0x27u, 0x10u},\r
- {0x29u, 0x10u},\r
- {0x2Au, 0x54u},\r
- {0x2Bu, 0x40u},\r
- {0x2Cu, 0xA0u},\r
+ {0x00u, 0x06u},\r
+ {0x01u, 0x80u},\r
+ {0x03u, 0x08u},\r
+ {0x05u, 0x05u},\r
+ {0x07u, 0x08u},\r
+ {0x08u, 0x10u},\r
+ {0x09u, 0x01u},\r
+ {0x0Au, 0x20u},\r
+ {0x0Bu, 0x01u},\r
+ {0x0Cu, 0x24u},\r
+ {0x0Du, 0x40u},\r
+ {0x0Eu, 0x40u},\r
+ {0x11u, 0x40u},\r
+ {0x12u, 0xA4u},\r
+ {0x14u, 0x10u},\r
+ {0x15u, 0x02u},\r
+ {0x16u, 0x08u},\r
+ {0x17u, 0x04u},\r
+ {0x18u, 0x86u},\r
+ {0x19u, 0x88u},\r
+ {0x1Bu, 0x10u},\r
+ {0x1Cu, 0x08u},\r
+ {0x1Du, 0x04u},\r
+ {0x1Fu, 0x08u},\r
+ {0x22u, 0x01u},\r
+ {0x25u, 0x08u},\r
+ {0x26u, 0x10u},\r
+ {0x27u, 0x40u},\r
+ {0x29u, 0x08u},\r
+ {0x2Du, 0x02u},\r
{0x2Eu, 0x80u},\r
- {0x2Fu, 0x08u},\r
- {0x30u, 0x20u},\r
- {0x31u, 0x08u},\r
- {0x35u, 0x10u},\r
- {0x36u, 0x08u},\r
- {0x37u, 0x01u},\r
- {0x39u, 0x80u},\r
- {0x3Au, 0x09u},\r
- {0x3Bu, 0x20u},\r
- {0x3Du, 0x21u},\r
- {0x3Fu, 0x80u},\r
- {0x42u, 0x08u},\r
- {0x43u, 0x10u},\r
- {0x59u, 0x80u},\r
- {0x5Au, 0x20u},\r
- {0x5Cu, 0x50u},\r
- {0x60u, 0x04u},\r
+ {0x2Fu, 0x18u},\r
+ {0x35u, 0x01u},\r
+ {0x36u, 0x11u},\r
+ {0x37u, 0x44u},\r
+ {0x38u, 0x80u},\r
+ {0x39u, 0x40u},\r
+ {0x3Eu, 0x08u},\r
+ {0x3Fu, 0x41u},\r
+ {0x48u, 0x01u},\r
+ {0x4Au, 0x01u},\r
+ {0x58u, 0x40u},\r
+ {0x5Cu, 0x40u},\r
+ {0x5Du, 0x10u},\r
{0x62u, 0x40u},\r
- {0x65u, 0x40u},\r
- {0x67u, 0x04u},\r
- {0x81u, 0x40u},\r
- {0x82u, 0x01u},\r
- {0x83u, 0x88u},\r
- {0x87u, 0x63u},\r
- {0x88u, 0x01u},\r
- {0x8Au, 0x04u},\r
- {0x8Bu, 0x08u},\r
- {0x8Cu, 0x50u},\r
- {0xC0u, 0x70u},\r
- {0xC2u, 0xF0u},\r
- {0xC4u, 0xF4u},\r
- {0xCAu, 0xFFu},\r
- {0xCCu, 0xE6u},\r
- {0xCEu, 0xBFu},\r
- {0xD6u, 0x3Cu},\r
- {0xD8u, 0x3Cu},\r
- {0xE0u, 0x70u},\r
- {0xE4u, 0x20u},\r
- {0x80u, 0x09u},\r
- {0x81u, 0x01u},\r
- {0x82u, 0x02u},\r
- {0x83u, 0x32u},\r
- {0x84u, 0x22u},\r
- {0x85u, 0x62u},\r
- {0x86u, 0x01u},\r
- {0x87u, 0x08u},\r
- {0x89u, 0x0Du},\r
- {0x8Du, 0x0Du},\r
+ {0x65u, 0x10u},\r
+ {0x66u, 0x90u},\r
+ {0x80u, 0x01u},\r
+ {0x81u, 0x04u},\r
+ {0x83u, 0x10u},\r
+ {0x84u, 0x04u},\r
+ {0x85u, 0x01u},\r
+ {0x86u, 0x90u},\r
+ {0x88u, 0x40u},\r
+ {0x8Au, 0x10u},\r
+ {0x8Bu, 0x50u},\r
+ {0x8Eu, 0x40u},\r
+ {0x8Fu, 0x01u},\r
+ {0xC0u, 0x7Fu},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0x7Fu},\r
+ {0xCAu, 0xF2u},\r
+ {0xCCu, 0xF0u},\r
+ {0xCEu, 0xD0u},\r
+ {0xD6u, 0x38u},\r
+ {0xD8u, 0x38u},\r
+ {0xE0u, 0x60u},\r
+ {0xE4u, 0xC0u},\r
+ {0xE6u, 0x20u},\r
+ {0x8Eu, 0x38u},\r
{0x90u, 0x3Eu},\r
{0x94u, 0x01u},\r
- {0x95u, 0x02u},\r
{0x96u, 0x14u},\r
- {0x97u, 0x54u},\r
- {0x9Bu, 0x10u},\r
- {0x9Du, 0x02u},\r
- {0x9Fu, 0x0Du},\r
- {0xA1u, 0x0Du},\r
- {0xA5u, 0x0Du},\r
- {0xAAu, 0x38u},\r
- {0xADu, 0x0Du},\r
+ {0xA0u, 0x09u},\r
+ {0xA2u, 0x02u},\r
+ {0xA4u, 0x22u},\r
+ {0xA6u, 0x01u},\r
{0xB0u, 0x07u},\r
- {0xB3u, 0x70u},\r
- {0xB4u, 0x38u},\r
- {0xB7u, 0x0Fu},\r
+ {0xB6u, 0x38u},\r
{0xB8u, 0x02u},\r
- {0xBBu, 0x80u},\r
- {0xBEu, 0x10u},\r
- {0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDFu, 0x01u},\r
- {0x01u, 0xA0u},\r
- {0x02u, 0x40u},\r
- {0x04u, 0x05u},\r
- {0x08u, 0x80u},\r
- {0x09u, 0x01u},\r
- {0x0Du, 0x08u},\r
- {0x0Eu, 0x80u},\r
- {0x11u, 0x04u},\r
- {0x13u, 0x40u},\r
- {0x17u, 0x10u},\r
- {0x1Au, 0x04u},\r
- {0x1Bu, 0x05u},\r
- {0x1Eu, 0x80u},\r
- {0x1Fu, 0x20u},\r
- {0x21u, 0x02u},\r
- {0x26u, 0x80u},\r
- {0x27u, 0x20u},\r
- {0x29u, 0x40u},\r
- {0x2Au, 0x20u},\r
- {0x2Bu, 0x80u},\r
- {0x2Cu, 0x20u},\r
- {0x2Fu, 0x82u},\r
- {0x31u, 0x88u},\r
- {0x32u, 0x10u},\r
- {0x33u, 0x02u},\r
- {0x36u, 0x88u},\r
- {0x37u, 0x20u},\r
- {0x38u, 0x69u},\r
- {0x3Cu, 0x85u},\r
- {0x3Eu, 0x10u},\r
- {0x40u, 0x05u},\r
- {0x41u, 0x09u},\r
- {0x49u, 0x06u},\r
- {0x4Au, 0x04u},\r
- {0x52u, 0x25u},\r
- {0x53u, 0x40u},\r
- {0x83u, 0x20u},\r
- {0x86u, 0x24u},\r
- {0x87u, 0x40u},\r
- {0x8Bu, 0x20u},\r
- {0x8Eu, 0x04u},\r
- {0x90u, 0x6Du},\r
- {0x91u, 0x06u},\r
- {0x92u, 0x30u},\r
- {0x93u, 0x40u},\r
- {0x98u, 0x80u},\r
- {0x99u, 0xE0u},\r
- {0x9Au, 0x40u},\r
- {0x9Bu, 0x10u},\r
- {0x9Du, 0x06u},\r
- {0x9Eu, 0x05u},\r
- {0xA0u, 0x60u},\r
- {0xA1u, 0x89u},\r
- {0xA2u, 0x08u},\r
- {0xA3u, 0x82u},\r
- {0xA5u, 0x02u},\r
- {0xA6u, 0x20u},\r
- {0xA7u, 0x05u},\r
- {0xB3u, 0x01u},\r
- {0xC0u, 0x3Bu},\r
- {0xC2u, 0x39u},\r
- {0xC4u, 0x45u},\r
- {0xCAu, 0xDDu},\r
- {0xCCu, 0x7Fu},\r
- {0xCEu, 0xFFu},\r
- {0xD0u, 0x0Fu},\r
- {0xD2u, 0x04u},\r
- {0xE0u, 0x42u},\r
- {0xE2u, 0x80u},\r
- {0x00u, 0x0Fu},\r
- {0x01u, 0x11u},\r
- {0x02u, 0xF0u},\r
- {0x03u, 0x62u},\r
- {0x04u, 0x03u},\r
- {0x05u, 0x58u},\r
- {0x06u, 0x0Cu},\r
- {0x07u, 0x23u},\r
- {0x08u, 0x60u},\r
- {0x09u, 0x40u},\r
- {0x0Au, 0x90u},\r
- {0x0Bu, 0x30u},\r
- {0x0Cu, 0x05u},\r
- {0x0Eu, 0x0Au},\r
- {0x13u, 0x01u},\r
- {0x15u, 0x34u},\r
- {0x17u, 0x43u},\r
- {0x1Bu, 0x0Cu},\r
- {0x1Cu, 0x06u},\r
- {0x1Eu, 0x09u},\r
- {0x20u, 0x30u},\r
- {0x22u, 0xC0u},\r
- {0x23u, 0x82u},\r
- {0x24u, 0x50u},\r
- {0x26u, 0xA0u},\r
- {0x30u, 0xFFu},\r
- {0x33u, 0x0Fu},\r
+ {0xBEu, 0x40u},\r
+ {0xD8u, 0x04u},\r
+ {0xDFu, 0x01u},\r
+ {0x00u, 0x40u},\r
+ {0x01u, 0x05u},\r
+ {0x02u, 0x08u},\r
+ {0x07u, 0x01u},\r
+ {0x0Au, 0x19u},\r
+ {0x0Eu, 0x90u},\r
+ {0x10u, 0x08u},\r
+ {0x12u, 0x01u},\r
+ {0x13u, 0x06u},\r
+ {0x15u, 0x0Au},\r
+ {0x1Au, 0x98u},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Cu, 0x02u},\r
+ {0x1Eu, 0x80u},\r
+ {0x20u, 0xC0u},\r
+ {0x21u, 0x15u},\r
+ {0x22u, 0x0Au},\r
+ {0x23u, 0x04u},\r
+ {0x2Au, 0x02u},\r
+ {0x2Bu, 0x01u},\r
+ {0x30u, 0x22u},\r
+ {0x32u, 0x08u},\r
+ {0x33u, 0x40u},\r
+ {0x38u, 0x40u},\r
+ {0x39u, 0x10u},\r
+ {0x3Au, 0x01u},\r
+ {0x3Bu, 0x04u},\r
+ {0x42u, 0x58u},\r
+ {0x49u, 0x08u},\r
+ {0x4Au, 0x8Au},\r
+ {0x51u, 0x40u},\r
+ {0x52u, 0x51u},\r
+ {0x53u, 0x81u},\r
+ {0x60u, 0x04u},\r
+ {0x68u, 0x2Au},\r
+ {0x69u, 0x15u},\r
+ {0x6Au, 0x22u},\r
+ {0x6Bu, 0x42u},\r
+ {0x72u, 0x03u},\r
+ {0x73u, 0x01u},\r
+ {0x82u, 0x08u},\r
+ {0x84u, 0x01u},\r
+ {0x86u, 0x04u},\r
+ {0x88u, 0x40u},\r
+ {0x8Du, 0x10u},\r
+ {0x8Fu, 0x01u},\r
+ {0x90u, 0x04u},\r
+ {0x92u, 0x44u},\r
+ {0x94u, 0x40u},\r
+ {0x95u, 0xAFu},\r
+ {0x96u, 0xA3u},\r
+ {0x97u, 0x05u},\r
+ {0x9Bu, 0x01u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Du, 0x18u},\r
+ {0x9Eu, 0x52u},\r
+ {0xA4u, 0x42u},\r
+ {0xA6u, 0x88u},\r
+ {0xA7u, 0x81u},\r
+ {0xA9u, 0x80u},\r
+ {0xC0u, 0x8Fu},\r
+ {0xC2u, 0x37u},\r
+ {0xC4u, 0x3Fu},\r
+ {0xCAu, 0x09u},\r
+ {0xCCu, 0x0Fu},\r
+ {0xCEu, 0x0Fu},\r
+ {0xD0u, 0x07u},\r
+ {0xD2u, 0x0Cu},\r
+ {0xD8u, 0x04u},\r
+ {0xEAu, 0x04u},\r
+ {0xEEu, 0x02u},\r
+ {0x01u, 0x34u},\r
+ {0x03u, 0x43u},\r
+ {0x04u, 0x02u},\r
+ {0x05u, 0x40u},\r
+ {0x06u, 0x01u},\r
+ {0x07u, 0x30u},\r
+ {0x0Cu, 0x02u},\r
+ {0x0Du, 0x11u},\r
+ {0x0Eu, 0x01u},\r
+ {0x0Fu, 0x62u},\r
+ {0x13u, 0x0Cu},\r
+ {0x14u, 0x02u},\r
+ {0x15u, 0x58u},\r
+ {0x16u, 0x05u},\r
+ {0x17u, 0x23u},\r
+ {0x18u, 0x01u},\r
+ {0x1Au, 0x02u},\r
+ {0x23u, 0x02u},\r
+ {0x2Bu, 0x01u},\r
+ {0x2Cu, 0x02u},\r
+ {0x2Eu, 0x09u},\r
+ {0x32u, 0x04u},\r
+ {0x34u, 0x03u},\r
{0x35u, 0x70u},\r
- {0x37u, 0x80u},\r
+ {0x36u, 0x08u},\r
+ {0x37u, 0x0Fu},\r
+ {0x3Au, 0x20u},\r
{0x3Bu, 0x20u},\r
- {0x3Eu, 0x01u},\r
- {0x56u, 0x02u},\r
- {0x57u, 0x28u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
+ {0x5Cu, 0x01u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x10u},\r
- {0x81u, 0x16u},\r
- {0x85u, 0x10u},\r
- {0x87u, 0x06u},\r
- {0x88u, 0x47u},\r
- {0x89u, 0x12u},\r
- {0x8Au, 0x18u},\r
- {0x8Bu, 0x04u},\r
- {0x8Cu, 0x01u},\r
- {0x8Du, 0x22u},\r
- {0x8Fu, 0x10u},\r
- {0x90u, 0x04u},\r
- {0x91u, 0x40u},\r
- {0x94u, 0x62u},\r
- {0x95u, 0x29u},\r
- {0x96u, 0x08u},\r
- {0x97u, 0x16u},\r
- {0x99u, 0x31u},\r
- {0x9Bu, 0x0Eu},\r
- {0x9Cu, 0x01u},\r
- {0x9Du, 0x17u},\r
- {0x9Fu, 0x28u},\r
- {0xA0u, 0x01u},\r
- {0xA1u, 0x16u},\r
- {0xA4u, 0x01u},\r
- {0xA5u, 0x04u},\r
- {0xA8u, 0x48u},\r
- {0xA9u, 0x40u},\r
- {0xAAu, 0x21u},\r
- {0xACu, 0x01u},\r
- {0xADu, 0x06u},\r
- {0xAFu, 0x10u},\r
+ {0x81u, 0xC0u},\r
+ {0x82u, 0x01u},\r
+ {0x83u, 0x02u},\r
+ {0x85u, 0xC0u},\r
+ {0x86u, 0x04u},\r
+ {0x87u, 0x04u},\r
+ {0x89u, 0x80u},\r
+ {0x8Cu, 0x02u},\r
+ {0x8Du, 0x1Fu},\r
+ {0x8Eu, 0x04u},\r
+ {0x8Fu, 0x20u},\r
+ {0x91u, 0x90u},\r
+ {0x92u, 0x10u},\r
+ {0x93u, 0x40u},\r
+ {0x94u, 0x09u},\r
+ {0x95u, 0x7Fu},\r
+ {0x97u, 0x80u},\r
+ {0x99u, 0xC0u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Cu, 0x09u},\r
+ {0x9Fu, 0xFFu},\r
+ {0xA0u, 0x09u},\r
+ {0xA1u, 0xC0u},\r
+ {0xA3u, 0x01u},\r
+ {0xA4u, 0x09u},\r
+ {0xAAu, 0x02u},\r
+ {0xABu, 0x60u},\r
+ {0xAEu, 0x09u},\r
+ {0xAFu, 0x9Fu},\r
{0xB0u, 0x08u},\r
- {0xB1u, 0x30u},\r
- {0xB2u, 0x3Fu},\r
- {0xB3u, 0x0Fu},\r
- {0xB4u, 0x40u},\r
- {0xB7u, 0x40u},\r
- {0xB8u, 0x08u},\r
- {0xB9u, 0x88u},\r
- {0xBBu, 0x02u},\r
- {0xBEu, 0x15u},\r
+ {0xB2u, 0x01u},\r
+ {0xB3u, 0xFFu},\r
+ {0xB4u, 0x10u},\r
+ {0xB6u, 0x06u},\r
+ {0xBEu, 0x45u},\r
+ {0xBFu, 0x04u},\r
+ {0xD4u, 0x40u},\r
+ {0xD6u, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x01u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x80u},\r
- {0x01u, 0x12u},\r
- {0x04u, 0x02u},\r
- {0x05u, 0x18u},\r
- {0x06u, 0x02u},\r
- {0x09u, 0x40u},\r
- {0x0Au, 0xA0u},\r
- {0x0Eu, 0x01u},\r
- {0x10u, 0x20u},\r
- {0x11u, 0x01u},\r
- {0x12u, 0x0Au},\r
- {0x16u, 0x90u},\r
+ {0x00u, 0x08u},\r
+ {0x01u, 0x40u},\r
+ {0x02u, 0x80u},\r
+ {0x05u, 0x44u},\r
+ {0x0Au, 0x22u},\r
+ {0x0Bu, 0x80u},\r
+ {0x0Eu, 0x08u},\r
+ {0x0Fu, 0x20u},\r
+ {0x10u, 0x06u},\r
+ {0x11u, 0x04u},\r
+ {0x13u, 0x01u},\r
+ {0x14u, 0x02u},\r
+ {0x18u, 0x10u},\r
+ {0x19u, 0x01u},\r
{0x1Au, 0x40u},\r
- {0x1Bu, 0x28u},\r
- {0x1Eu, 0x80u},\r
- {0x20u, 0x40u},\r
- {0x21u, 0x88u},\r
- {0x22u, 0x4Au},\r
- {0x25u, 0x10u},\r
- {0x27u, 0x12u},\r
- {0x28u, 0x40u},\r
- {0x2Au, 0x04u},\r
- {0x2Bu, 0x0Au},\r
- {0x2Du, 0x02u},\r
- {0x31u, 0x0Au},\r
- {0x32u, 0x90u},\r
- {0x36u, 0x08u},\r
- {0x37u, 0x12u},\r
- {0x38u, 0x68u},\r
- {0x39u, 0x01u},\r
- {0x3Cu, 0x05u},\r
- {0x3Du, 0x20u},\r
- {0x45u, 0x10u},\r
- {0x46u, 0x08u},\r
- {0x4Cu, 0x01u},\r
- {0x4Fu, 0x40u},\r
- {0x58u, 0x40u},\r
- {0x59u, 0x40u},\r
- {0x66u, 0x08u},\r
- {0x6Cu, 0x34u},\r
- {0x6Du, 0x81u},\r
- {0x6Eu, 0x10u},\r
- {0x6Fu, 0x82u},\r
- {0x74u, 0x40u},\r
- {0x75u, 0x40u},\r
- {0x8Du, 0x08u},\r
- {0x90u, 0x07u},\r
- {0x91u, 0x16u},\r
- {0x92u, 0x21u},\r
- {0x94u, 0x68u},\r
- {0x96u, 0x40u},\r
- {0x98u, 0x80u},\r
- {0x99u, 0xB0u},\r
- {0x9Au, 0xD2u},\r
- {0x9Du, 0x44u},\r
- {0x9Eu, 0x05u},\r
- {0xA1u, 0x01u},\r
- {0xA2u, 0x80u},\r
- {0xA6u, 0x68u},\r
- {0xA7u, 0xA6u},\r
- {0xB0u, 0x40u},\r
- {0xB3u, 0x20u},\r
- {0xC0u, 0xFBu},\r
- {0xC2u, 0x8Du},\r
- {0xC4u, 0x3Fu},\r
- {0xCAu, 0x8Fu},\r
- {0xCCu, 0xEFu},\r
- {0xCEu, 0xEFu},\r
- {0xD8u, 0x40u},\r
- {0xE2u, 0x08u},\r
- {0xEAu, 0x02u},\r
- {0xEEu, 0x08u},\r
- {0x38u, 0x80u},\r
- {0x3Eu, 0x40u},\r
- {0x58u, 0x04u},\r
- {0x5Fu, 0x01u},\r
+ {0x1Bu, 0x50u},\r
+ {0x1Du, 0x44u},\r
+ {0x1Eu, 0x08u},\r
{0x1Fu, 0x40u},\r
- {0x87u, 0x40u},\r
- {0x8Eu, 0x04u},\r
- {0x9Du, 0x08u},\r
- {0xA2u, 0x04u},\r
- {0xE2u, 0x40u},\r
- {0xEAu, 0x02u},\r
- {0xEEu, 0x08u},\r
- {0x8Du, 0x08u},\r
- {0x9Du, 0x08u},\r
- {0xE0u, 0x02u},\r
- {0xE8u, 0x80u},\r
- {0x04u, 0x10u},\r
- {0x0Eu, 0x08u},\r
- {0x12u, 0x08u},\r
+ {0x20u, 0x20u},\r
+ {0x24u, 0x04u},\r
+ {0x27u, 0x01u},\r
+ {0x2Au, 0x42u},\r
+ {0x2Bu, 0x04u},\r
+ {0x2Fu, 0x88u},\r
+ {0x30u, 0x02u},\r
+ {0x32u, 0x58u},\r
+ {0x36u, 0x08u},\r
+ {0x37u, 0x01u},\r
+ {0x38u, 0x40u},\r
+ {0x39u, 0x25u},\r
+ {0x3Cu, 0x84u},\r
+ {0x3Fu, 0x02u},\r
+ {0x5Du, 0x80u},\r
+ {0x60u, 0x10u},\r
+ {0x62u, 0x92u},\r
+ {0x64u, 0x02u},\r
+ {0x82u, 0x06u},\r
+ {0x8Fu, 0x40u},\r
+ {0x91u, 0x40u},\r
+ {0x92u, 0x04u},\r
+ {0x95u, 0x8Fu},\r
+ {0x96u, 0x81u},\r
+ {0x97u, 0x04u},\r
+ {0x98u, 0x04u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Du, 0x19u},\r
+ {0x9Eu, 0x40u},\r
+ {0xA0u, 0x04u},\r
+ {0xA3u, 0x0Cu},\r
+ {0xA4u, 0x52u},\r
+ {0xA6u, 0x08u},\r
+ {0xA7u, 0x01u},\r
+ {0xAAu, 0x80u},\r
+ {0xB1u, 0x80u},\r
+ {0xB4u, 0x08u},\r
+ {0xB6u, 0x28u},\r
+ {0xC0u, 0xADu},\r
+ {0xC2u, 0x6Du},\r
+ {0xC4u, 0x8Fu},\r
+ {0xCAu, 0xADu},\r
+ {0xCCu, 0xCFu},\r
+ {0xCEu, 0xDFu},\r
+ {0xD6u, 0x10u},\r
+ {0xD8u, 0x1Fu},\r
+ {0xE4u, 0x04u},\r
+ {0xEEu, 0x04u},\r
+ {0xB8u, 0x08u},\r
+ {0xBEu, 0x04u},\r
+ {0xD8u, 0x04u},\r
+ {0xDFu, 0x01u},\r
+ {0x1Bu, 0x08u},\r
+ {0x80u, 0x20u},\r
+ {0x95u, 0x10u},\r
+ {0x9Cu, 0x20u},\r
+ {0xA2u, 0x01u},\r
+ {0xA8u, 0x81u},\r
+ {0xB0u, 0x01u},\r
+ {0xB1u, 0x08u},\r
+ {0xB2u, 0x40u},\r
+ {0xB4u, 0x80u},\r
+ {0xB6u, 0x02u},\r
+ {0xB7u, 0x40u},\r
+ {0xE4u, 0x40u},\r
+ {0xEAu, 0x10u},\r
+ {0xECu, 0xD0u},\r
+ {0xEEu, 0x01u},\r
+ {0x82u, 0x01u},\r
+ {0x85u, 0x10u},\r
+ {0x95u, 0x10u},\r
+ {0xA2u, 0x01u},\r
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+ {0xE2u, 0x80u},\r
+ {0xE4u, 0x01u},\r
+ {0xE6u, 0x08u},\r
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+ {0x05u, 0x80u},\r
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+ {0x13u, 0x20u},\r
{0x16u, 0x80u},\r
{0x17u, 0x80u},\r
{0x32u, 0x02u},\r
+ {0x35u, 0x01u},\r
{0x36u, 0x80u},\r
- {0x37u, 0x08u},\r
- {0x39u, 0x04u},\r
+ {0x39u, 0x01u},\r
{0x3Au, 0x80u},\r
- {0x3Cu, 0x08u},\r
- {0x3Fu, 0x10u},\r
- {0x42u, 0x08u},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x01u},\r
+ {0x41u, 0x40u},\r
{0x66u, 0x40u},\r
- {0x87u, 0x08u},\r
- {0x89u, 0x04u},\r
- {0x8Cu, 0x10u},\r
- {0x8Eu, 0x06u},\r
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+ {0x88u, 0x80u},\r
+ {0x8Eu, 0x40u},\r
{0xC0u, 0x80u},\r
{0xC2u, 0x80u},\r
{0xC4u, 0xE0u},\r
{0xCEu, 0xF0u},\r
{0xD0u, 0x10u},\r
{0xD6u, 0x80u},\r
- {0xE2u, 0x10u},\r
- {0x33u, 0x11u},\r
- {0x36u, 0x02u},\r
- {0x37u, 0x80u},\r
- {0x39u, 0x80u},\r
- {0x50u, 0x04u},\r
- {0x54u, 0x20u},\r
- {0x63u, 0x40u},\r
- {0x86u, 0x42u},\r
- {0x87u, 0x40u},\r
- {0x9Bu, 0x90u},\r
- {0x9Eu, 0x48u},\r
- {0xA4u, 0x04u},\r
- {0xA6u, 0x80u},\r
- {0xAAu, 0x08u},\r
- {0xABu, 0x10u},\r
- {0xAFu, 0x10u},\r
+ {0x33u, 0x42u},\r
+ {0x37u, 0x84u},\r
+ {0x38u, 0x10u},\r
+ {0x56u, 0x20u},\r
+ {0x58u, 0x10u},\r
+ {0x66u, 0x80u},\r
+ {0x86u, 0x40u},\r
+ {0x8Au, 0x80u},\r
+ {0x8Eu, 0x20u},\r
+ {0x95u, 0x80u},\r
+ {0x97u, 0x01u},\r
+ {0x99u, 0x80u},\r
+ {0x9Bu, 0xC0u},\r
+ {0x9Eu, 0x40u},\r
+ {0xA6u, 0x82u},\r
+ {0xA9u, 0x01u},\r
+ {0xADu, 0x01u},\r
{0xCCu, 0xF0u},\r
{0xCEu, 0x10u},\r
- {0xD4u, 0x60u},\r
- {0xD8u, 0x40u},\r
- {0xE2u, 0x50u},\r
- {0xE6u, 0x40u},\r
- {0xEAu, 0x10u},\r
+ {0xD4u, 0xC0u},\r
+ {0xD6u, 0x80u},\r
+ {0xE2u, 0x10u},\r
+ {0xEAu, 0x30u},\r
{0x12u, 0x80u},\r
- {0x33u, 0x80u},\r
- {0x86u, 0x08u},\r
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+ {0x82u, 0x10u},\r
+ {0x94u, 0x10u},\r
{0x95u, 0x80u},\r
- {0x9Eu, 0x08u},\r
- {0x9Fu, 0x01u},\r
- {0xA4u, 0x04u},\r
+ {0x97u, 0x01u},\r
+ {0x9Fu, 0x04u},\r
{0xA6u, 0x80u},\r
- {0xA8u, 0x04u},\r
- {0xB4u, 0x20u},\r
+ {0xA7u, 0x02u},\r
+ {0xA9u, 0x80u},\r
+ {0xB0u, 0x10u},\r
+ {0xB6u, 0x02u},\r
{0xC4u, 0x10u},\r
{0xCCu, 0x10u},\r
- {0xE6u, 0x40u},\r
- {0xEEu, 0x80u},\r
+ {0xE6u, 0x20u},\r
+ {0xE8u, 0x20u},\r
+ {0x80u, 0x10u},\r
{0x81u, 0x40u},\r
- {0x88u, 0x04u},\r
+ {0x87u, 0x02u},\r
+ {0x94u, 0x10u},\r
{0x95u, 0x80u},\r
- {0x9Fu, 0x01u},\r
- {0xA4u, 0x04u},\r
- {0xA7u, 0x80u},\r
- {0xE2u, 0x80u},\r
+ {0x97u, 0x01u},\r
+ {0xA7u, 0x02u},\r
+ {0xABu, 0x04u},\r
+ {0xE2u, 0x90u},\r
+ {0xE6u, 0x80u},\r
+ {0xEAu, 0x80u},\r
{0x00u, 0x10u},\r
- {0x04u, 0x40u},\r
- {0x09u, 0x20u},\r
- {0x0Eu, 0x02u},\r
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- {0x14u, 0x20u},\r
- {0x62u, 0x08u},\r
- {0x65u, 0x01u},\r
- {0x88u, 0x20u},\r
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+ {0x65u, 0x20u},\r
+ {0x8Bu, 0x80u},\r
{0xC0u, 0x03u},\r
{0xC2u, 0x03u},\r
{0xC4u, 0x0Cu},\r
{0xD8u, 0x03u},\r
{0xE2u, 0x01u},\r
- {0x00u, 0x08u},\r
+ {0x03u, 0x80u},\r
{0x07u, 0x40u},\r
- {0x08u, 0x02u},\r
- {0x0Du, 0x01u},\r
- {0x56u, 0x20u},\r
- {0x5Au, 0x08u},\r
- {0x5Fu, 0x80u},\r
- {0x62u, 0x10u},\r
- {0x84u, 0x08u},\r
- {0x88u, 0x02u},\r
- {0x8Bu, 0x80u},\r
- {0x8Eu, 0x80u},\r
- {0x9Du, 0x01u},\r
- {0xA2u, 0x81u},\r
- {0xB2u, 0x08u},\r
- {0xB4u, 0x50u},\r
- {0xB5u, 0x20u},\r
+ {0x0Bu, 0x80u},\r
+ {0x0Cu, 0x02u},\r
+ {0x57u, 0x08u},\r
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+ {0x64u, 0x20u},\r
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+ {0x83u, 0x40u},\r
+ {0x87u, 0x02u},\r
+ {0x90u, 0x10u},\r
+ {0x91u, 0x08u},\r
+ {0x98u, 0x80u},\r
+ {0x99u, 0x80u},\r
+ {0x9Au, 0x80u},\r
+ {0x9Bu, 0x02u},\r
+ {0xA7u, 0xC0u},\r
+ {0xABu, 0x04u},\r
+ {0xADu, 0x20u},\r
+ {0xAEu, 0x80u},\r
{0xC0u, 0x0Cu},\r
{0xC2u, 0x0Cu},\r
- {0xD4u, 0x02u},\r
- {0xD6u, 0x06u},\r
- {0xD8u, 0x02u},\r
- {0xE2u, 0x06u},\r
- {0xE4u, 0x04u},\r
- {0xEAu, 0x0Au},\r
- {0xECu, 0x01u},\r
- {0xEEu, 0x02u},\r
- {0x53u, 0x40u},\r
- {0x81u, 0x01u},\r
- {0x83u, 0x40u},\r
- {0x86u, 0x10u},\r
- {0x88u, 0x04u},\r
- {0x8Eu, 0x20u},\r
- {0x96u, 0x08u},\r
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+ {0xD8u, 0x01u},\r
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+ {0x82u, 0x04u},\r
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+ {0x88u, 0x80u},\r
+ {0x8Bu, 0x80u},\r
+ {0x91u, 0x08u},\r
+ {0x98u, 0x80u},\r
+ {0x99u, 0x80u},\r
{0x9Bu, 0x40u},\r
- {0x9Du, 0x01u},\r
- {0x9Eu, 0x30u},\r
- {0xA0u, 0x04u},\r
- {0xA2u, 0x01u},\r
- {0xA4u, 0x08u},\r
- {0xB1u, 0x01u},\r
+ {0x9Cu, 0x30u},\r
+ {0xA7u, 0x08u},\r
+ {0xA8u, 0x10u},\r
+ {0xB3u, 0x40u},\r
+ {0xB4u, 0x02u},\r
{0xD4u, 0x04u},\r
+ {0xE0u, 0x01u},\r
{0xE2u, 0x04u},\r
- {0xE4u, 0x02u},\r
- {0xEAu, 0x04u},\r
- {0x09u, 0x08u},\r
- {0x0Bu, 0x01u},\r
- {0x0Cu, 0x08u},\r
- {0x0Fu, 0x02u},\r
- {0x81u, 0x20u},\r
- {0x83u, 0x01u},\r
- {0x8Bu, 0x80u},\r
- {0x96u, 0x08u},\r
- {0xA4u, 0x08u},\r
- {0xAFu, 0x40u},\r
- {0xB6u, 0x01u},\r
- {0xC2u, 0x0Fu},\r
- {0xE4u, 0x04u},\r
- {0xEAu, 0x08u},\r
- {0x67u, 0x80u},\r
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+ {0x80u, 0x80u},\r
+ {0x84u, 0x20u},\r
{0x87u, 0x40u},\r
- {0xAFu, 0x81u},\r
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+ {0x99u, 0x80u},\r
+ {0x9Bu, 0x40u},\r
+ {0x9Cu, 0x20u},\r
+ {0xA5u, 0x02u},\r
+ {0xA6u, 0x04u},\r
+ {0xA7u, 0x08u},\r
+ {0xA9u, 0x02u},\r
+ {0xADu, 0x04u},\r
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+ {0xE0u, 0x08u},\r
+ {0x67u, 0x40u},\r
+ {0x83u, 0x01u},\r
+ {0x97u, 0x01u},\r
{0xD8u, 0x80u},\r
- {0xE2u, 0x10u},\r
- {0xEAu, 0x40u},\r
- {0xEEu, 0x10u},\r
- {0x04u, 0x02u},\r
- {0x52u, 0x02u},\r
- {0x53u, 0x04u},\r
- {0x82u, 0x02u},\r
- {0x8Bu, 0x04u},\r
- {0x8Cu, 0x01u},\r
- {0xC0u, 0x20u},\r
- {0xD4u, 0xA0u},\r
{0xE2u, 0x80u},\r
- {0x96u, 0x08u},\r
- {0x9Bu, 0x80u},\r
- {0x9Du, 0x20u},\r
- {0xADu, 0x08u},\r
- {0xAFu, 0x01u},\r
- {0x01u, 0x20u},\r
- {0x04u, 0x40u},\r
- {0x5Bu, 0x80u},\r
- {0x5Fu, 0x20u},\r
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+ {0x52u, 0x02u},\r
+ {0x57u, 0x20u},\r
+ {0x81u, 0x04u},\r
+ {0x86u, 0x02u},\r
{0x87u, 0x20u},\r
- {0x8Cu, 0x40u},\r
- {0x9Bu, 0x80u},\r
- {0x9Du, 0x20u},\r
- {0xB2u, 0x04u},\r
+ {0xAFu, 0x40u},\r
+ {0xC0u, 0x20u},\r
+ {0xD4u, 0xC0u},\r
+ {0xE2u, 0x40u},\r
+ {0xE4u, 0x80u},\r
+ {0xE6u, 0x10u},\r
+ {0xEEu, 0x40u},\r
+ {0x8Cu, 0x02u},\r
+ {0x99u, 0x80u},\r
+ {0xABu, 0x40u},\r
+ {0xE4u, 0x02u},\r
+ {0x01u, 0x10u},\r
+ {0x06u, 0x02u},\r
+ {0x50u, 0x06u},\r
+ {0x80u, 0x04u},\r
+ {0x86u, 0x02u},\r
+ {0x89u, 0x10u},\r
+ {0xA0u, 0x02u},\r
+ {0xA9u, 0x80u},\r
{0xC0u, 0x03u},\r
- {0xD4u, 0x01u},\r
- {0xD6u, 0x04u},\r
- {0xE2u, 0x02u},\r
- {0xE8u, 0x01u},\r
- {0x10u, 0x01u},\r
- {0x1Au, 0x01u},\r
+ {0xD4u, 0x05u},\r
+ {0xE2u, 0x01u},\r
+ {0x10u, 0x03u},\r
+ {0x11u, 0x01u},\r
+ {0x1Au, 0x03u},\r
+ {0x1Bu, 0x01u},\r
{0x00u, 0xFDu},\r
{0x01u, 0xBFu},\r
{0x02u, 0x2Au},\r
\r
/* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */\r
static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {\r
- 0x02u, 0x1Fu, 0x01u, 0x20u, 0x00u, 0xC0u, 0x00u, 0x08u, 0x00u, 0xC0u, 0x10u, 0x04u, 0x04u, 0x80u, 0x88u, 0x00u, \r
- 0x08u, 0x90u, 0x04u, 0x40u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x00u, 0x7Fu, 0x00u, 0x80u, 0x01u, 0x00u, 0x42u, 0x60u, \r
- 0x00u, 0xC0u, 0x00u, 0x02u, 0x00u, 0x00u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x9Fu, 0x53u, 0xC0u, 0xACu, 0x01u, \r
- 0xC0u, 0xFFu, 0x0Fu, 0x00u, 0x30u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x15u, 0x01u, \r
- 0x32u, 0x01u, 0x40u, 0x00u, 0x06u, 0xBEu, 0xFBu, 0xDCu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, \r
+ 0xD6u, 0x20u, 0x00u, 0x40u, 0xD2u, 0x92u, 0x04u, 0x01u, 0x21u, 0x01u, 0x8Eu, 0xB0u, 0x17u, 0xC5u, 0x28u, 0x0Au, \r
+ 0x00u, 0xB0u, 0x00u, 0x01u, 0x29u, 0x03u, 0x46u, 0xBCu, 0x20u, 0x91u, 0xD0u, 0x20u, 0xD6u, 0xB1u, 0x00u, 0x00u, \r
+ 0xD6u, 0xB1u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0xD0u, 0x00u, 0x06u, 0x00u, 0x04u, 0x46u, 0x00u, 0x39u, \r
+ 0x0Fu, 0x3Cu, 0x0Fu, 0xC4u, 0xF0u, 0x03u, 0x00u, 0x00u, 0x0Au, 0x00u, 0x20u, 0x2Cu, 0x00u, 0x00u, 0x00u, 0x00u, \r
+ 0x36u, 0x05u, 0x40u, 0x00u, 0x02u, 0xDEu, 0xFBu, 0xC0u, 0x2Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, \r
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
\r
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u};\r
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x00u, 0x02u, 0x01u, 0x02u, 0x01u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
.set EXTLED__SLW, CYREG_PRT0_SLW\r
\r
/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1\r
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0\r
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
.set SDCard_BSPIM_TxStsReg__2__POS, 2\r
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08\r
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB04_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB04_ST\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
\r
/* SD_SCK */\r
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK\r
\r
/* SCSI_Out_Ctl */\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Out_DBx */\r
.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG\r
.set scsiTarget_StatusReg__0__POS, 0\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__2__POS, 2\r
.set scsiTarget_StatusReg__3__MASK, 0x08\r
.set scsiTarget_StatusReg__4__MASK, 0x10\r
.set scsiTarget_StatusReg__4__POS, 4\r
.set scsiTarget_StatusReg__MASK, 0x1F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB04_MSK\r
+.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB04_ST\r
\r
/* Debug_Timer_Interrupt */\r
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST\r
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK\r
-.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB02_ST_CTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB02_ST_CTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST\r
\r
/* SCSI_CTL_PHASE */\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
/* SCSI_Parity_Error */\r
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST\r
\r
/* Miscellaneous */\r
.set BCLK__BUS_CLK__HZ, 50000000\r
EXTLED__SLW EQU CYREG_PRT0_SLW\r
\r
/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
\r
/* SD_SCK */\r
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
\r
/* SCSI_Out_Ctl */\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Out_DBx */\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
\r
/* Debug_Timer_Interrupt */\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
\r
/* SCSI_CTL_PHASE */\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
/* SCSI_Parity_Error */\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
\r
/* Miscellaneous */\r
BCLK__BUS_CLK__HZ EQU 50000000\r
EXTLED__SLW EQU CYREG_PRT0_SLW\r
\r
; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
\r
; SD_SCK\r
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
\r
; SCSI_Out_Ctl\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
\r
; SCSI_Out_DBx\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
\r
; Debug_Timer_Interrupt\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
\r
; SCSI_CTL_PHASE\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
; SCSI_Parity_Error\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
\r
; Miscellaneous\r
BCLK__BUS_CLK__HZ EQU 50000000\r
<?xml version="1.0" encoding="utf-8"?>\r
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
- <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Filtered_STATUS_REG" address="0x40006462" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Filtered_MASK_REG" address="0x40006482" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006492" bitWidth="8" desc="" hidden="false">\r
+ <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006465" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x40006485" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="" hidden="false">\r
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
</field>\r
</register>\r
</block>\r
- <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646B" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_MASK_REG" address="0x4000648B" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649B" bitWidth="8" desc="" hidden="false">\r
+ <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
+ <register name="SCSI_Filtered_STATUS_REG" address="0x40006468" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Filtered_MASK_REG" address="0x40006488" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006498" bitWidth="8" desc="" hidden="false">\r
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
</field>\r
</register>\r
</block>\r
- <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647D" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="Clock_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG" hidden="false">\r
+ <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />\r
+ </register>\r
+ <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0" hidden="false">\r
+ <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />\r
+ <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">\r
+ <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />\r
+ <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />\r
+ </field>\r
+ <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />\r
+ <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />\r
+ <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />\r
+ <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">\r
+ <value name="Timer" value="0" desc="CMP and TC are output." />\r
+ <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />\r
+ </field>\r
+ <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />\r
+ </register>\r
+ <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1" hidden="false">\r
+ <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />\r
+ <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">\r
+ <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />\r
+ <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />\r
+ </field>\r
+ <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />\r
+ <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />\r
+ <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />\r
+ <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />\r
+ </register>\r
+ <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2" hidden="false">\r
+ <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">\r
+ <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />\r
+ <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />\r
+ <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />\r
+ <value name="Irq" value="11" desc="Timer runs until IRQ." />\r
+ </field>\r
+ <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />\r
+ <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />\r
+ <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">\r
+ <value name="Equal" value="0" desc="Compare Equal " />\r
+ <value name="Less than" value="1" desc="Compare Less Than " />\r
+ <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />\r
+ <value name="Greater" value="11" desc="Compare Greater Than ." />\r
+ <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />\r
+ </field>\r
+ <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />\r
+ </register>\r
+ <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />\r
+ <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />\r
+ </block>\r
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true" hidden="false">\r
<block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" hidden="false" />\r
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" hidden="false" />\r
</block>\r
- <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
- <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG" hidden="false">\r
- <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." />\r
- </register>\r
- <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0" hidden="false">\r
- <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." />\r
- <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)">\r
- <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />\r
- <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />\r
- </field>\r
- <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." />\r
- <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." />\r
- <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" />\r
- <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.">\r
- <value name="Timer" value="0" desc="CMP and TC are output." />\r
- <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />\r
- </field>\r
- <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" />\r
- </register>\r
- <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1" hidden="false">\r
- <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" />\r
- <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.">\r
- <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />\r
- <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />\r
- </field>\r
- <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." />\r
- <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." />\r
- <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." />\r
- <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." />\r
- </register>\r
- <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2" hidden="false">\r
- <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ">\r
- <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />\r
- <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />\r
- <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />\r
- <value name="Irq" value="11" desc="Timer runs until IRQ." />\r
- </field>\r
- <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." />\r
- <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" />\r
- <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations">\r
- <value name="Equal" value="0" desc="Compare Equal " />\r
- <value name="Less than" value="1" desc="Compare Less Than " />\r
- <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />\r
- <value name="Greater" value="11" desc="Compare Greater Than ." />\r
- <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />\r
- </field>\r
- <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." />\r
- </register>\r
- <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />\r
- <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />\r
- </block>\r
+ <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />\r
</block>\r
- <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
+ <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="not_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<width>32</width>\r
<peripherals>\r
<peripheral>\r
- <name>SCSI_Filtered</name>\r
+ <name>SCSI_Parity_Error</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006462</baseAddress>\r
+ <baseAddress>0x40006465</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
</addressBlock>\r
<registers>\r
<register>\r
- <name>SCSI_Filtered_STATUS_REG</name>\r
+ <name>SCSI_Parity_Error_STATUS_REG</name>\r
<description>No description available</description>\r
<addressOffset>0x0</addressOffset>\r
<size>8</size>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>SCSI_Filtered_MASK_REG</name>\r
+ <name>SCSI_Parity_Error_MASK_REG</name>\r
<description>No description available</description>\r
<addressOffset>0x20</addressOffset>\r
<size>8</size>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>\r
+ <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>\r
<description>No description available</description>\r
<addressOffset>0x30</addressOffset>\r
<size>8</size>\r
</registers>\r
</peripheral>\r
<peripheral>\r
- <name>SCSI_Parity_Error</name>\r
+ <name>SCSI_Filtered</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000646B</baseAddress>\r
+ <baseAddress>0x40006468</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
</addressBlock>\r
<registers>\r
<register>\r
- <name>SCSI_Parity_Error_STATUS_REG</name>\r
+ <name>SCSI_Filtered_STATUS_REG</name>\r
<description>No description available</description>\r
<addressOffset>0x0</addressOffset>\r
<size>8</size>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>SCSI_Parity_Error_MASK_REG</name>\r
+ <name>SCSI_Filtered_MASK_REG</name>\r
<description>No description available</description>\r
<addressOffset>0x20</addressOffset>\r
<size>8</size>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>\r
+ <name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>\r
<description>No description available</description>\r
<addressOffset>0x30</addressOffset>\r
<size>8</size>\r
</registers>\r
</peripheral>\r
<peripheral>\r
- <name>SCSI_CTL_PHASE</name>\r
+ <name>Debug_Timer</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000647C</baseAddress>\r
+ <baseAddress>0x0</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
</addressBlock>\r
<registers>\r
<register>\r
- <name>SCSI_CTL_PHASE_CONTROL_REG</name>\r
- <description>No description available</description>\r
- <addressOffset>0x0</addressOffset>\r
+ <name>Debug_Timer_GLOBAL_ENABLE</name>\r
+ <description>PM.ACT.CFG</description>\r
+ <addressOffset>0x400043A3</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>en_timer</name>\r
+ <description>Enable timer/counters.</description>\r
+ <lsb>0</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
- </registers>\r
- </peripheral>\r
- <peripheral>\r
- <name>USBFS</name>\r
- <description>USBFS</description>\r
- <baseAddress>0x0</baseAddress>\r
- <addressBlock>\r
- <offset>0</offset>\r
- <size>0x0</size>\r
- <usage>registers</usage>\r
- </addressBlock>\r
- <registers>\r
<register>\r
- <name>USBFS_PM_USB_CR0</name>\r
- <description>USB Power Mode Control Register 0</description>\r
- <addressOffset>0x40004394</addressOffset>\r
+ <name>Debug_Timer_CONTROL</name>\r
+ <description>TMRx.CFG0</description>\r
+ <addressOffset>0x40004F00</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>fsusbio_ref_en</name>\r
- <description>No description available</description>\r
+ <name>EN</name>\r
+ <description>Enables timer/comparator.</description>\r
<lsb>0</lsb>\r
<msb>0</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>fsusbio_pd_n</name>\r
- <description>No description available</description>\r
+ <name>MODE</name>\r
+ <description>Mode. (0 = Timer; 1 = Comparator)</description>\r
<lsb>1</lsb>\r
<msb>1</msb>\r
<access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Timer</name>\r
+ <description>Timer mode. CNT/CMP register holds timer count value.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Comparator</name>\r
+ <description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
</field>\r
<field>\r
- <name>fsusbio_pd_pullup_n</name>\r
- <description>No description available</description>\r
+ <name>ONESHOT</name>\r
+ <description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>\r
<lsb>2</lsb>\r
<msb>2</msb>\r
<access>read-write</access>\r
</field>\r
- </fields>\r
- </register>\r
- <register>\r
- <name>USBFS_PM_ACT_CFG</name>\r
- <description>Active Power Mode Configuration Register</description>\r
- <addressOffset>0x400043A5</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_PM_STBY_CFG</name>\r
- <description>Standby Power Mode Configuration Register</description>\r
- <addressOffset>0x400043B5</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_PRT_PS</name>\r
- <description>Port Pin State Register</description>\r
- <addressOffset>0x400051F1</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- <fields>\r
<field>\r
- <name>PinState_DP</name>\r
- <description>No description available</description>\r
- <lsb>6</lsb>\r
- <msb>6</msb>\r
- <access>read-only</access>\r
+ <name>CMP_BUFF</name>\r
+ <description>Buffer compare register. Compare register updates only on timer terminal count.</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
</field>\r
<field>\r
- <name>PinState_DM</name>\r
- <description>No description available</description>\r
- <lsb>7</lsb>\r
- <msb>7</msb>\r
- <access>read-only</access>\r
+ <name>INV</name>\r
+ <description>Invert sense of TIMEREN signal</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
</field>\r
- </fields>\r
- </register>\r
- <register>\r
- <name>USBFS_PRT_DM0</name>\r
- <description>Port Drive Mode Register</description>\r
- <addressOffset>0x400051F2</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- <fields>\r
<field>\r
- <name>DriveMode_DP</name>\r
- <description>No description available</description>\r
- <lsb>6</lsb>\r
- <msb>6</msb>\r
+ <name>DB</name>\r
+ <description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
<access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Timer</name>\r
+ <description>CMP and TC are output.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Deadband</name>\r
+ <description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
</field>\r
<field>\r
- <name>DriveMode_DM</name>\r
- <description>No description available</description>\r
- <lsb>7</lsb>\r
+ <name>DEADBAND_PERIOD</name>\r
+ <description>Deadband Period</description>\r
+ <lsb>6</lsb>\r
<msb>7</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_PRT_DM1</name>\r
- <description>Port Drive Mode Register</description>\r
- <addressOffset>0x400051F3</addressOffset>\r
+ <name>Debug_Timer_CONTROL2</name>\r
+ <description>TMRx.CFG1</description>\r
+ <addressOffset>0x40004F01</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>PullUp_en_DP</name>\r
- <description>No description available</description>\r
- <lsb>6</lsb>\r
- <msb>6</msb>\r
+ <name>IRQ_SEL</name>\r
+ <description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>PullUp_en_DM</name>\r
- <description>No description available</description>\r
- <lsb>7</lsb>\r
- <msb>7</msb>\r
+ <name>FTC</name>\r
+ <description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Disable_FTC</name>\r
+ <description>Disable the single cycle pulse, which signifies the timer is starting.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Enable_FTC</name>\r
+ <description>Enable the single cycle pulse, which signifies the timer is starting.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>DCOR</name>\r
+ <description>Disable Clear on Read (DCOR) of Status Register SR0.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
<access>read-write</access>\r
</field>\r
- </fields>\r
- </register>\r
- <register>\r
- <name>USBFS_PRT_INP_DIS</name>\r
- <description>Input buffer disable override</description>\r
- <addressOffset>0x400051F8</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- <fields>\r
<field>\r
- <name>seinput_dis_dp</name>\r
- <description>No description available</description>\r
- <lsb>6</lsb>\r
+ <name>DBMODE</name>\r
+ <description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>CLK_BUS_EN_SEL</name>\r
+ <description>Digital Global Clock selection.</description>\r
+ <lsb>4</lsb>\r
<msb>6</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>seinput_dis_dm</name>\r
- <description>No description available</description>\r
+ <name>BUS_CLK_SEL</name>\r
+ <description>Bus Clock selection.</description>\r
<lsb>7</lsb>\r
<msb>7</msb>\r
<access>read-write</access>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_EP0_DR0</name>\r
- <description>bmRequestType</description>\r
- <addressOffset>0x40006000</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_EP0_DR1</name>\r
- <description>bRequest</description>\r
- <addressOffset>0x40006001</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_EP0_DR2</name>\r
- <description>wValueLo</description>\r
- <addressOffset>0x40006002</addressOffset>\r
+ <name>Debug_Timer_CONTROL3_</name>\r
+ <description>TMRx.CFG2</description>\r
+ <addressOffset>0x40004F02</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>TMR_CFG</name>\r
+ <description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>\r
+ <lsb>0</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Continuous</name>\r
+ <description>Timer runs while EN bit of CFG0 register is set to '1'.</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Pulsewidth</name>\r
+ <description>Timer runs from positive to negative edge of TIMEREN.</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Period</name>\r
+ <description>Timer runs from positive to positive edge of TIMEREN.</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Irq</name>\r
+ <description>Timer runs until IRQ.</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>COD</name>\r
+ <description>Clear On Disable (COD). Clears or gates outputs to zero.</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>ROD</name>\r
+ <description>Reset On Disable (ROD). Resets internal state of output logic</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>CMP_CFG</name>\r
+ <description>Comparator configurations</description>\r
+ <lsb>4</lsb>\r
+ <msb>6</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>Equal</name>\r
+ <description>Compare Equal </description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Less_than</name>\r
+ <description>Compare Less Than </description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Less_than_or_equal</name>\r
+ <description>Compare Less Than or Equal .</description>\r
+ <value>2</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Greater</name>\r
+ <description>Compare Greater Than .</description>\r
+ <value>3</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>Greater_than_or_equal</name>\r
+ <description>Compare Greater Than or Equal </description>\r
+ <value>4</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>HW_EN</name>\r
+ <description>When set Timer Enable controls counting.</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_EP0_DR3</name>\r
- <description>wValueHi</description>\r
- <addressOffset>0x40006003</addressOffset>\r
- <size>8</size>\r
+ <name>Debug_Timer_PERIOD</name>\r
+ <description>TMRx.PER0 - Assigned Period</description>\r
+ <addressOffset>0x40004F04</addressOffset>\r
+ <size>16</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_EP0_DR4</name>\r
- <description>wIndexLo</description>\r
- <addressOffset>0x40006004</addressOffset>\r
+ <name>Debug_Timer_COUNTER</name>\r
+ <description>TMRx.CNT_CMP0 - Current Down Counter Value</description>\r
+ <addressOffset>0x40004F06</addressOffset>\r
+ <size>16</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
+ <peripheral>\r
+ <name>SCSI_CTL_PHASE</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x4000647C</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x0</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_CTL_PHASE_CONTROL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
+ </registers>\r
+ </peripheral>\r
+ <peripheral>\r
+ <name>USBFS</name>\r
+ <description>USBFS</description>\r
+ <baseAddress>0x0</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x0</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
<register>\r
- <name>USBFS_EP0_DR5</name>\r
- <description>wIndexHi</description>\r
- <addressOffset>0x40006005</addressOffset>\r
+ <name>USBFS_PM_USB_CR0</name>\r
+ <description>USB Power Mode Control Register 0</description>\r
+ <addressOffset>0x40004394</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>fsusbio_ref_en</name>\r
+ <description>No description available</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>fsusbio_pd_n</name>\r
+ <description>No description available</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ <field>\r
+ <name>fsusbio_pd_pullup_n</name>\r
+ <description>No description available</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ </field>\r
+ </fields>\r
</register>\r
<register>\r
- <name>USBFS_EP0_DR6</name>\r
- <description>lengthLo</description>\r
- <addressOffset>0x40006006</addressOffset>\r
+ <name>USBFS_PM_ACT_CFG</name>\r
+ <description>Active Power Mode Configuration Register</description>\r
+ <addressOffset>0x400043A5</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_EP0_DR7</name>\r
- <description>lengthHi</description>\r
- <addressOffset>0x40006007</addressOffset>\r
+ <name>USBFS_PM_STBY_CFG</name>\r
+ <description>Standby Power Mode Configuration Register</description>\r
+ <addressOffset>0x400043B5</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_CR0</name>\r
- <description>USB Control Register 0</description>\r
- <addressOffset>0x40006008</addressOffset>\r
+ <name>USBFS_PRT_PS</name>\r
+ <description>Port Pin State Register</description>\r
+ <addressOffset>0x400051F1</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>device_address</name>\r
+ <name>PinState_DP</name>\r
<description>No description available</description>\r
- <lsb>0</lsb>\r
+ <lsb>6</lsb>\r
<msb>6</msb>\r
<access>read-only</access>\r
</field>\r
<field>\r
- <name>usb_enable</name>\r
+ <name>PinState_DM</name>\r
<description>No description available</description>\r
<lsb>7</lsb>\r
<msb>7</msb>\r
- <access>read-write</access>\r
+ <access>read-only</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_CR1</name>\r
- <description>USB Control Register 1</description>\r
- <addressOffset>0x40006009</addressOffset>\r
+ <name>USBFS_PRT_DM0</name>\r
+ <description>Port Drive Mode Register</description>\r
+ <addressOffset>0x400051F2</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>reg_enable</name>\r
- <description>No description available</description>\r
- <lsb>0</lsb>\r
- <msb>0</msb>\r
- <access>read-write</access>\r
- </field>\r
- <field>\r
- <name>enable_lock</name>\r
- <description>No description available</description>\r
- <lsb>1</lsb>\r
- <msb>1</msb>\r
- <access>read-write</access>\r
- </field>\r
- <field>\r
- <name>bus_activity</name>\r
+ <name>DriveMode_DP</name>\r
<description>No description available</description>\r
- <lsb>2</lsb>\r
- <msb>2</msb>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>trim_offset_msb</name>\r
+ <name>DriveMode_DM</name>\r
<description>No description available</description>\r
- <lsb>3</lsb>\r
- <msb>3</msb>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_SIE_EP1_CR0</name>\r
- <description>The Endpoint1 Control Register</description>\r
- <addressOffset>0x4000600E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_USBIO_CR0</name>\r
- <description>USBIO Control Register 0</description>\r
- <addressOffset>0x40006010</addressOffset>\r
+ <name>USBFS_PRT_DM1</name>\r
+ <description>Port Drive Mode Register</description>\r
+ <addressOffset>0x400051F3</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>rd</name>\r
- <description>No description available</description>\r
- <lsb>0</lsb>\r
- <msb>0</msb>\r
- <access>read-only</access>\r
- </field>\r
- <field>\r
- <name>td</name>\r
- <description>No description available</description>\r
- <lsb>5</lsb>\r
- <msb>5</msb>\r
- <access>read-write</access>\r
- </field>\r
- <field>\r
- <name>tse0</name>\r
+ <name>PullUp_en_DP</name>\r
<description>No description available</description>\r
<lsb>6</lsb>\r
<msb>6</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>ten</name>\r
+ <name>PullUp_en_DM</name>\r
<description>No description available</description>\r
<lsb>7</lsb>\r
<msb>7</msb>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_USBIO_CR1</name>\r
- <description>USBIO Control Register 1</description>\r
- <addressOffset>0x40006012</addressOffset>\r
+ <name>USBFS_PRT_INP_DIS</name>\r
+ <description>Input buffer disable override</description>\r
+ <addressOffset>0x400051F8</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>dmo</name>\r
- <description>No description available</description>\r
- <lsb>0</lsb>\r
- <msb>0</msb>\r
- <access>read-only</access>\r
- </field>\r
- <field>\r
- <name>dpo</name>\r
- <description>No description available</description>\r
- <lsb>1</lsb>\r
- <msb>1</msb>\r
- <access>read-only</access>\r
- </field>\r
- <field>\r
- <name>usbpuen</name>\r
+ <name>seinput_dis_dp</name>\r
<description>No description available</description>\r
- <lsb>2</lsb>\r
- <msb>2</msb>\r
+ <lsb>6</lsb>\r
+ <msb>6</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>iomode</name>\r
+ <name>seinput_dis_dm</name>\r
<description>No description available</description>\r
- <lsb>5</lsb>\r
- <msb>5</msb>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>USBFS_SIE_EP2_CR0</name>\r
- <description>The Endpoint2 Control Register</description>\r
- <addressOffset>0x4000601E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_SIE_EP3_CR0</name>\r
- <description>The Endpoint3 Control Register</description>\r
- <addressOffset>0x4000602E</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- <register>\r
- <name>USBFS_SIE_EP4_CR0</name>\r
- <description>The Endpoint4 Control Register</description>\r
- <addressOffset>0x4000603E</addressOffset>\r
+ <name>USBFS_EP0_DR0</name>\r
+ <description>bmRequestType</description>\r
+ <addressOffset>0x40006000</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_SIE_EP5_CR0</name>\r
- <description>The Endpoint5 Control Register</description>\r
- <addressOffset>0x4000604E</addressOffset>\r
+ <name>USBFS_EP0_DR1</name>\r
+ <description>bRequest</description>\r
+ <addressOffset>0x40006001</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_SIE_EP6_CR0</name>\r
- <description>The Endpoint6 Control Register</description>\r
- <addressOffset>0x4000605E</addressOffset>\r
+ <name>USBFS_EP0_DR2</name>\r
+ <description>wValueLo</description>\r
+ <addressOffset>0x40006002</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_SIE_EP7_CR0</name>\r
- <description>The Endpoint7 Control Register</description>\r
- <addressOffset>0x4000606E</addressOffset>\r
+ <name>USBFS_EP0_DR3</name>\r
+ <description>wValueHi</description>\r
+ <addressOffset>0x40006003</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_SIE_EP8_CR0</name>\r
- <description>The Endpoint8 Control Register</description>\r
- <addressOffset>0x4000607E</addressOffset>\r
+ <name>USBFS_EP0_DR4</name>\r
+ <description>wIndexLo</description>\r
+ <addressOffset>0x40006004</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_BUF_SIZE</name>\r
- <description>Dedicated Endpoint Buffer Size Register</description>\r
- <addressOffset>0x4000608C</addressOffset>\r
+ <name>USBFS_EP0_DR5</name>\r
+ <description>wIndexHi</description>\r
+ <addressOffset>0x40006005</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_EP_ACTIVE</name>\r
- <description>Endpoint Active Indication Register</description>\r
- <addressOffset>0x4000608E</addressOffset>\r
+ <name>USBFS_EP0_DR6</name>\r
+ <description>lengthLo</description>\r
+ <addressOffset>0x40006006</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_EP_TYPE</name>\r
- <description>Endpoint Type (IN/OUT) Indication</description>\r
- <addressOffset>0x4000608F</addressOffset>\r
+ <name>USBFS_EP0_DR7</name>\r
+ <description>lengthHi</description>\r
+ <addressOffset>0x40006007</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>USBFS_USB_CLK_EN</name>\r
- <description>USB Block Clock Enable Register</description>\r
- <addressOffset>0x4000609D</addressOffset>\r
- <size>8</size>\r
- <access>read-write</access>\r
- <resetValue>0</resetValue>\r
- <resetMask>0</resetMask>\r
- </register>\r
- </registers>\r
- </peripheral>\r
- <peripheral>\r
- <name>Debug_Timer</name>\r
- <description>No description available</description>\r
- <baseAddress>0x0</baseAddress>\r
- <addressBlock>\r
- <offset>0</offset>\r
- <size>0x0</size>\r
- <usage>registers</usage>\r
- </addressBlock>\r
- <registers>\r
- <register>\r
- <name>Debug_Timer_GLOBAL_ENABLE</name>\r
- <description>PM.ACT.CFG</description>\r
- <addressOffset>0x400043A3</addressOffset>\r
+ <name>USBFS_CR0</name>\r
+ <description>USB Control Register 0</description>\r
+ <addressOffset>0x40006008</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>en_timer</name>\r
- <description>Enable timer/counters.</description>\r
+ <name>device_address</name>\r
+ <description>No description available</description>\r
<lsb>0</lsb>\r
- <msb>3</msb>\r
+ <msb>6</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>usb_enable</name>\r
+ <description>No description available</description>\r
+ <lsb>7</lsb>\r
+ <msb>7</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>Debug_Timer_CONTROL</name>\r
- <description>TMRx.CFG0</description>\r
- <addressOffset>0x40004F00</addressOffset>\r
+ <name>USBFS_CR1</name>\r
+ <description>USB Control Register 1</description>\r
+ <addressOffset>0x40006009</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>EN</name>\r
- <description>Enables timer/comparator.</description>\r
+ <name>reg_enable</name>\r
+ <description>No description available</description>\r
<lsb>0</lsb>\r
<msb>0</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>MODE</name>\r
- <description>Mode. (0 = Timer; 1 = Comparator)</description>\r
+ <name>enable_lock</name>\r
+ <description>No description available</description>\r
<lsb>1</lsb>\r
<msb>1</msb>\r
<access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>Timer</name>\r
- <description>Timer mode. CNT/CMP register holds timer count value.</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Comparator</name>\r
- <description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
</field>\r
<field>\r
- <name>ONESHOT</name>\r
- <description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>\r
+ <name>bus_activity</name>\r
+ <description>No description available</description>\r
<lsb>2</lsb>\r
<msb>2</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>CMP_BUFF</name>\r
- <description>Buffer compare register. Compare register updates only on timer terminal count.</description>\r
+ <name>trim_offset_msb</name>\r
+ <description>No description available</description>\r
<lsb>3</lsb>\r
<msb>3</msb>\r
<access>read-write</access>\r
</field>\r
- <field>\r
- <name>INV</name>\r
- <description>Invert sense of TIMEREN signal</description>\r
- <lsb>4</lsb>\r
- <msb>4</msb>\r
- <access>read-write</access>\r
- </field>\r
- <field>\r
- <name>DB</name>\r
- <description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>\r
- <lsb>5</lsb>\r
- <msb>5</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>Timer</name>\r
- <description>CMP and TC are output.</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Deadband</name>\r
- <description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>DEADBAND_PERIOD</name>\r
- <description>Deadband Period</description>\r
- <lsb>6</lsb>\r
- <msb>7</msb>\r
- <access>read-write</access>\r
- </field>\r
</fields>\r
</register>\r
<register>\r
- <name>Debug_Timer_CONTROL2</name>\r
- <description>TMRx.CFG1</description>\r
- <addressOffset>0x40004F01</addressOffset>\r
+ <name>USBFS_SIE_EP1_CR0</name>\r
+ <description>The Endpoint1 Control Register</description>\r
+ <addressOffset>0x4000600E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>USBFS_USBIO_CR0</name>\r
+ <description>USBIO Control Register 0</description>\r
+ <addressOffset>0x40006010</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>IRQ_SEL</name>\r
- <description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>\r
+ <name>rd</name>\r
+ <description>No description available</description>\r
<lsb>0</lsb>\r
<msb>0</msb>\r
- <access>read-write</access>\r
- </field>\r
- <field>\r
- <name>FTC</name>\r
- <description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>\r
- <lsb>1</lsb>\r
- <msb>1</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>Disable_FTC</name>\r
- <description>Disable the single cycle pulse, which signifies the timer is starting.</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Enable_FTC</name>\r
- <description>Enable the single cycle pulse, which signifies the timer is starting.</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>DCOR</name>\r
- <description>Disable Clear on Read (DCOR) of Status Register SR0.</description>\r
- <lsb>2</lsb>\r
- <msb>2</msb>\r
- <access>read-write</access>\r
+ <access>read-only</access>\r
</field>\r
<field>\r
- <name>DBMODE</name>\r
- <description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>\r
- <lsb>3</lsb>\r
- <msb>3</msb>\r
+ <name>td</name>\r
+ <description>No description available</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>CLK_BUS_EN_SEL</name>\r
- <description>Digital Global Clock selection.</description>\r
- <lsb>4</lsb>\r
+ <name>tse0</name>\r
+ <description>No description available</description>\r
+ <lsb>6</lsb>\r
<msb>6</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>BUS_CLK_SEL</name>\r
- <description>Bus Clock selection.</description>\r
+ <name>ten</name>\r
+ <description>No description available</description>\r
<lsb>7</lsb>\r
<msb>7</msb>\r
<access>read-write</access>\r
</fields>\r
</register>\r
<register>\r
- <name>Debug_Timer_CONTROL3_</name>\r
- <description>TMRx.CFG2</description>\r
- <addressOffset>0x40004F02</addressOffset>\r
+ <name>USBFS_USBIO_CR1</name>\r
+ <description>USBIO Control Register 1</description>\r
+ <addressOffset>0x40006012</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<fields>\r
<field>\r
- <name>TMR_CFG</name>\r
- <description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>\r
+ <name>dmo</name>\r
+ <description>No description available</description>\r
<lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-only</access>\r
+ </field>\r
+ <field>\r
+ <name>dpo</name>\r
+ <description>No description available</description>\r
+ <lsb>1</lsb>\r
<msb>1</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>Continuous</name>\r
- <description>Timer runs while EN bit of CFG0 register is set to '1'.</description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Pulsewidth</name>\r
- <description>Timer runs from positive to negative edge of TIMEREN.</description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Period</name>\r
- <description>Timer runs from positive to positive edge of TIMEREN.</description>\r
- <value>2</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Irq</name>\r
- <description>Timer runs until IRQ.</description>\r
- <value>3</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
+ <access>read-only</access>\r
</field>\r
<field>\r
- <name>COD</name>\r
- <description>Clear On Disable (COD). Clears or gates outputs to zero.</description>\r
+ <name>usbpuen</name>\r
+ <description>No description available</description>\r
<lsb>2</lsb>\r
<msb>2</msb>\r
<access>read-write</access>\r
</field>\r
<field>\r
- <name>ROD</name>\r
- <description>Reset On Disable (ROD). Resets internal state of output logic</description>\r
- <lsb>3</lsb>\r
- <msb>3</msb>\r
- <access>read-write</access>\r
- </field>\r
- <field>\r
- <name>CMP_CFG</name>\r
- <description>Comparator configurations</description>\r
- <lsb>4</lsb>\r
- <msb>6</msb>\r
- <access>read-write</access>\r
- <enumeratedValues>\r
- <enumeratedValue>\r
- <name>Equal</name>\r
- <description>Compare Equal </description>\r
- <value>0</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Less_than</name>\r
- <description>Compare Less Than </description>\r
- <value>1</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Less_than_or_equal</name>\r
- <description>Compare Less Than or Equal .</description>\r
- <value>2</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Greater</name>\r
- <description>Compare Greater Than .</description>\r
- <value>3</value>\r
- </enumeratedValue>\r
- <enumeratedValue>\r
- <name>Greater_than_or_equal</name>\r
- <description>Compare Greater Than or Equal </description>\r
- <value>4</value>\r
- </enumeratedValue>\r
- </enumeratedValues>\r
- </field>\r
- <field>\r
- <name>HW_EN</name>\r
- <description>When set Timer Enable controls counting.</description>\r
- <lsb>7</lsb>\r
- <msb>7</msb>\r
+ <name>iomode</name>\r
+ <description>No description available</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
<access>read-write</access>\r
</field>\r
</fields>\r
</register>\r
<register>\r
- <name>Debug_Timer_PERIOD</name>\r
- <description>TMRx.PER0 - Assigned Period</description>\r
- <addressOffset>0x40004F04</addressOffset>\r
- <size>16</size>\r
+ <name>USBFS_SIE_EP2_CR0</name>\r
+ <description>The Endpoint2 Control Register</description>\r
+ <addressOffset>0x4000601E</addressOffset>\r
+ <size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
</register>\r
<register>\r
- <name>Debug_Timer_COUNTER</name>\r
- <description>TMRx.CNT_CMP0 - Current Down Counter Value</description>\r
- <addressOffset>0x40004F06</addressOffset>\r
- <size>16</size>\r
+ <name>USBFS_SIE_EP3_CR0</name>\r
+ <description>The Endpoint3 Control Register</description>\r
+ <addressOffset>0x4000602E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>USBFS_SIE_EP4_CR0</name>\r
+ <description>The Endpoint4 Control Register</description>\r
+ <addressOffset>0x4000603E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>USBFS_SIE_EP5_CR0</name>\r
+ <description>The Endpoint5 Control Register</description>\r
+ <addressOffset>0x4000604E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>USBFS_SIE_EP6_CR0</name>\r
+ <description>The Endpoint6 Control Register</description>\r
+ <addressOffset>0x4000605E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>USBFS_SIE_EP7_CR0</name>\r
+ <description>The Endpoint7 Control Register</description>\r
+ <addressOffset>0x4000606E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>USBFS_SIE_EP8_CR0</name>\r
+ <description>The Endpoint8 Control Register</description>\r
+ <addressOffset>0x4000607E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>USBFS_BUF_SIZE</name>\r
+ <description>Dedicated Endpoint Buffer Size Register</description>\r
+ <addressOffset>0x4000608C</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>USBFS_EP_ACTIVE</name>\r
+ <description>Endpoint Active Indication Register</description>\r
+ <addressOffset>0x4000608E</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>USBFS_EP_TYPE</name>\r
+ <description>Endpoint Type (IN/OUT) Indication</description>\r
+ <addressOffset>0x4000608F</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>USBFS_USB_CLK_EN</name>\r
+ <description>USB Block Clock Enable Register</description>\r
+ <addressOffset>0x4000609D</addressOffset>\r
+ <size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<resetMask>0</resetMask>\r
<peripheral>\r
<name>SCSI_Out_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006471</baseAddress>\r
+ <baseAddress>0x40006474</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_Out_Bits</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006472</baseAddress>\r
+ <baseAddress>0x40006473</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
return std::make_pair(value, static_cast<bool>(conv));
}
- void CtrlGetFixedString(wxTextEntry* ctrl, char* dest, size_t len)
- {
- memset(dest, ' ', len);
- std::string str(ctrl->GetValue().ToAscii());
- // Don't use strncpy - we need to avoid NULL's
- memcpy(dest, str.c_str(), std::min(len, str.size()));
- }
-
- bool CtrlIsAscii(wxTextEntry* ctrl)
- {
- return ctrl->GetValue().IsAscii();
- }
-
}
BoardPanel::BoardPanel(wxWindow* parent, const BoardConfig& initialConfig) :
wxPanel(parent),
- myParent(parent)
+ myParent(parent),
+ myDelayValidator(new wxIntegerValidator<uint8_t>)
{
- wxFlexGridSizer *fgs = new wxFlexGridSizer(6, 2, 9, 25);
+ wxFlexGridSizer *fgs = new wxFlexGridSizer(8, 2, 9, 25);
+
+ fgs->Add(new wxStaticText(this, wxID_ANY, _("Startup Delay (seconds)")));
+ myStartDelayCtrl =
+ new wxTextCtrl(
+ this,
+ ID_startDelayCtrl,
+ "0",
+ wxDefaultPosition,
+ wxDefaultSize,
+ 0,
+ *myDelayValidator);
+ myStartDelayCtrl->SetToolTip(_("Extra delay on power on, normally set to 0"));
+ fgs->Add(myStartDelayCtrl);
+
+
+ fgs->Add(new wxStaticText(this, wxID_ANY, _("SCSI Selection Delay (ms, 255 = auto)")));
+ mySelDelayCtrl =
+ new wxTextCtrl(
+ this,
+ ID_selDelayCtrl,
+ "255",
+ wxDefaultPosition,
+ wxDefaultSize,
+ 0,
+ *myDelayValidator);
+ mySelDelayCtrl->SetToolTip(_("Delay before responding to SCSI selection. SCSI1 hosts usually require 1ms delay, however some require no delay"));
+ fgs->Add(mySelDelayCtrl);
fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
myParityCtrl =
(myCacheCtrl->IsChecked() ? CONFIG_ENABLE_CACHE: 0) |
(myDisconnectCtrl->IsChecked() ? CONFIG_ENABLE_DISCONNECT: 0);
+ config.startupDelay = CtrlGetValue<unsigned int>(myStartDelayCtrl).first;
+ config.selectionDelay = CtrlGetValue<unsigned int>(mySelDelayCtrl).first;
return config;
}
myGlitchCtrl->SetValue(config.flags & CONFIG_DISABLE_GLITCH);
myCacheCtrl->SetValue(config.flags & CONFIG_ENABLE_CACHE);
myDisconnectCtrl->SetValue(config.flags & CONFIG_ENABLE_DISCONNECT);
+
+ {
+ std::stringstream conv;
+ conv << static_cast<unsigned int>(config.startupDelay);
+ myStartDelayCtrl->ChangeValue(conv.str());
+ }
+ {
+ std::stringstream conv;
+ conv << static_cast<unsigned int>(config.selectionDelay);
+ mySelDelayCtrl->ChangeValue(conv.str());
+ }
}
ID_scsi2Ctrl,
ID_glitchCtrl,
ID_cacheCtrl,
- ID_disconnectCtrl
+ ID_disconnectCtrl,
+ ID_startDelayCtrl,
+ ID_selDelayCtrl
};
wxWindow* myParent;
wxCheckBox* myGlitchCtrl;
wxCheckBox* myCacheCtrl;
wxCheckBox* myDisconnectCtrl;
+
+ wxIntegerValidator<uint8_t>* myDelayValidator;
+ wxTextCtrl* myStartDelayCtrl;
+ wxTextCtrl* mySelDelayCtrl;
};
} // namespace SCSI2SD
void OnID_ConfigDefaults(wxCommandEvent& event)
{
+ myBoardPanel->setConfig(ConfigUtil::DefaultBoardConfig());
for (size_t i = 0; i < myTargets.size(); ++i)
{
myTargets[i]->setConfig(ConfigUtil::Default(i));
projects / SCSI2SD-V6.git / commitdiff