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diff --git a/InstructionSet.opcode b/InstructionSet.opcode
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+<?xml version="1.0" encoding="UTF-8" ?>\r
+<opcodes>\r
+<!--\r
+       Z80 Core Emulation\r
+       8 bit LD instructions\r
+       Copyright 2010, Michael McMaster <email@michaelmcmaster.name>\r
+-->\r
+\r
+code gen expectations:\r
+masks result in each instruction being unrolled and the mask name being replaced\r
+with an actual register\r
+operand = op8();\r
+operand="UPPERCASE" is 16bit operand. (first 8 bits = low bytes) N = op16()\r
+\r
+<registerMask name="r" bits="3">\r
+       <reg name="A" mask="111">\r
+       <reg name="B" mask="000">\r
+       <reg name="C" mask="001">\r
+       <reg name="D" mask="010">\r
+       <reg name="E" mask="011">\r
+       <reg name="H" mask="100">\r
+       <reg name="L" mask="101">\r
+</registerMask>\r
+\r
+<registerMask name="d" alias="s" bits="2">\r
+       <reg name="BC" mask="00">\r
+       <reg name="DE" mask="01">\r
+       <reg name="HL" mask="10">\r
+       <reg name="SP" mask="11">\r
+</registerMask>\r
+\r
+<registerMask name="q" bits="2">\r
+       <reg name="BC" mask="00">\r
+       <reg name="DE" mask="01">\r
+       <reg name="HL" mask="10">\r
+       <reg name="AF" mask="11">\r
+</registerMask>\r
+\r
+<registerMask name="p" bits="2">\r
+       <reg name="BC" mask="00">\r
+       <reg name="DE" mask="01">\r
+       <reg name="IX" mask="10">\r
+       <reg name="SP" mask="11">\r
+</registerMask>\r
+\r
+<registerMask name="R" bits="2">\r
+       <reg name="BC" mask="00">\r
+       <reg name="DE" mask="01">\r
+       <reg name="IY" mask="10">\r
+       <reg name="SP" mask="11">\r
+</registerMask>\r
+\r
+<instruction name="LD r,r'" clock="4">\r
+<opcode mask="01rr" />\r
+r = r2;\r
+</instruction>\r
+\r
+<instruction name="LD r,n" clock="7">\r
+<opcode mask="00r110" operand="n"/>\r
+r = n;\r
+</instruction>\r
+\r
+<instruction name="LD r,(HL)" clock="7">\r
+<opcode mask="01r110" />\r
+r = m_mem.read8(m_reg.HL);\r
+</instruction>\r
+\r
+<instruction name="LD r,(IX+d)" clock="19">\r
+<opcode prefix="0xDD" mask="01r110" operand="d"/>\r
+r = m_mem.read8(m_reg.IX, d);\r
+</instruction>\r
+\r
+<instruction name="LD r,(IY+d)" clock="19">\r
+<opcode prefix="0xFD" mask="01r110" operand="d"/>\r
+r = m_mem.read8(m_reg.IY, d);\r
+</instruction>\r
+\r
+<instruction name="LD (HL),r" clock="7">\r
+<opcode mask="01110r"/>\r
+m_mem.write8(m_reg.HL, r);\r
+</instruction>\r
+\r
+<instruction name="LD (IX+d),r" clock="19">\r
+<opcode prefix="0xDD" mask="01110r" operand="d"/>\r
+m_mem.write8(m_reg.IX, d, r);\r
+</instruction>\r
+\r
+<instruction name="LD (IY+d),r" clock="19">\r
+<opcode prefix="0xFD" mask="01110r" operand="d"/>\r
+m_mem.write8(m_reg.IY, d, r);\r
+</instruction>\r
+\r
+<instruction name="LD (HL),n" clock="10">\r
+<opcode mask="00110110" operand="n"/>\r
+m_mem.write8(m_reg.HL, n);\r
+</instruction>\r
+\r
+<instruction name="LD (IX+d),r" clock="19">\r
+<opcode prefix="0xDD" mask="00110110" operand="dn"/>\r
+m_mem.write8(m_reg.IX, d, n);\r
+</instruction>\r
+\r
+<instruction name="LD (IY+d),n" clock="19">\r
+<opcode prefix="0xFD" mask="00110110" operand="dn"/>\r
+m_mem.write8(m_reg.IY, d, n);\r
+</instruction>\r
+\r
+<instruction name="LD A,(BC)" clock="7">\r
+<opcode mask="00001010"/>\r
+m_reg.A = m_mem.read8(m_reg.BC);\r
+</instruction>\r
+\r
+<instruction name="LD A,(DE)" clock="7">\r
+<opcode mask="00011010"/>\r
+m_reg.A = m_mem.read8(m_reg.DE);\r
+</instruction>\r
+\r
+<instruction name="LD A,(nn)" clock="13">\r
+<opcode mask="00111010" operand="N"/>\r
+m_reg.A = m_mem.read8(N);\r
+</instruction>\r
+\r
+<instruction name="LD (BC),A" clock="7">\r
+<opcode mask="00000010"/>\r
+m_mem.write8(m_reg.BC, m_reg.A);\r
+</instruction>\r
+\r
+<instruction name="LD (DE),A" clock="7">\r
+<opcode mask="00010010"/>\r
+m_mem.write8(m_reg.DE, m_reg.A);\r
+</instruction>\r
+\r
+<instruction name="LD (nn),A" clock="13">\r
+<opcode mask="00110010" operand="N"/>\r
+m_mem.write8(N, m_reg.A);\r
+</instruction>\r
+\r
+<instruction name="LD A,I" clock="9">\r
+<opcode prefix="0xED" mask="01010111"/>\r
+m_reg.F.set(m_reg.I, *this);\r
+m_reg.A = m_reg.I;\r
+</instruction>\r
+\r
+<instruction name="LD A,R" clock="9">\r
+<opcode prefix="0xED" mask="01011111"/>\r
+m_reg.F.set(m_reg.R, *this);\r
+m_reg.A = m_reg.R;\r
+</instruction>\r
+\r
+<instruction name="LD I,A" clock="9">\r
+<opcode prefix="0xED" mask="01000111"/>\r
+m_reg.I = m_reg.A;\r
+</instruction>\r
+\r
+<instruction name="LD R,A" clock="9">\r
+<opcode prefix="0xED" mask="01001111"/>\r
+m_reg.R = m_reg.A;\r
+</instruction>\r
+\r
+</opcodes>\r