+201601XX 4.6
+ - Fixed bug when using sector size that isn't a multiple of 4
+ (eg. 522 bytes)
+ - Fixed a bug that caused hanging or scsi phase errors on
+ high speed scsi hosts.
+ - Fixed a hang when processing a SCSI RESET in a data phase.
+ - scsi2sd-util: Fixed USB connection problems under Windows 10.
+ - Added option to treat luns as separate devices
+ - Improved boot up time.
+
+
20151105 4.5
- Fix bug in SCSI MODE SENSE that returned the wrong mode type
- Fixes CDROM emulation
\r
#include <string.h>\r
\r
-static const uint16_t FIRMWARE_VERSION = 0x0450;\r
+static const uint16_t FIRMWARE_VERSION = 0x0460;\r
\r
// 1 flash row\r
static const uint8_t DEFAULT_CONFIG[256] =\r
uint8_t flashArray = cmd[257];\r
uint8_t flashRow = cmd[258];\r
\r
- // Be very careful not to overwrite the bootloader or other\r
- // code\r
- if ((flashArray != SCSI_CONFIG_ARRAY) ||\r
- (flashRow < SCSI_CONFIG_BOARD_ROW) ||\r
- (flashRow >= SCSI_CONFIG_3_ROW + SCSI_CONFIG_ROWS))\r
- {\r
- uint8_t response[] = { CONFIG_STATUS_ERR};\r
- hidPacket_send(response, sizeof(response));\r
- }\r
- else\r
- {\r
- CySetTemp();\r
- int status = CyWriteRowData(flashArray, flashRow, cmd + 1);\r
+ CySetTemp();\r
+ int status = CyWriteRowData(flashArray, flashRow, cmd + 1);\r
\r
- uint8_t response[] =\r
- {\r
- status == CYRET_SUCCESS ? CONFIG_STATUS_GOOD : CONFIG_STATUS_ERR\r
- };\r
- hidPacket_send(response, sizeof(response));\r
- }\r
+ uint8_t response[] =\r
+ {\r
+ status == CYRET_SUCCESS ? CONFIG_STATUS_GOOD : CONFIG_STATUS_ERR\r
+ };\r
+ hidPacket_send(response, sizeof(response));\r
}\r
\r
static void\r
\r
ledOff();\r
scsiDev.phase = BUS_FREE;\r
+ scsiDev.selFlag = 0;\r
}\r
\r
static void enter_MessageIn(uint8 message)\r
scsiDev.lun = scsiDev.cdb[1] >> 5;\r
}\r
\r
+ // For Philips P2000C with Xebec S1410 SASI/MFM adapter\r
+ // http://bitsavers.trailing-edge.com/pdf/xebec/104524C_S1410Man_Aug83.pdf\r
+ if ((scsiDev.lun > 0) && (scsiDev.boardCfg.flags & CONFIG_MAP_LUNS_TO_IDS))\r
+ {\r
+ int tgtIndex;\r
+ for (tgtIndex = 0; tgtIndex < MAX_SCSI_TARGETS; ++tgtIndex)\r
+ {\r
+ if (scsiDev.targets[tgtIndex].targetId == scsiDev.lun)\r
+ {\r
+ scsiDev.target = &scsiDev.targets[tgtIndex];\r
+ scsiDev.lun = 0;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+\r
control = scsiDev.cdb[scsiDev.cdbLen - 1];\r
\r
scsiDev.cmdCount++;\r
- TargetConfig* cfg = scsiDev.target->cfg;\r
+ const TargetConfig* cfg = scsiDev.target->cfg;\r
\r
if (unlikely(scsiDev.resetFlag))\r
{\r
scsiDev.phase = BUS_FREE;\r
scsiDev.atnFlag = 0;\r
scsiDev.resetFlag = 0;\r
+ scsiDev.selFlag = 0;\r
scsiDev.lun = -1;\r
scsiDev.compatMode = COMPAT_UNKNOWN;\r
\r
CyDelay(scsiDev.boardCfg.selectionDelay);\r
}\r
\r
- int sel = SCSI_ReadFilt(SCSI_Filt_SEL);\r
+ int selLatchCfg = scsiDev.boardCfg.flags & CONFIG_ENABLE_SEL_LATCH;\r
+ int sel = (selLatchCfg && scsiDev.selFlag) || SCSI_ReadFilt(SCSI_Filt_SEL);\r
+\r
int bsy = SCSI_ReadFilt(SCSI_Filt_BSY);\r
int io = SCSI_ReadPin(SCSI_In_IO);\r
\r
break;\r
}\r
}\r
- sel &= SCSI_ReadFilt(SCSI_Filt_SEL);\r
+ sel &= (selLatchCfg && scsiDev.selFlag) || SCSI_ReadFilt(SCSI_Filt_SEL);\r
bsy |= SCSI_ReadFilt(SCSI_Filt_BSY);\r
io |= SCSI_ReadPin(SCSI_In_IO);\r
if (!bsy && !io && sel &&\r
{\r
scsiDev.phase = BUS_BUSY;\r
}\r
+ \r
+ scsiDev.selFlag = 0;\r
}\r
\r
static void process_MessageOut()\r
// one initiator in the chain. Support this by moving\r
// straight to selection if SEL is asserted.\r
// ie. the initiator won't assert BSY and it's own ID before moving to selection.\r
- else if (SCSI_ReadFilt(SCSI_Filt_SEL))\r
+ else if (SCSI_ReadFilt(SCSI_Filt_SEL) || scsiDev.selFlag)\r
{\r
enter_SelectionPhase();\r
}\r
case BUS_BUSY:\r
// Someone is using the bus. Perhaps they are trying to\r
// select us.\r
- if (SCSI_ReadFilt(SCSI_Filt_SEL))\r
+ if (SCSI_ReadFilt(SCSI_Filt_SEL) || scsiDev.selFlag)\r
{\r
enter_SelectionPhase();\r
}\r
{\r
scsiDev.atnFlag = 0;\r
scsiDev.resetFlag = 1;\r
+ scsiDev.selFlag = 0;\r
scsiDev.phase = BUS_FREE;\r
scsiDev.target = NULL;\r
scsiDev.compatMode = COMPAT_UNKNOWN;\r
// Set to true (1) if the RST flag was set.
volatile int resetFlag;
+
+ // Set to true (1) if the SEL flag was set.
+ volatile int selFlag;
// Set to true (1) if a parity error was observed.
int parityError;
// The SEL signal ISR ensures we wake up from a _WFI() (wait-for-interrupt)\r
// call in the main loop without waiting for our 1ms timer to\r
// expire. This is done to meet the 250us selection abort time.\r
+ \r
+ // selFlag is required for Philips P2000C which releases it after 600ns\r
+ // without waiting for BSY.\r
+ scsiDev.selFlag = 1;\r
}\r
\r
uint8_t\r
}\r
else\r
{\r
- uint32_t alignedCount = count & 0xFFFFFFF8;\r
- scsiReadDMA(data, alignedCount);\r
+ scsiReadDMA(data, count);\r
\r
// Wait for the next DMA interrupt (or the 1ms systick)\r
// It's beneficial to halt the processor to\r
{\r
__WFI();\r
};\r
-\r
- if (count > alignedCount)\r
- {\r
- scsiReadPIO(data + alignedCount, count - alignedCount);\r
- }\r
}\r
}\r
\r
}\r
else\r
{\r
- uint32_t alignedCount = count & 0xFFFFFFF8;\r
- scsiWriteDMA(data, alignedCount);\r
+ scsiWriteDMA(data, count);\r
\r
// Wait for the next DMA interrupt (or the 1ms systick)\r
// It's beneficial to halt the processor to\r
{\r
__WFI();\r
};\r
-\r
- if (count > alignedCount)\r
- {\r
- scsiWritePIO(data + alignedCount, count - alignedCount);\r
- }\r
}\r
}\r
\r
// CyDmaChGetRequest returns 0 for the relevant bit once the\r
// request is completed.\r
trace(trace_spinDMAReset);\r
- while (CyDmaChGetRequest(scsiDmaTxChan) & CY_DMA_CPU_TERM_CHAIN) {}\r
- while (CyDmaChGetRequest(scsiDmaRxChan) & CY_DMA_CPU_TERM_CHAIN) {}\r
+ while (\r
+ (CyDmaChGetRequest(scsiDmaTxChan) & CY_DMA_CPU_TERM_CHAIN) &&\r
+ !scsiTxDMAComplete\r
+ )\r
+ {}\r
+\r
+ while ((\r
+ CyDmaChGetRequest(scsiDmaRxChan) & CY_DMA_CPU_TERM_CHAIN) &&\r
+ !scsiRxDMAComplete\r
+ )\r
+ {}\r
+\r
+ CyDelayUs(1);\r
\r
CyDmaChDisable(scsiDmaTxChan);\r
CyDmaChDisable(scsiDmaRxChan);\r
{\r
scsiDmaRxChan =\r
SCSI_RX_DMA_DmaInitialize(\r
- 4, // Bytes per burst\r
+ 1, // Bytes per burst\r
1, // request per burst\r
HI16(CYDEV_PERIPH_BASE),\r
HI16(CYDEV_SRAM_BASE)\r
\r
scsiDmaTxChan =\r
SCSI_TX_DMA_DmaInitialize(\r
- 4, // Bytes per burst\r
+ 1, // Bytes per burst\r
1, // request per burst\r
HI16(CYDEV_SRAM_BASE),\r
HI16(CYDEV_PERIPH_BASE)\r
\r
void sdCheckPresent()\r
{\r
+ static int firstCheck = 1;\r
// Check if there's an SD card present.\r
if ((scsiDev.phase == BUS_FREE) &&\r
(sdIOState == SD_IDLE) &&\r
{\r
static int firstInit = 1;\r
\r
- // Debounce\r
- CyDelay(250);\r
+ // Debounce, except on startup if the card is present at\r
+ // power on\r
+ if (!firstCheck)\r
+ {\r
+ CyDelay(250);\r
+ }\r
\r
if (sdInit())\r
{\r
}\r
}\r
}\r
+ firstCheck = 0;\r
}\r
\r
#pragma GCC pop_options\r
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__2__POS 2\r
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB08_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB08_ST\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
+#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
\r
/* SD_SCK */\r
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
\r
/* SCSI_Out_Ctl */\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK\r
\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
#define scsiTarget_StatusReg__0__POS 0\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__2__POS 2\r
#define scsiTarget_StatusReg__3__MASK 0x08u\r
#define scsiTarget_StatusReg__4__MASK 0x10u\r
#define scsiTarget_StatusReg__4__POS 4\r
#define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST\r
\r
/* Debug_Timer_Interrupt */\r
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST\r
\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK\r
\r
/* SCSI_Parity_Error */\r
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB09_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB09_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST\r
\r
/* Miscellaneous */\r
#define BCLK__BUS_CLK__HZ 50000000U\r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 42u\r
+#define CY_CFG_BASE_ADDR_COUNT 40u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
0x4000520Bu, /* Base address: 0x40005200 Count: 11 */\r
0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
- 0x4001003Du, /* Base address: 0x40010000 Count: 61 */\r
- 0x40010138u, /* Base address: 0x40010100 Count: 56 */\r
- 0x40010248u, /* Base address: 0x40010200 Count: 72 */\r
- 0x40010356u, /* Base address: 0x40010300 Count: 86 */\r
- 0x40010445u, /* Base address: 0x40010400 Count: 69 */\r
- 0x4001054Au, /* Base address: 0x40010500 Count: 74 */\r
- 0x4001064Eu, /* Base address: 0x40010600 Count: 78 */\r
- 0x4001074Fu, /* Base address: 0x40010700 Count: 79 */\r
- 0x40010856u, /* Base address: 0x40010800 Count: 86 */\r
- 0x40010954u, /* Base address: 0x40010900 Count: 84 */\r
- 0x40010A4Cu, /* Base address: 0x40010A00 Count: 76 */\r
- 0x40010B4Bu, /* Base address: 0x40010B00 Count: 75 */\r
- 0x40010C51u, /* Base address: 0x40010C00 Count: 81 */\r
- 0x40010D56u, /* Base address: 0x40010D00 Count: 86 */\r
- 0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */\r
- 0x40010F42u, /* Base address: 0x40010F00 Count: 66 */\r
- 0x4001145Eu, /* Base address: 0x40011400 Count: 94 */\r
- 0x4001154Au, /* Base address: 0x40011500 Count: 74 */\r
- 0x40011650u, /* Base address: 0x40011600 Count: 80 */\r
- 0x4001174Au, /* Base address: 0x40011700 Count: 74 */\r
- 0x40011804u, /* Base address: 0x40011800 Count: 4 */\r
- 0x40011913u, /* Base address: 0x40011900 Count: 19 */\r
- 0x40011B0Cu, /* Base address: 0x40011B00 Count: 12 */\r
+ 0x40010054u, /* Base address: 0x40010000 Count: 84 */\r
+ 0x40010141u, /* Base address: 0x40010100 Count: 65 */\r
+ 0x40010243u, /* Base address: 0x40010200 Count: 67 */\r
+ 0x40010350u, /* Base address: 0x40010300 Count: 80 */\r
+ 0x40010454u, /* Base address: 0x40010400 Count: 84 */\r
+ 0x40010553u, /* Base address: 0x40010500 Count: 83 */\r
+ 0x40010651u, /* Base address: 0x40010600 Count: 81 */\r
+ 0x40010755u, /* Base address: 0x40010700 Count: 85 */\r
+ 0x40010916u, /* Base address: 0x40010900 Count: 22 */\r
+ 0x40010A56u, /* Base address: 0x40010A00 Count: 86 */\r
+ 0x40010B4Du, /* Base address: 0x40010B00 Count: 77 */\r
+ 0x40010C50u, /* Base address: 0x40010C00 Count: 80 */\r
+ 0x40010D51u, /* Base address: 0x40010D00 Count: 81 */\r
+ 0x40010E4Au, /* Base address: 0x40010E00 Count: 74 */\r
+ 0x40010F3Cu, /* Base address: 0x40010F00 Count: 60 */\r
+ 0x40011421u, /* Base address: 0x40011400 Count: 33 */\r
+ 0x40011551u, /* Base address: 0x40011500 Count: 81 */\r
+ 0x4001165Bu, /* Base address: 0x40011600 Count: 91 */\r
+ 0x40011747u, /* Base address: 0x40011700 Count: 71 */\r
+ 0x40011907u, /* Base address: 0x40011900 Count: 7 */\r
+ 0x40011B05u, /* Base address: 0x40011B00 Count: 5 */\r
0x4001401Bu, /* Base address: 0x40014000 Count: 27 */\r
- 0x4001411Au, /* Base address: 0x40014100 Count: 26 */\r
- 0x40014213u, /* Base address: 0x40014200 Count: 19 */\r
- 0x4001430Au, /* Base address: 0x40014300 Count: 10 */\r
- 0x4001440Eu, /* Base address: 0x40014400 Count: 14 */\r
- 0x4001451Bu, /* Base address: 0x40014500 Count: 27 */\r
- 0x4001460Cu, /* Base address: 0x40014600 Count: 12 */\r
- 0x4001470Fu, /* Base address: 0x40014700 Count: 15 */\r
- 0x40014807u, /* Base address: 0x40014800 Count: 7 */\r
+ 0x4001411Eu, /* Base address: 0x40014100 Count: 30 */\r
+ 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */\r
+ 0x40014310u, /* Base address: 0x40014300 Count: 16 */\r
+ 0x40014412u, /* Base address: 0x40014400 Count: 18 */\r
+ 0x40014516u, /* Base address: 0x40014500 Count: 22 */\r
+ 0x4001460Fu, /* Base address: 0x40014600 Count: 15 */\r
+ 0x4001470Bu, /* Base address: 0x40014700 Count: 11 */\r
+ 0x40014806u, /* Base address: 0x40014800 Count: 6 */\r
0x40014909u, /* Base address: 0x40014900 Count: 9 */\r
0x40014C03u, /* Base address: 0x40014C00 Count: 3 */\r
0x40014D03u, /* Base address: 0x40014D00 Count: 3 */\r
- 0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
+ 0x40015004u, /* Base address: 0x40015000 Count: 4 */\r
0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
\r
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
- {0x0Au, 0x36u},\r
- {0x00u, 0x05u},\r
- {0x01u, 0x13u},\r
- {0x18u, 0x08u},\r
+ {0x0Au, 0x1Bu},\r
+ {0x00u, 0x11u},\r
+ {0x01u, 0x02u},\r
+ {0x18u, 0x04u},\r
{0x1Cu, 0x71u},\r
- {0x20u, 0x50u},\r
- {0x21u, 0x90u},\r
+ {0x20u, 0x38u},\r
+ {0x21u, 0x60u},\r
{0x2Cu, 0x0Eu},\r
{0x30u, 0x0Cu},\r
- {0x31u, 0x09u},\r
+ {0x31u, 0x0Au},\r
{0x34u, 0x80u},\r
{0x7Cu, 0x40u},\r
{0x20u, 0x01u},\r
- {0x87u, 0x0Fu},\r
+ {0x85u, 0x0Fu},\r
{0x00u, 0x20u},\r
- {0x02u, 0x40u},\r
- {0x03u, 0x04u},\r
{0x04u, 0x01u},\r
- {0x05u, 0x08u},\r
- {0x08u, 0x0Au},\r
- {0x09u, 0x09u},\r
- {0x0Au, 0x35u},\r
- {0x0Bu, 0x72u},\r
- {0x0Cu, 0x48u},\r
- {0x0Eu, 0x36u},\r
- {0x10u, 0x07u},\r
- {0x11u, 0x01u},\r
- {0x12u, 0x18u},\r
- {0x13u, 0x66u},\r
- {0x14u, 0x4Fu},\r
- {0x16u, 0x30u},\r
- {0x17u, 0x7Fu},\r
- {0x1Bu, 0x01u},\r
- {0x1Du, 0x62u},\r
- {0x1Eu, 0x02u},\r
- {0x21u, 0x20u},\r
- {0x22u, 0x20u},\r
- {0x23u, 0x40u},\r
- {0x24u, 0x05u},\r
- {0x25u, 0x74u},\r
- {0x27u, 0x09u},\r
- {0x29u, 0x20u},\r
- {0x2Au, 0x27u},\r
- {0x2Bu, 0x40u},\r
- {0x30u, 0x1Fu},\r
- {0x31u, 0x60u},\r
- {0x33u, 0x1Fu},\r
- {0x36u, 0x60u},\r
- {0x3Au, 0x82u},\r
- {0x3Bu, 0x02u},\r
- {0x40u, 0x32u},\r
- {0x41u, 0x04u},\r
- {0x42u, 0x10u},\r
- {0x45u, 0x2Du},\r
- {0x46u, 0xFCu},\r
+ {0x08u, 0x51u},\r
+ {0x0Au, 0x2Cu},\r
+ {0x0Eu, 0x3Fu},\r
+ {0x10u, 0x4Au},\r
+ {0x12u, 0x15u},\r
+ {0x1Cu, 0x4Bu},\r
+ {0x1Eu, 0x34u},\r
+ {0x20u, 0x06u},\r
+ {0x22u, 0x40u},\r
+ {0x26u, 0x10u},\r
+ {0x30u, 0x3Fu},\r
+ {0x32u, 0x40u},\r
+ {0x3Eu, 0x04u},\r
+ {0x40u, 0x34u},\r
+ {0x41u, 0x05u},\r
+ {0x42u, 0x20u},\r
+ {0x45u, 0xCFu},\r
+ {0x46u, 0xD2u},\r
{0x47u, 0x0Eu},\r
{0x48u, 0x1Fu},\r
{0x49u, 0xFFu},\r
{0x4Fu, 0x2Cu},\r
{0x56u, 0x01u},\r
{0x58u, 0x04u},\r
- {0x59u, 0x04u},\r
{0x5Au, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
+ {0x5Cu, 0x01u},\r
{0x5Du, 0x01u},\r
{0x5Fu, 0x01u},\r
{0x60u, 0x08u},\r
{0x68u, 0x40u},\r
{0x69u, 0x40u},\r
{0x6Eu, 0x08u},\r
- {0x02u, 0x04u},\r
- {0x03u, 0x91u},\r
- {0x04u, 0x30u},\r
- {0x0Au, 0x80u},\r
- {0x0Bu, 0x11u},\r
- {0x11u, 0x10u},\r
- {0x12u, 0xA8u},\r
- {0x1Au, 0x80u},\r
- {0x1Bu, 0x80u},\r
- {0x20u, 0x30u},\r
- {0x23u, 0x90u},\r
- {0x28u, 0x48u},\r
- {0x2Au, 0x04u},\r
- {0x2Bu, 0x10u},\r
- {0x32u, 0x88u},\r
- {0x33u, 0x11u},\r
- {0x38u, 0x10u},\r
- {0x3Bu, 0x05u},\r
- {0x40u, 0x10u},\r
- {0x42u, 0x04u},\r
- {0x43u, 0x81u},\r
- {0x4Au, 0x20u},\r
- {0x4Bu, 0x05u},\r
- {0x50u, 0x80u},\r
- {0x53u, 0x28u},\r
- {0x58u, 0x40u},\r
- {0x59u, 0x20u},\r
- {0x5Au, 0x02u},\r
- {0x5Bu, 0x84u},\r
- {0x60u, 0x04u},\r
- {0x61u, 0x49u},\r
- {0x69u, 0x84u},\r
- {0x6Au, 0x20u},\r
- {0x6Bu, 0x40u},\r
- {0x71u, 0x80u},\r
- {0x72u, 0x88u},\r
- {0x73u, 0x20u},\r
- {0x80u, 0x80u},\r
- {0x81u, 0xC0u},\r
- {0x85u, 0x04u},\r
- {0x8Au, 0x08u},\r
- {0x8Eu, 0x10u},\r
- {0x8Fu, 0x22u},\r
- {0xC0u, 0x0Fu},\r
- {0xC2u, 0x0Du},\r
- {0xC4u, 0x0Eu},\r
- {0xCAu, 0x07u},\r
- {0xCCu, 0x0Fu},\r
- {0xCEu, 0x07u},\r
- {0xD0u, 0x0Fu},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x0Fu},\r
- {0xE0u, 0x05u},\r
- {0xE2u, 0x02u},\r
- {0xE4u, 0x03u},\r
- {0xE6u, 0x08u},\r
- {0x00u, 0x96u},\r
- {0x02u, 0x69u},\r
- {0x04u, 0x55u},\r
- {0x05u, 0x33u},\r
- {0x06u, 0xAAu},\r
- {0x07u, 0xCCu},\r
- {0x0Au, 0xFFu},\r
- {0x0Bu, 0xFFu},\r
- {0x0Cu, 0x33u},\r
- {0x0Du, 0x0Fu},\r
- {0x0Eu, 0xCCu},\r
- {0x0Fu, 0xF0u},\r
- {0x13u, 0xFFu},\r
- {0x14u, 0x0Fu},\r
- {0x16u, 0xF0u},\r
- {0x17u, 0xFFu},\r
- {0x18u, 0xFFu},\r
- {0x1Du, 0xFFu},\r
- {0x1Eu, 0xFFu},\r
- {0x25u, 0xFFu},\r
- {0x29u, 0x55u},\r
- {0x2Au, 0xFFu},\r
- {0x2Bu, 0xAAu},\r
- {0x2Cu, 0xFFu},\r
- {0x2Du, 0x69u},\r
- {0x2Fu, 0x96u},\r
- {0x32u, 0xFFu},\r
- {0x37u, 0xFFu},\r
- {0x3Au, 0x08u},\r
- {0x3Bu, 0x80u},\r
- {0x58u, 0x04u},\r
- {0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
- {0x5Fu, 0x01u},\r
- {0x80u, 0xE0u},\r
+ {0x80u, 0xC0u},\r
+ {0x81u, 0x69u},\r
+ {0x82u, 0x18u},\r
+ {0x83u, 0x12u},\r
{0x84u, 0x40u},\r
{0x86u, 0x80u},\r
- {0x89u, 0x44u},\r
- {0x8Au, 0xFFu},\r
- {0x8Bu, 0x88u},\r
- {0x8Cu, 0x06u},\r
- {0x8Eu, 0xF8u},\r
- {0x8Fu, 0x80u},\r
- {0x91u, 0x99u},\r
- {0x93u, 0x22u},\r
- {0x94u, 0x01u},\r
- {0x97u, 0x07u},\r
- {0x98u, 0xC6u},\r
- {0x9Au, 0x19u},\r
- {0x9Bu, 0x70u},\r
- {0x9Cu, 0x40u},\r
- {0x9Eu, 0x80u},\r
- {0x9Fu, 0x08u},\r
- {0xA0u, 0x14u},\r
- {0xA5u, 0xAAu},\r
- {0xA6u, 0x09u},\r
- {0xA7u, 0x55u},\r
- {0xA8u, 0x09u},\r
- {0xAAu, 0xF2u},\r
- {0xB3u, 0x0Fu},\r
- {0xB4u, 0x3Fu},\r
- {0xB5u, 0xF0u},\r
- {0xB6u, 0xC0u},\r
- {0xBAu, 0x80u},\r
- {0xD6u, 0x08u},\r
+ {0x8Cu, 0x25u},\r
+ {0x8Du, 0x20u},\r
+ {0x8Eu, 0xD8u},\r
+ {0x8Fu, 0x40u},\r
+ {0x93u, 0x67u},\r
+ {0x94u, 0x10u},\r
+ {0x95u, 0x03u},\r
+ {0x96u, 0x20u},\r
+ {0x97u, 0x1Cu},\r
+ {0x9Bu, 0x01u},\r
+ {0x9Cu, 0xC4u},\r
+ {0x9Du, 0x64u},\r
+ {0x9Eu, 0x18u},\r
+ {0xA0u, 0x02u},\r
+ {0xA1u, 0x08u},\r
+ {0xA2u, 0xD0u},\r
+ {0xA3u, 0x77u},\r
+ {0xA4u, 0x21u},\r
+ {0xA5u, 0x02u},\r
+ {0xA6u, 0xD8u},\r
+ {0xA9u, 0x0Bu},\r
+ {0xAAu, 0x01u},\r
+ {0xABu, 0x74u},\r
+ {0xACu, 0x40u},\r
+ {0xADu, 0x20u},\r
+ {0xAEu, 0x80u},\r
+ {0xAFu, 0x40u},\r
+ {0xB1u, 0x60u},\r
+ {0xB2u, 0x30u},\r
+ {0xB4u, 0xC0u},\r
+ {0xB5u, 0x1Fu},\r
+ {0xB6u, 0x0Fu},\r
+ {0xB8u, 0x80u},\r
+ {0xBAu, 0x28u},\r
+ {0xBBu, 0x22u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
{0xDCu, 0x11u},\r
- {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x10u},\r
- {0x02u, 0x90u},\r
- {0x03u, 0x01u},\r
- {0x04u, 0x20u},\r
- {0x05u, 0x04u},\r
- {0x06u, 0x40u},\r
- {0x07u, 0x02u},\r
- {0x09u, 0x04u},\r
- {0x0Au, 0x06u},\r
- {0x0Eu, 0x26u},\r
- {0x10u, 0x80u},\r
- {0x12u, 0x20u},\r
- {0x13u, 0x18u},\r
- {0x15u, 0x90u},\r
- {0x1Au, 0x06u},\r
- {0x1Bu, 0x30u},\r
- {0x1Eu, 0x20u},\r
- {0x21u, 0x20u},\r
- {0x22u, 0x04u},\r
- {0x24u, 0x02u},\r
- {0x25u, 0x40u},\r
- {0x2Bu, 0x10u},\r
- {0x2Eu, 0x20u},\r
- {0x2Fu, 0x21u},\r
- {0x31u, 0x20u},\r
- {0x32u, 0x04u},\r
- {0x33u, 0x41u},\r
- {0x36u, 0x89u},\r
- {0x37u, 0x01u},\r
- {0x38u, 0x20u},\r
- {0x3Au, 0x80u},\r
- {0x3Du, 0x80u},\r
- {0x3Fu, 0x18u},\r
- {0x58u, 0x10u},\r
+ {0x03u, 0x59u},\r
+ {0x05u, 0x44u},\r
+ {0x07u, 0x40u},\r
+ {0x0Au, 0x41u},\r
+ {0x0Eu, 0x20u},\r
+ {0x0Fu, 0x02u},\r
+ {0x12u, 0x90u},\r
+ {0x14u, 0x02u},\r
+ {0x15u, 0x08u},\r
+ {0x17u, 0x11u},\r
+ {0x1Au, 0xD0u},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Du, 0x40u},\r
+ {0x1Eu, 0x27u},\r
+ {0x1Fu, 0x40u},\r
+ {0x24u, 0x40u},\r
+ {0x27u, 0x88u},\r
+ {0x2Du, 0x08u},\r
+ {0x2Fu, 0x69u},\r
+ {0x36u, 0x20u},\r
+ {0x37u, 0x49u},\r
+ {0x3Cu, 0x40u},\r
+ {0x3Fu, 0x02u},\r
+ {0x40u, 0x08u},\r
+ {0x41u, 0x04u},\r
+ {0x42u, 0x40u},\r
+ {0x43u, 0x08u},\r
+ {0x48u, 0x10u},\r
+ {0x4Au, 0x81u},\r
+ {0x51u, 0x80u},\r
+ {0x52u, 0x18u},\r
+ {0x53u, 0x20u},\r
+ {0x59u, 0x06u},\r
+ {0x5Au, 0x24u},\r
{0x5Bu, 0x80u},\r
- {0x5Cu, 0x50u},\r
- {0x5Du, 0x09u},\r
- {0x60u, 0x08u},\r
- {0x62u, 0x40u},\r
- {0x63u, 0x08u},\r
- {0x65u, 0x80u},\r
- {0x81u, 0x08u},\r
- {0x82u, 0x40u},\r
- {0x83u, 0x80u},\r
- {0x85u, 0x20u},\r
- {0x87u, 0x08u},\r
- {0x89u, 0x20u},\r
- {0x8Bu, 0x80u},\r
- {0x8Cu, 0x40u},\r
- {0x8Eu, 0x04u},\r
- {0x90u, 0x20u},\r
- {0x91u, 0x10u},\r
- {0x93u, 0x10u},\r
- {0x94u, 0x04u},\r
- {0x96u, 0x06u},\r
- {0x98u, 0x04u},\r
- {0x9Au, 0x80u},\r
- {0x9Bu, 0x42u},\r
- {0x9Cu, 0x08u},\r
- {0x9Du, 0x61u},\r
- {0x9Fu, 0x15u},\r
- {0xA0u, 0x80u},\r
- {0xA2u, 0x28u},\r
- {0xA3u, 0x08u},\r
- {0xA5u, 0x08u},\r
- {0xA6u, 0x80u},\r
- {0xA7u, 0x10u},\r
- {0xAAu, 0x40u},\r
- {0xACu, 0x10u},\r
- {0xAEu, 0x04u},\r
- {0xB0u, 0x04u},\r
- {0xB3u, 0x20u},\r
- {0xB6u, 0x28u},\r
- {0xC0u, 0xFFu},\r
- {0xC2u, 0xE7u},\r
- {0xC4u, 0xCEu},\r
- {0xCAu, 0x72u},\r
- {0xCCu, 0xDFu},\r
- {0xCEu, 0x7Cu},\r
- {0xD6u, 0xFCu},\r
- {0xD8u, 0x1Cu},\r
- {0xE0u, 0x08u},\r
- {0xE6u, 0x03u},\r
- {0xE8u, 0x0Au},\r
- {0xEAu, 0x10u},\r
- {0xEEu, 0x06u},\r
- {0x01u, 0x02u},\r
- {0x02u, 0x02u},\r
- {0x03u, 0x01u},\r
- {0x05u, 0x01u},\r
- {0x07u, 0x06u},\r
+ {0x61u, 0x10u},\r
+ {0x63u, 0x91u},\r
+ {0x68u, 0x24u},\r
+ {0x69u, 0x40u},\r
+ {0x6Au, 0x02u},\r
+ {0x70u, 0x80u},\r
+ {0x72u, 0xA8u},\r
+ {0x78u, 0x08u},\r
+ {0x7Au, 0x10u},\r
+ {0x82u, 0x50u},\r
+ {0x83u, 0x08u},\r
+ {0x86u, 0x01u},\r
+ {0x88u, 0x14u},\r
+ {0x8Du, 0x40u},\r
+ {0x8Eu, 0x08u},\r
+ {0x8Fu, 0x08u},\r
+ {0xC0u, 0xBFu},\r
+ {0xC2u, 0xA9u},\r
+ {0xC4u, 0xFCu},\r
+ {0xCAu, 0xF0u},\r
+ {0xCCu, 0xF0u},\r
+ {0xCEu, 0x90u},\r
+ {0xD0u, 0x07u},\r
+ {0xD2u, 0x08u},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x0Fu},\r
+ {0xE0u, 0x05u},\r
+ {0xE2u, 0x08u},\r
+ {0xE4u, 0x03u},\r
+ {0xE6u, 0xC0u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Fu, 0x01u},\r
+ {0x10u, 0x0Au},\r
{0x11u, 0x04u},\r
+ {0x12u, 0x05u},\r
{0x13u, 0x08u},\r
- {0x17u, 0x10u},\r
- {0x1Eu, 0x01u},\r
- {0x21u, 0x02u},\r
- {0x23u, 0x01u},\r
- {0x29u, 0x02u},\r
- {0x2Bu, 0x01u},\r
- {0x2Du, 0x02u},\r
- {0x2Fu, 0x29u},\r
- {0x30u, 0x01u},\r
- {0x31u, 0x20u},\r
+ {0x15u, 0x02u},\r
+ {0x16u, 0x07u},\r
+ {0x17u, 0x11u},\r
+ {0x19u, 0x01u},\r
+ {0x1Bu, 0x06u},\r
+ {0x1Cu, 0x09u},\r
+ {0x1Du, 0x02u},\r
+ {0x1Eu, 0x02u},\r
+ {0x1Fu, 0x09u},\r
+ {0x22u, 0x08u},\r
+ {0x24u, 0x04u},\r
+ {0x25u, 0x02u},\r
+ {0x26u, 0x08u},\r
+ {0x27u, 0x21u},\r
+ {0x31u, 0x0Cu},\r
+ {0x32u, 0x0Fu},\r
{0x33u, 0x03u},\r
- {0x34u, 0x02u},\r
- {0x35u, 0x10u},\r
- {0x37u, 0x0Cu},\r
+ {0x35u, 0x20u},\r
+ {0x37u, 0x10u},\r
{0x3Bu, 0x08u},\r
- {0x3Fu, 0x40u},\r
+ {0x3Fu, 0x01u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x0Du},\r
- {0x85u, 0x02u},\r
- {0x87u, 0x54u},\r
- {0x8Bu, 0x10u},\r
- {0x8Cu, 0x02u},\r
- {0x8Du, 0x02u},\r
- {0x8Eu, 0x01u},\r
- {0x8Fu, 0x0Du},\r
- {0x94u, 0x02u},\r
- {0x95u, 0x62u},\r
- {0x96u, 0x09u},\r
- {0x97u, 0x08u},\r
- {0x98u, 0x01u},\r
- {0x99u, 0x01u},\r
- {0x9Au, 0x02u},\r
- {0x9Bu, 0x32u},\r
- {0x9Cu, 0x02u},\r
- {0x9Eu, 0x05u},\r
- {0xA1u, 0x0Du},\r
- {0xA5u, 0x0Du},\r
- {0xA8u, 0x02u},\r
- {0xA9u, 0x0Du},\r
- {0xAAu, 0x11u},\r
- {0xADu, 0x0Du},\r
- {0xB0u, 0x04u},\r
- {0xB2u, 0x10u},\r
+ {0x83u, 0x70u},\r
+ {0x86u, 0x01u},\r
+ {0x87u, 0x07u},\r
+ {0x88u, 0x40u},\r
+ {0x8Bu, 0x80u},\r
+ {0x8Eu, 0x10u},\r
+ {0x95u, 0x99u},\r
+ {0x96u, 0x04u},\r
+ {0x97u, 0x22u},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Du, 0xAAu},\r
+ {0x9Eu, 0x02u},\r
+ {0x9Fu, 0x55u},\r
+ {0xA6u, 0x20u},\r
+ {0xA9u, 0x44u},\r
+ {0xAAu, 0x08u},\r
+ {0xABu, 0x88u},\r
+ {0xACu, 0x15u},\r
+ {0xAEu, 0x2Au},\r
+ {0xB0u, 0x40u},\r
+ {0xB1u, 0xF0u},\r
+ {0xB2u, 0x30u},\r
+ {0xB3u, 0x0Fu},\r
{0xB4u, 0x03u},\r
- {0xB5u, 0x70u},\r
- {0xB6u, 0x08u},\r
- {0xB7u, 0x0Fu},\r
- {0xBAu, 0x20u},\r
- {0xBBu, 0x80u},\r
+ {0xB6u, 0x0Cu},\r
+ {0xBEu, 0x54u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x01u},\r
+ {0xDCu, 0x19u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x06u},\r
- {0x03u, 0x20u},\r
- {0x04u, 0x40u},\r
- {0x0Au, 0x02u},\r
- {0x0Eu, 0x1Au},\r
- {0x14u, 0x08u},\r
- {0x19u, 0x22u},\r
- {0x1Cu, 0x40u},\r
- {0x1Eu, 0x1Au},\r
- {0x20u, 0x01u},\r
- {0x21u, 0x45u},\r
- {0x22u, 0x91u},\r
- {0x25u, 0x50u},\r
- {0x28u, 0x02u},\r
- {0x29u, 0x22u},\r
- {0x2Cu, 0xA8u},\r
- {0x2Du, 0x40u},\r
- {0x30u, 0x02u},\r
- {0x32u, 0x08u},\r
- {0x36u, 0x20u},\r
- {0x37u, 0x08u},\r
+ {0x00u, 0x24u},\r
+ {0x02u, 0x02u},\r
+ {0x08u, 0x80u},\r
+ {0x0Au, 0x10u},\r
+ {0x0Eu, 0x62u},\r
+ {0x0Fu, 0x20u},\r
+ {0x10u, 0x06u},\r
+ {0x12u, 0x20u},\r
+ {0x14u, 0x10u},\r
+ {0x16u, 0x80u},\r
+ {0x18u, 0x20u},\r
+ {0x19u, 0x80u},\r
+ {0x1Bu, 0x22u},\r
+ {0x1Eu, 0x30u},\r
+ {0x21u, 0x05u},\r
+ {0x22u, 0x02u},\r
+ {0x24u, 0x80u},\r
+ {0x25u, 0x41u},\r
+ {0x27u, 0x68u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Fu, 0x10u},\r
+ {0x30u, 0x20u},\r
+ {0x31u, 0x04u},\r
+ {0x32u, 0x40u},\r
+ {0x36u, 0x80u},\r
+ {0x37u, 0x2Au},\r
+ {0x38u, 0x04u},\r
{0x39u, 0x0Au},\r
- {0x3Cu, 0x08u},\r
- {0x3Du, 0xA0u},\r
- {0x3Eu, 0x02u},\r
- {0x58u, 0x10u},\r
- {0x5Au, 0x84u},\r
- {0x5Eu, 0x40u},\r
- {0x5Fu, 0x20u},\r
- {0x60u, 0x02u},\r
- {0x61u, 0x24u},\r
- {0x62u, 0x04u},\r
- {0x64u, 0x08u},\r
- {0x67u, 0x02u},\r
- {0x68u, 0x02u},\r
- {0x6Du, 0x08u},\r
- {0x6Fu, 0x1Au},\r
- {0x83u, 0x0Au},\r
- {0x84u, 0x10u},\r
- {0x85u, 0x08u},\r
- {0x86u, 0x04u},\r
- {0x8Bu, 0x20u},\r
- {0x8Du, 0x10u},\r
- {0x90u, 0x22u},\r
- {0x92u, 0x80u},\r
- {0x94u, 0x14u},\r
- {0x95u, 0x89u},\r
- {0x97u, 0x02u},\r
- {0x98u, 0x04u},\r
- {0x9Du, 0x45u},\r
- {0x9Eu, 0x30u},\r
- {0x9Fu, 0x15u},\r
- {0xA2u, 0x10u},\r
- {0xA3u, 0x20u},\r
- {0xA5u, 0x0Cu},\r
- {0xA6u, 0x84u},\r
- {0xA7u, 0x80u},\r
- {0xABu, 0x18u},\r
- {0xACu, 0x10u},\r
- {0xAEu, 0x04u},\r
- {0xB1u, 0x84u},\r
- {0xB3u, 0x01u},\r
- {0xC0u, 0x88u},\r
- {0xC2u, 0xE1u},\r
- {0xC4u, 0x40u},\r
- {0xCAu, 0xFDu},\r
- {0xCCu, 0x63u},\r
- {0xCEu, 0xF3u},\r
+ {0x3Au, 0x2Au},\r
+ {0x3Du, 0x80u},\r
+ {0x58u, 0x60u},\r
+ {0x5Au, 0x04u},\r
+ {0x5Du, 0x20u},\r
+ {0x5Fu, 0x40u},\r
+ {0x60u, 0x0Au},\r
+ {0x62u, 0x08u},\r
+ {0x67u, 0x0Au},\r
+ {0x6Bu, 0x02u},\r
+ {0x6Cu, 0x04u},\r
+ {0x6Du, 0x40u},\r
+ {0x6Fu, 0x10u},\r
+ {0x80u, 0x04u},\r
+ {0x81u, 0x40u},\r
+ {0x84u, 0xA0u},\r
+ {0x88u, 0x18u},\r
+ {0x8Bu, 0x0Au},\r
+ {0x8Du, 0x0Cu},\r
+ {0x8Eu, 0x01u},\r
+ {0x8Fu, 0x30u},\r
+ {0x92u, 0xC0u},\r
+ {0x93u, 0x40u},\r
+ {0x96u, 0x20u},\r
+ {0x97u, 0x13u},\r
+ {0x99u, 0x20u},\r
+ {0x9Au, 0xB0u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Du, 0x12u},\r
+ {0x9Fu, 0x50u},\r
+ {0xA0u, 0xA0u},\r
+ {0xA1u, 0x80u},\r
+ {0xA2u, 0x01u},\r
+ {0xA7u, 0x48u},\r
+ {0xA9u, 0x28u},\r
+ {0xAFu, 0x01u},\r
+ {0xB2u, 0x08u},\r
+ {0xB3u, 0x40u},\r
+ {0xB5u, 0x80u},\r
+ {0xB6u, 0xA0u},\r
+ {0xC0u, 0x07u},\r
+ {0xC2u, 0xB5u},\r
+ {0xC4u, 0x37u},\r
+ {0xCAu, 0x44u},\r
+ {0xCCu, 0xFEu},\r
+ {0xCEu, 0x17u},\r
{0xD6u, 0x3Eu},\r
{0xD8u, 0x3Eu},\r
- {0xE2u, 0x22u},\r
- {0xE6u, 0x16u},\r
- {0xECu, 0x09u},\r
- {0xEEu, 0x06u},\r
- {0x00u, 0x02u},\r
- {0x02u, 0x01u},\r
- {0x05u, 0x34u},\r
- {0x07u, 0x08u},\r
- {0x09u, 0x01u},\r
- {0x0Bu, 0x38u},\r
- {0x11u, 0x05u},\r
- {0x13u, 0x38u},\r
- {0x14u, 0x02u},\r
- {0x15u, 0x10u},\r
- {0x16u, 0x01u},\r
- {0x17u, 0x20u},\r
- {0x1Bu, 0x01u},\r
- {0x1Cu, 0x01u},\r
- {0x1Du, 0x30u},\r
- {0x1Eu, 0x02u},\r
- {0x1Fu, 0x08u},\r
- {0x21u, 0x02u},\r
- {0x23u, 0x30u},\r
- {0x28u, 0x02u},\r
- {0x2Au, 0x01u},\r
- {0x2Bu, 0x40u},\r
- {0x2Cu, 0x02u},\r
- {0x2Du, 0x10u},\r
- {0x2Eu, 0x05u},\r
- {0x2Fu, 0x20u},\r
- {0x32u, 0x04u},\r
- {0x33u, 0x40u},\r
- {0x35u, 0x30u},\r
- {0x36u, 0x03u},\r
- {0x37u, 0x0Fu},\r
- {0x39u, 0x80u},\r
- {0x3Au, 0x80u},\r
- {0x3Bu, 0x20u},\r
+ {0xE6u, 0xCAu},\r
+ {0xEAu, 0x02u},\r
+ {0xECu, 0x04u},\r
+ {0xEEu, 0x81u},\r
+ {0x00u, 0x3Fu},\r
+ {0x01u, 0x01u},\r
+ {0x03u, 0x02u},\r
+ {0x04u, 0x04u},\r
+ {0x06u, 0x08u},\r
+ {0x08u, 0x01u},\r
+ {0x09u, 0x10u},\r
+ {0x0Au, 0x02u},\r
+ {0x0Bu, 0x20u},\r
+ {0x0Cu, 0x10u},\r
+ {0x0Du, 0x10u},\r
+ {0x0Eu, 0x20u},\r
+ {0x0Fu, 0x20u},\r
+ {0x10u, 0x3Fu},\r
+ {0x13u, 0x3Fu},\r
+ {0x14u, 0x04u},\r
+ {0x15u, 0x04u},\r
+ {0x16u, 0x08u},\r
+ {0x17u, 0x08u},\r
+ {0x19u, 0x04u},\r
+ {0x1Au, 0x3Fu},\r
+ {0x1Bu, 0x08u},\r
+ {0x1Cu, 0x10u},\r
+ {0x1Du, 0x3Fu},\r
+ {0x1Eu, 0x20u},\r
+ {0x22u, 0x3Fu},\r
+ {0x23u, 0x3Fu},\r
+ {0x25u, 0x01u},\r
+ {0x27u, 0x02u},\r
+ {0x28u, 0x01u},\r
+ {0x2Au, 0x02u},\r
+ {0x2Bu, 0x3Fu},\r
+ {0x2Du, 0x3Fu},\r
+ {0x2Eu, 0x3Fu},\r
+ {0x30u, 0x03u},\r
+ {0x33u, 0x30u},\r
+ {0x34u, 0x0Cu},\r
+ {0x35u, 0x0Cu},\r
+ {0x36u, 0x30u},\r
+ {0x37u, 0x03u},\r
+ {0x3Au, 0xA2u},\r
+ {0x3Bu, 0xA8u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x01u},\r
- {0x82u, 0x3Fu},\r
- {0x84u, 0x04u},\r
- {0x86u, 0x08u},\r
- {0x88u, 0x10u},\r
- {0x8Au, 0x20u},\r
- {0x8Cu, 0x10u},\r
- {0x8Eu, 0x20u},\r
+ {0x82u, 0x70u},\r
+ {0x84u, 0x0Fu},\r
+ {0x8Du, 0x02u},\r
{0x8Fu, 0x01u},\r
- {0x90u, 0x04u},\r
- {0x92u, 0x08u},\r
- {0x95u, 0x01u},\r
- {0x98u, 0x01u},\r
- {0x99u, 0x01u},\r
- {0x9Au, 0x02u},\r
- {0x9Cu, 0x01u},\r
- {0x9Du, 0x01u},\r
- {0x9Eu, 0x02u},\r
- {0xA0u, 0x3Fu},\r
- {0xA1u, 0x02u},\r
- {0xA4u, 0x3Fu},\r
- {0xAAu, 0x3Fu},\r
- {0xAEu, 0x3Fu},\r
- {0xB0u, 0x30u},\r
- {0xB1u, 0x01u},\r
- {0xB3u, 0x02u},\r
- {0xB4u, 0x0Cu},\r
- {0xB6u, 0x03u},\r
- {0xBAu, 0xA2u},\r
- {0xBFu, 0x01u},\r
- {0xD6u, 0x08u},\r
+ {0x90u, 0x40u},\r
+ {0x91u, 0x01u},\r
+ {0x92u, 0x1Fu},\r
+ {0x93u, 0x02u},\r
+ {0x94u, 0x06u},\r
+ {0x95u, 0x02u},\r
+ {0x96u, 0x09u},\r
+ {0x97u, 0x05u},\r
+ {0x98u, 0x05u},\r
+ {0x99u, 0x02u},\r
+ {0x9Au, 0x0Au},\r
+ {0x9Bu, 0x09u},\r
+ {0x9Cu, 0x10u},\r
+ {0x9Eu, 0x2Fu},\r
+ {0xA4u, 0x03u},\r
+ {0xA6u, 0x0Cu},\r
+ {0xA9u, 0x02u},\r
+ {0xABu, 0x11u},\r
+ {0xACu, 0x20u},\r
+ {0xAEu, 0x4Fu},\r
+ {0xB0u, 0x7Fu},\r
+ {0xB1u, 0x03u},\r
+ {0xB3u, 0x08u},\r
+ {0xB5u, 0x10u},\r
+ {0xB7u, 0x04u},\r
+ {0xBBu, 0x02u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x91u},\r
- {0xDDu, 0x90u},\r
+ {0xDCu, 0x11u},\r
{0xDFu, 0x01u},\r
{0x00u, 0x04u},\r
- {0x01u, 0x01u},\r
- {0x02u, 0x04u},\r
- {0x03u, 0x02u},\r
- {0x07u, 0x40u},\r
- {0x08u, 0x02u},\r
- {0x09u, 0x20u},\r
- {0x0Au, 0x01u},\r
- {0x0Eu, 0x12u},\r
- {0x11u, 0x94u},\r
- {0x12u, 0x80u},\r
+ {0x01u, 0x60u},\r
+ {0x03u, 0x40u},\r
+ {0x05u, 0x01u},\r
+ {0x07u, 0x13u},\r
+ {0x08u, 0x08u},\r
+ {0x0Au, 0x46u},\r
+ {0x0Cu, 0x60u},\r
+ {0x0Du, 0x08u},\r
+ {0x0Eu, 0x02u},\r
+ {0x0Fu, 0x40u},\r
+ {0x10u, 0x40u},\r
+ {0x11u, 0x10u},\r
+ {0x13u, 0x40u},\r
{0x14u, 0x01u},\r
- {0x17u, 0x20u},\r
+ {0x17u, 0x04u},\r
{0x18u, 0x04u},\r
- {0x19u, 0x41u},\r
- {0x1Au, 0x01u},\r
- {0x1Bu, 0x02u},\r
- {0x1Eu, 0x12u},\r
- {0x1Fu, 0x84u},\r
- {0x21u, 0x01u},\r
- {0x22u, 0x04u},\r
+ {0x19u, 0x12u},\r
+ {0x1Au, 0x02u},\r
+ {0x1Bu, 0x40u},\r
+ {0x1Du, 0x01u},\r
+ {0x1Eu, 0x80u},\r
+ {0x22u, 0x10u},\r
+ {0x23u, 0x11u},\r
+ {0x24u, 0x40u},\r
{0x25u, 0x40u},\r
- {0x27u, 0x25u},\r
- {0x2Bu, 0x80u},\r
- {0x2Du, 0x01u},\r
- {0x2Fu, 0x09u},\r
- {0x30u, 0xA8u},\r
- {0x36u, 0x80u},\r
- {0x37u, 0x15u},\r
- {0x38u, 0x20u},\r
- {0x39u, 0x50u},\r
- {0x3Au, 0x02u},\r
- {0x3Du, 0x14u},\r
- {0x58u, 0x84u},\r
- {0x59u, 0x20u},\r
- {0x5Eu, 0x40u},\r
- {0x60u, 0x02u},\r
- {0x61u, 0x04u},\r
- {0x62u, 0x18u},\r
- {0x64u, 0x01u},\r
- {0x85u, 0x20u},\r
- {0x8Bu, 0x01u},\r
- {0x8Du, 0x04u},\r
+ {0x26u, 0x16u},\r
+ {0x28u, 0x51u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Cu, 0x01u},\r
+ {0x2Eu, 0x40u},\r
+ {0x2Fu, 0x04u},\r
+ {0x32u, 0x18u},\r
+ {0x33u, 0x41u},\r
+ {0x36u, 0x16u},\r
+ {0x39u, 0x80u},\r
+ {0x3Bu, 0x11u},\r
+ {0x3Du, 0x80u},\r
+ {0x5Au, 0x80u},\r
+ {0x5Cu, 0x60u},\r
+ {0x5Fu, 0x0Au},\r
+ {0x62u, 0xC0u},\r
+ {0x66u, 0x80u},\r
+ {0x84u, 0x30u},\r
+ {0x85u, 0x12u},\r
+ {0x8Au, 0x08u},\r
+ {0x8Du, 0x40u},\r
{0x8Eu, 0x40u},\r
- {0x90u, 0x23u},\r
- {0x91u, 0x05u},\r
- {0x92u, 0x20u},\r
- {0x93u, 0x02u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x40u},\r
- {0x96u, 0x08u},\r
- {0x98u, 0x04u},\r
- {0x9Au, 0x04u},\r
- {0x9Bu, 0x10u},\r
- {0x9Du, 0x41u},\r
- {0x9Eu, 0x12u},\r
- {0x9Fu, 0x0Du},\r
- {0xA1u, 0x20u},\r
- {0xA2u, 0x90u},\r
- {0xA4u, 0xACu},\r
- {0xA6u, 0x28u},\r
- {0xA7u, 0x80u},\r
- {0xAEu, 0x24u},\r
- {0xB1u, 0x01u},\r
- {0xB4u, 0x11u},\r
- {0xB6u, 0x40u},\r
- {0xB7u, 0x20u},\r
- {0xC0u, 0x1Fu},\r
- {0xC2u, 0xABu},\r
- {0xC4u, 0xCFu},\r
- {0xCAu, 0xB1u},\r
- {0xCCu, 0xFEu},\r
- {0xCEu, 0x69u},\r
- {0xD6u, 0x1Eu},\r
- {0xD8u, 0x1Eu},\r
- {0xE2u, 0x01u},\r
- {0xE6u, 0x03u},\r
- {0xEAu, 0x0Bu},\r
- {0xEEu, 0x08u},\r
- {0x01u, 0x02u},\r
- {0x03u, 0x01u},\r
- {0x04u, 0x06u},\r
- {0x09u, 0x02u},\r
- {0x0Bu, 0x01u},\r
- {0x0Cu, 0x2Au},\r
- {0x0Eu, 0x11u},\r
- {0x10u, 0x19u},\r
- {0x11u, 0x01u},\r
- {0x12u, 0x24u},\r
- {0x13u, 0x02u},\r
- {0x14u, 0x20u},\r
- {0x15u, 0x02u},\r
- {0x16u, 0x18u},\r
- {0x17u, 0x09u},\r
- {0x18u, 0x09u},\r
- {0x19u, 0x02u},\r
- {0x1Au, 0x32u},\r
- {0x1Bu, 0x05u},\r
- {0x23u, 0x10u},\r
- {0x26u, 0x40u},\r
- {0x2Au, 0x80u},\r
- {0x2Cu, 0x40u},\r
- {0x2Eu, 0x80u},\r
- {0x31u, 0x08u},\r
- {0x32u, 0x38u},\r
- {0x33u, 0x04u},\r
- {0x34u, 0x07u},\r
- {0x35u, 0x10u},\r
- {0x36u, 0xC0u},\r
- {0x37u, 0x03u},\r
- {0x38u, 0x20u},\r
- {0x3Au, 0x08u},\r
- {0x3Bu, 0x80u},\r
- {0x3Eu, 0x40u},\r
- {0x54u, 0x09u},\r
- {0x56u, 0x04u},\r
+ {0x90u, 0x80u},\r
+ {0x91u, 0x80u},\r
+ {0x92u, 0x40u},\r
+ {0x93u, 0x0Au},\r
+ {0x96u, 0x20u},\r
+ {0x97u, 0x31u},\r
+ {0x98u, 0x0Au},\r
+ {0x9Au, 0x1Au},\r
+ {0x9Bu, 0x70u},\r
+ {0x9Cu, 0x04u},\r
+ {0x9Du, 0x12u},\r
+ {0xA0u, 0x80u},\r
+ {0xA1u, 0x89u},\r
+ {0xA2u, 0x09u},\r
+ {0xA3u, 0x10u},\r
+ {0xA4u, 0x12u},\r
+ {0xA6u, 0xA0u},\r
+ {0xA7u, 0x48u},\r
+ {0xA9u, 0x40u},\r
+ {0xACu, 0x40u},\r
+ {0xB1u, 0x80u},\r
+ {0xB2u, 0x04u},\r
+ {0xB4u, 0x50u},\r
+ {0xC0u, 0x3Fu},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0xABu},\r
+ {0xCAu, 0x2Fu},\r
+ {0xCCu, 0xEFu},\r
+ {0xCEu, 0x1Du},\r
+ {0xD6u, 0xF8u},\r
+ {0xD8u, 0x18u},\r
+ {0xE2u, 0x02u},\r
+ {0xE6u, 0x02u},\r
+ {0xEAu, 0x03u},\r
+ {0xEEu, 0xC8u},\r
+ {0x00u, 0x01u},\r
+ {0x01u, 0xFFu},\r
+ {0x02u, 0x0Eu},\r
+ {0x04u, 0x02u},\r
+ {0x07u, 0xFFu},\r
+ {0x09u, 0x0Fu},\r
+ {0x0Bu, 0xF0u},\r
+ {0x0Cu, 0x04u},\r
+ {0x0Du, 0xFFu},\r
+ {0x10u, 0x18u},\r
+ {0x11u, 0x69u},\r
+ {0x12u, 0x03u},\r
+ {0x13u, 0x96u},\r
+ {0x14u, 0x03u},\r
+ {0x15u, 0x55u},\r
+ {0x16u, 0x14u},\r
+ {0x17u, 0xAAu},\r
+ {0x1Au, 0x1Fu},\r
+ {0x1Eu, 0x08u},\r
+ {0x22u, 0x20u},\r
+ {0x23u, 0xFFu},\r
+ {0x2Au, 0x01u},\r
+ {0x2Bu, 0xFFu},\r
+ {0x2Du, 0x33u},\r
+ {0x2Fu, 0xCCu},\r
+ {0x32u, 0x1Fu},\r
+ {0x34u, 0x20u},\r
+ {0x35u, 0xFFu},\r
+ {0x3Bu, 0x20u},\r
+ {0x54u, 0x01u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x10u},\r
+ {0x5Cu, 0x11u},\r
+ {0x5Du, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x06u},\r
- {0x86u, 0x09u},\r
- {0x87u, 0xFFu},\r
- {0x88u, 0x05u},\r
- {0x89u, 0x50u},\r
- {0x8Au, 0x0Au},\r
- {0x8Bu, 0xA0u},\r
- {0x8Cu, 0x60u},\r
- {0x8Eu, 0x90u},\r
- {0x90u, 0x0Fu},\r
- {0x91u, 0x90u},\r
- {0x92u, 0xF0u},\r
- {0x93u, 0x60u},\r
- {0x94u, 0x50u},\r
- {0x95u, 0x30u},\r
- {0x96u, 0xA0u},\r
- {0x97u, 0xC0u},\r
- {0x98u, 0x03u},\r
- {0x99u, 0x09u},\r
- {0x9Au, 0x0Cu},\r
- {0x9Bu, 0x06u},\r
- {0x9Du, 0x0Fu},\r
- {0x9Fu, 0xF0u},\r
- {0xA2u, 0xFFu},\r
- {0xA3u, 0xFFu},\r
- {0xA4u, 0x30u},\r
- {0xA5u, 0x03u},\r
- {0xA6u, 0xC0u},\r
- {0xA7u, 0x0Cu},\r
- {0xA8u, 0xFFu},\r
- {0xA9u, 0x05u},\r
- {0xABu, 0x0Au},\r
- {0xAEu, 0xFFu},\r
- {0xAFu, 0xFFu},\r
- {0xB3u, 0xFFu},\r
- {0xB4u, 0xFFu},\r
- {0xBEu, 0x10u},\r
- {0xBFu, 0x04u},\r
- {0xD4u, 0x01u},\r
+ {0x81u, 0x04u},\r
+ {0x82u, 0x10u},\r
+ {0x83u, 0x20u},\r
+ {0x85u, 0x01u},\r
+ {0x87u, 0x5Eu},\r
+ {0x88u, 0x04u},\r
+ {0x89u, 0x39u},\r
+ {0x8Au, 0x08u},\r
+ {0x8Bu, 0x06u},\r
+ {0x8Du, 0x46u},\r
+ {0x8Eu, 0x07u},\r
+ {0x90u, 0x0Au},\r
+ {0x91u, 0x46u},\r
+ {0x92u, 0x05u},\r
+ {0x97u, 0x46u},\r
+ {0x99u, 0x42u},\r
+ {0x9Bu, 0x04u},\r
+ {0x9Cu, 0x09u},\r
+ {0x9Du, 0x46u},\r
+ {0x9Eu, 0x02u},\r
+ {0xA1u, 0x42u},\r
+ {0xA2u, 0x08u},\r
+ {0xA4u, 0x10u},\r
+ {0xA6u, 0x20u},\r
+ {0xAAu, 0x20u},\r
+ {0xADu, 0x77u},\r
+ {0xAFu, 0x08u},\r
+ {0xB0u, 0x0Fu},\r
+ {0xB1u, 0x08u},\r
+ {0xB2u, 0x30u},\r
+ {0xB3u, 0x70u},\r
+ {0xB5u, 0x0Fu},\r
+ {0xB7u, 0x01u},\r
+ {0xB8u, 0x80u},\r
+ {0xB9u, 0x20u},\r
+ {0xBBu, 0x0Cu},\r
+ {0xBEu, 0x44u},\r
+ {0xBFu, 0x41u},\r
+ {0xD4u, 0x09u},\r
+ {0xD6u, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDDu, 0x10u},\r
+ {0xDCu, 0x01u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x10u},\r
- {0x03u, 0x21u},\r
- {0x04u, 0x04u},\r
- {0x05u, 0x80u},\r
- {0x08u, 0x20u},\r
- {0x0Au, 0x80u},\r
- {0x0Bu, 0x20u},\r
- {0x0Cu, 0x10u},\r
- {0x0Eu, 0x20u},\r
- {0x0Fu, 0x80u},\r
- {0x11u, 0x04u},\r
- {0x12u, 0x45u},\r
- {0x14u, 0x24u},\r
- {0x17u, 0x40u},\r
- {0x19u, 0x20u},\r
- {0x1Cu, 0x04u},\r
- {0x1Eu, 0x22u},\r
- {0x1Fu, 0x04u},\r
- {0x20u, 0x10u},\r
- {0x24u, 0x08u},\r
- {0x25u, 0x01u},\r
- {0x26u, 0x08u},\r
- {0x27u, 0x02u},\r
- {0x28u, 0x20u},\r
- {0x29u, 0x04u},\r
- {0x2Au, 0x41u},\r
- {0x2Bu, 0x05u},\r
- {0x2Du, 0x02u},\r
- {0x30u, 0x04u},\r
- {0x32u, 0x44u},\r
- {0x33u, 0x61u},\r
- {0x35u, 0x10u},\r
+ {0x00u, 0x40u},\r
+ {0x02u, 0x80u},\r
+ {0x03u, 0x08u},\r
+ {0x04u, 0x80u},\r
+ {0x05u, 0x02u},\r
+ {0x06u, 0x10u},\r
+ {0x0Au, 0x41u},\r
+ {0x0Du, 0x80u},\r
+ {0x0Eu, 0x64u},\r
+ {0x10u, 0x80u},\r
+ {0x13u, 0x28u},\r
+ {0x16u, 0x40u},\r
+ {0x17u, 0x10u},\r
+ {0x18u, 0x40u},\r
+ {0x1Au, 0x20u},\r
+ {0x1Bu, 0x40u},\r
+ {0x1Eu, 0x20u},\r
+ {0x1Fu, 0x18u},\r
+ {0x20u, 0x08u},\r
+ {0x21u, 0x14u},\r
+ {0x23u, 0x95u},\r
+ {0x25u, 0x10u},\r
+ {0x27u, 0x04u},\r
+ {0x29u, 0x41u},\r
+ {0x2Eu, 0x01u},\r
+ {0x2Fu, 0x09u},\r
+ {0x30u, 0x28u},\r
+ {0x33u, 0x41u},\r
+ {0x34u, 0x02u},\r
{0x36u, 0x08u},\r
- {0x37u, 0x02u},\r
- {0x39u, 0x28u},\r
- {0x3Au, 0x04u},\r
- {0x3Bu, 0x20u},\r
- {0x3Du, 0x02u},\r
- {0x3Fu, 0x20u},\r
- {0x59u, 0x40u},\r
- {0x5Cu, 0x0Au},\r
- {0x5Eu, 0x90u},\r
- {0x64u, 0x40u},\r
- {0x67u, 0x02u},\r
- {0x8Bu, 0x04u},\r
- {0x8Fu, 0x10u},\r
- {0x91u, 0x3Cu},\r
- {0x92u, 0x88u},\r
+ {0x38u, 0x02u},\r
+ {0x39u, 0x6Au},\r
+ {0x3Du, 0x22u},\r
+ {0x3Eu, 0x44u},\r
+ {0x58u, 0x20u},\r
+ {0x59u, 0x04u},\r
+ {0x5Au, 0x02u},\r
+ {0x5Bu, 0x80u},\r
+ {0x5Du, 0x02u},\r
+ {0x5Eu, 0x83u},\r
+ {0x62u, 0x01u},\r
+ {0x63u, 0x01u},\r
+ {0x68u, 0x02u},\r
+ {0x80u, 0x21u},\r
+ {0x83u, 0x40u},\r
+ {0x8Au, 0xA0u},\r
+ {0x8Cu, 0x40u},\r
+ {0x90u, 0x80u},\r
+ {0x92u, 0x44u},\r
{0x93u, 0x02u},\r
- {0x94u, 0x10u},\r
- {0x97u, 0x80u},\r
- {0x99u, 0x04u},\r
- {0x9Bu, 0x01u},\r
- {0x9Cu, 0x40u},\r
- {0x9Du, 0x20u},\r
- {0x9Eu, 0x01u},\r
- {0x9Fu, 0x42u},\r
- {0xA2u, 0x40u},\r
- {0xA3u, 0x25u},\r
- {0xA5u, 0x04u},\r
- {0xA6u, 0x21u},\r
- {0xA7u, 0x40u},\r
- {0xAAu, 0x04u},\r
- {0xABu, 0x05u},\r
- {0xACu, 0x40u},\r
- {0xAEu, 0x40u},\r
- {0xB2u, 0x01u},\r
- {0xB6u, 0x82u},\r
- {0xB7u, 0x02u},\r
- {0xC0u, 0xA7u},\r
- {0xC2u, 0x7Eu},\r
- {0xC4u, 0xEFu},\r
- {0xCAu, 0x8Fu},\r
- {0xCCu, 0xEFu},\r
- {0xCEu, 0xA6u},\r
- {0xD6u, 0xF8u},\r
- {0xD8u, 0x90u},\r
- {0xE0u, 0x10u},\r
- {0xE2u, 0x81u},\r
- {0xE6u, 0x43u},\r
- {0xE8u, 0x40u},\r
- {0xEAu, 0x12u},\r
- {0xECu, 0x10u},\r
- {0xEEu, 0xC0u},\r
- {0x00u, 0x0Fu},\r
- {0x02u, 0xF0u},\r
- {0x04u, 0x09u},\r
- {0x06u, 0x06u},\r
- {0x07u, 0xFFu},\r
- {0x08u, 0x05u},\r
- {0x09u, 0x50u},\r
- {0x0Au, 0x0Au},\r
- {0x0Bu, 0xA0u},\r
- {0x0Cu, 0x90u},\r
- {0x0Eu, 0x60u},\r
- {0x10u, 0x03u},\r
- {0x11u, 0x60u},\r
- {0x12u, 0x0Cu},\r
- {0x13u, 0x90u},\r
- {0x15u, 0x30u},\r
- {0x16u, 0xFFu},\r
- {0x17u, 0xC0u},\r
- {0x18u, 0xFFu},\r
- {0x19u, 0x06u},\r
- {0x1Bu, 0x09u},\r
- {0x1Du, 0x0Fu},\r
- {0x1Fu, 0xF0u},\r
- {0x23u, 0xFFu},\r
+ {0x97u, 0x20u},\r
+ {0x98u, 0x06u},\r
+ {0x9Au, 0x52u},\r
+ {0x9Bu, 0x10u},\r
+ {0x9Fu, 0x04u},\r
+ {0xA0u, 0x80u},\r
+ {0xA1u, 0x81u},\r
+ {0xA2u, 0x49u},\r
+ {0xA3u, 0x10u},\r
+ {0xA4u, 0x12u},\r
+ {0xA6u, 0x20u},\r
+ {0xA7u, 0x08u},\r
+ {0xA8u, 0x20u},\r
+ {0xA9u, 0x20u},\r
+ {0xAAu, 0x80u},\r
+ {0xABu, 0x20u},\r
+ {0xACu, 0x10u},\r
+ {0xAEu, 0x04u},\r
+ {0xAFu, 0x09u},\r
+ {0xB0u, 0x04u},\r
+ {0xB3u, 0x48u},\r
+ {0xB6u, 0x01u},\r
+ {0xB7u, 0x10u},\r
+ {0xC0u, 0xBBu},\r
+ {0xC2u, 0xF9u},\r
+ {0xC4u, 0x5Eu},\r
+ {0xCAu, 0xB9u},\r
+ {0xCCu, 0xCFu},\r
+ {0xCEu, 0xFFu},\r
+ {0xD6u, 0x1Fu},\r
+ {0xD8u, 0x09u},\r
+ {0xE2u, 0x09u},\r
+ {0xE6u, 0x02u},\r
+ {0xEAu, 0x02u},\r
+ {0xEEu, 0x07u},\r
+ {0x88u, 0x04u},\r
+ {0x89u, 0x40u},\r
+ {0x8Fu, 0x04u},\r
+ {0x99u, 0x40u},\r
+ {0x9Cu, 0x84u},\r
+ {0xA0u, 0x24u},\r
+ {0xA7u, 0x04u},\r
+ {0xA8u, 0x02u},\r
+ {0xA9u, 0x10u},\r
+ {0xAAu, 0x40u},\r
+ {0xAEu, 0x20u},\r
+ {0xAFu, 0x04u},\r
+ {0xB0u, 0x42u},\r
+ {0xB6u, 0x08u},\r
+ {0xB7u, 0x08u},\r
+ {0xE0u, 0x40u},\r
+ {0xE2u, 0xA9u},\r
+ {0xE6u, 0x02u},\r
+ {0xE8u, 0x10u},\r
+ {0xEAu, 0x04u},\r
+ {0xECu, 0x40u},\r
+ {0xEEu, 0x80u},\r
+ {0x02u, 0xFFu},\r
+ {0x05u, 0x10u},\r
+ {0x06u, 0xFFu},\r
+ {0x08u, 0x50u},\r
+ {0x0Au, 0xA0u},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Fu, 0x04u},\r
+ {0x10u, 0x05u},\r
+ {0x12u, 0x0Au},\r
+ {0x13u, 0x02u},\r
+ {0x14u, 0x0Fu},\r
+ {0x15u, 0x05u},\r
+ {0x16u, 0xF0u},\r
+ {0x17u, 0x0Au},\r
+ {0x18u, 0x03u},\r
+ {0x1Au, 0x0Cu},\r
+ {0x1Cu, 0x06u},\r
+ {0x1Eu, 0x09u},\r
+ {0x20u, 0xFFu},\r
+ {0x23u, 0x01u},\r
{0x24u, 0x30u},\r
- {0x25u, 0x03u},\r
{0x26u, 0xC0u},\r
- {0x27u, 0x0Cu},\r
- {0x28u, 0x50u},\r
- {0x29u, 0x05u},\r
- {0x2Au, 0xA0u},\r
- {0x2Bu, 0x0Au},\r
- {0x2Cu, 0xFFu},\r
- {0x2Du, 0xFFu},\r
- {0x31u, 0xFFu},\r
- {0x32u, 0xFFu},\r
- {0x3Eu, 0x04u},\r
- {0x3Fu, 0x01u},\r
+ {0x2Cu, 0x60u},\r
+ {0x2Eu, 0x90u},\r
+ {0x31u, 0x0Cu},\r
+ {0x33u, 0x03u},\r
+ {0x35u, 0x10u},\r
+ {0x36u, 0xFFu},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x05u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
+ {0x5Cu, 0x90u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x02u},\r
- {0x84u, 0x04u},\r
- {0x86u, 0x38u},\r
- {0x88u, 0x10u},\r
- {0x8Au, 0x20u},\r
- {0x8Cu, 0x10u},\r
- {0x8Du, 0x05u},\r
- {0x8Eu, 0x20u},\r
- {0x96u, 0x07u},\r
- {0x98u, 0x09u},\r
- {0x99u, 0x01u},\r
- {0x9Au, 0x32u},\r
- {0x9Bu, 0x04u},\r
- {0x9Eu, 0x30u},\r
- {0xA0u, 0x30u},\r
- {0xA1u, 0x01u},\r
- {0xA3u, 0x04u},\r
- {0xAAu, 0x08u},\r
- {0xACu, 0x3Au},\r
- {0xAEu, 0x05u},\r
- {0xB2u, 0x0Fu},\r
- {0xB3u, 0x01u},\r
- {0xB4u, 0x30u},\r
- {0xB5u, 0x02u},\r
- {0xB7u, 0x04u},\r
+ {0x80u, 0x02u},\r
+ {0x81u, 0x09u},\r
+ {0x82u, 0x01u},\r
+ {0x83u, 0x06u},\r
+ {0x85u, 0x30u},\r
+ {0x86u, 0x80u},\r
+ {0x87u, 0xC0u},\r
+ {0x88u, 0x01u},\r
+ {0x89u, 0x50u},\r
+ {0x8Au, 0x02u},\r
+ {0x8Bu, 0xA0u},\r
+ {0x8Du, 0x03u},\r
+ {0x8Eu, 0x70u},\r
+ {0x8Fu, 0x0Cu},\r
+ {0x93u, 0xFFu},\r
+ {0x94u, 0x02u},\r
+ {0x96u, 0x05u},\r
+ {0x97u, 0xFFu},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Eu, 0x01u},\r
+ {0x9Fu, 0xFFu},\r
+ {0xA0u, 0x40u},\r
+ {0xA1u, 0x05u},\r
+ {0xA2u, 0x80u},\r
+ {0xA3u, 0x0Au},\r
+ {0xA4u, 0xA0u},\r
+ {0xA6u, 0x50u},\r
+ {0xA8u, 0x90u},\r
+ {0xA9u, 0x0Fu},\r
+ {0xAAu, 0x20u},\r
+ {0xABu, 0xF0u},\r
+ {0xACu, 0x02u},\r
+ {0xADu, 0x90u},\r
+ {0xAEu, 0x09u},\r
+ {0xAFu, 0x60u},\r
+ {0xB0u, 0x04u},\r
+ {0xB2u, 0x08u},\r
+ {0xB4u, 0x03u},\r
+ {0xB5u, 0xFFu},\r
+ {0xB6u, 0xF0u},\r
{0xBAu, 0x20u},\r
- {0xBFu, 0x44u},\r
+ {0xBFu, 0x10u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x91u},\r
+ {0xDCu, 0x01u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x10u},\r
- {0x03u, 0x61u},\r
- {0x05u, 0x90u},\r
- {0x06u, 0x20u},\r
- {0x08u, 0x12u},\r
- {0x09u, 0x04u},\r
- {0x0Cu, 0x20u},\r
- {0x0Eu, 0x21u},\r
- {0x10u, 0x09u},\r
- {0x11u, 0x04u},\r
- {0x14u, 0x10u},\r
- {0x15u, 0x08u},\r
- {0x16u, 0x8Au},\r
- {0x19u, 0x08u},\r
- {0x1Du, 0x14u},\r
- {0x1Eu, 0x24u},\r
- {0x21u, 0x01u},\r
- {0x26u, 0x44u},\r
+ {0x01u, 0x18u},\r
+ {0x03u, 0x40u},\r
+ {0x05u, 0x55u},\r
+ {0x08u, 0x14u},\r
+ {0x0Au, 0x01u},\r
+ {0x0Bu, 0x80u},\r
+ {0x0Du, 0x80u},\r
+ {0x0Eu, 0x20u},\r
+ {0x11u, 0x44u},\r
+ {0x13u, 0x02u},\r
+ {0x15u, 0x82u},\r
+ {0x16u, 0x28u},\r
+ {0x18u, 0x02u},\r
+ {0x1Du, 0x51u},\r
+ {0x1Eu, 0x20u},\r
+ {0x20u, 0x80u},\r
+ {0x22u, 0x28u},\r
{0x27u, 0x04u},\r
- {0x28u, 0x01u},\r
- {0x29u, 0x04u},\r
- {0x2Au, 0x01u},\r
- {0x2Bu, 0x05u},\r
- {0x2Fu, 0x40u},\r
- {0x32u, 0x44u},\r
- {0x33u, 0x21u},\r
- {0x36u, 0x20u},\r
- {0x39u, 0x28u},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x80u},\r
- {0x5Cu, 0x80u},\r
- {0x66u, 0x40u},\r
- {0x68u, 0x88u},\r
- {0x69u, 0x24u},\r
- {0x6Au, 0x08u},\r
- {0x6Bu, 0x01u},\r
- {0x71u, 0x60u},\r
- {0x72u, 0x50u},\r
- {0x79u, 0x10u},\r
- {0x7Bu, 0x04u},\r
- {0x80u, 0x80u},\r
- {0x86u, 0x04u},\r
- {0x8Cu, 0x02u},\r
- {0x8Du, 0x04u},\r
- {0x91u, 0x08u},\r
- {0x92u, 0x81u},\r
- {0x94u, 0x10u},\r
- {0x95u, 0x22u},\r
- {0x96u, 0x50u},\r
- {0x99u, 0x80u},\r
- {0x9Au, 0x28u},\r
- {0x9Du, 0x68u},\r
- {0x9Eu, 0xC2u},\r
- {0x9Fu, 0x01u},\r
- {0xA0u, 0x20u},\r
- {0xA3u, 0x25u},\r
- {0xA4u, 0x80u},\r
- {0xA5u, 0x20u},\r
- {0xA6u, 0x01u},\r
- {0xA8u, 0x81u},\r
- {0xAFu, 0x80u},\r
- {0xB0u, 0x20u},\r
- {0xB1u, 0x08u},\r
- {0xC0u, 0xEFu},\r
- {0xC2u, 0xEEu},\r
- {0xC4u, 0xD7u},\r
- {0xCAu, 0x8Fu},\r
- {0xCCu, 0x2Fu},\r
- {0xCEu, 0x96u},\r
- {0xD6u, 0x10u},\r
- {0xD8u, 0x10u},\r
- {0xE2u, 0x20u},\r
- {0xE6u, 0x27u},\r
- {0xECu, 0x20u},\r
- {0xEEu, 0x02u},\r
- {0x00u, 0x03u},\r
- {0x04u, 0x10u},\r
- {0x06u, 0x23u},\r
- {0x0Au, 0x20u},\r
- {0x0Bu, 0x08u},\r
- {0x0Cu, 0x2Bu},\r
- {0x0Du, 0x0Au},\r
- {0x0Eu, 0x14u},\r
- {0x0Fu, 0x05u},\r
- {0x13u, 0x20u},\r
- {0x14u, 0x24u},\r
- {0x16u, 0x0Bu},\r
- {0x1Au, 0x5Cu},\r
- {0x1Bu, 0x17u},\r
- {0x1Eu, 0x03u},\r
- {0x20u, 0x01u},\r
- {0x22u, 0x02u},\r
- {0x24u, 0x01u},\r
- {0x25u, 0x09u},\r
- {0x26u, 0x02u},\r
- {0x27u, 0x02u},\r
- {0x29u, 0x04u},\r
- {0x2Au, 0x80u},\r
- {0x2Bu, 0x08u},\r
- {0x2Cu, 0x40u},\r
- {0x2Du, 0x10u},\r
- {0x2Eu, 0x80u},\r
- {0x2Fu, 0x20u},\r
- {0x32u, 0x03u},\r
- {0x34u, 0x3Cu},\r
- {0x35u, 0x0Fu},\r
- {0x36u, 0xC0u},\r
- {0x37u, 0x30u},\r
- {0x3Au, 0x08u},\r
- {0x3Eu, 0x40u},\r
+ {0x2Au, 0x02u},\r
+ {0x2Cu, 0x04u},\r
+ {0x2Fu, 0x42u},\r
+ {0x30u, 0x04u},\r
+ {0x33u, 0x02u},\r
+ {0x34u, 0x80u},\r
+ {0x35u, 0x08u},\r
+ {0x37u, 0x49u},\r
+ {0x39u, 0x10u},\r
+ {0x3Bu, 0x84u},\r
+ {0x3Du, 0x14u},\r
+ {0x3Eu, 0x03u},\r
{0x3Fu, 0x40u},\r
- {0x58u, 0x04u},\r
- {0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
- {0x5Fu, 0x01u},\r
- {0x81u, 0x10u},\r
- {0x84u, 0x06u},\r
- {0x85u, 0x01u},\r
- {0x86u, 0x09u},\r
- {0x87u, 0x02u},\r
- {0x89u, 0x10u},\r
- {0x8Cu, 0x0Fu},\r
- {0x8Du, 0x23u},\r
- {0x8Eu, 0xF0u},\r
- {0x8Fu, 0x4Cu},\r
- {0x90u, 0x30u},\r
- {0x92u, 0xC0u},\r
- {0x93u, 0x40u},\r
- {0x94u, 0x50u},\r
- {0x96u, 0xA0u},\r
- {0x98u, 0x60u},\r
- {0x9Au, 0x90u},\r
- {0x9Bu, 0x20u},\r
- {0x9Du, 0x08u},\r
- {0x9Fu, 0x04u},\r
- {0xA1u, 0x02u},\r
- {0xA3u, 0x01u},\r
- {0xA4u, 0x03u},\r
- {0xA5u, 0x10u},\r
- {0xA6u, 0x0Cu},\r
- {0xA8u, 0x05u},\r
- {0xA9u, 0x10u},\r
- {0xAAu, 0x0Au},\r
- {0xADu, 0x04u},\r
- {0xAFu, 0x08u},\r
- {0xB0u, 0xFFu},\r
- {0xB1u, 0x10u},\r
- {0xB3u, 0x0Fu},\r
- {0xB5u, 0x60u},\r
- {0xB9u, 0x02u},\r
- {0xBEu, 0x01u},\r
- {0xBFu, 0x15u},\r
- {0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDFu, 0x01u},\r
- {0x00u, 0x04u},\r
- {0x01u, 0x40u},\r
- {0x05u, 0x10u},\r
- {0x06u, 0xA2u},\r
- {0x08u, 0x08u},\r
- {0x09u, 0x20u},\r
- {0x0Au, 0x50u},\r
- {0x0Du, 0x08u},\r
- {0x0Eu, 0x09u},\r
- {0x0Fu, 0x08u},\r
- {0x12u, 0x18u},\r
- {0x13u, 0x08u},\r
- {0x14u, 0x10u},\r
- {0x15u, 0xA0u},\r
- {0x16u, 0x40u},\r
- {0x1Bu, 0x01u},\r
- {0x1Cu, 0x02u},\r
- {0x1Eu, 0x08u},\r
- {0x1Fu, 0x08u},\r
- {0x20u, 0x08u},\r
- {0x21u, 0x04u},\r
- {0x22u, 0x01u},\r
- {0x24u, 0x0Au},\r
- {0x26u, 0x20u},\r
- {0x28u, 0x01u},\r
- {0x29u, 0x68u},\r
- {0x2Bu, 0x80u},\r
- {0x2Cu, 0x24u},\r
- {0x2Du, 0x40u},\r
- {0x2Eu, 0x20u},\r
- {0x30u, 0x80u},\r
- {0x33u, 0x21u},\r
- {0x34u, 0x01u},\r
- {0x36u, 0x20u},\r
- {0x38u, 0x18u},\r
- {0x39u, 0xC2u},\r
- {0x3Du, 0x80u},\r
- {0x3Fu, 0x20u},\r
- {0x5Cu, 0x80u},\r
- {0x5Du, 0x05u},\r
- {0x5Eu, 0x20u},\r
- {0x64u, 0x02u},\r
- {0x78u, 0x02u},\r
- {0x7Au, 0x80u},\r
- {0x84u, 0x10u},\r
- {0x85u, 0x01u},\r
- {0x87u, 0x08u},\r
- {0x88u, 0x05u},\r
- {0x8Bu, 0x08u},\r
- {0x90u, 0x04u},\r
- {0x91u, 0x84u},\r
- {0x92u, 0x81u},\r
- {0x96u, 0x42u},\r
- {0x98u, 0x04u},\r
- {0x99u, 0x90u},\r
- {0x9Au, 0x08u},\r
- {0x9Cu, 0x08u},\r
- {0x9Eu, 0x10u},\r
- {0xA1u, 0x40u},\r
- {0xA2u, 0x98u},\r
- {0xA3u, 0x30u},\r
- {0xA4u, 0xA0u},\r
- {0xA5u, 0x28u},\r
- {0xA6u, 0x01u},\r
- {0xA7u, 0x80u},\r
- {0xAAu, 0x01u},\r
+ {0x58u, 0x40u},\r
+ {0x5Eu, 0x40u},\r
+ {0x5Fu, 0x10u},\r
+ {0x60u, 0x02u},\r
+ {0x63u, 0x02u},\r
+ {0x65u, 0x20u},\r
+ {0x66u, 0x80u},\r
+ {0x67u, 0x02u},\r
+ {0x85u, 0x20u},\r
+ {0x86u, 0x04u},\r
+ {0x88u, 0x50u},\r
+ {0x8Bu, 0x48u},\r
+ {0x8Eu, 0x08u},\r
+ {0x8Fu, 0x01u},\r
+ {0x91u, 0xD6u},\r
+ {0x92u, 0x05u},\r
+ {0x93u, 0x94u},\r
+ {0x94u, 0x02u},\r
+ {0x99u, 0x04u},\r
+ {0x9Au, 0x20u},\r
+ {0x9Bu, 0x03u},\r
+ {0x9Cu, 0x14u},\r
+ {0x9Du, 0x28u},\r
+ {0x9Eu, 0x82u},\r
+ {0x9Fu, 0x44u},\r
+ {0xA0u, 0x26u},\r
+ {0xA1u, 0x80u},\r
+ {0xA3u, 0x02u},\r
+ {0xA7u, 0x0Du},\r
{0xABu, 0x01u},\r
- {0xACu, 0x04u},\r
- {0xADu, 0x41u},\r
- {0xAEu, 0x05u},\r
- {0xB2u, 0x10u},\r
- {0xB4u, 0x80u},\r
- {0xB7u, 0x40u},\r
- {0xC0u, 0xF5u},\r
- {0xC2u, 0xEEu},\r
- {0xC4u, 0xF6u},\r
- {0xCAu, 0x7Fu},\r
- {0xCCu, 0xADu},\r
- {0xCEu, 0x3Fu},\r
- {0xD6u, 0xF0u},\r
- {0xD8u, 0x10u},\r
- {0xE4u, 0x80u},\r
- {0xE6u, 0x21u},\r
- {0xE8u, 0x80u},\r
- {0xECu, 0x09u},\r
- {0xEEu, 0xC0u},\r
- {0x00u, 0x80u},\r
- {0x02u, 0x40u},\r
- {0x06u, 0x1Cu},\r
- {0x0Cu, 0x80u},\r
- {0x0Du, 0x0Au},\r
- {0x0Eu, 0x41u},\r
- {0x0Fu, 0x14u},\r
- {0x14u, 0x24u},\r
- {0x16u, 0x08u},\r
- {0x18u, 0x80u},\r
- {0x1Au, 0x40u},\r
- {0x1Bu, 0x04u},\r
- {0x1Cu, 0x40u},\r
- {0x1Eu, 0x80u},\r
- {0x1Fu, 0x10u},\r
- {0x20u, 0x80u},\r
- {0x22u, 0x42u},\r
- {0x23u, 0x08u},\r
- {0x26u, 0x20u},\r
- {0x27u, 0x02u},\r
- {0x28u, 0x10u},\r
- {0x2Au, 0x20u},\r
- {0x2Cu, 0x28u},\r
- {0x2Eu, 0x14u},\r
- {0x2Fu, 0x01u},\r
- {0x30u, 0x01u},\r
- {0x31u, 0x01u},\r
- {0x32u, 0x3Cu},\r
- {0x33u, 0x18u},\r
- {0x34u, 0x02u},\r
- {0x36u, 0xC0u},\r
- {0x37u, 0x06u},\r
- {0x3Au, 0x80u},\r
- {0x3Fu, 0x44u},\r
+ {0xAEu, 0x40u},\r
+ {0xAFu, 0x20u},\r
+ {0xB3u, 0x10u},\r
+ {0xB7u, 0x80u},\r
+ {0xC0u, 0xFEu},\r
+ {0xC2u, 0xAFu},\r
+ {0xC4u, 0xFDu},\r
+ {0xCAu, 0xB1u},\r
+ {0xCCu, 0xD3u},\r
+ {0xCEu, 0xFEu},\r
+ {0xD6u, 0x38u},\r
+ {0xD8u, 0x38u},\r
+ {0xE0u, 0x20u},\r
+ {0xE2u, 0x50u},\r
+ {0xECu, 0x10u},\r
+ {0xEEu, 0x2Au},\r
+ {0x04u, 0xFFu},\r
+ {0x05u, 0x01u},\r
+ {0x07u, 0x12u},\r
+ {0x08u, 0x55u},\r
+ {0x0Au, 0xAAu},\r
+ {0x0Du, 0x04u},\r
+ {0x0Fu, 0x28u},\r
+ {0x15u, 0x53u},\r
+ {0x16u, 0xFFu},\r
+ {0x17u, 0xACu},\r
+ {0x18u, 0x0Fu},\r
+ {0x19u, 0x02u},\r
+ {0x1Au, 0xF0u},\r
+ {0x1Bu, 0x41u},\r
+ {0x1Cu, 0x33u},\r
+ {0x1Eu, 0xCCu},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0xFFu},\r
+ {0x23u, 0x84u},\r
+ {0x24u, 0x69u},\r
+ {0x26u, 0x96u},\r
+ {0x2Au, 0xFFu},\r
+ {0x2Cu, 0xFFu},\r
+ {0x31u, 0xC0u},\r
+ {0x33u, 0x30u},\r
+ {0x34u, 0xFFu},\r
+ {0x37u, 0x0Fu},\r
+ {0x3Au, 0x20u},\r
+ {0x3Fu, 0x45u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
+ {0x5Cu, 0x01u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x44u},\r
- {0x83u, 0x08u},\r
- {0x86u, 0x10u},\r
- {0x87u, 0x17u},\r
- {0x8Bu, 0x40u},\r
- {0x8Cu, 0x0Au},\r
- {0x8Du, 0x4Au},\r
- {0x8Eu, 0x05u},\r
- {0x8Fu, 0x05u},\r
- {0x91u, 0x10u},\r
- {0x92u, 0x20u},\r
- {0x93u, 0x20u},\r
- {0x94u, 0x09u},\r
- {0x96u, 0x02u},\r
- {0x97u, 0x20u},\r
- {0x9Au, 0x07u},\r
- {0xA0u, 0x04u},\r
- {0xA2u, 0x08u},\r
- {0xA5u, 0x49u},\r
- {0xA7u, 0x02u},\r
- {0xAAu, 0x08u},\r
- {0xABu, 0x08u},\r
- {0xACu, 0x10u},\r
- {0xAEu, 0x20u},\r
- {0xB0u, 0x30u},\r
- {0xB1u, 0x30u},\r
- {0xB3u, 0x0Fu},\r
- {0xB4u, 0x0Fu},\r
- {0xB7u, 0x40u},\r
- {0xBEu, 0x01u},\r
- {0xBFu, 0x41u},\r
+ {0x80u, 0xFFu},\r
+ {0x81u, 0xFFu},\r
+ {0x85u, 0x30u},\r
+ {0x86u, 0xFFu},\r
+ {0x87u, 0xC0u},\r
+ {0x88u, 0x03u},\r
+ {0x89u, 0x50u},\r
+ {0x8Au, 0x0Cu},\r
+ {0x8Bu, 0xA0u},\r
+ {0x8Du, 0x05u},\r
+ {0x8Fu, 0x0Au},\r
+ {0x90u, 0x05u},\r
+ {0x91u, 0x60u},\r
+ {0x92u, 0x0Au},\r
+ {0x93u, 0x90u},\r
+ {0x94u, 0x0Fu},\r
+ {0x96u, 0xF0u},\r
+ {0x99u, 0x03u},\r
+ {0x9Bu, 0x0Cu},\r
+ {0x9Cu, 0x09u},\r
+ {0x9Eu, 0x06u},\r
+ {0x9Fu, 0xFFu},\r
+ {0xA0u, 0xFFu},\r
+ {0xA1u, 0x06u},\r
+ {0xA3u, 0x09u},\r
+ {0xA4u, 0x30u},\r
+ {0xA6u, 0xC0u},\r
+ {0xA7u, 0xFFu},\r
+ {0xA8u, 0x50u},\r
+ {0xA9u, 0x0Fu},\r
+ {0xAAu, 0xA0u},\r
+ {0xABu, 0xF0u},\r
+ {0xACu, 0x90u},\r
+ {0xAEu, 0x60u},\r
+ {0xB2u, 0xFFu},\r
+ {0xB7u, 0xFFu},\r
+ {0xBEu, 0x04u},\r
+ {0xBFu, 0x40u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x84u},\r
- {0x01u, 0x08u},\r
- {0x02u, 0x40u},\r
- {0x04u, 0x40u},\r
- {0x06u, 0x10u},\r
- {0x09u, 0x08u},\r
- {0x0Au, 0x05u},\r
- {0x0Du, 0x08u},\r
- {0x0Eu, 0x48u},\r
- {0x10u, 0x54u},\r
- {0x11u, 0x80u},\r
- {0x15u, 0x85u},\r
- {0x16u, 0x24u},\r
- {0x19u, 0x0Au},\r
- {0x1Au, 0x05u},\r
- {0x1Bu, 0x40u},\r
- {0x1Eu, 0x08u},\r
- {0x1Fu, 0x21u},\r
- {0x20u, 0x82u},\r
- {0x22u, 0x04u},\r
- {0x25u, 0x06u},\r
- {0x26u, 0x88u},\r
+ {0x01u, 0x09u},\r
+ {0x03u, 0x48u},\r
+ {0x05u, 0x20u},\r
+ {0x06u, 0x20u},\r
+ {0x08u, 0x04u},\r
+ {0x0Au, 0x01u},\r
+ {0x0Bu, 0x80u},\r
+ {0x0Cu, 0x08u},\r
+ {0x0Eu, 0x04u},\r
+ {0x0Fu, 0x22u},\r
+ {0x11u, 0x54u},\r
+ {0x13u, 0x02u},\r
+ {0x14u, 0x20u},\r
+ {0x15u, 0x22u},\r
+ {0x17u, 0x80u},\r
+ {0x18u, 0x20u},\r
+ {0x1Eu, 0x04u},\r
+ {0x22u, 0x40u},\r
+ {0x25u, 0x02u},\r
+ {0x26u, 0x80u},\r
+ {0x27u, 0x23u},\r
+ {0x28u, 0x04u},\r
{0x29u, 0x08u},\r
- {0x2Au, 0x40u},\r
- {0x2Bu, 0x80u},\r
- {0x2Cu, 0x60u},\r
- {0x2Du, 0x02u},\r
- {0x2Eu, 0x10u},\r
- {0x30u, 0x80u},\r
- {0x31u, 0x20u},\r
- {0x34u, 0x08u},\r
- {0x37u, 0x01u},\r
- {0x39u, 0x80u},\r
- {0x3Cu, 0x40u},\r
- {0x3Du, 0x89u},\r
- {0x3Eu, 0x20u},\r
- {0x58u, 0x80u},\r
- {0x5Du, 0x40u},\r
- {0x62u, 0x40u},\r
- {0x64u, 0x02u},\r
- {0x65u, 0x80u},\r
- {0x69u, 0x80u},\r
- {0x6Au, 0x80u},\r
- {0x6Bu, 0x01u},\r
- {0x81u, 0x40u},\r
- {0x82u, 0x24u},\r
- {0x83u, 0x10u},\r
- {0x84u, 0x01u},\r
- {0x85u, 0x02u},\r
- {0x86u, 0x08u},\r
- {0x88u, 0x10u},\r
- {0x8Cu, 0x02u},\r
+ {0x2Au, 0x02u},\r
+ {0x2Cu, 0x80u},\r
+ {0x30u, 0x10u},\r
+ {0x32u, 0x80u},\r
+ {0x33u, 0x02u},\r
+ {0x34u, 0x04u},\r
+ {0x36u, 0x10u},\r
+ {0x39u, 0x15u},\r
+ {0x3Bu, 0x80u},\r
+ {0x3Cu, 0x80u},\r
+ {0x3Fu, 0x08u},\r
+ {0x5Au, 0x40u},\r
+ {0x5Eu, 0x80u},\r
+ {0x61u, 0xC0u},\r
+ {0x64u, 0x01u},\r
+ {0x67u, 0x01u},\r
+ {0x6Cu, 0x80u},\r
+ {0x6Du, 0x54u},\r
+ {0x6Fu, 0x02u},\r
+ {0x74u, 0x66u},\r
+ {0x85u, 0x04u},\r
+ {0x88u, 0x20u},\r
+ {0x89u, 0x03u},\r
+ {0x8Cu, 0x80u},\r
{0x8Du, 0x10u},\r
- {0x8Eu, 0x10u},\r
- {0xC0u, 0xADu},\r
- {0xC2u, 0x77u},\r
- {0xC4u, 0xDFu},\r
- {0xCAu, 0x6Bu},\r
- {0xCCu, 0xCCu},\r
- {0xCEu, 0xF8u},\r
+ {0x8Fu, 0x10u},\r
+ {0x91u, 0xA0u},\r
+ {0x92u, 0x41u},\r
+ {0x93u, 0x84u},\r
+ {0x94u, 0x22u},\r
+ {0x96u, 0x80u},\r
+ {0x99u, 0x04u},\r
+ {0x9Au, 0x20u},\r
+ {0x9Cu, 0x81u},\r
+ {0x9Du, 0x40u},\r
+ {0x9Eu, 0x80u},\r
+ {0x9Fu, 0x84u},\r
+ {0xA1u, 0x10u},\r
+ {0xA2u, 0x10u},\r
+ {0xA4u, 0x08u},\r
+ {0xA9u, 0x02u},\r
+ {0xAFu, 0x04u},\r
+ {0xB1u, 0x80u},\r
+ {0xB5u, 0x08u},\r
+ {0xC0u, 0x6Eu},\r
+ {0xC2u, 0xEDu},\r
+ {0xC4u, 0xFFu},\r
+ {0xCAu, 0x87u},\r
+ {0xCCu, 0x6Du},\r
+ {0xCEu, 0x5Fu},\r
{0xD6u, 0x18u},\r
{0xD8u, 0x18u},\r
- {0xE0u, 0x60u},\r
- {0xE2u, 0x10u},\r
- {0xE4u, 0x10u},\r
- {0xE6u, 0x04u},\r
- {0x01u, 0x5Cu},\r
- {0x05u, 0x11u},\r
- {0x07u, 0x22u},\r
- {0x09u, 0x50u},\r
- {0x0Bu, 0x0Cu},\r
- {0x0Du, 0x0Cu},\r
- {0x0Fu, 0x50u},\r
- {0x15u, 0x30u},\r
- {0x17u, 0x0Fu},\r
- {0x19u, 0x54u},\r
+ {0xE0u, 0xF0u},\r
+ {0xE6u, 0x18u},\r
+ {0xE8u, 0x40u},\r
+ {0xEAu, 0x20u},\r
+ {0xECu, 0x80u},\r
+ {0xEEu, 0x01u},\r
+ {0x01u, 0x10u},\r
+ {0x02u, 0x07u},\r
+ {0x05u, 0x08u},\r
+ {0x07u, 0x06u},\r
+ {0x09u, 0x10u},\r
+ {0x0Du, 0x08u},\r
+ {0x0Eu, 0x10u},\r
+ {0x0Fu, 0x04u},\r
+ {0x10u, 0x04u},\r
+ {0x12u, 0x08u},\r
+ {0x15u, 0x10u},\r
+ {0x19u, 0x04u},\r
{0x1Bu, 0x08u},\r
- {0x1Du, 0x5Cu},\r
+ {0x1Du, 0x10u},\r
+ {0x1Eu, 0x20u},\r
{0x21u, 0x08u},\r
- {0x27u, 0x40u},\r
- {0x29u, 0x21u},\r
- {0x2Bu, 0x1Eu},\r
- {0x2Du, 0x24u},\r
- {0x2Fu, 0x10u},\r
- {0x31u, 0x30u},\r
- {0x33u, 0x40u},\r
- {0x35u, 0x0Fu},\r
- {0x3Bu, 0x02u},\r
+ {0x22u, 0x08u},\r
+ {0x23u, 0x04u},\r
+ {0x28u, 0x09u},\r
+ {0x29u, 0x08u},\r
+ {0x2Au, 0x02u},\r
+ {0x2Bu, 0x04u},\r
+ {0x2Cu, 0x0Au},\r
+ {0x2Eu, 0x05u},\r
+ {0x2Fu, 0x01u},\r
+ {0x30u, 0x20u},\r
+ {0x31u, 0x02u},\r
+ {0x33u, 0x10u},\r
+ {0x34u, 0x10u},\r
+ {0x35u, 0x0Cu},\r
+ {0x36u, 0x0Fu},\r
+ {0x37u, 0x01u},\r
+ {0x39u, 0x08u},\r
+ {0x3Bu, 0x20u},\r
{0x3Fu, 0x04u},\r
- {0x40u, 0x23u},\r
- {0x41u, 0x06u},\r
- {0x42u, 0x40u},\r
- {0x44u, 0x01u},\r
- {0x45u, 0xBDu},\r
- {0x46u, 0xF0u},\r
- {0x47u, 0xCEu},\r
- {0x48u, 0x3Bu},\r
- {0x49u, 0xFFu},\r
- {0x4Au, 0xFFu},\r
- {0x4Bu, 0xFFu},\r
- {0x4Cu, 0x22u},\r
- {0x4Eu, 0xF0u},\r
- {0x4Fu, 0x08u},\r
- {0x50u, 0x04u},\r
- {0x54u, 0x40u},\r
- {0x56u, 0x04u},\r
+ {0x56u, 0x08u},\r
+ {0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Au, 0x04u},\r
{0x5Bu, 0x04u},\r
+ {0x5Cu, 0x11u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x62u, 0xC0u},\r
- {0x64u, 0x40u},\r
- {0x65u, 0x01u},\r
- {0x66u, 0x10u},\r
- {0x67u, 0x11u},\r
- {0x68u, 0xC0u},\r
- {0x69u, 0x01u},\r
- {0x6Bu, 0x11u},\r
- {0x6Cu, 0x40u},\r
- {0x6Du, 0x01u},\r
- {0x6Eu, 0x40u},\r
- {0x6Fu, 0x01u},\r
- {0x80u, 0x20u},\r
- {0x82u, 0x01u},\r
- {0x84u, 0x10u},\r
- {0x85u, 0x04u},\r
- {0x86u, 0x42u},\r
- {0x87u, 0x23u},\r
- {0x89u, 0x48u},\r
- {0x8Bu, 0x03u},\r
- {0x8Cu, 0x02u},\r
- {0x90u, 0x02u},\r
- {0x91u, 0x80u},\r
- {0x94u, 0x44u},\r
- {0x96u, 0x10u},\r
- {0x97u, 0x7Cu},\r
- {0x98u, 0x02u},\r
- {0x99u, 0x11u},\r
- {0x9Bu, 0x02u},\r
- {0x9Cu, 0x02u},\r
- {0xA0u, 0x08u},\r
- {0xA3u, 0x02u},\r
- {0xA5u, 0x80u},\r
- {0xA8u, 0x0Eu},\r
- {0xA9u, 0x70u},\r
- {0xAAu, 0x30u},\r
- {0xACu, 0x02u},\r
- {0xAFu, 0x01u},\r
- {0xB0u, 0x01u},\r
- {0xB3u, 0x70u},\r
- {0xB4u, 0x7Eu},\r
- {0xB5u, 0x0Fu},\r
- {0xB7u, 0x80u},\r
- {0xB8u, 0x20u},\r
+ {0x81u, 0x96u},\r
+ {0x83u, 0x69u},\r
+ {0x84u, 0xAAu},\r
+ {0x86u, 0x55u},\r
+ {0x87u, 0xFFu},\r
+ {0x89u, 0xFFu},\r
+ {0x8Au, 0x80u},\r
+ {0x8Du, 0x55u},\r
+ {0x8Fu, 0xAAu},\r
+ {0x91u, 0x33u},\r
+ {0x93u, 0xCCu},\r
+ {0x95u, 0x0Fu},\r
+ {0x96u, 0x70u},\r
+ {0x97u, 0xF0u},\r
+ {0x9Bu, 0xFFu},\r
+ {0x9Du, 0xFFu},\r
+ {0x9Eu, 0x07u},\r
+ {0xA0u, 0x99u},\r
+ {0xA2u, 0x22u},\r
+ {0xA6u, 0x08u},\r
+ {0xA8u, 0x44u},\r
+ {0xAAu, 0x88u},\r
+ {0xABu, 0xFFu},\r
+ {0xB2u, 0xF0u},\r
+ {0xB5u, 0xFFu},\r
+ {0xB6u, 0x0Fu},\r
+ {0xBBu, 0x20u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x11u},\r
+ {0xDFu, 0x01u},\r
+ {0x03u, 0x82u},\r
+ {0x05u, 0x20u},\r
+ {0x06u, 0x20u},\r
+ {0x09u, 0x01u},\r
+ {0x0Au, 0x02u},\r
+ {0x0Eu, 0x22u},\r
+ {0x10u, 0x0Au},\r
+ {0x12u, 0x80u},\r
+ {0x14u, 0x80u},\r
+ {0x15u, 0x04u},\r
+ {0x16u, 0x08u},\r
+ {0x19u, 0x11u},\r
+ {0x1Au, 0x01u},\r
+ {0x1Bu, 0x82u},\r
+ {0x1Eu, 0x22u},\r
+ {0x1Fu, 0x40u},\r
+ {0x20u, 0x60u},\r
+ {0x21u, 0x50u},\r
+ {0x22u, 0x31u},\r
+ {0x23u, 0x04u},\r
+ {0x25u, 0x10u},\r
+ {0x27u, 0x08u},\r
+ {0x29u, 0x51u},\r
+ {0x2Cu, 0x08u},\r
+ {0x32u, 0x50u},\r
+ {0x33u, 0x04u},\r
+ {0x34u, 0x01u},\r
+ {0x36u, 0x20u},\r
+ {0x37u, 0x88u},\r
+ {0x38u, 0x66u},\r
+ {0x3Eu, 0xA8u},\r
+ {0x3Fu, 0x02u},\r
+ {0x58u, 0x60u},\r
+ {0x5Du, 0x8Au},\r
+ {0x5Fu, 0x10u},\r
+ {0x60u, 0x04u},\r
+ {0x63u, 0x02u},\r
+ {0x67u, 0x01u},\r
+ {0x80u, 0x02u},\r
+ {0x81u, 0x01u},\r
+ {0x82u, 0x28u},\r
+ {0x83u, 0x01u},\r
+ {0x84u, 0x30u},\r
+ {0x85u, 0x20u},\r
+ {0x88u, 0x40u},\r
+ {0x89u, 0x04u},\r
+ {0x8Bu, 0x10u},\r
+ {0x8Du, 0x04u},\r
+ {0x8Eu, 0xC0u},\r
+ {0xC0u, 0x69u},\r
+ {0xC2u, 0xA9u},\r
+ {0xC4u, 0x7Bu},\r
+ {0xCAu, 0x2Du},\r
+ {0xCCu, 0xFEu},\r
+ {0xCEu, 0xFFu},\r
+ {0xD6u, 0xFCu},\r
+ {0xD8u, 0x1Cu},\r
+ {0xE0u, 0x70u},\r
+ {0xE4u, 0x80u},\r
+ {0xE6u, 0x08u},\r
+ {0x85u, 0x0Bu},\r
+ {0x86u, 0x82u},\r
+ {0x87u, 0x24u},\r
+ {0x88u, 0x04u},\r
+ {0x89u, 0x15u},\r
+ {0x8Au, 0x23u},\r
+ {0x8Bu, 0x0Au},\r
+ {0x8Cu, 0x70u},\r
+ {0x91u, 0x30u},\r
+ {0x95u, 0x04u},\r
+ {0x96u, 0x7Cu},\r
+ {0x97u, 0x03u},\r
+ {0x9Au, 0x01u},\r
+ {0x9Cu, 0x11u},\r
+ {0x9Eu, 0x02u},\r
+ {0xA1u, 0x09u},\r
+ {0xA3u, 0x16u},\r
+ {0xA4u, 0x48u},\r
+ {0xA6u, 0x03u},\r
+ {0xB2u, 0x0Fu},\r
+ {0xB3u, 0x07u},\r
+ {0xB4u, 0x80u},\r
+ {0xB6u, 0x70u},\r
+ {0xB7u, 0x38u},\r
{0xB9u, 0x80u},\r
- {0xBEu, 0x10u},\r
- {0xBFu, 0x04u},\r
+ {0xBBu, 0x08u},\r
+ {0xBEu, 0x40u},\r
+ {0xD6u, 0x02u},\r
+ {0xD7u, 0x28u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x04u, 0x04u},\r
- {0x05u, 0x02u},\r
- {0x06u, 0x02u},\r
- {0x0Cu, 0xA1u},\r
- {0x0Du, 0x08u},\r
- {0x0Fu, 0x40u},\r
- {0x15u, 0x60u},\r
- {0x17u, 0x02u},\r
- {0x1Fu, 0x22u},\r
- {0x20u, 0x18u},\r
- {0x21u, 0x10u},\r
- {0x22u, 0x20u},\r
- {0x23u, 0x44u},\r
- {0x26u, 0x84u},\r
- {0x27u, 0x0Au},\r
- {0x28u, 0x01u},\r
- {0x29u, 0x04u},\r
- {0x2Au, 0x01u},\r
- {0x2Bu, 0x04u},\r
- {0x2Du, 0x02u},\r
- {0x2Eu, 0x20u},\r
- {0x2Fu, 0x22u},\r
- {0x30u, 0xA0u},\r
- {0x31u, 0x08u},\r
- {0x36u, 0x21u},\r
- {0x37u, 0x08u},\r
- {0x39u, 0x50u},\r
- {0x3Au, 0x02u},\r
- {0x3Bu, 0x04u},\r
- {0x3Cu, 0x24u},\r
- {0x40u, 0x04u},\r
- {0x41u, 0x09u},\r
- {0x42u, 0x01u},\r
+ {0x01u, 0x48u},\r
+ {0x03u, 0x40u},\r
+ {0x05u, 0x20u},\r
+ {0x06u, 0x10u},\r
+ {0x07u, 0x01u},\r
+ {0x0Au, 0x41u},\r
+ {0x0Bu, 0x14u},\r
+ {0x0Eu, 0x19u},\r
+ {0x10u, 0x28u},\r
+ {0x13u, 0x02u},\r
+ {0x15u, 0x08u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x08u},\r
+ {0x1Au, 0x42u},\r
+ {0x1Eu, 0x18u},\r
+ {0x1Fu, 0x80u},\r
+ {0x21u, 0x80u},\r
+ {0x26u, 0x08u},\r
+ {0x27u, 0x11u},\r
+ {0x2Au, 0x82u},\r
+ {0x2Bu, 0x10u},\r
+ {0x2Eu, 0x01u},\r
+ {0x30u, 0x06u},\r
+ {0x32u, 0xA0u},\r
+ {0x36u, 0x08u},\r
+ {0x37u, 0x01u},\r
+ {0x3Fu, 0x14u},\r
+ {0x40u, 0x06u},\r
+ {0x41u, 0x04u},\r
+ {0x46u, 0x08u},\r
+ {0x47u, 0x10u},\r
{0x48u, 0x04u},\r
- {0x49u, 0x06u},\r
- {0x51u, 0x20u},\r
- {0x52u, 0x01u},\r
- {0x53u, 0x04u},\r
- {0x60u, 0x92u},\r
- {0x61u, 0x20u},\r
- {0x82u, 0x20u},\r
- {0x84u, 0x04u},\r
- {0x86u, 0x01u},\r
- {0x8Cu, 0x02u},\r
- {0x8Du, 0x04u},\r
- {0x8Eu, 0x04u},\r
- {0x90u, 0x04u},\r
- {0x91u, 0x52u},\r
- {0x97u, 0x48u},\r
- {0x9Au, 0x02u},\r
- {0x9Cu, 0x80u},\r
- {0x9Du, 0x02u},\r
- {0x9Eu, 0x01u},\r
- {0xA0u, 0xB0u},\r
- {0xA1u, 0x08u},\r
- {0xA2u, 0x01u},\r
- {0xA3u, 0x04u},\r
- {0xA6u, 0xA0u},\r
- {0xABu, 0x01u},\r
- {0xB2u, 0x08u},\r
- {0xB3u, 0x20u},\r
- {0xB4u, 0x04u},\r
- {0xC0u, 0xB0u},\r
- {0xC2u, 0xF0u},\r
- {0xC4u, 0xD0u},\r
- {0xCAu, 0xFFu},\r
- {0xCCu, 0xEEu},\r
- {0xCEu, 0x6Fu},\r
- {0xD0u, 0x0Fu},\r
- {0xD2u, 0x04u},\r
- {0xD8u, 0x0Fu},\r
- {0xE2u, 0x44u},\r
- {0xE4u, 0x02u},\r
- {0xE8u, 0x01u},\r
- {0x00u, 0x03u},\r
- {0x01u, 0xC0u},\r
- {0x02u, 0x0Cu},\r
- {0x03u, 0x01u},\r
- {0x04u, 0x05u},\r
- {0x06u, 0x0Au},\r
- {0x07u, 0xFFu},\r
- {0x08u, 0x40u},\r
- {0x09u, 0xC0u},\r
- {0x0Au, 0x1Fu},\r
+ {0x49u, 0x64u},\r
+ {0x4Bu, 0x02u},\r
+ {0x51u, 0x01u},\r
+ {0x52u, 0x11u},\r
+ {0x53u, 0x48u},\r
+ {0x66u, 0x08u},\r
+ {0x6Cu, 0x38u},\r
+ {0x6Du, 0x44u},\r
+ {0x6Eu, 0x20u},\r
+ {0x6Fu, 0x60u},\r
+ {0x77u, 0x02u},\r
+ {0x82u, 0x80u},\r
+ {0x83u, 0x80u},\r
+ {0x89u, 0x80u},\r
+ {0x8Cu, 0x02u},\r
+ {0x8Du, 0x10u},\r
+ {0x8Eu, 0x40u},\r
+ {0x8Fu, 0x01u},\r
+ {0x91u, 0x08u},\r
+ {0x92u, 0x01u},\r
+ {0x93u, 0x14u},\r
+ {0x94u, 0x20u},\r
+ {0x95u, 0x46u},\r
+ {0x96u, 0x02u},\r
+ {0x97u, 0x80u},\r
+ {0x98u, 0x04u},\r
+ {0x99u, 0x40u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Du, 0x14u},\r
+ {0x9Eu, 0x11u},\r
+ {0x9Fu, 0x42u},\r
+ {0xA0u, 0x06u},\r
+ {0xA2u, 0xA0u},\r
+ {0xA3u, 0x10u},\r
+ {0xA4u, 0x28u},\r
+ {0xA6u, 0x10u},\r
+ {0xA7u, 0x28u},\r
+ {0xC0u, 0xEDu},\r
+ {0xC2u, 0xEFu},\r
+ {0xC4u, 0x2Eu},\r
+ {0xCAu, 0x8Bu},\r
+ {0xCCu, 0xCFu},\r
+ {0xCEu, 0x60u},\r
+ {0xD0u, 0x0Eu},\r
+ {0xD2u, 0x0Cu},\r
+ {0xD8u, 0x40u},\r
+ {0xE0u, 0x10u},\r
+ {0xE2u, 0x01u},\r
+ {0xE6u, 0x40u},\r
+ {0x00u, 0xC0u},\r
+ {0x01u, 0x01u},\r
+ {0x02u, 0x02u},\r
+ {0x05u, 0x08u},\r
+ {0x06u, 0x9Fu},\r
+ {0x07u, 0x21u},\r
+ {0x08u, 0xC0u},\r
+ {0x09u, 0x22u},\r
+ {0x0Au, 0x04u},\r
{0x0Bu, 0x08u},\r
- {0x0Cu, 0x10u},\r
- {0x0Du, 0x80u},\r
- {0x0Eu, 0x2Fu},\r
- {0x13u, 0x9Fu},\r
- {0x14u, 0x06u},\r
- {0x15u, 0x7Fu},\r
- {0x16u, 0x09u},\r
- {0x17u, 0x80u},\r
- {0x19u, 0x1Fu},\r
- {0x1Au, 0x70u},\r
- {0x1Bu, 0x20u},\r
- {0x1Fu, 0x60u},\r
- {0x21u, 0xC0u},\r
- {0x23u, 0x02u},\r
- {0x24u, 0x20u},\r
- {0x25u, 0xC0u},\r
- {0x26u, 0x4Fu},\r
- {0x27u, 0x04u},\r
- {0x28u, 0x0Fu},\r
- {0x2Du, 0x90u},\r
- {0x2Fu, 0x40u},\r
- {0x31u, 0xFFu},\r
- {0x34u, 0x7Fu},\r
- {0x3Fu, 0x01u},\r
+ {0x0Cu, 0x1Fu},\r
+ {0x0Du, 0x04u},\r
+ {0x0Eu, 0x20u},\r
+ {0x11u, 0x01u},\r
+ {0x12u, 0x60u},\r
+ {0x14u, 0xC0u},\r
+ {0x15u, 0x40u},\r
+ {0x16u, 0x08u},\r
+ {0x19u, 0x40u},\r
+ {0x1Au, 0xFFu},\r
+ {0x1Cu, 0x80u},\r
+ {0x1Du, 0x01u},\r
+ {0x20u, 0xC0u},\r
+ {0x21u, 0x07u},\r
+ {0x22u, 0x01u},\r
+ {0x23u, 0x18u},\r
+ {0x24u, 0x7Fu},\r
+ {0x25u, 0x01u},\r
+ {0x26u, 0x80u},\r
+ {0x29u, 0x10u},\r
+ {0x2Cu, 0x90u},\r
+ {0x2Du, 0x01u},\r
+ {0x2Eu, 0x40u},\r
+ {0x33u, 0x3Fu},\r
+ {0x34u, 0xFFu},\r
+ {0x37u, 0x40u},\r
+ {0x39u, 0x88u},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x04u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Cu, 0x01u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0xFFu},\r
+ {0x80u, 0x65u},\r
{0x81u, 0x04u},\r
- {0x83u, 0x20u},\r
- {0x84u, 0x33u},\r
- {0x85u, 0x39u},\r
- {0x86u, 0xCCu},\r
- {0x87u, 0x06u},\r
- {0x88u, 0x0Fu},\r
- {0x8Au, 0xF0u},\r
- {0x8Bu, 0x46u},\r
- {0x8Du, 0x46u},\r
- {0x8Eu, 0xFFu},\r
- {0x90u, 0x69u},\r
- {0x92u, 0x96u},\r
- {0x95u, 0x01u},\r
- {0x97u, 0x5Eu},\r
- {0x98u, 0x55u},\r
- {0x99u, 0x42u},\r
- {0x9Au, 0xAAu},\r
- {0x9Bu, 0x04u},\r
- {0x9Du, 0x46u},\r
- {0xA1u, 0x46u},\r
- {0xA2u, 0xFFu},\r
- {0xA4u, 0xFFu},\r
- {0xA5u, 0x77u},\r
- {0xA7u, 0x08u},\r
- {0xAAu, 0xFFu},\r
- {0xADu, 0x42u},\r
- {0xB3u, 0x70u},\r
- {0xB4u, 0xFFu},\r
- {0xB5u, 0x0Fu},\r
- {0xB9u, 0x20u},\r
- {0xBAu, 0x20u},\r
- {0xBBu, 0x0Cu},\r
- {0xD6u, 0x02u},\r
- {0xD7u, 0x20u},\r
+ {0x83u, 0x12u},\r
+ {0x84u, 0x25u},\r
+ {0x86u, 0x40u},\r
+ {0x88u, 0x22u},\r
+ {0x8Au, 0x01u},\r
+ {0x8Cu, 0x60u},\r
+ {0x8Du, 0x04u},\r
+ {0x8Eu, 0x05u},\r
+ {0x8Fu, 0x0Au},\r
+ {0x92u, 0x04u},\r
+ {0x94u, 0x03u},\r
+ {0x95u, 0x02u},\r
+ {0x96u, 0x78u},\r
+ {0x97u, 0x04u},\r
+ {0x98u, 0x0Au},\r
+ {0x99u, 0x04u},\r
+ {0x9Au, 0x71u},\r
+ {0x9Bu, 0x02u},\r
+ {0x9Cu, 0x09u},\r
+ {0x9Du, 0x04u},\r
+ {0x9Eu, 0x12u},\r
+ {0x9Fu, 0x03u},\r
+ {0xA0u, 0x65u},\r
+ {0xA8u, 0x05u},\r
+ {0xAAu, 0x60u},\r
+ {0xACu, 0x40u},\r
+ {0xB0u, 0x03u},\r
+ {0xB1u, 0x10u},\r
+ {0xB2u, 0x04u},\r
+ {0xB3u, 0x06u},\r
+ {0xB4u, 0x03u},\r
+ {0xB5u, 0x01u},\r
+ {0xB6u, 0x78u},\r
+ {0xB7u, 0x08u},\r
+ {0xBAu, 0x22u},\r
+ {0xBBu, 0x08u},\r
+ {0xBEu, 0x04u},\r
+ {0xD4u, 0x40u},\r
+ {0xD6u, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x01u},\r
+ {0xDCu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x01u},\r
- {0x01u, 0x20u},\r
- {0x02u, 0x10u},\r
- {0x03u, 0x01u},\r
- {0x04u, 0x2Au},\r
- {0x06u, 0x04u},\r
- {0x07u, 0x01u},\r
+ {0x01u, 0x64u},\r
+ {0x03u, 0x40u},\r
+ {0x04u, 0x20u},\r
+ {0x05u, 0x40u},\r
+ {0x06u, 0x10u},\r
+ {0x07u, 0x40u},\r
{0x08u, 0x02u},\r
- {0x09u, 0x20u},\r
- {0x0Eu, 0x28u},\r
- {0x11u, 0x05u},\r
- {0x12u, 0x04u},\r
- {0x15u, 0x04u},\r
- {0x17u, 0x10u},\r
- {0x18u, 0x08u},\r
- {0x19u, 0x20u},\r
+ {0x0Au, 0x01u},\r
+ {0x0Bu, 0x94u},\r
+ {0x0Eu, 0xA0u},\r
+ {0x0Fu, 0x06u},\r
+ {0x10u, 0x08u},\r
+ {0x12u, 0x01u},\r
+ {0x13u, 0x02u},\r
+ {0x15u, 0x48u},\r
+ {0x17u, 0x03u},\r
+ {0x18u, 0x10u},\r
+ {0x19u, 0x61u},\r
+ {0x1Au, 0x01u},\r
+ {0x1Bu, 0x81u},\r
{0x1Eu, 0x08u},\r
- {0x1Fu, 0x20u},\r
- {0x20u, 0x2Cu},\r
+ {0x20u, 0x60u},\r
{0x21u, 0x08u},\r
- {0x22u, 0x08u},\r
- {0x26u, 0x01u},\r
- {0x28u, 0x10u},\r
- {0x2Au, 0x82u},\r
- {0x2Cu, 0xA0u},\r
+ {0x22u, 0x50u},\r
+ {0x25u, 0x40u},\r
+ {0x26u, 0x40u},\r
+ {0x27u, 0x20u},\r
{0x2Du, 0x40u},\r
- {0x30u, 0xA0u},\r
+ {0x2Fu, 0xA8u},\r
{0x31u, 0x08u},\r
- {0x34u, 0x10u},\r
- {0x35u, 0x02u},\r
- {0x36u, 0xA8u},\r
- {0x37u, 0x08u},\r
- {0x38u, 0x04u},\r
- {0x39u, 0x50u},\r
- {0x3Au, 0x01u},\r
- {0x3Bu, 0x01u},\r
- {0x3Cu, 0x04u},\r
- {0x3Eu, 0x92u},\r
- {0x3Fu, 0x48u},\r
- {0x63u, 0x02u},\r
- {0x68u, 0xA8u},\r
- {0x69u, 0x50u},\r
- {0x6Au, 0x10u},\r
- {0x72u, 0x02u},\r
+ {0x32u, 0x50u},\r
+ {0x36u, 0x04u},\r
+ {0x37u, 0x62u},\r
+ {0x38u, 0x40u},\r
+ {0x3Bu, 0x02u},\r
+ {0x3Du, 0x80u},\r
+ {0x3Fu, 0x16u},\r
+ {0x5Cu, 0x80u},\r
+ {0x60u, 0x12u},\r
+ {0x61u, 0x10u},\r
+ {0x63u, 0x80u},\r
+ {0x67u, 0x02u},\r
{0x88u, 0x80u},\r
- {0x8Bu, 0x04u},\r
- {0x90u, 0x23u},\r
- {0x91u, 0x07u},\r
- {0x95u, 0x40u},\r
- {0x98u, 0x02u},\r
- {0x9Au, 0x10u},\r
- {0x9Bu, 0x11u},\r
- {0x9Eu, 0x02u},\r
- {0x9Fu, 0x08u},\r
- {0xA1u, 0x20u},\r
- {0xA2u, 0x10u},\r
- {0xA3u, 0x01u},\r
- {0xA4u, 0xACu},\r
- {0xA6u, 0x20u},\r
- {0xABu, 0x58u},\r
- {0xB1u, 0x01u},\r
- {0xB3u, 0x04u},\r
- {0xB4u, 0x80u},\r
- {0xB6u, 0x10u},\r
+ {0x8Fu, 0x40u},\r
+ {0x91u, 0x08u},\r
+ {0x93u, 0x14u},\r
+ {0x95u, 0x42u},\r
+ {0x96u, 0x02u},\r
+ {0x98u, 0x04u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Du, 0x45u},\r
+ {0x9Fu, 0x41u},\r
+ {0xA0u, 0x06u},\r
+ {0xA2u, 0xA0u},\r
+ {0xA3u, 0x10u},\r
+ {0xA4u, 0x38u},\r
+ {0xB0u, 0x02u},\r
+ {0xB3u, 0x08u},\r
+ {0xB6u, 0x11u},\r
+ {0xB7u, 0x20u},\r
{0xC0u, 0xFFu},\r
- {0xC2u, 0x6Au},\r
- {0xC4u, 0x6Eu},\r
- {0xCAu, 0xDBu},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0xBBu},\r
+ {0xCAu, 0xF0u},\r
{0xCCu, 0xFEu},\r
- {0xCEu, 0xFFu},\r
- {0xD8u, 0x08u},\r
- {0xE2u, 0x28u},\r
- {0xE8u, 0x04u},\r
- {0xEEu, 0x01u},\r
- {0x39u, 0x20u},\r
- {0x3Fu, 0x10u},\r
- {0x59u, 0x04u},\r
- {0x5Fu, 0x01u},\r
- {0x27u, 0x08u},\r
- {0x87u, 0x08u},\r
- {0x88u, 0x08u},\r
- {0x90u, 0x04u},\r
- {0x96u, 0x10u},\r
- {0x97u, 0x80u},\r
- {0x9Cu, 0x18u},\r
- {0x9Du, 0xC0u},\r
- {0xA6u, 0x20u},\r
- {0xA7u, 0x40u},\r
- {0xA8u, 0x04u},\r
- {0xA9u, 0x04u},\r
- {0xAAu, 0x01u},\r
- {0xB0u, 0x02u},\r
- {0xB1u, 0x02u},\r
- {0xB5u, 0x10u},\r
- {0xE0u, 0x80u},\r
- {0xE8u, 0xE0u},\r
- {0xEAu, 0x10u},\r
- {0x80u, 0x04u},\r
- {0x84u, 0x10u},\r
- {0x86u, 0x20u},\r
- {0x90u, 0x04u},\r
- {0x9Cu, 0x10u},\r
- {0xA6u, 0x20u},\r
- {0xAAu, 0x10u},\r
- {0xB1u, 0xC0u},\r
- {0xB3u, 0x40u},\r
- {0xB7u, 0x40u},\r
- {0xE8u, 0x80u},\r
- {0xECu, 0xC0u},\r
- {0x12u, 0x08u},\r
+ {0xCEu, 0xF9u},\r
+ {0xD6u, 0x10u},\r
+ {0xD8u, 0x1Fu},\r
+ {0xE6u, 0x40u},\r
+ {0xEAu, 0x40u},\r
+ {0xEEu, 0x48u},\r
+ {0x9Cu, 0x80u},\r
+ {0xA0u, 0x20u},\r
+ {0xB0u, 0x04u},\r
+ {0xB4u, 0x20u},\r
+ {0xE2u, 0x20u},\r
+ {0xECu, 0x80u},\r
+ {0xEEu, 0x18u},\r
+ {0x80u, 0x20u},\r
+ {0x88u, 0x80u},\r
+ {0x9Cu, 0x80u},\r
+ {0xA0u, 0x20u},\r
+ {0xE0u, 0x20u},\r
+ {0x13u, 0x20u},\r
{0x16u, 0x80u},\r
- {0x17u, 0x80u},\r
- {0x33u, 0x04u},\r
- {0x35u, 0x08u},\r
+ {0x17u, 0x40u},\r
+ {0x33u, 0x08u},\r
{0x36u, 0x80u},\r
- {0x3Au, 0x81u},\r
- {0x3Du, 0x04u},\r
- {0x3Fu, 0x20u},\r
- {0x43u, 0x20u},\r
- {0x52u, 0x20u},\r
- {0x5Bu, 0x01u},\r
- {0x60u, 0x20u},\r
- {0x64u, 0x08u},\r
- {0x65u, 0x40u},\r
- {0x82u, 0x01u},\r
- {0x85u, 0x40u},\r
- {0x87u, 0x01u},\r
+ {0x37u, 0x08u},\r
+ {0x39u, 0x08u},\r
+ {0x3Au, 0x80u},\r
+ {0x3Cu, 0x04u},\r
+ {0x3Fu, 0x10u},\r
+ {0x41u, 0x20u},\r
+ {0x56u, 0x20u},\r
+ {0x5Au, 0x04u},\r
+ {0x60u, 0x40u},\r
+ {0x65u, 0x01u},\r
+ {0x66u, 0x40u},\r
+ {0x86u, 0x20u},\r
+ {0x8Bu, 0x10u},\r
+ {0x8Eu, 0x40u},\r
{0xC4u, 0xE0u},\r
{0xCCu, 0xE0u},\r
{0xCEu, 0xF0u},\r
{0xD0u, 0x10u},\r
- {0xD4u, 0x20u},\r
+ {0xD4u, 0x40u},\r
{0xD6u, 0xC0u},\r
{0xD8u, 0xC0u},\r
- {0xE2u, 0x60u},\r
- {0xE6u, 0x10u},\r
- {0x33u, 0x18u},\r
- {0x35u, 0x04u},\r
- {0x37u, 0x80u},\r
- {0x39u, 0x80u},\r
- {0x54u, 0x02u},\r
- {0x57u, 0x10u},\r
- {0x5Bu, 0x40u},\r
- {0x63u, 0x80u},\r
- {0x95u, 0x04u},\r
- {0x9Bu, 0xD0u},\r
- {0x9Cu, 0x20u},\r
- {0x9Du, 0x08u},\r
- {0x9Fu, 0x04u},\r
+ {0xE2u, 0x10u},\r
+ {0x30u, 0x20u},\r
+ {0x32u, 0x01u},\r
+ {0x37u, 0x44u},\r
+ {0x3Bu, 0x10u},\r
+ {0x52u, 0x20u},\r
+ {0x56u, 0x20u},\r
+ {0x5Au, 0x40u},\r
+ {0x5Du, 0x02u},\r
+ {0x68u, 0x20u},\r
+ {0x6Bu, 0x20u},\r
+ {0x81u, 0x02u},\r
+ {0x82u, 0x20u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Eu, 0x20u},\r
+ {0x92u, 0x40u},\r
+ {0x94u, 0x44u},\r
+ {0x96u, 0x04u},\r
+ {0x9Bu, 0x60u},\r
+ {0x9Du, 0x01u},\r
+ {0x9Eu, 0x40u},\r
+ {0x9Fu, 0x08u},\r
+ {0xA5u, 0x20u},\r
{0xA6u, 0x80u},\r
- {0xA7u, 0x20u},\r
- {0xA8u, 0x08u},\r
- {0xAAu, 0x08u},\r
- {0xABu, 0x50u},\r
- {0xAEu, 0x20u},\r
- {0xB7u, 0x10u},\r
+ {0xA7u, 0x08u},\r
+ {0xB1u, 0x04u},\r
{0xCCu, 0xF0u},\r
{0xCEu, 0x10u},\r
- {0xD4u, 0xC0u},\r
- {0xD6u, 0x20u},\r
- {0xD8u, 0x40u},\r
- {0xEEu, 0xE0u},\r
+ {0xD4u, 0xE0u},\r
+ {0xD6u, 0x80u},\r
+ {0xE6u, 0xA0u},\r
{0x12u, 0x80u},\r
- {0x32u, 0x10u},\r
- {0x82u, 0x10u},\r
- {0x83u, 0x50u},\r
- {0x85u, 0x08u},\r
- {0x8Bu, 0x08u},\r
- {0x8Cu, 0x20u},\r
- {0x95u, 0x84u},\r
- {0x9Du, 0x0Cu},\r
+ {0x33u, 0x80u},\r
+ {0x94u, 0x44u},\r
+ {0x96u, 0x02u},\r
+ {0x97u, 0x10u},\r
{0x9Fu, 0x04u},\r
+ {0xA5u, 0x20u},\r
{0xA6u, 0x80u},\r
- {0xA7u, 0x78u},\r
- {0xA8u, 0x22u},\r
+ {0xA7u, 0x08u},\r
+ {0xAEu, 0x04u},\r
+ {0xB2u, 0x40u},\r
+ {0xB5u, 0x01u},\r
{0xC4u, 0x10u},\r
{0xCCu, 0x10u},\r
- {0xE2u, 0x20u},\r
- {0xE6u, 0xB0u},\r
- {0xEAu, 0x20u},\r
- {0xEEu, 0x20u},\r
- {0x81u, 0x44u},\r
- {0x95u, 0x84u},\r
- {0x9Du, 0x04u},\r
- {0xA0u, 0x20u},\r
- {0xABu, 0x04u},\r
- {0xAFu, 0x20u},\r
- {0xE2u, 0x80u},\r
- {0xE6u, 0x80u},\r
- {0xEAu, 0x80u},\r
- {0xEEu, 0x10u},\r
- {0x08u, 0x04u},\r
- {0x09u, 0x80u},\r
+ {0xEAu, 0x40u},\r
+ {0x61u, 0x01u},\r
+ {0x81u, 0x01u},\r
+ {0x83u, 0x04u},\r
+ {0x86u, 0x01u},\r
+ {0x87u, 0x10u},\r
+ {0x94u, 0x44u},\r
+ {0x96u, 0x02u},\r
+ {0x97u, 0x10u},\r
+ {0x9Fu, 0x04u},\r
+ {0xA5u, 0x20u},\r
+ {0xA7u, 0x80u},\r
+ {0xAFu, 0x08u},\r
+ {0xD8u, 0x40u},\r
+ {0xE2u, 0xB0u},\r
+ {0xE6u, 0x40u},\r
+ {0xEEu, 0x40u},\r
+ {0x09u, 0x04u},\r
+ {0x0Au, 0x08u},\r
{0x0Fu, 0x20u},\r
- {0x12u, 0x20u},\r
- {0x17u, 0x01u},\r
- {0x50u, 0x04u},\r
- {0x57u, 0x20u},\r
- {0x58u, 0x20u},\r
- {0x5Fu, 0x40u},\r
- {0x80u, 0x40u},\r
+ {0x10u, 0x10u},\r
+ {0x14u, 0x80u},\r
+ {0x51u, 0x08u},\r
+ {0x53u, 0x01u},\r
+ {0x55u, 0x40u},\r
+ {0x5Du, 0x80u},\r
+ {0x86u, 0x04u},\r
+ {0x8Bu, 0x80u},\r
+ {0x8Du, 0x04u},\r
{0xC2u, 0x0Eu},\r
{0xC4u, 0x0Cu},\r
{0xD4u, 0x07u},\r
{0xD6u, 0x04u},\r
- {0x00u, 0x40u},\r
- {0x02u, 0x10u},\r
- {0x05u, 0x20u},\r
- {0x07u, 0x20u},\r
- {0x08u, 0x02u},\r
- {0x09u, 0x20u},\r
- {0x0Du, 0x01u},\r
- {0x0Eu, 0x02u},\r
- {0x83u, 0x10u},\r
- {0x8Au, 0x10u},\r
- {0x8Bu, 0x60u},\r
- {0x94u, 0x40u},\r
- {0x97u, 0x40u},\r
- {0x9Bu, 0x01u},\r
- {0xA2u, 0x20u},\r
+ {0xE2u, 0x01u},\r
+ {0xE6u, 0x02u},\r
+ {0x03u, 0x88u},\r
+ {0x05u, 0x40u},\r
+ {0x06u, 0x20u},\r
+ {0x0Au, 0x08u},\r
+ {0x0Bu, 0x80u},\r
+ {0x0Du, 0x10u},\r
+ {0x0Eu, 0x20u},\r
+ {0x85u, 0x40u},\r
+ {0x89u, 0x08u},\r
+ {0x8Fu, 0x01u},\r
+ {0x97u, 0x02u},\r
+ {0x9Du, 0x80u},\r
{0xA3u, 0x10u},\r
- {0xA7u, 0x20u},\r
- {0xA8u, 0x04u},\r
- {0xACu, 0x20u},\r
- {0xB0u, 0x04u},\r
- {0xB5u, 0x80u},\r
+ {0xA5u, 0x48u},\r
+ {0xA7u, 0x80u},\r
+ {0xA8u, 0x80u},\r
+ {0xB0u, 0x10u},\r
{0xC0u, 0x0Fu},\r
{0xC2u, 0x0Fu},\r
- {0xE0u, 0x05u},\r
- {0xE6u, 0x04u},\r
- {0xEAu, 0x08u},\r
- {0xEEu, 0x01u},\r
- {0x82u, 0x05u},\r
- {0x84u, 0x02u},\r
- {0x8Bu, 0x11u},\r
- {0x91u, 0x02u},\r
- {0x98u, 0x02u},\r
- {0x99u, 0x20u},\r
- {0x9Bu, 0x21u},\r
- {0xA1u, 0x20u},\r
- {0xA2u, 0x01u},\r
- {0xAEu, 0x20u},\r
- {0xE2u, 0x04u},\r
- {0xE6u, 0x04u},\r
- {0x0Bu, 0x21u},\r
- {0x0Eu, 0x08u},\r
- {0x0Fu, 0x20u},\r
- {0x83u, 0x11u},\r
- {0x85u, 0x01u},\r
+ {0xE0u, 0x02u},\r
+ {0xE4u, 0x04u},\r
+ {0xEAu, 0x04u},\r
+ {0x8Au, 0x10u},\r
+ {0x8Du, 0x80u},\r
+ {0x8Fu, 0x10u},\r
+ {0x9Au, 0x20u},\r
+ {0x9Du, 0x80u},\r
+ {0xA2u, 0x10u},\r
+ {0xA3u, 0x10u},\r
+ {0xA5u, 0x40u},\r
+ {0xAEu, 0x04u},\r
+ {0xAFu, 0x08u},\r
+ {0xB1u, 0x10u},\r
+ {0xB3u, 0x40u},\r
+ {0xE2u, 0x09u},\r
+ {0xE4u, 0x02u},\r
+ {0xEEu, 0x05u},\r
+ {0x0Au, 0x01u},\r
+ {0x0Bu, 0x20u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Fu, 0x02u},\r
+ {0x81u, 0x02u},\r
+ {0x86u, 0x01u},\r
+ {0x87u, 0x10u},\r
+ {0xAAu, 0x20u},\r
+ {0xB1u, 0x40u},\r
+ {0xC2u, 0x0Fu},\r
+ {0xECu, 0x04u},\r
{0x8Cu, 0x04u},\r
- {0x91u, 0x02u},\r
- {0x97u, 0x20u},\r
- {0x99u, 0x20u},\r
- {0xA6u, 0x04u},\r
- {0xAFu, 0x20u},\r
+ {0x94u, 0x04u},\r
+ {0xAFu, 0x80u},\r
+ {0xB4u, 0x40u},\r
{0xB5u, 0x20u},\r
- {0xC2u, 0x0Fu},\r
- {0xE6u, 0x02u},\r
- {0xEEu, 0x02u},\r
- {0x67u, 0x80u},\r
- {0x87u, 0x40u},\r
- {0x89u, 0x04u},\r
- {0x95u, 0x04u},\r
- {0xA0u, 0x20u},\r
- {0xD8u, 0x80u},\r
- {0xE2u, 0x10u},\r
- {0x06u, 0x40u},\r
- {0x50u, 0x20u},\r
- {0x57u, 0x80u},\r
- {0x86u, 0x40u},\r
- {0x8Fu, 0x80u},\r
- {0xA0u, 0x20u},\r
+ {0xEEu, 0x10u},\r
+ {0x04u, 0x08u},\r
+ {0x52u, 0x80u},\r
+ {0x56u, 0x20u},\r
+ {0x82u, 0x80u},\r
+ {0x8Cu, 0x04u},\r
+ {0x8Eu, 0x20u},\r
{0xC0u, 0x20u},\r
{0xD4u, 0x60u},\r
- {0xE0u, 0x10u},\r
- {0x94u, 0x04u},\r
- {0xB5u, 0x20u},\r
- {0xEAu, 0x08u},\r
- {0x00u, 0x04u},\r
- {0x94u, 0x04u},\r
+ {0xE6u, 0x20u},\r
+ {0x88u, 0x04u},\r
+ {0xAFu, 0x01u},\r
+ {0xE2u, 0x04u},\r
+ {0x00u, 0x08u},\r
+ {0xA4u, 0x04u},\r
{0xC0u, 0x08u},\r
{0x10u, 0x03u},\r
+ {0x11u, 0x01u},\r
{0x1Au, 0x03u},\r
+ {0x1Bu, 0x01u},\r
{0x00u, 0xFDu},\r
{0x01u, 0xBFu},\r
{0x02u, 0x2Au},\r
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
{(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
{(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},\r
};\r
\r
+ /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */\r
+ static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {\r
+ 0x8Du, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x0Du, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Du, 0x00u, 0x80u, 0x00u, \r
+ 0x00u, 0x0Fu, 0x10u, 0xF0u, 0x62u, 0x30u, 0x08u, 0xC0u, 0x02u, 0x50u, 0x54u, 0xA0u, 0x01u, 0x06u, 0x32u, 0x09u, \r
+ 0x8Du, 0x05u, 0x00u, 0x0Au, 0x8Du, 0x03u, 0x00u, 0x0Cu, 0x8Du, 0x00u, 0x00u, 0x00u, 0x00u, 0x60u, 0x00u, 0x90u, \r
+ 0x70u, 0x00u, 0x0Fu, 0x00u, 0x80u, 0x00u, 0x80u, 0xFFu, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x50u, 0x40u, \r
+ 0x63u, 0x05u, 0x20u, 0x00u, 0x01u, 0xFEu, 0xBDu, 0xCBu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, \r
+ 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
+\r
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u};\r
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u},\r
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},\r
};\r
\r
.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
.set SDCard_BSPIM_TxStsReg__2__POS, 2\r
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08\r
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB08_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB08_ST\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
+.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
\r
/* SD_SCK */\r
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK\r
\r
/* SCSI_Out_Ctl */\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK\r
\r
/* SCSI_Out_DBx */\r
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
.set scsiTarget_StatusReg__0__POS, 0\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__2__POS, 2\r
.set scsiTarget_StatusReg__3__MASK, 0x08\r
.set scsiTarget_StatusReg__4__MASK, 0x10\r
.set scsiTarget_StatusReg__4__POS, 4\r
.set scsiTarget_StatusReg__MASK, 0x1F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST\r
\r
/* Debug_Timer_Interrupt */\r
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST\r
\r
/* SCSI_CTL_PHASE */\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK\r
\r
/* SCSI_Parity_Error */\r
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB09_MSK\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB09_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST\r
\r
/* Miscellaneous */\r
.set BCLK__BUS_CLK__HZ, 50000000\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
\r
/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
\r
/* SD_SCK */\r
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
\r
/* SCSI_Out_Ctl */\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
\r
/* SCSI_Out_DBx */\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST\r
\r
/* Debug_Timer_Interrupt */\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
\r
/* SCSI_CTL_PHASE */\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
\r
/* SCSI_Parity_Error */\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
\r
/* Miscellaneous */\r
BCLK__BUS_CLK__HZ EQU 50000000\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
\r
; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
\r
; SD_SCK\r
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
\r
; SCSI_Out_Ctl\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
\r
; SCSI_Out_DBx\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST\r
\r
; Debug_Timer_Interrupt\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
\r
; SCSI_CTL_PHASE\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK\r
\r
; SCSI_Glitch_Ctl\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
\r
; SCSI_Parity_Error\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
\r
; Miscellaneous\r
BCLK__BUS_CLK__HZ EQU 50000000\r
const uint8 cy_meta_loadable[] = {\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x50u, 0x04u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x60u, 0x04u,\r
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />\r
</block>\r
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647E" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006477" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="cydff_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Filtered_STATUS_REG" address="0x40006462" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Filtered_MASK_REG" address="0x40006482" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006492" bitWidth="8" desc="" hidden="false">\r
+ <register name="SCSI_Filtered_STATUS_REG" address="0x40006465" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Filtered_MASK_REG" address="0x40006485" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="" hidden="false">\r
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
</register>\r
</block>\r
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006469" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_MASK_REG" address="0x40006489" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006499" bitWidth="8" desc="" hidden="false">\r
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006466" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x40006486" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006496" bitWidth="8" desc="" hidden="false">\r
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
</block>\r
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647A" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<peripheral>\r
<name>SCSI_Out_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000647E</baseAddress>\r
+ <baseAddress>0x40006477</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_Glitch_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006474</baseAddress>\r
+ <baseAddress>0x40006473</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_Filtered</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006462</baseAddress>\r
+ <baseAddress>0x40006465</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_Parity_Error</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006469</baseAddress>\r
+ <baseAddress>0x40006466</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_CTL_PHASE</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006475</baseAddress>\r
+ <baseAddress>0x40006472</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_Out_Bits</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000647A</baseAddress>\r
+ <baseAddress>0x4000647C</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
);\r
\r
// DMA outputs\r
-//assign tx_intr = f0_bus_stat;\r
-assign tx_intr = f0_blk_stat;\r
-//assign rx_intr = f1_bus_stat;\r
-assign rx_intr = f1_blk_stat;\r
+assign tx_intr = f0_bus_stat;\r
+//assign tx_intr = f0_blk_stat;\r
+assign rx_intr = f1_bus_stat;\r
+//assign rx_intr = f1_blk_stat;\r
\r
/////////////////////////////////////////////////////////////////////////////\r
// State machine\r
else if (IO == IO_WRITE)\r
state <= STATE_TX;\r
\r
- // Check the output FIFO is not full.\r
- else if (!f1_blk_stat) begin\r
- state <= STATE_READY;\r
- REQReg <= 1'b1;\r
- end else begin\r
+ // Note: Cannot check whether the output FIFO is not full\r
+ // because we haven't finished writing to it yet.\r
+ // causes a rare race condition issue on fast SCSI hosts\r
+ \r
+ else begin\r
state <= STATE_WAIT_TIL_READY;\r
end\r
end\r
STATE_READY:\r
if (!nRST) state <= STATE_IDLE;\r
else if (~nACK) begin\r
+ REQReg <= 1'b0;\r
state <= STATE_RX;\r
dbxInReg[7:0] = ~nDBx_in[7:0]; // Invert active low scsi bus\r
\r
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL\r
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL\r
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB08_MSK\r
+#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB08_ST\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
+#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL\r
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
\r
/* SD_SCK */\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB07_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB07_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL\r
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB07_MSK\r
\r
/* SCSI_Out_Ctl */\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK\r
\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG\r
#define scsiTarget_StatusReg__0__POS 0\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__2__POS 2\r
#define scsiTarget_StatusReg__3__MASK 0x08u\r
#define scsiTarget_StatusReg__4__MASK 0x10u\r
#define scsiTarget_StatusReg__4__POS 4\r
#define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB04_MSK\r
-#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL\r
-#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB04_ST\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST\r
\r
/* Debug_Timer_Interrupt */\r
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST\r
\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B1_UDB05_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B1_UDB05_ST\r
\r
/* Miscellaneous */\r
#define BCLK__BUS_CLK__HZ 50000000U\r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 42u\r
+#define CY_CFG_BASE_ADDR_COUNT 41u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
0x4000520Eu, /* Base address: 0x40005200 Count: 14 */\r
0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
- 0x4001003Fu, /* Base address: 0x40010000 Count: 63 */\r
- 0x4001013Fu, /* Base address: 0x40010100 Count: 63 */\r
- 0x40010247u, /* Base address: 0x40010200 Count: 71 */\r
- 0x40010358u, /* Base address: 0x40010300 Count: 88 */\r
- 0x40010451u, /* Base address: 0x40010400 Count: 81 */\r
- 0x40010555u, /* Base address: 0x40010500 Count: 85 */\r
- 0x4001064Cu, /* Base address: 0x40010600 Count: 76 */\r
- 0x4001074Cu, /* Base address: 0x40010700 Count: 76 */\r
- 0x4001084Bu, /* Base address: 0x40010800 Count: 75 */\r
- 0x4001094Bu, /* Base address: 0x40010900 Count: 75 */\r
- 0x40010A50u, /* Base address: 0x40010A00 Count: 80 */\r
- 0x40010B56u, /* Base address: 0x40010B00 Count: 86 */\r
- 0x40010C47u, /* Base address: 0x40010C00 Count: 71 */\r
+ 0x40010050u, /* Base address: 0x40010000 Count: 80 */\r
+ 0x40010146u, /* Base address: 0x40010100 Count: 70 */\r
+ 0x4001025Cu, /* Base address: 0x40010200 Count: 92 */\r
+ 0x4001035Du, /* Base address: 0x40010300 Count: 93 */\r
+ 0x4001044Eu, /* Base address: 0x40010400 Count: 78 */\r
+ 0x40010558u, /* Base address: 0x40010500 Count: 88 */\r
+ 0x40010646u, /* Base address: 0x40010600 Count: 70 */\r
+ 0x4001074Eu, /* Base address: 0x40010700 Count: 78 */\r
+ 0x40010851u, /* Base address: 0x40010800 Count: 81 */\r
+ 0x4001095Au, /* Base address: 0x40010900 Count: 90 */\r
+ 0x40010A4Au, /* Base address: 0x40010A00 Count: 74 */\r
+ 0x40010B57u, /* Base address: 0x40010B00 Count: 87 */\r
+ 0x40010C53u, /* Base address: 0x40010C00 Count: 83 */\r
0x40010D51u, /* Base address: 0x40010D00 Count: 81 */\r
- 0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */\r
- 0x40010F45u, /* Base address: 0x40010F00 Count: 69 */\r
- 0x4001140Eu, /* Base address: 0x40011400 Count: 14 */\r
- 0x40011547u, /* Base address: 0x40011500 Count: 71 */\r
- 0x4001164Eu, /* Base address: 0x40011600 Count: 78 */\r
- 0x40011743u, /* Base address: 0x40011700 Count: 67 */\r
- 0x40011804u, /* Base address: 0x40011800 Count: 4 */\r
- 0x40011910u, /* Base address: 0x40011900 Count: 16 */\r
- 0x40011B09u, /* Base address: 0x40011B00 Count: 9 */\r
- 0x40014018u, /* Base address: 0x40014000 Count: 24 */\r
- 0x40014117u, /* Base address: 0x40014100 Count: 23 */\r
- 0x40014210u, /* Base address: 0x40014200 Count: 16 */\r
- 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */\r
- 0x4001440Eu, /* Base address: 0x40014400 Count: 14 */\r
- 0x40014519u, /* Base address: 0x40014500 Count: 25 */\r
- 0x40014612u, /* Base address: 0x40014600 Count: 18 */\r
- 0x40014712u, /* Base address: 0x40014700 Count: 18 */\r
- 0x40014805u, /* Base address: 0x40014800 Count: 5 */\r
- 0x4001490Du, /* Base address: 0x40014900 Count: 13 */\r
- 0x40014C04u, /* Base address: 0x40014C00 Count: 4 */\r
- 0x40014D0Bu, /* Base address: 0x40014D00 Count: 11 */\r
- 0x40015004u, /* Base address: 0x40015000 Count: 4 */\r
+ 0x40010E4Cu, /* Base address: 0x40010E00 Count: 76 */\r
+ 0x40010F3Du, /* Base address: 0x40010F00 Count: 61 */\r
+ 0x40011410u, /* Base address: 0x40011400 Count: 16 */\r
+ 0x40011548u, /* Base address: 0x40011500 Count: 72 */\r
+ 0x40011650u, /* Base address: 0x40011600 Count: 80 */\r
+ 0x4001174Eu, /* Base address: 0x40011700 Count: 78 */\r
+ 0x40011912u, /* Base address: 0x40011900 Count: 18 */\r
+ 0x40011B06u, /* Base address: 0x40011B00 Count: 6 */\r
+ 0x4001401Au, /* Base address: 0x40014000 Count: 26 */\r
+ 0x4001411Bu, /* Base address: 0x40014100 Count: 27 */\r
+ 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */\r
+ 0x40014308u, /* Base address: 0x40014300 Count: 8 */\r
+ 0x4001440Fu, /* Base address: 0x40014400 Count: 15 */\r
+ 0x4001451Fu, /* Base address: 0x40014500 Count: 31 */\r
+ 0x40014610u, /* Base address: 0x40014600 Count: 16 */\r
+ 0x4001470Eu, /* Base address: 0x40014700 Count: 14 */\r
+ 0x40014806u, /* Base address: 0x40014800 Count: 6 */\r
+ 0x40014909u, /* Base address: 0x40014900 Count: 9 */\r
+ 0x40014C09u, /* Base address: 0x40014C00 Count: 9 */\r
+ 0x40014D09u, /* Base address: 0x40014D00 Count: 9 */\r
+ 0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
\r
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
- {0x0Au, 0x36u},\r
+ {0x0Au, 0x1Bu},\r
{0x00u, 0x48u},\r
- {0x01u, 0x04u},\r
+ {0x01u, 0x0Cu},\r
{0x04u, 0x31u},\r
- {0x10u, 0xC8u},\r
- {0x11u, 0x44u},\r
+ {0x10u, 0x4Cu},\r
+ {0x11u, 0x84u},\r
{0x18u, 0x08u},\r
- {0x19u, 0x04u},\r
{0x1Cu, 0x30u},\r
{0x20u, 0x10u},\r
{0x24u, 0x44u},\r
{0x29u, 0x01u},\r
{0x30u, 0x20u},\r
{0x31u, 0x30u},\r
+ {0x78u, 0x20u},\r
{0x7Cu, 0x40u},\r
{0x20u, 0x01u},\r
{0x84u, 0x0Fu},\r
- {0x03u, 0x70u},\r
- {0x06u, 0xFFu},\r
- {0x07u, 0x80u},\r
- {0x08u, 0xFFu},\r
- {0x0Bu, 0x08u},\r
+ {0x04u, 0x0Fu},\r
+ {0x06u, 0xF0u},\r
+ {0x09u, 0x03u},\r
+ {0x0Bu, 0x04u},\r
+ {0x0Du, 0x04u},\r
{0x0Eu, 0xFFu},\r
- {0x10u, 0xFFu},\r
- {0x17u, 0x07u},\r
+ {0x0Fu, 0x03u},\r
+ {0x10u, 0x69u},\r
+ {0x11u, 0x05u},\r
+ {0x12u, 0x96u},\r
+ {0x13u, 0x02u},\r
+ {0x14u, 0xFFu},\r
+ {0x15u, 0x01u},\r
+ {0x17u, 0x06u},\r
{0x1Au, 0xFFu},\r
- {0x1Cu, 0x69u},\r
- {0x1Eu, 0x96u},\r
- {0x20u, 0x55u},\r
- {0x22u, 0xAAu},\r
- {0x25u, 0x44u},\r
- {0x27u, 0x88u},\r
- {0x28u, 0x33u},\r
- {0x29u, 0xAAu},\r
- {0x2Au, 0xCCu},\r
- {0x2Bu, 0x55u},\r
- {0x2Cu, 0x0Fu},\r
- {0x2Du, 0x99u},\r
- {0x2Eu, 0xF0u},\r
- {0x2Fu, 0x22u},\r
- {0x30u, 0xFFu},\r
- {0x31u, 0xF0u},\r
- {0x33u, 0x0Fu},\r
- {0x3Au, 0x02u},\r
- {0x40u, 0x36u},\r
- {0x41u, 0x04u},\r
- {0x42u, 0x10u},\r
- {0x45u, 0x2Cu},\r
- {0x46u, 0xDEu},\r
+ {0x1Eu, 0xFFu},\r
+ {0x20u, 0xFFu},\r
+ {0x24u, 0x33u},\r
+ {0x26u, 0xCCu},\r
+ {0x28u, 0x55u},\r
+ {0x2Au, 0xAAu},\r
+ {0x31u, 0x07u},\r
+ {0x32u, 0xFFu},\r
+ {0x3Au, 0x08u},\r
+ {0x3Bu, 0x02u},\r
+ {0x40u, 0x26u},\r
+ {0x41u, 0x03u},\r
+ {0x42u, 0x50u},\r
+ {0x45u, 0xECu},\r
+ {0x46u, 0xD2u},\r
{0x47u, 0x0Fu},\r
{0x48u, 0x1Fu},\r
{0x49u, 0xFFu},\r
{0x59u, 0x04u},\r
{0x5Au, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
+ {0x5Cu, 0x01u},\r
{0x5Du, 0x01u},\r
{0x5Fu, 0x01u},\r
{0x60u, 0x08u},\r
{0x68u, 0x40u},\r
{0x69u, 0x40u},\r
{0x6Eu, 0x08u},\r
- {0x8Du, 0x01u},\r
- {0x8Fu, 0x02u},\r
- {0x9Fu, 0x01u},\r
- {0xA7u, 0x02u},\r
- {0xAEu, 0x01u},\r
- {0xB2u, 0x01u},\r
- {0xB7u, 0x03u},\r
- {0xBFu, 0x40u},\r
+ {0x84u, 0x03u},\r
+ {0x85u, 0x03u},\r
+ {0x86u, 0x14u},\r
+ {0x87u, 0x1Cu},\r
+ {0x89u, 0x09u},\r
+ {0x8Bu, 0x12u},\r
+ {0x8Cu, 0x04u},\r
+ {0x91u, 0x04u},\r
+ {0x94u, 0x18u},\r
+ {0x96u, 0x03u},\r
+ {0x99u, 0x08u},\r
+ {0x9Au, 0x01u},\r
+ {0x9Bu, 0x17u},\r
+ {0x9Eu, 0x1Fu},\r
+ {0x9Fu, 0x07u},\r
+ {0xA2u, 0x08u},\r
+ {0xA3u, 0x01u},\r
+ {0xA4u, 0x01u},\r
+ {0xA5u, 0x02u},\r
+ {0xA6u, 0x0Eu},\r
+ {0xA8u, 0x02u},\r
+ {0xADu, 0x0Bu},\r
+ {0xAFu, 0x14u},\r
+ {0xB3u, 0x1Fu},\r
+ {0xB4u, 0x1Fu},\r
+ {0xBBu, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDCu, 0x11u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x28u},\r
+ {0x01u, 0x08u},\r
{0x03u, 0x02u},\r
- {0x04u, 0x80u},\r
- {0x06u, 0x01u},\r
- {0x08u, 0x02u},\r
- {0x09u, 0x50u},\r
- {0x10u, 0x08u},\r
- {0x12u, 0x41u},\r
- {0x15u, 0x80u},\r
- {0x18u, 0x80u},\r
- {0x1Fu, 0x08u},\r
- {0x21u, 0x01u},\r
- {0x22u, 0x04u},\r
- {0x23u, 0x80u},\r
- {0x26u, 0x40u},\r
- {0x29u, 0x20u},\r
- {0x2Bu, 0x12u},\r
- {0x2Cu, 0x20u},\r
- {0x30u, 0x04u},\r
- {0x32u, 0x04u},\r
- {0x37u, 0x80u},\r
- {0x39u, 0x16u},\r
- {0x3Bu, 0x02u},\r
- {0x3Du, 0x40u},\r
- {0x40u, 0x10u},\r
- {0x43u, 0x82u},\r
- {0x48u, 0x10u},\r
- {0x49u, 0x26u},\r
- {0x50u, 0x10u},\r
- {0x52u, 0x18u},\r
- {0x53u, 0x60u},\r
- {0x58u, 0x18u},\r
- {0x59u, 0x01u},\r
- {0x5Bu, 0x40u},\r
- {0x60u, 0x40u},\r
- {0x61u, 0x08u},\r
- {0x62u, 0xA0u},\r
- {0x69u, 0x14u},\r
- {0x6Au, 0x82u},\r
- {0x70u, 0x01u},\r
- {0x72u, 0x20u},\r
- {0x73u, 0x06u},\r
- {0x80u, 0x40u},\r
- {0x81u, 0x01u},\r
- {0x82u, 0x20u},\r
- {0x84u, 0x18u},\r
- {0x85u, 0x40u},\r
- {0x88u, 0x08u},\r
- {0x8Bu, 0x02u},\r
- {0x8Cu, 0x11u},\r
- {0xC0u, 0x07u},\r
- {0xC2u, 0x0Bu},\r
- {0xC4u, 0x8Bu},\r
- {0xCAu, 0x4Eu},\r
- {0xCCu, 0x12u},\r
- {0xCEu, 0x17u},\r
- {0xD0u, 0x0Bu},\r
- {0xD2u, 0x04u},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x0Fu},\r
- {0xE2u, 0x06u},\r
- {0xE4u, 0x80u},\r
- {0xE6u, 0x4Fu},\r
- {0x04u, 0x09u},\r
- {0x05u, 0x01u},\r
- {0x06u, 0x06u},\r
- {0x08u, 0x50u},\r
- {0x09u, 0x0Fu},\r
- {0x0Au, 0xA0u},\r
- {0x0Bu, 0x10u},\r
- {0x0Cu, 0xFFu},\r
- {0x10u, 0x90u},\r
- {0x12u, 0x60u},\r
+ {0x04u, 0x04u},\r
+ {0x07u, 0x02u},\r
+ {0x08u, 0xA1u},\r
+ {0x0Bu, 0x11u},\r
+ {0x0Eu, 0x08u},\r
+ {0x0Fu, 0x11u},\r
+ {0x10u, 0x14u},\r
{0x13u, 0x02u},\r
- {0x14u, 0x05u},\r
- {0x16u, 0x0Au},\r
- {0x17u, 0x07u},\r
- {0x18u, 0x30u},\r
- {0x19u, 0x07u},\r
- {0x1Au, 0xC0u},\r
- {0x1Bu, 0x18u},\r
- {0x20u, 0x03u},\r
- {0x22u, 0x0Cu},\r
- {0x24u, 0xFFu},\r
- {0x25u, 0x05u},\r
- {0x29u, 0x0Au},\r
- {0x2Au, 0xFFu},\r
- {0x2Bu, 0x15u},\r
- {0x2Cu, 0x0Fu},\r
- {0x2Du, 0x08u},\r
- {0x2Eu, 0xF0u},\r
- {0x2Fu, 0x16u},\r
- {0x33u, 0x1Fu},\r
- {0x34u, 0xFFu},\r
- {0x3Bu, 0x08u},\r
- {0x3Eu, 0x10u},\r
- {0x58u, 0x04u},\r
- {0x59u, 0x04u},\r
- {0x5Cu, 0x10u},\r
- {0x5Fu, 0x01u},\r
- {0x82u, 0x04u},\r
- {0x84u, 0x08u},\r
- {0x88u, 0x34u},\r
- {0x8Au, 0x09u},\r
- {0x8Bu, 0x08u},\r
- {0x8Eu, 0x20u},\r
- {0x90u, 0x02u},\r
- {0x96u, 0x1Fu},\r
- {0x97u, 0x70u},\r
- {0x98u, 0x29u},\r
- {0x9Au, 0x12u},\r
- {0x9Bu, 0x07u},\r
- {0x9Fu, 0x80u},\r
- {0xA2u, 0x01u},\r
- {0xA5u, 0x44u},\r
- {0xA7u, 0x88u},\r
- {0xA8u, 0x21u},\r
- {0xA9u, 0xAAu},\r
- {0xAAu, 0x06u},\r
- {0xABu, 0x55u},\r
- {0xADu, 0x99u},\r
- {0xAFu, 0x22u},\r
- {0xB0u, 0x20u},\r
- {0xB2u, 0x1Fu},\r
- {0xB3u, 0xF0u},\r
- {0xB5u, 0x0Fu},\r
- {0xBEu, 0x01u},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
- {0xDDu, 0x90u},\r
- {0xDFu, 0x01u},\r
- {0x01u, 0xA2u},\r
- {0x02u, 0x10u},\r
- {0x04u, 0x40u},\r
- {0x07u, 0x24u},\r
- {0x08u, 0x02u},\r
- {0x09u, 0x10u},\r
- {0x0Au, 0x20u},\r
- {0x0Cu, 0x24u},\r
- {0x0Eu, 0x40u},\r
- {0x13u, 0x12u},\r
- {0x15u, 0x42u},\r
- {0x16u, 0x08u},\r
- {0x17u, 0x08u},\r
- {0x18u, 0x10u},\r
- {0x1Bu, 0x05u},\r
+ {0x15u, 0x28u},\r
+ {0x16u, 0x40u},\r
+ {0x19u, 0x08u},\r
+ {0x1Au, 0x10u},\r
{0x1Cu, 0x04u},\r
- {0x20u, 0x20u},\r
- {0x21u, 0x28u},\r
- {0x23u, 0x20u},\r
- {0x27u, 0x10u},\r
+ {0x23u, 0x40u},\r
+ {0x25u, 0x04u},\r
{0x29u, 0x20u},\r
- {0x2Bu, 0x12u},\r
- {0x2Du, 0x20u},\r
- {0x2Fu, 0x22u},\r
- {0x31u, 0x28u},\r
- {0x32u, 0x40u},\r
- {0x35u, 0x0Au},\r
- {0x37u, 0x10u},\r
+ {0x2Bu, 0x08u},\r
+ {0x2Cu, 0xA0u},\r
+ {0x2Fu, 0x02u},\r
+ {0x32u, 0x0Au},\r
+ {0x34u, 0xA0u},\r
+ {0x37u, 0x02u},\r
{0x3Au, 0x20u},\r
- {0x3Cu, 0x10u},\r
- {0x3Du, 0x20u},\r
- {0x3Eu, 0x08u},\r
- {0x3Fu, 0x20u},\r
- {0x49u, 0x10u},\r
- {0x4Au, 0x08u},\r
- {0x58u, 0x40u},\r
- {0x62u, 0x40u},\r
- {0x68u, 0x24u},\r
- {0x69u, 0x01u},\r
- {0x6Au, 0x44u},\r
- {0x6Bu, 0x05u},\r
- {0x70u, 0x18u},\r
- {0x71u, 0x80u},\r
+ {0x3Bu, 0x40u},\r
+ {0x3Du, 0x08u},\r
+ {0x3Fu, 0x10u},\r
+ {0x40u, 0x24u},\r
+ {0x41u, 0x04u},\r
+ {0x48u, 0x05u},\r
+ {0x4Au, 0x90u},\r
+ {0x4Bu, 0x10u},\r
+ {0x50u, 0xA0u},\r
+ {0x51u, 0x10u},\r
+ {0x52u, 0x40u},\r
+ {0x53u, 0x08u},\r
+ {0x58u, 0x08u},\r
+ {0x59u, 0x50u},\r
+ {0x5Au, 0x01u},\r
+ {0x60u, 0x02u},\r
+ {0x61u, 0x24u},\r
+ {0x62u, 0x01u},\r
+ {0x68u, 0x10u},\r
+ {0x69u, 0x80u},\r
+ {0x6Au, 0x20u},\r
+ {0x6Bu, 0x40u},\r
+ {0x70u, 0x58u},\r
{0x72u, 0x80u},\r
- {0x81u, 0x08u},\r
- {0x82u, 0x10u},\r
- {0x89u, 0x81u},\r
- {0x8Fu, 0x10u},\r
- {0x90u, 0x80u},\r
- {0x91u, 0x02u},\r
- {0x92u, 0x80u},\r
- {0x93u, 0x86u},\r
- {0x94u, 0x10u},\r
- {0x95u, 0xC0u},\r
- {0x98u, 0x04u},\r
- {0x99u, 0xA6u},\r
- {0x9Au, 0x30u},\r
- {0x9Cu, 0x02u},\r
- {0x9Du, 0x08u},\r
- {0x9Eu, 0x40u},\r
- {0x9Fu, 0x40u},\r
- {0xA2u, 0x08u},\r
- {0xA3u, 0x28u},\r
- {0xA4u, 0x20u},\r
- {0xA5u, 0x10u},\r
- {0xA6u, 0x80u},\r
- {0xA7u, 0x92u},\r
- {0xA9u, 0x20u},\r
- {0xACu, 0x10u},\r
- {0xADu, 0x80u},\r
- {0xAEu, 0x40u},\r
- {0xB2u, 0x01u},\r
- {0xB4u, 0x10u},\r
- {0xB5u, 0x08u},\r
- {0xC0u, 0xEFu},\r
- {0xC2u, 0x7Eu},\r
- {0xC4u, 0xFAu},\r
- {0xCAu, 0x7Eu},\r
- {0xCCu, 0xEEu},\r
- {0xCEu, 0x64u},\r
- {0xD6u, 0x08u},\r
- {0xD8u, 0x08u},\r
- {0xE2u, 0x08u},\r
- {0xE6u, 0x64u},\r
- {0xE8u, 0x08u},\r
- {0xEAu, 0x04u},\r
- {0xECu, 0x02u},\r
- {0xEEu, 0x01u},\r
- {0x00u, 0xFFu},\r
- {0x04u, 0x50u},\r
- {0x05u, 0x05u},\r
- {0x06u, 0xA0u},\r
- {0x07u, 0x0Au},\r
- {0x08u, 0x06u},\r
- {0x09u, 0x0Fu},\r
- {0x0Au, 0x09u},\r
- {0x0Cu, 0x0Fu},\r
- {0x0Du, 0x03u},\r
- {0x0Eu, 0xF0u},\r
- {0x0Fu, 0x0Cu},\r
+ {0x81u, 0x40u},\r
+ {0x83u, 0x40u},\r
+ {0x84u, 0x14u},\r
+ {0x8Au, 0x80u},\r
+ {0x8Cu, 0x40u},\r
+ {0x8Du, 0x04u},\r
+ {0x8Eu, 0x10u},\r
+ {0xC0u, 0xA5u},\r
+ {0xC2u, 0xEFu},\r
+ {0xC4u, 0x7Eu},\r
+ {0xCAu, 0xD0u},\r
+ {0xCCu, 0xB3u},\r
+ {0xCEu, 0x6Cu},\r
+ {0xD0u, 0x06u},\r
+ {0xD2u, 0x0Cu},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x0Fu},\r
+ {0xE0u, 0x01u},\r
+ {0xE2u, 0x0Au},\r
+ {0xE4u, 0x09u},\r
+ {0xE6u, 0x42u},\r
+ {0x00u, 0x0Fu},\r
+ {0x02u, 0xF0u},\r
+ {0x05u, 0x20u},\r
+ {0x06u, 0xFFu},\r
+ {0x07u, 0x4Fu},\r
+ {0x09u, 0x05u},\r
+ {0x0Bu, 0x0Au},\r
+ {0x0Du, 0x06u},\r
+ {0x0Fu, 0x09u},\r
{0x13u, 0x70u},\r
- {0x14u, 0x05u},\r
- {0x16u, 0x0Au},\r
- {0x18u, 0x30u},\r
- {0x1Au, 0xC0u},\r
- {0x1Cu, 0x03u},\r
- {0x1Du, 0x10u},\r
- {0x1Eu, 0x0Cu},\r
- {0x1Fu, 0x2Fu},\r
- {0x20u, 0x60u},\r
- {0x22u, 0x90u},\r
- {0x25u, 0x40u},\r
- {0x26u, 0xFFu},\r
- {0x27u, 0x1Fu},\r
- {0x29u, 0x20u},\r
- {0x2Au, 0xFFu},\r
- {0x2Bu, 0x4Fu},\r
- {0x2Du, 0x06u},\r
- {0x2Fu, 0x09u},\r
+ {0x15u, 0x0Fu},\r
+ {0x16u, 0xFFu},\r
+ {0x18u, 0x55u},\r
+ {0x19u, 0x10u},\r
+ {0x1Au, 0xAAu},\r
+ {0x1Bu, 0x2Fu},\r
+ {0x1Du, 0x03u},\r
+ {0x1Eu, 0xFFu},\r
+ {0x1Fu, 0x0Cu},\r
+ {0x20u, 0xFFu},\r
+ {0x24u, 0xFFu},\r
+ {0x28u, 0x69u},\r
+ {0x2Au, 0x96u},\r
+ {0x2Cu, 0x33u},\r
+ {0x2Du, 0x40u},\r
+ {0x2Eu, 0xCCu},\r
+ {0x2Fu, 0x1Fu},\r
{0x30u, 0xFFu},\r
{0x31u, 0x7Fu},\r
- {0x3Eu, 0x01u},\r
+ {0x3Au, 0x02u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x10u},\r
+ {0x5Cu, 0x11u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x10u},\r
- {0x84u, 0x10u},\r
- {0x85u, 0x50u},\r
- {0x87u, 0xA0u},\r
- {0x88u, 0x0Au},\r
- {0x8Au, 0x05u},\r
- {0x8Bu, 0xFFu},\r
- {0x8Du, 0x0Fu},\r
- {0x8Eu, 0x07u},\r
+ {0x80u, 0x20u},\r
+ {0x81u, 0x40u},\r
+ {0x82u, 0x40u},\r
+ {0x83u, 0x80u},\r
+ {0x84u, 0x01u},\r
+ {0x85u, 0x10u},\r
+ {0x86u, 0x02u},\r
+ {0x87u, 0x20u},\r
+ {0x88u, 0x08u},\r
+ {0x8Au, 0x10u},\r
+ {0x8Cu, 0x44u},\r
+ {0x8Du, 0x02u},\r
+ {0x8Eu, 0x3Bu},\r
{0x8Fu, 0xF0u},\r
- {0x91u, 0x60u},\r
- {0x93u, 0x90u},\r
- {0x94u, 0x10u},\r
+ {0x90u, 0x44u},\r
+ {0x92u, 0x3Bu},\r
+ {0x94u, 0x1Fu},\r
{0x95u, 0x05u},\r
- {0x97u, 0x0Au},\r
- {0x99u, 0xFFu},\r
- {0x9Au, 0x08u},\r
- {0x9Fu, 0xFFu},\r
- {0xA0u, 0x09u},\r
- {0xA2u, 0x02u},\r
- {0xA4u, 0x04u},\r
- {0xA5u, 0x30u},\r
- {0xA6u, 0x08u},\r
- {0xA7u, 0xC0u},\r
- {0xA8u, 0x10u},\r
- {0xA9u, 0x06u},\r
- {0xABu, 0x09u},\r
- {0xADu, 0x03u},\r
- {0xAFu, 0x0Cu},\r
- {0xB2u, 0x10u},\r
- {0xB5u, 0xFFu},\r
- {0xB6u, 0x0Fu},\r
- {0xB8u, 0x08u},\r
- {0xBEu, 0x04u},\r
- {0xBFu, 0x10u},\r
- {0xD4u, 0x01u},\r
+ {0x96u, 0x20u},\r
+ {0x97u, 0xF8u},\r
+ {0x98u, 0x01u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Bu, 0x01u},\r
+ {0x9Du, 0xF0u},\r
+ {0x9Eu, 0x3Bu},\r
+ {0x9Fu, 0x08u},\r
+ {0xA0u, 0x1Bu},\r
+ {0xA1u, 0x40u},\r
+ {0xA2u, 0x20u},\r
+ {0xA3u, 0x80u},\r
+ {0xA4u, 0x08u},\r
+ {0xA5u, 0xF4u},\r
+ {0xA6u, 0x10u},\r
+ {0xA7u, 0x08u},\r
+ {0xA9u, 0x01u},\r
+ {0xAAu, 0x04u},\r
+ {0xABu, 0xF8u},\r
+ {0xADu, 0x10u},\r
+ {0xAFu, 0x20u},\r
+ {0xB0u, 0x60u},\r
+ {0xB2u, 0x18u},\r
+ {0xB3u, 0x0Fu},\r
+ {0xB4u, 0x03u},\r
+ {0xB5u, 0x30u},\r
+ {0xB6u, 0x04u},\r
+ {0xB7u, 0xC0u},\r
+ {0xB9u, 0x08u},\r
+ {0xBAu, 0x2Au},\r
+ {0xBBu, 0xA0u},\r
+ {0xBEu, 0x40u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x01u},\r
- {0xDDu, 0x10u},\r
+ {0xDCu, 0x11u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x28u},\r
- {0x01u, 0x40u},\r
- {0x02u, 0x80u},\r
+ {0x00u, 0x02u},\r
+ {0x02u, 0x20u},\r
+ {0x03u, 0x0Au},\r
{0x04u, 0x04u},\r
- {0x05u, 0x61u},\r
- {0x06u, 0x02u},\r
- {0x08u, 0x04u},\r
- {0x0Au, 0x44u},\r
- {0x0Bu, 0x82u},\r
- {0x0Eu, 0x20u},\r
- {0x0Fu, 0x04u},\r
- {0x11u, 0x12u},\r
- {0x13u, 0x08u},\r
- {0x14u, 0x20u},\r
- {0x16u, 0x40u},\r
- {0x17u, 0x20u},\r
- {0x19u, 0x01u},\r
- {0x1Du, 0x40u},\r
- {0x1Fu, 0x04u},\r
- {0x21u, 0x02u},\r
- {0x23u, 0x40u},\r
- {0x26u, 0x10u},\r
- {0x28u, 0x22u},\r
- {0x29u, 0x20u},\r
- {0x2Cu, 0x20u},\r
- {0x2Eu, 0x20u},\r
- {0x2Fu, 0x01u},\r
- {0x30u, 0x80u},\r
- {0x31u, 0x02u},\r
- {0x34u, 0x04u},\r
- {0x36u, 0xA0u},\r
- {0x37u, 0x01u},\r
- {0x38u, 0x80u},\r
- {0x39u, 0x10u},\r
- {0x3Au, 0x08u},\r
- {0x3Bu, 0x20u},\r
- {0x3Cu, 0x08u},\r
- {0x3Du, 0x50u},\r
- {0x45u, 0x01u},\r
- {0x47u, 0x01u},\r
- {0x59u, 0x16u},\r
- {0x5Au, 0x40u},\r
- {0x5Fu, 0x40u},\r
- {0x63u, 0x02u},\r
- {0x69u, 0x40u},\r
- {0x83u, 0x40u},\r
- {0x84u, 0x80u},\r
- {0x86u, 0x40u},\r
- {0x87u, 0x12u},\r
- {0x8Bu, 0x04u},\r
- {0x8Fu, 0x80u},\r
- {0x90u, 0xA4u},\r
- {0x92u, 0x04u},\r
- {0x93u, 0xA6u},\r
- {0x95u, 0xC0u},\r
- {0x97u, 0x10u},\r
- {0x98u, 0x04u},\r
- {0x99u, 0x34u},\r
- {0x9Au, 0x80u},\r
- {0x9Bu, 0x01u},\r
- {0x9Cu, 0x40u},\r
- {0x9Fu, 0x48u},\r
- {0xA0u, 0x3Cu},\r
- {0xA1u, 0x20u},\r
- {0xA3u, 0x2Du},\r
- {0xA7u, 0x82u},\r
- {0xA8u, 0x40u},\r
- {0xACu, 0x02u},\r
- {0xAEu, 0xC0u},\r
- {0xB2u, 0x08u},\r
- {0xB3u, 0x12u},\r
- {0xB5u, 0x40u},\r
- {0xC0u, 0xFFu},\r
- {0xC2u, 0x67u},\r
- {0xC4u, 0x7Eu},\r
- {0xCAu, 0x7Eu},\r
- {0xCCu, 0xF9u},\r
- {0xCEu, 0x7Eu},\r
+ {0x05u, 0x01u},\r
+ {0x06u, 0x10u},\r
+ {0x07u, 0x40u},\r
+ {0x08u, 0x80u},\r
+ {0x09u, 0x04u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Bu, 0x81u},\r
+ {0x0Du, 0x04u},\r
+ {0x0Fu, 0x09u},\r
+ {0x10u, 0x04u},\r
+ {0x13u, 0x1Au},\r
+ {0x14u, 0x12u},\r
+ {0x15u, 0x04u},\r
+ {0x16u, 0x08u},\r
+ {0x17u, 0x02u},\r
+ {0x18u, 0x01u},\r
+ {0x19u, 0x14u},\r
+ {0x1Au, 0x04u},\r
+ {0x1Bu, 0x09u},\r
+ {0x1Du, 0x01u},\r
+ {0x21u, 0xA4u},\r
+ {0x22u, 0x04u},\r
+ {0x23u, 0x24u},\r
+ {0x26u, 0x01u},\r
+ {0x28u, 0x11u},\r
+ {0x2Au, 0x12u},\r
+ {0x2Fu, 0x02u},\r
+ {0x30u, 0x20u},\r
+ {0x32u, 0x44u},\r
+ {0x36u, 0x05u},\r
+ {0x37u, 0x60u},\r
+ {0x3Au, 0x41u},\r
+ {0x3Bu, 0x04u},\r
+ {0x3Cu, 0x0Au},\r
+ {0x3Du, 0x0Cu},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x82u},\r
+ {0x44u, 0x80u},\r
+ {0x45u, 0x80u},\r
+ {0x46u, 0x41u},\r
+ {0x58u, 0x44u},\r
+ {0x59u, 0x20u},\r
+ {0x5Bu, 0x01u},\r
+ {0x5Eu, 0x60u},\r
+ {0x5Fu, 0x10u},\r
+ {0x60u, 0x01u},\r
+ {0x64u, 0x01u},\r
+ {0x82u, 0x0Au},\r
+ {0x87u, 0x08u},\r
+ {0x89u, 0x08u},\r
+ {0x8Au, 0x01u},\r
+ {0x8Eu, 0x40u},\r
+ {0x90u, 0x24u},\r
+ {0x91u, 0x20u},\r
+ {0x92u, 0x10u},\r
+ {0x93u, 0x40u},\r
+ {0x95u, 0x08u},\r
+ {0x98u, 0x40u},\r
+ {0x99u, 0x20u},\r
+ {0x9Cu, 0x89u},\r
+ {0x9Du, 0x54u},\r
+ {0x9Eu, 0x21u},\r
+ {0x9Fu, 0x02u},\r
+ {0xA0u, 0x18u},\r
+ {0xA2u, 0x10u},\r
+ {0xA3u, 0x40u},\r
+ {0xA4u, 0x05u},\r
+ {0xA5u, 0x20u},\r
+ {0xA6u, 0x0Eu},\r
+ {0xA7u, 0x02u},\r
+ {0xABu, 0x40u},\r
+ {0xACu, 0x04u},\r
+ {0xAEu, 0x01u},\r
+ {0xB0u, 0x42u},\r
+ {0xB2u, 0x80u},\r
+ {0xB7u, 0x08u},\r
+ {0xC0u, 0x3Fu},\r
+ {0xC2u, 0xEFu},\r
+ {0xC4u, 0xFEu},\r
+ {0xCAu, 0x1Fu},\r
+ {0xCCu, 0xFEu},\r
+ {0xCEu, 0x7Bu},\r
{0xD6u, 0x1Fu},\r
- {0xD8u, 0x08u},\r
+ {0xD8u, 0x18u},\r
{0xE2u, 0x08u},\r
- {0xE6u, 0x05u},\r
- {0xE8u, 0x0Cu},\r
- {0xEAu, 0x20u},\r
- {0xEEu, 0x1Eu},\r
- {0x05u, 0x50u},\r
- {0x07u, 0xA0u},\r
- {0x0Au, 0x10u},\r
- {0x0Bu, 0xFFu},\r
- {0x0Du, 0x0Fu},\r
- {0x0Eu, 0x08u},\r
- {0x0Fu, 0xF0u},\r
- {0x11u, 0x90u},\r
- {0x13u, 0x60u},\r
- {0x15u, 0x05u},\r
- {0x17u, 0x0Au},\r
- {0x1Au, 0x01u},\r
- {0x1Bu, 0xFFu},\r
- {0x1Eu, 0x05u},\r
- {0x1Fu, 0xFFu},\r
- {0x22u, 0x03u},\r
- {0x24u, 0x06u},\r
- {0x25u, 0x30u},\r
- {0x27u, 0xC0u},\r
- {0x29u, 0x09u},\r
- {0x2Bu, 0x06u},\r
- {0x2Cu, 0x08u},\r
- {0x2Du, 0x03u},\r
- {0x2Eu, 0x10u},\r
- {0x2Fu, 0x0Cu},\r
- {0x33u, 0xFFu},\r
- {0x34u, 0x07u},\r
- {0x36u, 0x18u},\r
+ {0xE6u, 0x2Fu},\r
+ {0xEAu, 0x9Cu},\r
+ {0xECu, 0x02u},\r
+ {0xEEu, 0x80u},\r
+ {0x00u, 0x10u},\r
+ {0x02u, 0x20u},\r
+ {0x04u, 0x08u},\r
+ {0x05u, 0x09u},\r
+ {0x06u, 0x04u},\r
+ {0x07u, 0x02u},\r
+ {0x08u, 0x04u},\r
+ {0x0Au, 0x08u},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Cu, 0x08u},\r
+ {0x0Eu, 0x04u},\r
+ {0x10u, 0x08u},\r
+ {0x11u, 0x10u},\r
+ {0x12u, 0x06u},\r
+ {0x13u, 0x20u},\r
+ {0x16u, 0x10u},\r
+ {0x1Bu, 0x07u},\r
+ {0x1Du, 0x04u},\r
+ {0x1Fu, 0x08u},\r
+ {0x20u, 0x08u},\r
+ {0x22u, 0x05u},\r
+ {0x27u, 0x10u},\r
+ {0x29u, 0x0Au},\r
+ {0x2Au, 0x20u},\r
+ {0x2Bu, 0x05u},\r
+ {0x2Fu, 0x20u},\r
+ {0x30u, 0x01u},\r
+ {0x32u, 0x0Cu},\r
+ {0x34u, 0x02u},\r
+ {0x35u, 0x0Fu},\r
+ {0x36u, 0x30u},\r
+ {0x37u, 0x30u},\r
+ {0x3Au, 0x08u},\r
{0x3Eu, 0x40u},\r
- {0x3Fu, 0x04u},\r
+ {0x3Fu, 0x40u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x11u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x10u},\r
- {0x84u, 0x01u},\r
- {0x88u, 0x40u},\r
- {0x89u, 0x60u},\r
- {0x8Bu, 0x90u},\r
- {0x8Cu, 0x87u},\r
- {0x8Du, 0x0Fu},\r
- {0x8Eu, 0x18u},\r
- {0x8Fu, 0xF0u},\r
- {0x90u, 0x88u},\r
- {0x92u, 0x21u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x50u},\r
- {0x97u, 0xA0u},\r
- {0x98u, 0x40u},\r
- {0x99u, 0x05u},\r
- {0x9Bu, 0x0Au},\r
- {0x9Cu, 0x01u},\r
- {0xA0u, 0x01u},\r
- {0xA1u, 0x06u},\r
- {0xA3u, 0x09u},\r
- {0xA4u, 0x01u},\r
- {0xA5u, 0x03u},\r
- {0xA7u, 0x0Cu},\r
- {0xA8u, 0xA2u},\r
- {0xAAu, 0x08u},\r
- {0xACu, 0x01u},\r
- {0xADu, 0x30u},\r
- {0xAFu, 0xC0u},\r
- {0xB0u, 0x08u},\r
- {0xB2u, 0x40u},\r
- {0xB4u, 0x3Fu},\r
- {0xB5u, 0xFFu},\r
- {0xB6u, 0x80u},\r
- {0xB8u, 0x28u},\r
- {0xBEu, 0x51u},\r
- {0xBFu, 0x10u},\r
- {0xD4u, 0x09u},\r
- {0xD6u, 0x04u},\r
- {0xD8u, 0x04u},\r
+ {0x85u, 0x02u},\r
+ {0x86u, 0x82u},\r
+ {0x87u, 0x05u},\r
+ {0x88u, 0x11u},\r
+ {0x89u, 0x02u},\r
+ {0x8Au, 0x02u},\r
+ {0x8Bu, 0x09u},\r
+ {0x8Du, 0x02u},\r
+ {0x8Fu, 0x01u},\r
+ {0x90u, 0x48u},\r
+ {0x91u, 0x01u},\r
+ {0x92u, 0x03u},\r
+ {0x93u, 0x02u},\r
+ {0x96u, 0x7Cu},\r
+ {0x9Au, 0x01u},\r
+ {0xA4u, 0x04u},\r
+ {0xA6u, 0x23u},\r
+ {0xA8u, 0x70u},\r
+ {0xADu, 0x02u},\r
+ {0xAFu, 0x11u},\r
+ {0xB1u, 0x04u},\r
+ {0xB2u, 0x0Fu},\r
+ {0xB3u, 0x08u},\r
+ {0xB4u, 0x80u},\r
+ {0xB5u, 0x10u},\r
+ {0xB6u, 0x70u},\r
+ {0xB7u, 0x03u},\r
+ {0xBBu, 0x80u},\r
+ {0xBEu, 0x40u},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDCu, 0x10u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0xA0u},\r
- {0x01u, 0x04u},\r
+ {0x00u, 0x04u},\r
{0x02u, 0x40u},\r
- {0x04u, 0x20u},\r
- {0x06u, 0x02u},\r
- {0x0Au, 0xA9u},\r
- {0x0Eu, 0x04u},\r
- {0x0Fu, 0x02u},\r
- {0x10u, 0x02u},\r
- {0x11u, 0x01u},\r
- {0x12u, 0x08u},\r
- {0x13u, 0x04u},\r
- {0x15u, 0x4Au},\r
- {0x19u, 0x40u},\r
- {0x1Au, 0x68u},\r
- {0x1Bu, 0x04u},\r
- {0x1Eu, 0x04u},\r
- {0x1Fu, 0x80u},\r
- {0x22u, 0x20u},\r
- {0x23u, 0x08u},\r
- {0x27u, 0x20u},\r
- {0x29u, 0x80u},\r
- {0x2Au, 0x8Au},\r
- {0x2Cu, 0x20u},\r
- {0x2Eu, 0x20u},\r
+ {0x03u, 0x0Eu},\r
+ {0x06u, 0x10u},\r
+ {0x07u, 0x08u},\r
+ {0x0Au, 0x60u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Eu, 0x14u},\r
+ {0x12u, 0x84u},\r
+ {0x16u, 0x20u},\r
+ {0x17u, 0x10u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x04u},\r
+ {0x1Au, 0x48u},\r
+ {0x1Bu, 0x48u},\r
+ {0x1Cu, 0x02u},\r
+ {0x1Eu, 0x14u},\r
+ {0x20u, 0x01u},\r
+ {0x22u, 0x50u},\r
+ {0x23u, 0x02u},\r
+ {0x24u, 0x42u},\r
+ {0x25u, 0x14u},\r
+ {0x27u, 0x01u},\r
+ {0x29u, 0x14u},\r
+ {0x2Bu, 0x01u},\r
{0x2Fu, 0x01u},\r
- {0x30u, 0x08u},\r
- {0x31u, 0x20u},\r
- {0x34u, 0x04u},\r
- {0x36u, 0xA0u},\r
- {0x37u, 0x01u},\r
+ {0x30u, 0x82u},\r
+ {0x32u, 0x10u},\r
+ {0x36u, 0x08u},\r
+ {0x37u, 0x09u},\r
{0x38u, 0x20u},\r
- {0x39u, 0x40u},\r
- {0x3Cu, 0x08u},\r
- {0x3Du, 0x50u},\r
- {0x59u, 0x19u},\r
- {0x5Au, 0x40u},\r
- {0x61u, 0x42u},\r
- {0x81u, 0x02u},\r
- {0x87u, 0x81u},\r
- {0x89u, 0x20u},\r
+ {0x39u, 0x08u},\r
+ {0x3Cu, 0x40u},\r
+ {0x3Du, 0x28u},\r
+ {0x44u, 0x80u},\r
+ {0x47u, 0x01u},\r
+ {0x49u, 0x80u},\r
+ {0x4Au, 0x01u},\r
+ {0x58u, 0x10u},\r
+ {0x5Bu, 0x40u},\r
+ {0x5Du, 0x40u},\r
+ {0x62u, 0xA0u},\r
+ {0x63u, 0x0Au},\r
+ {0x67u, 0x02u},\r
+ {0x68u, 0x02u},\r
+ {0x6Cu, 0x24u},\r
+ {0x6Du, 0x80u},\r
+ {0x6Eu, 0x08u},\r
+ {0x83u, 0x44u},\r
+ {0x84u, 0x08u},\r
+ {0x85u, 0x40u},\r
+ {0x88u, 0x10u},\r
+ {0x8Bu, 0x01u},\r
+ {0x8Cu, 0x41u},\r
+ {0x8Du, 0x01u},\r
+ {0x8Fu, 0x40u},\r
{0x90u, 0x20u},\r
- {0x91u, 0x50u},\r
- {0x93u, 0x02u},\r
- {0x95u, 0x80u},\r
- {0x98u, 0x04u},\r
- {0x9Au, 0xA2u},\r
- {0x9Bu, 0x01u},\r
- {0x9Cu, 0x40u},\r
- {0x9Fu, 0x28u},\r
- {0xA0u, 0x2Cu},\r
- {0xA1u, 0x20u},\r
- {0xA3u, 0x08u},\r
- {0xA6u, 0xA0u},\r
- {0xA8u, 0x20u},\r
- {0xABu, 0x04u},\r
- {0xACu, 0x10u},\r
- {0xAEu, 0x28u},\r
- {0xB1u, 0x02u},\r
- {0xB3u, 0x20u},\r
- {0xB4u, 0x02u},\r
- {0xC0u, 0xCFu},\r
- {0xC2u, 0xCFu},\r
- {0xC4u, 0xBFu},\r
- {0xCAu, 0x7Bu},\r
- {0xCCu, 0xF6u},\r
- {0xCEu, 0x7Cu},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x09u},\r
- {0xE0u, 0x02u},\r
- {0xE2u, 0x08u},\r
- {0xE4u, 0x08u},\r
- {0xE6u, 0x01u},\r
- {0xEAu, 0x01u},\r
+ {0x91u, 0x28u},\r
+ {0x93u, 0xC0u},\r
+ {0x96u, 0x82u},\r
+ {0x9Cu, 0x8Au},\r
+ {0x9Du, 0x40u},\r
+ {0x9Eu, 0x20u},\r
+ {0x9Fu, 0x02u},\r
+ {0xA0u, 0x98u},\r
+ {0xA2u, 0x11u},\r
+ {0xA4u, 0x24u},\r
+ {0xA5u, 0x08u},\r
+ {0xA6u, 0x2Eu},\r
+ {0xA7u, 0x04u},\r
+ {0xA8u, 0x84u},\r
+ {0xAAu, 0x04u},\r
+ {0xABu, 0x02u},\r
+ {0xB1u, 0x14u},\r
+ {0xB3u, 0x41u},\r
+ {0xC0u, 0x6Fu},\r
+ {0xC2u, 0x7Cu},\r
+ {0xC4u, 0x6Au},\r
+ {0xCAu, 0x1Eu},\r
+ {0xCCu, 0x8Du},\r
+ {0xCEu, 0x76u},\r
+ {0xD6u, 0x1Cu},\r
+ {0xD8u, 0x1Cu},\r
+ {0xE0u, 0x01u},\r
+ {0xE2u, 0x04u},\r
+ {0xE6u, 0x09u},\r
+ {0xE8u, 0x04u},\r
{0xECu, 0x04u},\r
- {0xEEu, 0x02u},\r
- {0x00u, 0x50u},\r
- {0x02u, 0xA0u},\r
- {0x06u, 0x20u},\r
- {0x0Au, 0x08u},\r
- {0x0Du, 0x01u},\r
- {0x0Eu, 0x40u},\r
- {0x0Fu, 0x02u},\r
- {0x10u, 0x09u},\r
- {0x12u, 0x02u},\r
- {0x13u, 0x02u},\r
- {0x16u, 0x07u},\r
+ {0x00u, 0xE0u},\r
+ {0x08u, 0xCAu},\r
+ {0x0Au, 0x15u},\r
+ {0x0Cu, 0x40u},\r
+ {0x0Eu, 0x80u},\r
+ {0x11u, 0x01u},\r
+ {0x14u, 0x06u},\r
+ {0x18u, 0x01u},\r
+ {0x1Cu, 0x11u},\r
+ {0x1Eu, 0xECu},\r
+ {0x22u, 0xFFu},\r
+ {0x24u, 0x0Bu},\r
+ {0x26u, 0xF4u},\r
+ {0x2Au, 0x10u},\r
+ {0x2Cu, 0x40u},\r
+ {0x2Eu, 0x80u},\r
+ {0x33u, 0x01u},\r
+ {0x34u, 0x3Fu},\r
+ {0x36u, 0xC0u},\r
+ {0x38u, 0x08u},\r
+ {0x3Au, 0x80u},\r
+ {0x3Eu, 0x04u},\r
+ {0x56u, 0x08u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x91u},\r
+ {0x5Du, 0x90u},\r
+ {0x5Fu, 0x01u},\r
+ {0x80u, 0x05u},\r
+ {0x82u, 0x0Au},\r
+ {0x85u, 0x50u},\r
+ {0x87u, 0xA0u},\r
+ {0x88u, 0x06u},\r
+ {0x8Au, 0x09u},\r
+ {0x8Cu, 0x30u},\r
+ {0x8Du, 0x30u},\r
+ {0x8Eu, 0xC0u},\r
+ {0x8Fu, 0xC0u},\r
+ {0x90u, 0x03u},\r
+ {0x92u, 0x0Cu},\r
+ {0x94u, 0x50u},\r
+ {0x96u, 0xA0u},\r
+ {0x99u, 0x06u},\r
+ {0x9Au, 0xFFu},\r
+ {0x9Bu, 0x09u},\r
+ {0x9Du, 0x03u},\r
+ {0x9Eu, 0xFFu},\r
+ {0x9Fu, 0x0Cu},\r
+ {0xA0u, 0x0Fu},\r
+ {0xA2u, 0xF0u},\r
+ {0xA5u, 0x60u},\r
+ {0xA7u, 0x90u},\r
+ {0xA8u, 0xFFu},\r
+ {0xA9u, 0x05u},\r
+ {0xABu, 0x0Au},\r
+ {0xACu, 0x60u},\r
+ {0xADu, 0x0Fu},\r
+ {0xAEu, 0x90u},\r
+ {0xAFu, 0xF0u},\r
+ {0xB0u, 0xFFu},\r
+ {0xB5u, 0xFFu},\r
+ {0xBEu, 0x01u},\r
+ {0xBFu, 0x10u},\r
+ {0xD4u, 0x09u},\r
+ {0xD6u, 0x04u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDFu, 0x01u},\r
+ {0x00u, 0x80u},\r
+ {0x03u, 0x84u},\r
+ {0x04u, 0x01u},\r
+ {0x05u, 0x50u},\r
+ {0x09u, 0x01u},\r
+ {0x0Au, 0x10u},\r
+ {0x0Bu, 0x06u},\r
+ {0x0Cu, 0x80u},\r
+ {0x0Eu, 0x28u},\r
+ {0x10u, 0x02u},\r
+ {0x12u, 0x40u},\r
+ {0x13u, 0x10u},\r
+ {0x14u, 0x02u},\r
+ {0x15u, 0x28u},\r
{0x17u, 0x01u},\r
- {0x18u, 0x04u},\r
- {0x1Au, 0x08u},\r
- {0x1Eu, 0x10u},\r
- {0x1Fu, 0x1Cu},\r
- {0x21u, 0x24u},\r
- {0x22u, 0x80u},\r
- {0x23u, 0x08u},\r
- {0x25u, 0x10u},\r
- {0x27u, 0x20u},\r
- {0x28u, 0x0Au},\r
- {0x29u, 0x28u},\r
- {0x2Au, 0x05u},\r
- {0x2Bu, 0x14u},\r
- {0x2Fu, 0x20u},\r
- {0x31u, 0x3Cu},\r
- {0x32u, 0x0Fu},\r
- {0x34u, 0xC0u},\r
- {0x35u, 0x03u},\r
- {0x36u, 0x30u},\r
- {0x3Eu, 0x50u},\r
- {0x3Fu, 0x10u},\r
+ {0x18u, 0x80u},\r
+ {0x1Cu, 0x08u},\r
+ {0x1Du, 0x50u},\r
+ {0x1Fu, 0x08u},\r
+ {0x23u, 0x04u},\r
+ {0x25u, 0x08u},\r
+ {0x29u, 0x20u},\r
+ {0x2Au, 0x4Cu},\r
+ {0x32u, 0x50u},\r
+ {0x37u, 0x01u},\r
+ {0x38u, 0x0Cu},\r
+ {0x3Au, 0x80u},\r
+ {0x58u, 0xA0u},\r
+ {0x59u, 0x05u},\r
+ {0x5Du, 0x40u},\r
+ {0x62u, 0x80u},\r
+ {0x63u, 0x80u},\r
+ {0x64u, 0x02u},\r
+ {0x68u, 0x02u},\r
+ {0x69u, 0x10u},\r
+ {0x6Au, 0x16u},\r
+ {0x70u, 0x04u},\r
+ {0x72u, 0x8Au},\r
+ {0x81u, 0x20u},\r
+ {0x82u, 0x02u},\r
+ {0x87u, 0x80u},\r
+ {0x89u, 0x10u},\r
+ {0x8Bu, 0x14u},\r
+ {0x8Du, 0x10u},\r
+ {0x90u, 0x01u},\r
+ {0x91u, 0x28u},\r
+ {0x92u, 0x28u},\r
+ {0x93u, 0xC0u},\r
+ {0x94u, 0x80u},\r
+ {0x96u, 0x02u},\r
+ {0x99u, 0x80u},\r
+ {0x9Bu, 0x01u},\r
+ {0x9Cu, 0x12u},\r
+ {0x9Du, 0x50u},\r
+ {0x9Eu, 0xF4u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA0u, 0x89u},\r
+ {0xA1u, 0x01u},\r
+ {0xA2u, 0x14u},\r
+ {0xA4u, 0x04u},\r
+ {0xA5u, 0x0Au},\r
+ {0xA6u, 0x0Au},\r
+ {0xA7u, 0x02u},\r
+ {0xA8u, 0x04u},\r
+ {0xA9u, 0x40u},\r
+ {0xAEu, 0x80u},\r
+ {0xB4u, 0x01u},\r
+ {0xC0u, 0xDBu},\r
+ {0xC2u, 0xEFu},\r
+ {0xC4u, 0xFBu},\r
+ {0xCAu, 0x0Eu},\r
+ {0xCCu, 0x8Cu},\r
+ {0xCEu, 0x0Au},\r
+ {0xD6u, 0x1Fu},\r
+ {0xD8u, 0x19u},\r
+ {0xE4u, 0x05u},\r
+ {0xE6u, 0x08u},\r
+ {0xE8u, 0x02u},\r
+ {0x00u, 0x0Fu},\r
+ {0x01u, 0x80u},\r
+ {0x02u, 0xF0u},\r
+ {0x03u, 0x50u},\r
+ {0x04u, 0x30u},\r
+ {0x05u, 0x04u},\r
+ {0x06u, 0xC0u},\r
+ {0x07u, 0x08u},\r
+ {0x08u, 0x09u},\r
+ {0x09u, 0x80u},\r
+ {0x0Au, 0x06u},\r
+ {0x0Bu, 0x40u},\r
+ {0x0Cu, 0x03u},\r
+ {0x0Eu, 0x0Cu},\r
+ {0x0Fu, 0x07u},\r
+ {0x11u, 0x80u},\r
+ {0x12u, 0xFFu},\r
+ {0x13u, 0x60u},\r
+ {0x14u, 0x50u},\r
+ {0x15u, 0x80u},\r
+ {0x16u, 0xA0u},\r
+ {0x17u, 0x40u},\r
+ {0x19u, 0x40u},\r
+ {0x1Au, 0xFFu},\r
+ {0x1Bu, 0x80u},\r
+ {0x1Cu, 0x90u},\r
+ {0x1Eu, 0x60u},\r
+ {0x20u, 0x05u},\r
+ {0x21u, 0x0Au},\r
+ {0x22u, 0x0Au},\r
+ {0x23u, 0x05u},\r
+ {0x26u, 0xFFu},\r
+ {0x27u, 0x08u},\r
+ {0x2Du, 0x09u},\r
+ {0x2Fu, 0x02u},\r
+ {0x31u, 0x0Fu},\r
+ {0x33u, 0xC0u},\r
+ {0x35u, 0x20u},\r
+ {0x36u, 0xFFu},\r
+ {0x37u, 0x10u},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Eu, 0x40u},\r
+ {0x54u, 0x40u},\r
+ {0x56u, 0x04u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x11u},\r
+ {0x5Cu, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0xFFu},\r
- {0x81u, 0x02u},\r
- {0x83u, 0x01u},\r
- {0x86u, 0xFFu},\r
- {0x88u, 0xFFu},\r
- {0x8Eu, 0xFFu},\r
- {0x90u, 0x96u},\r
- {0x92u, 0x69u},\r
- {0x94u, 0x0Fu},\r
- {0x95u, 0x01u},\r
- {0x96u, 0xF0u},\r
- {0x97u, 0x02u},\r
- {0x99u, 0x02u},\r
- {0x9Bu, 0x05u},\r
- {0x9Du, 0x02u},\r
- {0x9Fu, 0x09u},\r
- {0xA0u, 0x33u},\r
- {0xA2u, 0xCCu},\r
- {0xA8u, 0x55u},\r
- {0xAAu, 0xAAu},\r
- {0xADu, 0x02u},\r
- {0xAEu, 0xFFu},\r
- {0xAFu, 0x11u},\r
+ {0x80u, 0x02u},\r
+ {0x82u, 0x01u},\r
+ {0x84u, 0x01u},\r
+ {0x86u, 0x02u},\r
+ {0x8Bu, 0x04u},\r
+ {0x8Du, 0x12u},\r
+ {0x8Fu, 0x24u},\r
+ {0x93u, 0x01u},\r
+ {0x94u, 0x02u},\r
+ {0x96u, 0x01u},\r
+ {0x97u, 0x08u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Eu, 0x01u},\r
+ {0xA3u, 0x10u},\r
+ {0xA7u, 0x02u},\r
+ {0xA8u, 0x02u},\r
+ {0xAAu, 0x01u},\r
+ {0xABu, 0x20u},\r
{0xB1u, 0x08u},\r
- {0xB3u, 0x03u},\r
- {0xB4u, 0xFFu},\r
- {0xB5u, 0x10u},\r
- {0xB7u, 0x04u},\r
+ {0xB3u, 0x01u},\r
+ {0xB4u, 0x03u},\r
+ {0xB5u, 0x30u},\r
+ {0xB7u, 0x06u},\r
{0xBAu, 0x20u},\r
- {0xBBu, 0x08u},\r
+ {0xBFu, 0x50u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDCu, 0x11u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x4Au},\r
- {0x03u, 0x08u},\r
- {0x04u, 0x80u},\r
- {0x05u, 0x22u},\r
- {0x06u, 0x90u},\r
- {0x08u, 0x02u},\r
- {0x0Bu, 0x10u},\r
- {0x0Cu, 0xA2u},\r
- {0x0Eu, 0x28u},\r
- {0x10u, 0x02u},\r
- {0x12u, 0x84u},\r
- {0x14u, 0x04u},\r
- {0x16u, 0x40u},\r
- {0x1Bu, 0x10u},\r
- {0x1Eu, 0x22u},\r
- {0x1Fu, 0x10u},\r
- {0x21u, 0x09u},\r
- {0x22u, 0x50u},\r
- {0x24u, 0x88u},\r
- {0x27u, 0x40u},\r
- {0x29u, 0x40u},\r
- {0x2Cu, 0x24u},\r
- {0x2Fu, 0x49u},\r
+ {0x00u, 0x04u},\r
+ {0x02u, 0x80u},\r
+ {0x04u, 0x12u},\r
+ {0x05u, 0x40u},\r
+ {0x06u, 0x14u},\r
+ {0x09u, 0x08u},\r
+ {0x0Au, 0x02u},\r
+ {0x0Cu, 0x84u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Eu, 0x20u},\r
+ {0x0Fu, 0x08u},\r
+ {0x13u, 0x10u},\r
+ {0x14u, 0x40u},\r
+ {0x15u, 0x02u},\r
+ {0x17u, 0x08u},\r
+ {0x18u, 0x04u},\r
+ {0x1Fu, 0x80u},\r
+ {0x21u, 0x40u},\r
+ {0x22u, 0x11u},\r
+ {0x23u, 0x10u},\r
+ {0x24u, 0x40u},\r
+ {0x25u, 0x10u},\r
+ {0x26u, 0x21u},\r
+ {0x27u, 0x11u},\r
+ {0x28u, 0x44u},\r
+ {0x29u, 0x04u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Eu, 0x02u},\r
+ {0x2Fu, 0x02u},\r
{0x31u, 0x08u},\r
- {0x32u, 0x50u},\r
- {0x36u, 0x02u},\r
- {0x37u, 0x48u},\r
- {0x39u, 0x02u},\r
- {0x3Eu, 0x80u},\r
- {0x4Fu, 0x30u},\r
+ {0x32u, 0x01u},\r
+ {0x34u, 0x20u},\r
+ {0x37u, 0x15u},\r
+ {0x38u, 0x20u},\r
+ {0x39u, 0x40u},\r
+ {0x3Cu, 0x40u},\r
+ {0x3Du, 0x28u},\r
+ {0x3Fu, 0x02u},\r
{0x58u, 0x80u},\r
- {0x5Cu, 0x20u},\r
- {0x5Eu, 0x44u},\r
- {0x5Fu, 0x02u},\r
- {0x60u, 0x02u},\r
- {0x64u, 0x01u},\r
- {0x81u, 0x20u},\r
- {0x82u, 0x40u},\r
- {0x86u, 0x10u},\r
- {0x88u, 0x04u},\r
- {0x8Bu, 0x0Au},\r
- {0x8Cu, 0x04u},\r
- {0x90u, 0x42u},\r
- {0x92u, 0x04u},\r
- {0x93u, 0x82u},\r
- {0x95u, 0x10u},\r
- {0x97u, 0x20u},\r
- {0x99u, 0x62u},\r
- {0x9Au, 0x04u},\r
- {0xA0u, 0x07u},\r
- {0xA1u, 0x20u},\r
- {0xA2u, 0x84u},\r
- {0xA3u, 0x08u},\r
- {0xA5u, 0x08u},\r
- {0xA6u, 0x10u},\r
- {0xA7u, 0x10u},\r
- {0xA8u, 0x40u},\r
+ {0x63u, 0x02u},\r
+ {0x66u, 0x28u},\r
+ {0x67u, 0x82u},\r
+ {0x6Cu, 0x03u},\r
+ {0x6Du, 0x40u},\r
+ {0x81u, 0x04u},\r
+ {0x83u, 0x20u},\r
+ {0x84u, 0x40u},\r
+ {0x89u, 0x02u},\r
+ {0x8Au, 0x10u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Du, 0x08u},\r
+ {0x8Eu, 0x02u},\r
+ {0x90u, 0x10u},\r
+ {0x91u, 0x02u},\r
+ {0x92u, 0x08u},\r
+ {0x95u, 0x80u},\r
+ {0x96u, 0x40u},\r
+ {0x97u, 0x80u},\r
+ {0x99u, 0x40u},\r
+ {0x9Bu, 0x0Cu},\r
+ {0x9Cu, 0x26u},\r
+ {0x9Du, 0x08u},\r
+ {0x9Eu, 0x12u},\r
+ {0xA0u, 0x20u},\r
+ {0xA1u, 0x0Cu},\r
+ {0xA2u, 0x80u},\r
+ {0xA3u, 0x02u},\r
+ {0xA4u, 0x82u},\r
+ {0xA5u, 0x02u},\r
+ {0xA6u, 0x20u},\r
+ {0xA7u, 0xA0u},\r
+ {0xA9u, 0x40u},\r
{0xAAu, 0x04u},\r
- {0xACu, 0x44u},\r
{0xAEu, 0x01u},\r
- {0xAFu, 0x20u},\r
- {0xB5u, 0x84u},\r
- {0xB7u, 0x10u},\r
- {0xC0u, 0xFFu},\r
- {0xC2u, 0xFCu},\r
- {0xC4u, 0x5Bu},\r
- {0xCAu, 0xF8u},\r
- {0xCCu, 0xDEu},\r
- {0xCEu, 0x11u},\r
- {0xD6u, 0xF8u},\r
- {0xD8u, 0x18u},\r
- {0xE2u, 0x08u},\r
- {0xE4u, 0x88u},\r
- {0xE6u, 0x01u},\r
- {0xEAu, 0x19u},\r
- {0x00u, 0xFFu},\r
- {0x06u, 0xFFu},\r
- {0x08u, 0xFFu},\r
- {0x09u, 0x02u},\r
- {0x0Bu, 0x09u},\r
- {0x0Eu, 0xFFu},\r
- {0x12u, 0xFFu},\r
- {0x14u, 0x33u},\r
- {0x15u, 0x02u},\r
- {0x16u, 0xCCu},\r
- {0x17u, 0x01u},\r
- {0x19u, 0x01u},\r
- {0x1Bu, 0x02u},\r
- {0x1Cu, 0x0Fu},\r
- {0x1Du, 0x02u},\r
- {0x1Eu, 0xF0u},\r
- {0x1Fu, 0x05u},\r
- {0x24u, 0x69u},\r
- {0x26u, 0x96u},\r
- {0x28u, 0x55u},\r
- {0x2Au, 0xAAu},\r
- {0x2Du, 0x02u},\r
+ {0xAFu, 0x04u},\r
+ {0xB6u, 0x40u},\r
+ {0xB7u, 0x20u},\r
+ {0xC0u, 0xFCu},\r
+ {0xC2u, 0xF5u},\r
+ {0xC4u, 0x32u},\r
+ {0xCAu, 0xD7u},\r
+ {0xCCu, 0xE3u},\r
+ {0xCEu, 0xFCu},\r
+ {0xD6u, 0x08u},\r
+ {0xD8u, 0xF8u},\r
+ {0xE0u, 0xC0u},\r
+ {0xE4u, 0x20u},\r
+ {0xE6u, 0x80u},\r
+ {0xE8u, 0x01u},\r
+ {0xECu, 0x16u},\r
+ {0x04u, 0x0Au},\r
+ {0x06u, 0x05u},\r
+ {0x07u, 0x02u},\r
+ {0x0Au, 0x17u},\r
+ {0x0Cu, 0x09u},\r
+ {0x0Eu, 0x02u},\r
+ {0x11u, 0x01u},\r
+ {0x13u, 0x02u},\r
+ {0x14u, 0x04u},\r
+ {0x16u, 0x08u},\r
+ {0x1Au, 0x08u},\r
+ {0x1Fu, 0x04u},\r
+ {0x22u, 0x20u},\r
+ {0x2Cu, 0x10u},\r
+ {0x2Eu, 0x20u},\r
{0x2Fu, 0x01u},\r
+ {0x31u, 0x03u},\r
+ {0x32u, 0x0Fu},\r
{0x33u, 0x04u},\r
- {0x35u, 0x03u},\r
- {0x36u, 0xFFu},\r
- {0x37u, 0x08u},\r
- {0x3Au, 0x80u},\r
- {0x3Bu, 0x20u},\r
+ {0x34u, 0x30u},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x01u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x0Fu},\r
- {0x84u, 0x40u},\r
- {0x86u, 0x80u},\r
- {0x87u, 0x0Fu},\r
- {0x88u, 0x40u},\r
- {0x89u, 0x04u},\r
- {0x8Au, 0x80u},\r
- {0x8Bu, 0x08u},\r
- {0x8Cu, 0x06u},\r
- {0x8Eu, 0xE1u},\r
- {0x8Fu, 0x0Fu},\r
- {0x93u, 0x0Fu},\r
- {0x94u, 0xD0u},\r
- {0x95u, 0x01u},\r
- {0x96u, 0x21u},\r
- {0x97u, 0x02u},\r
- {0x99u, 0x04u},\r
- {0x9Bu, 0x08u},\r
- {0x9Cu, 0x16u},\r
- {0x9Eu, 0xE1u},\r
- {0xA0u, 0x01u},\r
- {0xA2u, 0x02u},\r
- {0xA3u, 0x10u},\r
- {0xA4u, 0x08u},\r
- {0xA6u, 0xC1u},\r
- {0xA9u, 0x0Fu},\r
- {0xAAu, 0x04u},\r
- {0xACu, 0xC0u},\r
- {0xADu, 0x01u},\r
- {0xAEu, 0x21u},\r
- {0xAFu, 0x02u},\r
- {0xB2u, 0xC0u},\r
- {0xB3u, 0x03u},\r
+ {0x82u, 0x80u},\r
+ {0x84u, 0x0Fu},\r
+ {0x85u, 0x10u},\r
+ {0x87u, 0x20u},\r
+ {0x88u, 0x04u},\r
+ {0x89u, 0x01u},\r
+ {0x8Au, 0x08u},\r
+ {0x8Cu, 0xAFu},\r
+ {0x8Eu, 0x50u},\r
+ {0x8Fu, 0x1Cu},\r
+ {0x90u, 0x40u},\r
+ {0x91u, 0x01u},\r
+ {0x92u, 0x8Fu},\r
+ {0x94u, 0x04u},\r
+ {0x95u, 0x28u},\r
+ {0x96u, 0x08u},\r
+ {0x97u, 0x14u},\r
+ {0x98u, 0x01u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Bu, 0x02u},\r
+ {0x9Eu, 0x70u},\r
+ {0xA0u, 0x90u},\r
+ {0xA1u, 0x01u},\r
+ {0xA2u, 0x2Fu},\r
+ {0xA7u, 0x20u},\r
+ {0xA8u, 0x01u},\r
+ {0xA9u, 0x01u},\r
+ {0xAAu, 0x02u},\r
+ {0xADu, 0x24u},\r
+ {0xAEu, 0x0Fu},\r
+ {0xAFu, 0x08u},\r
+ {0xB1u, 0x3Cu},\r
+ {0xB2u, 0x0Cu},\r
+ {0xB3u, 0x01u},\r
{0xB4u, 0x03u},\r
- {0xB5u, 0x0Cu},\r
- {0xB6u, 0x3Cu},\r
- {0xB7u, 0x10u},\r
- {0xB8u, 0x80u},\r
+ {0xB5u, 0x02u},\r
+ {0xB6u, 0xF0u},\r
+ {0xB9u, 0x08u},\r
{0xBAu, 0x28u},\r
- {0xBBu, 0x28u},\r
+ {0xBFu, 0x04u},\r
{0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDCu, 0x11u},\r
- {0xDFu, 0x01u},\r
- {0x00u, 0x4Au},\r
- {0x03u, 0x08u},\r
- {0x04u, 0x50u},\r
- {0x05u, 0x04u},\r
- {0x08u, 0x08u},\r
- {0x0Au, 0x02u},\r
- {0x0Bu, 0x80u},\r
- {0x0Du, 0x04u},\r
- {0x0Eu, 0x02u},\r
- {0x12u, 0x28u},\r
- {0x14u, 0x40u},\r
- {0x15u, 0x84u},\r
- {0x17u, 0x10u},\r
- {0x1Au, 0x02u},\r
- {0x1Du, 0x04u},\r
- {0x1Eu, 0x02u},\r
- {0x1Fu, 0x64u},\r
- {0x21u, 0x20u},\r
- {0x22u, 0x44u},\r
- {0x24u, 0x08u},\r
- {0x25u, 0x14u},\r
- {0x27u, 0x01u},\r
- {0x2Au, 0x40u},\r
- {0x2Du, 0x80u},\r
- {0x2Eu, 0x01u},\r
- {0x2Fu, 0x08u},\r
- {0x31u, 0x20u},\r
- {0x32u, 0x44u},\r
- {0x34u, 0x08u},\r
- {0x35u, 0x10u},\r
- {0x36u, 0x01u},\r
- {0x39u, 0x20u},\r
- {0x3Cu, 0x4Au},\r
- {0x3Du, 0x24u},\r
- {0x41u, 0x04u},\r
- {0x43u, 0x08u},\r
- {0x58u, 0x94u},\r
- {0x60u, 0x18u},\r
- {0x61u, 0x40u},\r
- {0x62u, 0x08u},\r
- {0x80u, 0x04u},\r
- {0x84u, 0x02u},\r
- {0x87u, 0x50u},\r
- {0x88u, 0x10u},\r
- {0x8Fu, 0x20u},\r
- {0x90u, 0x02u},\r
- {0x91u, 0xA0u},\r
- {0x92u, 0x05u},\r
- {0x93u, 0x02u},\r
- {0x95u, 0x10u},\r
- {0x97u, 0x08u},\r
- {0x98u, 0x80u},\r
- {0x99u, 0x32u},\r
- {0x9Au, 0x44u},\r
- {0x9Bu, 0x10u},\r
- {0x9Du, 0x40u},\r
- {0x9Fu, 0x01u},\r
- {0xA0u, 0x05u},\r
- {0xA2u, 0xA0u},\r
- {0xA3u, 0x08u},\r
- {0xA5u, 0x0Cu},\r
- {0xA6u, 0x11u},\r
- {0xA8u, 0x81u},\r
- {0xA9u, 0x80u},\r
- {0xAFu, 0x0Eu},\r
- {0xB0u, 0x04u},\r
- {0xB1u, 0x04u},\r
- {0xB4u, 0x40u},\r
- {0xB5u, 0x02u},\r
- {0xB6u, 0x40u},\r
- {0xB7u, 0x80u},\r
- {0xC0u, 0xEFu},\r
- {0xC2u, 0xADu},\r
- {0xC4u, 0xF6u},\r
- {0xCAu, 0xB8u},\r
- {0xCCu, 0xEEu},\r
- {0xCEu, 0xF4u},\r
- {0xD6u, 0x0Eu},\r
- {0xD8u, 0x0Eu},\r
- {0xE0u, 0x80u},\r
- {0xE2u, 0x40u},\r
- {0xE4u, 0x02u},\r
- {0xE6u, 0x04u},\r
- {0xE8u, 0x40u},\r
- {0xEAu, 0x20u},\r
- {0xEEu, 0x11u},\r
- {0x00u, 0x08u},\r
- {0x02u, 0x10u},\r
- {0x04u, 0x02u},\r
- {0x05u, 0x01u},\r
- {0x06u, 0x01u},\r
- {0x0Du, 0x06u},\r
- {0x0Fu, 0x18u},\r
- {0x12u, 0x10u},\r
- {0x15u, 0x20u},\r
- {0x16u, 0x08u},\r
- {0x18u, 0x01u},\r
- {0x19u, 0x04u},\r
- {0x1Au, 0x02u},\r
- {0x1Bu, 0x02u},\r
+ {0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x11u},\r
+ {0xDFu, 0x01u},\r
+ {0x00u, 0x10u},\r
+ {0x01u, 0x08u},\r
+ {0x03u, 0x02u},\r
+ {0x05u, 0x10u},\r
+ {0x06u, 0x42u},\r
+ {0x07u, 0x20u},\r
+ {0x09u, 0x14u},\r
+ {0x0Du, 0x20u},\r
+ {0x0Eu, 0x22u},\r
+ {0x0Fu, 0x80u},\r
+ {0x10u, 0x82u},\r
+ {0x14u, 0x01u},\r
+ {0x15u, 0x01u},\r
+ {0x16u, 0x04u},\r
+ {0x18u, 0x10u},\r
+ {0x1Au, 0x08u},\r
{0x1Cu, 0x02u},\r
- {0x1Du, 0x02u},\r
- {0x1Eu, 0x01u},\r
+ {0x1Du, 0x60u},\r
+ {0x1Eu, 0x22u},\r
{0x1Fu, 0x04u},\r
- {0x20u, 0x02u},\r
- {0x22u, 0x05u},\r
- {0x25u, 0x08u},\r
- {0x27u, 0x10u},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0x01u},\r
+ {0x24u, 0x40u},\r
+ {0x26u, 0x04u},\r
+ {0x27u, 0x04u},\r
{0x28u, 0x02u},\r
- {0x2Au, 0x21u},\r
- {0x2Du, 0x10u},\r
- {0x2Fu, 0x08u},\r
- {0x30u, 0x18u},\r
- {0x31u, 0x20u},\r
- {0x32u, 0x04u},\r
- {0x33u, 0x01u},\r
- {0x34u, 0x03u},\r
+ {0x2Eu, 0x08u},\r
+ {0x2Fu, 0x8Au},\r
+ {0x30u, 0x02u},\r
+ {0x32u, 0x80u},\r
+ {0x35u, 0x09u},\r
{0x36u, 0x20u},\r
- {0x37u, 0x1Eu},\r
- {0x3Au, 0x20u},\r
+ {0x3Bu, 0x04u},\r
+ {0x3Cu, 0x40u},\r
+ {0x3Du, 0x08u},\r
+ {0x3Eu, 0x10u},\r
+ {0x5Au, 0x80u},\r
+ {0x5Cu, 0x24u},\r
+ {0x5Du, 0x02u},\r
+ {0x5Eu, 0x40u},\r
+ {0x62u, 0x80u},\r
+ {0x67u, 0x01u},\r
+ {0x83u, 0x01u},\r
+ {0x87u, 0x04u},\r
+ {0x88u, 0x01u},\r
+ {0x8Au, 0x40u},\r
+ {0x8Du, 0x02u},\r
+ {0x8Eu, 0x11u},\r
+ {0x90u, 0x04u},\r
+ {0x91u, 0x03u},\r
+ {0x94u, 0x50u},\r
+ {0x97u, 0x80u},\r
+ {0x99u, 0x11u},\r
+ {0x9Au, 0x0Cu},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Cu, 0x04u},\r
+ {0x9Du, 0x4Au},\r
+ {0x9Eu, 0x10u},\r
+ {0x9Fu, 0x20u},\r
+ {0xA0u, 0x20u},\r
+ {0xA1u, 0x14u},\r
+ {0xA3u, 0x4Au},\r
+ {0xA4u, 0x83u},\r
+ {0xA5u, 0x22u},\r
+ {0xA7u, 0x20u},\r
+ {0xA9u, 0x04u},\r
+ {0xAAu, 0x10u},\r
+ {0xABu, 0x44u},\r
+ {0xADu, 0x80u},\r
+ {0xB1u, 0x01u},\r
+ {0xB2u, 0x08u},\r
+ {0xB3u, 0x02u},\r
+ {0xB6u, 0x40u},\r
+ {0xC0u, 0xF7u},\r
+ {0xC2u, 0xF6u},\r
+ {0xC4u, 0xD9u},\r
+ {0xCAu, 0xF8u},\r
+ {0xCCu, 0xE9u},\r
+ {0xCEu, 0x72u},\r
+ {0xD6u, 0xF8u},\r
+ {0xD8u, 0x18u},\r
+ {0xE0u, 0x40u},\r
+ {0xE2u, 0x14u},\r
+ {0xE4u, 0xF0u},\r
+ {0xE6u, 0x01u},\r
+ {0xEAu, 0x08u},\r
+ {0xECu, 0x80u},\r
+ {0x03u, 0x03u},\r
+ {0x04u, 0x30u},\r
+ {0x06u, 0xC0u},\r
+ {0x07u, 0x03u},\r
+ {0x08u, 0x06u},\r
+ {0x09u, 0x04u},\r
+ {0x0Au, 0x09u},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Cu, 0x03u},\r
+ {0x0Du, 0x08u},\r
+ {0x0Eu, 0x0Cu},\r
+ {0x0Fu, 0x04u},\r
+ {0x10u, 0xFFu},\r
+ {0x11u, 0x01u},\r
+ {0x13u, 0x02u},\r
+ {0x14u, 0x50u},\r
+ {0x15u, 0x03u},\r
+ {0x16u, 0xA0u},\r
+ {0x19u, 0x03u},\r
+ {0x1Au, 0xFFu},\r
+ {0x1Cu, 0x60u},\r
+ {0x1Du, 0x20u},\r
+ {0x1Eu, 0x90u},\r
+ {0x1Fu, 0x10u},\r
+ {0x20u, 0x05u},\r
+ {0x22u, 0x0Au},\r
+ {0x23u, 0x03u},\r
+ {0x25u, 0x10u},\r
+ {0x26u, 0xFFu},\r
+ {0x27u, 0x20u},\r
+ {0x29u, 0x01u},\r
+ {0x2Bu, 0x02u},\r
+ {0x2Cu, 0x0Fu},\r
+ {0x2Du, 0x0Cu},\r
+ {0x2Eu, 0xF0u},\r
+ {0x2Fu, 0x30u},\r
+ {0x30u, 0xFFu},\r
+ {0x35u, 0x3Cu},\r
+ {0x37u, 0x03u},\r
+ {0x3Bu, 0x80u},\r
{0x3Eu, 0x01u},\r
- {0x3Fu, 0x40u},\r
+ {0x3Fu, 0x10u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x91u},\r
+ {0x5Cu, 0x10u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x84u, 0x04u},\r
- {0x86u, 0x02u},\r
- {0x8Du, 0x02u},\r
- {0x8Fu, 0x04u},\r
- {0x90u, 0x04u},\r
- {0x92u, 0x03u},\r
- {0x94u, 0x04u},\r
- {0x96u, 0x02u},\r
- {0x97u, 0x02u},\r
- {0x98u, 0x02u},\r
- {0x9Au, 0x04u},\r
- {0x9Cu, 0x04u},\r
- {0x9Eu, 0x02u},\r
- {0x9Fu, 0x04u},\r
- {0xAFu, 0x01u},\r
- {0xB2u, 0x01u},\r
- {0xB4u, 0x06u},\r
+ {0x80u, 0x03u},\r
+ {0x82u, 0x0Cu},\r
+ {0x84u, 0x30u},\r
+ {0x85u, 0x01u},\r
+ {0x86u, 0xC0u},\r
+ {0x88u, 0x09u},\r
+ {0x8Au, 0x06u},\r
+ {0x8Fu, 0x02u},\r
+ {0x90u, 0xFFu},\r
+ {0x91u, 0x02u},\r
+ {0x93u, 0x04u},\r
+ {0x96u, 0xFFu},\r
+ {0x9Cu, 0x05u},\r
+ {0x9Eu, 0x0Au},\r
+ {0xA0u, 0x90u},\r
+ {0xA2u, 0x60u},\r
+ {0xA4u, 0xFFu},\r
+ {0xA8u, 0x50u},\r
+ {0xAAu, 0xA0u},\r
+ {0xABu, 0x04u},\r
+ {0xACu, 0x0Fu},\r
+ {0xAEu, 0xF0u},\r
+ {0xB2u, 0xFFu},\r
+ {0xB3u, 0x06u},\r
{0xB5u, 0x01u},\r
- {0xB7u, 0x06u},\r
- {0xBAu, 0x20u},\r
- {0xBFu, 0x40u},\r
+ {0xBEu, 0x04u},\r
+ {0xBFu, 0x04u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
+ {0xDCu, 0x90u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x01u, 0x08u},\r
- {0x05u, 0x06u},\r
- {0x08u, 0x02u},\r
- {0x0Au, 0x26u},\r
- {0x0Cu, 0x02u},\r
- {0x0Eu, 0x29u},\r
- {0x14u, 0x08u},\r
- {0x17u, 0x01u},\r
- {0x1Au, 0x24u},\r
- {0x1Cu, 0x08u},\r
- {0x1Du, 0x05u},\r
- {0x1Eu, 0x09u},\r
- {0x20u, 0x02u},\r
- {0x21u, 0x50u},\r
- {0x23u, 0x03u},\r
- {0x24u, 0x02u},\r
- {0x26u, 0x08u},\r
- {0x27u, 0x80u},\r
- {0x2Au, 0x40u},\r
- {0x2Cu, 0x02u},\r
- {0x2Fu, 0x10u},\r
- {0x31u, 0x48u},\r
- {0x36u, 0x14u},\r
- {0x37u, 0x44u},\r
- {0x39u, 0x40u},\r
+ {0x00u, 0x12u},\r
+ {0x02u, 0x10u},\r
+ {0x04u, 0x10u},\r
+ {0x05u, 0x40u},\r
+ {0x06u, 0x10u},\r
+ {0x09u, 0x02u},\r
+ {0x0Au, 0x22u},\r
+ {0x0Cu, 0x84u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Fu, 0x08u},\r
+ {0x10u, 0x86u},\r
+ {0x13u, 0x08u},\r
+ {0x14u, 0x01u},\r
+ {0x15u, 0x02u},\r
+ {0x17u, 0x08u},\r
+ {0x1Bu, 0x08u},\r
+ {0x1Du, 0x01u},\r
+ {0x20u, 0x20u},\r
+ {0x21u, 0x10u},\r
+ {0x27u, 0x0Au},\r
+ {0x29u, 0x20u},\r
+ {0x2Cu, 0x03u},\r
+ {0x2Du, 0x02u},\r
+ {0x2Eu, 0x20u},\r
+ {0x2Fu, 0x20u},\r
+ {0x30u, 0x02u},\r
+ {0x35u, 0x08u},\r
+ {0x36u, 0x40u},\r
+ {0x37u, 0x22u},\r
+ {0x38u, 0x44u},\r
+ {0x39u, 0x08u},\r
{0x3Cu, 0x40u},\r
- {0x3Eu, 0x04u},\r
- {0x58u, 0x14u},\r
+ {0x3Du, 0x19u},\r
+ {0x58u, 0x20u},\r
{0x5Au, 0x40u},\r
{0x5Du, 0x80u},\r
- {0x5Fu, 0x10u},\r
- {0x62u, 0xA4u},\r
- {0x64u, 0x0Au},\r
- {0x69u, 0x40u},\r
- {0x6Cu, 0x28u},\r
- {0x6Du, 0x04u},\r
- {0x6Fu, 0x12u},\r
- {0x81u, 0x01u},\r
- {0x82u, 0x04u},\r
- {0x84u, 0x10u},\r
- {0x87u, 0x02u},\r
- {0x88u, 0x0Au},\r
- {0x8Bu, 0x10u},\r
+ {0x61u, 0x10u},\r
+ {0x62u, 0xE0u},\r
+ {0x67u, 0x02u},\r
+ {0x78u, 0x08u},\r
+ {0x7Bu, 0x20u},\r
+ {0x82u, 0x20u},\r
+ {0x83u, 0x01u},\r
+ {0x86u, 0x40u},\r
+ {0x88u, 0x30u},\r
+ {0x89u, 0x20u},\r
+ {0x8Au, 0x40u},\r
+ {0x91u, 0x1Au},\r
{0x92u, 0x02u},\r
- {0x93u, 0x12u},\r
- {0x95u, 0x90u},\r
- {0x96u, 0x20u},\r
- {0x97u, 0x21u},\r
- {0x99u, 0x38u},\r
- {0x9Au, 0x40u},\r
- {0x9Bu, 0x40u},\r
+ {0x95u, 0x21u},\r
+ {0x97u, 0x82u},\r
+ {0x9Au, 0x2Cu},\r
+ {0x9Cu, 0x09u},\r
{0x9Du, 0x02u},\r
- {0x9Eu, 0x04u},\r
- {0x9Fu, 0x0Cu},\r
- {0xA3u, 0x08u},\r
- {0xA4u, 0x20u},\r
- {0xA5u, 0x04u},\r
- {0xA6u, 0xA9u},\r
- {0xA8u, 0x40u},\r
- {0xAAu, 0x08u},\r
- {0xABu, 0x08u},\r
- {0xACu, 0x04u},\r
- {0xADu, 0x08u},\r
- {0xB1u, 0x20u},\r
- {0xB4u, 0x40u},\r
- {0xB5u, 0x01u},\r
- {0xB6u, 0x08u},\r
- {0xC0u, 0x34u},\r
- {0xC2u, 0xFFu},\r
- {0xC4u, 0x50u},\r
- {0xCAu, 0x58u},\r
- {0xCCu, 0x7Au},\r
- {0xCEu, 0x58u},\r
- {0xD6u, 0x3Eu},\r
- {0xD8u, 0x3Eu},\r
- {0xE0u, 0x24u},\r
- {0xE4u, 0x80u},\r
- {0xE6u, 0x22u},\r
- {0xE8u, 0x32u},\r
- {0xECu, 0x02u},\r
- {0xEEu, 0x14u},\r
- {0x02u, 0x6Fu},\r
- {0x04u, 0x04u},\r
- {0x06u, 0x08u},\r
- {0x08u, 0x6Fu},\r
- {0x0Cu, 0x20u},\r
- {0x0Eu, 0x40u},\r
- {0x12u, 0x6Fu},\r
- {0x16u, 0x10u},\r
- {0x1Au, 0x6Fu},\r
- {0x1Cu, 0x6Fu},\r
- {0x20u, 0x01u},\r
- {0x22u, 0x02u},\r
- {0x24u, 0x04u},\r
+ {0x9Eu, 0x10u},\r
+ {0x9Fu, 0x22u},\r
+ {0xA0u, 0x20u},\r
+ {0xA1u, 0x10u},\r
+ {0xA4u, 0x01u},\r
+ {0xA5u, 0x20u},\r
+ {0xA6u, 0x88u},\r
+ {0xA7u, 0x40u},\r
+ {0xAAu, 0x10u},\r
+ {0xABu, 0x10u},\r
+ {0xADu, 0xA0u},\r
+ {0xAFu, 0x09u},\r
+ {0xB3u, 0x42u},\r
+ {0xB7u, 0x08u},\r
+ {0xC0u, 0xEEu},\r
+ {0xC2u, 0xFDu},\r
+ {0xC4u, 0xBFu},\r
+ {0xCAu, 0xF4u},\r
+ {0xCCu, 0xF1u},\r
+ {0xCEu, 0xFAu},\r
+ {0xD6u, 0x1Cu},\r
+ {0xD8u, 0x1Cu},\r
+ {0xE0u, 0x20u},\r
+ {0xE6u, 0x4Au},\r
+ {0xEAu, 0x21u},\r
+ {0xECu, 0x08u},\r
+ {0xEEu, 0x80u},\r
+ {0x01u, 0x02u},\r
+ {0x02u, 0x04u},\r
+ {0x03u, 0x01u},\r
+ {0x05u, 0x01u},\r
+ {0x07u, 0x02u},\r
+ {0x09u, 0x02u},\r
+ {0x0Bu, 0x01u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Fu, 0x01u},\r
+ {0x10u, 0x04u},\r
+ {0x12u, 0x08u},\r
+ {0x13u, 0x1Cu},\r
+ {0x15u, 0x24u},\r
+ {0x17u, 0x08u},\r
+ {0x1Au, 0x02u},\r
+ {0x1Bu, 0x20u},\r
+ {0x1Du, 0x28u},\r
+ {0x1Eu, 0x01u},\r
+ {0x1Fu, 0x14u},\r
+ {0x21u, 0x10u},\r
+ {0x22u, 0x10u},\r
+ {0x23u, 0x20u},\r
{0x26u, 0x08u},\r
- {0x27u, 0x01u},\r
- {0x28u, 0x20u},\r
- {0x2Au, 0x40u},\r
- {0x2Cu, 0x01u},\r
- {0x2Eu, 0x02u},\r
- {0x30u, 0x03u},\r
- {0x31u, 0x01u},\r
- {0x32u, 0x10u},\r
- {0x34u, 0x0Cu},\r
- {0x36u, 0x60u},\r
- {0x3Au, 0xA2u},\r
+ {0x29u, 0x02u},\r
+ {0x2Bu, 0x01u},\r
+ {0x30u, 0x0Cu},\r
+ {0x31u, 0x3Cu},\r
+ {0x32u, 0x02u},\r
+ {0x33u, 0x03u},\r
+ {0x34u, 0x01u},\r
+ {0x36u, 0x10u},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Eu, 0x01u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x06u},\r
- {0x81u, 0xC0u},\r
- {0x82u, 0xF8u},\r
- {0x84u, 0xC6u},\r
- {0x85u, 0x10u},\r
- {0x86u, 0x19u},\r
- {0x87u, 0xE0u},\r
- {0x88u, 0x40u},\r
- {0x8Au, 0x80u},\r
- {0x8Fu, 0x20u},\r
- {0x91u, 0x24u},\r
- {0x92u, 0x09u},\r
- {0x93u, 0xC8u},\r
- {0x94u, 0x14u},\r
- {0x97u, 0xC0u},\r
- {0x98u, 0x01u},\r
- {0x99u, 0x40u},\r
- {0x9Bu, 0x80u},\r
- {0x9Cu, 0xE0u},\r
- {0x9Fu, 0x1Du},\r
- {0xA0u, 0x40u},\r
- {0xA1u, 0x01u},\r
- {0xA2u, 0x80u},\r
- {0xA3u, 0x02u},\r
- {0xA6u, 0xFFu},\r
- {0xA7u, 0x02u},\r
- {0xA8u, 0x09u},\r
- {0xA9u, 0xE8u},\r
- {0xAAu, 0xF2u},\r
- {0xABu, 0x14u},\r
- {0xADu, 0x40u},\r
- {0xAFu, 0x80u},\r
- {0xB1u, 0x3Cu},\r
- {0xB2u, 0x3Fu},\r
- {0xB3u, 0x03u},\r
- {0xB4u, 0xC0u},\r
- {0xB5u, 0xC0u},\r
- {0xBAu, 0x20u},\r
- {0xBBu, 0x20u},\r
- {0xBFu, 0x04u},\r
+ {0x81u, 0x96u},\r
+ {0x83u, 0x69u},\r
+ {0x85u, 0x0Fu},\r
+ {0x87u, 0xF0u},\r
+ {0x8Fu, 0xFFu},\r
+ {0x90u, 0x10u},\r
+ {0x92u, 0x20u},\r
+ {0x96u, 0x20u},\r
+ {0x97u, 0xFFu},\r
+ {0x99u, 0xFFu},\r
+ {0x9Au, 0x1Du},\r
+ {0x9Cu, 0x28u},\r
+ {0x9Du, 0x33u},\r
+ {0x9Eu, 0x14u},\r
+ {0x9Fu, 0xCCu},\r
+ {0xA0u, 0x24u},\r
+ {0xA2u, 0x08u},\r
+ {0xA3u, 0xFFu},\r
+ {0xA9u, 0xFFu},\r
+ {0xAAu, 0x02u},\r
+ {0xACu, 0x01u},\r
+ {0xADu, 0x55u},\r
+ {0xAEu, 0x02u},\r
+ {0xAFu, 0xAAu},\r
+ {0xB0u, 0x03u},\r
+ {0xB3u, 0xFFu},\r
+ {0xB4u, 0x3Cu},\r
+ {0xBBu, 0x08u},\r
+ {0xBEu, 0x01u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDCu, 0x11u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x06u},\r
- {0x01u, 0x80u},\r
- {0x03u, 0x08u},\r
- {0x05u, 0x05u},\r
- {0x07u, 0x08u},\r
- {0x08u, 0x10u},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0x20u},\r
- {0x0Bu, 0x01u},\r
- {0x0Cu, 0x24u},\r
- {0x0Du, 0x40u},\r
- {0x0Eu, 0x40u},\r
- {0x11u, 0x40u},\r
- {0x12u, 0xA4u},\r
- {0x14u, 0x10u},\r
- {0x15u, 0x02u},\r
- {0x16u, 0x08u},\r
- {0x17u, 0x04u},\r
- {0x18u, 0x86u},\r
- {0x19u, 0x88u},\r
- {0x1Bu, 0x10u},\r
- {0x1Cu, 0x08u},\r
- {0x1Du, 0x04u},\r
- {0x1Fu, 0x08u},\r
+ {0x00u, 0x02u},\r
+ {0x08u, 0x01u},\r
+ {0x0Au, 0x05u},\r
+ {0x0Du, 0x88u},\r
+ {0x0Eu, 0x08u},\r
+ {0x0Fu, 0x80u},\r
+ {0x12u, 0x50u},\r
+ {0x14u, 0x09u},\r
+ {0x15u, 0x01u},\r
+ {0x18u, 0x22u},\r
+ {0x19u, 0x20u},\r
+ {0x1Au, 0x05u},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Du, 0x01u},\r
+ {0x1Eu, 0x08u},\r
+ {0x21u, 0x05u},\r
{0x22u, 0x01u},\r
- {0x25u, 0x08u},\r
- {0x26u, 0x10u},\r
- {0x27u, 0x40u},\r
- {0x29u, 0x08u},\r
+ {0x25u, 0x04u},\r
+ {0x27u, 0x10u},\r
+ {0x29u, 0x20u},\r
+ {0x2Bu, 0x40u},\r
{0x2Du, 0x02u},\r
- {0x2Eu, 0x80u},\r
- {0x2Fu, 0x18u},\r
- {0x35u, 0x01u},\r
- {0x36u, 0x11u},\r
- {0x37u, 0x44u},\r
- {0x38u, 0x80u},\r
- {0x39u, 0x40u},\r
- {0x3Eu, 0x08u},\r
- {0x3Fu, 0x41u},\r
- {0x48u, 0x01u},\r
- {0x4Au, 0x01u},\r
- {0x58u, 0x40u},\r
- {0x5Cu, 0x40u},\r
- {0x5Du, 0x10u},\r
+ {0x2Fu, 0x09u},\r
+ {0x31u, 0x80u},\r
+ {0x32u, 0x09u},\r
+ {0x33u, 0x20u},\r
+ {0x36u, 0x88u},\r
+ {0x37u, 0x20u},\r
+ {0x38u, 0x22u},\r
+ {0x39u, 0x08u},\r
+ {0x3Au, 0x40u},\r
+ {0x3Du, 0x08u},\r
+ {0x3Fu, 0x81u},\r
+ {0x59u, 0x40u},\r
+ {0x5Du, 0x80u},\r
+ {0x5Eu, 0x10u},\r
+ {0x5Fu, 0x08u},\r
{0x62u, 0x40u},\r
- {0x65u, 0x10u},\r
- {0x66u, 0x90u},\r
- {0x80u, 0x01u},\r
- {0x81u, 0x04u},\r
- {0x83u, 0x10u},\r
- {0x84u, 0x04u},\r
+ {0x66u, 0x24u},\r
+ {0x67u, 0x21u},\r
+ {0x79u, 0x10u},\r
+ {0x7Au, 0x04u},\r
+ {0x81u, 0x90u},\r
+ {0x82u, 0x08u},\r
+ {0x85u, 0x50u},\r
+ {0x86u, 0x20u},\r
+ {0x87u, 0x10u},\r
+ {0x88u, 0x20u},\r
+ {0x8Du, 0x09u},\r
+ {0x8Fu, 0x20u},\r
+ {0xC0u, 0x08u},\r
+ {0xC2u, 0xFBu},\r
+ {0xC4u, 0xDCu},\r
+ {0xCAu, 0xB5u},\r
+ {0xCCu, 0x7Fu},\r
+ {0xCEu, 0xDFu},\r
+ {0xD6u, 0x78u},\r
+ {0xD8u, 0x78u},\r
+ {0xE0u, 0x40u},\r
+ {0xE2u, 0x04u},\r
+ {0xE4u, 0x30u},\r
{0x85u, 0x01u},\r
- {0x86u, 0x90u},\r
- {0x88u, 0x40u},\r
- {0x8Au, 0x10u},\r
- {0x8Bu, 0x50u},\r
- {0x8Eu, 0x40u},\r
- {0x8Fu, 0x01u},\r
- {0xC0u, 0x7Fu},\r
- {0xC2u, 0xFFu},\r
- {0xC4u, 0x7Fu},\r
- {0xCAu, 0xF2u},\r
- {0xCCu, 0xF0u},\r
- {0xCEu, 0xD0u},\r
- {0xD6u, 0x38u},\r
- {0xD8u, 0x38u},\r
- {0xE0u, 0x60u},\r
- {0xE4u, 0xC0u},\r
- {0xE6u, 0x20u},\r
- {0x8Eu, 0x38u},\r
- {0x90u, 0x3Eu},\r
- {0x94u, 0x01u},\r
- {0x96u, 0x14u},\r
- {0xA0u, 0x09u},\r
- {0xA2u, 0x02u},\r
- {0xA4u, 0x22u},\r
- {0xA6u, 0x01u},\r
- {0xB0u, 0x07u},\r
- {0xB6u, 0x38u},\r
- {0xB8u, 0x02u},\r
- {0xBEu, 0x40u},\r
- {0xD8u, 0x04u},\r
+ {0x87u, 0x1Au},\r
+ {0x91u, 0x32u},\r
+ {0x93u, 0x01u},\r
+ {0x99u, 0x06u},\r
+ {0x9Fu, 0x08u},\r
+ {0xA5u, 0x01u},\r
+ {0xA7u, 0x2Cu},\r
+ {0xB5u, 0x07u},\r
+ {0xB7u, 0x38u},\r
+ {0xB9u, 0x20u},\r
+ {0xD4u, 0x01u},\r
+ {0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDDu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x40u},\r
- {0x01u, 0x05u},\r
- {0x02u, 0x08u},\r
- {0x07u, 0x01u},\r
- {0x0Au, 0x19u},\r
- {0x0Eu, 0x90u},\r
- {0x10u, 0x08u},\r
- {0x12u, 0x01u},\r
- {0x13u, 0x06u},\r
- {0x15u, 0x0Au},\r
- {0x1Au, 0x98u},\r
- {0x1Bu, 0x01u},\r
- {0x1Cu, 0x02u},\r
- {0x1Eu, 0x80u},\r
- {0x20u, 0xC0u},\r
- {0x21u, 0x15u},\r
- {0x22u, 0x0Au},\r
- {0x23u, 0x04u},\r
- {0x2Au, 0x02u},\r
- {0x2Bu, 0x01u},\r
- {0x30u, 0x22u},\r
- {0x32u, 0x08u},\r
- {0x33u, 0x40u},\r
- {0x38u, 0x40u},\r
- {0x39u, 0x10u},\r
- {0x3Au, 0x01u},\r
- {0x3Bu, 0x04u},\r
- {0x42u, 0x58u},\r
- {0x49u, 0x08u},\r
- {0x4Au, 0x8Au},\r
- {0x51u, 0x40u},\r
+ {0x01u, 0x41u},\r
+ {0x03u, 0x24u},\r
+ {0x09u, 0x06u},\r
+ {0x0Bu, 0x04u},\r
+ {0x11u, 0x10u},\r
+ {0x12u, 0x12u},\r
+ {0x13u, 0x01u},\r
+ {0x19u, 0x09u},\r
+ {0x1Au, 0x40u},\r
+ {0x21u, 0x04u},\r
+ {0x26u, 0xA0u},\r
+ {0x28u, 0x01u},\r
+ {0x2Au, 0x12u},\r
+ {0x2Bu, 0x20u},\r
+ {0x2Fu, 0x20u},\r
+ {0x32u, 0x12u},\r
+ {0x33u, 0x04u},\r
+ {0x36u, 0xA2u},\r
+ {0x37u, 0x10u},\r
+ {0x38u, 0x20u},\r
+ {0x39u, 0x45u},\r
+ {0x3Du, 0x08u},\r
+ {0x41u, 0x08u},\r
+ {0x42u, 0x41u},\r
+ {0x43u, 0x20u},\r
+ {0x49u, 0x06u},\r
+ {0x4Au, 0x02u},\r
{0x52u, 0x51u},\r
- {0x53u, 0x81u},\r
- {0x60u, 0x04u},\r
- {0x68u, 0x2Au},\r
- {0x69u, 0x15u},\r
- {0x6Au, 0x22u},\r
- {0x6Bu, 0x42u},\r
- {0x72u, 0x03u},\r
+ {0x53u, 0x01u},\r
+ {0x5Du, 0x80u},\r
+ {0x63u, 0x40u},\r
+ {0x68u, 0x20u},\r
+ {0x69u, 0x55u},\r
+ {0x6Au, 0xA4u},\r
+ {0x70u, 0x40u},\r
+ {0x72u, 0x02u},\r
{0x73u, 0x01u},\r
- {0x82u, 0x08u},\r
- {0x84u, 0x01u},\r
- {0x86u, 0x04u},\r
- {0x88u, 0x40u},\r
- {0x8Du, 0x10u},\r
- {0x8Fu, 0x01u},\r
- {0x90u, 0x04u},\r
- {0x92u, 0x44u},\r
- {0x94u, 0x40u},\r
- {0x95u, 0xAFu},\r
- {0x96u, 0xA3u},\r
- {0x97u, 0x05u},\r
- {0x9Bu, 0x01u},\r
- {0x9Cu, 0x40u},\r
- {0x9Du, 0x18u},\r
- {0x9Eu, 0x52u},\r
- {0xA4u, 0x42u},\r
- {0xA6u, 0x88u},\r
- {0xA7u, 0x81u},\r
- {0xA9u, 0x80u},\r
- {0xC0u, 0x8Fu},\r
- {0xC2u, 0x37u},\r
- {0xC4u, 0x3Fu},\r
- {0xCAu, 0x09u},\r
- {0xCCu, 0x0Fu},\r
- {0xCEu, 0x0Fu},\r
- {0xD0u, 0x07u},\r
- {0xD2u, 0x0Cu},\r
- {0xD8u, 0x04u},\r
- {0xEAu, 0x04u},\r
- {0xEEu, 0x02u},\r
- {0x01u, 0x34u},\r
- {0x03u, 0x43u},\r
- {0x04u, 0x02u},\r
- {0x05u, 0x40u},\r
- {0x06u, 0x01u},\r
- {0x07u, 0x30u},\r
- {0x0Cu, 0x02u},\r
- {0x0Du, 0x11u},\r
- {0x0Eu, 0x01u},\r
- {0x0Fu, 0x62u},\r
- {0x13u, 0x0Cu},\r
- {0x14u, 0x02u},\r
- {0x15u, 0x58u},\r
- {0x16u, 0x05u},\r
- {0x17u, 0x23u},\r
- {0x18u, 0x01u},\r
- {0x1Au, 0x02u},\r
- {0x23u, 0x02u},\r
- {0x2Bu, 0x01u},\r
- {0x2Cu, 0x02u},\r
- {0x2Eu, 0x09u},\r
- {0x32u, 0x04u},\r
- {0x34u, 0x03u},\r
- {0x35u, 0x70u},\r
- {0x36u, 0x08u},\r
- {0x37u, 0x0Fu},\r
- {0x3Au, 0x20u},\r
- {0x3Bu, 0x20u},\r
- {0x56u, 0x08u},\r
+ {0x85u, 0x02u},\r
+ {0x86u, 0x05u},\r
+ {0x88u, 0x10u},\r
+ {0x8Au, 0xC0u},\r
+ {0x90u, 0x20u},\r
+ {0x93u, 0x44u},\r
+ {0x94u, 0x80u},\r
+ {0x95u, 0x59u},\r
+ {0x96u, 0x80u},\r
+ {0x97u, 0x03u},\r
+ {0x98u, 0x01u},\r
+ {0x99u, 0x80u},\r
+ {0x9Bu, 0x04u},\r
+ {0x9Cu, 0x10u},\r
+ {0x9Du, 0x0Fu},\r
+ {0x9Eu, 0x11u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA1u, 0x0Cu},\r
+ {0xA2u, 0x02u},\r
+ {0xA3u, 0x20u},\r
+ {0xA4u, 0x20u},\r
+ {0xACu, 0x20u},\r
+ {0xADu, 0x40u},\r
+ {0xB4u, 0x10u},\r
+ {0xC0u, 0x0Fu},\r
+ {0xC2u, 0x0Eu},\r
+ {0xC4u, 0x0Fu},\r
+ {0xCAu, 0x4Fu},\r
+ {0xCCu, 0xB7u},\r
+ {0xCEu, 0x4Fu},\r
+ {0xD0u, 0x0Fu},\r
+ {0xD2u, 0x08u},\r
+ {0xD6u, 0x10u},\r
+ {0xD8u, 0x01u},\r
+ {0xE2u, 0x80u},\r
+ {0x01u, 0x6Cu},\r
+ {0x04u, 0x92u},\r
+ {0x05u, 0x71u},\r
+ {0x06u, 0x64u},\r
+ {0x07u, 0x82u},\r
+ {0x08u, 0x71u},\r
+ {0x0Au, 0x82u},\r
+ {0x0Cu, 0x40u},\r
+ {0x0Du, 0x2Cu},\r
+ {0x0Fu, 0x40u},\r
+ {0x10u, 0x12u},\r
+ {0x11u, 0xC0u},\r
+ {0x12u, 0xE8u},\r
+ {0x13u, 0x2Fu},\r
+ {0x14u, 0x02u},\r
+ {0x15u, 0xA4u},\r
+ {0x16u, 0x0Du},\r
+ {0x17u, 0x40u},\r
+ {0x18u, 0x2Du},\r
+ {0x19u, 0x91u},\r
+ {0x1Au, 0x40u},\r
+ {0x1Bu, 0x4Eu},\r
+ {0x1Cu, 0x6Du},\r
+ {0x20u, 0x6Du},\r
+ {0x21u, 0x6Cu},\r
+ {0x24u, 0x20u},\r
+ {0x25u, 0x64u},\r
+ {0x27u, 0x08u},\r
+ {0x28u, 0x0Du},\r
+ {0x29u, 0x40u},\r
+ {0x2Au, 0x60u},\r
+ {0x2Bu, 0x2Cu},\r
+ {0x2Cu, 0x6Du},\r
+ {0x2Du, 0x08u},\r
+ {0x2Fu, 0x10u},\r
+ {0x31u, 0x31u},\r
+ {0x32u, 0x0Fu},\r
+ {0x33u, 0x0Fu},\r
+ {0x34u, 0xF0u},\r
+ {0x35u, 0xC0u},\r
+ {0x38u, 0x20u},\r
+ {0x3Au, 0x08u},\r
+ {0x3Bu, 0x23u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Cu, 0x01u},\r
- {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0xC0u},\r
- {0x82u, 0x01u},\r
- {0x83u, 0x02u},\r
- {0x85u, 0xC0u},\r
- {0x86u, 0x04u},\r
- {0x87u, 0x04u},\r
- {0x89u, 0x80u},\r
- {0x8Cu, 0x02u},\r
- {0x8Du, 0x1Fu},\r
- {0x8Eu, 0x04u},\r
- {0x8Fu, 0x20u},\r
- {0x91u, 0x90u},\r
- {0x92u, 0x10u},\r
- {0x93u, 0x40u},\r
- {0x94u, 0x09u},\r
- {0x95u, 0x7Fu},\r
- {0x97u, 0x80u},\r
- {0x99u, 0xC0u},\r
- {0x9Bu, 0x08u},\r
- {0x9Cu, 0x09u},\r
- {0x9Fu, 0xFFu},\r
- {0xA0u, 0x09u},\r
- {0xA1u, 0xC0u},\r
- {0xA3u, 0x01u},\r
- {0xA4u, 0x09u},\r
- {0xAAu, 0x02u},\r
- {0xABu, 0x60u},\r
- {0xAEu, 0x09u},\r
- {0xAFu, 0x9Fu},\r
- {0xB0u, 0x08u},\r
- {0xB2u, 0x01u},\r
- {0xB3u, 0xFFu},\r
- {0xB4u, 0x10u},\r
- {0xB6u, 0x06u},\r
- {0xBEu, 0x45u},\r
- {0xBFu, 0x04u},\r
- {0xD4u, 0x40u},\r
- {0xD6u, 0x04u},\r
+ {0x81u, 0x04u},\r
+ {0x84u, 0x0Au},\r
+ {0x85u, 0x01u},\r
+ {0x86u, 0x05u},\r
+ {0x89u, 0x04u},\r
+ {0x8Au, 0x07u},\r
+ {0x8Du, 0x04u},\r
+ {0x90u, 0x09u},\r
+ {0x91u, 0x02u},\r
+ {0x92u, 0x02u},\r
+ {0x93u, 0x08u},\r
+ {0x95u, 0x02u},\r
+ {0x97u, 0x08u},\r
+ {0x99u, 0x04u},\r
+ {0x9Au, 0x10u},\r
+ {0x9Fu, 0x04u},\r
+ {0xA0u, 0x04u},\r
+ {0xA2u, 0x08u},\r
+ {0xA3u, 0x04u},\r
+ {0xA5u, 0x01u},\r
+ {0xA9u, 0x0Au},\r
+ {0xAAu, 0x08u},\r
+ {0xB0u, 0x10u},\r
+ {0xB1u, 0x08u},\r
+ {0xB3u, 0x04u},\r
+ {0xB4u, 0x0Fu},\r
+ {0xB5u, 0x01u},\r
+ {0xB7u, 0x02u},\r
+ {0xB9u, 0x20u},\r
+ {0xBFu, 0x45u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
{0xDCu, 0x01u},\r
{0xDFu, 0x01u},\r
{0x00u, 0x08u},\r
- {0x01u, 0x40u},\r
- {0x02u, 0x80u},\r
- {0x05u, 0x44u},\r
- {0x0Au, 0x22u},\r
+ {0x01u, 0x20u},\r
+ {0x04u, 0x24u},\r
+ {0x05u, 0x40u},\r
+ {0x06u, 0x01u},\r
+ {0x0Au, 0x08u},\r
{0x0Bu, 0x80u},\r
- {0x0Eu, 0x08u},\r
- {0x0Fu, 0x20u},\r
- {0x10u, 0x06u},\r
- {0x11u, 0x04u},\r
- {0x13u, 0x01u},\r
- {0x14u, 0x02u},\r
- {0x18u, 0x10u},\r
- {0x19u, 0x01u},\r
- {0x1Au, 0x40u},\r
- {0x1Bu, 0x50u},\r
- {0x1Du, 0x44u},\r
- {0x1Eu, 0x08u},\r
- {0x1Fu, 0x40u},\r
- {0x20u, 0x20u},\r
- {0x24u, 0x04u},\r
- {0x27u, 0x01u},\r
- {0x2Au, 0x42u},\r
- {0x2Bu, 0x04u},\r
- {0x2Fu, 0x88u},\r
- {0x30u, 0x02u},\r
- {0x32u, 0x58u},\r
- {0x36u, 0x08u},\r
- {0x37u, 0x01u},\r
- {0x38u, 0x40u},\r
- {0x39u, 0x25u},\r
- {0x3Cu, 0x84u},\r
- {0x3Fu, 0x02u},\r
- {0x5Du, 0x80u},\r
- {0x60u, 0x10u},\r
- {0x62u, 0x92u},\r
- {0x64u, 0x02u},\r
- {0x82u, 0x06u},\r
- {0x8Fu, 0x40u},\r
- {0x91u, 0x40u},\r
- {0x92u, 0x04u},\r
- {0x95u, 0x8Fu},\r
- {0x96u, 0x81u},\r
- {0x97u, 0x04u},\r
- {0x98u, 0x04u},\r
- {0x9Cu, 0x40u},\r
- {0x9Du, 0x19u},\r
- {0x9Eu, 0x40u},\r
- {0xA0u, 0x04u},\r
- {0xA3u, 0x0Cu},\r
- {0xA4u, 0x52u},\r
- {0xA6u, 0x08u},\r
- {0xA7u, 0x01u},\r
- {0xAAu, 0x80u},\r
- {0xB1u, 0x80u},\r
- {0xB4u, 0x08u},\r
- {0xB6u, 0x28u},\r
- {0xC0u, 0xADu},\r
- {0xC2u, 0x6Du},\r
- {0xC4u, 0x8Fu},\r
- {0xCAu, 0xADu},\r
- {0xCCu, 0xCFu},\r
+ {0x0Cu, 0x20u},\r
+ {0x0Du, 0x02u},\r
+ {0x0Eu, 0x20u},\r
+ {0x0Fu, 0x01u},\r
+ {0x10u, 0x88u},\r
+ {0x15u, 0x51u},\r
+ {0x17u, 0x04u},\r
+ {0x19u, 0x20u},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Cu, 0x04u},\r
+ {0x1Du, 0x10u},\r
+ {0x1Eu, 0x20u},\r
+ {0x1Fu, 0x20u},\r
+ {0x20u, 0x10u},\r
+ {0x21u, 0x01u},\r
+ {0x22u, 0x80u},\r
+ {0x23u, 0x04u},\r
+ {0x24u, 0x20u},\r
+ {0x25u, 0x0Eu},\r
+ {0x26u, 0x0Au},\r
+ {0x27u, 0x04u},\r
+ {0x29u, 0x1Au},\r
+ {0x2Au, 0x22u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Du, 0x11u},\r
+ {0x2Fu, 0x01u},\r
+ {0x30u, 0x20u},\r
+ {0x31u, 0x08u},\r
+ {0x32u, 0x42u},\r
+ {0x35u, 0x10u},\r
+ {0x36u, 0x02u},\r
+ {0x37u, 0x04u},\r
+ {0x38u, 0x80u},\r
+ {0x39u, 0x19u},\r
+ {0x3Du, 0x48u},\r
+ {0x3Fu, 0x01u},\r
+ {0x40u, 0x80u},\r
+ {0x41u, 0x01u},\r
+ {0x84u, 0x01u},\r
+ {0x87u, 0x04u},\r
+ {0x8Eu, 0x02u},\r
+ {0x92u, 0x08u},\r
+ {0x93u, 0xC0u},\r
+ {0x99u, 0x80u},\r
+ {0x9Cu, 0xB0u},\r
+ {0x9Du, 0x25u},\r
+ {0x9Eu, 0x30u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA0u, 0x8Cu},\r
+ {0xA5u, 0x02u},\r
+ {0xA6u, 0x8Au},\r
+ {0xA7u, 0x02u},\r
+ {0xA8u, 0x04u},\r
+ {0xAAu, 0x04u},\r
+ {0xABu, 0x0Du},\r
+ {0xAEu, 0x40u},\r
+ {0xB0u, 0x43u},\r
+ {0xB2u, 0x04u},\r
+ {0xB5u, 0x40u},\r
+ {0xB6u, 0x40u},\r
+ {0xB7u, 0x40u},\r
+ {0xC0u, 0xE6u},\r
+ {0xC2u, 0xFAu},\r
+ {0xC4u, 0xFAu},\r
+ {0xCAu, 0xF7u},\r
+ {0xCCu, 0xEFu},\r
{0xCEu, 0xDFu},\r
- {0xD6u, 0x10u},\r
- {0xD8u, 0x1Fu},\r
+ {0xE8u, 0x04u},\r
+ {0xEAu, 0x89u},\r
+ {0xECu, 0x04u},\r
+ {0xEEu, 0x48u},\r
+ {0x82u, 0x10u},\r
+ {0x8Fu, 0x01u},\r
+ {0x92u, 0x20u},\r
+ {0x97u, 0x02u},\r
+ {0x9Eu, 0x28u},\r
+ {0xA8u, 0x90u},\r
+ {0xAAu, 0x04u},\r
+ {0xABu, 0x04u},\r
+ {0xACu, 0x02u},\r
+ {0xB0u, 0x80u},\r
+ {0xB2u, 0x14u},\r
+ {0xB4u, 0x06u},\r
+ {0xB6u, 0x41u},\r
+ {0xE0u, 0x40u},\r
{0xE4u, 0x04u},\r
- {0xEEu, 0x04u},\r
- {0xB8u, 0x08u},\r
- {0xBEu, 0x04u},\r
- {0xD8u, 0x04u},\r
- {0xDFu, 0x01u},\r
- {0x1Bu, 0x08u},\r
- {0x80u, 0x20u},\r
- {0x95u, 0x10u},\r
- {0x9Cu, 0x20u},\r
- {0xA2u, 0x01u},\r
- {0xA8u, 0x81u},\r
- {0xB0u, 0x01u},\r
- {0xB1u, 0x08u},\r
- {0xB2u, 0x40u},\r
- {0xB4u, 0x80u},\r
- {0xB6u, 0x02u},\r
- {0xB7u, 0x40u},\r
- {0xE4u, 0x40u},\r
- {0xEAu, 0x10u},\r
- {0xECu, 0xD0u},\r
- {0xEEu, 0x01u},\r
- {0x82u, 0x01u},\r
- {0x85u, 0x10u},\r
- {0x95u, 0x10u},\r
- {0xA2u, 0x01u},\r
- {0xAFu, 0x08u},\r
- {0xE2u, 0x80u},\r
- {0xE4u, 0x01u},\r
- {0xE6u, 0x08u},\r
- {0xEAu, 0x04u},\r
- {0x05u, 0x80u},\r
- {0x0Cu, 0x80u},\r
+ {0xEAu, 0x50u},\r
+ {0xECu, 0xA0u},\r
+ {0xEEu, 0x09u},\r
+ {0x8Au, 0x20u},\r
+ {0x9Eu, 0x20u},\r
+ {0xB6u, 0x08u},\r
+ {0xE2u, 0x20u},\r
+ {0xE4u, 0x80u},\r
+ {0xE8u, 0x10u},\r
+ {0x05u, 0x40u},\r
+ {0x0Eu, 0x08u},\r
{0x13u, 0x20u},\r
{0x16u, 0x80u},\r
- {0x17u, 0x80u},\r
- {0x32u, 0x02u},\r
- {0x35u, 0x01u},\r
+ {0x17u, 0x40u},\r
+ {0x30u, 0x08u},\r
{0x36u, 0x80u},\r
- {0x39u, 0x01u},\r
+ {0x37u, 0x01u},\r
{0x3Au, 0x80u},\r
- {0x3Eu, 0x40u},\r
- {0x3Fu, 0x01u},\r
- {0x41u, 0x40u},\r
- {0x66u, 0x40u},\r
- {0x77u, 0x60u},\r
- {0x88u, 0x80u},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Eu, 0x01u},\r
+ {0x3Fu, 0x20u},\r
+ {0x41u, 0x20u},\r
+ {0x5Eu, 0x04u},\r
+ {0x85u, 0x40u},\r
+ {0x87u, 0x01u},\r
{0x8Eu, 0x40u},\r
{0xC0u, 0x80u},\r
{0xC2u, 0x80u},\r
{0xCEu, 0xF0u},\r
{0xD0u, 0x10u},\r
{0xD6u, 0x80u},\r
- {0x33u, 0x42u},\r
- {0x37u, 0x84u},\r
- {0x38u, 0x10u},\r
- {0x56u, 0x20u},\r
- {0x58u, 0x10u},\r
- {0x66u, 0x80u},\r
- {0x86u, 0x40u},\r
- {0x8Au, 0x80u},\r
- {0x8Eu, 0x20u},\r
- {0x95u, 0x80u},\r
- {0x97u, 0x01u},\r
- {0x99u, 0x80u},\r
- {0x9Bu, 0xC0u},\r
- {0x9Eu, 0x40u},\r
- {0xA6u, 0x82u},\r
- {0xA9u, 0x01u},\r
- {0xADu, 0x01u},\r
+ {0xE2u, 0x40u},\r
+ {0xE4u, 0x10u},\r
+ {0x30u, 0x22u},\r
+ {0x34u, 0x08u},\r
+ {0x37u, 0x40u},\r
+ {0x3Bu, 0x40u},\r
+ {0x50u, 0x01u},\r
+ {0x5Cu, 0x02u},\r
+ {0x5Eu, 0x40u},\r
+ {0x68u, 0x20u},\r
+ {0x6Bu, 0x20u},\r
+ {0x84u, 0x08u},\r
+ {0x87u, 0x40u},\r
+ {0x88u, 0x08u},\r
+ {0x92u, 0x40u},\r
+ {0x96u, 0x04u},\r
+ {0x9Bu, 0x60u},\r
+ {0xA2u, 0x04u},\r
+ {0xA4u, 0x08u},\r
+ {0xA5u, 0x20u},\r
+ {0xA6u, 0x80u},\r
+ {0xB2u, 0x01u},\r
+ {0xB3u, 0x04u},\r
+ {0xB7u, 0x10u},\r
{0xCCu, 0xF0u},\r
{0xCEu, 0x10u},\r
- {0xD4u, 0xC0u},\r
- {0xD6u, 0x80u},\r
- {0xE2u, 0x10u},\r
- {0xEAu, 0x30u},\r
+ {0xD4u, 0x80u},\r
+ {0xD6u, 0xA0u},\r
+ {0xE6u, 0x50u},\r
{0x12u, 0x80u},\r
- {0x32u, 0x10u},\r
- {0x82u, 0x10u},\r
- {0x94u, 0x10u},\r
- {0x95u, 0x80u},\r
- {0x97u, 0x01u},\r
- {0x9Fu, 0x04u},\r
+ {0x33u, 0x80u},\r
+ {0x80u, 0x02u},\r
+ {0x86u, 0x04u},\r
+ {0x96u, 0x04u},\r
+ {0x9Cu, 0x02u},\r
+ {0xA2u, 0x04u},\r
+ {0xA4u, 0x02u},\r
+ {0xA5u, 0x20u},\r
{0xA6u, 0x80u},\r
- {0xA7u, 0x02u},\r
- {0xA9u, 0x80u},\r
- {0xB0u, 0x10u},\r
- {0xB6u, 0x02u},\r
+ {0xA8u, 0x01u},\r
{0xC4u, 0x10u},\r
{0xCCu, 0x10u},\r
- {0xE6u, 0x20u},\r
- {0xE8u, 0x20u},\r
- {0x80u, 0x10u},\r
- {0x81u, 0x40u},\r
- {0x87u, 0x02u},\r
- {0x94u, 0x10u},\r
- {0x95u, 0x80u},\r
- {0x97u, 0x01u},\r
- {0xA7u, 0x02u},\r
- {0xABu, 0x04u},\r
- {0xE2u, 0x90u},\r
- {0xE6u, 0x80u},\r
- {0xEAu, 0x80u},\r
- {0x00u, 0x10u},\r
- {0x05u, 0x80u},\r
- {0x08u, 0x80u},\r
- {0x0Fu, 0x08u},\r
- {0x13u, 0x02u},\r
- {0x15u, 0x08u},\r
- {0x63u, 0x80u},\r
- {0x65u, 0x20u},\r
- {0x8Bu, 0x80u},\r
+ {0xE2u, 0x60u},\r
+ {0xEEu, 0x20u},\r
+ {0x63u, 0x20u},\r
+ {0xA5u, 0x20u},\r
+ {0xA7u, 0x80u},\r
+ {0xA8u, 0x02u},\r
+ {0xAAu, 0x04u},\r
+ {0xD8u, 0x40u},\r
+ {0xECu, 0x20u},\r
+ {0xEEu, 0x80u},\r
+ {0x03u, 0x08u},\r
+ {0x04u, 0x10u},\r
+ {0x09u, 0x20u},\r
+ {0x0Fu, 0x02u},\r
+ {0x10u, 0x80u},\r
+ {0x16u, 0x80u},\r
+ {0x62u, 0x08u},\r
+ {0x66u, 0x02u},\r
+ {0x81u, 0x01u},\r
+ {0x8Eu, 0x01u},\r
{0xC0u, 0x03u},\r
{0xC2u, 0x03u},\r
{0xC4u, 0x0Cu},\r
{0xD8u, 0x03u},\r
- {0xE2u, 0x01u},\r
- {0x03u, 0x80u},\r
- {0x07u, 0x40u},\r
- {0x0Bu, 0x80u},\r
- {0x0Cu, 0x02u},\r
- {0x57u, 0x08u},\r
- {0x58u, 0x10u},\r
- {0x64u, 0x20u},\r
- {0x66u, 0x80u},\r
- {0x83u, 0x40u},\r
- {0x87u, 0x02u},\r
+ {0xE4u, 0x02u},\r
+ {0x03u, 0x40u},\r
+ {0x05u, 0x01u},\r
+ {0x0Bu, 0x10u},\r
+ {0x0Fu, 0x80u},\r
+ {0x55u, 0x10u},\r
+ {0x5Eu, 0x80u},\r
+ {0x62u, 0x01u},\r
+ {0x65u, 0x80u},\r
+ {0x84u, 0x80u},\r
+ {0x86u, 0x10u},\r
+ {0x8Au, 0x08u},\r
+ {0x8Bu, 0x01u},\r
+ {0x8Cu, 0x80u},\r
{0x90u, 0x10u},\r
- {0x91u, 0x08u},\r
- {0x98u, 0x80u},\r
- {0x99u, 0x80u},\r
- {0x9Au, 0x80u},\r
- {0x9Bu, 0x02u},\r
- {0xA7u, 0xC0u},\r
- {0xABu, 0x04u},\r
- {0xADu, 0x20u},\r
- {0xAEu, 0x80u},\r
+ {0x9Au, 0x01u},\r
+ {0x9Du, 0x01u},\r
+ {0xA0u, 0x80u},\r
+ {0xA3u, 0x09u},\r
+ {0xA6u, 0x08u},\r
+ {0xAAu, 0x80u},\r
+ {0xAEu, 0x02u},\r
+ {0xB5u, 0x20u},\r
{0xC0u, 0x0Cu},\r
{0xC2u, 0x0Cu},\r
- {0xD4u, 0x03u},\r
- {0xD6u, 0x01u},\r
- {0xD8u, 0x01u},\r
- {0x53u, 0x80u},\r
- {0x82u, 0x04u},\r
- {0x84u, 0x10u},\r
- {0x88u, 0x80u},\r
- {0x8Bu, 0x80u},\r
- {0x91u, 0x08u},\r
- {0x98u, 0x80u},\r
- {0x99u, 0x80u},\r
+ {0xD4u, 0x02u},\r
+ {0xD6u, 0x05u},\r
+ {0xD8u, 0x02u},\r
+ {0xE2u, 0x01u},\r
+ {0xE4u, 0x01u},\r
+ {0xE6u, 0x02u},\r
+ {0xEEu, 0x02u},\r
+ {0x57u, 0x04u},\r
+ {0x82u, 0x40u},\r
+ {0x83u, 0x08u},\r
+ {0x8Du, 0x80u},\r
+ {0x90u, 0x10u},\r
{0x9Bu, 0x40u},\r
- {0x9Cu, 0x30u},\r
- {0xA7u, 0x08u},\r
- {0xA8u, 0x10u},\r
- {0xB3u, 0x40u},\r
- {0xB4u, 0x02u},\r
- {0xD4u, 0x04u},\r
- {0xE0u, 0x01u},\r
- {0xE2u, 0x04u},\r
- {0xEEu, 0x03u},\r
+ {0x9Cu, 0x80u},\r
+ {0x9Du, 0x80u},\r
+ {0xA3u, 0x08u},\r
+ {0xA5u, 0x10u},\r
+ {0xA6u, 0x50u},\r
+ {0xAFu, 0x10u},\r
+ {0xB7u, 0x40u},\r
+ {0xD4u, 0x02u},\r
+ {0xE4u, 0x02u},\r
+ {0xEEu, 0x02u},\r
{0x08u, 0x80u},\r
- {0x0Bu, 0x80u},\r
- {0x0Du, 0x02u},\r
- {0x0Eu, 0x08u},\r
- {0x80u, 0x80u},\r
- {0x84u, 0x20u},\r
- {0x87u, 0x40u},\r
- {0x8Fu, 0x08u},\r
- {0x99u, 0x80u},\r
- {0x9Bu, 0x40u},\r
- {0x9Cu, 0x20u},\r
- {0xA5u, 0x02u},\r
- {0xA6u, 0x04u},\r
- {0xA7u, 0x08u},\r
- {0xA9u, 0x02u},\r
- {0xADu, 0x04u},\r
+ {0x0Au, 0x40u},\r
+ {0x0Eu, 0x20u},\r
+ {0x0Fu, 0x02u},\r
+ {0x90u, 0x10u},\r
+ {0x96u, 0x40u},\r
+ {0x9Cu, 0x80u},\r
+ {0xA6u, 0x10u},\r
+ {0xA9u, 0x10u},\r
+ {0xABu, 0x04u},\r
+ {0xAEu, 0x40u},\r
+ {0xB7u, 0x40u},\r
{0xC2u, 0x0Fu},\r
- {0xE0u, 0x08u},\r
- {0x67u, 0x40u},\r
- {0x83u, 0x01u},\r
- {0x97u, 0x01u},\r
- {0xD8u, 0x80u},\r
- {0xE2u, 0x80u},\r
- {0x05u, 0x04u},\r
- {0x52u, 0x02u},\r
+ {0xEAu, 0x08u},\r
+ {0xA3u, 0x20u},\r
+ {0xABu, 0x10u},\r
+ {0xAFu, 0x80u},\r
+ {0xB3u, 0x20u},\r
+ {0xB5u, 0x20u},\r
+ {0xEEu, 0x90u},\r
+ {0x06u, 0x40u},\r
+ {0x53u, 0x04u},\r
{0x57u, 0x20u},\r
- {0x81u, 0x04u},\r
- {0x86u, 0x02u},\r
- {0x87u, 0x20u},\r
- {0xAFu, 0x40u},\r
+ {0x86u, 0x40u},\r
+ {0x8Bu, 0x04u},\r
+ {0xA3u, 0x20u},\r
{0xC0u, 0x20u},\r
- {0xD4u, 0xC0u},\r
- {0xE2u, 0x40u},\r
- {0xE4u, 0x80u},\r
- {0xE6u, 0x10u},\r
- {0xEEu, 0x40u},\r
- {0x8Cu, 0x02u},\r
- {0x99u, 0x80u},\r
- {0xABu, 0x40u},\r
- {0xE4u, 0x02u},\r
- {0x01u, 0x10u},\r
+ {0xD4u, 0x60u},\r
+ {0xE0u, 0x10u},\r
+ {0x83u, 0x01u},\r
+ {0x93u, 0x08u},\r
+ {0x9Eu, 0x02u},\r
+ {0xA8u, 0x10u},\r
+ {0xAFu, 0x01u},\r
+ {0xB3u, 0x04u},\r
+ {0xB6u, 0x02u},\r
+ {0xE8u, 0x01u},\r
+ {0xEAu, 0x02u},\r
+ {0x03u, 0x08u},\r
{0x06u, 0x02u},\r
- {0x50u, 0x06u},\r
- {0x80u, 0x04u},\r
- {0x86u, 0x02u},\r
- {0x89u, 0x10u},\r
- {0xA0u, 0x02u},\r
- {0xA9u, 0x80u},\r
+ {0x53u, 0x05u},\r
+ {0x8Bu, 0x08u},\r
+ {0x93u, 0x0Au},\r
+ {0x9Eu, 0x02u},\r
{0xC0u, 0x03u},\r
{0xD4u, 0x05u},\r
- {0xE2u, 0x01u},\r
+ {0xE2u, 0x04u},\r
{0x10u, 0x03u},\r
- {0x11u, 0x01u},\r
{0x1Au, 0x03u},\r
- {0x1Bu, 0x01u},\r
{0x00u, 0xFDu},\r
{0x01u, 0xBFu},\r
{0x02u, 0x2Au},\r
\r
/* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */\r
static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {\r
- 0xD6u, 0x20u, 0x00u, 0x40u, 0xD2u, 0x92u, 0x04u, 0x01u, 0x21u, 0x01u, 0x8Eu, 0xB0u, 0x17u, 0xC5u, 0x28u, 0x0Au, \r
- 0x00u, 0xB0u, 0x00u, 0x01u, 0x29u, 0x03u, 0x46u, 0xBCu, 0x20u, 0x91u, 0xD0u, 0x20u, 0xD6u, 0xB1u, 0x00u, 0x00u, \r
- 0xD6u, 0xB1u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0xD0u, 0x00u, 0x06u, 0x00u, 0x04u, 0x46u, 0x00u, 0x39u, \r
- 0x0Fu, 0x3Cu, 0x0Fu, 0xC4u, 0xF0u, 0x03u, 0x00u, 0x00u, 0x0Au, 0x00u, 0x20u, 0x2Cu, 0x00u, 0x00u, 0x00u, 0x00u, \r
- 0x36u, 0x05u, 0x40u, 0x00u, 0x02u, 0xDEu, 0xFBu, 0xC0u, 0x2Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, \r
+ 0x41u, 0xC0u, 0x00u, 0x02u, 0x08u, 0xC0u, 0x21u, 0x04u, 0x01u, 0x1Fu, 0x00u, 0x20u, 0x01u, 0x90u, 0x40u, 0x40u, \r
+ 0x41u, 0x7Fu, 0x00u, 0x80u, 0x07u, 0x80u, 0x18u, 0x00u, 0x04u, 0xC0u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, \r
+ 0x41u, 0xC0u, 0x00u, 0x01u, 0x10u, 0x00u, 0x00u, 0xFFu, 0x40u, 0x00u, 0x00u, 0x9Fu, 0x22u, 0x00u, 0x08u, 0x60u, \r
+ 0x40u, 0x00u, 0x3Fu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x05u, 0x04u, \r
+ 0x25u, 0x03u, 0x40u, 0x00u, 0x01u, 0xDEu, 0xBFu, 0xC0u, 0x2Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x2Cu, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, \r
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
\r
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x00u, 0x02u, 0x01u, 0x02u, 0x01u};\r
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL\r
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL\r
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB08_MSK\r
+.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB08_ST\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
+.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL\r
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
\r
/* SD_SCK */\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB07_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB07_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL\r
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB07_MSK\r
\r
/* SCSI_Out_Ctl */\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK\r
\r
/* SCSI_Out_DBx */\r
.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG\r
.set scsiTarget_StatusReg__0__POS, 0\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__2__POS, 2\r
.set scsiTarget_StatusReg__3__MASK, 0x08\r
.set scsiTarget_StatusReg__4__MASK, 0x10\r
.set scsiTarget_StatusReg__4__POS, 4\r
.set scsiTarget_StatusReg__MASK, 0x1F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB04_MSK\r
-.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL\r
-.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB04_ST\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST\r
\r
/* Debug_Timer_Interrupt */\r
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST\r
\r
/* SCSI_CTL_PHASE */\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST\r
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B1_UDB05_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B1_UDB05_ST\r
\r
/* Miscellaneous */\r
.set BCLK__BUS_CLK__HZ, 50000000\r
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
\r
/* SD_SCK */\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
\r
/* SCSI_Out_Ctl */\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
\r
/* SCSI_Out_DBx */\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL\r
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST\r
\r
/* Debug_Timer_Interrupt */\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
\r
/* SCSI_CTL_PHASE */\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
\r
/* SCSI_Glitch_Ctl */\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
\r
/* SCSI_Parity_Error */\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB05_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB05_ST\r
\r
/* Miscellaneous */\r
BCLK__BUS_CLK__HZ EQU 50000000\r
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
+SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL\r
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
\r
; SD_SCK\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB07_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB07_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB07_MSK\r
\r
; SCSI_Out_Ctl\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK\r
\r
; SCSI_Out_DBx\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG\r
scsiTarget_StatusReg__0__POS EQU 0\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__2__POS EQU 2\r
scsiTarget_StatusReg__3__MASK EQU 0x08\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK\r
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL\r
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST\r
\r
; Debug_Timer_Interrupt\r
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
\r
; SCSI_CTL_PHASE\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
\r
; SCSI_Glitch_Ctl\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
\r
; SCSI_Parity_Error\r
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB05_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB05_ST\r
\r
; Miscellaneous\r
BCLK__BUS_CLK__HZ EQU 50000000\r
const uint8 cy_meta_loadable[] = {\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x50u, 0x04u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x60u, 0x04u,\r
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006465" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_MASK_REG" address="0x40006485" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="" hidden="false">\r
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006565" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x40006585" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006595" bitWidth="8" desc="" hidden="false">\r
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Filtered_STATUS_REG" address="0x40006468" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Filtered_MASK_REG" address="0x40006488" bitWidth="8" desc="" hidden="false" />\r
- <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006498" bitWidth="8" desc="" hidden="false">\r
+ <register name="SCSI_Filtered_STATUS_REG" address="0x4000646B" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Filtered_MASK_REG" address="0x4000648B" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649B" bitWidth="8" desc="" hidden="false">\r
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
<block name="Clock_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647D" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
</block>\r
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">\r
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />\r
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006477" bitWidth="8" desc="" hidden="false" />\r
</block>\r
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />\r
<peripheral>\r
<name>SCSI_Parity_Error</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006465</baseAddress>\r
+ <baseAddress>0x40006565</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_Filtered</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006468</baseAddress>\r
+ <baseAddress>0x4000646B</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_Glitch_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000647D</baseAddress>\r
+ <baseAddress>0x40006474</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_CTL_PHASE</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000647C</baseAddress>\r
+ <baseAddress>0x40006475</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_Out_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006474</baseAddress>\r
+ <baseAddress>0x40006478</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
<peripheral>\r
<name>SCSI_Out_Bits</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006473</baseAddress>\r
+ <baseAddress>0x40006477</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x0</size>\r
#define BL_DUAL_APP_BOOTLOADER (0u)
#define BL_BOOTLOADER_APP_VERSION (0u)
-#define BL_FAST_APP_VALIDATION (0u)
+#define BL_FAST_APP_VALIDATION (1u)
#define BL_PACKET_CHECKSUM_CRC (0u)
-#define BL_WAIT_FOR_COMMAND (1u)
+#define BL_WAIT_FOR_COMMAND (0u)
#define BL_WAIT_FOR_COMMAND_TIME (20u)
#define BL_BOOTLOADER_APP_VALIDATION (1u)
#include "USBFS.h"
+
#if defined(USBFS_ENABLE_AUDIO_CLASS)
#include "USBFS_audio.h"
/* `#START AUDIO_READ_REQUESTS` Place other request handler here */
/* `#END` */
+
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK
+ USBFS_DispatchAUDIOClass_AUDIO_READ_REQUESTS_Callback();
+ #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK */
+
break;
default:
break;
/* `#END` */
- /* Entity ID Control Selector is MUTE */
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK
+ USBFS_DispatchAUDIOClass_MUTE_CONTROL_GET_REQUEST_Callback();
+ #endif /* USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK */
+
+ /* Entity ID Control Selector is MUTE */
USBFS_currentTD.wCount = 1u;
USBFS_currentTD.pData = &USBFS_currentMute;
requestHandled = USBFS_InitControlRead();
/* `#END` */
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK
+ USBFS_DispatchAUDIOClass_VOLUME_CONTROL_GET_REQUEST_Callback();
+ #endif /* USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK */
+
/* Entity ID Control Selector is VOLUME, */
USBFS_currentTD.wCount = USBFS_VOLUME_LEN;
USBFS_currentTD.pData = USBFS_currentVolume;
/* `#START OTHER_GET_CUR_REQUESTS` Place other request handler here */
/* `#END` */
+
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK
+ USBFS_DispatchAUDIOClass_OTHER_GET_CUR_REQUESTS_Callback();
+ #endif /* USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK */
}
break;
case USBFS_GET_MIN: /* GET_MIN */
/* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */
/* `#END` */
+
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_WRITE_REQUESTS_CALLBACK
+ USBFS_DispatchAUDIOClass_AUDIO_WRITE_REQUESTS_Callback();
+ #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_WRITE_REQUESTS_CALLBACK */
+
break;
default:
break;
/* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */
/* `#END` */
+
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_SAMPLING_FREQ_REQUESTS_CALLBACK
+ USBFS_DispatchAUDIOClass_AUDIO_SAMPLING_FREQ_REQUESTS_Callback();
+ #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_SAMPLING_FREQ_REQUESTS_CALLBACK */
+
break;
default:
break;
/* `#END` */
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK
+ USBFS_DispatchAUDIOClass_MUTE_SET_REQUEST_Callback();
+ #endif /* USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK */
+
/* Entity ID Control Selector is MUTE */
USBFS_currentTD.wCount = 1u;
USBFS_currentTD.pData = &USBFS_currentMute;
/* `#END` */
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK
+ USBFS_DispatchAUDIOClass_VOLUME_CONTROL_SET_REQUEST_Callback();
+ #endif /* USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK */
+
/* Entity ID Control Selector is VOLUME */
USBFS_currentTD.wCount = USBFS_VOLUME_LEN;
USBFS_currentTD.pData = USBFS_currentVolume;
/* `#START OTHER_SET_CUR_REQUESTS` Place other request handler here */
/* `#END` */
+
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK
+ USBFS_DispatchAUDIOClass_OTHER_SET_CUR_REQUESTS_Callback();
+ #endif /* USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK */
}
#endif /* USBFS_ENABLE_AUDIO_STREAMING */
/* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */
/* `#END` */
+
+ #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_CONTROL_SEL_REQUESTS_CALLBACK
+ USBFS_DispatchAUDIOClass_AUDIO_CONTROL_SEL_REQUESTS_Callback();
+ #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_CONTROL_SEL_REQUESTS_CALLBACK */
+
break;
default:
break;
#include "USBFS_pvt.h"
+
/***************************************
* CDC Variables
***************************************/
/* `#END` */
+ #ifdef USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK
+ USBFS_DispatchCDCClass_CDC_READ_REQUESTS_Callback();
+ #endif /* USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK */
+
default: /* requestHandled is initialized as FALSE by default */
break;
}
/* `#END` */
+ #ifdef USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK
+ USBFS_DispatchCDCClass_CDC_WRITE_REQUESTS_Callback();
+ #endif /* USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK */
+
default: /* requestHandled is initialized as FALSE by default */
break;
}
#include "USBFS_pvt.h"
+
/***************************************
* User Implemented Class Driver Declarations.
***************************************/
/* `#END` */
+ #ifdef USBFS_DISPATCH_CLASS_RQST_CALLBACK
+ USBFS_DispatchClassRqst_Callback();
+ #endif /* USBFS_DISPATCH_CLASS_RQST_CALLBACK */
+
return(requestHandled);
}
#include "USBFS_pvt.h"
+
/***************************************
* Global data allocation
***************************************/
uint8 bRegTemp;
uint8 modifyReg;
-
+ #ifdef USBFS_EP_0_ISR_ENTRY_CALLBACK
+ USBFS_EP_0_ISR_EntryCallback();
+ #endif /* USBFS_EP_0_ISR_ENTRY_CALLBACK */
+
bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR);
if ((bRegTemp & USBFS_MODE_ACKD) != 0u)
{
}
}
}
+ #ifdef USBFS_EP_0_ISR_EXIT_CALLBACK
+ USBFS_EP_0_ISR_ExitCallback();
+ #endif /* USBFS_EP_0_ISR_EXIT_CALLBACK */
}
#include "USBFS.h"
#include "USBFS_pvt.h"
+
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u))
#include "USBFS_midi.h"
#endif /* (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)) */
uint8 int_en;
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
+ #ifdef USBFS_EP_1_ISR_ENTRY_CALLBACK
+ USBFS_EP_1_ISR_EntryCallback();
+ #endif /* USBFS_EP_1_ISR_ENTRY_CALLBACK */
+
/* `#START EP1_USER_CODE` Place your code here */
/* `#END` */
/* `#END` */
+ #ifdef USBFS_EP_1_ISR_EXIT_CALLBACK
+ USBFS_EP_1_ISR_ExitCallback();
+ #endif /* USBFS_EP_1_ISR_EXIT_CALLBACK */
+
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
uint8 int_en;
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
+ #ifdef USBFS_EP_2_ISR_ENTRY_CALLBACK
+ USBFS_EP_2_ISR_EntryCallback();
+ #endif /* USBFS_EP_2_ISR_ENTRY_CALLBACK */
+
/* `#START EP2_USER_CODE` Place your code here */
/* `#END` */
/* `#END` */
+ #ifdef USBFS_EP_2_ISR_EXIT_CALLBACK
+ USBFS_EP_2_ISR_ExitCallback();
+ #endif /* USBFS_EP_2_ISR_EXIT_CALLBACK */
+
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
uint8 int_en;
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
+ #ifdef USBFS_EP_3_ISR_ENTRY_CALLBACK
+ USBFS_EP_3_ISR_EntryCallback();
+ #endif /* USBFS_EP_3_ISR_ENTRY_CALLBACK */
+
/* `#START EP3_USER_CODE` Place your code here */
/* `#END` */
/* `#END` */
+ #ifdef USBFS_EP_3_ISR_EXIT_CALLBACK
+ USBFS_EP_3_ISR_ExitCallback();
+ #endif /* USBFS_EP_3_ISR_EXIT_CALLBACK */
+
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
+ #ifdef USBFS_EP_4_ISR_ENTRY_CALLBACK
+ USBFS_EP_4_ISR_EntryCallback();
+ #endif /* USBFS_EP_4_ISR_ENTRY_CALLBACK */
+
/* `#START EP4_USER_CODE` Place your code here */
/* `#END` */
/* `#END` */
+ #ifdef USBFS_EP_4_ISR_EXIT_CALLBACK
+ USBFS_EP_4_ISR_ExitCallback();
+ #endif /* USBFS_EP_4_ISR_EXIT_CALLBACK */
+
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
+ #ifdef USBFS_EP_5_ISR_ENTRY_CALLBACK
+ USBFS_EP_5_ISR_EntryCallback();
+ #endif /* USBFS_EP_5_ISR_ENTRY_CALLBACK */
+
/* `#START EP5_USER_CODE` Place your code here */
/* `#END` */
/* `#END` */
+ #ifdef USBFS_EP_5_ISR_EXIT_CALLBACK
+ USBFS_EP_5_ISR_ExitCallback();
+ #endif /* USBFS_EP_5_ISR_EXIT_CALLBACK */
+
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
+ #ifdef USBFS_EP_6_ISR_ENTRY_CALLBACK
+ USBFS_EP_6_ISR_EntryCallback();
+ #endif /* USBFS_EP_6_ISR_ENTRY_CALLBACK */
+
/* `#START EP6_USER_CODE` Place your code here */
/* `#END` */
/* `#END` */
+ #ifdef USBFS_EP_6_ISR_EXIT_CALLBACK
+ USBFS_EP_6_ISR_ExitCallback();
+ #endif /* USBFS_EP_6_ISR_EXIT_CALLBACK */
+
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
+ #ifdef USBFS_EP_7_ISR_ENTRY_CALLBACK
+ USBFS_EP_7_ISR_EntryCallback();
+ #endif /* USBFS_EP_7_ISR_ENTRY_CALLBACK */
+
/* `#START EP7_USER_CODE` Place your code here */
/* `#END` */
/* `#END` */
+ #ifdef USBFS_EP_7_ISR_EXIT_CALLBACK
+ USBFS_EP_7_ISR_ExitCallback();
+ #endif /* USBFS_EP_7_ISR_EXIT_CALLBACK */
+
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
+ #ifdef USBFS_EP_8_ISR_ENTRY_CALLBACK
+ USBFS_EP_8_ISR_EntryCallback();
+ #endif /* USBFS_EP_8_ISR_ENTRY_CALLBACK */
+
/* `#START EP8_USER_CODE` Place your code here */
/* `#END` */
/* `#END` */
+ #ifdef USBFS_EP_8_ISR_EXIT_CALLBACK
+ USBFS_EP_8_ISR_ExitCallback();
+ #endif /* USBFS_EP_8_ISR_EXIT_CALLBACK */
+
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
*******************************************************************************/
CY_ISR(USBFS_SOF_ISR)
{
+ #ifdef USBFS_SOF_ISR_INTERRUPT_CALLBACK
+ USBFS_SOF_ISR_InterruptCallback();
+ #endif /* USBFS_SOF_ISR_INTERRUPT_CALLBACK */
+
/* `#START SOF_USER_CODE` Place your code here */
/* `#END` */
*******************************************************************************/
CY_ISR(USBFS_BUS_RESET_ISR)
{
+ #ifdef USBFS_BUS_RESET_ISR_ENTRY_CALLBACK
+ USBFS_BUS_RESET_ISR_EntryCallback();
+ #endif /* USBFS_BUS_RESET_ISR_ENTRY_CALLBACK */
+
/* `#START BUS_RESET_USER_CODE` Place your code here */
/* `#END` */
USBFS_ReInitComponent();
+
+ #ifdef USBFS_BUS_RESET_ISR_EXIT_CALLBACK
+ USBFS_BUS_RESET_ISR_ExitCallback();
+ #endif /* USBFS_BUS_RESET_ISR_EXIT_CALLBACK */
}
uint8 ep = USBFS_EP1;
uint8 ptr = 0u;
+ #ifdef USBFS_ARB_ISR_ENTRY_CALLBACK
+ USBFS_ARB_ISR_EntryCallback();
+ #endif /* USBFS_ARB_ISR_ENTRY_CALLBACK */
+
/* `#START ARB_BEGIN_USER_CODE` Place your code here */
/* `#END` */
/* `#END` */
+ #ifdef USBFS_ARB_ISR_CALLBACK
+ USBFS_ARB_ISR_Callback();
+ #endif /* USBFS_ARB_ISR_CALLBACK */
+
CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr), ep_status); /* Clear Serviced events */
}
ptr += USBFS_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */
/* `#START ARB_END_USER_CODE` Place your code here */
/* `#END` */
+
+ #ifdef USBFS_ARB_ISR_EXIT_CALLBACK
+ USBFS_ARB_ISR_ExitCallback();
+ #endif /* USBFS_ARB_ISR_EXIT_CALLBACK */
}
#endif /* USBFS_EP_MM */
uint8 ep = USBFS_EP1;
uint8 ptr = 0u;
+ #ifdef USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK
+ USBFS_EP_DMA_DONE_ISR_EntryCallback();
+ #endif /* USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK */
+
/* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */
/* `#END` */
/* `#END` */
+ #ifdef USBFS_EP_DMA_DONE_ISR_CALLBACK
+ USBFS_EP_DMA_DONE_ISR_Callback();
+ #endif /* USBFS_EP_DMA_DONE_ISR_CALLBACK */
+
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ptr), 0x00u);
/* repeat 2 last bytes to prefetch endpoint area */
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ptr),
/* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */
/* `#END` */
+
+ #ifdef USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK
+ USBFS_EP_DMA_DONE_ISR_ExitCallback();
+ #endif /* USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK */
}
#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
#include "USBFS_hid.h"
+
/***************************************
* HID Variables
***************************************/
/* `#START HID_FINDREPORT` Place custom handling here */
/* `#END` */
+
+ #ifdef USBFS_FIND_REPORT_CALLBACK
+ USBFS_FindReport_Callback();
+ #endif /* USBFS_FIND_REPORT_CALLBACK */
+
USBFS_currentTD.count = 0u; /* Init not supported condition */
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);
reportType = CY_GET_REG8(USBFS_wValueHi);
#include "USBFS_pvt.h"
+
/***************************************
* MIDI Constants
***************************************/
/* `#START CUSTOM_MIDI_OUT_EP_SERV` Place your code here */
/* `#END` */
+
+ #ifdef USBFS_MIDI_OUT_EP_SERVICE_CALLBACK
+ USBFS_MIDI_OUT_EP_Service_Callback();
+ #endif /* USBFS_MIDI_OUT_EP_SERVICE_CALLBACK */
}
#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
/* `#END` */
+ #ifdef USBFS_MIDI_INIT_CALLBACK
+ USBFS_MIDI_Init_Callback();
+ #endif /* USBFS_MIDI_INIT_CALLBACK */
}
/* `#END` */
+ #ifdef USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK
+ USBFS_MIDI1_ProcessUsbOut_EntryCallback();
+ #endif /* USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK */
+
cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK;
if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1))
{
/* `#START MIDI1_PROCESS_OUT_END` */
/* `#END` */
+
+ #ifdef USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK
+ USBFS_MIDI1_ProcessUsbOut_ExitCallback();
+ #endif /* USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK */
}
/* `#END` */
+ #ifdef USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK
+ USBFS_MIDI2_ProcessUsbOut_EntryCallback();
+ #endif /* USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK */
+
cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK;
if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1))
{
/* `#START MIDI2_PROCESS_OUT_END` */
/* `#END` */
+
+ #ifdef USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK
+ USBFS_MIDI2_ProcessUsbOut_ExitCallback();
+ #endif /* USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK */
}
#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
#include "USBFS_pvt.h"
+
/***************************************
* Custom Declarations
***************************************/
*******************************************************************************/
CY_ISR(USBFS_DP_ISR)
{
+ #ifdef USBFS_DP_ISR_ENTRY_CALLBACK
+ USBFS_DP_ISR_EntryCallback();
+ #endif /* USBFS_DP_ISR_ENTRY_CALLBACK */
+
/* `#START DP_USER_CODE` Place your code here */
/* `#END` */
/* Clears active interrupt */
CY_GET_REG8(USBFS_DP_INTSTAT_PTR);
+
+ #ifdef USBFS_DP_ISR_EXIT_CALLBACK
+ USBFS_DP_ISR_ExitCallback();
+ #endif /* USBFS_DP_ISR_EXIT_CALLBACK */
}
#endif /* (USBFS_DP_ISR_REMOVE == 0u) */
#include "USBFS.h"
#include "USBFS_pvt.h"
+
#if(USBFS_EXTERN_VND == USBFS_FALSE)
/* `#END` */
+ #ifdef USBFS_HANDLE_VENDOR_RQST_CALLBACK
+ USBFS_HandleVendorRqst_Callback();
+ #endif /* USBFS_HANDLE_VENDOR_RQST_CALLBACK */
+
return(requestHandled);
}
/* `#END` */
-
#endif /* USBFS_EXTERN_VND */
/*******************************************************************************
-* FILENAME: cydevice.h
+* File Name: cydevice.h
* OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 3.1
+* PSoC Creator 3.3
*
-* DESCRIPTION:
+* Description:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************
-* FILENAME: cydevice_trm.h
+* File Name: cydevice_trm.h
*
-* PSoC Creator 3.1
+* PSoC Creator 3.3
*
-* DESCRIPTION:
+* Description:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************
-* FILENAME: cydevicegnu.inc
+* File Name: cydevicegnu.inc
* OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 3.1
+* PSoC Creator 3.3
*
-* DESCRIPTION:
+* Description:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************
-* FILENAME: cydevicegnu_trm.inc
+* File Name: cydevicegnu_trm.inc
*
-* PSoC Creator 3.1
+* PSoC Creator 3.3
*
-* DESCRIPTION:
+* Description:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
;
-; FILENAME: cydeviceiar.inc
+; File Name: cydeviceiar.inc
; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 3.1
+; PSoC Creator 3.3
;
-; DESCRIPTION:
+; Description:
; This file provides all of the address values for the entire PSoC device.
;
;-------------------------------------------------------------------------------
-; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
;
-; FILENAME: cydeviceiar_trm.inc
+; File Name: cydeviceiar_trm.inc
;
-; PSoC Creator 3.1
+; PSoC Creator 3.3
;
-; DESCRIPTION:
+; Description:
; This file provides all of the address values for the entire PSoC device.
;
;-------------------------------------------------------------------------------
-; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
;
-; FILENAME: cydevicerv.inc
+; File Name: cydevicerv.inc
; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 3.1
+; PSoC Creator 3.3
;
-; DESCRIPTION:
+; Description:
; This file provides all of the address values for the entire PSoC device.
;
;-------------------------------------------------------------------------------
-; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
;
-; FILENAME: cydevicerv_trm.inc
+; File Name: cydevicerv_trm.inc
;
-; PSoC Creator 3.1
+; PSoC Creator 3.3
;
-; DESCRIPTION:
+; Description:
; This file provides all of the address values for the entire PSoC device.
;
;-------------------------------------------------------------------------------
-; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+; Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
-#include <cydevice.h>
-#include <cydevice_trm.h>
+#include "cydevice.h"
+#include "cydevice_trm.h"
/* LED */
+#define LED__0__INTTYPE CYREG_PICU0_INTTYPE1
#define LED__0__MASK 0x02u
#define LED__0__PC CYREG_PRT0_PC1
#define LED__0__PORT 0u
#define LED__DM2 CYREG_PRT0_DM2
#define LED__DR CYREG_PRT0_DR
#define LED__INP_DIS CYREG_PRT0_INP_DIS
+#define LED__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE
#define LED__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define LED__LCD_EN CYREG_PRT0_LCD_EN
#define LED__MASK 0x02u
#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* USBFS_Dm */
+#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7
#define USBFS_Dm__0__MASK 0x80u
#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
#define USBFS_Dm__0__PORT 15u
#define USBFS_Dm__DM2 CYREG_PRT15_DM2
#define USBFS_Dm__DR CYREG_PRT15_DR
#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
+#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
#define USBFS_Dm__MASK 0x80u
#define USBFS_Dm__SLW CYREG_PRT15_SLW
/* USBFS_Dp */
+#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6
#define USBFS_Dp__0__MASK 0x40u
#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
#define USBFS_Dp__0__PORT 15u
#define USBFS_Dp__DR CYREG_PRT15_DR
#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
+#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE
#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
#define USBFS_Dp__MASK 0x40u
#define SCSI_Out__0__DM2 CYREG_PRT15_DM2
#define SCSI_Out__0__DR CYREG_PRT15_DR
#define SCSI_Out__0__INP_DIS CYREG_PRT15_INP_DIS
+#define SCSI_Out__0__INTTYPE CYREG_PICU15_INTTYPE5
#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define SCSI_Out__0__LCD_EN CYREG_PRT15_LCD_EN
#define SCSI_Out__0__MASK 0x20u
#define SCSI_Out__1__DM2 CYREG_PRT15_DM2
#define SCSI_Out__1__DR CYREG_PRT15_DR
#define SCSI_Out__1__INP_DIS CYREG_PRT15_INP_DIS
+#define SCSI_Out__1__INTTYPE CYREG_PICU15_INTTYPE4
#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define SCSI_Out__1__LCD_EN CYREG_PRT15_LCD_EN
#define SCSI_Out__1__MASK 0x10u
#define SCSI_Out__2__DM2 CYREG_PRT6_DM2
#define SCSI_Out__2__DR CYREG_PRT6_DR
#define SCSI_Out__2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out__2__INTTYPE CYREG_PICU6_INTTYPE1
#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_Out__2__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_Out__2__MASK 0x02u
#define SCSI_Out__3__DM2 CYREG_PRT6_DM2
#define SCSI_Out__3__DR CYREG_PRT6_DR
#define SCSI_Out__3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out__3__INTTYPE CYREG_PICU6_INTTYPE0
#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_Out__3__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_Out__3__MASK 0x01u
#define SCSI_Out__4__DM2 CYREG_PRT4_DM2
#define SCSI_Out__4__DR CYREG_PRT4_DR
#define SCSI_Out__4__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__4__INTTYPE CYREG_PICU4_INTTYPE5
#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
#define SCSI_Out__4__LCD_EN CYREG_PRT4_LCD_EN
#define SCSI_Out__4__MASK 0x20u
#define SCSI_Out__5__DM2 CYREG_PRT4_DM2
#define SCSI_Out__5__DR CYREG_PRT4_DR
#define SCSI_Out__5__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__5__INTTYPE CYREG_PICU4_INTTYPE4
#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
#define SCSI_Out__5__LCD_EN CYREG_PRT4_LCD_EN
#define SCSI_Out__5__MASK 0x10u
#define SCSI_Out__6__DM2 CYREG_PRT0_DM2
#define SCSI_Out__6__DR CYREG_PRT0_DR
#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__6__INTTYPE CYREG_PICU0_INTTYPE7
#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__6__MASK 0x80u
#define SCSI_Out__7__DM2 CYREG_PRT0_DM2
#define SCSI_Out__7__DR CYREG_PRT0_DR
#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__7__INTTYPE CYREG_PICU0_INTTYPE6
#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__7__MASK 0x40u
#define SCSI_Out__8__DM2 CYREG_PRT0_DM2
#define SCSI_Out__8__DR CYREG_PRT0_DR
#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__8__INTTYPE CYREG_PICU0_INTTYPE3
#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__8__MASK 0x08u
#define SCSI_Out__9__DM2 CYREG_PRT0_DM2
#define SCSI_Out__9__DR CYREG_PRT0_DR
#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__9__INTTYPE CYREG_PICU0_INTTYPE2
#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__9__MASK 0x04u
#define SCSI_Out__ACK__DM2 CYREG_PRT6_DM2
#define SCSI_Out__ACK__DR CYREG_PRT6_DR
#define SCSI_Out__ACK__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out__ACK__INTTYPE CYREG_PICU6_INTTYPE0
#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_Out__ACK__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_Out__ACK__MASK 0x01u
#define SCSI_Out__ATN__DM2 CYREG_PRT15_DM2
#define SCSI_Out__ATN__DR CYREG_PRT15_DR
#define SCSI_Out__ATN__INP_DIS CYREG_PRT15_INP_DIS
+#define SCSI_Out__ATN__INTTYPE CYREG_PICU15_INTTYPE4
#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define SCSI_Out__ATN__LCD_EN CYREG_PRT15_LCD_EN
#define SCSI_Out__ATN__MASK 0x10u
#define SCSI_Out__BSY__DM2 CYREG_PRT6_DM2
#define SCSI_Out__BSY__DR CYREG_PRT6_DR
#define SCSI_Out__BSY__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out__BSY__INTTYPE CYREG_PICU6_INTTYPE1
#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_Out__BSY__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_Out__BSY__MASK 0x02u
#define SCSI_Out__CD__DM2 CYREG_PRT0_DM2
#define SCSI_Out__CD__DR CYREG_PRT0_DR
#define SCSI_Out__CD__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__CD__INTTYPE CYREG_PICU0_INTTYPE6
#define SCSI_Out__CD__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__CD__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__CD__MASK 0x40u
#define SCSI_Out__DBP_raw__DM2 CYREG_PRT15_DM2
#define SCSI_Out__DBP_raw__DR CYREG_PRT15_DR
#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT15_INP_DIS
+#define SCSI_Out__DBP_raw__INTTYPE CYREG_PICU15_INTTYPE5
#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT15_LCD_EN
#define SCSI_Out__DBP_raw__MASK 0x20u
#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2
#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR
#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__IO_raw__INTTYPE CYREG_PICU0_INTTYPE2
#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__IO_raw__MASK 0x04u
#define SCSI_Out__MSG__DM2 CYREG_PRT4_DM2
#define SCSI_Out__MSG__DR CYREG_PRT4_DR
#define SCSI_Out__MSG__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__MSG__INTTYPE CYREG_PICU4_INTTYPE4
#define SCSI_Out__MSG__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
#define SCSI_Out__MSG__LCD_EN CYREG_PRT4_LCD_EN
#define SCSI_Out__MSG__MASK 0x10u
#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2
#define SCSI_Out__REQ__DR CYREG_PRT0_DR
#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__REQ__INTTYPE CYREG_PICU0_INTTYPE3
#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__REQ__MASK 0x08u
#define SCSI_Out__RST__DM2 CYREG_PRT4_DM2
#define SCSI_Out__RST__DR CYREG_PRT4_DR
#define SCSI_Out__RST__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__RST__INTTYPE CYREG_PICU4_INTTYPE5
#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
#define SCSI_Out__RST__LCD_EN CYREG_PRT4_LCD_EN
#define SCSI_Out__RST__MASK 0x20u
#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2
#define SCSI_Out__SEL__DR CYREG_PRT0_DR
#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__SEL__INTTYPE CYREG_PICU0_INTTYPE7
#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN
#define SCSI_Out__SEL__MASK 0x80u
#define SCSI_Out_DBx__0__DM2 CYREG_PRT5_DM2
#define SCSI_Out_DBx__0__DR CYREG_PRT5_DR
#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__0__INTTYPE CYREG_PICU5_INTTYPE1
#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT5_LCD_EN
#define SCSI_Out_DBx__0__MASK 0x02u
#define SCSI_Out_DBx__1__DM2 CYREG_PRT5_DM2
#define SCSI_Out_DBx__1__DR CYREG_PRT5_DR
#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__1__INTTYPE CYREG_PICU5_INTTYPE0
#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT5_LCD_EN
#define SCSI_Out_DBx__1__MASK 0x01u
#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2
#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR
#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__2__INTTYPE CYREG_PICU6_INTTYPE5
#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_Out_DBx__2__MASK 0x20u
#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2
#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR
#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__3__INTTYPE CYREG_PICU6_INTTYPE4
#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_Out_DBx__3__MASK 0x10u
#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2
#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR
#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__4__INTTYPE CYREG_PICU2_INTTYPE7
#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
#define SCSI_Out_DBx__4__MASK 0x80u
#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2
#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR
#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__5__INTTYPE CYREG_PICU2_INTTYPE6
#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
#define SCSI_Out_DBx__5__MASK 0x40u
#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2
#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR
#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__6__INTTYPE CYREG_PICU2_INTTYPE3
#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
#define SCSI_Out_DBx__6__MASK 0x08u
#define SCSI_Out_DBx__7__DM2 CYREG_PRT2_DM2
#define SCSI_Out_DBx__7__DR CYREG_PRT2_DR
#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__7__INTTYPE CYREG_PICU2_INTTYPE2
#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT2_LCD_EN
#define SCSI_Out_DBx__7__MASK 0x04u
#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT5_DM2
#define SCSI_Out_DBx__DB0__DR CYREG_PRT5_DR
#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__DB0__INTTYPE CYREG_PICU5_INTTYPE1
#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN
#define SCSI_Out_DBx__DB0__MASK 0x02u
#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT5_DM2
#define SCSI_Out_DBx__DB1__DR CYREG_PRT5_DR
#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__DB1__INTTYPE CYREG_PICU5_INTTYPE0
#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN
#define SCSI_Out_DBx__DB1__MASK 0x01u
#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2
#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR
#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB2__INTTYPE CYREG_PICU6_INTTYPE5
#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_Out_DBx__DB2__MASK 0x20u
#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2
#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR
#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB3__INTTYPE CYREG_PICU6_INTTYPE4
#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_Out_DBx__DB3__MASK 0x10u
#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2
#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR
#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB4__INTTYPE CYREG_PICU2_INTTYPE7
#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
#define SCSI_Out_DBx__DB4__MASK 0x80u
#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2
#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR
#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB5__INTTYPE CYREG_PICU2_INTTYPE6
#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
#define SCSI_Out_DBx__DB5__MASK 0x40u
#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2
#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR
#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE3
#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
#define SCSI_Out_DBx__DB6__MASK 0x08u
#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT2_DM2
#define SCSI_Out_DBx__DB7__DR CYREG_PRT2_DR
#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB7__INTTYPE CYREG_PICU2_INTTYPE2
#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN
#define SCSI_Out_DBx__DB7__MASK 0x04u
#define SCSI_Out_DBx__DB7__SLW CYREG_PRT2_SLW
/* SD_PULLUP */
+#define SD_PULLUP__0__INTTYPE CYREG_PICU3_INTTYPE1
#define SD_PULLUP__0__MASK 0x02u
#define SD_PULLUP__0__PC CYREG_PRT3_PC1
#define SD_PULLUP__0__PORT 3u
#define SD_PULLUP__0__SHIFT 1
+#define SD_PULLUP__1__INTTYPE CYREG_PICU3_INTTYPE2
#define SD_PULLUP__1__MASK 0x04u
#define SD_PULLUP__1__PC CYREG_PRT3_PC2
#define SD_PULLUP__1__PORT 3u
#define SD_PULLUP__1__SHIFT 2
+#define SD_PULLUP__2__INTTYPE CYREG_PICU3_INTTYPE3
#define SD_PULLUP__2__MASK 0x08u
#define SD_PULLUP__2__PC CYREG_PRT3_PC3
#define SD_PULLUP__2__PORT 3u
#define SD_PULLUP__2__SHIFT 3
+#define SD_PULLUP__3__INTTYPE CYREG_PICU3_INTTYPE4
#define SD_PULLUP__3__MASK 0x10u
#define SD_PULLUP__3__PC CYREG_PRT3_PC4
#define SD_PULLUP__3__PORT 3u
#define SD_PULLUP__3__SHIFT 4
+#define SD_PULLUP__4__INTTYPE CYREG_PICU3_INTTYPE5
#define SD_PULLUP__4__MASK 0x20u
#define SD_PULLUP__4__PC CYREG_PRT3_PC5
#define SD_PULLUP__4__PORT 3u
#define SD_PULLUP__DM2 CYREG_PRT3_DM2
#define SD_PULLUP__DR CYREG_PRT3_DR
#define SD_PULLUP__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_PULLUP__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE
#define SD_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
#define SD_PULLUP__LCD_EN CYREG_PRT3_LCD_EN
#define SD_PULLUP__MASK 0x3Eu
#define BCLK__BUS_CLK__HZ 64000000U
#define BCLK__BUS_CLK__KHZ 64000U
#define BCLK__BUS_CLK__MHZ 64U
-#define CY_VERSION "PSoC Creator 3.1"
+#define CY_PROJECT_NAME "USB_Bootloader"
+#define CY_VERSION "PSoC Creator 3.3"
#define CYDEV_BOOTLOADER_APPLICATIONS 1u
#define CYDEV_BOOTLOADER_CHECKSUM_BASIC 0
#define CYDEV_BOOTLOADER_CHECKSUM_CRC 1
#define CyBtldr_USBFS CYDEV_BOOTLOADER_IO_COMP_USBFS
#define CYDEV_BOOTLOADER_IO_COMP CYDEV_BOOTLOADER_IO_COMP_USBFS
#define CYDEV_CHIP_DIE_LEOPARD 1u
-#define CYDEV_CHIP_DIE_PANTHER 6u
-#define CYDEV_CHIP_DIE_PSOC4A 3u
-#define CYDEV_CHIP_DIE_PSOC5LP 5u
+#define CYDEV_CHIP_DIE_PANTHER 18u
+#define CYDEV_CHIP_DIE_PSOC4A 10u
+#define CYDEV_CHIP_DIE_PSOC5LP 17u
+#define CYDEV_CHIP_DIE_TMA4 2u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
#define CYDEV_CHIP_JTAG_ID 0x2E133069u
#define CYDEV_CHIP_MEMBER_3A 1u
-#define CYDEV_CHIP_MEMBER_4A 3u
-#define CYDEV_CHIP_MEMBER_4D 2u
-#define CYDEV_CHIP_MEMBER_4F 4u
-#define CYDEV_CHIP_MEMBER_5A 6u
-#define CYDEV_CHIP_MEMBER_5B 5u
+#define CYDEV_CHIP_MEMBER_4A 10u
+#define CYDEV_CHIP_MEMBER_4C 15u
+#define CYDEV_CHIP_MEMBER_4D 6u
+#define CYDEV_CHIP_MEMBER_4E 4u
+#define CYDEV_CHIP_MEMBER_4F 11u
+#define CYDEV_CHIP_MEMBER_4G 2u
+#define CYDEV_CHIP_MEMBER_4H 9u
+#define CYDEV_CHIP_MEMBER_4I 14u
+#define CYDEV_CHIP_MEMBER_4J 7u
+#define CYDEV_CHIP_MEMBER_4K 8u
+#define CYDEV_CHIP_MEMBER_4L 13u
+#define CYDEV_CHIP_MEMBER_4M 12u
+#define CYDEV_CHIP_MEMBER_4N 5u
+#define CYDEV_CHIP_MEMBER_4U 3u
+#define CYDEV_CHIP_MEMBER_5A 17u
+#define CYDEV_CHIP_MEMBER_5B 16u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
+#define CYDEV_CHIP_REV_TMA4_ES 17u
+#define CYDEV_CHIP_REV_TMA4_ES2 33u
+#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_3A_ES1 0u
#define CYDEV_CHIP_REVISION_3A_ES2 1u
#define CYDEV_CHIP_REVISION_3A_ES3 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
+#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u
+#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
+#define CYDEV_CHIP_REVISION_4G_ES 17u
+#define CYDEV_CHIP_REVISION_4G_ES2 33u
+#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
+#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CONFIGURATION_COMPRESSED 1
#define CYDEV_CONFIGURATION_DMA 0
-#define CYDEV_CONFIGURATION_ECC 0
+#define CYDEV_CONFIGURATION_ECC 1
#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
#define CYDEV_HEAP_SIZE 0x0800
#define CYDEV_INSTRUCT_CACHE_ENABLED 1
#define CYDEV_INTR_RISING 0x00000000u
+#define CYDEV_IS_EXPORTING_CODE 0
+#define CYDEV_IS_IMPORTING_CODE 0
#define CYDEV_PROJ_TYPE 1
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
+#define CYDEV_PROJ_TYPE_LAUNCHER 5
#define CYDEV_PROJ_TYPE_LOADABLE 2
+#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_PROTECTION_ENABLE 0
/*******************************************************************************
-* FILENAME: cyfitter_cfg.c
-* PSoC Creator 3.1
+* File Name: cyfitter_cfg.c
+*
+* PSoC Creator 3.3
*
* Description:
-* This file is automatically generated by PSoC Creator with device
-* initialization code. Except for the user defined sections in
-* CyClockStartupError(), this file should not be modified.
+* This file contains device initialization code.
+* Except for the user defined sections in CyClockStartupError(), this file should not be modified.
+* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#include <string.h>
-#include <cytypes.h>
-#include <cydevice_trm.h>
-#include <cyfitter.h>
-#include <CyLib.h>
-#include <cyfitter_cfg.h>
+#include "cytypes.h"
+#include "cydevice_trm.h"
+#include "cyfitter.h"
+#include "CyLib.h"
+#include "cyfitter_cfg.h"
#define CY_NEED_CYCLOCKSTARTUPERROR 1
CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u);
}
+
/* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DR), (const void CYCODE *)(BS_IOPINS0_0_VAL), 10u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT5_DM0), (const void CYCODE *)(BS_IOPINS0_5_VAL), 8u);
CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u);
-
/* Switch Boost to the precision bandgap reference from its internal reference */
CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));
/*******************************************************************************
-* FILENAME: cyfitter_cfg.h
-* PSoC Creator 3.1
+* File Name: cyfitter_cfg.h
+*
+* PSoC Creator 3.3
*
* Description:
+* This file provides basic startup and mux configration settings
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#ifndef CYFITTER_CFG_H
#define CYFITTER_CFG_H
-#include <cytypes.h>
+#include "cytypes.h"
extern void cyfitter_cfg(void);
.include "cydevicegnu_trm.inc"
/* LED */
+.set LED__0__INTTYPE, CYREG_PICU0_INTTYPE1
.set LED__0__MASK, 0x02
.set LED__0__PC, CYREG_PRT0_PC1
.set LED__0__PORT, 0
.set LED__DM2, CYREG_PRT0_DM2
.set LED__DR, CYREG_PRT0_DR
.set LED__INP_DIS, CYREG_PRT0_INP_DIS
+.set LED__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU0_BASE
.set LED__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set LED__LCD_EN, CYREG_PRT0_LCD_EN
.set LED__MASK, 0x02
.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* USBFS_Dm */
+.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7
.set USBFS_Dm__0__MASK, 0x80
.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
.set USBFS_Dm__0__PORT, 15
.set USBFS_Dm__DM2, CYREG_PRT15_DM2
.set USBFS_Dm__DR, CYREG_PRT15_DR
.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS
+.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE
.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN
.set USBFS_Dm__MASK, 0x80
.set USBFS_Dm__SLW, CYREG_PRT15_SLW
/* USBFS_Dp */
+.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6
.set USBFS_Dp__0__MASK, 0x40
.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0
.set USBFS_Dp__0__PORT, 15
.set USBFS_Dp__DR, CYREG_PRT15_DR
.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS
.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT
+.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE
.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN
.set USBFS_Dp__MASK, 0x40
.set SCSI_Out__0__DM2, CYREG_PRT15_DM2
.set SCSI_Out__0__DR, CYREG_PRT15_DR
.set SCSI_Out__0__INP_DIS, CYREG_PRT15_INP_DIS
+.set SCSI_Out__0__INTTYPE, CYREG_PICU15_INTTYPE5
.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
.set SCSI_Out__0__LCD_EN, CYREG_PRT15_LCD_EN
.set SCSI_Out__0__MASK, 0x20
.set SCSI_Out__1__DM2, CYREG_PRT15_DM2
.set SCSI_Out__1__DR, CYREG_PRT15_DR
.set SCSI_Out__1__INP_DIS, CYREG_PRT15_INP_DIS
+.set SCSI_Out__1__INTTYPE, CYREG_PICU15_INTTYPE4
.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
.set SCSI_Out__1__LCD_EN, CYREG_PRT15_LCD_EN
.set SCSI_Out__1__MASK, 0x10
.set SCSI_Out__2__DM2, CYREG_PRT6_DM2
.set SCSI_Out__2__DR, CYREG_PRT6_DR
.set SCSI_Out__2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out__2__INTTYPE, CYREG_PICU6_INTTYPE1
.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_Out__2__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_Out__2__MASK, 0x02
.set SCSI_Out__3__DM2, CYREG_PRT6_DM2
.set SCSI_Out__3__DR, CYREG_PRT6_DR
.set SCSI_Out__3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out__3__INTTYPE, CYREG_PICU6_INTTYPE0
.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_Out__3__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_Out__3__MASK, 0x01
.set SCSI_Out__4__DM2, CYREG_PRT4_DM2
.set SCSI_Out__4__DR, CYREG_PRT4_DR
.set SCSI_Out__4__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__4__INTTYPE, CYREG_PICU4_INTTYPE5
.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
.set SCSI_Out__4__LCD_EN, CYREG_PRT4_LCD_EN
.set SCSI_Out__4__MASK, 0x20
.set SCSI_Out__5__DM2, CYREG_PRT4_DM2
.set SCSI_Out__5__DR, CYREG_PRT4_DR
.set SCSI_Out__5__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__5__INTTYPE, CYREG_PICU4_INTTYPE4
.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
.set SCSI_Out__5__LCD_EN, CYREG_PRT4_LCD_EN
.set SCSI_Out__5__MASK, 0x10
.set SCSI_Out__6__DM2, CYREG_PRT0_DM2
.set SCSI_Out__6__DR, CYREG_PRT0_DR
.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__6__INTTYPE, CYREG_PICU0_INTTYPE7
.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__6__MASK, 0x80
.set SCSI_Out__7__DM2, CYREG_PRT0_DM2
.set SCSI_Out__7__DR, CYREG_PRT0_DR
.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__7__INTTYPE, CYREG_PICU0_INTTYPE6
.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__7__MASK, 0x40
.set SCSI_Out__8__DM2, CYREG_PRT0_DM2
.set SCSI_Out__8__DR, CYREG_PRT0_DR
.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__8__INTTYPE, CYREG_PICU0_INTTYPE3
.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__8__MASK, 0x08
.set SCSI_Out__9__DM2, CYREG_PRT0_DM2
.set SCSI_Out__9__DR, CYREG_PRT0_DR
.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__9__INTTYPE, CYREG_PICU0_INTTYPE2
.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__9__MASK, 0x04
.set SCSI_Out__ACK__DM2, CYREG_PRT6_DM2
.set SCSI_Out__ACK__DR, CYREG_PRT6_DR
.set SCSI_Out__ACK__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out__ACK__INTTYPE, CYREG_PICU6_INTTYPE0
.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_Out__ACK__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_Out__ACK__MASK, 0x01
.set SCSI_Out__ATN__DM2, CYREG_PRT15_DM2
.set SCSI_Out__ATN__DR, CYREG_PRT15_DR
.set SCSI_Out__ATN__INP_DIS, CYREG_PRT15_INP_DIS
+.set SCSI_Out__ATN__INTTYPE, CYREG_PICU15_INTTYPE4
.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
.set SCSI_Out__ATN__LCD_EN, CYREG_PRT15_LCD_EN
.set SCSI_Out__ATN__MASK, 0x10
.set SCSI_Out__BSY__DM2, CYREG_PRT6_DM2
.set SCSI_Out__BSY__DR, CYREG_PRT6_DR
.set SCSI_Out__BSY__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out__BSY__INTTYPE, CYREG_PICU6_INTTYPE1
.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_Out__BSY__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_Out__BSY__MASK, 0x02
.set SCSI_Out__CD__DM2, CYREG_PRT0_DM2
.set SCSI_Out__CD__DR, CYREG_PRT0_DR
.set SCSI_Out__CD__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__CD__INTTYPE, CYREG_PICU0_INTTYPE6
.set SCSI_Out__CD__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__CD__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__CD__MASK, 0x40
.set SCSI_Out__DBP_raw__DM2, CYREG_PRT15_DM2
.set SCSI_Out__DBP_raw__DR, CYREG_PRT15_DR
.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT15_INP_DIS
+.set SCSI_Out__DBP_raw__INTTYPE, CYREG_PICU15_INTTYPE5
.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT15_LCD_EN
.set SCSI_Out__DBP_raw__MASK, 0x20
.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2
.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR
.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__IO_raw__INTTYPE, CYREG_PICU0_INTTYPE2
.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__IO_raw__MASK, 0x04
.set SCSI_Out__MSG__DM2, CYREG_PRT4_DM2
.set SCSI_Out__MSG__DR, CYREG_PRT4_DR
.set SCSI_Out__MSG__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__MSG__INTTYPE, CYREG_PICU4_INTTYPE4
.set SCSI_Out__MSG__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
.set SCSI_Out__MSG__LCD_EN, CYREG_PRT4_LCD_EN
.set SCSI_Out__MSG__MASK, 0x10
.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2
.set SCSI_Out__REQ__DR, CYREG_PRT0_DR
.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__REQ__INTTYPE, CYREG_PICU0_INTTYPE3
.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__REQ__MASK, 0x08
.set SCSI_Out__RST__DM2, CYREG_PRT4_DM2
.set SCSI_Out__RST__DR, CYREG_PRT4_DR
.set SCSI_Out__RST__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__RST__INTTYPE, CYREG_PICU4_INTTYPE5
.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
.set SCSI_Out__RST__LCD_EN, CYREG_PRT4_LCD_EN
.set SCSI_Out__RST__MASK, 0x20
.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2
.set SCSI_Out__SEL__DR, CYREG_PRT0_DR
.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__SEL__INTTYPE, CYREG_PICU0_INTTYPE7
.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN
.set SCSI_Out__SEL__MASK, 0x80
.set SCSI_Out_DBx__0__DM2, CYREG_PRT5_DM2
.set SCSI_Out_DBx__0__DR, CYREG_PRT5_DR
.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__0__INTTYPE, CYREG_PICU5_INTTYPE1
.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN
.set SCSI_Out_DBx__0__MASK, 0x02
.set SCSI_Out_DBx__1__DM2, CYREG_PRT5_DM2
.set SCSI_Out_DBx__1__DR, CYREG_PRT5_DR
.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__1__INTTYPE, CYREG_PICU5_INTTYPE0
.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN
.set SCSI_Out_DBx__1__MASK, 0x01
.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2
.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR
.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__2__INTTYPE, CYREG_PICU6_INTTYPE5
.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_Out_DBx__2__MASK, 0x20
.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2
.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR
.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__3__INTTYPE, CYREG_PICU6_INTTYPE4
.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_Out_DBx__3__MASK, 0x10
.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2
.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR
.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__4__INTTYPE, CYREG_PICU2_INTTYPE7
.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN
.set SCSI_Out_DBx__4__MASK, 0x80
.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2
.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR
.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__5__INTTYPE, CYREG_PICU2_INTTYPE6
.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN
.set SCSI_Out_DBx__5__MASK, 0x40
.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2
.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR
.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__6__INTTYPE, CYREG_PICU2_INTTYPE3
.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
.set SCSI_Out_DBx__6__MASK, 0x08
.set SCSI_Out_DBx__7__DM2, CYREG_PRT2_DM2
.set SCSI_Out_DBx__7__DR, CYREG_PRT2_DR
.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__7__INTTYPE, CYREG_PICU2_INTTYPE2
.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN
.set SCSI_Out_DBx__7__MASK, 0x04
.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT5_DM2
.set SCSI_Out_DBx__DB0__DR, CYREG_PRT5_DR
.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__DB0__INTTYPE, CYREG_PICU5_INTTYPE1
.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN
.set SCSI_Out_DBx__DB0__MASK, 0x02
.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT5_DM2
.set SCSI_Out_DBx__DB1__DR, CYREG_PRT5_DR
.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__DB1__INTTYPE, CYREG_PICU5_INTTYPE0
.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN
.set SCSI_Out_DBx__DB1__MASK, 0x01
.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2
.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR
.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB2__INTTYPE, CYREG_PICU6_INTTYPE5
.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_Out_DBx__DB2__MASK, 0x20
.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2
.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR
.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB3__INTTYPE, CYREG_PICU6_INTTYPE4
.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_Out_DBx__DB3__MASK, 0x10
.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2
.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR
.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB4__INTTYPE, CYREG_PICU2_INTTYPE7
.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN
.set SCSI_Out_DBx__DB4__MASK, 0x80
.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2
.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR
.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB5__INTTYPE, CYREG_PICU2_INTTYPE6
.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN
.set SCSI_Out_DBx__DB5__MASK, 0x40
.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2
.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR
.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB6__INTTYPE, CYREG_PICU2_INTTYPE3
.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
.set SCSI_Out_DBx__DB6__MASK, 0x08
.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT2_DM2
.set SCSI_Out_DBx__DB7__DR, CYREG_PRT2_DR
.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB7__INTTYPE, CYREG_PICU2_INTTYPE2
.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN
.set SCSI_Out_DBx__DB7__MASK, 0x04
.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT2_SLW
/* SD_PULLUP */
+.set SD_PULLUP__0__INTTYPE, CYREG_PICU3_INTTYPE1
.set SD_PULLUP__0__MASK, 0x02
.set SD_PULLUP__0__PC, CYREG_PRT3_PC1
.set SD_PULLUP__0__PORT, 3
.set SD_PULLUP__0__SHIFT, 1
+.set SD_PULLUP__1__INTTYPE, CYREG_PICU3_INTTYPE2
.set SD_PULLUP__1__MASK, 0x04
.set SD_PULLUP__1__PC, CYREG_PRT3_PC2
.set SD_PULLUP__1__PORT, 3
.set SD_PULLUP__1__SHIFT, 2
+.set SD_PULLUP__2__INTTYPE, CYREG_PICU3_INTTYPE3
.set SD_PULLUP__2__MASK, 0x08
.set SD_PULLUP__2__PC, CYREG_PRT3_PC3
.set SD_PULLUP__2__PORT, 3
.set SD_PULLUP__2__SHIFT, 3
+.set SD_PULLUP__3__INTTYPE, CYREG_PICU3_INTTYPE4
.set SD_PULLUP__3__MASK, 0x10
.set SD_PULLUP__3__PC, CYREG_PRT3_PC4
.set SD_PULLUP__3__PORT, 3
.set SD_PULLUP__3__SHIFT, 4
+.set SD_PULLUP__4__INTTYPE, CYREG_PICU3_INTTYPE5
.set SD_PULLUP__4__MASK, 0x20
.set SD_PULLUP__4__PC, CYREG_PRT3_PC5
.set SD_PULLUP__4__PORT, 3
.set SD_PULLUP__DM2, CYREG_PRT3_DM2
.set SD_PULLUP__DR, CYREG_PRT3_DR
.set SD_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_PULLUP__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE
.set SD_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
.set SD_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN
.set SD_PULLUP__MASK, 0x3E
.set CyBtldr_USBFS, CYDEV_BOOTLOADER_IO_COMP_USBFS
.set CYDEV_BOOTLOADER_IO_COMP, CYDEV_BOOTLOADER_IO_COMP_USBFS
.set CYDEV_CHIP_DIE_LEOPARD, 1
-.set CYDEV_CHIP_DIE_PANTHER, 6
-.set CYDEV_CHIP_DIE_PSOC4A, 3
-.set CYDEV_CHIP_DIE_PSOC5LP, 5
+.set CYDEV_CHIP_DIE_PANTHER, 18
+.set CYDEV_CHIP_DIE_PSOC4A, 10
+.set CYDEV_CHIP_DIE_PSOC5LP, 17
+.set CYDEV_CHIP_DIE_TMA4, 2
.set CYDEV_CHIP_DIE_UNKNOWN, 0
.set CYDEV_CHIP_FAMILY_PSOC3, 1
.set CYDEV_CHIP_FAMILY_PSOC4, 2
.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5
.set CYDEV_CHIP_JTAG_ID, 0x2E133069
.set CYDEV_CHIP_MEMBER_3A, 1
-.set CYDEV_CHIP_MEMBER_4A, 3
-.set CYDEV_CHIP_MEMBER_4D, 2
-.set CYDEV_CHIP_MEMBER_4F, 4
-.set CYDEV_CHIP_MEMBER_5A, 6
-.set CYDEV_CHIP_MEMBER_5B, 5
+.set CYDEV_CHIP_MEMBER_4A, 10
+.set CYDEV_CHIP_MEMBER_4C, 15
+.set CYDEV_CHIP_MEMBER_4D, 6
+.set CYDEV_CHIP_MEMBER_4E, 4
+.set CYDEV_CHIP_MEMBER_4F, 11
+.set CYDEV_CHIP_MEMBER_4G, 2
+.set CYDEV_CHIP_MEMBER_4H, 9
+.set CYDEV_CHIP_MEMBER_4I, 14
+.set CYDEV_CHIP_MEMBER_4J, 7
+.set CYDEV_CHIP_MEMBER_4K, 8
+.set CYDEV_CHIP_MEMBER_4L, 13
+.set CYDEV_CHIP_MEMBER_4M, 12
+.set CYDEV_CHIP_MEMBER_4N, 5
+.set CYDEV_CHIP_MEMBER_4U, 3
+.set CYDEV_CHIP_MEMBER_5A, 17
+.set CYDEV_CHIP_MEMBER_5B, 16
.set CYDEV_CHIP_MEMBER_UNKNOWN, 0
.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B
.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
+.set CYDEV_CHIP_REV_TMA4_ES, 17
+.set CYDEV_CHIP_REV_TMA4_ES2, 33
+.set CYDEV_CHIP_REV_TMA4_PRODUCTION, 17
.set CYDEV_CHIP_REVISION_3A_ES1, 0
.set CYDEV_CHIP_REVISION_3A_ES2, 1
.set CYDEV_CHIP_REVISION_3A_ES3, 3
.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
.set CYDEV_CHIP_REVISION_4A_ES0, 17
.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
+.set CYDEV_CHIP_REVISION_4C_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA, 0
+.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256K, 0
+.set CYDEV_CHIP_REVISION_4G_ES, 17
+.set CYDEV_CHIP_REVISION_4G_ES2, 33
+.set CYDEV_CHIP_REVISION_4G_PRODUCTION, 17
+.set CYDEV_CHIP_REVISION_4H_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4I_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4J_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4K_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4N_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_5A_ES0, 0
.set CYDEV_CHIP_REVISION_5A_ES1, 1
.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
.set CYDEV_CONFIGURATION_COMPRESSED, 1
.set CYDEV_CONFIGURATION_DMA, 0
-.set CYDEV_CONFIGURATION_ECC, 0
+.set CYDEV_CONFIGURATION_ECC, 1
.set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED
.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED
.set CYDEV_HEAP_SIZE, 0x0800
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1
.set CYDEV_INTR_RISING, 0x00000000
+.set CYDEV_IS_EXPORTING_CODE, 0
+.set CYDEV_IS_IMPORTING_CODE, 0
.set CYDEV_PROJ_TYPE, 1
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1
+.set CYDEV_PROJ_TYPE_LAUNCHER, 5
.set CYDEV_PROJ_TYPE_LOADABLE, 2
+.set CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER, 4
.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3
.set CYDEV_PROJ_TYPE_STANDARD, 0
.set CYDEV_PROTECTION_ENABLE, 0
INCLUDE cydeviceiar_trm.inc
/* LED */
+LED__0__INTTYPE EQU CYREG_PICU0_INTTYPE1
LED__0__MASK EQU 0x02
LED__0__PC EQU CYREG_PRT0_PC1
LED__0__PORT EQU 0
LED__DM2 EQU CYREG_PRT0_DM2
LED__DR EQU CYREG_PRT0_DR
LED__INP_DIS EQU CYREG_PRT0_INP_DIS
+LED__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE
LED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
LED__LCD_EN EQU CYREG_PRT0_LCD_EN
LED__MASK EQU 0x02
USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* USBFS_Dm */
+USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7
USBFS_Dm__0__MASK EQU 0x80
USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
USBFS_Dm__0__PORT EQU 15
USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
USBFS_Dm__DR EQU CYREG_PRT15_DR
USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
USBFS_Dm__MASK EQU 0x80
USBFS_Dm__SLW EQU CYREG_PRT15_SLW
/* USBFS_Dp */
+USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6
USBFS_Dp__0__MASK EQU 0x40
USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
USBFS_Dp__0__PORT EQU 15
USBFS_Dp__DR EQU CYREG_PRT15_DR
USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
+USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
USBFS_Dp__MASK EQU 0x40
SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2
SCSI_Out__0__DR EQU CYREG_PRT15_DR
SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__0__INTTYPE EQU CYREG_PICU15_INTTYPE5
SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN
SCSI_Out__0__MASK EQU 0x20
SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2
SCSI_Out__1__DR EQU CYREG_PRT15_DR
SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__1__INTTYPE EQU CYREG_PICU15_INTTYPE4
SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN
SCSI_Out__1__MASK EQU 0x10
SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2
SCSI_Out__2__DR EQU CYREG_PRT6_DR
SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__2__INTTYPE EQU CYREG_PICU6_INTTYPE1
SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out__2__MASK EQU 0x02
SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2
SCSI_Out__3__DR EQU CYREG_PRT6_DR
SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__3__INTTYPE EQU CYREG_PICU6_INTTYPE0
SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out__3__MASK EQU 0x01
SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__4__DR EQU CYREG_PRT4_DR
SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__4__INTTYPE EQU CYREG_PICU4_INTTYPE5
SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__4__MASK EQU 0x20
SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__5__DR EQU CYREG_PRT4_DR
SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__5__INTTYPE EQU CYREG_PICU4_INTTYPE4
SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__5__MASK EQU 0x10
SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__6__DR EQU CYREG_PRT0_DR
SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__6__INTTYPE EQU CYREG_PICU0_INTTYPE7
SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__6__MASK EQU 0x80
SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__7__DR EQU CYREG_PRT0_DR
SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__7__INTTYPE EQU CYREG_PICU0_INTTYPE6
SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__7__MASK EQU 0x40
SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__8__DR EQU CYREG_PRT0_DR
SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__8__INTTYPE EQU CYREG_PICU0_INTTYPE3
SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__8__MASK EQU 0x08
SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__9__DR EQU CYREG_PRT0_DR
SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__9__INTTYPE EQU CYREG_PICU0_INTTYPE2
SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__9__MASK EQU 0x04
SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2
SCSI_Out__ACK__DR EQU CYREG_PRT6_DR
SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE0
SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out__ACK__MASK EQU 0x01
SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2
SCSI_Out__ATN__DR EQU CYREG_PRT15_DR
SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__ATN__INTTYPE EQU CYREG_PICU15_INTTYPE4
SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN
SCSI_Out__ATN__MASK EQU 0x10
SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2
SCSI_Out__BSY__DR EQU CYREG_PRT6_DR
SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE1
SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out__BSY__MASK EQU 0x02
SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__CD__DR EQU CYREG_PRT0_DR
SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__CD__INTTYPE EQU CYREG_PICU0_INTTYPE6
SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__CD__MASK EQU 0x40
SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2
SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR
SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU15_INTTYPE5
SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN
SCSI_Out__DBP_raw__MASK EQU 0x20
SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR
SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU0_INTTYPE2
SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__IO_raw__MASK EQU 0x04
SCSI_Out__MSG__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__MSG__DR EQU CYREG_PRT4_DR
SCSI_Out__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__MSG__INTTYPE EQU CYREG_PICU4_INTTYPE4
SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__MSG__MASK EQU 0x10
SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__REQ__DR EQU CYREG_PRT0_DR
SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE3
SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__REQ__MASK EQU 0x08
SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__RST__DR EQU CYREG_PRT4_DR
SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__RST__INTTYPE EQU CYREG_PICU4_INTTYPE5
SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__RST__MASK EQU 0x20
SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE7
SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__SEL__MASK EQU 0x80
SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU5_INTTYPE1
SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_Out_DBx__0__MASK EQU 0x02
SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU5_INTTYPE0
SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_Out_DBx__1__MASK EQU 0x01
SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE5
SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out_DBx__2__MASK EQU 0x20
SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE4
SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out_DBx__3__MASK EQU 0x10
SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE7
SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__4__MASK EQU 0x80
SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE6
SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__5__MASK EQU 0x40
SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE3
SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__6__MASK EQU 0x08
SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE2
SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__7__MASK EQU 0x04
SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU5_INTTYPE1
SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_Out_DBx__DB0__MASK EQU 0x02
SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU5_INTTYPE0
SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_Out_DBx__DB1__MASK EQU 0x01
SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE5
SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out_DBx__DB2__MASK EQU 0x20
SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE4
SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out_DBx__DB3__MASK EQU 0x10
SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE7
SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__DB4__MASK EQU 0x80
SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE6
SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__DB5__MASK EQU 0x40
SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE3
SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__DB6__MASK EQU 0x08
SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE2
SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__DB7__MASK EQU 0x04
SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
/* SD_PULLUP */
+SD_PULLUP__0__INTTYPE EQU CYREG_PICU3_INTTYPE1
SD_PULLUP__0__MASK EQU 0x02
SD_PULLUP__0__PC EQU CYREG_PRT3_PC1
SD_PULLUP__0__PORT EQU 3
SD_PULLUP__0__SHIFT EQU 1
+SD_PULLUP__1__INTTYPE EQU CYREG_PICU3_INTTYPE2
SD_PULLUP__1__MASK EQU 0x04
SD_PULLUP__1__PC EQU CYREG_PRT3_PC2
SD_PULLUP__1__PORT EQU 3
SD_PULLUP__1__SHIFT EQU 2
+SD_PULLUP__2__INTTYPE EQU CYREG_PICU3_INTTYPE3
SD_PULLUP__2__MASK EQU 0x08
SD_PULLUP__2__PC EQU CYREG_PRT3_PC3
SD_PULLUP__2__PORT EQU 3
SD_PULLUP__2__SHIFT EQU 3
+SD_PULLUP__3__INTTYPE EQU CYREG_PICU3_INTTYPE4
SD_PULLUP__3__MASK EQU 0x10
SD_PULLUP__3__PC EQU CYREG_PRT3_PC4
SD_PULLUP__3__PORT EQU 3
SD_PULLUP__3__SHIFT EQU 4
+SD_PULLUP__4__INTTYPE EQU CYREG_PICU3_INTTYPE5
SD_PULLUP__4__MASK EQU 0x20
SD_PULLUP__4__PC EQU CYREG_PRT3_PC5
SD_PULLUP__4__PORT EQU 3
SD_PULLUP__DM2 EQU CYREG_PRT3_DM2
SD_PULLUP__DR EQU CYREG_PRT3_DR
SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_PULLUP__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN
SD_PULLUP__MASK EQU 0x3E
CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 6
-CYDEV_CHIP_DIE_PSOC4A EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 5
+CYDEV_CHIP_DIE_PANTHER EQU 18
+CYDEV_CHIP_DIE_PSOC4A EQU 10
+CYDEV_CHIP_DIE_PSOC5LP EQU 17
+CYDEV_CHIP_DIE_TMA4 EQU 2
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
CYDEV_CHIP_JTAG_ID EQU 0x2E133069
CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 3
-CYDEV_CHIP_MEMBER_4D EQU 2
-CYDEV_CHIP_MEMBER_4F EQU 4
-CYDEV_CHIP_MEMBER_5A EQU 6
-CYDEV_CHIP_MEMBER_5B EQU 5
+CYDEV_CHIP_MEMBER_4A EQU 10
+CYDEV_CHIP_MEMBER_4C EQU 15
+CYDEV_CHIP_MEMBER_4D EQU 6
+CYDEV_CHIP_MEMBER_4E EQU 4
+CYDEV_CHIP_MEMBER_4F EQU 11
+CYDEV_CHIP_MEMBER_4G EQU 2
+CYDEV_CHIP_MEMBER_4H EQU 9
+CYDEV_CHIP_MEMBER_4I EQU 14
+CYDEV_CHIP_MEMBER_4J EQU 7
+CYDEV_CHIP_MEMBER_4K EQU 8
+CYDEV_CHIP_MEMBER_4L EQU 13
+CYDEV_CHIP_MEMBER_4M EQU 12
+CYDEV_CHIP_MEMBER_4N EQU 5
+CYDEV_CHIP_MEMBER_4U EQU 3
+CYDEV_CHIP_MEMBER_5A EQU 17
+CYDEV_CHIP_MEMBER_5B EQU 16
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
+CYDEV_CHIP_REV_TMA4_ES EQU 17
+CYDEV_CHIP_REV_TMA4_ES2 EQU 33
+CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
+CYDEV_CHIP_REVISION_4G_ES EQU 17
+CYDEV_CHIP_REVISION_4G_ES2 EQU 33
+CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_DMA EQU 0
-CYDEV_CONFIGURATION_ECC EQU 0
+CYDEV_CONFIGURATION_ECC EQU 1
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_HEAP_SIZE EQU 0x0800
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
CYDEV_INTR_RISING EQU 0x00000000
+CYDEV_IS_EXPORTING_CODE EQU 0
+CYDEV_IS_IMPORTING_CODE EQU 0
CYDEV_PROJ_TYPE EQU 1
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
+CYDEV_PROJ_TYPE_LAUNCHER EQU 5
CYDEV_PROJ_TYPE_LOADABLE EQU 2
+CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_PROTECTION_ENABLE EQU 0
GET cydevicerv_trm.inc
; LED
+LED__0__INTTYPE EQU CYREG_PICU0_INTTYPE1
LED__0__MASK EQU 0x02
LED__0__PC EQU CYREG_PRT0_PC1
LED__0__PORT EQU 0
LED__DM2 EQU CYREG_PRT0_DM2
LED__DR EQU CYREG_PRT0_DR
LED__INP_DIS EQU CYREG_PRT0_INP_DIS
+LED__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE
LED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
LED__LCD_EN EQU CYREG_PRT0_LCD_EN
LED__MASK EQU 0x02
USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; USBFS_Dm
+USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7
USBFS_Dm__0__MASK EQU 0x80
USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
USBFS_Dm__0__PORT EQU 15
USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
USBFS_Dm__DR EQU CYREG_PRT15_DR
USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
USBFS_Dm__MASK EQU 0x80
USBFS_Dm__SLW EQU CYREG_PRT15_SLW
; USBFS_Dp
+USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6
USBFS_Dp__0__MASK EQU 0x40
USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
USBFS_Dp__0__PORT EQU 15
USBFS_Dp__DR EQU CYREG_PRT15_DR
USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
+USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE
USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
USBFS_Dp__MASK EQU 0x40
SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2
SCSI_Out__0__DR EQU CYREG_PRT15_DR
SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__0__INTTYPE EQU CYREG_PICU15_INTTYPE5
SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN
SCSI_Out__0__MASK EQU 0x20
SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2
SCSI_Out__1__DR EQU CYREG_PRT15_DR
SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__1__INTTYPE EQU CYREG_PICU15_INTTYPE4
SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN
SCSI_Out__1__MASK EQU 0x10
SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2
SCSI_Out__2__DR EQU CYREG_PRT6_DR
SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__2__INTTYPE EQU CYREG_PICU6_INTTYPE1
SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out__2__MASK EQU 0x02
SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2
SCSI_Out__3__DR EQU CYREG_PRT6_DR
SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__3__INTTYPE EQU CYREG_PICU6_INTTYPE0
SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out__3__MASK EQU 0x01
SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__4__DR EQU CYREG_PRT4_DR
SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__4__INTTYPE EQU CYREG_PICU4_INTTYPE5
SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__4__MASK EQU 0x20
SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__5__DR EQU CYREG_PRT4_DR
SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__5__INTTYPE EQU CYREG_PICU4_INTTYPE4
SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__5__MASK EQU 0x10
SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__6__DR EQU CYREG_PRT0_DR
SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__6__INTTYPE EQU CYREG_PICU0_INTTYPE7
SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__6__MASK EQU 0x80
SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__7__DR EQU CYREG_PRT0_DR
SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__7__INTTYPE EQU CYREG_PICU0_INTTYPE6
SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__7__MASK EQU 0x40
SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__8__DR EQU CYREG_PRT0_DR
SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__8__INTTYPE EQU CYREG_PICU0_INTTYPE3
SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__8__MASK EQU 0x08
SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__9__DR EQU CYREG_PRT0_DR
SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__9__INTTYPE EQU CYREG_PICU0_INTTYPE2
SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__9__MASK EQU 0x04
SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2
SCSI_Out__ACK__DR EQU CYREG_PRT6_DR
SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__ACK__INTTYPE EQU CYREG_PICU6_INTTYPE0
SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out__ACK__MASK EQU 0x01
SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2
SCSI_Out__ATN__DR EQU CYREG_PRT15_DR
SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__ATN__INTTYPE EQU CYREG_PICU15_INTTYPE4
SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN
SCSI_Out__ATN__MASK EQU 0x10
SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2
SCSI_Out__BSY__DR EQU CYREG_PRT6_DR
SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__BSY__INTTYPE EQU CYREG_PICU6_INTTYPE1
SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out__BSY__MASK EQU 0x02
SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__CD__DR EQU CYREG_PRT0_DR
SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__CD__INTTYPE EQU CYREG_PICU0_INTTYPE6
SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__CD__MASK EQU 0x40
SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2
SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR
SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU15_INTTYPE5
SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN
SCSI_Out__DBP_raw__MASK EQU 0x20
SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR
SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU0_INTTYPE2
SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__IO_raw__MASK EQU 0x04
SCSI_Out__MSG__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__MSG__DR EQU CYREG_PRT4_DR
SCSI_Out__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__MSG__INTTYPE EQU CYREG_PICU4_INTTYPE4
SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__MSG__MASK EQU 0x10
SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__REQ__DR EQU CYREG_PRT0_DR
SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__REQ__INTTYPE EQU CYREG_PICU0_INTTYPE3
SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__REQ__MASK EQU 0x08
SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2
SCSI_Out__RST__DR EQU CYREG_PRT4_DR
SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__RST__INTTYPE EQU CYREG_PICU4_INTTYPE5
SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
SCSI_Out__RST__MASK EQU 0x20
SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE7
SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
SCSI_Out__SEL__MASK EQU 0x80
SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU5_INTTYPE1
SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_Out_DBx__0__MASK EQU 0x02
SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU5_INTTYPE0
SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_Out_DBx__1__MASK EQU 0x01
SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU6_INTTYPE5
SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out_DBx__2__MASK EQU 0x20
SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU6_INTTYPE4
SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out_DBx__3__MASK EQU 0x10
SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE7
SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__4__MASK EQU 0x80
SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE6
SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__5__MASK EQU 0x40
SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE3
SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__6__MASK EQU 0x08
SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU2_INTTYPE2
SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__7__MASK EQU 0x04
SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU5_INTTYPE1
SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_Out_DBx__DB0__MASK EQU 0x02
SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU5_INTTYPE0
SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_Out_DBx__DB1__MASK EQU 0x01
SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU6_INTTYPE5
SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out_DBx__DB2__MASK EQU 0x20
SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU6_INTTYPE4
SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_Out_DBx__DB3__MASK EQU 0x10
SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE7
SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__DB4__MASK EQU 0x80
SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE6
SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__DB5__MASK EQU 0x40
SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE3
SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__DB6__MASK EQU 0x08
SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU2_INTTYPE2
SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
SCSI_Out_DBx__DB7__MASK EQU 0x04
SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
; SD_PULLUP
+SD_PULLUP__0__INTTYPE EQU CYREG_PICU3_INTTYPE1
SD_PULLUP__0__MASK EQU 0x02
SD_PULLUP__0__PC EQU CYREG_PRT3_PC1
SD_PULLUP__0__PORT EQU 3
SD_PULLUP__0__SHIFT EQU 1
+SD_PULLUP__1__INTTYPE EQU CYREG_PICU3_INTTYPE2
SD_PULLUP__1__MASK EQU 0x04
SD_PULLUP__1__PC EQU CYREG_PRT3_PC2
SD_PULLUP__1__PORT EQU 3
SD_PULLUP__1__SHIFT EQU 2
+SD_PULLUP__2__INTTYPE EQU CYREG_PICU3_INTTYPE3
SD_PULLUP__2__MASK EQU 0x08
SD_PULLUP__2__PC EQU CYREG_PRT3_PC3
SD_PULLUP__2__PORT EQU 3
SD_PULLUP__2__SHIFT EQU 3
+SD_PULLUP__3__INTTYPE EQU CYREG_PICU3_INTTYPE4
SD_PULLUP__3__MASK EQU 0x10
SD_PULLUP__3__PC EQU CYREG_PRT3_PC4
SD_PULLUP__3__PORT EQU 3
SD_PULLUP__3__SHIFT EQU 4
+SD_PULLUP__4__INTTYPE EQU CYREG_PICU3_INTTYPE5
SD_PULLUP__4__MASK EQU 0x20
SD_PULLUP__4__PC EQU CYREG_PRT3_PC5
SD_PULLUP__4__PORT EQU 3
SD_PULLUP__DM2 EQU CYREG_PRT3_DM2
SD_PULLUP__DR EQU CYREG_PRT3_DR
SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_PULLUP__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE
SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN
SD_PULLUP__MASK EQU 0x3E
CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 6
-CYDEV_CHIP_DIE_PSOC4A EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 5
+CYDEV_CHIP_DIE_PANTHER EQU 18
+CYDEV_CHIP_DIE_PSOC4A EQU 10
+CYDEV_CHIP_DIE_PSOC5LP EQU 17
+CYDEV_CHIP_DIE_TMA4 EQU 2
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
CYDEV_CHIP_JTAG_ID EQU 0x2E133069
CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 3
-CYDEV_CHIP_MEMBER_4D EQU 2
-CYDEV_CHIP_MEMBER_4F EQU 4
-CYDEV_CHIP_MEMBER_5A EQU 6
-CYDEV_CHIP_MEMBER_5B EQU 5
+CYDEV_CHIP_MEMBER_4A EQU 10
+CYDEV_CHIP_MEMBER_4C EQU 15
+CYDEV_CHIP_MEMBER_4D EQU 6
+CYDEV_CHIP_MEMBER_4E EQU 4
+CYDEV_CHIP_MEMBER_4F EQU 11
+CYDEV_CHIP_MEMBER_4G EQU 2
+CYDEV_CHIP_MEMBER_4H EQU 9
+CYDEV_CHIP_MEMBER_4I EQU 14
+CYDEV_CHIP_MEMBER_4J EQU 7
+CYDEV_CHIP_MEMBER_4K EQU 8
+CYDEV_CHIP_MEMBER_4L EQU 13
+CYDEV_CHIP_MEMBER_4M EQU 12
+CYDEV_CHIP_MEMBER_4N EQU 5
+CYDEV_CHIP_MEMBER_4U EQU 3
+CYDEV_CHIP_MEMBER_5A EQU 17
+CYDEV_CHIP_MEMBER_5B EQU 16
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
+CYDEV_CHIP_REV_TMA4_ES EQU 17
+CYDEV_CHIP_REV_TMA4_ES2 EQU 33
+CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4C_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0
+CYDEV_CHIP_REVISION_4G_ES EQU 17
+CYDEV_CHIP_REVISION_4G_ES2 EQU 33
+CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_DMA EQU 0
-CYDEV_CONFIGURATION_ECC EQU 0
+CYDEV_CONFIGURATION_ECC EQU 1
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_HEAP_SIZE EQU 0x0800
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
CYDEV_INTR_RISING EQU 0x00000000
+CYDEV_IS_EXPORTING_CODE EQU 0
+CYDEV_IS_IMPORTING_CODE EQU 0
CYDEV_PROJ_TYPE EQU 1
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
+CYDEV_PROJ_TYPE_LAUNCHER EQU 5
CYDEV_PROJ_TYPE_LOADABLE EQU 2
+CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_PROTECTION_ENABLE EQU 0
/*******************************************************************************
-* FILENAME: cymetadata.c
+* File Name: cymetadata.c
*
-* PSoC Creator 3.1
+* PSoC Creator 3.3
*
-* DESCRIPTION:
+* Description:
* This file defines all extra memory spaces that need to be included.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************
- * File Name: project.h
- * PSoC Creator 3.1
- *
- * Description:
- * This file is automatically generated by PSoC Creator and should not
- * be edited by hand.
- *
- *
- ********************************************************************************
- * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
- * You may use this file only in accordance with the license, terms, conditions,
- * disclaimers, and limitations in the end user license agreement accompanying
- * the software package with which this file was provided.
- ********************************************************************************/
+* File Name: project.h
+*
+* PSoC Creator 3.3
+*
+* Description:
+* It contains references to all generated header files and should not be modified.
+* This file is automatically generated by PSoC Creator.
+*
+********************************************************************************
+* Copyright (c) 2007-2015 Cypress Semiconductor. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+********************************************************************************/
-#include <cyfitter_cfg.h>
-#include <cydevice.h>
-#include <cydevice_trm.h>
-#include <cyfitter.h>
-#include <cydisabledsheets.h>
-#include <USBFS.h>
-#include <USBFS_audio.h>
-#include <USBFS_cdc.h>
-#include <USBFS_hid.h>
-#include <USBFS_midi.h>
-#include <USBFS_pvt.h>
-#include <BL.h>
-#include <BL_PVT.h>
-#include <SCSI_Out_DBx_aliases.h>
-#include <SCSI_Out_aliases.h>
-#include <SD_PULLUP_aliases.h>
-#include <SD_PULLUP.h>
-#include <LED_aliases.h>
-#include <LED.h>
-#include <USBFS_Dm_aliases.h>
-#include <USBFS_Dm.h>
-#include <USBFS_Dp_aliases.h>
-#include <USBFS_Dp.h>
-#include <core_cm3_psoc5.h>
-#include <core_cm3.h>
-#include <CyDmac.h>
-#include <CyFlash.h>
-#include <CyLib.h>
-#include <cypins.h>
-#include <cyPm.h>
-#include <CySpc.h>
-#include <cytypes.h>
-#include <core_cmFunc.h>
-#include <core_cmInstr.h>
+#include "cyfitter_cfg.h"
+#include "cydevice.h"
+#include "cydevice_trm.h"
+#include "cyfitter.h"
+#include "cydisabledsheets.h"
+#include "USBFS.h"
+#include "USBFS_audio.h"
+#include "USBFS_cdc.h"
+#include "USBFS_hid.h"
+#include "USBFS_midi.h"
+#include "USBFS_pvt.h"
+#include "BL.h"
+#include "BL_PVT.h"
+#include "SCSI_Out_DBx_aliases.h"
+#include "SCSI_Out_aliases.h"
+#include "SD_PULLUP_aliases.h"
+#include "SD_PULLUP.h"
+#include "LED_aliases.h"
+#include "LED.h"
+#include "USBFS_Dm_aliases.h"
+#include "USBFS_Dm.h"
+#include "USBFS_Dp_aliases.h"
+#include "USBFS_Dp.h"
+#include "core_cm3_psoc5.h"
+#include "core_cm3.h"
+#include "CyDmac.h"
+#include "CyFlash.h"
+#include "CyLib.h"
+#include "cypins.h"
+#include "cyPm.h"
+#include "CySpc.h"
+#include "cytypes.h"
+#include "core_cmFunc.h"
+#include "core_cmInstr.h"
/*[]*/
<?xml version="1.0" encoding="utf-8"?>
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
- <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SD_PULLUP" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="LED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
- <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="ZeroTerminal_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="ZeroTerminal_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0">
+ <block name="SD_PULLUP" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="LED" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true" hidden="false">
+ <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="ZeroTerminal_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="ZeroTerminal_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0" hidden="false">
<field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />
<field name="fsusbio_pd_n" from="1" to="1" access="RW" resetVal="" desc="" />
<field name="fsusbio_pd_pullup_n" from="2" to="2" access="RW" resetVal="" desc="" />
</register>
- <register name="USBFS_PM_ACT_CFG" address="0x400043A5" bitWidth="8" desc="Active Power Mode Configuration Register" />
- <register name="USBFS_PM_STBY_CFG" address="0x400043B5" bitWidth="8" desc="Standby Power Mode Configuration Register" />
- <register name="USBFS_PRT.PS" address="0x400051F1" bitWidth="8" desc="Port Pin State Register">
+ <register name="USBFS_PM_ACT_CFG" address="0x400043A5" bitWidth="8" desc="Active Power Mode Configuration Register" hidden="false" />
+ <register name="USBFS_PM_STBY_CFG" address="0x400043B5" bitWidth="8" desc="Standby Power Mode Configuration Register" hidden="false" />
+ <register name="USBFS_PRT.PS" address="0x400051F1" bitWidth="8" desc="Port Pin State Register" hidden="false">
<field name="PinState_DP" from="6" to="6" access="R" resetVal="" desc="" />
<field name="PinState_DM" from="7" to="7" access="R" resetVal="" desc="" />
</register>
- <register name="USBFS_PRT_DM0" address="0x400051F2" bitWidth="8" desc="Port Drive Mode Register">
+ <register name="USBFS_PRT_DM0" address="0x400051F2" bitWidth="8" desc="Port Drive Mode Register" hidden="false">
<field name="DriveMode_DP" from="6" to="6" access="RW" resetVal="" desc="" />
<field name="DriveMode_DM" from="7" to="7" access="RW" resetVal="" desc="" />
</register>
- <register name="USBFS_PRT_DM1" address="0x400051F3" bitWidth="8" desc="Port Drive Mode Register">
+ <register name="USBFS_PRT_DM1" address="0x400051F3" bitWidth="8" desc="Port Drive Mode Register" hidden="false">
<field name="PullUp_en_DP" from="6" to="6" access="RW" resetVal="" desc="" />
<field name="PullUp_en_DM" from="7" to="7" access="RW" resetVal="" desc="" />
</register>
- <register name="USBFS_PRT.INP_DIS" address="0x400051F8" bitWidth="8" desc="Input buffer disable override">
+ <register name="USBFS_PRT.INP_DIS" address="0x400051F8" bitWidth="8" desc="Input buffer disable override" hidden="false">
<field name="seinput_dis_dp" from="6" to="6" access="RW" resetVal="" desc="" />
<field name="seinput_dis_dm" from="7" to="7" access="RW" resetVal="" desc="" />
</register>
- <register name="USBFS_EP0_DR0" address="0x40006000" bitWidth="8" desc="bmRequestType" />
- <register name="USBFS_EP0_DR1" address="0x40006001" bitWidth="8" desc="bRequest" />
- <register name="USBFS_EP0_DR2" address="0x40006002" bitWidth="8" desc="wValueLo" />
- <register name="USBFS_EP0_DR3" address="0x40006003" bitWidth="8" desc="wValueHi" />
- <register name="USBFS_EP0_DR4" address="0x40006004" bitWidth="8" desc="wIndexLo" />
- <register name="USBFS_EP0_DR5" address="0x40006005" bitWidth="8" desc="wIndexHi" />
- <register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" />
- <register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" />
- <register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0">
+ <register name="USBFS_EP0_DR0" address="0x40006000" bitWidth="8" desc="bmRequestType" hidden="false" />
+ <register name="USBFS_EP0_DR1" address="0x40006001" bitWidth="8" desc="bRequest" hidden="false" />
+ <register name="USBFS_EP0_DR2" address="0x40006002" bitWidth="8" desc="wValueLo" hidden="false" />
+ <register name="USBFS_EP0_DR3" address="0x40006003" bitWidth="8" desc="wValueHi" hidden="false" />
+ <register name="USBFS_EP0_DR4" address="0x40006004" bitWidth="8" desc="wIndexLo" hidden="false" />
+ <register name="USBFS_EP0_DR5" address="0x40006005" bitWidth="8" desc="wIndexHi" hidden="false" />
+ <register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" hidden="false" />
+ <register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" hidden="false" />
+ <register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0" hidden="false">
<field name="device_address" from="6" to="0" access="R" resetVal="" desc="" />
<field name="usb_enable" from="7" to="7" access="RW" resetVal="" desc="" />
</register>
- <register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1">
+ <register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1" hidden="false">
<field name="reg_enable" from="0" to="0" access="RW" resetVal="" desc="" />
<field name="enable_lock" from="1" to="1" access="RW" resetVal="" desc="" />
<field name="bus_activity" from="2" to="2" access="RW" resetVal="" desc="" />
<field name="trim_offset_msb" from="3" to="3" access="RW" resetVal="" desc="" />
</register>
- <register name="USBFS_SIE_EP1_CR0" address="0x4000600E" bitWidth="8" desc="The Endpoint1 Control Register" />
- <register name="USBFS_USBIO_CR0" address="0x40006010" bitWidth="8" desc="USBIO Control Register 0">
+ <register name="USBFS_SIE_EP1_CR0" address="0x4000600E" bitWidth="8" desc="The Endpoint1 Control Register" hidden="false" />
+ <register name="USBFS_USBIO_CR0" address="0x40006010" bitWidth="8" desc="USBIO Control Register 0" hidden="false">
<field name="rd" from="0" to="0" access="R" resetVal="" desc="" />
<field name="td" from="5" to="5" access="RW" resetVal="" desc="" />
<field name="tse0" from="6" to="6" access="RW" resetVal="" desc="" />
<field name="ten" from="7" to="7" access="RW" resetVal="" desc="" />
</register>
- <register name="USBFS_USBIO_CR1" address="0x40006012" bitWidth="8" desc="USBIO Control Register 1">
+ <register name="USBFS_USBIO_CR1" address="0x40006012" bitWidth="8" desc="USBIO Control Register 1" hidden="false">
<field name="dmo" from="0" to="0" access="R" resetVal="" desc="" />
<field name="dpo" from="1" to="1" access="R" resetVal="" desc="" />
<field name="usbpuen" from="2" to="2" access="RW" resetVal="" desc="" />
<field name="iomode" from="5" to="5" access="RW" resetVal="" desc="" />
</register>
- <register name="USBFS_SIE_EP2_CR0" address="0x4000601E" bitWidth="8" desc="The Endpoint2 Control Register" />
- <register name="USBFS_SIE_EP3_CR0" address="0x4000602E" bitWidth="8" desc="The Endpoint3 Control Register" />
- <register name="USBFS_SIE_EP4_CR0" address="0x4000603E" bitWidth="8" desc="The Endpoint4 Control Register" />
- <register name="USBFS_SIE_EP5_CR0" address="0x4000604E" bitWidth="8" desc="The Endpoint5 Control Register" />
- <register name="USBFS_SIE_EP6_CR0" address="0x4000605E" bitWidth="8" desc="The Endpoint6 Control Register" />
- <register name="USBFS_SIE_EP7_CR0" address="0x4000606E" bitWidth="8" desc="The Endpoint7 Control Register" />
- <register name="USBFS_SIE_EP8_CR0" address="0x4000607E" bitWidth="8" desc="The Endpoint8 Control Register" />
- <register name="USBFS_BUF_SIZE" address="0x4000608C" bitWidth="8" desc="Dedicated Endpoint Buffer Size Register" />
- <register name="USBFS_EP_ACTIVE" address="0x4000608E" bitWidth="8" desc="Endpoint Active Indication Register" />
- <register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />
- <register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />
+ <register name="USBFS_SIE_EP2_CR0" address="0x4000601E" bitWidth="8" desc="The Endpoint2 Control Register" hidden="false" />
+ <register name="USBFS_SIE_EP3_CR0" address="0x4000602E" bitWidth="8" desc="The Endpoint3 Control Register" hidden="false" />
+ <register name="USBFS_SIE_EP4_CR0" address="0x4000603E" bitWidth="8" desc="The Endpoint4 Control Register" hidden="false" />
+ <register name="USBFS_SIE_EP5_CR0" address="0x4000604E" bitWidth="8" desc="The Endpoint5 Control Register" hidden="false" />
+ <register name="USBFS_SIE_EP6_CR0" address="0x4000605E" bitWidth="8" desc="The Endpoint6 Control Register" hidden="false" />
+ <register name="USBFS_SIE_EP7_CR0" address="0x4000606E" bitWidth="8" desc="The Endpoint7 Control Register" hidden="false" />
+ <register name="USBFS_SIE_EP8_CR0" address="0x4000607E" bitWidth="8" desc="The Endpoint8 Control Register" hidden="false" />
+ <register name="USBFS_BUF_SIZE" address="0x4000608C" bitWidth="8" desc="Dedicated Endpoint Buffer Size Register" hidden="false" />
+ <register name="USBFS_EP_ACTIVE" address="0x4000608E" bitWidth="8" desc="Endpoint Active Indication Register" hidden="false" />
+ <register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" hidden="false" />
+ <register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" hidden="false" />
</block>
- <block name="BL" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="BL" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
</blockRegMap>
\ No newline at end of file
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<filters />
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="cycodeshareimport.ld" persistent=".\Generated_Source\PSoC5\cycodeshareimport.ld">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="cycodeshareimport.scat" persistent=".\Generated_Source\PSoC5\cycodeshareimport.scat">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
</dependencies>
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<GlobalPages />
<GlobalTools name="Code Generation">
<GlobalPages>
-<name_val_pair name="General@Application Type" v="Bootloader" />
<name_val_pair name="General@Custom Code Gen Options" v="" />
<name_val_pair name="General@Skip Code Generation" v="False" />
<name_val_pair name="General@Custom Synthesis Options" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Fat LTO objects" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Libraries" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Link Files" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Generate Map File" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Nano Lib" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Enable printf Float" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@Optimization Level" v="None" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Enable Float printf" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
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<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Additional Library Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Use MicroLib" v="True" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Map File" v="True" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Debugging Information" v="True" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Libraries" v="" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Library Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Use MicroLib" v="True" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Map File" v="True" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Debugging Information" v="True" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@Command Line@Command Line" v="" />
</name>
</platform>
+<platform>
+<name v="e9305a93-d091-4da5-bdc7-2813049dcdbf">
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Assembly@Command Line@Command Line" v="-s+ -M<> -w+ -r -DNDEBUG --fpu None" />
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@C/C++@Command Line@Command Line" v="-D NDEBUG --debug --endian=little -e --fpu=None --no_wrap_diagnostics" />
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Linker@Command Line@Command Line" v="--semihosting --entry __iar_program_start --config Generated_Source\PSoC5\Cm3Iar.icf" />
+</name>
+</platform>
</platforms>
<project_current_platform v="c9323d49-d323-40b8-9b59-cc008d68a989" />
<project_current_processor v="CortexM3" />
-<component_generation v="PSoC Creator 3.0" />
<last_selected_tab v="Cypress" />
-<component_dependent_projects_generation v="(69eeda1b-ded5-4da3-a74d-3a98f2d5d4ab , 2.1PR) | (b1a3f413-e018-46a5-a51c-20818b2f118e , 3.0) | (cd381074-8dad-4f43-bb88-7719b3e16126 , 2.1) | (29420278-6fcc-46a7-a651-999ec5c253d2 , 2.1)" />
-<WriteAppVersionLastSavedWith v="3.1.0.1570" />
-<WriteAppMarketingVersionLastSavedWith v=" 3.1" />
+<WriteAppVersionLastSavedWith v="3.3.0.410" />
+<WriteAppMarketingVersionLastSavedWith v=" 3.3" />
<project_id v="61ede17a-ffe1-47e5-a8cd-0424bf996857" /><custom_data><CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1"><CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997 type_name="CyDesigner.Common.Base.CyCustomData" version="2"><userData /></CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997><properties /></CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111></custom_data></CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>
</CyGuid_60697ce6-dce2-4816-8680-4de0635742eb>
<top_block v="TopDesign" />
<ignored_deps />
</CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>
<boot_component v="cy_boot_v4_20" />
-<BootloaderTag hexFile="" elfFile="" />
-<current_generation v="0" />
-</CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
+<current_generation v="0" /><BootloaderTag hexFile="" elfFile="" /></CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
</CyXmlSerializer>
\ No newline at end of file
CONFIG_ENABLE_SCSI2 = 4,
CONFIG_DISABLE_GLITCH = 8,
CONFIG_ENABLE_CACHE = 16,
- CONFIG_ENABLE_DISCONNECT = 32
+ CONFIG_ENABLE_DISCONNECT = 32,
+ CONFIG_ENABLE_SEL_LATCH = 64,
+ CONFIG_MAP_LUNS_TO_IDS = 128
} CONFIG_FLAGS;
typedef enum
myParent(parent),
myDelayValidator(new wxIntegerValidator<uint8_t>)
{
- wxFlexGridSizer *fgs = new wxFlexGridSizer(8, 2, 9, 25);
+ wxFlexGridSizer *fgs = new wxFlexGridSizer(10, 2, 9, 25);
fgs->Add(new wxStaticText(this, wxID_ANY, _("Startup Delay (seconds)")));
myStartDelayCtrl =
myDisconnectCtrl->SetToolTip(_("Release the SCSI bus while waiting for SD card writes to complete. Must also be enabled in host OS."));
fgs->Add(myDisconnectCtrl);
+ fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
+ mySelLatchCtrl =
+ new wxCheckBox(
+ this,
+ ID_selLatchCtrl,
+ _("Respond to short SCSI selection pulses"));
+ mySelLatchCtrl->SetToolTip(_("Respond to very short duration selection attempts. This supports non-standard hardware, but is generally safe to enable. Required for Philips P2000C."));
+ fgs->Add(mySelLatchCtrl);
+
+ fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
+ myMapLunsCtrl =
+ new wxCheckBox(
+ this,
+ ID_mapLunsCtrl,
+ _("Map LUNS to SCSI IDs"));
+ myMapLunsCtrl->SetToolTip(_("Treat LUNS as IDs instead. Supports multiple drives on XEBEC S1410 SASI Bridge"));
+ fgs->Add(myMapLunsCtrl);
+
wxBoxSizer* hbox = new wxBoxSizer(wxHORIZONTAL);
hbox->Add(fgs, 1, wxALL | wxEXPAND, 15);
this->SetSizer(hbox);
(myScsi2Ctrl->IsChecked() ? CONFIG_ENABLE_SCSI2 : 0) |
(myGlitchCtrl->IsChecked() ? CONFIG_DISABLE_GLITCH : 0) |
(myCacheCtrl->IsChecked() ? CONFIG_ENABLE_CACHE: 0) |
- (myDisconnectCtrl->IsChecked() ? CONFIG_ENABLE_DISCONNECT: 0);
+ (myDisconnectCtrl->IsChecked() ? CONFIG_ENABLE_DISCONNECT: 0) |
+ (mySelLatchCtrl->IsChecked() ? CONFIG_ENABLE_SEL_LATCH : 0) |
+ (myMapLunsCtrl->IsChecked() ? CONFIG_MAP_LUNS_TO_IDS : 0);
config.startupDelay = CtrlGetValue<unsigned int>(myStartDelayCtrl).first;
config.selectionDelay = CtrlGetValue<unsigned int>(mySelDelayCtrl).first;
myGlitchCtrl->SetValue(config.flags & CONFIG_DISABLE_GLITCH);
myCacheCtrl->SetValue(config.flags & CONFIG_ENABLE_CACHE);
myDisconnectCtrl->SetValue(config.flags & CONFIG_ENABLE_DISCONNECT);
+ mySelLatchCtrl->SetValue(config.flags & CONFIG_ENABLE_SEL_LATCH);
+ myMapLunsCtrl->SetValue(config.flags & CONFIG_MAP_LUNS_TO_IDS);
{
std::stringstream conv;
ID_glitchCtrl,
ID_cacheCtrl,
ID_disconnectCtrl,
+ ID_selLatchCtrl,
+ ID_mapLunsCtrl,
ID_startDelayCtrl,
ID_selDelayCtrl
};
wxCheckBox* myGlitchCtrl;
wxCheckBox* myCacheCtrl;
wxCheckBox* myDisconnectCtrl;
+ wxCheckBox* mySelLatchCtrl;
+ wxCheckBox* myMapLunsCtrl;
wxIntegerValidator<uint8_t>* myDelayValidator;
wxTextCtrl* myStartDelayCtrl;
" <enableDisconnect>" <<
(config.flags & CONFIG_ENABLE_DISCONNECT ? "true" : "false") <<
"</enableDisconnect>\n" <<
+
+ " <!-- ********************************************************\n" <<
+ " Respond to very short duration selection attempts. This supports\n" <<
+ " non-standard hardware, but is generally safe to enable.\n" <<
+ " Required for Philips P2000C.\n" <<
+ " ********************************************************* -->\n" <<
+ " <selLatch>" <<
+ (config.flags & CONFIG_ENABLE_SEL_LATCH? "true" : "false") <<
+ "</selLatch>\n" <<
+
+
+ " <!-- ********************************************************\n" <<
+ " Convert luns to IDs. The unit must already be configured to respond\n" <<
+ " on the ID. Allows dual drives to be accessed from a \n" <<
+ " XEBEC S1410 SASI bridge.\n" <<
+ " eg. Configured for dual drives as IDs 0 and 1, but the XEBEC will\n" <<
+ " access the second disk as ID0, lun 1.\n" <<
+ " See ttp://bitsavers.trailing-edge.com/pdf/xebec/104524C_S1410Man_Aug83.pdf\n" <<
+ " ********************************************************* -->\n" <<
+ " <mapLunsToIds>" <<
+ (config.flags & CONFIG_MAP_LUNS_TO_IDS ? "true" : "false") <<
+ "</mapLunsToIds>\n" <<
"</BoardConfig>\n";
return s.str();
result.flags = result.flags & ~CONFIG_ENABLE_DISCONNECT;
}
}
+ else if (child->GetName() == "selLatch")
+ {
+ std::string s(child->GetNodeContent().mb_str());
+ if (s == "true")
+ {
+ result.flags |= CONFIG_ENABLE_SEL_LATCH;
+ }
+ else
+ {
+ result.flags = result.flags & ~CONFIG_ENABLE_SEL_LATCH;
+ }
+ }
+ else if (child->GetName() == "mapLunsToIds")
+ {
+ std::string s(child->GetNodeContent().mb_str());
+ if (s == "true")
+ {
+ result.flags |= CONFIG_MAP_LUNS_TO_IDS;
+ }
+ else
+ {
+ result.flags = result.flags & ~CONFIG_MAP_LUNS_TO_IDS;
+ }
+ }
child = child->GetNext();
}
return result;
ID_Firmware,
_("&Upgrade Firmware..."),
_("Upgrade or inspect device firmware version."));
+ menuFile->Append(
+ ID_Bootloader,
+ _("&Upgrade Bootloader (ADVANCED) ..."),
+ _("Upgrade device bootloader."));
menuFile->AppendSeparator();
menuFile->Append(wxID_EXIT);
{
ID_ConfigDefaults = wxID_HIGHEST + 1,
ID_Firmware,
+ ID_Bootloader,
ID_Timer,
ID_Notebook,
ID_BtnLoad,
doFirmwareUpdate();
}
+ void OnID_Bootloader(wxCommandEvent& event)
+ {
+ TimerLock lock(myTimer);
+ doBootloaderUpdate();
+ }
+
void OnID_LogWindow(wxCommandEvent& event)
{
myLogWindow->Show();
}
}
+ void doBootloaderUpdate()
+ {
+ if (!myHID)
+ {
+ wxMessageBox(
+ "No device",
+ "No device",
+ wxOK | wxICON_ERROR);
+ return;
+ }
+
+ wxFileDialog dlg(
+ this,
+ "Load bootloader file",
+ "",
+ "",
+ "SCSI2SD Bootloader files (*.bin)|*.bin",
+ wxFD_OPEN | wxFD_FILE_MUST_EXIST);
+ if (dlg.ShowModal() == wxID_CANCEL) return;
+
+ std::string filename(dlg.GetPath());
+
+ wxFile file(filename);
+ if (file.Length() != 0x2400)
+ {
+ wxMessageBox(
+ "Invalid file",
+ "Invalid file",
+ wxOK | wxICON_ERROR);
+ return;
+
+ }
+ uint8_t data[0x2400];
+ if (file.Read(data, sizeof(data)) != sizeof(data))
+ {
+ wxMessageBox(
+ "Couldn't read file",
+ "Couldn't read file",
+ wxOK | wxICON_ERROR);
+ return;
+ }
+
+ static char magic[] = {
+ 'P', 0, 'S', 0, 'o', 0, 'C', 0, '3', 0, ' ', 0,
+ 'B', 0, 'o', 0, 'o', 0, 't', 0, 'l', 0, 'o', 0, 'a', 0, 'd', 0, 'e', 0, 'r', 0};
+
+ uint8_t* dataEnd = data + sizeof(data);
+ if (std::search(data, dataEnd, magic, magic + sizeof(magic)) >= dataEnd)
+ {
+ wxMessageBox(
+ "Bad file",
+ "Not a valid bootloader file.",
+ wxOK | wxICON_ERROR);
+ return;
+ }
+
+ std::stringstream msg;
+ msg << "Upgrading bootloader from file: " << filename;
+ mmLogStatus(msg.str());
+
+ wxWindowPtr<wxGenericProgressDialog> progress(
+ new wxGenericProgressDialog(
+ "Update bootloader",
+ "Update bootloader",
+ 100,
+ this,
+ wxPD_REMAINING_TIME)
+ );
+
+
+ int currentProgress = 0;
+ int totalProgress = 36;
+
+ for (size_t flashRow = 0; flashRow < 36; ++flashRow)
+ {
+ std::stringstream ss;
+ ss << "Programming flash array 0 row " << (flashRow);
+ mmLogStatus(ss.str());
+ currentProgress += 1;
+
+ if (currentProgress == totalProgress)
+ {
+ ss.str("Save Complete.");
+ mmLogStatus("Save Complete.");
+ }
+ if (!progress->Update(
+ (100 * currentProgress) / totalProgress,
+ ss.str()
+ )
+ )
+ {
+ goto abort;
+ }
+
+ uint8_t* rowData = data + (flashRow * 256);
+ std::vector<uint8_t> flashData(rowData, rowData + 256);
+ try
+ {
+ myHID->writeFlashRow(0, flashRow, flashData);
+ }
+ catch (std::runtime_error& e)
+ {
+ mmLogStatus(e.what());
+ goto err;
+ }
+ }
+
+ goto out;
+
+ err:
+ mmLogStatus("Bootloader update failed");
+ progress->Update(100, "Bootloader update failed");
+ goto out;
+
+ abort:
+ mmLogStatus("Bootloader update aborted");
+
+ out:
+ return;
+
+
+ }
+
void dumpSCSICommand(std::vector<uint8_t> buf)
{
std::stringstream msg;
}
}
- // Reboot so new settings take effect.
- myHID->enterBootloader();
myHID.reset();
-
goto out;
err:
wxBEGIN_EVENT_TABLE(AppFrame, wxFrame)
EVT_MENU(AppFrame::ID_ConfigDefaults, AppFrame::OnID_ConfigDefaults)
EVT_MENU(AppFrame::ID_Firmware, AppFrame::OnID_Firmware)
+ EVT_MENU(AppFrame::ID_Bootloader, AppFrame::OnID_Bootloader)
EVT_MENU(AppFrame::ID_LogWindow, AppFrame::OnID_LogWindow)
EVT_MENU(AppFrame::ID_SaveFile, AppFrame::OnID_SaveFile)
EVT_MENU(AppFrame::ID_OpenFile, AppFrame::OnID_OpenFile)
projects / SCSI2SD.git / commitdiff