Disable the FMC fifo until we have code that can detect when it's empty.

diff --git a/STM32CubeMX/2021/Src/fmc.c b/STM32CubeMX/2021/Src/fmc.c
index 56e0f7c337e2c3690dac5882de8fdab4045639f2..cc23ebee33d01a4a9983bcf0050b4dff4598b5c8 100644 (file)
--- a/STM32CubeMX/2021/Src/fmc.c
+++ b/STM32CubeMX/2021/Src/fmc.c
@@ -49,7 +49,9 @@ void MX_FMC_Init(void)
   hsram1.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
   hsram1.Init.WriteBurst = FMC_WRITE_BURST_DISABLE;
   hsram1.Init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ONLY;
-  hsram1.Init.WriteFifo = FMC_WRITE_FIFO_ENABLE;
+  hsram1.Init.WriteFifo = FMC_WRITE_FIFO_DISABLE;
+  // WE MAY start writing another 512 bytes before this FIFO is empty!
+
   hsram1.Init.PageSize = FMC_PAGE_SIZE_NONE;
   /* Timing */
 

diff --git a/src/firmware/bsp_driver_sd.c b/src/firmware/bsp_driver_sd.c
index e69c7183844bc18c842d873173506c09f9536ebd..2ac26625994728a3957f0b036ca48701f251329d 100755 (executable)
--- a/src/firmware/bsp_driver_sd.c
+++ b/src/firmware/bsp_driver_sd.c
@@ -55,7 +55,7 @@ uint8_t BSP_SD_Init(void)
   }
   SD_state = HAL_SD_Init(&hsd);
 #ifdef BUS_4BITS
-  if (SD_state == MSD_OK)
+  if (SD_state == HAL_OK)
   {
     if (HAL_SD_ConfigWideBusOperation(&hsd, SDIO_BUS_WIDE_4B) != HAL_OK)
     {

diff --git a/src/firmware/config.c b/src/firmware/config.c
index 109b856f0670df171a68a0e37734629cea85c2a1..81de8b61e5409437746f6f3d05b179c96b350f1e 100755 (executable)
--- a/src/firmware/config.c
+++ b/src/firmware/config.c
@@ -36,11 +36,13 @@
 \r
 #include <string.h>\r
 \r
-static const uint16_t FIRMWARE_VERSION = 0x0646;\r
+static const uint16_t FIRMWARE_VERSION = 0x0647;\r
 \r
 // Optional static config\r
 extern uint8_t* __fixed_config;\r
 \r
+extern SD_HandleTypeDef hsd;\r
+\r
 #ifdef S2S_USB_HS\r
 #define configUsbDev hUsbDeviceHS\r
 #else\r
@@ -235,7 +237,7 @@ debugCommand()
     response[23] = scsiDev.msgCount;\r
     response[24] = scsiDev.cmdCount;\r
     response[25] = scsiDev.watchdogTick;\r
-    response[26] = blockDev.state;\r
+    response[26] = (hsd.State << 4) | blockDev.state;\r
     response[27] = scsiDev.lastSenseASC >> 8;\r
     response[28] = scsiDev.lastSenseASC;\r
     response[29] = *SCSI_STS_DBX & 0xff; // What we've read\r

diff --git a/src/firmware/scsiPhy.c b/src/firmware/scsiPhy.c
index 684887dcdfeb16435a066c5d3d3481a65159f38f..a883dd5a2c89d578ece62961bf62a897fb7324cf 100755 (executable)
--- a/src/firmware/scsiPhy.c
+++ b/src/firmware/scsiPhy.c
@@ -104,17 +104,15 @@ scsiSetDataCount(uint32_t count)
 int scsiFifoReady(void)\r
 {\r
        __NOP();\r
-#ifdef STM32F4xx\r
-       __NOP();\r
-#endif\r
-       HAL_GPIO_ReadPin(GPIOE, FPGA_GPIO3_Pin);\r
+       uint8_t test1 = HAL_GPIO_ReadPin(GPIOE, FPGA_GPIO3_Pin);\r
        __NOP();\r
 #ifdef STM32F4xx\r
        __NOP();\r
        __NOP();\r
        __NOP();\r
 #endif\r
-       return HAL_GPIO_ReadPin(GPIOE, FPGA_GPIO3_Pin) != 0;\r
+       uint8_t test2 = HAL_GPIO_ReadPin(GPIOE, FPGA_GPIO3_Pin);\r
+       return test1 != 0 && test2 != 0;\r
 }\r
 \r
 uint8_t\r