From: Michael McMaster Date: Sun, 2 Mar 2014 11:52:06 +0000 (+1000) Subject: Fixed broken Unit Attention Condition and reset behaviour. X-Git-Tag: 3.3~8 X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=030fc25ffb35b4c766de9e46323b301f86becbdc;p=SCSI2SD-V6.git Fixed broken Unit Attention Condition and reset behaviour. --- diff --git a/CHANGELOG b/CHANGELOG index 5a4eb9f4..81e04ecf 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,10 @@ +20140??? 3.3 + - Fix to SCSI Reset handling to avoid lockups + - Bug fixes to improve standards compatibility + - Bug fix for Unit Attention Condition, which is now enabled by default. + - scsi2sd-config can be used to disable it for those systems that + truely require it (eg. Mac Plus). + 20140214 3.2 - Remove hacks around ATN handling, and implement proper select-with-atn support. This fix is essential for communicating with some SCSI hosts. diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c index cce3cf39..14425977 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c @@ -104,7 +104,7 @@ const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[41u] = { /* bEndpointAddress */ 0x82u, /* bmAttributes */ 0x03u, /* wMaxPacketSize */ 0x40u, 0x00u, -/* bInterval */ 0x80u +/* bInterval */ 0x40u }; /********************************************************************* diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index af7277c2..7d179bd1 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -478,34 +478,34 @@ #define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -513,9 +513,9 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB06_MSK -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB06_ST +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 #define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL @@ -530,31 +530,27 @@ #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu #define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK -#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL #define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL -#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL #define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB06_07_A0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB06_07_A1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB06_07_D0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB06_07_D1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB06_07_F0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB06_07_F1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB06_A0_A1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB06_A0 -#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB06_A1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB06_D0_D1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB06_D0 -#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB06_D1 -#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB06_F0_F1 -#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB06_F0 -#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB06_F1 -#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1 +#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL /* USBFS_dp_int */ #define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -569,24 +565,24 @@ /* SCSI_CTL_IO */ #define SCSI_CTL_IO_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_IO_Sync_ctrl_reg__0__POS 0 -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL -#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL -#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL +#define SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL #define SCSI_CTL_IO_Sync_ctrl_reg__MASK 0x01u -#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL -#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK -#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK +#define SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL /* SCSI_In_DBx */ #define SCSI_In_DBx__0__AG CYREG_PRT12_AG @@ -1045,8 +1041,8 @@ /* scsiTarget */ #define scsiTarget_StatusReg__0__MASK 0x01u #define scsiTarget_StatusReg__0__POS 0 -#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 #define scsiTarget_StatusReg__2__MASK 0x04u @@ -1054,76 +1050,76 @@ #define scsiTarget_StatusReg__3__MASK 0x08u #define scsiTarget_StatusReg__3__POS 3 #define scsiTarget_StatusReg__MASK 0x0Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST -#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST -#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK -#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL -#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL -#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB03_ST -#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL -#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK -#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK -#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK -#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB03_CTL -#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL -#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB03_CTL -#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL -#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB03_MSK -#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB03_04_A0 -#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB03_04_A1 -#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB03_04_D0 -#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB03_04_D1 -#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB03_04_F0 -#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB03_04_F1 -#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB03_A0_A1 -#define scsiTarget_datapath__A0_REG CYREG_B0_UDB03_A0 -#define scsiTarget_datapath__A1_REG CYREG_B0_UDB03_A1 -#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB03_D0_D1 -#define scsiTarget_datapath__D0_REG CYREG_B0_UDB03_D0 -#define scsiTarget_datapath__D1_REG CYREG_B0_UDB03_D1 -#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB03_F0_F1 -#define scsiTarget_datapath__F0_REG CYREG_B0_UDB03_F0 -#define scsiTarget_datapath__F1_REG CYREG_B0_UDB03_F1 -#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB14_MSK +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB14_ST +#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL +#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST +#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB13_MSK +#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL +#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB13_ST_CTL +#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB13_ST_CTL +#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB13_ST +#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL +#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK +#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK +#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL +#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB13_CTL +#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL +#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB13_CTL +#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL +#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB13_MSK +#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB13_14_A0 +#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB13_14_A1 +#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB13_14_D0 +#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB13_14_D1 +#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL +#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB13_14_F0 +#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB13_14_F1 +#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB13_A0_A1 +#define scsiTarget_datapath__A0_REG CYREG_B0_UDB13_A0 +#define scsiTarget_datapath__A1_REG CYREG_B0_UDB13_A1 +#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB13_D0_D1 +#define scsiTarget_datapath__D0_REG CYREG_B0_UDB13_D0 +#define scsiTarget_datapath__D1_REG CYREG_B0_UDB13_D1 +#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB13_ACTL +#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB13_F0_F1 +#define scsiTarget_datapath__F0_REG CYREG_B0_UDB13_F0 +#define scsiTarget_datapath__F1_REG CYREG_B0_UDB13_F1 +#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL /* SD_Clk_Ctl */ #define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0 -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL -#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL -#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL +#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL #define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL -#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK -#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK +#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL /* USBFS_ep_0 */ #define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index fae86639..d3600d72 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode) } #endif -#define CY_CFG_BASE_ADDR_COUNT 34u +#define CY_CFG_BASE_ADDR_COUNT 33u CYPACKED typedef struct { uint8 offset; @@ -364,36 +364,35 @@ void cyfitter_cfg(void) static const uint32 CYCODE cy_cfg_addr_table[] = { 0x40004502u, /* Base address: 0x40004500 Count: 2 */ 0x4000520Au, /* Base address: 0x40005200 Count: 10 */ - 0x40006401u, /* Base address: 0x40006400 Count: 1 */ - 0x40006501u, /* Base address: 0x40006500 Count: 1 */ - 0x40010043u, /* Base address: 0x40010000 Count: 67 */ - 0x40010130u, /* Base address: 0x40010100 Count: 48 */ - 0x4001023Au, /* Base address: 0x40010200 Count: 58 */ - 0x4001034Cu, /* Base address: 0x40010300 Count: 76 */ - 0x40010447u, /* Base address: 0x40010400 Count: 71 */ - 0x4001054Du, /* Base address: 0x40010500 Count: 77 */ - 0x40010649u, /* Base address: 0x40010600 Count: 73 */ - 0x40010746u, /* Base address: 0x40010700 Count: 70 */ - 0x4001090Du, /* Base address: 0x40010900 Count: 13 */ - 0x40010A33u, /* Base address: 0x40010A00 Count: 51 */ - 0x40010B38u, /* Base address: 0x40010B00 Count: 56 */ - 0x40010D06u, /* Base address: 0x40010D00 Count: 6 */ - 0x40010F03u, /* Base address: 0x40010F00 Count: 3 */ - 0x40011503u, /* Base address: 0x40011500 Count: 3 */ - 0x40011736u, /* Base address: 0x40011700 Count: 54 */ - 0x40011902u, /* Base address: 0x40011900 Count: 2 */ - 0x40011B02u, /* Base address: 0x40011B00 Count: 2 */ - 0x4001400Du, /* Base address: 0x40014000 Count: 13 */ + 0x40006402u, /* Base address: 0x40006400 Count: 2 */ + 0x40010101u, /* Base address: 0x40010100 Count: 1 */ + 0x40010308u, /* Base address: 0x40010300 Count: 8 */ + 0x40010442u, /* Base address: 0x40010400 Count: 66 */ + 0x4001053Cu, /* Base address: 0x40010500 Count: 60 */ + 0x40010604u, /* Base address: 0x40010600 Count: 4 */ + 0x40010747u, /* Base address: 0x40010700 Count: 71 */ + 0x40010908u, /* Base address: 0x40010900 Count: 8 */ + 0x40010A44u, /* Base address: 0x40010A00 Count: 68 */ + 0x40010B40u, /* Base address: 0x40010B00 Count: 64 */ + 0x40010C35u, /* Base address: 0x40010C00 Count: 53 */ + 0x40010D49u, /* Base address: 0x40010D00 Count: 73 */ + 0x40010E43u, /* Base address: 0x40010E00 Count: 67 */ + 0x40010F2Fu, /* Base address: 0x40010F00 Count: 47 */ + 0x40011504u, /* Base address: 0x40011500 Count: 4 */ + 0x40011648u, /* Base address: 0x40011600 Count: 72 */ + 0x40011740u, /* Base address: 0x40011700 Count: 64 */ + 0x40011904u, /* Base address: 0x40011900 Count: 4 */ + 0x4001400Bu, /* Base address: 0x40014000 Count: 11 */ 0x4001410Fu, /* Base address: 0x40014100 Count: 15 */ - 0x4001420Au, /* Base address: 0x40014200 Count: 10 */ - 0x40014308u, /* Base address: 0x40014300 Count: 8 */ - 0x4001440Bu, /* Base address: 0x40014400 Count: 11 */ - 0x40014512u, /* Base address: 0x40014500 Count: 18 */ - 0x4001460Cu, /* Base address: 0x40014600 Count: 12 */ - 0x40014706u, /* Base address: 0x40014700 Count: 6 */ + 0x40014207u, /* Base address: 0x40014200 Count: 7 */ + 0x40014303u, /* Base address: 0x40014300 Count: 3 */ + 0x4001440Cu, /* Base address: 0x40014400 Count: 12 */ + 0x40014516u, /* Base address: 0x40014500 Count: 22 */ + 0x40014608u, /* Base address: 0x40014600 Count: 8 */ + 0x40014708u, /* Base address: 0x40014700 Count: 8 */ 0x4001480Au, /* Base address: 0x40014800 Count: 10 */ - 0x40014909u, /* Base address: 0x40014900 Count: 9 */ - 0x40014C02u, /* Base address: 0x40014C00 Count: 2 */ + 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */ + 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */ 0x40015006u, /* Base address: 0x40015000 Count: 6 */ 0x40015101u, /* Base address: 0x40015100 Count: 1 */ }; @@ -402,172 +401,402 @@ void cyfitter_cfg(void) {0x36u, 0x02u}, {0x7Eu, 0x02u}, {0x00u, 0x01u}, - {0x01u, 0x01u}, - {0x18u, 0x08u}, - {0x19u, 0x04u}, + {0x01u, 0x03u}, + {0x18u, 0x04u}, + {0x19u, 0x0Cu}, {0x1Cu, 0x61u}, {0x20u, 0x98u}, - {0x21u, 0x50u}, + {0x21u, 0x38u}, {0x30u, 0x03u}, - {0x31u, 0x06u}, + {0x31u, 0x05u}, {0x7Cu, 0x40u}, - {0x33u, 0x03u}, + {0x3Du, 0x03u}, {0x86u, 0x0Fu}, - {0x06u, 0x44u}, - {0x07u, 0x03u}, - {0x09u, 0x10u}, - {0x10u, 0x44u}, - {0x12u, 0x22u}, - {0x16u, 0x03u}, - {0x17u, 0x04u}, + {0xE2u, 0x80u}, + {0x81u, 0x40u}, + {0x85u, 0x04u}, + {0xA0u, 0x04u}, + {0xACu, 0x04u}, + {0xE2u, 0x08u}, + {0xE6u, 0x25u}, + {0xEAu, 0x01u}, + {0xEEu, 0x02u}, + {0x07u, 0x04u}, + {0x0Bu, 0x04u}, + {0x0Du, 0x04u}, + {0x0Fu, 0x02u}, + {0x13u, 0x03u}, {0x19u, 0x04u}, - {0x1Au, 0x30u}, {0x1Bu, 0x01u}, - {0x1Du, 0x08u}, - {0x1Eu, 0x40u}, - {0x21u, 0x04u}, - {0x23u, 0x02u}, + {0x31u, 0x07u}, + {0x56u, 0x08u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x90u}, + {0x5Du, 0x90u}, + {0x5Fu, 0x01u}, + {0x80u, 0xD6u}, + {0x81u, 0x2Cu}, + {0x84u, 0x17u}, + {0x86u, 0x28u}, + {0x88u, 0xD2u}, + {0x89u, 0x31u}, + {0x8Au, 0x04u}, + {0x8Bu, 0x42u}, + {0x8Cu, 0xD6u}, + {0x8Du, 0x2Cu}, + {0x91u, 0xC0u}, + {0x94u, 0x29u}, + {0x96u, 0x46u}, + {0x97u, 0x2Cu}, + {0x98u, 0x20u}, + {0x99u, 0x40u}, + {0x9Au, 0xD0u}, + {0x9Bu, 0x2Fu}, + {0x9Cu, 0x04u}, + {0x9Du, 0x24u}, + {0xA0u, 0xD6u}, + {0xA1u, 0x08u}, + {0xA3u, 0x10u}, + {0xA4u, 0xD0u}, + {0xA5u, 0x24u}, + {0xA6u, 0x06u}, + {0xA7u, 0x08u}, + {0xA8u, 0x21u}, + {0xA9u, 0x11u}, + {0xAAu, 0x8Eu}, + {0xABu, 0x8Eu}, + {0xACu, 0x02u}, + {0xADu, 0x2Cu}, + {0xB0u, 0x01u}, + {0xB1u, 0xC1u}, + {0xB2u, 0x0Fu}, + {0xB3u, 0x31u}, + {0xB4u, 0xF0u}, + {0xB5u, 0x0Fu}, + {0xB6u, 0x08u}, + {0xB8u, 0x08u}, + {0xB9u, 0x02u}, + {0xBAu, 0x20u}, + {0xBBu, 0x0Cu}, + {0xBEu, 0x41u}, + {0xD4u, 0x09u}, + {0xD8u, 0x0Bu}, + {0xD9u, 0x0Bu}, + {0xDBu, 0x0Bu}, + {0xDCu, 0x99u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x04u, 0x29u}, + {0x06u, 0x02u}, + {0x0Eu, 0x28u}, + {0x0Fu, 0x02u}, + {0x17u, 0x65u}, + {0x1Cu, 0x10u}, + {0x1Du, 0x48u}, + {0x1Eu, 0x28u}, + {0x1Fu, 0x09u}, + {0x21u, 0x02u}, + {0x23u, 0x40u}, {0x24u, 0x08u}, - {0x28u, 0x44u}, - {0x2Au, 0x11u}, - {0x2Bu, 0x04u}, - {0x2Eu, 0x04u}, - {0x31u, 0x10u}, - {0x32u, 0x07u}, - {0x33u, 0x07u}, - {0x34u, 0x70u}, - {0x35u, 0x08u}, - {0x36u, 0x08u}, + {0x25u, 0x10u}, + {0x26u, 0x02u}, + {0x27u, 0x38u}, + {0x29u, 0xC0u}, + {0x2Du, 0x02u}, + {0x2Fu, 0x2Au}, + {0x31u, 0x02u}, + {0x32u, 0x10u}, + {0x34u, 0x01u}, + {0x36u, 0x02u}, + {0x37u, 0x54u}, + {0x39u, 0x48u}, + {0x3Au, 0x10u}, + {0x3Cu, 0x81u}, + {0x3Du, 0x20u}, + {0x3Eu, 0x01u}, + {0x58u, 0x80u}, + {0x5Du, 0x98u}, + {0x5Eu, 0x02u}, + {0x60u, 0x02u}, + {0x62u, 0x80u}, + {0x65u, 0x08u}, + {0x66u, 0x04u}, + {0x67u, 0x02u}, + {0x7Eu, 0x80u}, + {0x89u, 0x02u}, + {0x8Cu, 0x20u}, + {0x91u, 0x48u}, + {0x92u, 0x20u}, + {0x9Au, 0x10u}, + {0xA0u, 0x04u}, + {0xA4u, 0x10u}, + {0xAEu, 0x10u}, + {0xB0u, 0x10u}, + {0xB6u, 0x10u}, + {0xC0u, 0xF0u}, + {0xC2u, 0xE0u}, + {0xC4u, 0xF0u}, + {0xCAu, 0xF0u}, + {0xCCu, 0xF5u}, + {0xCEu, 0xBEu}, + {0xD6u, 0xF8u}, + {0xD8u, 0x18u}, + {0xDEu, 0x80u}, + {0xE2u, 0x40u}, + {0xE6u, 0x20u}, + {0xEAu, 0x02u}, + {0xEEu, 0x08u}, + {0xD4u, 0x40u}, + {0xDBu, 0x0Bu}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x04u, 0x20u}, + {0x06u, 0x02u}, + {0x07u, 0x60u}, + {0x0Eu, 0xA1u}, + {0x0Fu, 0x04u}, + {0x15u, 0x14u}, + {0x17u, 0x09u}, + {0x1Fu, 0x08u}, + {0x25u, 0x40u}, + {0x26u, 0x40u}, + {0x27u, 0x80u}, + {0x2Cu, 0x80u}, + {0x2Fu, 0x2Au}, + {0x36u, 0x02u}, + {0x37u, 0xA8u}, + {0x3Cu, 0x10u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x01u}, + {0x3Fu, 0x04u}, + {0x45u, 0x88u}, + {0x46u, 0x40u}, + {0x47u, 0x20u}, + {0x4Cu, 0x04u}, + {0x4Du, 0x0Au}, + {0x4Fu, 0x06u}, + {0x55u, 0x20u}, + {0x56u, 0x84u}, + {0x61u, 0x20u}, + {0x62u, 0x08u}, + {0x63u, 0x01u}, + {0x65u, 0x80u}, + {0x6Cu, 0x10u}, + {0x6Du, 0x11u}, + {0x6Eu, 0x09u}, + {0x6Fu, 0x27u}, + {0x74u, 0xC0u}, + {0x76u, 0x02u}, + {0x78u, 0x02u}, + {0x7Eu, 0x80u}, + {0x81u, 0x48u}, + {0x90u, 0x18u}, + {0x92u, 0x80u}, + {0x93u, 0x40u}, + {0x94u, 0x20u}, + {0x96u, 0x01u}, + {0x98u, 0x23u}, + {0x9Bu, 0x38u}, + {0x9Du, 0x02u}, + {0x9Eu, 0x06u}, + {0x9Fu, 0x45u}, + {0xA0u, 0x04u}, + {0xA1u, 0x08u}, + {0xA2u, 0x90u}, + {0xA4u, 0x50u}, + {0xA6u, 0x01u}, + {0xA7u, 0x23u}, + {0xAAu, 0x40u}, + {0xACu, 0x80u}, + {0xB1u, 0x12u}, + {0xC0u, 0xF0u}, + {0xC2u, 0xF0u}, + {0xC4u, 0x70u}, + {0xCAu, 0xF0u}, + {0xCCu, 0xF0u}, + {0xCEu, 0xF0u}, + {0xD0u, 0xF0u}, + {0xD2u, 0x20u}, + {0xD8u, 0x1Eu}, + {0xDEu, 0x81u}, + {0xE8u, 0x40u}, + {0xEEu, 0x03u}, + {0x9Cu, 0x04u}, + {0xA7u, 0x40u}, + {0xAEu, 0x11u}, + {0xB0u, 0x80u}, + {0xB6u, 0x10u}, + {0xE8u, 0x40u}, + {0xEAu, 0x02u}, + {0xEEu, 0x01u}, + {0x04u, 0x24u}, + {0x06u, 0x12u}, + {0x07u, 0x03u}, + {0x0Au, 0x24u}, + {0x0Bu, 0x04u}, + {0x0Eu, 0x03u}, + {0x10u, 0x40u}, + {0x12u, 0x80u}, + {0x13u, 0x20u}, + {0x16u, 0x80u}, + {0x1Au, 0x18u}, + {0x1Bu, 0x24u}, + {0x1Fu, 0x18u}, + {0x21u, 0x40u}, + {0x22u, 0x20u}, + {0x25u, 0x24u}, + {0x26u, 0x04u}, + {0x27u, 0x12u}, + {0x29u, 0x80u}, + {0x2Au, 0x40u}, + {0x2Cu, 0x24u}, + {0x2Du, 0x24u}, + {0x2Eu, 0x09u}, + {0x2Fu, 0x09u}, + {0x30u, 0x07u}, + {0x31u, 0x80u}, + {0x33u, 0x40u}, + {0x34u, 0x38u}, + {0x35u, 0x07u}, + {0x36u, 0xC0u}, + {0x37u, 0x38u}, {0x3Eu, 0x40u}, - {0x3Fu, 0x11u}, + {0x3Fu, 0x05u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, {0x5Cu, 0x99u}, {0x5Fu, 0x01u}, - {0x84u, 0x18u}, - {0x86u, 0x60u}, - {0x87u, 0x04u}, - {0x88u, 0x07u}, - {0x8Bu, 0x08u}, - {0x8Du, 0x08u}, - {0x8Fu, 0x10u}, - {0x90u, 0x28u}, - {0x92u, 0x50u}, - {0x93u, 0x03u}, - {0x98u, 0x04u}, - {0x9Bu, 0x04u}, - {0xA0u, 0x30u}, - {0xA2u, 0x48u}, - {0xA3u, 0x10u}, - {0xA5u, 0x04u}, - {0xA6u, 0x02u}, - {0xA7u, 0x01u}, - {0xA8u, 0x01u}, - {0xADu, 0x04u}, - {0xAEu, 0x07u}, - {0xAFu, 0x02u}, - {0xB1u, 0x18u}, - {0xB2u, 0x78u}, - {0xB4u, 0x07u}, - {0xB7u, 0x07u}, - {0xBEu, 0x14u}, - {0xBFu, 0x01u}, - {0xD6u, 0x08u}, + {0x85u, 0x33u}, + {0x86u, 0xFFu}, + {0x87u, 0xCCu}, + {0x89u, 0xFFu}, + {0x8Du, 0x0Fu}, + {0x8Eu, 0xFFu}, + {0x8Fu, 0xF0u}, + {0x90u, 0x96u}, + {0x92u, 0x69u}, + {0x93u, 0xFFu}, + {0x94u, 0xFFu}, + {0x98u, 0x33u}, + {0x9Au, 0xCCu}, + {0x9Du, 0x96u}, + {0x9Fu, 0x69u}, + {0xA0u, 0x55u}, + {0xA1u, 0x55u}, + {0xA2u, 0xAAu}, + {0xA3u, 0xAAu}, + {0xA7u, 0xFFu}, + {0xACu, 0x0Fu}, + {0xAEu, 0xF0u}, + {0xB2u, 0xFFu}, + {0xB3u, 0xFFu}, + {0xBEu, 0x04u}, + {0xBFu, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x90u}, - {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x04u}, - {0x05u, 0x08u}, - {0x06u, 0x08u}, - {0x09u, 0x80u}, - {0x0Au, 0x54u}, - {0x0Cu, 0x02u}, - {0x0Eu, 0x08u}, - {0x12u, 0x08u}, - {0x13u, 0x48u}, - {0x14u, 0x08u}, - {0x16u, 0x01u}, - {0x17u, 0x05u}, - {0x19u, 0x08u}, - {0x1Au, 0x16u}, + {0x00u, 0x50u}, + {0x03u, 0x20u}, + {0x05u, 0x04u}, + {0x06u, 0x20u}, + {0x07u, 0x01u}, + {0x0Au, 0x64u}, + {0x0Eu, 0x80u}, + {0x0Fu, 0xA4u}, + {0x10u, 0xA5u}, + {0x13u, 0x40u}, + {0x14u, 0x40u}, + {0x15u, 0x40u}, + {0x18u, 0x40u}, + {0x1Au, 0x06u}, {0x1Bu, 0x10u}, - {0x1Du, 0x18u}, - {0x21u, 0x04u}, - {0x22u, 0x12u}, - {0x24u, 0x40u}, - {0x27u, 0x01u}, - {0x29u, 0x21u}, - {0x2Du, 0x02u}, - {0x2Eu, 0x40u}, - {0x2Fu, 0x20u}, - {0x30u, 0x40u}, - {0x31u, 0x24u}, - {0x33u, 0x20u}, - {0x35u, 0x20u}, + {0x1Fu, 0x04u}, + {0x22u, 0x46u}, + {0x23u, 0x04u}, + {0x25u, 0x08u}, + {0x28u, 0x81u}, + {0x2Au, 0x10u}, + {0x2Bu, 0x20u}, + {0x2Cu, 0x40u}, + {0x2Eu, 0x04u}, + {0x30u, 0x42u}, + {0x31u, 0x20u}, + {0x32u, 0x40u}, + {0x36u, 0x40u}, {0x37u, 0x01u}, - {0x39u, 0x08u}, - {0x3Bu, 0x10u}, - {0x3Du, 0x80u}, + {0x39u, 0x10u}, + {0x3Bu, 0x04u}, + {0x3Du, 0x40u}, {0x3Eu, 0x20u}, {0x3Fu, 0x04u}, - {0x5Cu, 0x40u}, - {0x67u, 0x02u}, - {0x69u, 0x80u}, - {0x82u, 0x10u}, - {0x83u, 0x01u}, - {0xC0u, 0x64u}, - {0xC2u, 0x5Fu}, - {0xC4u, 0xF7u}, - {0xCAu, 0xD5u}, - {0xCCu, 0xAEu}, + {0x6Au, 0x40u}, + {0x6Fu, 0x01u}, + {0x8Cu, 0x40u}, + {0x90u, 0x10u}, + {0x91u, 0x50u}, + {0x93u, 0x40u}, + {0x96u, 0x08u}, + {0x97u, 0x0Cu}, + {0x99u, 0x04u}, + {0x9Cu, 0x40u}, + {0x9Fu, 0x01u}, + {0xA0u, 0xA2u}, + {0xA1u, 0x20u}, + {0xA3u, 0x20u}, + {0xA5u, 0x08u}, + {0xA6u, 0x02u}, + {0xA7u, 0x50u}, + {0xADu, 0x50u}, + {0xB2u, 0xC0u}, + {0xB3u, 0x08u}, + {0xB4u, 0x42u}, + {0xC0u, 0xA7u}, + {0xC2u, 0x7Eu}, + {0xC4u, 0x9Fu}, + {0xCAu, 0xCFu}, + {0xCCu, 0x9Du}, {0xCEu, 0x76u}, - {0xD6u, 0x10u}, - {0xD8u, 0x10u}, - {0xE4u, 0x04u}, - {0x82u, 0x40u}, - {0x83u, 0x06u}, - {0x84u, 0x16u}, - {0x85u, 0x10u}, - {0x86u, 0x48u}, - {0x8Bu, 0x08u}, - {0x8Cu, 0x02u}, - {0x8Fu, 0x20u}, - {0x90u, 0x67u}, - {0x92u, 0x18u}, - {0x94u, 0x01u}, - {0x96u, 0x02u}, - {0x98u, 0x10u}, - {0x99u, 0x28u}, - {0x9Au, 0x2Du}, - {0x9Bu, 0x02u}, - {0x9Du, 0x01u}, - {0xA0u, 0x80u}, - {0xA1u, 0x48u}, - {0xA3u, 0x04u}, - {0xA4u, 0x02u}, - {0xA9u, 0x20u}, - {0xABu, 0x08u}, - {0xB0u, 0x07u}, - {0xB1u, 0x0Eu}, - {0xB2u, 0x80u}, - {0xB3u, 0x10u}, - {0xB4u, 0x70u}, - {0xB5u, 0x60u}, - {0xB6u, 0x08u}, - {0xB7u, 0x01u}, - {0xBBu, 0x30u}, - {0xBEu, 0x44u}, + {0xE2u, 0x40u}, + {0xEAu, 0x40u}, + {0xECu, 0x80u}, + {0x80u, 0x10u}, + {0x84u, 0x0Eu}, + {0x89u, 0x01u}, + {0x8Au, 0x0Eu}, + {0x8Bu, 0x92u}, + {0x8Cu, 0x04u}, + {0x8Du, 0x19u}, + {0x8Fu, 0xA4u}, + {0x90u, 0x0Cu}, + {0x91u, 0x08u}, + {0x92u, 0x01u}, + {0x94u, 0x02u}, + {0x96u, 0x04u}, + {0x97u, 0x3Fu}, + {0x9Au, 0x0Bu}, + {0xA4u, 0x04u}, + {0xA7u, 0x04u}, + {0xA9u, 0x26u}, + {0xABu, 0x99u}, + {0xADu, 0x40u}, + {0xB0u, 0x10u}, + {0xB1u, 0x38u}, + {0xB3u, 0x40u}, + {0xB4u, 0x0Eu}, + {0xB5u, 0x07u}, + {0xB6u, 0x01u}, + {0xB7u, 0x80u}, + {0xBEu, 0x41u}, {0xBFu, 0x44u}, - {0xC0u, 0x24u}, - {0xC1u, 0x06u}, + {0xC0u, 0x26u}, + {0xC1u, 0x04u}, {0xC2u, 0x50u}, - {0xC5u, 0xCFu}, - {0xC6u, 0xD2u}, - {0xC7u, 0x0Eu}, + {0xC5u, 0xD2u}, + {0xC6u, 0xCEu}, + {0xC7u, 0x0Fu}, {0xC8u, 0x1Fu}, {0xC9u, 0xFFu}, {0xCAu, 0xFFu}, @@ -586,681 +815,449 @@ void cyfitter_cfg(void) {0xE8u, 0x40u}, {0xE9u, 0x40u}, {0xEEu, 0x08u}, - {0x00u, 0x88u}, + {0x00u, 0x80u}, {0x02u, 0x80u}, - {0x09u, 0x04u}, - {0x0Au, 0x44u}, - {0x11u, 0x02u}, + {0x03u, 0x28u}, + {0x04u, 0x08u}, + {0x07u, 0x10u}, + {0x09u, 0x20u}, + {0x0Bu, 0x60u}, {0x12u, 0x10u}, - {0x18u, 0x14u}, - {0x19u, 0xA1u}, - {0x1Au, 0x44u}, - {0x1Bu, 0x02u}, - {0x20u, 0x08u}, - {0x21u, 0x21u}, - {0x22u, 0x04u}, - {0x23u, 0x01u}, - {0x29u, 0x21u}, - {0x31u, 0x20u}, - {0x33u, 0x40u}, - {0x39u, 0xA2u}, - {0x3Bu, 0x08u}, - {0x40u, 0x04u}, - {0x42u, 0x40u}, - {0x48u, 0x54u}, - {0x49u, 0x80u}, - {0x4Au, 0x08u}, - {0x52u, 0x94u}, - {0x53u, 0x10u}, - {0x58u, 0x80u}, - {0x5Au, 0x2Au}, - {0x60u, 0x10u}, - {0x62u, 0x02u}, - {0x63u, 0x09u}, - {0x68u, 0x80u}, - {0x69u, 0x24u}, - {0x6Au, 0x80u}, - {0x71u, 0x84u}, - {0x73u, 0x44u}, - {0x81u, 0x05u}, - {0x82u, 0x04u}, - {0x87u, 0x1Cu}, - {0x8Du, 0x10u}, - {0x91u, 0x80u}, - {0x92u, 0x22u}, - {0x93u, 0x02u}, - {0x94u, 0x04u}, - {0x96u, 0x40u}, - {0x97u, 0x54u}, - {0x99u, 0x10u}, - {0x9Cu, 0x48u}, - {0x9Du, 0x25u}, - {0x9Eu, 0x29u}, - {0x9Fu, 0x0Cu}, - {0xA1u, 0x08u}, - {0xA2u, 0x02u}, - {0xA3u, 0x10u}, - {0xA5u, 0xE0u}, - {0xA6u, 0x0Cu}, - {0xABu, 0x10u}, - {0xACu, 0x02u}, - {0xADu, 0x04u}, - {0xAFu, 0x01u}, - {0xB5u, 0x02u}, - {0xC0u, 0x0Du}, + {0x13u, 0x08u}, + {0x19u, 0x52u}, + {0x1Bu, 0x20u}, + {0x20u, 0x42u}, + {0x21u, 0x31u}, + {0x22u, 0x08u}, + {0x23u, 0x40u}, + {0x28u, 0x02u}, + {0x29u, 0x18u}, + {0x33u, 0x09u}, + {0x38u, 0x50u}, + {0x39u, 0x20u}, + {0x40u, 0x40u}, + {0x41u, 0x10u}, + {0x48u, 0x41u}, + {0x49u, 0x19u}, + {0x50u, 0x04u}, + {0x52u, 0x10u}, + {0x53u, 0x80u}, + {0x59u, 0x02u}, + {0x5Au, 0xA8u}, + {0x60u, 0x04u}, + {0x62u, 0x4Au}, + {0x68u, 0x82u}, + {0x69u, 0x14u}, + {0x70u, 0x20u}, + {0x72u, 0x80u}, + {0x73u, 0x12u}, + {0x81u, 0x10u}, + {0x84u, 0x01u}, + {0x87u, 0x10u}, + {0x8Bu, 0x11u}, + {0x90u, 0x04u}, + {0x91u, 0x40u}, + {0x92u, 0xA0u}, + {0x95u, 0x26u}, + {0x97u, 0x4Cu}, + {0x99u, 0x04u}, + {0x9Cu, 0x41u}, + {0x9Du, 0x11u}, + {0x9Eu, 0x80u}, + {0x9Fu, 0x1Bu}, + {0xA5u, 0x28u}, + {0xA7u, 0xF0u}, + {0xA8u, 0x40u}, + {0xAAu, 0x10u}, + {0xACu, 0x40u}, + {0xAEu, 0x01u}, + {0xAFu, 0x04u}, + {0xB2u, 0x02u}, + {0xB7u, 0x10u}, + {0xC0u, 0x0Fu}, {0xC2u, 0x0Eu}, - {0xC4u, 0x0Cu}, - {0xCAu, 0x05u}, - {0xCCu, 0x0Cu}, - {0xCEu, 0x0Fu}, + {0xC4u, 0x04u}, + {0xCAu, 0x0Eu}, + {0xCCu, 0x03u}, + {0xCEu, 0x0Cu}, {0xD0u, 0x05u}, {0xD2u, 0x0Cu}, {0xD6u, 0x0Fu}, {0xD8u, 0x0Fu}, - {0xE0u, 0x01u}, - {0xE2u, 0x4Cu}, - {0xE4u, 0x02u}, - {0xE6u, 0x09u}, - {0xE8u, 0x40u}, + {0xE2u, 0x02u}, + {0xE6u, 0x21u}, + {0xE8u, 0x02u}, + {0xECu, 0x0Cu}, + {0x01u, 0x04u}, + {0x03u, 0x01u}, {0x04u, 0x24u}, - {0x06u, 0x49u}, - {0x0Cu, 0x24u}, - {0x0Eu, 0x12u}, - {0x0Fu, 0xFFu}, - {0x11u, 0xFFu}, - {0x12u, 0x04u}, - {0x15u, 0x96u}, + {0x05u, 0x10u}, + {0x06u, 0x12u}, + {0x0Bu, 0x04u}, + {0x0Eu, 0x18u}, + {0x0Fu, 0x04u}, + {0x10u, 0x40u}, + {0x13u, 0x03u}, + {0x15u, 0x10u}, {0x16u, 0x03u}, - {0x17u, 0x69u}, - {0x19u, 0x55u}, - {0x1Au, 0x64u}, - {0x1Bu, 0xAAu}, - {0x1Du, 0x33u}, - {0x1Eu, 0x18u}, - {0x1Fu, 0xCCu}, - {0x21u, 0x0Fu}, - {0x22u, 0x20u}, - {0x23u, 0xF0u}, - {0x27u, 0xFFu}, + {0x19u, 0x04u}, + {0x1Au, 0x24u}, + {0x1Bu, 0x02u}, + {0x1Du, 0x10u}, + {0x21u, 0x20u}, + {0x22u, 0x04u}, + {0x26u, 0x20u}, + {0x29u, 0x08u}, + {0x2Cu, 0x24u}, + {0x2Du, 0x10u}, + {0x2Eu, 0x09u}, + {0x30u, 0x38u}, + {0x31u, 0x07u}, {0x32u, 0x07u}, + {0x33u, 0x10u}, {0x34u, 0x40u}, - {0x35u, 0xFFu}, - {0x36u, 0x38u}, + {0x35u, 0x08u}, + {0x37u, 0x20u}, + {0x39u, 0x08u}, {0x3Eu, 0x10u}, - {0x3Fu, 0x10u}, + {0x3Fu, 0x54u}, {0x58u, 0x04u}, {0x59u, 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{0x98u, 0x30u}, + {0x99u, 0x0Cu}, + {0x9Au, 0x48u}, + {0x9Du, 0x01u}, + {0xA4u, 0x01u}, + {0xA6u, 0x06u}, + {0xA8u, 0x05u}, + {0xAAu, 0x02u}, + {0xACu, 0x28u}, + {0xAEu, 0x50u}, + {0xB1u, 0x0Eu}, + {0xB3u, 0x01u}, + {0xB4u, 0x78u}, + {0xB6u, 0x07u}, + {0xBAu, 0x80u}, + {0xBEu, 0x10u}, + {0xBFu, 0x04u}, {0xD8u, 0x0Bu}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x09u}, + {0xD9u, 0x0Bu}, + {0xDCu, 0x99u}, {0xDFu, 0x01u}, - {0x00u, 0x10u}, - {0x05u, 0x28u}, - {0x07u, 0x02u}, - {0x09u, 0x10u}, - {0x0Au, 0x02u}, - {0x0Bu, 0x20u}, - {0x0Du, 0x20u}, - {0x0Eu, 0x21u}, - {0x10u, 0x08u}, - {0x11u, 0x40u}, - {0x12u, 0x80u}, - {0x14u, 0x40u}, - {0x16u, 0x20u}, - {0x1Au, 0x01u}, - {0x1Eu, 0xA0u}, - {0x20u, 0x40u}, - {0x22u, 0x20u}, - {0x25u, 0x20u}, - {0x28u, 0x80u}, - {0x2Cu, 0x08u}, - {0x2Eu, 0x08u}, - {0x32u, 0x08u}, - {0x34u, 0x18u}, - {0x36u, 0x01u}, - {0x3Du, 0x20u}, - {0x3Fu, 0x08u}, - {0x5Cu, 0x02u}, - {0x5Fu, 0x94u}, - {0x7Fu, 0x80u}, - {0x81u, 0x50u}, - {0x82u, 0x20u}, - {0x83u, 0x04u}, - {0x86u, 0x40u}, - {0x88u, 0x50u}, - {0x8Au, 0x01u}, - {0x8Bu, 0x04u}, - {0x8Cu, 0x18u}, - {0x8Eu, 0x81u}, - {0x93u, 0x10u}, - {0x98u, 0x82u}, - {0x9Bu, 0x80u}, - {0xA3u, 0x80u}, - {0xB3u, 0x10u}, - {0xC0u, 0xE2u}, - {0xC2u, 0xE7u}, - {0xC4u, 0x3Bu}, - {0xCAu, 0x61u}, - {0xCCu, 0xE2u}, - {0xCEu, 0x60u}, - {0xD6u, 0xF0u}, - {0xDEu, 0x80u}, - {0xE0u, 0xF0u}, - {0xE4u, 0x24u}, - {0xEAu, 0x08u}, - {0xECu, 0x80u}, - {0xEEu, 0x09u}, - {0x83u, 0x80u}, - {0x84u, 0x02u}, - {0x98u, 0x80u}, - {0xA3u, 0x80u}, - {0xE2u, 0x0Cu}, - {0xE6u, 0x09u}, - {0x83u, 0x80u}, - {0x84u, 0x80u}, - {0xE6u, 0x02u}, - {0x80u, 0x01u}, - {0x94u, 0x02u}, - {0xB5u, 0x04u}, + {0x00u, 0x08u}, + {0x01u, 0x80u}, {0x05u, 0x05u}, - {0x06u, 0x0Au}, - {0x0Eu, 0x99u}, - {0x15u, 0x01u}, + {0x06u, 0x20u}, + {0x07u, 0x09u}, + {0x08u, 0x20u}, + {0x09u, 0x08u}, + {0x0Cu, 0x80u}, + {0x0Eu, 0x28u}, + {0x11u, 0x04u}, + {0x13u, 0x60u}, + {0x15u, 0x41u}, {0x17u, 0x14u}, - {0x1Du, 0x8Du}, + {0x18u, 0x04u}, + {0x19u, 0x80u}, + {0x1Du, 0x85u}, {0x1Eu, 0x02u}, - {0x1Fu, 0x1Au}, + {0x20u, 0x20u}, + {0x22u, 0x01u}, + {0x24u, 0x02u}, + {0x26u, 0x0Au}, {0x27u, 0x40u}, - {0x2Eu, 0x02u}, - {0x2Fu, 0x0Au}, - {0x36u, 0x6Au}, - {0x3Eu, 0x15u}, - {0x3Fu, 0x80u}, - {0x45u, 0xA8u}, - {0x4Cu, 0x01u}, - {0x4Du, 0x09u}, - {0x4Eu, 0x08u}, - {0x4Fu, 0x01u}, - {0x56u, 0xA8u}, - {0x57u, 0x40u}, - {0x66u, 0x10u}, - {0x6Cu, 0x10u}, - {0x6Du, 0x80u}, - {0x6Eu, 0x95u}, - {0x6Fu, 0x11u}, - {0x75u, 0x80u}, - {0x76u, 0x02u}, - {0x7Fu, 0x01u}, - {0x93u, 0x02u}, - {0x94u, 0x20u}, - {0x96u, 0x11u}, - {0x97u, 0x21u}, - {0x9Au, 0x10u}, - {0x9Bu, 0x04u}, - {0x9Du, 0x8Du}, - {0x9Eu, 0xAAu}, - {0x9Fu, 0x51u}, - {0xA1u, 0x20u}, - {0xA2u, 0x2Eu}, - {0xA5u, 0x40u}, - {0xA6u, 0x01u}, - {0xA7u, 0x48u}, - {0xC0u, 0xF0u}, - {0xC2u, 0xF0u}, - {0xC4u, 0x70u}, - {0xCAu, 0xB0u}, - {0xCCu, 0xF0u}, - {0xCEu, 0xF0u}, - {0xD0u, 0x70u}, - {0xD2u, 0x30u}, - {0xD8u, 0x20u}, - {0xDEu, 0x10u}, - {0xEEu, 0x0Au}, - {0x9Du, 0x20u}, - {0xEEu, 0x0Au}, - {0xB5u, 0x20u}, - {0xE8u, 0x10u}, - {0x33u, 0x80u}, + {0x2Cu, 0x81u}, + {0x2Fu, 0x28u}, + {0x31u, 0x08u}, + {0x32u, 0x41u}, + {0x33u, 0x18u}, + {0x37u, 0x65u}, + {0x38u, 0x08u}, + {0x3Du, 0x05u}, + {0x3Eu, 0xA0u}, + {0x78u, 0x02u}, + {0x7Eu, 0x80u}, + {0x90u, 0x08u}, + {0x91u, 0x45u}, + {0x92u, 0x80u}, + {0x93u, 0x40u}, + {0x94u, 0x04u}, + {0x98u, 0x23u}, + {0x9Au, 0x80u}, + {0x9Bu, 0x3Du}, + {0x9Du, 0x80u}, + {0x9Fu, 0x40u}, + {0xA0u, 0x84u}, + {0xA1u, 0x08u}, + {0xA2u, 0x94u}, + {0xA3u, 0x20u}, + {0xA4u, 0x10u}, + {0xA5u, 0x80u}, + {0xA6u, 0x0Bu}, + {0xA8u, 0x04u}, + {0xAEu, 0x40u}, + {0xB6u, 0x80u}, + {0xB7u, 0x01u}, + {0xC0u, 0xF5u}, + {0xC2u, 0xE6u}, + {0xC4u, 0xF7u}, + {0xCAu, 0xF0u}, + {0xCCu, 0xFFu}, + {0xCEu, 0xF2u}, + {0xDEu, 0x81u}, + {0xE8u, 0x04u}, + {0xECu, 0x80u}, + {0xEEu, 0x02u}, + {0xABu, 0x40u}, + {0xB0u, 0x04u}, + {0xECu, 0x80u}, + {0xEEu, 0x02u}, + {0x33u, 0x40u}, {0x36u, 0x40u}, - {0x56u, 0x08u}, - {0x58u, 0x04u}, - {0x5Eu, 0x02u}, - {0x62u, 0x02u}, - {0x66u, 0x04u}, - {0x82u, 0x04u}, + {0x58u, 0x08u}, + {0x5Cu, 0x01u}, + {0x5Du, 0x10u}, + {0x61u, 0x08u}, + {0x64u, 0x10u}, + {0x89u, 0x10u}, {0xCCu, 0x30u}, - {0xD4u, 0x40u}, - {0xD6u, 0xC0u}, + {0xD6u, 0xE0u}, {0xD8u, 0xC0u}, - {0xE2u, 0x80u}, - {0x52u, 0x20u}, + {0x59u, 0x40u}, {0x5Fu, 0x20u}, - {0x8Fu, 0x04u}, - {0x94u, 0x02u}, - {0x9Eu, 0x08u}, + {0x83u, 0x40u}, + {0x8Bu, 0x20u}, + {0x9Cu, 0x08u}, + {0x9Fu, 0x40u}, + {0xA5u, 0x08u}, {0xA6u, 0x40u}, - {0xA7u, 0x80u}, - {0xAAu, 0x01u}, - {0xACu, 0x04u}, - {0xAEu, 0x02u}, - {0xB4u, 0x01u}, - {0xD4u, 0x20u}, + {0xA8u, 0x01u}, + {0xACu, 0x10u}, + {0xD4u, 0x80u}, {0xD6u, 0x20u}, - {0xEAu, 0x50u}, - {0xEEu, 0x80u}, - {0x86u, 0x08u}, - {0x8Eu, 0x08u}, - {0x94u, 0x02u}, - {0x9Eu, 0x08u}, - {0xA3u, 0x04u}, - {0xA6u, 0x60u}, - {0xA7u, 0x80u}, - {0xABu, 0x20u}, - {0xE6u, 0x40u}, + {0xE6u, 0x80u}, {0xEAu, 0x80u}, + {0xEEu, 0x40u}, + {0x89u, 0x08u}, + {0x8Cu, 0x08u}, + {0x9Cu, 0x08u}, + {0xA5u, 0x08u}, + {0xA6u, 0x40u}, + {0xADu, 0x40u}, + {0xEEu, 0x10u}, {0x94u, 0x02u}, - {0x98u, 0x20u}, - {0xA3u, 0x04u}, - {0xA6u, 0x48u}, - {0xA7u, 0x80u}, - {0xAAu, 0x20u}, - {0xB0u, 0x20u}, - {0xEEu, 0x80u}, - {0x0Cu, 0x02u}, - {0x12u, 0x20u}, - {0x53u, 0x80u}, - {0x55u, 0x80u}, - {0x58u, 0x80u}, - {0x5Cu, 0x40u}, - {0x86u, 0x20u}, - {0xC2u, 0x04u}, + {0xA6u, 0x40u}, + {0xB4u, 0x01u}, + {0x08u, 0x80u}, + {0x0Fu, 0x40u}, + {0x12u, 0x80u}, + {0x53u, 0x04u}, + {0x57u, 0x80u}, + {0x5Bu, 0x20u}, + {0x5Cu, 0x10u}, + {0x84u, 0x80u}, + {0xC2u, 0x06u}, {0xC4u, 0x08u}, {0xD4u, 0x07u}, {0xD6u, 0x04u}, {0x01u, 0x20u}, - {0x06u, 0x40u}, - {0x07u, 0x08u}, - {0x08u, 0x02u}, - {0x0Bu, 0x08u}, - {0x0Du, 0x04u}, - {0x0Fu, 0x02u}, - {0x80u, 0x02u}, - {0x81u, 0x20u}, - {0x85u, 0x04u}, - {0x87u, 0x04u}, - {0x94u, 0x40u}, - {0x9Cu, 0x80u}, - {0xA0u, 0x02u}, - {0xA5u, 0x80u}, - {0xA7u, 0x80u}, + {0x06u, 0x80u}, + {0x07u, 0x01u}, + {0x09u, 0x01u}, + {0x0Au, 0x02u}, + {0x0Cu, 0x80u}, + {0x0Eu, 0x20u}, + {0x82u, 0x40u}, + {0x87u, 0x01u}, + {0x8Bu, 0x40u}, + {0x93u, 0x40u}, + {0x98u, 0x80u}, + {0xA4u, 0x80u}, + {0xABu, 0x80u}, + {0xAFu, 0x24u}, + {0xB2u, 0x80u}, + {0xB4u, 0x10u}, {0xC0u, 0x07u}, {0xC2u, 0x0Fu}, - {0x80u, 0x40u}, - {0x88u, 0x80u}, - {0x8Fu, 0x80u}, - {0x94u, 0x40u}, - {0x9Bu, 0x08u}, - {0x9Cu, 0x80u}, - {0xA5u, 0x80u}, - {0xA7u, 0x80u}, - {0xA8u, 0x02u}, - {0xAEu, 0x40u}, - {0xAFu, 0x01u}, - {0xE0u, 0x06u}, - {0x08u, 0x08u}, + {0xE2u, 0x04u}, + {0xE8u, 0x08u}, + {0xEAu, 0x01u}, + {0x92u, 0x02u}, + {0x96u, 0x80u}, + {0x9Au, 0x80u}, + {0xA1u, 0x01u}, + {0xB0u, 0x80u}, + {0xB2u, 0x10u}, + {0xB5u, 0x20u}, + {0xEAu, 0x0Du}, + {0x0Au, 0x80u}, {0x0Fu, 0x40u}, - {0xAFu, 0x08u}, - {0xB1u, 0x80u}, + {0x96u, 0x80u}, + {0xA9u, 0x01u}, + {0xAEu, 0x80u}, + {0xB2u, 0x01u}, {0xC2u, 0x0Cu}, - {0xE8u, 0x04u}, + {0xEAu, 0x04u}, {0x22u, 0x08u}, {0x24u, 0x02u}, {0x94u, 0x02u}, - {0x98u, 0x20u}, - {0xA3u, 0x04u}, + {0x9Eu, 0x20u}, {0xA6u, 0x08u}, - {0xAEu, 0x40u}, - {0xAFu, 0x80u}, + {0xAEu, 0x60u}, + {0xB2u, 0x08u}, {0xC8u, 0x60u}, - {0xEEu, 0x50u}, - {0x05u, 0x02u}, - {0x57u, 0x04u}, - {0x58u, 0x20u}, - {0x81u, 0x02u}, - {0x98u, 0x20u}, - {0xA3u, 0x04u}, + {0xE8u, 0x10u}, + {0xEEu, 0x40u}, + {0x06u, 0x20u}, + {0x53u, 0x01u}, + {0x5Du, 0x20u}, + {0x83u, 0x01u}, + {0x99u, 0x20u}, + {0x9Eu, 0x20u}, + {0xB1u, 0x20u}, {0xC0u, 0x20u}, - {0xD4u, 0xC0u}, - {0xE4u, 0x20u}, - {0xACu, 0x08u}, + {0xD4u, 0x80u}, + {0xD6u, 0x20u}, + {0xE6u, 0x20u}, {0xAFu, 0x40u}, {0x01u, 0x01u}, - {0x09u, 0x01u}, {0x0Bu, 0x01u}, {0x0Du, 0x01u}, + {0x0Fu, 0x01u}, {0x11u, 0x01u}, {0x1Bu, 0x01u}, {0x00u, 0x0Au}, @@ -1283,28 +1280,28 @@ void cyfitter_cfg(void) static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYREG_PRT1_DR), 16u}, - {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 512u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P3_U1_BASE), 1408u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1536u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), 2432u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u}, }; - /* UDB_1_1_1_CONFIG Address: CYDEV_UCFG_B1_P3_U0_BASE Size (bytes): 128 */ - static const uint8 CYCODE BS_UDB_1_1_1_CONFIG_VAL[] = { - 0x24u, 0xC0u, 0x10u, 0x02u, 0x11u, 0xC0u, 0x22u, 0x04u, 0x08u, 0xC0u, 0x00u, 0x08u, 0xDCu, 0x00u, 0x00u, 0x9Fu, - 0x0Cu, 0x00u, 0xD0u, 0x60u, 0xD0u, 0x7Fu, 0x0Cu, 0x80u, 0x30u, 0x00u, 0x0Fu, 0xFFu, 0xDCu, 0x90u, 0x00u, 0x40u, - 0x00u, 0xC0u, 0x80u, 0x01u, 0x21u, 0x00u, 0x1Eu, 0x00u, 0xD4u, 0x1Fu, 0x08u, 0x20u, 0x00u, 0x80u, 0x00u, 0x00u, - 0x30u, 0xFFu, 0x0Fu, 0x00u, 0x80u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x50u, 0x01u, - 0x26u, 0x03u, 0x10u, 0x00u, 0x05u, 0xDEu, 0xFBu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x08u, 0x04u, 0x08u, 0x08u, 0x09u, 0x99u, 0x00u, 0x01u, + /* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */ + static const uint8 CYCODE BS_UDB_1_2_1_CONFIG_VAL[] = { + 0x80u, 0x01u, 0x00u, 0x00u, 0x7Fu, 0x10u, 0x80u, 0x00u, 0xC0u, 0x08u, 0x04u, 0x21u, 0xC0u, 0x04u, 0x01u, 0x00u, + 0x00u, 0x01u, 0x60u, 0x00u, 0x00u, 0x07u, 0xFFu, 0x18u, 0x00u, 0x22u, 0x9Fu, 0x08u, 0xC0u, 0x40u, 0x02u, 0x00u, + 0x90u, 0x01u, 0x40u, 0x00u, 0x1Fu, 0x01u, 0x20u, 0x00u, 0xC0u, 0x40u, 0x08u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, + 0x00u, 0x3Fu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x82u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x01u, + 0x32u, 0x06u, 0x10u, 0x00u, 0x04u, 0xCBu, 0xFDu, 0x0Eu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ - {(void CYFAR *)(CYDEV_UCFG_B1_P3_U0_BASE), BS_UDB_1_1_1_CONFIG_VAL, 128u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P3_U0_BASE), BS_UDB_1_2_1_CONFIG_VAL, 128u}, }; uint8 CYDATA i; diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 099248a0..25148f44 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -478,34 +478,34 @@ .set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -513,9 +513,9 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB06_MSK -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB06_ST +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 .set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL @@ -530,31 +530,27 @@ .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F .set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK -.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL .set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL -.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL .set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB06_07_A0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB06_07_A1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB06_07_D0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB06_07_D1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB06_07_F0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB06_07_F1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB06_A0_A1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB06_A0 -.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB06_A1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB06_D0_D1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB06_D0 -.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB06_D1 -.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB06_F0_F1 -.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB06_F0 -.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB06_F1 -.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1 +.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL /* USBFS_dp_int */ .set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -569,24 +565,24 @@ /* SCSI_CTL_IO */ .set SCSI_CTL_IO_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_IO_Sync_ctrl_reg__0__POS, 0 -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL -.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL -.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL +.set SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL .set SCSI_CTL_IO_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL -.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK -.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK +.set SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL /* SCSI_In_DBx */ .set SCSI_In_DBx__0__AG, CYREG_PRT12_AG @@ -1045,8 +1041,8 @@ /* scsiTarget */ .set scsiTarget_StatusReg__0__MASK, 0x01 .set scsiTarget_StatusReg__0__POS, 0 -.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 .set scsiTarget_StatusReg__2__MASK, 0x04 @@ -1054,76 +1050,76 @@ .set scsiTarget_StatusReg__3__MASK, 0x08 .set scsiTarget_StatusReg__3__POS, 3 .set scsiTarget_StatusReg__MASK, 0x0F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST -.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST -.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK -.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL -.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL -.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB03_ST -.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK -.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK -.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK -.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB03_CTL -.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL -.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB03_CTL -.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL -.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB03_MSK -.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB03_04_A0 -.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB03_04_A1 -.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB03_04_D0 -.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB03_04_D1 -.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB03_04_F0 -.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB03_04_F1 -.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB03_A0_A1 -.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB03_A0 -.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB03_A1 -.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB03_D0_D1 -.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB03_D0 -.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB03_D1 -.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB03_F0_F1 -.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB03_F0 -.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB03_F1 -.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB14_MSK +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB14_ST +.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL +.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST +.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB13_MSK +.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL +.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB13_ST_CTL +.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB13_ST_CTL +.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB13_ST +.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL +.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK +.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK +.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL +.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB13_CTL +.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL +.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB13_CTL +.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL +.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB13_MSK +.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB13_14_A0 +.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB13_14_A1 +.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB13_14_D0 +.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB13_14_D1 +.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL +.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB13_14_F0 +.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB13_14_F1 +.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB13_A0_A1 +.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB13_A0 +.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB13_A1 +.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB13_D0_D1 +.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB13_D0 +.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB13_D1 +.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB13_ACTL +.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB13_F0_F1 +.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB13_F0 +.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB13_F1 +.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL /* SD_Clk_Ctl */ .set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL -.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL -.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL +.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL .set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL -.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK -.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK +.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL /* USBFS_ep_0 */ .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 962465cb..94834410 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -478,34 +478,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -513,9 +513,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL @@ -530,31 +530,27 @@ SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK -SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL -SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL /* USBFS_dp_int */ USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -569,24 +565,24 @@ USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_CTL_IO */ SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL -SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL -SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK -SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK +SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL /* SCSI_In_DBx */ SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG @@ -1045,8 +1041,8 @@ SD_Init_Clk__PM_STBY_MSK EQU 0x02 /* scsiTarget */ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1054,76 +1050,76 @@ scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__MASK EQU 0x0F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL /* SD_Clk_Ctl */ SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK -SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK +SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL /* USBFS_ep_0 */ USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index 05b91a04..d2068011 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -478,34 +478,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SDCard_BSPIM -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -513,9 +513,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL @@ -530,31 +530,27 @@ SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK -SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL -SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL ; USBFS_dp_int USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -569,24 +565,24 @@ USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_CTL_IO SCSI_CTL_IO_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_IO_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL -SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL -SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL -SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_IO_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL +SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL +SCSI_CTL_IO_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_CTL_IO_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL -SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK -SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_CTL_IO_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK +SCSI_CTL_IO_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL ; SCSI_In_DBx SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG @@ -1045,8 +1041,8 @@ SD_Init_Clk__PM_STBY_MSK EQU 0x02 ; scsiTarget scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1054,76 +1050,76 @@ scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__MASK EQU 0x0F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST -scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST -scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK -scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST -scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL -scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL -scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK -scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0 -scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1 -scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0 -scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1 -scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0 -scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1 -scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1 -scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0 -scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1 -scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1 -scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0 -scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1 -scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1 -scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0 -scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1 -scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB14_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB14_ST +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB13_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB13_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB13_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB13_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB13_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB13_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB13_MSK +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB13_14_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB13_14_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB13_14_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB13_14_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB13_14_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB13_14_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB13_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB13_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB13_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB13_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB13_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB13_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB13_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB13_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB13_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL ; SD_Clk_Ctl SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK -SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL -SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL -SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL +SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL +SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL -SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK -SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK +SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL ; USBFS_ep_0 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx index b9aff615..ad440cf0 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -103,7 +103,7 @@ - + @@ -112,6 +112,6 @@ - + \ No newline at end of file diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit index 3c24266f..99bdf8a7 100755 Binary files a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit differ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd index 37701597..6c18cab7 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd @@ -493,7 +493,7 @@ SD_Clk_Ctl No description available - 0x40006475 + 0x4000647A 0 0x1 @@ -514,7 +514,7 @@ SCSI_CTL_IO No description available - 0x40006470 + 0x4000647B 0 0x1 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index 430cf963..e342d20d 100755 Binary files a/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/config.c b/software/SCSI2SD/SCSI2SD.cydsn/config.c index 98578f99..9abdc676 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/config.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/config.c @@ -22,6 +22,7 @@ #include "scsi.h" #include "scsiPhy.h" +#include "disk.h" #include @@ -34,9 +35,9 @@ static Config shadow = 0, // SCSI ID " codesrc", // vendor (68k Apple Drive Setup: Set to " SEAGATE") " SCSI2SD", //prodId (68k Apple Drive Setup: Set to " ST225N") - " 3.2", // revision (68k Apple Drive Setup: Set to "1.0 ") + " 3.3", // revision (68k Apple Drive Setup: Set to "1.0 ") 1, // enable parity - 0, // disable unit attention, + 1, // enable unit attention, 0 // Max blocks (0 == disabled) // reserved bytes will be initialised to 0. }; @@ -194,7 +195,10 @@ void configPoll() shadow.reserved[21] = scsiDev.rstCount; shadow.reserved[22] = scsiDev.selCount; shadow.reserved[23] = scsiDev.msgCount; - shadow.reserved[24] = scsiDev.watchdogTick++; + shadow.reserved[24] = scsiDev.cmdCount; + shadow.reserved[25] = scsiDev.watchdogTick; + shadow.reserved[26] = blockDev.state; + shadow.reserved[27] = scsiReadDBxPins(); #endif USBFS_LoadInEP(USB_EP_IN, (uint8 *)&shadow, sizeof(shadow)); diff --git a/software/SCSI2SD/SCSI2SD.cydsn/disk.c b/software/SCSI2SD/SCSI2SD.cydsn/disk.c index cfd5b9ac..32b3bc39 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/disk.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/disk.c @@ -406,20 +406,15 @@ void scsiDiskPoll() transfer.currentBlock++; if (transfer.currentBlock >= transfer.blocks) { - int needComplete = transfer.multiBlock; scsiDev.phase = STATUS; scsiDiskReset(); - if (needComplete) - { - sdCompleteRead(); - } } } } else if (scsiDev.phase == DATA_OUT && transfer.currentBlock != transfer.blocks) { - int writeOk = sdWriteSector(); + sdWriteSector(); // TODO FIX scsiDiskPoll() scsiDev.dataPtr = 0; transfer.currentBlock++; if (transfer.currentBlock >= transfer.blocks) @@ -429,24 +424,32 @@ void scsiDiskPoll() scsiDev.phase = STATUS; scsiDiskReset(); - - if (writeOk) - { - sdCompleteWrite(); - } } } } void scsiDiskReset() { - // todo if SPI command in progress, cancel it. scsiDev.dataPtr = 0; scsiDev.savedDataPtr = 0; scsiDev.dataLen = 0; - transfer.lba = 0; + // transfer.lba = 0; // Needed in Request Sense to determine failure transfer.blocks = 0; transfer.currentBlock = 0; + + // Cancel long running commands! + if (transfer.inProgress == 1) + { + if (transfer.dir == TRANSFER_WRITE) + { + sdCompleteWrite(); + } + else + { + sdCompleteRead(); + } + } + transfer.inProgress = 0; transfer.multiBlock = 0; } @@ -454,6 +457,7 @@ void scsiDiskInit() { blockDev.bs = SCSI_BLOCK_SIZE; blockDev.capacity = 0; + transfer.inProgress = 0; scsiDiskReset(); // Don't require the host to send us a START STOP UNIT command diff --git a/software/SCSI2SD/SCSI2SD.cydsn/disk.h b/software/SCSI2SD/SCSI2SD.cydsn/disk.h index a58425f1..c7c2c80f 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/disk.h +++ b/software/SCSI2SD/SCSI2SD.cydsn/disk.h @@ -43,6 +43,7 @@ typedef struct { int dir; int multiBlock; // True if we're using a multi-block SPI transfer. + int inProgress; // True if we need to call sdComplete{Read|Write} uint32 lba; uint32 blocks; diff --git a/software/SCSI2SD/SCSI2SD.cydsn/inquiry.c b/software/SCSI2SD/SCSI2SD.cydsn/inquiry.c index 9cc8f8b0..d5a3d85f 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/inquiry.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/inquiry.c @@ -120,8 +120,6 @@ void scsiInquiry() sizeof(config->prodId) + sizeof(config->revision); scsiDev.phase = DATA_IN; - - if (!lun) scsiDev.unitAttention = 0; } } else if (pageCode == 0x00) diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsi.c b/software/SCSI2SD/SCSI2SD.cydsn/scsi.c index af9d1f74..bc8d8488 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/scsi.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/scsi.c @@ -48,12 +48,28 @@ static void doReserveRelease(void); static void enter_BusFree() { - scsiEnterPhase(BUS_FREE); + // TODO MPC3000 testing. + // 1,2us: Cannot see SCSI device. + // 5us: Can see SCSI device, format fails + // 10us: Format succeeds. + // 25us: Format fails. + CyDelayUs(10); + + - ledOff(); - scsiDev.phase = BUS_FREE; SCSI_ClearPin(SCSI_Out_BSY); + // We now have a Bus Clear Delay of 800ns to release remaining signals. + SCSI_ClearPin(SCSI_Out_MSG); + SCSI_ClearPin(SCSI_Out_CD); + SCSI_CTL_IO_Write(0); + + // Wait for the initiator to cease driving signals + // Bus settle delay + bus clear delay = 1200ns + CyDelayUs(2); + + ledOff(); + scsiDev.phase = BUS_FREE; } static void enter_MessageIn(uint8 message) @@ -89,13 +105,19 @@ static void enter_Status(uint8 status) { scsiDev.status = status; scsiDev.phase = STATUS; + + + #ifdef MM_DEBUG + scsiDev.lastStatus = scsiDev.status; + scsiDev.lastSense = scsiDev.sense.code; + #endif } static void process_Status() { scsiEnterPhase(STATUS); scsiWriteByte(scsiDev.status); - + #ifdef MM_DEBUG scsiDev.lastStatus = scsiDev.status; scsiDev.lastSense = scsiDev.sense.code; @@ -115,7 +137,7 @@ static void enter_DataIn(int len) static void process_DataIn() { uint32 len; - + if (scsiDev.dataLen > sizeof(scsiDev.data)) { scsiDev.dataLen = sizeof(scsiDev.data); @@ -139,7 +161,7 @@ static void process_DataIn() static void process_DataOut() { uint32 len; - + if (scsiDev.dataLen > sizeof(scsiDev.data)) { scsiDev.dataLen = sizeof(scsiDev.data); @@ -177,7 +199,7 @@ static void process_Command() int cmdSize; uint8 command; uint8 lun; - + scsiEnterPhase(COMMAND); scsiDev.parityError = 0; @@ -191,7 +213,20 @@ static void process_Command() command = scsiDev.cdb[0]; lun = scsiDev.cdb[1] >> 5; - if (scsiDev.parityError) + #ifdef MM_DEBUG + scsiDev.cmdCount++; + #endif + + if (scsiDev.resetFlag) + { +#ifdef MM_DEBUG + // Don't log bogus commands + scsiDev.cmdCount--; + memset(scsiDev.cdb, 0xff, sizeof(scsiDev.cdb)); +#endif + return; + } + else if (scsiDev.parityError) { scsiDev.sense.code = ABORTED_COMMAND; scsiDev.sense.asc = SCSI_PARITY_ERROR; @@ -210,26 +245,47 @@ static void process_Command() scsiDev.data[0] = 0xF0; scsiDev.data[2] = scsiDev.sense.code & 0x0F; - // TODO populate "information" field with requested LBA. - // TODO support more detailed sense data ? + scsiDev.data[3] = transfer.lba >> 24; + scsiDev.data[4] = transfer.lba >> 16; + scsiDev.data[5] = transfer.lba >> 8; + scsiDev.data[6] = transfer.lba; - scsiDev.data[12] = scsiDev.sense.asc >> 8; - scsiDev.data[13] = scsiDev.sense.asc; + // Additional bytes if there are errors to report + int responseLength; + if (scsiDev.sense.code == NO_SENSE) + { + responseLength = 8; + } + else + { + responseLength = 18; + scsiDev.data[7] = 10; // additional length + scsiDev.data[12] = scsiDev.sense.asc >> 8; + scsiDev.data[13] = scsiDev.sense.asc; + } // Silently truncate results. SCSI-2 spec 8.2.14. - enter_DataIn(allocLength < 18 ? allocLength : 18); + enter_DataIn( + (allocLength < responseLength) ? allocLength : responseLength + ); // This is a good time to clear out old sense information. scsiDev.sense.code = NO_SENSE; scsiDev.sense.asc = NO_ADDITIONAL_SENSE_INFORMATION; } // Some old SCSI drivers do NOT properly support - // unitAttention. OTOH, Linux seems to require it - // confirmed LCIII with unknown scsi driver fials here. + // unitAttention. eg. the Mac Plus would trigger a SCSI reset + // on receiving the unit attention response on boot, thus + // triggering another unit attention condition. else if (scsiDev.unitAttention && config->enableUnitAttention) { scsiDev.sense.code = UNIT_ATTENTION; scsiDev.sense.asc = scsiDev.unitAttention; + + // If initiator doesn't do REQUEST SENSE for the next command, then + // data is lost. + scsiDev.unitAttention = 0; + enter_Status(CHECK_CONDITION); } else if (lun) @@ -269,6 +325,7 @@ static void process_Command() { enter_Status(GOOD); } + } static void doReserveRelease() @@ -332,19 +389,13 @@ static void scsiReset() scsiDev.rstCount++; #endif ledOff(); - // done in verilog SCSI_Out_DBx_Write(0); - SCSI_CTL_IO_Write(0); - SCSI_ClearPin(SCSI_Out_ATN); - SCSI_ClearPin(SCSI_Out_BSY); - SCSI_ClearPin(SCSI_Out_ACK); - SCSI_ClearPin(SCSI_Out_RST); - SCSI_ClearPin(SCSI_Out_SEL); - SCSI_ClearPin(SCSI_Out_REQ); - SCSI_ClearPin(SCSI_Out_MSG); - SCSI_ClearPin(SCSI_Out_CD); + + scsiPhyReset(); scsiDev.parityError = 0; scsiDev.phase = BUS_FREE; + scsiDev.atnFlag = 0; + scsiDev.resetFlag = 0; if (scsiDev.unitAttention != POWER_ON_RESET) { @@ -364,8 +415,6 @@ static void scsiReset() // in which case TERMPWR cannot be supplied, and reset will ALWAYS // be true. CyDelay(10); // 10ms. - scsiDev.resetFlag = SCSI_ReadPin(SCSI_RST_INT); - scsiDev.atnFlag = 0; } static void enter_SelectionPhase() @@ -590,6 +639,11 @@ void scsiPoll(void) if (scsiDev.resetFlag) { scsiReset(); + if ((scsiDev.resetFlag = SCSI_ReadPin(SCSI_RST_INT))) + { + // Still in reset phase. Do not try and process any commands. + return; + } } switch (scsiDev.phase) diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsi.h b/software/SCSI2SD/SCSI2SD.cydsn/scsi.h index fe169544..9677a58a 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/scsi.h +++ b/software/SCSI2SD/SCSI2SD.cydsn/scsi.h @@ -109,6 +109,7 @@ typedef struct uint8 msgOut; #ifdef MM_DEBUG + uint8 cmdCount; uint8 selCount; uint8 rstCount; uint8 msgCount; diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c b/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c index f67f5f86..dfb4d887 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c @@ -20,6 +20,8 @@ #include "scsiPhy.h" #include "bits.h" +#define scsiTarget_AUX_CTL (* (reg8 *) scsiTarget_datapath__DP_AUX_CTL_REG) + CY_ISR_PROTO(scsiResetISR); CY_ISR(scsiResetISR) { @@ -42,9 +44,11 @@ uint8 scsiReadDBxPins() uint8 scsiReadByte(void) { - while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1)) {} + while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1) && + !scsiDev.resetFlag) {} CY_SET_REG8(scsiTarget_datapath__F0_REG, 0); - while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2)) {} + while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2) && + !scsiDev.resetFlag) {} return CY_GET_REG8(scsiTarget_datapath__F1_REG); } @@ -53,7 +57,7 @@ void scsiRead(uint8* data, uint32 count) int prep = 0; int i = 0; - while (i < count) + while (i < count && !scsiDev.resetFlag) { if (prep < count && (CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1)) { @@ -70,12 +74,14 @@ void scsiRead(uint8* data, uint32 count) void scsiWriteByte(uint8 value) { - while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1)) {} + while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1) && + !scsiDev.resetFlag) {} CY_SET_REG8(scsiTarget_datapath__F0_REG, value); // TODO maybe move this TX EMPTY check to scsiEnterPhase ? //while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 4)) {} - while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2)) {} + while (!(CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 2) && + !scsiDev.resetFlag) {} value = CY_GET_REG8(scsiTarget_datapath__F1_REG); } @@ -84,7 +90,7 @@ void scsiWrite(uint8* data, uint32 count) int prep = 0; int i = 0; - while (i < count) + while (i < count && !scsiDev.resetFlag) { if (prep < count && (CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG) & 1)) { @@ -139,6 +145,32 @@ void scsiEnterPhase(int phase) busSettleDelay(); } +void scsiPhyReset() +{ + // Set the Clear bits for both SCSI device FIFOs + scsiTarget_AUX_CTL = scsiTarget_AUX_CTL | 0x03; + + // Trigger RST outselves. It is connected to the datapath and will + // ensure it returns to the idle state. The datapath runs at the BUS clk + // speed (ie. same as the CPU), so we can be sure it is active for a sufficient + // duration. + SCSI_SetPin(SCSI_Out_RST); + + SCSI_CTL_IO_Write(0); + SCSI_ClearPin(SCSI_Out_ATN); + SCSI_ClearPin(SCSI_Out_BSY); + SCSI_ClearPin(SCSI_Out_ACK); + SCSI_ClearPin(SCSI_Out_RST); + SCSI_ClearPin(SCSI_Out_SEL); + SCSI_ClearPin(SCSI_Out_REQ); + SCSI_ClearPin(SCSI_Out_MSG); + SCSI_ClearPin(SCSI_Out_CD); + + // Allow the FIFOs to fill up again. + SCSI_ClearPin(SCSI_Out_RST); + scsiTarget_AUX_CTL = scsiTarget_AUX_CTL & ~(0x03); +} + void scsiPhyInit() { SCSI_RST_ISR_StartEx(scsiResetISR); diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.h b/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.h index 658c1dfd..94c47e29 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.h +++ b/software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.h @@ -30,6 +30,7 @@ // Contains the odd-parity flag for a given 8-bit value. extern const uint8 Lookup_OddParity[256]; +void scsiPhyReset(void); void scsiPhyInit(void); uint8 scsiReadByte(void); void scsiRead(uint8* data, uint32 count); diff --git a/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.v b/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.v index e820cd31..339cf568 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.v +++ b/software/SCSI2SD/SCSI2SD.cydsn/scsiTarget/scsiTarget.v @@ -159,7 +159,8 @@ always @(posedge op_clk) begin // Check that SCSI initiator is ready, and input FIFO is not empty, // and output FIFO is not full. // Note that output FIFO is unused in TX mode. - if (nACK & !f0_blk_stat && !f1_blk_stat) + if (!nRST) state <= STATE_IDLE; + else if (nACK & !f0_blk_stat && !f1_blk_stat) state <= STATE_FIFOLOAD; else state <= STATE_IDLE; @@ -169,22 +170,28 @@ always @(posedge op_clk) begin end STATE_FIFOLOAD: - state <= IO == IO_WRITE ? STATE_TX : STATE_READY; + if (!nRST) state <= STATE_IDLE; + else state <= IO == IO_WRITE ? STATE_TX : STATE_READY; STATE_TX: begin - state <= STATE_DESKEW_INIT; + if (!nRST) state <= STATE_IDLE; + else state <= STATE_DESKEW_INIT; data <= po; end - STATE_DESKEW_INIT: state <= STATE_DESKEW; + STATE_DESKEW_INIT: + if (!nRST) state <= STATE_IDLE; + else state <= STATE_DESKEW; STATE_DESKEW: - if(deskewComplete) state <= STATE_READY; + if (!nRST) state <= STATE_IDLE; + else if(deskewComplete) state <= STATE_READY; else state <= STATE_DESKEW; STATE_READY: - if (~nACK) state <= STATE_RX; + if (!nRST) state <= STATE_IDLE; + else if (~nACK) state <= STATE_RX; else state <= STATE_READY; STATE_RX: state <= STATE_IDLE; diff --git a/software/SCSI2SD/SCSI2SD.cydsn/sd.c b/software/SCSI2SD/SCSI2SD.cydsn/sd.c index bf2d12c1..95016883 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/sd.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/sd.c @@ -145,12 +145,16 @@ void sdPrepareRead() scsiDev.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; scsiDev.phase = STATUS; } + else + { + transfer.inProgress = 1; + } } static void doReadSector() { int prep, i, guard; - + // Wait for a start-block token. // Don't wait more than 100ms, which is the timeout recommended // in the standard. @@ -180,7 +184,10 @@ static void doReadSector() // Don't do a bus settle delay if we're already in the correct phase. if (transfer.currentBlock == 0) { + //scsiEnterPhase(DATA_OUT); + //CyDelayUs(200); scsiEnterPhase(DATA_IN); + //CyDelayUs(200); // TODO BLOODY SLOW INTERLEAVE } // Quickly seed the FIFO @@ -196,8 +203,8 @@ static void doReadSector() // This loop is critically important for performance. // We stream data straight from the SDCard fifos into the SCSI component // FIFO's. If the loop isn't fast enough, the transmit FIFO's will empty, - // and performance will suffer. Every clock cycle counts. - while (i < SCSI_BLOCK_SIZE) + // and performance will suffer. Every clock cycle counts. + while (i < SCSI_BLOCK_SIZE && !scsiDev.resetFlag) { uint8_t sdRxStatus = CY_GET_REG8(SDCard_RX_STATUS_PTR); uint8_t scsiStatus = CY_GET_REG8(scsiTarget_StatusReg__STATUS_REG); @@ -205,7 +212,7 @@ static void doReadSector() // Read from the SPIM fifo if there is room to stream the byte to the // SCSI fifos if((sdRxStatus & SDCard_STS_RX_FIFO_NOT_EMPTY) && - (scsiStatus & 1) // SCSI TX FIFO NOT FULL + (scsiDev.resetFlag || (scsiStatus & 1)) // SCSI TX FIFO NOT FULL ) { uint8_t val = CY_GET_REG8(SDCard_RXDATA_PTR); @@ -214,7 +221,7 @@ static void doReadSector() } // Byte has been sent out the SCSI interface. - if (scsiStatus & 2) // SCSI RX FIFO NOT EMPTY + if (scsiDev.resetFlag || (scsiStatus & 2)) // SCSI RX FIFO NOT EMPTY { CY_GET_REG8(scsiTarget_datapath__F1_REG); ++i; @@ -229,7 +236,7 @@ static void doReadSector() { CY_SET_REG8(SDCard_TXDATA_PTR, 0xFF); // Put a byte in the FIFO prep++; - } + } } sdSpiByte(0xFF); // CRC @@ -273,6 +280,8 @@ void sdReadSectorMulti() void sdCompleteRead() { + transfer.inProgress = 0; + // We cannot send even a single "padding" byte, as we normally would when // sending a command. If we've just finished reading the very last block // on the card, then reading an additional dummy byte will just trigger @@ -320,7 +329,7 @@ static void sdWaitWriteBusy() int sdWriteSector() { - int prep, i, guard; + int prep, i, guard; int result, maxWait; uint8 dataToken; @@ -349,13 +358,14 @@ int sdWriteSector() // SPIM fifos // See sdReadSector for comment on guard (FIFO size is really 5) if((guard - i < 4) && - (scsiStatus & 2)) // SCSI RX FIFO NOT EMPTY + (scsiDev.resetFlag || (scsiStatus & 2)) + ) // SCSI RX FIFO NOT EMPTY { uint8_t val = CY_GET_REG8(scsiTarget_datapath__F1_REG); CY_SET_REG8(SDCard_TXDATA_PTR, val); guard++; } - + // Byte has been sent out the SPIM interface. if (sdRxStatus & SDCard_STS_RX_FIFO_NOT_EMPTY) { @@ -364,13 +374,13 @@ int sdWriteSector() } if (prep < SCSI_BLOCK_SIZE && - (scsiStatus & 1) // SCSI TX FIFO NOT FULL + (scsiDev.resetFlag || (scsiStatus & 1)) // SCSI TX FIFO NOT FULL ) { // Trigger the SCSI component to read a byte CY_SET_REG8(scsiTarget_datapath__F0_REG, 0xFF); prep++; - } + } } sdSpiByte(0x00); // CRC @@ -405,6 +415,7 @@ int sdWriteSector() // Wait for the card to come out of busy. sdWaitWriteBusy(); + transfer.inProgress = 0; scsiDiskReset(); sdClearStatus(); @@ -425,8 +436,10 @@ int sdWriteSector() void sdCompleteWrite() { + transfer.inProgress = 0; + uint8 r1, r2; - + sdSpiByte(0xFD); // STOP TOKEN // Wait for the card to come out of busy. sdWaitWriteBusy(); @@ -674,5 +687,9 @@ void sdPrepareWrite() scsiDev.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; scsiDev.phase = STATUS; } + else + { + transfer.inProgress = 1; + } }