From: Michael McMaster Date: Fri, 30 May 2014 13:35:19 +0000 (+1000) Subject: Fix DMA transfer bug. X-Git-Tag: 3.5~7 X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=092541dd02c641563d43127d1d04075cc93d1e3e;p=SCSI2SD-V6.git Fix DMA transfer bug. --- diff --git a/readme.txt b/readme.txt index a57e4511..b6d848d3 100644 --- a/readme.txt +++ b/readme.txt @@ -45,15 +45,20 @@ Performance As currently implemented: -Sequential read: 2.5MB/s Sequential write: 900kb/sec +Transfer size: 512 2048 8192 65536 +------------------------------------------------------- +read: 2MB/s 2.1MB/s 2.5MB/s 2.6MB/s +write: 125kB/s 441kB/s 1.5MB/s 2.3MB/s +------------------------------------------------------- + Tested with a 16GB class 10 SD card, via the commands: # WRITE TEST - sudo dd bs=8192 count=100 if=/dev/zero of=/dev/sdX oflag=dsync + sudo dd bs=${SIZE} count=100 if=/dev/zero of=/dev/sdX oflag=dsync # READ TEST - sudo dd bs=8192 count=100 if=/dev/sdX of=/dev/null + sudo dd bs=${SIZE} count=100 if=/dev/sdX of=/dev/null Compatibility diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index bd7996bb..2ce57f82 100644 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -84,28 +84,28 @@ /* SCSI_CTL_PHASE */ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL /* SCSI_Out_Bits */ #define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u @@ -630,34 +630,34 @@ #define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL -#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u #define SDCard_BSPIM_RxStsReg__4__POS 4 #define SDCard_BSPIM_RxStsReg__5__MASK 0x20u @@ -665,13 +665,17 @@ #define SDCard_BSPIM_RxStsReg__6__MASK 0x40u #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u -#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK -#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB05_MSK +#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL +#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB05_ST #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u @@ -681,30 +685,28 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK -#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL -#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL -#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB04_05_D1 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB04_05_F0 -#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB04_05_F1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB04_A0_A1 -#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB04_A0 -#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB04_A1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB04_D0_D1 -#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB04_D0 -#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB04_D1 -#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1 -#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB04_F0 -#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB04_F1 +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB05_06_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB05_06_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB05_06_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB05_06_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB05_06_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB05_06_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB05_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB05_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB05_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB05_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB05_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB05_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB05_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB05_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB05_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB05_F1 +#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL /* USBFS_dp_int */ #define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -1183,17 +1185,6 @@ #define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 #define SD_Data_Clk__PM_STBY_MSK 0x01u -/* SD_Init_Clk */ -#define SD_Init_Clk__CFG0 CYREG_CLKDIST_DCFG3_CFG0 -#define SD_Init_Clk__CFG1 CYREG_CLKDIST_DCFG3_CFG1 -#define SD_Init_Clk__CFG2 CYREG_CLKDIST_DCFG3_CFG2 -#define SD_Init_Clk__CFG2_SRC_SEL_MASK 0x07u -#define SD_Init_Clk__INDEX 0x03u -#define SD_Init_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 -#define SD_Init_Clk__PM_ACT_MSK 0x08u -#define SD_Init_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 -#define SD_Init_Clk__PM_STBY_MSK 0x08u - /* timer_clock */ #define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0 #define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1 @@ -1208,8 +1199,8 @@ /* scsiTarget */ #define scsiTarget_StatusReg__0__MASK 0x01u #define scsiTarget_StatusReg__0__POS 0 -#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL -#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 #define scsiTarget_StatusReg__2__MASK 0x04u @@ -1219,9 +1210,9 @@ #define scsiTarget_StatusReg__4__MASK 0x10u #define scsiTarget_StatusReg__4__POS 4 #define scsiTarget_StatusReg__MASK 0x1Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB04_MSK -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB04_ST +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB00_MSK +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB00_ST #define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL #define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST #define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK @@ -1268,9 +1259,6 @@ #define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL #define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -/* SD_Clk_Ctl */ -#define SD_Clk_Ctl_Sync_ctrl_reg__REMOVED 1u - /* USBFS_ep_0 */ #define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index f2497a0b..081c1e28 100644 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -121,7 +121,7 @@ static void CyClockStartupError(uint8 errorCode) } #endif -#define CY_CFG_BASE_ADDR_COUNT 37u +#define CY_CFG_BASE_ADDR_COUNT 36u CYPACKED typedef struct { uint8 offset; @@ -193,8 +193,6 @@ static void ClockSetup(void) CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x58u); CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u); - CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0), 0x001Du); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0 + 0x2u), 0x19u); /* Configure ILO based on settings from Clock DWR */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); @@ -230,7 +228,7 @@ static void ClockSetup(void) CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x0Fu))); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x07u))); } @@ -383,39 +381,38 @@ void cyfitter_cfg(void) 0x40004502u, /* Base address: 0x40004500 Count: 2 */ 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ 0x4000520Au, /* Base address: 0x40005200 Count: 10 */ - 0x40006401u, /* Base address: 0x40006400 Count: 1 */ - 0x40006501u, /* Base address: 0x40006500 Count: 1 */ - 0x40010052u, /* Base address: 0x40010000 Count: 82 */ - 0x40010139u, /* Base address: 0x40010100 Count: 57 */ - 0x40010241u, /* Base address: 0x40010200 Count: 65 */ - 0x4001035Cu, /* Base address: 0x40010300 Count: 92 */ - 0x40010417u, /* Base address: 0x40010400 Count: 23 */ - 0x40010560u, /* Base address: 0x40010500 Count: 96 */ - 0x4001065Du, /* Base address: 0x40010600 Count: 93 */ - 0x40010754u, /* Base address: 0x40010700 Count: 84 */ - 0x40010804u, /* Base address: 0x40010800 Count: 4 */ - 0x4001090Eu, /* Base address: 0x40010900 Count: 14 */ - 0x40010B12u, /* Base address: 0x40010B00 Count: 18 */ - 0x40010C47u, /* Base address: 0x40010C00 Count: 71 */ - 0x40010D45u, /* Base address: 0x40010D00 Count: 69 */ - 0x40010F05u, /* Base address: 0x40010F00 Count: 5 */ - 0x40011505u, /* Base address: 0x40011500 Count: 5 */ - 0x4001164Cu, /* Base address: 0x40011600 Count: 76 */ - 0x4001174Bu, /* Base address: 0x40011700 Count: 75 */ - 0x4001190Au, /* Base address: 0x40011900 Count: 10 */ - 0x40011B03u, /* Base address: 0x40011B00 Count: 3 */ - 0x40014019u, /* Base address: 0x40014000 Count: 25 */ - 0x40014117u, /* Base address: 0x40014100 Count: 23 */ - 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */ - 0x4001430Du, /* Base address: 0x40014300 Count: 13 */ - 0x4001440Du, /* Base address: 0x40014400 Count: 13 */ - 0x40014516u, /* Base address: 0x40014500 Count: 22 */ - 0x40014608u, /* Base address: 0x40014600 Count: 8 */ - 0x40014705u, /* Base address: 0x40014700 Count: 5 */ + 0x40006402u, /* Base address: 0x40006400 Count: 2 */ + 0x4001004Bu, /* Base address: 0x40010000 Count: 75 */ + 0x40010138u, /* Base address: 0x40010100 Count: 56 */ + 0x40010248u, /* Base address: 0x40010200 Count: 72 */ + 0x4001035Au, /* Base address: 0x40010300 Count: 90 */ + 0x40010462u, /* Base address: 0x40010400 Count: 98 */ + 0x40010551u, /* Base address: 0x40010500 Count: 81 */ + 0x40010657u, /* Base address: 0x40010600 Count: 87 */ + 0x40010752u, /* Base address: 0x40010700 Count: 82 */ + 0x4001090Au, /* Base address: 0x40010900 Count: 10 */ + 0x40010A04u, /* Base address: 0x40010A00 Count: 4 */ + 0x40010B1Au, /* Base address: 0x40010B00 Count: 26 */ + 0x40010C3Eu, /* Base address: 0x40010C00 Count: 62 */ + 0x40010D42u, /* Base address: 0x40010D00 Count: 66 */ + 0x40010F06u, /* Base address: 0x40010F00 Count: 6 */ + 0x40011506u, /* Base address: 0x40011500 Count: 6 */ + 0x40011652u, /* Base address: 0x40011600 Count: 82 */ + 0x4001174Eu, /* Base address: 0x40011700 Count: 78 */ + 0x40011907u, /* Base address: 0x40011900 Count: 7 */ + 0x40011B05u, /* Base address: 0x40011B00 Count: 5 */ + 0x40014017u, /* Base address: 0x40014000 Count: 23 */ + 0x40014116u, /* Base address: 0x40014100 Count: 22 */ + 0x40014210u, /* Base address: 0x40014200 Count: 16 */ + 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */ + 0x4001440Cu, /* Base address: 0x40014400 Count: 12 */ + 0x40014518u, /* Base address: 0x40014500 Count: 24 */ + 0x40014607u, /* Base address: 0x40014600 Count: 7 */ + 0x4001470Au, /* Base address: 0x40014700 Count: 10 */ 0x40014807u, /* Base address: 0x40014800 Count: 7 */ - 0x4001490Au, /* Base address: 0x40014900 Count: 10 */ + 0x40014909u, /* Base address: 0x40014900 Count: 9 */ 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */ - 0x40015005u, /* Base address: 0x40015000 Count: 5 */ + 0x40015006u, /* Base address: 0x40015000 Count: 6 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; @@ -423,205 +420,204 @@ void cyfitter_cfg(void) {0x36u, 0x02u}, {0x7Eu, 0x02u}, {0x01u, 0x20u}, - {0x0Au, 0x1Bu}, - {0x00u, 0x14u}, - {0x01u, 0x01u}, + {0x0Au, 0x4Bu}, + {0x00u, 0x05u}, + {0x01u, 0x13u}, {0x18u, 0x0Cu}, {0x19u, 0x08u}, {0x1Cu, 0x61u}, - {0x20u, 0x60u}, - {0x21u, 0xC0u}, + {0x20u, 0x90u}, + {0x21u, 0x58u}, {0x30u, 0x06u}, {0x31u, 0x0Cu}, {0x7Cu, 0x40u}, {0x23u, 0x02u}, {0x86u, 0x0Fu}, - {0x00u, 0x03u}, {0x01u, 0x09u}, - {0x02u, 0x0Cu}, {0x03u, 0x24u}, - {0x04u, 0x09u}, - {0x06u, 0x06u}, - {0x07u, 0x09u}, - {0x08u, 0xFFu}, - {0x09u, 0x40u}, - {0x0Cu, 0x90u}, - {0x0Eu, 0x60u}, - {0x0Fu, 0x30u}, - {0x10u, 0xFFu}, - {0x11u, 0x09u}, - {0x13u, 0x12u}, - {0x14u, 0x05u}, - {0x15u, 0x40u}, - {0x16u, 0x0Au}, + {0x05u, 0x09u}, + {0x06u, 0x0Eu}, + {0x07u, 0x12u}, + {0x0Bu, 0x30u}, + {0x0Cu, 0x21u}, + {0x0Eu, 0x84u}, + {0x0Fu, 0x46u}, + {0x12u, 0x21u}, + {0x16u, 0xC0u}, + {0x18u, 0x21u}, + {0x1Au, 0x42u}, {0x1Bu, 0x01u}, - {0x1Cu, 0x0Fu}, - {0x1Eu, 0xF0u}, - {0x1Fu, 0x06u}, - {0x20u, 0x50u}, - {0x22u, 0xA0u}, - {0x23u, 0x08u}, - {0x25u, 0x80u}, - {0x26u, 0xFFu}, - {0x29u, 0x40u}, - {0x2Cu, 0x30u}, - {0x2Du, 0x40u}, - {0x2Eu, 0xC0u}, - {0x31u, 0x38u}, - {0x32u, 0xFFu}, - {0x33u, 0x40u}, - {0x35u, 0x80u}, - {0x37u, 0x07u}, - {0x39u, 0x08u}, - {0x3Eu, 0x04u}, - {0x3Fu, 0x14u}, + {0x1Eu, 0x20u}, + {0x1Fu, 0x08u}, + {0x21u, 0x40u}, + {0x22u, 0x10u}, + {0x23u, 0x80u}, + {0x26u, 0x01u}, + {0x2Bu, 0x80u}, + {0x2Cu, 0x08u}, + {0x2Eu, 0x10u}, + {0x2Fu, 0x09u}, + {0x30u, 0x18u}, + {0x31u, 0x07u}, + {0x32u, 0xE0u}, + {0x33u, 0xC0u}, + {0x34u, 0x07u}, + {0x35u, 0x38u}, + {0x3Eu, 0x01u}, + {0x3Fu, 0x04u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Cu, 0x10u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x11u}, {0x5Fu, 0x01u}, - {0x81u, 0x10u}, - {0x83u, 0x20u}, - {0x85u, 0x43u}, - {0x86u, 0xC1u}, + {0x80u, 0x30u}, + {0x81u, 0x01u}, + {0x82u, 0xC0u}, + {0x84u, 0x09u}, + {0x85u, 0x02u}, + {0x86u, 0x06u}, {0x87u, 0x04u}, - {0x89u, 0x45u}, - {0x8Au, 0x04u}, + {0x88u, 0xFFu}, {0x8Bu, 0x02u}, - {0x8Du, 0x08u}, - {0x8Eu, 0x02u}, - {0x90u, 0x24u}, - {0x91u, 0x41u}, - {0x92u, 0x90u}, - {0x93u, 0x06u}, - {0x95u, 0x04u}, - {0x96u, 0x24u}, - {0x97u, 0x03u}, - {0x9Au, 0x18u}, - {0x9Fu, 0x10u}, - {0xA0u, 0x01u}, - {0xA2u, 0x02u}, - {0xA6u, 0x20u}, - {0xA8u, 0x24u}, - {0xAAu, 0x48u}, - {0xABu, 0x20u}, - {0xB1u, 0x08u}, - {0xB2u, 0xE0u}, - {0xB3u, 0x07u}, - {0xB4u, 0x1Cu}, - {0xB5u, 0x30u}, - {0xB6u, 0x03u}, - {0xB7u, 0x40u}, - {0xBBu, 0x08u}, + {0x8Cu, 0x50u}, + {0x8Du, 0x02u}, + {0x8Eu, 0xA0u}, + {0x8Fu, 0x08u}, + {0x91u, 0x01u}, + {0x94u, 0x03u}, + {0x96u, 0x0Cu}, + {0x97u, 0x0Cu}, + {0x98u, 0x90u}, + {0x9Au, 0x60u}, + {0x9Cu, 0xFFu}, + {0x9Fu, 0x02u}, + {0xA4u, 0x05u}, + {0xA5u, 0x01u}, + {0xA6u, 0x0Au}, + {0xA9u, 0x01u}, + {0xAAu, 0xFFu}, + {0xACu, 0x0Fu}, + {0xAEu, 0xF0u}, + {0xB5u, 0x0Eu}, + {0xB6u, 0xFFu}, + {0xB7u, 0x01u}, + {0xB9u, 0x80u}, {0xBEu, 0x40u}, - {0xBFu, 0x51u}, + {0xBFu, 0x40u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDCu, 0x01u}, + {0xDCu, 0x10u}, {0xDFu, 0x01u}, - {0x00u, 0x80u}, - {0x02u, 0xA0u}, - {0x03u, 0x08u}, - {0x05u, 0x14u}, - {0x07u, 0x01u}, - {0x08u, 0x40u}, - {0x09u, 0x05u}, - {0x0Au, 0x01u}, - {0x0Du, 0x25u}, - {0x0Fu, 0x08u}, - {0x11u, 0x84u}, - {0x12u, 0x04u}, - {0x13u, 0x22u}, - {0x14u, 0x40u}, - {0x15u, 0x20u}, - {0x16u, 0x20u}, - {0x18u, 0x10u}, - {0x1Du, 0x24u}, - {0x1Eu, 0x20u}, - {0x1Fu, 0x80u}, - {0x20u, 0x20u}, - {0x22u, 0xD0u}, - {0x23u, 0xC0u}, - {0x24u, 0x40u}, - {0x25u, 0x80u}, - {0x26u, 0x04u}, - {0x27u, 0x28u}, - {0x28u, 0x08u}, - {0x2Au, 0x02u}, - {0x2Bu, 0x22u}, - {0x2Cu, 0x04u}, - {0x31u, 0x01u}, - {0x32u, 0x44u}, - {0x33u, 0x10u}, - {0x36u, 0x06u}, - {0x37u, 0x80u}, - {0x38u, 0x10u}, - {0x39u, 0x0Au}, - {0x3Bu, 0x40u}, + {0x00u, 0x88u}, + {0x03u, 0x20u}, + {0x05u, 0x20u}, + {0x06u, 0x42u}, + {0x07u, 0x60u}, + {0x08u, 0x01u}, + {0x0Au, 0x24u}, + {0x0Bu, 0x01u}, + {0x0Eu, 0x08u}, + {0x0Fu, 0x22u}, + {0x11u, 0x44u}, + {0x12u, 0x40u}, + {0x15u, 0xC0u}, + {0x16u, 0x01u}, + {0x17u, 0x18u}, + {0x19u, 0x02u}, + {0x1Au, 0x20u}, + {0x1Bu, 0x30u}, + {0x1Eu, 0x01u}, + {0x20u, 0x40u}, + {0x21u, 0x18u}, + {0x22u, 0x01u}, + {0x24u, 0x02u}, + {0x27u, 0x08u}, + {0x28u, 0x05u}, + {0x29u, 0x40u}, + {0x2Au, 0x11u}, + {0x2Du, 0x08u}, + {0x2Eu, 0x10u}, + {0x30u, 0xA0u}, + {0x35u, 0x40u}, + {0x36u, 0x02u}, + {0x37u, 0x08u}, + {0x38u, 0x44u}, + {0x39u, 0x22u}, + {0x3Cu, 0x80u}, + {0x3Du, 0x10u}, {0x3Eu, 0x05u}, - {0x3Fu, 0x90u}, - {0x46u, 0x40u}, - {0x47u, 0x01u}, - {0x86u, 0x20u}, - {0x87u, 0x02u}, - {0x88u, 0x08u}, - {0x8Cu, 0x40u}, - {0x8Du, 0x01u}, - {0x8Fu, 0x08u}, - {0xC0u, 0xEFu}, - {0xC2u, 0x7Du}, - {0xC4u, 0x7Du}, - {0xCAu, 0x2Fu}, - {0xCCu, 0xDFu}, + {0x58u, 0x82u}, + {0x59u, 0x14u}, + {0x61u, 0x80u}, + {0x81u, 0x10u}, + {0x82u, 0x80u}, + {0x84u, 0x04u}, + {0x89u, 0x10u}, + {0x8Cu, 0x01u}, + {0xC0u, 0xF5u}, + {0xC2u, 0xEFu}, + {0xC4u, 0xEDu}, + {0xCAu, 0x6Du}, + {0xCCu, 0xDCu}, {0xCEu, 0xFFu}, - {0xE2u, 0x08u}, - {0xE6u, 0x72u}, - {0x21u, 0x01u}, - {0x35u, 0x01u}, - {0x3Fu, 0x10u}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x08u}, + {0xE2u, 0x48u}, + {0xE6u, 0x02u}, + {0x06u, 0xFFu}, + {0x08u, 0xFFu}, + {0x0Cu, 0x50u}, + {0x0Du, 0x04u}, + {0x0Eu, 0xA0u}, + {0x0Fu, 0x03u}, + {0x11u, 0x01u}, + {0x12u, 0xFFu}, + {0x13u, 0x06u}, + {0x14u, 0x03u}, + {0x15u, 0x03u}, + {0x16u, 0x0Cu}, + {0x17u, 0x04u}, + {0x18u, 0x60u}, + {0x19u, 0x05u}, + {0x1Au, 0x90u}, + {0x1Bu, 0x02u}, + {0x1Cu, 0x0Fu}, + {0x1Eu, 0xF0u}, + {0x24u, 0x05u}, + {0x26u, 0x0Au}, + {0x28u, 0x06u}, + {0x2Au, 0x09u}, + {0x2Cu, 0x30u}, + {0x2Eu, 0xC0u}, + {0x32u, 0xFFu}, + {0x37u, 0x07u}, + {0x3Bu, 0x80u}, + {0x3Eu, 0x04u}, + {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Bu, 0x04u}, {0x5Fu, 0x01u}, - {0x80u, 0x80u}, - {0x81u, 0x40u}, - {0x84u, 0x02u}, - {0x85u, 0x01u}, - {0x8Au, 0x1Fu}, - {0x8Bu, 0x20u}, - {0x8Cu, 0x5Bu}, - {0x8Du, 0x80u}, - {0x8Eu, 0x24u}, - {0x94u, 0x03u}, - {0x95u, 0x08u}, - {0x96u, 0x0Cu}, - {0x97u, 0x12u}, - {0x98u, 0x58u}, - {0x99u, 0x0Bu}, - {0x9Au, 0x24u}, - {0x9Bu, 0x24u}, - {0xA0u, 0x0Cu}, - {0xA1u, 0x34u}, - {0xA2u, 0x40u}, - {0xA3u, 0x0Bu}, - {0xA6u, 0x01u}, - {0xA8u, 0x40u}, - {0xAAu, 0x37u}, - {0xABu, 0x3Fu}, - {0xB0u, 0x1Fu}, - {0xB1u, 0x80u}, - {0xB2u, 0x20u}, - {0xB3u, 0x38u}, - {0xB4u, 0x80u}, - {0xB5u, 0x07u}, - {0xB6u, 0x40u}, - {0xB7u, 0x40u}, - {0xBEu, 0x54u}, - {0xBFu, 0x41u}, - {0xC0u, 0x64u}, + {0x82u, 0x3Fu}, + {0x84u, 0x01u}, + {0x89u, 0x01u}, + {0x8Cu, 0x34u}, + {0x8Eu, 0x4Bu}, + {0x98u, 0x0Bu}, + {0x9Au, 0x64u}, + {0x9Cu, 0x08u}, + {0x9Eu, 0x52u}, + {0xA6u, 0x20u}, + {0xB2u, 0x40u}, + {0xB4u, 0x07u}, + {0xB6u, 0x38u}, + {0xB7u, 0x01u}, + {0xBEu, 0x04u}, + {0xBFu, 0x40u}, + {0xC0u, 0x54u}, {0xC1u, 0x02u}, {0xC2u, 0x30u}, - {0xC5u, 0xCDu}, - {0xC6u, 0x2Eu}, - {0xC7u, 0x0Fu}, + {0xC5u, 0xE2u}, + {0xC6u, 0xCFu}, + {0xC7u, 0x0Du}, {0xC8u, 0x1Fu}, {0xC9u, 0xFFu}, {0xCAu, 0xFFu}, @@ -632,7 +628,7 @@ void cyfitter_cfg(void) {0xD9u, 0x04u}, {0xDAu, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x11u}, + {0xDCu, 0x01u}, {0xDDu, 0x01u}, {0xDFu, 0x01u}, {0xE2u, 0xC0u}, @@ -640,891 +636,944 @@ void cyfitter_cfg(void) {0xE8u, 0x40u}, {0xE9u, 0x40u}, {0xEEu, 0x08u}, - {0x00u, 0x02u}, - {0x01u, 0x08u}, - {0x03u, 0x0Au}, - {0x09u, 0x20u}, - {0x0Bu, 0x20u}, - {0x10u, 0x80u}, - {0x11u, 0x04u}, - {0x12u, 0x08u}, - {0x18u, 0x04u}, - {0x19u, 0x42u}, - {0x1Au, 0x10u}, - {0x1Bu, 0x02u}, - {0x21u, 0x34u}, - {0x22u, 0x09u}, - {0x23u, 0x05u}, - {0x27u, 0x04u}, - {0x29u, 0x02u}, - {0x2Bu, 0x08u}, - {0x2Cu, 0x08u}, - {0x2Du, 0x20u}, - {0x2Fu, 0x80u}, - {0x31u, 0x20u}, - {0x32u, 0x08u}, - {0x38u, 0x20u}, - {0x39u, 0x85u}, - {0x41u, 0x11u}, - {0x42u, 0x10u}, - {0x43u, 0x02u}, - {0x48u, 0x90u}, - {0x49u, 0x08u}, - {0x4Au, 0x08u}, - {0x50u, 0x58u}, - {0x5Au, 0xA2u}, - {0x5Bu, 0x04u}, - {0x60u, 0x44u}, - {0x61u, 0x08u}, - {0x63u, 0x01u}, - {0x69u, 0x10u}, - {0x6Au, 0x40u}, - {0x6Bu, 0x50u}, - {0x6Du, 0x64u}, - {0x71u, 0x10u}, - {0x72u, 0x22u}, - {0x73u, 0x40u}, - {0x81u, 0x40u}, - {0x82u, 0x40u}, - {0x87u, 0x80u}, - {0x89u, 0x05u}, - {0x8Au, 0x80u}, - {0x8Bu, 0x80u}, - {0x8Cu, 0x08u}, + {0x00u, 0x80u}, + {0x02u, 0x40u}, + {0x03u, 0x10u}, + {0x05u, 0x20u}, + {0x06u, 0x02u}, + {0x07u, 0x10u}, + {0x0Au, 0x05u}, + {0x0Cu, 0x01u}, + {0x0Du, 0x40u}, + {0x0Eu, 0x08u}, + {0x0Fu, 0x20u}, + {0x13u, 0x04u}, + {0x14u, 0x08u}, + {0x16u, 0x01u}, + {0x17u, 0x68u}, + {0x18u, 0x14u}, + {0x19u, 0x40u}, + {0x1Au, 0x0Du}, + {0x1Bu, 0x80u}, + {0x1Eu, 0x10u}, + {0x22u, 0x40u}, + {0x25u, 0x40u}, + {0x28u, 0x01u}, + {0x29u, 0x04u}, + {0x2Bu, 0x21u}, + {0x35u, 0x11u}, + {0x36u, 0x08u}, + {0x3Au, 0x20u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x80u}, + {0x40u, 0x14u}, + {0x41u, 0x01u}, + {0x49u, 0x40u}, + {0x4Au, 0x40u}, + {0x4Bu, 0x04u}, + {0x51u, 0x10u}, + {0x52u, 0x80u}, + {0x53u, 0x28u}, + {0x58u, 0x14u}, + {0x59u, 0x02u}, + {0x5Au, 0x80u}, + {0x60u, 0x02u}, + {0x62u, 0x04u}, + {0x63u, 0x88u}, + {0x68u, 0x80u}, + {0x69u, 0x54u}, + {0x70u, 0x20u}, + {0x73u, 0x51u}, + {0x83u, 0x04u}, + {0x84u, 0x80u}, + {0x86u, 0x42u}, + {0x88u, 0x02u}, + {0x89u, 0x02u}, + {0x8Cu, 0x04u}, {0x8Du, 0x40u}, - {0x8Fu, 0x08u}, - {0x90u, 0x40u}, - {0x92u, 0x20u}, - {0x93u, 0x20u}, - {0x94u, 0x80u}, - {0x95u, 0x2Eu}, - {0x96u, 0x0Du}, - {0x97u, 0x10u}, - {0x9Au, 0x44u}, - {0x9Bu, 0x80u}, - {0x9Cu, 0x08u}, - {0x9Du, 0x11u}, - {0x9Eu, 0x22u}, - {0x9Fu, 0x12u}, - {0xA1u, 0x80u}, - {0xA2u, 0x90u}, - {0xA3u, 0x04u}, - {0xA4u, 0x48u}, - {0xA5u, 0x44u}, - {0xA6u, 0x02u}, - {0xA7u, 0x20u}, - {0xABu, 0x40u}, - {0xACu, 0x10u}, - {0xAFu, 0x91u}, - {0xB0u, 0x04u}, - {0xB7u, 0x08u}, - {0xC0u, 0x0Fu}, - {0xC2u, 0x06u}, - {0xC4u, 0x0Eu}, - {0xCAu, 0x85u}, - {0xCCu, 0x06u}, - {0xCEu, 0x0Fu}, + {0x92u, 0x02u}, + {0x94u, 0x04u}, + {0x95u, 0x96u}, + {0x96u, 0x14u}, + {0x97u, 0x81u}, + {0x9Au, 0x30u}, + {0x9Bu, 0x08u}, + {0x9Cu, 0x80u}, + {0x9Du, 0x6Cu}, + {0x9Eu, 0x02u}, + {0x9Fu, 0x70u}, + {0xA0u, 0x04u}, + {0xA3u, 0x10u}, + {0xA4u, 0xE0u}, + {0xA5u, 0x80u}, + {0xA6u, 0x86u}, + {0xA7u, 0x09u}, + {0xAAu, 0x30u}, + {0xAFu, 0x40u}, + {0xB0u, 0x02u}, + {0xB1u, 0x0Au}, + {0xB3u, 0x08u}, + {0xC0u, 0xEDu}, + {0xC2u, 0xF3u}, + {0xC4u, 0xE4u}, + {0xCCu, 0xE0u}, + {0xCEu, 0x14u}, {0xD0u, 0x07u}, - {0xD2u, 0x04u}, + {0xD2u, 0x08u}, {0xD6u, 0x0Fu}, {0xD8u, 0x0Fu}, - {0xE2u, 0x20u}, - {0xE6u, 0x09u}, - {0xEAu, 0x06u}, - {0xEEu, 0x02u}, - {0x85u, 0x02u}, - {0x87u, 0x05u}, - {0x8Fu, 0x02u}, - {0x97u, 0x03u}, - {0x9Au, 0x01u}, - {0x9Fu, 0x0Cu}, - {0xA1u, 0x02u}, - {0xA2u, 0x04u}, - {0xA3u, 0x08u}, - {0xA4u, 0x05u}, - {0xA6u, 0x0Au}, - {0xAAu, 0x02u}, - {0xAEu, 0x08u}, - {0xB1u, 0x0Eu}, - {0xB4u, 0x0Cu}, - {0xB5u, 0x01u}, - {0xB6u, 0x03u}, - {0xBEu, 0x50u}, + {0xE6u, 0x0Cu}, + {0xEAu, 0x04u}, + {0xECu, 0x04u}, + {0xEEu, 0x21u}, + {0x01u, 0x9Bu}, + {0x03u, 0x04u}, + {0x04u, 0x03u}, + {0x06u, 0x0Cu}, + {0x07u, 0x40u}, + {0x08u, 0x30u}, + {0x09u, 0x0Cu}, + {0x0Au, 0xC0u}, + {0x0Bu, 0x80u}, + {0x0Cu, 0x0Fu}, + {0x0Du, 0x20u}, + {0x0Eu, 0xF0u}, + {0x0Fu, 0x40u}, + {0x10u, 0x50u}, + {0x12u, 0xA0u}, + {0x15u, 0x98u}, + {0x17u, 0x04u}, + {0x1Bu, 0x01u}, + {0x1Cu, 0x06u}, + {0x1Du, 0x80u}, + {0x1Eu, 0x09u}, + {0x1Fu, 0x17u}, + {0x20u, 0x05u}, + {0x22u, 0x0Au}, + {0x23u, 0x20u}, + {0x24u, 0x60u}, + {0x25u, 0x03u}, + {0x26u, 0x90u}, + {0x27u, 0x0Cu}, + {0x29u, 0x02u}, + {0x2Fu, 0x1Fu}, + {0x31u, 0x1Fu}, + {0x34u, 0xFFu}, + {0x35u, 0x60u}, + {0x37u, 0x80u}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x50u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Cu, 0x10u}, + {0x5Fu, 0x01u}, + {0x81u, 0x35u}, + {0x89u, 0x39u}, + {0x8Bu, 0x42u}, + {0x8Fu, 0x04u}, + {0x91u, 0x20u}, + {0x95u, 0x4Au}, + {0x97u, 0x31u}, + {0x99u, 0x0Bu}, + {0x9Bu, 0x70u}, + {0x9Du, 0x12u}, + {0x9Fu, 0x01u}, + {0xA1u, 0x35u}, + {0xA5u, 0x15u}, + {0xA7u, 0x20u}, + {0xA9u, 0x05u}, + {0xABu, 0x30u}, + {0xADu, 0x30u}, + {0xAFu, 0x05u}, + {0xB3u, 0x78u}, + {0xB5u, 0x04u}, + {0xB7u, 0x03u}, + {0xB9u, 0x08u}, + {0xBBu, 0x80u}, {0xBFu, 0x10u}, - {0xD8u, 0x04u}, + {0xC0u, 0x62u}, + {0xC1u, 0x04u}, + {0xC2u, 0x10u}, + {0xC4u, 0x05u}, + {0xC5u, 0xCEu}, + {0xC6u, 0xFDu}, + {0xC7u, 0x0Bu}, + {0xC8u, 0x1Fu}, + {0xC9u, 0xFFu}, + {0xCAu, 0xFFu}, + {0xCBu, 0xFFu}, + {0xCCu, 0x22u}, + {0xCEu, 0xF0u}, + {0xCFu, 0x08u}, + {0xD0u, 0x04u}, + {0xD4u, 0x40u}, + {0xD6u, 0x04u}, {0xD9u, 0x04u}, - {0xDCu, 0x10u}, + {0xDAu, 0x04u}, + {0xDBu, 0x04u}, {0xDFu, 0x01u}, - {0x01u, 0x41u}, - {0x03u, 0x18u}, - {0x04u, 0x80u}, - {0x05u, 0x80u}, - {0x08u, 0x48u}, - {0x0Au, 0x86u}, - {0x0Du, 0x80u}, - {0x0Fu, 0x0Au}, - {0x10u, 0x80u}, - {0x12u, 0x02u}, - {0x13u, 0x10u}, - {0x14u, 0x01u}, - {0x15u, 0x02u}, - {0x17u, 0x28u}, - {0x1Au, 0x82u}, - {0x1Bu, 0x10u}, - {0x1Fu, 0x90u}, - {0x20u, 0x40u}, + {0xE2u, 0xC0u}, + {0xE4u, 0x40u}, + {0xE5u, 0x01u}, + {0xE6u, 0x10u}, + {0xE7u, 0x11u}, + {0xE8u, 0xC0u}, + {0xE9u, 0x01u}, + {0xEBu, 0x11u}, + {0xECu, 0x40u}, + {0xEDu, 0x01u}, + {0xEEu, 0x40u}, + {0xEFu, 0x01u}, + {0x00u, 0x64u}, + {0x09u, 0x01u}, + {0x0Au, 0x02u}, + {0x10u, 0x40u}, + {0x12u, 0x10u}, + {0x19u, 0x20u}, + {0x20u, 0x80u}, + {0x21u, 0x81u}, {0x22u, 0x10u}, - {0x27u, 0x84u}, - {0x29u, 0x02u}, - {0x2Du, 0x02u}, - {0x32u, 0x18u}, - {0x33u, 0x40u}, - {0x36u, 0x08u}, - {0x37u, 0x80u}, - {0x38u, 0x40u}, - {0x39u, 0x10u}, - {0x3Bu, 0x04u}, - {0x3Fu, 0x44u}, - {0x40u, 0x20u}, - {0x42u, 0x04u}, - {0x43u, 0x02u}, - {0x49u, 0x04u}, - {0x4Au, 0x02u}, - {0x4Bu, 0x11u}, - {0x50u, 0x08u}, - {0x51u, 0x60u}, - {0x53u, 0x01u}, - {0x58u, 0x04u}, - {0x59u, 0xA0u}, - {0x5Au, 0x01u}, - {0x61u, 0x40u}, + {0x24u, 0x02u}, + {0x26u, 0xACu}, + {0x28u, 0xC1u}, + {0x2Au, 0x48u}, + {0x2Bu, 0x08u}, + {0x2Du, 0x40u}, + {0x2Eu, 0x12u}, + {0x2Fu, 0x20u}, + {0x30u, 0x10u}, + {0x32u, 0x04u}, + {0x33u, 0x90u}, + {0x35u, 0x12u}, + {0x36u, 0x88u}, + {0x38u, 0x48u}, + {0x39u, 0xA2u}, + {0x3Du, 0x21u}, + {0x3Fu, 0x80u}, + {0x45u, 0x62u}, + {0x4Du, 0x82u}, + {0x4Eu, 0x08u}, + {0x4Fu, 0x05u}, + {0x55u, 0x04u}, + {0x56u, 0x24u}, + {0x57u, 0x40u}, {0x64u, 0x02u}, - {0x67u, 0x02u}, - {0x79u, 0x02u}, - {0x7Au, 0x80u}, - {0x7Du, 0x08u}, - {0x7Eu, 0x10u}, - {0x80u, 0x08u}, - {0x83u, 0x05u}, - {0x85u, 0x40u}, - {0x88u, 0x20u}, - {0x8Bu, 0x10u}, - {0x8Fu, 0x80u}, - {0x90u, 0x80u}, - {0x91u, 0x14u}, - {0x92u, 0x40u}, - {0x93u, 0x44u}, - {0x96u, 0x0Cu}, - {0x97u, 0x10u}, - {0x98u, 0x04u}, - {0x99u, 0x62u}, - {0x9Au, 0x44u}, - {0x9Bu, 0x68u}, - {0xA0u, 0x10u}, - {0xA1u, 0x80u}, - {0xA2u, 0x98u}, - {0xA3u, 0x04u}, + {0x66u, 0x20u}, + {0x67u, 0xA0u}, + {0x6Eu, 0x40u}, + {0x6Fu, 0x14u}, + {0x78u, 0x02u}, + {0x7Bu, 0x40u}, + {0x7Eu, 0x20u}, + {0x7Fu, 0x10u}, + {0x82u, 0x40u}, + {0x88u, 0x40u}, + {0x8Eu, 0x19u}, + {0x91u, 0x20u}, + {0x92u, 0x0Eu}, + {0x93u, 0x50u}, + {0x95u, 0x82u}, + {0x97u, 0x80u}, + {0x9Au, 0x90u}, + {0x9Bu, 0x08u}, + {0x9Cu, 0x08u}, + {0x9Du, 0x39u}, + {0x9Eu, 0x41u}, + {0x9Fu, 0x14u}, + {0xA0u, 0x04u}, + {0xA3u, 0x88u}, {0xA4u, 0x40u}, - {0xA5u, 0x04u}, - {0xA6u, 0x02u}, - {0xA7u, 0x40u}, - {0xA9u, 0x29u}, - {0xABu, 0x20u}, - {0xACu, 0x84u}, - {0xADu, 0x40u}, - {0xB0u, 0x01u}, - {0xB2u, 0x01u}, - {0xB3u, 0x28u}, - {0xB5u, 0x10u}, - {0xB7u, 0x42u}, - {0xC0u, 0x0Fu}, - {0xC2u, 0x4Fu}, - {0xC4u, 0xFBu}, - {0xCAu, 0x81u}, - {0xCCu, 0x5Eu}, - {0xCEu, 0x5Eu}, - {0xD0u, 0x07u}, - {0xD2u, 0x0Cu}, - {0xD6u, 0x0Fu}, - {0xD8u, 0x08u}, - {0xE0u, 0x80u}, - {0xE2u, 0x40u}, - {0xEAu, 0x03u}, - {0xEEu, 0x54u}, - {0x00u, 0x01u}, - {0x03u, 0x9Fu}, - {0x04u, 0x01u}, - {0x07u, 0xFFu}, - {0x08u, 0x04u}, - {0x09u, 0x7Fu}, - {0x0Bu, 0x80u}, - {0x0Cu, 0x01u}, - {0x0Du, 0x90u}, - {0x0Fu, 0x40u}, - {0x11u, 0x1Fu}, - {0x12u, 0x40u}, - {0x13u, 0x20u}, - {0x14u, 0xA2u}, - {0x15u, 0x80u}, - {0x16u, 0x08u}, - {0x18u, 0x08u}, - {0x1Au, 0x61u}, - {0x1Bu, 0x60u}, - {0x1Cu, 0x01u}, - {0x1Du, 0xC0u}, - {0x1Fu, 0x02u}, - {0x20u, 0x07u}, - {0x21u, 0xC0u}, - {0x22u, 0xD8u}, - {0x23u, 0x01u}, - {0x25u, 0xC0u}, - {0x27u, 0x04u}, - {0x28u, 0x01u}, - {0x29u, 0xC0u}, - {0x2Bu, 0x08u}, - {0x2Cu, 0x10u}, - {0x30u, 0xE0u}, - {0x36u, 0x3Fu}, - {0x37u, 0xFFu}, - {0x38u, 0x80u}, + {0xA5u, 0x80u}, + {0xA6u, 0x0Au}, + {0xAAu, 0x04u}, + {0xABu, 0x14u}, + {0xACu, 0x15u}, + {0xB1u, 0x40u}, + {0xB3u, 0x08u}, + {0xB5u, 0x40u}, + {0xB6u, 0x04u}, + {0xB7u, 0x40u}, + {0xC0u, 0x07u}, + {0xC2u, 0x09u}, + {0xC4u, 0x0Cu}, + {0xCAu, 0xFFu}, + {0xCCu, 0xFEu}, + {0xCEu, 0xBFu}, + {0xD0u, 0xB0u}, + {0xD2u, 0x30u}, + {0xD8u, 0xF0u}, + {0xE2u, 0x41u}, + {0xEAu, 0x0Au}, + {0xEEu, 0x06u}, + {0x00u, 0x24u}, + {0x01u, 0x01u}, + {0x04u, 0x6Cu}, + {0x05u, 0x10u}, + {0x0Au, 0x2Fu}, + {0x0Bu, 0x40u}, + {0x0Cu, 0x2Cu}, + {0x0Eu, 0x40u}, + {0x10u, 0x31u}, + {0x11u, 0x07u}, + {0x12u, 0x02u}, + {0x13u, 0xD8u}, + {0x14u, 0x40u}, + {0x15u, 0x08u}, + {0x16u, 0x2Cu}, + {0x17u, 0x61u}, + {0x18u, 0x11u}, + {0x19u, 0xA2u}, + {0x1Au, 0x0Eu}, + {0x1Bu, 0x08u}, + {0x1Cu, 0x08u}, + {0x1Du, 0x01u}, + {0x1Eu, 0x10u}, + {0x20u, 0x6Cu}, + {0x21u, 0x01u}, + {0x24u, 0x80u}, + {0x25u, 0x01u}, + {0x28u, 0x64u}, + {0x29u, 0x04u}, + {0x2Au, 0x08u}, + {0x2Cu, 0x80u}, + {0x2Du, 0x01u}, + {0x30u, 0x0Fu}, + {0x31u, 0x3Fu}, + {0x32u, 0x80u}, + {0x34u, 0x31u}, + {0x35u, 0xE0u}, + {0x36u, 0x40u}, + {0x37u, 0x08u}, + {0x38u, 0x08u}, + {0x39u, 0x02u}, + {0x3Au, 0x30u}, {0x3Eu, 0x40u}, - {0x3Fu, 0x40u}, + {0x3Fu, 0x41u}, + {0x56u, 0x02u}, + {0x57u, 0x20u}, {0x58u, 0x04u}, {0x59u, 0x04u}, + {0x5Bu, 0x04u}, {0x5Fu, 0x01u}, - {0x80u, 0x56u}, - {0x81u, 0x64u}, - {0x84u, 0x52u}, - {0x85u, 0x83u}, - {0x86u, 0x04u}, - {0x87u, 0x70u}, - {0x88u, 0x50u}, - {0x8Au, 0x06u}, - {0x8Bu, 0xF5u}, - {0x8Cu, 0x17u}, - {0x8Du, 0x64u}, - {0x8Eu, 0x28u}, - {0x91u, 0x07u}, - {0x93u, 0x90u}, - {0x94u, 0x31u}, - {0x95u, 0x40u}, - {0x96u, 0x0Eu}, - {0x97u, 0x02u}, - {0x98u, 0x29u}, - {0x99u, 0x24u}, - {0x9Au, 0x16u}, - {0x9Bu, 0x40u}, - {0x9Du, 0x08u}, - {0xA0u, 0x56u}, - {0xA1u, 0x64u}, - {0xA4u, 0x22u}, - {0xA5u, 0x24u}, - {0xA6u, 0x10u}, - {0xA8u, 0x04u}, - {0xABu, 0x64u}, - {0xACu, 0x06u}, - {0xADu, 0x08u}, - {0xAEu, 0x50u}, + {0x81u, 0xC0u}, + {0x82u, 0x49u}, + {0x83u, 0x01u}, + {0x86u, 0x06u}, + {0x87u, 0x9Fu}, + {0x89u, 0xC0u}, + {0x8Bu, 0x08u}, + {0x8Cu, 0x09u}, + {0x8Du, 0xC0u}, + {0x8Eu, 0x24u}, + {0x8Fu, 0x02u}, + {0x91u, 0x90u}, + {0x93u, 0x40u}, + {0x97u, 0xFFu}, + {0x98u, 0x09u}, + {0x99u, 0xC0u}, + {0x9Au, 0x52u}, + {0x9Bu, 0x04u}, + {0x9Du, 0x80u}, + {0x9Eu, 0x30u}, + {0xA1u, 0x1Fu}, + {0xA3u, 0x20u}, + {0xA7u, 0x60u}, + {0xA9u, 0x7Fu}, + {0xAAu, 0x08u}, + {0xABu, 0x80u}, + {0xAEu, 0x01u}, {0xB0u, 0x40u}, - {0xB1u, 0x71u}, - {0xB2u, 0x30u}, - {0xB3u, 0x07u}, - {0xB4u, 0x0Fu}, - {0xB5u, 0x08u}, - {0xB7u, 0x80u}, - {0xB8u, 0x20u}, - {0xB9u, 0x20u}, - {0xBAu, 0x08u}, - {0xBBu, 0x0Cu}, + {0xB3u, 0xFFu}, + {0xB4u, 0x07u}, + {0xB6u, 0x38u}, {0xBEu, 0x01u}, - {0xBFu, 0x40u}, - {0xD4u, 0x40u}, - {0xD6u, 0x04u}, + {0xBFu, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDBu, 0x04u}, + {0xDCu, 0x01u}, {0xDFu, 0x01u}, - {0x01u, 0x01u}, - {0x02u, 0x02u}, - {0x03u, 0x18u}, - {0x05u, 0x08u}, - {0x07u, 0x49u}, - {0x0Au, 0x04u}, - {0x0Bu, 0x10u}, - {0x0Cu, 0x80u}, - {0x0Eu, 0x84u}, - {0x0Fu, 0x10u}, - {0x10u, 0x98u}, - {0x11u, 0x40u}, - {0x15u, 0x82u}, - {0x17u, 0x10u}, - {0x18u, 0x08u}, - {0x19u, 0x09u}, - {0x1Au, 0x04u}, - {0x1Bu, 0x02u}, - {0x1Du, 0x40u}, - {0x1Eu, 0x80u}, - {0x21u, 0x01u}, - {0x22u, 0x62u}, - {0x23u, 0x18u}, - {0x25u, 0x80u}, - {0x28u, 0x10u}, - {0x29u, 0x48u}, - {0x2Bu, 0x88u}, - {0x2Cu, 0xA0u}, - {0x2Fu, 0x08u}, - {0x30u, 0x28u}, - {0x31u, 0x80u}, - {0x32u, 0x02u}, - {0x35u, 0x08u}, - {0x36u, 0x22u}, - {0x37u, 0x40u}, - {0x38u, 0x08u}, - {0x39u, 0x40u}, - {0x3Au, 0x02u}, - {0x3Bu, 0x10u}, - {0x3Du, 0x40u}, - {0x3Eu, 0x04u}, - {0x3Fu, 0x11u}, - {0x48u, 0x08u}, - {0x49u, 0x20u}, - {0x60u, 0x02u}, - {0x61u, 0x20u}, - {0x63u, 0xA0u}, - {0x86u, 0x40u}, - {0x88u, 0x01u}, - {0x91u, 0x84u}, - {0x92u, 0x60u}, - {0x93u, 0x05u}, - {0x95u, 0x41u}, - {0x96u, 0x0Cu}, - {0x97u, 0x10u}, - {0x98u, 0x42u}, - {0x99u, 0x06u}, - {0x9Au, 0xC4u}, - {0x9Bu, 0xA0u}, - {0x9Cu, 0x01u}, - {0x9Fu, 0x10u}, - {0xA0u, 0x08u}, - {0xA1u, 0x20u}, - {0xA2u, 0x98u}, - {0xA3u, 0x15u}, - {0xA4u, 0x80u}, - {0xA5u, 0x40u}, + {0x00u, 0x84u}, + {0x03u, 0x80u}, + {0x04u, 0x02u}, + {0x05u, 0x10u}, + {0x06u, 0x20u}, + {0x07u, 0x01u}, + {0x08u, 0x80u}, + {0x0Au, 0x05u}, + {0x0Du, 0x02u}, + {0x0Eu, 0x18u}, + {0x0Fu, 0x01u}, + {0x13u, 0x50u}, + {0x15u, 0x09u}, + {0x17u, 0x50u}, + {0x18u, 0x04u}, + {0x1Au, 0x01u}, + {0x1Bu, 0x01u}, + {0x1Du, 0xB7u}, + {0x1Eu, 0x02u}, + {0x1Fu, 0x08u}, + {0x21u, 0x04u}, + {0x25u, 0x10u}, + {0x26u, 0x50u}, + {0x27u, 0x40u}, + {0x29u, 0x15u}, + {0x2Du, 0x40u}, + {0x2Eu, 0x02u}, + {0x2Fu, 0x28u}, + {0x32u, 0x88u}, + {0x33u, 0x11u}, + {0x35u, 0x11u}, + {0x36u, 0x88u}, + {0x38u, 0x80u}, + {0x39u, 0x10u}, + {0x3Au, 0x06u}, + {0x3Du, 0x29u}, + {0x45u, 0xC0u}, + {0x66u, 0x80u}, + {0x6Cu, 0x40u}, + {0x6Du, 0x51u}, + {0x6Eu, 0x10u}, + {0x6Fu, 0x31u}, + {0x75u, 0x80u}, + {0x76u, 0x02u}, + {0x81u, 0x80u}, + {0x82u, 0x20u}, + {0x8Bu, 0x01u}, + {0x90u, 0x02u}, + {0x92u, 0x04u}, + {0x93u, 0x55u}, + {0x94u, 0x04u}, + {0x95u, 0xC1u}, + {0x96u, 0x10u}, + {0x98u, 0x10u}, + {0x99u, 0x20u}, + {0x9Au, 0x85u}, + {0x9Bu, 0x08u}, + {0x9Cu, 0x88u}, + {0x9Du, 0x19u}, + {0x9Eu, 0x02u}, + {0xA0u, 0x44u}, + {0xA1u, 0x04u}, + {0xA2u, 0x8Cu}, + {0xA3u, 0x80u}, + {0xA5u, 0x62u}, {0xA6u, 0x02u}, - {0xA7u, 0x4Au}, - {0xAAu, 0x10u}, - {0xACu, 0x50u}, - {0xAEu, 0x81u}, - {0xB4u, 0x40u}, - {0xC0u, 0xFFu}, - {0xC2u, 0xF6u}, - {0xC4u, 0xDFu}, - {0xCAu, 0xEFu}, + {0xA7u, 0x20u}, + {0xA8u, 0x04u}, + {0xA9u, 0x93u}, + {0xACu, 0x10u}, + {0xB0u, 0x01u}, + {0xC0u, 0xFDu}, + {0xC2u, 0xF3u}, + {0xC4u, 0xF3u}, + {0xCAu, 0xF7u}, {0xCCu, 0xFFu}, - {0xCEu, 0xFFu}, - {0xD8u, 0x0Fu}, - {0xE2u, 0x09u}, - {0xE6u, 0x08u}, - {0xEAu, 0x02u}, - {0xECu, 0x04u}, - {0x38u, 0x80u}, - {0x3Eu, 0x40u}, - {0x58u, 0x04u}, - {0x5Fu, 0x01u}, - {0x1Fu, 0x80u}, - {0x8Au, 0x04u}, - {0x92u, 0x0Cu}, - {0x97u, 0x01u}, - {0x9Bu, 0x80u}, - {0x9Cu, 0x02u}, - {0x9Du, 0x20u}, - {0xA3u, 0x08u}, - {0xAAu, 0x04u}, - {0xADu, 0x40u}, - {0xB5u, 0x08u}, - {0xE2u, 0x09u}, - {0xE6u, 0x28u}, - {0xE8u, 0x40u}, - {0x92u, 0x0Cu}, - {0x97u, 0x01u}, - {0x9Bu, 0x80u}, - {0x9Cu, 0x02u}, - {0x9Du, 0x28u}, - {0xA1u, 0x40u}, - {0xA3u, 0x08u}, - {0xA6u, 0x04u}, - {0xA8u, 0x40u}, + {0xCEu, 0xEFu}, + {0xD8u, 0x10u}, + {0xE2u, 0x89u}, + {0xE6u, 0x20u}, + {0xEAu, 0x08u}, + {0xEEu, 0x01u}, + {0x90u, 0x08u}, + {0x91u, 0x40u}, + {0x9Bu, 0x01u}, + {0x9Eu, 0x20u}, + {0xA2u, 0x10u}, {0xA9u, 0x04u}, - {0xAEu, 0x04u}, - {0xB0u, 0x20u}, - {0xB1u, 0x01u}, - {0xB6u, 0x08u}, - {0xB7u, 0x08u}, - {0xE0u, 0x20u}, - {0xEAu, 0x94u}, - {0xEEu, 0xA4u}, - {0x01u, 0x0Fu}, - {0x03u, 0xF0u}, - {0x04u, 0x50u}, - {0x05u, 0x30u}, - {0x06u, 0xA0u}, - {0x07u, 0xC0u}, - {0x08u, 0x06u}, - {0x09u, 0x50u}, - {0x0Au, 0x09u}, - {0x0Bu, 0xA0u}, - {0x0Cu, 0x03u}, - {0x0Du, 0x60u}, - {0x0Eu, 0x0Cu}, - {0x0Fu, 0x90u}, - {0x11u, 0xFFu}, - {0x12u, 0xFFu}, - {0x14u, 0xFFu}, - {0x15u, 0x05u}, - {0x17u, 0x0Au}, - {0x18u, 0x05u}, - {0x19u, 0x06u}, - {0x1Au, 0x0Au}, - {0x1Bu, 0x09u}, - {0x1Cu, 0x0Fu}, - {0x1Eu, 0xF0u}, - {0x1Fu, 0xFFu}, - {0x21u, 0x03u}, - {0x22u, 0xFFu}, - {0x23u, 0x0Cu}, - {0x24u, 0x30u}, - {0x26u, 0xC0u}, - {0x27u, 0xFFu}, - {0x2Cu, 0x60u}, - {0x2Eu, 0x90u}, - {0x35u, 0xFFu}, - {0x36u, 0xFFu}, - {0x3Eu, 0x40u}, - {0x3Fu, 0x10u}, + {0xAEu, 0x40u}, + {0xE2u, 0x09u}, + {0xE6u, 0x20u}, + {0xEEu, 0x20u}, + {0xB9u, 0x08u}, + {0xBFu, 0x04u}, + {0xD9u, 0x04u}, + {0xDFu, 0x01u}, + {0x27u, 0x20u}, + {0x83u, 0x20u}, + {0x8Bu, 0x04u}, + {0x8Fu, 0x10u}, + {0x90u, 0x08u}, + {0x91u, 0x40u}, + {0x97u, 0x04u}, + {0x99u, 0x04u}, + {0x9Au, 0x40u}, + {0x9Bu, 0x11u}, + {0x9Eu, 0x20u}, + {0xA2u, 0x10u}, + {0xA9u, 0x54u}, + {0xADu, 0x05u}, + {0xAFu, 0x01u}, + {0xB1u, 0x02u}, + {0xB2u, 0x18u}, + {0xB4u, 0x40u}, + {0xB5u, 0x41u}, + {0xE2u, 0x10u}, + {0xE4u, 0x20u}, + {0xE6u, 0x40u}, + {0xE8u, 0xC4u}, + {0xEAu, 0x01u}, + {0xECu, 0x80u}, + {0xEEu, 0x50u}, + {0x02u, 0x04u}, + {0x06u, 0x20u}, + {0x08u, 0x21u}, + {0x0Au, 0x42u}, + {0x0Eu, 0x04u}, + {0x11u, 0x20u}, + {0x13u, 0x90u}, + {0x15u, 0x04u}, + {0x16u, 0x18u}, + {0x17u, 0x08u}, + {0x18u, 0x04u}, + {0x1Au, 0x10u}, + {0x1Bu, 0x01u}, + {0x1Eu, 0x02u}, + {0x21u, 0x10u}, + {0x22u, 0x40u}, + {0x23u, 0x20u}, + {0x24u, 0x04u}, + {0x25u, 0x08u}, + {0x26u, 0x08u}, + {0x27u, 0x44u}, + {0x29u, 0x4Du}, + {0x2Au, 0x01u}, + {0x2Bu, 0xB2u}, + {0x2Cu, 0x80u}, + {0x2Fu, 0x02u}, + {0x30u, 0x03u}, + {0x31u, 0xC0u}, + {0x32u, 0x1Cu}, + {0x33u, 0x03u}, + {0x34u, 0x80u}, + {0x36u, 0x60u}, + {0x37u, 0x3Cu}, + {0x3Eu, 0x51u}, + {0x3Fu, 0x45u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, + {0x5Cu, 0x01u}, {0x5Fu, 0x01u}, - {0x84u, 0x10u}, - {0x86u, 0x09u}, - {0x87u, 0x10u}, {0x8Bu, 0x08u}, - {0x8Du, 0x0Au}, - {0x8Fu, 0x14u}, - {0x90u, 0x08u}, - {0x92u, 0x10u}, - {0x93u, 0x04u}, - {0x94u, 0x04u}, - {0x95u, 0x01u}, - {0x9Cu, 0x19u}, - {0x9Eu, 0x62u}, - {0xA0u, 0x40u}, - {0xA2u, 0x22u}, - {0xABu, 0x02u}, - {0xACu, 0x20u}, - {0xAEu, 0x40u}, - {0xB0u, 0x04u}, - {0xB1u, 0x06u}, - {0xB2u, 0x03u}, - {0xB3u, 0x18u}, - {0xB4u, 0x78u}, - {0xB5u, 0x01u}, - {0xBEu, 0x15u}, - {0xBFu, 0x15u}, + {0x8Cu, 0x01u}, + {0x8Du, 0x10u}, + {0x91u, 0x04u}, + {0x93u, 0x08u}, + {0x97u, 0x04u}, + {0x98u, 0x02u}, + {0xA5u, 0x01u}, + {0xA9u, 0x02u}, + {0xACu, 0x04u}, + {0xB0u, 0x02u}, + {0xB1u, 0x02u}, + {0xB3u, 0x10u}, + {0xB4u, 0x01u}, + {0xB5u, 0x0Cu}, + {0xB6u, 0x04u}, + {0xB7u, 0x01u}, + {0xBEu, 0x51u}, + {0xBFu, 0x55u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDFu, 0x01u}, - {0x01u, 0x08u}, - {0x04u, 0x08u}, - {0x05u, 0x20u}, - {0x06u, 0x02u}, - {0x09u, 0x06u}, - {0x0Bu, 0x01u}, - {0x0Cu, 0x01u}, - {0x0Du, 0x50u}, - {0x0Eu, 0x08u}, - {0x0Fu, 0x21u}, - {0x11u, 0x02u}, - {0x12u, 0x01u}, - {0x14u, 0x80u}, - {0x15u, 0x44u}, - {0x18u, 0xA0u}, - {0x1Au, 0x08u}, - {0x1Bu, 0x30u}, - {0x1Fu, 0x80u}, - {0x22u, 0x2Au}, - {0x27u, 0x08u}, - {0x29u, 0x20u}, - {0x2Eu, 0x02u}, - {0x2Fu, 0x20u}, - {0x31u, 0x08u}, - {0x33u, 0x02u}, - {0x34u, 0x83u}, - {0x35u, 0x20u}, - {0x36u, 0x04u}, - {0x38u, 0x08u}, - {0x39u, 0xA0u}, - {0x3Du, 0x91u}, - {0x3Eu, 0x04u}, - {0x3Fu, 0x01u}, + {0x03u, 0x02u}, + {0x04u, 0x40u}, + {0x05u, 0x02u}, + {0x06u, 0x24u}, + {0x09u, 0x10u}, + {0x0Cu, 0x80u}, + {0x0Eu, 0x20u}, + {0x0Fu, 0x04u}, + {0x10u, 0x01u}, + {0x14u, 0x08u}, + {0x16u, 0x40u}, + {0x17u, 0x48u}, + {0x19u, 0x61u}, + {0x1Du, 0x90u}, + {0x1Eu, 0xA0u}, + {0x21u, 0x45u}, + {0x22u, 0x10u}, + {0x24u, 0x80u}, + {0x25u, 0x04u}, + {0x27u, 0x01u}, + {0x2Au, 0x18u}, + {0x2Cu, 0xA8u}, + {0x2Du, 0x40u}, + {0x31u, 0x02u}, + {0x32u, 0x08u}, + {0x34u, 0x08u}, + {0x36u, 0x11u}, + {0x39u, 0x10u}, + {0x3Au, 0x80u}, {0x6Cu, 0x04u}, - {0x6Du, 0xD6u}, - {0x6Eu, 0x04u}, - {0x6Fu, 0x0Au}, - {0x74u, 0x20u}, - {0x75u, 0x80u}, - {0x76u, 0x11u}, - {0x77u, 0x80u}, - {0x82u, 0x20u}, - {0x86u, 0x02u}, - {0x88u, 0x80u}, - {0x89u, 0x02u}, - {0x8Au, 0x02u}, - {0x8Cu, 0x10u}, - {0x8Fu, 0x80u}, - {0x9Cu, 0x02u}, - {0x9Du, 0xA0u}, - {0x9Eu, 0x10u}, - {0x9Fu, 0x08u}, - {0xA1u, 0x08u}, - {0xA7u, 0x10u}, - {0xAEu, 0x10u}, - {0xB1u, 0x80u}, - {0xB7u, 0x10u}, - {0xC0u, 0xE4u}, - {0xC2u, 0xFDu}, - {0xC4u, 0xB9u}, - {0xCAu, 0xC4u}, - {0xCCu, 0xF3u}, - {0xCEu, 0xFEu}, - {0xE0u, 0xA2u}, - {0xE2u, 0x50u}, + {0x6Du, 0x50u}, + {0x6Eu, 0x02u}, + {0x6Fu, 0x10u}, + {0x74u, 0x90u}, + {0x75u, 0x04u}, + {0x76u, 0x40u}, + {0x81u, 0x10u}, + {0x83u, 0x40u}, + {0x84u, 0x01u}, + {0x85u, 0x10u}, + {0x87u, 0x02u}, + {0x89u, 0x60u}, + {0x8Au, 0x80u}, + {0x8Cu, 0x08u}, + {0x8Du, 0x02u}, + {0x8Eu, 0x1Cu}, + {0x8Fu, 0x08u}, + {0x94u, 0x80u}, + {0x98u, 0x08u}, + {0xA0u, 0x20u}, + {0xA4u, 0x10u}, + {0xA5u, 0x80u}, + {0xA6u, 0x40u}, + {0xA8u, 0x08u}, + {0xA9u, 0x80u}, + {0xC0u, 0xF1u}, + {0xC2u, 0xE2u}, + {0xC4u, 0xF1u}, + {0xCAu, 0xF6u}, + {0xCCu, 0xE3u}, + {0xCEu, 0x0Cu}, + {0xE2u, 0xAAu}, + {0xE4u, 0x50u}, + {0xE6u, 0x01u}, + {0xE8u, 0x80u}, + {0xEAu, 0x04u}, + {0x80u, 0x40u}, + {0x84u, 0x10u}, + {0x86u, 0x40u}, + {0x88u, 0x20u}, + {0xE0u, 0x01u}, {0xE4u, 0x20u}, - {0xE6u, 0x98u}, - {0xEAu, 0x14u}, - {0xEEu, 0x82u}, - {0x85u, 0x20u}, - {0x87u, 0x08u}, - {0x8Cu, 0x02u}, - {0x8Du, 0x08u}, - {0xE2u, 0x10u}, - {0xAFu, 0x10u}, - {0xB2u, 0x20u}, - {0xB4u, 0x40u}, - {0xEAu, 0x40u}, - {0xECu, 0x02u}, - {0x00u, 0x03u}, - {0x02u, 0x0Cu}, - {0x04u, 0x60u}, - {0x05u, 0x01u}, - {0x06u, 0x90u}, - {0x07u, 0x02u}, - {0x0Bu, 0x10u}, - {0x0Cu, 0x0Fu}, - {0x0Eu, 0xF0u}, - {0x11u, 0x08u}, - {0x13u, 0x10u}, - {0x14u, 0x05u}, - {0x16u, 0x0Au}, - {0x17u, 0x01u}, - {0x18u, 0x06u}, - {0x1Au, 0x09u}, - {0x1Bu, 0x06u}, - {0x1Fu, 0x08u}, - {0x20u, 0x50u}, - {0x21u, 0x01u}, - {0x22u, 0xA0u}, - {0x23u, 0x04u}, - {0x24u, 0x30u}, - {0x26u, 0xC0u}, - {0x2Fu, 0x01u}, - {0x34u, 0xFFu}, - {0x35u, 0x07u}, - {0x37u, 0x18u}, - {0x3Eu, 0x10u}, + {0xABu, 0x21u}, + {0xAFu, 0x80u}, + {0xB0u, 0x08u}, + {0xB1u, 0x40u}, + {0xB2u, 0x10u}, + {0xB7u, 0x40u}, + {0x00u, 0x21u}, + {0x01u, 0x02u}, + {0x02u, 0x02u}, + {0x03u, 0x0Du}, + {0x04u, 0xE0u}, + {0x05u, 0x60u}, + {0x08u, 0x88u}, + {0x09u, 0x0Du}, + {0x0Au, 0x03u}, + {0x0Eu, 0x01u}, + {0x11u, 0x91u}, + {0x13u, 0x22u}, + {0x15u, 0x92u}, + {0x16u, 0xECu}, + {0x17u, 0x44u}, + {0x18u, 0x04u}, + {0x19u, 0xA2u}, + {0x1Au, 0x43u}, + {0x1Bu, 0x18u}, + {0x1Du, 0x0Du}, + {0x21u, 0x0Du}, + {0x25u, 0x0Du}, + {0x2Au, 0x12u}, + {0x2Du, 0x0Du}, + {0x30u, 0x10u}, + {0x31u, 0x0Fu}, + {0x32u, 0x0Fu}, + {0x35u, 0x70u}, + {0x36u, 0xE0u}, + {0x37u, 0x80u}, + {0x39u, 0x20u}, + {0x3Bu, 0x02u}, + {0x3Eu, 0x40u}, {0x3Fu, 0x40u}, - {0x56u, 0x02u}, - {0x57u, 0x28u}, + {0x54u, 0x09u}, + {0x56u, 0x04u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x10u}, {0x5Fu, 0x01u}, - {0x86u, 0xECu}, - {0x87u, 0xFFu}, - {0x8Bu, 0xFFu}, - {0x8Du, 0x0Fu}, - {0x8Eu, 0x01u}, - {0x8Fu, 0xF0u}, - {0x91u, 0x30u}, - {0x93u, 0xC0u}, - {0x98u, 0x04u}, + {0x80u, 0x50u}, + {0x81u, 0x30u}, + {0x82u, 0xA0u}, + {0x83u, 0xC0u}, + {0x84u, 0x03u}, + {0x85u, 0x06u}, + {0x86u, 0x0Cu}, + {0x87u, 0x09u}, + {0x89u, 0xFFu}, + {0x8Au, 0xFFu}, + {0x8Cu, 0x30u}, + {0x8Eu, 0xC0u}, + {0x90u, 0x0Fu}, + {0x92u, 0xF0u}, + {0x94u, 0x09u}, + {0x95u, 0x03u}, + {0x96u, 0x06u}, + {0x97u, 0x0Cu}, {0x99u, 0x05u}, - {0x9Au, 0x43u}, + {0x9Au, 0xFFu}, {0x9Bu, 0x0Au}, - {0x9Du, 0x03u}, - {0x9Eu, 0x12u}, - {0x9Fu, 0x0Cu}, - {0xA0u, 0xE0u}, + {0x9Du, 0x0Fu}, + {0x9Eu, 0xFFu}, + {0x9Fu, 0xF0u}, + {0xA0u, 0x90u}, {0xA1u, 0x50u}, + {0xA2u, 0x60u}, {0xA3u, 0xA0u}, + {0xA4u, 0x05u}, + {0xA6u, 0x0Au}, {0xA7u, 0xFFu}, - {0xA8u, 0x88u}, - {0xA9u, 0x09u}, - {0xAAu, 0x03u}, - {0xABu, 0x06u}, - {0xACu, 0x21u}, - {0xADu, 0x90u}, - {0xAEu, 0x02u}, - {0xAFu, 0x60u}, - {0xB0u, 0xE0u}, - {0xB3u, 0xFFu}, - {0xB4u, 0x0Fu}, - {0xB6u, 0x10u}, - {0xBEu, 0x01u}, - {0xBFu, 0x04u}, - {0xD4u, 0x09u}, - {0xD6u, 0x04u}, + {0xABu, 0xFFu}, + {0xADu, 0x60u}, + {0xAFu, 0x90u}, + {0xB1u, 0xFFu}, + {0xB2u, 0xFFu}, + {0xBEu, 0x04u}, + {0xBFu, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDFu, 0x01u}, - {0x00u, 0x04u}, - {0x01u, 0x80u}, - {0x07u, 0xA2u}, - {0x0Au, 0x04u}, - {0x0Bu, 0x01u}, - {0x0Eu, 0x20u}, - {0x0Fu, 0x08u}, - {0x10u, 0x40u}, - {0x12u, 0x02u}, - {0x13u, 0x10u}, - {0x16u, 0x60u}, - {0x18u, 0x44u}, - {0x19u, 0x80u}, - {0x1Fu, 0x10u}, - {0x22u, 0x04u}, - {0x25u, 0x40u}, - {0x26u, 0x20u}, - {0x28u, 0xA0u}, - {0x29u, 0x10u}, - {0x2Au, 0x80u}, - {0x2Du, 0x02u}, - {0x2Eu, 0x40u}, - {0x30u, 0x01u}, - {0x32u, 0x90u}, - {0x35u, 0x10u}, - {0x36u, 0x28u}, - {0x37u, 0x82u}, - {0x39u, 0x84u}, - {0x3Bu, 0x20u}, - {0x3Du, 0x20u}, - {0x3Eu, 0x20u}, - {0x3Fu, 0x04u}, - {0x59u, 0x25u}, - {0x5Au, 0x80u}, - {0x63u, 0x82u}, - {0x66u, 0x04u}, + {0x00u, 0x08u}, + {0x01u, 0x22u}, + {0x02u, 0x01u}, + {0x03u, 0x40u}, + {0x04u, 0x44u}, + {0x05u, 0x11u}, + {0x08u, 0x18u}, + {0x09u, 0x40u}, + {0x0Au, 0x80u}, + {0x0Eu, 0x28u}, + {0x10u, 0x20u}, + {0x12u, 0xC0u}, + {0x13u, 0x08u}, + {0x16u, 0x04u}, + {0x19u, 0x08u}, + {0x1Cu, 0x40u}, + {0x1Eu, 0x20u}, + {0x1Fu, 0x80u}, + {0x22u, 0x02u}, + {0x24u, 0x04u}, + {0x25u, 0x01u}, + {0x27u, 0x01u}, + {0x28u, 0x10u}, + {0x29u, 0x22u}, + {0x2Au, 0x40u}, + {0x2Du, 0x41u}, + {0x2Fu, 0x20u}, + {0x30u, 0x20u}, + {0x32u, 0x48u}, + {0x35u, 0x91u}, + {0x36u, 0x04u}, + {0x3Au, 0x11u}, + {0x3Bu, 0x08u}, + {0x3Cu, 0x04u}, + {0x3Du, 0x02u}, + {0x3Eu, 0x10u}, + {0x46u, 0x80u}, + {0x47u, 0x01u}, + {0x48u, 0x04u}, + {0x4Au, 0x08u}, + {0x5Eu, 0x82u}, + {0x5Fu, 0x24u}, + {0x64u, 0x08u}, + {0x66u, 0x82u}, + {0x67u, 0x08u}, {0x69u, 0x80u}, - {0x6Bu, 0x02u}, - {0x6Cu, 0x20u}, - {0x6Du, 0x41u}, - {0x6Fu, 0xD9u}, - {0x74u, 0x80u}, - {0x76u, 0x02u}, + {0x6Au, 0x80u}, + {0x82u, 0x80u}, + {0x8Au, 0x02u}, + {0x91u, 0x41u}, + {0x92u, 0x10u}, + {0x93u, 0x05u}, + {0x95u, 0x80u}, + {0x98u, 0x10u}, + {0x99u, 0xB1u}, + {0x9Au, 0x05u}, + {0x9Bu, 0x08u}, + {0x9Cu, 0x08u}, + {0x9Du, 0x08u}, + {0xA0u, 0x04u}, + {0xA2u, 0x45u}, + {0xA3u, 0x20u}, + {0xA6u, 0x02u}, + {0xA8u, 0x04u}, + {0xB2u, 0x10u}, + {0xC0u, 0xFFu}, + {0xC2u, 0x6Fu}, + {0xC4u, 0x4Cu}, + {0xCAu, 0xDFu}, + {0xCCu, 0xFEu}, + {0xCEu, 0xE7u}, + {0xD6u, 0xF0u}, + {0xD8u, 0x90u}, + {0xE2u, 0x80u}, + {0xE6u, 0x04u}, + {0xE8u, 0x04u}, + {0xEAu, 0x80u}, + {0xEEu, 0x02u}, {0x81u, 0x40u}, - {0x8Fu, 0x40u}, - {0x91u, 0x04u}, - {0x92u, 0xE4u}, - {0x93u, 0x15u}, - {0x95u, 0x41u}, - {0x96u, 0x08u}, - {0x98u, 0xE1u}, - {0x99u, 0x27u}, - {0x9Au, 0xC4u}, - {0x9Bu, 0xA0u}, - {0x9Eu, 0x02u}, - {0x9Fu, 0x51u}, - {0xA1u, 0x10u}, - {0xA2u, 0x9Au}, - {0xA3u, 0x05u}, - {0xA4u, 0xA0u}, - {0xA5u, 0x40u}, - {0xA7u, 0x88u}, - {0xB0u, 0xA0u}, - {0xB5u, 0x10u}, - {0xC0u, 0xB5u}, - {0xC2u, 0x63u}, - {0xC4u, 0x3Bu}, - {0xCAu, 0x9Fu}, - {0xCCu, 0xFDu}, - {0xCEu, 0x6Eu}, - {0xD6u, 0x0Fu}, - {0xD8u, 0x49u}, - {0xE0u, 0x01u}, - {0xE6u, 0x40u}, - {0xEEu, 0x06u}, - {0x83u, 0x01u}, - {0x97u, 0x01u}, - {0x9Cu, 0x02u}, - {0x9Du, 0x20u}, - {0xABu, 0x80u}, - {0xB2u, 0x04u}, - {0xB3u, 0x08u}, - {0xB7u, 0x80u}, - {0xEAu, 0xA0u}, - {0xEEu, 0x12u}, - {0xACu, 0x02u}, - {0xB1u, 0x20u}, - {0xE8u, 0x20u}, + {0x90u, 0x08u}, + {0x91u, 0x40u}, + {0x9Bu, 0x01u}, + {0xA2u, 0x10u}, + {0xAAu, 0x20u}, + {0xEEu, 0x02u}, + {0xB2u, 0x10u}, + {0xB3u, 0x01u}, + {0xB4u, 0x04u}, + {0xEAu, 0x90u}, + {0xEEu, 0x20u}, {0x12u, 0x08u}, {0x15u, 0x80u}, {0x17u, 0x01u}, {0x33u, 0x01u}, {0x36u, 0x88u}, - {0x38u, 0x01u}, - {0x39u, 0x80u}, - {0x3Cu, 0x04u}, - {0x3Du, 0x80u}, - {0x43u, 0x10u}, - {0x50u, 0x80u}, - {0x5Au, 0x04u}, - {0x5Du, 0x02u}, - {0x61u, 0x20u}, - {0x64u, 0x08u}, - {0x89u, 0x40u}, - {0x8Cu, 0x01u}, - {0x8Du, 0x20u}, + {0x39u, 0x84u}, + {0x3Du, 0x41u}, + {0x40u, 0x08u}, + {0x59u, 0x12u}, + {0x5Fu, 0x02u}, + {0x61u, 0x02u}, + {0x65u, 0x04u}, + {0x81u, 0x40u}, + {0x87u, 0x02u}, + {0x8Du, 0x10u}, {0xC4u, 0xE0u}, {0xCCu, 0xE0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, - {0xD4u, 0x20u}, + {0xD4u, 0x80u}, {0xD6u, 0xC0u}, {0xD8u, 0xC0u}, - {0x31u, 0x20u}, - {0x32u, 0x04u}, + {0xE6u, 0x60u}, + {0x31u, 0x22u}, {0x36u, 0x40u}, {0x37u, 0x04u}, - {0x50u, 0x08u}, - {0x51u, 0x01u}, - {0x55u, 0x08u}, - {0x5Du, 0x02u}, - {0x81u, 0x02u}, - {0x89u, 0x01u}, - {0x94u, 0x04u}, - {0x96u, 0x04u}, + {0x54u, 0x02u}, + {0x56u, 0x80u}, + {0x59u, 0x40u}, + {0x63u, 0x80u}, + {0x85u, 0x04u}, + {0x95u, 0x04u}, {0x9Cu, 0x08u}, - {0x9Fu, 0x10u}, + {0x9Du, 0x02u}, {0xA6u, 0x80u}, - {0xACu, 0x80u}, - {0xADu, 0x02u}, + {0xA9u, 0x04u}, + {0xADu, 0x01u}, + {0xB1u, 0x02u}, {0xCCu, 0xF0u}, - {0xD4u, 0xE0u}, - {0xD6u, 0x80u}, - {0xE6u, 0x20u}, + {0xD4u, 0xC0u}, + {0xD6u, 0x20u}, + {0xD8u, 0x40u}, + {0xE6u, 0x40u}, {0xEAu, 0x10u}, - {0xEEu, 0x10u}, + {0xEEu, 0x80u}, {0x12u, 0x80u}, - {0x80u, 0x08u}, - {0x86u, 0x04u}, - {0x89u, 0x02u}, - {0x8Cu, 0x08u}, - {0x96u, 0x0Cu}, + {0x63u, 0x01u}, + {0x83u, 0x41u}, + {0x8Du, 0x02u}, {0x9Cu, 0x08u}, - {0x9Fu, 0x14u}, - {0xA4u, 0x08u}, - {0xA5u, 0x20u}, + {0x9Du, 0x42u}, + {0x9Fu, 0x04u}, + {0xA5u, 0x22u}, {0xA6u, 0xC0u}, - {0xB4u, 0x04u}, - {0xB5u, 0x08u}, + {0xA7u, 0x40u}, + {0xA8u, 0x02u}, + {0xAAu, 0x80u}, {0xC4u, 0x10u}, - {0xE2u, 0xC0u}, - {0x63u, 0x08u}, + {0xD6u, 0x40u}, + {0xE2u, 0xA0u}, + {0xEAu, 0xA0u}, {0x83u, 0x04u}, {0x85u, 0x20u}, - {0x86u, 0x04u}, - {0x87u, 0x08u}, - {0x96u, 0x08u}, - {0x9Du, 0x02u}, - {0x9Fu, 0x14u}, - {0xA5u, 0x20u}, + {0x89u, 0x42u}, + {0x9Cu, 0x08u}, + {0x9Du, 0x41u}, + {0x9Fu, 0x04u}, + {0xA5u, 0x22u}, {0xA6u, 0x40u}, - {0xD8u, 0x40u}, + {0xA9u, 0x01u}, {0xE2u, 0x90u}, - {0xE6u, 0x50u}, - {0x09u, 0x80u}, - {0x0Eu, 0x80u}, - {0x13u, 0x01u}, - {0x50u, 0x80u}, - {0x51u, 0x02u}, - {0x54u, 0x04u}, - {0x56u, 0x01u}, - {0x8Fu, 0x01u}, + {0xE8u, 0x20u}, + {0x09u, 0x40u}, + {0x0Fu, 0x20u}, + {0x13u, 0x08u}, + {0x51u, 0x08u}, + {0x53u, 0x02u}, + {0x57u, 0x20u}, + {0x5Cu, 0x40u}, + {0x81u, 0x08u}, {0xC2u, 0x06u}, {0xC4u, 0x08u}, {0xD4u, 0x07u}, {0xD6u, 0x04u}, - {0xE6u, 0x08u}, - {0x02u, 0x08u}, - {0x05u, 0x40u}, - {0x06u, 0x20u}, - {0x08u, 0x24u}, - {0x0Du, 0x08u}, - {0x0Eu, 0x08u}, - {0x84u, 0x20u}, - {0x85u, 0x02u}, - {0x88u, 0x04u}, - {0x8Cu, 0x80u}, - {0x8Du, 0x88u}, - {0x9Eu, 0x21u}, - {0xA1u, 0x80u}, - {0xA4u, 0x84u}, - {0xA5u, 0x02u}, - {0xAAu, 0x20u}, - {0xAEu, 0x40u}, + {0x03u, 0x08u}, + {0x06u, 0x08u}, + {0x07u, 0x80u}, + {0x0Bu, 0x84u}, + {0x0Cu, 0x08u}, + {0x0Du, 0x10u}, + {0x82u, 0x08u}, + {0x84u, 0x08u}, + {0x87u, 0x40u}, + {0x8Bu, 0x04u}, + {0x8Cu, 0x40u}, + {0x8Fu, 0x08u}, + {0x94u, 0x40u}, + {0xA1u, 0x40u}, + {0xA3u, 0x10u}, + {0xA7u, 0x02u}, + {0xABu, 0x08u}, + {0xB3u, 0x20u}, {0xC0u, 0x07u}, {0xC2u, 0x0Fu}, + {0xE0u, 0x02u}, {0xE2u, 0x08u}, - {0xE4u, 0x02u}, - {0xE6u, 0x09u}, - {0x88u, 0x04u}, - {0xA4u, 0x04u}, - {0xAAu, 0x0Cu}, - {0xB1u, 0x40u}, - {0xB6u, 0x01u}, - {0xE0u, 0x04u}, - {0xEAu, 0x01u}, - {0xECu, 0x02u}, - {0x0Bu, 0x88u}, + {0xE6u, 0x04u}, + {0xE8u, 0x01u}, + {0x8Fu, 0x10u}, + {0xA1u, 0x40u}, + {0xA3u, 0x10u}, + {0xABu, 0x82u}, + {0xB1u, 0x10u}, + {0xE2u, 0x08u}, + {0xEEu, 0x04u}, + {0x09u, 0x40u}, + {0x0Bu, 0x80u}, {0x0Fu, 0x41u}, {0x83u, 0x01u}, - {0x87u, 0x44u}, + {0x87u, 0x40u}, + {0x89u, 0x40u}, + {0xB1u, 0x40u}, {0xC2u, 0x0Fu}, - {0x8Fu, 0x10u}, - {0x9Du, 0x02u}, - {0x9Fu, 0x10u}, - {0xA3u, 0x08u}, - {0xABu, 0x04u}, + {0xE6u, 0x04u}, + {0xEEu, 0x04u}, + {0x88u, 0x08u}, + {0x9Cu, 0x08u}, + {0x9Du, 0x01u}, + {0xA3u, 0x20u}, {0xAEu, 0x40u}, - {0xEEu, 0x60u}, - {0x05u, 0x02u}, - {0x57u, 0x08u}, - {0x5Du, 0x40u}, - {0x91u, 0x40u}, - {0x9Du, 0x02u}, - {0xA3u, 0x08u}, - {0xB5u, 0x40u}, + {0xB3u, 0x20u}, + {0xEEu, 0x40u}, + {0x05u, 0x01u}, + {0x57u, 0x21u}, + {0x9Du, 0x01u}, + {0xA3u, 0x21u}, + {0xAFu, 0x01u}, {0xC0u, 0x20u}, {0xD4u, 0x40u}, {0xD6u, 0x20u}, + {0xEEu, 0x10u}, {0xAFu, 0x40u}, {0x00u, 0x03u}, {0x08u, 0x03u}, {0x0Au, 0x03u}, - {0x10u, 0x03u}, - {0x1Au, 0x03u}, + {0x0Eu, 0x02u}, + {0x10u, 0x01u}, + {0x1Au, 0x01u}, {0x00u, 0xFDu}, {0x01u, 0xABu}, {0x02u, 0x02u}, @@ -1538,41 +1587,17 @@ void cyfitter_cfg(void) uint16 size; } CYPACKED_ATTR cfg_memset_t; - - CYPACKED typedef struct { - void CYFAR *dest; - const void CYCODE *src; - uint16 size; - } CYPACKED_ATTR cfg_memcpy_t; - static const cfg_memset_t CYCODE cfg_memset_list [] = { /* address, size */ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT1_DR), 16u}, - {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1024u}, - {(void CYFAR *)(CYDEV_UCFG_B0_P2_U1_BASE), 2944u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u}, }; - /* UDB_1_3_0_CONFIG Address: CYDEV_UCFG_B0_P2_U0_BASE Size (bytes): 128 */ - static const uint8 CYCODE BS_UDB_1_3_0_CONFIG_VAL[] = { - 0x8Du, 0x00u, 0x00u, 0x00u, 0x8Du, 0x09u, 0x00u, 0x12u, 0x8Du, 0x00u, 0x00u, 0x01u, 0x0Du, 0x00u, 0x80u, 0x30u, - 0x02u, 0x00u, 0x0Du, 0x00u, 0x00u, 0x00u, 0x80u, 0x09u, 0x12u, 0x00u, 0x44u, 0x06u, 0x60u, 0x00u, 0x00u, 0x08u, - 0x8Du, 0x09u, 0x00u, 0x24u, 0x00u, 0x00u, 0x00u, 0x00u, 0x22u, 0x00u, 0x18u, 0x00u, 0x11u, 0x00u, 0x22u, 0x00u, - 0x0Fu, 0x38u, 0x00u, 0x00u, 0x80u, 0x07u, 0x70u, 0x00u, 0x80u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, - 0x26u, 0x05u, 0x40u, 0x00u, 0x03u, 0xBEu, 0xFBu, 0xDCu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x04u, 0x10u, 0x00u, 0x00u, 0x01u, - 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; - - static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { - /* dest, src, size */ - {(void CYFAR *)(CYDEV_UCFG_B0_P2_U0_BASE), BS_UDB_1_3_0_CONFIG_VAL, 128u}, - }; - uint8 CYDATA i; /* Zero out critical memory blocks before beginning configuration */ @@ -1582,16 +1607,6 @@ void cyfitter_cfg(void) CYMEMZERO(ms->address, (uint32)(ms->size)); } - /* Copy device configuration data into registers */ - for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) - { - const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i]; - void * CYDATA destPtr = mc->dest; - const void CYCODE * CYDATA srcPtr = mc->src; - uint16 CYDATA numBytes = mc->size; - CYCONFIGCPYCODE(destPtr, srcPtr, numBytes); - } - cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); /* Perform normal device configuration. Order is not critical for these items. */ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index b4c3cb67..9362175a 100644 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -84,28 +84,28 @@ /* SCSI_CTL_PHASE */ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL /* SCSI_Out_Bits */ .set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01 @@ -630,34 +630,34 @@ .set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL -.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_RxStsReg__4__POS, 4 .set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 @@ -665,13 +665,17 @@ .set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 -.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK -.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB05_MSK +.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL +.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB05_ST .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 @@ -681,30 +685,28 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK -.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL -.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL -.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB04_05_D1 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB04_05_F0 -.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB04_05_F1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB04_A0_A1 -.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB04_A0 -.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB04_A1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB04_D0_D1 -.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB04_D0 -.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB04_D1 -.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1 -.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB04_F0 -.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB04_F1 +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB05_06_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB05_06_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB05_06_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB05_06_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB05_06_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB05_06_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB05_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB05_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB05_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB05_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB05_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB05_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB05_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB05_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB05_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB05_F1 +.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL /* USBFS_dp_int */ .set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -1183,17 +1185,6 @@ .set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 .set SD_Data_Clk__PM_STBY_MSK, 0x01 -/* SD_Init_Clk */ -.set SD_Init_Clk__CFG0, CYREG_CLKDIST_DCFG3_CFG0 -.set SD_Init_Clk__CFG1, CYREG_CLKDIST_DCFG3_CFG1 -.set SD_Init_Clk__CFG2, CYREG_CLKDIST_DCFG3_CFG2 -.set SD_Init_Clk__CFG2_SRC_SEL_MASK, 0x07 -.set SD_Init_Clk__INDEX, 0x03 -.set SD_Init_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2 -.set SD_Init_Clk__PM_ACT_MSK, 0x08 -.set SD_Init_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 -.set SD_Init_Clk__PM_STBY_MSK, 0x08 - /* timer_clock */ .set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0 .set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1 @@ -1208,8 +1199,8 @@ /* scsiTarget */ .set scsiTarget_StatusReg__0__MASK, 0x01 .set scsiTarget_StatusReg__0__POS, 0 -.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL -.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 .set scsiTarget_StatusReg__2__MASK, 0x04 @@ -1219,9 +1210,9 @@ .set scsiTarget_StatusReg__4__MASK, 0x10 .set scsiTarget_StatusReg__4__POS, 4 .set scsiTarget_StatusReg__MASK, 0x1F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB04_MSK -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB04_ST +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB00_MSK +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB00_ST .set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL .set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST .set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK @@ -1268,9 +1259,6 @@ .set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL .set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -/* SD_Clk_Ctl */ -.set SD_Clk_Ctl_Sync_ctrl_reg__REMOVED, 1 - /* USBFS_ep_0 */ .set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index b9e9e28b..aefac3b5 100644 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -84,28 +84,28 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_CTL_PHASE */ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL /* SCSI_Out_Bits */ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 @@ -630,34 +630,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SDCard_BSPIM */ -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -665,13 +665,17 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK +SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -681,30 +685,28 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1 +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB05_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB05_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB05_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB05_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB05_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB05_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL /* USBFS_dp_int */ USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1183,17 +1185,6 @@ SD_Data_Clk__PM_ACT_MSK EQU 0x01 SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 SD_Data_Clk__PM_STBY_MSK EQU 0x01 -/* SD_Init_Clk */ -SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG3_CFG0 -SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG3_CFG1 -SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG3_CFG2 -SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07 -SD_Init_Clk__INDEX EQU 0x03 -SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SD_Init_Clk__PM_ACT_MSK EQU 0x08 -SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SD_Init_Clk__PM_STBY_MSK EQU 0x08 - /* timer_clock */ timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 @@ -1208,8 +1199,8 @@ timer_clock__PM_STBY_MSK EQU 0x04 /* scsiTarget */ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1219,9 +1210,9 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK @@ -1268,9 +1259,6 @@ scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1 scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -/* SD_Clk_Ctl */ -SD_Clk_Ctl_Sync_ctrl_reg__REMOVED EQU 1 - /* USBFS_ep_0 */ USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index 79c7a64b..2145cf34 100644 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -84,28 +84,28 @@ USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_CTL_PHASE SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL ; SCSI_Out_Bits SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 @@ -630,34 +630,34 @@ SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SDCard_BSPIM -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_RxStsReg__4__POS EQU 4 SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -665,13 +665,17 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5 SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 -SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK -SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK +SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 @@ -681,30 +685,28 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST -SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1 -SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0 -SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1 -SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1 -SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0 -SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1 -SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1 -SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0 -SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1 -SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 -SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0 -SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1 +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB05_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB05_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB05_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB05_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB05_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB05_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL ; USBFS_dp_int USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -1183,17 +1185,6 @@ SD_Data_Clk__PM_ACT_MSK EQU 0x01 SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 SD_Data_Clk__PM_STBY_MSK EQU 0x01 -; SD_Init_Clk -SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG3_CFG0 -SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG3_CFG1 -SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG3_CFG2 -SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07 -SD_Init_Clk__INDEX EQU 0x03 -SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SD_Init_Clk__PM_ACT_MSK EQU 0x08 -SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SD_Init_Clk__PM_STBY_MSK EQU 0x08 - ; timer_clock timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 @@ -1208,8 +1199,8 @@ timer_clock__PM_STBY_MSK EQU 0x04 ; scsiTarget scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 scsiTarget_StatusReg__2__MASK EQU 0x04 @@ -1219,9 +1210,9 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK @@ -1268,9 +1259,6 @@ scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1 scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -; SD_Clk_Ctl -SD_Clk_Ctl_Sync_ctrl_reg__REMOVED EQU 1 - ; USBFS_ep_0 USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index b47a2048..d49b3af1 100644 --- a/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -21,9 +21,7 @@ #include #include #include -#include #include -#include #include #include #include diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx index 4acdeea3..e13d32d6 100644 --- a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -1,10 +1,12 @@ - - + + + + @@ -62,11 +64,8 @@ - - - - - + + @@ -74,6 +73,7 @@ + @@ -154,39 +154,36 @@ - - - - + + - - + + - - - + - + + + + - + - - - - + + + - - - + + + - \ No newline at end of file diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit index 1850b93d..f9a09137 100644 Binary files a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit differ diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj index df390351..870f81c3 100755 --- a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyprj @@ -1244,14 +1244,14 @@ - + - + @@ -1260,7 +1260,7 @@ - + @@ -1304,14 +1304,14 @@ - + - + @@ -1320,7 +1320,7 @@ - + diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd index f326a568..55e6e85b 100644 --- a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd +++ b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd @@ -6,6 +6,27 @@ 8 32 + + SCSI_Out_Ctl + No description available + 0x40006577 + + 0 + 0x1 + registers + + + + SCSI_Out_Ctl_CONTROL_REG + No description available + 0x0 + 8 + read-write + 0 + 0 + + + SCSI_Out_Bits No description available @@ -319,27 +340,6 @@ - - SCSI_Out_Ctl - No description available - 0x40006577 - - 0 - 0x1 - registers - - - - SCSI_Out_Ctl_CONTROL_REG - No description available - 0x0 - 8 - read-write - 0 - 0 - - - USBFS USBFS @@ -827,7 +827,7 @@ SCSI_CTL_PHASE No description available - 0x40006472 + 0x40006475 0 0x1 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index 3602a0d7..82399df9 100755 Binary files a/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ diff --git a/software/SCSI2SD/src/config.c b/software/SCSI2SD/src/config.c index fa0693bf..f03a0a8f 100755 --- a/software/SCSI2SD/src/config.c +++ b/software/SCSI2SD/src/config.c @@ -238,6 +238,7 @@ void configPoll() } } +#ifdef MM_DEBUG void debugPoll() { if (!usbReady) @@ -286,6 +287,7 @@ CY_ISR(debugTimerISR) debugPoll(); CyExitCriticalSection(savedIntrStatus); } +#endif void debugInit() { diff --git a/software/SCSI2SD/src/disk.c b/software/SCSI2SD/src/disk.c index 3974ccff..188b4b55 100755 --- a/software/SCSI2SD/src/disk.c +++ b/software/SCSI2SD/src/disk.c @@ -463,6 +463,8 @@ void scsiDiskPoll() if (scsiDev.phase == DATA_IN && transfer.currentBlock != transfer.blocks) { + scsiEnterPhase(DATA_IN); + int totalSDSectors = transfer.blocks * SDSectorsPerSCSISector(); uint32_t sdLBA = SCSISector2SD(transfer.lba); int buffers = sizeof(scsiDev.data) / SD_SECTOR_SIZE; @@ -519,6 +521,8 @@ void scsiDiskPoll() else if (scsiDev.phase == DATA_OUT && transfer.currentBlock != transfer.blocks) { + scsiEnterPhase(DATA_OUT); + int totalSDSectors = transfer.blocks * SDSectorsPerSCSISector(); int buffers = sizeof(scsiDev.data) / SD_SECTOR_SIZE; int prep = 0; diff --git a/software/SCSI2SD/src/scsi.h b/software/SCSI2SD/src/scsi.h index 5da10f51..c7c1d2d9 100755 --- a/software/SCSI2SD/src/scsi.h +++ b/software/SCSI2SD/src/scsi.h @@ -20,7 +20,8 @@ // Set this to true to log SCSI commands and status information via // USB HID packets. The can be captured and viewed in wireshark. // For windows users, capture using USBPcap http://desowin.org/usbpcap/ -#define MM_DEBUG 0 +//#define MM_DEBUG 1 +#undef MM_DEBUG #include "geometry.h" #include "sense.h" diff --git a/software/SCSI2SD/src/sd.c b/software/SCSI2SD/src/sd.c index 19e02fde..7d5a11ec 100755 --- a/software/SCSI2SD/src/sd.c +++ b/software/SCSI2SD/src/sd.c @@ -647,8 +647,9 @@ int sdInit() // Set the SPI clock for 400kHz transfers // 25MHz / 400kHz approx factor of 63. + // The register contains (divider - 1) uint16_t clkDiv25MHz = SD_Data_Clk_GetDividerRegister(); - SD_Data_Clk_SetDivider(clkDiv25MHz * 63); + SD_Data_Clk_SetDivider(((clkDiv25MHz + 1) * 63) - 1); // Wait for the clock to settle. CyDelayUs(1);