From: Michael McMaster Date: Sat, 2 Jan 2021 12:51:19 +0000 (+1000) Subject: Add SPI NOR Flash as a backend storage device X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=125d1d9e82d82ea63a854755f1bc98421a002140;p=SCSI2SD.git Add SPI NOR Flash as a backend storage device --- diff --git a/software/SCSI2SD/src/cdrom.c b/software/SCSI2SD/src/cdrom.c index 9b40859..9b28326 100755 --- a/software/SCSI2SD/src/cdrom.c +++ b/software/SCSI2SD/src/cdrom.c @@ -152,8 +152,8 @@ static void doReadTOC(int MSF, uint8_t track, uint16_t allocationLength) if (track > 1) { scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB; scsiDev.phase = STATUS; } else @@ -162,8 +162,9 @@ static void doReadTOC(int MSF, uint8_t track, uint16_t allocationLength) memcpy(scsiDev.data, SimpleTOC, len); uint32_t capacity = getScsiCapacity( + scsiDev.target->device, scsiDev.target->cfg->sdSectorStart, - scsiDev.target->liveCfg.bytesPerSector, + scsiDev.target->state.bytesPerSector, scsiDev.target->cfg->scsiSectors); // Replace start of leadout track @@ -213,8 +214,8 @@ static void doReadFullTOC(int convertBCD, uint8_t session, uint16_t allocationLe if (session > 1) { scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB; scsiDev.phase = STATUS; } else @@ -297,8 +298,8 @@ int scsiCDRomCommand() default: { scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB; scsiDev.phase = STATUS; } } diff --git a/software/SCSI2SD/src/config.c b/software/SCSI2SD/src/config.c index cc3233e..e7176e8 100755 --- a/software/SCSI2SD/src/config.c +++ b/software/SCSI2SD/src/config.c @@ -31,7 +31,7 @@ #include -static const uint16_t FIRMWARE_VERSION = 0x0484; +static const uint16_t FIRMWARE_VERSION = 0x0485; // 1 flash row static const uint8_t DEFAULT_CONFIG[256] = @@ -63,7 +63,7 @@ static int usbInEpState; static int usbDebugEpState; static int usbReady; -static void initBoardConfig(BoardConfig* config) { +static void initBoardConfig(S2S_BoardConfig* config) { memcpy( config, ( @@ -71,7 +71,7 @@ static void initBoardConfig(BoardConfig* config) { (CY_FLASH_SIZEOF_ARRAY * (size_t) SCSI_CONFIG_ARRAY) + (CY_FLASH_SIZEOF_ROW * SCSI_CONFIG_BOARD_ROW) ), - sizeof(BoardConfig)); + sizeof(S2S_BoardConfig)); if (memcmp(config->magic, "BCFG", 4)) { // Set a default from the deprecated flags, or 0 if @@ -83,7 +83,7 @@ static void initBoardConfig(BoardConfig* config) { } } -void configInit(BoardConfig* config) +void configInit(S2S_BoardConfig* config) { // The USB block will be powered by an internal 3.3V regulator. // The PSoC must be operating between 4.6V and 5V for the regulator @@ -93,7 +93,7 @@ void configInit(BoardConfig* config) usbReady = 0; // We don't know if host is connected yet. int invalid = 1; - uint8_t* rawConfig = getConfigByIndex(0); + uint8_t* rawConfig = (uint8_t*)getConfigByIndex(0); int i; for (i = 0; i < 64; ++i) { @@ -175,9 +175,9 @@ pingCommand() static void sdInfoCommand() { - uint8_t response[sizeof(sdDev.csd) + sizeof(sdDev.cid)]; - memcpy(response, sdDev.csd, sizeof(sdDev.csd)); - memcpy(response + sizeof(sdDev.csd), sdDev.cid, sizeof(sdDev.cid)); + uint8_t response[sizeof(sdCard.csd) + sizeof(sdCard.cid)]; + memcpy(response, sdCard.csd, sizeof(sdCard.csd)); + memcpy(response + sizeof(sdCard.csd), sdCard.cid, sizeof(sdCard.cid)); hidPacket_send(response, sizeof(response)); } @@ -195,6 +195,100 @@ scsiTestCommand() hidPacket_send(response, sizeof(response)); } +static void +deviceListCommand() +{ + int deviceCount; + S2S_Device** devices = s2s_GetDevices(&deviceCount); + + uint8_t response[16] = // Make larger if there can be more than 2 devices + { + deviceCount + }; + + int pos = 1; + + for (int i = 0; i < deviceCount; ++i) + { + response[pos++] = devices[i]->deviceType; + + uint32_t capacity = devices[i]->getCapacity(devices[i]); + response[pos++] = capacity >> 24; + response[pos++] = capacity >> 16; + response[pos++] = capacity >> 8; + response[pos++] = capacity; + } + + hidPacket_send(response, pos); +} + +static void +deviceEraseCommand(const uint8_t* cmd) +{ + int deviceCount; + S2S_Device** devices = s2s_GetDevices(&deviceCount); + + uint32_t sectorNum = + ((uint32_t)cmd[2]) << 24 | + ((uint32_t)cmd[3]) << 16 | + ((uint32_t)cmd[4]) << 8 | + ((uint32_t)cmd[5]); + + uint32_t count = + ((uint32_t)cmd[6]) << 24 | + ((uint32_t)cmd[7]) << 16 | + ((uint32_t)cmd[8]) << 8 | + ((uint32_t)cmd[9]); + + devices[cmd[1]]->erase(devices[cmd[1]], sectorNum, count); + + uint8_t response[] = + { + CONFIG_STATUS_GOOD + }; + hidPacket_send(response, sizeof(response)); +} + +static void +deviceWriteCommand(const uint8_t* cmd) +{ + int deviceCount; + S2S_Device** devices = s2s_GetDevices(&deviceCount); + + uint32_t sectorNum = + ((uint32_t)cmd[2]) << 24 | + ((uint32_t)cmd[3]) << 16 | + ((uint32_t)cmd[4]) << 8 | + ((uint32_t)cmd[5]); + + devices[cmd[1]]->write(devices[cmd[1]], sectorNum, 1, &cmd[6]); + + uint8_t response[] = + { + CONFIG_STATUS_GOOD + }; + hidPacket_send(response, sizeof(response)); +} + + +static void +deviceReadCommand(const uint8_t* cmd) +{ + int deviceCount; + S2S_Device** devices = s2s_GetDevices(&deviceCount); + + uint32_t sectorNum = + ((uint32_t)cmd[2]) << 24 | + ((uint32_t)cmd[3]) << 16 | + ((uint32_t)cmd[4]) << 8 | + ((uint32_t)cmd[5]); + + uint8_t response[512]; + devices[cmd[1]]->read(devices[cmd[1]], sectorNum, 1, &response[0]); + + hidPacket_send(&response[0], 512); +} + static void processCommand(const uint8_t* cmd, size_t cmdSize) { @@ -224,6 +318,22 @@ processCommand(const uint8_t* cmd, size_t cmdSize) scsiTestCommand(); break; + case S2S_CMD_DEV_LIST: + deviceListCommand(); + break; + + case S2S_CMD_DEV_ERASE: + deviceEraseCommand(cmd); + break; + + case S2S_CMD_DEV_WRITE: + deviceWriteCommand(cmd); + break; + + case S2S_CMD_DEV_READ: + deviceReadCommand(cmd); + break; + case CONFIG_NONE: // invalid default: break; @@ -340,16 +450,16 @@ void debugPoll() hidBuffer[23] = scsiDev.msgCount; hidBuffer[24] = scsiDev.cmdCount; hidBuffer[25] = scsiDev.watchdogTick; - hidBuffer[26] = blockDev.state; + hidBuffer[26] = 0; // OBSOLETE. Previously media state hidBuffer[27] = scsiDev.lastSenseASC >> 8; hidBuffer[28] = scsiDev.lastSenseASC; hidBuffer[29] = scsiReadDBxPins(); hidBuffer[30] = LastTrace; - hidBuffer[58] = sdDev.capacity >> 24; - hidBuffer[59] = sdDev.capacity >> 16; - hidBuffer[60] = sdDev.capacity >> 8; - hidBuffer[61] = sdDev.capacity; + hidBuffer[58] = sdCard.capacity >> 24; + hidBuffer[59] = sdCard.capacity >> 16; + hidBuffer[60] = sdCard.capacity >> 8; + hidBuffer[61] = sdCard.capacity; hidBuffer[62] = FIRMWARE_VERSION >> 8; hidBuffer[63] = FIRMWARE_VERSION; @@ -404,14 +514,14 @@ void configSave(int scsiId, uint16_t bytesPerSector) int cfgIdx; for (cfgIdx = 0; cfgIdx < MAX_SCSI_TARGETS; ++cfgIdx) { - const TargetConfig* tgt = getConfigByIndex(cfgIdx); + const S2S_TargetCfg* tgt = getConfigByIndex(cfgIdx); if ((tgt->scsiId & CONFIG_TARGET_ID_BITS) == scsiId) { // Save row to flash // We only save the first row of the configuration // this contains the parameters changeable by a MODE SELECT command uint8_t rowData[CYDEV_FLS_ROW_SIZE]; - TargetConfig* rowCfgData = (TargetConfig*)&rowData; + S2S_TargetCfg* rowCfgData = (S2S_TargetCfg*)&rowData; memcpy(rowCfgData, tgt, sizeof(rowData)); rowCfgData->bytesPerSector = bytesPerSector; @@ -426,12 +536,12 @@ void configSave(int scsiId, uint16_t bytesPerSector) } -const TargetConfig* getConfigByIndex(int i) +const S2S_TargetCfg* getConfigByIndex(int i) { if (i <= 3) { size_t row = SCSI_CONFIG_0_ROW + (i * SCSI_CONFIG_ROWS); - return (const TargetConfig*) + return (const S2S_TargetCfg*) ( CY_FLASH_BASE + (CY_FLASH_SIZEOF_ARRAY * (size_t) SCSI_CONFIG_ARRAY) + @@ -439,7 +549,7 @@ const TargetConfig* getConfigByIndex(int i) ); } else { size_t row = SCSI_CONFIG_4_ROW + ((i-4) * SCSI_CONFIG_ROWS); - return (const TargetConfig*) + return (const S2S_TargetCfg*) ( CY_FLASH_BASE + (CY_FLASH_SIZEOF_ARRAY * (size_t) SCSI_CONFIG_ARRAY) + @@ -448,12 +558,12 @@ const TargetConfig* getConfigByIndex(int i) } } -const TargetConfig* getConfigById(int scsiId) +const S2S_TargetCfg* getConfigById(int scsiId) { int i; for (i = 0; i < MAX_SCSI_TARGETS; ++i) { - const TargetConfig* tgt = getConfigByIndex(i); + const S2S_TargetCfg* tgt = getConfigByIndex(i); if ((tgt->scsiId & CONFIG_TARGET_ID_BITS) == scsiId) { return tgt; diff --git a/software/SCSI2SD/src/config.h b/software/SCSI2SD/src/config.h index 2c47a1e..42b0fc5 100755 --- a/software/SCSI2SD/src/config.h +++ b/software/SCSI2SD/src/config.h @@ -20,12 +20,12 @@ #include "device.h" #include "scsi2sd.h" -void configInit(BoardConfig* config); +void configInit(S2S_BoardConfig* config); void debugInit(void); void configPoll(void); void configSave(int scsiId, uint16_t byesPerSector); -const TargetConfig* getConfigByIndex(int index); -const TargetConfig* getConfigById(int scsiId); +const S2S_TargetCfg* getConfigByIndex(int index); +const S2S_TargetCfg* getConfigById(int scsiId); #endif diff --git a/software/SCSI2SD/src/diagnostic.c b/software/SCSI2SD/src/diagnostic.c index d8f6477..a359df3 100755 --- a/software/SCSI2SD/src/diagnostic.c +++ b/software/SCSI2SD/src/diagnostic.c @@ -50,8 +50,8 @@ void scsiSendDiagnostic() // Nowhere to store this data! // Shouldn't happen - our buffer should be many magnitudes larger // than the required size for diagnostic parameters. - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB; scsiDev.status = CHECK_CONDITION; scsiDev.phase = STATUS; } @@ -95,14 +95,14 @@ void scsiReceiveDiagnostic() // 64bit linear address, then convert back again. uint64 fromByteAddr = scsiByteAddress( - scsiDev.target->liveCfg.bytesPerSector, + scsiDev.target->state.bytesPerSector, scsiDev.target->cfg->headsPerCylinder, scsiDev.target->cfg->sectorsPerTrack, suppliedFmt, &scsiDev.data[6]); scsiSaveByteAddress( - scsiDev.target->liveCfg.bytesPerSector, + scsiDev.target->state.bytesPerSector, scsiDev.target->cfg->headsPerCylinder, scsiDev.target->cfg->sectorsPerTrack, translateFmt, @@ -121,8 +121,8 @@ void scsiReceiveDiagnostic() { // error. scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB; scsiDev.phase = STATUS; } @@ -169,8 +169,8 @@ void scsiReadBuffer() { // error. scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB; scsiDev.phase = STATUS; } } @@ -208,8 +208,8 @@ void scsiWriteBuffer() { // error. scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB; scsiDev.phase = STATUS; } } @@ -219,7 +219,7 @@ void scsiWriteBuffer() // Section 4.3.14 void scsiWriteSectorBuffer() { - scsiDev.dataLen = scsiDev.target->liveCfg.bytesPerSector; + scsiDev.dataLen = scsiDev.target->state.bytesPerSector; scsiDev.phase = DATA_OUT; scsiDev.postDataOutHook = doWriteBuffer; } diff --git a/software/SCSI2SD/src/disk.c b/software/SCSI2SD/src/disk.c index 5c5a1de..540d098 100755 --- a/software/SCSI2SD/src/disk.c +++ b/software/SCSI2SD/src/disk.c @@ -28,24 +28,8 @@ #include // Global -BlockDevice blockDev; Transfer transfer; -static int doSdInit() -{ - int result = 0; - if (blockDev.state & DISK_PRESENT) - { - result = sdInit(); - - if (result) - { - blockDev.state = blockDev.state | DISK_INITIALISED; - } - } - return result; -} - // Callback once all data has been read in the data out phase. static void doFormatUnitComplete(void) { @@ -92,8 +76,8 @@ static void doFormatUnitHeader(void) { // Save the "MODE SELECT savable parameters" configSave( - scsiDev.target->targetId, - scsiDev.target->liveCfg.bytesPerSector); + scsiDev.target->cfg->scsiId & CONFIG_TARGET_ID_BITS, + scsiDev.target->state.bytesPerSector); } if (IP) @@ -123,8 +107,9 @@ static void doReadCapacity() int pmi = scsiDev.cdb[8] & 1; uint32_t capacity = getScsiCapacity( + scsiDev.target->device, scsiDev.target->cfg->sdSectorStart, - scsiDev.target->liveCfg.bytesPerSector, + scsiDev.target->state.bytesPerSector, scsiDev.target->cfg->scsiSectors); if (!pmi && lba) @@ -134,8 +119,8 @@ static void doReadCapacity() // assume that delays are constant across each block. But the spec // says we must return this error if pmi is specified incorrectly. scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB; scsiDev.phase = STATUS; } else if (capacity > 0) @@ -147,7 +132,7 @@ static void doReadCapacity() scsiDev.data[2] = highestBlock >> 8; scsiDev.data[3] = highestBlock; - uint32_t bytesPerSector = scsiDev.target->liveCfg.bytesPerSector; + uint32_t bytesPerSector = scsiDev.target->state.bytesPerSector; scsiDev.data[4] = bytesPerSector >> 24; scsiDev.data[5] = bytesPerSector >> 16; scsiDev.data[6] = bytesPerSector >> 8; @@ -158,8 +143,8 @@ static void doReadCapacity() else { scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = NOT_READY; - scsiDev.target->sense.asc = MEDIUM_NOT_PRESENT; + scsiDev.target->state.sense.code = NOT_READY; + scsiDev.target->state.sense.asc = MEDIUM_NOT_PRESENT; scsiDev.phase = STATUS; } } @@ -172,19 +157,22 @@ static void doWrite(uint32 lba, uint32 blocks) CyDelay(10); } - uint32_t bytesPerSector = scsiDev.target->liveCfg.bytesPerSector; + uint32_t bytesPerSector = scsiDev.target->state.bytesPerSector; + MEDIA_STATE* mediaState = &(scsiDev.target->device->mediaState); - if (unlikely(blockDev.state & DISK_WP) || - unlikely(scsiDev.target->cfg->deviceType == CONFIG_OPTICAL)) + if (unlikely(*mediaState & MEDIA_WP) || + unlikely(scsiDev.target->cfg->deviceType == CONFIG_OPTICAL) || + (scsiDev.target->cfg->storageDevice != CONFIG_STOREDEVICE_SD)) { scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = WRITE_PROTECTED; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = WRITE_PROTECTED; scsiDev.phase = STATUS; } else if (unlikely(((uint64) lba) + blocks > getScsiCapacity( + scsiDev.target->device, scsiDev.target->cfg->sdSectorStart, bytesPerSector, scsiDev.target->cfg->scsiSectors @@ -192,8 +180,8 @@ static void doWrite(uint32 lba, uint32 blocks) )) { scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; scsiDev.phase = STATUS; } else @@ -230,14 +218,15 @@ static void doRead(uint32 lba, uint32 blocks) } uint32_t capacity = getScsiCapacity( + scsiDev.target->device, scsiDev.target->cfg->sdSectorStart, - scsiDev.target->liveCfg.bytesPerSector, + scsiDev.target->state.bytesPerSector, scsiDev.target->cfg->scsiSectors); if (unlikely(((uint64) lba) + blocks > capacity)) { scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; scsiDev.phase = STATUS; } else @@ -248,7 +237,7 @@ static void doRead(uint32 lba, uint32 blocks) scsiDev.phase = DATA_IN; scsiDev.dataLen = 0; // No data yet - uint32_t bytesPerSector = scsiDev.target->liveCfg.bytesPerSector; + uint32_t bytesPerSector = scsiDev.target->state.bytesPerSector; uint32_t sdSectorPerSCSISector = SDSectorsPerSCSISector(bytesPerSector); uint32_t sdSectors = blocks * sdSectorPerSCSISector; @@ -257,7 +246,8 @@ static void doRead(uint32 lba, uint32 blocks) (sdSectors == 1) && !(scsiDev.boardCfg.flags & CONFIG_ENABLE_CACHE) ) || - unlikely(((uint64) lba) + blocks == capacity) + unlikely(((uint64) lba) + blocks == capacity) || + (scsiDev.target->cfg->storageDevice != CONFIG_STOREDEVICE_SD) ) { // We get errors on reading the last sector using a multi-sector @@ -283,14 +273,15 @@ static void doSeek(uint32 lba) { if (lba >= getScsiCapacity( + scsiDev.target->device, scsiDev.target->cfg->sdSectorStart, - scsiDev.target->liveCfg.bytesPerSector, + scsiDev.target->state.bytesPerSector, scsiDev.target->cfg->scsiSectors) ) { scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; scsiDev.phase = STATUS; } else @@ -301,33 +292,35 @@ static void doSeek(uint32 lba) static int doTestUnitReady() { + MEDIA_STATE* mediaState = &(scsiDev.target->device->mediaState); + int ready = 1; - if (likely(blockDev.state == (DISK_STARTED | DISK_PRESENT | DISK_INITIALISED))) + if (likely(*mediaState == (MEDIA_STARTED | MEDIA_PRESENT | MEDIA_INITIALISED))) { // nothing to do. } - else if (unlikely(!(blockDev.state & DISK_STARTED))) + else if (unlikely(!(*mediaState & MEDIA_STARTED))) { ready = 0; scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = NOT_READY; - scsiDev.target->sense.asc = LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED; + scsiDev.target->state.sense.code = NOT_READY; + scsiDev.target->state.sense.asc = LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED; scsiDev.phase = STATUS; } - else if (unlikely(!(blockDev.state & DISK_PRESENT))) + else if (unlikely(!(*mediaState & MEDIA_PRESENT))) { ready = 0; scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = NOT_READY; - scsiDev.target->sense.asc = MEDIUM_NOT_PRESENT; + scsiDev.target->state.sense.code = NOT_READY; + scsiDev.target->state.sense.asc = MEDIUM_NOT_PRESENT; scsiDev.phase = STATUS; } - else if (unlikely(!(blockDev.state & DISK_INITIALISED))) + else if (unlikely(!(*mediaState & MEDIA_INITIALISED))) { ready = 0; scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = NOT_READY; - scsiDev.target->sense.asc = LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE; + scsiDev.target->state.sense.code = NOT_READY; + scsiDev.target->state.sense.asc = LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE; scsiDev.phase = STATUS; } return ready; @@ -347,17 +340,21 @@ int scsiDiskCommand() //int immed = scsiDev.cdb[1] & 1; int start = scsiDev.cdb[4] & 1; + MEDIA_STATE* mediaState = &(scsiDev.target->device->mediaState); if (start) { - blockDev.state = blockDev.state | DISK_STARTED; - if (!(blockDev.state & DISK_INITIALISED)) + *mediaState = *mediaState | MEDIA_STARTED; + if (!(*mediaState & MEDIA_INITIALISED)) { - doSdInit(); + if (*mediaState & MEDIA_PRESENT) + { + *mediaState = *mediaState | MEDIA_INITIALISED; + } } } else { - blockDev.state &= ~DISK_STARTED; + *mediaState &= ~MEDIA_STARTED; } } else if (unlikely(command == 0x00)) @@ -514,8 +511,8 @@ int scsiDiskCommand() // TODO. This means they are supplying data to verify against. // Technically we should probably grab the data and compare it. scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB; scsiDev.phase = STATUS; } } @@ -548,7 +545,7 @@ int scsiDiskCommand() void scsiDiskPoll() { - uint32_t bytesPerSector = scsiDev.target->liveCfg.bytesPerSector; + uint32_t bytesPerSector = scsiDev.target->state.bytesPerSector; if (scsiDev.phase == DATA_IN && transfer.currentBlock != transfer.blocks) @@ -569,6 +566,9 @@ void scsiDiskPoll() int i = 0; int scsiActive = 0; int sdActive = 0; + + int isSDDevice = scsiDev.target->cfg->storageDevice == CONFIG_STOREDEVICE_SD; + while ((i < totalSDSectors) && likely(scsiDev.phase == DATA_IN) && likely(!scsiDev.resetFlag)) @@ -590,11 +590,23 @@ void scsiDiskPoll() CyExitCriticalSection(intr); } - if (sdActive && !sdBusy && sdReadSectorDMAPoll()) - { - sdActive = 0; - prep++; - } + if (isSDDevice) + { + if (sdActive && !sdBusy && sdReadSectorDMAPoll()) + { + sdActive = 0; + prep++; + } + } + else + { + S2S_Device* device = scsiDev.target->device; + if (sdActive && device->readAsyncPoll(device)) + { + sdActive = 0; + prep++; + } + } // Usually SD is slower than the SCSI interface. // Prioritise starting the read of the next sector over starting a @@ -604,16 +616,26 @@ void scsiDiskPoll() (prep - i < buffers) && (prep < totalSDSectors)) { - // Start an SD transfer if we have space. - if (transfer.multiBlock) - { - sdReadMultiSectorDMA(&scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]); - } - else - { - sdReadSingleSectorDMA(sdLBA + prep, &scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]); - } - sdActive = 1; + if (isSDDevice) + { + // Start an SD transfer if we have space. + if (transfer.multiBlock) + { + sdReadMultiSectorDMA(&scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]); + } + else + { + sdReadSingleSectorDMA(sdLBA + prep, &scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]); + } + sdActive = 1; + } + else + { + // Sync Read onboard flash + S2S_Device* device = scsiDev.target->device; + device->readAsync(device, sdLBA + prep, 1, &scsiDev.data[SD_SECTOR_SIZE * (prep % buffers)]); + sdActive = 1; + } } if (scsiActive && !scsiBusy && scsiWriteDMAPoll()) @@ -638,6 +660,15 @@ void scsiDiskPoll() scsiDev.phase = STATUS; } scsiDiskReset(); + + // Wait for current DMA transfer done then deselect (if reset encountered) + if (!isSDDevice) + { + S2S_Device* device = scsiDev.target->device; + while (!device->readAsyncPoll(device)) + { + } + } } else if (scsiDev.phase == DATA_OUT && transfer.currentBlock != transfer.blocks) @@ -799,8 +830,8 @@ void scsiDiskPoll() (scsiDev.boardCfg.flags & CONFIG_ENABLE_PARITY) && (scsiDev.compatMode >= COMPAT_SCSI2)) { - scsiDev.target->sense.code = ABORTED_COMMAND; - scsiDev.target->sense.asc = SCSI_PARITY_ERROR; + scsiDev.target->state.sense.code = ABORTED_COMMAND; + scsiDev.target->state.sense.asc = SCSI_PARITY_ERROR; scsiDev.status = CHECK_CONDITION;; } scsiDev.phase = STATUS; @@ -834,8 +865,6 @@ void scsiDiskInit() { scsiDiskReset(); - // Don't require the host to send us a START STOP UNIT command - blockDev.state = DISK_STARTED; // WP pin not available for micro-sd // TODO read card WP register #if 0 diff --git a/software/SCSI2SD/src/disk.h b/software/SCSI2SD/src/disk.h index df197d7..f78b032 100755 --- a/software/SCSI2SD/src/disk.h +++ b/software/SCSI2SD/src/disk.h @@ -17,25 +17,12 @@ #ifndef DISK_H #define DISK_H -typedef enum -{ - DISK_STARTED = 1, // Controlled via START STOP UNIT - DISK_PRESENT = 2, // SD card is physically present - DISK_INITIALISED = 4, // SD card responded to init sequence - DISK_WP = 8 // Write-protect. -} DISK_STATE; - typedef enum { TRANSFER_READ, TRANSFER_WRITE } TRANSFER_DIR; -typedef struct -{ - int state; -} BlockDevice; - typedef struct { int multiBlock; // True if we're using a multi-block SPI transfer. @@ -45,7 +32,6 @@ typedef struct uint32 currentBlock; } Transfer; -extern BlockDevice blockDev; extern Transfer transfer; void scsiDiskInit(void); diff --git a/software/SCSI2SD/src/flash.c b/software/SCSI2SD/src/flash.c new file mode 100644 index 0000000..0e8783c --- /dev/null +++ b/software/SCSI2SD/src/flash.c @@ -0,0 +1,453 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . + +#include "device.h" +#include "flash.h" + +#include "config.h" +#include "led.h" +#include "time.h" + +typedef struct +{ + S2S_Device dev; + + S2S_Target targets[MAX_SCSI_TARGETS]; + + uint32_t capacity; // in 512 byte blocks + + // CFI info + uint8_t manufacturerID; + uint8_t deviceID[2]; + + +} SpiFlash; + +static void spiFlash_earlyInit(S2S_Device* dev); +static void spiFlash_init(S2S_Device* dev); +static S2S_Target* spiFlash_getTargets(S2S_Device* dev, int* count); +static uint32_t spiFlash_getCapacity(S2S_Device* dev); +static int spiFlash_pollMediaChange(S2S_Device* dev); +static void spiFlash_pollMediaBusy(S2S_Device* dev); +static void spiFlash_erase(S2S_Device* dev, uint32_t sectorNumber, uint32_t count); +static void spiFlash_read(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); +static void spiFlash_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); +static int spiFlash_readAsyncPoll(S2S_Device* dev); +static void spiFlash_write(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); + +SpiFlash spiFlash = { + { + spiFlash_earlyInit, + spiFlash_init, + spiFlash_getTargets, + spiFlash_getCapacity, + spiFlash_pollMediaChange, + spiFlash_pollMediaBusy, + spiFlash_erase, + spiFlash_read, + spiFlash_readAsync, + spiFlash_readAsyncPoll, + spiFlash_write, + 0, // initial mediaState + CONFIG_STOREDEVICE_FLASH + } +}; + +S2S_Device* spiFlashDevice = &(spiFlash.dev); + +// Private DMA variables. +static uint8 spiFlashDMARxChan = CY_DMA_INVALID_CHANNEL; +static uint8 spiFlashDMATxChan = CY_DMA_INVALID_CHANNEL; +static uint8_t spiFlashDmaRxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD }; +static uint8_t spiFlashDmaTxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD }; + +// Source of dummy SPI bytes for DMA +static uint8_t dummyBuffer[2] __attribute__((aligned(4))) = {0xFF, 0xFF}; +// Dummy location for DMA to sink usless data to +static uint8 discardBuffer[2] __attribute__((aligned(4))); + + +volatile uint8_t spiFlashRxDMAComplete = 1; +volatile uint8_t spiFlashTxDMAComplete = 1; + +CY_ISR_PROTO(spiFlashRxISR); +CY_ISR(spiFlashRxISR) +{ + spiFlashRxDMAComplete = 1; +} +CY_ISR_PROTO(spiFlashTxISR); +CY_ISR(spiFlashTxISR) +{ + spiFlashTxDMAComplete = 1; +} + +// Read and write 1 byte. +static uint8_t spiFlashByte(uint8_t value) +{ + NOR_SPI_WriteTxData(value); + while (!(NOR_SPI_ReadRxStatus() & NOR_SPI_STS_RX_FIFO_NOT_EMPTY)) {} + return NOR_SPI_ReadRxData(); +} + +static void spiFlash_earlyInit(S2S_Device* dev) +{ + SpiFlash* spiFlash = (SpiFlash*)dev; + + for (int i = 0; i < MAX_SCSI_TARGETS; ++i) + { + spiFlash->targets[i].device = dev; + + const S2S_TargetCfg* cfg = getConfigByIndex(i); + if (cfg->storageDevice == CONFIG_STOREDEVICE_FLASH) + { + spiFlash->targets[i].cfg = (S2S_TargetCfg*)cfg; + } + else + { + spiFlash->targets[i].cfg = NULL; + } + } + + // Don't require the host to send us a START STOP UNIT command + spiFlash->dev.mediaState = MEDIA_STARTED; + + // DMA stuff + spiFlashDMATxChan = + NOR_TX_DMA_DmaInitialize( + 2, // Bytes per burst + 1, // request per burst + HI16(CYDEV_SRAM_BASE), + HI16(CYDEV_PERIPH_BASE) + ); + + spiFlashDMARxChan = + NOR_RX_DMA_DmaInitialize( + 1, // Bytes per burst + 1, // request per burst + HI16(CYDEV_PERIPH_BASE), + HI16(CYDEV_SRAM_BASE) + ); + + CyDmaChDisable(spiFlashDMATxChan); + CyDmaChDisable(spiFlashDMARxChan); + + NOR_RX_DMA_COMPLETE_StartEx(spiFlashRxISR); + NOR_TX_DMA_COMPLETE_StartEx(spiFlashTxISR); + + spiFlashDmaRxTd[0] = CyDmaTdAllocate(); + spiFlashDmaRxTd[1] = CyDmaTdAllocate(); + + spiFlashDmaTxTd[0] = CyDmaTdAllocate(); + spiFlashDmaTxTd[1] = CyDmaTdAllocate(); +} + +static void spiFlash_init(S2S_Device* dev) +{ + SpiFlash* spiFlash = (SpiFlash*)dev; + spiFlash->capacity = 0; + + nNOR_WP_Write(1); // We don't need write Protect + nNOR_CS_Write(1); // Deselect + + NOR_SPI_Start(); + CyDelayUs(1); + + nNOR_CS_Write(0); // Select + CyDelayCycles(4); // Tiny delay + + // JEDEC standard "Read Identification" command + // returns CFI information + spiFlashByte(0x9F); + + // 1 byte manufacturer ID + spiFlash->manufacturerID = spiFlashByte(0xFF); + + // 2 bytes device ID + spiFlash->deviceID[0] = spiFlashByte(0xFF); + spiFlash->deviceID[1] = spiFlashByte(0xFF); + + uint8_t bytesFollowing = spiFlashByte(0xFF); + + // Chances are this says 0, which means up to 512 bytes. + // But ignore it for now and just get the capacity. + for (int i = 0; i < 0x23; ++i) + { + spiFlashByte(0xFF); + } + + // Capacity is 2^n at offset 0x27 + //spiFlash->capacity = (1 << spiFlashByte(0xFF)) / 512; + // Record value in 512-byte sectors. + spiFlash->capacity = 1 << (spiFlashByte(0xFF) - 9); + + if (spiFlash->capacity > 0) + { + spiFlash->dev.mediaState |= MEDIA_PRESENT | MEDIA_INITIALISED; + } + + // Don't bother reading the rest. Deselecting will cancel the command. + + nNOR_CS_Write(1); // Deselect +} + +static S2S_Target* spiFlash_getTargets(S2S_Device* dev, int* count) +{ + SpiFlash* spiFlash = (SpiFlash*)dev; + *count = MAX_SCSI_TARGETS; + return spiFlash->targets; +} + +static uint32_t spiFlash_getCapacity(S2S_Device* dev) +{ + SpiFlash* spiFlash = (SpiFlash*)dev; + return spiFlash->capacity; +} + +static int spiFlash_pollMediaChange(S2S_Device* dev) +{ + // Non-removable + return 0; +} + +static void spiFlash_pollMediaBusy(S2S_Device* dev) +{ + // Non-removable +} + +static void spiFlash_WaitForWIP() +{ + int inProgress = 1; + while (inProgress) + { + nNOR_CS_Write(0); + uint8_t status = spiFlashByte(0x05); // Read Status Register 1; + inProgress = status & 1; + nNOR_CS_Write(1); + } +} + +static void spiFlash_erase(S2S_Device* dev, uint32_t sectorNumber, uint32_t count) +{ + // SpiFlash* spiFlash = (SpiFlash*)dev; + + nNOR_CS_Write(0); // Select + + // Send the WREN - Write Enable command + spiFlashByte(0x06); + + // We NEED to deselect the device now for writes to work + nNOR_CS_Write(1); + + // For now we assume 256kb sectors. This needs to be expanded to cater for + // different sector sizes. We safely assume it will always be >= 512 bytes. + const uint32_t flashSectorSize = 256*1024; + + // We don't have enough memory to do a read-modify-write cycle, so the caller + // had better line these up on sector boundaries. + for (uint32_t linearAddress = sectorNumber * 512; + linearAddress < (sectorNumber + count) * 512; + linearAddress += flashSectorSize) + { + nNOR_CS_Write(0); + + spiFlashByte(0xDC); + + // 4-byte address + spiFlashByte(linearAddress >> 24); + spiFlashByte(linearAddress >> 16); + spiFlashByte(linearAddress >> 8); + spiFlashByte(linearAddress); + + // Initiate erase + nNOR_CS_Write(1); + + spiFlash_WaitForWIP(); + } + + nNOR_CS_Write(0); + + // Send the WREN - Write Disable command + spiFlashByte(0x04); + + nNOR_CS_Write(1); // Deselect +} + +static void spiFlash_write(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer) +{ + // SpiFlash* spiFlash = (SpiFlash*)dev; + + nNOR_CS_Write(0); // Select + + // Send the WREN - Write Enable command + spiFlashByte(0x06); + + // We NEED to deselect the device now for writes to work + nNOR_CS_Write(1); + + // We're assuming here that the page size is 512 bytes or more. + for (unsigned int i = 0; i < count; ++i) + { + nNOR_CS_Write(0); + + spiFlashByte(0x12); + + uint32_t linearAddress = (sectorNumber + i) * 512; + spiFlashByte(linearAddress >> 24); + spiFlashByte(linearAddress >> 16); + spiFlashByte(linearAddress >> 8); + spiFlashByte(linearAddress); + + for (int off = 0; off < 512; ++off) + { + spiFlashByte(buffer[i * 512 + off]); + } + + // Initiate write + nNOR_CS_Write(1); + + spiFlash_WaitForWIP(); + } + + nNOR_CS_Write(0); + + // Send the WREN - Write Disable command + spiFlashByte(0x04); + + nNOR_CS_Write(1); // Deselect +} + +static void spiFlash_read(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer) +{ + // SpiFlash* spiFlash = (SpiFlash*)dev; + + nNOR_CS_Write(0); // Select + spiFlashByte(0x13); + + uint32_t linearAddress = sectorNumber * 512; + spiFlashByte(linearAddress >> 24); + spiFlashByte(linearAddress >> 16); + spiFlashByte(linearAddress >> 8); + spiFlashByte(linearAddress); + + // There's no harm in reading -extra- data, so keep the FIFO + // one step ahead. + NOR_SPI_WriteTxData(0xFF); + NOR_SPI_WriteTxData(0xFF); + NOR_SPI_WriteTxData(0xFF); + + for (int off = 0; off < count * 512; ++off) + { + NOR_SPI_WriteTxData(0xFF); + + while (!(NOR_SPI_ReadRxStatus() & NOR_SPI_STS_RX_FIFO_NOT_EMPTY)) {} + buffer[off] = NOR_SPI_ReadRxData(); + } + + // Read and discard the extra bytes of data. It was only used to improve + // performance with a full FIFO. + for (int i = 0; i < 3; ++i) + { + while (!(NOR_SPI_ReadRxStatus() & NOR_SPI_STS_RX_FIFO_NOT_EMPTY)) {} + NOR_SPI_ReadRxData(); + } + + nNOR_CS_Write(1); // Deselect +} + +static void spiFlash_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer) +{ + // SpiFlash* spiFlash = (SpiFlash*)dev; + + nNOR_CS_Write(0); // Select + spiFlashByte(0x13); + + uint32_t linearAddress = sectorNumber * 512; + + // DMA implementation + // send is static as the address must remain consistent for the static + // DMA descriptors to work. + // Size must be divisible by 2 to suit 2-byte-burst TX DMA channel. + static uint8_t send[4] __attribute__((aligned(4))); + send[0] = linearAddress >> 24; + send[1] = linearAddress >> 16; + send[2] = linearAddress >> 8; + send[3] = linearAddress; + + // Prepare DMA transfer + CyDmaTdSetConfiguration(spiFlashDmaTxTd[0], sizeof(send), spiFlashDmaTxTd[1], TD_INC_SRC_ADR); + CyDmaTdSetAddress(spiFlashDmaTxTd[0], LO16((uint32)&send), LO16((uint32)NOR_SPI_TXDATA_PTR)); + + CyDmaTdSetConfiguration( + spiFlashDmaTxTd[1], + count * 512, + CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes + NOR_TX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete + ); + CyDmaTdSetAddress( + spiFlashDmaTxTd[1], + LO16((uint32)&dummyBuffer), + LO16((uint32)NOR_SPI_TXDATA_PTR)); + + CyDmaTdSetConfiguration(spiFlashDmaRxTd[0], sizeof(send), spiFlashDmaRxTd[1], 0); + CyDmaTdSetAddress(spiFlashDmaRxTd[0], LO16((uint32)NOR_SPI_RXDATA_PTR), LO16((uint32)&discardBuffer)); + + CyDmaTdSetConfiguration( + spiFlashDmaRxTd[1], + count * 512, + CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes + TD_INC_DST_ADR | + NOR_RX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete + ); + + CyDmaTdSetAddress( + spiFlashDmaRxTd[1], + LO16((uint32)NOR_SPI_RXDATA_PTR), + LO16((uint32)buffer) + ); + + CyDmaChSetInitialTd(spiFlashDMATxChan, spiFlashDmaTxTd[0]); + CyDmaChSetInitialTd(spiFlashDMARxChan, spiFlashDmaRxTd[0]); + + // The DMA controller is a bit trigger-happy. It will retain + // a drq request that was triggered while the channel was + // disabled. + CyDmaChSetRequest(spiFlashDMATxChan, CY_DMA_CPU_REQ); + CyDmaClearPendingDrq(spiFlashDMARxChan); + + spiFlashTxDMAComplete = 0; + spiFlashRxDMAComplete = 0; + + CyDmaChEnable(spiFlashDMARxChan, 1); + CyDmaChEnable(spiFlashDMATxChan, 1); +} + +static int spiFlash_readAsyncPoll(S2S_Device* dev) +{ + // SpiFlash* spiFlash = (SpiFlash*)dev; + + int allComplete = 0; + uint8_t intr = CyEnterCriticalSection(); + allComplete = spiFlashTxDMAComplete && spiFlashRxDMAComplete; + CyExitCriticalSection(intr); + + if (allComplete) + { + nNOR_CS_Write(1); // Deselect + } + + return allComplete; +} \ No newline at end of file diff --git a/software/SCSI2SD/src/flash.h b/software/SCSI2SD/src/flash.h new file mode 100644 index 0000000..5daf3ba --- /dev/null +++ b/software/SCSI2SD/src/flash.h @@ -0,0 +1,25 @@ +// Copyright (C) 2020 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +#ifndef S2S_FLASH_H +#define S2S_FLASH_H + +#include "storedevice.h" + +extern S2S_Device* spiFlashDevice; + + +#endif diff --git a/software/SCSI2SD/src/geometry.c b/software/SCSI2SD/src/geometry.c index c3c6bb7..7d4d4e6 100755 --- a/software/SCSI2SD/src/geometry.c +++ b/software/SCSI2SD/src/geometry.c @@ -21,19 +21,22 @@ #include uint32_t getScsiCapacity( + S2S_Device* device, uint32_t sdSectorStart, uint16_t bytesPerSector, uint32_t scsiSectors) { + uint32_t devCapacity = device->getCapacity(device); + uint32_t capacity = - (sdDev.capacity - sdSectorStart) / + (devCapacity - sdSectorStart) / SDSectorsPerSCSISector(bytesPerSector); - if (sdDev.capacity == 0) + if (devCapacity == 0) { capacity = 0; } - else if (sdSectorStart >= sdDev.capacity) + else if (sdSectorStart >= devCapacity) { capacity = 0; } diff --git a/software/SCSI2SD/src/geometry.h b/software/SCSI2SD/src/geometry.h index 8df3d4c..26fda1a 100755 --- a/software/SCSI2SD/src/geometry.h +++ b/software/SCSI2SD/src/geometry.h @@ -20,8 +20,9 @@ #include "device.h" #include "config.h" +#include "storedevice.h" #include "sd.h" - + typedef enum { ADDRESS_BLOCK = 0, @@ -35,6 +36,7 @@ static inline int SDSectorsPerSCSISector(uint16_t bytesPerSector) } uint32_t getScsiCapacity( + S2S_Device* device, uint32_t sdSectorStart, uint16_t bytesPerSector, uint32_t scsiSectors); diff --git a/software/SCSI2SD/src/inquiry.c b/software/SCSI2SD/src/inquiry.c index 3b84c52..e1778a4 100755 --- a/software/SCSI2SD/src/inquiry.c +++ b/software/SCSI2SD/src/inquiry.c @@ -91,7 +91,7 @@ static const uint8 AscImpOperatingDefinition[] = 'S','C','S','I','-','2' }; -static void useCustomVPD(const TargetConfig* cfg, int pageCode) +static void useCustomVPD(const S2S_TargetCfg* cfg, int pageCode) { int cfgIdx = 0; int found = 0; @@ -116,8 +116,8 @@ static void useCustomVPD(const TargetConfig* cfg, int pageCode) { // error. scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB; scsiDev.phase = STATUS; } } @@ -141,13 +141,13 @@ void scsiInquiry() { // error. scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB; scsiDev.phase = STATUS; } else { - const TargetConfig* config = scsiDev.target->cfg; + const S2S_TargetCfg* config = scsiDev.target->cfg; memcpy(scsiDev.data, StandardResponse, sizeof(StandardResponse)); scsiDev.data[1] = scsiDev.target->cfg->deviceTypeModifier; @@ -180,7 +180,7 @@ void scsiInquiry() { memcpy(scsiDev.data, UnitSerialNumber, sizeof(UnitSerialNumber)); scsiDev.dataLen = sizeof(UnitSerialNumber); - const TargetConfig* config = scsiDev.target->cfg; + const S2S_TargetCfg* config = scsiDev.target->cfg; memcpy(&scsiDev.data[4], config->serial, sizeof(config->serial)); scsiDev.phase = DATA_IN; } @@ -206,8 +206,8 @@ void scsiInquiry() { // error. scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB; scsiDev.phase = STATUS; } diff --git a/software/SCSI2SD/src/main.c b/software/SCSI2SD/src/main.c index aa144bd..5e93e70 100755 --- a/software/SCSI2SD/src/main.c +++ b/software/SCSI2SD/src/main.c @@ -29,6 +29,7 @@ int main() { timeInit(); ledInit(); + s2s_deviceEarlyInit(); traceInit(); // Enable global interrupts. @@ -60,8 +61,7 @@ int main() ++delaySeconds; } - uint32_t lastSDPoll = getTime_ms(); - sdCheckPresent(); + s2s_deviceInit(); while (1) { @@ -74,10 +74,10 @@ int main() if (unlikely(scsiDev.phase == BUS_FREE)) { - if (unlikely(elapsedTime_ms(lastSDPoll) > 200)) + if (s2s_pollMediaChange()) { - lastSDPoll = getTime_ms(); - sdCheckPresent(); + scsiPhyConfig(); + scsiInit(); } else { @@ -94,10 +94,11 @@ int main() CyExitCriticalSection(interruptState); } } - else if ((scsiDev.phase >= 0) && (blockDev.state & DISK_PRESENT)) + else if ((scsiDev.phase >= 0) && + scsiDev.target && + (scsiDev.target->device->mediaState & MEDIA_PRESENT)) { - // don't waste time scanning SD cards while we're doing disk IO - lastSDPoll = getTime_ms(); + scsiDev.target->device->pollMediaBusy(scsiDev.target->device); } } return 0; diff --git a/software/SCSI2SD/src/mode.c b/software/SCSI2SD/src/mode.c index bb16cf7..0a5056d 100755 --- a/software/SCSI2SD/src/mode.c +++ b/software/SCSI2SD/src/mode.c @@ -241,7 +241,7 @@ static void pageIn(int pc, int dataIdx, const uint8* pageData, int pageLen) } } -static int useCustomPages(const TargetConfig* cfg, int pc, int pageCode, int* idx) +static int useCustomPages(const S2S_TargetCfg* cfg, int pc, int pageCode, int* idx) { int found = 0; int cfgIdx = 0; @@ -269,7 +269,12 @@ static int useCustomPages(const TargetConfig* cfg, int pc, int pageCode, int* id } static void doModeSense( - int sixByteCmd, int dbd, int pc, int pageCode, int allocLength) + S2S_Device* dev, + int sixByteCmd, + int dbd, + int pc, + int pageCode, + int allocLength) { ////////////// Mode Parameter Header //////////////////////////////////// @@ -288,14 +293,14 @@ static void doModeSense( mediumType = 0; // We should support various floppy types here! // Contains cache bits (0) and a Write-Protect bit. deviceSpecificParam = - (blockDev.state & DISK_WP) ? 0x80 : 0; + (dev->mediaState & MEDIA_WP) ? 0x80 : 0; density = 0; // reserved for direct access break; case CONFIG_FLOPPY_14MB: mediumType = 0x1E; // 90mm/3.5" deviceSpecificParam = - (blockDev.state & DISK_WP) ? 0x80 : 0; + (dev->mediaState & MEDIA_WP) ? 0x80 : 0; density = 0; // reserved for direct access break; @@ -308,14 +313,14 @@ static void doModeSense( case CONFIG_SEQUENTIAL: mediumType = 0; // reserved deviceSpecificParam = - (blockDev.state & DISK_WP) ? 0x80 : 0; - density = 0x13; // DAT Data Storage, X3B5/88-185A + (dev->mediaState & MEDIA_WP) ? 0x80 : 0; + density = 0x13; // DAT Data Storage, X3B5/88-185A break; case CONFIG_MO: - mediumType = 0x03; // Optical reversible or erasable medium + mediumType = 0x03; // Optical reversible or erasable medium deviceSpecificParam = - (blockDev.state & DISK_WP) ? 0x80 : 0; + (dev->mediaState & MEDIA_WP) ? 0x80 : 0; density = 0x00; // Default break; @@ -368,7 +373,7 @@ static void doModeSense( scsiDev.data[idx++] = 0; // reserved // Block length - uint32_t bytesPerSector = scsiDev.target->liveCfg.bytesPerSector; + uint32_t bytesPerSector = scsiDev.target->state.bytesPerSector; scsiDev.data[idx++] = bytesPerSector >> 16; scsiDev.data[idx++] = bytesPerSector >> 8; scsiDev.data[idx++] = bytesPerSector & 0xFF; @@ -423,7 +428,7 @@ static void doModeSense( scsiDev.data[idx+11] = sectorsPerTrack & 0xFF; // Fill out the configured bytes-per-sector - uint32_t bytesPerSector = scsiDev.target->liveCfg.bytesPerSector; + uint32_t bytesPerSector = scsiDev.target->state.bytesPerSector; scsiDev.data[idx+12] = bytesPerSector >> 8; scsiDev.data[idx+13] = bytesPerSector & 0xFF; } @@ -457,8 +462,9 @@ static void doModeSense( uint32 sector; LBA2CHS( getScsiCapacity( + scsiDev.target->device, scsiDev.target->cfg->sdSectorStart, - scsiDev.target->liveCfg.bytesPerSector, + scsiDev.target->state.bytesPerSector, scsiDev.target->cfg->scsiSectors), &cyl, &head, @@ -557,8 +563,8 @@ static void doModeSense( // Unknown Page Code pageFound = 0; scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB; scsiDev.phase = STATUS; } else @@ -617,10 +623,10 @@ static void doModeSelect(void) } else { - scsiDev.target->liveCfg.bytesPerSector = bytesPerSector; + scsiDev.target->state.bytesPerSector = bytesPerSector; if (bytesPerSector != scsiDev.target->cfg->bytesPerSector) { - configSave(scsiDev.target->targetId, bytesPerSector); + configSave(scsiDev.target->cfg->scsiId & CONFIG_TARGET_ID_BITS, bytesPerSector); } } } @@ -650,10 +656,10 @@ static void doModeSelect(void) goto bad; } - scsiDev.target->liveCfg.bytesPerSector = bytesPerSector; + scsiDev.target->state.bytesPerSector = bytesPerSector; if (scsiDev.cdb[1] & 1) // SP Save Pages flag { - configSave(scsiDev.target->targetId, bytesPerSector); + configSave(scsiDev.target->cfg->scsiId & CONFIG_TARGET_ID_BITS, bytesPerSector); } } break; @@ -669,14 +675,14 @@ static void doModeSelect(void) goto out; bad: scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_FIELD_IN_PARAMETER_LIST; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = INVALID_FIELD_IN_PARAMETER_LIST; out: scsiDev.phase = STATUS; } -int scsiModeCommand() +int scsiModeCommand(S2S_Device* dev) { int commandHandled = 1; @@ -696,7 +702,7 @@ int scsiModeCommand() // SCSI1 standard: (CCS X3T9.2/86-52) // "An Allocation Length of zero indicates that no MODE SENSE data shall // be transferred. This condition shall not be considered as an error." - doModeSense(1, dbd, pc, pageCode, allocLength); + doModeSense(dev, 1, dbd, pc, pageCode, allocLength); } else if (command == 0x5A) { @@ -707,7 +713,7 @@ int scsiModeCommand() int allocLength = (((uint16) scsiDev.cdb[7]) << 8) + scsiDev.cdb[8]; - doModeSense(0, dbd, pc, pageCode, allocLength); + doModeSense(dev, 0, dbd, pc, pageCode, allocLength); } else if (command == 0x15) { diff --git a/software/SCSI2SD/src/mode.h b/software/SCSI2SD/src/mode.h index 819b1f5..887e91a 100755 --- a/software/SCSI2SD/src/mode.h +++ b/software/SCSI2SD/src/mode.h @@ -17,6 +17,6 @@ #ifndef MODE_H #define MODE_H -int scsiModeCommand(void); +int scsiModeCommand(S2S_Device* dev); #endif diff --git a/software/SCSI2SD/src/scsi.c b/software/SCSI2SD/src/scsi.c index dc39968..b25bf13 100755 --- a/software/SCSI2SD/src/scsi.c +++ b/software/SCSI2SD/src/scsi.c @@ -132,8 +132,8 @@ static void enter_Status(uint8 status) scsiDev.phase = STATUS; scsiDev.lastStatus = scsiDev.status; - scsiDev.lastSense = scsiDev.target->sense.code; - scsiDev.lastSenseASC = scsiDev.target->sense.asc; + scsiDev.lastSense = scsiDev.target->state.sense.code; + scsiDev.lastSenseASC = scsiDev.target->state.sense.asc; } void process_Status() @@ -192,7 +192,7 @@ void process_Status() } else if (scsiDev.target->cfg->quirks == CONFIG_QUIRKS_OMTI) { - scsiDev.status |= (scsiDev.target->targetId & 0x03) << 5; + scsiDev.status |= (scsiDev.target->cfg->scsiId & 0x03) << 5; scsiWriteByte(scsiDev.status); } else @@ -201,8 +201,8 @@ void process_Status() } scsiDev.lastStatus = scsiDev.status; - scsiDev.lastSense = scsiDev.target->sense.code; - scsiDev.lastSenseASC = scsiDev.target->sense.asc; + scsiDev.lastSense = scsiDev.target->state.sense.code; + scsiDev.lastSenseASC = scsiDev.target->state.sense.asc; // Command Complete occurs AFTER a valid status has been @@ -262,8 +262,8 @@ static void process_DataOut() (scsiDev.boardCfg.flags & CONFIG_ENABLE_PARITY) && (scsiDev.compatMode >= COMPAT_SCSI2)) { - scsiDev.target->sense.code = ABORTED_COMMAND; - scsiDev.target->sense.asc = SCSI_PARITY_ERROR; + scsiDev.target->state.sense.code = ABORTED_COMMAND; + scsiDev.target->state.sense.asc = SCSI_PARITY_ERROR; enter_Status(CHECK_CONDITION); } } @@ -318,15 +318,11 @@ static void process_Command() // http://bitsavers.trailing-edge.com/pdf/xebec/104524C_S1410Man_Aug83.pdf if ((scsiDev.lun > 0) && (scsiDev.boardCfg.flags & CONFIG_MAP_LUNS_TO_IDS)) { - int tgtIndex; - for (tgtIndex = 0; tgtIndex < MAX_SCSI_TARGETS; ++tgtIndex) + S2S_Target* lunTarget = s2s_DeviceFindByScsiId(scsiDev.lun); + if (lunTarget != NULL) { - if (scsiDev.targets[tgtIndex].targetId == scsiDev.lun) - { - scsiDev.target = &scsiDev.targets[tgtIndex]; - scsiDev.lun = 0; - break; - } + scsiDev.target = lunTarget; + scsiDev.lun = 0; } } @@ -334,7 +330,7 @@ static void process_Command() control = scsiDev.cdb[scsiDev.cdbLen - 1]; scsiDev.cmdCount++; - const TargetConfig* cfg = scsiDev.target->cfg; + const S2S_TargetCfg* cfg = scsiDev.target->cfg; if (unlikely(scsiDev.resetFlag)) { @@ -347,8 +343,8 @@ static void process_Command() (scsiDev.boardCfg.flags & CONFIG_ENABLE_PARITY) && (scsiDev.compatMode >= COMPAT_SCSI2)) { - scsiDev.target->sense.code = ABORTED_COMMAND; - scsiDev.target->sense.asc = SCSI_PARITY_ERROR; + scsiDev.target->state.sense.code = ABORTED_COMMAND; + scsiDev.target->state.sense.asc = SCSI_PARITY_ERROR; enter_Status(CHECK_CONDITION); } else if ((control & 0x02) && ((control & 0x01) == 0) && @@ -356,8 +352,8 @@ static void process_Command() likely(scsiDev.target->cfg->quirks != CONFIG_QUIRKS_XEBEC)) { // FLAG set without LINK flag. - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB; enter_Status(CHECK_CONDITION); } else if (command == 0x12) @@ -373,11 +369,11 @@ static void process_Command() { // Completely non-standard allocLength = 4; - if (scsiDev.target->sense.code == NO_SENSE) + if (scsiDev.target->state.sense.code == NO_SENSE) scsiDev.data[0] = 0; - else if (scsiDev.target->sense.code == ILLEGAL_REQUEST) + else if (scsiDev.target->state.sense.code == ILLEGAL_REQUEST) scsiDev.data[0] = 0x20; // Illegal command - else if (scsiDev.target->sense.code == NOT_READY) + else if (scsiDev.target->state.sense.code == NOT_READY) scsiDev.data[0] = 0x04; // Drive not ready else scsiDev.data[0] = 0x11; // Uncorrectable data error @@ -395,7 +391,7 @@ static void process_Command() memset(scsiDev.data, 0, 256); // Max possible alloc length scsiDev.data[0] = 0xF0; - scsiDev.data[2] = scsiDev.target->sense.code & 0x0F; + scsiDev.data[2] = scsiDev.target->state.sense.code & 0x0F; scsiDev.data[3] = transfer.lba >> 24; scsiDev.data[4] = transfer.lba >> 16; @@ -404,45 +400,45 @@ static void process_Command() // Additional bytes if there are errors to report scsiDev.data[7] = 10; // additional length - scsiDev.data[12] = scsiDev.target->sense.asc >> 8; - scsiDev.data[13] = scsiDev.target->sense.asc; + scsiDev.data[12] = scsiDev.target->state.sense.asc >> 8; + scsiDev.data[13] = scsiDev.target->state.sense.asc; } // Silently truncate results. SCSI-2 spec 8.2.14. enter_DataIn(allocLength); // This is a good time to clear out old sense information. - scsiDev.target->sense.code = NO_SENSE; - scsiDev.target->sense.asc = NO_ADDITIONAL_SENSE_INFORMATION; + scsiDev.target->state.sense.code = NO_SENSE; + scsiDev.target->state.sense.asc = NO_ADDITIONAL_SENSE_INFORMATION; } // Some old SCSI drivers do NOT properly support // unitAttention. eg. the Mac Plus would trigger a SCSI reset // on receiving the unit attention response on boot, thus // triggering another unit attention condition. - else if (scsiDev.target->unitAttention && + else if (scsiDev.target->state.unitAttention && (scsiDev.boardCfg.flags & CONFIG_ENABLE_UNIT_ATTENTION)) { - scsiDev.target->sense.code = UNIT_ATTENTION; - scsiDev.target->sense.asc = scsiDev.target->unitAttention; + scsiDev.target->state.sense.code = UNIT_ATTENTION; + scsiDev.target->state.sense.asc = scsiDev.target->state.unitAttention; // If initiator doesn't do REQUEST SENSE for the next command, then // data is lost. - scsiDev.target->unitAttention = 0; + scsiDev.target->state.unitAttention = 0; enter_Status(CHECK_CONDITION); } else if (scsiDev.lun) { - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = LOGICAL_UNIT_NOT_SUPPORTED; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = LOGICAL_UNIT_NOT_SUPPORTED; enter_Status(CHECK_CONDITION); } else if (command == 0x17 || command == 0x16) { doReserveRelease(); } - else if ((scsiDev.target->reservedId >= 0) && - (scsiDev.target->reservedId != scsiDev.initiatorId)) + else if ((scsiDev.target->state.reservedId >= 0) && + (scsiDev.target->state.reservedId != scsiDev.initiatorId)) { enter_Status(CONFLICT); } @@ -481,10 +477,10 @@ static void process_Command() { scsiReadBuffer(); } - else if (!scsiModeCommand() && !scsiVendorCommand()) + else if (!scsiModeCommand(scsiDev.target->device) && !scsiVendorCommand()) { - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_COMMAND_OPERATION_CODE; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = INVALID_COMMAND_OPERATION_CODE; enter_Status(CHECK_CONDITION); } @@ -504,25 +500,25 @@ static void doReserveRelease() uint8 command = scsiDev.cdb[0]; int canRelease = - (!thirdPty && (scsiDev.initiatorId == scsiDev.target->reservedId)) || + (!thirdPty && (scsiDev.initiatorId == scsiDev.target->state.reservedId)) || (thirdPty && - (scsiDev.target->reserverId == scsiDev.initiatorId) && - (scsiDev.target->reservedId == thirdPtyId) + (scsiDev.target->state.reserverId == scsiDev.initiatorId) && + (scsiDev.target->state.reservedId == thirdPtyId) ); if (extentReservation) { // Not supported. - scsiDev.target->sense.code = ILLEGAL_REQUEST; - scsiDev.target->sense.asc = INVALID_FIELD_IN_CDB; + scsiDev.target->state.sense.code = ILLEGAL_REQUEST; + scsiDev.target->state.sense.asc = INVALID_FIELD_IN_CDB; enter_Status(CHECK_CONDITION); } else if (command == 0x17) // release { - if ((scsiDev.target->reservedId < 0) || canRelease) + if ((scsiDev.target->state.reservedId < 0) || canRelease) { - scsiDev.target->reservedId = -1; - scsiDev.target->reserverId = -1; + scsiDev.target->state.reservedId = -1; + scsiDev.target->state.reserverId = -1; } else { @@ -531,16 +527,16 @@ static void doReserveRelease() } else // assume reserve. { - if ((scsiDev.target->reservedId < 0) || canRelease) + if ((scsiDev.target->state.reservedId < 0) || canRelease) { - scsiDev.target->reserverId = scsiDev.initiatorId; + scsiDev.target->state.reserverId = scsiDev.initiatorId; if (thirdPty) { - scsiDev.target->reservedId = thirdPtyId; + scsiDev.target->state.reservedId = thirdPtyId; } else { - scsiDev.target->reservedId = scsiDev.initiatorId; + scsiDev.target->state.reservedId = scsiDev.initiatorId; } } else @@ -569,14 +565,14 @@ static void scsiReset() if (scsiDev.target) { - if (scsiDev.target->unitAttention != POWER_ON_RESET) + if (scsiDev.target->state.unitAttention != POWER_ON_RESET) { - scsiDev.target->unitAttention = SCSI_BUS_RESET; + scsiDev.target->state.unitAttention = SCSI_BUS_RESET; } - scsiDev.target->reservedId = -1; - scsiDev.target->reserverId = -1; - scsiDev.target->sense.code = NO_SENSE; - scsiDev.target->sense.asc = NO_ADDITIONAL_SENSE_INFORMATION; + scsiDev.target->state.reservedId = -1; + scsiDev.target->state.reserverId = -1; + scsiDev.target->state.sense.code = NO_SENSE; + scsiDev.target->state.sense.asc = NO_ADDITIONAL_SENSE_INFORMATION; } scsiDev.target = NULL; scsiDiskReset(); @@ -666,16 +662,19 @@ static void process_SelectionPhase() int goodParity = (Lookup_OddParity[mask] == SCSI_ReadPin(SCSI_In_DBP)); int atnFlag = SCSI_ReadFilt(SCSI_Filt_ATN); - int tgtIndex; - TargetState* target = NULL; - for (tgtIndex = 0; tgtIndex < MAX_SCSI_TARGETS; ++tgtIndex) + S2S_Target* target = NULL; + for (int testIdx = 0; testIdx < 8; ++testIdx) { - if (mask & (1 << scsiDev.targets[tgtIndex].targetId)) - { - target = &scsiDev.targets[tgtIndex]; - break; - } + if (mask & (1 << testIdx)) + { + target = s2s_DeviceFindByScsiId(testIdx); + if (target) + { + break; + } + } } + sel &= (selLatchCfg && scsiDev.selFlag) || SCSI_ReadFilt(SCSI_Filt_SEL); bsy |= SCSI_ReadFilt(SCSI_Filt_BSY); #ifdef SCSI_In_IO @@ -709,7 +708,7 @@ static void process_SelectionPhase() // controllers don't generate parity bits. if (!scsiDev.atnFlag) { - target->unitAttention = 0; + target->state.unitAttention = 0; scsiDev.compatMode = COMPAT_SCSI1; } else if (!(scsiDev.boardCfg.flags & CONFIG_ENABLE_SCSI2)) @@ -729,7 +728,7 @@ static void process_SelectionPhase() // SCSI1/SASI initiators may not set their own ID. { int i; - uint8_t initiatorMask = mask ^ (1 << target->targetId); + uint8_t initiatorMask = mask ^ (1 << (target->cfg->scsiId & CONFIG_TARGET_ID_BITS)); scsiDev.initiatorId = -1; for (i = 0; i < 8; ++i) { @@ -816,11 +815,11 @@ static void process_MessageOut() scsiDiskReset(); - scsiDev.target->unitAttention = SCSI_BUS_RESET; + scsiDev.target->state.unitAttention = SCSI_BUS_RESET; // ANY initiator can reset the reservation state via this message. - scsiDev.target->reservedId = -1; - scsiDev.target->reserverId = -1; + scsiDev.target->state.reservedId = -1; + scsiDev.target->state.reserverId = -1; enter_BusFree(); } else if (scsiDev.msgOut == 0x05) @@ -1055,27 +1054,28 @@ void scsiInit() scsiDev.target = NULL; scsiDev.compatMode = COMPAT_UNKNOWN; - int i; - for (i = 0; i < MAX_SCSI_TARGETS; ++i) + int deviceCount; + S2S_Device** allDevices = s2s_GetDevices(&deviceCount); + for (int devIdx = 0; devIdx < deviceCount; ++devIdx) { - const TargetConfig* cfg = getConfigByIndex(i); - if (cfg && (cfg->scsiId & CONFIG_TARGET_ENABLED)) - { - scsiDev.targets[i].targetId = cfg->scsiId & CONFIG_TARGET_ID_BITS; - scsiDev.targets[i].cfg = cfg; + int targetCount; + S2S_Target* targets = allDevices[devIdx]->getTargets(allDevices[devIdx], &targetCount); - scsiDev.targets[i].liveCfg.bytesPerSector = cfg->bytesPerSector; - } - else + for (int i = 0; i < targetCount; ++i) { - scsiDev.targets[i].targetId = 0xff; - scsiDev.targets[i].cfg = NULL; + S2S_TargetState* state = &(targets[i].state); + + state->reservedId = -1; + state->reserverId = -1; + state->unitAttention = POWER_ON_RESET; + state->sense.code = NO_SENSE; + state->sense.asc = NO_ADDITIONAL_SENSE_INFORMATION; + + if (targets[i].cfg) + { + state->bytesPerSector = targets[i].cfg->bytesPerSector; + } } - scsiDev.targets[i].reservedId = -1; - scsiDev.targets[i].reserverId = -1; - scsiDev.targets[i].unitAttention = POWER_ON_RESET; - scsiDev.targets[i].sense.code = NO_SENSE; - scsiDev.targets[i].sense.asc = NO_ADDITIONAL_SENSE_INFORMATION; } } @@ -1111,7 +1111,7 @@ int scsiReconnect() { // Arbitrate. ledOn(); - uint8_t scsiIdMask = 1 << scsiDev.target->targetId; + uint8_t scsiIdMask = 1 << (scsiDev.target->cfg->scsiId & CONFIG_TARGET_ID_BITS); SCSI_Out_Bits_Write(scsiIdMask); SCSI_Out_Ctl_Write(1); // Write bits manually. SCSI_SetPin(SCSI_Out_BSY); diff --git a/software/SCSI2SD/src/scsi.h b/software/SCSI2SD/src/scsi.h index d1a9f54..f353e58 100755 --- a/software/SCSI2SD/src/scsi.h +++ b/software/SCSI2SD/src/scsi.h @@ -17,8 +17,8 @@ #ifndef SCSI_H #define SCSI_H +#include "storedevice.h" #include "geometry.h" -#include "sense.h" typedef enum { @@ -73,37 +73,10 @@ typedef enum #define MAX_SECTOR_SIZE 8192 #define MIN_SECTOR_SIZE 64 -// Shadow parameters, possibly not saved to flash yet. -// Set via Mode Select typedef struct { - uint16_t bytesPerSector; -} LiveCfg; - -typedef struct -{ - uint8_t targetId; - - const TargetConfig* cfg; - - LiveCfg liveCfg; - - ScsiSense sense; - - uint16 unitAttention; // Set to the sense qualifier key to be returned. - - // Only let the reserved initiator talk to us. - // A 3rd party may be sending the RESERVE/RELEASE commands - int reservedId; // 0 -> 7 if reserved. -1 if not reserved. - int reserverId; // 0 -> 7 if reserved. -1 if not reserved. -} TargetState; - -typedef struct -{ - TargetState targets[MAX_SCSI_TARGETS]; - TargetState* target; - BoardConfig boardCfg; - + S2S_Target* target; + S2S_BoardConfig boardCfg; // Set to true (1) if the ATN flag was set, and we need to // enter the MESSAGE_OUT phase. diff --git a/software/SCSI2SD/src/sd.c b/software/SCSI2SD/src/sd.c index 6cd9029..536318a 100755 --- a/software/SCSI2SD/src/sd.c +++ b/software/SCSI2SD/src/sd.c @@ -28,8 +28,38 @@ #include +static void sd_earlyInit(S2S_Device* dev); +static void sd_deviceInit(S2S_Device* dev); +static S2S_Target* sd_getTargets(S2S_Device* dev, int* count); +static uint32_t sd_getCapacity(S2S_Device* dev); +static int sd_pollMediaChange(S2S_Device* dev); +static void sd_pollMediaBusy(S2S_Device* dev); +static void sd_erase(S2S_Device* dev, uint32_t sectorNumber, uint32_t count); +static void sd_read(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); +static void sd_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); +static int sd_readAsyncPoll(S2S_Device* dev); +static void sd_write(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); + + // Global -SdDevice sdDev; +SdCard sdCard = { + { + sd_earlyInit, + sd_deviceInit, + sd_getTargets, + sd_getCapacity, + sd_pollMediaChange, + sd_pollMediaBusy, + sd_erase, + sd_read, + sd_readAsync, + sd_readAsyncPoll, + sd_write, + 0, // initial mediaState + CONFIG_STOREDEVICE_SD + } +}; +S2S_Device* sdDevice = &(sdCard.dev); enum SD_CMD_STATE { CMD_STATE_IDLE, CMD_STATE_READ, CMD_STATE_WRITE }; static int sdCmdState = CMD_STATE_IDLE; @@ -268,7 +298,7 @@ sdReadMultiSectorPrep(uint32_t sdLBA, uint32_t sdSectors) { uint32_t tmpNextLBA = sdLBA + sdSectors; - if (!sdDev.ccs) + if (!sdCard.ccs) { sdLBA = sdLBA * SD_SECTOR_SIZE; tmpNextLBA = tmpNextLBA * SD_SECTOR_SIZE; @@ -291,8 +321,8 @@ sdReadMultiSectorPrep(uint32_t sdLBA, uint32_t sdSectors) sdClearStatus(); scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = HARDWARE_ERROR; - scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; + scsiDev.target->state.sense.code = HARDWARE_ERROR; + scsiDev.target->state.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; scsiDev.phase = STATUS; } else @@ -330,8 +360,8 @@ dmaReadSector(uint8_t* outputBuffer) if (scsiDev.status != CHECK_CONDITION) { scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = HARDWARE_ERROR; - scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR; + scsiDev.target->state.sense.code = HARDWARE_ERROR; + scsiDev.target->state.sense.asc = UNRECOVERED_READ_ERROR; scsiDev.phase = STATUS; } sdClearStatus(); @@ -399,7 +429,7 @@ void sdReadSingleSectorDMA(uint32_t lba, uint8_t* outputBuffer) sdPreCmdState(CMD_STATE_READ); uint8 v; - if (!sdDev.ccs) + if (!sdCard.ccs) { lba = lba * SD_SECTOR_SIZE; } @@ -410,8 +440,8 @@ void sdReadSingleSectorDMA(uint32_t lba, uint8_t* outputBuffer) sdClearStatus(); scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = HARDWARE_ERROR; - scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; + scsiDev.target->state.sense.code = HARDWARE_ERROR; + scsiDev.target->state.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; scsiDev.phase = STATUS; } else @@ -446,8 +476,8 @@ static void sdCompleteRead() if (unlikely(r1b) && (scsiDev.phase == DATA_IN)) { scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = HARDWARE_ERROR; - scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR; + scsiDev.target->state.sense.code = HARDWARE_ERROR; + scsiDev.target->state.sense.asc = UNRECOVERED_READ_ERROR; scsiDev.phase = STATUS; } } @@ -544,8 +574,8 @@ sdWriteSectorDMAPoll() sdClearStatus(); scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = HARDWARE_ERROR; - scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; + scsiDev.target->state.sense.code = HARDWARE_ERROR; + scsiDev.target->state.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; scsiDev.phase = STATUS; } else @@ -599,8 +629,8 @@ static void sdCompleteWrite() { sdClearStatus(); scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = HARDWARE_ERROR; - scsiDev.target->sense.asc = WRITE_ERROR_AUTO_REALLOCATION_FAILED; + scsiDev.target->state.sense.code = HARDWARE_ERROR; + scsiDev.target->state.sense.asc = WRITE_ERROR_AUTO_REALLOCATION_FAILED; scsiDev.phase = STATUS; } } @@ -627,7 +657,7 @@ static int sendIfCond() if (status == SD_R1_IDLE) { // Version 2 card. - sdDev.version = 2; + sdCard.version = 2; // Read 32bit response. Should contain the same bytes that // we sent in the command parameter. sdSpiByte(0xFF); @@ -639,7 +669,7 @@ static int sendIfCond() else if (status & SD_R1_ILLEGAL) { // Version 1 card. - sdDev.version = 1; + sdCard.version = 1; sdClearStatus(); break; } @@ -688,7 +718,7 @@ static int sdReadOCR() buf[i] = sdSpiByte(0xFF); } - sdDev.ccs = (buf[0] & 0x40) ? 1 : 0; + sdCard.ccs = (buf[0] & 0x40) ? 1 : 0; complete = (buf[0] & 0x80); } while (!status && @@ -715,7 +745,7 @@ static void sdReadCID() for (i = 0; i < 16; ++i) { - sdDev.cid[i] = sdSpiByte(0xFF); + sdCard.cid[i] = sdSpiByte(0xFF); } sdSpiByte(0xFF); // CRC sdSpiByte(0xFF); // CRC @@ -738,30 +768,30 @@ static int sdReadCSD() for (i = 0; i < 16; ++i) { - sdDev.csd[i] = sdSpiByte(0xFF); + sdCard.csd[i] = sdSpiByte(0xFF); } sdSpiByte(0xFF); // CRC sdSpiByte(0xFF); // CRC - if ((sdDev.csd[0] >> 6) == 0x00) + if ((sdCard.csd[0] >> 6) == 0x00) { // CSD version 1 // C_SIZE in bits [73:62] - uint32 c_size = (((((uint32)sdDev.csd[6]) & 0x3) << 16) | (((uint32)sdDev.csd[7]) << 8) | sdDev.csd[8]) >> 6; - uint32 c_mult = (((((uint32)sdDev.csd[9]) & 0x3) << 8) | ((uint32)sdDev.csd[0xa])) >> 7; - uint32 sectorSize = sdDev.csd[5] & 0x0F; - sdDev.capacity = ((c_size+1) * ((uint64)1 << (c_mult+2)) * ((uint64)1 << sectorSize)) / SD_SECTOR_SIZE; + uint32 c_size = (((((uint32)sdCard.csd[6]) & 0x3) << 16) | (((uint32)sdCard.csd[7]) << 8) | sdCard.csd[8]) >> 6; + uint32 c_mult = (((((uint32)sdCard.csd[9]) & 0x3) << 8) | ((uint32)sdCard.csd[0xa])) >> 7; + uint32 sectorSize = sdCard.csd[5] & 0x0F; + sdCard.capacity = ((c_size+1) * ((uint64)1 << (c_mult+2)) * ((uint64)1 << sectorSize)) / SD_SECTOR_SIZE; } - else if ((sdDev.csd[0] >> 6) == 0x01) + else if ((sdCard.csd[0] >> 6) == 0x01) { // CSD version 2 // C_SIZE in bits [69:48] uint32 c_size = - ((((uint32)sdDev.csd[7]) & 0x3F) << 16) | - (((uint32)sdDev.csd[8]) << 8) | - ((uint32)sdDev.csd[7]); - sdDev.capacity = (c_size + 1) * 1024; + ((((uint32)sdCard.csd[7]) & 0x3F) << 16) | + (((uint32)sdCard.csd[8]) << 8) | + ((uint32)sdCard.csd[7]); + sdCard.capacity = (c_size + 1) * 1024; } else { @@ -809,11 +839,11 @@ int sdInit() uint8 v; sdCmdState = CMD_STATE_IDLE; - sdDev.version = 0; - sdDev.ccs = 0; - sdDev.capacity = 0; - memset(sdDev.csd, 0, sizeof(sdDev.csd)); - memset(sdDev.cid, 0, sizeof(sdDev.cid)); + sdCard.version = 0; + sdCard.ccs = 0; + sdCard.capacity = 0; + memset(sdCard.csd, 0, sizeof(sdCard.csd)); + memset(sdCard.cid, 0, sizeof(sdCard.cid)); sdInitDMA(); @@ -848,7 +878,7 @@ int sdInit() if (!sdOpCond()) goto bad; // ACMD41. Wait for init completes. if (!sdReadOCR()) goto bad; // CMD58. Get CCS flag. Only valid after init. - // This command will be ignored if sdDev.ccs is set. + // This command will be ignored if sdCard.ccs is set. // SDHC and SDXC are always 512bytes. v = sdCRCCommandAndResponse(SD_SET_BLOCKLEN, SD_SECTOR_SIZE); //Force sector size if(v){goto bad;} @@ -882,7 +912,7 @@ int sdInit() bad: SD_Data_Clk_SetDivider(clkDiv25MHz); // Restore the clock for our next retry - sdDev.capacity = 0; + sdCard.capacity = 0; out: sdClearStatus(); @@ -895,7 +925,7 @@ void sdWriteMultiSectorPrep(uint32_t sdLBA, uint32_t sdSectors) { uint32_t tmpNextLBA = sdLBA + sdSectors; - if (!sdDev.ccs) + if (!sdCard.ccs) { sdLBA = sdLBA * SD_SECTOR_SIZE; tmpNextLBA = tmpNextLBA * SD_SECTOR_SIZE; @@ -924,8 +954,8 @@ void sdWriteMultiSectorPrep(uint32_t sdLBA, uint32_t sdSectors) scsiDiskReset(); sdClearStatus(); scsiDev.status = CHECK_CONDITION; - scsiDev.target->sense.code = HARDWARE_ERROR; - scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; + scsiDev.target->state.sense.code = HARDWARE_ERROR; + scsiDev.target->state.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE; scsiDev.phase = STATUS; } else @@ -968,7 +998,7 @@ void sdCheckPresent() uint8_t cs = SD_CS_Read(); SD_CS_SetDriveMode(SD_CS_DM_STRONG) ; - if (cs && !(blockDev.state & DISK_PRESENT)) + if (cs && !(sdCard.dev.mediaState & MEDIA_PRESENT)) { static int firstInit = 1; @@ -981,38 +1011,127 @@ void sdCheckPresent() if (sdInit()) { - blockDev.state |= DISK_PRESENT | DISK_INITIALISED; + sdCard.dev.mediaState |= MEDIA_PRESENT | MEDIA_INITIALISED; // Always "start" the device. Many systems (eg. Apple System 7) // won't respond properly to // LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED sense // code, even if they stopped it first with // START STOP UNIT command. - blockDev.state |= DISK_STARTED; + sdCard.dev.mediaState |= MEDIA_STARTED; if (!firstInit) { int i; for (i = 0; i < MAX_SCSI_TARGETS; ++i) { - scsiDev.targets[i].unitAttention = PARAMETERS_CHANGED; + sdCard.targets[i].state.unitAttention = PARAMETERS_CHANGED; } } firstInit = 0; } } - else if (!cs && (blockDev.state & DISK_PRESENT)) + else if (!cs && (sdCard.dev.mediaState & MEDIA_PRESENT)) { - sdDev.capacity = 0; - blockDev.state &= ~DISK_PRESENT; - blockDev.state &= ~DISK_INITIALISED; + sdCard.capacity = 0; + sdCard.dev.mediaState &= ~MEDIA_PRESENT; + sdCard.dev.mediaState &= ~MEDIA_INITIALISED; int i; for (i = 0; i < MAX_SCSI_TARGETS; ++i) { - scsiDev.targets[i].unitAttention = PARAMETERS_CHANGED; + sdCard.targets[i].state.unitAttention = PARAMETERS_CHANGED; } } } firstCheck = 0; } +static void sd_earlyInit(S2S_Device* dev) +{ + SdCard* sdCardDevice = (SdCard*)dev; + + for (int i = 0; i < MAX_SCSI_TARGETS; ++i) + { + sdCardDevice->targets[i].device = dev; + + const S2S_TargetCfg* cfg = getConfigByIndex(i); + if (cfg->storageDevice == CONFIG_STOREDEVICE_SD) + { + sdCardDevice->targets[i].cfg = (S2S_TargetCfg*)cfg; + } + else + { + sdCardDevice->targets[i].cfg = NULL; + } + } + sdCardDevice->lastPollMediaTime = getTime_ms(); + + // Don't require the host to send us a START STOP UNIT command + sdCardDevice->dev.mediaState = MEDIA_STARTED; +} + +static void sd_deviceInit(S2S_Device* dev) +{ + sdCheckPresent(); +} + +static S2S_Target* sd_getTargets(S2S_Device* dev, int* count) +{ + SdCard* sdCardDevice = (SdCard*)dev; + *count = MAX_SCSI_TARGETS; + return sdCardDevice->targets; +} + +static uint32_t sd_getCapacity(S2S_Device* dev) +{ + SdCard* sdCardDevice = (SdCard*)dev; + return sdCardDevice->capacity; +} + +static int sd_pollMediaChange(S2S_Device* dev) +{ + SdCard* sdCardDevice = (SdCard*)dev; + if (elapsedTime_ms(sdCardDevice->lastPollMediaTime) > 200) + { + sdCardDevice->lastPollMediaTime = getTime_ms(); + sdCheckPresent(); + return 0; + } + else + { + return 0; + } +} + +static void sd_pollMediaBusy(S2S_Device* dev) +{ + SdCard* sdCardDevice = (SdCard*)dev; + sdCardDevice->lastPollMediaTime = getTime_ms(); +} + +static void sd_erase(S2S_Device* dev, uint32_t sectorNumber, uint32_t count) +{ + // TODO +} + +static void sd_read(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer) +{ + // TODO +} + +static void sd_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer) +{ + // TODO +} + + +static int sd_readAsyncPoll(S2S_Device* dev) +{ + return 1; +} + + +static void sd_write(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer) +{ + // TODO +} diff --git a/software/SCSI2SD/src/sd.h b/software/SCSI2SD/src/sd.h index 8ffcee7..602f938 100755 --- a/software/SCSI2SD/src/sd.h +++ b/software/SCSI2SD/src/sd.h @@ -17,6 +17,8 @@ #ifndef SD_H #define SD_H +#include "storedevice.h" + #define SD_SECTOR_SIZE 512 typedef enum @@ -52,15 +54,23 @@ typedef enum typedef struct { + S2S_Device dev; + + S2S_Target targets[MAX_SCSI_TARGETS]; + int version; // SDHC = version 2. int ccs; // Card Capacity Status. 1 = SDHC or SDXC - uint32 capacity; // in 512 byte blocks + uint32_t capacity; // in 512 byte blocks uint8_t csd[16]; // Unparsed CSD uint8_t cid[16]; // Unparsed CID -} SdDevice; -extern SdDevice sdDev; + uint32_t lastPollMediaTime; +} SdCard; + +extern SdCard sdCard; +extern S2S_Device* sdDevice; + extern volatile uint8_t sdRxDMAComplete; extern volatile uint8_t sdTxDMAComplete; diff --git a/software/SCSI2SD/src/sense.h b/software/SCSI2SD/src/sense.h index 7852868..e73631f 100755 --- a/software/SCSI2SD/src/sense.h +++ b/software/SCSI2SD/src/sense.h @@ -169,8 +169,8 @@ typedef enum typedef struct { - uint8 code; - uint16 asc; + uint8_t code; + uint16_t asc; } ScsiSense; #endif diff --git a/software/SCSI2SD/src/storedevice.c b/software/SCSI2SD/src/storedevice.c new file mode 100644 index 0000000..d00eb4e --- /dev/null +++ b/software/SCSI2SD/src/storedevice.c @@ -0,0 +1,100 @@ +// Copyright (C) 2020 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +#include "storedevice.h" + +#include "device.h" + +#ifdef NOR_SPI_DATA_WIDTH +#include "flash.h" +#endif + +#include "sd.h" + +#include +#include + +S2S_Target* s2s_DeviceFindByScsiId(int scsiId) +{ + int deviceCount; + S2S_Device** devices = s2s_GetDevices(&deviceCount); + for (int deviceIdx = 0; deviceIdx < deviceCount; ++deviceIdx) + { + int targetCount; + S2S_Target* targets = devices[deviceIdx]->getTargets(devices[deviceIdx], &targetCount); + for (int targetIdx = 0; targetIdx < targetCount; ++targetIdx) + { + S2S_Target* target = targets + targetIdx; + if (target && + target->cfg && + (target->cfg->scsiId & CONFIG_TARGET_ENABLED) && + ((target->cfg->scsiId & CONFIG_TARGET_ID_BITS) == scsiId)) + { + return target; + } + } + } + + return NULL; +} + +S2S_Device** s2s_GetDevices(int* count) +{ + static S2S_Device* allDevices[2]; + + *count = 1; + allDevices[0] = sdDevice; + + #ifdef NOR_SPI_DATA_WIDTH + *count = 2; + allDevices[1] = spiFlashDevice; + #endif + + return allDevices; +} + +void s2s_deviceEarlyInit() +{ + int count; + S2S_Device** devices = s2s_GetDevices(&count); + for (int i = 0; i < count; ++i) + { + devices[i]->earlyInit(devices[i]); + } +} + +void s2s_deviceInit() +{ + int count; + S2S_Device** devices = s2s_GetDevices(&count); + for (int i = 0; i < count; ++i) + { + devices[i]->init(devices[i]); + } +} + +int s2s_pollMediaChange() +{ + int result = 0; + int count; + S2S_Device** devices = s2s_GetDevices(&count); + for (int i = 0; i < count; ++i) + { + int devResult = devices[i]->pollMediaChange(devices[i]); + result = result || devResult; + } + return result; +} diff --git a/software/SCSI2SD/src/storedevice.h b/software/SCSI2SD/src/storedevice.h new file mode 100644 index 0000000..e66c640 --- /dev/null +++ b/software/SCSI2SD/src/storedevice.h @@ -0,0 +1,98 @@ +// Copyright (C) 2020 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +#ifndef S2S_DEVICE_H +#define S2S_DEVICE_H + +#include "scsi2sd.h" +#include "sense.h" + +#include + +struct S2S_DeviceStruct; +typedef struct S2S_DeviceStruct S2S_Device; + +struct S2S_TargetStruct; +typedef struct S2S_TargetStruct S2S_Target; + +struct S2S_TargetStateStruct; +typedef struct S2S_TargetStateStruct S2S_TargetState; + +typedef enum +{ + MEDIA_STARTED = 1, // Controlled via START STOP UNIT + MEDIA_PRESENT = 2, // SD card is physically present + MEDIA_INITIALISED = 4, // SD card responded to init sequence + MEDIA_WP = 8 // Write-protect. +} MEDIA_STATE; + +struct S2S_TargetStateStruct +{ + ScsiSense sense; + + uint16_t unitAttention; // Set to the sense qualifier key to be returned. + + // Only let the reserved initiator talk to us. + // A 3rd party may be sending the RESERVE/RELEASE commands + int reservedId; // 0 -> 7 if reserved. -1 if not reserved. + int reserverId; // 0 -> 7 if reserved. -1 if not reserved. + + // Shadow parameters, possibly not saved to flash yet. + // Set via Mode Select + uint16_t bytesPerSector; +}; + +struct S2S_TargetStruct +{ + S2S_Device* device; + S2S_TargetCfg* cfg; + + S2S_TargetState state; +}; + +struct S2S_DeviceStruct +{ + void (*earlyInit)(S2S_Device* dev); + void (*init)(S2S_Device* dev); + + S2S_Target* (*getTargets)(S2S_Device* dev, int* count); + + // Get the number of 512 byte blocks + uint32_t (*getCapacity)(S2S_Device* dev); + + int (*pollMediaChange)(S2S_Device* dev); + void (*pollMediaBusy)(S2S_Device* dev); + + void (*erase)(S2S_Device* dev, uint32_t sectorNumber, uint32_t count); + void (*read)(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); + void (*readAsync)(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); + int (*readAsyncPoll)(S2S_Device* dev); + void (*write)(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer); + + MEDIA_STATE mediaState; + CONFIG_STOREDEVICE deviceType; +}; + +S2S_Target* s2s_DeviceFindByScsiId(int scsiId); + +S2S_Device** s2s_GetDevices(int* count); + +void s2s_deviceEarlyInit(); +void s2s_deviceInit(); +int s2s_pollMediaChange(); +#endif + + diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI.h index c0f90bd..53893b9 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI.h +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI.h @@ -135,7 +135,7 @@ extern uint8 NOR_SPI_initVar; ***************************************/ #define NOR_SPI_INT_ON_SPI_DONE ((uint8) (0u << NOR_SPI_STS_SPI_DONE_SHIFT)) -#define NOR_SPI_INT_ON_TX_EMPTY ((uint8) (0u << NOR_SPI_STS_TX_FIFO_EMPTY_SHIFT)) +#define NOR_SPI_INT_ON_TX_EMPTY ((uint8) (1u << NOR_SPI_STS_TX_FIFO_EMPTY_SHIFT)) #define NOR_SPI_INT_ON_TX_NOT_FULL ((uint8) (0u << \ NOR_SPI_STS_TX_FIFO_NOT_FULL_SHIFT)) #define NOR_SPI_INT_ON_BYTE_COMP ((uint8) (0u << NOR_SPI_STS_BYTE_COMPLETE_SHIFT)) @@ -154,7 +154,7 @@ extern uint8 NOR_SPI_initVar; #define NOR_SPI_INT_ON_RX_FULL ((uint8) (0u << \ NOR_SPI_STS_RX_FIFO_FULL_SHIFT)) -#define NOR_SPI_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \ +#define NOR_SPI_INT_ON_RX_NOT_EMPTY ((uint8) (1u << \ NOR_SPI_STS_RX_FIFO_NOT_EMPTY_SHIFT)) #define NOR_SPI_INT_ON_RX_OVER ((uint8) (0u << \ NOR_SPI_STS_RX_FIFO_OVERRUN_SHIFT)) diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h index 59d3e2c..e7a420e 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevice.h * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h index b05fd82..e45bc3e 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevice_trm.h * -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc index 754b960..1346980 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevicegnu.inc * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc index e2e2aa7..7877dc7 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevicegnu_trm.inc * -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc index 147a861..d8f2a6e 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc @@ -1,13 +1,13 @@ ; ; File Name: cydeviceiar.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 4.2 +; PSoC Creator 4.4 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc index 30429cd..067042d 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc @@ -1,13 +1,13 @@ ; ; File Name: cydeviceiar_trm.inc ; -; PSoC Creator 4.2 +; PSoC Creator 4.4 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc index cff336b..fdafe7a 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc @@ -1,13 +1,13 @@ ; ; File Name: cydevicerv.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 4.2 +; PSoC Creator 4.4 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc index fc79212..c7a64f2 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc @@ -1,13 +1,13 @@ ; ; File Name: cydevicerv_trm.inc ; -; PSoC Creator 4.2 +; PSoC Creator 4.4 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index 6704c4a..c5ff31e 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cyfitter.h * -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -192,34 +192,34 @@ #define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 #define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_1__INTC_MASK 0x80u -#define USBFS_ep_1__INTC_NUMBER 7u +#define USBFS_ep_1__INTC_MASK 0x200u +#define USBFS_ep_1__INTC_NUMBER 9u #define USBFS_ep_1__INTC_PRIOR_NUM 7u -#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7 +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_9 #define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 #define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_2__INTC_MASK 0x100u -#define USBFS_ep_2__INTC_NUMBER 8u +#define USBFS_ep_2__INTC_MASK 0x400u +#define USBFS_ep_2__INTC_NUMBER 10u #define USBFS_ep_2__INTC_PRIOR_NUM 7u -#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8 +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_10 #define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 #define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_3__INTC_MASK 0x200u -#define USBFS_ep_3__INTC_NUMBER 9u +#define USBFS_ep_3__INTC_MASK 0x800u +#define USBFS_ep_3__INTC_NUMBER 11u #define USBFS_ep_3__INTC_PRIOR_NUM 7u -#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9 +#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_11 #define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 #define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define USBFS_ep_4__INTC_MASK 0x400u -#define USBFS_ep_4__INTC_NUMBER 10u +#define USBFS_ep_4__INTC_MASK 0x2000u +#define USBFS_ep_4__INTC_NUMBER 13u #define USBFS_ep_4__INTC_PRIOR_NUM 7u -#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10 +#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_13 #define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 #define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -424,32 +424,32 @@ #define NOR_SO__SLW CYREG_PRT15_SLW /* SDCard */ -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB04_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB04_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB04_ST #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u @@ -460,11 +460,7 @@ #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u #define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK -#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL #define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL -#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL #define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 @@ -483,12 +479,12 @@ #define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 #define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 #define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 +#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u #define SDCard_BSPIM_TxStsReg__2__POS 2 #define SDCard_BSPIM_TxStsReg__3__MASK 0x08u @@ -496,9 +492,9 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB06_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB06_ST +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB11_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB11_ST /* SD_SCK */ #define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE1 @@ -534,30 +530,6 @@ #define SD_SCK__SHIFT 1u #define SD_SCK__SLW CYREG_PRT3_SLW -/* NOR_CTL */ -#define NOR_CTL_Sync_ctrl_reg__0__MASK 0x01u -#define NOR_CTL_Sync_ctrl_reg__0__POS 0 -#define NOR_CTL_Sync_ctrl_reg__1__MASK 0x02u -#define NOR_CTL_Sync_ctrl_reg__1__POS 1 -#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL -#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL -#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL -#define NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL -#define NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL -#define NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK -#define NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK -#define NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK -#define NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK -#define NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL -#define NOR_CTL_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB06_CTL -#define NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL -#define NOR_CTL_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB06_CTL -#define NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL -#define NOR_CTL_Sync_ctrl_reg__MASK 0x03u -#define NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL -#define NOR_CTL_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB06_MSK - /* NOR_SCK */ #define NOR_SCK__0__INTTYPE CYREG_PICU3_INTTYPE7 #define NOR_SCK__0__MASK 0x80u @@ -593,34 +565,34 @@ #define NOR_SCK__SLW CYREG_PRT3_SLW /* NOR_SPI */ -#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL -#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK -#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK -#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK -#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK -#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL -#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB08_CTL -#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL -#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB08_CTL -#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL -#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB08_MSK -#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL -#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST -#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB08_MSK -#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL -#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL -#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL -#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL -#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB08_ST -#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL -#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST +#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK +#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK +#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL +#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL +#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL +#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL +#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK +#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST +#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK +#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST +#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST #define NOR_SPI_BSPIM_RxStsReg__4__MASK 0x10u #define NOR_SPI_BSPIM_RxStsReg__4__POS 4 #define NOR_SPI_BSPIM_RxStsReg__5__MASK 0x20u @@ -628,9 +600,9 @@ #define NOR_SPI_BSPIM_RxStsReg__6__MASK 0x40u #define NOR_SPI_BSPIM_RxStsReg__6__POS 6 #define NOR_SPI_BSPIM_RxStsReg__MASK 0x70u -#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK -#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL -#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST +#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK +#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST #define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0 #define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1 #define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0 @@ -648,6 +620,8 @@ #define NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1 #define NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB04_F0 #define NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB04_F1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL +#define NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL #define NOR_SPI_BSPIM_TxStsReg__0__MASK 0x01u #define NOR_SPI_BSPIM_TxStsReg__0__POS 0 #define NOR_SPI_BSPIM_TxStsReg__1__MASK 0x02u @@ -1784,15 +1758,15 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u @@ -1805,35 +1779,35 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB09_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB09_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB09_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB09_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu -#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB09_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB09_MSK #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG #define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX #define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE @@ -2293,42 +2267,42 @@ #define NOR_Clock__PM_STBY_MSK 0x01u /* SD_RX_DMA */ -#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SD_RX_DMA__DRQ_NUMBER 2u +#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL1 +#define SD_RX_DMA__DRQ_NUMBER 4u #define SD_RX_DMA__NUMBEROF_TDS 0u #define SD_RX_DMA__PRIORITY 0u #define SD_RX_DMA__TERMIN_EN 0u #define SD_RX_DMA__TERMIN_SEL 0u #define SD_RX_DMA__TERMOUT0_EN 1u -#define SD_RX_DMA__TERMOUT0_SEL 2u +#define SD_RX_DMA__TERMOUT0_SEL 4u #define SD_RX_DMA__TERMOUT1_EN 0u #define SD_RX_DMA__TERMOUT1_SEL 0u #define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u -#define SD_RX_DMA_COMPLETE__INTC_NUMBER 5u +#define SD_RX_DMA_COMPLETE__INTC_MASK 0x80u +#define SD_RX_DMA_COMPLETE__INTC_NUMBER 7u #define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5 +#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_7 #define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* SD_TX_DMA */ -#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SD_TX_DMA__DRQ_NUMBER 3u +#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL1 +#define SD_TX_DMA__DRQ_NUMBER 5u #define SD_TX_DMA__NUMBEROF_TDS 0u #define SD_TX_DMA__PRIORITY 1u #define SD_TX_DMA__TERMIN_EN 0u #define SD_TX_DMA__TERMIN_SEL 0u #define SD_TX_DMA__TERMOUT0_EN 1u -#define SD_TX_DMA__TERMOUT0_SEL 3u +#define SD_TX_DMA__TERMOUT0_SEL 5u #define SD_TX_DMA__TERMOUT1_EN 0u #define SD_TX_DMA__TERMOUT1_SEL 0u #define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u -#define SD_TX_DMA_COMPLETE__INTC_NUMBER 6u +#define SD_TX_DMA_COMPLETE__INTC_MASK 0x100u +#define SD_TX_DMA_COMPLETE__INTC_NUMBER 8u #define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6 +#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_8 #define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 @@ -2365,6 +2339,46 @@ #define nNOR_HOLD__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ #define nNOR_HOLD__SLW CYREG_PRT12_SLW +/* NOR_RX_DMA */ +#define NOR_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define NOR_RX_DMA__DRQ_NUMBER 0u +#define NOR_RX_DMA__NUMBEROF_TDS 0u +#define NOR_RX_DMA__PRIORITY 2u +#define NOR_RX_DMA__TERMIN_EN 0u +#define NOR_RX_DMA__TERMIN_SEL 0u +#define NOR_RX_DMA__TERMOUT0_EN 1u +#define NOR_RX_DMA__TERMOUT0_SEL 0u +#define NOR_RX_DMA__TERMOUT1_EN 0u +#define NOR_RX_DMA__TERMOUT1_SEL 0u +#define NOR_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define NOR_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define NOR_RX_DMA_COMPLETE__INTC_MASK 0x02u +#define NOR_RX_DMA_COMPLETE__INTC_NUMBER 1u +#define NOR_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define NOR_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define NOR_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define NOR_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* NOR_TX_DMA */ +#define NOR_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define NOR_TX_DMA__DRQ_NUMBER 1u +#define NOR_TX_DMA__NUMBEROF_TDS 0u +#define NOR_TX_DMA__PRIORITY 2u +#define NOR_TX_DMA__TERMIN_EN 0u +#define NOR_TX_DMA__TERMIN_SEL 0u +#define NOR_TX_DMA__TERMOUT0_EN 1u +#define NOR_TX_DMA__TERMOUT0_SEL 1u +#define NOR_TX_DMA__TERMOUT1_EN 0u +#define NOR_TX_DMA__TERMOUT1_SEL 0u +#define NOR_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define NOR_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define NOR_TX_DMA_COMPLETE__INTC_MASK 0x04u +#define NOR_TX_DMA_COMPLETE__INTC_NUMBER 2u +#define NOR_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define NOR_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2 +#define NOR_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define NOR_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + /* SCSI_Noise */ #define SCSI_Noise__0__AG CYREG_PRT4_AG #define SCSI_Noise__0__AMUX CYREG_PRT4_AMUX @@ -2697,8 +2711,8 @@ #define scsiTarget_StatusReg__0__POS 0 #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 -#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST #define scsiTarget_StatusReg__2__MASK 0x04u #define scsiTarget_StatusReg__2__POS 2 #define scsiTarget_StatusReg__3__MASK 0x08u @@ -2706,13 +2720,13 @@ #define scsiTarget_StatusReg__4__MASK 0x10u #define scsiTarget_StatusReg__4__POS 4 #define scsiTarget_StatusReg__MASK 0x1Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK -#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL -#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK +#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL +#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST /* Debug_Timer */ #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -2742,41 +2756,41 @@ /* SCSI_RX_DMA */ #define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SCSI_RX_DMA__DRQ_NUMBER 0u +#define SCSI_RX_DMA__DRQ_NUMBER 2u #define SCSI_RX_DMA__NUMBEROF_TDS 0u #define SCSI_RX_DMA__PRIORITY 2u #define SCSI_RX_DMA__TERMIN_EN 0u #define SCSI_RX_DMA__TERMIN_SEL 0u #define SCSI_RX_DMA__TERMOUT0_EN 1u -#define SCSI_RX_DMA__TERMOUT0_SEL 0u +#define SCSI_RX_DMA__TERMOUT0_SEL 2u #define SCSI_RX_DMA__TERMOUT1_EN 0u #define SCSI_RX_DMA__TERMOUT1_SEL 0u #define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x04u -#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 2u +#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x10u +#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 4u #define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2 +#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 #define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* SCSI_TX_DMA */ #define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 -#define SCSI_TX_DMA__DRQ_NUMBER 1u +#define SCSI_TX_DMA__DRQ_NUMBER 3u #define SCSI_TX_DMA__NUMBEROF_TDS 0u #define SCSI_TX_DMA__PRIORITY 2u #define SCSI_TX_DMA__TERMIN_EN 0u #define SCSI_TX_DMA__TERMIN_SEL 0u #define SCSI_TX_DMA__TERMOUT0_EN 1u -#define SCSI_TX_DMA__TERMOUT0_SEL 1u +#define SCSI_TX_DMA__TERMOUT0_SEL 3u #define SCSI_TX_DMA__TERMOUT1_EN 0u #define SCSI_TX_DMA__TERMOUT1_SEL 0u #define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u -#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u +#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x40u +#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 6u #define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u -#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6 #define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 @@ -2805,20 +2819,20 @@ /* SCSI_RST_ISR */ #define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_RST_ISR__INTC_MASK 0x02u -#define SCSI_RST_ISR__INTC_NUMBER 1u +#define SCSI_RST_ISR__INTC_MASK 0x08u +#define SCSI_RST_ISR__INTC_NUMBER 3u #define SCSI_RST_ISR__INTC_PRIOR_NUM 7u -#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3 #define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* SCSI_SEL_ISR */ #define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 #define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 -#define SCSI_SEL_ISR__INTC_MASK 0x08u -#define SCSI_SEL_ISR__INTC_NUMBER 3u +#define SCSI_SEL_ISR__INTC_MASK 0x20u +#define SCSI_SEL_ISR__INTC_NUMBER 5u #define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u -#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3 +#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_5 #define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 @@ -2827,6 +2841,8 @@ #define SCSI_Filtered_sts_sts_reg__0__POS 0 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u #define SCSI_Filtered_sts_sts_reg__1__POS 1 +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u #define SCSI_Filtered_sts_sts_reg__2__POS 2 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u @@ -2834,76 +2850,80 @@ #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u #define SCSI_Filtered_sts_sts_reg__4__POS 4 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu -#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB15_MSK -#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB15_ST +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK +#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL +#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST /* SCSI_CTL_PHASE */ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK -#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK /* SCSI_Glitch_Ctl */ #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL #define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK /* SCSI_Parity_Error */ #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u #define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB09_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB09_ST /* Miscellaneous */ #define BCLK__BUS_CLK__HZ 50000000U #define BCLK__BUS_CLK__KHZ 50000U #define BCLK__BUS_CLK__MHZ 50U #define CY_PROJECT_NAME "SCSI2SD" -#define CY_VERSION "PSoC Creator 4.2" +#define CY_VERSION "PSoC Creator 4.4" #define CYDEV_CHIP_DIE_LEOPARD 1u -#define CYDEV_CHIP_DIE_PSOC4A 18u +#define CYDEV_CHIP_DIE_PSOC4A 26u #define CYDEV_CHIP_DIE_PSOC5LP 2u #define CYDEV_CHIP_DIE_PSOC5TM 3u #define CYDEV_CHIP_DIE_TMA4 4u @@ -2919,34 +2939,43 @@ #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5 #define CYDEV_CHIP_JTAG_ID 0x2E133069u #define CYDEV_CHIP_MEMBER_3A 1u -#define CYDEV_CHIP_MEMBER_4A 18u -#define CYDEV_CHIP_MEMBER_4D 13u +#define CYDEV_CHIP_MEMBER_4A 26u +#define CYDEV_CHIP_MEMBER_4AA 25u +#define CYDEV_CHIP_MEMBER_4AB 30u +#define CYDEV_CHIP_MEMBER_4AC 14u +#define CYDEV_CHIP_MEMBER_4AD 15u +#define CYDEV_CHIP_MEMBER_4AE 16u +#define CYDEV_CHIP_MEMBER_4D 20u #define CYDEV_CHIP_MEMBER_4E 6u -#define CYDEV_CHIP_MEMBER_4F 19u +#define CYDEV_CHIP_MEMBER_4F 27u #define CYDEV_CHIP_MEMBER_4G 4u -#define CYDEV_CHIP_MEMBER_4H 17u -#define CYDEV_CHIP_MEMBER_4I 23u -#define CYDEV_CHIP_MEMBER_4J 14u -#define CYDEV_CHIP_MEMBER_4K 15u -#define CYDEV_CHIP_MEMBER_4L 22u -#define CYDEV_CHIP_MEMBER_4M 21u -#define CYDEV_CHIP_MEMBER_4N 10u -#define CYDEV_CHIP_MEMBER_4O 7u -#define CYDEV_CHIP_MEMBER_4P 20u -#define CYDEV_CHIP_MEMBER_4Q 12u -#define CYDEV_CHIP_MEMBER_4R 8u -#define CYDEV_CHIP_MEMBER_4S 11u -#define CYDEV_CHIP_MEMBER_4T 9u +#define CYDEV_CHIP_MEMBER_4H 24u +#define CYDEV_CHIP_MEMBER_4I 32u +#define CYDEV_CHIP_MEMBER_4J 21u +#define CYDEV_CHIP_MEMBER_4K 22u +#define CYDEV_CHIP_MEMBER_4L 31u +#define CYDEV_CHIP_MEMBER_4M 29u +#define CYDEV_CHIP_MEMBER_4N 11u +#define CYDEV_CHIP_MEMBER_4O 8u +#define CYDEV_CHIP_MEMBER_4P 28u +#define CYDEV_CHIP_MEMBER_4Q 17u +#define CYDEV_CHIP_MEMBER_4R 9u +#define CYDEV_CHIP_MEMBER_4S 12u +#define CYDEV_CHIP_MEMBER_4T 10u #define CYDEV_CHIP_MEMBER_4U 5u -#define CYDEV_CHIP_MEMBER_4V 16u +#define CYDEV_CHIP_MEMBER_4V 23u +#define CYDEV_CHIP_MEMBER_4W 13u +#define CYDEV_CHIP_MEMBER_4X 7u +#define CYDEV_CHIP_MEMBER_4Y 18u +#define CYDEV_CHIP_MEMBER_4Z 19u #define CYDEV_CHIP_MEMBER_5A 3u #define CYDEV_CHIP_MEMBER_5B 2u -#define CYDEV_CHIP_MEMBER_6A 24u -#define CYDEV_CHIP_MEMBER_FM3 28u -#define CYDEV_CHIP_MEMBER_FM4 29u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 25u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 26u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 27u +#define CYDEV_CHIP_MEMBER_6A 33u +#define CYDEV_CHIP_MEMBER_FM3 37u +#define CYDEV_CHIP_MEMBER_FM4 38u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 34u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 35u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 36u #define CYDEV_CHIP_MEMBER_UNKNOWN 0u #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED @@ -2971,6 +3000,11 @@ #define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u #define CYDEV_CHIP_REVISION_4A_ES0 17u #define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_4AA_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4AB_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4AC_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4AD_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4AE_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD 0u #define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u @@ -2995,6 +3029,10 @@ #define CYDEV_CHIP_REVISION_4T_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4V_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4W_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4X_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4Y_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4Z_PRODUCTION 0u #define CYDEV_CHIP_REVISION_5A_ES0 0u #define CYDEV_CHIP_REVISION_5A_ES1 1u #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u @@ -3034,7 +3072,7 @@ #define CYDEV_ECC_ENABLE 0 #define CYDEV_HEAP_SIZE 0x0400 #define CYDEV_INSTRUCT_CACHE_ENABLED 1 -#define CYDEV_INTR_RISING 0x0000007Fu +#define CYDEV_INTR_RISING 0x000001FFu #define CYDEV_IS_EXPORTING_CODE 0 #define CYDEV_IS_IMPORTING_CODE 0 #define CYDEV_PROJ_TYPE 2 @@ -3089,7 +3127,7 @@ #define CYIPBLOCK_S8_SAR_VERSION 0 #define CYIPBLOCK_S8_SIO_VERSION 0 #define CYIPBLOCK_S8_UDB_VERSION 0 -#define DMA_CHANNELS_USED__MASK0 0x0000000Fu +#define DMA_CHANNELS_USED__MASK0 0x0000003Fu #define CYDEV_BOOTLOADER_ENABLE 0 #endif /* INCLUDED_CYFITTER_H */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index b9cd1c4..17daa0e 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -2,7 +2,7 @@ /******************************************************************************* * File Name: cyfitter_cfg.c * -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * This file contains device initialization code. @@ -10,7 +10,7 @@ * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -149,7 +149,7 @@ static void CyClockStartupError(uint8 errorCode) } #endif -#define CY_CFG_BASE_ADDR_COUNT 42u +#define CY_CFG_BASE_ADDR_COUNT 43u CYPACKED typedef struct { uint8 offset; @@ -369,7 +369,7 @@ void cyfitter_cfg(void) /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */ static const uint8 CYCODE BS_IOPINS0_3_VAL[] = { - 0x08u, 0x00u, 0x01u, 0xFEu, 0xFEu, 0x02u, 0xF6u, 0x00u, 0x00u, 0x01u}; + 0x08u, 0x00u, 0x01u, 0xFEu, 0xFEu, 0x02u, 0xC6u, 0x00u, 0x00u, 0x01u}; /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */ static const uint8 CYCODE BS_IOPINS0_4_VAL[] = { @@ -391,6 +391,14 @@ void cyfitter_cfg(void) static const uint8 CYCODE BS_PHUB_CFGMEM3_VAL[] = { 0x00u, 0x03u, 0x00u, 0x00u}; + /* PHUB_CFGMEM4 Address: CYREG_PHUB_CFGMEM4_CFG0 Size (bytes): 4 */ + static const uint8 CYCODE BS_PHUB_CFGMEM4_VAL[] = { + 0x00u, 0x04u, 0x00u, 0x00u}; + + /* PHUB_CFGMEM5 Address: CYREG_PHUB_CFGMEM5_CFG0 Size (bytes): 4 */ + static const uint8 CYCODE BS_PHUB_CFGMEM5_VAL[] = { + 0x00u, 0x05u, 0x00u, 0x00u}; + #ifdef CYGlobalIntDisable /* Disable interrupts by default. Let user enable if/when they want. */ CYGlobalIntDisable @@ -410,93 +418,100 @@ void cyfitter_cfg(void) static const uint32 CYCODE cy_cfg_addr_table[] = { 0x40004501u, /* Base address: 0x40004500 Count: 1 */ 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ - 0x4000520Eu, /* Base address: 0x40005200 Count: 14 */ + 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */ 0x40006402u, /* Base address: 0x40006400 Count: 2 */ - 0x40006502u, /* Base address: 0x40006500 Count: 2 */ - 0x40010045u, /* Base address: 0x40010000 Count: 69 */ - 0x4001013Au, /* Base address: 0x40010100 Count: 58 */ - 0x4001024Eu, /* Base address: 0x40010200 Count: 78 */ - 0x4001035Bu, /* Base address: 0x40010300 Count: 91 */ - 0x4001041Bu, /* Base address: 0x40010400 Count: 27 */ - 0x40010545u, /* Base address: 0x40010500 Count: 69 */ - 0x40010651u, /* Base address: 0x40010600 Count: 81 */ - 0x40010751u, /* Base address: 0x40010700 Count: 81 */ + 0x40006501u, /* Base address: 0x40006500 Count: 1 */ + 0x4001003Du, /* Base address: 0x40010000 Count: 61 */ + 0x4001013Fu, /* Base address: 0x40010100 Count: 63 */ + 0x4001025Au, /* Base address: 0x40010200 Count: 90 */ + 0x40010354u, /* Base address: 0x40010300 Count: 84 */ + 0x40010419u, /* Base address: 0x40010400 Count: 25 */ + 0x40010556u, /* Base address: 0x40010500 Count: 86 */ + 0x40010653u, /* Base address: 0x40010600 Count: 83 */ + 0x40010759u, /* Base address: 0x40010700 Count: 89 */ 0x4001084Eu, /* Base address: 0x40010800 Count: 78 */ - 0x4001095Fu, /* Base address: 0x40010900 Count: 95 */ - 0x40010A5Cu, /* Base address: 0x40010A00 Count: 92 */ - 0x40010B60u, /* Base address: 0x40010B00 Count: 96 */ - 0x40010C49u, /* Base address: 0x40010C00 Count: 73 */ - 0x40010D54u, /* Base address: 0x40010D00 Count: 84 */ - 0x40010E51u, /* Base address: 0x40010E00 Count: 81 */ - 0x40010F43u, /* Base address: 0x40010F00 Count: 67 */ - 0x40011462u, /* Base address: 0x40011400 Count: 98 */ - 0x40011540u, /* Base address: 0x40011500 Count: 64 */ - 0x40011651u, /* Base address: 0x40011600 Count: 81 */ - 0x4001174Cu, /* Base address: 0x40011700 Count: 76 */ - 0x40011855u, /* Base address: 0x40011800 Count: 85 */ - 0x40011948u, /* Base address: 0x40011900 Count: 72 */ - 0x40011B06u, /* Base address: 0x40011B00 Count: 6 */ - 0x4001401Du, /* Base address: 0x40014000 Count: 29 */ - 0x40014120u, /* Base address: 0x40014100 Count: 32 */ - 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */ - 0x4001430Au, /* Base address: 0x40014300 Count: 10 */ - 0x40014411u, /* Base address: 0x40014400 Count: 17 */ - 0x40014517u, /* Base address: 0x40014500 Count: 23 */ - 0x4001460Fu, /* Base address: 0x40014600 Count: 15 */ - 0x4001470Cu, /* Base address: 0x40014700 Count: 12 */ - 0x4001480Du, /* Base address: 0x40014800 Count: 13 */ - 0x4001491Au, /* Base address: 0x40014900 Count: 26 */ - 0x40014C0Cu, /* Base address: 0x40014C00 Count: 12 */ + 0x4001095Eu, /* Base address: 0x40010900 Count: 94 */ + 0x40010A41u, /* Base address: 0x40010A00 Count: 65 */ + 0x40010B5Cu, /* Base address: 0x40010B00 Count: 92 */ + 0x40010C4Fu, /* Base address: 0x40010C00 Count: 79 */ + 0x40010D61u, /* Base address: 0x40010D00 Count: 97 */ + 0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */ + 0x40010F41u, /* Base address: 0x40010F00 Count: 65 */ + 0x40011411u, /* Base address: 0x40011400 Count: 17 */ + 0x40011550u, /* Base address: 0x40011500 Count: 80 */ + 0x40011650u, /* Base address: 0x40011600 Count: 80 */ + 0x40011754u, /* Base address: 0x40011700 Count: 84 */ + 0x40011848u, /* Base address: 0x40011800 Count: 72 */ + 0x40011954u, /* Base address: 0x40011900 Count: 84 */ + 0x40011A4Eu, /* Base address: 0x40011A00 Count: 78 */ + 0x40011B48u, /* Base address: 0x40011B00 Count: 72 */ + 0x4001401Cu, /* Base address: 0x40014000 Count: 28 */ + 0x4001411Fu, /* Base address: 0x40014100 Count: 31 */ + 0x40014218u, /* Base address: 0x40014200 Count: 24 */ + 0x40014312u, /* Base address: 0x40014300 Count: 18 */ + 0x40014412u, /* Base address: 0x40014400 Count: 18 */ + 0x40014515u, /* Base address: 0x40014500 Count: 21 */ + 0x4001460Du, /* Base address: 0x40014600 Count: 13 */ + 0x4001470Eu, /* Base address: 0x40014700 Count: 14 */ + 0x40014817u, /* Base address: 0x40014800 Count: 23 */ + 0x40014914u, /* Base address: 0x40014900 Count: 20 */ + 0x40014C04u, /* Base address: 0x40014C00 Count: 4 */ 0x40014D07u, /* Base address: 0x40014D00 Count: 7 */ - 0x40015005u, /* Base address: 0x40015000 Count: 5 */ - 0x40015104u, /* Base address: 0x40015100 Count: 4 */ + 0x40015006u, /* Base address: 0x40015000 Count: 6 */ + 0x40015102u, /* Base address: 0x40015100 Count: 2 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x7Eu, 0x02u}, {0x01u, 0x30u}, - {0x0Au, 0x4Bu}, - {0x00u, 0x02u}, - {0x01u, 0x20u}, - {0x10u, 0xA8u}, - {0x11u, 0x2Au}, - {0x18u, 0x62u}, - {0x19u, 0x38u}, + {0x0Au, 0x36u}, + {0x00u, 0x22u}, + {0x10u, 0x0Au}, + {0x11u, 0x88u}, + {0x18u, 0xC2u}, + {0x19u, 0x44u}, {0x1Cu, 0x08u}, {0x20u, 0x01u}, - {0x30u, 0x84u}, - {0x31u, 0x20u}, - {0x61u, 0x20u}, + {0x31u, 0x84u}, + {0x60u, 0x20u}, + {0x61u, 0x22u}, {0x78u, 0x20u}, - {0x79u, 0x20u}, {0x7Cu, 0x40u}, {0x20u, 0x01u}, - {0x88u, 0x0Fu}, - {0x76u, 0x01u}, - {0x85u, 0x0Fu}, - {0x00u, 0x0Au}, - {0x02u, 0x55u}, - {0x06u, 0x7Fu}, - {0x0Cu, 0x8Bu}, - {0x0Eu, 0x74u}, - {0x14u, 0x91u}, - {0x16u, 0x6Cu}, - {0x18u, 0x01u}, - {0x1Cu, 0x40u}, - {0x1Eu, 0x80u}, - {0x22u, 0x10u}, - {0x24u, 0x06u}, - {0x28u, 0x20u}, - {0x2Au, 0x40u}, - {0x30u, 0x3Fu}, - {0x36u, 0xC0u}, - {0x3Au, 0x80u}, - {0x40u, 0x62u}, - {0x41u, 0x04u}, - {0x42u, 0x10u}, - {0x45u, 0xECu}, - {0x46u, 0x2Du}, - {0x47u, 0x0Fu}, + {0x84u, 0x0Fu}, + {0x84u, 0x0Fu}, + {0x01u, 0x06u}, + {0x02u, 0x03u}, + {0x05u, 0x02u}, + {0x06u, 0x04u}, + {0x07u, 0x01u}, + {0x0Du, 0x01u}, + {0x0Eu, 0x24u}, + {0x0Fu, 0x04u}, + {0x10u, 0x24u}, + {0x11u, 0x08u}, + {0x12u, 0x09u}, + {0x19u, 0x08u}, + {0x1Au, 0x18u}, + {0x28u, 0x24u}, + {0x29u, 0x10u}, + {0x2Au, 0x12u}, + {0x2Du, 0x01u}, + {0x2Eu, 0x20u}, + {0x2Fu, 0x02u}, + {0x30u, 0x07u}, + {0x31u, 0x07u}, + {0x33u, 0x10u}, + {0x34u, 0x38u}, + {0x35u, 0x08u}, + {0x39u, 0x22u}, + {0x3Fu, 0x04u}, + {0x40u, 0x46u}, + {0x41u, 0x02u}, + {0x42u, 0x50u}, + {0x45u, 0xDCu}, + {0x46u, 0x2Fu}, + {0x47u, 0x0Eu}, {0x48u, 0x1Fu}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, @@ -504,6 +519,7 @@ void cyfitter_cfg(void) {0x4Fu, 0x2Cu}, {0x56u, 0x01u}, {0x58u, 0x04u}, + {0x59u, 0x04u}, {0x5Au, 0x04u}, {0x5Bu, 0x04u}, {0x5Cu, 0x02u}, @@ -515,280 +531,270 @@ void cyfitter_cfg(void) {0x68u, 0x40u}, {0x69u, 0x40u}, {0x6Eu, 0x08u}, - {0x81u, 0x04u}, - {0x84u, 0x02u}, - {0x86u, 0x01u}, - {0x89u, 0x02u}, - {0x8Du, 0x01u}, - {0x94u, 0x02u}, {0x96u, 0x01u}, - {0x98u, 0x02u}, - {0x9Au, 0x05u}, - {0x9Cu, 0x01u}, - {0x9Eu, 0x02u}, - {0xA0u, 0x02u}, - {0xA2u, 0x09u}, - {0xB1u, 0x04u}, - {0xB2u, 0x08u}, - {0xB4u, 0x04u}, - {0xB5u, 0x02u}, - {0xB6u, 0x03u}, - {0xB7u, 0x01u}, - {0xBAu, 0x80u}, - {0xBFu, 0x50u}, - {0xD6u, 0x08u}, + {0x97u, 0x01u}, + {0xAAu, 0x02u}, + {0xB2u, 0x01u}, + {0xB3u, 0x01u}, + {0xB4u, 0x02u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x92u}, - {0xDDu, 0x90u}, + {0xDCu, 0x22u}, {0xDFu, 0x01u}, - {0x01u, 0x02u}, - {0x03u, 0x12u}, - {0x04u, 0x04u}, - {0x0Au, 0x01u}, - {0x0Bu, 0x28u}, - {0x0Eu, 0x2Au}, - {0x10u, 0xA4u}, - {0x16u, 0x80u}, + {0x01u, 0x06u}, + {0x03u, 0x02u}, + {0x08u, 0x20u}, + {0x0Au, 0x44u}, + {0x0Eu, 0x20u}, + {0x11u, 0x40u}, + {0x12u, 0x08u}, + {0x17u, 0x10u}, {0x19u, 0x02u}, - {0x1Au, 0x01u}, - {0x1Cu, 0x04u}, - {0x1Eu, 0x22u}, - {0x1Fu, 0x80u}, - {0x24u, 0x02u}, - {0x25u, 0x02u}, - {0x27u, 0x04u}, - {0x3Du, 0xA2u}, - {0x3Fu, 0x02u}, - {0x40u, 0x08u}, - {0x42u, 0x01u}, + {0x1Au, 0x04u}, + {0x1Eu, 0x10u}, + {0x1Fu, 0x10u}, + {0x21u, 0x11u}, + {0x22u, 0x02u}, + {0x23u, 0x20u}, + {0x25u, 0x04u}, + {0x27u, 0x10u}, + {0x29u, 0x20u}, + {0x2Bu, 0x01u}, + {0x31u, 0x22u}, + {0x36u, 0x04u}, + {0x39u, 0x02u}, + {0x3Bu, 0x44u}, + {0x40u, 0x04u}, {0x43u, 0x02u}, - {0x48u, 0x20u}, - {0x49u, 0x14u}, - {0x4Bu, 0x22u}, - {0x50u, 0x80u}, - {0x51u, 0x60u}, + {0x48u, 0x04u}, + {0x49u, 0x84u}, + {0x4Au, 0x88u}, {0x52u, 0x10u}, - {0x53u, 0x08u}, - {0x59u, 0xA0u}, - {0x5Bu, 0x0Au}, - {0x5Cu, 0x80u}, - {0x60u, 0x60u}, - {0x62u, 0xA0u}, - {0x66u, 0x80u}, - {0x68u, 0x04u}, + {0x53u, 0x68u}, + {0x58u, 0x12u}, + {0x59u, 0x08u}, + {0x5Au, 0x80u}, + {0x60u, 0x80u}, + {0x62u, 0x20u}, + {0x63u, 0x21u}, + {0x68u, 0x80u}, {0x69u, 0x44u}, - {0x6Bu, 0x40u}, - {0x70u, 0x50u}, - {0x72u, 0x40u}, - {0x73u, 0x10u}, - {0x81u, 0x60u}, - {0x83u, 0x01u}, - {0x84u, 0x08u}, - {0x85u, 0x46u}, - {0x87u, 0x10u}, - {0x88u, 0xA0u}, - {0x8Cu, 0x41u}, - {0xC0u, 0x2Du}, - {0xC2u, 0xE7u}, - {0xC4u, 0x1Eu}, - {0xCEu, 0xB0u}, - {0xD0u, 0x0Du}, - {0xD2u, 0x04u}, - {0xD6u, 0x1Fu}, - {0xD8u, 0x1Fu}, - {0xE0u, 0x2Du}, - {0xE2u, 0x42u}, - {0xE4u, 0x0Au}, - {0x01u, 0x02u}, - {0x03u, 0x11u}, - {0x05u, 0x02u}, - {0x07u, 0x05u}, - {0x0Cu, 0x02u}, - {0x0Du, 0x02u}, - {0x0Eu, 0x01u}, - {0x0Fu, 0x01u}, - {0x11u, 0x01u}, - {0x13u, 0x02u}, + {0x6Bu, 0x08u}, + {0x70u, 0x08u}, + {0x72u, 0x0Au}, + {0x73u, 0x80u}, + {0x81u, 0x04u}, + {0x84u, 0x02u}, + {0x86u, 0x88u}, + {0x87u, 0x80u}, + {0x8Au, 0x02u}, + {0x8Bu, 0x40u}, + {0x8Fu, 0x01u}, + {0xC0u, 0x0Du}, + {0xC2u, 0x2Au}, + {0xC4u, 0x43u}, + {0xCAu, 0x0Cu}, + {0xCCu, 0x45u}, + {0xCEu, 0x0Bu}, + {0xD0u, 0x05u}, + {0xD2u, 0x0Cu}, + {0xD6u, 0x0Fu}, + {0xD8u, 0x0Fu}, + {0xE0u, 0x02u}, + {0xE2u, 0x08u}, + {0xE4u, 0x09u}, + {0xE6u, 0x82u}, + {0x01u, 0x1Cu}, + {0x04u, 0x01u}, + {0x05u, 0x14u}, + {0x06u, 0x02u}, + {0x07u, 0x08u}, + {0x08u, 0x02u}, + {0x09u, 0x24u}, + {0x0Au, 0x01u}, + {0x0Bu, 0x10u}, + {0x0Du, 0x30u}, + {0x0Fu, 0x0Fu}, + {0x11u, 0x0Cu}, + {0x13u, 0x10u}, {0x14u, 0x02u}, - {0x15u, 0x02u}, - {0x16u, 0x11u}, - {0x17u, 0x09u}, - {0x18u, 0x02u}, - {0x1Au, 0x05u}, - {0x1Cu, 0x01u}, - {0x1Eu, 0x02u}, - {0x24u, 0x02u}, - {0x26u, 0x09u}, - {0x30u, 0x04u}, - {0x31u, 0x03u}, - {0x32u, 0x08u}, - {0x33u, 0x08u}, - {0x34u, 0x10u}, - {0x35u, 0x10u}, - {0x36u, 0x03u}, - {0x37u, 0x04u}, - {0x3Au, 0x80u}, - {0x3Bu, 0x02u}, + {0x15u, 0x21u}, + {0x16u, 0x01u}, + {0x17u, 0x1Eu}, + {0x19u, 0x11u}, + {0x1Bu, 0x22u}, + {0x1Cu, 0x02u}, + {0x1Eu, 0x05u}, + {0x20u, 0x02u}, + {0x21u, 0x1Cu}, + {0x22u, 0x09u}, + {0x29u, 0x10u}, + {0x2Bu, 0x0Cu}, + {0x2Du, 0x08u}, + {0x32u, 0x04u}, + {0x33u, 0x0Fu}, + {0x34u, 0x03u}, + {0x35u, 0x30u}, + {0x36u, 0x08u}, + {0x3Au, 0x20u}, + {0x3Bu, 0x20u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x22u}, + {0x5Cu, 0x12u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x78u}, - {0x82u, 0x03u}, - {0x86u, 0x7Fu}, - {0x87u, 0x06u}, - {0x8Cu, 0x20u}, - {0x8Eu, 0x40u}, - {0x8Fu, 0x08u}, - {0x90u, 0x01u}, - {0x92u, 0x6Eu}, - {0x94u, 0x20u}, - {0x96u, 0x40u}, - {0x97u, 0x30u}, - {0x98u, 0x80u}, - {0x9Au, 0x01u}, - {0x9Bu, 0x01u}, - {0x9Cu, 0x03u}, - {0x9Eu, 0x74u}, - {0x9Fu, 0x40u}, - {0xA0u, 0x02u}, - {0xA1u, 0x49u}, - {0xA3u, 0x24u}, + {0x81u, 0xC0u}, + {0x83u, 0x02u}, + {0x85u, 0x7Fu}, + {0x87u, 0x80u}, + {0x88u, 0x50u}, + {0x8Au, 0x0Cu}, + {0x8Bu, 0x60u}, + {0x8Cu, 0x5Cu}, + {0x8Fu, 0xFFu}, + {0x90u, 0x21u}, + {0x91u, 0x90u}, + {0x92u, 0x1Eu}, + {0x93u, 0x40u}, + {0x94u, 0x24u}, + {0x95u, 0xC0u}, + {0x96u, 0x10u}, + {0x97u, 0x08u}, + {0x98u, 0x30u}, + {0x99u, 0xC0u}, + {0x9Au, 0x0Fu}, + {0x9Bu, 0x04u}, + {0x9Cu, 0x5Cu}, + {0x9Du, 0xC0u}, + {0x9Fu, 0x01u}, + {0xA0u, 0x11u}, + {0xA2u, 0x22u}, + {0xA3u, 0x9Fu}, + {0xA4u, 0x54u}, + {0xA5u, 0x80u}, {0xA6u, 0x08u}, - {0xA8u, 0x64u}, - {0xA9u, 0x01u}, - {0xABu, 0x48u}, - {0xADu, 0x49u}, - {0xAFu, 0x12u}, - {0xB2u, 0x80u}, - {0xB3u, 0x70u}, - {0xB4u, 0x1Fu}, - {0xB5u, 0x0Eu}, - {0xB6u, 0x60u}, - {0xB7u, 0x01u}, - {0xBAu, 0x80u}, - {0xBEu, 0x04u}, - {0xBFu, 0x40u}, + {0xA8u, 0x08u}, + {0xACu, 0x0Cu}, + {0xADu, 0x1Fu}, + {0xAEu, 0x50u}, + {0xAFu, 0x20u}, + {0xB0u, 0x0Fu}, + {0xB2u, 0x30u}, + {0xB4u, 0x40u}, + {0xB5u, 0xFFu}, + {0xB6u, 0x40u}, + {0xBAu, 0x08u}, + {0xBEu, 0x50u}, + {0xBFu, 0x10u}, + {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x22u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x82u}, - {0x03u, 0x10u}, - {0x04u, 0x40u}, - {0x08u, 0x89u}, - {0x0Bu, 0x08u}, - {0x0Du, 0x20u}, + {0x00u, 0x80u}, + {0x03u, 0x04u}, + {0x04u, 0x14u}, + {0x06u, 0x20u}, + {0x09u, 0x80u}, + {0x0Au, 0x20u}, + {0x0Bu, 0x44u}, {0x0Eu, 0x12u}, - {0x10u, 0x84u}, - {0x12u, 0x10u}, - {0x13u, 0x02u}, - {0x16u, 0x20u}, - {0x18u, 0x28u}, - {0x19u, 0x90u}, - {0x1Cu, 0x42u}, - {0x1Du, 0x20u}, - {0x1Eu, 0x12u}, - {0x20u, 0x24u}, - {0x21u, 0x88u}, - {0x25u, 0x45u}, - {0x26u, 0x02u}, - {0x27u, 0x04u}, - {0x28u, 0x01u}, - {0x29u, 0x12u}, - {0x2Bu, 0x02u}, - {0x2Eu, 0x40u}, + {0x10u, 0x22u}, + {0x12u, 0x44u}, + {0x16u, 0x80u}, + {0x18u, 0x40u}, + {0x19u, 0x14u}, + {0x1Au, 0x22u}, + {0x1Bu, 0x05u}, + {0x1Cu, 0x14u}, + {0x1Eu, 0x22u}, + {0x21u, 0x20u}, + {0x24u, 0x08u}, + {0x25u, 0x18u}, + {0x27u, 0x20u}, + {0x29u, 0x05u}, + {0x2Au, 0x40u}, + {0x2Bu, 0x01u}, + {0x2Du, 0x11u}, {0x2Fu, 0x01u}, - {0x30u, 0x20u}, - {0x31u, 0x08u}, - {0x33u, 0x40u}, - {0x36u, 0x02u}, - {0x37u, 0x04u}, - {0x38u, 0x04u}, - {0x39u, 0x40u}, - {0x3Du, 0x88u}, - {0x3Fu, 0x01u}, - {0x40u, 0x20u}, - {0x43u, 0x08u}, - {0x58u, 0x20u}, - {0x59u, 0x04u}, - {0x5Au, 0x40u}, - {0x5Bu, 0x02u}, - {0x5Fu, 0x50u}, - {0x61u, 0x80u}, - {0x66u, 0x20u}, - {0x67u, 0x01u}, - {0x6Bu, 0x01u}, - {0x80u, 0x10u}, - {0x81u, 0x10u}, - {0x84u, 0x54u}, - {0x87u, 0x04u}, - {0x8Bu, 0x50u}, - {0x91u, 0x40u}, - {0x93u, 0x02u}, - {0x97u, 0x08u}, - {0x99u, 0x06u}, - {0x9Au, 0x10u}, - {0x9Bu, 0x40u}, - {0x9Cu, 0x04u}, - {0x9Du, 0x90u}, - {0x9Fu, 0x18u}, - {0xA0u, 0xA4u}, - {0xA2u, 0x10u}, + {0x30u, 0x22u}, + {0x31u, 0x80u}, + {0x33u, 0x04u}, + {0x34u, 0x04u}, + {0x37u, 0x21u}, + {0x39u, 0x22u}, + {0x3Bu, 0x44u}, + {0x3Du, 0x20u}, + {0x3Eu, 0x46u}, + {0x58u, 0x40u}, + {0x5Du, 0x40u}, + {0x60u, 0x02u}, + {0x66u, 0x80u}, + {0x82u, 0x20u}, + {0x89u, 0x02u}, + {0x8Bu, 0x08u}, + {0x8Cu, 0x02u}, + {0x8Eu, 0x08u}, + {0x8Fu, 0x02u}, + {0x91u, 0x20u}, + {0x92u, 0x10u}, + {0x93u, 0xA0u}, + {0x96u, 0x80u}, + {0x97u, 0x44u}, + {0x98u, 0x61u}, + {0x99u, 0x02u}, + {0x9Au, 0x18u}, + {0x9Du, 0xA0u}, + {0xA0u, 0x84u}, + {0xA1u, 0x04u}, + {0xA2u, 0x80u}, {0xA3u, 0x08u}, - {0xA4u, 0x01u}, - {0xA5u, 0x11u}, - {0xA6u, 0xA4u}, - {0xA7u, 0x02u}, - {0xA8u, 0x10u}, - {0xABu, 0x82u}, - {0xACu, 0x01u}, - {0xADu, 0x22u}, - {0xB3u, 0x01u}, - {0xB4u, 0x40u}, + {0xA5u, 0x22u}, + {0xA6u, 0x34u}, + {0xA7u, 0x13u}, + {0xA8u, 0x80u}, + {0xA9u, 0x08u}, + {0xABu, 0x20u}, + {0xACu, 0x08u}, + {0xAFu, 0x08u}, + {0xB0u, 0x51u}, + {0xB2u, 0x02u}, + {0xB4u, 0x04u}, {0xB6u, 0x40u}, - {0xB7u, 0x0Cu}, - {0xC0u, 0x8Du}, - {0xC2u, 0xEFu}, - {0xC4u, 0x2Eu}, - {0xCAu, 0x0Du}, - {0xCCu, 0xCEu}, - {0xCEu, 0xDAu}, - {0xD6u, 0x3Fu}, - {0xD8u, 0x38u}, - {0xE0u, 0x28u}, - {0xE2u, 0x01u}, - {0xE4u, 0x82u}, - {0xE6u, 0x08u}, - {0xE8u, 0x04u}, + {0xB7u, 0x28u}, + {0xC0u, 0x63u}, + {0xC2u, 0xAFu}, + {0xC4u, 0x1Fu}, + {0xCAu, 0xBBu}, + {0xCCu, 0xEFu}, + {0xCEu, 0xFFu}, + {0xD6u, 0x18u}, + {0xD8u, 0x18u}, + {0xE0u, 0x04u}, + {0xE4u, 0x04u}, + {0xE8u, 0x0Au}, {0xEAu, 0x10u}, - {0xECu, 0x0Cu}, - {0xEEu, 0x13u}, - {0x88u, 0x02u}, - {0x8Du, 0x02u}, - {0x8Fu, 0x01u}, - {0x91u, 0x02u}, - {0x93u, 0x05u}, + {0xEEu, 0x05u}, + {0x85u, 0x02u}, + {0x87u, 0x01u}, + {0x8Du, 0x01u}, + {0x8Fu, 0x02u}, {0x95u, 0x02u}, - {0x96u, 0x01u}, - {0x97u, 0x09u}, - {0x99u, 0x01u}, - {0x9Bu, 0x02u}, + {0x97u, 0x01u}, + {0xA2u, 0x02u}, + {0xA5u, 0x02u}, + {0xA7u, 0x01u}, + {0xACu, 0x01u}, {0xADu, 0x02u}, - {0xAFu, 0x11u}, - {0xB0u, 0x02u}, - {0xB1u, 0x04u}, - {0xB3u, 0x03u}, - {0xB4u, 0x01u}, - {0xB5u, 0x10u}, - {0xB7u, 0x08u}, - {0xBBu, 0x08u}, + {0xAFu, 0x05u}, + {0xB0u, 0x01u}, + {0xB2u, 0x02u}, + {0xB3u, 0x04u}, + {0xB7u, 0x03u}, + {0xBBu, 0x80u}, {0xBEu, 0x01u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, @@ -797,785 +803,626 @@ void cyfitter_cfg(void) {0xDCu, 0x22u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x18u}, - {0x01u, 0x80u}, - {0x05u, 0x10u}, - {0x08u, 0xA0u}, - {0x09u, 0x88u}, - {0x0Bu, 0x80u}, - {0x0Eu, 0x20u}, - {0x11u, 0xAAu}, - {0x19u, 0x01u}, - {0x1Au, 0x02u}, - {0x1Cu, 0x80u}, - {0x1Eu, 0x08u}, - {0x20u, 0x08u}, - {0x21u, 0x24u}, - {0x23u, 0x01u}, - {0x24u, 0x40u}, - {0x27u, 0x36u}, - {0x28u, 0x20u}, - {0x29u, 0x21u}, - {0x2Au, 0x40u}, + {0x00u, 0x0Au}, + {0x01u, 0xA0u}, + {0x08u, 0x42u}, + {0x0Bu, 0x08u}, + {0x12u, 0x99u}, + {0x14u, 0x01u}, + {0x17u, 0x02u}, + {0x19u, 0xA0u}, + {0x1Au, 0x80u}, + {0x1Eu, 0x80u}, + {0x1Fu, 0x08u}, + {0x20u, 0x20u}, + {0x21u, 0x04u}, + {0x22u, 0x20u}, + {0x25u, 0x40u}, + {0x26u, 0x04u}, + {0x28u, 0x04u}, {0x2Eu, 0x80u}, - {0x30u, 0x02u}, - {0x31u, 0xA8u}, - {0x37u, 0x26u}, - {0x38u, 0x90u}, + {0x2Fu, 0x10u}, + {0x30u, 0x40u}, + {0x31u, 0x08u}, + {0x32u, 0x60u}, + {0x36u, 0x04u}, + {0x38u, 0x80u}, {0x39u, 0x08u}, - {0x3Au, 0x01u}, - {0x3Cu, 0x40u}, - {0x40u, 0x81u}, - {0x41u, 0x08u}, - {0x48u, 0x80u}, - {0x49u, 0x08u}, - {0x4Au, 0x0Au}, - {0x4Bu, 0x02u}, - {0x52u, 0x50u}, - {0x53u, 0x48u}, - {0x5Du, 0x40u}, + {0x3Du, 0x88u}, + {0x40u, 0x44u}, + {0x42u, 0x20u}, + {0x49u, 0x15u}, + {0x4Bu, 0x40u}, + {0x50u, 0x01u}, + {0x51u, 0x20u}, + {0x52u, 0x04u}, + {0x53u, 0x80u}, + {0x5Cu, 0x80u}, + {0x62u, 0x20u}, {0x66u, 0x80u}, - {0x82u, 0x20u}, - {0x86u, 0x90u}, - {0x87u, 0x08u}, - {0x8Du, 0x40u}, - {0x8Fu, 0x20u}, - {0x90u, 0x04u}, - {0x9Bu, 0x01u}, - {0x9Fu, 0x18u}, - {0xA2u, 0x10u}, - {0xA4u, 0x40u}, - {0xA6u, 0xA4u}, - {0xA7u, 0x02u}, - {0xA8u, 0x08u}, - {0xACu, 0x04u}, - {0xB4u, 0x84u}, - {0xC0u, 0x47u}, - {0xC2u, 0x2Fu}, - {0xC4u, 0x0Fu}, - {0xCAu, 0x1Fu}, - {0xCCu, 0xEFu}, - {0xCEu, 0x1Fu}, - {0xD0u, 0x0Bu}, + {0x69u, 0x51u}, + {0x6Au, 0x04u}, + {0x6Bu, 0x51u}, + {0x72u, 0x03u}, + {0x73u, 0x01u}, + {0x8Au, 0x60u}, + {0x8Cu, 0x01u}, + {0x90u, 0x48u}, + {0x91u, 0x20u}, + {0x92u, 0x02u}, + {0x93u, 0xB0u}, + {0x95u, 0x13u}, + {0x96u, 0xC4u}, + {0x97u, 0x46u}, + {0x98u, 0x23u}, + {0x99u, 0x12u}, + {0x9Au, 0x10u}, + {0x9Bu, 0x20u}, + {0x9Cu, 0x04u}, + {0x9Du, 0xA1u}, + {0x9Eu, 0x06u}, + {0x9Fu, 0x05u}, + {0xA0u, 0x84u}, + {0xA1u, 0x0Cu}, + {0xA2u, 0x88u}, + {0xA3u, 0x05u}, + {0xA4u, 0x62u}, + {0xA5u, 0x82u}, + {0xA6u, 0x04u}, + {0xA7u, 0x10u}, + {0xAEu, 0x20u}, + {0xAFu, 0x10u}, + {0xB5u, 0x40u}, + {0xB6u, 0x08u}, + {0xB7u, 0x20u}, + {0xC0u, 0x0Fu}, + {0xC2u, 0x0Bu}, + {0xC4u, 0x9Fu}, + {0xCAu, 0x54u}, + {0xCCu, 0x46u}, + {0xCEu, 0x5Au}, + {0xD0u, 0x07u}, {0xD2u, 0x0Cu}, {0xD6u, 0x10u}, - {0xD8u, 0x10u}, - {0xE0u, 0x42u}, - {0xE4u, 0x02u}, - {0xE6u, 0x89u}, + {0xD8u, 0x14u}, + {0xE2u, 0x21u}, + {0xE4u, 0x80u}, {0xE8u, 0x40u}, - {0xEAu, 0x08u}, - {0xEEu, 0x04u}, - {0x01u, 0x01u}, - {0x02u, 0x9Fu}, - {0x04u, 0x80u}, - {0x05u, 0x01u}, - {0x08u, 0x1Fu}, - {0x09u, 0x88u}, - {0x0Au, 0x20u}, - {0x0Bu, 0x21u}, - {0x0Cu, 0xC0u}, - {0x0Du, 0xA2u}, - {0x0Eu, 0x01u}, - {0x0Fu, 0x08u}, - {0x10u, 0x7Fu}, - {0x11u, 0x01u}, - {0x12u, 0x80u}, - {0x15u, 0x01u}, - {0x16u, 0xFFu}, - {0x18u, 0xC0u}, - {0x19u, 0x40u}, - {0x1Au, 0x04u}, - {0x1Cu, 0xC0u}, - {0x1Du, 0x04u}, - {0x1Eu, 0x02u}, - {0x21u, 0x10u}, - {0x22u, 0x60u}, - {0x25u, 0x87u}, - {0x27u, 0x18u}, - {0x28u, 0xC0u}, - {0x2Au, 0x08u}, - {0x2Cu, 0x90u}, - {0x2Du, 0x01u}, - {0x2Eu, 0x40u}, - {0x31u, 0x80u}, - {0x32u, 0xFFu}, - {0x33u, 0x40u}, - {0x35u, 0x3Fu}, - {0x37u, 0x08u}, - {0x39u, 0x20u}, - {0x3Eu, 0x04u}, - {0x3Fu, 0x51u}, - {0x54u, 0x09u}, - {0x56u, 0x04u}, + {0xEEu, 0x02u}, + {0x00u, 0x04u}, + {0x02u, 0x02u}, + {0x0Du, 0x02u}, + {0x0Fu, 0x01u}, + {0x11u, 0x02u}, + {0x13u, 0x09u}, + {0x14u, 0x02u}, + {0x15u, 0x02u}, + {0x16u, 0x04u}, + {0x17u, 0x01u}, + {0x18u, 0x04u}, + {0x19u, 0x01u}, + {0x1Au, 0x0Au}, + {0x1Bu, 0x02u}, + {0x1Cu, 0x04u}, + {0x1Eu, 0x03u}, + {0x24u, 0x04u}, + {0x26u, 0x12u}, + {0x29u, 0x02u}, + {0x2Bu, 0x05u}, + {0x30u, 0x01u}, + {0x32u, 0x06u}, + {0x33u, 0x04u}, + {0x34u, 0x10u}, + {0x35u, 0x03u}, + {0x36u, 0x08u}, + {0x37u, 0x08u}, + {0x3Au, 0x08u}, + {0x3Bu, 0x20u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x90u}, - {0x5Du, 0x10u}, + {0x5Cu, 0x22u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x81u, 0x9Cu}, - {0x84u, 0x01u}, - {0x89u, 0x61u}, - {0x8Bu, 0x1Eu}, + {0x80u, 0xC6u}, + {0x81u, 0x10u}, + {0x84u, 0x42u}, + {0x85u, 0x22u}, + {0x87u, 0x08u}, + {0x88u, 0x39u}, + {0x89u, 0x04u}, + {0x8Au, 0x06u}, {0x8Cu, 0x01u}, - {0x8Du, 0xA4u}, - {0x8Eu, 0x02u}, - {0x8Fu, 0x10u}, - {0x91u, 0x8Cu}, - {0x93u, 0x10u}, - {0x95u, 0x30u}, - {0x97u, 0x8Fu}, - {0x98u, 0x02u}, - {0x99u, 0xD1u}, - {0x9Bu, 0x22u}, - {0x9Du, 0x08u}, - {0x9Fu, 0x40u}, - {0xA1u, 0x9Cu}, - {0xA5u, 0x94u}, - {0xA7u, 0x08u}, - {0xADu, 0x10u}, - {0xAFu, 0x8Cu}, - {0xB0u, 0x03u}, - {0xB1u, 0x30u}, - {0xB3u, 0xC1u}, - {0xB7u, 0x0Fu}, - {0xBBu, 0x0Eu}, - {0xBEu, 0x01u}, + {0x8Du, 0x08u}, + {0x8Eu, 0x5Eu}, + {0x8Fu, 0x21u}, + {0x91u, 0x01u}, + {0x94u, 0x77u}, + {0x96u, 0x08u}, + {0x98u, 0xC2u}, + {0x99u, 0x01u}, + {0x9Au, 0x04u}, + {0x9Cu, 0x04u}, + {0x9Du, 0x01u}, + {0x9Eu, 0x20u}, + {0xA0u, 0xC6u}, + {0xA1u, 0x01u}, + {0xA8u, 0x80u}, + {0xA9u, 0x01u}, + {0xAAu, 0x46u}, + {0xACu, 0x46u}, + {0xADu, 0x07u}, + {0xAEu, 0x80u}, + {0xAFu, 0x18u}, + {0xB0u, 0x70u}, + {0xB1u, 0x3Fu}, + {0xB4u, 0x0Fu}, + {0xB6u, 0x80u}, + {0xB7u, 0x08u}, + {0xB8u, 0x20u}, + {0xB9u, 0x02u}, + {0xBAu, 0x03u}, + {0xBEu, 0x40u}, + {0xBFu, 0x41u}, {0xD4u, 0x09u}, + {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, + {0xDCu, 0x01u}, {0xDFu, 0x01u}, - {0x00u, 0x04u}, - {0x03u, 0x01u}, - {0x05u, 0x16u}, - {0x06u, 0x02u}, - {0x0Au, 0x08u}, - {0x0Eu, 0x56u}, - {0x14u, 0x40u}, - {0x15u, 0x50u}, - {0x19u, 0x01u}, + {0x00u, 0x40u}, + {0x01u, 0x20u}, + {0x02u, 0x10u}, + {0x03u, 0x40u}, + {0x04u, 0x08u}, + {0x05u, 0x01u}, + {0x06u, 0x10u}, + {0x09u, 0x08u}, + {0x0Au, 0x04u}, + {0x0Bu, 0x02u}, + {0x0Eu, 0x2Au}, + {0x11u, 0x50u}, + {0x13u, 0x01u}, + {0x16u, 0x20u}, + {0x18u, 0xC0u}, + {0x19u, 0x60u}, + {0x1Au, 0x48u}, + {0x1Du, 0x01u}, + {0x1Eu, 0x2Au}, {0x1Fu, 0x04u}, - {0x20u, 0x40u}, - {0x21u, 0x88u}, - {0x26u, 0x44u}, - {0x27u, 0x48u}, - {0x28u, 0xA0u}, - {0x2Au, 0x80u}, - {0x2Du, 0x42u}, - {0x2Fu, 0x20u}, - {0x30u, 0x82u}, - {0x31u, 0x08u}, - {0x32u, 0x20u}, - {0x34u, 0x40u}, - {0x35u, 0x04u}, - {0x36u, 0x81u}, - {0x37u, 0x20u}, - {0x38u, 0xD0u}, - {0x3Au, 0x01u}, - {0x3Cu, 0x80u}, - {0x3Eu, 0x16u}, - {0x44u, 0x01u}, - {0x47u, 0x40u}, - {0x59u, 0x08u}, - {0x5Bu, 0x92u}, - {0x5Cu, 0x02u}, - {0x5Eu, 0x80u}, - {0x5Fu, 0x14u}, - {0x63u, 0x01u}, - {0x64u, 0x01u}, - {0x67u, 0x40u}, - {0x7Cu, 0x40u}, - {0x7Du, 0x80u}, - {0x80u, 0xB0u}, - {0x81u, 0x35u}, - {0x82u, 0x81u}, - {0x84u, 0x02u}, - {0x85u, 0x80u}, - {0x8Au, 0x04u}, - {0x8Bu, 0x40u}, - {0x8Du, 0x81u}, - {0x8Eu, 0x22u}, - {0x90u, 0x04u}, - {0x93u, 0x83u}, - {0x94u, 0x91u}, - {0x99u, 0x08u}, - {0x9Bu, 0x21u}, - {0x9Cu, 0x20u}, - {0x9Du, 0xA0u}, - {0x9Eu, 0x01u}, - {0xA0u, 0x80u}, - {0xA4u, 0x02u}, - {0xA5u, 0xDDu}, - {0xA6u, 0x0Au}, - {0xABu, 0x08u}, - {0xAFu, 0x01u}, - {0xB2u, 0x01u}, - {0xB4u, 0x10u}, - {0xB5u, 0x10u}, - {0xB7u, 0x02u}, - {0xC0u, 0xF5u}, - {0xC2u, 0xF2u}, - {0xC4u, 0xD0u}, - {0xCAu, 0xDBu}, - {0xCCu, 0xFFu}, - {0xCEu, 0xFDu}, - {0xD6u, 0xFFu}, - {0xD8u, 0x98u}, - {0xE2u, 0x2Du}, - {0xE4u, 0x10u}, - {0xE6u, 0x05u}, - {0xE8u, 0x02u}, - {0xEAu, 0x25u}, - {0x00u, 0x11u}, - {0x01u, 0x40u}, - {0x02u, 0x22u}, - {0x03u, 0x03u}, - {0x04u, 0xFFu}, - {0x05u, 0x80u}, - {0x0Au, 0xFFu}, - {0x0Bu, 0x20u}, - {0x0Cu, 0x0Fu}, - {0x0Du, 0x40u}, - {0x0Eu, 0xF0u}, + {0x21u, 0x02u}, + {0x22u, 0x40u}, + {0x25u, 0x40u}, + {0x26u, 0x28u}, + {0x27u, 0x0Au}, + {0x28u, 0x10u}, + {0x2Au, 0x44u}, + {0x2Bu, 0x47u}, + {0x2Fu, 0x08u}, + {0x30u, 0x26u}, + {0x31u, 0x80u}, + {0x32u, 0x04u}, + {0x34u, 0x02u}, + {0x36u, 0x28u}, + {0x38u, 0x02u}, + {0x39u, 0x20u}, + {0x3Bu, 0x44u}, + {0x3Du, 0x80u}, + {0x58u, 0x10u}, + {0x59u, 0x04u}, + {0x5Au, 0x82u}, + {0x5Du, 0x80u}, + {0x5Fu, 0x10u}, + {0x60u, 0x80u}, + {0x62u, 0x80u}, + {0x64u, 0x02u}, + {0x66u, 0x20u}, + {0x84u, 0x80u}, + {0x85u, 0x40u}, + {0x90u, 0x0Au}, + {0x91u, 0x70u}, + {0x92u, 0x07u}, + {0x93u, 0x11u}, + {0x94u, 0x84u}, + {0x95u, 0x02u}, + {0x96u, 0x40u}, + {0x97u, 0x4Eu}, + {0x98u, 0x20u}, + {0x99u, 0x06u}, + {0x9Au, 0x06u}, + {0x9Bu, 0x71u}, + {0x9Cu, 0x04u}, + {0x9Fu, 0x06u}, + {0xA0u, 0x10u}, + {0xA1u, 0x28u}, + {0xA3u, 0x8Du}, + {0xA4u, 0x62u}, + {0xA5u, 0x82u}, + {0xAAu, 0x01u}, + {0xABu, 0x10u}, + {0xACu, 0x81u}, + {0xAFu, 0x40u}, + {0xB1u, 0x40u}, + {0xB3u, 0x01u}, + {0xB4u, 0x80u}, + {0xC0u, 0x1Fu}, + {0xC2u, 0xE7u}, + {0xC4u, 0x2Bu}, + {0xCAu, 0x2Du}, + {0xCCu, 0xEDu}, + {0xCEu, 0x1Fu}, + {0xD6u, 0x3Fu}, + {0xD8u, 0x39u}, + {0xE2u, 0x04u}, + {0xE4u, 0x08u}, + {0xE6u, 0x04u}, + {0xE8u, 0x08u}, + {0xEAu, 0x05u}, + {0xEEu, 0x09u}, + {0x00u, 0x04u}, + {0x01u, 0x01u}, + {0x03u, 0x02u}, + {0x05u, 0x04u}, + {0x06u, 0x20u}, + {0x07u, 0x08u}, + {0x09u, 0x10u}, + {0x0Au, 0x07u}, + {0x0Bu, 0x8Fu}, + {0x0Cu, 0x01u}, + {0x0Du, 0x0Fu}, {0x0Fu, 0x80u}, - {0x10u, 0x33u}, - {0x12u, 0xCCu}, - {0x13u, 0x24u}, - {0x14u, 0x48u}, - {0x16u, 0x84u}, - {0x17u, 0x18u}, - {0x18u, 0x12u}, - {0x19u, 0x24u}, - {0x1Au, 0x21u}, - {0x1Bu, 0x09u}, - {0x1Cu, 0xFFu}, - {0x24u, 0x44u}, - {0x26u, 0x88u}, - {0x27u, 0x04u}, - {0x29u, 0x24u}, - {0x2Bu, 0x12u}, - {0x30u, 0xFFu}, - {0x31u, 0x07u}, - {0x33u, 0x38u}, - {0x37u, 0xC0u}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x40u}, - {0x56u, 0x02u}, - {0x57u, 0x2Cu}, + {0x11u, 0x01u}, + {0x13u, 0x02u}, + {0x15u, 0x20u}, + {0x16u, 0x18u}, + {0x17u, 0x0Fu}, + {0x18u, 0x07u}, + {0x19u, 0x04u}, + {0x1Bu, 0x08u}, + {0x1Eu, 0x20u}, + {0x20u, 0x20u}, + {0x21u, 0x4Fu}, + {0x22u, 0x10u}, + {0x23u, 0x80u}, + {0x26u, 0x02u}, + {0x27u, 0x10u}, + {0x28u, 0x20u}, + {0x29u, 0x50u}, + {0x2Au, 0x08u}, + {0x2Bu, 0x8Fu}, + {0x31u, 0x03u}, + {0x32u, 0x38u}, + {0x33u, 0xF0u}, + {0x34u, 0x07u}, + {0x35u, 0x0Cu}, + {0x39u, 0x08u}, + {0x3Bu, 0x22u}, + {0x3Eu, 0x10u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x20u}, + {0x5Cu, 0x22u}, {0x5Fu, 0x01u}, - {0x80u, 0x0Fu}, - {0x82u, 0xF0u}, - {0x84u, 0xFFu}, - {0x85u, 0x44u}, - {0x87u, 0x88u}, - {0x89u, 0x84u}, - {0x8Bu, 0x48u}, - {0x8Fu, 0xFFu}, - {0x91u, 0x11u}, - {0x92u, 0xFFu}, - {0x93u, 0x22u}, - {0x94u, 0x33u}, - {0x96u, 0xCCu}, - {0x98u, 0xFFu}, - {0x9Bu, 0xFFu}, - {0x9Cu, 0x96u}, - {0x9Eu, 0x69u}, - {0xA0u, 0x55u}, - {0xA1u, 0x33u}, - {0xA2u, 0xAAu}, - {0xA3u, 0xCCu}, - {0xA5u, 0xFFu}, - {0xA6u, 0xFFu}, - {0xA9u, 0x21u}, - {0xABu, 0x12u}, - {0xADu, 0x0Fu}, - {0xAEu, 0xFFu}, - {0xAFu, 0xF0u}, - {0xB0u, 0xFFu}, - {0xB3u, 0xFFu}, - {0xBAu, 0x02u}, - {0xBFu, 0x04u}, + {0x80u, 0x05u}, + {0x82u, 0x0Au}, + {0x85u, 0x08u}, + {0x88u, 0x06u}, + {0x89u, 0x20u}, + {0x8Au, 0x09u}, + {0x8Cu, 0x0Fu}, + {0x8Eu, 0xF0u}, + {0x90u, 0x30u}, + {0x91u, 0x10u}, + {0x92u, 0xC0u}, + {0x94u, 0x03u}, + {0x95u, 0x04u}, + {0x96u, 0x0Cu}, + {0x9Du, 0x01u}, + {0xA4u, 0x60u}, + {0xA6u, 0x90u}, + {0xA8u, 0x50u}, + {0xA9u, 0x02u}, + {0xAAu, 0xA0u}, + {0xADu, 0x15u}, + {0xAFu, 0x2Au}, + {0xB1u, 0x30u}, + {0xB3u, 0x0Cu}, + {0xB5u, 0x03u}, + {0xB6u, 0xFFu}, + {0xBEu, 0x40u}, + {0xBFu, 0x15u}, + {0xD4u, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x02u}, + {0xDDu, 0x20u}, {0xDFu, 0x01u}, - {0x01u, 0x02u}, - {0x02u, 0x20u}, - {0x05u, 0x95u}, - {0x07u, 0xA2u}, - {0x08u, 0x0Au}, - {0x0Bu, 0x09u}, - {0x0Cu, 0x01u}, - {0x0Du, 0x40u}, - {0x0Eu, 0x12u}, - {0x0Fu, 0x98u}, - {0x10u, 0x10u}, - {0x11u, 0x08u}, - {0x12u, 0x42u}, - {0x15u, 0x04u}, - {0x19u, 0x02u}, - {0x1Fu, 0x01u}, - {0x22u, 0x08u}, + {0x00u, 0x02u}, + {0x02u, 0x80u}, + {0x03u, 0x0Au}, + {0x05u, 0x10u}, + {0x06u, 0xA2u}, + {0x0Au, 0x20u}, + {0x0Bu, 0x40u}, + {0x0Du, 0x10u}, + {0x0Eu, 0x22u}, + {0x10u, 0x04u}, + {0x13u, 0x14u}, + {0x14u, 0x20u}, + {0x15u, 0x01u}, + {0x17u, 0x10u}, + {0x1Bu, 0x80u}, + {0x1Eu, 0x20u}, + {0x1Fu, 0x18u}, + {0x20u, 0x08u}, + {0x21u, 0x06u}, {0x24u, 0x20u}, - {0x25u, 0x01u}, - {0x26u, 0x84u}, - {0x27u, 0x80u}, - {0x29u, 0x84u}, - {0x2Bu, 0x48u}, - {0x2Fu, 0x14u}, - {0x31u, 0x11u}, - {0x34u, 0x12u}, - {0x36u, 0x04u}, - {0x39u, 0x84u}, - {0x3Bu, 0x10u}, - {0x3Cu, 0x20u}, - {0x3Du, 0x86u}, - {0x48u, 0x02u}, - {0x4Au, 0x01u}, - {0x67u, 0x80u}, - {0x68u, 0x05u}, - {0x69u, 0x05u}, - {0x6Au, 0x12u}, - {0x6Cu, 0x01u}, - {0x6Eu, 0x04u}, - {0x6Fu, 0x66u}, - {0x70u, 0x04u}, - {0x71u, 0xA0u}, - {0x72u, 0x01u}, - {0x73u, 0x40u}, - {0x74u, 0x80u}, - {0x76u, 0x01u}, - {0x7Bu, 0x0Cu}, - {0x80u, 0x80u}, - {0x83u, 0x64u}, - {0x87u, 0x02u}, - {0x88u, 0x01u}, - {0x8Cu, 0x82u}, - {0x8Eu, 0x08u}, - {0x91u, 0x20u}, - {0x92u, 0x28u}, - {0x93u, 0xA8u}, - {0x94u, 0x68u}, - {0x95u, 0x01u}, - {0x96u, 0x01u}, - {0x97u, 0x42u}, - {0x98u, 0x0Fu}, - {0x99u, 0x38u}, - {0x9Au, 0x40u}, - {0x9Bu, 0x02u}, - {0x9Du, 0x02u}, - {0x9Eu, 0x0Cu}, - {0x9Fu, 0x08u}, - {0xA0u, 0x10u}, - {0xA1u, 0x44u}, - {0xA2u, 0x22u}, - {0xA3u, 0x08u}, - {0xA4u, 0x04u}, - {0xA5u, 0x20u}, - {0xA6u, 0x08u}, - {0xA8u, 0x04u}, - {0xA9u, 0x10u}, - {0xABu, 0x60u}, - {0xACu, 0x11u}, - {0xADu, 0x40u}, - {0xB4u, 0x80u}, - {0xB5u, 0x44u}, + {0x26u, 0x2Au}, + {0x27u, 0x10u}, + {0x28u, 0x04u}, + {0x2Bu, 0x02u}, + {0x2Cu, 0x28u}, + {0x2Du, 0x01u}, + {0x2Fu, 0x20u}, + {0x32u, 0x81u}, + {0x33u, 0x08u}, + {0x34u, 0x08u}, + {0x36u, 0x22u}, + {0x39u, 0x10u}, + {0x3Bu, 0x04u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x20u}, + {0x3Fu, 0x0Au}, + {0x44u, 0x08u}, + {0x46u, 0x04u}, + {0x48u, 0x08u}, + {0x4Au, 0x08u}, + {0x58u, 0x60u}, + {0x59u, 0x20u}, + {0x5Cu, 0x04u}, + {0x5Eu, 0x40u}, + {0x5Fu, 0x21u}, + {0x64u, 0x40u}, + {0x65u, 0x81u}, + {0x6Fu, 0x02u}, + {0x85u, 0x02u}, + {0x89u, 0x02u}, + {0x8Eu, 0x04u}, + {0x8Fu, 0x01u}, + {0x91u, 0xA1u}, + {0x92u, 0x62u}, + {0x93u, 0x08u}, + {0x94u, 0xA8u}, + {0x95u, 0x1Cu}, + {0x97u, 0x40u}, + {0x98u, 0x80u}, + {0x99u, 0x01u}, + {0x9Au, 0x32u}, + {0x9Bu, 0x28u}, + {0x9Du, 0x08u}, + {0x9Eu, 0x04u}, + {0xA0u, 0x23u}, + {0xA1u, 0x40u}, + {0xA2u, 0x05u}, + {0xA3u, 0x45u}, + {0xA4u, 0x54u}, + {0xA5u, 0x01u}, + {0xA6u, 0x2Au}, + {0xA7u, 0x82u}, + {0xAAu, 0x28u}, + {0xACu, 0x10u}, + {0xADu, 0x08u}, + {0xAEu, 0x80u}, + {0xAFu, 0x10u}, + {0xB2u, 0x02u}, + {0xB3u, 0x20u}, {0xB7u, 0x40u}, - {0xC0u, 0xFCu}, - {0xC2u, 0xFFu}, - {0xC4u, 0x2Du}, - {0xCAu, 0x6Fu}, - {0xCCu, 0xE5u}, - {0xCEu, 0xFEu}, - {0xD8u, 0x80u}, - {0xE0u, 0x10u}, - {0xE2u, 0x80u}, - {0xE4u, 0x40u}, - {0xE8u, 0x10u}, - {0xEAu, 0x41u}, - {0xEEu, 0x43u}, - {0x05u, 0x50u}, - {0x06u, 0x04u}, - {0x07u, 0xA0u}, - {0x09u, 0x05u}, - {0x0Au, 0x03u}, - {0x0Bu, 0x0Au}, - {0x0Cu, 0x40u}, - {0x0Du, 0x30u}, - {0x0Fu, 0xC0u}, - {0x11u, 0x06u}, + {0xC0u, 0xFBu}, + {0xC2u, 0xECu}, + {0xC4u, 0x76u}, + {0xCAu, 0xECu}, + {0xCCu, 0xEBu}, + {0xCEu, 0xF6u}, + {0xD6u, 0xF8u}, + {0xD8u, 0x10u}, + {0xE2u, 0x04u}, + {0xE6u, 0x04u}, + {0xE8u, 0x82u}, + {0xEAu, 0x01u}, + {0xECu, 0x60u}, + {0xEEu, 0x02u}, + {0x01u, 0x04u}, + {0x02u, 0x40u}, + {0x03u, 0x02u}, + {0x06u, 0x30u}, + {0x0Bu, 0x04u}, + {0x0Du, 0x10u}, + {0x10u, 0x48u}, + {0x11u, 0x08u}, {0x12u, 0x24u}, - {0x13u, 0x09u}, - {0x14u, 0x24u}, - {0x15u, 0x03u}, - {0x16u, 0x09u}, - {0x17u, 0x0Cu}, - {0x18u, 0x24u}, - {0x19u, 0x60u}, - {0x1Au, 0x12u}, - {0x1Bu, 0x90u}, - {0x1Cu, 0x40u}, - {0x22u, 0x18u}, - {0x24u, 0x40u}, - {0x28u, 0x40u}, - {0x2Du, 0x0Fu}, - {0x2Eu, 0x20u}, - {0x2Fu, 0xF0u}, - {0x30u, 0x40u}, - {0x32u, 0x07u}, - {0x34u, 0x38u}, - {0x37u, 0xFFu}, - {0x3Eu, 0x01u}, - {0x3Fu, 0x40u}, + {0x13u, 0x10u}, + {0x16u, 0x48u}, + {0x17u, 0x04u}, + {0x19u, 0x08u}, + {0x1Au, 0x01u}, + {0x1Bu, 0x03u}, + {0x1Eu, 0x06u}, + {0x22u, 0x08u}, + {0x28u, 0x48u}, + {0x29u, 0x04u}, + {0x2Au, 0x12u}, + {0x2Bu, 0x01u}, + {0x30u, 0x01u}, + {0x33u, 0x18u}, + {0x34u, 0x70u}, + {0x35u, 0x07u}, + {0x36u, 0x0Eu}, + {0x3Fu, 0x04u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x02u}, + {0x5Cu, 0x22u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x81u, 0x01u}, - {0x83u, 0x02u}, - {0x84u, 0x04u}, - {0x85u, 0x04u}, - {0x86u, 0x08u}, - {0x87u, 0x08u}, - {0x89u, 0x01u}, - {0x8Au, 0x3Fu}, - {0x8Bu, 0x02u}, - {0x8Cu, 0x3Fu}, - {0x8Du, 0x50u}, - {0x8Fu, 0x8Fu}, - {0x91u, 0x10u}, - {0x92u, 0x3Fu}, - {0x93u, 0x8Fu}, - {0x94u, 0x3Fu}, - {0x95u, 0x20u}, - {0x97u, 0x0Fu}, - {0x98u, 0x01u}, - {0x99u, 0x0Fu}, - {0x9Au, 0x02u}, - {0x9Bu, 0x80u}, - {0x9Cu, 0x10u}, - {0x9Du, 0x04u}, - {0x9Eu, 0x20u}, - {0x9Fu, 0x08u}, - {0xA0u, 0x10u}, - {0xA1u, 0x4Fu}, - {0xA2u, 0x20u}, - {0xA3u, 0x80u}, - {0xA4u, 0x04u}, - {0xA6u, 0x08u}, - {0xA7u, 0x10u}, - {0xA8u, 0x01u}, - {0xAAu, 0x02u}, - {0xAEu, 0x3Fu}, - {0xB1u, 0x03u}, - {0xB2u, 0x0Cu}, - {0xB3u, 0xF0u}, - {0xB4u, 0x03u}, - {0xB6u, 0x30u}, - {0xB7u, 0x0Cu}, - {0xB9u, 0x08u}, - {0xBAu, 0xA8u}, - {0xBBu, 0x82u}, - {0xD4u, 0x01u}, + {0x82u, 0x70u}, + {0x84u, 0xC0u}, + {0x86u, 0x1Fu}, + {0x88u, 0x90u}, + {0x8Au, 0x2Fu}, + {0x8Cu, 0x06u}, + {0x8Eu, 0x09u}, + {0x8Fu, 0x04u}, + {0x94u, 0x03u}, + {0x96u, 0x0Cu}, + {0x97u, 0x02u}, + {0x98u, 0x0Fu}, + {0x9Cu, 0xA0u}, + {0x9Eu, 0x4Fu}, + {0xA0u, 0x05u}, + {0xA2u, 0x0Au}, + {0xA6u, 0x80u}, + {0xA9u, 0x01u}, + {0xADu, 0x02u}, + {0xAFu, 0x04u}, + {0xB0u, 0x7Fu}, + {0xB5u, 0x01u}, + {0xB6u, 0x80u}, + {0xB7u, 0x06u}, + {0xBEu, 0x40u}, + {0xBFu, 0x50u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x22u}, - {0xDDu, 0x20u}, + {0xDCu, 0x02u}, {0xDFu, 0x01u}, - {0x00u, 0x40u}, - {0x01u, 0x04u}, - {0x03u, 0x08u}, - {0x05u, 0x04u}, - {0x06u, 0x02u}, - {0x07u, 0x04u}, - {0x08u, 0x02u}, + {0x00u, 0x04u}, + {0x01u, 0x02u}, + {0x02u, 0x10u}, + {0x04u, 0xA0u}, + {0x05u, 0x01u}, + {0x06u, 0x20u}, {0x09u, 0x04u}, - {0x0Bu, 0x0Au}, - {0x0Eu, 0x28u}, - {0x0Fu, 0x82u}, - {0x10u, 0x42u}, - {0x12u, 0x08u}, - {0x13u, 0x08u}, - {0x14u, 0x02u}, + {0x0Au, 0x0Au}, + {0x0Bu, 0x80u}, + {0x0Cu, 0x60u}, + {0x0Eu, 0x20u}, + {0x10u, 0x80u}, + {0x12u, 0x08u}, {0x15u, 0x02u}, - {0x16u, 0x20u}, - {0x17u, 0x10u}, - {0x1Au, 0x48u}, - {0x1Bu, 0x08u}, - {0x1Cu, 0x04u}, - {0x1Du, 0x04u}, - {0x1Eu, 0x08u}, - {0x1Fu, 0x80u}, - {0x23u, 0x02u}, - {0x25u, 0x05u}, + {0x17u, 0x04u}, + {0x18u, 0x04u}, + {0x1Au, 0x82u}, + {0x1Du, 0x41u}, + {0x21u, 0x08u}, + {0x22u, 0x10u}, + {0x25u, 0x50u}, {0x26u, 0x80u}, - {0x28u, 0x01u}, - {0x29u, 0x40u}, - {0x2Du, 0x08u}, - {0x2Eu, 0x02u}, - {0x2Fu, 0x20u}, - {0x31u, 0x20u}, - {0x32u, 0x05u}, - {0x34u, 0x02u}, - {0x36u, 0xA0u}, - {0x37u, 0x04u}, - {0x38u, 0x28u}, + {0x27u, 0x01u}, + {0x29u, 0x10u}, + {0x2Cu, 0x40u}, + {0x2Du, 0x41u}, + {0x2Fu, 0x08u}, + {0x30u, 0x08u}, + {0x32u, 0x10u}, + {0x33u, 0x02u}, + {0x37u, 0x08u}, + {0x39u, 0x01u}, + {0x3Au, 0x20u}, {0x3Bu, 0x40u}, - {0x3Du, 0x02u}, - {0x3Fu, 0xA8u}, - {0x58u, 0x10u}, - {0x5Bu, 0x40u}, - {0x5Du, 0x80u}, - {0x60u, 0x08u}, - {0x62u, 0x40u}, - {0x63u, 0x08u}, - {0x79u, 0x02u}, - {0x7Bu, 0x80u}, - {0x81u, 0x01u}, - {0x85u, 0x30u}, - {0x87u, 0x80u}, - {0x88u, 0x40u}, - {0x8Au, 0x04u}, - {0x8Cu, 0x20u}, - {0x8Du, 0x08u}, - {0x8Eu, 0x42u}, - {0x8Fu, 0x04u}, - {0x91u, 0x44u}, - {0x92u, 0x22u}, - {0x93u, 0xA8u}, - {0x95u, 0x01u}, - {0x96u, 0x01u}, - {0x98u, 0x06u}, - {0x99u, 0x80u}, - {0x9Au, 0x22u}, - {0x9Bu, 0x10u}, - {0x9Cu, 0x80u}, - {0x9Du, 0x46u}, - {0x9Eu, 0x4Cu}, - {0xA0u, 0x12u}, - {0xA2u, 0x30u}, - {0xA3u, 0x31u}, - {0xA4u, 0x24u}, - {0xA5u, 0x2Cu}, - {0xA6u, 0x80u}, - {0xA7u, 0x48u}, - {0xA8u, 0x40u}, - {0xABu, 0x04u}, - {0xADu, 0x20u}, - {0xAFu, 0x88u}, - {0xB2u, 0x04u}, - {0xB4u, 0x42u}, - {0xC0u, 0xE7u}, - {0xC2u, 0xFFu}, - {0xC4u, 0xFFu}, - {0xCAu, 0xC8u}, - {0xCCu, 0xF7u}, - {0xCEu, 0xFEu}, - {0xD6u, 0x1Cu}, - {0xD8u, 0x0Cu}, - {0xE4u, 0x10u}, - {0xE6u, 0x80u}, - {0xE8u, 0x51u}, - {0xECu, 0x08u}, - {0xEEu, 0x02u}, - {0x01u, 0x02u}, - {0x03u, 0x01u}, - {0x08u, 0x01u}, - {0x0Au, 0x06u}, - {0x0Du, 0x02u}, - {0x0Fu, 0x01u}, - {0x11u, 0x10u}, - {0x13u, 0x20u}, - {0x15u, 0x01u}, - {0x17u, 0x12u}, - {0x1Cu, 0x04u}, - {0x1Eu, 0x03u}, - {0x20u, 0x03u}, - {0x22u, 0x04u}, - {0x25u, 0x02u}, - {0x27u, 0x09u}, - {0x28u, 0x05u}, - {0x2Au, 0x02u}, - {0x2Du, 0x02u}, - {0x2Fu, 0x25u}, - {0x31u, 0x08u}, - {0x33u, 0x03u}, - {0x35u, 0x30u}, - {0x36u, 0x07u}, - {0x37u, 0x04u}, - {0x3Au, 0x80u}, - {0x3Bu, 0x08u}, - {0x3Fu, 0x10u}, - {0x56u, 0x08u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, + {0x3Eu, 0x80u}, + {0x49u, 0x10u}, + {0x4Au, 0x08u}, + {0x58u, 0x18u}, + {0x59u, 0x80u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x20u}, - {0x5Du, 0x90u}, - {0x5Fu, 0x01u}, - {0x81u, 0x24u}, - {0x83u, 0x12u}, - {0x84u, 0x40u}, - {0x88u, 0x20u}, - {0x8Bu, 0x18u}, - {0x8Fu, 0x20u}, - {0x90u, 0x29u}, - {0x91u, 0x40u}, - {0x92u, 0x52u}, - {0x93u, 0x03u}, - {0x94u, 0x08u}, - {0x97u, 0x04u}, - {0x99u, 0x80u}, - {0x9Cu, 0x10u}, - {0x9Du, 0x40u}, - {0x9Fu, 0x80u}, - {0xA0u, 0x02u}, - {0xA1u, 0x24u}, - {0xA3u, 0x09u}, - {0xA8u, 0x01u}, - {0xAEu, 0x04u}, - {0xAFu, 0x24u}, - {0xB0u, 0x03u}, - {0xB1u, 0x07u}, - {0xB2u, 0x04u}, - {0xB3u, 0xC0u}, - {0xB4u, 0x60u}, - {0xB5u, 0x38u}, - {0xB6u, 0x18u}, - {0xBEu, 0x51u}, - {0xBFu, 0x04u}, - {0xD6u, 0x08u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDCu, 0x22u}, - {0xDDu, 0x90u}, - {0xDFu, 0x01u}, - {0x00u, 0x08u}, - {0x03u, 0x08u}, - {0x06u, 0x08u}, - {0x0Au, 0xA1u}, - {0x0Eu, 0x02u}, - {0x10u, 0x04u}, - {0x11u, 0x81u}, - {0x14u, 0x80u}, - {0x16u, 0x04u}, - {0x18u, 0x80u}, - {0x19u, 0x18u}, - {0x1Bu, 0x80u}, - {0x1Eu, 0x02u}, - {0x1Fu, 0x40u}, - {0x21u, 0x10u}, - {0x22u, 0x15u}, - {0x25u, 0x41u}, - {0x26u, 0x34u}, - {0x27u, 0x0Cu}, - {0x28u, 0x02u}, - {0x2Bu, 0x40u}, - {0x2Du, 0x08u}, - {0x2Fu, 0x01u}, - {0x31u, 0x60u}, - {0x32u, 0x49u}, - {0x36u, 0x04u}, - {0x37u, 0x01u}, - {0x39u, 0xA0u}, - {0x3Au, 0x02u}, - {0x3Du, 0x82u}, - {0x59u, 0x20u}, - {0x5Au, 0x44u}, - {0x5Cu, 0x50u}, - {0x63u, 0x2Au}, - {0x66u, 0x20u}, - {0x67u, 0x02u}, - {0x6Bu, 0x01u}, - {0x6Du, 0x40u}, - {0x6Eu, 0x10u}, - {0x6Fu, 0x20u}, - {0x80u, 0x10u}, + {0x5Cu, 0x08u}, + {0x5Eu, 0x81u}, + {0x5Fu, 0x10u}, + {0x63u, 0x0Au}, + {0x65u, 0x40u}, + {0x69u, 0x40u}, + {0x6Cu, 0x22u}, + {0x6Fu, 0x18u}, + {0x80u, 0x04u}, {0x81u, 0x10u}, - {0x82u, 0x50u}, {0x84u, 0x04u}, {0x85u, 0x04u}, - {0x87u, 0x20u}, - {0x8Au, 0x04u}, - {0x91u, 0x80u}, - {0x93u, 0x28u}, - {0x99u, 0x80u}, - {0x9Au, 0x02u}, - {0x9Bu, 0x10u}, - {0x9Cu, 0x02u}, - {0x9Du, 0x06u}, - {0x9Eu, 0x60u}, - {0x9Fu, 0x04u}, - {0xA0u, 0x12u}, - {0xA2u, 0x08u}, - {0xA4u, 0x20u}, - {0xA5u, 0x0Cu}, - {0xA6u, 0xA4u}, - {0xA7u, 0x75u}, - {0xA8u, 0x61u}, - {0xA9u, 0x04u}, - {0xAAu, 0x08u}, - {0xADu, 0x10u}, - {0xAFu, 0x08u}, - {0xB1u, 0x08u}, - {0xB4u, 0x02u}, - {0xB7u, 0x80u}, - {0xC0u, 0x46u}, - {0xC2u, 0x8Du}, - {0xC4u, 0x5Bu}, - {0xCAu, 0x59u}, - {0xCCu, 0xCFu}, - {0xCEu, 0x9Du}, - {0xD6u, 0x3Eu}, - {0xD8u, 0x3Eu}, - {0xE2u, 0x04u}, - {0xE4u, 0x04u}, - {0xE6u, 0x01u}, - {0xE8u, 0x80u}, - {0xEAu, 0x40u}, - {0xECu, 0x40u}, - {0x00u, 0x06u}, - {0x01u, 0x55u}, - {0x02u, 0x09u}, - {0x03u, 0xAAu}, - {0x04u, 0x0Fu}, - {0x05u, 0xFFu}, - {0x09u, 0x69u}, - {0x0Bu, 0x96u}, - {0x10u, 0x40u}, - {0x11u, 0x0Fu}, - {0x12u, 0x1Fu}, - {0x13u, 0xF0u}, - {0x14u, 0x10u}, - {0x16u, 0x2Fu}, - {0x17u, 0xFFu}, - {0x19u, 0xFFu}, - {0x1Eu, 0x70u}, - {0x23u, 0xFFu}, - {0x24u, 0x05u}, - {0x26u, 0x0Au}, - {0x28u, 0x20u}, - {0x29u, 0x33u}, - {0x2Au, 0x4Fu}, - {0x2Bu, 0xCCu}, - {0x2Cu, 0x03u}, - {0x2Eu, 0x0Cu}, - {0x2Fu, 0xFFu}, - {0x31u, 0xFFu}, - {0x36u, 0x7Fu}, - {0x3Bu, 0x02u}, + {0x8Eu, 0x04u}, + {0x91u, 0xA3u}, + {0x92u, 0x49u}, + {0x93u, 0x88u}, + {0x94u, 0x20u}, + {0x95u, 0x14u}, + {0x96u, 0x82u}, + {0x98u, 0x80u}, + {0x99u, 0x82u}, + {0x9Au, 0xA0u}, + {0x9Bu, 0x0Cu}, + {0x9Du, 0x08u}, + {0x9Eu, 0x04u}, + {0x9Fu, 0x11u}, + {0xA0u, 0x89u}, + {0xA1u, 0x04u}, + {0xA2u, 0x51u}, + {0xA4u, 0x70u}, + {0xA5u, 0x01u}, + {0xA6u, 0x0Au}, + {0xA7u, 0x83u}, + {0xA8u, 0x82u}, + {0xADu, 0x60u}, + {0xAFu, 0x02u}, + {0xB5u, 0x41u}, + {0xB6u, 0x09u}, + {0xC0u, 0xFCu}, + {0xC2u, 0xEFu}, + {0xC4u, 0x3Au}, + {0xCAu, 0x34u}, + {0xCCu, 0x47u}, + {0xCEu, 0x1Du}, + {0xD6u, 0xFCu}, + {0xD8u, 0x1Cu}, + {0xE0u, 0x48u}, + {0xE4u, 0x03u}, + {0xE8u, 0x10u}, + {0xEAu, 0x04u}, + {0xECu, 0x10u}, + {0xEEu, 0x09u}, + {0x01u, 0x02u}, + {0x02u, 0xFFu}, + {0x05u, 0x20u}, + {0x06u, 0xFFu}, + {0x07u, 0x40u}, + {0x08u, 0x0Fu}, + {0x09u, 0x01u}, + {0x0Au, 0xF0u}, + {0x0Bu, 0x6Eu}, + {0x11u, 0x64u}, + {0x14u, 0x33u}, + {0x15u, 0x03u}, + {0x16u, 0xCCu}, + {0x17u, 0x74u}, + {0x1Bu, 0x01u}, + {0x1Cu, 0xFFu}, + {0x20u, 0xFFu}, + {0x21u, 0x78u}, + {0x23u, 0x03u}, + {0x26u, 0xFFu}, + {0x27u, 0x7Fu}, + {0x28u, 0x69u}, + {0x29u, 0x20u}, + {0x2Au, 0x96u}, + {0x2Bu, 0x40u}, + {0x2Cu, 0x55u}, + {0x2Eu, 0xAAu}, + {0x2Fu, 0x08u}, + {0x32u, 0xFFu}, + {0x33u, 0x1Fu}, + {0x37u, 0x60u}, + {0x3Au, 0x08u}, + {0x3Bu, 0x80u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, @@ -1583,819 +1430,1082 @@ void cyfitter_cfg(void) {0x5Cu, 0x22u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x0Bu}, - {0x81u, 0x55u}, - {0x82u, 0xF4u}, - {0x83u, 0xAAu}, - {0x84u, 0x02u}, - {0x88u, 0x10u}, - {0x89u, 0x69u}, - {0x8Au, 0x20u}, - {0x8Bu, 0x96u}, - {0x8Cu, 0x40u}, - {0x8Eu, 0x80u}, - {0x8Fu, 0xFFu}, - {0x90u, 0x08u}, - {0x92u, 0xF7u}, - {0x93u, 0xFFu}, - {0x95u, 0x0Fu}, - {0x96u, 0xF7u}, - {0x97u, 0xF0u}, - {0x98u, 0x03u}, - {0x99u, 0xFFu}, - {0x9Au, 0x0Cu}, - {0x9Cu, 0x10u}, - {0x9Eu, 0x20u}, - {0xA0u, 0x40u}, - {0xA1u, 0xFFu}, - {0xA2u, 0x80u}, - {0xA4u, 0xF4u}, + {0x80u, 0x0Fu}, + {0x81u, 0x0Fu}, + {0x82u, 0xF0u}, + {0x83u, 0xF0u}, + {0x84u, 0x44u}, + {0x86u, 0x88u}, + {0x8Bu, 0xFFu}, + {0x8Cu, 0x33u}, + {0x8Du, 0x33u}, + {0x8Eu, 0xCCu}, + {0x8Fu, 0xCCu}, + {0x91u, 0xFFu}, + {0x92u, 0xFFu}, + {0x96u, 0xFFu}, + {0x97u, 0xFFu}, + {0x98u, 0x11u}, + {0x9Au, 0x22u}, + {0x9Cu, 0x21u}, + {0x9Du, 0xFFu}, + {0x9Eu, 0x12u}, {0xA7u, 0xFFu}, - {0xA8u, 0xFDu}, - {0xA9u, 0x33u}, - {0xAAu, 0x02u}, - {0xABu, 0xCCu}, - {0xAEu, 0x01u}, - {0xB2u, 0x30u}, - {0xB4u, 0x0Fu}, - {0xB5u, 0xFFu}, - {0xB6u, 0xC0u}, - {0xBAu, 0xA8u}, - {0xBBu, 0x20u}, + {0xA8u, 0x84u}, + {0xA9u, 0x69u}, + {0xAAu, 0x48u}, + {0xABu, 0x96u}, + {0xACu, 0xFFu}, + {0xADu, 0x55u}, + {0xAFu, 0xAAu}, + {0xB1u, 0xFFu}, + {0xB4u, 0xFFu}, + {0xBBu, 0x02u}, + {0xBEu, 0x10u}, + {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x22u}, + {0xDCu, 0x20u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x02u}, - {0x03u, 0x20u}, + {0x01u, 0x04u}, + {0x03u, 0x82u}, {0x04u, 0x10u}, - {0x05u, 0x41u}, - {0x07u, 0x20u}, - {0x08u, 0x02u}, - {0x09u, 0x04u}, - {0x0Au, 0x01u}, - {0x0Du, 0x08u}, - {0x0Eu, 0x04u}, - {0x0Fu, 0x81u}, - {0x12u, 0x06u}, - {0x13u, 0x08u}, - {0x16u, 0x45u}, - {0x17u, 0x04u}, - {0x19u, 0x80u}, - {0x1Au, 0x01u}, + {0x05u, 0x05u}, + {0x08u, 0x28u}, + {0x09u, 0x01u}, + {0x0Au, 0x02u}, + {0x0Du, 0x80u}, + {0x0Fu, 0x20u}, + {0x10u, 0x02u}, + {0x11u, 0x10u}, + {0x14u, 0x06u}, + {0x16u, 0x20u}, + {0x17u, 0x01u}, + {0x1Au, 0x04u}, {0x1Cu, 0x10u}, - {0x1Du, 0x40u}, - {0x1Eu, 0x04u}, - {0x1Fu, 0x88u}, - {0x22u, 0x02u}, - {0x27u, 0x08u}, - {0x28u, 0x02u}, - {0x2Bu, 0x44u}, - {0x2Cu, 0x20u}, - {0x2Eu, 0x22u}, - {0x31u, 0x08u}, - {0x32u, 0x22u}, - {0x34u, 0x02u}, - {0x35u, 0x01u}, - {0x36u, 0x20u}, - {0x37u, 0x08u}, - {0x3Au, 0x14u}, - {0x3Bu, 0x09u}, - {0x3Fu, 0xA2u}, - {0x41u, 0x20u}, + {0x1Eu, 0x20u}, + {0x21u, 0x01u}, + {0x25u, 0x04u}, + {0x26u, 0x04u}, + {0x27u, 0x02u}, + {0x29u, 0x04u}, + {0x2Au, 0x0Cu}, + {0x2Bu, 0x05u}, + {0x2Du, 0x60u}, + {0x2Eu, 0x08u}, + {0x2Fu, 0x40u}, + {0x31u, 0x80u}, + {0x32u, 0x08u}, + {0x33u, 0x01u}, + {0x36u, 0x04u}, + {0x37u, 0x11u}, + {0x39u, 0x02u}, + {0x3Au, 0x60u}, + {0x3Eu, 0x03u}, + {0x3Fu, 0x18u}, + {0x40u, 0x08u}, {0x43u, 0x10u}, - {0x58u, 0x10u}, - {0x5Au, 0x80u}, - {0x5Cu, 0x41u}, - {0x5Du, 0x18u}, - {0x61u, 0x20u}, - {0x62u, 0x10u}, - {0x63u, 0x01u}, - {0x67u, 0x02u}, - {0x82u, 0x41u}, - {0x83u, 0x20u}, - {0x84u, 0x10u}, - {0x86u, 0x06u}, - {0x87u, 0x14u}, - {0x88u, 0x10u}, - {0x8Au, 0x80u}, - {0x8Du, 0x40u}, - {0x8Eu, 0x04u}, - {0x8Fu, 0x01u}, - {0xC0u, 0xFCu}, - {0xC2u, 0xFDu}, - {0xC4u, 0xF7u}, - {0xCAu, 0xEDu}, - {0xCCu, 0xE7u}, - {0xCEu, 0xB7u}, - {0xD6u, 0xFCu}, - {0xD8u, 0x1Cu}, - {0xE2u, 0x80u}, - {0xE4u, 0x10u}, - {0xE6u, 0x01u}, - {0x01u, 0x88u}, - {0x03u, 0x03u}, + {0x4Au, 0x08u}, + {0x4Bu, 0x10u}, + {0x59u, 0x40u}, + {0x5Au, 0x20u}, + {0x5Cu, 0x40u}, + {0x5Eu, 0x10u}, + {0x62u, 0x40u}, + {0x63u, 0x08u}, + {0x66u, 0x80u}, + {0x67u, 0x08u}, + {0x80u, 0x40u}, + {0x82u, 0x50u}, + {0x88u, 0x20u}, + {0x89u, 0x80u}, + {0x8Au, 0x40u}, + {0x8Du, 0x04u}, + {0x8Eu, 0x31u}, + {0x8Fu, 0x10u}, + {0x91u, 0x61u}, + {0x92u, 0x08u}, + {0x93u, 0x80u}, + {0x94u, 0x20u}, + {0x96u, 0x84u}, + {0x97u, 0x08u}, + {0x98u, 0x06u}, + {0x99u, 0x02u}, + {0x9Au, 0x02u}, + {0x9Bu, 0x0Cu}, + {0x9Du, 0x08u}, + {0x9Eu, 0xC5u}, + {0x9Fu, 0x01u}, + {0xA0u, 0x89u}, + {0xA1u, 0x80u}, + {0xA4u, 0x70u}, + {0xA5u, 0x04u}, + {0xA6u, 0x02u}, + {0xAAu, 0x24u}, + {0xACu, 0x80u}, + {0xADu, 0x08u}, + {0xB1u, 0x10u}, + {0xB2u, 0x40u}, + {0xB4u, 0x12u}, + {0xB5u, 0x40u}, + {0xB7u, 0x40u}, + {0xC0u, 0x7Du}, + {0xC2u, 0xAFu}, + {0xC4u, 0xF3u}, + {0xCAu, 0xFEu}, + {0xCCu, 0xEBu}, + {0xCEu, 0xEDu}, + {0xD6u, 0x3Cu}, + {0xD8u, 0x3Cu}, + {0xE0u, 0xB0u}, + {0xE2u, 0x01u}, + {0xE6u, 0x40u}, + {0xE8u, 0x40u}, + {0xEAu, 0xA0u}, + {0xECu, 0x20u}, + {0xEEu, 0x40u}, + {0x01u, 0x20u}, + {0x03u, 0x10u}, + {0x04u, 0x02u}, + {0x08u, 0x02u}, {0x09u, 0x04u}, - {0x0Bu, 0x43u}, - {0x11u, 0xE0u}, - {0x17u, 0xECu}, - {0x19u, 0x21u}, - {0x1Bu, 0x02u}, - {0x1Fu, 0x01u}, - {0x23u, 0x12u}, - {0x33u, 0x0Fu}, - {0x35u, 0xE0u}, - {0x37u, 0x10u}, - {0x3Fu, 0x10u}, - {0x40u, 0x34u}, - {0x41u, 0x06u}, - {0x42u, 0x10u}, - {0x44u, 0x05u}, - {0x45u, 0xBEu}, - {0x46u, 0xFCu}, - {0x47u, 0x0Du}, - {0x48u, 0x1Fu}, - {0x49u, 0xFFu}, - {0x4Au, 0xFFu}, - {0x4Bu, 0xFFu}, - {0x4Cu, 0x22u}, - {0x4Eu, 0xF0u}, - {0x4Fu, 0x08u}, - {0x50u, 0x04u}, + {0x0Bu, 0x02u}, + {0x0Cu, 0x02u}, + {0x0Fu, 0x18u}, + {0x11u, 0x20u}, + {0x12u, 0x01u}, + {0x13u, 0x08u}, + {0x17u, 0x20u}, + {0x18u, 0x02u}, + {0x19u, 0x02u}, + {0x1Bu, 0x04u}, + {0x1Du, 0x04u}, + {0x1Fu, 0x02u}, + {0x23u, 0x20u}, + {0x29u, 0x04u}, + {0x2Bu, 0x02u}, + {0x2Du, 0x04u}, + {0x2Fu, 0x03u}, + {0x32u, 0x02u}, + {0x33u, 0x01u}, + {0x34u, 0x01u}, + {0x35u, 0x06u}, + {0x37u, 0x38u}, + {0x3Bu, 0x20u}, + {0x3Eu, 0x04u}, + {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Au, 0x04u}, - {0x5Cu, 0x10u}, - {0x5Du, 0x01u}, + {0x5Cu, 0x22u}, {0x5Fu, 0x01u}, - {0x62u, 0xC0u}, - {0x64u, 0x40u}, - {0x65u, 0x01u}, - {0x66u, 0x10u}, - {0x67u, 0x11u}, - {0x68u, 0xC0u}, - {0x69u, 0x01u}, - {0x6Bu, 0x11u}, - {0x6Cu, 0x40u}, - {0x6Du, 0x01u}, - {0x6Eu, 0x40u}, - {0x6Fu, 0x01u}, - {0x80u, 0xC0u}, - {0x84u, 0x24u}, - {0x85u, 0x40u}, - {0x86u, 0x10u}, - {0x87u, 0x30u}, - {0x88u, 0x11u}, - {0x89u, 0x32u}, - {0x8Au, 0x62u}, - {0x8Bu, 0x44u}, - {0x8Cu, 0x1Cu}, - {0x8Du, 0x0Du}, - {0x8Fu, 0x80u}, - {0x90u, 0x70u}, - {0x91u, 0x8Du}, - {0x92u, 0x0Fu}, - {0x94u, 0x21u}, - {0x95u, 0x8Du}, - {0x96u, 0x9Eu}, - {0x98u, 0x14u}, - {0x99u, 0x02u}, - {0x9Au, 0x08u}, - {0x9Bu, 0x0Du}, - {0x9Cu, 0x1Cu}, - {0xA0u, 0x08u}, - {0xA1u, 0x8Du}, - {0xA5u, 0x11u}, - {0xA7u, 0x62u}, - {0xA8u, 0x10u}, - {0xA9u, 0x8Du}, - {0xAAu, 0x0Cu}, - {0xACu, 0x0Cu}, - {0xADu, 0x52u}, - {0xAEu, 0x10u}, - {0xAFu, 0x28u}, - {0xB0u, 0xC1u}, - {0xB2u, 0x30u}, - {0xB3u, 0x70u}, - {0xB4u, 0x0Fu}, - {0xB5u, 0x0Fu}, - {0xB7u, 0x80u}, - {0xB8u, 0x02u}, - {0xBAu, 0x08u}, - {0xBBu, 0x28u}, - {0xBFu, 0x40u}, - {0xD6u, 0x02u}, - {0xD7u, 0x28u}, + {0x80u, 0x40u}, + {0x82u, 0x80u}, + {0x84u, 0x40u}, + {0x86u, 0x80u}, + {0x87u, 0x3Fu}, + {0x88u, 0x06u}, + {0x89u, 0x10u}, + {0x8Bu, 0x20u}, + {0x8Eu, 0x10u}, + {0x8Fu, 0x3Fu}, + {0x90u, 0x0Bu}, + {0x91u, 0x3Fu}, + {0x92u, 0xF4u}, + {0x95u, 0x01u}, + {0x97u, 0x02u}, + {0x98u, 0x01u}, + {0x99u, 0x01u}, + {0x9Bu, 0x02u}, + {0x9Cu, 0xCAu}, + {0x9Du, 0x04u}, + {0x9Eu, 0x15u}, + {0x9Fu, 0x08u}, + {0xA0u, 0xE0u}, + {0xA1u, 0x3Fu}, + {0xA7u, 0x3Fu}, + {0xA9u, 0x10u}, + {0xAAu, 0xFFu}, + {0xABu, 0x20u}, + {0xACu, 0x11u}, + {0xADu, 0x04u}, + {0xAEu, 0xECu}, + {0xAFu, 0x08u}, + {0xB3u, 0x03u}, + {0xB4u, 0xC0u}, + {0xB5u, 0x30u}, + {0xB6u, 0x3Fu}, + {0xB7u, 0x0Cu}, + {0xBAu, 0x20u}, + {0xBBu, 0xA8u}, + {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x11u}, - {0xDDu, 0x10u}, + {0xDCu, 0x22u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x05u, 0x15u}, - {0x06u, 0x02u}, - {0x0Eu, 0x5Au}, - {0x15u, 0x50u}, - {0x16u, 0x40u}, - {0x1Du, 0x15u}, - {0x1Fu, 0x20u}, - {0x21u, 0x88u}, + {0x00u, 0xA0u}, + {0x01u, 0x08u}, + {0x04u, 0x04u}, + {0x05u, 0x20u}, + {0x06u, 0x42u}, + {0x07u, 0x04u}, + {0x0Au, 0x84u}, + {0x0Cu, 0x20u}, + {0x0Du, 0x80u}, + {0x0Fu, 0x80u}, + {0x16u, 0x0Du}, + {0x17u, 0x01u}, + {0x19u, 0x10u}, + {0x1Au, 0x20u}, + {0x1Cu, 0x04u}, + {0x1Du, 0x80u}, + {0x1Fu, 0x50u}, + {0x20u, 0x12u}, + {0x21u, 0x60u}, + {0x22u, 0x04u}, {0x23u, 0x08u}, - {0x24u, 0x01u}, - {0x26u, 0x20u}, + {0x25u, 0x10u}, + {0x26u, 0x64u}, {0x27u, 0x10u}, - {0x29u, 0x02u}, - {0x2Du, 0x10u}, - {0x2Eu, 0x42u}, - {0x2Fu, 0x20u}, - {0x31u, 0x99u}, - {0x36u, 0x25u}, + {0x29u, 0x10u}, + {0x2Au, 0x81u}, + {0x2Cu, 0x01u}, + {0x2Eu, 0x08u}, + {0x2Fu, 0x44u}, + {0x30u, 0x02u}, + {0x31u, 0x28u}, + {0x32u, 0x40u}, + {0x34u, 0x04u}, + {0x36u, 0x40u}, + {0x37u, 0x11u}, {0x38u, 0x10u}, - {0x39u, 0x02u}, - {0x3Du, 0x40u}, - {0x3Eu, 0x18u}, - {0x40u, 0x13u}, - {0x41u, 0x01u}, - {0x42u, 0x50u}, - {0x46u, 0x08u}, - {0x47u, 0x10u}, - {0x48u, 0x01u}, - {0x49u, 0x12u}, - {0x4Bu, 0x04u}, + {0x39u, 0x81u}, + {0x3Du, 0x28u}, + {0x3Fu, 0x80u}, + {0x5Cu, 0x40u}, + {0x5Fu, 0x20u}, + {0x64u, 0x07u}, + {0x7Du, 0x01u}, + {0x7Fu, 0x40u}, + {0x81u, 0x20u}, + {0x82u, 0x10u}, + {0x83u, 0x20u}, + {0x84u, 0x08u}, + {0x86u, 0x02u}, + {0x87u, 0x50u}, + {0x89u, 0x02u}, + {0x8Cu, 0x40u}, + {0x8Eu, 0x02u}, + {0xC0u, 0xF7u}, + {0xC2u, 0xDAu}, + {0xC4u, 0xD0u}, + {0xCAu, 0xFDu}, + {0xCCu, 0xFFu}, + {0xCEu, 0x7Du}, + {0xD6u, 0x30u}, + {0xD8u, 0x30u}, + {0xE0u, 0x80u}, + {0xE2u, 0x01u}, + {0xE4u, 0x04u}, + {0xE6u, 0x10u}, + {0x89u, 0x07u}, + {0x97u, 0x07u}, + {0x98u, 0x01u}, + {0x99u, 0x01u}, + {0x9Bu, 0x18u}, + {0x9Fu, 0x08u}, + {0xABu, 0x2Au}, + {0xADu, 0x34u}, + {0xB0u, 0x01u}, + {0xB5u, 0x07u}, + {0xB7u, 0x38u}, + {0xBEu, 0x01u}, + {0xBFu, 0x10u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDCu, 0x10u}, + {0xDFu, 0x01u}, + {0x01u, 0xA0u}, + {0x03u, 0x50u}, + {0x0Au, 0x41u}, + {0x0Bu, 0x14u}, + {0x0Cu, 0x03u}, + {0x0Fu, 0x08u}, + {0x11u, 0x40u}, + {0x12u, 0x60u}, + {0x13u, 0x20u}, + {0x19u, 0x80u}, + {0x1Bu, 0x01u}, + {0x1Fu, 0x02u}, + {0x23u, 0x10u}, + {0x26u, 0x40u}, + {0x27u, 0x08u}, + {0x29u, 0x24u}, + {0x2Au, 0x42u}, + {0x2Bu, 0x01u}, + {0x2Du, 0x20u}, + {0x2Eu, 0x40u}, + {0x31u, 0x08u}, + {0x33u, 0x51u}, + {0x36u, 0x48u}, + {0x37u, 0x20u}, + {0x38u, 0x88u}, + {0x39u, 0x10u}, + {0x3Bu, 0x04u}, + {0x3Cu, 0x20u}, + {0x41u, 0x08u}, + {0x42u, 0x44u}, + {0x49u, 0x64u}, + {0x4Au, 0xA0u}, + {0x4Bu, 0x02u}, {0x51u, 0x04u}, - {0x52u, 0x50u}, - {0x66u, 0x08u}, - {0x6Du, 0x50u}, - {0x6Eu, 0x0Eu}, - {0x76u, 0x02u}, - {0x84u, 0x01u}, - {0x87u, 0x08u}, - {0x89u, 0x40u}, - {0x92u, 0x50u}, - {0x95u, 0x58u}, - {0x96u, 0x04u}, - {0x97u, 0x04u}, - {0x9Cu, 0x02u}, - {0x9Du, 0x16u}, - {0x9Eu, 0x52u}, - {0xA1u, 0x40u}, - {0xA6u, 0x01u}, - {0xA7u, 0x20u}, - {0xABu, 0x20u}, + {0x52u, 0x12u}, + {0x61u, 0x10u}, + {0x68u, 0x62u}, + {0x69u, 0x02u}, + {0x6Au, 0x20u}, + {0x6Bu, 0x04u}, + {0x71u, 0x80u}, + {0x79u, 0x02u}, + {0x7Bu, 0x40u}, + {0x83u, 0x0Cu}, + {0x86u, 0x44u}, + {0x8Au, 0xAAu}, + {0x8Fu, 0x02u}, + {0x90u, 0x88u}, + {0x91u, 0x50u}, + {0x92u, 0x41u}, + {0x95u, 0x0Au}, + {0x96u, 0x20u}, + {0x97u, 0x02u}, + {0x99u, 0x70u}, + {0x9Au, 0x02u}, + {0x9Bu, 0x71u}, + {0x9Cu, 0x01u}, + {0x9Eu, 0x10u}, + {0x9Fu, 0x04u}, + {0xA0u, 0x10u}, + {0xA1u, 0x08u}, + {0xA4u, 0x62u}, + {0xA5u, 0x80u}, + {0xA7u, 0x40u}, + {0xACu, 0x20u}, {0xADu, 0x84u}, - {0xB4u, 0x10u}, - {0xB5u, 0x01u}, - {0xC0u, 0xF0u}, - {0xC2u, 0xF0u}, - {0xC4u, 0xD0u}, - {0xCAu, 0xF1u}, - {0xCCu, 0xEFu}, - {0xCEu, 0x75u}, - {0xD0u, 0x0Bu}, + {0xB3u, 0x44u}, + {0xB6u, 0x20u}, + {0xC0u, 0x0Fu}, + {0xC2u, 0x4Fu}, + {0xC4u, 0x0Fu}, + {0xCAu, 0x3Fu}, + {0xCCu, 0x7Fu}, + {0xCEu, 0x2Eu}, + {0xD0u, 0x07u}, {0xD2u, 0x0Cu}, - {0xD8u, 0x40u}, - {0xE6u, 0x20u}, - {0xEEu, 0x40u}, - {0x04u, 0x42u}, - {0x08u, 0x77u}, - {0x0Au, 0x08u}, - {0x0Bu, 0x05u}, - {0x0Cu, 0xC6u}, - {0x10u, 0x01u}, - {0x12u, 0x5Eu}, - {0x14u, 0x39u}, - {0x15u, 0x08u}, - {0x16u, 0x06u}, - {0x18u, 0xC2u}, - {0x1Au, 0x04u}, - {0x1Bu, 0x01u}, - {0x1Cu, 0xC6u}, - {0x20u, 0x04u}, - {0x22u, 0x20u}, - {0x26u, 0x80u}, - {0x27u, 0x03u}, - {0x28u, 0x80u}, - {0x29u, 0x08u}, - {0x2Au, 0x46u}, - {0x2Cu, 0x46u}, - {0x2Du, 0x06u}, - {0x2Eu, 0x80u}, - {0x30u, 0x70u}, + {0xD8u, 0x04u}, + {0xE6u, 0x44u}, + {0xEAu, 0x10u}, + {0xECu, 0x08u}, + {0x00u, 0x1Du}, + {0x04u, 0x1Du}, + {0x08u, 0x02u}, + {0x0Au, 0x04u}, + {0x10u, 0x02u}, + {0x12u, 0x08u}, + {0x14u, 0x02u}, + {0x15u, 0x02u}, + {0x16u, 0x0Du}, + {0x18u, 0x01u}, + {0x1Au, 0x02u}, + {0x20u, 0x0Du}, + {0x22u, 0x10u}, + {0x26u, 0x10u}, + {0x28u, 0x1Du}, + {0x29u, 0x01u}, + {0x2Cu, 0x1Du}, + {0x31u, 0x02u}, {0x32u, 0x0Fu}, - {0x33u, 0x07u}, - {0x34u, 0x80u}, - {0x37u, 0x08u}, - {0x38u, 0x08u}, - {0x39u, 0x80u}, - {0x3Au, 0x03u}, + {0x34u, 0x10u}, + {0x35u, 0x01u}, + {0x3Au, 0x08u}, {0x3Eu, 0x10u}, {0x54u, 0x40u}, {0x56u, 0x04u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, + {0x5Cu, 0x91u}, {0x5Du, 0x10u}, {0x5Fu, 0x01u}, - {0x81u, 0x04u}, - {0x86u, 0xECu}, - {0x89u, 0x86u}, - {0x8Au, 0x01u}, - {0x8Du, 0x02u}, - {0x91u, 0x06u}, - {0x92u, 0x12u}, - {0x93u, 0x80u}, - {0x94u, 0x88u}, - {0x95u, 0x61u}, - {0x96u, 0x03u}, - {0x97u, 0x0Eu}, - {0x9Bu, 0x10u}, - {0x9Cu, 0x21u}, - {0x9Du, 0x07u}, - {0x9Eu, 0x02u}, - {0x9Fu, 0x38u}, - {0xA0u, 0xE0u}, - {0xA1u, 0x86u}, - {0xA5u, 0x82u}, - {0xA7u, 0x04u}, - {0xA8u, 0x04u}, - {0xA9u, 0x09u}, - {0xAAu, 0x43u}, - {0xABu, 0x56u}, - {0xADu, 0x80u}, - {0xAFu, 0x06u}, - {0xB0u, 0xE0u}, - {0xB1u, 0x08u}, - {0xB2u, 0x0Fu}, - {0xB3u, 0x0Fu}, - {0xB4u, 0x10u}, + {0x80u, 0x11u}, + {0x81u, 0xC6u}, + {0x82u, 0x62u}, + {0x84u, 0x52u}, + {0x85u, 0x01u}, + {0x86u, 0x28u}, + {0x87u, 0x5Eu}, + {0x8Cu, 0x02u}, + {0x8Du, 0x39u}, + {0x8Eu, 0x0Du}, + {0x8Fu, 0x06u}, + {0x90u, 0x0Du}, + {0x91u, 0x77u}, + {0x93u, 0x08u}, + {0x94u, 0x0Du}, + {0x95u, 0x80u}, + {0x97u, 0x46u}, + {0x98u, 0x40u}, + {0x99u, 0xC2u}, + {0x9Au, 0x30u}, + {0x9Bu, 0x04u}, + {0x9Cu, 0x0Du}, + {0x9Du, 0xC6u}, + {0xA0u, 0x0Du}, + {0xA3u, 0x80u}, + {0xA4u, 0x0Du}, + {0xA5u, 0x04u}, + {0xA7u, 0x20u}, + {0xA9u, 0x42u}, + {0xACu, 0x32u}, + {0xADu, 0x46u}, + {0xAEu, 0x44u}, + {0xAFu, 0x80u}, + {0xB0u, 0x0Fu}, + {0xB1u, 0x0Fu}, + {0xB3u, 0x80u}, + {0xB4u, 0x70u}, {0xB5u, 0x70u}, - {0xB7u, 0x80u}, - {0xB9u, 0x08u}, - {0xBEu, 0x01u}, - {0xBFu, 0x41u}, + {0xB7u, 0x01u}, + {0xB9u, 0x02u}, + {0xBAu, 0x22u}, + {0xBBu, 0x30u}, + {0xBFu, 0x44u}, + {0xD4u, 0x40u}, + {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, + {0xDBu, 0x04u}, {0xDFu, 0x01u}, - {0x01u, 0x28u}, - {0x05u, 0x14u}, - {0x06u, 0x02u}, - {0x09u, 0x88u}, - {0x0Bu, 0x80u}, - {0x0Eu, 0x56u}, - {0x10u, 0x04u}, - {0x11u, 0x02u}, - {0x12u, 0x08u}, - {0x15u, 0x58u}, - {0x16u, 0x40u}, - {0x19u, 0x29u}, - {0x1Cu, 0x80u}, - {0x1Eu, 0x50u}, + {0x00u, 0x44u}, + {0x02u, 0x40u}, + {0x05u, 0x20u}, + {0x07u, 0x50u}, + {0x08u, 0x01u}, + {0x09u, 0x80u}, + {0x0Au, 0x28u}, + {0x0Cu, 0x10u}, + {0x0Eu, 0x60u}, + {0x10u, 0x20u}, + {0x11u, 0x01u}, + {0x13u, 0x40u}, + {0x15u, 0x18u}, + {0x16u, 0x02u}, + {0x17u, 0x01u}, + {0x18u, 0x40u}, + {0x19u, 0x10u}, + {0x1Au, 0x08u}, + {0x1Eu, 0x20u}, {0x1Fu, 0x10u}, - {0x20u, 0x11u}, - {0x22u, 0x18u}, - {0x23u, 0x82u}, - {0x26u, 0x80u}, - {0x27u, 0x20u}, - {0x28u, 0xA4u}, - {0x2Au, 0x80u}, - {0x2Eu, 0x40u}, - {0x2Fu, 0x24u}, - {0x30u, 0x02u}, - {0x31u, 0x88u}, - {0x32u, 0x10u}, - {0x37u, 0x28u}, - {0x38u, 0x60u}, - {0x3Bu, 0x02u}, - {0x3Eu, 0x10u}, - {0x64u, 0x40u}, - {0x65u, 0x80u}, + {0x20u, 0x04u}, + {0x22u, 0x88u}, + {0x23u, 0x44u}, + {0x26u, 0x21u}, + {0x28u, 0x01u}, + {0x2Au, 0x04u}, + {0x2Bu, 0x84u}, + {0x2Fu, 0x04u}, + {0x30u, 0x20u}, + {0x31u, 0x80u}, + {0x33u, 0x06u}, + {0x37u, 0x08u}, + {0x38u, 0x04u}, + {0x39u, 0x03u}, + {0x3Bu, 0x40u}, + {0x40u, 0x02u}, + {0x43u, 0x80u}, + {0x44u, 0x10u}, + {0x45u, 0x08u}, + {0x60u, 0x02u}, + {0x61u, 0x20u}, + {0x62u, 0x0Au}, + {0x65u, 0x81u}, {0x66u, 0x10u}, {0x67u, 0x20u}, - {0x6Du, 0x80u}, - {0x6Eu, 0x20u}, - {0x84u, 0x40u}, - {0x8Au, 0x10u}, - {0x8Du, 0x01u}, + {0x81u, 0x03u}, + {0x82u, 0x01u}, + {0x86u, 0x02u}, + {0x90u, 0x88u}, + {0x91u, 0x50u}, + {0x92u, 0x41u}, + {0x93u, 0x08u}, + {0x94u, 0x04u}, + {0x95u, 0x02u}, + {0x97u, 0x46u}, + {0x98u, 0x20u}, + {0x99u, 0x62u}, + {0x9Au, 0x46u}, + {0x9Bu, 0x79u}, + {0x9Fu, 0x04u}, + {0xA0u, 0x10u}, + {0xA1u, 0x28u}, + {0xA3u, 0x86u}, + {0xA4u, 0x62u}, + {0xA5u, 0x80u}, + {0xA6u, 0x80u}, + {0xA7u, 0x40u}, + {0xB1u, 0xA0u}, + {0xB3u, 0x04u}, + {0xB4u, 0x40u}, + {0xB7u, 0x08u}, + {0xC0u, 0x7Du}, + {0xC2u, 0x7Fu}, + {0xC4u, 0xFDu}, + {0xCAu, 0x2Fu}, + {0xCCu, 0x4Fu}, + {0xCEu, 0x0Bu}, + {0xD8u, 0xFFu}, + {0xE2u, 0x01u}, + {0xE4u, 0x04u}, + {0xE6u, 0x32u}, + {0xEAu, 0x08u}, + {0xECu, 0x80u}, + {0xEEu, 0x02u}, + {0x01u, 0x96u}, + {0x03u, 0x69u}, + {0x05u, 0x33u}, + {0x06u, 0x0Cu}, + {0x07u, 0xCCu}, + {0x08u, 0x04u}, + {0x0Au, 0xA3u}, + {0x0Bu, 0xFFu}, + {0x0Du, 0xFFu}, + {0x16u, 0x20u}, + {0x17u, 0xFFu}, + {0x1Au, 0x12u}, + {0x1Bu, 0xFFu}, + {0x1Du, 0x0Fu}, + {0x1Eu, 0x01u}, + {0x1Fu, 0xF0u}, + {0x21u, 0xFFu}, + {0x28u, 0xC8u}, + {0x29u, 0x55u}, + {0x2Au, 0x03u}, + {0x2Bu, 0xAAu}, + {0x2Cu, 0x01u}, + {0x2Eu, 0x62u}, + {0x31u, 0xFFu}, + {0x32u, 0xE0u}, + {0x34u, 0x0Fu}, + {0x36u, 0x10u}, + {0x3Bu, 0x02u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Cu, 0x20u}, + {0x5Fu, 0x01u}, + {0x84u, 0x80u}, + {0x85u, 0x44u}, + {0x87u, 0x88u}, + {0x89u, 0x48u}, + {0x8Bu, 0x84u}, + {0x8Cu, 0x4Du}, + {0x8Du, 0x33u}, + {0x8Eu, 0xB2u}, + {0x8Fu, 0xCCu}, + {0x91u, 0x12u}, + {0x93u, 0x21u}, + {0x98u, 0x40u}, + {0x99u, 0x11u}, + {0x9Bu, 0x22u}, + {0x9Cu, 0x20u}, + {0x9Du, 0xFFu}, + {0x9Eu, 0x10u}, + {0xA0u, 0x12u}, + {0xA1u, 0x0Fu}, + {0xA2u, 0x20u}, + {0xA3u, 0xF0u}, + {0xA4u, 0x05u}, + {0xA6u, 0x08u}, + {0xA7u, 0xFFu}, + {0xA8u, 0x08u}, + {0xAAu, 0x04u}, + {0xADu, 0xFFu}, + {0xB0u, 0x3Cu}, + {0xB2u, 0xC0u}, + {0xB3u, 0xFFu}, + {0xB4u, 0x03u}, + {0xB9u, 0x02u}, + {0xBEu, 0x15u}, + {0xBFu, 0x05u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x01u, 0x44u}, + {0x03u, 0x02u}, + {0x04u, 0x04u}, + {0x05u, 0x20u}, + {0x08u, 0x20u}, + {0x0Au, 0x01u}, + {0x0Du, 0x80u}, + {0x0Eu, 0x18u}, + {0x12u, 0x10u}, + {0x13u, 0x21u}, + {0x15u, 0x20u}, + {0x16u, 0x02u}, + {0x18u, 0x08u}, + {0x1Au, 0x80u}, + {0x1Bu, 0x08u}, + {0x1Cu, 0x04u}, + {0x1Du, 0x90u}, + {0x1Eu, 0x10u}, + {0x20u, 0x20u}, + {0x22u, 0x02u}, + {0x24u, 0x80u}, + {0x27u, 0x80u}, + {0x29u, 0x80u}, + {0x2Bu, 0xA0u}, + {0x2Du, 0x01u}, + {0x2Fu, 0x04u}, + {0x32u, 0x51u}, + {0x34u, 0x08u}, + {0x37u, 0x90u}, + {0x39u, 0x54u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x20u}, + {0x3Fu, 0x0Au}, + {0x48u, 0x04u}, + {0x4Au, 0x08u}, + {0x58u, 0x80u}, + {0x63u, 0x02u}, + {0x69u, 0x14u}, + {0x6Au, 0x01u}, + {0x6Bu, 0x01u}, + {0x73u, 0x55u}, + {0x80u, 0x20u}, + {0x81u, 0x87u}, + {0x82u, 0x50u}, + {0x87u, 0x10u}, + {0x8Au, 0x02u}, {0x8Eu, 0x10u}, - {0x90u, 0x60u}, - {0x93u, 0x8Au}, - {0x94u, 0x11u}, - {0x95u, 0x50u}, - {0x96u, 0x54u}, - {0x97u, 0x04u}, - {0x98u, 0xA0u}, - {0x9Au, 0x80u}, - {0x9Bu, 0x08u}, - {0x9Cu, 0x02u}, - {0x9Du, 0x16u}, - {0x9Eu, 0x42u}, - {0x9Fu, 0x82u}, + {0x91u, 0x81u}, + {0x92u, 0x02u}, + {0x93u, 0x28u}, + {0x94u, 0x88u}, + {0x95u, 0x14u}, + {0x97u, 0xD4u}, + {0x98u, 0x98u}, + {0x99u, 0x02u}, + {0x9Au, 0x32u}, + {0x9Bu, 0x14u}, + {0x9Du, 0x38u}, + {0x9Eu, 0x80u}, {0xA0u, 0x02u}, - {0xA1u, 0x88u}, - {0xA4u, 0x40u}, - {0xA6u, 0x89u}, - {0xA7u, 0x20u}, - {0xA8u, 0x80u}, - {0xA9u, 0x08u}, - {0xAAu, 0x04u}, - {0xABu, 0x10u}, - {0xAEu, 0x40u}, - {0xAFu, 0x10u}, - {0xC0u, 0xE6u}, - {0xC2u, 0xFDu}, - {0xC4u, 0xFAu}, - {0xCAu, 0x7Fu}, - {0xCCu, 0x6Fu}, - {0xCEu, 0x2Du}, - {0xD8u, 0xF0u}, - {0xE2u, 0xD0u}, - {0xE8u, 0x01u}, - {0xEAu, 0x10u}, - {0xEEu, 0x08u}, - {0x00u, 0x0Du}, - {0x01u, 0x11u}, - {0x02u, 0x10u}, - {0x03u, 0x22u}, - {0x04u, 0x02u}, + {0xA1u, 0x40u}, + {0xA2u, 0x0Cu}, + {0xA3u, 0xE6u}, + {0xA4u, 0x50u}, + {0xA5u, 0x01u}, + {0xA9u, 0x80u}, + {0xABu, 0x08u}, + {0xAFu, 0x40u}, + {0xB0u, 0x18u}, + {0xB4u, 0x04u}, + {0xB7u, 0x04u}, + {0xC0u, 0x65u}, + {0xC2u, 0xE3u}, + {0xC4u, 0xCEu}, + {0xCAu, 0xABu}, + {0xCCu, 0x7Du}, + {0xCEu, 0xFEu}, + {0xD6u, 0x08u}, + {0xD8u, 0x08u}, + {0xE0u, 0x04u}, + {0xE6u, 0x30u}, + {0xE8u, 0xA0u}, + {0xECu, 0x50u}, + {0xEEu, 0x02u}, + {0x00u, 0x0Fu}, + {0x02u, 0xF0u}, {0x05u, 0x44u}, - {0x06u, 0x0Du}, + {0x06u, 0xFFu}, {0x07u, 0x88u}, - {0x08u, 0x1Du}, - {0x09u, 0x48u}, - {0x0Bu, 0x84u}, - {0x0Cu, 0x1Du}, - {0x0Du, 0x33u}, - {0x0Fu, 0xCCu}, - {0x10u, 0x42u}, - {0x11u, 0x0Fu}, - {0x12u, 0x28u}, - {0x13u, 0xF0u}, - {0x14u, 0x22u}, - {0x16u, 0x84u}, - {0x18u, 0x1Du}, + {0x09u, 0x84u}, + {0x0Bu, 0x48u}, + {0x0Cu, 0x33u}, + {0x0Eu, 0xCCu}, + {0x11u, 0x21u}, + {0x12u, 0xFFu}, + {0x13u, 0x12u}, + {0x16u, 0xFFu}, + {0x17u, 0xFFu}, + {0x18u, 0x11u}, + {0x1Au, 0x22u}, {0x1Bu, 0xFFu}, - {0x1Cu, 0xC0u}, - {0x20u, 0x21u}, - {0x22u, 0x42u}, - {0x27u, 0xFFu}, - {0x29u, 0x12u}, - {0x2Au, 0x10u}, - {0x2Bu, 0x21u}, - {0x2Cu, 0x1Du}, - {0x2Fu, 0xFFu}, - {0x32u, 0x10u}, - {0x34u, 0x0Fu}, - {0x35u, 0xFFu}, - {0x36u, 0xE0u}, - {0x38u, 0x80u}, - {0x3Au, 0x20u}, + {0x1Cu, 0x12u}, + {0x1Du, 0xFFu}, + {0x1Eu, 0x21u}, + {0x21u, 0x0Fu}, + {0x23u, 0xF0u}, + {0x24u, 0x44u}, + {0x25u, 0x11u}, + {0x26u, 0x88u}, + {0x27u, 0x22u}, + {0x28u, 0x48u}, + {0x2Au, 0x84u}, + {0x2Du, 0x33u}, + {0x2Fu, 0xCCu}, + {0x31u, 0xFFu}, + {0x32u, 0xFFu}, {0x3Eu, 0x04u}, - {0x3Fu, 0x10u}, - {0x54u, 0x40u}, + {0x3Fu, 0x01u}, {0x58u, 0x04u}, {0x59u, 0x04u}, - {0x5Bu, 0x04u}, {0x5Fu, 0x01u}, - {0x80u, 0x0Fu}, - {0x82u, 0xF0u}, - {0x84u, 0x84u}, - {0x85u, 0x20u}, - {0x86u, 0x48u}, - {0x88u, 0x21u}, - {0x89u, 0x10u}, - {0x8Au, 0x12u}, - {0x8Du, 0x80u}, - {0x90u, 0x11u}, - {0x91u, 0x08u}, - {0x92u, 0x22u}, - {0x93u, 0x04u}, - {0x95u, 0x40u}, - {0x96u, 0xFFu}, - {0x99u, 0x01u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0x33u}, - {0x9Du, 0x04u}, - {0x9Eu, 0xCCu}, - {0x9Fu, 0x08u}, - {0xA1u, 0x53u}, - {0xA3u, 0xACu}, - {0xA4u, 0x44u}, - {0xA6u, 0x88u}, - {0xA9u, 0x02u}, - {0xAAu, 0xFFu}, - {0xABu, 0x01u}, - {0xACu, 0xFFu}, - {0xB0u, 0xFFu}, - {0xB1u, 0xC0u}, - {0xB3u, 0x0Fu}, - {0xB7u, 0x30u}, - {0xBEu, 0x01u}, + {0x81u, 0x10u}, + {0x85u, 0x04u}, + {0x87u, 0x01u}, + {0x88u, 0x18u}, + {0x8Au, 0x23u}, + {0x8Bu, 0x04u}, + {0x8Fu, 0x04u}, + {0x91u, 0x40u}, + {0x95u, 0x28u}, + {0x96u, 0x0Cu}, + {0x97u, 0x50u}, + {0x99u, 0x08u}, + {0x9Au, 0x01u}, + {0x9Bu, 0x03u}, + {0x9Cu, 0x11u}, + {0x9Du, 0x20u}, + {0x9Eu, 0x22u}, + {0xA1u, 0x04u}, + {0xA2u, 0x42u}, + {0xA3u, 0x02u}, + {0xA4u, 0x34u}, + {0xA6u, 0x03u}, + {0xADu, 0x80u}, + {0xB0u, 0x20u}, + {0xB1u, 0x80u}, + {0xB2u, 0x0Fu}, + {0xB3u, 0x60u}, + {0xB4u, 0x40u}, + {0xB5u, 0x07u}, + {0xB6u, 0x10u}, + {0xB7u, 0x18u}, + {0xBEu, 0x41u}, {0xBFu, 0x45u}, - {0xD6u, 0x08u}, + {0xD4u, 0x09u}, + {0xD6u, 0x04u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDDu, 0x90u}, + {0xDCu, 0x21u}, + {0xDDu, 0x10u}, {0xDFu, 0x01u}, - {0x00u, 0x08u}, - {0x01u, 0x02u}, - {0x03u, 0x08u}, - {0x04u, 0x06u}, - {0x06u, 0x01u}, + {0x03u, 0xA2u}, {0x07u, 0x04u}, - {0x09u, 0x41u}, - {0x0Bu, 0x20u}, - {0x0Du, 0x02u}, - {0x0Eu, 0x06u}, - {0x0Fu, 0x20u}, - {0x10u, 0x02u}, - {0x11u, 0x04u}, - {0x13u, 0x20u}, - {0x14u, 0x80u}, - {0x15u, 0x20u}, - {0x17u, 0x40u}, - {0x18u, 0x40u}, - {0x1Cu, 0x04u}, - {0x1Du, 0x04u}, - {0x1Eu, 0x02u}, - {0x20u, 0x02u}, - {0x23u, 0xA0u}, - {0x27u, 0x08u}, - {0x28u, 0x04u}, - {0x2Bu, 0x40u}, + {0x08u, 0x20u}, + {0x09u, 0x04u}, + {0x0Au, 0x82u}, + {0x0Du, 0x40u}, + {0x0Eu, 0x18u}, + {0x11u, 0x14u}, + {0x14u, 0x10u}, + {0x15u, 0x02u}, + {0x19u, 0x08u}, + {0x1Cu, 0x20u}, + {0x1Du, 0x40u}, + {0x1Eu, 0x58u}, + {0x20u, 0x80u}, + {0x24u, 0x02u}, + {0x25u, 0x0Eu}, + {0x26u, 0x20u}, + {0x28u, 0x20u}, + {0x2Bu, 0x82u}, {0x2Cu, 0x02u}, - {0x2Du, 0x08u}, - {0x2Fu, 0x18u}, - {0x31u, 0x80u}, - {0x32u, 0x15u}, - {0x35u, 0x02u}, - {0x37u, 0x22u}, - {0x38u, 0x28u}, - {0x3Bu, 0x40u}, - {0x3Du, 0x86u}, - {0x3Eu, 0x10u}, + {0x2Du, 0x01u}, + {0x31u, 0x08u}, + {0x32u, 0x41u}, + {0x33u, 0x20u}, + {0x36u, 0xA8u}, + {0x37u, 0x21u}, + {0x39u, 0x14u}, + {0x3Cu, 0x08u}, + {0x3Eu, 0x21u}, {0x3Fu, 0x80u}, - {0x59u, 0x80u}, - {0x63u, 0x01u}, - {0x65u, 0x24u}, - {0x66u, 0x80u}, - {0x8Bu, 0x80u}, - {0x8Eu, 0x01u}, - {0x90u, 0x2Au}, - {0x91u, 0x24u}, - {0x92u, 0x3Eu}, - {0x93u, 0x40u}, - {0x94u, 0x40u}, - {0x97u, 0x01u}, - {0x98u, 0x84u}, - {0x99u, 0x28u}, - {0x9Au, 0x01u}, - {0x9Bu, 0x46u}, - {0x9Fu, 0x28u}, + {0x5Du, 0x02u}, + {0x5Eu, 0x64u}, + {0x65u, 0x40u}, + {0x67u, 0x80u}, + {0x82u, 0x08u}, + {0x83u, 0x22u}, + {0x88u, 0x10u}, + {0x89u, 0x01u}, + {0x8Au, 0x14u}, + {0x8Cu, 0x01u}, + {0x91u, 0x95u}, + {0x92u, 0x83u}, + {0x97u, 0x80u}, + {0x98u, 0x30u}, + {0x99u, 0x02u}, + {0x9Au, 0x20u}, + {0x9Bu, 0x05u}, + {0x9Du, 0x08u}, + {0x9Fu, 0x20u}, {0xA0u, 0x06u}, - {0xA1u, 0xC3u}, - {0xA3u, 0x08u}, - {0xA9u, 0x02u}, - {0xAAu, 0x04u}, - {0xB6u, 0x80u}, - {0xC0u, 0xFEu}, - {0xC2u, 0xFDu}, - {0xC4u, 0xD7u}, - {0xCAu, 0x75u}, - {0xCCu, 0xAFu}, - {0xCEu, 0xFEu}, - {0xD6u, 0x08u}, - {0xD8u, 0x78u}, - {0xE2u, 0x10u}, - {0xEAu, 0x10u}, - {0xEEu, 0x08u}, - {0xB0u, 0x01u}, - {0xB1u, 0x10u}, + {0xA2u, 0x80u}, + {0xA3u, 0xE2u}, + {0xA4u, 0x40u}, + {0xA5u, 0x06u}, + {0xAEu, 0x80u}, + {0xAFu, 0x08u}, + {0xB1u, 0x30u}, {0xB2u, 0x80u}, - {0xB5u, 0x80u}, - {0xB7u, 0x10u}, - {0xE8u, 0x10u}, + {0xC0u, 0x4Du}, + {0xC2u, 0xEFu}, + {0xC4u, 0x36u}, + {0xCAu, 0x9Bu}, + {0xCCu, 0xFFu}, + {0xCEu, 0xF6u}, + {0xD6u, 0xF0u}, + {0xD8u, 0x90u}, + {0xE0u, 0xA0u}, + {0xE4u, 0x20u}, + {0xE6u, 0x80u}, + {0xE8u, 0x20u}, + {0xECu, 0x22u}, {0x04u, 0x40u}, - {0x0Cu, 0x10u}, - {0x0Du, 0x04u}, - {0x12u, 0x01u}, - {0x13u, 0x02u}, - {0x16u, 0x80u}, - {0x17u, 0x40u}, - {0x30u, 0x40u}, + {0x0Eu, 0x08u}, + {0x0Fu, 0x40u}, + {0x12u, 0x20u}, + {0x13u, 0x10u}, + {0x17u, 0x81u}, + {0x19u, 0x01u}, + {0x1Du, 0x04u}, + {0x30u, 0x10u}, {0x33u, 0x01u}, - {0x34u, 0x20u}, - {0x36u, 0x02u}, - {0x3Au, 0x82u}, - {0x3Cu, 0x02u}, - {0x3Fu, 0x20u}, + {0x36u, 0x20u}, + {0x37u, 0x02u}, + {0x39u, 0x04u}, + {0x3Bu, 0x10u}, + {0x3Du, 0x01u}, + {0x3Eu, 0x80u}, {0x42u, 0x08u}, - {0x53u, 0x20u}, - {0x54u, 0x80u}, - {0x6Bu, 0x03u}, - {0x82u, 0x02u}, - {0x88u, 0x10u}, - {0x8Fu, 0x20u}, + {0x50u, 0x20u}, + {0x56u, 0x20u}, + {0x89u, 0x01u}, {0xC0u, 0x80u}, {0xC2u, 0xA0u}, {0xC4u, 0xF0u}, + {0xC6u, 0x30u}, {0xCCu, 0xF0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, {0xD4u, 0x60u}, - {0xE6u, 0x20u}, - {0x01u, 0x20u}, - {0x0Bu, 0x02u}, - {0x30u, 0x10u}, - {0x32u, 0x08u}, - {0x36u, 0x01u}, - {0x37u, 0x40u}, - {0x39u, 0x80u}, - {0x56u, 0x04u}, - {0x62u, 0x02u}, - {0x64u, 0x10u}, - {0x66u, 0x01u}, - {0x80u, 0x80u}, - {0x86u, 0x02u}, - {0x89u, 0x24u}, + {0x03u, 0x02u}, + {0x0Au, 0x01u}, + {0x31u, 0x01u}, + {0x32u, 0x40u}, + {0x35u, 0x04u}, + {0x37u, 0x80u}, + {0x39u, 0x08u}, + {0x3Bu, 0x20u}, + {0x3Fu, 0x80u}, + {0x54u, 0x08u}, + {0x5Fu, 0x01u}, + {0x80u, 0x40u}, {0x90u, 0x40u}, - {0x91u, 0x08u}, - {0x9Au, 0x05u}, - {0x9Bu, 0x40u}, - {0x9Cu, 0x60u}, - {0x9Eu, 0x08u}, - {0xA4u, 0x81u}, - {0xAEu, 0x02u}, - {0xB6u, 0x04u}, - {0xB7u, 0x10u}, + {0x93u, 0x40u}, + {0x95u, 0x04u}, + {0x99u, 0x05u}, + {0x9Bu, 0x80u}, + {0x9Cu, 0x10u}, + {0x9Eu, 0xA0u}, + {0x9Fu, 0x02u}, + {0xA2u, 0x04u}, + {0xA8u, 0x20u}, + {0xB6u, 0x08u}, {0xC0u, 0x40u}, {0xC2u, 0x40u}, {0xCCu, 0xF0u}, - {0xCEu, 0x10u}, + {0xCEu, 0x70u}, {0xD4u, 0x40u}, - {0xD8u, 0x40u}, - {0xE2u, 0x60u}, - {0xEAu, 0x40u}, - {0x10u, 0x40u}, - {0x33u, 0x80u}, - {0x5Bu, 0x02u}, - {0x8Au, 0x08u}, - {0x8Fu, 0x01u}, - {0x93u, 0x02u}, - {0x95u, 0x80u}, - {0x9Cu, 0x60u}, - {0x9Eu, 0x08u}, - {0xA4u, 0x01u}, - {0xA6u, 0x09u}, - {0xB4u, 0x40u}, + {0xD6u, 0x80u}, + {0xE4u, 0x20u}, + {0xEAu, 0x80u}, + {0x10u, 0x10u}, + {0x33u, 0x10u}, + {0x34u, 0x08u}, + {0x37u, 0x80u}, + {0x52u, 0x20u}, + {0x80u, 0x08u}, + {0x8Au, 0x28u}, + {0x93u, 0x40u}, + {0x95u, 0x0Cu}, + {0x96u, 0x80u}, + {0x97u, 0x21u}, + {0x9Cu, 0x10u}, + {0x9Eu, 0xA0u}, + {0x9Fu, 0x02u}, + {0xA3u, 0x02u}, + {0xA4u, 0x08u}, + {0xA7u, 0x40u}, + {0xAEu, 0x01u}, + {0xB6u, 0x04u}, {0xC4u, 0x10u}, - {0xCCu, 0x10u}, - {0xD6u, 0x40u}, - {0x8Au, 0x08u}, - {0x8Eu, 0x04u}, - {0x9Cu, 0x20u}, - {0x9Eu, 0x08u}, - {0xA4u, 0x01u}, - {0xA6u, 0x01u}, - {0xA7u, 0x80u}, - {0xA9u, 0x40u}, - {0xB3u, 0x02u}, + {0xCCu, 0xB0u}, + {0xD4u, 0x20u}, + {0xE2u, 0x80u}, + {0xE8u, 0x10u}, + {0x80u, 0x08u}, + {0x83u, 0x10u}, + {0x85u, 0x04u}, + {0x95u, 0x0Cu}, + {0x96u, 0x80u}, + {0x97u, 0x21u}, + {0x9Cu, 0x08u}, + {0x9Eu, 0xA0u}, + {0x9Fu, 0x12u}, + {0xA3u, 0x02u}, + {0xA6u, 0x08u}, + {0xA7u, 0x40u}, + {0xABu, 0x80u}, + {0xAFu, 0x40u}, + {0xE2u, 0x20u}, + {0xE6u, 0x60u}, {0xEAu, 0x80u}, - {0x06u, 0x08u}, - {0x07u, 0x10u}, - {0x08u, 0x02u}, - {0x0Au, 0x02u}, - {0x13u, 0x02u}, - {0x56u, 0x20u}, - {0x5Cu, 0x04u}, - {0x60u, 0x20u}, - {0x80u, 0x02u}, - {0x8Bu, 0x02u}, + {0xECu, 0x40u}, + {0x04u, 0x80u}, + {0x05u, 0x04u}, + {0x08u, 0x40u}, + {0x0Au, 0x20u}, + {0x10u, 0x20u}, + {0x53u, 0x01u}, + {0x58u, 0x01u}, + {0x60u, 0x04u}, + {0x80u, 0x20u}, + {0x83u, 0x01u}, + {0x8Eu, 0x10u}, {0xC0u, 0x05u}, {0xC2u, 0x0Au}, {0xC4u, 0x08u}, - {0xD4u, 0x02u}, - {0xD6u, 0x01u}, + {0xD4u, 0x01u}, + {0xD6u, 0x02u}, {0xD8u, 0x02u}, - {0xE2u, 0x04u}, - {0x00u, 0x08u}, - {0x02u, 0x02u}, - {0x08u, 0x80u}, - {0x09u, 0x04u}, - {0x56u, 0x02u}, - {0x58u, 0x40u}, - {0x5Cu, 0x01u}, - {0x64u, 0x08u}, - {0x80u, 0xA0u}, - {0x81u, 0x04u}, - {0x8Au, 0x02u}, - {0x92u, 0x02u}, + {0xE2u, 0x02u}, + {0x00u, 0x48u}, + {0x08u, 0x40u}, + {0x0Bu, 0x10u}, + {0x57u, 0x0Au}, + {0x61u, 0x90u}, + {0x80u, 0x40u}, + {0x8Bu, 0x10u}, + {0x8Cu, 0x40u}, + {0x90u, 0x80u}, {0x94u, 0x04u}, - {0x9Au, 0x08u}, - {0x9Bu, 0x10u}, - {0x9Cu, 0x20u}, - {0x9Eu, 0x20u}, + {0x99u, 0x04u}, + {0x9Cu, 0x01u}, + {0xB0u, 0x40u}, {0xC0u, 0x0Au}, {0xC2u, 0x0Au}, - {0xD4u, 0x01u}, - {0xD6u, 0x05u}, - {0xD8u, 0x01u}, - {0xE6u, 0x04u}, - {0x8Bu, 0x40u}, - {0x8Eu, 0x20u}, + {0xD4u, 0x02u}, + {0xD6u, 0x06u}, + {0xD8u, 0x02u}, + {0xE2u, 0x02u}, + {0xE6u, 0x01u}, + {0xEAu, 0x01u}, + {0x56u, 0x80u}, + {0x81u, 0x80u}, + {0x87u, 0x0Au}, {0x94u, 0x04u}, - {0x9Au, 0x08u}, - {0x9Bu, 0x10u}, - {0x9Cu, 0x40u}, - {0x9Eu, 0x20u}, + {0x9Cu, 0x01u}, + {0x9Du, 0x10u}, {0xA0u, 0x04u}, - {0xA8u, 0x01u}, - {0xACu, 0x08u}, - {0xAEu, 0x01u}, - {0xB2u, 0x02u}, - {0xE4u, 0x02u}, - {0xE6u, 0x01u}, - {0xE8u, 0x01u}, - {0x0Bu, 0x81u}, - {0x0Fu, 0x22u}, - {0x8Cu, 0x04u}, + {0xA5u, 0x80u}, + {0xA7u, 0x0Au}, + {0xA8u, 0x04u}, + {0xA9u, 0x04u}, + {0xACu, 0x40u}, + {0xD4u, 0x02u}, + {0x09u, 0x10u}, + {0x0Bu, 0x40u}, + {0x0Fu, 0x88u}, + {0x83u, 0x44u}, + {0x88u, 0x01u}, {0x94u, 0x04u}, - {0x97u, 0x81u}, - {0x9Bu, 0x10u}, - {0x9Cu, 0x40u}, - {0xAAu, 0x08u}, - {0xABu, 0x01u}, + {0x9Cu, 0x01u}, + {0x9Du, 0x10u}, + {0xA5u, 0x10u}, + {0xA9u, 0x10u}, {0xACu, 0x04u}, + {0xAEu, 0x80u}, {0xC2u, 0x0Fu}, - {0xE4u, 0x02u}, - {0x02u, 0x04u}, - {0x84u, 0x01u}, - {0x89u, 0x02u}, - {0x8Cu, 0x08u}, - {0x8Eu, 0x01u}, - {0x9Eu, 0x04u}, - {0xA4u, 0x01u}, - {0xA8u, 0x20u}, - {0xAFu, 0x80u}, - {0xB6u, 0x01u}, + {0xE4u, 0x04u}, + {0x02u, 0x08u}, + {0x66u, 0x10u}, + {0x82u, 0x40u}, + {0x83u, 0x41u}, + {0x86u, 0x80u}, + {0x87u, 0x10u}, + {0x8Au, 0x10u}, + {0x8Cu, 0x01u}, + {0x96u, 0x80u}, + {0x97u, 0x01u}, + {0x9Eu, 0xA0u}, + {0x9Fu, 0x02u}, + {0xA6u, 0x08u}, + {0xA7u, 0x40u}, + {0xADu, 0x04u}, + {0xAFu, 0x10u}, + {0xB3u, 0x02u}, {0xC0u, 0x40u}, - {0xE6u, 0x10u}, - {0xEEu, 0x30u}, - {0x03u, 0x20u}, - {0x51u, 0x20u}, - {0x55u, 0x08u}, - {0x58u, 0x08u}, - {0x5Fu, 0x08u}, - {0x61u, 0x02u}, - {0x65u, 0x02u}, - {0x7Au, 0x01u}, - {0x85u, 0x20u}, - {0x87u, 0x20u}, - {0x89u, 0x02u}, - {0x98u, 0x08u}, - {0x99u, 0x02u}, - {0x9Bu, 0x08u}, - {0xA1u, 0x08u}, - {0xA2u, 0x01u}, - {0xA9u, 0x08u}, - {0xB7u, 0x08u}, + {0xD8u, 0x80u}, + {0xE2u, 0xE0u}, + {0xE6u, 0xC0u}, + {0xEAu, 0x10u}, + {0xEEu, 0x40u}, + {0x02u, 0x10u}, + {0x57u, 0x08u}, + {0x5Au, 0x40u}, + {0x5Cu, 0x01u}, + {0x67u, 0x20u}, + {0x82u, 0x40u}, + {0x86u, 0x10u}, + {0x87u, 0x08u}, + {0x8Eu, 0x20u}, + {0x90u, 0x01u}, + {0x93u, 0x20u}, + {0x9Eu, 0x20u}, + {0xB7u, 0x02u}, {0xC0u, 0x10u}, - {0xD4u, 0x60u}, - {0xD6u, 0xC0u}, - {0xD8u, 0xC0u}, - {0xDCu, 0x80u}, - {0xE2u, 0x10u}, - {0xE4u, 0x10u}, - {0xEAu, 0x80u}, - {0x74u, 0x08u}, - {0x88u, 0x08u}, - {0x90u, 0x02u}, - {0x9Bu, 0x10u}, - {0x9Cu, 0x40u}, - {0xAFu, 0x01u}, - {0xB4u, 0x01u}, - {0xB7u, 0x10u}, + {0xD4u, 0xC0u}, + {0xD6u, 0x80u}, + {0xD8u, 0x80u}, + {0xE0u, 0x40u}, + {0xE2u, 0x20u}, + {0xE6u, 0x40u}, + {0x80u, 0x04u}, + {0x94u, 0x04u}, + {0x9Du, 0x10u}, + {0xAFu, 0x40u}, + {0x74u, 0x04u}, + {0x8Du, 0x10u}, + {0x9Du, 0x10u}, + {0xA0u, 0x04u}, + {0xACu, 0x04u}, {0xDEu, 0x04u}, - {0xE4u, 0x04u}, - {0xE8u, 0x02u}, - {0xEAu, 0x08u}, - {0x70u, 0x01u}, - {0x90u, 0x02u}, - {0xB0u, 0x40u}, - {0xB7u, 0x10u}, - {0xDCu, 0x01u}, - {0xE8u, 0x01u}, - {0xEEu, 0x02u}, - {0x10u, 0x03u}, + {0xE0u, 0x02u}, + {0x10u, 0x07u}, {0x11u, 0x01u}, {0x1Au, 0x03u}, - {0x1Cu, 0x01u}, + {0x1Bu, 0x01u}, + {0x1Cu, 0x07u}, {0x1Du, 0x01u}, - {0x00u, 0xFFu}, - {0x01u, 0xBFu}, - {0x02u, 0x2Au}, - {0x10u, 0x95u}, + {0x10u, 0x59u}, + {0x11u, 0x09u}, }; @@ -2418,30 +2528,47 @@ void cyfitter_cfg(void) {(void CYFAR *)(CYREG_PRT5_DR), 16u}, {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1024u}, {(void CYFAR *)(CYDEV_UCFG_B0_P2_U1_BASE), 2944u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, }; + /* IDMUX_IRQ Address: CYREG_IDMUX_IRQ_CTL0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IDMUX_IRQ_VAL[] = { + 0xFFu, 0xFFu, 0xABu, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u}; + /* UDB_1_3_0_CONFIG Address: CYDEV_UCFG_B0_P2_U0_BASE Size (bytes): 128 */ static const uint8 CYCODE BS_UDB_1_3_0_CONFIG_VAL[] = { - 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x40u, 0x60u, 0x00u, 0x00u, 0x88u, 0xFFu, 0x21u, 0x90u, 0x01u, 0x40u, 0x00u, - 0x00u, 0x01u, 0x9Fu, 0x00u, 0x7Fu, 0xA2u, 0x80u, 0x08u, 0xC0u, 0x04u, 0x04u, 0x00u, 0x1Fu, 0x87u, 0x20u, 0x18u, - 0xC0u, 0x40u, 0x02u, 0x00u, 0xC0u, 0x01u, 0x01u, 0x00u, 0xC0u, 0x01u, 0x08u, 0x00u, 0x80u, 0x10u, 0x00u, 0x00u, - 0xFFu, 0x00u, 0x00u, 0x3Fu, 0x00u, 0x40u, 0x00u, 0x80u, 0x80u, 0x28u, 0x00u, 0x00u, 0x00u, 0x00u, 0x41u, 0x44u, - 0x63u, 0x04u, 0x10u, 0x00u, 0x05u, 0xCEu, 0xDBu, 0x0Fu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, + 0x34u, 0x00u, 0x40u, 0x00u, 0x3Du, 0x30u, 0x42u, 0x00u, 0x03u, 0x00u, 0x0Cu, 0x00u, 0x40u, 0x15u, 0x80u, 0x0Au, + 0x10u, 0x00u, 0x20u, 0x00u, 0x00u, 0x09u, 0x00u, 0x16u, 0x00u, 0x04u, 0x77u, 0x03u, 0x10u, 0x00u, 0x20u, 0x00u, + 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x8Bu, 0x0Bu, 0x74u, 0x24u, 0x88u, 0x00u, 0x77u, 0x00u, + 0x30u, 0x00u, 0x00u, 0x38u, 0x0Fu, 0x07u, 0xC0u, 0x00u, 0x00u, 0x08u, 0xA2u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x52u, 0x04u, 0x60u, 0x00u, 0x03u, 0xBEu, 0xFDu, 0xBCu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x04u, 0x04u, 0x04u, 0x12u, 0x10u, 0x00u, 0x01u, + 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ + static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = { + 0x02u, 0x00u, 0x00u, 0x00u, 0x02u, 0x80u, 0x00u, 0x00u, 0x10u, 0xC0u, 0x42u, 0x08u, 0x01u, 0x7Fu, 0x00u, 0x80u, + 0x44u, 0x90u, 0x10u, 0x40u, 0x01u, 0x1Fu, 0x00u, 0x20u, 0x02u, 0xC0u, 0x00u, 0x04u, 0x02u, 0xC0u, 0x00u, 0x02u, + 0x08u, 0xC0u, 0x00u, 0x01u, 0x20u, 0x00u, 0x00u, 0x9Fu, 0x0Eu, 0x00u, 0x30u, 0xFFu, 0x02u, 0x00u, 0x00u, 0x60u, + 0x01u, 0x00u, 0x00u, 0xFFu, 0x00u, 0x00u, 0x7Eu, 0x00u, 0x82u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x04u, + 0x64u, 0x03u, 0x50u, 0x00u, 0x02u, 0xCBu, 0xF0u, 0xEDu, 0x3Bu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x04u, 0x04u, 0x04u, 0x01u, 0x01u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { - 0x07u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x01u, 0x07u, 0x01u, 0x05u, 0x01u, 0x05u, 0x01u}; + 0x07u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x07u, 0x01u, 0x07u, 0x01u, 0x04u, 0x01u, 0x04u, 0x01u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ + {(void CYFAR *)(CYREG_IDMUX_IRQ_CTL0), BS_IDMUX_IRQ_VAL, 8u}, {(void CYFAR *)(CYDEV_UCFG_B0_P2_U0_BASE), BS_UDB_1_3_0_CONFIG_VAL, 128u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, }; @@ -2471,6 +2598,8 @@ void cyfitter_cfg(void) CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM1_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM1_VAL), 4u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM2_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM2_VAL), 4u); CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM3_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM3_VAL), 4u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM4_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM4_VAL), 4u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM5_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM5_VAL), 4u); /* Enable digital routing */ CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u); diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h index eefc440..58a0447 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cyfitter_cfg.h * -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * This file provides basic startup and mux configuration settings * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 043d4f7..92ae462 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cyfittergnu.inc * -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -192,34 +192,34 @@ .set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 .set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_1__INTC_MASK, 0x80 -.set USBFS_ep_1__INTC_NUMBER, 7 +.set USBFS_ep_1__INTC_MASK, 0x200 +.set USBFS_ep_1__INTC_NUMBER, 9 .set USBFS_ep_1__INTC_PRIOR_NUM, 7 -.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 +.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 .set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 .set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_2__INTC_MASK, 0x100 -.set USBFS_ep_2__INTC_NUMBER, 8 +.set USBFS_ep_2__INTC_MASK, 0x400 +.set USBFS_ep_2__INTC_NUMBER, 10 .set USBFS_ep_2__INTC_PRIOR_NUM, 7 -.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 +.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_10 .set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 .set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_3__INTC_MASK, 0x200 -.set USBFS_ep_3__INTC_NUMBER, 9 +.set USBFS_ep_3__INTC_MASK, 0x800 +.set USBFS_ep_3__INTC_NUMBER, 11 .set USBFS_ep_3__INTC_PRIOR_NUM, 7 -.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 +.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_11 .set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 .set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set USBFS_ep_4__INTC_MASK, 0x400 -.set USBFS_ep_4__INTC_NUMBER, 10 +.set USBFS_ep_4__INTC_MASK, 0x2000 +.set USBFS_ep_4__INTC_NUMBER, 13 .set USBFS_ep_4__INTC_PRIOR_NUM, 7 -.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10 +.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_13 .set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 .set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -424,32 +424,32 @@ .set NOR_SO__SLW, CYREG_PRT15_SLW /* SDCard */ -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB04_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB04_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB04_ST .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 @@ -460,11 +460,7 @@ .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 .set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK -.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL .set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL -.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL .set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 @@ -483,12 +479,12 @@ .set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 .set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 .set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 +.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 .set SDCard_BSPIM_TxStsReg__2__POS, 2 .set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 @@ -496,9 +492,9 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB06_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB06_ST +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB11_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB11_ST /* SD_SCK */ .set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE1 @@ -534,30 +530,6 @@ .set SD_SCK__SHIFT, 1 .set SD_SCK__SLW, CYREG_PRT3_SLW -/* NOR_CTL */ -.set NOR_CTL_Sync_ctrl_reg__0__MASK, 0x01 -.set NOR_CTL_Sync_ctrl_reg__0__POS, 0 -.set NOR_CTL_Sync_ctrl_reg__1__MASK, 0x02 -.set NOR_CTL_Sync_ctrl_reg__1__POS, 1 -.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL -.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL -.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL -.set NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL -.set NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL -.set NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK -.set NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK -.set NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK -.set NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK -.set NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL -.set NOR_CTL_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB06_CTL -.set NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL -.set NOR_CTL_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB06_CTL -.set NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL -.set NOR_CTL_Sync_ctrl_reg__MASK, 0x03 -.set NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL -.set NOR_CTL_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB06_MSK - /* NOR_SCK */ .set NOR_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE7 .set NOR_SCK__0__MASK, 0x80 @@ -593,34 +565,34 @@ .set NOR_SCK__SLW, CYREG_PRT3_SLW /* NOR_SPI */ -.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL -.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK -.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK -.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK -.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK -.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL -.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB08_CTL -.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL -.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB08_CTL -.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL -.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB08_MSK -.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL -.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST -.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB08_MSK -.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL -.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL -.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL -.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL -.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB08_ST -.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL -.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST +.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK +.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK +.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL +.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL +.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL +.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL +.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK +.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST +.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK +.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST +.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST .set NOR_SPI_BSPIM_RxStsReg__4__MASK, 0x10 .set NOR_SPI_BSPIM_RxStsReg__4__POS, 4 .set NOR_SPI_BSPIM_RxStsReg__5__MASK, 0x20 @@ -628,9 +600,9 @@ .set NOR_SPI_BSPIM_RxStsReg__6__MASK, 0x40 .set NOR_SPI_BSPIM_RxStsReg__6__POS, 6 .set NOR_SPI_BSPIM_RxStsReg__MASK, 0x70 -.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK -.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL -.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST +.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK +.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST .set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0 .set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1 .set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0 @@ -648,6 +620,8 @@ .set NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1 .set NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB04_F0 .set NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB04_F1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL +.set NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL .set NOR_SPI_BSPIM_TxStsReg__0__MASK, 0x01 .set NOR_SPI_BSPIM_TxStsReg__0__POS, 0 .set NOR_SPI_BSPIM_TxStsReg__1__MASK, 0x02 @@ -1784,15 +1758,15 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB09_10_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB09_10_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB09_10_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB09_10_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB09_10_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB09_10_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB09_10_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB09_10_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB09_10_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB09_10_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB09_10_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB09_10_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB09_10_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB09_10_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB09_10_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB09_10_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08 @@ -1805,35 +1779,35 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB09_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB09_ST_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB09_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB09_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB09_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB09_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB09_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB09_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF -.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB09_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB09_MSK .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG .set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX .set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE @@ -2293,42 +2267,42 @@ .set NOR_Clock__PM_STBY_MSK, 0x01 /* SD_RX_DMA */ -.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SD_RX_DMA__DRQ_NUMBER, 2 +.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL1 +.set SD_RX_DMA__DRQ_NUMBER, 4 .set SD_RX_DMA__NUMBEROF_TDS, 0 .set SD_RX_DMA__PRIORITY, 0 .set SD_RX_DMA__TERMIN_EN, 0 .set SD_RX_DMA__TERMIN_SEL, 0 .set SD_RX_DMA__TERMOUT0_EN, 1 -.set SD_RX_DMA__TERMOUT0_SEL, 2 +.set SD_RX_DMA__TERMOUT0_SEL, 4 .set SD_RX_DMA__TERMOUT1_EN, 0 .set SD_RX_DMA__TERMOUT1_SEL, 0 .set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20 -.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 5 +.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x80 +.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 7 .set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5 +.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 .set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* SD_TX_DMA */ -.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SD_TX_DMA__DRQ_NUMBER, 3 +.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL1 +.set SD_TX_DMA__DRQ_NUMBER, 5 .set SD_TX_DMA__NUMBEROF_TDS, 0 .set SD_TX_DMA__PRIORITY, 1 .set SD_TX_DMA__TERMIN_EN, 0 .set SD_TX_DMA__TERMIN_SEL, 0 .set SD_TX_DMA__TERMOUT0_EN, 1 -.set SD_TX_DMA__TERMOUT0_SEL, 3 +.set SD_TX_DMA__TERMOUT0_SEL, 5 .set SD_TX_DMA__TERMOUT1_EN, 0 .set SD_TX_DMA__TERMOUT1_SEL, 0 .set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40 -.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 6 +.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x100 +.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 8 .set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6 +.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 .set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 @@ -2365,6 +2339,46 @@ .set nNOR_HOLD__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ .set nNOR_HOLD__SLW, CYREG_PRT12_SLW +/* NOR_RX_DMA */ +.set NOR_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set NOR_RX_DMA__DRQ_NUMBER, 0 +.set NOR_RX_DMA__NUMBEROF_TDS, 0 +.set NOR_RX_DMA__PRIORITY, 2 +.set NOR_RX_DMA__TERMIN_EN, 0 +.set NOR_RX_DMA__TERMIN_SEL, 0 +.set NOR_RX_DMA__TERMOUT0_EN, 1 +.set NOR_RX_DMA__TERMOUT0_SEL, 0 +.set NOR_RX_DMA__TERMOUT1_EN, 0 +.set NOR_RX_DMA__TERMOUT1_SEL, 0 +.set NOR_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set NOR_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set NOR_RX_DMA_COMPLETE__INTC_MASK, 0x02 +.set NOR_RX_DMA_COMPLETE__INTC_NUMBER, 1 +.set NOR_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set NOR_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 +.set NOR_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set NOR_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* NOR_TX_DMA */ +.set NOR_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set NOR_TX_DMA__DRQ_NUMBER, 1 +.set NOR_TX_DMA__NUMBEROF_TDS, 0 +.set NOR_TX_DMA__PRIORITY, 2 +.set NOR_TX_DMA__TERMIN_EN, 0 +.set NOR_TX_DMA__TERMIN_SEL, 0 +.set NOR_TX_DMA__TERMOUT0_EN, 1 +.set NOR_TX_DMA__TERMOUT0_SEL, 1 +.set NOR_TX_DMA__TERMOUT1_EN, 0 +.set NOR_TX_DMA__TERMOUT1_SEL, 0 +.set NOR_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set NOR_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set NOR_TX_DMA_COMPLETE__INTC_MASK, 0x04 +.set NOR_TX_DMA_COMPLETE__INTC_NUMBER, 2 +.set NOR_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set NOR_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 +.set NOR_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set NOR_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + /* SCSI_Noise */ .set SCSI_Noise__0__AG, CYREG_PRT4_AG .set SCSI_Noise__0__AMUX, CYREG_PRT4_AMUX @@ -2697,8 +2711,8 @@ .set scsiTarget_StatusReg__0__POS, 0 .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 -.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST .set scsiTarget_StatusReg__2__MASK, 0x04 .set scsiTarget_StatusReg__2__POS, 2 .set scsiTarget_StatusReg__3__MASK, 0x08 @@ -2706,13 +2720,13 @@ .set scsiTarget_StatusReg__4__MASK, 0x10 .set scsiTarget_StatusReg__4__POS, 4 .set scsiTarget_StatusReg__MASK, 0x1F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK -.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL -.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK +.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL +.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST /* Debug_Timer */ .set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -2742,41 +2756,41 @@ /* SCSI_RX_DMA */ .set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SCSI_RX_DMA__DRQ_NUMBER, 0 +.set SCSI_RX_DMA__DRQ_NUMBER, 2 .set SCSI_RX_DMA__NUMBEROF_TDS, 0 .set SCSI_RX_DMA__PRIORITY, 2 .set SCSI_RX_DMA__TERMIN_EN, 0 .set SCSI_RX_DMA__TERMIN_SEL, 0 .set SCSI_RX_DMA__TERMOUT0_EN, 1 -.set SCSI_RX_DMA__TERMOUT0_SEL, 0 +.set SCSI_RX_DMA__TERMOUT0_SEL, 2 .set SCSI_RX_DMA__TERMOUT1_EN, 0 .set SCSI_RX_DMA__TERMOUT1_SEL, 0 .set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x04 -.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 2 +.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x10 +.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 4 .set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 +.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 .set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* SCSI_TX_DMA */ .set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 -.set SCSI_TX_DMA__DRQ_NUMBER, 1 +.set SCSI_TX_DMA__DRQ_NUMBER, 3 .set SCSI_TX_DMA__NUMBEROF_TDS, 0 .set SCSI_TX_DMA__PRIORITY, 2 .set SCSI_TX_DMA__TERMIN_EN, 0 .set SCSI_TX_DMA__TERMIN_SEL, 0 .set SCSI_TX_DMA__TERMOUT0_EN, 1 -.set SCSI_TX_DMA__TERMOUT0_SEL, 1 +.set SCSI_TX_DMA__TERMOUT0_SEL, 3 .set SCSI_TX_DMA__TERMOUT1_EN, 0 .set SCSI_TX_DMA__TERMOUT1_SEL, 0 .set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10 -.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4 +.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x40 +.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 6 .set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 -.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6 .set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 @@ -2805,20 +2819,20 @@ /* SCSI_RST_ISR */ .set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_RST_ISR__INTC_MASK, 0x02 -.set SCSI_RST_ISR__INTC_NUMBER, 1 +.set SCSI_RST_ISR__INTC_MASK, 0x08 +.set SCSI_RST_ISR__INTC_NUMBER, 3 .set SCSI_RST_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 +.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 .set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* SCSI_SEL_ISR */ .set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 .set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 -.set SCSI_SEL_ISR__INTC_MASK, 0x08 -.set SCSI_SEL_ISR__INTC_NUMBER, 3 +.set SCSI_SEL_ISR__INTC_MASK, 0x20 +.set SCSI_SEL_ISR__INTC_NUMBER, 5 .set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7 -.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 +.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_5 .set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 @@ -2827,6 +2841,8 @@ .set SCSI_Filtered_sts_sts_reg__0__POS, 0 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 .set SCSI_Filtered_sts_sts_reg__1__POS, 1 +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 .set SCSI_Filtered_sts_sts_reg__2__POS, 2 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 @@ -2834,74 +2850,78 @@ .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 .set SCSI_Filtered_sts_sts_reg__4__POS, 4 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F -.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB15_MSK -.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB15_ST +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK +.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL +.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST /* SCSI_CTL_PHASE */ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK -.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK /* SCSI_Glitch_Ctl */ .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL .set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK /* SCSI_Parity_Error */ .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB09_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB09_ST /* Miscellaneous */ .set BCLK__BUS_CLK__HZ, 50000000 .set BCLK__BUS_CLK__KHZ, 50000 .set BCLK__BUS_CLK__MHZ, 50 .set CYDEV_CHIP_DIE_LEOPARD, 1 -.set CYDEV_CHIP_DIE_PSOC4A, 18 +.set CYDEV_CHIP_DIE_PSOC4A, 26 .set CYDEV_CHIP_DIE_PSOC5LP, 2 .set CYDEV_CHIP_DIE_PSOC5TM, 3 .set CYDEV_CHIP_DIE_TMA4, 4 @@ -2917,34 +2937,43 @@ .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 .set CYDEV_CHIP_JTAG_ID, 0x2E133069 .set CYDEV_CHIP_MEMBER_3A, 1 -.set CYDEV_CHIP_MEMBER_4A, 18 -.set CYDEV_CHIP_MEMBER_4D, 13 +.set CYDEV_CHIP_MEMBER_4A, 26 +.set CYDEV_CHIP_MEMBER_4AA, 25 +.set CYDEV_CHIP_MEMBER_4AB, 30 +.set CYDEV_CHIP_MEMBER_4AC, 14 +.set CYDEV_CHIP_MEMBER_4AD, 15 +.set CYDEV_CHIP_MEMBER_4AE, 16 +.set CYDEV_CHIP_MEMBER_4D, 20 .set CYDEV_CHIP_MEMBER_4E, 6 -.set CYDEV_CHIP_MEMBER_4F, 19 +.set CYDEV_CHIP_MEMBER_4F, 27 .set CYDEV_CHIP_MEMBER_4G, 4 -.set CYDEV_CHIP_MEMBER_4H, 17 -.set CYDEV_CHIP_MEMBER_4I, 23 -.set CYDEV_CHIP_MEMBER_4J, 14 -.set CYDEV_CHIP_MEMBER_4K, 15 -.set CYDEV_CHIP_MEMBER_4L, 22 -.set CYDEV_CHIP_MEMBER_4M, 21 -.set CYDEV_CHIP_MEMBER_4N, 10 -.set CYDEV_CHIP_MEMBER_4O, 7 -.set CYDEV_CHIP_MEMBER_4P, 20 -.set CYDEV_CHIP_MEMBER_4Q, 12 -.set CYDEV_CHIP_MEMBER_4R, 8 -.set CYDEV_CHIP_MEMBER_4S, 11 -.set CYDEV_CHIP_MEMBER_4T, 9 +.set CYDEV_CHIP_MEMBER_4H, 24 +.set CYDEV_CHIP_MEMBER_4I, 32 +.set CYDEV_CHIP_MEMBER_4J, 21 +.set CYDEV_CHIP_MEMBER_4K, 22 +.set CYDEV_CHIP_MEMBER_4L, 31 +.set CYDEV_CHIP_MEMBER_4M, 29 +.set CYDEV_CHIP_MEMBER_4N, 11 +.set CYDEV_CHIP_MEMBER_4O, 8 +.set CYDEV_CHIP_MEMBER_4P, 28 +.set CYDEV_CHIP_MEMBER_4Q, 17 +.set CYDEV_CHIP_MEMBER_4R, 9 +.set CYDEV_CHIP_MEMBER_4S, 12 +.set CYDEV_CHIP_MEMBER_4T, 10 .set CYDEV_CHIP_MEMBER_4U, 5 -.set CYDEV_CHIP_MEMBER_4V, 16 +.set CYDEV_CHIP_MEMBER_4V, 23 +.set CYDEV_CHIP_MEMBER_4W, 13 +.set CYDEV_CHIP_MEMBER_4X, 7 +.set CYDEV_CHIP_MEMBER_4Y, 18 +.set CYDEV_CHIP_MEMBER_4Z, 19 .set CYDEV_CHIP_MEMBER_5A, 3 .set CYDEV_CHIP_MEMBER_5B, 2 -.set CYDEV_CHIP_MEMBER_6A, 24 -.set CYDEV_CHIP_MEMBER_FM3, 28 -.set CYDEV_CHIP_MEMBER_FM4, 29 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 25 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 26 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 27 +.set CYDEV_CHIP_MEMBER_6A, 33 +.set CYDEV_CHIP_MEMBER_FM3, 37 +.set CYDEV_CHIP_MEMBER_FM4, 38 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 34 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 35 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 36 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED @@ -2969,6 +2998,11 @@ .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 .set CYDEV_CHIP_REVISION_4A_ES0, 17 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_4AA_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4AB_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4AC_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4AD_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4AE_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD, 0 .set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0 @@ -2993,6 +3027,10 @@ .set CYDEV_CHIP_REVISION_4T_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4V_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4W_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4X_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4Y_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4Z_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_5A_ES0, 0 .set CYDEV_CHIP_REVISION_5A_ES1, 1 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 @@ -3032,7 +3070,7 @@ .set CYDEV_ECC_ENABLE, 0 .set CYDEV_HEAP_SIZE, 0x0400 .set CYDEV_INSTRUCT_CACHE_ENABLED, 1 -.set CYDEV_INTR_RISING, 0x0000007F +.set CYDEV_INTR_RISING, 0x000001FF .set CYDEV_IS_EXPORTING_CODE, 0 .set CYDEV_IS_IMPORTING_CODE, 0 .set CYDEV_PROJ_TYPE, 2 @@ -3085,6 +3123,6 @@ .set CYIPBLOCK_S8_SAR_VERSION, 0 .set CYIPBLOCK_S8_SIO_VERSION, 0 .set CYIPBLOCK_S8_UDB_VERSION, 0 -.set DMA_CHANNELS_USED__MASK0, 0x0000000F +.set DMA_CHANNELS_USED__MASK0, 0x0000003F .set CYDEV_BOOTLOADER_ENABLE, 0 .endif diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 5442ef3..23043fc 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -1,13 +1,13 @@ ; ; File Name: cyfitteriar.inc ; -; PSoC Creator 4.2 +; PSoC Creator 4.4 ; ; Description: ; ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. @@ -191,34 +191,34 @@ USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x80 -USBFS_ep_1__INTC_NUMBER EQU 7 +USBFS_ep_1__INTC_MASK EQU 0x200 +USBFS_ep_1__INTC_NUMBER EQU 9 USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x100 -USBFS_ep_2__INTC_NUMBER EQU 8 +USBFS_ep_2__INTC_MASK EQU 0x400 +USBFS_ep_2__INTC_NUMBER EQU 10 USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x200 -USBFS_ep_3__INTC_NUMBER EQU 9 +USBFS_ep_3__INTC_MASK EQU 0x800 +USBFS_ep_3__INTC_NUMBER EQU 11 USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_11 USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x400 -USBFS_ep_4__INTC_NUMBER EQU 10 +USBFS_ep_4__INTC_MASK EQU 0x2000 +USBFS_ep_4__INTC_NUMBER EQU 13 USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_13 USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -423,32 +423,32 @@ NOR_SO__SHIFT EQU 2 NOR_SO__SLW EQU CYREG_PRT15_SLW /* SDCard */ -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB04_ST SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 @@ -459,11 +459,7 @@ SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 @@ -482,12 +478,12 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -495,9 +491,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST /* SD_SCK */ SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 @@ -533,30 +529,6 @@ SD_SCK__PS EQU CYREG_PRT3_PS SD_SCK__SHIFT EQU 1 SD_SCK__SLW EQU CYREG_PRT3_SLW -/* NOR_CTL */ -NOR_CTL_Sync_ctrl_reg__0__MASK EQU 0x01 -NOR_CTL_Sync_ctrl_reg__0__POS EQU 0 -NOR_CTL_Sync_ctrl_reg__1__MASK EQU 0x02 -NOR_CTL_Sync_ctrl_reg__1__POS EQU 1 -NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK -NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK -NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -NOR_CTL_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB06_CTL -NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL -NOR_CTL_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB06_CTL -NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL -NOR_CTL_Sync_ctrl_reg__MASK EQU 0x03 -NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -NOR_CTL_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB06_MSK - /* NOR_SCK */ NOR_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE7 NOR_SCK__0__MASK EQU 0x80 @@ -592,34 +564,34 @@ NOR_SCK__SHIFT EQU 7 NOR_SCK__SLW EQU CYREG_PRT3_SLW /* NOR_SPI */ -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL -NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL -NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL -NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL -NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK -NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST -NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK -NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST -NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL -NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10 NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4 NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -627,9 +599,9 @@ NOR_SPI_BSPIM_RxStsReg__5__POS EQU 5 NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40 NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6 NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70 -NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK -NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL -NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST +NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 @@ -647,6 +619,8 @@ NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0 NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01 NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0 NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02 @@ -1783,15 +1757,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1804,35 +1778,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE @@ -2292,42 +2266,42 @@ NOR_Clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 NOR_Clock__PM_STBY_MSK EQU 0x01 /* SD_RX_DMA */ -SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SD_RX_DMA__DRQ_NUMBER EQU 2 +SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL1 +SD_RX_DMA__DRQ_NUMBER EQU 4 SD_RX_DMA__NUMBEROF_TDS EQU 0 SD_RX_DMA__PRIORITY EQU 0 SD_RX_DMA__TERMIN_EN EQU 0 SD_RX_DMA__TERMIN_SEL EQU 0 SD_RX_DMA__TERMOUT0_EN EQU 1 -SD_RX_DMA__TERMOUT0_SEL EQU 2 +SD_RX_DMA__TERMOUT0_SEL EQU 4 SD_RX_DMA__TERMOUT1_EN EQU 0 SD_RX_DMA__TERMOUT1_SEL EQU 0 SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20 -SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5 +SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x80 +SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 7 SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 +SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SD_TX_DMA */ -SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SD_TX_DMA__DRQ_NUMBER EQU 3 +SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL1 +SD_TX_DMA__DRQ_NUMBER EQU 5 SD_TX_DMA__NUMBEROF_TDS EQU 0 SD_TX_DMA__PRIORITY EQU 1 SD_TX_DMA__TERMIN_EN EQU 0 SD_TX_DMA__TERMIN_SEL EQU 0 SD_TX_DMA__TERMOUT0_EN EQU 1 -SD_TX_DMA__TERMOUT0_SEL EQU 3 +SD_TX_DMA__TERMOUT0_SEL EQU 5 SD_TX_DMA__TERMOUT1_EN EQU 0 SD_TX_DMA__TERMOUT1_SEL EQU 0 SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 -SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6 +SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x100 +SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 8 SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 +SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2364,6 +2338,46 @@ nNOR_HOLD__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN nNOR_HOLD__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ nNOR_HOLD__SLW EQU CYREG_PRT12_SLW +/* NOR_RX_DMA */ +NOR_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +NOR_RX_DMA__DRQ_NUMBER EQU 0 +NOR_RX_DMA__NUMBEROF_TDS EQU 0 +NOR_RX_DMA__PRIORITY EQU 2 +NOR_RX_DMA__TERMIN_EN EQU 0 +NOR_RX_DMA__TERMIN_SEL EQU 0 +NOR_RX_DMA__TERMOUT0_EN EQU 1 +NOR_RX_DMA__TERMOUT0_SEL EQU 0 +NOR_RX_DMA__TERMOUT1_EN EQU 0 +NOR_RX_DMA__TERMOUT1_SEL EQU 0 +NOR_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +NOR_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +NOR_RX_DMA_COMPLETE__INTC_MASK EQU 0x02 +NOR_RX_DMA_COMPLETE__INTC_NUMBER EQU 1 +NOR_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +NOR_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +NOR_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +NOR_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* NOR_TX_DMA */ +NOR_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +NOR_TX_DMA__DRQ_NUMBER EQU 1 +NOR_TX_DMA__NUMBEROF_TDS EQU 0 +NOR_TX_DMA__PRIORITY EQU 2 +NOR_TX_DMA__TERMIN_EN EQU 0 +NOR_TX_DMA__TERMIN_SEL EQU 0 +NOR_TX_DMA__TERMOUT0_EN EQU 1 +NOR_TX_DMA__TERMOUT0_SEL EQU 1 +NOR_TX_DMA__TERMOUT1_EN EQU 0 +NOR_TX_DMA__TERMOUT1_SEL EQU 0 +NOR_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +NOR_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +NOR_TX_DMA_COMPLETE__INTC_MASK EQU 0x04 +NOR_TX_DMA_COMPLETE__INTC_NUMBER EQU 2 +NOR_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +NOR_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +NOR_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +NOR_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + /* SCSI_Noise */ SCSI_Noise__0__AG EQU CYREG_PRT4_AG SCSI_Noise__0__AMUX EQU CYREG_PRT4_AMUX @@ -2696,8 +2710,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2705,13 +2719,13 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK -scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST /* Debug_Timer */ Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2741,41 +2755,41 @@ Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 /* SCSI_RX_DMA */ SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__DRQ_NUMBER EQU 2 SCSI_RX_DMA__NUMBEROF_TDS EQU 0 SCSI_RX_DMA__PRIORITY EQU 2 SCSI_RX_DMA__TERMIN_EN EQU 0 SCSI_RX_DMA__TERMIN_SEL EQU 0 SCSI_RX_DMA__TERMOUT0_EN EQU 1 -SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_SEL EQU 2 SCSI_RX_DMA__TERMOUT1_EN EQU 0 SCSI_RX_DMA__TERMOUT1_SEL EQU 0 SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 -SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 4 SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_TX_DMA */ SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__DRQ_NUMBER EQU 3 SCSI_TX_DMA__NUMBEROF_TDS EQU 0 SCSI_TX_DMA__PRIORITY EQU 2 SCSI_TX_DMA__TERMIN_EN EQU 0 SCSI_TX_DMA__TERMIN_SEL EQU 0 SCSI_TX_DMA__TERMOUT0_EN EQU 1 -SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 3 SCSI_TX_DMA__TERMOUT1_EN EQU 0 SCSI_TX_DMA__TERMOUT1_SEL EQU 0 SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 6 SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2804,20 +2818,20 @@ timer_clock__PM_STBY_MSK EQU 0x08 /* SCSI_RST_ISR */ SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x02 -SCSI_RST_ISR__INTC_NUMBER EQU 1 +SCSI_RST_ISR__INTC_MASK EQU 0x08 +SCSI_RST_ISR__INTC_NUMBER EQU 3 SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SCSI_SEL_ISR */ SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_SEL_ISR__INTC_MASK EQU 0x08 -SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_MASK EQU 0x20 +SCSI_SEL_ISR__INTC_NUMBER EQU 5 SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2826,6 +2840,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2833,74 +2849,78 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB15_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB15_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK +SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST /* SCSI_CTL_PHASE */ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK /* SCSI_Glitch_Ctl */ SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK /* SCSI_Parity_Error */ SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST /* Miscellaneous */ BCLK__BUS_CLK__HZ EQU 50000000 BCLK__BUS_CLK__KHZ EQU 50000 BCLK__BUS_CLK__MHZ EQU 50 CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PSOC4A EQU 18 +CYDEV_CHIP_DIE_PSOC4A EQU 26 CYDEV_CHIP_DIE_PSOC5LP EQU 2 CYDEV_CHIP_DIE_PSOC5TM EQU 3 CYDEV_CHIP_DIE_TMA4 EQU 4 @@ -2916,34 +2936,43 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x2E133069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 18 -CYDEV_CHIP_MEMBER_4D EQU 13 +CYDEV_CHIP_MEMBER_4A EQU 26 +CYDEV_CHIP_MEMBER_4AA EQU 25 +CYDEV_CHIP_MEMBER_4AB EQU 30 +CYDEV_CHIP_MEMBER_4AC EQU 14 +CYDEV_CHIP_MEMBER_4AD EQU 15 +CYDEV_CHIP_MEMBER_4AE EQU 16 +CYDEV_CHIP_MEMBER_4D EQU 20 CYDEV_CHIP_MEMBER_4E EQU 6 -CYDEV_CHIP_MEMBER_4F EQU 19 +CYDEV_CHIP_MEMBER_4F EQU 27 CYDEV_CHIP_MEMBER_4G EQU 4 -CYDEV_CHIP_MEMBER_4H EQU 17 -CYDEV_CHIP_MEMBER_4I EQU 23 -CYDEV_CHIP_MEMBER_4J EQU 14 -CYDEV_CHIP_MEMBER_4K EQU 15 -CYDEV_CHIP_MEMBER_4L EQU 22 -CYDEV_CHIP_MEMBER_4M EQU 21 -CYDEV_CHIP_MEMBER_4N EQU 10 -CYDEV_CHIP_MEMBER_4O EQU 7 -CYDEV_CHIP_MEMBER_4P EQU 20 -CYDEV_CHIP_MEMBER_4Q EQU 12 -CYDEV_CHIP_MEMBER_4R EQU 8 -CYDEV_CHIP_MEMBER_4S EQU 11 -CYDEV_CHIP_MEMBER_4T EQU 9 +CYDEV_CHIP_MEMBER_4H EQU 24 +CYDEV_CHIP_MEMBER_4I EQU 32 +CYDEV_CHIP_MEMBER_4J EQU 21 +CYDEV_CHIP_MEMBER_4K EQU 22 +CYDEV_CHIP_MEMBER_4L EQU 31 +CYDEV_CHIP_MEMBER_4M EQU 29 +CYDEV_CHIP_MEMBER_4N EQU 11 +CYDEV_CHIP_MEMBER_4O EQU 8 +CYDEV_CHIP_MEMBER_4P EQU 28 +CYDEV_CHIP_MEMBER_4Q EQU 17 +CYDEV_CHIP_MEMBER_4R EQU 9 +CYDEV_CHIP_MEMBER_4S EQU 12 +CYDEV_CHIP_MEMBER_4T EQU 10 CYDEV_CHIP_MEMBER_4U EQU 5 -CYDEV_CHIP_MEMBER_4V EQU 16 +CYDEV_CHIP_MEMBER_4V EQU 23 +CYDEV_CHIP_MEMBER_4W EQU 13 +CYDEV_CHIP_MEMBER_4X EQU 7 +CYDEV_CHIP_MEMBER_4Y EQU 18 +CYDEV_CHIP_MEMBER_4Z EQU 19 CYDEV_CHIP_MEMBER_5A EQU 3 CYDEV_CHIP_MEMBER_5B EQU 2 -CYDEV_CHIP_MEMBER_6A EQU 24 -CYDEV_CHIP_MEMBER_FM3 EQU 28 -CYDEV_CHIP_MEMBER_FM4 EQU 29 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 +CYDEV_CHIP_MEMBER_6A EQU 33 +CYDEV_CHIP_MEMBER_FM3 EQU 37 +CYDEV_CHIP_MEMBER_FM4 EQU 38 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 34 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 35 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 36 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED @@ -2968,6 +2997,11 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 CYDEV_CHIP_REVISION_4A_ES0 EQU 17 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4AA_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4AB_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4AC_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4AD_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4AE_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 @@ -2992,6 +3026,10 @@ CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4W_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4X_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Y_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Z_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 @@ -3031,7 +3069,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x0400 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x0000007F +CYDEV_INTR_RISING EQU 0x000001FF CYDEV_IS_EXPORTING_CODE EQU 0 CYDEV_IS_IMPORTING_CODE EQU 0 CYDEV_PROJ_TYPE EQU 2 @@ -3084,7 +3122,7 @@ CYIPBLOCK_S8_IRQ_VERSION EQU 0 CYIPBLOCK_S8_SAR_VERSION EQU 0 CYIPBLOCK_S8_SIO_VERSION EQU 0 CYIPBLOCK_S8_UDB_VERSION EQU 0 -DMA_CHANNELS_USED__MASK0 EQU 0x0000000F +DMA_CHANNELS_USED__MASK0 EQU 0x0000003F CYDEV_BOOTLOADER_ENABLE EQU 0 #endif /* INCLUDED_CYFITTERIAR_INC */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index 5ddb795..8641b07 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -1,13 +1,13 @@ ; ; File Name: cyfitterrv.inc ; -; PSoC Creator 4.2 +; PSoC Creator 4.4 ; ; Description: ; ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. @@ -191,34 +191,34 @@ USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_1__INTC_MASK EQU 0x80 -USBFS_ep_1__INTC_NUMBER EQU 7 +USBFS_ep_1__INTC_MASK EQU 0x200 +USBFS_ep_1__INTC_NUMBER EQU 9 USBFS_ep_1__INTC_PRIOR_NUM EQU 7 -USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_2__INTC_MASK EQU 0x100 -USBFS_ep_2__INTC_NUMBER EQU 8 +USBFS_ep_2__INTC_MASK EQU 0x400 +USBFS_ep_2__INTC_NUMBER EQU 10 USBFS_ep_2__INTC_PRIOR_NUM EQU 7 -USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_3__INTC_MASK EQU 0x200 -USBFS_ep_3__INTC_NUMBER EQU 9 +USBFS_ep_3__INTC_MASK EQU 0x800 +USBFS_ep_3__INTC_NUMBER EQU 11 USBFS_ep_3__INTC_PRIOR_NUM EQU 7 -USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_11 USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -USBFS_ep_4__INTC_MASK EQU 0x400 -USBFS_ep_4__INTC_NUMBER EQU 10 +USBFS_ep_4__INTC_MASK EQU 0x2000 +USBFS_ep_4__INTC_NUMBER EQU 13 USBFS_ep_4__INTC_PRIOR_NUM EQU 7 -USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_13 USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -423,32 +423,32 @@ NOR_SO__SHIFT EQU 2 NOR_SO__SLW EQU CYREG_PRT15_SLW ; SDCard -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB04_ST SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 @@ -459,11 +459,7 @@ SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK -SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL -SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 @@ -482,12 +478,12 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -495,9 +491,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST ; SD_SCK SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 @@ -533,30 +529,6 @@ SD_SCK__PS EQU CYREG_PRT3_PS SD_SCK__SHIFT EQU 1 SD_SCK__SLW EQU CYREG_PRT3_SLW -; NOR_CTL -NOR_CTL_Sync_ctrl_reg__0__MASK EQU 0x01 -NOR_CTL_Sync_ctrl_reg__0__POS EQU 0 -NOR_CTL_Sync_ctrl_reg__1__MASK EQU 0x02 -NOR_CTL_Sync_ctrl_reg__1__POS EQU 1 -NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL -NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL -NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL -NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK -NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK -NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK -NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL -NOR_CTL_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB06_CTL -NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL -NOR_CTL_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB06_CTL -NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL -NOR_CTL_Sync_ctrl_reg__MASK EQU 0x03 -NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL -NOR_CTL_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB06_MSK - ; NOR_SCK NOR_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE7 NOR_SCK__0__MASK EQU 0x80 @@ -592,34 +564,34 @@ NOR_SCK__SHIFT EQU 7 NOR_SCK__SLW EQU CYREG_PRT3_SLW ; NOR_SPI -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL -NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK -NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK -NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL -NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL -NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL -NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL -NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK -NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL -NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST -NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK -NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL -NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST -NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL -NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10 NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4 NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20 @@ -627,9 +599,9 @@ NOR_SPI_BSPIM_RxStsReg__5__POS EQU 5 NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40 NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6 NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70 -NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK -NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL -NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST +NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 @@ -647,6 +619,8 @@ NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0 NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01 NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0 NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02 @@ -1783,15 +1757,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1804,35 +1778,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB09_MSK SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE @@ -2292,42 +2266,42 @@ NOR_Clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 NOR_Clock__PM_STBY_MSK EQU 0x01 ; SD_RX_DMA -SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SD_RX_DMA__DRQ_NUMBER EQU 2 +SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL1 +SD_RX_DMA__DRQ_NUMBER EQU 4 SD_RX_DMA__NUMBEROF_TDS EQU 0 SD_RX_DMA__PRIORITY EQU 0 SD_RX_DMA__TERMIN_EN EQU 0 SD_RX_DMA__TERMIN_SEL EQU 0 SD_RX_DMA__TERMOUT0_EN EQU 1 -SD_RX_DMA__TERMOUT0_SEL EQU 2 +SD_RX_DMA__TERMOUT0_SEL EQU 4 SD_RX_DMA__TERMOUT1_EN EQU 0 SD_RX_DMA__TERMOUT1_SEL EQU 0 SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20 -SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5 +SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x80 +SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 7 SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 +SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SD_TX_DMA -SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SD_TX_DMA__DRQ_NUMBER EQU 3 +SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL1 +SD_TX_DMA__DRQ_NUMBER EQU 5 SD_TX_DMA__NUMBEROF_TDS EQU 0 SD_TX_DMA__PRIORITY EQU 1 SD_TX_DMA__TERMIN_EN EQU 0 SD_TX_DMA__TERMIN_SEL EQU 0 SD_TX_DMA__TERMOUT0_EN EQU 1 -SD_TX_DMA__TERMOUT0_SEL EQU 3 +SD_TX_DMA__TERMOUT0_SEL EQU 5 SD_TX_DMA__TERMOUT1_EN EQU 0 SD_TX_DMA__TERMOUT1_SEL EQU 0 SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 -SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6 +SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x100 +SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 8 SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 +SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2364,6 +2338,46 @@ nNOR_HOLD__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN nNOR_HOLD__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ nNOR_HOLD__SLW EQU CYREG_PRT12_SLW +; NOR_RX_DMA +NOR_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +NOR_RX_DMA__DRQ_NUMBER EQU 0 +NOR_RX_DMA__NUMBEROF_TDS EQU 0 +NOR_RX_DMA__PRIORITY EQU 2 +NOR_RX_DMA__TERMIN_EN EQU 0 +NOR_RX_DMA__TERMIN_SEL EQU 0 +NOR_RX_DMA__TERMOUT0_EN EQU 1 +NOR_RX_DMA__TERMOUT0_SEL EQU 0 +NOR_RX_DMA__TERMOUT1_EN EQU 0 +NOR_RX_DMA__TERMOUT1_SEL EQU 0 +NOR_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +NOR_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +NOR_RX_DMA_COMPLETE__INTC_MASK EQU 0x02 +NOR_RX_DMA_COMPLETE__INTC_NUMBER EQU 1 +NOR_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +NOR_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +NOR_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +NOR_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; NOR_TX_DMA +NOR_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +NOR_TX_DMA__DRQ_NUMBER EQU 1 +NOR_TX_DMA__NUMBEROF_TDS EQU 0 +NOR_TX_DMA__PRIORITY EQU 2 +NOR_TX_DMA__TERMIN_EN EQU 0 +NOR_TX_DMA__TERMIN_SEL EQU 0 +NOR_TX_DMA__TERMOUT0_EN EQU 1 +NOR_TX_DMA__TERMOUT0_SEL EQU 1 +NOR_TX_DMA__TERMOUT1_EN EQU 0 +NOR_TX_DMA__TERMOUT1_SEL EQU 0 +NOR_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +NOR_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +NOR_TX_DMA_COMPLETE__INTC_MASK EQU 0x04 +NOR_TX_DMA_COMPLETE__INTC_NUMBER EQU 2 +NOR_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +NOR_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +NOR_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +NOR_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + ; SCSI_Noise SCSI_Noise__0__AG EQU CYREG_PRT4_AG SCSI_Noise__0__AMUX EQU CYREG_PRT4_AMUX @@ -2696,8 +2710,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 -scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2705,13 +2719,13 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK -scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST ; Debug_Timer Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2741,41 +2755,41 @@ Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 ; SCSI_RX_DMA SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__DRQ_NUMBER EQU 2 SCSI_RX_DMA__NUMBEROF_TDS EQU 0 SCSI_RX_DMA__PRIORITY EQU 2 SCSI_RX_DMA__TERMIN_EN EQU 0 SCSI_RX_DMA__TERMIN_SEL EQU 0 SCSI_RX_DMA__TERMOUT0_EN EQU 1 -SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_SEL EQU 2 SCSI_RX_DMA__TERMOUT1_EN EQU 0 SCSI_RX_DMA__TERMOUT1_SEL EQU 0 SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 -SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 4 SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_TX_DMA SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 -SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__DRQ_NUMBER EQU 3 SCSI_TX_DMA__NUMBEROF_TDS EQU 0 SCSI_TX_DMA__PRIORITY EQU 2 SCSI_TX_DMA__TERMIN_EN EQU 0 SCSI_TX_DMA__TERMIN_SEL EQU 0 SCSI_TX_DMA__TERMOUT0_EN EQU 1 -SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 3 SCSI_TX_DMA__TERMOUT1_EN EQU 0 SCSI_TX_DMA__TERMOUT1_SEL EQU 0 SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 -SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 6 SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 -SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2804,20 +2818,20 @@ timer_clock__PM_STBY_MSK EQU 0x08 ; SCSI_RST_ISR SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_RST_ISR__INTC_MASK EQU 0x02 -SCSI_RST_ISR__INTC_NUMBER EQU 1 +SCSI_RST_ISR__INTC_MASK EQU 0x08 +SCSI_RST_ISR__INTC_NUMBER EQU 3 SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SCSI_SEL_ISR SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 -SCSI_SEL_ISR__INTC_MASK EQU 0x08 -SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_MASK EQU 0x20 +SCSI_SEL_ISR__INTC_NUMBER EQU 5 SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 -SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 @@ -2826,6 +2840,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2833,74 +2849,78 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB15_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB15_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK +SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST ; SCSI_CTL_PHASE SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK -SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK ; SCSI_Glitch_Ctl SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK ; SCSI_Parity_Error SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST ; Miscellaneous BCLK__BUS_CLK__HZ EQU 50000000 BCLK__BUS_CLK__KHZ EQU 50000 BCLK__BUS_CLK__MHZ EQU 50 CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PSOC4A EQU 18 +CYDEV_CHIP_DIE_PSOC4A EQU 26 CYDEV_CHIP_DIE_PSOC5LP EQU 2 CYDEV_CHIP_DIE_PSOC5TM EQU 3 CYDEV_CHIP_DIE_TMA4 EQU 4 @@ -2916,34 +2936,43 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x2E133069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 18 -CYDEV_CHIP_MEMBER_4D EQU 13 +CYDEV_CHIP_MEMBER_4A EQU 26 +CYDEV_CHIP_MEMBER_4AA EQU 25 +CYDEV_CHIP_MEMBER_4AB EQU 30 +CYDEV_CHIP_MEMBER_4AC EQU 14 +CYDEV_CHIP_MEMBER_4AD EQU 15 +CYDEV_CHIP_MEMBER_4AE EQU 16 +CYDEV_CHIP_MEMBER_4D EQU 20 CYDEV_CHIP_MEMBER_4E EQU 6 -CYDEV_CHIP_MEMBER_4F EQU 19 +CYDEV_CHIP_MEMBER_4F EQU 27 CYDEV_CHIP_MEMBER_4G EQU 4 -CYDEV_CHIP_MEMBER_4H EQU 17 -CYDEV_CHIP_MEMBER_4I EQU 23 -CYDEV_CHIP_MEMBER_4J EQU 14 -CYDEV_CHIP_MEMBER_4K EQU 15 -CYDEV_CHIP_MEMBER_4L EQU 22 -CYDEV_CHIP_MEMBER_4M EQU 21 -CYDEV_CHIP_MEMBER_4N EQU 10 -CYDEV_CHIP_MEMBER_4O EQU 7 -CYDEV_CHIP_MEMBER_4P EQU 20 -CYDEV_CHIP_MEMBER_4Q EQU 12 -CYDEV_CHIP_MEMBER_4R EQU 8 -CYDEV_CHIP_MEMBER_4S EQU 11 -CYDEV_CHIP_MEMBER_4T EQU 9 +CYDEV_CHIP_MEMBER_4H EQU 24 +CYDEV_CHIP_MEMBER_4I EQU 32 +CYDEV_CHIP_MEMBER_4J EQU 21 +CYDEV_CHIP_MEMBER_4K EQU 22 +CYDEV_CHIP_MEMBER_4L EQU 31 +CYDEV_CHIP_MEMBER_4M EQU 29 +CYDEV_CHIP_MEMBER_4N EQU 11 +CYDEV_CHIP_MEMBER_4O EQU 8 +CYDEV_CHIP_MEMBER_4P EQU 28 +CYDEV_CHIP_MEMBER_4Q EQU 17 +CYDEV_CHIP_MEMBER_4R EQU 9 +CYDEV_CHIP_MEMBER_4S EQU 12 +CYDEV_CHIP_MEMBER_4T EQU 10 CYDEV_CHIP_MEMBER_4U EQU 5 -CYDEV_CHIP_MEMBER_4V EQU 16 +CYDEV_CHIP_MEMBER_4V EQU 23 +CYDEV_CHIP_MEMBER_4W EQU 13 +CYDEV_CHIP_MEMBER_4X EQU 7 +CYDEV_CHIP_MEMBER_4Y EQU 18 +CYDEV_CHIP_MEMBER_4Z EQU 19 CYDEV_CHIP_MEMBER_5A EQU 3 CYDEV_CHIP_MEMBER_5B EQU 2 -CYDEV_CHIP_MEMBER_6A EQU 24 -CYDEV_CHIP_MEMBER_FM3 EQU 28 -CYDEV_CHIP_MEMBER_FM4 EQU 29 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 +CYDEV_CHIP_MEMBER_6A EQU 33 +CYDEV_CHIP_MEMBER_FM3 EQU 37 +CYDEV_CHIP_MEMBER_FM4 EQU 38 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 34 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 35 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 36 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED @@ -2968,6 +2997,11 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 CYDEV_CHIP_REVISION_4A_ES0 EQU 17 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4AA_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4AB_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4AC_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4AD_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4AE_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 @@ -2992,6 +3026,10 @@ CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4W_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4X_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Y_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Z_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 @@ -3031,7 +3069,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 CYDEV_ECC_ENABLE EQU 0 CYDEV_HEAP_SIZE EQU 0x0400 CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 -CYDEV_INTR_RISING EQU 0x0000007F +CYDEV_INTR_RISING EQU 0x000001FF CYDEV_IS_EXPORTING_CODE EQU 0 CYDEV_IS_IMPORTING_CODE EQU 0 CYDEV_PROJ_TYPE EQU 2 @@ -3084,7 +3122,7 @@ CYIPBLOCK_S8_IRQ_VERSION EQU 0 CYIPBLOCK_S8_SAR_VERSION EQU 0 CYIPBLOCK_S8_SIO_VERSION EQU 0 CYIPBLOCK_S8_UDB_VERSION EQU 0 -DMA_CHANNELS_USED__MASK0 EQU 0x0000000F +DMA_CHANNELS_USED__MASK0 EQU 0x0000003F CYDEV_BOOTLOADER_ENABLE EQU 0 ENDIF END diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c index 82ddcb0..9664407 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cymetadata.c * -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * This file defines all extra memory spaces that need to be included. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index fde38ec..b9c3435 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: project.h * -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * It contains references to all generated header files and should not be modified. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -81,11 +81,14 @@ #include "nNOR_HOLD.h" #include "NOR_SI_aliases.h" #include "NOR_SI.h" -#include "NOR_CTL.h" #include "nNOR_CS_aliases.h" #include "nNOR_CS.h" #include "nNOR_WP_aliases.h" #include "nNOR_WP.h" +#include "NOR_RX_DMA_dma.h" +#include "NOR_TX_DMA_dma.h" +#include "NOR_RX_DMA_COMPLETE.h" +#include "NOR_TX_DMA_COMPLETE.h" #include "USBFS_Dm_aliases.h" #include "USBFS_Dm.h" #include "USBFS_Dp_aliases.h" diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx index d68d1f5..ef7bdae 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -1,20 +1,20 @@ - \ No newline at end of file diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyfit index c3ea79e..6dec319 100644 Binary files a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyfit differ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyprj index b52eef2..068706b 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyprj +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyprj @@ -151,6 +151,20 @@ + + + + + + + + + + + + + + @@ -322,6 +336,20 @@ + + + + + + + + + + + + + + @@ -2503,27 +2531,27 @@ - + - + - + - + @@ -2599,6 +2627,110 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -3207,8 +3339,8 @@ - - + + diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.svd index 9c0eed5..11866b9 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.svd +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.svd @@ -19,7 +19,7 @@ SCSI_Glitch_Ctl_CONTROL_REG No description available - 0x4000647D + 0x4000647A 8 read-write 0 @@ -28,7 +28,7 @@ - SCSI_Parity_Error + SCSI_Filtered No description available 0x0 @@ -38,27 +38,27 @@ - SCSI_Parity_Error_STATUS_REG + SCSI_Filtered_STATUS_REG No description available - 0x4000646B + 0x40006468 8 read-write 0 0 - SCSI_Parity_Error_MASK_REG + SCSI_Filtered_MASK_REG No description available - 0x4000648B + 0x40006488 8 read-write 0 0 - SCSI_Parity_Error_STATUS_AUX_CTL_REG + SCSI_Filtered_STATUS_AUX_CTL_REG No description available - 0x4000649B + 0x40006498 8 read-write 0 @@ -183,7 +183,7 @@ - SCSI_Filtered + SCSI_Parity_Error No description available 0x0 @@ -193,27 +193,27 @@ - SCSI_Filtered_STATUS_REG + SCSI_Parity_Error_STATUS_REG No description available - 0x4000646F + 0x40006469 8 read-write 0 0 - SCSI_Filtered_MASK_REG + SCSI_Parity_Error_MASK_REG No description available - 0x4000648F + 0x40006489 8 read-write 0 0 - SCSI_Filtered_STATUS_AUX_CTL_REG + SCSI_Parity_Error_STATUS_AUX_CTL_REG No description available - 0x4000649F + 0x40006499 8 read-write 0 @@ -337,27 +337,6 @@ - - NOR_CTL - No description available - 0x0 - - 0 - 0x0 - registers - - - - NOR_CTL_CONTROL_REG - No description available - 0x40006576 - 8 - read-write - 0 - 0 - - - SCSI_CTL_PHASE No description available @@ -371,7 +350,7 @@ SCSI_CTL_PHASE_CONTROL_REG No description available - 0x4000647C + 0x4000647B 8 read-write 0 @@ -2617,27 +2596,6 @@ - - SCSI_Out_Ctl - No description available - 0x0 - - 0 - 0x0 - registers - - - - SCSI_Out_Ctl_CONTROL_REG - No description available - 0x40006473 - 8 - read-write - 0 - 0 - - - Debug_Timer No description available @@ -2943,7 +2901,28 @@ SCSI_Out_Bits_CONTROL_REG No description available - 0x40006479 + 0x40006579 + 8 + read-write + 0 + 0 + + + + + SCSI_Out_Ctl + No description available + 0x0 + + 0 + 0x0 + registers + + + + SCSI_Out_Ctl_CONTROL_REG + No description available + 0x40006478 8 read-write 0 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index e4871d0..700ec84 100644 Binary files a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.c index 76594e2..2c1528f 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.c +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: LED.c -* Version 2.10 +* Version 2.20 * * Description: * This file contains API to enable firmware control of a Pins component. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -24,19 +24,37 @@ /******************************************************************************* * Function Name: LED_Write -******************************************************************************** +****************************************************************************//** * -* Summary: -* Assign a new value to the digital port's data output register. +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. * -* Parameters: -* prtValue: The value to be assigned to the Digital Port. +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). * -* Return: -* None -* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet LED_SUT.c usage_LED_Write *******************************************************************************/ -void LED_Write(uint8 value) +void LED_Write(uint8 value) { uint8 staticBits = (LED_DR & (uint8)(~LED_MASK)); LED_DR = staticBits | ((uint8)(value << LED_SHIFT) & LED_MASK); @@ -45,28 +63,31 @@ void LED_Write(uint8 value) /******************************************************************************* * Function Name: LED_SetDriveMode -******************************************************************************** +****************************************************************************//** * -* Summary: -* Change the drive mode on the pins of the port. +* \brief Sets the drive mode for each of the Pins component's pins. * -* Parameters: -* mode: Change the pins to one of the following drive modes. -* -* LED_DM_STRONG Strong Drive -* LED_DM_OD_HI Open Drain, Drives High -* LED_DM_OD_LO Open Drain, Drives Low -* LED_DM_RES_UP Resistive Pull Up -* LED_DM_RES_DWN Resistive Pull Down -* LED_DM_RES_UPDWN Resistive Pull Up/Down -* LED_DM_DIG_HIZ High Impedance Digital -* LED_DM_ALG_HIZ High Impedance Analog -* -* Return: +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return * None * +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet LED_SUT.c usage_LED_SetDriveMode *******************************************************************************/ -void LED_SetDriveMode(uint8 mode) +void LED_SetDriveMode(uint8 mode) { CyPins_SetPinDriveMode(LED_0, mode); CyPins_SetPinDriveMode(LED_1, mode); @@ -75,23 +96,22 @@ void LED_SetDriveMode(uint8 mode) /******************************************************************************* * Function Name: LED_Read -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value on the pins of the Digital Port in right justified -* form. +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The pin's status register returns the current logic level present on the +* physical pin. * -* Return: -* Returns the current value of the Digital Port as a right justified number -* -* Note: -* Macro LED_ReadPS calls this function. -* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet LED_SUT.c usage_LED_Read *******************************************************************************/ -uint8 LED_Read(void) +uint8 LED_Read(void) { return (LED_PS & LED_MASK) >> LED_SHIFT; } @@ -99,42 +119,106 @@ uint8 LED_Read(void) /******************************************************************************* * Function Name: LED_ReadDataReg -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value assigned to a Digital Port's data output register +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred LED_Read() API because the +* LED_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. * -* Return: -* Returns the current value assigned to the Digital Port's data output register -* +* \funcusage +* \snippet LED_SUT.c usage_LED_ReadDataReg *******************************************************************************/ -uint8 LED_ReadDataReg(void) +uint8 LED_ReadDataReg(void) { return (LED_DR & LED_MASK) >> LED_SHIFT; } -/* If Interrupts Are Enabled for this Pins component */ +/* If interrupt is connected for this Pins component */ #if defined(LED_INTSTAT) + /******************************************************************************* + * Function Name: LED_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use LED_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - LED_0_INTR (First pin in the list) + * - LED_1_INTR (Second pin in the list) + * - ... + * - LED_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet LED_SUT.c usage_LED_SetInterruptMode + *******************************************************************************/ + void LED_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & LED_0_INTR) != 0u) + { + LED_0_INTTYPE_REG = (uint8)mode; + } + if((position & LED_1_INTR) != 0u) + { + LED_1_INTTYPE_REG = (uint8)mode; + } + } + + /******************************************************************************* * Function Name: LED_ClearInterrupt - ******************************************************************************** - * Summary: - * Clears any active interrupts attached to port and returns the value of the - * interrupt status register. + ****************************************************************************//** * - * Parameters: - * None + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. * - * Return: - * Returns the value of the interrupt status register + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet LED_SUT.c usage_LED_ClearInterrupt *******************************************************************************/ - uint8 LED_ClearInterrupt(void) + uint8 LED_ClearInterrupt(void) { return (LED_INTSTAT & LED_MASK) >> LED_SHIFT; } diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.h index d29df9e..69e72b2 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.h +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: LED.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains Pin function prototypes and register defines * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -22,12 +22,6 @@ #include "cypins.h" #include "LED_aliases.h" -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component cy_pins_v2_10 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ - /* APIs are not generated for P15[7:6] */ #if !(CY_PSOC5A &&\ LED__PORT == 15 && ((LED__MASK & 0xC0) != 0)) @@ -37,32 +31,65 @@ * Function Prototypes ***************************************/ -void LED_Write(uint8 value) ; -void LED_SetDriveMode(uint8 mode) ; -uint8 LED_ReadDataReg(void) ; -uint8 LED_Read(void) ; -uint8 LED_ClearInterrupt(void) ; - +/** +* \addtogroup group_general +* @{ +*/ +void LED_Write(uint8 value); +void LED_SetDriveMode(uint8 mode); +uint8 LED_ReadDataReg(void); +uint8 LED_Read(void); +void LED_SetInterruptMode(uint16 position, uint16 mode); +uint8 LED_ClearInterrupt(void); +/** @} general */ /*************************************** * API Constants ***************************************/ - -/* Drive Modes */ -#define LED_DM_ALG_HIZ PIN_DM_ALG_HIZ -#define LED_DM_DIG_HIZ PIN_DM_DIG_HIZ -#define LED_DM_RES_UP PIN_DM_RES_UP -#define LED_DM_RES_DWN PIN_DM_RES_DWN -#define LED_DM_OD_LO PIN_DM_OD_LO -#define LED_DM_OD_HI PIN_DM_OD_HI -#define LED_DM_STRONG PIN_DM_STRONG -#define LED_DM_RES_UPDWN PIN_DM_RES_UPDWN - +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the LED_SetDriveMode() function. + * @{ + */ + #define LED_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define LED_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define LED_DM_RES_UP PIN_DM_RES_UP + #define LED_DM_RES_DWN PIN_DM_RES_DWN + #define LED_DM_OD_LO PIN_DM_OD_LO + #define LED_DM_OD_HI PIN_DM_OD_HI + #define LED_DM_STRONG PIN_DM_STRONG + #define LED_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + /* Digital Port Constants */ #define LED_MASK LED__MASK #define LED_SHIFT LED__SHIFT #define LED_WIDTH 2u +/* Interrupt constants */ +#if defined(LED__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in LED_SetInterruptMode() function. + * @{ + */ + #define LED_INTR_NONE (uint16)(0x0000u) + #define LED_INTR_RISING (uint16)(0x0001u) + #define LED_INTR_FALLING (uint16)(0x0002u) + #define LED_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define LED_INTR_MASK (0x01u) +#endif /* (LED__INTSTAT) */ + /*************************************** * Registers @@ -114,13 +141,22 @@ uint8 LED_ClearInterrupt(void) ; /* Sync Output Enable Registers */ #define LED_PRTDSI__SYNC_OUT (* (reg8 *) LED__PRTDSI__SYNC_OUT) - -#if defined(LED__INTSTAT) /* Interrupt Registers */ - - #define LED_INTSTAT (* (reg8 *) LED__INTSTAT) - #define LED_SNAP (* (reg8 *) LED__SNAP) - -#endif /* Interrupt Registers */ +/* SIO registers */ +#if defined(LED__SIO_CFG) + #define LED_SIO_HYST_EN (* (reg8 *) LED__SIO_HYST_EN) + #define LED_SIO_REG_HIFREQ (* (reg8 *) LED__SIO_REG_HIFREQ) + #define LED_SIO_CFG (* (reg8 *) LED__SIO_CFG) + #define LED_SIO_DIFF (* (reg8 *) LED__SIO_DIFF) +#endif /* (LED__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(LED__INTSTAT) + #define LED_INTSTAT (* (reg8 *) LED__INTSTAT) + #define LED_SNAP (* (reg8 *) LED__SNAP) + + #define LED_0_INTTYPE_REG (* (reg8 *) LED__0__INTTYPE) + #define LED_1_INTTYPE_REG (* (reg8 *) LED__1__INTTYPE) +#endif /* (LED__INTSTAT) */ #endif /* CY_PSOC5A... */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED_aliases.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED_aliases.h index 6ba9bb4..19916b0 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED_aliases.h +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: LED.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,13 +22,18 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define LED_0 (LED__0__PC) -#define LED_1 (LED__1__PC) +#define LED_0 (LED__0__PC) +#define LED_0_INTR ((uint16)((uint16)0x0001u << LED__0__SHIFT)) + +#define LED_1 (LED__1__PC) +#define LED_1_INTR ((uint16)((uint16)0x0001u << LED__1__SHIFT)) + +#define LED_INTR_ALL ((uint16)(LED_0_INTR| LED_1_INTR)) #endif /* End Pins LED_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h index 6fcc5f6..6006db5 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: SCSI_Out_DBx.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,28 +22,59 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define SCSI_Out_DBx_0 (SCSI_Out_DBx__0__PC) -#define SCSI_Out_DBx_1 (SCSI_Out_DBx__1__PC) -#define SCSI_Out_DBx_2 (SCSI_Out_DBx__2__PC) -#define SCSI_Out_DBx_3 (SCSI_Out_DBx__3__PC) -#define SCSI_Out_DBx_4 (SCSI_Out_DBx__4__PC) -#define SCSI_Out_DBx_5 (SCSI_Out_DBx__5__PC) -#define SCSI_Out_DBx_6 (SCSI_Out_DBx__6__PC) -#define SCSI_Out_DBx_7 (SCSI_Out_DBx__7__PC) - -#define SCSI_Out_DBx_DB0 (SCSI_Out_DBx__DB0__PC) -#define SCSI_Out_DBx_DB1 (SCSI_Out_DBx__DB1__PC) -#define SCSI_Out_DBx_DB2 (SCSI_Out_DBx__DB2__PC) -#define SCSI_Out_DBx_DB3 (SCSI_Out_DBx__DB3__PC) -#define SCSI_Out_DBx_DB4 (SCSI_Out_DBx__DB4__PC) -#define SCSI_Out_DBx_DB5 (SCSI_Out_DBx__DB5__PC) -#define SCSI_Out_DBx_DB6 (SCSI_Out_DBx__DB6__PC) -#define SCSI_Out_DBx_DB7 (SCSI_Out_DBx__DB7__PC) +#define SCSI_Out_DBx_0 (SCSI_Out_DBx__0__PC) +#define SCSI_Out_DBx_0_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__0__SHIFT)) + +#define SCSI_Out_DBx_1 (SCSI_Out_DBx__1__PC) +#define SCSI_Out_DBx_1_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__1__SHIFT)) + +#define SCSI_Out_DBx_2 (SCSI_Out_DBx__2__PC) +#define SCSI_Out_DBx_2_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__2__SHIFT)) + +#define SCSI_Out_DBx_3 (SCSI_Out_DBx__3__PC) +#define SCSI_Out_DBx_3_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__3__SHIFT)) + +#define SCSI_Out_DBx_4 (SCSI_Out_DBx__4__PC) +#define SCSI_Out_DBx_4_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__4__SHIFT)) + +#define SCSI_Out_DBx_5 (SCSI_Out_DBx__5__PC) +#define SCSI_Out_DBx_5_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__5__SHIFT)) + +#define SCSI_Out_DBx_6 (SCSI_Out_DBx__6__PC) +#define SCSI_Out_DBx_6_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__6__SHIFT)) + +#define SCSI_Out_DBx_7 (SCSI_Out_DBx__7__PC) +#define SCSI_Out_DBx_7_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__7__SHIFT)) + +#define SCSI_Out_DBx_INTR_ALL ((uint16)(SCSI_Out_DBx_0_INTR| SCSI_Out_DBx_1_INTR| SCSI_Out_DBx_2_INTR| SCSI_Out_DBx_3_INTR| SCSI_Out_DBx_4_INTR| SCSI_Out_DBx_5_INTR| SCSI_Out_DBx_6_INTR| SCSI_Out_DBx_7_INTR)) +#define SCSI_Out_DBx_DB0 (SCSI_Out_DBx__DB0__PC) +#define SCSI_Out_DBx_DB0_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__0__SHIFT)) + +#define SCSI_Out_DBx_DB1 (SCSI_Out_DBx__DB1__PC) +#define SCSI_Out_DBx_DB1_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__1__SHIFT)) + +#define SCSI_Out_DBx_DB2 (SCSI_Out_DBx__DB2__PC) +#define SCSI_Out_DBx_DB2_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__2__SHIFT)) + +#define SCSI_Out_DBx_DB3 (SCSI_Out_DBx__DB3__PC) +#define SCSI_Out_DBx_DB3_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__3__SHIFT)) + +#define SCSI_Out_DBx_DB4 (SCSI_Out_DBx__DB4__PC) +#define SCSI_Out_DBx_DB4_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__4__SHIFT)) + +#define SCSI_Out_DBx_DB5 (SCSI_Out_DBx__DB5__PC) +#define SCSI_Out_DBx_DB5_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__5__SHIFT)) + +#define SCSI_Out_DBx_DB6 (SCSI_Out_DBx__DB6__PC) +#define SCSI_Out_DBx_DB6_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__6__SHIFT)) + +#define SCSI_Out_DBx_DB7 (SCSI_Out_DBx__DB7__PC) +#define SCSI_Out_DBx_DB7_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__7__SHIFT)) #endif /* End Pins SCSI_Out_DBx_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h index a06c1fa..4f819a8 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: SCSI_Out.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,28 +22,59 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define SCSI_Out_0 (SCSI_Out__0__PC) -#define SCSI_Out_1 (SCSI_Out__1__PC) -#define SCSI_Out_2 (SCSI_Out__2__PC) -#define SCSI_Out_3 (SCSI_Out__3__PC) -#define SCSI_Out_4 (SCSI_Out__4__PC) -#define SCSI_Out_5 (SCSI_Out__5__PC) -#define SCSI_Out_6 (SCSI_Out__6__PC) -#define SCSI_Out_7 (SCSI_Out__7__PC) - -#define SCSI_Out_DBP_raw (SCSI_Out__DBP_raw__PC) -#define SCSI_Out_BSY (SCSI_Out__BSY__PC) -#define SCSI_Out_RST (SCSI_Out__RST__PC) -#define SCSI_Out_MSG (SCSI_Out__MSG__PC) -#define SCSI_Out_SEL (SCSI_Out__SEL__PC) -#define SCSI_Out_CD (SCSI_Out__CD__PC) -#define SCSI_Out_REQ (SCSI_Out__REQ__PC) -#define SCSI_Out_IO_raw (SCSI_Out__IO_raw__PC) +#define SCSI_Out_0 (SCSI_Out__0__PC) +#define SCSI_Out_0_INTR ((uint16)((uint16)0x0001u << SCSI_Out__0__SHIFT)) + +#define SCSI_Out_1 (SCSI_Out__1__PC) +#define SCSI_Out_1_INTR ((uint16)((uint16)0x0001u << SCSI_Out__1__SHIFT)) + +#define SCSI_Out_2 (SCSI_Out__2__PC) +#define SCSI_Out_2_INTR ((uint16)((uint16)0x0001u << SCSI_Out__2__SHIFT)) + +#define SCSI_Out_3 (SCSI_Out__3__PC) +#define SCSI_Out_3_INTR ((uint16)((uint16)0x0001u << SCSI_Out__3__SHIFT)) + +#define SCSI_Out_4 (SCSI_Out__4__PC) +#define SCSI_Out_4_INTR ((uint16)((uint16)0x0001u << SCSI_Out__4__SHIFT)) + +#define SCSI_Out_5 (SCSI_Out__5__PC) +#define SCSI_Out_5_INTR ((uint16)((uint16)0x0001u << SCSI_Out__5__SHIFT)) + +#define SCSI_Out_6 (SCSI_Out__6__PC) +#define SCSI_Out_6_INTR ((uint16)((uint16)0x0001u << SCSI_Out__6__SHIFT)) + +#define SCSI_Out_7 (SCSI_Out__7__PC) +#define SCSI_Out_7_INTR ((uint16)((uint16)0x0001u << SCSI_Out__7__SHIFT)) + +#define SCSI_Out_INTR_ALL ((uint16)(SCSI_Out_0_INTR| SCSI_Out_1_INTR| SCSI_Out_2_INTR| SCSI_Out_3_INTR| SCSI_Out_4_INTR| SCSI_Out_5_INTR| SCSI_Out_6_INTR| SCSI_Out_7_INTR)) +#define SCSI_Out_DBP_raw (SCSI_Out__DBP_raw__PC) +#define SCSI_Out_DBP_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__0__SHIFT)) + +#define SCSI_Out_BSY (SCSI_Out__BSY__PC) +#define SCSI_Out_BSY_INTR ((uint16)((uint16)0x0001u << SCSI_Out__1__SHIFT)) + +#define SCSI_Out_RST (SCSI_Out__RST__PC) +#define SCSI_Out_RST_INTR ((uint16)((uint16)0x0001u << SCSI_Out__2__SHIFT)) + +#define SCSI_Out_MSG (SCSI_Out__MSG__PC) +#define SCSI_Out_MSG_INTR ((uint16)((uint16)0x0001u << SCSI_Out__3__SHIFT)) + +#define SCSI_Out_SEL (SCSI_Out__SEL__PC) +#define SCSI_Out_SEL_INTR ((uint16)((uint16)0x0001u << SCSI_Out__4__SHIFT)) + +#define SCSI_Out_CD (SCSI_Out__CD__PC) +#define SCSI_Out_CD_INTR ((uint16)((uint16)0x0001u << SCSI_Out__5__SHIFT)) + +#define SCSI_Out_REQ (SCSI_Out__REQ__PC) +#define SCSI_Out_REQ_INTR ((uint16)((uint16)0x0001u << SCSI_Out__6__SHIFT)) + +#define SCSI_Out_IO_raw (SCSI_Out__IO_raw__PC) +#define SCSI_Out_IO_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__7__SHIFT)) #endif /* End Pins SCSI_Out_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c index fb427cc..98b86f0 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SD_PULLUP.c -* Version 2.10 +* Version 2.20 * * Description: * This file contains API to enable firmware control of a Pins component. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -24,19 +24,37 @@ /******************************************************************************* * Function Name: SD_PULLUP_Write -******************************************************************************** +****************************************************************************//** * -* Summary: -* Assign a new value to the digital port's data output register. +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. * -* Parameters: -* prtValue: The value to be assigned to the Digital Port. +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). * -* Return: -* None -* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SD_PULLUP_SUT.c usage_SD_PULLUP_Write *******************************************************************************/ -void SD_PULLUP_Write(uint8 value) +void SD_PULLUP_Write(uint8 value) { uint8 staticBits = (SD_PULLUP_DR & (uint8)(~SD_PULLUP_MASK)); SD_PULLUP_DR = staticBits | ((uint8)(value << SD_PULLUP_SHIFT) & SD_PULLUP_MASK); @@ -45,28 +63,31 @@ void SD_PULLUP_Write(uint8 value) /******************************************************************************* * Function Name: SD_PULLUP_SetDriveMode -******************************************************************************** +****************************************************************************//** * -* Summary: -* Change the drive mode on the pins of the port. +* \brief Sets the drive mode for each of the Pins component's pins. * -* Parameters: -* mode: Change the pins to one of the following drive modes. -* -* SD_PULLUP_DM_STRONG Strong Drive -* SD_PULLUP_DM_OD_HI Open Drain, Drives High -* SD_PULLUP_DM_OD_LO Open Drain, Drives Low -* SD_PULLUP_DM_RES_UP Resistive Pull Up -* SD_PULLUP_DM_RES_DWN Resistive Pull Down -* SD_PULLUP_DM_RES_UPDWN Resistive Pull Up/Down -* SD_PULLUP_DM_DIG_HIZ High Impedance Digital -* SD_PULLUP_DM_ALG_HIZ High Impedance Analog -* -* Return: +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return * None * +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SD_PULLUP_SUT.c usage_SD_PULLUP_SetDriveMode *******************************************************************************/ -void SD_PULLUP_SetDriveMode(uint8 mode) +void SD_PULLUP_SetDriveMode(uint8 mode) { CyPins_SetPinDriveMode(SD_PULLUP_0, mode); CyPins_SetPinDriveMode(SD_PULLUP_1, mode); @@ -77,23 +98,22 @@ void SD_PULLUP_SetDriveMode(uint8 mode) /******************************************************************************* * Function Name: SD_PULLUP_Read -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value on the pins of the Digital Port in right justified -* form. +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The pin's status register returns the current logic level present on the +* physical pin. * -* Return: -* Returns the current value of the Digital Port as a right justified number -* -* Note: -* Macro SD_PULLUP_ReadPS calls this function. -* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SD_PULLUP_SUT.c usage_SD_PULLUP_Read *******************************************************************************/ -uint8 SD_PULLUP_Read(void) +uint8 SD_PULLUP_Read(void) { return (SD_PULLUP_PS & SD_PULLUP_MASK) >> SD_PULLUP_SHIFT; } @@ -101,42 +121,114 @@ uint8 SD_PULLUP_Read(void) /******************************************************************************* * Function Name: SD_PULLUP_ReadDataReg -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value assigned to a Digital Port's data output register +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SD_PULLUP_Read() API because the +* SD_PULLUP_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. * -* Return: -* Returns the current value assigned to the Digital Port's data output register -* +* \funcusage +* \snippet SD_PULLUP_SUT.c usage_SD_PULLUP_ReadDataReg *******************************************************************************/ -uint8 SD_PULLUP_ReadDataReg(void) +uint8 SD_PULLUP_ReadDataReg(void) { return (SD_PULLUP_DR & SD_PULLUP_MASK) >> SD_PULLUP_SHIFT; } -/* If Interrupts Are Enabled for this Pins component */ +/* If interrupt is connected for this Pins component */ #if defined(SD_PULLUP_INTSTAT) + /******************************************************************************* + * Function Name: SD_PULLUP_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SD_PULLUP_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SD_PULLUP_0_INTR (First pin in the list) + * - SD_PULLUP_1_INTR (Second pin in the list) + * - ... + * - SD_PULLUP_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SD_PULLUP_SUT.c usage_SD_PULLUP_SetInterruptMode + *******************************************************************************/ + void SD_PULLUP_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SD_PULLUP_0_INTR) != 0u) + { + SD_PULLUP_0_INTTYPE_REG = (uint8)mode; + } + if((position & SD_PULLUP_1_INTR) != 0u) + { + SD_PULLUP_1_INTTYPE_REG = (uint8)mode; + } + if((position & SD_PULLUP_2_INTR) != 0u) + { + SD_PULLUP_2_INTTYPE_REG = (uint8)mode; + } + if((position & SD_PULLUP_3_INTR) != 0u) + { + SD_PULLUP_3_INTTYPE_REG = (uint8)mode; + } + } + + /******************************************************************************* * Function Name: SD_PULLUP_ClearInterrupt - ******************************************************************************** - * Summary: - * Clears any active interrupts attached to port and returns the value of the - * interrupt status register. + ****************************************************************************//** * - * Parameters: - * None + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. * - * Return: - * Returns the value of the interrupt status register + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SD_PULLUP_SUT.c usage_SD_PULLUP_ClearInterrupt *******************************************************************************/ - uint8 SD_PULLUP_ClearInterrupt(void) + uint8 SD_PULLUP_ClearInterrupt(void) { return (SD_PULLUP_INTSTAT & SD_PULLUP_MASK) >> SD_PULLUP_SHIFT; } diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h index 4090a3b..0849775 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: SD_PULLUP.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains Pin function prototypes and register defines * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -22,12 +22,6 @@ #include "cypins.h" #include "SD_PULLUP_aliases.h" -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component cy_pins_v2_10 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ - /* APIs are not generated for P15[7:6] */ #if !(CY_PSOC5A &&\ SD_PULLUP__PORT == 15 && ((SD_PULLUP__MASK & 0xC0) != 0)) @@ -37,32 +31,65 @@ * Function Prototypes ***************************************/ -void SD_PULLUP_Write(uint8 value) ; -void SD_PULLUP_SetDriveMode(uint8 mode) ; -uint8 SD_PULLUP_ReadDataReg(void) ; -uint8 SD_PULLUP_Read(void) ; -uint8 SD_PULLUP_ClearInterrupt(void) ; - +/** +* \addtogroup group_general +* @{ +*/ +void SD_PULLUP_Write(uint8 value); +void SD_PULLUP_SetDriveMode(uint8 mode); +uint8 SD_PULLUP_ReadDataReg(void); +uint8 SD_PULLUP_Read(void); +void SD_PULLUP_SetInterruptMode(uint16 position, uint16 mode); +uint8 SD_PULLUP_ClearInterrupt(void); +/** @} general */ /*************************************** * API Constants ***************************************/ - -/* Drive Modes */ -#define SD_PULLUP_DM_ALG_HIZ PIN_DM_ALG_HIZ -#define SD_PULLUP_DM_DIG_HIZ PIN_DM_DIG_HIZ -#define SD_PULLUP_DM_RES_UP PIN_DM_RES_UP -#define SD_PULLUP_DM_RES_DWN PIN_DM_RES_DWN -#define SD_PULLUP_DM_OD_LO PIN_DM_OD_LO -#define SD_PULLUP_DM_OD_HI PIN_DM_OD_HI -#define SD_PULLUP_DM_STRONG PIN_DM_STRONG -#define SD_PULLUP_DM_RES_UPDWN PIN_DM_RES_UPDWN - +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SD_PULLUP_SetDriveMode() function. + * @{ + */ + #define SD_PULLUP_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SD_PULLUP_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SD_PULLUP_DM_RES_UP PIN_DM_RES_UP + #define SD_PULLUP_DM_RES_DWN PIN_DM_RES_DWN + #define SD_PULLUP_DM_OD_LO PIN_DM_OD_LO + #define SD_PULLUP_DM_OD_HI PIN_DM_OD_HI + #define SD_PULLUP_DM_STRONG PIN_DM_STRONG + #define SD_PULLUP_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + /* Digital Port Constants */ #define SD_PULLUP_MASK SD_PULLUP__MASK #define SD_PULLUP_SHIFT SD_PULLUP__SHIFT #define SD_PULLUP_WIDTH 4u +/* Interrupt constants */ +#if defined(SD_PULLUP__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SD_PULLUP_SetInterruptMode() function. + * @{ + */ + #define SD_PULLUP_INTR_NONE (uint16)(0x0000u) + #define SD_PULLUP_INTR_RISING (uint16)(0x0001u) + #define SD_PULLUP_INTR_FALLING (uint16)(0x0002u) + #define SD_PULLUP_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SD_PULLUP_INTR_MASK (0x01u) +#endif /* (SD_PULLUP__INTSTAT) */ + /*************************************** * Registers @@ -114,13 +141,24 @@ uint8 SD_PULLUP_ClearInterrupt(void) ; /* Sync Output Enable Registers */ #define SD_PULLUP_PRTDSI__SYNC_OUT (* (reg8 *) SD_PULLUP__PRTDSI__SYNC_OUT) - -#if defined(SD_PULLUP__INTSTAT) /* Interrupt Registers */ - - #define SD_PULLUP_INTSTAT (* (reg8 *) SD_PULLUP__INTSTAT) - #define SD_PULLUP_SNAP (* (reg8 *) SD_PULLUP__SNAP) - -#endif /* Interrupt Registers */ +/* SIO registers */ +#if defined(SD_PULLUP__SIO_CFG) + #define SD_PULLUP_SIO_HYST_EN (* (reg8 *) SD_PULLUP__SIO_HYST_EN) + #define SD_PULLUP_SIO_REG_HIFREQ (* (reg8 *) SD_PULLUP__SIO_REG_HIFREQ) + #define SD_PULLUP_SIO_CFG (* (reg8 *) SD_PULLUP__SIO_CFG) + #define SD_PULLUP_SIO_DIFF (* (reg8 *) SD_PULLUP__SIO_DIFF) +#endif /* (SD_PULLUP__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(SD_PULLUP__INTSTAT) + #define SD_PULLUP_INTSTAT (* (reg8 *) SD_PULLUP__INTSTAT) + #define SD_PULLUP_SNAP (* (reg8 *) SD_PULLUP__SNAP) + + #define SD_PULLUP_0_INTTYPE_REG (* (reg8 *) SD_PULLUP__0__INTTYPE) + #define SD_PULLUP_1_INTTYPE_REG (* (reg8 *) SD_PULLUP__1__INTTYPE) + #define SD_PULLUP_2_INTTYPE_REG (* (reg8 *) SD_PULLUP__2__INTTYPE) + #define SD_PULLUP_3_INTTYPE_REG (* (reg8 *) SD_PULLUP__3__INTTYPE) +#endif /* (SD_PULLUP__INTSTAT) */ #endif /* CY_PSOC5A... */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h index 32f544b..5fd27b2 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: SD_PULLUP.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,15 +22,24 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define SD_PULLUP_0 (SD_PULLUP__0__PC) -#define SD_PULLUP_1 (SD_PULLUP__1__PC) -#define SD_PULLUP_2 (SD_PULLUP__2__PC) -#define SD_PULLUP_3 (SD_PULLUP__3__PC) +#define SD_PULLUP_0 (SD_PULLUP__0__PC) +#define SD_PULLUP_0_INTR ((uint16)((uint16)0x0001u << SD_PULLUP__0__SHIFT)) + +#define SD_PULLUP_1 (SD_PULLUP__1__PC) +#define SD_PULLUP_1_INTR ((uint16)((uint16)0x0001u << SD_PULLUP__1__SHIFT)) + +#define SD_PULLUP_2 (SD_PULLUP__2__PC) +#define SD_PULLUP_2_INTR ((uint16)((uint16)0x0001u << SD_PULLUP__2__SHIFT)) + +#define SD_PULLUP_3 (SD_PULLUP__3__PC) +#define SD_PULLUP_3_INTR ((uint16)((uint16)0x0001u << SD_PULLUP__3__SHIFT)) + +#define SD_PULLUP_INTR_ALL ((uint16)(SD_PULLUP_0_INTR| SD_PULLUP_1_INTR| SD_PULLUP_2_INTR| SD_PULLUP_3_INTR)) #endif /* End Pins SD_PULLUP_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP.c index d6b0e46..d25a8fe 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP.c +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SPI_PULLUP.c -* Version 2.10 +* Version 2.20 * * Description: * This file contains API to enable firmware control of a Pins component. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -24,19 +24,37 @@ /******************************************************************************* * Function Name: SPI_PULLUP_Write -******************************************************************************** +****************************************************************************//** * -* Summary: -* Assign a new value to the digital port's data output register. +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. * -* Parameters: -* prtValue: The value to be assigned to the Digital Port. +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). * -* Return: -* None -* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SPI_PULLUP_SUT.c usage_SPI_PULLUP_Write *******************************************************************************/ -void SPI_PULLUP_Write(uint8 value) +void SPI_PULLUP_Write(uint8 value) { uint8 staticBits = (SPI_PULLUP_DR & (uint8)(~SPI_PULLUP_MASK)); SPI_PULLUP_DR = staticBits | ((uint8)(value << SPI_PULLUP_SHIFT) & SPI_PULLUP_MASK); @@ -45,28 +63,31 @@ void SPI_PULLUP_Write(uint8 value) /******************************************************************************* * Function Name: SPI_PULLUP_SetDriveMode -******************************************************************************** +****************************************************************************//** * -* Summary: -* Change the drive mode on the pins of the port. +* \brief Sets the drive mode for each of the Pins component's pins. * -* Parameters: -* mode: Change the pins to one of the following drive modes. -* -* SPI_PULLUP_DM_STRONG Strong Drive -* SPI_PULLUP_DM_OD_HI Open Drain, Drives High -* SPI_PULLUP_DM_OD_LO Open Drain, Drives Low -* SPI_PULLUP_DM_RES_UP Resistive Pull Up -* SPI_PULLUP_DM_RES_DWN Resistive Pull Down -* SPI_PULLUP_DM_RES_UPDWN Resistive Pull Up/Down -* SPI_PULLUP_DM_DIG_HIZ High Impedance Digital -* SPI_PULLUP_DM_ALG_HIZ High Impedance Analog -* -* Return: +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return * None * +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SPI_PULLUP_SUT.c usage_SPI_PULLUP_SetDriveMode *******************************************************************************/ -void SPI_PULLUP_SetDriveMode(uint8 mode) +void SPI_PULLUP_SetDriveMode(uint8 mode) { CyPins_SetPinDriveMode(SPI_PULLUP_0, mode); CyPins_SetPinDriveMode(SPI_PULLUP_1, mode); @@ -77,23 +98,22 @@ void SPI_PULLUP_SetDriveMode(uint8 mode) /******************************************************************************* * Function Name: SPI_PULLUP_Read -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value on the pins of the Digital Port in right justified -* form. +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The pin's status register returns the current logic level present on the +* physical pin. * -* Return: -* Returns the current value of the Digital Port as a right justified number -* -* Note: -* Macro SPI_PULLUP_ReadPS calls this function. -* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SPI_PULLUP_SUT.c usage_SPI_PULLUP_Read *******************************************************************************/ -uint8 SPI_PULLUP_Read(void) +uint8 SPI_PULLUP_Read(void) { return (SPI_PULLUP_PS & SPI_PULLUP_MASK) >> SPI_PULLUP_SHIFT; } @@ -101,42 +121,114 @@ uint8 SPI_PULLUP_Read(void) /******************************************************************************* * Function Name: SPI_PULLUP_ReadDataReg -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value assigned to a Digital Port's data output register +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SPI_PULLUP_Read() API because the +* SPI_PULLUP_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. * -* Return: -* Returns the current value assigned to the Digital Port's data output register -* +* \funcusage +* \snippet SPI_PULLUP_SUT.c usage_SPI_PULLUP_ReadDataReg *******************************************************************************/ -uint8 SPI_PULLUP_ReadDataReg(void) +uint8 SPI_PULLUP_ReadDataReg(void) { return (SPI_PULLUP_DR & SPI_PULLUP_MASK) >> SPI_PULLUP_SHIFT; } -/* If Interrupts Are Enabled for this Pins component */ +/* If interrupt is connected for this Pins component */ #if defined(SPI_PULLUP_INTSTAT) + /******************************************************************************* + * Function Name: SPI_PULLUP_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SPI_PULLUP_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SPI_PULLUP_0_INTR (First pin in the list) + * - SPI_PULLUP_1_INTR (Second pin in the list) + * - ... + * - SPI_PULLUP_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SPI_PULLUP_SUT.c usage_SPI_PULLUP_SetInterruptMode + *******************************************************************************/ + void SPI_PULLUP_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SPI_PULLUP_0_INTR) != 0u) + { + SPI_PULLUP_0_INTTYPE_REG = (uint8)mode; + } + if((position & SPI_PULLUP_1_INTR) != 0u) + { + SPI_PULLUP_1_INTTYPE_REG = (uint8)mode; + } + if((position & SPI_PULLUP_2_INTR) != 0u) + { + SPI_PULLUP_2_INTTYPE_REG = (uint8)mode; + } + if((position & SPI_PULLUP_3_INTR) != 0u) + { + SPI_PULLUP_3_INTTYPE_REG = (uint8)mode; + } + } + + /******************************************************************************* * Function Name: SPI_PULLUP_ClearInterrupt - ******************************************************************************** - * Summary: - * Clears any active interrupts attached to port and returns the value of the - * interrupt status register. + ****************************************************************************//** * - * Parameters: - * None + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. * - * Return: - * Returns the value of the interrupt status register + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SPI_PULLUP_SUT.c usage_SPI_PULLUP_ClearInterrupt *******************************************************************************/ - uint8 SPI_PULLUP_ClearInterrupt(void) + uint8 SPI_PULLUP_ClearInterrupt(void) { return (SPI_PULLUP_INTSTAT & SPI_PULLUP_MASK) >> SPI_PULLUP_SHIFT; } diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP.h index 6f2c043..06a32aa 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP.h +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: SPI_PULLUP.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains Pin function prototypes and register defines * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -22,12 +22,6 @@ #include "cypins.h" #include "SPI_PULLUP_aliases.h" -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component cy_pins_v2_10 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ - /* APIs are not generated for P15[7:6] */ #if !(CY_PSOC5A &&\ SPI_PULLUP__PORT == 15 && ((SPI_PULLUP__MASK & 0xC0) != 0)) @@ -37,32 +31,65 @@ * Function Prototypes ***************************************/ -void SPI_PULLUP_Write(uint8 value) ; -void SPI_PULLUP_SetDriveMode(uint8 mode) ; -uint8 SPI_PULLUP_ReadDataReg(void) ; -uint8 SPI_PULLUP_Read(void) ; -uint8 SPI_PULLUP_ClearInterrupt(void) ; - +/** +* \addtogroup group_general +* @{ +*/ +void SPI_PULLUP_Write(uint8 value); +void SPI_PULLUP_SetDriveMode(uint8 mode); +uint8 SPI_PULLUP_ReadDataReg(void); +uint8 SPI_PULLUP_Read(void); +void SPI_PULLUP_SetInterruptMode(uint16 position, uint16 mode); +uint8 SPI_PULLUP_ClearInterrupt(void); +/** @} general */ /*************************************** * API Constants ***************************************/ - -/* Drive Modes */ -#define SPI_PULLUP_DM_ALG_HIZ PIN_DM_ALG_HIZ -#define SPI_PULLUP_DM_DIG_HIZ PIN_DM_DIG_HIZ -#define SPI_PULLUP_DM_RES_UP PIN_DM_RES_UP -#define SPI_PULLUP_DM_RES_DWN PIN_DM_RES_DWN -#define SPI_PULLUP_DM_OD_LO PIN_DM_OD_LO -#define SPI_PULLUP_DM_OD_HI PIN_DM_OD_HI -#define SPI_PULLUP_DM_STRONG PIN_DM_STRONG -#define SPI_PULLUP_DM_RES_UPDWN PIN_DM_RES_UPDWN - +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SPI_PULLUP_SetDriveMode() function. + * @{ + */ + #define SPI_PULLUP_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SPI_PULLUP_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SPI_PULLUP_DM_RES_UP PIN_DM_RES_UP + #define SPI_PULLUP_DM_RES_DWN PIN_DM_RES_DWN + #define SPI_PULLUP_DM_OD_LO PIN_DM_OD_LO + #define SPI_PULLUP_DM_OD_HI PIN_DM_OD_HI + #define SPI_PULLUP_DM_STRONG PIN_DM_STRONG + #define SPI_PULLUP_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + /* Digital Port Constants */ #define SPI_PULLUP_MASK SPI_PULLUP__MASK #define SPI_PULLUP_SHIFT SPI_PULLUP__SHIFT #define SPI_PULLUP_WIDTH 4u +/* Interrupt constants */ +#if defined(SPI_PULLUP__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SPI_PULLUP_SetInterruptMode() function. + * @{ + */ + #define SPI_PULLUP_INTR_NONE (uint16)(0x0000u) + #define SPI_PULLUP_INTR_RISING (uint16)(0x0001u) + #define SPI_PULLUP_INTR_FALLING (uint16)(0x0002u) + #define SPI_PULLUP_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SPI_PULLUP_INTR_MASK (0x01u) +#endif /* (SPI_PULLUP__INTSTAT) */ + /*************************************** * Registers @@ -114,13 +141,24 @@ uint8 SPI_PULLUP_ClearInterrupt(void) ; /* Sync Output Enable Registers */ #define SPI_PULLUP_PRTDSI__SYNC_OUT (* (reg8 *) SPI_PULLUP__PRTDSI__SYNC_OUT) - -#if defined(SPI_PULLUP__INTSTAT) /* Interrupt Registers */ - - #define SPI_PULLUP_INTSTAT (* (reg8 *) SPI_PULLUP__INTSTAT) - #define SPI_PULLUP_SNAP (* (reg8 *) SPI_PULLUP__SNAP) - -#endif /* Interrupt Registers */ +/* SIO registers */ +#if defined(SPI_PULLUP__SIO_CFG) + #define SPI_PULLUP_SIO_HYST_EN (* (reg8 *) SPI_PULLUP__SIO_HYST_EN) + #define SPI_PULLUP_SIO_REG_HIFREQ (* (reg8 *) SPI_PULLUP__SIO_REG_HIFREQ) + #define SPI_PULLUP_SIO_CFG (* (reg8 *) SPI_PULLUP__SIO_CFG) + #define SPI_PULLUP_SIO_DIFF (* (reg8 *) SPI_PULLUP__SIO_DIFF) +#endif /* (SPI_PULLUP__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(SPI_PULLUP__INTSTAT) + #define SPI_PULLUP_INTSTAT (* (reg8 *) SPI_PULLUP__INTSTAT) + #define SPI_PULLUP_SNAP (* (reg8 *) SPI_PULLUP__SNAP) + + #define SPI_PULLUP_0_INTTYPE_REG (* (reg8 *) SPI_PULLUP__0__INTTYPE) + #define SPI_PULLUP_1_INTTYPE_REG (* (reg8 *) SPI_PULLUP__1__INTTYPE) + #define SPI_PULLUP_2_INTTYPE_REG (* (reg8 *) SPI_PULLUP__2__INTTYPE) + #define SPI_PULLUP_3_INTTYPE_REG (* (reg8 *) SPI_PULLUP__3__INTTYPE) +#endif /* (SPI_PULLUP__INTSTAT) */ #endif /* CY_PSOC5A... */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1.c index 55aa560..e3d8a78 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1.c +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1.c @@ -1,6 +1,6 @@ /******************************************************************************* * File Name: SPI_PULLUP_1.c -* Version 2.10 +* Version 2.20 * * Description: * This file contains API to enable firmware control of a Pins component. @@ -8,7 +8,7 @@ * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -24,19 +24,37 @@ /******************************************************************************* * Function Name: SPI_PULLUP_1_Write -******************************************************************************** +****************************************************************************//** * -* Summary: -* Assign a new value to the digital port's data output register. +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. * -* Parameters: -* prtValue: The value to be assigned to the Digital Port. +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). * -* Return: -* None -* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SPI_PULLUP_1_SUT.c usage_SPI_PULLUP_1_Write *******************************************************************************/ -void SPI_PULLUP_1_Write(uint8 value) +void SPI_PULLUP_1_Write(uint8 value) { uint8 staticBits = (SPI_PULLUP_1_DR & (uint8)(~SPI_PULLUP_1_MASK)); SPI_PULLUP_1_DR = staticBits | ((uint8)(value << SPI_PULLUP_1_SHIFT) & SPI_PULLUP_1_MASK); @@ -45,28 +63,31 @@ void SPI_PULLUP_1_Write(uint8 value) /******************************************************************************* * Function Name: SPI_PULLUP_1_SetDriveMode -******************************************************************************** +****************************************************************************//** * -* Summary: -* Change the drive mode on the pins of the port. +* \brief Sets the drive mode for each of the Pins component's pins. * -* Parameters: -* mode: Change the pins to one of the following drive modes. -* -* SPI_PULLUP_1_DM_STRONG Strong Drive -* SPI_PULLUP_1_DM_OD_HI Open Drain, Drives High -* SPI_PULLUP_1_DM_OD_LO Open Drain, Drives Low -* SPI_PULLUP_1_DM_RES_UP Resistive Pull Up -* SPI_PULLUP_1_DM_RES_DWN Resistive Pull Down -* SPI_PULLUP_1_DM_RES_UPDWN Resistive Pull Up/Down -* SPI_PULLUP_1_DM_DIG_HIZ High Impedance Digital -* SPI_PULLUP_1_DM_ALG_HIZ High Impedance Analog -* -* Return: +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return * None * +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SPI_PULLUP_1_SUT.c usage_SPI_PULLUP_1_SetDriveMode *******************************************************************************/ -void SPI_PULLUP_1_SetDriveMode(uint8 mode) +void SPI_PULLUP_1_SetDriveMode(uint8 mode) { CyPins_SetPinDriveMode(SPI_PULLUP_1_0, mode); CyPins_SetPinDriveMode(SPI_PULLUP_1_1, mode); @@ -75,23 +96,22 @@ void SPI_PULLUP_1_SetDriveMode(uint8 mode) /******************************************************************************* * Function Name: SPI_PULLUP_1_Read -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value on the pins of the Digital Port in right justified -* form. +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The pin's status register returns the current logic level present on the +* physical pin. * -* Return: -* Returns the current value of the Digital Port as a right justified number -* -* Note: -* Macro SPI_PULLUP_1_ReadPS calls this function. -* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SPI_PULLUP_1_SUT.c usage_SPI_PULLUP_1_Read *******************************************************************************/ -uint8 SPI_PULLUP_1_Read(void) +uint8 SPI_PULLUP_1_Read(void) { return (SPI_PULLUP_1_PS & SPI_PULLUP_1_MASK) >> SPI_PULLUP_1_SHIFT; } @@ -99,42 +119,106 @@ uint8 SPI_PULLUP_1_Read(void) /******************************************************************************* * Function Name: SPI_PULLUP_1_ReadDataReg -******************************************************************************** +****************************************************************************//** * -* Summary: -* Read the current value assigned to a Digital Port's data output register +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. * -* Parameters: -* None +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SPI_PULLUP_1_Read() API because the +* SPI_PULLUP_1_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. * -* Return: -* Returns the current value assigned to the Digital Port's data output register -* +* \funcusage +* \snippet SPI_PULLUP_1_SUT.c usage_SPI_PULLUP_1_ReadDataReg *******************************************************************************/ -uint8 SPI_PULLUP_1_ReadDataReg(void) +uint8 SPI_PULLUP_1_ReadDataReg(void) { return (SPI_PULLUP_1_DR & SPI_PULLUP_1_MASK) >> SPI_PULLUP_1_SHIFT; } -/* If Interrupts Are Enabled for this Pins component */ +/* If interrupt is connected for this Pins component */ #if defined(SPI_PULLUP_1_INTSTAT) + /******************************************************************************* + * Function Name: SPI_PULLUP_1_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SPI_PULLUP_1_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SPI_PULLUP_1_0_INTR (First pin in the list) + * - SPI_PULLUP_1_1_INTR (Second pin in the list) + * - ... + * - SPI_PULLUP_1_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SPI_PULLUP_1_SUT.c usage_SPI_PULLUP_1_SetInterruptMode + *******************************************************************************/ + void SPI_PULLUP_1_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SPI_PULLUP_1_0_INTR) != 0u) + { + SPI_PULLUP_1_0_INTTYPE_REG = (uint8)mode; + } + if((position & SPI_PULLUP_1_1_INTR) != 0u) + { + SPI_PULLUP_1_1_INTTYPE_REG = (uint8)mode; + } + } + + /******************************************************************************* * Function Name: SPI_PULLUP_1_ClearInterrupt - ******************************************************************************** - * Summary: - * Clears any active interrupts attached to port and returns the value of the - * interrupt status register. + ****************************************************************************//** * - * Parameters: - * None + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. * - * Return: - * Returns the value of the interrupt status register + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SPI_PULLUP_1_SUT.c usage_SPI_PULLUP_1_ClearInterrupt *******************************************************************************/ - uint8 SPI_PULLUP_1_ClearInterrupt(void) + uint8 SPI_PULLUP_1_ClearInterrupt(void) { return (SPI_PULLUP_1_INTSTAT & SPI_PULLUP_1_MASK) >> SPI_PULLUP_1_SHIFT; } diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1.h index 7b83fd4..44b83b6 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1.h +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: SPI_PULLUP_1.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains Pin function prototypes and register defines * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -22,12 +22,6 @@ #include "cypins.h" #include "SPI_PULLUP_1_aliases.h" -/* Check to see if required defines such as CY_PSOC5A are available */ -/* They are defined starting with cy_boot v3.0 */ -#if !defined (CY_PSOC5A) - #error Component cy_pins_v2_10 requires cy_boot v3.0 or later -#endif /* (CY_PSOC5A) */ - /* APIs are not generated for P15[7:6] */ #if !(CY_PSOC5A &&\ SPI_PULLUP_1__PORT == 15 && ((SPI_PULLUP_1__MASK & 0xC0) != 0)) @@ -37,32 +31,65 @@ * Function Prototypes ***************************************/ -void SPI_PULLUP_1_Write(uint8 value) ; -void SPI_PULLUP_1_SetDriveMode(uint8 mode) ; -uint8 SPI_PULLUP_1_ReadDataReg(void) ; -uint8 SPI_PULLUP_1_Read(void) ; -uint8 SPI_PULLUP_1_ClearInterrupt(void) ; - +/** +* \addtogroup group_general +* @{ +*/ +void SPI_PULLUP_1_Write(uint8 value); +void SPI_PULLUP_1_SetDriveMode(uint8 mode); +uint8 SPI_PULLUP_1_ReadDataReg(void); +uint8 SPI_PULLUP_1_Read(void); +void SPI_PULLUP_1_SetInterruptMode(uint16 position, uint16 mode); +uint8 SPI_PULLUP_1_ClearInterrupt(void); +/** @} general */ /*************************************** * API Constants ***************************************/ - -/* Drive Modes */ -#define SPI_PULLUP_1_DM_ALG_HIZ PIN_DM_ALG_HIZ -#define SPI_PULLUP_1_DM_DIG_HIZ PIN_DM_DIG_HIZ -#define SPI_PULLUP_1_DM_RES_UP PIN_DM_RES_UP -#define SPI_PULLUP_1_DM_RES_DWN PIN_DM_RES_DWN -#define SPI_PULLUP_1_DM_OD_LO PIN_DM_OD_LO -#define SPI_PULLUP_1_DM_OD_HI PIN_DM_OD_HI -#define SPI_PULLUP_1_DM_STRONG PIN_DM_STRONG -#define SPI_PULLUP_1_DM_RES_UPDWN PIN_DM_RES_UPDWN - +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SPI_PULLUP_1_SetDriveMode() function. + * @{ + */ + #define SPI_PULLUP_1_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SPI_PULLUP_1_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SPI_PULLUP_1_DM_RES_UP PIN_DM_RES_UP + #define SPI_PULLUP_1_DM_RES_DWN PIN_DM_RES_DWN + #define SPI_PULLUP_1_DM_OD_LO PIN_DM_OD_LO + #define SPI_PULLUP_1_DM_OD_HI PIN_DM_OD_HI + #define SPI_PULLUP_1_DM_STRONG PIN_DM_STRONG + #define SPI_PULLUP_1_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + /* Digital Port Constants */ #define SPI_PULLUP_1_MASK SPI_PULLUP_1__MASK #define SPI_PULLUP_1_SHIFT SPI_PULLUP_1__SHIFT #define SPI_PULLUP_1_WIDTH 2u +/* Interrupt constants */ +#if defined(SPI_PULLUP_1__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SPI_PULLUP_1_SetInterruptMode() function. + * @{ + */ + #define SPI_PULLUP_1_INTR_NONE (uint16)(0x0000u) + #define SPI_PULLUP_1_INTR_RISING (uint16)(0x0001u) + #define SPI_PULLUP_1_INTR_FALLING (uint16)(0x0002u) + #define SPI_PULLUP_1_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SPI_PULLUP_1_INTR_MASK (0x01u) +#endif /* (SPI_PULLUP_1__INTSTAT) */ + /*************************************** * Registers @@ -114,13 +141,22 @@ uint8 SPI_PULLUP_1_ClearInterrupt(void) ; /* Sync Output Enable Registers */ #define SPI_PULLUP_1_PRTDSI__SYNC_OUT (* (reg8 *) SPI_PULLUP_1__PRTDSI__SYNC_OUT) - -#if defined(SPI_PULLUP_1__INTSTAT) /* Interrupt Registers */ - - #define SPI_PULLUP_1_INTSTAT (* (reg8 *) SPI_PULLUP_1__INTSTAT) - #define SPI_PULLUP_1_SNAP (* (reg8 *) SPI_PULLUP_1__SNAP) - -#endif /* Interrupt Registers */ +/* SIO registers */ +#if defined(SPI_PULLUP_1__SIO_CFG) + #define SPI_PULLUP_1_SIO_HYST_EN (* (reg8 *) SPI_PULLUP_1__SIO_HYST_EN) + #define SPI_PULLUP_1_SIO_REG_HIFREQ (* (reg8 *) SPI_PULLUP_1__SIO_REG_HIFREQ) + #define SPI_PULLUP_1_SIO_CFG (* (reg8 *) SPI_PULLUP_1__SIO_CFG) + #define SPI_PULLUP_1_SIO_DIFF (* (reg8 *) SPI_PULLUP_1__SIO_DIFF) +#endif /* (SPI_PULLUP_1__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(SPI_PULLUP_1__INTSTAT) + #define SPI_PULLUP_1_INTSTAT (* (reg8 *) SPI_PULLUP_1__INTSTAT) + #define SPI_PULLUP_1_SNAP (* (reg8 *) SPI_PULLUP_1__SNAP) + + #define SPI_PULLUP_1_0_INTTYPE_REG (* (reg8 *) SPI_PULLUP_1__0__INTTYPE) + #define SPI_PULLUP_1_1_INTTYPE_REG (* (reg8 *) SPI_PULLUP_1__1__INTTYPE) +#endif /* (SPI_PULLUP_1__INTSTAT) */ #endif /* CY_PSOC5A... */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1_aliases.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1_aliases.h index 7cf3fa9..e5f0204 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1_aliases.h +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: SPI_PULLUP_1.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,13 +22,18 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define SPI_PULLUP_1_0 (SPI_PULLUP_1__0__PC) -#define SPI_PULLUP_1_1 (SPI_PULLUP_1__1__PC) +#define SPI_PULLUP_1_0 (SPI_PULLUP_1__0__PC) +#define SPI_PULLUP_1_0_INTR ((uint16)((uint16)0x0001u << SPI_PULLUP_1__0__SHIFT)) + +#define SPI_PULLUP_1_1 (SPI_PULLUP_1__1__PC) +#define SPI_PULLUP_1_1_INTR ((uint16)((uint16)0x0001u << SPI_PULLUP_1__1__SHIFT)) + +#define SPI_PULLUP_1_INTR_ALL ((uint16)(SPI_PULLUP_1_0_INTR| SPI_PULLUP_1_1_INTR)) #endif /* End Pins SPI_PULLUP_1_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_aliases.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_aliases.h index 3d26b85..e060bf6 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_aliases.h +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_aliases.h @@ -1,14 +1,15 @@ /******************************************************************************* * File Name: SPI_PULLUP.h -* Version 2.10 +* Version 2.20 * * Description: -* This file containts Control Register function prototypes and register defines +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. * * Note: * ******************************************************************************** -* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -21,15 +22,24 @@ #include "cyfitter.h" - /*************************************** * Constants ***************************************/ -#define SPI_PULLUP_0 (SPI_PULLUP__0__PC) -#define SPI_PULLUP_1 (SPI_PULLUP__1__PC) -#define SPI_PULLUP_2 (SPI_PULLUP__2__PC) -#define SPI_PULLUP_3 (SPI_PULLUP__3__PC) +#define SPI_PULLUP_0 (SPI_PULLUP__0__PC) +#define SPI_PULLUP_0_INTR ((uint16)((uint16)0x0001u << SPI_PULLUP__0__SHIFT)) + +#define SPI_PULLUP_1 (SPI_PULLUP__1__PC) +#define SPI_PULLUP_1_INTR ((uint16)((uint16)0x0001u << SPI_PULLUP__1__SHIFT)) + +#define SPI_PULLUP_2 (SPI_PULLUP__2__PC) +#define SPI_PULLUP_2_INTR ((uint16)((uint16)0x0001u << SPI_PULLUP__2__SHIFT)) + +#define SPI_PULLUP_3 (SPI_PULLUP__3__PC) +#define SPI_PULLUP_3_INTR ((uint16)((uint16)0x0001u << SPI_PULLUP__3__SHIFT)) + +#define SPI_PULLUP_INTR_ALL ((uint16)(SPI_PULLUP_0_INTR| SPI_PULLUP_1_INTR| SPI_PULLUP_2_INTR| SPI_PULLUP_3_INTR)) #endif /* End Pins SPI_PULLUP_ALIASES_H */ + /* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h index 59d3e2c..e7a420e 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevice.h * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h index b05fd82..e45bc3e 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevice_trm.h * -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc index 754b960..1346980 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevicegnu.inc * OBSOLETE: Do not use this file. Use the _trm version instead. -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc index e2e2aa7..7877dc7 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cydevicegnu_trm.inc * -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * This file provides all of the address values for the entire PSoC device. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc index 147a861..d8f2a6e 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc @@ -1,13 +1,13 @@ ; ; File Name: cydeviceiar.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 4.2 +; PSoC Creator 4.4 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc index 30429cd..067042d 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc @@ -1,13 +1,13 @@ ; ; File Name: cydeviceiar_trm.inc ; -; PSoC Creator 4.2 +; PSoC Creator 4.4 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc index cff336b..fdafe7a 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc @@ -1,13 +1,13 @@ ; ; File Name: cydevicerv.inc ; OBSOLETE: Do not use this file. Use the _trm version instead. -; PSoC Creator 4.2 +; PSoC Creator 4.4 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc index fc79212..c7a64f2 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc @@ -1,13 +1,13 @@ ; ; File Name: cydevicerv_trm.inc ; -; PSoC Creator 4.2 +; PSoC Creator 4.4 ; ; Description: ; This file provides all of the address values for the entire PSoC device. ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h index f1c21ce..c3fc0eb 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cyfitter.h * -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -1408,7 +1408,7 @@ #define BCLK__BUS_CLK__KHZ 64000U #define BCLK__BUS_CLK__MHZ 64U #define CY_PROJECT_NAME "USB_Bootloader" -#define CY_VERSION "PSoC Creator 4.2" +#define CY_VERSION "PSoC Creator 4.4" #define CYDEV_BOOTLOADER_APPLICATIONS 1u #define CYDEV_BOOTLOADER_CHECKSUM_BASIC 0 #define CYDEV_BOOTLOADER_CHECKSUM_CRC 1 @@ -1420,7 +1420,7 @@ #define CyBtldr_USBFS CYDEV_BOOTLOADER_IO_COMP_USBFS #define CYDEV_BOOTLOADER_IO_COMP CYDEV_BOOTLOADER_IO_COMP_USBFS #define CYDEV_CHIP_DIE_LEOPARD 1u -#define CYDEV_CHIP_DIE_PSOC4A 18u +#define CYDEV_CHIP_DIE_PSOC4A 26u #define CYDEV_CHIP_DIE_PSOC5LP 2u #define CYDEV_CHIP_DIE_PSOC5TM 3u #define CYDEV_CHIP_DIE_TMA4 4u @@ -1436,34 +1436,43 @@ #define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5 #define CYDEV_CHIP_JTAG_ID 0x2E133069u #define CYDEV_CHIP_MEMBER_3A 1u -#define CYDEV_CHIP_MEMBER_4A 18u -#define CYDEV_CHIP_MEMBER_4D 13u +#define CYDEV_CHIP_MEMBER_4A 26u +#define CYDEV_CHIP_MEMBER_4AA 25u +#define CYDEV_CHIP_MEMBER_4AB 30u +#define CYDEV_CHIP_MEMBER_4AC 14u +#define CYDEV_CHIP_MEMBER_4AD 15u +#define CYDEV_CHIP_MEMBER_4AE 16u +#define CYDEV_CHIP_MEMBER_4D 20u #define CYDEV_CHIP_MEMBER_4E 6u -#define CYDEV_CHIP_MEMBER_4F 19u +#define CYDEV_CHIP_MEMBER_4F 27u #define CYDEV_CHIP_MEMBER_4G 4u -#define CYDEV_CHIP_MEMBER_4H 17u -#define CYDEV_CHIP_MEMBER_4I 23u -#define CYDEV_CHIP_MEMBER_4J 14u -#define CYDEV_CHIP_MEMBER_4K 15u -#define CYDEV_CHIP_MEMBER_4L 22u -#define CYDEV_CHIP_MEMBER_4M 21u -#define CYDEV_CHIP_MEMBER_4N 10u -#define CYDEV_CHIP_MEMBER_4O 7u -#define CYDEV_CHIP_MEMBER_4P 20u -#define CYDEV_CHIP_MEMBER_4Q 12u -#define CYDEV_CHIP_MEMBER_4R 8u -#define CYDEV_CHIP_MEMBER_4S 11u -#define CYDEV_CHIP_MEMBER_4T 9u +#define CYDEV_CHIP_MEMBER_4H 24u +#define CYDEV_CHIP_MEMBER_4I 32u +#define CYDEV_CHIP_MEMBER_4J 21u +#define CYDEV_CHIP_MEMBER_4K 22u +#define CYDEV_CHIP_MEMBER_4L 31u +#define CYDEV_CHIP_MEMBER_4M 29u +#define CYDEV_CHIP_MEMBER_4N 11u +#define CYDEV_CHIP_MEMBER_4O 8u +#define CYDEV_CHIP_MEMBER_4P 28u +#define CYDEV_CHIP_MEMBER_4Q 17u +#define CYDEV_CHIP_MEMBER_4R 9u +#define CYDEV_CHIP_MEMBER_4S 12u +#define CYDEV_CHIP_MEMBER_4T 10u #define CYDEV_CHIP_MEMBER_4U 5u -#define CYDEV_CHIP_MEMBER_4V 16u +#define CYDEV_CHIP_MEMBER_4V 23u +#define CYDEV_CHIP_MEMBER_4W 13u +#define CYDEV_CHIP_MEMBER_4X 7u +#define CYDEV_CHIP_MEMBER_4Y 18u +#define CYDEV_CHIP_MEMBER_4Z 19u #define CYDEV_CHIP_MEMBER_5A 3u #define CYDEV_CHIP_MEMBER_5B 2u -#define CYDEV_CHIP_MEMBER_6A 24u -#define CYDEV_CHIP_MEMBER_FM3 28u -#define CYDEV_CHIP_MEMBER_FM4 29u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 25u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 26u -#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 27u +#define CYDEV_CHIP_MEMBER_6A 33u +#define CYDEV_CHIP_MEMBER_FM3 37u +#define CYDEV_CHIP_MEMBER_FM4 38u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 34u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 35u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 36u #define CYDEV_CHIP_MEMBER_UNKNOWN 0u #define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B #define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED @@ -1488,6 +1497,11 @@ #define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u #define CYDEV_CHIP_REVISION_4A_ES0 17u #define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_4AA_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4AB_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4AC_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4AD_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4AE_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD 0u #define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u @@ -1512,6 +1526,10 @@ #define CYDEV_CHIP_REVISION_4T_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u #define CYDEV_CHIP_REVISION_4V_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4W_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4X_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4Y_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4Z_PRODUCTION 0u #define CYDEV_CHIP_REVISION_5A_ES0 0u #define CYDEV_CHIP_REVISION_5A_ES1 1u #define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index 4375ff9..f291f18 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -2,7 +2,7 @@ /******************************************************************************* * File Name: cyfitter_cfg.c * -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * This file contains device initialization code. @@ -10,7 +10,7 @@ * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h index eefc440..58a0447 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cyfitter_cfg.h * -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * This file provides basic startup and mux configuration settings * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index 1667be7..339ae77 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cyfittergnu.inc * -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. @@ -1418,7 +1418,7 @@ .set CyBtldr_USBFS, CYDEV_BOOTLOADER_IO_COMP_USBFS .set CYDEV_BOOTLOADER_IO_COMP, CYDEV_BOOTLOADER_IO_COMP_USBFS .set CYDEV_CHIP_DIE_LEOPARD, 1 -.set CYDEV_CHIP_DIE_PSOC4A, 18 +.set CYDEV_CHIP_DIE_PSOC4A, 26 .set CYDEV_CHIP_DIE_PSOC5LP, 2 .set CYDEV_CHIP_DIE_PSOC5TM, 3 .set CYDEV_CHIP_DIE_TMA4, 4 @@ -1434,34 +1434,43 @@ .set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 .set CYDEV_CHIP_JTAG_ID, 0x2E133069 .set CYDEV_CHIP_MEMBER_3A, 1 -.set CYDEV_CHIP_MEMBER_4A, 18 -.set CYDEV_CHIP_MEMBER_4D, 13 +.set CYDEV_CHIP_MEMBER_4A, 26 +.set CYDEV_CHIP_MEMBER_4AA, 25 +.set CYDEV_CHIP_MEMBER_4AB, 30 +.set CYDEV_CHIP_MEMBER_4AC, 14 +.set CYDEV_CHIP_MEMBER_4AD, 15 +.set CYDEV_CHIP_MEMBER_4AE, 16 +.set CYDEV_CHIP_MEMBER_4D, 20 .set CYDEV_CHIP_MEMBER_4E, 6 -.set CYDEV_CHIP_MEMBER_4F, 19 +.set CYDEV_CHIP_MEMBER_4F, 27 .set CYDEV_CHIP_MEMBER_4G, 4 -.set CYDEV_CHIP_MEMBER_4H, 17 -.set CYDEV_CHIP_MEMBER_4I, 23 -.set CYDEV_CHIP_MEMBER_4J, 14 -.set CYDEV_CHIP_MEMBER_4K, 15 -.set CYDEV_CHIP_MEMBER_4L, 22 -.set CYDEV_CHIP_MEMBER_4M, 21 -.set CYDEV_CHIP_MEMBER_4N, 10 -.set CYDEV_CHIP_MEMBER_4O, 7 -.set CYDEV_CHIP_MEMBER_4P, 20 -.set CYDEV_CHIP_MEMBER_4Q, 12 -.set CYDEV_CHIP_MEMBER_4R, 8 -.set CYDEV_CHIP_MEMBER_4S, 11 -.set CYDEV_CHIP_MEMBER_4T, 9 +.set CYDEV_CHIP_MEMBER_4H, 24 +.set CYDEV_CHIP_MEMBER_4I, 32 +.set CYDEV_CHIP_MEMBER_4J, 21 +.set CYDEV_CHIP_MEMBER_4K, 22 +.set CYDEV_CHIP_MEMBER_4L, 31 +.set CYDEV_CHIP_MEMBER_4M, 29 +.set CYDEV_CHIP_MEMBER_4N, 11 +.set CYDEV_CHIP_MEMBER_4O, 8 +.set CYDEV_CHIP_MEMBER_4P, 28 +.set CYDEV_CHIP_MEMBER_4Q, 17 +.set CYDEV_CHIP_MEMBER_4R, 9 +.set CYDEV_CHIP_MEMBER_4S, 12 +.set CYDEV_CHIP_MEMBER_4T, 10 .set CYDEV_CHIP_MEMBER_4U, 5 -.set CYDEV_CHIP_MEMBER_4V, 16 +.set CYDEV_CHIP_MEMBER_4V, 23 +.set CYDEV_CHIP_MEMBER_4W, 13 +.set CYDEV_CHIP_MEMBER_4X, 7 +.set CYDEV_CHIP_MEMBER_4Y, 18 +.set CYDEV_CHIP_MEMBER_4Z, 19 .set CYDEV_CHIP_MEMBER_5A, 3 .set CYDEV_CHIP_MEMBER_5B, 2 -.set CYDEV_CHIP_MEMBER_6A, 24 -.set CYDEV_CHIP_MEMBER_FM3, 28 -.set CYDEV_CHIP_MEMBER_FM4, 29 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 25 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 26 -.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 27 +.set CYDEV_CHIP_MEMBER_6A, 33 +.set CYDEV_CHIP_MEMBER_FM3, 37 +.set CYDEV_CHIP_MEMBER_FM4, 38 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 34 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 35 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 36 .set CYDEV_CHIP_MEMBER_UNKNOWN, 0 .set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B .set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED @@ -1486,6 +1495,11 @@ .set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 .set CYDEV_CHIP_REVISION_4A_ES0, 17 .set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_4AA_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4AB_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4AC_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4AD_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4AE_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD, 0 .set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0 @@ -1510,6 +1524,10 @@ .set CYDEV_CHIP_REVISION_4T_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_4V_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4W_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4X_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4Y_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4Z_PRODUCTION, 0 .set CYDEV_CHIP_REVISION_5A_ES0, 0 .set CYDEV_CHIP_REVISION_5A_ES1, 1 .set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 4fb9f0a..9e24525 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -1,13 +1,13 @@ ; ; File Name: cyfitteriar.inc ; -; PSoC Creator 4.2 +; PSoC Creator 4.4 ; ; Description: ; ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. @@ -1417,7 +1417,7 @@ CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 2 CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PSOC4A EQU 18 +CYDEV_CHIP_DIE_PSOC4A EQU 26 CYDEV_CHIP_DIE_PSOC5LP EQU 2 CYDEV_CHIP_DIE_PSOC5TM EQU 3 CYDEV_CHIP_DIE_TMA4 EQU 4 @@ -1433,34 +1433,43 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x2E133069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 18 -CYDEV_CHIP_MEMBER_4D EQU 13 +CYDEV_CHIP_MEMBER_4A EQU 26 +CYDEV_CHIP_MEMBER_4AA EQU 25 +CYDEV_CHIP_MEMBER_4AB EQU 30 +CYDEV_CHIP_MEMBER_4AC EQU 14 +CYDEV_CHIP_MEMBER_4AD EQU 15 +CYDEV_CHIP_MEMBER_4AE EQU 16 +CYDEV_CHIP_MEMBER_4D EQU 20 CYDEV_CHIP_MEMBER_4E EQU 6 -CYDEV_CHIP_MEMBER_4F EQU 19 +CYDEV_CHIP_MEMBER_4F EQU 27 CYDEV_CHIP_MEMBER_4G EQU 4 -CYDEV_CHIP_MEMBER_4H EQU 17 -CYDEV_CHIP_MEMBER_4I EQU 23 -CYDEV_CHIP_MEMBER_4J EQU 14 -CYDEV_CHIP_MEMBER_4K EQU 15 -CYDEV_CHIP_MEMBER_4L EQU 22 -CYDEV_CHIP_MEMBER_4M EQU 21 -CYDEV_CHIP_MEMBER_4N EQU 10 -CYDEV_CHIP_MEMBER_4O EQU 7 -CYDEV_CHIP_MEMBER_4P EQU 20 -CYDEV_CHIP_MEMBER_4Q EQU 12 -CYDEV_CHIP_MEMBER_4R EQU 8 -CYDEV_CHIP_MEMBER_4S EQU 11 -CYDEV_CHIP_MEMBER_4T EQU 9 +CYDEV_CHIP_MEMBER_4H EQU 24 +CYDEV_CHIP_MEMBER_4I EQU 32 +CYDEV_CHIP_MEMBER_4J EQU 21 +CYDEV_CHIP_MEMBER_4K EQU 22 +CYDEV_CHIP_MEMBER_4L EQU 31 +CYDEV_CHIP_MEMBER_4M EQU 29 +CYDEV_CHIP_MEMBER_4N EQU 11 +CYDEV_CHIP_MEMBER_4O EQU 8 +CYDEV_CHIP_MEMBER_4P EQU 28 +CYDEV_CHIP_MEMBER_4Q EQU 17 +CYDEV_CHIP_MEMBER_4R EQU 9 +CYDEV_CHIP_MEMBER_4S EQU 12 +CYDEV_CHIP_MEMBER_4T EQU 10 CYDEV_CHIP_MEMBER_4U EQU 5 -CYDEV_CHIP_MEMBER_4V EQU 16 +CYDEV_CHIP_MEMBER_4V EQU 23 +CYDEV_CHIP_MEMBER_4W EQU 13 +CYDEV_CHIP_MEMBER_4X EQU 7 +CYDEV_CHIP_MEMBER_4Y EQU 18 +CYDEV_CHIP_MEMBER_4Z EQU 19 CYDEV_CHIP_MEMBER_5A EQU 3 CYDEV_CHIP_MEMBER_5B EQU 2 -CYDEV_CHIP_MEMBER_6A EQU 24 -CYDEV_CHIP_MEMBER_FM3 EQU 28 -CYDEV_CHIP_MEMBER_FM4 EQU 29 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 +CYDEV_CHIP_MEMBER_6A EQU 33 +CYDEV_CHIP_MEMBER_FM3 EQU 37 +CYDEV_CHIP_MEMBER_FM4 EQU 38 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 34 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 35 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 36 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED @@ -1485,6 +1494,11 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 CYDEV_CHIP_REVISION_4A_ES0 EQU 17 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4AA_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4AB_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4AC_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4AD_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4AE_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 @@ -1509,6 +1523,10 @@ CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4W_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4X_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Y_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Z_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index 21c6360..2de8934 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -1,13 +1,13 @@ ; ; File Name: cyfitterrv.inc ; -; PSoC Creator 4.2 +; PSoC Creator 4.4 ; ; Description: ; ; ;------------------------------------------------------------------------------- -; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. ; You may use this file only in accordance with the license, terms, conditions, ; disclaimers, and limitations in the end user license agreement accompanying ; the software package with which this file was provided. @@ -1417,7 +1417,7 @@ CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 2 CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS CYDEV_CHIP_DIE_LEOPARD EQU 1 -CYDEV_CHIP_DIE_PSOC4A EQU 18 +CYDEV_CHIP_DIE_PSOC4A EQU 26 CYDEV_CHIP_DIE_PSOC5LP EQU 2 CYDEV_CHIP_DIE_PSOC5TM EQU 3 CYDEV_CHIP_DIE_TMA4 EQU 4 @@ -1433,34 +1433,43 @@ CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 CYDEV_CHIP_JTAG_ID EQU 0x2E133069 CYDEV_CHIP_MEMBER_3A EQU 1 -CYDEV_CHIP_MEMBER_4A EQU 18 -CYDEV_CHIP_MEMBER_4D EQU 13 +CYDEV_CHIP_MEMBER_4A EQU 26 +CYDEV_CHIP_MEMBER_4AA EQU 25 +CYDEV_CHIP_MEMBER_4AB EQU 30 +CYDEV_CHIP_MEMBER_4AC EQU 14 +CYDEV_CHIP_MEMBER_4AD EQU 15 +CYDEV_CHIP_MEMBER_4AE EQU 16 +CYDEV_CHIP_MEMBER_4D EQU 20 CYDEV_CHIP_MEMBER_4E EQU 6 -CYDEV_CHIP_MEMBER_4F EQU 19 +CYDEV_CHIP_MEMBER_4F EQU 27 CYDEV_CHIP_MEMBER_4G EQU 4 -CYDEV_CHIP_MEMBER_4H EQU 17 -CYDEV_CHIP_MEMBER_4I EQU 23 -CYDEV_CHIP_MEMBER_4J EQU 14 -CYDEV_CHIP_MEMBER_4K EQU 15 -CYDEV_CHIP_MEMBER_4L EQU 22 -CYDEV_CHIP_MEMBER_4M EQU 21 -CYDEV_CHIP_MEMBER_4N EQU 10 -CYDEV_CHIP_MEMBER_4O EQU 7 -CYDEV_CHIP_MEMBER_4P EQU 20 -CYDEV_CHIP_MEMBER_4Q EQU 12 -CYDEV_CHIP_MEMBER_4R EQU 8 -CYDEV_CHIP_MEMBER_4S EQU 11 -CYDEV_CHIP_MEMBER_4T EQU 9 +CYDEV_CHIP_MEMBER_4H EQU 24 +CYDEV_CHIP_MEMBER_4I EQU 32 +CYDEV_CHIP_MEMBER_4J EQU 21 +CYDEV_CHIP_MEMBER_4K EQU 22 +CYDEV_CHIP_MEMBER_4L EQU 31 +CYDEV_CHIP_MEMBER_4M EQU 29 +CYDEV_CHIP_MEMBER_4N EQU 11 +CYDEV_CHIP_MEMBER_4O EQU 8 +CYDEV_CHIP_MEMBER_4P EQU 28 +CYDEV_CHIP_MEMBER_4Q EQU 17 +CYDEV_CHIP_MEMBER_4R EQU 9 +CYDEV_CHIP_MEMBER_4S EQU 12 +CYDEV_CHIP_MEMBER_4T EQU 10 CYDEV_CHIP_MEMBER_4U EQU 5 -CYDEV_CHIP_MEMBER_4V EQU 16 +CYDEV_CHIP_MEMBER_4V EQU 23 +CYDEV_CHIP_MEMBER_4W EQU 13 +CYDEV_CHIP_MEMBER_4X EQU 7 +CYDEV_CHIP_MEMBER_4Y EQU 18 +CYDEV_CHIP_MEMBER_4Z EQU 19 CYDEV_CHIP_MEMBER_5A EQU 3 CYDEV_CHIP_MEMBER_5B EQU 2 -CYDEV_CHIP_MEMBER_6A EQU 24 -CYDEV_CHIP_MEMBER_FM3 EQU 28 -CYDEV_CHIP_MEMBER_FM4 EQU 29 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 -CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 +CYDEV_CHIP_MEMBER_6A EQU 33 +CYDEV_CHIP_MEMBER_FM3 EQU 37 +CYDEV_CHIP_MEMBER_FM4 EQU 38 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 34 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 35 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 36 CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED @@ -1485,6 +1494,11 @@ CYDEV_CHIP_REVISION_3A_ES3 EQU 3 CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 CYDEV_CHIP_REVISION_4A_ES0 EQU 17 CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4AA_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4AB_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4AC_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4AD_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4AE_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 @@ -1509,6 +1523,10 @@ CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4W_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4X_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Y_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Z_PRODUCTION EQU 0 CYDEV_CHIP_REVISION_5A_ES0 EQU 0 CYDEV_CHIP_REVISION_5A_ES1 EQU 1 CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c index 5cb139f..ec05878 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: cymetadata.c * -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * This file defines all extra memory spaces that need to be included. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h index ef7e5ab..f3f00e4 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h @@ -1,14 +1,14 @@ /******************************************************************************* * File Name: project.h * -* PSoC Creator 4.2 +* PSoC Creator 4.4 * * Description: * It contains references to all generated header files and should not be modified. * This file is automatically generated by PSoC Creator. * ******************************************************************************** -* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* Copyright (c) 2007-2020 Cypress Semiconductor. All rights reserved. * You may use this file only in accordance with the license, terms, conditions, * disclaimers, and limitations in the end user license agreement accompanying * the software package with which this file was provided. diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch index 51e3e9c..360920b 100644 Binary files a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch differ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cyfit b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cyfit index d467eea..9474815 100644 Binary files a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cyfit and b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cyfit differ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cyprj b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cyprj index 7859b10..f7d0b87 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cyprj +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cyprj @@ -1343,8 +1343,8 @@ - - + + diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.rpt b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.rpt index 92ea60e..6a6ac71 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.rpt +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.rpt @@ -1,13 +1,13 @@ -Loading plugins phase: Elapsed time ==> 0s.109ms +Loading plugins phase: Elapsed time ==> 1s.308ms -cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE +cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p C:\Users\micha\Documents\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s C:\Users\micha\Documents\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -Elaboration phase: Elapsed time ==> 1s.465ms +Elaboration phase: Elapsed time ==> 5s.313ms -HDL generation phase: Elapsed time ==> 0s.041ms +HDL generation phase: Elapsed time ==> 0s.065ms | | | | | | | @@ -24,24 +24,24 @@ HDL generation phase: Elapsed time ==> 0s.041ms ====================================================================== Compiling: USB_Bootloader.v -Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\bin\warp.exe -Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog +Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\bin\warp.exe +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\micha\Documents\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog ====================================================================== ====================================================================== Compiling: USB_Bootloader.v -Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\bin\warp.exe -Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog +Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\bin\warp.exe +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\micha\Documents\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog ====================================================================== ====================================================================== Compiling: USB_Bootloader.v Program : vlogfe -Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\micha\Documents\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v ====================================================================== vlogfe V6.3 IR 41: Verilog parser -Mon Oct 12 10:51:56 2020 +Thu Jan 21 22:31:48 2021 ====================================================================== @@ -51,25 +51,25 @@ Options : -yv2 -q10 USB_Bootloader.v ====================================================================== vpp V6.3 IR 41: Verilog Pre-Processor -Mon Oct 12 10:51:56 2020 +Thu Jan 21 22:31:48 2021 -Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v' -Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v' vpp: No errors. Library 'work' => directory 'lcpsoc3' General_symbol_table General_symbol_table -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\work\cypress.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\std.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\work\cypress.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. Using control file 'USB_Bootloader.ctl'. vlogfe: No errors. @@ -78,25 +78,25 @@ vlogfe: No errors. ====================================================================== Compiling: USB_Bootloader.v Program : tovif -Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\micha\Documents\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v ====================================================================== tovif V6.3 IR 41: High-level synthesis -Mon Oct 12 10:51:56 2020 - -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\work\cypress.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'. -Linking 'C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'. +Thu Jan 21 22:31:49 2021 + +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\std.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\work\cypress.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. +Linking 'C:\Users\micha\Documents\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'. +Linking 'C:\Users\micha\Documents\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'. tovif: No errors. @@ -104,26 +104,26 @@ tovif: No errors. ====================================================================== Compiling: USB_Bootloader.v Program : topld -Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\micha\Documents\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v ====================================================================== topld V6.3 IR 41: Synthesis and optimization -Mon Oct 12 10:51:56 2020 - -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\work\cypress.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. -Linking 'C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'. -Linking 'C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'. -Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'. +Thu Jan 21 22:31:49 2021 + +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\std.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\cypress.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\work\cypress.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. +Linking 'C:\Users\micha\Documents\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'. +Linking 'C:\Users\micha\Documents\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'. ---------------------------------------------------------- Detecting unused logic. @@ -239,18 +239,18 @@ Circuit simplification results: topld: No errors. -CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp -Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\bin\warp.exe -Warp Arguments : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog +CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp +Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\warp\bin\warp.exe +Warp Arguments : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\micha\Documents\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog -Warp synthesis phase: Elapsed time ==> 0s.471ms +Warp synthesis phase: Elapsed time ==> 2s.599ms -cyp3fit: V4.2.0.641, Family: PSoC3, Started at: Monday, 12 October 2020 10:51:56 -Options: -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog +cyp3fit: V4.4.0.80, Family: PSoC3, Started at: Thursday, 21 January 2021 22:31:50 +Options: -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\micha\Documents\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog -Design parsing phase: Elapsed time ==> 0s.009ms +Design parsing phase: Elapsed time ==> 0s.007ms @@ -1619,7 +1619,7 @@ Design Equations interrupt: Name =\USBFS:sof_int\ PORT MAP ( - interrupt => Net_40 ); + interrupt => Net_122 ); Properties: { int_type = "10" @@ -1659,8 +1659,8 @@ SAR ADC : 0 : 1 : 1 : 0.00 % DAC : : : : VIDAC : 0 : 1 : 1 : 0.00 % -Technology Mapping: Elapsed time ==> 0s.073ms -Tech Mapping phase: Elapsed time ==> 0s.130ms +Technology Mapping: Elapsed time ==> 0s.065ms +Tech Mapping phase: Elapsed time ==> 0s.122ms Initial Analog Placement Results: @@ -1697,7 +1697,7 @@ IO_3@[IOP=(15)][IoId=(3)] : TERM_EN(0) (fixed) IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed) IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed) USB[0]@[FFB(USB,0)] : \USBFS:USB\ -Analog Placement phase: Elapsed time ==> 0s.053ms +Analog Placement phase: Elapsed time ==> 0s.008ms Analog Routing phase: Elapsed time ==> 0s.000ms @@ -1715,12 +1715,12 @@ Dump of CyP35AnalogRoutingResultsDB IsVddaHalfUsedForComp = False IsVddaHalfUsedForSar0 = False IsVddaHalfUsedForSar1 = False -Analog Code Generation phase: Elapsed time ==> 0s.328ms +Analog Code Generation phase: Elapsed time ==> 0s.212ms I2659: No Constrained paths were found. The placer will run in non-timing driven mode. -I2076: Total run-time: 0.6 sec. +I2076: Total run-time: 0.5 sec. @@ -1734,7 +1734,7 @@ PLD Packing: Elapsed time ==> 0s.000ms Initial Partitioning Summary not displayed at this verbose level. Final Partitioning Summary not displayed at this verbose level. -Partitioning: Elapsed time ==> 0s.028ms +Partitioning: Elapsed time ==> 0s.016ms @@ -1806,7 +1806,7 @@ Intr container @ [IntrContainer=(0)]: Intr@ [IntrContainer=(0)][IntrId=(21)] interrupt: Name =\USBFS:sof_int\ PORT MAP ( - interrupt => Net_40 ); + interrupt => Net_122 ); Properties: { int_type = "10" @@ -3252,7 +3252,7 @@ USB group 0: PORT MAP ( dp => \USBFS:Net_1000\ , dm => \USBFS:Net_597\ , - sof_int => Net_40 , + sof_int => Net_122 , arb_int => \USBFS:Net_79\ , usb_int => \USBFS:Net_81\ , ept_int_8 => \USBFS:ept_int_8\ , @@ -3336,33 +3336,33 @@ Port | Pin | Fixed | Type | Drive Mode | Name | Connection -Digital component placer commit/Report: Elapsed time ==> 0s.048ms -Digital Placement phase: Elapsed time ==> 0s.964ms +Digital component placer commit/Report: Elapsed time ==> 0s.031ms +Digital Placement phase: Elapsed time ==> 0s.947ms -"C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\bin/sjrouter.exe" --xml-path "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\dev\psoc5/psoc5lp/route_arch-rrg.cydata" --vh2-path "USB_Bootloader_r.vh2" --pcf-path "USB_Bootloader.pco" --des-name "USB_Bootloader" --dsf-path "USB_Bootloader.dsf" --sdc-path "USB_Bootloader.sdc" --lib-path "USB_Bootloader_r.lib" +"C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\bin/sjrouter.exe" --xml-path "C:\Program Files (x86)\Cypress\PSoC Creator\4.4\PSoC Creator\dev\psoc5/psoc5lp/route_arch-rrg.cydata" --vh2-path "USB_Bootloader_r.vh2" --pcf-path "USB_Bootloader.pco" --des-name "USB_Bootloader" --dsf-path "USB_Bootloader.dsf" --sdc-path "USB_Bootloader.sdc" --lib-path "USB_Bootloader_r.lib" Routing successful. -Digital Routing phase: Elapsed time ==> 1s.346ms +Digital Routing phase: Elapsed time ==> 0s.910ms -Bitstream Generation phase: Elapsed time ==> 0s.136ms +Bitstream Generation phase: Elapsed time ==> 0s.220ms -Bitstream Verification phase: Elapsed time ==> 0s.030ms +Bitstream Verification phase: Elapsed time ==> 0s.028ms Timing report is in USB_Bootloader_timing.html. -Static timing analysis phase: Elapsed time ==> 0s.229ms +Static timing analysis phase: Elapsed time ==> 0s.315ms Data reporting phase: Elapsed time ==> 0s.000ms -Design database save phase: Elapsed time ==> 0s.159ms +Design database save phase: Elapsed time ==> 0s.147ms -cydsfit: Elapsed time ==> 3s.406ms +cydsfit: Elapsed time ==> 2s.990ms -Fitter phase: Elapsed time ==> 3s.407ms -API generation phase: Elapsed time ==> 1s.335ms -Dependency generation phase: Elapsed time ==> 0s.009ms +Fitter phase: Elapsed time ==> 2s.990ms +API generation phase: Elapsed time ==> 3s.949ms +Dependency generation phase: Elapsed time ==> 0s.045ms Cleanup phase: Elapsed time ==> 0s.000ms diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader_timing.html b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader_timing.html index cca1641..52e55e8 100644 --- a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader_timing.html +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader_timing.html @@ -539,7 +539,7 @@ function getElementsByClass(rootNode, elemName, className) Project : USB_Bootloader Build Time : - 10/12/20 10:51:59 + 01/21/21 22:31:52 Device : CY8C5267AXI-LP051 Temperature : diff --git a/software/include/hidpacket.h b/software/include/hidpacket.h index db81158..d0ea3d8 100644 --- a/software/include/hidpacket.h +++ b/software/include/hidpacket.h @@ -24,9 +24,9 @@ extern "C" { #define USBHID_LEN 64 -// Maximum packet payload length. Must be large enough to support a flash row -// + flash array index + flash row index -#define HIDPACKET_MAX_LEN 260 +// Maximum packet payload length. Must be large enough to support a SD sector +// + sector number + device number +#define HIDPACKET_MAX_LEN 520 #include #include diff --git a/software/include/scsi2sd.h b/software/include/scsi2sd.h index e9e44e2..8b60b3e 100755 --- a/software/include/scsi2sd.h +++ b/software/include/scsi2sd.h @@ -141,6 +141,12 @@ typedef enum CONFIG_SPEED_ASYNC_15 } CONFIG_SPEED; +typedef enum +{ + CONFIG_STOREDEVICE_SD, + CONFIG_STOREDEVICE_FLASH +} CONFIG_STOREDEVICE; + typedef struct __attribute__((packed)) { uint8_t deviceType; @@ -178,13 +184,17 @@ typedef struct __attribute__((packed)) char serial[16]; uint16_t quirks; // CONFIG_QUIRKS + + // 0 == SD card + // 1 == SPI Flash + uint8_t storageDevice; // CONFIG_STOREDEVICE - uint8_t reserved[960]; // Pad out to 1024 bytes for main section. + uint8_t reserved[959]; // Pad out to 1024 bytes for main section. uint8_t modePages[1024]; uint8_t vpd[1024]; uint8_t unused[1024]; // Total size is 4k. -} TargetConfig; +} S2S_TargetCfg; typedef struct __attribute__((packed)) { @@ -198,7 +208,7 @@ typedef struct __attribute__((packed)) uint8_t reserved[247]; // Pad out to 256 bytes -} BoardConfig; +} S2S_BoardConfig; typedef enum { @@ -244,7 +254,87 @@ typedef enum // Response: // CONFIG_STATUS // uint8_t result code (0 = passed) - CONFIG_SCSITEST + CONFIG_SCSITEST, + + // Not implemented, V6 only + // Command content: + // uint8_t S2S_CMD_DEVINFO + // Response: + // uint16_t protocol version (MSB) + // uint16_t firmware version (MSB) + // uint32_t SD capacity(MSB) + S2S_CMD_DEVINFO_OBSOLETE, + + // Not implemented, V6 only + // Command content: + // uint8_t S2S_CMD_SD_WRITE + // uint32_t Sector Number (MSB) + // uint8_t[512] data + // Response: + // S2S_CMD_STATUS + S2S_CMD_SD_WRITE, + + // Not implemented, V6 only + // Command content: + // uint8_t S2S_CMD_SD_READ + // uint32_t Sector Number (MSB) + // Response: + // 512 bytes of data + S2S_CMD_SD_READ, + + // Not implemented, V6 only + // Command content: + // uint8_t S2S_CMD_DEBUG + // Response: + S2S_CMD_DEBUG, + + // Command content: + // uint8_t S2S_CMD_DEV_LIST + // Response: + // uint8_t Number of devices + // For each device: + // uint8_t device type + // 0 == SD card + // 1 == NOR FLASH + // uint32_t capacity(MSB) + S2S_CMD_DEV_LIST, + + // Command content: + // uint8_t S2S_CMD_DEV_INFO + // uint8_t Device Number + // Response: + // SD card: + // uint8_t[16] CSD + // uint8_t[16] CID + // NOR Flash: + // uint8_t[512] JEDEC CFI from RDID command + S2S_CMD_DEV_INFO, + + // Command content: + // uint8_t S2S_CMD_DEV_ERASE + // uint8_t Device Number + // uint32_t Sector Number (MSB) + // uint32_t Sector Count (MSB) + // Response: + // S2S_CMD_STATUS + S2S_CMD_DEV_ERASE, + + // Command content: + // uint8_t S2S_CMD_DEV_WRITE + // uint8_t Device Number (MSB) + // uint32_t Sector Number (MSB) + // uint8_t[512] data + // Response: + // S2S_CMD_STATUS + S2S_CMD_DEV_WRITE, + + // Command content: + // uint8_t S2S_CMD_DEV_READ + // uint8_t Device Number (MSB) + // uint32_t Sector Number (MSB) + // Response: + // 512 bytes of data + S2S_CMD_DEV_READ, } CONFIG_COMMAND; typedef enum