From: Michael McMaster Date: Wed, 16 Apr 2014 11:46:01 +0000 (+1000) Subject: Force unit-attention-condition off for pre-SCSI2 hosts X-Git-Tag: 3.3^0 X-Git-Url: http://git.codesrc.com/gitweb.cgi?a=commitdiff_plain;h=36ce697d7a67f571c1edabebba5e59a15a0a59ed;p=SCSI2SD.git Force unit-attention-condition off for pre-SCSI2 hosts --- diff --git a/CHANGELOG b/CHANGELOG index 0e6de11..6c4b96f 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,11 +1,13 @@ -20140??? 3.3 +20140416 3.3 - Fix to SCSI Reset handling to avoid lockups - Bug fixes to improve standards compatibility - Bug fix for Unit Attention Condition, which is now enabled by default. - - scsi2sd-config can be used to disable it for those systems that + scsi2sd-config can be used to disable it for those systems that truely require it (eg. Mac Plus). - Added Linked commands support. - Added support for configurable sector sizes between 64 and 2048 bytes. + The sector size can be set via the MODE SELECT command using a SCSI + format utility, or via scsi2sd-config - Powerbook firmware added 20140214 3.2 diff --git a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit index d6ca504..8b99a49 100755 Binary files a/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.cyfit differ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyfit b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyfit index 0ec8f5f..08bc6f0 100755 Binary files a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyfit and b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyfit differ diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 index 5f6a944..60d50ee 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 +++ b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.cyprj.Micha_000 @@ -1663,14 +1663,14 @@ C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif - + - + diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt index 1536367..3b14907 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt +++ b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader.rpt @@ -1,13 +1,13 @@ -Loading plugins phase: Elapsed time ==> 0s.499ms -Initializing data phase: Elapsed time ==> 3s.703ms +Loading plugins phase: Elapsed time ==> 0s.481ms +Initializing data phase: Elapsed time ==> 3s.796ms cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -Elaboration phase: Elapsed time ==> 7s.531ms +Elaboration phase: Elapsed time ==> 7s.874ms -HDL generation phase: Elapsed time ==> 0s.109ms +HDL generation phase: Elapsed time ==> 0s.173ms | | | | | | | @@ -41,7 +41,7 @@ Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\sof ====================================================================== vlogfe V6.3 IR 41: Verilog parser -Sun Mar 23 21:45:41 2014 +Wed Apr 16 21:15:58 2014 ====================================================================== @@ -51,7 +51,7 @@ Options : -yv2 -q10 USB_Bootloader.v ====================================================================== vpp V6.3 IR 41: Verilog Pre-Processor -Sun Mar 23 21:45:41 2014 +Wed Apr 16 21:15:59 2014 vpp: No errors. @@ -80,7 +80,7 @@ Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\sof ====================================================================== tovif V6.3 IR 41: High-level synthesis -Sun Mar 23 21:45:42 2014 +Wed Apr 16 21:15:59 2014 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -104,7 +104,7 @@ Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\sof ====================================================================== topld V6.3 IR 41: Synthesis and optimization -Sun Mar 23 21:45:42 2014 +Wed Apr 16 21:16:00 2014 Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'. Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'. @@ -204,10 +204,10 @@ CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\wa Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog -Warp synthesis phase: Elapsed time ==> 1s.454ms +Warp synthesis phase: Elapsed time ==> 2s.967ms -cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Sunday, 23 March 2014 21:45:43 +cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Wednesday, 16 April 2014 21:16:01 Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=W:\SCSI2SD\software\SCSI2SD\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog @@ -1314,7 +1314,7 @@ EMIF Fixed Blocks : 0 : 1 : 1 : 0.00% LPF Fixed Blocks : 0 : 2 : 2 : 0.00% SAR Fixed Blocks : 0 : 1 : 1 : 0.00% -Technology Mapping: Elapsed time ==> 0s.031ms +Technology Mapping: Elapsed time ==> 0s.015ms Tech mapping phase: Elapsed time ==> 0s.281ms @@ -1345,7 +1345,7 @@ IO_5@[IOP=(3)][IoId=(5)] : SD_PULLUP(4) (fixed) IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed) IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed) USB[0]@[FFB(USB,0)] : \USBFS:USB\ -Analog Placement phase: Elapsed time ==> 0s.156ms +Analog Placement phase: Elapsed time ==> 0s.109ms Analog Routing phase: Elapsed time ==> 0s.000ms @@ -1363,12 +1363,12 @@ Dump of CyP35AnalogRoutingResultsDB IsVddaHalfUsedForComp = False IsVddaHalfUsedForSar0 = False IsVddaHalfUsedForSar1 = False -Analog Code Generation phase: Elapsed time ==> 1s.187ms +Analog Code Generation phase: Elapsed time ==> 1s.031ms I2659: No Constrained paths were found. The placer will run in non-timing driven mode. -I2076: Total run-time: 2.4 sec. +I2076: Total run-time: 1.6 sec. @@ -1382,7 +1382,7 @@ PLD Packing: Elapsed time ==> 0s.000ms Initial Partitioning Summary not displayed at this verbose level. Final Partitioning Summary not displayed at this verbose level. -Partitioning: Elapsed time ==> 0s.078ms +Partitioning: Elapsed time ==> 0s.077ms Annealing: Elapsed time ==> 0s.000ms @@ -2664,32 +2664,32 @@ Port | Pin | Fixed | Type | Drive Mode | Name | Connection -Digital component placer commit/Report: Elapsed time ==> 0s.016ms -Digital Placement phase: Elapsed time ==> 3s.031ms +Digital component placer commit/Report: Elapsed time ==> 0s.017ms +Digital Placement phase: Elapsed time ==> 2s.641ms Routing successful. -Digital Routing phase: Elapsed time ==> 3s.046ms +Digital Routing phase: Elapsed time ==> 3s.404ms -Bitstream and API generation phase: Elapsed time ==> 0s.718ms +Bitstream and API generation phase: Elapsed time ==> 0s.796ms -Bitstream verification phase: Elapsed time ==> 0s.159ms +Bitstream verification phase: Elapsed time ==> 0s.171ms Timing report is in USB_Bootloader_timing.html. -Static timing analysis phase: Elapsed time ==> 1s.074ms +Static timing analysis phase: Elapsed time ==> 0s.812ms Data reporting phase: Elapsed time ==> 0s.000ms -Design database save phase: Elapsed time ==> 0s.374ms +Design database save phase: Elapsed time ==> 0s.406ms -cydsfit: Elapsed time ==> 10s.140ms +cydsfit: Elapsed time ==> 9s.781ms -Fitter phase: Elapsed time ==> 10s.233ms -API generation phase: Elapsed time ==> 4s.062ms -Dependency generation phase: Elapsed time ==> 0s.031ms -Cleanup phase: Elapsed time ==> 0s.046ms +Fitter phase: Elapsed time ==> 9s.859ms +API generation phase: Elapsed time ==> 4s.706ms +Dependency generation phase: Elapsed time ==> 0s.028ms +Cleanup phase: Elapsed time ==> 0s.063ms diff --git a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html index 5617ccc..20322ae 100755 --- a/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html +++ b/software/SCSI2SD/USB_Bootloader.cydsn/USB_Bootloader_timing.html @@ -539,7 +539,7 @@ function getElementsByClass(rootNode, elemName, className) Project : USB_Bootloader Build Time : - 03/23/14 21:45:52 + 04/16/14 21:16:10 Device : CY8C5267AXI-LP051 Temperature : diff --git a/software/SCSI2SD/src/scsi.c b/software/SCSI2SD/src/scsi.c index 3751833..7a9d359 100755 --- a/software/SCSI2SD/src/scsi.c +++ b/software/SCSI2SD/src/scsi.c @@ -48,6 +48,10 @@ static void doReserveRelease(void); static void enter_BusFree() { + // This delay probably isn't needed for most SCSI hosts, but it won't + // hurt either. It's possible some of the samplers needed this delay. + CyDelayUs(2); + SCSI_ClearPin(SCSI_Out_BSY); // We now have a Bus Clear Delay of 800ns to release remaining signals. SCSI_ClearPin(SCSI_Out_MSG); @@ -492,9 +496,16 @@ static void process_SelectionPhase() (goodParity || !config->enableParity) && (maskBitCount <= 2)) { // Do we enter MESSAGE OUT immediately ? SCSI 1 and 2 standards says - // move to MESSAGE OUT if ATN is true before we release BSY. - // The initiate should assert ATN with SEL. + // move to MESSAGE OUT if ATN is true before we assert BSY. + // The initiator should assert ATN with SEL. scsiDev.atnFlag = SCSI_ReadPin(SCSI_ATN_INT); + + // Unit attention breaks many older SCSI hosts. Disable it completely for + // SCSI-1 (and older) hosts, regardless of our configured setting. + if (!scsiDev.atnFlag) + { + scsiDev.unitAttention = 0; + } // We've been selected! // Assert BSY - Selection success! diff --git a/software/SCSI2SD/src/scsi.h b/software/SCSI2SD/src/scsi.h index dd0c33a..4ed618b 100755 --- a/software/SCSI2SD/src/scsi.h +++ b/software/SCSI2SD/src/scsi.h @@ -20,7 +20,7 @@ // Set this to true to log SCSI commands and status information via // USB HID packets. The can be captured and viewed in wireshark. // For windows users, capture using USBPcap http://desowin.org/usbpcap/ -#define MM_DEBUG 1 +#define MM_DEBUG 0 #include "geometry.h" #include "sense.h"